From bafa9d95453387814ef25e6b6256ba8db2df612f Mon Sep 17 00:00:00 2001
From: Martin Braun <martin.braun@ettus.com>
Date: Thu, 23 Jan 2020 16:10:22 -0800
Subject: Merge FPGA repository back into UHD repository
MIME-Version: 1.0
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The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>
---
 fpga/usrp3/lib/axi/Makefile.srcs                   |     36 +
 fpga/usrp3/lib/axi/axi_add_preamble.v              |    157 +
 fpga/usrp3/lib/axi/axi_chdr_header_trigger.v       |     43 +
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(limited to 'fpga/usrp3/lib')

diff --git a/fpga/usrp3/lib/axi/Makefile.srcs b/fpga/usrp3/lib/axi/Makefile.srcs
new file mode 100644
index 000000000..28f63104d
--- /dev/null
+++ b/fpga/usrp3/lib/axi/Makefile.srcs
@@ -0,0 +1,36 @@
+#
+# Copyright 2012-2013 Ettus Research LLC
+# Copyright 2014 Ettus Research, a National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+##################################################
+# FIFO Sources
+##################################################
+AXI_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/axi/, \
+axi_chdr_header_trigger.v \
+axi_chdr_test_pattern.v \
+axi_defs.v \
+axi_dma_fifo.v \
+axi_dma_master.v \
+axi_replay.v \
+axi_embed_tlast.v \
+axi_extract_tlast.v \
+axi_fast_extract_tlast.v \
+axi_embed_tlast_tkeep.v \
+axi_extract_tlast_tkeep.v \
+axi_fast_fifo.v \
+axi_to_strobed.v \
+axis_data_swap.v \
+axi_dummy.v \
+strobed_to_axi.v \
+axi_add_preamble.v \
+axi_strip_preamble.v \
+crc_xnor.v \
+axis_packet_flush.v \
+axis_shift_register.v \
+axis_upsizer.v \
+axis_downsizer.v \
+axis_width_conv.v \
+))
diff --git a/fpga/usrp3/lib/axi/axi_add_preamble.v b/fpga/usrp3/lib/axi/axi_add_preamble.v
new file mode 100644
index 000000000..a66b4229d
--- /dev/null
+++ b/fpga/usrp3/lib/axi/axi_add_preamble.v
@@ -0,0 +1,157 @@
+//
+// Copyright 2016 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Adds preamble, EOP, and CRC/num_words check
+// <preamble> <packet> <EOP> [control_chksum,word_count,payload_chksum] 
+// <preamble>   = 64'h9E6774129E677412
+// <EOP>        = 64'h2A1D632F2A1D632F
+
+module axi_add_preamble #(
+  parameter WIDTH=64
+) (
+   input clk,
+   input reset,
+   input clear,
+   //
+   input [WIDTH-1:0] i_tdata,
+   input i_tlast,
+   input i_tvalid,
+   output i_tready,
+   //
+   output reg [WIDTH-1:0] o_tdata,
+   output o_tvalid,
+   input o_tready
+);
+
+    function [0:0] cvita_get_has_time;
+        input [63:0] header;
+        cvita_get_has_time = header[61];
+    endfunction
+
+   //States
+   localparam IDLE = 0;
+   localparam PREAMBLE = 1;
+   localparam PASS = 3;
+   localparam EOP = 4;
+   localparam CRC = 5;
+   
+   localparam PAYLOAD_WORDCOUNT_WIDTH = 16;
+   localparam PAYLOAD_CHKSUM_WIDTH = 32;
+   localparam CONTROL_CHKSUM_WIDTH = 16;
+   
+   reg [2:0]  state, next_state;
+   
+   reg [PAYLOAD_WORDCOUNT_WIDTH-1:0] word_count;
+   reg [PAYLOAD_WORDCOUNT_WIDTH-1:0] cntrl_length = 16'd2;
+   wire [PAYLOAD_CHKSUM_WIDTH-1:0] payload_chksum;
+   wire [CONTROL_CHKSUM_WIDTH-1:0] control_chksum;
+
+  // Payload LFSR
+  crc_xnor #(.INPUT_WIDTH(WIDTH), .OUTPUT_WIDTH(PAYLOAD_CHKSUM_WIDTH)) payload_chksum_gen (
+     .clk(clk), .rst(word_count<=cntrl_length), .hold(~(i_tready && i_tvalid)),
+     .input_data(i_tdata), .crc_out(payload_chksum)
+  );
+  
+  // Control LFSR
+  crc_xnor #(.INPUT_WIDTH(WIDTH), .OUTPUT_WIDTH(CONTROL_CHKSUM_WIDTH)) control_chksum_gen (
+     .clk(clk), .rst(word_count=='d0), .hold(~(i_tready && i_tvalid) || word_count>=cntrl_length),
+     .input_data(i_tdata), .crc_out(control_chksum)
+  );
+  
+  //Update control length so control checksum is correct
+  always @(posedge clk) begin
+    if (state == IDLE && i_tvalid)
+        cntrl_length <= cvita_get_has_time(i_tdata) ? 16'd2 : 16'd1;
+  end
+  
+  //Note that word_count includes EOP
+  always @(posedge clk) begin
+     if (state == IDLE) begin
+        word_count <= 0;
+     end else if (i_tready && i_tvalid || (o_tready && state == EOP)) begin
+        word_count <= word_count+1;
+     end
+  end
+      
+   always @(posedge clk) 
+      if (reset | clear) begin
+         state <= IDLE;
+      end else begin
+         state <= next_state;
+      end 
+
+   always @(*) begin
+      case(state)
+         IDLE: begin
+            if (i_tvalid) begin
+               next_state = PREAMBLE;
+            end else begin
+               next_state = IDLE;
+            end
+         end 
+         
+         PREAMBLE: begin
+            if(o_tready) begin
+                next_state = PASS;
+            end else begin
+                next_state = PREAMBLE;
+            end
+         end                
+
+         PASS: begin
+            if(i_tready && i_tvalid && i_tlast) begin
+                 next_state = EOP;
+             end else begin
+                 next_state = PASS;
+             end
+         end
+         
+         EOP: begin
+            if(o_tready) begin
+                next_state = CRC;
+            end else begin
+                next_state = EOP;
+            end
+         end          
+
+         CRC: begin
+            if(o_tready) begin
+                 next_state = IDLE;
+             end else begin
+                 next_state = CRC;
+             end
+         end
+         
+         default: begin
+            next_state = IDLE;
+         end
+        
+      endcase
+   end 
+
+   //
+   // Muxes
+   //
+   always @*
+      begin
+         case(state)
+            IDLE:           o_tdata = 0; 
+            PASS:           o_tdata = i_tdata;
+            PREAMBLE:       o_tdata = 64'h9E6774129E677412;
+            EOP:            o_tdata = 64'h2A1D632F2A1D632F;
+            CRC:            o_tdata = {control_chksum,word_count,payload_chksum};
+            default:        o_tdata = 0;
+            
+         endcase 
+      end
+
+   assign o_tvalid = (state == PASS) ? i_tvalid : (state != IDLE);
+   assign i_tready = (state == PASS) ? o_tready : 1'b0;
+
+endmodule 
+
+
+
diff --git a/fpga/usrp3/lib/axi/axi_chdr_header_trigger.v b/fpga/usrp3/lib/axi/axi_chdr_header_trigger.v
new file mode 100644
index 000000000..452e85052
--- /dev/null
+++ b/fpga/usrp3/lib/axi/axi_chdr_header_trigger.v
@@ -0,0 +1,43 @@
+
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+
+
+module axi_chdr_header_trigger
+  #(
+    parameter WIDTH=64,
+    parameter SID=0
+   )
+    (input clk, input reset, input clear,
+     input [WIDTH-1:0] i_tdata, input i_tlast, input i_tvalid, input i_tready,
+     output trigger
+     );
+
+   
+   reg 	  state;
+   localparam IDLE = 0;
+   localparam RUN  = 1;
+ 
+
+   always @(posedge clk)
+     if(reset | clear)
+       state <= IDLE;
+     else
+       case (state)
+	 IDLE :
+	   if(i_tvalid && i_tready)
+	     state <= RUN;
+
+	 RUN :
+	   if(i_tready && i_tvalid && i_tlast)	    
+	     state <= IDLE;
+
+	 default :
+	   state <= IDLE;
+       endcase // case (state)
+
+   assign     trigger =  i_tvalid && i_tready && (state == IDLE) && (i_tdata[15:0] != SID);
+
+endmodule // axi_chdr_header_trigger
diff --git a/fpga/usrp3/lib/axi/axi_chdr_test_pattern.v b/fpga/usrp3/lib/axi/axi_chdr_test_pattern.v
new file mode 100644
index 000000000..e73eaaa9d
--- /dev/null
+++ b/fpga/usrp3/lib/axi/axi_chdr_test_pattern.v
@@ -0,0 +1,505 @@
+//
+// Copyright 2014 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+//
+// Synthesizable test pattern generator and checker
+// for AXI-Stream that can be used to test transparent blocks
+// (FIFOs, switches, etc)
+//
+
+module axi_chdr_test_pattern #(
+  parameter SR_BASE     = 8'h0,         //Base address for settings in this module
+  parameter DELAY_MODE  = "DYNAMIC",    //Are delays configurable at runtime {STATIC, DYNAMIC}
+  parameter SID_MODE    = "DYNAMIC",    //Is the SID configurable at runtime {STATIC, DYNAMIC}
+  parameter STATIC_SID  = 32'h0,        //SID Value if it is static
+  parameter BW_COUNTER  = 1             //Instantiate counters to measure bandwidth (Cycles of Data Xfer / Total cycles)
+) (
+  input             clk,
+  input             reset,
+
+  // AXI stream to hook up to input of DUT
+  output reg [63:0] i_tdata,
+  output reg        i_tlast,
+  output reg        i_tvalid,
+  input             i_tready,
+
+  // AXI stream to hook up to output of DUT
+  input      [63:0] o_tdata,
+  input             o_tlast,
+  input             o_tvalid,
+  output reg        o_tready,
+
+  //Settings bus interface
+  input             set_stb,
+  input       [7:0] set_addr,
+  input      [31:0] set_data,
+
+  // Test flags
+  output reg        running,    //Test is currently in progress
+  output reg        done,       //(Sticky) Test has finished executing
+  output reg  [1:0] error,      //Error code from last test execution
+
+  output    [127:0] status_vtr, //More information about test failure.
+  output     [95:0] bw_ratio    //Bandwidth counter info
+);
+
+  //
+  // Error Codes
+  //
+  localparam ERR_SUCCESS                  = 0;
+  localparam ERR_DATA_MISMATCH            = 1;
+  localparam ERR_SIZE_MISMATCH_TOO_LONG   = 2;
+  localparam ERR_SIZE_MISMATCH_TOO_SHORT  = 3;
+  
+  localparam ERR_TIMEOUT_LOG2             = 10;
+
+  //
+  // Settings
+  //
+  wire        bist_size_ramp;
+  wire [1:0]  bist_test_patt;
+  wire [12:0] bist_max_pkt_size;
+  wire        bist_go, bist_cont, bist_ctrl_wr;
+  wire [1:0]  bist_ctrl_reserved;
+  wire [17:0] bist_max_pkts;
+  wire [15:0] bist_tx_pkt_delay;
+  wire [7:0]  bist_rx_samp_delay;
+  wire [31:0] bist_cvita_sid;
+
+  localparam TEST_PATT_ZERO_ONE     = 2'd0;
+  localparam TEST_PATT_CHECKERBOARD = 2'd1;
+  localparam TEST_PATT_COUNT        = 2'd2;
+  localparam TEST_PATT_COUNT_INV    = 2'd3;
+
+  // SETTING: Test Control Register
+  // Fields:
+  // - [0]    : (Strobe) Start the test if 1, otherwise stop a running test.
+  //            If no test is running then reset the status. (Reseting a
+  //            continuously running test requires two writes to this reg)
+  // - [1]    : Start the test in continuous mode. (Run until reset or failure)
+  // - [3:2]  : <Unused>
+  // - [5:4]  : Test pattern:
+  //            * 00 = Zeros and Ones (0x0000000000000000 <-> 0xFFFFFFFFFFFFFFFF)
+  //            * 01 = Checkerboard   (0x5555555555555555 <-> 0xAAAAAAAAAAAAAAAA)
+  //            * 10 = Counter        (Each byte will count up)
+  //            * 11 = Invert Counter (Each byte will count up and invert)
+  setting_reg #(
+    .my_addr(SR_BASE + 0), .width(6), .at_reset(3'b0)
+  ) reg_ctrl (
+    .clk(clk), .rst(reset),
+    .strobe(set_stb), .addr(set_addr), .in(set_data),
+    .out({bist_test_patt, bist_ctrl_reserved, bist_cont, bist_go}),.changed(bist_ctrl_wr)
+  );
+  
+  wire bist_start = bist_ctrl_wr & bist_go;
+  wire bist_clear = bist_ctrl_wr & ~bist_go;
+
+  // SETTING: Test Packet Configuration Register
+  // Fields:
+  // - [17:0]  : Number of packets to transfer per BIST execution
+  // - [30:18] : Max number of bytes of payload per packet
+  // - [31]    : Send variable (ramping) sized packets
+  setting_reg #(
+    .my_addr(SR_BASE + 1), .width(32), .at_reset(32'b0)
+  ) reg_pkt_config (
+    .clk(clk), .rst(reset),
+    .strobe(set_stb), .addr(set_addr), .in(set_data),
+    .out({bist_size_ramp, bist_max_pkt_size, bist_max_pkts}),.changed()
+  );
+
+  generate if (DELAY_MODE == "DYNAMIC") begin
+    // SETTING: Delay Register
+    // Fields:
+    // - [15:0]   : Number of cycles to wait between generating consecutive *packets*
+    // - [23:16]  : Number of cycles to wait between consuming consecutive *samples*
+    setting_reg #(
+      .my_addr(SR_BASE + 2), .width(24), .at_reset(24'b0)
+    ) reg_delay (
+      .clk(clk), .rst(reset),
+      .strobe(set_stb), .addr(set_addr), .in(set_data),
+      .out({bist_rx_samp_delay, bist_tx_pkt_delay}),.changed()
+    );
+  end else begin
+    assign {bist_rx_samp_delay, bist_tx_pkt_delay} = 24'h0;
+  end endgenerate
+
+  generate if (SID_MODE == "DYNAMIC") begin
+    // SETTING: CHDR Stream ID Register
+    // Fields:
+    // - [31:0]   : Stream ID to attach to CHDR packets
+    setting_reg #(
+      .my_addr(SR_BASE + 3), .width(32), .at_reset(32'b0)
+    ) reg_sid (
+      .clk(clk), .rst(reset),
+      .strobe(set_stb), .addr(set_addr), .in(set_data),
+      .out(bist_cvita_sid),.changed()
+    );
+  end else begin
+    assign bist_cvita_sid = STATIC_SID;
+  end endgenerate
+
+  //
+  // State
+  //
+  localparam TX_IDLE    = 3'd0;
+  localparam TX_START   = 3'd1;
+  localparam TX_ACTIVE  = 3'd2;
+  localparam TX_GAP     = 3'd3;
+  localparam TX_DONE    = 3'd4;
+  localparam TX_WAIT    = 3'd5;
+
+  localparam RX_IDLE    = 3'd0;
+  localparam RX_ACTIVE  = 3'd1;
+  localparam RX_FAIL    = 3'd2;
+  localparam RX_DONE    = 3'd3;
+  localparam RX_WAIT    = 3'd4;
+
+  reg [2:0]                   tx_state, rx_state;
+  reg [ERR_TIMEOUT_LOG2-1:0]  err_timeout;
+  reg [1:0]                   test_pattern;
+  reg                         rearm_test;
+
+  reg [17:0]  tx_pkt_cnt, rx_pkt_cnt;
+  reg [13:0]  tx_byte_cnt, rx_byte_cnt;
+  reg [23:0]  test_run_cnt;
+  reg [15:0]  tx_delay;
+  reg [7:0]   rx_delay;
+  wire [63:0] tx_cvita_hdr, rx_cvita_hdr;
+
+  wire tx_next_pkt_cond, rx_next_pkt_cond;
+  assign tx_next_pkt_cond = (tx_byte_cnt[12:3] == bist_max_pkt_size[12:3]) ||               //Packet size reaches max OR
+                            (bist_size_ramp && ({7'h0, tx_byte_cnt[13:3]} == tx_pkt_cnt));  //Packet size / 8 == Packet Count
+  assign rx_next_pkt_cond = (rx_byte_cnt[12:3] == bist_max_pkt_size[12:3]) || 
+                            (bist_size_ramp && ({7'h0, rx_byte_cnt[13:3]} == rx_pkt_cnt));
+
+  wire tx_test_done_cond, rx_test_done_cond;
+  assign tx_test_done_cond = (tx_pkt_cnt == bist_max_pkts);
+  assign rx_test_done_cond = (rx_pkt_cnt == bist_max_pkts);
+  
+  reg [63:0] tx_data_next, rx_data_exp;
+  always @(*) begin
+    case (test_pattern)
+      TEST_PATT_ZERO_ONE: begin
+        tx_data_next  <= {8{tx_byte_cnt[3] ? 8'h00 : 8'hFF}};
+        rx_data_exp   <= {8{rx_byte_cnt[3] ? 8'h00 : 8'hFF}};
+      end
+      TEST_PATT_CHECKERBOARD: begin
+        tx_data_next  <= {32{tx_byte_cnt[3] ? 2'b01 : 2'b10}};
+        rx_data_exp   <= {32{rx_byte_cnt[3] ? 2'b01 : 2'b10}};
+      end
+      TEST_PATT_COUNT: begin
+        tx_data_next  <= {8{tx_byte_cnt[10:3]}};
+        rx_data_exp   <= {8{rx_byte_cnt[10:3]}};
+      end
+      TEST_PATT_COUNT_INV: begin
+        tx_data_next  <= {8{(tx_byte_cnt[3] ? 8'hFF : 8'h00) ^ tx_byte_cnt[10:3]}};
+        rx_data_exp   <= {8{(rx_byte_cnt[3] ? 8'hFF : 8'h00) ^ rx_byte_cnt[10:3]}};
+      end
+      default: begin
+        tx_data_next  <= 64'd0;
+        rx_data_exp   <= 64'd0;
+      end
+    endcase
+  end
+
+  //NOTE: We always attach the max size in the packet header for simplicity.
+  //      This will not work with state machines that validate the packet length in the
+  //      header with the tlast position.
+  assign tx_cvita_hdr = {4'h0, tx_pkt_cnt[11:0], 2'b00, bist_max_pkt_size, bist_cvita_sid};
+  assign rx_cvita_hdr = {4'h0, rx_pkt_cnt[11:0], 2'b00, bist_max_pkt_size, bist_cvita_sid};
+
+  reg [63:0] o_tdata_fail;
+  assign status_vtr = {     //Status at the time of failure
+    o_tdata_fail,           //[127:64]
+    test_run_cnt,           //[63:40]
+    rx_data_exp[7:0],       //[39:32]
+    rx_pkt_cnt,             //[31:14]
+    rx_byte_cnt             //[13:0]
+  };
+
+  //-------------------------------------------------------
+  // Transmitter
+  //-------------------------------------------------------
+  always @(posedge clk) begin
+    if (reset | (bist_clear & ~rearm_test)) begin
+      tx_delay      <= 0;
+      tx_pkt_cnt    <= 0;
+      tx_byte_cnt   <= 0;
+      i_tdata       <= 64'h0;
+      i_tlast       <= 1'b0;
+      i_tvalid      <= 1'b0;
+      tx_state      <= TX_IDLE;
+    end else begin
+      case(tx_state)
+        TX_IDLE: begin
+          tx_delay      <= 0;
+          tx_pkt_cnt    <= 1;
+          tx_byte_cnt   <= 0;
+          i_tdata       <= 64'h0;
+          i_tlast       <= 1'b0;
+          i_tvalid      <= 1'b0;
+          // Run when bist_start asserted.
+          if (bist_start | rearm_test) begin
+            tx_state      <= TX_START;
+            test_pattern  <= bist_test_patt;
+          end
+        end // case: TX_IDLE
+
+        // START signal is asserted.
+        // Now need to start transmiting a packet.
+        TX_START: begin
+          // At the next clock edge drive first beat of new packet onto HDR bus.
+          i_tlast     <= 1'b0;
+          i_tvalid    <= 1'b1;
+          tx_byte_cnt <= tx_byte_cnt + 8;
+          i_tdata     <= tx_cvita_hdr;
+          tx_state    <= TX_ACTIVE;
+        end
+
+        // Valid data is (already) being driven onto the CHDR bus.
+        // i_tlast may also be driven asserted if current data count has reached EOP.
+        // Watch i_tready to see when it's consumed.
+        // When packets are consumed increment data counter or transition state if
+        // EOP has sucsesfully concluded.
+        TX_ACTIVE: begin
+          i_tvalid <= 1'b1; // Always assert tvalid
+          if (i_tready) begin
+            i_tdata <= tx_data_next;
+            // Will this next beat be the last in a packet?
+            if (tx_next_pkt_cond) begin
+              tx_byte_cnt <= 0;
+              i_tlast     <= 1'b1;
+              tx_state    <= TX_GAP;
+            end else begin
+              tx_byte_cnt <= tx_byte_cnt + 8;
+              i_tlast     <= 1'b0;
+              tx_state    <= TX_ACTIVE;
+            end
+          end else begin
+            //Keep driving all CHDR bus signals as-is until i_tready is asserted.
+            tx_state <= TX_ACTIVE;
+          end
+        end // case: TX_ACTIVE
+
+        // Force an inter-packet gap between packets in a BIST sequence where tvalid is driven low.
+        // As we leave this state check if all packets in BIST sequence have been generated yet,
+        // and if so go to done state.
+        TX_GAP: begin
+          if (i_tready) begin
+            i_tvalid    <= 1'b0;
+            i_tdata     <= 64'h0;
+            i_tlast     <= 1'b0;
+            tx_pkt_cnt  <= tx_pkt_cnt + 1;
+
+            if (tx_test_done_cond) begin
+              tx_state <= TX_DONE;
+            end else begin
+              tx_state <= TX_WAIT;
+              tx_delay <= bist_tx_pkt_delay;
+            end
+          end else begin // if (i_tready)
+            tx_state <= TX_GAP;
+          end
+        end // case: TX_GAP
+
+        // Simulate inter packet gap in real UHD system
+        TX_WAIT: begin
+          if (tx_delay == 0)
+            tx_state <= TX_START;
+          else begin
+            tx_delay <= tx_delay - 1;
+            tx_state <= TX_WAIT;
+          end
+        end
+
+        // Complete test pattern BIST sequence has been transmitted.
+        // Sit in this state until the RX side consumes all packets except
+        // for when the test is running in continuous mode.
+        TX_DONE: begin
+          i_tvalid  <= 1'b0;
+          i_tlast   <= 1'b0;
+          i_tdata   <= 64'd0;
+
+          if (running & ~rearm_test) begin
+            tx_state <= TX_DONE;
+          end else begin
+            tx_state <= TX_IDLE;
+          end
+        end
+      endcase // case (tx_state)
+    end
+  end
+
+  //-------------------------------------------------------
+  // Receiver
+  //-------------------------------------------------------
+  always @(posedge clk) begin
+    if (reset | (bist_clear & ~rearm_test)) begin
+      rx_delay      <= 0;
+      rx_pkt_cnt    <= 0;
+      rx_byte_cnt   <= 0;
+      o_tdata_fail  <= 64'h0;
+      o_tready      <= 1'b0;
+      error         <= ERR_SUCCESS;
+      done          <= 1'b0;
+      rx_state      <= RX_IDLE;
+      err_timeout   <= {ERR_TIMEOUT_LOG2{1'b0}};
+      test_run_cnt  <= 0;
+    end else begin
+      case(rx_state)
+        RX_IDLE: begin
+          rx_delay      <= 0;
+          rx_pkt_cnt    <= 1;
+          rx_byte_cnt   <= 0;
+          o_tdata_fail  <= 64'h0;
+          o_tready      <= 1'b0;
+          error         <= ERR_SUCCESS;
+          done          <= 1'b0;
+          err_timeout   <= {ERR_TIMEOUT_LOG2{1'b0}};
+          // Not accepting data whilst Idle,
+          // switch to active when packet arrives
+          if (o_tvalid) begin
+            o_tready <= 1'b1;
+            rx_state <= RX_ACTIVE;
+          end else begin
+            rx_state <= RX_IDLE;
+          end
+        end
+
+        RX_ACTIVE: begin
+          o_tready <= 1'b1;
+          if (o_tvalid) begin
+            if (o_tdata != (rx_byte_cnt == 0 ? rx_cvita_hdr : rx_data_exp)) begin
+              $display("axis_test_pattern: o_tdata: %x  !=  expected:  %x @ time: %d", o_tdata, rx_data_exp, $time);
+              error         <= ERR_DATA_MISMATCH;
+              rx_state      <= RX_FAIL;
+              o_tdata_fail  <= o_tdata;
+            end else if (rx_next_pkt_cond) begin
+              // Last not asserted when it should be!
+              if (~(o_tlast === 1)) begin
+                $display("axis_test_pattern: o_tlast not asserted when it should be @ time: %d", $time);
+                error    <= ERR_SIZE_MISMATCH_TOO_LONG;
+                rx_state <= RX_FAIL;
+              end else begin
+                // End of packet, set up to RX next
+                rx_byte_cnt <= 0;
+                rx_pkt_cnt  <= rx_pkt_cnt + 1;
+                rx_delay    <= bist_rx_samp_delay;
+                if (rx_test_done_cond) begin
+                  rx_state      <= rearm_test ? RX_IDLE : RX_DONE;
+                  error         <= ERR_SUCCESS;
+                  test_run_cnt  <= test_run_cnt + 1;
+                end else begin
+                  rx_state      <= RX_WAIT;
+                end
+                o_tready        <= 1'b0;
+              end
+            end else begin
+              // ...last asserted when it should not be!
+              if (~(o_tlast === 0)) begin
+                $display("axis_test_pattern: o_tlast asserted when it should not be @ time: %d", $time);
+                error       <= ERR_SIZE_MISMATCH_TOO_SHORT;
+                rx_state    <= RX_FAIL;
+              end else begin
+                // Still in packet body
+                rx_byte_cnt <= rx_byte_cnt + 8;
+                rx_delay    <= bist_rx_samp_delay;
+                if (bist_rx_samp_delay == 0) begin
+                  rx_state    <= RX_ACTIVE;
+                end else begin
+                  rx_state    <= RX_WAIT;
+                  o_tready    <= 1'b0;
+                end
+              end
+            end
+          end else begin
+            // Nothing to do this cycle
+            rx_state <= RX_ACTIVE;
+          end
+        end // case: RX_ACTIVE
+
+        // To simulate the radio consuming samples at a steady rate set by the decimation
+        // have a programable delay here
+        RX_WAIT: begin
+          if (rx_delay == 0) begin
+            rx_state <= RX_ACTIVE;
+            o_tready <= 1'b1;
+          end else begin
+            rx_delay <= rx_delay - 1;
+            rx_state <= RX_WAIT;
+          end
+        end
+
+        RX_FAIL: begin
+          //The test has failed but the sender still has packets en route
+          //Consume all of them before asserting done. Packets could be
+          //malformed so just blindly consume lines and count cycles of
+          //gaps. If non-valid cycles are more than 2^ERR_TIMEOUT_LOG2 then stop.
+          o_tready <= 1'b1;
+          if (~o_tvalid) begin
+            if (err_timeout == {ERR_TIMEOUT_LOG2{1'b1}}) begin
+              rx_state <= RX_DONE;
+            end
+            err_timeout <= err_timeout + 1;
+          end
+        end
+
+        RX_DONE: begin
+          o_tready    <= 1'b0;
+          done        <= 1'b1;
+          //The only way to exit this state is by asserting bist_clear
+        end
+      endcase // case (rx_state)
+    end
+  end
+
+  //-------------------------------------------------------
+  // Status Monitor
+  //-------------------------------------------------------
+  always @(posedge clk) begin
+    if (reset)
+      running <= 1'b0;
+    else if (tx_state == TX_START)
+      running <= 1'b1;
+    else if (rx_state == RX_DONE)
+      running <= 1'b0;
+  end
+
+  always @(posedge clk) begin
+    if (reset | bist_clear)
+      rearm_test  <= 1'b0;
+    else if (bist_start & bist_cont)
+      rearm_test  <= 1'b1;
+    else if (rx_state == RX_FAIL)
+      rearm_test  <= 1'b0;
+  end
+  
+  //-------------------------------------------------------
+  // Bandwidth Counter
+  //-------------------------------------------------------
+  generate if (BW_COUNTER) begin
+    reg [47:0]         word_count, cyc_count;
+    assign bw_ratio = {word_count, cyc_count};
+
+    //Count number of lines transferred
+    always @(posedge clk) begin
+      if (reset| (bist_clear & ~rearm_test) | bist_start)
+        word_count  <= 48'd0;
+      else if (o_tvalid && rx_state == RX_ACTIVE)
+        word_count  <= word_count + 48'd1;
+    end
+
+    //Count cycles as long as test is running
+    always @(posedge clk) begin
+      if (reset| (bist_clear & ~rearm_test) | bist_start)
+        cyc_count   <= 48'd0;
+      else if (rx_state == RX_ACTIVE || rx_state == RX_WAIT)
+        cyc_count   <= cyc_count + 48'd1;
+    end
+  end else begin
+    assign bw_ratio = 96'h0;
+  end endgenerate
+
+endmodule
diff --git a/fpga/usrp3/lib/axi/axi_defs.v b/fpga/usrp3/lib/axi/axi_defs.v
new file mode 100644
index 000000000..f6f5a1ede
--- /dev/null
+++ b/fpga/usrp3/lib/axi/axi_defs.v
@@ -0,0 +1,40 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+//
+// AXI4 Burst enumeration
+//
+`define AXI4_BURST_FIXED 2'b00
+`define AXI4_BURST_INCR 2'b01
+`define AXI4_BURST_WRAP 2'b10
+`define AXI4_BURST_RSVD 2'b11
+//
+// AXI4 response code enumeration
+//
+`define AXI4_RESP_OKAY 2'b00
+`define AXI4_RESP_EXOKAY 2'b01
+`define AXI4_RESP_SLVERR 2'b10
+`define AXI4_RESP_DECERR 2'b11
+//
+// AXI4 lock enumeration
+//
+`define AXI4_LOCK_NORMAL 1'b0
+`define AXI4_LOCK_EXCLUSIVE 1'b1
+//
+// AXI4 memory attrubutes
+//
+`define AXI4_CACHE_ALLOCATE 4'h8
+`define AXI4_CACHE_OTHER_ALLOCATE 4'h4
+`define AXI4_CACHE_MODIFIABLE 4'h2
+`define AXI4_CACHE_BUFFERABLE 4'h1
+//
+// AXI4 PROT attributes
+//
+`define AXI4_PROT_PRIVILEDGED 3'h1
+`define AXI4_PROT_NON_SECURE 3'h2
+`define AXI4_PROT_INSTRUCTION 3'h4
+
+
diff --git a/fpga/usrp3/lib/axi/axi_dma_fifo.v b/fpga/usrp3/lib/axi/axi_dma_fifo.v
new file mode 100644
index 000000000..3664b43b3
--- /dev/null
+++ b/fpga/usrp3/lib/axi/axi_dma_fifo.v
@@ -0,0 +1,1073 @@
+//
+// Copyright 2015 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+//
+// There are various obligations put on this code not present in regular BRAM based FIFO's
+//
+// 1) Bursts are way more efficient, use local small FIFO's to interact with DRAM
+// 2) Never cross a 4KByte address boundary within a single transaction, this is an AXI4 rule.
+// 3) 2^SIZE must be greater than 4KB so that the 4KByte page protection also deals with FIFO wrap corner case.
+//
+module axi_dma_fifo 
+#(
+   parameter SIMULATION       = 0,             // Shorten flush counter for simulation
+   parameter DEFAULT_BASE     = 30'h00000000,
+   parameter DEFAULT_MASK     = 30'hFF000000,
+   parameter DEFAULT_TIMEOUT  = 12'd256,
+   parameter BUS_CLK_RATE     = 32'd166666666,  // Frequency in Hz of bus_clk
+   parameter SR_BASE          = 0,              // Base address for settings registers
+   parameter EXT_BIST         = 0,              // If 1 then instantiate extended BIST with dynamic SID, delays and BW counters
+   parameter MAX_PKT_LEN      = 12              // Log2 of maximum packet length
+) (
+   input bus_clk,
+   input bus_reset, 
+   input dram_clk,
+   input dram_reset,
+   //
+   // AXI Write address channel
+   //
+   output [0 : 0] m_axi_awid,     // Write address ID. This signal is the identification tag for the write address signals
+   output [31 : 0] m_axi_awaddr,  // Write address. The write address gives the address of the first transfer in a write burst
+   output [7 : 0] m_axi_awlen,    // Burst length. The burst length gives the exact number of transfers in a burst.
+   output [2 : 0] m_axi_awsize,   // Burst size. This signal indicates the size of each transfer in the burst. 
+   output [1 : 0] m_axi_awburst,  // Burst type. The burst type and the size information, determine how the address is calculated
+   output [0 : 0] m_axi_awlock,   // Lock type. Provides additional information about the atomic characteristics of the transfer.
+   output [3 : 0] m_axi_awcache,  // Memory type. This signal indicates how transactions are required to progress
+   output [2 : 0] m_axi_awprot,   // Protection type. This signal indicates the privilege and security level of the transaction
+   output [3 : 0] m_axi_awqos,    // Quality of Service, QoS. The QoS identifier sent for each write transaction
+   output [3 : 0] m_axi_awregion, // Region identifier. Permits a single physical interface on a slave to be re-used.
+   output [0 : 0] m_axi_awuser,   // User signal. Optional User-defined signal in the write address channel.
+   output m_axi_awvalid,          // Write address valid. This signal indicates that the channel is signaling valid write addr
+   input m_axi_awready,           // Write address ready. This signal indicates that the slave is ready to accept an address
+   //
+   // AXI Write data channel.
+   //
+   output [63 : 0] m_axi_wdata,   // Write data
+   output [7 : 0] m_axi_wstrb,    // Write strobes. This signal indicates which byte lanes hold valid data.
+   output m_axi_wlast,            // Write last. This signal indicates the last transfer in a write burst
+   output [0 : 0] m_axi_wuser,    // User signal. Optional User-defined signal in the write data channel.
+   output m_axi_wvalid,           // Write valid. This signal indicates that valid write data and strobes are available. 
+   input m_axi_wready,            // Write ready. This signal indicates that the slave can accept the write data.
+   //
+   // AXI Write response channel signals
+   //
+   input [0 : 0] m_axi_bid,       // Response ID tag. This signal is the ID tag of the write response. 
+   input [1 : 0] m_axi_bresp,     // Write response. This signal indicates the status of the write transaction.
+   input [0 : 0] m_axi_buser,     // User signal. Optional User-defined signal in the write response channel.
+   input m_axi_bvalid,            // Write response valid. This signal indicates that the channel is signaling a valid response
+   output m_axi_bready,           // Response ready. This signal indicates that the master can accept a write response
+   //
+   // AXI Read address channel
+   //
+   output [0 : 0] m_axi_arid,     // Read address ID. This signal is the identification tag for the read address group of signals
+   output [31 : 0] m_axi_araddr,  // Read address. The read address gives the address of the first transfer in a read burst
+   output [7 : 0] m_axi_arlen,    // Burst length. This signal indicates the exact number of transfers in a burst.
+   output [2 : 0] m_axi_arsize,   // Burst size. This signal indicates the size of each transfer in the burst.
+   output [1 : 0] m_axi_arburst,  // Burst type. The burst type and the size information determine how the address for each transfer
+   output [0 : 0] m_axi_arlock,   // Lock type. This signal provides additional information about the atomic characteristics
+   output [3 : 0] m_axi_arcache,  // Memory type. This signal indicates how transactions are required to progress 
+   output [2 : 0] m_axi_arprot,   // Protection type. This signal indicates the privilege and security level of the transaction
+   output [3 : 0] m_axi_arqos,    // Quality of Service, QoS. QoS identifier sent for each read transaction.
+   output [3 : 0] m_axi_arregion, // Region identifier. Permits a single physical interface on a slave to be re-used
+   output [0 : 0] m_axi_aruser,   // User signal. Optional User-defined signal in the read address channel.
+   output m_axi_arvalid,          // Read address valid. This signal indicates that the channel is signaling valid read addr
+   input m_axi_arready,           // Read address ready. This signal indicates that the slave is ready to accept an address
+   //
+   // AXI Read data channel
+   //
+   input [0 : 0] m_axi_rid,       // Read ID tag. This signal is the identification tag for the read data group of signals
+   input [63 : 0] m_axi_rdata,    // Read data.
+   input [1 : 0] m_axi_rresp,     // Read response. This signal indicates the status of the read transfer
+   input m_axi_rlast,             // Read last. This signal indicates the last transfer in a read burst.
+   input [0 : 0] m_axi_ruser,     // User signal. Optional User-defined signal in the read data channel.
+   input m_axi_rvalid,            // Read valid. This signal indicates that the channel is signaling the required read data. 
+   output m_axi_rready,           // Read ready. This signal indicates that the master can accept the read data and response
+   //
+   // CHDR friendly AXI stream input
+   //
+   input [63:0] i_tdata,
+   input i_tlast,
+   input i_tvalid,
+   output i_tready,
+   //
+   // CHDR friendly AXI Stream output
+   //
+   output [63:0] o_tdata,
+   output o_tlast,
+   output o_tvalid,
+   input o_tready,
+   //
+   // Settings and Readback
+   //
+   input              set_stb,
+   input [7:0]        set_addr,
+   input [31:0]       set_data,
+   output reg [31:0]  rb_data,
+   //
+   // Debug Bus
+   //
+   output [197:0] debug
+);
+
+   //
+   // We are only solving for width 64bits here, since it's our standard CHDR quanta
+   //
+   localparam DWIDTH = 64;
+   localparam AWIDTH = 30;  //Can address 1GiB of memory
+
+   //
+   // Settings and Readback
+   //
+   wire [2:0]         rb_addr;
+   wire               clear_bclk, flush_bclk;
+   wire               supress_enable_bclk;
+   wire [15:0]        supress_threshold_bclk;
+   wire [11:0]        timeout_bclk;
+   wire [AWIDTH-1:0]  fifo_base_addr_bclk;
+   wire [AWIDTH-1:0]  fifo_addr_mask_bclk;
+   wire [0:0]         ctrl_reserved;
+
+   wire [31:0]  rb_fifo_status;
+   wire [3:0]   rb_bist_status;
+   wire [95:0]  rb_bist_bw_ratio;
+   reg  [31:0]  out_pkt_count = 32'd0;
+
+   localparam RB_FIFO_STATUS    = 3'd0;
+   localparam RB_BIST_STATUS    = 3'd1;
+   localparam RB_BIST_XFER_CNT  = 3'd2;
+   localparam RB_BIST_CYC_CNT   = 3'd3;
+   localparam RB_BUS_CLK_RATE   = 3'd4;
+   localparam RB_OUT_PKT_CNT    = 3'd5;
+
+   // SETTING: Readback Address Register
+   // Fields:
+   // - [2:0]  : Address for readback register
+   //            - 0 = RB_FIFO_STATUS
+   //            - 1 = RB_BIST_STATUS
+   //            - 2 = RB_BIST_XFER_CNT
+   //            - 3 = RB_BIST_CYC_CNT
+   //            - 4 = RB_BUS_CLK_RATE
+   //            - rest reserved
+   setting_reg #(.my_addr(SR_BASE + 0), .awidth(8), .width(3), .at_reset(3'b000)) sr_readback
+     (.clk(bus_clk), .rst(bus_reset),
+      .strobe(set_stb), .addr(set_addr), .in(set_data),
+      .out(rb_addr), .changed());
+
+   // SETTING: FIFO Control Register
+   // Fields:
+   // - [0]     : Clear FIFO and discard stored data
+   // - [1]     : Enable read suppression to prioritize writes
+   // - [2]     : Flush all packets from the FIFO
+   // - [3]     : Reserved
+   // - [15:4]  : Timeout (in memory clock beats) for issuing smaller than optimal bursts
+   // - [31:16] : Read suppression threshold in number of words
+   setting_reg #(.my_addr(SR_BASE + 1), .awidth(8), .width(32), .at_reset({16'h0, DEFAULT_TIMEOUT[11:0], 1'b0, 1'b0, 1'b0, 1'b1})) sr_fifo_ctrl
+     (.clk(bus_clk), .rst(bus_reset),
+      .strobe(set_stb), .addr(set_addr), .in(set_data),
+      .out({supress_threshold_bclk, timeout_bclk, ctrl_reserved, flush_bclk, supress_enable_bclk, clear_bclk}), .changed());
+
+   // SETTING: Base Address for FIFO in memory space
+   // Fields:
+   // - [29:0]  : Base address
+   setting_reg #(.my_addr(SR_BASE + 2), .awidth(8), .width(AWIDTH), .at_reset(DEFAULT_BASE)) sr_fifo_base_addr
+     (.clk(bus_clk), .rst(bus_reset),
+      .strobe(set_stb), .addr(set_addr), .in(set_data),
+      .out(fifo_base_addr_bclk), .changed());
+
+   // SETTING: Address Mask for FIFO in memory space. The mask is ANDed with the base address to define
+   //          a unique address for this FIFO. A zero in the mask signifies that the DRAM FIFO can
+   //          utilize the address bit internally for maintaining FIFO data
+   // Fields:
+   // - [29:0]  : Address mask
+   setting_reg #(.my_addr(SR_BASE + 3), .awidth(8), .width(AWIDTH), .at_reset(DEFAULT_MASK)) sr_fifo_addr_mask
+     (.clk(bus_clk), .rst(bus_reset),
+      .strobe(set_stb), .addr(set_addr), .in(set_data),
+      .out(fifo_addr_mask_bclk), .changed());
+
+   always @(*) begin
+      case(rb_addr)
+         RB_FIFO_STATUS:      rb_data = rb_fifo_status;
+         RB_BIST_STATUS:      rb_data = {(EXT_BIST?1'b1:1'b0), 27'h0, rb_bist_status};
+         RB_BIST_XFER_CNT:    rb_data = rb_bist_bw_ratio[79:48];
+         RB_BIST_CYC_CNT:     rb_data = rb_bist_bw_ratio[31:0];
+         RB_BUS_CLK_RATE:     rb_data = BUS_CLK_RATE;
+         RB_OUT_PKT_CNT:      rb_data = out_pkt_count;
+         default:             rb_data = 32'h0;
+      endcase
+   end
+
+   //
+   // Synchronize settings register values to dram_clk
+   //
+   wire clear;
+   synchronizer #(.INITIAL_VAL(1'b1)) clear_sync_inst (.clk(dram_clk), .rst(1'b0), .in(clear_bclk), .out(clear));
+
+   wire               set_suppress_en;
+   wire [15:0]        set_supress_threshold;
+   wire [11:0]        set_timeout;
+   wire [AWIDTH-1:0]  set_fifo_base_addr, set_fifo_addr_mask, set_fifo_addr_mask_bar;
+
+   wire [(72-AWIDTH-29-1):0]  set_sync_discard0;
+   wire [(72-(2*AWIDTH)-1):0] set_sync_discard1;
+   fifo_short_2clk set_sync_fifo0(
+      .rst(bus_reset),
+      .wr_clk(bus_clk), .din({{(72-AWIDTH-29){1'b0}}, timeout_bclk, supress_enable_bclk, supress_threshold_bclk, fifo_base_addr_bclk}),
+      .wr_en(1'b1), .full(), .wr_data_count(),
+      .rd_clk(dram_clk), .dout({set_sync_discard0, set_timeout, set_suppress_en, set_supress_threshold, set_fifo_base_addr}),
+      .rd_en(1'b1), .empty(), .rd_data_count()
+   );
+   fifo_short_2clk set_sync_fifo1(
+      .rst(bus_reset),
+      .wr_clk(bus_clk), .din({{(72-(2*AWIDTH)){1'b0}}, ~fifo_addr_mask_bclk, fifo_addr_mask_bclk}),
+      .wr_en(1'b1), .full(), .wr_data_count(),
+      .rd_clk(dram_clk), .dout({set_sync_discard1, set_fifo_addr_mask_bar, set_fifo_addr_mask}),
+      .rd_en(1'b1), .empty(), .rd_data_count()
+   );
+
+   //
+   // Input side declarations
+   //
+   localparam [2:0] INPUT_IDLE = 0;
+   localparam [2:0] INPUT1 = 1;
+   localparam [2:0] INPUT2 = 2;
+   localparam [2:0] INPUT3 = 3;   
+   localparam [2:0] INPUT4 = 4;
+   localparam [2:0] INPUT5 = 5;
+   localparam [2:0] INPUT6 = 6;
+
+   reg [2:0]   input_state;
+   reg         input_timeout_triggered;
+   reg         input_timeout_reset;
+   reg [8:0]   input_timeout_count;
+   reg [AWIDTH-1:0]  write_addr;
+   reg         write_ctrl_valid;
+   wire        write_ctrl_ready;
+   reg [7:0]   write_count = 8'd0;
+   reg [8:0]   write_count_plus_one = 9'd1;  // Maintain a +1 version to break critical timing paths
+   reg         update_write;
+
+   //
+   // Output side declarations
+   //
+   localparam [2:0] OUTPUT_IDLE = 0;
+   localparam [2:0] OUTPUT1 = 1;
+   localparam [2:0] OUTPUT2 = 2;
+   localparam [2:0] OUTPUT3 = 3;   
+   localparam [2:0] OUTPUT4 = 4;
+   localparam [2:0] OUTPUT5 = 5;
+   localparam [2:0] OUTPUT6 = 6;
+
+   reg [2:0]   output_state;
+   reg         output_timeout_triggered;
+   reg         output_timeout_reset;
+   reg [8:0]   output_timeout_count;
+   reg [AWIDTH-1:0]  read_addr;
+   reg         read_ctrl_valid;
+   wire        read_ctrl_ready;
+   reg [7:0]   read_count = 8'd0; 
+   reg [8:0]   read_count_plus_one = 9'd1;  // Maintain a +1 version to break critical timing paths
+   reg         update_read;
+   
+   // Track main FIFO active size.
+   reg [AWIDTH-3:0] space, occupied, occupied_minus_one;  // Maintain a -1 version to break critical timing paths
+   reg [AWIDTH-3:0] input_page_boundry, output_page_boundry;  // Cache in a register to break critical timing paths
+
+   // Assign FIFO status bits
+   wire [71:0] status_out_bclk;
+   fifo_short_2clk status_fifo_2clk(
+      .rst(dram_reset),
+      .wr_clk(dram_clk), .din({{(72-(AWIDTH-2)){1'b0}}, occupied}),
+      .wr_en(1'b1), .full(), .wr_data_count(),
+      .rd_clk(bus_clk), .dout(status_out_bclk),
+      .rd_en(1'b1), .empty(), .rd_data_count()
+   );
+   assign rb_fifo_status[31]    = 1'b1;   //DRAM FIFO signature (validates existence of DRAM FIFO)
+   assign rb_fifo_status[30:27] = {o_tvalid, o_tready, i_tvalid, i_tready};   //Ready valid flags
+   assign rb_fifo_status[26:0]  = status_out_bclk[26:0];   //FIFO fullness count in 64bit words (max 27 bits = 1GiB)
+
+   ///////////////////////////////////////////////////////////////////////////////
+   // Inline BIST for production testing
+   //
+   wire       i_tready_int;
+
+   wire [DWIDTH-1:0] i_tdata_fifo;
+   wire       i_tvalid_fifo, i_tready_fifo, i_tlast_fifo;
+
+   wire [DWIDTH-1:0] i_tdata_bist;
+   wire       i_tvalid_bist, i_tready_bist, i_tlast_bist;
+
+   wire [DWIDTH-1:0] o_tdata_int;
+   wire       o_tvalid_int, o_tready_int, o_tlast_int;
+
+   wire [DWIDTH-1:0] o_tdata_fifo;
+   wire       o_tvalid_fifo, o_tready_fifo, o_tlast_fifo;
+
+   wire [DWIDTH-1:0] o_tdata_bist;
+   wire       o_tvalid_bist, o_tready_bist, o_tlast_bist;
+
+   wire [DWIDTH-1:0] o_tdata_gate;
+   wire       o_tvalid_gate, o_tready_gate, o_tlast_gate;
+
+   axi_mux4 #(.PRIO(1), .WIDTH(DWIDTH), .BUFFER(1)) axi_mux (
+      .clk(bus_clk), .reset(bus_reset), .clear(clear_bclk),
+      .i0_tdata(i_tdata), .i0_tlast(i_tlast), .i0_tvalid(i_tvalid), .i0_tready(i_tready_int),
+      .i1_tdata(i_tdata_bist), .i1_tlast(i_tlast_bist), .i1_tvalid(i_tvalid_bist), .i1_tready(i_tready_bist),
+      .i2_tdata({DWIDTH{1'b0}}), .i2_tlast(1'b0), .i2_tvalid(1'b0), .i2_tready(),
+      .i3_tdata({DWIDTH{1'b0}}), .i3_tlast(1'b0), .i3_tvalid(1'b0), .i3_tready(),
+      .o_tdata(i_tdata_fifo), .o_tlast(i_tlast_fifo), .o_tvalid(i_tvalid_fifo), .o_tready(i_tready_fifo)
+   );
+   assign i_tready = i_tready_int & (~clear_bclk);
+
+   wire       bist_running, bist_done;
+   wire [1:0] bist_error;
+   
+   axi_chdr_test_pattern #(
+     .DELAY_MODE(EXT_BIST ? "DYNAMIC" : "STATIC"), 
+     .SID_MODE(EXT_BIST ? "DYNAMIC" : "STATIC"), 
+     .BW_COUNTER(EXT_BIST ? 1 : 0),
+     .SR_BASE(SR_BASE + 4)
+   ) axi_chdr_test_pattern_i (
+      .clk(bus_clk), .reset(bus_reset | clear_bclk),
+      .i_tdata(i_tdata_bist), .i_tlast(i_tlast_bist), .i_tvalid(i_tvalid_bist), .i_tready(i_tready_bist),
+      .o_tdata(o_tdata_bist), .o_tlast(o_tlast_bist), .o_tvalid(o_tvalid_bist), .o_tready(o_tready_bist),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .running(bist_running), .done(bist_done), .error(bist_error), .status_vtr(), .bw_ratio(rb_bist_bw_ratio)
+   );
+   assign rb_bist_status = {bist_error, bist_done, bist_running};
+
+   axi_demux4 #(.ACTIVE_CHAN(4'b0011), .WIDTH(DWIDTH)) axi_demux(
+      .clk(bus_clk), .reset(bus_reset), .clear(clear_bclk),
+      .header(), .dest({1'b0, bist_running}),
+      .i_tdata(o_tdata_fifo), .i_tlast(o_tlast_fifo), .i_tvalid(o_tvalid_fifo), .i_tready(o_tready_fifo),
+      .o0_tdata(o_tdata_gate), .o0_tlast(o_tlast_gate), .o0_tvalid(o_tvalid_gate), .o0_tready(o_tready_gate),
+      .o1_tdata(o_tdata_bist), .o1_tlast(o_tlast_bist), .o1_tvalid(o_tvalid_bist), .o1_tready(o_tready_bist),
+      .o2_tdata(), .o2_tlast(), .o2_tvalid(), .o2_tready(1'b0),
+      .o3_tdata(), .o3_tlast(), .o3_tvalid(), .o3_tready(1'b0)
+   );
+
+   //Insert package gate before output to absorb any intra-packet bubble cycles
+   axi_packet_gate #(.WIDTH(DWIDTH), .SIZE(MAX_PKT_LEN)) out_pkt_gate (
+      .clk(bus_clk), .reset(bus_reset), .clear(clear_bclk),
+      .i_tdata(o_tdata_gate), .i_tlast(o_tlast_gate), .i_tvalid(o_tvalid_gate), .i_tready(o_tready_gate),
+      .i_terror(1'b0),
+      .o_tdata(o_tdata_int), .o_tlast(o_tlast_int), .o_tvalid(o_tvalid_int), .o_tready(o_tready_int)
+   );
+
+   axis_packet_flush #(
+      .WIDTH(DWIDTH), .FLUSH_PARTIAL_PKTS(0), .TIMEOUT_W(1), .PIPELINE("NONE")
+   ) flusher_i (
+      .clk(bus_clk), .reset(bus_reset),
+      .enable(clear_bclk | flush_bclk), .timeout(1'b0), .flushing(), .done(),
+      .s_axis_tdata(o_tdata_int), .s_axis_tlast(o_tlast_int),
+      .s_axis_tvalid(o_tvalid_int), .s_axis_tready(o_tready_int),
+      .m_axis_tdata(o_tdata), .m_axis_tlast(o_tlast),
+      .m_axis_tvalid(o_tvalid), .m_axis_tready(o_tready)
+   );
+
+   always @(posedge bus_clk) begin
+      if (bus_reset) begin
+        out_pkt_count <= 32'd0;
+      end else if (o_tlast_int & o_tvalid_int & o_tready_int) begin
+        out_pkt_count <= out_pkt_count + 32'd1;
+      end
+   end
+
+   //
+   // Buffer input in FIFO's. Embeded tlast signal using ESCape code.
+   //
+
+   wire [DWIDTH-1:0] i_tdata_i0;
+   wire             i_tvalid_i0, i_tready_i0, i_tlast_i0;
+ 
+   wire [DWIDTH-1:0] i_tdata_i1;
+   wire             i_tvalid_i1, i_tready_i1, i_tlast_i1;
+
+   wire [DWIDTH-1:0] i_tdata_i2;
+   wire             i_tvalid_i2, i_tready_i2;
+
+   wire [DWIDTH-1:0] i_tdata_i3;
+   wire             i_tvalid_i3, i_tready_i3;
+
+   wire [DWIDTH-1:0] i_tdata_input;
+   wire             i_tvalid_input, i_tready_input;
+   wire [15:0]      space_input, occupied_input;
+   reg [15:0]       space_input_reg;
+   reg              supress_reads;
+
+
+   ///////////////////////////////////////////////////////////////////////////////
+   
+   wire         write_in, read_in, empty_in, full_in;
+   assign       i_tready_fifo = ~full_in;
+   assign       write_in = i_tvalid_fifo & i_tready_fifo;
+   assign       i_tvalid_i0 = ~empty_in;
+   assign       read_in = i_tvalid_i0 & i_tready_i0;
+   wire [6:0]   discard_i0;
+   
+   fifo_short_2clk fifo_short_2clk_i0 (
+      .rst(bus_reset),
+      .wr_clk(bus_clk),
+      .din({7'h0,i_tlast_fifo,i_tdata_fifo}), // input [71 : 0] din
+      .wr_en(write_in), // input wr_en
+      .full(full_in), // output full
+      .wr_data_count(), // output [9 : 0] wr_data_count
+
+      .rd_clk(dram_clk), // input rd_clk
+      .dout({discard_i0,i_tlast_i0,i_tdata_i0}), // output [71 : 0] dout
+      .rd_en(read_in), // input rd_en
+      .empty(empty_in), // output empty
+      .rd_data_count()  // output [9 : 0] rd_data_count
+   );
+
+   axi_fifo_flop2 #(.WIDTH(DWIDTH+1)) input_pipe_i0
+     (
+      .clk(dram_clk), 
+      .reset(dram_reset), 
+      .clear(clear),
+      //
+      .i_tdata({i_tlast_i0, i_tdata_i0}), 
+      .i_tvalid(i_tvalid_i0), 
+      .i_tready(i_tready_i0),
+      //
+      .o_tdata({i_tlast_i1, i_tdata_i1}), 
+      .o_tvalid(i_tvalid_i1), 
+      .o_tready(i_tready_i1)
+   );
+
+   axi_embed_tlast #(.WIDTH(DWIDTH), .ADD_CHECKSUM(0)) axi_embed_tlast_i (
+      .clk(dram_clk),
+      .reset(dram_reset),
+      .clear(clear),
+      //
+      .i_tdata(i_tdata_i1),
+      .i_tlast(i_tlast_i1),
+      .i_tvalid(i_tvalid_i1),
+      .i_tready(i_tready_i1),
+      //
+      .o_tdata(i_tdata_i2),
+      .o_tvalid(i_tvalid_i2),
+      .o_tready(i_tready_i2)
+   );
+
+   axi_fifo_flop2 #(.WIDTH(DWIDTH)) input_pipe_i1 (
+      .clk(dram_clk), 
+      .reset(dram_reset), 
+      .clear(clear),
+      //
+      .i_tdata(i_tdata_i2), 
+      .i_tvalid(i_tvalid_i2), 
+      .i_tready(i_tready_i2),
+      //
+      .o_tdata(i_tdata_i3), 
+      .o_tvalid(i_tvalid_i3), 
+      .o_tready(i_tready_i3)
+   );
+
+   axi_fifo #(.WIDTH(DWIDTH),.SIZE(10)) fifo_i1 (
+      .clk(dram_clk), 
+      .reset(dram_reset), 
+      .clear(clear),
+      //
+      .i_tdata(i_tdata_i3), 
+      .i_tvalid(i_tvalid_i3), 
+      .i_tready(i_tready_i3),
+      //
+      .o_tdata(i_tdata_input), 
+      .o_tvalid(i_tvalid_input), 
+      .o_tready(i_tready_input),
+      //
+      .space(space_input), 
+      .occupied(occupied_input)
+   );
+
+   //
+   // Monitor occupied_input to deduce when DRAM FIFO is running short of bandwidth and there is a danger of backpressure
+   // passing upstream of the DRAM FIFO.
+   // In this situation supress read requests to the DRAM FIFO so that more bandwidth is available to writes.
+   //
+   always @(posedge dram_clk) 
+      begin
+         space_input_reg <= space_input;
+         if ((space_input_reg < set_supress_threshold[15:0])  && set_suppress_en)
+            supress_reads <= 1'b1;
+         else 
+            supress_reads <= 1'b0;
+      end
+
+   //
+   // Buffer output in 32entry FIFO's. Extract embeded tlast signal.
+   //
+   wire [DWIDTH-1:0] o_tdata_output;
+   wire             o_tvalid_output, o_tready_output;
+   wire [15:0]      space_output, occupied_output;
+
+   wire [DWIDTH-1:0] o_tdata_i0;
+   wire             o_tvalid_i0, o_tready_i0;
+   
+   wire [DWIDTH-1:0] o_tdata_i1;
+   wire             o_tvalid_i1, o_tready_i1;
+   
+   wire [DWIDTH-1:0] o_tdata_i2;
+   wire             o_tvalid_i2, o_tready_i2;
+   
+   wire [DWIDTH-1:0] o_tdata_i3;
+   wire             o_tvalid_i3, o_tready_i3;
+   
+   wire [DWIDTH-1:0] o_tdata_i4;
+   wire             o_tvalid_i4, o_tready_i4, o_tlast_i4;
+
+   wire [DWIDTH-1:0] o_tdata_i5;
+   wire             o_tvalid_i5, o_tready_i5, o_tlast_i5;
+
+   wire             checksum_error;
+
+   axi_fifo #(.WIDTH(DWIDTH),.SIZE(10)) fifo_i2 (
+      .clk(dram_clk), 
+      .reset(dram_reset), 
+      .clear(clear),
+      //
+      .i_tdata(o_tdata_output), 
+      .i_tvalid(o_tvalid_output), 
+      .i_tready(o_tready_output),
+      //
+      .o_tdata(o_tdata_i0), 
+      .o_tvalid(o_tvalid_i0), 
+      .o_tready(o_tready_i0),
+      //
+      .space(space_output), 
+      .occupied(occupied_output)
+   );
+
+   // Place FLops straight after SRAM read access for timing.
+   axi_fifo_flop2 #(.WIDTH(DWIDTH)) output_pipe_i0
+     (
+      .clk(dram_clk), 
+      .reset(dram_reset), 
+      .clear(clear),
+      //
+      .i_tdata(o_tdata_i0), 
+      .i_tvalid(o_tvalid_i0), 
+      .i_tready(o_tready_i0),
+      //
+      .o_tdata(o_tdata_i1), 
+      .o_tvalid(o_tvalid_i1), 
+      .o_tready(o_tready_i1 && ~supress_reads)
+   );
+
+   // Read suppression logic
+   // The CL part of this exists between these
+   // axi_flops 
+   axi_fifo_flop2 #(.WIDTH(DWIDTH)) output_pipe_i1
+     (
+      .clk(dram_clk), 
+      .reset(dram_reset), 
+      .clear(clear),
+      //
+      .i_tdata(o_tdata_i1), 
+      .i_tvalid(o_tvalid_i1 && ~supress_reads), 
+      .i_tready(o_tready_i1),
+      //
+      .o_tdata(o_tdata_i2), 
+      .o_tvalid(o_tvalid_i2), 
+      .o_tready(o_tready_i2)
+   );
+
+   // Pipeline flop before tlast extraction logic
+   axi_fifo_flop2 #(.WIDTH(DWIDTH)) output_pipe_i2
+     (
+      .clk(dram_clk), 
+      .reset(dram_reset), 
+      .clear(clear),
+      //
+      .i_tdata(o_tdata_i2), 
+      .i_tvalid(o_tvalid_i2), 
+      .i_tready(o_tready_i2),
+      //
+      .o_tdata(o_tdata_i3), 
+      .o_tvalid(o_tvalid_i3), 
+      .o_tready(o_tready_i3)
+   );
+
+    axi_extract_tlast #(.WIDTH(DWIDTH), .VALIDATE_CHECKSUM(0)) axi_extract_tlast_i (
+      .clk(dram_clk),
+      .reset(dram_reset),
+      .clear(clear),
+      //
+      .i_tdata(o_tdata_i3),
+      .i_tvalid(o_tvalid_i3),
+      .i_tready(o_tready_i3),
+      //
+      .o_tdata(o_tdata_i4),
+      .o_tlast(o_tlast_i4),
+      .o_tvalid(o_tvalid_i4),
+      .o_tready(o_tready_i4),
+      //
+      .checksum_error()
+   );
+
+   // Pipeline flop after tlast extraction logic
+   axi_fifo_flop2 #(.WIDTH(DWIDTH+1)) output_pipe_i3
+     (
+      .clk(dram_clk), 
+      .reset(dram_reset), 
+      .clear(clear),
+      //
+      .i_tdata({o_tlast_i4,o_tdata_i4}), 
+      .i_tvalid(o_tvalid_i4), 
+      .i_tready(o_tready_i4),
+      //
+      .o_tdata({o_tlast_i5,o_tdata_i5}), 
+      .o_tvalid(o_tvalid_i5), 
+      .o_tready(o_tready_i5)
+   );
+
+   wire         write_out, read_out, empty_out, full_out;
+   assign       o_tready_i5 = ~full_out;
+   assign       write_out = o_tvalid_i5 & o_tready_i5;
+   assign       o_tvalid_fifo = ~empty_out;
+   assign       read_out = o_tvalid_fifo & o_tready_fifo;
+   wire [6:0]   discard_i1;
+   
+   fifo_short_2clk fifo_short_2clk_i1 (
+      .rst(dram_reset),
+      .wr_clk(dram_clk),
+      .din({7'h0,o_tlast_i5,o_tdata_i5}), // input [71 : 0] din
+      .wr_en(write_out), // input wr_en
+      .full(full_out), // output full
+      .wr_data_count(), // output [9 : 0] wr_data_count
+
+      .rd_clk(bus_clk), // input rd_clk
+      .dout({discard_i1,o_tlast_fifo,o_tdata_fifo}), // output [71 : 0] dout
+      .rd_en(read_out), // input rd_en
+      .empty(empty_out), // output empty
+      .rd_data_count()  // output [9 : 0] rd_data_count
+   );
+
+   //
+   // Simple input timeout counter for now.
+   // Timeout count only increments when there is some data waiting to be written.
+   //
+   always @(posedge dram_clk)
+      if (dram_reset | clear) begin
+         input_timeout_count <= 9'd0;
+         input_timeout_triggered <= 1'b0;
+      end else if (input_timeout_reset) begin
+         input_timeout_count <= 9'd0;
+         input_timeout_triggered <= 1'b0;
+     end else if (input_timeout_count == set_timeout[8:0]) begin
+         input_timeout_triggered <= 1'b1;
+     end else if (input_state == INPUT_IDLE) begin
+         input_timeout_count <= input_timeout_count + ((occupied_input != 16'd0) ? 9'd1 : 9'd0);
+     end
+
+   //
+   // Wait for 16 entries in input FIFO to trigger DRAM write burst.
+   // Timeout can also trigger burst so fragments of data are not left to rot in the input FIFO.
+   // Also if enough data is present in the input FIFO to complete a burst upto the edge
+   // of a 4KByte page then immediately start the burst.
+   //
+   always @(posedge dram_clk)
+      if (dram_reset | clear) begin
+         input_state <= INPUT_IDLE;
+         write_addr <= set_fifo_base_addr & set_fifo_addr_mask;
+         input_timeout_reset <= 1'b0;
+         write_ctrl_valid <= 1'b0;
+         write_count <= 8'd0;
+         write_count_plus_one <= 9'd1;
+         update_write <= 1'b0;
+      end else
+         case (input_state)
+         //
+         // INPUT_IDLE.
+         // To start an input transfer to DRAM need:
+         // 1) Space in the DRAM FIFO 
+         // and either
+         // 2) 256 entrys in the input FIFO
+         // or
+         // 3) Timeout waiting for more data.
+         //
+         INPUT_IDLE: begin
+            write_ctrl_valid <= 1'b0;
+            update_write <= 1'b0;
+            if (space[AWIDTH-3:8] != 'd0) begin // (space > 255): Space in the DRAM FIFO
+               if (occupied_input[15:8] != 'd0) begin  // (occupied_input > 255): 256 or more entries in input FIFO
+                  input_state <= INPUT1;
+                  input_timeout_reset <= 1'b1;
+                  // Calculate number of entries remaining until next 4KB page boundry is crossed minus 1.
+                  // Note, units of calculation are 64bit wide words. Address is always 64bit alligned.
+                  input_page_boundry <= {write_addr[AWIDTH-1:12],9'h1ff} - write_addr[AWIDTH-1:3];   
+               end else if (input_timeout_triggered) begin // input FIFO timeout waiting for new data.
+                  input_state <= INPUT2;
+                  input_timeout_reset <= 1'b1;
+                  // Calculate number of entries remaining until next 4KB page boundry is crossed minus 1.
+                  // Note, units of calculation are 64bit wide words. Address is always 64bit alligned.
+                  input_page_boundry <= {write_addr[AWIDTH-1:12],9'h1ff} - write_addr[AWIDTH-1:3];   
+               end else begin
+                  input_timeout_reset <= 1'b0;
+                  input_state <= INPUT_IDLE;
+               end
+            end else begin
+               input_timeout_reset <= 1'b0;
+               input_state <= INPUT_IDLE;
+            end
+         end
+         //
+         // INPUT1.
+         // Caused by input FIFO reaching 256 entries.
+         // Request write burst of lesser of:
+         // 1) Entrys until page boundry crossed
+         // 2) 256.
+         //
+         INPUT1: begin
+            // Replicated write logic to break a read timing critical path for write_count
+            write_count <= (input_page_boundry[11:8] == 4'd0) ? input_page_boundry[7:0] : 8'd255;
+            write_count_plus_one <= (input_page_boundry[11:8] == 4'd0) ? ({1'b0,input_page_boundry[7:0]} + 9'd1) : 9'd256;
+            write_ctrl_valid <= 1'b1;
+            if (write_ctrl_ready)
+               input_state <= INPUT4; // Pre-emptive ACK
+            else
+               input_state <= INPUT3; // Wait for ACK
+         end
+         //
+         // INPUT2.
+         // Caused by timeout of input FIFO. (occupied_input was implicitly less than 256 last cycle)
+         // Request write burst of lesser of:
+         // 1) Entries until page boundry crossed
+         // 2) Entries in input FIFO
+         //
+         INPUT2: begin
+            // Replicated write logic to break a read timing critical path for write_count
+            write_count <= (input_page_boundry < ({3'h0,occupied_input[8:0]} - 12'd1)) ? input_page_boundry[7:0] : (occupied_input[8:0] - 9'd1);
+            write_count_plus_one <= (input_page_boundry < ({3'h0,occupied_input[8:0]} - 12'd1)) ? ({1'b0,input_page_boundry[7:0]} + 9'd1) : occupied_input[8:0];
+            write_ctrl_valid <= 1'b1;
+            if (write_ctrl_ready)
+               input_state <= INPUT4; // Pre-emptive ACK
+            else
+               input_state <= INPUT3; // Wait for ACK
+         end
+         //
+         // INPUT3.
+         // Wait in this state for AXI4_DMA engine to accept transaction.
+         //
+         INPUT3: begin
+            if (write_ctrl_ready) begin
+               write_ctrl_valid <= 1'b0;
+               input_state <= INPUT4; // ACK
+            end else begin
+               write_ctrl_valid <= 1'b1;
+               input_state <= INPUT3; // Wait for ACK
+            end
+         end
+         //
+         // INPUT4.
+         // Wait here until write_ctrl_ready_deasserts.
+         // This is important as the next time it asserts we know that a write response was receieved.
+         INPUT4: begin
+            write_ctrl_valid <= 1'b0;
+            if (!write_ctrl_ready)
+               input_state <= INPUT5; // Move on
+            else
+               input_state <= INPUT4; // Wait for deassert
+         end   
+         //
+         // INPUT5.
+         // Transaction has been accepted by AXI4 DMA engine. Now we wait for the re-assertion
+         // of write_ctrl_ready which signals that the AXI4 DMA engine has receieved a response
+         // for the whole write transaction and we assume that this means it is commited to DRAM.
+         // We are now free to update write_addr pointer and go back to idle state.
+         // 
+         INPUT5: begin
+            write_ctrl_valid <= 1'b0;
+            if (write_ctrl_ready) begin
+               write_addr <= ((write_addr + (write_count_plus_one << 3)) & set_fifo_addr_mask_bar) | (write_addr & set_fifo_addr_mask);
+               input_state <= INPUT6;
+               update_write <= 1'b1;
+            end else begin
+               input_state <= INPUT5;
+            end
+         end
+         //
+         // INPUT6:
+         // Need to let space update before looking if there's more to do.
+         //
+         INPUT6: begin
+            input_state <= INPUT_IDLE;
+            update_write <= 1'b0;
+         end
+
+         default: 
+            input_state <= INPUT_IDLE;
+      endcase // case(input_state)
+
+
+   //
+   // Simple output timeout counter for now
+   //
+   always @(posedge dram_clk)
+      if (dram_reset | clear) begin
+         output_timeout_count <= 9'd0;
+         output_timeout_triggered <= 1'b0;
+      end else if (output_timeout_reset) begin
+         output_timeout_count <= 9'd0;
+         output_timeout_triggered <= 1'b0;
+      end else if (output_timeout_count == set_timeout[8:0]) begin
+         output_timeout_triggered <= 1'b1;
+      end else if (output_state == OUTPUT_IDLE) begin
+         output_timeout_count <= output_timeout_count + ((occupied != 'd0) ? 9'd1 : 9'd0);
+     end
+
+
+   //
+   // Wait for 64 entries in main FIFO to trigger DRAM read burst.
+   // Timeout can also trigger burst so fragments of data are not left to rot in the main FIFO.
+   // Also if enough data is present in the main FIFO to complete a burst upto the edge
+   // of a 4KByte page then immediately start the burst.
+   //
+   always @(posedge dram_clk)
+      if (dram_reset | clear) begin
+         output_state <= OUTPUT_IDLE;
+         read_addr <= set_fifo_base_addr & set_fifo_addr_mask;
+         output_timeout_reset <= 1'b0;
+         read_ctrl_valid <= 1'b0;
+         read_count <= 8'd0;
+         read_count_plus_one <= 9'd1;
+         update_read <= 1'b0;
+      end else
+         case (output_state)
+         //
+         // OUTPUT_IDLE.
+         // To start an output tranfer from DRAM
+         // 1) Space in the small output FIFO 
+         // and either
+         // 2) 256 entrys in the DRAM FIFO
+         // or
+         // 3) Timeout waiting for more data.
+         //
+         OUTPUT_IDLE: begin
+            read_ctrl_valid <= 1'b0;
+            update_read <= 1'b0;
+            if (space_output[15:8] != 'd0) begin // (space_output > 255): Space in the output FIFO.
+               if (occupied[AWIDTH-3:8] != 'd0) begin // (occupied > 255): 64 or more entrys in main FIFO
+                  output_state <= OUTPUT1;
+                  output_timeout_reset <= 1'b1;
+                  // Calculate number of entries remaining until next 4KB page boundry is crossed minus 1.
+                  // Note, units of calculation are 64bit wide words. Address is always 64bit alligned.
+                  output_page_boundry <= {read_addr[AWIDTH-1:12],9'h1ff} - read_addr[AWIDTH-1:3];
+               end else if (output_timeout_triggered) begin // output FIFO timeout waiting for new data.
+                  output_state <= OUTPUT2;
+                  output_timeout_reset <= 1'b1;
+                  // Calculate number of entries remaining until next 4KB page boundry is crossed minus 1.
+                  // Note, units of calculation are 64bit wide words. Address is always 64bit alligned.
+                  output_page_boundry <= {read_addr[AWIDTH-1:12],9'h1ff} - read_addr[AWIDTH-1:3];
+               end else begin
+                  output_timeout_reset <= 1'b0;
+                  output_state <= OUTPUT_IDLE;
+               end
+            end else begin
+               output_timeout_reset <= 1'b0;
+               output_state <= OUTPUT_IDLE;
+            end
+         end // case: OUTPUT_IDLE
+         //
+         // OUTPUT1.
+         // Caused by main FIFO reaching 256 entries.
+         // Request read burst of lesser of lesser of:
+         // 1) Entrys until page boundry crossed
+         // 2) 256.
+         //
+         OUTPUT1: begin
+            // Replicated write logic to break a read timing critical path for read_count
+            read_count <= (output_page_boundry[11:8] == 4'd0) ? output_page_boundry[7:0] : 8'd255;
+            read_count_plus_one <= (output_page_boundry[11:8] == 4'd0) ? ({1'b0,output_page_boundry[7:0]} + 9'd1) : 9'd256;
+            read_ctrl_valid <= 1'b1;
+            if (read_ctrl_ready)
+               output_state <= OUTPUT4; // Pre-emptive ACK
+            else
+               output_state <= OUTPUT3; // Wait for ACK
+         end
+         //
+         // OUTPUT2.
+         // Caused by timeout of main FIFO
+         // Request read burst of lesser of:
+         // 1) Entries until page boundry crossed
+         // 2) Entries in main FIFO
+         //
+         OUTPUT2: begin
+            // Replicated write logic to break a read timing critical path for read_count
+            read_count <= (output_page_boundry < occupied_minus_one) ? output_page_boundry[7:0] : occupied_minus_one[7:0];
+            read_count_plus_one <= (output_page_boundry < occupied_minus_one) ? ({1'b0,output_page_boundry[7:0]} + 9'd1) : {1'b0, occupied[7:0]};
+            read_ctrl_valid <= 1'b1;
+            if (read_ctrl_ready)
+               output_state <= OUTPUT4; // Pre-emptive ACK
+            else
+               output_state <= OUTPUT3; // Wait for ACK
+         end
+         //
+         // OUTPUT3.
+         // Wait in this state for AXI4_DMA engine to accept transaction.
+         //
+         OUTPUT3: begin
+            if (read_ctrl_ready) begin
+               read_ctrl_valid <= 1'b0;
+               output_state <= OUTPUT4; // ACK
+            end else begin
+               read_ctrl_valid <= 1'b1;
+               output_state <= OUTPUT3; // Wait for ACK
+            end
+         end
+         //
+         // OUTPUT4.
+         // Wait here unitl read_ctrl_ready_deasserts.
+         // This is important as the next time it asserts we know that a read response was receieved.
+         OUTPUT4: begin
+            read_ctrl_valid <= 1'b0;
+            if (!read_ctrl_ready)
+               output_state <= OUTPUT5; // Move on
+            else
+               output_state <= OUTPUT4; // Wait for deassert
+         end   
+         //
+         // OUTPUT5.
+         // Transaction has been accepted by AXI4 DMA engine. Now we wait for the re-assertion
+         // of read_ctrl_ready which signals that the AXI4 DMA engine has receieved a last signal and good response
+         // for the whole read transaction.
+         // We are now free to update read_addr pointer and go back to idle state.
+         // 
+         OUTPUT5: begin
+            read_ctrl_valid <= 1'b0;
+            if (read_ctrl_ready) begin
+               read_addr <= ((read_addr + (read_count_plus_one << 3)) & set_fifo_addr_mask_bar) | (read_addr & set_fifo_addr_mask);
+               output_state <= OUTPUT6;
+               update_read <= 1'b1;
+            end else begin
+               output_state <= OUTPUT5;
+            end
+         end // case: OUTPUT5
+         //
+         // OUTPUT6.
+         // Need to get occupied value updated before checking if there's more to do.
+         //
+         OUTPUT6: begin
+            update_read <= 1'b0;
+            output_state <= OUTPUT_IDLE;
+         end
+
+         default: 
+            output_state <= OUTPUT_IDLE;
+       endcase // case(output_state)
+
+   //
+   // Count number of used entries in main DRAM FIFO.
+   // Note that this is expressed in units of 64bit wide words.
+   //
+   always @(posedge dram_clk)
+      if (dram_reset | clear) begin
+         occupied <= 'd0;
+         occupied_minus_one <= {(AWIDTH-2){1'b1}};
+      end else begin
+         occupied <= occupied + (update_write ? write_count_plus_one : 9'd0) - (update_read ? read_count_plus_one : 9'd0);
+         occupied_minus_one <= occupied_minus_one + (update_write ? write_count_plus_one : 9'd0) - (update_read ? read_count_plus_one : 9'd0);
+      end
+
+   always @(posedge dram_clk)
+      if (dram_reset | clear)
+         space <= set_fifo_addr_mask_bar[AWIDTH-1:3] & ~('d63); // Subtract 64 from space to make allowance for read/write reordering in DRAM controller
+      else
+         space <= space - (update_write ? write_count_plus_one : 9'd0) + (update_read ? read_count_plus_one : 9'd0);
+
+   //
+   // Instamce of axi_dma_master
+   //
+   axi_dma_master axi_dma_master_i
+   (
+      .aclk(dram_clk), // input aclk
+      .areset(dram_reset | clear), // input aresetn
+      // Write control
+      .m_axi_awid(m_axi_awid), // input [0 : 0] m_axi_awid
+      .m_axi_awaddr(m_axi_awaddr), // input [31 : 0] m_axi_awaddr
+      .m_axi_awlen(m_axi_awlen), // input [7 : 0] m_axi_awlen
+      .m_axi_awsize(m_axi_awsize), // input [2 : 0] m_axi_awsize
+      .m_axi_awburst(m_axi_awburst), // input [1 : 0] m_axi_awburst
+      .m_axi_awvalid(m_axi_awvalid), // input m_axi_awvalid
+      .m_axi_awready(m_axi_awready), // output m_axi_awready
+      .m_axi_awlock(m_axi_awlock),
+      .m_axi_awcache(m_axi_awcache),
+      .m_axi_awprot(m_axi_awprot),
+      .m_axi_awqos(m_axi_awqos),
+      .m_axi_awregion(m_axi_awregion),
+      .m_axi_awuser(m_axi_awuser),
+      // Write Data
+      .m_axi_wdata(m_axi_wdata), // input [63 : 0] m_axi_wdata
+      .m_axi_wstrb(m_axi_wstrb), // input [7 : 0] m_axi_wstrb
+      .m_axi_wlast(m_axi_wlast), // input m_axi_wlast
+      .m_axi_wvalid(m_axi_wvalid), // input m_axi_wvalid
+      .m_axi_wready(m_axi_wready), // output m_axi_wready
+      .m_axi_wuser(m_axi_wuser),
+      // Write Response
+      .m_axi_bid(m_axi_bid), // output [0 : 0] m_axi_bid
+      .m_axi_bresp(m_axi_bresp), // output [1 : 0] m_axi_bresp
+      .m_axi_bvalid(m_axi_bvalid), // output m_axi_bvalid
+      .m_axi_bready(m_axi_bready), // input m_axi_bready
+      .m_axi_buser(m_axi_buser),
+      // Read Control
+      .m_axi_arid(m_axi_arid), // input [0 : 0] m_axi_arid
+      .m_axi_araddr(m_axi_araddr), // input [31 : 0] m_axi_araddr
+      .m_axi_arlen(m_axi_arlen), // input [7 : 0] m_axi_arlen
+      .m_axi_arsize(m_axi_arsize), // input [2 : 0] m_axi_arsize
+      .m_axi_arburst(m_axi_arburst), // input [1 : 0] m_axi_arburst
+      .m_axi_arvalid(m_axi_arvalid), // input m_axi_arvalid
+      .m_axi_arready(m_axi_arready), // output m_axi_arready
+      .m_axi_arlock(m_axi_arlock),
+      .m_axi_arcache(m_axi_arcache),
+      .m_axi_arprot(m_axi_arprot),
+      .m_axi_arqos(m_axi_arqos),
+      .m_axi_arregion(m_axi_arregion),
+      .m_axi_aruser(m_axi_aruser),
+      // Read Data
+      .m_axi_rid(m_axi_rid), // output [0 : 0] m_axi_rid
+      .m_axi_rdata(m_axi_rdata), // output [63 : 0] m_axi_rdata
+      .m_axi_rresp(m_axi_rresp), // output [1 : 0] m_axi_rresp
+      .m_axi_rlast(m_axi_rlast), // output m_axi_rlast
+      .m_axi_rvalid(m_axi_rvalid), // output m_axi_rvalid
+      .m_axi_rready(m_axi_rready), // input m_axi_rready
+      .m_axi_ruser(m_axi_ruser),
+      //
+      // DMA interface for Write transaction
+      //
+      .write_addr({{(32-AWIDTH){1'b0}}, write_addr}),       // Byte address for start of write transaction (should be 64bit alligned)
+      .write_count(write_count),       // Count of 64bit words to write.
+      .write_ctrl_valid(write_ctrl_valid),
+      .write_ctrl_ready(write_ctrl_ready),
+      .write_data(i_tdata_input),
+      .write_data_valid(i_tvalid_input),
+      .write_data_ready(i_tready_input),
+      //
+      // DMA interface for Read
+      //
+      .read_addr({{(32-AWIDTH){1'b0}}, read_addr}),       // Byte address for start of read transaction (should be 64bit alligned)
+      .read_count(read_count),       // Count of 64bit words to read.
+      .read_ctrl_valid(read_ctrl_valid),
+      .read_ctrl_ready(read_ctrl_ready),
+      .read_data(o_tdata_output),
+      .read_data_valid(o_tvalid_output),
+      .read_data_ready(o_tready_output),
+      //
+      // Debug
+      //
+      .debug()
+   );
+
+  //ila_axi_dma_fifo inst_ila (
+  //  .clk(ce_clk), // input wire clk
+  //  .probe0(rb_bist_status), // input wire [3:0]  probe0  channel 0
+  //  .probe1(), // input wire [3:0]  probe0  channel 0
+  //);
+
+
+
+
+ endmodule // axi_dma_fifo
+
diff --git a/fpga/usrp3/lib/axi/axi_dma_master.v b/fpga/usrp3/lib/axi/axi_dma_master.v
new file mode 100644
index 000000000..59e2e97a7
--- /dev/null
+++ b/fpga/usrp3/lib/axi/axi_dma_master.v
@@ -0,0 +1,548 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+`include "axi_defs.v"
+
+`define DEBUG if (0)
+
+module axi_dma_master #(
+   parameter AWIDTH = 32,
+   parameter DWIDTH = 64
+) (
+   input aclk,                    // Global AXI clock
+   input areset,                 // Global AXI reset
+   //
+   // AXI Write address channel
+   //
+   output [0 : 0] m_axi_awid,     // Write address ID. This signal is the identification tag for the write address signals
+   output reg [AWIDTH-1 : 0] m_axi_awaddr,  // Write address. The write address gives the address of the first transfer in a write burst
+   output reg [7 : 0] m_axi_awlen,    // Burst length. The burst length gives the exact number of transfers in a burst.
+   output [2 : 0] m_axi_awsize,   // Burst size. This signal indicates the size of each transfer in the burst. 
+   output [1 : 0] m_axi_awburst,  // Burst type. The burst type and the size information, determine how the address is calculated
+   output [0 : 0] m_axi_awlock,   // Lock type. Provides additional information about the atomic characteristics of the transfer.
+   output [3 : 0] m_axi_awcache,  // Memory type. This signal indicates how transactions are required to progress
+   output [2 : 0] m_axi_awprot,   // Protection type. This signal indicates the privilege and security level of the transaction
+   output [3 : 0] m_axi_awqos,    // Quality of Service, QoS. The QoS identifier sent for each write transaction
+   output [3 : 0] m_axi_awregion, // Region identifier. Permits a single physical interface on a slave to be re-used.
+   output [0 : 0] m_axi_awuser,   // User signal. Optional User-defined signal in the write address channel.
+   output reg m_axi_awvalid,      // Write address valid. This signal indicates that the channel is signaling valid write addr
+   input m_axi_awready,           // Write address ready. This signal indicates that the slave is ready to accept an address
+   //
+   // AXI Write data channel.
+   //
+   output [DWIDTH-1 : 0] m_axi_wdata,   // Write data
+   output [DWIDTH/8-1 : 0] m_axi_wstrb,    // Write strobes. This signal indicates which byte lanes hold valid data.
+   output reg m_axi_wlast,        // Write last. This signal indicates the last transfer in a write burst
+   output m_axi_wuser,            // User signal. Optional User-defined signal in the write data channel.
+   output m_axi_wvalid,           // Write valid. This signal indicates that valid write data and strobes are available. 
+   input m_axi_wready,            // Write ready. This signal indicates that the slave can accept the write data.
+   //
+   // AXI Write response channel signals
+   //
+   input [0 : 0] m_axi_bid,       // Response ID tag. This signal is the ID tag of the write response. 
+   input [1 : 0] m_axi_bresp,     // Write response. This signal indicates the status of the write transaction.
+   input [0 : 0] m_axi_buser,     // User signal. Optional User-defined signal in the write response channel.
+   input m_axi_bvalid,            // Write response valid. This signal indicates that the channel is signaling a valid response
+   output reg m_axi_bready,       // Response ready. This signal indicates that the master can accept a write response
+   //
+   // AXI Read address channel
+   //
+   output [0 : 0] m_axi_arid,     // Read address ID. This signal is the identification tag for the read address group of signals
+   output reg [AWIDTH-1 : 0] m_axi_araddr,  // Read address. The read address gives the address of the first transfer in a read burst
+   output reg [7 : 0] m_axi_arlen,    // Burst length. This signal indicates the exact number of transfers in a burst.
+   output [2 : 0] m_axi_arsize,   // Burst size. This signal indicates the size of each transfer in the burst.
+   output [1 : 0] m_axi_arburst,  // Burst type. The burst type and the size information determine how the address for each transfer
+   output [0 : 0] m_axi_arlock,   // Lock type. This signal provides additional information about the atomic characteristics
+   output [3 : 0] m_axi_arcache,  // Memory type. This signal indicates how transactions are required to progress 
+   output [2 : 0] m_axi_arprot,   // Protection type. This signal indicates the privilege and security level of the transaction
+   output [3 : 0] m_axi_arqos,    // Quality of Service, QoS. QoS identifier sent for each read transaction.
+   output [3 : 0] m_axi_arregion, // Region identifier. Permits a single physical interface on a slave to be re-used
+   output [0 : 0] m_axi_aruser,   // User signal. Optional User-defined signal in the read address channel.
+   output reg m_axi_arvalid,          // Read address valid. This signal indicates that the channel is signaling valid read addr
+   input m_axi_arready,           // Read address ready. This signal indicates that the slave is ready to accept an address
+   //
+   // AXI Read data channel
+   //
+   input [0 : 0] m_axi_rid,       // Read ID tag. This signal is the identification tag for the read data group of signals
+   input [DWIDTH-1 : 0] m_axi_rdata,    // Read data.
+   input [1 : 0] m_axi_rresp,     // Read response. This signal indicates the status of the read transfer
+   input m_axi_rlast,             // Read last. This signal indicates the last transfer in a read burst.
+   input [0 : 0] m_axi_ruser,     // User signal. Optional User-defined signal in the read data channel.
+   input m_axi_rvalid,            // Read valid. This signal indicates that the channel is signaling the required read data. 
+   output m_axi_rready,           // Read ready. This signal indicates that the master can accept the read data and response
+   //
+   // DMA interface for Write transaction
+   //
+   input [AWIDTH-1:0] write_addr,       // Byte address for start of write transaction (should be 64bit alligned)
+   input [7:0] write_count,       // Count of 64bit words to write. (minus one)
+   input write_ctrl_valid,
+   output reg write_ctrl_ready,
+   input [DWIDTH-1:0] write_data,
+   input write_data_valid,
+   output write_data_ready,
+   //
+   // DMA interface for Read
+   //
+   input [AWIDTH-1:0] read_addr,       // Byte address for start of read transaction (should be 64bit alligned)
+   input [7:0] read_count,       // Count of 64bit words to read.
+   input read_ctrl_valid,
+   output reg read_ctrl_ready,
+   output [DWIDTH-1:0] read_data,
+   output read_data_valid,
+   input read_data_ready,
+   //
+   // Debug Bus
+   //
+   output [31:0] debug
+   
+   );
+ 
+   
+   localparam AW_IDLE = 0;
+   localparam WAIT_AWREADY = 1;
+   localparam WAIT_BVALID = 2;
+   localparam AW_ERROR = 3;
+   
+   reg [1:0] write_addr_state;  
+   reg [7:0] write_data_count;         // Count write transfers.
+   reg 	     enable_data_write;
+   
+   localparam DW_IDLE = 0;
+   localparam DW_RUN = 1;
+   localparam DW_LAST = 2;
+   
+   reg [1:0]  write_data_state;
+   
+   localparam AR_IDLE = 0;
+   localparam WAIT_ARREADY = 1;
+   localparam WAIT_READ_DONE = 2;
+   localparam AR_ERROR = 3;
+   
+   reg [1:0]  read_addr_state;
+
+   localparam DR_IDLE = 0;
+   localparam DR_RUN = 1;
+   localparam DR_WAIT_ERROR = 2;
+   localparam DR_ERROR = 3;
+
+   reg [1:0]  read_data_state;
+   reg [7:0]  read_data_count;
+   reg 	      enable_data_read;
+
+   ///////////////////////////
+   // DEBUG
+   ///////////////////////////
+   assign debug= {24'h0,write_addr_state[1:0],write_data_state[1:0],read_addr_state[1:0],read_data_state[1:0]};
+   
+   
+   //
+   //
+   //
+   
+   
+   
+   
+   /////////////////////////////////////////////////////////////////////////////////
+   //
+   // AXI Write address channel
+   //
+   /////////////////////////////////////////////////////////////////////////////////
+   assign m_axi_awid = 1'b0;
+   assign m_axi_awsize = $clog2(DWIDTH/8);
+   assign m_axi_awburst = `AXI4_BURST_INCR;
+   assign m_axi_awlock = `AXI4_LOCK_NORMAL;
+   assign m_axi_awcache = `AXI4_CACHE_ALLOCATE | `AXI4_CACHE_OTHER_ALLOCATE | `AXI4_CACHE_MODIFIABLE | `AXI4_CACHE_BUFFERABLE;
+   assign m_axi_awprot = `AXI4_PROT_NON_SECURE;
+   assign m_axi_awqos = 4'h0;
+   assign m_axi_awregion = 4'h0;
+   assign m_axi_awuser = 1'b0;
+
+   
+   //
+   // AXI Write address state machine
+   //
+   always @(posedge aclk)
+     if (areset) begin
+	write_ctrl_ready <= 1'b0;
+	write_addr_state <= AW_IDLE;
+	m_axi_awaddr <= {AWIDTH{1'b0}};
+	m_axi_awlen[7:0] <= 8'h0;
+	m_axi_awvalid <= 1'b0;
+	m_axi_bready <= 1'b0;
+     end else
+       case (write_addr_state)
+	 //
+	 // AW_IDLE
+	 // We are ready to accept a new write transaction.
+	 //
+	 AW_IDLE: begin
+	    // Premptively accept new write transaction since we are idle.
+	    write_ctrl_ready <= 1'b1;
+	    // No need to be waiting for a response while idle.
+	    m_axi_bready <= 1'b0;
+	    // If we are offered a new transaction then.....
+	    if (write_ctrl_valid) begin
+	       // Drive all the relevent AXI4 write address channel signals next cycle.
+	       m_axi_awaddr <= write_addr;
+	       m_axi_awlen[7:0] <= {write_count};
+	       m_axi_awvalid <= 1'b1;
+	       // If the AXI4 write channel is pre-emptively accepting the transaction...
+	       if (m_axi_awready == 1'b1) begin
+		  // ...go straight to looking for a transaction response...
+		  `DEBUG $display("WRITE TRANSACTION: ADDR: %x  LEN: %x @ time %d",write_addr,write_count,$time);	 		  
+		  write_addr_state <= WAIT_BVALID;
+		  m_axi_bready <= 1'b1;
+	       end else begin
+                  // ...otherwise wait to get the transaction accepted.
+		  write_addr_state <= WAIT_AWREADY;
+	       end	       
+	    end
+	 end
+	 //
+	 // WAIT_AWREADY
+	 // Waiting for AXI4 slave to accept new write transaction.
+	 //
+	 WAIT_AWREADY: begin
+	    write_ctrl_ready <= 1'b0;
+	    // If the AXI4 write channel is accepting the transaction...
+	    if (m_axi_awready == 1'b1) begin
+	       // ...go to looking for a transaction response...
+	       write_addr_state <= WAIT_BVALID;
+	       m_axi_awvalid <= 1'b0;
+	       m_axi_bready <= 1'b1;
+	       `DEBUG $display("WRITE TRANSACTION: ADDR: %x  LEN: %x @ time %d",m_axi_awaddr,m_axi_awlen[7:0],$time);	       
+	    end else begin
+               // ...otherwise wait to get the trasaction accepted.
+	       write_addr_state <= WAIT_AWREADY;
+	    end
+	 end // case: WAIT_AWREADY
+	 //
+	 // WAIT_BVALID
+	 // Write transaction has been accepted, now waiting for a response to signal it's sucsesful.
+	 // Ignoring ID tag for the moment
+	 //
+	 WAIT_BVALID: begin
+	    write_ctrl_ready <= 1'b0;
+	    m_axi_awvalid <= 1'b0;
+	    // Wait for response channel to signal how write transaction went down....
+	    if (m_axi_bvalid == 1'b1) begin
+	       if ((m_axi_bresp == `AXI4_RESP_OKAY) ||  (m_axi_bresp == `AXI4_RESP_EXOKAY)) begin
+		  // ....it went well, we are ready to start something new.
+		  write_addr_state <= AW_IDLE;
+		  m_axi_bready <= 1'b0;
+		  write_ctrl_ready <= 1'b1; // Ready to run again as soon as we hit idle.
+	       end else if ((m_axi_bresp == `AXI4_RESP_SLVERR) || (m_axi_bresp == `AXI4_RESP_DECERR)) begin
+		  // ....things got ugly, retreat to an error stat and wait for intervention.
+		  write_addr_state <= AW_ERROR;
+		  m_axi_bready <= 1'b0;
+	       end	       
+	    end else begin
+	       write_addr_state <= WAIT_BVALID;
+	       m_axi_bready <= 1'b1;
+	    end
+	 end // case: WAIT_BVALID
+	 //
+	 // AW_ERROR
+	 // Something bad happened, going to need external intervention to restore a safe state.
+	 //
+	 AW_ERROR: begin
+	    write_ctrl_ready <= 1'b0;
+	    write_addr_state <= AW_ERROR;
+	    m_axi_awaddr <= {AWIDTH{1'b0}};
+	    m_axi_awlen[7:0] <= 8'h0;
+	    m_axi_awvalid <= 1'b0;
+	    m_axi_bready <= 1'b0;
+	 end
+       endcase // case(write_addr_state)
+
+   /////////////////////////////////////////////////////////////////////////////////
+   //
+   // AXI Write data channel
+   //
+   /////////////////////////////////////////////////////////////////////////////////
+   assign m_axi_wstrb = {DWIDTH/8{1'b1}};
+   assign m_axi_wuser = 1'b0;
+
+   //
+   // AXI Write data state machine
+   //
+   always @(posedge aclk)
+     if (areset) begin
+	write_data_state <= AW_IDLE;
+	write_data_count <= 1;
+	enable_data_write <= 1'b0;
+	m_axi_wlast <= 1'b0;
+	
+     end else
+       case (write_data_state)
+	 //
+	 // DW_IDLE
+	 // Sit in this state until presented with the control details of a new write transaction.
+	 //
+	 DW_IDLE: begin
+	    write_data_count <= 1;
+	    m_axi_wlast <= 1'b0;
+	    
+	    if (write_ctrl_valid && write_ctrl_ready) begin	       
+	       enable_data_write <= 1'b1;
+	       if (write_count[7:0] == 8'h0) begin
+		  // Single transfer transaction
+		  write_data_state <= DW_LAST;
+		  m_axi_wlast <= 1'b1;
+	       end else begin
+		  write_data_state <= DW_RUN;
+	       end
+	    end else begin
+	       write_data_state <= DW_IDLE;
+	    end
+	 end
+	 //
+	 // DW_RUN
+	 //
+	 DW_RUN : begin
+	    enable_data_write <= 1'b1;
+	    m_axi_wlast <= 1'b0;
+	    
+	    if (write_data_valid && m_axi_wready) begin
+	      // Single write transfer
+	       write_data_count <= write_data_count + 1;
+	    
+	       if (write_data_count == m_axi_awlen[7:0]) begin
+		  write_data_state <= DW_LAST;
+		  m_axi_wlast <= 1'b1;
+	       end else begin
+		  write_data_state <= DW_RUN;
+	       end
+	    end else begin
+	       write_data_state <= DW_RUN;
+	    end	    
+	 end
+	 //
+	 // DW_LAST
+	 //
+	 DW_LAST: begin
+	    if (write_data_valid && m_axi_wready) begin
+	       enable_data_write <= 1'b0;
+	       write_data_state <= DW_IDLE;
+	       m_axi_wlast <= 1'b0;
+	    end else begin
+	       enable_data_write <= 1'b1;
+	       write_data_state <= DW_LAST;
+	       m_axi_wlast <= 1'b1;
+	    end
+	 end // case: DW_LAST
+	 //
+	 default:
+	   write_data_state <= DW_IDLE;
+	 
+       endcase // case(write_data_state)
+   
+	       
+   assign m_axi_wdata = write_data;
+   assign m_axi_wvalid = enable_data_write && write_data_valid;
+   assign write_data_ready = enable_data_write && m_axi_wready;
+
+   /////////////////////////////////////////////////////////////////////////////////
+   //
+   // AXI Read address channel
+   //
+   /////////////////////////////////////////////////////////////////////////////////
+   assign m_axi_arid = 1'b0;
+   assign m_axi_arsize = $clog2(DWIDTH/8);
+   assign m_axi_arburst = `AXI4_BURST_INCR;
+   assign m_axi_arlock = `AXI4_LOCK_NORMAL;
+   assign m_axi_arcache = `AXI4_CACHE_ALLOCATE | `AXI4_CACHE_OTHER_ALLOCATE | `AXI4_CACHE_MODIFIABLE | `AXI4_CACHE_BUFFERABLE;
+   assign m_axi_arprot = `AXI4_PROT_NON_SECURE;
+   assign m_axi_arqos = 4'h0;
+   assign m_axi_arregion = 4'h0;
+   assign m_axi_aruser = 1'b0;
+
+
+   //
+   // AXI Read address state machine
+   //
+   always @(posedge aclk)
+     if (areset) begin
+	read_ctrl_ready <= 1'b0;
+	read_addr_state <= AR_IDLE;
+	m_axi_araddr <= {AWIDTH{1'b0}};
+	m_axi_arlen[7:0] <= 8'h0;
+	m_axi_arvalid <= 1'b0;
+     end else
+       case (read_addr_state)
+	 //
+	 // AR_IDLE
+	 // We are ready to accept a new read transaction.
+	 //
+	 AR_IDLE: begin
+	    // Premptively accept new read transaction since we are idle.
+	    read_ctrl_ready <= 1'b1;
+	    // If we are offered a new transaction then.....
+	    if (read_ctrl_valid) begin
+	       // Drive all the relevent AXI4 read address channel signals next cycle.
+	       m_axi_araddr <= read_addr;
+	       m_axi_arlen[7:0] <= {read_count};
+	       m_axi_arvalid <= 1'b1;
+	       // If the AXI4 read channel is pre-emptively accepting the transaction...
+	       if (m_axi_arready == 1'b1) begin
+		  // ...go straight to looking for the transaction to complete
+		   `DEBUG $display("READ TRANSACTION: ADDR: %x  LEN: %x @ time %d",read_addr,read_count,$time);
+		  read_addr_state <= WAIT_READ_DONE;
+	       end else begin
+                  // ...otherwise wait to get the transaction accepted.
+		  read_addr_state <= WAIT_ARREADY;
+	       end	       
+	    end
+	 end
+	 //
+	 // WAIT_ARREADY
+	 // Waiting for AXI4 slave to accept new read transaction.
+	 //
+	 WAIT_ARREADY: begin
+	    read_ctrl_ready <= 1'b0;
+	    // If the AXI4 read channel is accepting the transaction...
+	    if (m_axi_arready == 1'b1) begin
+	       // ...go to looking for the transaction to complete...
+	       read_addr_state <= WAIT_READ_DONE;
+	       m_axi_arvalid <= 1'b0;
+	        `DEBUG $display("READ TRANSACTION: ADDR: %x  LEN: %x @ time %d",m_axi_araddr,m_axi_arlen[7:0],$time);	       
+	    end else begin
+               // ...otherwise wait to get the trasaction accepted.
+	       read_addr_state <= WAIT_ARREADY;
+	    end
+	 end // case: WAIT_ARREADY
+	 //
+	 // WAIT_READ_DONE
+	 // Read transaction has been accepted, now waiting for the data transfer to complete
+	 // Ignoring ID tag for the moment
+	 //
+	 WAIT_READ_DONE: begin
+	    read_ctrl_ready <= 1'b0;
+	    m_axi_arvalid <= 1'b0;
+	    // Wait for read transaction to complete
+	    if (read_data_state == DR_IDLE) begin
+		 // ....it went well, we are ready to start something new.
+	       read_addr_state <= AR_IDLE;
+	       read_ctrl_ready <= 1'b1; // Ready to run again as soon as we hit idle.
+	    end else if (read_data_state == DR_ERROR) begin
+		 // ....things got ugly, retreat to an error stat and wait for intervention.
+	       read_addr_state <= AR_ERROR;
+	    end else begin
+	       read_addr_state <= WAIT_READ_DONE;
+	    end
+	 end // case: WAIT_BVALID
+	 //
+	 // AR_ERROR
+	 // Something bad happened, going to need external intervention to restore a safe state.
+	 //
+	 AR_ERROR: begin
+	    read_ctrl_ready <= 1'b0;
+	    read_addr_state <= AR_ERROR;
+	    m_axi_araddr <= {AWIDTH{1'b0}};
+	    m_axi_arlen[7:0] <= 8'h0;
+	    m_axi_arvalid <= 1'b0;
+	 end
+       endcase // case(read_addr_state)
+
+   /////////////////////////////////////////////////////////////////////////////////
+   //
+   // AXI Read data channel
+   //
+   /////////////////////////////////////////////////////////////////////////////////
+  
+
+   //
+   // AXI Read data state machine
+   //
+   always @(posedge aclk)
+     if (areset) begin
+	read_data_state <= AR_IDLE;
+	read_data_count <= 0;
+	enable_data_read <= 1'b0;
+	
+     end else
+       case (read_data_state)
+	 //
+	 // DR_IDLE
+	 // Sit in this state until presented with the control details of a new read transaction.
+	 //
+	 DR_IDLE: begin
+	    read_data_count <= 0;
+	    
+	    if (read_ctrl_valid && read_ctrl_ready) begin	       
+	       enable_data_read <= 1'b1;
+	       read_data_state <= DR_RUN;			   
+	    end else begin
+	       read_data_state <= DR_IDLE;
+	    end
+	 end
+	 //
+	 // DR_RUN
+	 // Sit here counting read transfers. If any have error's shift to error state.
+	 //
+	 DR_RUN : begin
+	    enable_data_read <= 1'b1;
+	     
+	    if (read_data_ready && m_axi_rvalid) begin
+	      // Single read transfer
+	       read_data_count <= read_data_count + 1;
+	       if ((m_axi_rresp == `AXI4_RESP_SLVERR) ||  (m_axi_rresp == `AXI4_RESP_DECERR)) begin
+		  if (m_axi_rlast) begin
+		     read_data_state <= DR_ERROR;
+		  end else begin
+		     read_data_state <= DR_WAIT_ERROR;
+		  end
+	       end else if (m_axi_rlast) begin // Implicitly good response signalled this transfer.
+		  if (read_data_count == m_axi_arlen[7:0]) begin
+		     read_data_state <= DR_IDLE;
+		  end else begin
+		     read_data_state <= DR_ERROR;
+		  end
+	       end else begin
+		  read_data_state <= DR_RUN;
+	       end
+	    end else begin
+	       read_data_state <= DR_RUN;
+	    end
+	 end
+	 //
+	 // DR_WAIT_ERROR
+	 // Something bad happened, wait for last signalled in this burst
+	 //
+	 DR_WAIT_ERROR: begin
+	    if (read_data_ready && m_axi_rvalid && m_axi_rlast) begin
+	       enable_data_read <= 1'b0;
+	       read_data_state <= DR_ERROR;
+	    end else begin
+	       enable_data_read <= 1'b1;
+	       read_data_state <= DR_WAIT_ERROR;
+	    end
+	 end // case: DR_WAIT_ERROR
+	 //
+	 // DR_ERROR
+	 // Something bad happened, going to need external intervention to restore a safe state.
+	 //
+	 DR_ERROR: begin
+	    enable_data_read <= 1'b0;
+	    read_data_state <= DR_ERROR;
+	 end // case: DR_ERROR
+	 
+
+       endcase // case(read_data_state)
+   
+	       
+   assign read_data = m_axi_rdata;
+   assign m_axi_rready = enable_data_read && read_data_ready;
+   assign read_data_valid = enable_data_read && m_axi_rvalid;
+			   
+endmodule // axi_dma_master
+
+	      
+	    
+	 
+   
+	      
\ No newline at end of file
diff --git a/fpga/usrp3/lib/axi/axi_dummy.v b/fpga/usrp3/lib/axi/axi_dummy.v
new file mode 100644
index 000000000..5ba430fc4
--- /dev/null
+++ b/fpga/usrp3/lib/axi/axi_dummy.v
@@ -0,0 +1,85 @@
+//
+// Copyright 2015 Ettus Research
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module axi_dummy
+(
+  // sys connect
+  input         s_axi_aclk,
+  input         s_axi_areset,
+
+  // axi4 lite slave port
+  input [31:0]  s_axi_awaddr,
+  input         s_axi_awvalid,
+  output        s_axi_awready,
+
+  input [31:0]  s_axi_wdata,
+  input [3:0]   s_axi_wstrb,
+  input         s_axi_wvalid,
+  output        s_axi_wready,
+
+  output [1:0]  s_axi_bresp,
+  output        s_axi_bvalid,
+  input         s_axi_bready,
+
+  input [31:0]  s_axi_araddr,
+  input         s_axi_arvalid,
+  output        s_axi_arready,
+
+  output [31:0] s_axi_rdata,
+  output [1:0]  s_axi_rresp,
+  output        s_axi_rvalid,
+  input         s_axi_rready
+);
+  parameter DEC_ERR = 1'b1;
+
+  localparam IDLE              = 3'b001;
+  localparam READ_IN_PROGRESS  = 3'b010;
+  localparam WRITE_IN_PROGRESS = 3'b100;
+
+  reg [2:0] state;
+
+  always @ (posedge s_axi_aclk) begin
+    if (s_axi_areset) begin
+      state <= IDLE;
+    end
+    else case (state)
+
+    IDLE: begin
+      if (s_axi_arvalid)
+        state <= READ_IN_PROGRESS;
+      else if (s_axi_awvalid)
+        state <= WRITE_IN_PROGRESS;
+    end
+
+    READ_IN_PROGRESS: begin
+      if (s_axi_rready)
+        state <= IDLE;
+    end
+
+    WRITE_IN_PROGRESS: begin
+      if (s_axi_bready)
+        state <= IDLE;
+    end
+
+    default: begin
+      state <= IDLE;
+    end
+
+    endcase
+  end
+
+  assign s_axi_awready = (state == IDLE);
+  assign s_axi_wready  = (state == WRITE_IN_PROGRESS);
+  assign s_axi_bvalid  = (state == WRITE_IN_PROGRESS);
+
+  assign s_axi_arready = (state == IDLE);
+  assign s_axi_rdata = 32'hdead_ba5e;
+  assign s_axi_rvalid  = (state == READ_IN_PROGRESS);
+  assign s_axi_rresp = DEC_ERR ? 2'b11 : 2'b00;
+  assign s_axi_bresp = DEC_ERR ? 2'b11 : 2'b00;
+
+endmodule
diff --git a/fpga/usrp3/lib/axi/axi_embed_tlast.v b/fpga/usrp3/lib/axi/axi_embed_tlast.v
new file mode 100644
index 000000000..bc14043e9
--- /dev/null
+++ b/fpga/usrp3/lib/axi/axi_embed_tlast.v
@@ -0,0 +1,132 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+//
+// AXI stream neds N+1 bits to transmit packets of N bits so that the LAST bit can be represented.
+// LAST occurs relatively infrequently and can be synthesized by using an in-band ESC code to generate
+// a multi-word sequence to encode it (and the escape character when it appears as data input).
+//
+// 0x1234567887654321 with last becomes
+// 0xDEADBEEFFEEDCAFE 0x0000000000000001 0x1234567887654321
+//
+// 0xDEADBEEFFEEDCAFE with last becomes
+// 0xDEADBEEFFEEDCAFE 0x0000000000000001 0xDEADBEEFFEEDCAFE
+//
+// 0xDEADBEEFFEEDCAFE without last becomes
+// 0xDEADBEEFFEEDCAFE 0x0000000000000000 0xDEADBEEFFEEDCAFE
+//
+
+module axi_embed_tlast #(
+  parameter WIDTH=64,
+  parameter ADD_CHECKSUM=0
+) (
+   input clk,
+   input reset,
+   input clear,
+   //
+   input [WIDTH-1:0] i_tdata,
+   input i_tlast,
+   input i_tvalid,
+   output i_tready,
+   //
+   output reg [WIDTH-1:0] o_tdata,
+   output o_tvalid,
+   input o_tready
+);
+
+   localparam PASS = 0;
+   localparam ZERO = 1;
+   localparam ONE = 2;
+   localparam ESCAPE = 3;
+
+   localparam IDLE = 0;
+   localparam LAST = 1;
+   localparam ESC = 2;
+   localparam FINISH = 3;
+   
+   reg [1:0]  state, next_state;
+
+   reg [1:0]  select;
+
+   wire [31:0] checksum;
+   generate if (ADD_CHECKSUM == 1) begin
+      reg [31:0] checksum_reg;
+      always @(posedge clk) begin
+         if (reset | clear) begin
+            checksum_reg <= 0;
+         end else if (i_tready && i_tvalid && i_tlast) begin
+            checksum_reg <= 0;
+         end else if (i_tready && i_tvalid) begin
+            checksum_reg <= checksum_reg ^ i_tdata[31:0] ^ i_tdata[63:32];
+         end
+      end
+      assign checksum = checksum_reg;
+   end else begin
+      assign checksum = 32'h0;
+   end endgenerate
+
+   always @(posedge clk) 
+      if (reset | clear) begin
+         state <= IDLE;
+      end else begin if (o_tready)
+         state <= next_state;
+      end 
+
+   always @(*) begin
+      case(state)
+         IDLE: begin
+            if (i_tlast && i_tvalid) begin
+               next_state = LAST;
+               select = ESCAPE;
+            end else if ((i_tdata == 64'hDEADBEEFFEEDCAFE) && i_tvalid) begin
+               next_state = ESC;
+               select = ESCAPE;
+            end else begin
+               next_state = IDLE;
+               select = PASS;
+            end
+         end // case: IDLE
+
+         LAST: begin
+            select = ONE;
+            next_state = FINISH;
+         end
+
+         ESC: begin
+            select = ZERO;
+            next_state = FINISH;
+         end
+
+         FINISH: begin
+            select = PASS;
+            if (i_tvalid)
+               next_state = IDLE;
+            else
+               next_state = FINISH;
+         end
+      endcase // case(state)
+   end // always @ (*)
+
+   //
+   // Muxes
+   //
+   always @*
+      begin
+         case(select)
+            PASS:   o_tdata = i_tdata;
+            ZERO:   o_tdata = 0;
+            ONE:    o_tdata = {checksum[31:0],32'h1};
+            ESCAPE: o_tdata = 64'hDEADBEEFFEEDCAFE;
+         endcase // case(select)
+      end
+
+   assign o_tvalid = (select == PASS) ? i_tvalid : 1'b1;
+   assign i_tready = (select == PASS) ? o_tready : 1'b0;
+
+endmodule // axi_embed_tlast
+
+
+
diff --git a/fpga/usrp3/lib/axi/axi_embed_tlast_tkeep.v b/fpga/usrp3/lib/axi/axi_embed_tlast_tkeep.v
new file mode 100644
index 000000000..4adb91fa6
--- /dev/null
+++ b/fpga/usrp3/lib/axi/axi_embed_tlast_tkeep.v
@@ -0,0 +1,152 @@
+//
+// Copyright 2019 Ettus Research, a National Instruments Brand
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: axi_embed_tlast_tkeep
+//
+// Description:
+//
+//   This module takes the TLAST and TKEEP values of an AXI-Stream interface
+//   and embeds them into the data stream. This allows a data pipe to be used
+//   that isn't wide enough for the TDATA, TLAST,and TKEEP to be passed through
+//   in parallel. Since TLAST and TKEEP are only usually needed for one word
+//   per packet, this also reduces the amount of memory required to store a
+//   packet. Note that this module only supports TKEEP at the end of a packet
+//   when TLAST is asserted. See also axi_extract_tlast_tkeep.
+//
+//   This embedding is accomplished by using an escape sequence using the word
+//   0xDEADBEEF as the escape code. If TLAST and TKEEP are both 0 (the usual
+//   case) then no escape sequence is used. Any word that has "DEADBEEF" in the
+//   most significant position is considered an escape word. The least
+//   significant bits of the escape word contain the TKEEP and TLAST bits. The
+//   word following the escape word is the normal data word associated with
+//   those TLAST and TKEEP values.
+//
+//   Here are some examples for the case where DATA_W = 64
+//
+//     0x1234567887654321 with TLAST=0 and TKEEP=0 becomes
+//     0x1234567887654321
+//
+//     0x1234567887654321 with TLAST=1 and TKEEP=0 becomes
+//     0xDEADBEEF00000001 0x1234567887654321
+//
+//     0x1234567887654321 with TLAST=1 and TKEEP=2 becomes
+//     0xDEADBEEF00000005 0x1234567887654321
+//
+//     0x1234567887654321 with TLAST=0 and TKEEP=1 becomes
+//     0x1234567887654321 (because TKEEP is ignored when TLAST=0)
+//
+//     0xDEADBEEFFEEDCAFE without TLAST=0 and TKEEP=0 becomes
+//     0xDEADBEEF00000000 0xDEADBEEFFEEDCAFE
+//
+//     0xDEADBEEFFEEDCAFE with TLAST=0 and TKEEP=1 becomes
+//     0xDEADBEEF00000002 0xDEADBEEFFEEDCAFE
+//
+
+module axi_embed_tlast_tkeep #(
+  parameter DATA_W = 64,
+  parameter KEEP_W = DATA_W/8
+) (
+  input clk,
+  input rst,
+
+  // Input AXI-Stream
+  input  [DATA_W-1:0] i_tdata,
+  input  [KEEP_W-1:0] i_tkeep,
+  input               i_tlast,
+  input               i_tvalid,
+  output              i_tready,
+
+  // Output AXI-Stream
+  output reg [DATA_W-1:0] o_tdata,
+  output                  o_tvalid,
+  input                   o_tready
+);
+
+  localparam                  ESC_WORD_W = 32;
+  localparam [ESC_WORD_W-1:0] ESC_WORD   = 'hDEADBEEF;
+
+
+  //---------------------------------------------------------------------------
+  // Parameter Checking
+  //---------------------------------------------------------------------------
+
+  if (DATA_W < ESC_WORD_W+KEEP_W+1) begin : gen_assertion
+    // Cause an error if DATA_W is not large enough.
+    DATA_W_is_not_large_enough_to_store_escape_code_TKEEP_and_TLAST();
+  end
+
+
+  //---------------------------------------------------------------------------
+  // State Machine
+  //---------------------------------------------------------------------------
+
+  localparam PASS   = 0;
+  localparam ESCAPE = 1;
+
+  localparam ST_IDLE = 0;
+  localparam ST_DATA = 1;
+
+  reg [0:0] state = ST_IDLE;
+  reg [0:0] next_state;
+
+  reg [0:0] select;
+
+  always @(posedge clk) begin
+    if (rst) begin
+      state <= ST_IDLE;
+    end else begin if (o_tready)
+      state <= next_state;
+    end
+  end
+
+  always @(*) begin
+    case(state)
+      ST_IDLE: begin
+        if (i_tlast && i_tvalid) begin
+          next_state = ST_DATA;
+          select     = ESCAPE;
+        end else if ((i_tdata[DATA_W-1 -: ESC_WORD_W] == ESC_WORD) && i_tvalid) begin
+          next_state = ST_DATA;
+          select     = ESCAPE;
+        end else begin
+          next_state = ST_IDLE;
+          select     = PASS;
+        end
+      end
+
+      ST_DATA: begin
+        select = PASS;
+        if (i_tvalid) begin
+          next_state = ST_IDLE;
+        end else begin
+          next_state = ST_DATA;
+        end
+      end
+    endcase
+  end
+
+
+  //---------------------------------------------------------------------------
+  // Output Multiplexers
+  //---------------------------------------------------------------------------
+
+  always @(*) begin
+    case(select)
+      PASS   : begin
+        o_tdata = i_tdata;
+      end
+      ESCAPE : begin
+        o_tdata                         = {DATA_W{1'b0}};
+        o_tdata[DATA_W-1 -: ESC_WORD_W] = ESC_WORD;
+        o_tdata[       1 +:     KEEP_W] = i_tkeep;
+        o_tdata[       0 +:          1] = i_tlast;
+      end
+    endcase
+  end
+
+  assign o_tvalid = (select == PASS) ? i_tvalid : 1'b1;
+  assign i_tready = (select == PASS) ? o_tready : 1'b0;
+
+endmodule
diff --git a/fpga/usrp3/lib/axi/axi_extract_tlast.v b/fpga/usrp3/lib/axi/axi_extract_tlast.v
new file mode 100644
index 000000000..9afef3c35
--- /dev/null
+++ b/fpga/usrp3/lib/axi/axi_extract_tlast.v
@@ -0,0 +1,147 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+//
+// AXI stream neds N+1 bits to transmit packets of N bits so that the LAST bit can be represented.
+// LAST occurs relatively infrequently and can be synthesized by using an in-band ESC code to generate
+// a multi-word sequence to encode it (and the escape character when it appears as data input).
+//
+// 0x1234567887654321 with last becomes
+// 0xDEADBEEFFEEDCAFE 0x0000000000000001 0x1234567887654321
+//
+// 0xDEADBEEFFEEDCAFE with last becomes
+// 0xDEADBEEFFEEDCAFE 0x0000000000000001 0xDEADBEEFFEEDCAFE
+//
+// 0xDEADBEEFFEEDCAFE without last becomes
+// 0xDEADBEEFFEEDCAFE 0x0000000000000000 0xDEADBEEFFEEDCAFE
+//
+
+module axi_extract_tlast #(
+  parameter WIDTH=64,
+  parameter VALIDATE_CHECKSUM=0
+) (
+   input clk,
+   input reset,
+   input clear,
+   //
+   input [WIDTH-1:0] i_tdata,
+   input i_tvalid,
+   output reg i_tready,
+   //
+   output [WIDTH-1:0] o_tdata,
+   output reg o_tlast,
+   output reg o_tvalid,
+   input  o_tready,
+   //
+   output reg checksum_error
+);
+
+   reg [1:0] state, next_state;
+   
+   localparam IDLE = 0;
+   localparam EXTRACT1 = 1;
+   localparam EXTRACT2 = 2;
+   localparam EXTRACT3 = 3;
+   
+   assign     o_tdata = i_tdata;
+
+   reg        checksum_error_pre;
+   reg [31:0] checksum, old_checksum;
+
+   always @(posedge clk) 
+      if (reset | clear) begin
+         checksum <= 0;
+         old_checksum <= 0;
+      end else if (VALIDATE_CHECKSUM && o_tready && i_tvalid && o_tlast) begin
+         checksum <= 0;
+         old_checksum <= 0;
+      end else if (VALIDATE_CHECKSUM && i_tready && i_tvalid && (state == IDLE)) begin
+         checksum <= checksum ^ i_tdata[31:0] ^ i_tdata[63:32];
+         old_checksum <= checksum;
+      end
+
+   always @(posedge clk)
+      checksum_error <= checksum_error_pre;
+
+   always @(posedge clk) 
+      if (reset | clear) begin
+         state <= IDLE;
+      end else begin
+         state <= next_state;
+      end 
+
+   always @(*) begin
+      checksum_error_pre = 0;
+      case(state)
+         //
+         // Search for Escape sequence "0xDEADBEEFFEEDCAFE"
+         // If ESC found don't pass data downstream but transition to next state.
+         // else pass data downstream.
+         //
+         IDLE: begin
+            o_tlast = 1'b0;
+            if ((i_tdata == 64'hDEADBEEFFEEDCAFE) && i_tvalid) begin
+               next_state = EXTRACT1;
+               o_tvalid = 1'b0;
+               i_tready = 1'b1;
+            end else begin
+               next_state = IDLE;
+               o_tvalid = i_tvalid;
+               i_tready = o_tready;
+            end // else: !if((i_tdata == 'hDEADBEEFFEEDCAFE) && i_tvalid)
+         end // case: IDLE
+         //
+         // Look at next data. If it's a 0x1 then o_tlast should be asserted with next data word.
+         // if it's 0x0 then it signals emulation of the Escape code in the original data stream
+         // and we should just pass the next data word through unchanged with no o_tlast indication.
+         //
+         EXTRACT1: begin
+            o_tvalid = 1'b0;
+            i_tready = 1'b1;
+            o_tlast = 1'b0;
+            if (i_tvalid) begin
+               if (i_tdata[31:0] == 'h1) begin
+                  if (VALIDATE_CHECKSUM && (old_checksum != i_tdata[63:32])) 
+                     checksum_error_pre = 1'b1;
+                  next_state = EXTRACT2;
+               end else  begin
+                  // We assume emulation and don't look for illegal codes.
+                  next_state = EXTRACT3;
+               end // else: !if(i_tdata == 'h1)
+            end else begin // if (i_tvalid)
+               next_state = EXTRACT1;
+            end // else: !if(i_tvalid)
+         end // case: EXTRACT1
+         //
+         // Assert o_tlast with data word.
+         //
+         EXTRACT2: begin
+            o_tvalid = i_tvalid;
+            i_tready = o_tready;
+            o_tlast = 1'b1;
+            if (i_tvalid & o_tready)
+               next_state = IDLE;
+            else
+               next_state = EXTRACT2;
+         end
+         //
+         // Emulation, don't assert o_tlast with dataword.
+         //
+         EXTRACT3: begin
+            o_tvalid = i_tvalid;
+            i_tready = o_tready;
+            o_tlast = 1'b0;
+            if (i_tvalid & o_tready)
+               next_state = IDLE;
+            else
+               next_state = EXTRACT2;
+         end
+      endcase // case(state)
+   end
+
+endmodule // axi_extract_tlast
+
+  
\ No newline at end of file
diff --git a/fpga/usrp3/lib/axi/axi_extract_tlast_tkeep.v b/fpga/usrp3/lib/axi/axi_extract_tlast_tkeep.v
new file mode 100644
index 000000000..4d9178052
--- /dev/null
+++ b/fpga/usrp3/lib/axi/axi_extract_tlast_tkeep.v
@@ -0,0 +1,128 @@
+//
+// Copyright 2019 Ettus Research, a National Instruments Brand
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: axi_extract_tlast_tkeep
+//
+// Description:
+//
+//   This module extracts the TLAST and TKEEP values that were embedded by the
+//   axi_embed_tlast_tkeep module. See axi_embed_tlast_tkeep for a description
+//   of how the data is encoded.
+//
+//   Here are some extraction examples for DATA_W = 64.
+//
+//     0x1234567887654321 becomes
+//     0x1234567887654321 (no changes)
+//
+//     0xDEADBEEF00000001 0x1234567887654321 becomes
+//     0x1234567887654321 with TLAST=1 and TKEEP=0
+//
+//     0xDEADBEEF00000005 0x1234567887654321 becomes
+//     0x1234567887654321 with TLAST=1 and TKEEP=2
+//
+//     0xDEADBEEF00000000 0xDEADBEEFFEEDCAFE
+//     0xDEADBEEFFEEDCAFE without TLAST=0 and TKEEP=0 becomes
+//
+//     0xDEADBEEF00000002 0xDEADBEEFFEEDCAFE
+//     0xDEADBEEFFEEDCAFE with TLAST=0 and TKEEP=1 becomes
+//
+
+module axi_extract_tlast_tkeep #(
+   parameter DATA_W = 64,
+   parameter KEEP_W = DATA_W  /8
+) (
+   input clk,
+   input rst,
+
+   // Input AXI-Stream
+   input      [DATA_W-1:0] i_tdata,
+   input                   i_tvalid,
+   output reg              i_tready,
+
+   // Output AXI-Stream
+   output reg [DATA_W-1:0] o_tdata,
+   output reg [KEEP_W-1:0] o_tkeep,
+   output reg              o_tlast,
+   output reg              o_tvalid,
+   input                   o_tready
+);
+
+  localparam                  ESC_WORD_W = 32;
+  localparam [ESC_WORD_W-1:0] ESC_WORD   = 'hDEADBEEF;
+
+
+  //---------------------------------------------------------------------------
+  // TKEEP and TLAST Holding Register
+  //---------------------------------------------------------------------------
+
+  reg              save_flags;
+  reg              tlast_saved;
+  reg [KEEP_W-1:0] tkeep_saved;
+
+  always @(posedge clk) begin
+    if (save_flags) begin
+      // Save the TLAST and TKEEP values embedded in the escape word
+      tlast_saved <= i_tdata[0];
+      tkeep_saved <= i_tdata[1 +: KEEP_W];
+    end
+  end
+
+
+  //--------------------------------------------------------------------------
+  // State Machine
+  //--------------------------------------------------------------------------
+
+  localparam ST_IDLE = 0;
+  localparam ST_DATA = 1;
+
+  reg [0:0] state = ST_IDLE;
+  reg [0:0] next_state;
+
+  always @(posedge clk) begin
+    if (rst) begin
+      state <= ST_IDLE;
+    end else begin
+      state <= next_state;
+    end
+  end
+
+  always @(*) begin
+    // Default assignments (pass through)
+    o_tdata    = i_tdata;
+    o_tlast    = 1'b0;
+    o_tkeep    = {KEEP_W{1'b1}};
+    save_flags = 1'b0;
+    next_state = state;
+    o_tvalid   = i_tvalid;
+    i_tready   = o_tready;
+
+    case(state)
+      //
+      // Search for escape code. If found don't pass data downstream but
+      // transition to next state. Otherwise, pass data downstream.
+      //
+      ST_IDLE: begin
+        if ((i_tdata[DATA_W-1 -: ESC_WORD_W] == ESC_WORD) && i_tvalid) begin
+          save_flags = 1'b1;
+          next_state = ST_DATA;
+          o_tvalid   = 1'b0;
+          i_tready   = 1'b1;
+        end
+      end
+
+      //
+      // Output data word with the saved TLAST and TKEEP values
+      //
+      ST_DATA: begin
+        o_tlast = tlast_saved;
+        o_tkeep = tkeep_saved;
+        if (i_tvalid & o_tready) begin
+          next_state = ST_IDLE;
+        end
+      end
+    endcase
+  end
+
+endmodule
diff --git a/fpga/usrp3/lib/axi/axi_fast_extract_tlast.v b/fpga/usrp3/lib/axi/axi_fast_extract_tlast.v
new file mode 100644
index 000000000..59e925caf
--- /dev/null
+++ b/fpga/usrp3/lib/axi/axi_fast_extract_tlast.v
@@ -0,0 +1,193 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+//
+// Ultra fast critical path FIFO.
+// Only 2 entrys but no combinatorial feed through paths
+//
+
+
+module axi_fast_extract_tlast
+  #(parameter WIDTH=64)
+  (
+   input clk,
+   input reset,
+   input clear,
+   //
+   input [WIDTH-1:0] i_tdata,
+   input i_tvalid,
+   output reg i_tready,
+   //
+   output [WIDTH-1:0] o_tdata,
+   output o_tlast,
+   output reg o_tvalid,
+   input  o_tready
+   );
+
+   reg [WIDTH:0] data_reg1, data_reg2;
+
+   reg [1:0] 	   fifo_state;
+   
+   localparam EMPTY = 0;
+   localparam HALF = 1;
+   localparam FULL = 2;
+
+   reg [1:0]  extract_state;
+   
+   localparam IDLE = 0;
+   localparam EXTRACT1 = 1;
+   localparam EXTRACT2 = 2;
+   localparam EXTRACT3 = 3;
+
+   
+   always @(posedge clk) 
+     if (reset | clear) begin
+	fifo_state <= EMPTY;
+     end else begin
+	case (fifo_state)
+	  // Nothing in either register.
+	  // Upstream can always push data to us.
+	  // Downstream has nothing to take from us.
+	  EMPTY: begin
+	     if ((extract_state == IDLE) && (i_tdata == 64'hDEADBEEFFEEDCAFE) && i_tvalid) begin
+		// Embeded escpae code received.
+		extract_state <= EXTRACT1;
+		i_tready <= 1'b1;
+		o_tvalid <= 1'b0;
+		fifo_state <= EMPTY;
+	     end else if ((extract_state == EXTRACT1) && i_tvalid) begin
+		// Now work out if its a genuine embeded tlast or emulation.
+		i_tready <= 1'b1;
+		o_tvalid <= 1'b0;
+		fifo_state <= EMPTY;
+		if (i_tdata[31:0] == 'h1) begin
+		   extract_state <= EXTRACT2;
+		end else begin
+		   extract_state <= EXTRACT3;
+		end
+	     end else if ((extract_state == EXTRACT2) && i_tvalid) begin
+		// Extract tlast.
+		data_reg1 <= {1'b1,i_tdata};
+		i_tready <= 1'b1;
+		o_tvalid <= 1'b1;
+		fifo_state <= HALF;
+		extract_state <= IDLE;
+	     end else if (i_tvalid) begin
+		// Get here both for normal data and for EXTRACT3 emulation data.
+		data_reg1 <= {1'b0,i_tdata};
+		fifo_state <= HALF;
+		extract_state <= IDLE;
+		i_tready <= 1'b1;
+		o_tvalid <= 1'b1;
+	     end else begin
+		// Nothing to do.
+		fifo_state <= EMPTY;
+		i_tready <= 1'b1;
+		o_tvalid <= 1'b0;
+	     end
+	  end
+	  // First Register Full.
+	  // Upstream can always push data to us.
+	  // Downstream can always read from us.
+	  HALF: begin
+	     if ((extract_state == IDLE) && (i_tdata == 64'hDEADBEEFFEEDCAFE) && i_tvalid) begin
+		// Embeded escpae code received.
+		extract_state <= EXTRACT1;
+		if (o_tready) begin
+		   // If meanwhile we get read then go empty...
+		   i_tready <= 1'b1;
+		   o_tvalid <= 1'b0;
+		   fifo_state <= EMPTY;
+		end else begin
+		   // ...else stay half full.
+		   fifo_state <= HALF;
+		   i_tready <= 1'b1;
+		   o_tvalid <= 1'b1;
+		end
+	     end else if ((extract_state == EXTRACT1) && i_tvalid) begin
+		// Now work out if its a genuine embeded tlast or emulation.
+		if (i_tdata[31:0] == 'h1) begin
+		   extract_state <= EXTRACT2;
+		end else begin
+		   extract_state <= EXTRACT3;
+		end
+		if (o_tready) begin
+		   // If meanwhile we get read then go empty...
+		   i_tready <= 1'b1;
+		   o_tvalid <= 1'b0;
+		   fifo_state <= EMPTY;
+		end else begin
+		   // ...else stay half full.
+		   fifo_state <= HALF;
+		   i_tready <= 1'b1;
+		   o_tvalid <= 1'b1;
+		end		
+	     end else if ((extract_state == EXTRACT2) && i_tvalid) begin
+		// Extract tlast.
+		data_reg1 <= {1'b1,i_tdata};
+		extract_state <= IDLE;
+		if (o_tready) begin
+		   // We get read and writen same cycle...
+		   i_tready <= 1'b1;
+		   o_tvalid <= 1'b1;
+		   fifo_state <= HALF;
+		end else begin
+		   // ...or we get written and go full.
+		   data_reg2 <= data_reg1;
+		   i_tready <= 1'b0;
+		   o_tvalid <= 1'b1;
+		   fifo_state <= FULL;
+		end	
+	     end else if (i_tvalid) begin
+		// Get here both for normal data and for EXTRACT3 emulation data.
+		data_reg1 <= {1'b0,i_tdata};
+		extract_state <= IDLE;
+		if (o_tready) begin
+		   // We get read and writen same cycle...
+		   fifo_state <= HALF;
+		   i_tready <= 1'b1;
+		   o_tvalid <= 1'b1;
+		end else begin
+		   // ...or we get written and go full.
+		   data_reg2 <= data_reg1;
+		   i_tready <= 1'b0;
+		   o_tvalid <= 1'b1;
+		   fifo_state <= FULL;
+		end	
+	     end else if (o_tready) begin // if (i_tvalid)
+		// Only getting read this cycle so go empty
+		fifo_state <= EMPTY;
+		i_tready <= 1'b1;
+		o_tvalid <= 1'b0;
+	     end else begin
+		// Absolutley nothing happens, everything stays the same.
+		fifo_state <= HALF;
+		i_tready <= 1'b1;
+		o_tvalid <= 1'b1;
+	     end
+	  end // case: HALF
+	  // Both Registers Full.
+	  // Upstream can not push to us in this fifo_state.
+	  // Downstream can always read from us.
+	  FULL: begin
+	     if (o_tready) begin
+		fifo_state <= HALF;
+		i_tready <= 1'b1;
+		o_tvalid <= 1'b1;
+	     end
+	     else begin
+		fifo_state <= FULL;
+		i_tready <= 1'b0;
+		o_tvalid <= 1'b1;
+	     end
+	  end
+	endcase // case(fifo_state)
+     end // else: !if(reset | clear)
+   
+   assign {o_tlast,o_tdata} = (fifo_state == FULL) ? data_reg2 : data_reg1;
+   
+
+endmodule // axi_fast_extract_tlast
diff --git a/fpga/usrp3/lib/axi/axi_fast_fifo.v b/fpga/usrp3/lib/axi/axi_fast_fifo.v
new file mode 100644
index 000000000..5ff303b11
--- /dev/null
+++ b/fpga/usrp3/lib/axi/axi_fast_fifo.v
@@ -0,0 +1,108 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+//
+// Ultra fast critical path FIFO.
+// Only 2 entrys but no combinatorial feed through paths
+//
+
+
+module axi_fast_fifo
+  #(parameter WIDTH=64)
+  (
+   input clk,
+   input reset,
+   input clear,
+   //
+   input [WIDTH-1:0] i_tdata,
+   input i_tvalid,
+   output reg i_tready,
+   //
+   output [WIDTH-1:0] o_tdata,
+   output reg o_tvalid,
+   input  o_tready
+   );
+
+   reg [WIDTH-1:0] data_reg1, data_reg2;
+
+   reg [1:0] 	   state;
+   
+   localparam EMPTY = 0;
+   localparam HALF = 1;
+   localparam FULL = 2;
+   
+   always @(posedge clk) 
+     if (reset | clear) begin
+	state <= EMPTY;
+	data_reg1 <= 0;
+	data_reg2 <= 0;
+	o_tvalid <= 1'b0;
+	i_tready <= 1'b0;
+	
+     end else begin
+	case (state)
+	  // Nothing in either register.
+	  // Upstream can always push data to us.
+	  // Downstream has nothing to take from us.
+	  EMPTY: begin
+	     if (i_tvalid) begin
+		data_reg1 <= i_tdata;
+		state <= HALF;
+		i_tready <= 1'b1;
+		o_tvalid <= 1'b1;
+	     end else begin
+		state <= EMPTY;
+		i_tready <= 1'b1;
+		o_tvalid <= 1'b0;
+	     end
+	  end
+	  // First Register Full.
+	  // Upstream can always push data to us.
+	  // Downstream can always read from us.
+	  HALF: begin
+	     if (i_tvalid && o_tready) begin
+		data_reg1 <= i_tdata;
+		state <= HALF;
+		i_tready <= 1'b1;
+		o_tvalid <= 1'b1;
+	     end else if (i_tvalid) begin
+		data_reg1 <= i_tdata;
+		data_reg2 <= data_reg1;
+		state <= FULL;
+		i_tready <= 1'b0;
+		o_tvalid <= 1'b1;
+	     end else if (o_tready) begin
+		state <= EMPTY;
+		i_tready <= 1'b1;
+		o_tvalid <= 1'b0;
+	     end else begin
+		state <= HALF;
+		i_tready <= 1'b1;
+		o_tvalid <= 1'b1;
+	     end
+	  end // case: HALF
+	  // Both Registers Full.
+	  // Upstream can not push to us in this state.
+	  // Downstream can always read from us.
+	  FULL: begin
+	     if (o_tready) begin
+		state <= HALF;
+		i_tready <= 1'b1;
+		o_tvalid <= 1'b1;
+	     end
+	     else begin
+		state <= FULL;
+		i_tready <= 1'b0;
+		o_tvalid <= 1'b1;
+	     end
+	  end
+	endcase // case(state)
+     end // else: !if(reset | clear)
+
+   assign o_tdata = (state == FULL) ? data_reg2 : data_reg1;
+   
+
+endmodule // axi_fast_fifo
diff --git a/fpga/usrp3/lib/axi/axi_replay.v b/fpga/usrp3/lib/axi/axi_replay.v
new file mode 100644
index 000000000..49e4318c5
--- /dev/null
+++ b/fpga/usrp3/lib/axi/axi_replay.v
@@ -0,0 +1,867 @@
+//
+// Copyright 2017 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0
+//
+// Module: axi_replay.v
+// Description:
+//
+// This block implements the state machine and control logic for recording and 
+// playback of AXI-Stream data, using a DMA-accessible memory as a buffer.
+
+
+module axi_replay #(
+  parameter DATA_WIDTH  = 64,
+  parameter ADDR_WIDTH  = 32, // Byte address width used by DMA master
+  parameter COUNT_WIDTH = 8   // Length of counters used to connect to the DMA 
+                              // master's read and write interfaces.
+) (
+  input wire clk,
+  input wire rst,  // Synchronous to clk
+
+  //---------------------------------------------------------------------------
+  // Settings Bus
+  //---------------------------------------------------------------------------
+
+  input  wire        set_stb,
+  input  wire [ 7:0] set_addr,
+  input  wire [31:0] set_data,
+  output reg  [31:0] rb_data,
+  input  wire [ 7:0] rb_addr,
+
+  //---------------------------------------------------------------------------
+  // AXI Stream Interface
+  //---------------------------------------------------------------------------
+
+  // Input
+  input  wire [DATA_WIDTH-1:0] i_tdata,
+  input  wire                  i_tvalid,
+  input  wire                  i_tlast,
+  output wire                  i_tready,
+
+  // Output
+  output wire [DATA_WIDTH-1:0] o_tdata,
+  output wire                  o_tvalid,
+  output wire                  o_tlast,
+  input  wire                  o_tready,
+
+  //---------------------------------------------------------------------------
+  // DMA Interface
+  //---------------------------------------------------------------------------
+
+  // Write interface
+  output reg  [ ADDR_WIDTH-1:0] write_addr,       // Byte address for start of write
+                                                  // transaction (64-bit aligned).
+  output reg  [COUNT_WIDTH-1:0] write_count,      // Count of 64-bit words to write, minus 1.
+  output reg                    write_ctrl_valid,
+  input  wire                   write_ctrl_ready,
+  output wire [ DATA_WIDTH-1:0] write_data,
+  output wire                   write_data_valid,
+  input  wire                   write_data_ready,
+
+  // Read interface
+  output reg  [ ADDR_WIDTH-1:0] read_addr,       // Byte address for start of read
+                                                 // transaction (64-bit aligned).
+  output reg  [COUNT_WIDTH-1:0] read_count,      // Count of 64-bit words to read, minus 1.
+  output reg                    read_ctrl_valid,
+  input  wire                   read_ctrl_ready,
+  input  wire [ DATA_WIDTH-1:0] read_data,
+  input  wire                   read_data_valid,
+  output wire                   read_data_ready
+);
+
+  //---------------------------------------------------------------------------
+  // Constants
+  //---------------------------------------------------------------------------
+
+  // Size constants
+  localparam CMD_WIDTH   = 32;           // Command width
+  localparam LINES_WIDTH = 28;           // Width of cmd_num_lines
+  localparam WORD_SIZE   = DATA_WIDTH/8; // Size of DATA_WIDTH in bytes
+
+  // Register offsets
+  localparam [7:0] SR_REC_BASE_ADDR    = 128;
+  localparam [7:0] SR_REC_BUFFER_SIZE  = 129;
+  localparam [7:0] SR_REC_RESTART      = 130;
+  localparam [7:0] SR_REC_FULLNESS     = 131;
+  localparam [7:0] SR_PLAY_BASE_ADDR   = 132;
+  localparam [7:0] SR_PLAY_BUFFER_SIZE = 133;
+  localparam [7:0] SR_RX_CTRL_COMMAND  = 152; // Same offset as radio
+  localparam [7:0] SR_RX_CTRL_HALT     = 155; // Same offset as radio
+  localparam [7:0] SR_RX_CTRL_MAXLEN   = 156; // Same offset as radio
+
+
+  // Memory buffering parameters:
+  //
+  // Log base 2 of the depth of the input and output FIFOs to use. The FIFOs 
+  // should be large enough to store more than a complete burst 
+  // (MEM_BURST_SIZE). A size of 9 (512 64-bit words) is one 36-kbit BRAM.
+  localparam REC_FIFO_ADDR_WIDTH  = 9;  // Log2 of input/record FIFO size
+  localparam PLAY_FIFO_ADDR_WIDTH = 9;  // Log2 of output/playback FIFO size
+  //
+  // Amount of data to buffer before writing to RAM. This should be a power of 
+  // two so that it evenly divides the AXI_ALIGNMENT requirement. It also must 
+  // not exceed 2**COUNT_WIDTH (the maximum count allowed by DMA master).
+  localparam MEM_BURST_SIZE = 2**COUNT_WIDTH;  // Size in DATA_WIDTH-sized words
+  //
+  // AXI alignment requirement (4096 bytes) in DATA_WIDTH-bit words
+  localparam AXI_ALIGNMENT = 4096 / WORD_SIZE;
+  //
+  // Clock cycles to wait before writing something less than MEM_BURST_SIZE 
+  // to memory.
+  localparam DATA_WAIT_TIMEOUT = 31;  
+
+
+  //---------------------------------------------------------------------------
+  // Signals
+  //---------------------------------------------------------------------------
+
+  // Command wires
+  wire                   cmd_send_imm_cf, cmd_chain_cf, cmd_reload_cf, cmd_stop_cf;
+  wire [LINES_WIDTH-1:0] cmd_num_lines_cf;
+
+  // Settings registers signals
+  wire [ ADDR_WIDTH-1:0] rec_base_addr_sr;    // Byte address
+  wire [ ADDR_WIDTH-1:0] rec_buffer_size_sr;  // Size in bytes
+  wire [ ADDR_WIDTH-1:0] play_base_addr_sr;   // Byte address
+  wire [ ADDR_WIDTH-1:0] play_buffer_size_sr; // Size in bytes
+  reg                    rec_restart;
+  reg                    rec_restart_clear;
+  wire [  CMD_WIDTH-1:0] command;
+  wire                   command_valid;
+  reg                    play_halt;
+  reg                    play_halt_clear;
+  wire [COUNT_WIDTH:0]   play_max_len_sr;
+
+  // Command FIFO
+  wire cmd_fifo_valid;
+  reg  cmd_fifo_ready;
+
+  // Record Data FIFO (Input)
+  wire [DATA_WIDTH-1:0] rec_fifo_o_tdata;
+  wire                  rec_fifo_o_tvalid;
+  wire                  rec_fifo_o_tready;
+  wire [          15:0] rec_fifo_occupied;
+
+  // Playback Data FIFO (Output)
+  wire [DATA_WIDTH-1:0] play_fifo_i_tdata; 
+  wire                  play_fifo_i_tvalid;
+  wire                  play_fifo_i_tready;
+  wire [          15:0] play_fifo_space;    // Free space in play_axi_fifo
+
+  // Buffer usage registers
+  reg [ADDR_WIDTH-1:0] rec_buffer_avail;  // Amount of free buffer space in words
+  reg [ADDR_WIDTH-1:0] rec_buffer_used;   // Amount of occupied buffer space in words
+
+
+  //---------------------------------------------------------------------------
+  // Registers
+  //---------------------------------------------------------------------------
+
+  // Record Base Address Register. Address is a byte address. This must be a 
+  // multiple of 8 bytes.
+  setting_reg #(
+    .my_addr (SR_REC_BASE_ADDR),
+    .width   (ADDR_WIDTH)
+  ) sr_rec_base_addr (
+    .clk     (clk),
+    .rst     (rst),
+    .strobe  (set_stb),
+    .addr    (set_addr),
+    .in      (set_data),
+    .out     (rec_base_addr_sr),
+    .changed ()
+  );
+
+
+  // Record Buffer Size Register. This indicates the portion of the RAM 
+  // allocated to the record buffer, in bytes. This should be a multiple of 8 
+  // bytes.
+  setting_reg #(
+    .my_addr (SR_REC_BUFFER_SIZE),
+    .width   (ADDR_WIDTH)
+  ) sr_rec_buffer_size (
+    .clk     (clk),
+    .rst     (rst),
+    .strobe  (set_stb),
+    .addr    (set_addr),
+    .in      (set_data),
+    .out     (rec_buffer_size_sr),
+    .changed ()
+  );
+
+
+  // Playback Base Address Register. Address is a byte address. This must be a 
+  // multiple of the 8 bytes.   
+  setting_reg #(
+    .my_addr (SR_PLAY_BASE_ADDR),
+    .width   (ADDR_WIDTH)
+  ) sr_play_base_addr (
+    .clk     (clk),
+    .rst     (rst),
+    .strobe  (set_stb),
+    .addr    (set_addr),
+    .in      (set_data),
+    .out     (play_base_addr_sr),
+    .changed ()
+  );
+
+
+  // Playback Buffer Size Register. This indicates the portion of the RAM 
+  // allocated to the record buffer, in bytes. This should be a multiple of 8 
+  // bytes.
+  setting_reg #(
+    .my_addr (SR_PLAY_BUFFER_SIZE),
+    .width   (ADDR_WIDTH)
+  ) sr_play_buffer_size (
+    .clk     (clk),
+    .rst     (rst),
+    .strobe  (set_stb),
+    .addr    (set_addr),
+    .in      (set_data),
+    .out     (play_buffer_size_sr),
+    .changed ()
+  );
+
+
+  // Record Buffer Restart Register. Software must write to this register after 
+  // updating the base address or buffer size. A write to this register means 
+  // we need to stop any recording in progress and reset the record buffers 
+  // according to the current buffer base address and size registers.
+  always @(posedge clk)
+  begin : sr_restart
+    if(rst) begin
+      rec_restart <= 1'b0;
+    end else begin
+      if(set_stb & (set_addr == SR_REC_RESTART)) begin
+        rec_restart <= 1'b1;
+      end else if (rec_restart_clear) begin
+        rec_restart <= 1'b0;
+      end
+    end
+  end
+
+
+  // Halt Register. A write to this register stops any replay operation as soon 
+  // as the current DRAM transaction completes.
+  always @(posedge clk)
+  begin : sr_halt
+    if(rst) begin
+      play_halt <= 1'b0;
+    end else begin
+      if(set_stb & (set_addr == SR_RX_CTRL_HALT)) begin
+        play_halt <= 1'b1;
+      end else if (play_halt_clear) begin
+        play_halt <= 1'b0;
+      end
+    end
+  end
+
+
+  // Play Command Register
+  //
+  // This register mirrors the behavior of the RFNoC RX radio block. All 
+  // commands are queued up in the replay command FIFO. The fields are as 
+  // follows.
+  //
+  //   send_imm    [31]  Send command immediately (don't use time).
+  //   
+  //   chain       [30]  When done with num_lines, immediately run next command.
+  //   
+  //   reload      [29]  When done with num_lines, rerun the same command if 
+  //                     cmd_chain is set and no new command is available.
+  //   
+  //   stop        [28]  When done with num_lines, stop transferring if 
+  //                     cmd_chain is set.
+  //   
+  //   num_lines [27:0]  Number of samples to transfer to/from block.
+  //
+  setting_reg #(
+    .my_addr (SR_RX_CTRL_COMMAND),
+    .width   (CMD_WIDTH)
+  ) sr_command (
+    .clk     (clk),
+    .rst     (rst),
+    .strobe  (set_stb),
+    .addr    (set_addr),
+    .in      (set_data),
+    .out     (command),
+    .changed (command_valid)
+  );
+
+
+  // Max Length Register. This register sets the number of words for the 
+  // maximum packet size.
+  setting_reg #(
+    .my_addr (SR_RX_CTRL_MAXLEN),
+    .width   (COUNT_WIDTH+1),
+    .at_reset({1'b1, {COUNT_WIDTH{1'b0}}})
+  ) sr_max_len (
+    .clk     (clk),
+    .rst     (rst),
+    .strobe  (set_stb),
+    .addr    (set_addr),
+    .in      (set_data),
+    .out     (play_max_len_sr),
+    .changed ()
+  );
+
+
+  // Implement register read
+  always @(*) begin
+    case (rb_addr)
+      SR_REC_BASE_ADDR    : rb_data = rec_base_addr_sr;
+      SR_REC_BUFFER_SIZE  : rb_data = rec_buffer_size_sr;
+      SR_REC_FULLNESS     : rb_data = rec_buffer_used * WORD_SIZE;
+      SR_PLAY_BASE_ADDR   : rb_data = play_base_addr_sr;
+      SR_PLAY_BUFFER_SIZE : rb_data = play_buffer_size_sr;
+      SR_RX_CTRL_MAXLEN   : rb_data = play_max_len_sr;
+      default             : rb_data = 32'h0;
+    endcase
+  end
+
+
+  //---------------------------------------------------------------------------
+  // Playback Command FIFO
+  //---------------------------------------------------------------------------
+  //
+  // This block queues up commands for playback control.
+  //
+  //---------------------------------------------------------------------------
+
+  axi_fifo_short #(
+    .WIDTH (CMD_WIDTH)
+  ) command_fifo (
+    .clk      (clk),
+    .reset    (rst),
+    .clear    (play_halt_clear),
+    .i_tdata  (command),
+    .i_tvalid (command_valid),
+    .i_tready (),
+    .o_tdata  ({cmd_send_imm_cf, cmd_chain_cf, cmd_reload_cf, cmd_stop_cf, cmd_num_lines_cf}),
+    .o_tvalid (cmd_fifo_valid),
+    .o_tready (cmd_fifo_ready),
+    .occupied (),
+    .space    ()
+  );
+
+
+  //---------------------------------------------------------------------------
+  // Record Input Data FIFO
+  //---------------------------------------------------------------------------
+  //
+  // This FIFO stores data to be recording into the RAM buffer.
+  //
+  //---------------------------------------------------------------------------
+
+  axi_fifo #(
+    .WIDTH (DATA_WIDTH),
+    .SIZE  (REC_FIFO_ADDR_WIDTH)
+  ) rec_axi_fifo (
+    .clk      (clk),
+    .reset    (rst),
+    .clear    (1'b0),
+    //
+    .i_tdata  (i_tdata),
+    .i_tvalid (i_tvalid),
+    .i_tready (i_tready),
+    //
+    .o_tdata  (rec_fifo_o_tdata),
+    .o_tvalid (rec_fifo_o_tvalid),
+    .o_tready (rec_fifo_o_tready),
+    //
+    .space    (),
+    .occupied (rec_fifo_occupied)
+  );
+
+
+  //---------------------------------------------------------------------------
+  // Record State Machine
+  //---------------------------------------------------------------------------
+
+  // FSM States
+  localparam REC_WAIT_FIFO       = 0;
+  localparam REC_CHECK_ALIGN     = 1;
+  localparam REC_DMA_REQ         = 2;
+  localparam REC_WAIT_DMA_START  = 3;
+  localparam REC_WAIT_DMA_COMMIT = 4;
+
+  // State Signals
+  reg [2:0] rec_state;
+
+  // Registers
+  reg [ADDR_WIDTH-1:0] rec_base_addr;   // Last base address pulled from settings register
+  reg [ADDR_WIDTH-1:0] rec_buffer_size; // Last buffer size pulled from settings register
+  reg [ADDR_WIDTH-1:0] rec_addr;        // Current offset into record buffer
+  reg [ADDR_WIDTH-1:0] rec_size;        // Number of words to transfer next
+  reg [ADDR_WIDTH-1:0] rec_size_0;      // Pipeline stage for computation of rec_size
+
+  reg signed [ADDR_WIDTH:0] rec_size_aligned; // rec_size reduced to not cross 4k boundary
+
+  // Timer to count how many cycles we've been waiting for new data
+  reg [$clog2(DATA_WAIT_TIMEOUT+1)-1:0] rec_wait_timer;
+  reg                                   rec_wait_timeout;
+
+  always @(posedge clk) begin
+    if (rst) begin
+      rec_state        <= REC_WAIT_FIFO;
+      rec_addr         <= 0;
+      write_ctrl_valid <= 1'b0;
+
+      rec_buffer_avail <= 0;
+      rec_buffer_used  <= 0;
+      rec_wait_timer   <= 0;
+      rec_wait_timeout <= 0;
+
+    end else begin
+
+      // Default assignments
+      rec_restart_clear <= 1'b0;
+
+      // Update wait timer
+      if (i_tvalid || !rec_fifo_occupied) begin
+        // If a new word is presented to the input FIFO, or the FIFO is empty, 
+        // then reset the timer.
+        rec_wait_timer   <= 0;
+        rec_wait_timeout <= 1'b0;
+      end else if (rec_fifo_occupied) begin
+        // If no new word is written, but there's data in the FIFO, update the 
+        // timer. Latch timeout condition when we reach out limit.
+        rec_wait_timer <= rec_wait_timer + 1;
+
+        if (rec_wait_timer == DATA_WAIT_TIMEOUT) begin
+          rec_wait_timeout <= 1'b1;
+        end
+      end
+
+      // Pre-calculate the aligned size
+      rec_size_aligned <= $signed(AXI_ALIGNMENT) - $signed(rec_addr & (AXI_ALIGNMENT-1));
+
+      //
+      // State logic
+      //
+      case (rec_state)
+
+        REC_WAIT_FIFO : begin
+          // Wait until there's enough data to initiate a transfer from the 
+          // FIFO to the RAM.
+
+          // Check if a restart was requested on the record interface
+          if (rec_restart) begin
+            rec_restart_clear <= 1'b1;
+
+            // Latch the new register values. We don't want them to change 
+            // while we're running.
+            rec_base_addr   <= rec_base_addr_sr;
+            rec_buffer_size <= rec_buffer_size_sr / WORD_SIZE;   // Store size in words
+
+            // Reset counters and address any time we update the buffer size or 
+            // base address.
+            rec_buffer_avail <= rec_buffer_size_sr / WORD_SIZE;  // Store size in words
+            rec_buffer_used  <= 0;
+            rec_addr         <= rec_base_addr_sr;
+
+          // Check if there's room left in the record RAM buffer
+          end else if (rec_buffer_used < rec_buffer_size) begin
+            // See if we can transfer a full burst
+            if (rec_fifo_occupied >= MEM_BURST_SIZE && rec_buffer_avail >= MEM_BURST_SIZE) begin
+              rec_size_0 <= MEM_BURST_SIZE;
+              rec_state  <= REC_CHECK_ALIGN;
+
+            // Otherwise, if we've been waiting a long time, see if we can 
+            // transfer less than a burst.
+            end else if (rec_fifo_occupied > 0 && rec_wait_timeout) begin
+              rec_size_0 <= (rec_fifo_occupied <= rec_buffer_avail) ?
+                            rec_fifo_occupied : rec_buffer_avail;
+              rec_state  <= REC_CHECK_ALIGN;
+            end
+          end
+        end
+
+        REC_CHECK_ALIGN : begin
+          // Check the address alignment, since AXI requires that an access not 
+          // cross 4k boundaries (boo), and the axi_dma_master doesn't handle 
+          // this automatically (boo again). 
+          rec_size <= ($signed({1'b0,rec_size_0}) > rec_size_aligned) ? 
+                      rec_size_aligned : rec_size_0;
+
+          // DMA interface is ready, so transaction will begin
+          rec_state <= REC_DMA_REQ;
+        end
+
+        REC_DMA_REQ : begin
+          // The write count written to the DMA engine should be 1 less than 
+          // the number of words you want to write (not the number of bytes).
+          write_count <= rec_size - 1;
+
+          // Create the physical RAM byte address by combining the address and 
+          // base address.
+          write_addr <= rec_addr;
+
+          // Once the interface is ready, make the DMA request
+          if (write_ctrl_ready) begin
+            // Request the write transaction
+            write_ctrl_valid <= 1'b1;
+            rec_state        <= REC_WAIT_DMA_START;
+          end
+        end
+
+        REC_WAIT_DMA_START : begin
+          // Wait until DMA interface deasserts ready, indicating it has 
+          // started on the request.
+          write_ctrl_valid <= 1'b0;
+          if (!write_ctrl_ready) begin
+            rec_state <= REC_WAIT_DMA_COMMIT;
+          end
+        end
+
+        REC_WAIT_DMA_COMMIT : begin
+          // Wait for the DMA interface to reassert write_ctrl_ready, which 
+          // signals that the DMA engine has received a response for the whole 
+          // write transaction and (we assume) it has been committed to RAM. 
+          // After this, we can update the write address and start the next 
+          // transaction.
+          if (write_ctrl_ready) begin
+             rec_addr         <= rec_addr + (rec_size * WORD_SIZE);
+             rec_buffer_used  <= rec_buffer_used + rec_size;
+             rec_buffer_avail <= rec_buffer_avail - rec_size;
+             rec_state        <= REC_WAIT_FIFO;
+          end
+        end
+
+        default : begin
+          rec_state <= REC_WAIT_FIFO;
+        end
+
+      endcase
+    end
+  end
+
+  // Connect output of record FIFO to input of DMA write interface
+  assign write_data        = rec_fifo_o_tdata;
+  assign write_data_valid  = rec_fifo_o_tvalid;
+  assign rec_fifo_o_tready = write_data_ready;
+
+
+  //---------------------------------------------------------------------------
+  // Playback State Machine
+  //---------------------------------------------------------------------------
+
+  // FSM States
+  localparam PLAY_IDLE            = 0;
+  localparam PLAY_WAIT_DATA_READY = 1;
+  localparam PLAY_SIZE_CALC       = 2;
+  localparam PLAY_DMA_REQ         = 3;
+  localparam PLAY_WAIT_DMA_START  = 4;
+  localparam PLAY_WAIT_DMA_COMMIT = 5;
+  localparam PLAY_DONE_CHECK      = 6;
+
+  // State Signals
+  reg [2:0] play_state;
+
+  // Registers
+  reg [ADDR_WIDTH-1:0] play_base_addr;    // Last base address pulled from settings register
+  reg [ADDR_WIDTH-1:0] play_buffer_size;  // Last buffer size pulled from settings register
+  reg [ADDR_WIDTH-1:0] play_addr;         // Current byte offset into record buffer
+  reg [ADDR_WIDTH-1:0] play_addr_0;       // Pipeline stage for computing play_addr
+  reg [ADDR_WIDTH-1:0] play_addr_1;       // Pipeline stage for computing play_addr
+  reg [ADDR_WIDTH-1:0] play_buffer_end;   // Address of location after end of buffer
+  reg [ADDR_WIDTH-1:0] max_dma_size;      // Maximum size of next transfer, in words
+  //
+  reg [LINES_WIDTH-1:0] cmd_num_lines;        // Copy of cmd_num_lines from last command
+  reg [LINES_WIDTH-1:0] play_words_remaining; // Number of lines left to read for command
+  reg                   cmd_chain;            // Copy of cmd_chain from last command
+  reg                   cmd_reload;           // Copy of cmd_reload from last command
+
+  reg play_full_burst_avail;     // True if we there's a full burst to read
+  reg play_buffer_avail_nonzero; // True if > 0
+  reg cmd_num_lines_cf_nonzero;  // True if > 0
+  reg max_dma_size_ok;           // True if it's OK to read max_dma_size
+
+  reg [ADDR_WIDTH-1:0] max_dma_size_m1;         // max_dma_size - 1
+  reg [ADDR_WIDTH-1:0] play_words_remaining_m1; // play_words_remaining - 1
+
+  reg [ADDR_WIDTH-1:0] play_buffer_avail;   // Number of words left to read in record buffer
+  reg [ADDR_WIDTH-1:0] play_buffer_avail_0; // Pipeline stage for computing play_buffer_avail
+
+  always @(posedge clk)
+  begin
+    if (rst) begin
+      play_state     <= PLAY_IDLE;
+      cmd_fifo_ready <= 1'b0;
+
+    end else begin
+      
+      // Calculate how many words are left to read from the record buffer
+      play_full_burst_avail     <= (play_buffer_avail >= MEM_BURST_SIZE);
+      play_buffer_avail_nonzero <= (play_buffer_avail > 0);
+      cmd_num_lines_cf_nonzero  <= (cmd_num_lines_cf > 0);
+      play_buffer_end           <= play_base_addr_sr + play_buffer_size_sr;
+
+      // Default values
+      cmd_fifo_ready  <= 1'b0;
+      read_ctrl_valid <= 1'b0;
+      play_halt_clear <= 1'b0;
+
+      //
+      // State logic
+      //
+      case (play_state)
+        PLAY_IDLE : begin
+          // Always start reading at the start of the record buffer
+          play_addr <= play_base_addr_sr;
+
+          // Save off command info, in case we need to repeat the command
+          cmd_num_lines    <= cmd_num_lines_cf;
+          cmd_reload       <= cmd_reload_cf;
+          cmd_chain        <= cmd_chain_cf;
+
+          // Save the buffer info so it doesn't update during playback
+          play_base_addr    <= play_base_addr_sr;
+          play_buffer_size  <= play_buffer_size_sr;
+          play_buffer_avail <= play_buffer_size_sr / WORD_SIZE;
+
+          // Wait until we receive a command and we have enough data recorded 
+          // to honor it.
+          if (cmd_fifo_valid && ~play_halt_clear) begin
+            // Load the number of word remaining to complete this command
+            play_words_remaining <= cmd_num_lines_cf;
+
+            // We don't support time yet, so we require send_imm to do 
+            // anything. Also, we can't do anything until we have data recorded.
+            if (cmd_stop_cf) begin
+              // Do nothing, except clear command from the FIFO
+              cmd_fifo_ready <= 1'b1;
+            end else if (cmd_send_imm_cf
+                         && play_buffer_avail_nonzero 
+                         && cmd_num_lines_cf_nonzero) begin
+              // Dequeue the command from the FIFO
+              cmd_fifo_ready <= 1'b1;
+
+              play_state <= PLAY_WAIT_DATA_READY;
+            end
+          end else if (play_halt) begin
+            // In case we get a HALT after a command has finished
+            play_halt_clear <= 1'b1;
+          end
+        end
+
+        PLAY_WAIT_DATA_READY : begin
+          // Save the maximum size we can read from RAM
+          max_dma_size  <= play_full_burst_avail ? MEM_BURST_SIZE : play_buffer_avail;
+
+          // Check if we got a halt command while waiting
+          if (play_halt) begin
+            play_halt_clear <= 1'b1;
+            play_state      <= PLAY_IDLE;
+
+          // Wait for output FIFO to empty sufficiently so we can read an 
+          // entire burst at once. This may be more space than needed, but we 
+          // won't know the exact size until the next state.
+          end else if (play_fifo_space >= MEM_BURST_SIZE) begin
+            play_state <= PLAY_SIZE_CALC;
+          end
+        end
+
+        PLAY_SIZE_CALC : begin
+          // Do some intermediate calculations to determine what the read_count 
+          // should be.
+          play_words_remaining_m1 <= play_words_remaining-1;
+          max_dma_size_m1         <= max_dma_size-1;
+          max_dma_size_ok         <= play_words_remaining >= max_dma_size;
+          play_state              <= PLAY_DMA_REQ;
+        end
+
+        PLAY_DMA_REQ : begin
+          // Load the size of the next read into a register. We try to read the 
+          // max amount available (up to the burst size) or however many words 
+          // are needed to reach the end of the RAM buffer.
+          //
+          // The read count written to the DMA engine should be 1 less than the 
+          // number of words you want to read (not the number of bytes).
+          read_count <= max_dma_size_ok ? max_dma_size_m1 : play_words_remaining_m1;
+
+          // Load the address to read. Note that we don't do an alignment check 
+          // since we assume that multiples of MEM_BURST_SIZE meet the 
+          // AXI_ALIGNMENT requirement.
+          read_addr <= play_addr;
+
+          // Request the read transaction as soon as DMA interface is ready
+          if (read_ctrl_ready) begin
+            read_ctrl_valid <= 1'b1;
+            play_state      <= PLAY_WAIT_DMA_START;
+          end
+        end
+
+        PLAY_WAIT_DMA_START : begin
+          // Wait until DMA interface deasserts ready, indicating it has 
+          // started on the request.
+          read_ctrl_valid <= 1'b0;
+          if (!read_ctrl_ready) begin
+            // Update values for next transaction
+            play_addr_0          <= play_addr + ({{(ADDR_WIDTH-COUNT_WIDTH){1'b0}}, read_count} + 1) * WORD_SIZE;
+            play_words_remaining <= play_words_remaining - ({1'b0, read_count} + 1);
+            play_buffer_avail_0  <= play_buffer_avail - ({1'b0, read_count} + 1);
+
+            play_state <= PLAY_WAIT_DMA_COMMIT;
+          end
+        end
+
+        PLAY_WAIT_DMA_COMMIT : begin
+          // Wait for the DMA interface to reassert read_ctrl_ready, which 
+          // signals that the DMA engine has received a response for the whole 
+          // read transaction.
+          if (read_ctrl_ready) begin
+            // Check if we need to wrap the address for the next transaction
+            if (play_addr_0 >= play_buffer_end) begin
+              play_addr_1       <= play_base_addr_sr;
+              play_buffer_avail <= play_buffer_size_sr / WORD_SIZE;
+            end else begin
+              play_addr_1       <= play_addr_0;
+              play_buffer_avail <= play_buffer_avail_0;
+            end
+
+            play_state <= PLAY_DONE_CHECK;
+          end
+        end
+
+        PLAY_DONE_CHECK : begin
+          play_addr <= play_addr_1;
+
+          // Check if we have more data to transfer for this command
+          if (play_words_remaining) begin
+            play_state <= PLAY_WAIT_DATA_READY;
+
+          // Check if we're chaining
+          end else if (cmd_chain) begin
+            // Check if there's a new command waiting
+            if (cmd_fifo_valid) begin
+              // Load the next command. Note that we don't reset the playback 
+              // address when commands are chained together.
+              play_words_remaining <= cmd_num_lines_cf;
+              cmd_num_lines        <= cmd_num_lines_cf;
+              cmd_reload           <= cmd_reload_cf;
+              cmd_chain            <= cmd_chain_cf;
+
+              // Dequeue the command from the FIFO
+              cmd_fifo_ready <= 1'b1;
+
+              // Stop if it's a stop command, otherwise restart
+              if (cmd_stop_cf) begin
+                play_state <= PLAY_IDLE;
+              end else begin
+                play_state <= PLAY_WAIT_DATA_READY;
+              end
+
+            // Check if we need to restart the previous command
+            end else if (cmd_reload) begin
+              play_words_remaining <= cmd_num_lines;
+              play_state           <= PLAY_WAIT_DATA_READY;
+            end
+          // Nothing left to do
+          end else begin
+            play_state <= PLAY_IDLE;
+          end
+        end
+      endcase
+
+    end
+  end
+
+  // Connect output of DMA master to playback data FIFO
+  assign play_fifo_i_tdata  = read_data;
+  assign play_fifo_i_tvalid = read_data_valid;
+  assign read_data_ready    = play_fifo_i_tready;
+
+
+  //---------------------------------------------------------------------------
+  // TLAST Generation
+  //---------------------------------------------------------------------------
+  //
+  // This block monitors the signals to/from the DMA master and generates the 
+  // TLAST signal. We assert TLAST at the end of every read transaction and 
+  // after every play_max_len_sr words, so that no packets are longer than the 
+  // length indicated by the max_len register.
+  //
+  // The timing of this block relies on the fact that read_ctrl_ready is not 
+  // reasserted by the DMA master until after TLAST gets asserted.
+  //
+  //---------------------------------------------------------------------------
+
+  reg [COUNT_WIDTH-1:0] read_counter;
+  reg [COUNT_WIDTH-1:0] length_counter;
+  reg                   play_fifo_i_tlast;
+
+  always @(posedge clk)
+  begin
+    if (rst) begin
+      play_fifo_i_tlast <= 1'b0;
+    end else begin
+      // Check if we're requesting a read transaction
+      if (read_ctrl_valid && read_ctrl_ready) begin
+        // Initialize read_counter for new transaction
+        read_counter   <= read_count;
+        length_counter <= play_max_len_sr;
+
+        // If read_count is 0, then the first word is also the last word
+        if (read_count == 0) begin
+          play_fifo_i_tlast <= 1'b1;
+        end
+
+      // Track the number of words read out by DMA master
+      end else if (read_data_valid && read_data_ready) begin
+        read_counter   <= read_counter - 1;
+        length_counter <= length_counter - 1;        
+
+        // Check if the word currently being output is the last word of a 
+        // packet, which means we need to clear tlast. 
+        if (play_fifo_i_tlast) begin
+          // But make sure that the next word isn't also the last of a DMA 
+          // burst, for which we will need to keep tlast asserted.
+          if (read_counter != 1) begin
+            play_fifo_i_tlast <= 1'b0;
+          end
+          
+          // Restart length counter
+          length_counter <= play_max_len_sr;
+
+        // Check if the next word to be output should be the last of a packet.
+        end else if (read_counter == 1 || length_counter == 2) begin
+          play_fifo_i_tlast <= 1'b1;
+        end 
+      end
+
+    end
+  end
+
+
+  //---------------------------------------------------------------------------
+  // Playback Output Data FIFO 
+  //---------------------------------------------------------------------------
+  //
+  // This FIFO buffers data that has been read out of RAM as part of a playback 
+  // operation.
+  //
+  //---------------------------------------------------------------------------
+
+  axi_fifo #(
+    .WIDTH (DATA_WIDTH+1),
+    .SIZE  (PLAY_FIFO_ADDR_WIDTH)
+  ) play_axi_fifo (
+    .clk      (clk),
+    .reset    (rst),
+    .clear    (1'b0),
+    //
+    .i_tdata  ({play_fifo_i_tlast, play_fifo_i_tdata}),
+    .i_tvalid (play_fifo_i_tvalid),
+    .i_tready (play_fifo_i_tready),
+    //
+    .o_tdata  ({o_tlast, o_tdata}),
+    .o_tvalid (o_tvalid),
+    .o_tready (o_tready),
+    //
+    .space    (play_fifo_space),
+    .occupied ()
+  );
+
+endmodule
\ No newline at end of file
diff --git a/fpga/usrp3/lib/axi/axi_strip_preamble.v b/fpga/usrp3/lib/axi/axi_strip_preamble.v
new file mode 100644
index 000000000..b4a911880
--- /dev/null
+++ b/fpga/usrp3/lib/axi/axi_strip_preamble.v
@@ -0,0 +1,296 @@
+//
+// Copyright 2016 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Strips preamble, EOP, and CRC/num_words check
+// <preamble> <packet> <EOP> [control_chksum,word_count,payload_chksum] 
+// <preamble>   = 64'h9E6774129E677412
+// <EOP>        = 64'h2A1D632F2A1D632F
+
+module axi_strip_preamble #(
+  parameter WIDTH=64,
+  parameter MAX_PKT_SIZE=512 //Set to 128 in sim to fill up buffers faster to help try and trigger more fail cases. 
+) (
+   input clk,
+   input reset,
+   input clear,
+   //
+   input [WIDTH-1:0] i_tdata,
+   input i_tvalid,
+   output i_tready,
+   //
+   output [WIDTH-1:0] o_tdata,
+   output o_tlast,
+   output o_tvalid,
+   input  o_tready,
+   //
+   output pkt_dropped,
+   output crc_err,
+   output crit_error
+);
+
+    function [0:0] cvita_get_has_time;
+        input [63:0] header;
+        cvita_get_has_time = header[61];
+    endfunction
+    
+   //State machine info
+   reg [1:0] state, next_state;
+   
+   localparam IDLE = 0;
+   localparam CHECK_HDR = 1; 
+   localparam PASS = 2;
+   localparam CHECK_CRC = 3;
+   
+   localparam PAYLOAD_WORDCOUNT_WIDTH = 16;
+   localparam PAYLOAD_CHKSUM_WIDTH = 32;
+   localparam CONTROL_CHKSUM_WIDTH = 16;  
+
+   //Note that held_word is required when EOP is detected
+   //so that we can rewrite into memory the last word + last bit
+   reg [WIDTH-1:0] held_word;
+   reg [WIDTH-1:0] held_word_r;
+   always @(posedge clk) begin
+    if(i_tvalid && i_tready) begin
+        held_word <= i_tdata;
+        held_word_r <= held_word;
+    end
+   end   
+   
+   //Look for next word that specifies if frame has timestamp
+   reg [PAYLOAD_WORDCOUNT_WIDTH-1:0] cntrl_length = 16'd2;
+   always @(posedge clk) begin 
+     if ((next_state == CHECK_HDR || state == CHECK_HDR) && i_tvalid)
+         cntrl_length <= cvita_get_has_time(i_tdata) ? 16'd2 : 16'd1;
+   end
+
+   reg [PAYLOAD_WORDCOUNT_WIDTH-1:0] word_count;
+   wire det_preamble =  (i_tdata == 64'h9E6774129E677412);
+   wire det_eop =       (i_tdata == 64'h2A1D632F2A1D632F);
+
+   wire [PAYLOAD_CHKSUM_WIDTH-1:0] payload_chksum;
+   wire [CONTROL_CHKSUM_WIDTH-1:0] control_chksum;
+   
+   // Payload LFSR. Must hold LFSR once detected EOP so checksum does not keep updating after EOP
+   // Note the payload LFSR also includes the EOP in its checksum
+   crc_xnor #(.INPUT_WIDTH(WIDTH), .OUTPUT_WIDTH(PAYLOAD_CHKSUM_WIDTH)) payload_chksum_gen (
+      .clk(clk), .rst(word_count<=cntrl_length), .hold(~(i_tready && i_tvalid) || det_eop || state == CHECK_CRC),
+      .input_data(i_tdata), .crc_out(payload_chksum)
+   );
+   
+   // Control LFSR. Varies in size based on whether the control information includes a timestamp
+   // Hold the LFSR once the control word(s) have been parsed
+   crc_xnor #(.INPUT_WIDTH(WIDTH), .OUTPUT_WIDTH(CONTROL_CHKSUM_WIDTH)) control_chksum_gen (
+      .clk(clk), .rst(word_count=='d0), .hold(~(i_tready && i_tvalid) || word_count>=cntrl_length),
+      .input_data(i_tdata), .crc_out(control_chksum)
+   );    
+   
+   //Good frame is when the word_count is correct and the control checksum passes. 
+   //Allows passthrough of payloads with bit errors to reduce overall dropped frame rate
+   wire frame_good = (word_count == i_tdata[47:32]) && (control_chksum == i_tdata[63:48]) && state == CHECK_CRC;
+   
+   //CRC error only increments when the state machine makes it to CHECK_CRC state
+   //It will not increment if a preamble or eop is detected outside of IDLE
+   wire payload_crc_check = (payload_chksum == i_tdata[31:0]) && state == CHECK_CRC;
+   assign crc_err = (~frame_good || ~payload_crc_check) && state == CHECK_CRC && i_tvalid;
+
+   //Increment word_count for payload and EOP
+   always @(posedge clk) begin
+      if (state == IDLE || pkt_dropped) begin
+         word_count <= 0;
+      end else if ((state == PASS || state == CHECK_HDR) && i_tready && i_tvalid) begin
+         word_count <= word_count+1'b1;
+      end
+   end
+
+   always @(posedge clk) begin
+      if (reset | clear) begin
+         state <= IDLE;
+      end else begin
+         state <= next_state;
+      end
+   end
+   
+   //Only drop packet if preamble detected outside of idle or bad frame was detected during CRC check
+   assign pkt_dropped = ((state != IDLE) && det_preamble && i_tvalid) || ((state == CHECK_CRC) && ~frame_good && i_tvalid);
+
+   //When preamble is missing or has bit error, state machine stays in IDLE
+   //When EOP is missing or has bit error, either the next preamble is detected and resets logic
+   //or state machine exits on next EOP and fails CRC check.
+   //For cables with very high BER its possible for the write buffer to fill up which causes a critical error and resets everything
+   always @(*) begin
+      case(state)
+         IDLE: begin
+            if (det_preamble && i_tvalid) //Preamble detected so check to see if timestamp is part of header
+               next_state = CHECK_HDR;
+            else
+               next_state = IDLE;
+         end 
+         
+         //Check incoming word to see if frame will have timestamp
+         CHECK_HDR: begin
+            if(crit_error) begin //Critical error so reset SM
+                next_state = IDLE; 
+            end else if(~det_preamble && i_tvalid && i_tready) begin //Found control word so go to normal pass state
+                next_state = PASS; 
+            end else begin
+                next_state = CHECK_HDR;
+            end
+         end             
+         
+         //Note if early preamble is detected in PASS state everything is reset for the next frame
+         PASS: begin
+            if(crit_error) begin //Critical error so reset SM
+                next_state = IDLE;
+            end else if(det_preamble && i_tvalid) begin //Saw preamble so drop packet and start over
+                next_state = CHECK_HDR;  
+            end else if(det_eop && i_tvalid && i_tready) begin //Saw EOP so check for crc on next word
+                next_state = CHECK_CRC; 
+            end else begin
+                next_state = PASS;
+            end
+         end     
+         
+         //Check for crc and go to idle or go back to pass if another preamble is detected
+         CHECK_CRC: begin
+             if(crit_error) begin //Critical error so reset SM
+                 next_state = IDLE; 
+             end else if(det_preamble && i_tvalid) begin //Saw preamble so drop packet and start over
+                 next_state = CHECK_HDR; 
+             end else if(i_tvalid) begin //Got word which should've been the CRC
+                 next_state = IDLE;
+             end else begin
+                 next_state = CHECK_CRC;
+             end
+          end
+         
+         default: begin
+            next_state = IDLE;
+         end
+
+      endcase
+   end 
+
+   wire [WIDTH-1:0] buf_tdata;
+   wire buf_tlast, buf_tvalid, buf_tready, buf_empty;
+   reg buf_full = 1'b0;
+   wire [$clog2(MAX_PKT_SIZE)-1:0] valid_rd_addr;
+   reg buf_empty_r;
+
+   assign mem_tvalid = (state == PASS || state == CHECK_HDR) ? (i_tvalid && ~pkt_dropped) : 1'b0;
+   assign i_tready = (state == PASS || state == CHECK_HDR) ?  buf_tready : 1'b1;
+   
+   assign crit_error = buf_full && buf_empty; //This should never happen, if it does that indicates poor BER over Aurora or packet size too large
+   
+   /////////////////////////////////////////////////
+   //Fifo to store incoming packets
+   //The write pntr rewinds whenever an error occurs
+   /////////////////////////////////////////////////
+   
+   wire int_tready;
+
+   reg [$clog2(MAX_PKT_SIZE)-1:0] wr_addr, prev_wr_addr, rd_addr, old_rd_addr;
+   reg [$clog2(MAX_PKT_SIZE):0] in_pkt_cnt, out_pkt_cnt;
+   wire read         = ~buf_empty && (int_tready || buf_empty_r); //Read from buffer if its no longer empty to prime output reg
+   wire almost_full  = (wr_addr == valid_rd_addr-1'b1); //We need to look at the masked rd_addr in case its 1 ahead
+
+   assign buf_tready   = ~buf_full;
+   wire write        = mem_tvalid && buf_tready && ~det_eop;
+   
+   //If frame was good we need to go back and rewrite the last word and set the last bit
+   wire [WIDTH:0] int_write_data = (frame_good) ? {1'b1,held_word_r} : {1'b0,i_tdata};
+   wire [$clog2(MAX_PKT_SIZE)-1:0] int_wr_addr = (frame_good) ? wr_addr-1 : wr_addr;
+   
+   //BRAM inferred
+   wire [WIDTH:0] buf_data;
+    ram_2port #(.DWIDTH(WIDTH+1), .AWIDTH($clog2(MAX_PKT_SIZE))) pkt_buf
+      (.clka(clk), .ena(1'b1), .wea(1'b1), .addra(int_wr_addr),
+       .dia(int_write_data), .doa(),
+       .clkb(clk), .enb(read), .web(1'b0), .addrb(rd_addr), .dib(),
+       .dob(buf_data));
+
+   // Write logic
+   always @(posedge clk) begin
+        
+        // Rewind logic
+        if(pkt_dropped || crit_error)
+            wr_addr <= prev_wr_addr;
+        else if(write)
+            wr_addr <= wr_addr + 1'b1;
+        
+        if (almost_full) begin
+            if (write && ~read) begin
+                buf_full       <= 1'b1;
+            end
+        end else begin
+            if (~write && read) begin
+                buf_full       <= 1'b0;
+            end
+        end
+            
+        if (frame_good) begin
+            in_pkt_cnt   <= in_pkt_cnt + 1'b1;
+            prev_wr_addr <= wr_addr;
+        end
+           
+        if (reset || clear) begin
+            wr_addr       <= 0;
+            prev_wr_addr  <= 0;
+            in_pkt_cnt    <= 0;
+        end
+        
+        if(reset || clear || crit_error) begin
+            buf_full          <= 1'b0;
+        end
+   end
+
+   // Read logic. Hold data if pkt_count is equal
+   assign buf_empty = in_pkt_cnt == out_pkt_cnt;
+   reg last_word;
+   
+   //Use current read addr only if read is enabled
+   assign valid_rd_addr = (read) ? rd_addr : old_rd_addr;
+   
+   assign buf_tvalid = ~buf_empty_r && ~(last_word && buf_empty);
+   
+   assign buf_tdata = buf_data[WIDTH-1:0];
+   assign buf_tlast = buf_data[WIDTH];
+
+   always @(posedge clk) begin
+     buf_empty_r <= buf_empty;
+     
+     if (read) old_rd_addr <= rd_addr; //Keeps track of last valid rd_addr
+     
+     //Last word has two possibilities
+     //If buffer empty then we need to rewind rd_addr and mask reading from buffer
+     //If buffer is not empty continue with rd_addr and continue reading from buffer
+     last_word <= buf_tvalid && int_tready && buf_tlast;
+     
+     //Need to rewind rd_addr since it incremented one too far
+     //This means there will be one cycle where rd_addr is ahead of where it should be
+     //Other logic that uses rd_addr will have it masked for that cycle
+     if (last_word && buf_empty)    rd_addr      <= rd_addr - 1;
+     else if (read)                 rd_addr      <= rd_addr + 1;
+     
+     // Prevent output until we have a full packet
+     if (buf_tvalid && int_tready && buf_tlast) begin
+       out_pkt_cnt  <= out_pkt_cnt + 1'b1;
+     end
+     
+     if (reset || clear) begin
+       old_rd_addr <= 0;
+       rd_addr     <= 0;
+       out_pkt_cnt <= 0;
+     end
+   end
+   
+   assign o_tlast = buf_tlast;
+   assign o_tdata = buf_tdata;
+   assign o_tvalid = buf_tvalid;
+   assign int_tready = o_tready;
+
+endmodule
+
+  
diff --git a/fpga/usrp3/lib/axi/axi_to_strobed.v b/fpga/usrp3/lib/axi/axi_to_strobed.v
new file mode 100644
index 000000000..9703be5bf
--- /dev/null
+++ b/fpga/usrp3/lib/axi/axi_to_strobed.v
@@ -0,0 +1,52 @@
+//
+// Copyright 2016 Ettus Research
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Convert AXI Stream to a strobed interface.
+// Note: Not especially useful if simply wanting to set
+//       
+
+module axi_to_strobed #(
+  parameter WIDTH = 32,
+  parameter FIFO_SIZE = 1,
+  parameter MIN_RATE = 256
+)(
+  input clk, input reset, input clear,
+  input [$clog2(MIN_RATE):0] out_rate,  // Number of clock cycles between strobes
+  input ready,
+  output error,                           // Output strobe but no data
+  input [WIDTH-1:0] i_tdata, input i_tvalid, input i_tlast, output i_tready,
+  output out_stb, output out_last, output [WIDTH-1:0] out_data
+);
+
+  reg strobe;
+  wire valid;
+  reg [$clog2(MIN_RATE):0] counter = 1;
+  always @(posedge clk) begin
+    if (reset | clear) begin
+      strobe    <= 1'b0;
+      counter   <= 1;
+    end else if (ready) begin
+      if (counter >= out_rate) begin
+        strobe  <= 1'b1;
+        counter <= 1;
+      end else begin
+        strobe  <= 1'b0;
+        counter <= counter + 1'b1;
+      end
+    end else begin
+      strobe <= 1'b0;
+    end
+  end
+
+  axi_fifo #(.WIDTH(WIDTH+1), .SIZE(FIFO_SIZE)) axi_fifo (
+    .clk(clk), .reset(reset), .clear(clear),
+    .i_tdata({i_tlast,i_tdata}), .i_tvalid(i_tvalid), .i_tready(i_tready),
+    .o_tdata({out_last,out_data}), .o_tvalid(valid), .o_tready(strobe),
+    .space(), .occupied());
+
+  assign out_stb = valid & strobe;
+  assign error = ~valid & strobe;
+endmodule
\ No newline at end of file
diff --git a/fpga/usrp3/lib/axi/axis_data_swap.v b/fpga/usrp3/lib/axi/axis_data_swap.v
new file mode 100644
index 000000000..2408ab6c6
--- /dev/null
+++ b/fpga/usrp3/lib/axi/axis_data_swap.v
@@ -0,0 +1,125 @@
+//
+// Copyright 2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: axis_data_swap
+// Description:
+//  A generic data swapper module for AXI-Stream. The contents of
+//  tdata are swapped based on the tswap signal. For each bit 'i'
+//  in tswap, adjacent words of width 2^i are swapped if tswap[i]
+//  is high. For example, if tswap[3] = 1, then each byte in tdata
+//  will be swapped with its adjacent neighbor. It is permissible
+//  for tswap to change for each transfer in an AXIS packet.
+//  Swapping can also be configured to be static (zero logic) by
+//  setting DYNAMIC = 0. To reduce area, certain swap stages can
+//  even be disabled. For example, if STAGES_EN[2:0] is set to 0
+//  then the lowest granularity for swaps will be a byte.
+//
+// Parameters:
+//   - DATA_W: Width of the tdata bus in bits
+//   - USER_W: Width of the tuser bus in bits
+//   - STAGES_EN: Which swap stages are enabled.
+//   - DYNAMIC: Dynamic swapping enabled (use tswap)
+//
+// Signals:
+//   - s_axis_*: The input AXI stream
+//   - m_axis_*: The output AXI stream
+//
+
+module axis_data_swap #(
+  parameter integer              DATA_W    = 256,
+  parameter integer              USER_W    = 1,
+  parameter [$clog2(DATA_W)-1:0] STAGES_EN = 'hFFFFFFFF, //@HACK: Vivado does not allow $clog2 in value of this expr
+  parameter [0:0]                DYNAMIC   = 1
+)(
+  // Clock and Reset
+  input  wire                      clk,
+  input  wire                      rst,
+  // Input AXIS
+  input  wire [DATA_W-1:0]         s_axis_tdata,
+  input  wire [$clog2(DATA_W)-2:0] s_axis_tswap,
+  input  wire [USER_W-1:0]         s_axis_tuser,
+  input  wire                      s_axis_tlast,
+  input  wire                      s_axis_tvalid,
+  output wire                      s_axis_tready,
+  // Output AXIS                   
+  output wire [DATA_W-1:0]         m_axis_tdata,
+  output wire [USER_W-1:0]         m_axis_tuser,
+  output wire                      m_axis_tlast,
+  output wire                      m_axis_tvalid,
+  input  wire                      m_axis_tready
+);
+
+  parameter SWAP_STAGES = $clog2(DATA_W);
+  parameter SWAP_W      = $clog2(DATA_W)-1;
+  genvar s, w;
+
+  wire [DATA_W-1:0] stg_tdata [0:SWAP_STAGES], stg_tdata_swp[0:SWAP_STAGES], stg_tdata_res[0:SWAP_STAGES];
+  wire [SWAP_W-1:0] stg_tswap [0:SWAP_STAGES];
+  wire [USER_W-1:0] stg_tuser [0:SWAP_STAGES];
+  wire              stg_tlast [0:SWAP_STAGES];
+  wire              stg_tvalid[0:SWAP_STAGES];
+  wire              stg_tready[0:SWAP_STAGES];
+
+  // Connect input and output to stage wires
+  generate
+    assign stg_tdata [0] = s_axis_tdata;
+    assign stg_tswap [0] = s_axis_tswap;
+    assign stg_tuser [0] = s_axis_tuser;
+    assign stg_tlast [0] = s_axis_tlast;
+    assign stg_tvalid[0] = s_axis_tvalid;
+    assign s_axis_tready = stg_tready[0];
+
+    assign m_axis_tdata            = stg_tdata [SWAP_STAGES];
+    assign m_axis_tuser            = stg_tuser [SWAP_STAGES];
+    assign m_axis_tlast            = stg_tlast [SWAP_STAGES];
+    assign m_axis_tvalid           = stg_tvalid[SWAP_STAGES];
+    assign stg_tready[SWAP_STAGES] = m_axis_tready;
+  endgenerate
+
+  // Instantiate AXIS flip-flops for each stage
+  generate
+    for (s = 0; s < SWAP_STAGES; s=s+1) begin
+      if (STAGES_EN[SWAP_STAGES-s-1]) begin
+        // Swap Logic
+        for (w = 0; w < (1<<s); w=w+1) begin
+          assign stg_tdata_swp[s][(w*(DATA_W/(1<<s)))+:(DATA_W/(1<<s))] =
+            stg_tdata[s][(((1<<s)-w-1)*(DATA_W/(1<<s)))+:(DATA_W/(1<<s))];
+        end
+        if (DYNAMIC) begin
+          // Honor tswap in DYNAMIC mode.
+          // Also add a flip_flop to break the long start-to-end critical path
+          assign stg_tdata_res[s] = (s > 0 && stg_tswap[s][SWAP_W-s]) ?
+            stg_tdata_swp[s] : stg_tdata[s];
+          // Flip-flop
+          axi_fifo_flop #(.WIDTH(DATA_W+SWAP_W+USER_W+1)) reg_i (
+            .clk(clk), .reset(rst), .clear(1'b0),
+            .i_tdata({stg_tlast[s], stg_tuser[s], stg_tswap[s], stg_tdata_res[s]}),
+            .i_tvalid(stg_tvalid[s]), .i_tready(stg_tready[s]),
+            .o_tdata({stg_tlast[s+1], stg_tuser[s+1], stg_tswap[s+1], stg_tdata[s+1]}),
+            .o_tvalid(stg_tvalid[s+1]), .o_tready(stg_tready[s+1]),
+            .occupied(), .space()
+          );
+        end else begin
+          // Static swapping logic
+          assign stg_tdata [s+1] = stg_tdata_swp[s];
+          assign stg_tswap [s+1] = stg_tswap    [s];
+          assign stg_tuser [s+1] = stg_tuser    [s];
+          assign stg_tlast [s+1] = stg_tlast    [s];
+          assign stg_tvalid[s+1] = stg_tvalid   [s];
+          assign stg_tready[s]   = stg_tready   [s+1];
+        end
+      end else begin
+        // Skip this stage
+        assign stg_tdata [s+1] = stg_tdata [s];
+        assign stg_tswap [s+1] = stg_tswap [s];
+        assign stg_tuser [s+1] = stg_tuser [s];
+        assign stg_tlast [s+1] = stg_tlast [s];
+        assign stg_tvalid[s+1] = stg_tvalid[s];
+        assign stg_tready[s]   = stg_tready[s+1];
+      end
+    end
+  endgenerate
+
+endmodule // axis_data_swap
diff --git a/fpga/usrp3/lib/axi/axis_downsizer.v b/fpga/usrp3/lib/axi/axis_downsizer.v
new file mode 100644
index 000000000..aa8426e5f
--- /dev/null
+++ b/fpga/usrp3/lib/axi/axis_downsizer.v
@@ -0,0 +1,96 @@
+//
+// Copyright 2018 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: axis_downsizer
+// Description: 
+//   An AXI-Stream width conversion module that narrows the input
+//   sample with by a factor of RATIO.
+//   NOTE: This module has end-to-end combanitorial paths. For a
+//         pipelined version, please use axis_width_conv
+//
+// Parameters:
+//   - OUT_DATA_W: The bitwidth of the output data bus. The width of the
+//                 input data bus is OUT_DATA_W*RATIO
+//   - OUT_USER_W: The bitwidth of the output user bus. The width of the
+//                 input user bus is OUT_USER_W*RATIO
+//   - RATIO: The downsizing ratio
+//
+// Signals:
+//   - s_axis_* : Input sample stream (AXI-Stream)
+//   - m_axis_* : Output sample stream (AXI-Stream)
+
+module axis_downsizer #(
+  parameter OUT_DATA_W  = 32,
+  parameter OUT_USER_W  = 1,
+  parameter RATIO       = 4
+)(
+  // Clock, reset and settings
+  input  wire                          clk,              // Clock
+  input  wire                          reset,            // Reset
+  // Data In (AXI-Stream)              
+  input  wire [(OUT_DATA_W*RATIO)-1:0] s_axis_tdata,     // Input stream tdata
+  input  wire [(OUT_USER_W*RATIO)-1:0] s_axis_tuser,     // Input stream tuser
+  input  wire [RATIO-1:0]              s_axis_tkeep,     // Input stream tkeep
+  input  wire                          s_axis_tlast,     // Input stream tlast
+  input  wire                          s_axis_tvalid,    // Input stream tvalid
+  output wire                          s_axis_tready,    // Input stream tready
+  // Data Out (AXI-Stream)             
+  output wire [OUT_DATA_W-1:0]         m_axis_tdata,     // Output stream tdata
+  output wire [OUT_USER_W-1:0]         m_axis_tuser,     // Output stream tuser
+  output wire                          m_axis_tlast,     // Output stream tlast
+  output wire                          m_axis_tvalid,    // Output stream tvalid
+  input  wire                          m_axis_tready     // Output stream tready
+);
+
+  genvar i;
+  generate if (RATIO != 1) begin
+    // Constants
+    localparam [$clog2(RATIO)-1:0] SEL_FIRST  = 'd0;
+    localparam [$clog2(RATIO)-1:0] SEL_LAST   = RATIO-1;
+    localparam [RATIO-1:0]         KEEP_FIRST = {{(RATIO-1){1'b0}}, 1'b1};
+    localparam [RATIO-1:0]         KEEP_ALL   = {(RATIO){1'b1}};
+
+    // Keep a binary-coded and one-hot version of the current
+    // section of the input that is being processed.
+    reg [$clog2(RATIO)-1:0] select = SEL_FIRST;
+    reg [RATIO-1:0]         keep   = KEEP_FIRST;
+
+    // State machine to drive the select bits for the
+    // input selection MUX.
+    always @(posedge clk) begin
+      if (reset) begin
+        select <= SEL_FIRST;
+        keep   <= KEEP_FIRST;
+      end else if (m_axis_tvalid & m_axis_tready) begin
+        select <= (select == SEL_LAST || m_axis_tlast) ? SEL_FIRST  : (select + 'd1);
+        keep   <= (keep   == KEEP_ALL || m_axis_tlast) ? KEEP_FIRST : {keep[RATIO-2:0], 1'b1};
+      end
+    end
+
+    // The input selection MUX
+    wire [OUT_DATA_W-1:0] in_data[0:RATIO-1];
+    wire [OUT_USER_W-1:0] in_user[0:RATIO-1];
+    for (i = 0; i < RATIO; i=i+1) begin
+      assign in_data[i] = s_axis_tdata[i*OUT_DATA_W+:OUT_DATA_W];
+      assign in_user[i] = s_axis_tuser[i*OUT_USER_W+:OUT_USER_W];
+    end
+    assign m_axis_tdata   = in_data[select];
+    assign m_axis_tuser   = in_user[select];
+    assign m_axis_tlast   = s_axis_tlast && (keep == s_axis_tkeep);
+    assign m_axis_tvalid  = s_axis_tvalid;
+    assign s_axis_tready  = m_axis_tvalid && m_axis_tready && ((keep == KEEP_ALL) || m_axis_tlast);
+
+  end else begin  // if (RATIO != 1)
+
+    // Passthrough
+    assign m_axis_tdata   = s_axis_tdata;
+    assign m_axis_tuser   = s_axis_tuser;
+    assign m_axis_tlast   = s_axis_tlast;
+    assign m_axis_tvalid  = s_axis_tvalid;
+    assign s_axis_tready  = m_axis_tready;
+
+  end endgenerate
+
+endmodule // axis_downsizer
diff --git a/fpga/usrp3/lib/axi/axis_packet_flush.v b/fpga/usrp3/lib/axi/axis_packet_flush.v
new file mode 100644
index 000000000..f8b57e0a0
--- /dev/null
+++ b/fpga/usrp3/lib/axi/axis_packet_flush.v
@@ -0,0 +1,148 @@
+//
+// Copyright 2018-2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: axis_packet_flush
+// Description:
+//   When this module is inserted in an AXI-Stream link, it allows
+//   the client to flip a bit to make the stream lossy. When enable=1
+//   all data coming through the input is dropped. This module can
+//   start and stop flushing at packet boundaries to ensure no partial
+//   packets are introduces into the stream. Set FLUSH_PARTIAL_PKTS = 1
+//   to disable that behavior. An optional timeout can be set to 
+//   determine if flushing was done (without turning it off).
+//
+// Parameters:
+//   - WIDTH: The bitwidth of the AXI-Stream bus
+//   - TIMEOUT_W: Width of the timeout counter
+//   - FLUSH_PARTIAL_PKTS: Start flusing immediately even if a packet is in flight
+//   - PIPELINE: Which ports to pipeline? {NONE, IN, OUT, INOUT}
+//
+// Signals:
+//   - s_axis_*  : Input AXI-Stream
+//   - m_axis_*  : Output AXI-Stream
+//   - enable    : Enable flush mode
+//   - timeout   : Flush timeout (# of cycles of inactivity until done)
+//   - flushing  : The module is currently flushing
+//   - done      : Finished flushing (but is still active)
+
+module axis_packet_flush #(
+  parameter WIDTH               = 64,
+  parameter TIMEOUT_W           = 32,
+  parameter FLUSH_PARTIAL_PKTS  = 0,
+  parameter PIPELINE            = "NONE"
+)(
+  // Clock and reset
+  input  wire                 clk,
+  input  wire                 reset,
+  // Control and status       
+  input  wire                 enable,
+  input  wire [TIMEOUT_W-1:0] timeout,
+  output wire                 flushing,
+  output reg                  done = 1'b0,
+  // Input stream             
+  input  wire [WIDTH-1:0]     s_axis_tdata,
+  input  wire                 s_axis_tlast,
+  input  wire                 s_axis_tvalid,
+  output wire                 s_axis_tready,
+  // Output stream            
+  output wire [WIDTH-1:0]     m_axis_tdata,
+  output wire                 m_axis_tlast,
+  output wire                 m_axis_tvalid,
+  input  wire                 m_axis_tready
+);
+
+  //----------------------------------------------
+  // Pipeline Logic
+  //----------------------------------------------
+
+  wire [WIDTH-1:0] i_pipe_tdata,  o_pipe_tdata;
+  wire             i_pipe_tlast,  o_pipe_tlast;
+  wire             i_pipe_tvalid, o_pipe_tvalid;
+  wire             i_pipe_tready, o_pipe_tready;
+
+  generate
+    if (PIPELINE == "IN" || PIPELINE == "INOUT") begin
+      axi_fifo_flop2 #(.WIDTH(WIDTH+1)) in_pipe_i (
+        .clk(clk), .reset(reset), .clear(1'b0),
+        .i_tdata({s_axis_tlast, s_axis_tdata}), .i_tvalid(s_axis_tvalid), .i_tready(s_axis_tready),
+        .o_tdata({i_pipe_tlast, i_pipe_tdata}), .o_tvalid(i_pipe_tvalid), .o_tready(i_pipe_tready),
+        .space(), .occupied()
+      );
+    end else begin
+      assign {i_pipe_tlast, i_pipe_tdata, i_pipe_tvalid} = {s_axis_tlast, s_axis_tdata, s_axis_tvalid}; 
+      assign s_axis_tready = i_pipe_tready;
+    end
+
+    if (PIPELINE == "OUT" || PIPELINE == "INOUT") begin
+      axi_fifo_flop2 #(.WIDTH(WIDTH+1)) out_pipe_i (
+        .clk(clk), .reset(reset), .clear(1'b0),
+        .i_tdata({o_pipe_tlast, o_pipe_tdata}), .i_tvalid(o_pipe_tvalid), .i_tready(o_pipe_tready),
+        .o_tdata({m_axis_tlast, m_axis_tdata}), .o_tvalid(m_axis_tvalid), .o_tready(m_axis_tready),
+        .space(), .occupied()
+      );
+    end else begin
+      assign {m_axis_tlast, m_axis_tdata, m_axis_tvalid} = {o_pipe_tlast, o_pipe_tdata, o_pipe_tvalid};
+      assign o_pipe_tready = m_axis_tready;
+    end
+  endgenerate
+
+  //----------------------------------------------
+  // Flushing Logic
+  //----------------------------------------------
+
+  // Shortcuts
+  wire xfer_stb = i_pipe_tvalid & i_pipe_tready;
+  wire pkt_stb  = xfer_stb & i_pipe_tlast;
+
+  // Packet boundary detector
+  reg mid_pkt = 1'b0;
+  always @(posedge clk) begin
+    if (reset) begin
+      mid_pkt <= 1'b0;
+    end else if (xfer_stb) begin
+      mid_pkt <= ~pkt_stb;
+    end
+  end
+
+  // Flush startup state machine
+  reg active  = 1'b0;
+  always @(posedge clk) begin
+    if (reset) begin
+      active <= 1'b0;
+    end else begin
+      if (enable & (pkt_stb | (~mid_pkt & ~xfer_stb))) begin
+        active <= 1'b1;
+      end else if (~enable) begin
+        active <= 1'b0;
+      end
+    end
+  end
+  assign flushing = (FLUSH_PARTIAL_PKTS == 0) ? active : enable;
+
+  // Flush done detector based on timeout
+  reg [TIMEOUT_W-1:0] cyc_to_go = {TIMEOUT_W{1'b1}};
+  wire done_tmp = (cyc_to_go == {TIMEOUT_W{1'b0}});
+  always @(posedge clk) begin
+    if (reset | ~enable) begin
+      cyc_to_go <= {TIMEOUT_W{1'b1}};
+      done <= 1'b0;
+    end else if (enable & ~active) begin
+      cyc_to_go <= timeout;
+    end else begin
+      if (~done_tmp) begin
+        cyc_to_go <= xfer_stb ? timeout : (cyc_to_go - 1'b1);
+      end
+      done <= done_tmp;
+    end
+  end
+
+  // When flushing, drop all input data and quiet output data
+  // When no flushing, pass data without interruption
+  assign o_pipe_tdata  = i_pipe_tdata;
+  assign o_pipe_tlast  = i_pipe_tlast;
+  assign o_pipe_tvalid = flushing ? 1'b0 : i_pipe_tvalid;
+  assign i_pipe_tready = flushing ? 1'b1 : o_pipe_tready;
+
+endmodule
\ No newline at end of file
diff --git a/fpga/usrp3/lib/axi/axis_shift_register.v b/fpga/usrp3/lib/axi/axis_shift_register.v
new file mode 100644
index 000000000..4b3c9f4de
--- /dev/null
+++ b/fpga/usrp3/lib/axi/axis_shift_register.v
@@ -0,0 +1,209 @@
+//
+// Copyright 2018 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: axis_shift_register
+// Description:
+//   This module implements a chain of flip-flops in connected
+//   using AXI-Stream. It can be used in the following ways:
+//   * As a AXI-Stream shift register. The tready path is 
+//     combinatorial from the output to the input so backpressure
+//     is immediate. The same behavior makes this module non-ideal
+//     to actually break timing critical paths.
+//   * An AXI-Stream wrapper module for a multi-cycle operation
+//     with clock-enables. This can most commonly be used with DSP
+//     operations like filters. Enable the sideband datapath to 
+//     let the module handle handshaking while processing samples
+//     outside it.
+//
+// Parameters:
+//   - WIDTH: The bitwidth of a sample on the data bus.
+//   - NSPC: The number of parallel samples per cycle to process. The
+//       total width of the data bus will be WIDTH*NSPC.
+//   - LATENCY: Number of stages in the shift register
+//   - SIDEBAND_DATAPATH: If SIDEBAND_DATAPATH==1 then tdata is managed
+//       outside this module and imported from s_sideband_data. 
+//       If SIDEBAND_DATAPATH=0, then tdata is managed internally and 
+//       the sideband signals are unused.
+//       Useful when using this module to manage a DSP pipeline where the
+//       data could be changing in each stage.
+//   - GAPLESS: After the shift register has filled up, should gaps be
+//       allowed? If set to 1, then if s_axis_tvalid goes low then the 
+//       pipeline will stall and all bits in stage_stb will immediately go low 
+//       to ensure all stages in the shift register have valid data.
+//       NOTE: This GAPLESS=1 will not allow the final "LATENCY" samples
+//       to exit the shift register.
+//   - PIPELINE: Which ports to pipeline? {NONE, IN, OUT, INOUT}
+//
+// Signals:
+//   - s_axis_* : Input sample stream (AXI-Stream)
+//   - m_axis_* : Output sample stream (AXI-Stream)
+//   - stage_stb : Transfer strobe for each stage 
+//   - stage_eop : Transfer end-of-packet out. bit[i] = stage[i]
+//   - m_sideband_data : Sideband data out for external consumer
+//   - m_sideband_keep : Sideband keep signal out for external consumer
+//   - s_sideband_data : Sideband data in from external producer
+
+module axis_shift_register #(
+  parameter WIDTH             = 32,
+  parameter NSPC              = 1,
+  parameter LATENCY           = 3,
+  parameter SIDEBAND_DATAPATH = 0,
+  parameter GAPLESS           = 0,
+  parameter PIPELINE          = "NONE"
+)(
+  // Clock, reset and settings
+  input  wire                     clk,              // Clock
+  input  wire                     reset,            // Reset
+  // Serial Data In (AXI-Stream)              
+  input  wire [(WIDTH*NSPC)-1:0]  s_axis_tdata,     // Input stream tdata
+  input  wire [NSPC-1:0]          s_axis_tkeep,     // Input stream tkeep (used as a sample qualifier)
+  input  wire                     s_axis_tlast,     // Input stream tlast
+  input  wire                     s_axis_tvalid,    // Input stream tvalid
+  output wire                     s_axis_tready,    // Input stream tready
+  // Serial Data Out (AXI-Stream)             
+  output wire [(WIDTH*NSPC)-1:0]  m_axis_tdata,     // Output stream tdata
+  output wire [NSPC-1:0]          m_axis_tkeep,     // Output stream tkeep (used as a sample qualifier)
+  output wire                     m_axis_tlast,     // Output stream tlast
+  output wire                     m_axis_tvalid,    // Output stream tvalid
+  input  wire                     m_axis_tready,    // Output stream tready
+  // Signals for the sideband data path                     
+  output wire [LATENCY-1:0]       stage_stb,        // Transfer strobe out. bit[i] = stage[i]
+  output wire [LATENCY-1:0]       stage_eop,        // Transfer end-of-packet out. bit[i] = stage[i]
+  output wire [(WIDTH*NSPC)-1:0]  m_sideband_data,  // Sideband data out for external consumer
+  output wire [NSPC-1:0]          m_sideband_keep,  // Sideband keep signal out for external consumer
+  input  wire [(WIDTH*NSPC)-1:0]  s_sideband_data   // Sideband data in from external producer
+);
+  // Shift register width depends on whether the datapath is internal
+  localparam SHREG_WIDTH     = SIDEBAND_DATAPATH[0] ? (NSPC + 1) : ((WIDTH*NSPC) + NSPC + 1);
+  localparam SHREG_TLAST_LOC = SHREG_WIDTH-1;
+  localparam SHREG_TKEEP_HI  = SHREG_WIDTH-2;
+  localparam SHREG_TKEEP_LO  = SHREG_WIDTH-NSPC-1;
+
+  //----------------------------------------------
+  // Pipeline Logic
+  // (fifo_flop2 is used because it breaks timing
+  //  path going both ways: valid and ready)
+  //----------------------------------------------
+  wire [(WIDTH*NSPC)-1:0] i_tdata,  o_tdata;
+  wire [NSPC-1:0]         i_tkeep,  o_tkeep;
+  wire                    i_tlast,  o_tlast;
+  wire                    i_tvalid, o_tvalid;
+  wire                    i_tready, o_tready;
+
+  generate
+    // Input pipeline register if requested
+    if (PIPELINE == "IN" || PIPELINE == "INOUT") begin
+      axi_fifo_flop2 #(.WIDTH((WIDTH*NSPC) + NSPC + 1)) in_pipe_i (
+        .clk(clk), .reset(reset), .clear(1'b0),
+        .i_tdata({s_axis_tlast, s_axis_tkeep, s_axis_tdata}),
+        .i_tvalid(s_axis_tvalid), .i_tready(s_axis_tready),
+        .o_tdata({i_tlast, i_tkeep, i_tdata}), .o_tvalid(i_tvalid), .o_tready(i_tready),
+        .space(), .occupied()
+      );
+    end else begin
+      assign {i_tlast, i_tkeep, i_tdata} = {s_axis_tlast, s_axis_tkeep, s_axis_tdata};
+      assign i_tvalid = s_axis_tvalid;
+      assign s_axis_tready = i_tready;
+    end
+
+    // Output pipeline register if requested
+    if (PIPELINE == "OUT" || PIPELINE == "INOUT") begin
+      axi_fifo_flop2 #(.WIDTH((WIDTH*NSPC) + NSPC + 1)) out_pipe_i (
+        .clk(clk), .reset(reset), .clear(1'b0),
+        .i_tdata({o_tlast, o_tkeep, o_tdata}), .i_tvalid(o_tvalid), .i_tready(o_tready),
+        .o_tdata({m_axis_tlast, m_axis_tkeep, m_axis_tdata}),
+        .o_tvalid(m_axis_tvalid), .o_tready(m_axis_tready),
+        .space(), .occupied()
+      );
+    end else begin
+      assign {m_axis_tlast, m_axis_tkeep, m_axis_tdata} = {o_tlast, o_tkeep, o_tdata};
+      assign m_axis_tvalid = o_tvalid;
+      assign o_tready = m_axis_tready;
+    end
+  endgenerate
+
+  assign m_sideband_data = i_tdata;
+  assign m_sideband_keep = i_tkeep;
+
+  //----------------------------------------------
+  // Shift register stages
+  //----------------------------------------------
+  genvar i;
+  generate
+    if (GAPLESS == 0) begin
+      // Individual stage wires
+      wire [SHREG_WIDTH-1:0]  stg_tdata [0:LATENCY];
+      wire                    stg_tvalid[0:LATENCY];
+      wire                    stg_tready[0:LATENCY];
+      // Shift register input
+      assign stg_tdata[0] = SIDEBAND_DATAPATH[0] ? {i_tlast, i_tkeep} : {i_tlast, i_tkeep, i_tdata};
+      assign stg_tvalid[0] = i_tvalid;
+      assign i_tready = stg_tready[0];
+      // Shift register output
+      assign o_tlast = stg_tdata[LATENCY][SHREG_TLAST_LOC];
+      assign o_tkeep = stg_tdata[LATENCY][SHREG_TKEEP_HI:SHREG_TKEEP_LO];
+      assign o_tdata = SIDEBAND_DATAPATH[0] ? s_sideband_data : stg_tdata[LATENCY][(WIDTH*NSPC)-1:0];
+      assign o_tvalid = stg_tvalid[LATENCY];
+      assign stg_tready[LATENCY] = o_tready;
+  
+      for (i = 0; i < LATENCY; i=i+1) begin: stages
+        axi_fifo_flop #(.WIDTH(SHREG_WIDTH)) reg_i (
+          .clk(clk), .reset(reset), .clear(1'b0),
+          .i_tdata(stg_tdata[i  ]), .i_tvalid(stg_tvalid[i  ]), .i_tready(stg_tready[i  ]),
+          .o_tdata(stg_tdata[i+1]), .o_tvalid(stg_tvalid[i+1]), .o_tready(stg_tready[i+1]),
+          .occupied(), .space()
+        );
+        assign stage_stb[i] = stg_tvalid[i] & stg_tready[i];
+        assign stage_eop[i] = stage_stb[i] & stg_tdata[i][SHREG_TLAST_LOC];
+      end
+    end else begin // if (GAPLESS == 0)
+      wire [(WIDTH*NSPC)-1:0] o_tdata_fifo;
+      wire [NSPC-1:0]         o_tkeep_fifo;
+      wire                    o_tlast_fifo, o_tvalid_fifo, o_tready_fifo;
+
+      // Shift register to hold valids
+      reg  [LATENCY-1:0]     stage_valid = {LATENCY{1'b0}};
+      // Shift register to hold data/last
+      reg  [SHREG_WIDTH-1:0] stage_shreg[0:LATENCY-1];
+      wire [SHREG_WIDTH-1:0] shreg_input = SIDEBAND_DATAPATH[0] ? {i_tlast, i_tkeep} : {i_tlast, i_tkeep, i_tdata};
+      wire                   shreg_ce = i_tready & i_tvalid;
+
+      assign i_tready      = o_tready_fifo;
+      assign o_tvalid_fifo = stage_valid[LATENCY-1] & shreg_ce;
+      assign o_tlast_fifo  = stage_shreg[LATENCY-1][SHREG_TLAST_LOC];
+      assign o_tkeep_fifo  = stage_shreg[LATENCY-1][SHREG_TKEEP_HI:SHREG_TKEEP_LO];
+      assign o_tdata_fifo  = SIDEBAND_DATAPATH[0] ? s_sideband_data : stage_shreg[LATENCY-1][(WIDTH*NSPC)-1:0];
+
+      for (i = 0; i < LATENCY; i=i+1) begin
+        // Initialize shift register
+        initial begin
+          stage_shreg[i] <= {SHREG_WIDTH{1'b0}};
+        end
+        // Shift register logic
+        always @(posedge clk) begin
+          if (reset) begin
+            stage_shreg[i] <= {SHREG_WIDTH{1'b0}};
+            stage_valid[i] <= 1'b0;
+          end else if (shreg_ce) begin
+            stage_shreg[i] <= (i == 0) ? shreg_input : stage_shreg[i-1];
+            stage_valid[i] <= (i == 0) ? 1'b1        : stage_valid[i-1];
+          end
+        end
+        // Outputs
+        assign stage_stb[i] = ((i == 0) ? 1'b1 : stage_valid[i-1]) & shreg_ce;
+        assign stage_eop[i] = stage_stb[i] & ((i == 0) ? i_tlast : stage_shreg[i-1][SHREG_TLAST_LOC]);
+      end
+
+      // The "gapless" logic violates AXI-Stream by having an o_tready -> o_tvalid dependency, 
+      // so we add a FIFO downstream to prevent deadlocks.
+      axi_fifo #(.WIDTH((WIDTH*NSPC) + NSPC + 1), .SIZE($clog2(LATENCY))) out_fifo_i (
+        .clk(clk), .reset(reset), .clear(1'b0),
+        .i_tdata({o_tlast_fifo, o_tkeep_fifo, o_tdata_fifo}), .i_tvalid(o_tvalid_fifo), .i_tready(o_tready_fifo),
+        .o_tdata({o_tlast, o_tkeep, o_tdata}), .o_tvalid(o_tvalid), .o_tready(o_tready),
+        .space(), .occupied()
+      );
+    end
+  endgenerate
+endmodule // axis_shift_register
diff --git a/fpga/usrp3/lib/axi/axis_upsizer.v b/fpga/usrp3/lib/axi/axis_upsizer.v
new file mode 100644
index 000000000..07e313e2d
--- /dev/null
+++ b/fpga/usrp3/lib/axi/axis_upsizer.v
@@ -0,0 +1,104 @@
+//
+// Copyright 2018 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: axis_upsizer
+// Description: 
+//   An AXI-Stream width conversion module that widens the input
+//   sample with by a factor of RATIO.
+//   NOTE: This module has end-to-end combanitorial paths. For a
+//         pipelined version, please use axis_width_conv
+//
+// Parameters:
+//   - IN_DATA_W: The bitwidth of the input data bus. The width of the
+//                output data bus is IN_DATA_W*RATIO
+//   - IN_USER_W: The bitwidth of the input user bus. The width of the
+//                output user bus is IN_USER_W*RATIO
+//   - RATIO: The upsizing ratio
+//
+// Signals:
+//   - s_axis_* : Input sample stream (AXI-Stream)
+//   - m_axis_* : Output sample stream (AXI-Stream)
+
+module axis_upsizer #(
+  parameter IN_DATA_W = 32,
+  parameter IN_USER_W = 1,
+  parameter RATIO     = 4
+)(
+  // Clock, reset and settings
+  input  wire                         clk,              // Clock
+  input  wire                         reset,            // Reset
+  // Data In (AXI-Stream)              
+  input  wire [IN_DATA_W-1:0]         s_axis_tdata,     // Input stream tdata
+  input  wire [IN_USER_W-1:0]         s_axis_tuser,     // Input stream tuser
+  input  wire                         s_axis_tlast,     // Input stream tlast
+  input  wire                         s_axis_tvalid,    // Input stream tvalid
+  output wire                         s_axis_tready,    // Input stream tready
+  // Data Out (AXI-Stream)             
+  output wire [(IN_DATA_W*RATIO)-1:0] m_axis_tdata,     // Output stream tdata
+  output wire [(IN_USER_W*RATIO)-1:0] m_axis_tuser,     // Output stream tuser
+  output wire [RATIO-1:0]             m_axis_tkeep,     // Output stream tkeep
+  output wire                         m_axis_tlast,     // Output stream tlast
+  output wire                         m_axis_tvalid,    // Output stream tvalid
+  input  wire                         m_axis_tready     // Output stream tready
+);
+
+  genvar i;
+  generate if (RATIO != 1) begin
+    // Constants
+    localparam [$clog2(RATIO)-1:0] SEL_FIRST  = 'd0;
+    localparam [$clog2(RATIO)-1:0] SEL_LAST   = RATIO-1;
+    localparam [RATIO-1:0]         KEEP_FIRST = {{(RATIO-1){1'b0}}, 1'b1};
+    localparam [RATIO-1:0]         KEEP_ALL   = {(RATIO){1'b1}};
+  
+    // Keep a binary-coded and one-hot version of the current
+    // section of the output that is being processed.
+    reg [$clog2(RATIO)-1:0] select = SEL_FIRST;
+    reg [RATIO-1:0]         keep   = KEEP_FIRST;
+    // Cached data. Incomplete output word.
+    reg [IN_DATA_W-1:0] cached_data[0:RATIO-2];
+    reg [IN_USER_W-1:0] cached_user[0:RATIO-2];
+
+    // State machine to drive the select bits for the
+    // output DEMUX.
+    always @(posedge clk) begin
+      if (reset) begin
+        select <= SEL_FIRST;
+        keep   <= KEEP_FIRST;
+      end else if (s_axis_tvalid & s_axis_tready) begin
+        select <= (select == SEL_LAST || s_axis_tlast) ? SEL_FIRST  : (select + 'd1);
+        keep   <= (keep   == KEEP_ALL || s_axis_tlast) ? KEEP_FIRST : {keep[RATIO-2:0], 1'b1};
+        cached_data[select] <= s_axis_tdata;
+        cached_user[select] <= s_axis_tuser;
+      end
+    end
+
+    // The output DEMUX
+    for (i = 0; i < RATIO; i=i+1) begin
+      if (i == SEL_LAST) begin
+        assign m_axis_tdata[(i*IN_DATA_W)+:IN_DATA_W] = s_axis_tdata;
+        assign m_axis_tuser[(i*IN_USER_W)+:IN_USER_W] = s_axis_tuser;
+      end else begin
+        assign m_axis_tdata[(i*IN_DATA_W)+:IN_DATA_W] = keep[i+1] ? cached_data[i] : s_axis_tdata;
+        assign m_axis_tuser[(i*IN_USER_W)+:IN_USER_W] = keep[i+1] ? cached_user[i] : s_axis_tuser;
+      end
+    end
+    assign m_axis_tkeep   = keep;
+    assign m_axis_tlast   = s_axis_tlast;
+    assign m_axis_tvalid  = s_axis_tvalid & ((keep == KEEP_ALL) | s_axis_tlast);
+    assign s_axis_tready  = m_axis_tvalid ? m_axis_tready : s_axis_tvalid;
+
+  end else begin  // if (RATIO != 1)
+
+    // Passthrough
+    assign m_axis_tdata   = s_axis_tdata;
+    assign m_axis_tuser   = s_axis_tuser;
+    assign m_axis_tkeep   = 1'b1;
+    assign m_axis_tlast   = s_axis_tlast;
+    assign m_axis_tvalid  = s_axis_tvalid;
+    assign s_axis_tready  = m_axis_tready;
+
+  end endgenerate
+
+endmodule // axis_upsizer
diff --git a/fpga/usrp3/lib/axi/axis_width_conv.v b/fpga/usrp3/lib/axi/axis_width_conv.v
new file mode 100644
index 000000000..2cf19ece8
--- /dev/null
+++ b/fpga/usrp3/lib/axi/axis_width_conv.v
@@ -0,0 +1,232 @@
+//
+// Copyright 2018 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: axis_width_conv
+// Description: 
+//   An AXI-Stream width conversion module that can convert from
+//   an arbitrary input width to an arbitrary output width. The
+//   module also supports an optional clock crossing. Data bits
+//   are grouped into words which will be rearranged by this module.
+//   The contents of a word are not rearranged.
+//   Example (WORD_W=4, IN_WORDS=4, OUT_WORDS=6):
+//    Input  : 3_1_2_0, x_6_5_4           (comma-delimited packets)
+//    Output : 5_4_3_2_1_0, x_x_x_x_x_6   (comma-delimited packets)
+//   NOTE: The use of tkeep in this module is a slight deviation from
+//         the AXI standard where the bits are "byte qualifiers". In
+//         this module, tkeep is a "word qualifier" where the width
+//         of a word can be arbitrary. If WORD_W = 8, the behavior
+//         of this module is identical to an AXI width converter. 
+//
+// Parameters:
+//   - WORD_W: Bitwidth of a word
+//   - IN_WORDS: Number of words in the input stream
+//   - OUT_WORDS: Number of words in the output stream
+//   - SYNC_CLKS: Are s_axis_aclk and m_axis_aclk synchronous to each other?
+//   - PIPELINE: Which ports to pipeline? {NONE, IN, OUT, INOUT}
+//
+// Signals:
+//   - s_axis_* : Input sample stream (AXI-Stream)
+//   - m_axis_* : Output sample stream (AXI-Stream)
+
+module axis_width_conv #(
+  parameter WORD_W    = 8,
+  parameter IN_WORDS  = 4,
+  parameter OUT_WORDS = 6,
+  parameter SYNC_CLKS = 0,
+  parameter PIPELINE  = "NONE"
+)(
+  // Data In (AXI-Stream)                
+  input  wire                          s_axis_aclk,    // Input stream Clock
+  input  wire                          s_axis_rst,     // Input stream Reset
+  input  wire [(IN_WORDS*WORD_W)-1:0]  s_axis_tdata,   // Input stream tdata
+  input  wire [IN_WORDS-1:0]           s_axis_tkeep,   // Input stream tkeep
+  input  wire                          s_axis_tlast,   // Input stream tlast
+  input  wire                          s_axis_tvalid,  // Input stream tvalid
+  output wire                          s_axis_tready,  // Input stream tready
+  // Data Out (AXI-Stream)             
+  input  wire                          m_axis_aclk,    // Output stream Clock
+  input  wire                          m_axis_rst,     // Output stream Reset
+  output wire [(OUT_WORDS*WORD_W)-1:0] m_axis_tdata,   // Output stream tdata
+  output wire [OUT_WORDS-1:0]          m_axis_tkeep,   // Output stream tkeep
+  output wire                          m_axis_tlast,   // Output stream tlast
+  output wire                          m_axis_tvalid,  // Output stream tvalid
+  input  wire                          m_axis_tready   // Output stream tready
+);
+
+  //----------------------------------------------
+  // Pipeline Logic
+  //----------------------------------------------
+  // Add optional input and output pipeline stages
+
+  wire [(IN_WORDS*WORD_W)-1:0]  i_tdata;
+  wire [IN_WORDS-1:0]           i_tkeep;
+  wire                          i_tlast, i_tvalid, i_tready;
+  wire [(OUT_WORDS*WORD_W)-1:0] o_tdata;
+  wire [OUT_WORDS-1:0]          o_tkeep;
+  wire                          o_tlast, o_tvalid, o_tready;
+
+  generate
+    if (PIPELINE == "IN" || PIPELINE == "INOUT") begin
+      axi_fifo_flop2 #(.WIDTH((IN_WORDS*(WORD_W+1))+1)) in_pipe_i (
+        .clk(s_axis_aclk), .reset(s_axis_rst), .clear(1'b0),
+        .i_tdata({s_axis_tlast, s_axis_tkeep, s_axis_tdata}),
+        .i_tvalid(s_axis_tvalid), .i_tready(s_axis_tready),
+        .o_tdata({i_tlast, i_tkeep, i_tdata}),
+        .o_tvalid(i_tvalid), .o_tready(i_tready),
+        .space(), .occupied()
+      );
+    end else begin
+      assign {i_tlast, i_tkeep, i_tdata} = {s_axis_tlast, s_axis_tkeep, s_axis_tdata};
+      assign i_tvalid = s_axis_tvalid;
+      assign s_axis_tready = i_tready;
+    end
+
+    if (PIPELINE == "OUT" || PIPELINE == "INOUT") begin
+      axi_fifo_flop2 #(.WIDTH((OUT_WORDS*(WORD_W+1))+1)) out_pipe_i (
+        .clk(m_axis_aclk), .reset(m_axis_rst), .clear(1'b0),
+        .i_tdata({o_tlast, o_tkeep, o_tdata}),
+        .i_tvalid(o_tvalid), .i_tready(o_tready),
+        .o_tdata({m_axis_tlast, m_axis_tkeep, m_axis_tdata}),
+        .o_tvalid(m_axis_tvalid), .o_tready(m_axis_tready),
+        .space(), .occupied()
+      );
+    end else begin
+      assign {m_axis_tlast, m_axis_tkeep, m_axis_tdata} = {o_tlast, o_tkeep, o_tdata};
+      assign m_axis_tvalid = o_tvalid;
+      assign o_tready = m_axis_tready;
+    end
+  endgenerate
+
+  //----------------------------------------------
+  // Intermediate Data Bus
+  //----------------------------------------------
+  // To perform an M to N width conversion, we first
+  // convert from M to LCM(M, N), then to N
+
+  // Function to compute the least common multiple
+  // of two numbers (parameters or localparams only)
+  function integer lcm;
+    input integer a;
+    input integer b;
+    integer x, y, swap;
+    reg done;
+  begin
+    done = 1'b0;
+    x = a;
+    y = b;
+    while (!done) begin
+      if (x < y) begin
+        swap = x; 
+        x = y; 
+        y = swap; 
+      end else if (y != 0) begin
+        x = x - y;
+      end else begin
+        done = 1'b1; 
+      end
+    end
+    // x is the greatest common divisor
+    // LCM = (a*b)/GCD
+    lcm = (a*b)/x;
+  end
+  endfunction
+
+  // Intermediate bus parameters
+  localparam integer INT_KEEP_W     = lcm(IN_WORDS, OUT_WORDS);
+  localparam integer INT_DATA_W     = INT_KEEP_W * WORD_W;
+  localparam integer UPSIZE_RATIO   = INT_KEEP_W / IN_WORDS;
+  localparam integer DOWNSIZE_RATIO = INT_KEEP_W / OUT_WORDS;
+
+  wire [INT_DATA_W-1:0] fifo_i_tdata, fifo_o_tdata;
+  wire [INT_KEEP_W-1:0] fifo_i_tkeep, fifo_o_tkeep;
+  wire                  fifo_i_tlast, fifo_i_tvalid, fifo_i_tready;
+  wire                  fifo_o_tlast, fifo_o_tvalid, fifo_o_tready;
+
+  // Skip the intermediate FIFO if
+  // - The input and output clocks are the same
+  // - The upsizer is effectively a passthrough and input registering is requested
+  // - The downsizer is effectively a passthrough and output registering is requested
+  localparam [0:0] SKIP_FIFO = (SYNC_CLKS == 1) && (
+      ((PIPELINE == "IN"  || PIPELINE == "INOUT") && (UPSIZE_RATIO == 1)) ||
+      ((PIPELINE == "OUT" || PIPELINE == "INOUT") && (DOWNSIZE_RATIO == 1))
+    );
+  localparam FIFO_SIZE = 1;
+
+  //----------------------------------------------
+  // In => Upsizer => FIFO => Downsizer => Out
+  //----------------------------------------------
+
+  wire [INT_KEEP_W-1:0]     up_keep_flat;
+  wire [UPSIZE_RATIO-1:0]   up_keep_keep;
+  wire [DOWNSIZE_RATIO-1:0] down_keep_keep;
+
+  axis_upsizer #(
+    .IN_DATA_W(IN_WORDS*WORD_W), .IN_USER_W(IN_WORDS),
+    .RATIO(UPSIZE_RATIO)
+  ) upsizer_i (
+    .clk(s_axis_aclk), .reset(s_axis_rst),
+    .s_axis_tdata(i_tdata), .s_axis_tuser(i_tkeep),
+    .s_axis_tlast(i_tlast), .s_axis_tvalid(i_tvalid), .s_axis_tready(i_tready),
+    .m_axis_tdata(fifo_i_tdata), .m_axis_tuser(up_keep_flat), .m_axis_tkeep(up_keep_keep),
+    .m_axis_tlast(fifo_i_tlast), .m_axis_tvalid(fifo_i_tvalid), .m_axis_tready(fifo_i_tready)
+  );
+
+  // tkeep unmasking logic after upsizer
+  genvar i;
+  generate for (i = 0; i < INT_KEEP_W; i = i + 1) begin
+    // tkeep is assumed to be valid only when tlast is asserted
+    // otherwise it is 1
+    assign fifo_i_tkeep[i] = ~fifo_i_tlast |
+      (up_keep_keep[i/IN_WORDS] ? up_keep_flat[i] : 1'b0);
+  end endgenerate
+
+  generate
+    if (SKIP_FIFO) begin
+      assign fifo_o_tdata  = fifo_i_tdata;
+      assign fifo_o_tkeep  = fifo_i_tkeep;
+      assign fifo_o_tlast  = fifo_i_tlast;
+      assign fifo_o_tvalid = fifo_i_tvalid;
+      assign fifo_i_tready = fifo_o_tready;
+    end else begin
+      if (SYNC_CLKS) begin
+        axi_fifo #(.WIDTH(INT_DATA_W+INT_KEEP_W+1), .SIZE(FIFO_SIZE)) fifo_i (
+          .clk(s_axis_aclk), .reset(s_axis_rst), .clear(1'b0),
+          .i_tdata({fifo_i_tlast, fifo_i_tkeep, fifo_i_tdata}),
+          .i_tvalid(fifo_i_tvalid), .i_tready(fifo_i_tready),
+          .o_tdata({fifo_o_tlast, fifo_o_tkeep, fifo_o_tdata}),
+          .o_tvalid(fifo_o_tvalid), .o_tready(fifo_o_tready),
+          .space(), .occupied()
+        );
+      end else begin
+        axi_fifo_2clk #(.WIDTH(INT_DATA_W+INT_KEEP_W+1), .SIZE(FIFO_SIZE)) fifo_i (
+          .reset(s_axis_rst),
+          .i_aclk(s_axis_aclk),
+          .i_tdata({fifo_i_tlast, fifo_i_tkeep, fifo_i_tdata}),
+          .i_tvalid(fifo_i_tvalid), .i_tready(fifo_i_tready),
+          .o_aclk(m_axis_aclk),
+          .o_tdata({fifo_o_tlast, fifo_o_tkeep, fifo_o_tdata}),
+          .o_tvalid(fifo_o_tvalid), .o_tready(fifo_o_tready)
+        );
+      end
+    end
+  endgenerate
+
+  // tkeep masking logic after downsizer
+  generate for (i = 0; i < DOWNSIZE_RATIO; i = i + 1) begin
+    assign down_keep_keep[i] = |fifo_o_tkeep[i*OUT_WORDS+:OUT_WORDS];
+  end endgenerate
+
+  axis_downsizer #(
+    .OUT_DATA_W(OUT_WORDS*WORD_W), .OUT_USER_W(OUT_WORDS),
+    .RATIO(DOWNSIZE_RATIO)
+  ) downsizer_i (
+    .clk(m_axis_aclk), .reset(m_axis_rst),
+    .s_axis_tdata(fifo_o_tdata), .s_axis_tuser(fifo_o_tkeep), .s_axis_tkeep(down_keep_keep),
+    .s_axis_tlast(fifo_o_tlast), .s_axis_tvalid(fifo_o_tvalid), .s_axis_tready(fifo_o_tready),
+    .m_axis_tdata(o_tdata), .m_axis_tuser(o_tkeep),
+    .m_axis_tlast(o_tlast), .m_axis_tvalid(o_tvalid), .m_axis_tready(o_tready)
+  );
+
+endmodule // axis_width_conv
diff --git a/fpga/usrp3/lib/axi/crc_xnor.v b/fpga/usrp3/lib/axi/crc_xnor.v
new file mode 100644
index 000000000..c0923be66
--- /dev/null
+++ b/fpga/usrp3/lib/axi/crc_xnor.v
@@ -0,0 +1,57 @@
+//
+// Copyright 2017 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Generates an LFSR based on a given seed value
+// Note that not all length LFSRs are supported in the file
+// For xnor LSFR equations please refer to following link:
+// https://www.xilinx.com/support/documentation/application_notes/xapp210.pdf
+
+// All indexing will be from 1 to match indexing used in table from app note above
+
+
+module crc_xnor #(
+  parameter INPUT_WIDTH=64,
+  parameter OUTPUT_WIDTH=8
+) (
+   input clk,
+   input [INPUT_WIDTH:1] input_data,
+   input rst,
+   input hold,
+   output [OUTPUT_WIDTH:1] crc_out
+);
+
+    wire [INPUT_WIDTH:1] current_lfsr;
+    reg  [INPUT_WIDTH:1] current_lfsr_r;
+
+    // LFSR based on table given by Xilinx
+    generate if (INPUT_WIDTH == 64) begin
+        assign current_lfsr[1] = current_lfsr_r[64] ^ current_lfsr_r[63] ^ current_lfsr_r[61] ^ current_lfsr_r[60];
+        assign current_lfsr[INPUT_WIDTH:2] = current_lfsr_r[INPUT_WIDTH-1:1]; 
+    end else begin
+        fake_error_thrower invalid_width_parameter();
+    end endgenerate
+
+   always @(posedge clk) begin
+      if (rst) begin
+         current_lfsr_r <= input_data;
+      end else if(~hold) begin
+         current_lfsr_r <= current_lfsr ^ input_data;
+      end
+   end
+
+    // Sum reduce based on output width
+    generate if(INPUT_WIDTH == 64 && OUTPUT_WIDTH == 16) begin
+        assign crc_out =    current_lfsr_r[INPUT_WIDTH:INPUT_WIDTH/4*3+1]+current_lfsr_r[INPUT_WIDTH/4*3:INPUT_WIDTH/4*2+1]+
+                            current_lfsr_r[INPUT_WIDTH/4*2:INPUT_WIDTH/4+1]+current_lfsr_r[INPUT_WIDTH/4:1];
+    end else if(INPUT_WIDTH == 64 && OUTPUT_WIDTH == 32) begin
+        assign crc_out =    current_lfsr_r[INPUT_WIDTH:INPUT_WIDTH/2+1]+current_lfsr_r[INPUT_WIDTH/2:1];
+    end else begin
+        fake_error_thrower invalid_width_parameter();
+    end endgenerate
+      
+   
+
+endmodule 
diff --git a/fpga/usrp3/lib/axi/strobed_to_axi.v b/fpga/usrp3/lib/axi/strobed_to_axi.v
new file mode 100644
index 000000000..378fdc3ab
--- /dev/null
+++ b/fpga/usrp3/lib/axi/strobed_to_axi.v
@@ -0,0 +1,22 @@
+//
+// Copyright 2016 Ettus Research
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module strobed_to_axi #(
+  parameter WIDTH = 32,
+  parameter FIFO_SIZE = 1
+)(
+  input clk, input reset, input clear,
+  input in_stb, input [WIDTH-1:0] in_data, input in_last,
+  output [WIDTH-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready
+);
+
+  axi_fifo #(.WIDTH(WIDTH+1), .SIZE(FIFO_SIZE)) axi_fifo (
+    .clk(clk), .reset(reset), .clear(clear),
+    .i_tdata({in_last,in_data}), .i_tvalid(in_stb), .i_tready(),
+    .o_tdata({o_tlast,o_tdata}), .o_tvalid(o_tvalid), .o_tready(o_tready),
+    .space(), .occupied());
+endmodule
\ No newline at end of file
diff --git a/fpga/usrp3/lib/control/Makefile.srcs b/fpga/usrp3/lib/control/Makefile.srcs
new file mode 100644
index 000000000..578f19ea5
--- /dev/null
+++ b/fpga/usrp3/lib/control/Makefile.srcs
@@ -0,0 +1,61 @@
+#
+# Copyright 2013 Ettus Research LLC
+# Copyright 2017 Ettus Research, a National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+##################################################
+# Control Lib Sources
+##################################################
+CONTROL_LIB_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/control/, \
+ad5662_auto_spi.v \
+arb_qualify_master.v \
+axi_crossbar.v \
+axi_crossbar_regport.v \
+axi_fifo_header.v \
+axi_forwarding_cam.v \
+axi_setting_reg.v \
+axi_slave_mux.v \
+axi_test_vfifo.v \
+bin2gray.v \
+binary_encoder.v \
+db_control.v \
+fe_control.v \
+filter_bad_sid.v \
+gpio_atr_io.v \
+gpio_atr.v \
+gray2bin.v \
+por_gen.v \
+priority_encoder_one_hot.v \
+priority_encoder.v \
+ram_2port_impl.vh \
+ram_2port.v \
+reset_sync.v \
+s7_icap_wb.v \
+serial_to_settings.v \
+setting_reg.v \
+settings_bus_mux.v \
+settings_bus_timed_2clk.v \
+simple_i2c_core.v \
+simple_spi_core.v \
+synchronizer_impl.v \
+synchronizer.v \
+pulse_synchronizer.v \
+user_settings.v \
+axil_regport_master.v \
+axil_to_ni_regport.v \
+regport_resp_mux.v \
+regport_to_xbar_settingsbus.v \
+regport_to_settingsbus.v \
+pulse_stretch.v \
+pulse_stretch_min.v \
+mdio_master.v \
+map/cam_priority_encoder.v \
+map/cam_bram.v \
+map/cam_srl.v \
+map/cam.v \
+map/kv_map.v \
+map/axis_muxed_kv_map.v \
+axil_ctrlport_master.v\
+))
diff --git a/fpga/usrp3/lib/control/ad5662_auto_spi.v b/fpga/usrp3/lib/control/ad5662_auto_spi.v
new file mode 100644
index 000000000..d9f2e53be
--- /dev/null
+++ b/fpga/usrp3/lib/control/ad5662_auto_spi.v
@@ -0,0 +1,99 @@
+//
+// Copyright 2015 Ettus Research
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// The AD5662 DAC serial interface uses 24-bit transfers to encode 16-bits
+// of actual data, two bits for power-down mode, and six pad bits. This
+// module stores a copy of the last-programmed value, and will generate a
+// serial stream if ever the input word (dat) changes. It will ignore
+// changes to (dat) while it is busy with a serial update.
+//
+module ad5662_auto_spi
+(
+  input clk,
+  input [15:0] dat,
+  output reg sclk,
+  output reg mosi,
+  output reg sync_n
+);
+  // initialize ldat to 0, thus forcing
+  // a reload on init.
+  reg [15:0] ldat = 16'd0;
+  wire upd = (dat != ldat); // new data present, need to update hw
+
+  reg [23:0] shft=24'b0;
+  wire [23:0] nxt_shft;
+
+  // clock cycle counter to throttle generated spi cycles
+  // allowing one spi clock cycle every 16 cycles of clk, with clk at 200 MHz
+  // gives a spi clock rate of 12 MHz. This can be made more sophisticated
+  // or parameterized, if more flexibility in clk is needed, of course.
+  reg [3:0] ccnt=4'b0;
+  wire [3:0] nxt_ccnt = ccnt + 1'b1;
+  wire half = ccnt==4'b1000;
+  wire full = ccnt==4'b1111;
+  reg sena, hena;
+  wire cena;
+  always @(posedge clk) if (cena) ccnt <= nxt_ccnt;
+  always @(posedge clk) sena <= full; // state updates and rising sclk
+  always @(posedge clk) hena <= half; // for falling sclk
+
+  // transfer state counter
+  reg [4:0] scnt = 5'b0;
+  reg [4:0] nxt_scnt;
+  always @(posedge clk) begin
+    if (sena) begin
+      scnt <= nxt_scnt;
+      shft <= nxt_shft;
+      mosi <= shft[23];
+    end
+  end
+
+
+  // 32 possible states - more than enough to shift-out 24 bits and manage
+  // the sync_n line
+
+  // particular scnt values of interest
+  localparam READY=5'b00000; // waiting for new data
+  localparam DCAPT=5'b00001; // new data transfers into ldat
+  localparam SYNCL=5'b00010; // assert sync_n low
+  localparam SYNCH=5'b11011; // return sync_n high
+
+  assign cena = upd | scnt != READY;
+
+  always @(scnt or upd)
+  begin
+    case (scnt)
+    READY:
+      nxt_scnt = upd ? DCAPT : READY;
+    SYNCH:
+      nxt_scnt = READY;
+    default:
+      nxt_scnt = scnt + 1'b1;
+    endcase
+  end
+
+  // note: defining the power-down mode bits to 00 for "normal operation"
+  assign nxt_shft = (scnt == SYNCL) ? { 8'b000000_00, ldat } : { shft[22:0], 1'b0 };
+
+  // Update ldat when dat has changed, but only if READY.
+  // Changes to dat arriving faster than can be kept up with here are ignored
+  // until the cycle-in-progress is completed.
+  wire ldat_ena = sena & (scnt == DCAPT);
+  always @(posedge clk) begin
+    if (ldat_ena) ldat <= dat;
+  end
+
+  // keep the sync_n line low when idle to minimize power consumption
+  // it gets brought high just before beginning each transaction
+  wire nxt_sync_n = (scnt==SYNCL) | (scnt==SYNCH);
+  always @(posedge clk) if (sena) sync_n <= nxt_sync_n;
+
+  reg sclk_go;
+  always @(posedge clk) sclk_go <= (scnt > SYNCL);
+  wire nxt_sclk = ~sclk_go ? 1'b1 : ~sclk;
+  always @(posedge clk) if (sena | hena) sclk <= nxt_sclk;
+
+endmodule
diff --git a/fpga/usrp3/lib/control/arb_qualify_master.v b/fpga/usrp3/lib/control/arb_qualify_master.v
new file mode 100644
index 000000000..9a8fdb015
--- /dev/null
+++ b/fpga/usrp3/lib/control/arb_qualify_master.v
@@ -0,0 +1,91 @@
+//
+// Copyright 2012 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+//
+// This module forms the qualification engine for a single master as
+// part of a larger arbitration engine for a slave. It would typically
+// be instantiated from arb_select_master.v to form a complete arbitor solution.
+//
+
+module arb_qualify_master
+  #(
+    parameter WIDTH=16  // Bit width of destination field.
+    )
+    (  
+       input clk,
+       input reset,
+       input clear,     
+       // Header signals
+       input [WIDTH-1:0] header,
+       input header_valid,
+       // Slave Confg Signals
+       input [WIDTH-1:0] slave_addr,
+       input [WIDTH-1:0] slave_mask,
+       input slave_valid,
+       // Arbitration flags
+       output reg master_valid,
+       input master_ack
+       );
+
+   localparam WAIT_HEADER_VALID = 0;
+   localparam MATCH = 1;
+   localparam WAIT_HEADER_NOT_VALID = 2;
+   
+   
+   reg [1:0] state, next_state;
+
+   
+   // Does masked slave address match header field for dest from master?
+   assign    header_match = ((header & slave_mask) == (slave_addr & slave_mask)) && slave_valid;
+   
+   
+   always @(posedge clk)
+     if (reset | clear) begin
+        state <= WAIT_HEADER_VALID;
+	master_valid <= 0;
+     end else
+       begin	  
+	  case(state)
+	    //
+	    // Wait here until Masters FIFO presents a valid header word.
+	    //
+	    WAIT_HEADER_VALID: begin
+	       if (header_valid)
+		 if (header_match) begin
+		    state <= MATCH;
+		    master_valid <= 1;
+		 end else
+		   next_state <= WAIT_HEADER_NOT_VALID;
+	    end
+	    //
+	    // There should only ever be one match across various arbitors
+	    // if they are configured correctly and since the backing FIFO in the
+	    // master should not start to drain until the arbitration is won
+	    // by that master, master_ack should always preceed de-assertion of
+	    // header_valid so we don't check for the other order of deassertion.
+	    //
+	    MATCH: begin
+	       if (master_ack) begin
+		  master_valid <= 0;
+		  state <= WAIT_HEADER_NOT_VALID;
+	       end
+	    end
+	    //
+	    // Wait here until this master starts to drain this packet from his FIFO.
+	    //
+	    WAIT_HEADER_NOT_VALID: begin
+	       if (!header_valid) begin
+		  state <= WAIT_HEADER_VALID;
+	       end
+	    end
+	  endcase // case(state)
+       end // else: !if(reset | clear)
+
+endmodule // arb_qualify_master
+
+	 
\ No newline at end of file
diff --git a/fpga/usrp3/lib/control/axi_crossbar.v b/fpga/usrp3/lib/control/axi_crossbar.v
new file mode 100644
index 000000000..e34c3f43f
--- /dev/null
+++ b/fpga/usrp3/lib/control/axi_crossbar.v
@@ -0,0 +1,164 @@
+/////////////////////////////////////////////////////////////////////
+//
+// Copyright 2012 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: axi_crossbar
+// Description:
+//   - Control Registers
+//   - CAM to setup routing between RFNoC blocks
+//
+/////////////////////////////////////////////////////////////////////
+
+module axi_crossbar
+  #(
+    parameter BASE        = 0,  // settings bus base address
+    parameter FIFO_WIDTH  = 64, // AXI4-STREAM data bus width
+    parameter DST_WIDTH   = 16, // Width of DST field we are routing on.
+    parameter NUM_INPUTS  = 2,  // number of input AXI4-STREAM buses
+    parameter NUM_OUTPUTS = 2   // number of output AXI4-STREAM buses
+    )
+    (
+     input 				   clk,
+     input 				   reset,
+     input 				   clear,
+     input [7:0] 		 local_addr,
+     // Inputs
+     input [(FIFO_WIDTH*NUM_INPUTS)-1:0]   i_tdata,
+     input [NUM_INPUTS-1:0] 		   i_tvalid,
+     input [NUM_INPUTS-1:0] 		   i_tlast,
+     output [NUM_INPUTS-1:0] 		   i_tready,
+     input [NUM_INPUTS-1:0] 		   pkt_present,
+     // Setting Bus
+     input 				   set_stb,
+     input [15:0] 			   set_addr,
+     input [31:0] 			   set_data,
+     // Output
+     output [(FIFO_WIDTH*NUM_OUTPUTS)-1:0] o_tdata,
+     output [NUM_OUTPUTS-1:0] 		   o_tvalid,
+     output [NUM_OUTPUTS-1:0] 		   o_tlast,
+     input [NUM_OUTPUTS-1:0] 		   o_tready,
+     // readback bus
+     input                        rb_rd_stb,
+     input [$clog2(NUM_OUTPUTS)+$clog2(NUM_INPUTS)-1:0] rb_addr,
+     output reg [31:0]            rb_data
+     );
+
+   genvar m,n;
+
+   wire [(NUM_INPUTS*NUM_OUTPUTS)-1:0] forward_valid_in;
+   wire [(NUM_INPUTS*NUM_OUTPUTS)-1:0] forward_ack_in;
+   wire [(NUM_INPUTS*NUM_OUTPUTS)-1:0] forward_valid_out;
+   wire [(NUM_INPUTS*NUM_OUTPUTS)-1:0] forward_ack_out;
+
+   wire [NUM_INPUTS-1:0] i_tready_slave [0:NUM_OUTPUTS-1];
+
+   //
+   // Instantiate an axi_slave_mux for every slave/output of the Crossbar switch.
+   // Each axi_slave_mux contains logic to maux and resolve arbitration
+   // for this particular slave/output.
+   //
+
+   generate
+      for (m = 0; m < NUM_OUTPUTS; m = m + 1) begin: instantiate_slave_mux
+
+	 wire [NUM_INPUTS-1:0] i_tready_tmp;
+
+	 axi_slave_mux
+	   #(
+	     .FIFO_WIDTH(FIFO_WIDTH),     // AXI4-STREAM data bus width
+	     .DST_WIDTH(DST_WIDTH),  // Width of DST field we are routing on.
+	     .NUM_INPUTS(NUM_INPUTS)  // number of input AXI buses
+	     ) 	axi_slave_mux_i
+	     (
+	      .clk(clk),
+	      .reset(reset),
+	      .clear(clear),
+	      // Inputs
+	      .i_tdata(i_tdata),
+	      .i_tvalid(i_tvalid),
+	      .i_tlast(i_tlast),
+	      .i_tready(i_tready_tmp),
+	      // Forwarding flags (One from each Input/Master)
+	      .forward_valid(forward_valid_in[(m+1)*NUM_INPUTS-1:m*NUM_INPUTS]),
+	      .forward_ack(forward_ack_out[(m+1)*NUM_INPUTS-1:m*NUM_INPUTS]),
+	      // Output
+	      .o_tdata(o_tdata[(m*FIFO_WIDTH)+FIFO_WIDTH-1:m*FIFO_WIDTH]),
+	      .o_tvalid(o_tvalid[m]),
+	      .o_tlast(o_tlast[m]),
+	      .o_tready(o_tready[m])
+	      );
+
+	 if (m==0)
+	       assign i_tready_slave[0] = i_tready_tmp;
+	 else
+	      assign i_tready_slave[m] = i_tready_tmp | i_tready_slave[m-1] ;
+
+      end // block: instantiate_slave_mux
+   endgenerate
+
+   assign 	  i_tready = i_tready_slave[NUM_OUTPUTS-1];
+
+   //
+   // Permute the forwarding flag buses
+   //
+
+   generate
+      for (m = 0; m < NUM_OUTPUTS; m = m + 1) begin: permute_outer
+	 for (n = 0; n < NUM_INPUTS; n = n + 1) begin: permute_inner
+	    assign forward_valid_in[n*NUM_OUTPUTS+m] = forward_valid_out[n+m*NUM_INPUTS];
+	    assign forward_ack_in[n+m*NUM_INPUTS] = forward_ack_out[n*NUM_OUTPUTS+m];
+	 end
+      end
+
+   endgenerate
+
+
+   //
+   // Instantiate an axi_forwarding_cam for every Input/Master of the Crossbar switch.
+   // Each contains a TCAM like lookup that allocates an egress port.
+   //
+
+   wire [31:0] 	   rb_data_mux[0:NUM_INPUTS-1];
+
+   generate
+      for (m = 0; m < NUM_INPUTS; m = m + 1) begin: instantiate_cam
+	 axi_forwarding_cam
+	   #(
+	     .BASE(BASE),
+	     .WIDTH(FIFO_WIDTH),  // Bit width of FIFO word.
+	     .NUM_OUTPUTS(NUM_OUTPUTS)
+	     ) axi_forwarding_cam_i
+	     (
+	      .clk(clk),
+	      .reset(reset),
+	      .clear(clear),
+	      // Monitored FIFO signals
+	      .o_tdata(i_tdata[(m*FIFO_WIDTH)+FIFO_WIDTH-1:m*FIFO_WIDTH]),
+	      .o_tvalid(i_tvalid[m]),
+	      .o_tready(i_tready[m]),
+	      .o_tlast(i_tlast[m]),
+	      .pkt_present(pkt_present[m]),
+	      // Configuration
+	      .local_addr(local_addr),
+	      // Setting Bus
+	      .set_stb(set_stb),
+	      .set_addr(set_addr),
+	      .set_data(set_data),
+	      // Header signals
+	      .forward_valid(forward_valid_out[(m+1)*NUM_OUTPUTS-1:m*NUM_OUTPUTS]),
+	      .forward_ack(forward_ack_in[(m+1)*NUM_OUTPUTS-1:m*NUM_OUTPUTS]),
+	      // Readback bus
+	      .rb_rd_stb(rb_rd_stb && (rb_addr[$clog2(NUM_OUTPUTS)+$clog2(NUM_INPUTS)-1:$clog2(NUM_OUTPUTS)] == m)),
+	      .rb_addr(rb_addr[$clog2(NUM_OUTPUTS)-1:0]),
+	      .rb_data(rb_data_mux[m])
+	      );
+      end // block: instantiate_fifo_header
+   endgenerate
+
+   // Pipeline readback data to alleviate timing issues
+   always @(posedge clk) rb_data <= rb_data_mux[rb_addr[$clog2(NUM_OUTPUTS)+$clog2(NUM_INPUTS)-1:$clog2(NUM_OUTPUTS)]];
+
+
+endmodule // axi_crossbar
diff --git a/fpga/usrp3/lib/control/axi_crossbar_intf.sv b/fpga/usrp3/lib/control/axi_crossbar_intf.sv
new file mode 100644
index 000000000..b0c07ba9f
--- /dev/null
+++ b/fpga/usrp3/lib/control/axi_crossbar_intf.sv
@@ -0,0 +1,87 @@
+//
+// Copyright 2015 Ettus Research LLC
+// Copyright 2017 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Wraps AXI crossbar and exposes cvita_stream_t and settings_bus_t interfaces 
+
+`include "sim_cvita_lib.svh"
+`include "sim_set_rb_lib.svh"
+
+module axi_crossbar_intf
+#(
+  parameter BASE        = 0,  // settings bus base address
+  parameter FIFO_WIDTH  = 64, // AXI4-STREAM data bus width
+  parameter DST_WIDTH   = 16, // Width of DST field we are routing on.
+  parameter NUM_PORTS   = 2   // number of cvita busses
+)(
+  input clk,
+  input reset,
+  input clear,
+  input [7:0] local_addr,
+  axis_t.slave s_cvita[0:NUM_PORTS-1],
+  axis_t.master m_cvita[0:NUM_PORTS-1],
+  settings_bus_t.slave  set_bus,
+  readback_bus_t.master rb_bus
+);
+
+  wire [NUM_PORTS*64-1:0]  flat_i_tdata;
+  wire [NUM_PORTS-1:0]     i_tlast, i_tvalid, i_tready;
+  wire [NUM_PORTS*64-1:0]  flat_o_tdata;
+  wire [NUM_PORTS-1:0]     o_tlast, o_tvalid, o_tready;
+
+  // Flattern CE tdata arrays
+  genvar i;
+  generate
+    for (i = 0; i < NUM_PORTS; i = i + 1) begin
+      assign flat_i_tdata[i*FIFO_WIDTH+FIFO_WIDTH-1:i*FIFO_WIDTH] = s_cvita[i].tdata;
+      assign i_tlast[i] = s_cvita[i].tlast;
+      assign i_tvalid[i] = s_cvita[i].tvalid;
+      assign s_cvita[i].tready = i_tready[i];
+    end
+    for (i = 0; i < NUM_PORTS; i = i + 1) begin
+      assign m_cvita[i].tdata = flat_o_tdata[i*FIFO_WIDTH+FIFO_WIDTH-1:i*FIFO_WIDTH];
+      assign m_cvita[i].tlast = o_tlast[i];
+      assign m_cvita[i].tvalid = o_tvalid[i];
+      assign o_tready[i] = m_cvita[i].tready;
+    end
+  endgenerate
+
+  wire set_stb = set_bus.stb;
+  wire [15:0] set_addr = set_bus.addr;
+  wire [31:0] set_data = set_bus.data;
+  wire rb_rd_stb = rb_bus.stb;
+  wire [2*$clog2(NUM_PORTS):0] rb_addr = rb_bus.addr[2*$clog2(NUM_PORTS):0];
+  wire [31:0] rb_data;
+  assign rb_bus.data = rb_data;
+
+  axi_crossbar #(
+    .BASE(BASE),
+    .FIFO_WIDTH(FIFO_WIDTH),
+    .DST_WIDTH(DST_WIDTH),
+    .NUM_INPUTS(NUM_PORTS),
+    .NUM_OUTPUTS(NUM_PORTS))
+  inst_axi_crossbar (
+    .clk(clk),
+    .reset(reset),
+    .clear(clear),
+    .local_addr(local_addr),
+    .i_tdata(flat_i_tdata),
+    .i_tvalid(i_tvalid),
+    .i_tlast(i_tlast),
+    .i_tready(i_tready),
+    .pkt_present(i_tvalid),
+    .set_stb(set_stb),
+    .set_addr(set_addr),
+    .set_data(set_data),
+    .o_tdata(flat_o_tdata),
+    .o_tvalid(o_tvalid),
+    .o_tlast(o_tlast),
+    .o_tready(o_tready),
+    .rb_rd_stb(rb_rd_stb),
+    .rb_addr(rb_addr),
+    .rb_data(rb_data));
+
+endmodule
+
diff --git a/fpga/usrp3/lib/control/axi_crossbar_regport.v b/fpga/usrp3/lib/control/axi_crossbar_regport.v
new file mode 100644
index 000000000..15b74517d
--- /dev/null
+++ b/fpga/usrp3/lib/control/axi_crossbar_regport.v
@@ -0,0 +1,193 @@
+/////////////////////////////////////////////////////////////////////
+//
+// Copyright 2017 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: axi_crossbar_regport
+// Description:
+//   - axi_crossbar with regport interface for register/CAM access
+//
+//////////////////////////////////////////////////////////////////////
+
+module axi_crossbar_regport #(
+  parameter REG_BASE    = 0,  // settings bus base address
+  parameter FIFO_WIDTH  = 64, // AXI4-STREAM data bus width
+  parameter DST_WIDTH   = 16, // Width of DST field we are routing on.
+  parameter NUM_INPUTS  = 2,  // number of input AXI4-STREAM buses
+  parameter NUM_OUTPUTS = 2,   // number of output AXI4-STREAM buses
+  parameter REG_DWIDTH  = 32, // Width of the AXI4-Lite data bus (must be 32 or 64)
+  parameter REG_AWIDTH  = 14  // Width of the address bus
+)(
+  input                                 clk,
+  input                                 reset,
+  input                                 clear,
+
+  input                                 reg_wr_req,
+  input  [REG_AWIDTH-1:0]               reg_wr_addr,
+  input  [REG_DWIDTH-1:0]               reg_wr_data,
+
+  input                                 reg_rd_req,
+  input  [REG_AWIDTH-1:0]               reg_rd_addr,
+  output [REG_DWIDTH-1:0]               reg_rd_data,
+  output                                reg_rd_resp,
+
+  // Inputs
+  input [(FIFO_WIDTH*NUM_INPUTS)-1:0]   i_tdata,
+  input [NUM_INPUTS-1:0]                i_tvalid,
+  input [NUM_INPUTS-1:0]                i_tlast,
+  output [NUM_INPUTS-1:0]               i_tready,
+  input [NUM_INPUTS-1:0]                pkt_present,
+
+  // Output
+  output [(FIFO_WIDTH*NUM_OUTPUTS)-1:0] o_tdata,
+  output [NUM_OUTPUTS-1:0]              o_tvalid,
+  output [NUM_OUTPUTS-1:0]              o_tlast,
+  input [NUM_OUTPUTS-1:0]               o_tready
+);
+
+  localparam XBAR_VERSION              = 32'b1;
+  localparam XBAR_NUM_PORTS            = NUM_INPUTS; //or NUM_OUTPUTS
+
+  localparam REG_XBAR_VERSION          = REG_BASE + 14'h10;
+  localparam REG_XBAR_NUM_PORTS        = REG_BASE + 14'h14;
+  localparam REG_XBAR_LOCAL_ADDR       = REG_BASE + 14'h18;
+  localparam REG_BASE_XBAR_SETTING_REG = REG_BASE + 14'h20;
+  localparam REG_END_ADDR_XBAR_SETTING_REG = REG_BASE + 14'h1000;
+
+  // Settings bus address width
+  localparam SR_AWIDTH = 12;
+
+  wire                  xbar_set_stb;
+  wire [REG_DWIDTH-1:0] xbar_set_data;
+  wire [SR_AWIDTH-1:0]  xbar_set_addr;
+
+  wire                  xbar_rb_stb;
+  wire [SR_AWIDTH-1:0]  xbar_rb_addr;
+  wire [REG_DWIDTH-1:0] xbar_rb_data;
+
+  reg  [31:0]           local_addr_reg;
+  reg                   reg_rd_resp_glob;
+  reg  [REG_DWIDTH-1:0] reg_rd_data_glob;
+
+  wire [REG_DWIDTH-1:0] reg_rd_data_xbar;
+  wire                  reg_rd_resp_xbar;
+
+  regport_resp_mux #(
+    .WIDTH(REG_DWIDTH),
+    .NUM_SLAVES(2)
+  ) inst_regport_resp_mux_xbar (
+    .clk(clk),
+    .reset(reset),
+    .sla_rd_resp({reg_rd_resp_glob, reg_rd_resp_xbar}),
+    .sla_rd_data({reg_rd_data_glob, reg_rd_data_xbar}),
+    .mst_rd_resp(reg_rd_resp),
+    .mst_rd_data(reg_rd_data)
+  );
+
+  // Read Registers
+  always @ (posedge clk) begin
+    if (reset) begin
+      local_addr_reg <= 32'h0;
+    end
+    else begin
+    if (reg_wr_req)
+      case (reg_wr_addr)
+        REG_XBAR_LOCAL_ADDR:
+          local_addr_reg  <= reg_wr_data;
+      endcase
+    end
+  end
+
+  // Write Registers
+  always @ (posedge clk) begin
+    if (reset)
+      reg_rd_resp_glob <= 1'b0;
+
+    else begin
+      if (reg_rd_req) begin
+        reg_rd_resp_glob <= 1'b1;
+
+        case (reg_rd_addr)
+        REG_XBAR_VERSION:
+          reg_rd_data_glob <= XBAR_VERSION;
+
+        REG_XBAR_NUM_PORTS:
+          reg_rd_data_glob <= XBAR_NUM_PORTS;
+
+        REG_XBAR_LOCAL_ADDR:
+          reg_rd_data_glob <= local_addr_reg;
+
+        default:
+          reg_rd_resp_glob <= 1'b0;
+        endcase
+      end
+      else if (reg_rd_resp_glob) begin
+          reg_rd_resp_glob <= 1'b0;
+      end
+    end
+  end
+
+  regport_to_xbar_settingsbus #(
+    .BASE(REG_BASE_XBAR_SETTING_REG),
+    .END_ADDR(REG_END_ADDR_XBAR_SETTING_REG),
+    .DWIDTH(REG_DWIDTH),
+    .AWIDTH(REG_AWIDTH),
+    .SR_AWIDTH(SR_AWIDTH),
+    .ADDRESSING("WORD")
+  ) inst_regport_to_xbar_settingsbus (
+    .clk(clk),
+    .reset(reset),
+
+    .reg_wr_req(reg_wr_req),
+    .reg_wr_addr(reg_wr_addr),
+    .reg_wr_data(reg_wr_data),
+    .reg_rd_req(reg_rd_req),
+    .reg_rd_addr(reg_rd_addr),
+    .reg_rd_data(reg_rd_data_xbar),
+    .reg_rd_resp(reg_rd_resp_xbar),
+
+    .set_stb(xbar_set_stb),
+    .set_addr(xbar_set_addr),
+    .set_data(xbar_set_data),
+    .rb_stb(xbar_rb_stb),
+    .rb_addr(xbar_rb_addr),
+    .rb_data(xbar_rb_data)
+  );
+
+  axi_crossbar #(
+    .BASE(0), // Set to 0 as logic for other values has not been tested
+    .FIFO_WIDTH(FIFO_WIDTH),
+    .DST_WIDTH(DST_WIDTH),
+    .NUM_INPUTS(NUM_INPUTS),
+    .NUM_OUTPUTS(NUM_OUTPUTS)
+  ) axi_crossbar (
+    .clk(clk),
+    .reset(reset),
+    .clear(1'b0),
+    .local_addr(local_addr_reg),
+
+    // settings bus for config
+    .set_stb(xbar_set_stb),
+    .set_addr({4'b0000,xbar_set_addr}),
+    .set_data(xbar_set_data),
+    .rb_rd_stb(xbar_rb_stb),
+    .rb_addr(xbar_rb_addr[$clog2(NUM_INPUTS)+$clog2(NUM_OUTPUTS)-1:0]),
+    .rb_data(xbar_rb_data),
+
+    // inputs, real men flatten busses
+    .i_tdata(i_tdata),
+    .i_tlast(i_tlast),
+    .i_tvalid(i_tvalid),
+    .i_tready(i_tready),
+
+    // outputs, real men flatten busses
+    .o_tdata(o_tdata),
+    .o_tlast(o_tlast),
+    .o_tvalid(o_tvalid),
+    .o_tready(o_tready),
+    .pkt_present(pkt_present)
+  );
+
+endmodule // axi_crossbar_regport
+
diff --git a/fpga/usrp3/lib/control/axi_fifo_header.v b/fpga/usrp3/lib/control/axi_fifo_header.v
new file mode 100644
index 000000000..551c2b760
--- /dev/null
+++ b/fpga/usrp3/lib/control/axi_fifo_header.v
@@ -0,0 +1,87 @@
+//
+// Copyright 2012 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+//
+// This module is connected to the output port of an AXI4-STREAM FIFO that is used to move packetized data.
+// It extracts and indicates the header (first word) of a packet in the FIFO. The header and flag are pipelined
+// for timing closure.
+//
+
+module axi_fifo_header
+  #(
+    parameter WIDTH=64  // Bit width of FIFO word.
+    )
+    (
+     input clk,
+     input reset,
+     input clear,
+     // Monitored FIFO signals
+     input [WIDTH-1:0] o_tdata,
+     input o_tvalid,
+     input o_tready,
+     input o_tlast,
+     input pkt_present,
+     // Header signals
+     output reg [WIDTH-1:0] header,
+     output reg header_valid
+     );
+
+   localparam WAIT_SOF = 0;
+   localparam WAIT_EOF = 1;
+   
+   reg 	    out_state;
+   
+
+    //
+    // Monitor packets leaving FIFO
+    //
+    always @(posedge clk)
+      if (reset | clear) begin
+         out_state <= WAIT_SOF;
+      end else
+	case(out_state)
+	  //
+	  // After RESET or the EOF of previous packet, the first cycle with
+	  // output valid asserted is the SOF and presents the Header word.
+	  // The cycle following the concurrent presentation of asserted output 
+	  // valid and output ready presents the word following the header.
+	  //
+          WAIT_SOF: 
+            if (o_tvalid && o_tready) begin
+               out_state <= WAIT_EOF;
+            end else begin
+               out_state <= WAIT_SOF;
+            end
+	  //
+	  // EOF is signalled by o_tlast asserted whilst output valid and ready asserted.
+	  //
+          WAIT_EOF: 
+            if (o_tlast && o_tvalid && o_tready) begin
+               out_state <= WAIT_SOF;
+            end else begin
+               out_state <= WAIT_EOF;
+            end
+	endcase // case(in_state)
+   
+   //
+   // Pipeline Header signals
+   //
+   always @(posedge clk)
+     if (reset | clear) begin
+	header <= 0;
+	header_valid <= 0;
+     end else if (o_tvalid && (out_state == WAIT_SOF) && pkt_present) begin
+	// Header will remian valid until o_tready is asserted as this will cause a state transition.
+	header <= o_tdata;
+	header_valid <= 1;
+     end else begin
+	header_valid <= 0;
+     end
+
+
+endmodule // axi_fifo_header
diff --git a/fpga/usrp3/lib/control/axi_forwarding_cam.v b/fpga/usrp3/lib/control/axi_forwarding_cam.v
new file mode 100644
index 000000000..64076bd0a
--- /dev/null
+++ b/fpga/usrp3/lib/control/axi_forwarding_cam.v
@@ -0,0 +1,232 @@
+//
+// Copyright 2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// This module implements a highly customized content-addressable memory (CAM)
+// that enables forwarding decisions to be made on a 16 bit field from a stream ID (SID) field.
+// The forwarding is generic in the sense that a SID's host destination can map to any endpoint / crossbar port.
+//
+// The 16 bits are allocated by convention as 8 bits of Network address (addresses USRP's / AXI crossbars) and
+// 8 bits of Host address (addresses endpoints / crossbar ports in a USRP).
+//
+// By definition if the destination field in the SID addresses a different
+// USRP / crossbar than this one then we don't care about the Host field, only the Network field.
+// We only look at the Host field when the Network field addresses us.
+// Thus we need a CAM of 256+256 entries with Log2(N) bits, where N is the number of
+// slave(output) ports on the crossbar switch.
+//
+// SID format:
+//
+// |---------|---------|---------|---------|
+// |   SRC   |   SRC   |   DST   |   DST   |
+// | NETWORK |   HOST  | NETWORK |   HOST  |
+// |---------|---------|---------|---------|
+//      8         8         8         8
+
+module axi_forwarding_cam
+  #(
+    parameter BASE = 0,      // BASE address for setting registers in this block. (512 addrs used)
+    parameter WIDTH=64,      // Bit width of FIFO word.
+    parameter NUM_OUTPUTS=2  // Number of outputs (destinations) in crossbar.
+    )
+    (
+     input 			  clk,
+     input 			  reset,
+     input 			  clear,
+     // Monitored FIFO signals
+     input [WIDTH-1:0] 		  o_tdata,
+     input 			  o_tvalid,
+     input 			  o_tready,
+     input 			  o_tlast,
+     input 			  pkt_present,
+     // Configuration
+     input [7:0] 		  local_addr,
+     // Setting Bus
+     input 			  set_stb,
+     input [15:0] 		  set_addr,
+     input [31:0] 		  set_data,
+
+     output reg [NUM_OUTPUTS-1:0] forward_valid,
+     input [NUM_OUTPUTS-1:0] 	  forward_ack,
+
+     input                        rb_rd_stb,
+     input [$clog2(NUM_OUTPUTS)-1:0] rb_addr,
+     output [31:0]                rb_data
+     );
+
+
+   localparam WAIT_SOF = 0;
+   localparam WAIT_EOF = 1;
+   reg 				  state;
+
+   localparam IDLE = 0;
+   localparam FORWARD = 1;
+   localparam WAIT = 2;
+
+   reg 	[1:0]			  demux_state;
+
+   reg [15:0] 			  dst;
+   reg 				  dst_valid, dst_valid_reg;
+   wire 			  local_dst;
+   wire [8:0] 			  read_addr;
+
+   //
+   // Monitor packets leaving FIFO
+   //
+   always @(posedge clk)
+     if (reset | clear) begin
+        state <= WAIT_SOF;
+     end else
+       case(state)
+	 //
+	 // After RESET or the EOF of previous packet, the first cycle with
+	 // output valid asserted is the SOF and presents the Header word.
+	 // The cycle following the concurrent presentation of asserted output
+	 // valid and output ready presents the word following the header.
+	 //
+         WAIT_SOF:
+           if (o_tvalid && o_tready) begin
+              state <= WAIT_EOF;
+           end else begin
+              state <= WAIT_SOF;
+           end
+	 //
+	 // EOF is signalled by o_tlast asserted whilst output valid and ready asserted.
+	 //
+         WAIT_EOF:
+           if (o_tlast && o_tvalid && o_tready) begin
+              state <= WAIT_SOF;
+           end else begin
+              state <= WAIT_EOF;
+           end
+       endcase // case(in_state)
+
+   //
+   // Extract Destination fields(s) from SID
+   //
+   always @(posedge clk)
+     if (reset | clear) begin
+	dst <= 0;
+	dst_valid <= 0;
+	dst_valid_reg <= 0;
+     end else if (o_tvalid && (state == WAIT_SOF) && pkt_present) begin
+	// SID will remain valid until o_tready is asserted as this will cause a state transition.
+	dst <= o_tdata[15:0];
+	dst_valid <= 1;
+	dst_valid_reg <= dst_valid;
+     end else begin
+	dst_valid <= 0;
+	dst_valid_reg <= dst_valid;
+     end
+
+   //
+   // Is Network field in DST our local address?
+   //
+   assign local_dst = (dst[15:8] == local_addr) && dst_valid;
+
+
+   //
+   // Mux address to RAM so that it searches CAM for Network field or Host field.
+   // Network addresses are stored in the lower 256 locations, host addresses the upper 256.
+   //
+   assign read_addr = {local_dst,(local_dst ? dst[7:0] : dst[15:8])};
+
+   //
+   // Implement CAM as block RAM here, 512xCeil(Log2(NUM_OUTPUTS))
+   //
+   //synthesis attribute ram_style of mem is block
+   reg [$clog2(NUM_OUTPUTS)-1 : 0] mem [0:511];
+
+   // Initialize the CAM's local address forwarding decisions with sensible defaults by
+   // assuming dst[7:4] = crossbar port, dst[3:0] = block port. Setup a one-to-one mapping
+   // for crossbar ports and always map same crossbar port regardless of block port.
+   // i.e.
+   //   dst 8'h00 => forward to crossbar port 0
+   //   dst 8'h01 => forward to crossbar port 0
+   //   dst 8'h10 => forward to crossbar port 1
+   // etc.
+   integer xbar_port;
+   integer block_port;
+   initial begin
+     for (xbar_port = 0; xbar_port < NUM_OUTPUTS; xbar_port = xbar_port + 1) begin
+       for (block_port = 0; block_port < 16; block_port = block_port + 1) begin
+         mem[256+(xbar_port << 4)+block_port] = xbar_port;
+       end
+     end
+   end
+
+   reg [8:0] 			   read_addr_reg;
+   wire 			   write;
+   wire [$clog2(NUM_OUTPUTS)-1:0] 	   read_data;
+
+   assign write = (set_addr[15:9] == (BASE >>9)) && set_stb; // Addr decode.
+
+   always @(posedge clk)
+     begin
+	read_addr_reg <= read_addr;
+
+	if (write) begin
+	   mem[set_addr[8:0]] <= set_data[$clog2(NUM_OUTPUTS)-1:0];
+	end
+
+     end
+
+   assign read_data = mem[read_addr_reg];
+
+
+   //
+   // State machine to manage forwarding flags.
+   //
+    always @(posedge clk)
+     if (reset | clear) begin
+        forward_valid <= {NUM_OUTPUTS{1'b0}};
+        demux_state <= IDLE;
+     end else
+       case(demux_state)
+
+	 // Wait for Valid DST which indicates a new packet lookup in the CAM.
+	 IDLE: begin
+	    if (dst_valid_reg == 1) begin
+	       forward_valid <= 1'b1 << read_data;
+	       demux_state <= FORWARD;
+	    end
+	 end
+	 // When Slave/Output thats forwarding ACK's the forward flag, clear request and wait for packet to be transfered
+	 FORWARD: begin
+	    if ((forward_ack & forward_valid) != 0) begin
+	       forward_valid <= {NUM_OUTPUTS{1'b0}};
+	       demux_state <= WAIT;
+	    end
+	 end
+	 // When packet transfered go back to idle.
+	 WAIT: begin
+	    if (forward_ack == 0)
+	      demux_state <= IDLE;
+	 end
+
+       endcase // case (demux_state)
+
+  //
+  // Compile forwarding statistics
+  // (This uses a lot of registers!)
+  //
+  genvar m;
+  reg [31:0] statistics [0:NUM_OUTPUTS-1];
+
+  generate
+    for (m = 0; m < NUM_OUTPUTS; m = m + 1) begin: generate_stats
+      always @(posedge clk) begin
+        if (reset | clear) begin
+          statistics[m] <= 0;
+        end else if (forward_ack[m] & forward_valid[m]) begin
+            statistics[m] <= statistics[m] + 1;
+        end
+      end
+    end
+  endgenerate
+
+  assign rb_data = statistics[rb_addr];
+
+endmodule
diff --git a/fpga/usrp3/lib/control/axi_setting_reg.v b/fpga/usrp3/lib/control/axi_setting_reg.v
new file mode 100644
index 000000000..9d419ec32
--- /dev/null
+++ b/fpga/usrp3/lib/control/axi_setting_reg.v
@@ -0,0 +1,97 @@
+//
+// Copyright 2016 Ettus Research
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Settings register with AXI stream output.
+//
+// Parameters / common use cases:
+// USE_ADDR_LAST & ADDR_LAST  User wants additional address that when written to asserts tlast.
+//                            Useful for the last word in a packet.
+// USE_FIFO & FIFO_SIZE       Downstream block can throttle and a FIFO is needed to handle that case.
+// STROBE_LAST                User always wants to assert tlast on writes. More efficient than USE_ADDR_LAST
+//                            since only one address is used instead of two.
+// REPEATS                    Keep tvalid asserted after initial write.
+// STROBE_LAST & REPEATS      tlast is asserted on the initial write then deasserted for repeating output. 
+// MSB_ALIGN                  Left justify data versus right justify.
+
+module axi_setting_reg #(
+  parameter ADDR = 0,
+  parameter USE_ADDR_LAST = 0,
+  parameter ADDR_LAST = ADDR+1,
+  parameter AWIDTH = 8,
+  parameter WIDTH = 32,
+  parameter USE_FIFO = 0,
+  parameter FIFO_SIZE = 5,
+  parameter DATA_AT_RESET = 0,
+  parameter VALID_AT_RESET = 0,
+  parameter LAST_AT_RESET = 0,
+  parameter STROBE_LAST = 0,
+  parameter REPEATS = 0,
+  parameter MSB_ALIGN = 0
+)
+(
+  input clk, input reset, output reg error_stb,
+  input set_stb, input [AWIDTH-1:0] set_addr, input [31:0] set_data,
+  output [WIDTH-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready
+);
+
+  reg init;
+
+  reg [WIDTH-1:0] o_tdata_int;
+  reg o_tlast_int, o_tvalid_int;
+  wire o_tready_int;
+
+  always @(posedge clk) begin
+    if (reset) begin
+      o_tdata_int <= DATA_AT_RESET;
+      o_tvalid_int <= VALID_AT_RESET;
+      o_tlast_int <= LAST_AT_RESET;
+      init <= 1'b0;
+      error_stb <= 1'b0;
+    end else begin
+      error_stb <= 1'b0;
+      if (o_tvalid_int & o_tready_int) begin
+        // Deassert tvalid / tlast only if not repeating the output
+        if (REPEATS == 0) begin
+          o_tvalid_int <= 1'b0;
+        end
+        if ((REPEATS == 0) | (STROBE_LAST == 1)) begin
+          o_tlast_int <= 1'b0;
+        end
+      end
+      if (set_stb & ((ADDR[AWIDTH-1:0] == set_addr) | (USE_ADDR_LAST & (ADDR_LAST[AWIDTH-1:0] == set_addr)))) begin
+        init <= 1'b1;
+        o_tdata_int <= (MSB_ALIGN == 0) ? set_data[WIDTH-1:0] : set_data[31:32-WIDTH];
+        o_tvalid_int <= 1'b1;
+        if (set_stb & (STROBE_LAST | (USE_ADDR_LAST & (ADDR_LAST[AWIDTH-1:0] == set_addr)))) begin
+          o_tlast_int <= 1'b1;
+        end else begin
+          o_tlast_int <= 1'b0;
+        end
+        if (~o_tready_int) begin
+          error_stb <= 1'b1;
+        end
+      end
+    end
+  end
+
+  generate
+    if (USE_FIFO) begin
+      axi_fifo #(
+        .WIDTH(WIDTH+1), .SIZE(FIFO_SIZE))
+      axi_fifo (
+        .clk(clk), .reset(reset), .clear(1'b0),
+        .i_tdata({o_tlast_int,o_tdata_int}), .i_tvalid(o_tvalid_int), .i_tready(o_tready_int),
+        .o_tdata({o_tlast,o_tdata}), .o_tvalid(o_tvalid), .o_tready(o_tready),
+        .space(), .occupied());
+    end else begin
+      assign o_tdata = o_tdata_int;
+      assign o_tlast = o_tlast_int;
+      assign o_tvalid = o_tvalid_int;
+      assign o_tready_int = o_tready;
+    end
+  endgenerate
+
+endmodule
diff --git a/fpga/usrp3/lib/control/axi_slave_mux.v b/fpga/usrp3/lib/control/axi_slave_mux.v
new file mode 100644
index 000000000..0b217dc92
--- /dev/null
+++ b/fpga/usrp3/lib/control/axi_slave_mux.v
@@ -0,0 +1,122 @@
+//
+// Copyright 2012 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+`ifndef LOG2
+`define LOG2(N) (\
+                 N < 2    ? 0 : \
+                 N < 4    ? 1 : \
+                 N < 8    ? 2 : \
+                 N < 16   ? 3 : \
+                 N < 32   ? 4 : \
+                 N < 64   ? 5 : \
+                 N < 128  ? 6 : \
+                 N < 256  ? 7 : \
+                 N < 512  ? 8 : \
+                 N < 1024 ? 9 : 10)
+`endif
+
+module axi_slave_mux
+  #(
+    parameter FIFO_WIDTH = 64, // AXI4-STREAM data bus width
+    parameter DST_WIDTH = 16,  // Width of DST field we are routing on.
+    parameter NUM_INPUTS = 2   // number of input AXI buses
+    )
+    (
+     input 				 clk,
+     input 				 reset,
+     input 				 clear,
+     // Inputs
+     input [(FIFO_WIDTH*NUM_INPUTS)-1:0] i_tdata,
+     input [NUM_INPUTS-1:0] 		 i_tvalid,
+     input [NUM_INPUTS-1:0] 		 i_tlast,
+     output [NUM_INPUTS-1:0] 		 i_tready,
+     // Forwarding Flags
+     input [NUM_INPUTS-1:0] 		 forward_valid,
+     output reg [NUM_INPUTS-1:0] 	 forward_ack,
+     // Output
+     output [FIFO_WIDTH-1:0] 		 o_tdata,
+     output 				 o_tvalid,
+     output 				 o_tlast,
+     input 				 o_tready
+     );
+
+   wire [FIFO_WIDTH-1:0] i_tdata_array [0:NUM_INPUTS-1];
+   
+   reg [`LOG2(NUM_INPUTS):0] select;
+   reg 			     enable;
+
+
+   reg 			     state;
+
+   localparam CHECK_THIS_INPUT = 0;
+   localparam WAIT_LAST = 1;
+   
+
+   always @(posedge clk)
+     if (reset | clear) begin
+	state <= CHECK_THIS_INPUT;
+	select <= 0;
+	enable <= 0;
+	forward_ack <= 0;	
+     end else begin
+	case(state)
+	  // Is the currently selected input addressing this slave with a ready packet?
+	  CHECK_THIS_INPUT:  begin
+	     if (forward_valid[select]) begin
+		enable <= 1;
+		forward_ack[select] <= 1;
+		state <= WAIT_LAST;
+	     end else if (select == NUM_INPUTS - 1 ) begin
+		select <= 0;
+	     end else begin
+		select <= select + 1;
+	     end
+	  end
+	  // Assert ACK immediately to forwarding logic and then wait for end of packet.
+	  WAIT_LAST: begin
+	    
+	     if (i_tlast[select] && i_tvalid[select] && o_tready) begin
+		if (select == NUM_INPUTS - 1 ) begin
+		   select <= 0;
+		end else begin
+		   select <= select + 1;
+		end
+		state <= CHECK_THIS_INPUT;
+		forward_ack <= 0;
+		enable <= 0;
+	     end else begin
+		forward_ack[select] <= 1;
+		enable <= 1;
+	     end
+	  end
+	endcase // case(state)
+     end
+	
+   //
+   // Combinatorial mux
+   //
+   genvar m;
+     
+   generate
+      for (m = 0; m < NUM_INPUTS; m = m + 1) begin: form_buses
+	 assign i_tdata_array[m] = i_tdata[(m*FIFO_WIDTH)+FIFO_WIDTH-1:m*FIFO_WIDTH];
+      end
+   endgenerate
+
+   assign 	o_tdata = i_tdata_array[select];
+   assign 	o_tvalid = enable && i_tvalid[select];
+   assign 	o_tlast = enable && i_tlast[select];
+ //  assign 	i_tready = {NUM_INPUTS{o_tready}} & (enable << select);
+
+   generate
+      for (m = 0; m < NUM_INPUTS; m = m + 1) begin: form_ready
+	 assign i_tready[m] = o_tready && enable && (select == m);
+      end
+   endgenerate
+
+    
+endmodule // axi_slave_mux
diff --git a/fpga/usrp3/lib/control/axi_test_vfifo.v b/fpga/usrp3/lib/control/axi_test_vfifo.v
new file mode 100644
index 000000000..1d37bfd1b
--- /dev/null
+++ b/fpga/usrp3/lib/control/axi_test_vfifo.v
@@ -0,0 +1,145 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+//
+// Test Virtual FIFO's by streaming modulo 2^32 counter (replicated in upper
+// and lower 32bits). Test result by tracking count on receive and using 
+// sticky flag for error indication.
+// Also provide signal from MSB of 32bit count to blink LED.
+//
+
+module axi_test_vfifo
+  #(parameter PACKET_SIZE = 128)
+   (
+    input aclk,
+    input aresetn,
+    input enable,
+    // AXI Stream Out
+    output reg out_axis_tvalid,
+    input out_axis_tready,
+    output [63 : 0] out_axis_tdata,
+    output reg [7 : 0] out_axis_tstrb,
+    output reg [7 : 0] out_axis_tkeep,
+    output reg out_axis_tlast,
+    output reg [0 : 0] out_axis_tid,
+    output reg [0 : 0] out_axis_tdest,
+    input vfifo_full,
+    // AXI Stream In
+    input in_axis_tvalid,
+    output reg in_axis_tready,
+    input [63 : 0] in_axis_tdata,
+    input [7 : 0] in_axis_tstrb,
+    input [7 : 0] in_axis_tkeep,
+    input in_axis_tlast,
+    input [0 : 0] in_axis_tid,
+    input [0 : 0] in_axis_tdest,
+    // Flags
+    output reg flag_error,
+    output heartbeat_in,
+    output heartbeat_out,
+    output [31:0] expected_count
+    );
+   
+
+   reg [31:0] 	  out_count;
+   reg [31:0] 	  in_count;
+   reg [63:0] 	  in_axis_tdata_reg;
+   reg 		  in_data_valid;
+   
+
+
+   //
+   // Output 
+   //
+   always @(posedge aclk)
+     if (!aresetn) begin
+	out_count <= 0;
+	out_axis_tvalid <= 0;
+	out_axis_tid <= 0; // Don't care.
+	out_axis_tdest <= 0; // Only use port 0 of VFIFO.
+	out_axis_tstrb <= 0;  // Unused in VFIFO
+	out_axis_tkeep <= 8'hFF; // Always use every byte of data
+	out_axis_tlast <= 1'b0;
+     end else if (enable) begin
+	if (~vfifo_full) begin
+	   // Always ready to output new count value.
+	   out_axis_tvalid <= 1;
+	   if (out_axis_tready) 
+	     out_count <= out_count + 1;
+	   // Assert TLAST every PACKET_SIZE beats.
+	   if (out_count[15:0] == PACKET_SIZE)
+	     out_axis_tlast <= 1'b1;
+	   else
+	     out_axis_tlast <= 1'b0;
+	end else begin
+	   out_axis_tvalid <= 0;
+	end
+     end else begin
+	out_axis_tlast <= 1'b0;	
+	out_axis_tvalid <= 0;
+     end
+
+   assign out_axis_tdata = {out_count,out_count};
+
+   assign heartbeat_out = out_count[28];
+   
+
+   //
+   // Input (Ignore TLAST signal)
+   //
+   always @(posedge aclk)
+     if (!aresetn) begin
+	in_axis_tready <= 0;
+	in_axis_tdata_reg <= 0;
+	in_data_valid <= 0;
+	
+     end else if (enable) begin
+	in_axis_tready <= 1;
+	in_axis_tdata_reg <= in_axis_tdata;
+	if (in_axis_tvalid) 
+	  in_data_valid <= 1;
+	else
+	  in_data_valid <= 0;
+     end else begin
+	in_data_valid <= 0;
+	in_axis_tready <= 0;
+     end // else: !if(enable)
+   
+   	  
+   assign heartbeat_in = in_count[28];
+   
+   //
+   // Input Checker
+   //
+   always @(posedge aclk)
+     if (!aresetn) begin
+	in_count <= 0;
+	flag_error <= 0;
+     end else if (enable) begin
+	if (in_data_valid) begin
+	   
+	   if ((in_axis_tdata_reg[63:32] != in_count) || (in_axis_tdata_reg[31:0] != in_count))
+	     begin
+		flag_error <= 1;
+		in_count <= in_axis_tdata_reg[63:32] + 1;
+	     end
+	   else
+	     begin
+		flag_error <= 0;
+		in_count <= in_count + 1;
+	     end
+	   
+	end
+     end
+
+   assign expected_count = in_count;
+   
+
+endmodule // axi_test_vfifo
+
+
+   
+   
diff --git a/fpga/usrp3/lib/control/axil_ctrlport_master.v b/fpga/usrp3/lib/control/axil_ctrlport_master.v
new file mode 100644
index 000000000..b1b5a7d2c
--- /dev/null
+++ b/fpga/usrp3/lib/control/axil_ctrlport_master.v
@@ -0,0 +1,248 @@
+//
+// Copyright 2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: axil_ctrlport_master
+// Description:
+// An AXI4-Lite read/write control port adapter
+//
+// Converts AXI4-Lite transactions into control port requests.
+// Converts all AXI requests to control port by only forwarding the
+// CTRLPORT_AWIDTH LSBs of the address.
+//
+// Limitation:
+// The control port interface will only use address, data, byte enable and
+// wr/rd flags. All other signals are tied to 0.
+
+
+module axil_ctrlport_master #(
+  parameter TIMEOUT         = 10, // log2(timeout). Control port will timeout after 2^TIMEOUT AXI clock cycles
+  parameter AXI_AWIDTH      = 17, // Width of the AXI bus. Aliasing occurs of AXI_AWIDTH > CTRLPORT_AWIDTH
+  parameter CTRLPORT_AWIDTH = 17  // Number of address LSBs forwarded to m_ctrlport_req_addr
+)(
+  //Clock and reset
+  input  wire                  s_axi_aclk,
+  input  wire                  s_axi_aresetn,
+  // AXI4-Lite: Write address port (domain: s_axi_aclk)
+  input  wire [AXI_AWIDTH-1:0] s_axi_awaddr,
+  input  wire                  s_axi_awvalid,
+  output reg                   s_axi_awready,
+  // AXI4-Lite: Write data port (domain: s_axi_aclk)
+  input  wire [31:0]           s_axi_wdata,
+  input  wire [ 3:0]           s_axi_wstrb,
+  input  wire                  s_axi_wvalid,
+  output reg                   s_axi_wready,
+  // AXI4-Lite: Write response port (domain: s_axi_aclk)
+  output reg  [ 1:0]           s_axi_bresp = 0,
+  output reg                   s_axi_bvalid,
+  input  wire                  s_axi_bready,
+  // AXI4-Lite: Read address port (domain: s_axi_aclk)
+  input  wire [AXI_AWIDTH-1:0] s_axi_araddr,
+  input  wire                  s_axi_arvalid,
+  output reg                   s_axi_arready,
+  // AXI4-Lite: Read data port (domain: s_axi_aclk)
+  output reg [31:0]            s_axi_rdata = 0,
+  output reg [ 1:0]            s_axi_rresp = 0,
+  output reg                   s_axi_rvalid,
+  input  wire                  s_axi_rready,
+  // Control port master request interface
+  output reg                   m_ctrlport_req_wr,
+  output reg                   m_ctrlport_req_rd,
+  output reg  [19:0]           m_ctrlport_req_addr = 0,
+  output wire [ 9:0]           m_ctrlport_req_portid,
+  output wire [15:0]           m_ctrlport_req_rem_epid,
+  output wire [ 9:0]           m_ctrlport_req_rem_portid,
+  output reg  [31:0]           m_ctrlport_req_data = 0,
+  output reg  [ 3:0]           m_ctrlport_req_byte_en = 0,
+  output wire                  m_ctrlport_req_has_time,
+  output wire [63:0]           m_ctrlport_req_time,
+  // Control port master response interface
+  input  wire                  m_ctrlport_resp_ack,
+  input  wire [ 1:0]           m_ctrlport_resp_status,
+  input  wire [31:0]           m_ctrlport_resp_data
+);
+
+  `include "../axi/axi_defs.v"
+  `include "../rfnoc/core/ctrlport.vh"
+
+  //----------------------------------------------------------
+  // unused ctrlport outputs
+  //----------------------------------------------------------
+  assign m_ctrlport_req_portid = 10'b0;
+  assign m_ctrlport_req_rem_epid = 16'b0;
+  assign m_ctrlport_req_rem_portid = 10'b0;
+  assign m_ctrlport_req_has_time = 1'b0;
+  assign m_ctrlport_req_time = 64'b0;
+
+  //----------------------------------------------------------
+  // Address calculation
+  //----------------------------------------------------------
+  // define configuration for the address calculation
+  localparam [CTRLPORT_ADDR_W-1:0] ADDRESS_MASK = {CTRLPORT_ADDR_W {1'b0}} | {CTRLPORT_AWIDTH {1'b1}};
+
+  // bits to extract from AXI address
+  localparam AXI_ADDR_BITS_TO_FORWARD = (AXI_AWIDTH < CTRLPORT_ADDR_W) ? AXI_AWIDTH : CTRLPORT_ADDR_W;
+
+  //----------------------------------------------------------
+  // State machine for read and write
+  //----------------------------------------------------------
+  localparam IDLE              = 4'd0;
+  localparam READ_INIT         = 4'd1;
+  localparam WRITE_INIT        = 4'd2;
+  localparam READ_TRANSFER     = 4'd3;
+  localparam WRITE_TRANSFER    = 4'd4;
+  localparam READ_IN_PROGRESS  = 4'd5;
+  localparam WRITE_IN_PROGRESS = 4'd6;
+  localparam WRITE_DONE        = 4'd7;
+  localparam READ_DONE         = 4'd8;
+
+  reg [3:0] state;
+  reg [TIMEOUT-1:0] timeout_counter;
+
+  always @ (posedge s_axi_aclk) begin
+    if (~s_axi_aresetn) begin
+      state <= IDLE;
+
+      // clear AXI feedback paths and controlport requests
+      s_axi_awready <= 1'b0;
+      s_axi_wready  <= 1'b0;
+      s_axi_bvalid  <= 1'b0;
+      s_axi_arready <= 1'b0;
+      s_axi_rvalid  <= 1'b0;
+      m_ctrlport_req_rd <= 1'b0;
+      m_ctrlport_req_wr <= 1'b0;
+    end else begin
+      case (state)
+        // decide whether a read or write should be handled
+        IDLE: begin
+          timeout_counter <= {TIMEOUT {1'b1}};
+
+          if (s_axi_arvalid) begin
+            state <= READ_INIT;
+          end
+          else if (s_axi_awvalid) begin
+            state <= WRITE_INIT;
+          end
+        end
+
+        // wait for FIFO to get read to assign valid
+        READ_INIT: begin
+          // signal ready to upstream module
+          s_axi_arready <= 1'b1;
+
+          state <= READ_TRANSFER;
+        end
+
+        // transfer data to FIFO
+        READ_TRANSFER: begin
+          // clear ready flag from READ_INIT state
+          s_axi_arready <= 1'b0;
+          // transfer data to controlport
+          m_ctrlport_req_rd <= 1'b1;
+          m_ctrlport_req_addr <= s_axi_araddr[AXI_ADDR_BITS_TO_FORWARD-1:0] & ADDRESS_MASK;
+          m_ctrlport_req_byte_en <= 4'b1111;
+
+          state <= READ_IN_PROGRESS;
+        end
+
+        // wait for controlport response is available
+        READ_IN_PROGRESS: begin
+          // clear read flag from previous state
+          m_ctrlport_req_rd <= 1'b0;
+
+          //decrement timeout
+          timeout_counter <= timeout_counter - 1;
+
+          if (m_ctrlport_resp_ack == 1'b1 || timeout_counter == 0) begin
+            s_axi_rvalid <= 1'b1;
+            s_axi_rdata <= m_ctrlport_resp_data;
+            s_axi_rresp <= `AXI4_RESP_OKAY;
+
+            // use AXI DECERR to inform about failed transaction
+            if (timeout_counter == 0) begin
+              s_axi_rresp <= `AXI4_RESP_DECERR;
+            end else begin
+              // if controlport response is not OKAY use AXI SLVERR to propagate error
+              if (m_ctrlport_resp_status != CTRL_STS_OKAY) begin
+                s_axi_rresp <= `AXI4_RESP_SLVERR;
+              end
+            end
+
+            state <= READ_DONE;
+          end
+        end
+
+        // wait until read response is transferred
+        READ_DONE: begin
+          if (s_axi_rready) begin
+            s_axi_rvalid <= 1'b0;
+            state <= IDLE;
+          end
+        end
+
+        //wait for FIFO and data to process
+        WRITE_INIT: begin
+          if (s_axi_wvalid) begin
+            s_axi_awready <= 1'b1;
+            s_axi_wready <= 1'b1;
+            state <= WRITE_TRANSFER;
+          end
+        end
+
+        // transfer data to FIFO
+        WRITE_TRANSFER: begin
+          // clear ready flags from READ_INIT state
+          s_axi_awready <= 1'b0;
+          s_axi_wready <= 1'b0;
+          // transfer data to controlport
+          m_ctrlport_req_wr <= 1'b1;
+          m_ctrlport_req_addr <= s_axi_awaddr[AXI_ADDR_BITS_TO_FORWARD-1:0] & ADDRESS_MASK;
+          m_ctrlport_req_data <= s_axi_wdata;
+          m_ctrlport_req_byte_en <= s_axi_wstrb;
+
+          state <= WRITE_IN_PROGRESS;
+        end
+
+        // wait for write to complete
+        WRITE_IN_PROGRESS: begin
+          // clear write flag from previous state
+          m_ctrlport_req_wr <= 1'b0;
+
+          //decrement timeout
+          timeout_counter <= timeout_counter - 1;
+
+          if (m_ctrlport_resp_ack == 1'b1 || timeout_counter == 0) begin
+            s_axi_bvalid <= 1'b1;
+            s_axi_rdata <= 32'b0;
+            s_axi_bresp <= `AXI4_RESP_OKAY;
+
+            // use AXI DECERR to inform about failed transaction
+            if (timeout_counter == 0) begin
+              s_axi_bresp <= `AXI4_RESP_DECERR;
+            end else begin
+              // if controlport response is not OKAY use AXI SLVERR to propagate error
+              if (m_ctrlport_resp_status != CTRL_STS_OKAY) begin
+                s_axi_bresp <= `AXI4_RESP_SLVERR;
+              end
+            end
+
+            state <= WRITE_DONE;
+          end
+        end
+
+        WRITE_DONE: begin
+          if (s_axi_bready) begin
+            state <= IDLE;
+            s_axi_bvalid <= 1'b0;
+          end
+        end
+
+        default: begin
+          state <= IDLE;
+        end
+      endcase
+    end
+  end
+
+endmodule
diff --git a/fpga/usrp3/lib/control/axil_regport_master.v b/fpga/usrp3/lib/control/axil_regport_master.v
new file mode 100644
index 000000000..de23e7697
--- /dev/null
+++ b/fpga/usrp3/lib/control/axil_regport_master.v
@@ -0,0 +1,228 @@
+//
+// Copyright 2016-2017 Ettus Research
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+// An AXI4-Lite read/write register port adapter
+//
+// Converts memory mapped flow controlled AXI4-Lite transactions into a much
+// simpler non flow controlled write and read register bus.
+//
+// WRITE Transaction:
+// - Transaction completes in one cycle
+// - Valid, Strobe, Address and Data asserted in same cycle
+//                      __    __    __    __
+//   clk             __|  |__|  |__|  |__|  |__
+//                            _____
+//   reg_wr_req      ________|     |___________
+//                            _____
+//   reg_wr_keep     XXXXXXXX|_____|XXXXXXXXXXX
+//                            _____
+//   reg_wr_addr     XXXXXXXX|_____|XXXXXXXXXXX
+//                            _____
+//   reg_wr_data     XXXXXXXX|_____|XXXXXXXXXXX
+//;
+// READ Transaction:
+// - Transaction request completes in one cycle, with valid and address assertion
+// - Transaction response must complete in at least one cycle with resp and data
+//   - resp must be asserted between 1 and pow(2, TIMEOUT) cycles otherwise the read will timeout
+//                      __    __    __    __    __
+//   clk             __|  |__|  |__|  |__|  |__|  |__
+//                            _____
+//   reg_rd_req      ________|     |_________________
+//                            _____
+//   reg_rd_addr     XXXXXXXX|_____|XXXXXXXXXXXXXXXXX
+//                                        _____
+//   reg_rd_resp     ____________________|     |_____
+//                                        _____
+//   reg_rd_data     XXXXXXXXXXXXXXXXXXXX|_____|XXXXX
+
+
+module axil_regport_master #(
+  parameter DWIDTH  = 32,    // Width of the AXI4-Lite data bus (must be 32 or 64)
+  parameter AWIDTH  = 32,    // Width of the address bus
+  parameter WRBASE  = 32'h0, // Write address base
+  parameter RDBASE  = 32'h0, // Read address base
+  parameter TIMEOUT = 10     // log2(timeout). Read will timeout after (2^TIMEOUT - 1) cycles
+)(
+  // Clock and reset
+  input                      s_axi_aclk,
+  input                      s_axi_aresetn,
+  input                      reg_clk,
+  // AXI4-Lite: Write address port (domain: s_axi_aclk)
+  input      [AWIDTH-1:0]    s_axi_awaddr,
+  input                      s_axi_awvalid,
+  output reg                 s_axi_awready,
+  // AXI4-Lite: Write data port (domain: s_axi_aclk)
+  input      [DWIDTH-1:0]    s_axi_wdata,
+  input      [DWIDTH/8-1:0]  s_axi_wstrb,
+  input                      s_axi_wvalid,
+  output reg                 s_axi_wready,
+  // AXI4-Lite: Write response port (domain: s_axi_aclk)
+  output reg [1:0]           s_axi_bresp,
+  output reg                 s_axi_bvalid,
+  input                      s_axi_bready,
+  // AXI4-Lite: Read address port (domain: s_axi_aclk)
+  input      [AWIDTH-1:0]    s_axi_araddr,
+  input                      s_axi_arvalid,
+  output reg                 s_axi_arready,
+  // AXI4-Lite: Read data port (domain: s_axi_aclk)
+  output reg [DWIDTH-1:0]    s_axi_rdata,
+  output reg [1:0]           s_axi_rresp,
+  output reg                 s_axi_rvalid,
+  input                      s_axi_rready,
+  // Register port: Write port (domain: reg_clk)
+  output                     reg_wr_req,
+  output     [AWIDTH-1:0]    reg_wr_addr,
+  output     [DWIDTH-1:0]    reg_wr_data,
+  output     [DWIDTH/8-1:0]  reg_wr_keep,
+  // Register port: Read port (domain: reg_clk)
+  output                     reg_rd_req,
+  output     [AWIDTH-1:0]    reg_rd_addr,
+  input                      reg_rd_resp,
+  input      [DWIDTH-1:0]    reg_rd_data
+);
+
+  //NOTE: clog2 only works when assigned to a parameter
+  //      localparam does not work
+  parameter ADDR_LSB = $clog2(DWIDTH/8); //Do not modify
+
+  //----------------------------------------------------------
+  // Write state machine
+  //----------------------------------------------------------
+  reg [AWIDTH-1:0]  wr_addr_cache;
+  wire              wr_fifo_valid, wr_fifo_ready;
+  wire [AWIDTH-1:0] wr_addr_rel = (s_axi_awaddr - WRBASE);
+
+  // Generate s_axi_awready and latch write address
+  always @(posedge s_axi_aclk) begin
+     if (!s_axi_aresetn) begin
+        s_axi_awready <= 1'b0;
+        wr_addr_cache <= {AWIDTH{1'b0}};
+     end else begin
+        if (~s_axi_awready && s_axi_awvalid && s_axi_wvalid && wr_fifo_ready) begin
+           s_axi_awready <= 1'b1;
+           wr_addr_cache <= {wr_addr_rel[AWIDTH-1:ADDR_LSB], {ADDR_LSB{1'b0}}};
+        end else begin
+           s_axi_awready <= 1'b0;
+        end
+     end
+  end
+
+  // Generate s_axi_wready
+  always @(posedge s_axi_aclk) begin
+     if (!s_axi_aresetn) begin
+        s_axi_wready <= 1'b0;
+     end else begin
+        if (~s_axi_wready && s_axi_wvalid && s_axi_awvalid)
+           s_axi_wready <= 1'b1;
+        else
+           s_axi_wready <= 1'b0;
+     end
+  end
+
+  // Generate write response
+  assign wr_fifo_valid = s_axi_awready && s_axi_awvalid && s_axi_wready && s_axi_wvalid && ~s_axi_bvalid;
+
+  always @(posedge s_axi_aclk) begin
+     if (!s_axi_aresetn) begin
+        s_axi_bvalid <= 1'b0;
+        s_axi_bresp <= 2'b0;
+     end else begin
+        if (wr_fifo_valid && wr_fifo_ready) begin
+            // indicates a valid write response is available
+           s_axi_bvalid <= 1'b1;
+           s_axi_bresp <= 2'b0; // 'OKAY' response
+        end else begin
+           if (s_axi_bready && s_axi_bvalid)
+              s_axi_bvalid <= 1'b0;
+        end
+     end
+  end
+
+   axi_fifo_2clk #( .WIDTH(DWIDTH/8 + AWIDTH + DWIDTH), .SIZE(0) ) wr_fifo_2clk_i (
+      .reset(~s_axi_aresetn), .i_aclk(s_axi_aclk),
+      .i_tdata({s_axi_wstrb, wr_addr_cache, s_axi_wdata}),
+      .i_tvalid(wr_fifo_valid), .i_tready(wr_fifo_ready),
+      .o_aclk(reg_clk),
+      .o_tdata({reg_wr_keep, reg_wr_addr, reg_wr_data}),
+      .o_tvalid(reg_wr_req), .o_tready(1'b1)
+   );
+
+   //----------------------------------------------------------
+   // Read state machine
+   //----------------------------------------------------------
+   reg [TIMEOUT-1:0] read_pending_ctr = {TIMEOUT{1'b0}};
+   wire              read_timed_out = (read_pending_ctr == {{(TIMEOUT-1){1'b0}}, 1'b1});
+   wire              read_pending = (read_pending_ctr != {TIMEOUT{1'b0}});
+   wire [AWIDTH-1:0] rd_addr_rel = (s_axi_araddr - RDBASE);
+
+   wire              rdreq_fifo_ready, rdresp_fifo_valid;
+   wire [DWIDTH-1:0] rdresp_fifo_data;
+
+   // Generate s_axi_arready and latch read address
+   always @(posedge s_axi_aclk) begin
+      if (!s_axi_aresetn) begin
+         s_axi_arready <= 1'b0;
+         read_pending_ctr <= {TIMEOUT{1'b0}};
+      end else begin
+         if (~s_axi_arready && s_axi_arvalid && rdreq_fifo_ready) begin
+            s_axi_arready <= 1'b1;
+            read_pending_ctr <= {TIMEOUT{1'b1}};
+         end else begin
+            s_axi_arready <= 1'b0;
+         end
+         if (read_pending) begin
+            if (rdresp_fifo_valid && ~s_axi_rvalid)
+               read_pending_ctr <= {TIMEOUT{1'b0}};
+            else
+               read_pending_ctr <= read_pending_ctr - 1'b1;
+         end
+      end
+   end
+
+   // Perform read transaction
+   always @(posedge s_axi_aclk) begin
+      if (!s_axi_aresetn) begin
+         s_axi_rvalid <= 1'b0;
+         s_axi_rresp <= 2'b00;
+         s_axi_rdata <= 0;
+      end else begin
+         if (read_pending && rdresp_fifo_valid && ~s_axi_rvalid) begin
+            // Valid read data is available at the read data bus
+            s_axi_rvalid <= 1'b1;
+            s_axi_rresp <= 2'b00; // 'OKAY' response
+            s_axi_rdata <= rdresp_fifo_data;
+         end else if (read_pending && read_timed_out && ~s_axi_rvalid) begin
+            // Read timed out. Assert error.
+            s_axi_rvalid <= 1'b1;
+            s_axi_rresp <= 2'b10; // 'SLVERR' response
+            s_axi_rdata <= {DWIDTH{1'b1}};
+         end else if (s_axi_rvalid && s_axi_rready) begin
+             // Read data is accepted by the master
+            s_axi_rvalid <= 1'b0;
+         end
+      end
+   end
+
+   axi_fifo_2clk #( .WIDTH(AWIDTH), .SIZE(0) ) readreq_fifo_2clk_i (
+      .reset(~s_axi_aresetn), .i_aclk(s_axi_aclk),
+      .i_tdata({rd_addr_rel[AWIDTH-1:ADDR_LSB], {ADDR_LSB{1'b0}}}),
+      .i_tvalid(s_axi_arready && s_axi_arvalid), .i_tready(rdreq_fifo_ready),
+      .o_aclk(reg_clk),
+      .o_tdata(reg_rd_addr),
+      .o_tvalid(reg_rd_req), .o_tready(1'b1)
+   );
+
+   axi_fifo_2clk #( .WIDTH(DWIDTH), .SIZE(0) ) rdresp_fifo_2clk_i (
+      .reset(~s_axi_aresetn), .i_aclk(reg_clk),
+      .i_tdata(reg_rd_data),
+      .i_tvalid(reg_rd_resp), .i_tready(/* lossy */),
+      .o_aclk(s_axi_aclk),
+      .o_tdata(rdresp_fifo_data),
+      .o_tvalid(rdresp_fifo_valid), .o_tready(~read_pending || (s_axi_rvalid && (s_axi_rresp == 2'b00)))
+   );
+
+endmodule
diff --git a/fpga/usrp3/lib/control/axil_to_ni_regport.v b/fpga/usrp3/lib/control/axil_to_ni_regport.v
new file mode 100644
index 000000000..876991ed9
--- /dev/null
+++ b/fpga/usrp3/lib/control/axil_to_ni_regport.v
@@ -0,0 +1,164 @@
+//
+// Copyright 2016 Ettus Research
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// AXI4lite to NI Register Port interface
+//
+
+module axil_to_ni_regport #(
+  parameter RP_AWIDTH = 16,
+  parameter RP_DWIDTH = 32,
+  parameter TIMEOUT   = 512
+)(
+  input                  s_axi_aclk,
+  input                  s_axi_areset,
+
+  // AXI4lite interface
+  input [31:0]           s_axi_awaddr,
+  input                  s_axi_awvalid,
+  output                 s_axi_awready,
+  input [31:0]           s_axi_wdata,
+  input [3:0]            s_axi_wstrb,
+  input                  s_axi_wvalid,
+  output                 s_axi_wready,
+  output [1:0]           s_axi_bresp,
+  output                 s_axi_bvalid,
+  input                  s_axi_bready,
+  input [31:0]           s_axi_araddr,
+  input                  s_axi_arvalid,
+  output                 s_axi_arready,
+  output [31:0]          s_axi_rdata,
+  output [1:0]           s_axi_rresp,
+  output                 s_axi_rvalid,
+  input                  s_axi_rready,
+
+  // RegPort interface, the out vs in
+  // is seen from the slave device
+  // hooked up to the regport
+  output                 reg_port_in_rd,
+  output                 reg_port_in_wt,
+  output [RP_AWIDTH-1:0] reg_port_in_addr,
+  output [RP_DWIDTH-1:0] reg_port_in_data,
+  input  [RP_DWIDTH-1:0] reg_port_out_data,
+  input                  reg_port_out_ready
+);
+
+  localparam IDLE              = 3'd0;
+  localparam READ_INIT         = 3'd1;
+  localparam WRITE_INIT        = 3'd2;
+  localparam READ_IN_PROGRESS  = 3'd3;
+  localparam WRITE_IN_PROGRESS = 3'd4;
+  localparam WRITE_DONE        = 3'd5;
+  localparam READ_DONE         = 3'd6;
+
+  reg [RP_AWIDTH-1:0] addr;
+  reg [RP_DWIDTH-1:0] rb_data;
+  reg [RP_DWIDTH-1:0] wr_data;
+  reg [2:0] state;
+  reg [9:0] count;
+  reg [1:0] rresp;
+  reg [1:0] bresp;
+
+  always @ (posedge s_axi_aclk) begin
+    if (s_axi_areset) begin
+      state   <= IDLE;
+      addr    <= 'd0;
+      rb_data <= 'd0;
+      wr_data <= 'd0;
+
+      count    <= 10'd0;
+      rresp    <= 2'd0;
+      bresp    <= 2'd0;
+    end
+    else case (state)
+
+    IDLE: begin
+      if (s_axi_arvalid) begin
+        state <= READ_INIT;
+        addr  <= s_axi_araddr[RP_AWIDTH-1:0];
+      end
+      else if (s_axi_awvalid) begin
+        state <= WRITE_INIT;
+        addr  <= s_axi_awaddr[RP_AWIDTH-1:0];
+      end
+    end
+
+    READ_INIT: begin
+      state <= READ_IN_PROGRESS;
+      count <= 10'd0;
+      rresp <= 2'b00;
+    end
+
+    READ_IN_PROGRESS: begin
+      if (reg_port_out_ready) begin
+        rb_data <= reg_port_out_data;
+        state   <= READ_DONE;
+      end
+      else if (count >= TIMEOUT) begin
+        state   <= READ_DONE;
+        rresp   <= 2'b10;
+      end
+      else begin
+        count   <= count + 1'b1;
+      end
+    end
+
+    READ_DONE: begin
+      if (s_axi_rready) begin
+        state <= IDLE;
+      end
+    end
+
+    WRITE_INIT: begin
+      if (s_axi_wvalid) begin
+        wr_data <= s_axi_wdata[RP_DWIDTH-1:0];
+        state   <= WRITE_IN_PROGRESS;
+        count <= 10'd0;
+        bresp <= 2'b00;
+      end
+    end
+
+    WRITE_IN_PROGRESS: begin
+      if (reg_port_out_ready) begin
+        state <= WRITE_DONE;
+      end
+      else if (count >= TIMEOUT) begin
+        state   <= READ_DONE;
+        bresp   <= 2'b10;
+      end
+      else begin
+        count   <= count + 1'b1;
+      end
+    end
+
+    WRITE_DONE: begin
+      if (s_axi_bready)
+        state <= IDLE;
+    end
+
+    default: begin
+      state <= IDLE;
+    end
+
+    endcase
+  end
+
+  assign s_axi_awready = (state == IDLE);
+  assign s_axi_wready  = (state == WRITE_INIT);
+  assign s_axi_bvalid  = (state == WRITE_DONE);
+  assign s_axi_bresp   = bresp;
+
+  assign s_axi_arready = (state == IDLE);
+  assign s_axi_rdata   = rb_data;
+  assign s_axi_rvalid  = (state == READ_DONE);
+  assign s_axi_rresp   = rresp;
+
+  assign reg_port_in_wt   = (state == WRITE_INIT) & s_axi_wvalid;
+  assign reg_port_in_data = (state == WRITE_INIT) ? s_axi_wdata : wr_data;
+  assign reg_port_in_addr = addr;
+
+  assign reg_port_in_rd   = (state == READ_INIT);
+
+endmodule
diff --git a/fpga/usrp3/lib/control/bin2gray.v b/fpga/usrp3/lib/control/bin2gray.v
new file mode 100644
index 000000000..bd68cdb80
--- /dev/null
+++ b/fpga/usrp3/lib/control/bin2gray.v
@@ -0,0 +1,30 @@
+//
+// Copyright 2011 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+
+
+module bin2gray
+  #(parameter WIDTH=8)
+    (input [WIDTH-1:0] bin,
+     output [WIDTH-1:0] gray);
+
+   assign 		gray = (bin >> 1) ^ bin;
+   
+endmodule // bin2gray
diff --git a/fpga/usrp3/lib/control/binary_encoder.v b/fpga/usrp3/lib/control/binary_encoder.v
new file mode 100644
index 000000000..6262b3df0
--- /dev/null
+++ b/fpga/usrp3/lib/control/binary_encoder.v
@@ -0,0 +1,45 @@
+//
+// Copyright 2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+`define log2(N) ( N < 2    ? 0 : \
+                  N < 4    ? 1 : \
+                  N < 8    ? 2 : \
+                  N < 16   ? 3 : \
+                  N < 32   ? 4 : \
+                  N < 64   ? 5 : \
+                  N < 128  ? 6 : \
+                  N < 256  ? 7 : \
+                  N < 512  ? 8 : \
+                  N < 1024 ? 9 : \
+                             10 \
+                )
+
+module binary_encoder
+#(
+      parameter SIZE = 16
+)
+(
+       input [SIZE-1:0] in,
+       output [`log2(SIZE)-1:0] out
+);
+
+  genvar m,n;
+
+  generate
+  // Loop enough times to represent the total number of input bits as an encoded value
+  for (m = 0; m <= `log2(SIZE-1); m = m + 1)  begin: expand_or_tree
+    wire [SIZE-1:0] encoding;
+     // Build enable mask by iterating through every input bit.
+     for (n = 0; n < SIZE ; n = n + 1) begin: encode_this_bit
+       assign encoding[n] = n[m];
+     end
+     // OR tree for this output bit with appropriate bits enabled.
+     assign out[m] = |(encoding & in);
+   end
+ endgenerate
+
+endmodule // binary_encoder
diff --git a/fpga/usrp3/lib/control/db_control.v b/fpga/usrp3/lib/control/db_control.v
new file mode 100644
index 000000000..757657a22
--- /dev/null
+++ b/fpga/usrp3/lib/control/db_control.v
@@ -0,0 +1,148 @@
+//
+// Copyright 2016 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module db_control #(
+  // Drive SPI core with input spi_clk instead of ce_clk. This is useful if ce_clk is very slow which
+  // would cause spi transactions to take a long time. WARNING: This adds a clock crossing FIFO!
+  parameter USE_SPI_CLK = 0,
+  parameter SR_BASE     = 160,
+  parameter RB_BASE     = 16,
+  parameter NUM_SPI_SEN = 8
+)(
+  // Commands from Radio Core
+  input clk, input reset,
+  input set_stb, input [7:0] set_addr, input [31:0] set_data,
+  output reg rb_stb, input [7:0] rb_addr, output reg [63:0] rb_data,
+  input run_rx, input run_tx,
+  // Frontend / Daughterboard I/O
+  input [31:0] misc_ins, output [31:0] misc_outs,
+  input [31:0] fp_gpio_in, output [31:0] fp_gpio_out, output [31:0] fp_gpio_ddr, input [31:0] fp_gpio_fab,
+  input [31:0] db_gpio_in, output [31:0] db_gpio_out, output [31:0] db_gpio_ddr, input [31:0] db_gpio_fab,
+  output [31:0] leds,
+  input spi_clk, input spi_rst, output [NUM_SPI_SEN-1:0] sen, output sclk, output mosi, input miso
+);
+
+  localparam [7:0] SR_MISC_OUTS = SR_BASE + 8'd0;
+  localparam [7:0] SR_SPI       = SR_BASE + 8'd8;
+  localparam [7:0] SR_LEDS      = SR_BASE + 8'd16;
+  localparam [7:0] SR_FP_GPIO   = SR_BASE + 8'd24;
+  localparam [7:0] SR_DB_GPIO   = SR_BASE + 8'd32;
+
+  localparam [7:0] RB_MISC_IO   = RB_BASE + 0;
+  localparam [7:0] RB_SPI       = RB_BASE + 1;
+  localparam [7:0] RB_LEDS      = RB_BASE + 2;
+  localparam [7:0] RB_DB_GPIO   = RB_BASE + 3;
+  localparam [7:0] RB_FP_GPIO   = RB_BASE + 4;
+
+  /********************************************************
+  ** Settings registers
+  ********************************************************/
+  setting_reg #(.my_addr(SR_MISC_OUTS), .width(32)) sr_misc_outs (
+    .clk(clk), .rst(reset),
+    .strobe(set_stb), .addr(set_addr), .in(set_data),
+    .out(misc_outs), .changed());
+
+  // Readback
+  reg spi_readback_stb_hold;
+  reg [31:0] spi_readback_hold;
+  wire [31:0] spi_readback_sync;
+  wire [31:0] fp_gpio_readback, db_gpio_readback;
+  always @* begin
+    case(rb_addr)
+      // Use a latched spi readback stobe so additional readbacks after a SPI transaction will work
+      RB_MISC_IO  : {rb_stb, rb_data} <= {spi_readback_stb_hold, {misc_ins, misc_outs}};
+      RB_SPI      : {rb_stb, rb_data} <= {spi_readback_stb_hold, {32'd0, spi_readback_hold}};
+      RB_LEDS     : {rb_stb, rb_data} <= {spi_readback_stb_hold, {32'd0, leds}};
+      RB_DB_GPIO  : {rb_stb, rb_data} <= {spi_readback_stb_hold, {32'd0, db_gpio_readback}};
+      RB_FP_GPIO  : {rb_stb, rb_data} <= {spi_readback_stb_hold, {32'd0, fp_gpio_readback}};
+      default     : {rb_stb, rb_data} <= {spi_readback_stb_hold, {64'h0BADC0DE0BADC0DE}};
+    endcase
+  end
+
+  /********************************************************
+  ** GPIO
+  ********************************************************/
+  gpio_atr #(.BASE(SR_LEDS), .WIDTH(32), .FAB_CTRL_EN(0), .DEFAULT_DDR(32'hFFFF_FFFF), .DEFAULT_IDLE(32'd0)) leds_gpio_atr (
+    .clk(clk), .reset(reset),
+    .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+    .rx(run_rx), .tx(run_tx),
+    .gpio_in(32'd0), .gpio_out(leds), .gpio_ddr(/*unused, assumed output only*/),
+    .gpio_out_fab(32'h00000000 /*LEDs don't have fabric control*/), .gpio_sw_rb());
+
+  gpio_atr #(.BASE(SR_FP_GPIO), .WIDTH(32), .FAB_CTRL_EN(1), .DEFAULT_DDR(32'hFFFF_FFFF), .DEFAULT_IDLE(32'd0)) fp_gpio_atr (
+    .clk(clk), .reset(reset),
+    .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+    .rx(run_rx), .tx(run_tx),
+    .gpio_in(fp_gpio_in), .gpio_out(fp_gpio_out), .gpio_ddr(fp_gpio_ddr),
+    .gpio_out_fab(fp_gpio_fab), .gpio_sw_rb(fp_gpio_readback));
+
+  gpio_atr #(.BASE(SR_DB_GPIO), .WIDTH(32), .FAB_CTRL_EN(1), .DEFAULT_DDR(32'hFFFF_FFFF), .DEFAULT_IDLE(32'd0)) db_gpio_atr (
+    .clk(clk), .reset(reset),
+    .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+    .rx(run_rx), .tx(run_tx),
+    .gpio_in(db_gpio_in), .gpio_out(db_gpio_out), .gpio_ddr(db_gpio_ddr),
+    .gpio_out_fab(db_gpio_fab), .gpio_sw_rb(db_gpio_readback));
+
+  /********************************************************
+  ** SPI
+  ********************************************************/
+  wire spi_set_stb;
+  wire [7:0] spi_set_addr;
+  wire [31:0] spi_set_data;
+  wire spi_readback_stb, spi_readback_stb_sync;
+  wire [31:0] spi_readback;
+  wire spi_clk_int, spi_rst_int;
+  generate
+    if (USE_SPI_CLK) begin
+      axi_fifo_2clk #(.WIDTH(8 + 32), .SIZE(0)) set_2clk_i (
+        .reset(reset),
+        .i_aclk(clk), .i_tdata({set_addr, set_data}), .i_tvalid(set_stb), .i_tready(),
+        .o_aclk(spi_clk), .o_tdata({spi_set_addr, spi_set_data}), .o_tvalid(spi_set_stb), .o_tready(spi_set_stb));
+
+      axi_fifo_2clk #(.WIDTH(32), .SIZE(0)) rb_2clk_i (
+        .reset(reset),
+        .i_aclk(spi_clk), .i_tdata(spi_readback), .i_tvalid(spi_readback_stb), .i_tready(),
+        .o_aclk(clk), .o_tdata(spi_readback_sync), .o_tvalid(spi_readback_stb_sync), .o_tready(spi_readback_stb_sync));
+
+      assign spi_clk_int = spi_clk;
+      assign spi_rst_int = spi_rst;
+    end else begin
+      assign spi_set_stb           = set_stb;
+      assign spi_set_addr          = set_addr;
+      assign spi_set_data          = set_data;
+      assign spi_readback_stb_sync = spi_readback_stb;
+      assign spi_readback_sync     = spi_readback;
+      assign spi_clk_int           = clk;
+      assign spi_rst_int           = reset;
+    end
+  endgenerate
+
+  // Need to latch spi_readback_stb in case of additional readbacks
+  // after the initial spi transaction.
+  always @(posedge clk) begin
+    if (reset) begin
+      spi_readback_stb_hold       <= 1'b1;
+    end else begin
+      if (set_stb & (set_addr == SR_SPI+2 /* Trigger address */)) begin
+        spi_readback_stb_hold     <= 1'b0;
+      end else if (spi_readback_stb_sync) begin
+        spi_readback_hold         <= spi_readback_sync;
+        spi_readback_stb_hold     <= 1'b1;
+      end
+    end
+  end
+
+  // SPI Core instantiation
+  // Note: We don't use "ready" because we use readback_stb to backpressure the settings bus
+  simple_spi_core #(.BASE(SR_SPI), .WIDTH(NUM_SPI_SEN), .CLK_IDLE(0), .SEN_IDLE(8'hFF)) simple_spi_core (
+    .clock(spi_clk_int), .reset(spi_rst_int),
+    .set_stb(spi_set_stb), .set_addr(spi_set_addr), .set_data(spi_set_data),
+    .readback(spi_readback), .readback_stb(spi_readback_stb), .ready(/* Unused */),
+    .sen(sen), .sclk(sclk), .mosi(mosi), .miso(miso),
+    .debug());
+
+endmodule
diff --git a/fpga/usrp3/lib/control/fe_control.v b/fpga/usrp3/lib/control/fe_control.v
new file mode 100644
index 000000000..9e0c6cea5
--- /dev/null
+++ b/fpga/usrp3/lib/control/fe_control.v
@@ -0,0 +1,70 @@
+//
+// Copyright 2019 Ettus Research, a National Instruments Brand
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: fe_control
+//
+// Description: Handle the front end control from the radio settings bus.
+// The module gets generated NUM_CHANNELS times to give independent control to
+// the individual channels.
+//
+
+module fe_control #(
+  parameter NUM_CHANNELS = 2,
+  parameter [7:0] SR_FE_CHAN_OFFSET = 16,
+  parameter [7:0] SR_TX_FE_BASE = 192,
+  parameter [7:0] SR_RX_FE_BASE = 200
+)(
+  input clk, input reset,
+  // Commands from Radio Core
+  input  set_stb, input [7:0] set_addr, input  [31:0] set_data,
+  input  time_sync,
+  // Radio datapath
+  input  [NUM_CHANNELS-1:0] tx_stb, input [32*NUM_CHANNELS-1:0] tx_data_in, output [32*NUM_CHANNELS-1:0] tx_data_out,
+  output [NUM_CHANNELS-1:0] rx_stb, input [32*NUM_CHANNELS-1:0] rx_data_in, output [32*NUM_CHANNELS-1:0] rx_data_out
+);
+
+  genvar i;
+  generate for (i = 0; i < NUM_CHANNELS; i = i + 1)
+    begin
+      localparam SR_TX_OFFSET_I         = SR_TX_FE_BASE + SR_FE_CHAN_OFFSET*i + 0;
+      localparam SR_TX_OFFSET_Q         = SR_TX_FE_BASE + SR_FE_CHAN_OFFSET*i + 1;
+      localparam SR_TX_MAG_CORRECTION   = SR_TX_FE_BASE + SR_FE_CHAN_OFFSET*i + 2;
+      localparam SR_TX_PHASE_CORRECTION = SR_TX_FE_BASE + SR_FE_CHAN_OFFSET*i + 3;
+      localparam SR_TX_MUX              = SR_TX_FE_BASE + SR_FE_CHAN_OFFSET*i + 4;
+
+      tx_frontend_gen3 #(
+        .SR_OFFSET_I(SR_TX_OFFSET_I), .SR_OFFSET_Q(SR_TX_OFFSET_Q),.SR_MAG_CORRECTION(SR_TX_MAG_CORRECTION),
+        .SR_PHASE_CORRECTION(SR_TX_PHASE_CORRECTION), .SR_MUX(SR_TX_MUX),
+        .BYPASS_DC_OFFSET_CORR(0), .BYPASS_IQ_COMP(0),
+        .DEVICE("7SERIES")
+      ) tx_fe_corr_i (
+        .clk(clk), .reset(reset),
+        .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+        .tx_stb(tx_stb[i]), .tx_i(tx_data_in[32+(32*i)-1:16+(32*i)]), .tx_q(tx_data_in[16+(32*i)-1:(32*i)]),
+        .dac_stb(), .dac_i(tx_data_out[32+(32*i)-1:16+(32*i)]), .dac_q(tx_data_out[16+(32*i)-1:(32*i)])
+      );
+
+      localparam SR_RX_MAG_CORRECTION   = SR_RX_FE_BASE + SR_FE_CHAN_OFFSET*i + 0;
+      localparam SR_RX_PHASE_CORRECTION = SR_RX_FE_BASE + SR_FE_CHAN_OFFSET*i + 1;
+      localparam SR_RX_OFFSET_I         = SR_RX_FE_BASE + SR_FE_CHAN_OFFSET*i + 2;
+      localparam SR_RX_OFFSET_Q         = SR_RX_FE_BASE + SR_FE_CHAN_OFFSET*i + 3;
+      localparam SR_RX_IQ_MAPPING       = SR_RX_FE_BASE + SR_FE_CHAN_OFFSET*i + 4;
+      localparam SR_RX_HET_PHASE_INCR   = SR_RX_FE_BASE + SR_FE_CHAN_OFFSET*i + 5;
+
+      rx_frontend_gen3 #(
+        .SR_MAG_CORRECTION(SR_RX_MAG_CORRECTION), .SR_PHASE_CORRECTION(SR_RX_PHASE_CORRECTION), .SR_OFFSET_I(SR_RX_OFFSET_I),
+        .SR_OFFSET_Q(SR_RX_OFFSET_Q), .SR_IQ_MAPPING(SR_RX_IQ_MAPPING), .SR_HET_PHASE_INCR(SR_RX_HET_PHASE_INCR),
+        .BYPASS_DC_OFFSET_CORR(0), .BYPASS_IQ_COMP(0), .BYPASS_REALMODE_DSP(0),
+        .DEVICE("7SERIES")
+      ) rx_fe_corr_i (
+        .clk(clk), .reset(reset), .sync_in(time_sync),
+        .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+        .adc_stb(1'b1), .adc_i(rx_data_in[32+(32*i)-1:16+(32*i)]), .adc_q(rx_data_in[16+(32*i)-1:(32*i)]),
+        .rx_stb(rx_stb[i]), .rx_i(rx_data_out[32+(32*i)-1:16+(32*i)]), .rx_q(rx_data_out[16+(32*i)-1:(32*i)])
+      );
+    end
+  endgenerate
+
+endmodule
diff --git a/fpga/usrp3/lib/control/filter_bad_sid.v b/fpga/usrp3/lib/control/filter_bad_sid.v
new file mode 100644
index 000000000..41e42c516
--- /dev/null
+++ b/fpga/usrp3/lib/control/filter_bad_sid.v
@@ -0,0 +1,78 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Discard silently packets which don't match this SID
+
+module filter_bad_sid
+  (
+   input clk,
+   input reset,
+   input clear,
+   //
+   input [64:0] i_tdata,
+   input i_tvalid,
+   output i_tready,
+   //
+   output [64:0] o_tdata,
+   output o_tvalid,
+   input  o_tready,
+   //
+   output reg [15:0] count
+   );
+
+   reg [1:0] state;
+   wire      good_sid;
+   wire      qualify_i_tvalid;
+   
+   localparam IDLE = 0;
+   localparam ACCEPT = 1;
+   localparam DISCARD = 2;
+   
+
+   always @(posedge clk)
+     if (reset | clear) begin
+	state <= IDLE;
+	count <= 0;
+     end else
+       case(state)
+	 //
+	 IDLE: begin
+	    if  (i_tvalid && i_tready)
+	      if (good_sid)
+		state <= ACCEPT;
+	      else begin
+		 count <= count + 1;
+		 state <= DISCARD;
+	      end	    
+	 end
+	 //
+	 ACCEPT: begin
+	    if (i_tvalid && i_tready && i_tdata[64]) 
+	      state <= IDLE;
+	 end
+	 //
+	 DISCARD: begin
+	    if (i_tvalid && i_tready && i_tdata[64]) 
+	      state <= IDLE;
+	 end
+       endcase // case(state)
+   
+   assign good_sid = ((i_tdata[15:0] == 16'h00A0) || (i_tdata[15:0] == 16'h00B0));
+   
+   assign qualify_i_tvalid = (state == IDLE) ? good_sid : ((state == DISCARD) ? 1'b0 : 1'b1);
+
+   //
+   // Buffer output, break combinatorial timing paths
+   //
+   axi_fifo_short #(.WIDTH(65)) fifo_short
+     (
+      .clk(clk), .reset(reset), .clear(clear),
+      .i_tdata(i_tdata), .i_tvalid(i_tvalid && qualify_i_tvalid), .i_tready(i_tready),
+      .o_tdata(o_tdata), .o_tvalid(o_tvalid), .o_tready(o_tready),
+      .space(), .occupied()
+      );
+   
+endmodule // filter_bad_sid
diff --git a/fpga/usrp3/lib/control/gpio_atr.v b/fpga/usrp3/lib/control/gpio_atr.v
new file mode 100644
index 000000000..f99ac55b1
--- /dev/null
+++ b/fpga/usrp3/lib/control/gpio_atr.v
@@ -0,0 +1,98 @@
+
+//
+// Copyright 2011 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module gpio_atr #(
+  parameter BASE          = 0,
+  parameter WIDTH         = 32,
+  parameter FAB_CTRL_EN   = 0,
+  parameter DEFAULT_DDR   = 0,
+  parameter DEFAULT_IDLE  = 0
+) (
+  input clk, input reset,                                       //Clock and reset
+  input set_stb, input [7:0] set_addr, input [31:0] set_data,   //Settings control interface
+  input rx, input tx,                                           //Run signals that indicate tx and rx operation
+  input      [WIDTH-1:0]  gpio_in,                              //GPIO input state
+  output reg [WIDTH-1:0]  gpio_out,                             //GPIO output state
+  output reg [WIDTH-1:0]  gpio_ddr,                             //GPIO direction (0=input, 1=output)
+  input      [WIDTH-1:0]  gpio_out_fab,                         //GPIO driver bus from fabric
+  output reg [WIDTH-1:0]  gpio_sw_rb                            //Readback value for software
+);
+  genvar i;
+
+  wire [WIDTH-1:0]   in_idle, in_tx, in_rx, in_fdx, ddr_reg, atr_disable, fabric_ctrl;
+  reg [WIDTH-1:0]    ogpio, igpio;
+
+  setting_reg #(.my_addr(BASE+0), .width(WIDTH), .at_reset(DEFAULT_IDLE)) reg_idle (
+    .clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),
+    .out(in_idle),.changed());
+
+  setting_reg #(.my_addr(BASE+1), .width(WIDTH)) reg_rx (
+    .clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),
+    .out(in_rx),.changed());
+
+  setting_reg #(.my_addr(BASE+2), .width(WIDTH)) reg_tx (
+    .clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),
+    .out(in_tx),.changed());
+
+  setting_reg #(.my_addr(BASE+3), .width(WIDTH)) reg_fdx (
+    .clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),
+    .out(in_fdx),.changed());
+
+  setting_reg #(.my_addr(BASE+4), .width(WIDTH), .at_reset(DEFAULT_DDR)) reg_ddr (
+    .clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),
+    .out(ddr_reg),.changed());
+
+  setting_reg #(.my_addr(BASE+5), .width(WIDTH)) reg_atr_disable (
+    .clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),
+    .out(atr_disable),.changed());
+
+  generate if (FAB_CTRL_EN == 1) begin
+    setting_reg #(.my_addr(BASE+6), .width(WIDTH)) reg_fabric_ctrl (
+      .clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),
+      .out(fabric_ctrl),.changed());
+  end else begin
+    assign fabric_ctrl = {WIDTH{1'b0}};
+  end endgenerate
+
+  //Pipeline rx and tx signals for easier timing closure
+  reg rx_d, tx_d;
+  always @(posedge clk)
+    {rx_d, tx_d} <= {rx, tx};
+
+  generate for (i=0; i<WIDTH; i=i+1) begin: gpio_mux_gen
+    //ATR selection MUX
+    always @(posedge clk) begin
+      case({atr_disable[i], tx_d, rx_d})
+        3'b000:   ogpio[i] <= in_idle[i];
+        3'b001:   ogpio[i] <= in_rx[i];
+        3'b010:   ogpio[i] <= in_tx[i];
+        3'b011:   ogpio[i] <= in_fdx[i];
+        default:  ogpio[i] <= in_idle[i];   //If ATR mode is disabled, always use IDLE value
+      endcase
+    end
+
+   //Pipeline input, output and direction
+   //For fabric access, insert MUX as close to the IO as possible
+   always @(posedge clk) begin
+     gpio_out[i] <= fabric_ctrl[i] ? gpio_out_fab[i] : ogpio[i];
+   end
+  end endgenerate
+
+  always @(posedge clk)
+    igpio <= gpio_in;
+
+  always @(posedge clk)
+    gpio_ddr <= ddr_reg;
+
+  //Generate software readback state
+  generate for (i=0; i<WIDTH; i=i+1) begin: gpio_rb_gen
+    always @(posedge clk)
+      gpio_sw_rb[i] <= gpio_ddr[i] ? gpio_out[i] : igpio[i];
+  end endgenerate
+
+endmodule // gpio_atr
diff --git a/fpga/usrp3/lib/control/gpio_atr_io.v b/fpga/usrp3/lib/control/gpio_atr_io.v
new file mode 100644
index 000000000..4c427177b
--- /dev/null
+++ b/fpga/usrp3/lib/control/gpio_atr_io.v
@@ -0,0 +1,38 @@
+
+//
+// Copyright 2015 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module gpio_atr_io #(
+  parameter WIDTH = 32
+) (
+  input               clk,
+  input  [WIDTH-1:0]  gpio_ddr,
+  input  [WIDTH-1:0]  gpio_out,
+  output [WIDTH-1:0]  gpio_in,
+  inout  [WIDTH-1:0]  gpio_pins
+);
+
+  //Instantiate registers in the IOB
+  (* IOB = "true" *) reg [WIDTH-1:0] gpio_in_iob, gpio_out_iob;
+  always @(posedge clk) begin
+    gpio_in_iob   <= gpio_pins;
+    gpio_out_iob  <= gpio_out;
+  end
+  assign gpio_in = gpio_in_iob;
+
+  //Pipeline the data direction bus
+  reg [WIDTH-1:0] gpio_ddr_reg;
+  always @(posedge clk)
+    gpio_ddr_reg <= gpio_ddr;
+
+  //Tristate buffers
+  genvar i;
+  generate for (i=0; i<WIDTH; i=i+1) begin: io_tristate_gen
+    assign gpio_pins[i] = gpio_ddr_reg[i] ? gpio_out_iob[i] : 1'bz;
+  end endgenerate
+
+endmodule // gpio_atr_io
diff --git a/fpga/usrp3/lib/control/gray2bin.v b/fpga/usrp3/lib/control/gray2bin.v
new file mode 100644
index 000000000..c75ad80c6
--- /dev/null
+++ b/fpga/usrp3/lib/control/gray2bin.v
@@ -0,0 +1,25 @@
+//
+// Copyright 2016 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+//
+// Gray: {a,b,c,d}
+// Bits: {a,a^b,a^b^c,a^b^c^d}
+//
+module gray2bin #(
+    parameter WIDTH = 8)
+(
+    input [WIDTH-1:0] gray,
+    output reg [WIDTH-1:0] bin
+);
+
+    integer i;
+    always @(*) begin
+        bin[WIDTH-1] = gray[WIDTH-1];
+        for (i = WIDTH-2; i >= 0; i = i - 1) begin
+            bin[i] = bin[i+1] ^ gray[i];
+        end
+    end
+
+endmodule
diff --git a/fpga/usrp3/lib/control/map/AUTHORS b/fpga/usrp3/lib/control/map/AUTHORS
new file mode 100644
index 000000000..c727d8d3c
--- /dev/null
+++ b/fpga/usrp3/lib/control/map/AUTHORS
@@ -0,0 +1,3 @@
+Contributions from:
+Ettus Research, A National Instruments Company
+Alex Forencich <alex@alexforencich.com>
\ No newline at end of file
diff --git a/fpga/usrp3/lib/control/map/axis_muxed_kv_map.v b/fpga/usrp3/lib/control/map/axis_muxed_kv_map.v
new file mode 100644
index 000000000..152cee8eb
--- /dev/null
+++ b/fpga/usrp3/lib/control/map/axis_muxed_kv_map.v
@@ -0,0 +1,206 @@
+//
+// Copyright 2018 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: axis_muxed_kv_map
+//
+// Description:
+//
+//   This module implements a memory that stores key and value (KV) pairs such
+//   that the value can be looked up using the key (e.g., for a routing table).
+//   This implementation uses AXI stream for both inserting key-value pairs and
+//   for looking up a value by its key. It also supports multiple find/result
+//   AXI streams, which share the same KV map internally.
+//
+//   Values are inserted into the KV map using the axis_insert_* AXI stream. A
+//   value can be looked up by its key using the axis_find_* AXI stream, in
+//   which case the resulting value is output on the axis_result_* AXI stream.
+//
+// Ports:
+//
+//   axis_insert_tdest  : Key to insert into the KV map
+//   axis_insert_tdata  : Value to associate with the key in TDEST
+//   axis_insert_tvalid : Standard AXI stream TVALID
+//   axis_insert_tready : Standard AXI stream TREADY
+//  
+//   axis_find_tdata    : Key to look up in the KV map
+//   axis_find_tvalid   : Standard AXI stream TVALID
+//   axis_find_tready   : Standard AXI stream TREADY
+//
+//   axis_result_tdata  : Value associated with key that was input on axis_find
+//   axis_result_tkeep  : Indicates if TDATA contains a valid value (i.e.,
+//                        TKEEP is 0 if the lookup fails to find a match)
+//   axis_result_tvalid : Standard AXI stream TVALID 
+//   axis_result_tready : Standard AXI stream TREADY
+//
+// Parameters:
+//
+//   KEY_WIDTH : Width of the key (axis_insert_tdest, axis_find_tdata)
+//   VAL_WIDTH : Width of the value (axis_insert_tdata, axis_result_tdata)
+//   SIZE      : Size of the KV map (i.e., 2**SIZE key-value pairs)
+//   NUM_PORTS : Number of AXI-Stream ports for the find and result interfaces
+//
+
+module axis_muxed_kv_map #(
+  parameter KEY_WIDTH   = 16,
+  parameter VAL_WIDTH   = 32,
+  parameter SIZE        = 6,
+  parameter NUM_PORTS   = 4
+) (
+  input  wire                             clk,
+  input  wire                             reset,
+                                          
+  input  wire [KEY_WIDTH-1:0]             axis_insert_tdest,
+  input  wire [VAL_WIDTH-1:0]             axis_insert_tdata,
+  input  wire                             axis_insert_tvalid,
+  output wire                             axis_insert_tready,
+
+  input  wire [(KEY_WIDTH*NUM_PORTS)-1:0] axis_find_tdata,
+  input  wire [NUM_PORTS-1:0]             axis_find_tvalid,
+  output wire [NUM_PORTS-1:0]             axis_find_tready,
+
+  output wire [(VAL_WIDTH*NUM_PORTS)-1:0] axis_result_tdata,
+  output wire [NUM_PORTS-1:0]             axis_result_tkeep,
+  output wire [NUM_PORTS-1:0]             axis_result_tvalid,
+  input  wire [NUM_PORTS-1:0]             axis_result_tready
+);
+
+  localparam MUX_W   = $clog2(NUM_PORTS) + KEY_WIDTH;
+  localparam DEMUX_W = $clog2(NUM_PORTS) + VAL_WIDTH + 1;
+  genvar i;
+
+  localparam [1:0] ST_IDLE    = 2'd0;
+  localparam [1:0] ST_REQUEST = 2'd1;
+  localparam [1:0] ST_PENDING = 2'd2;
+
+  //---------------------------------------------------------
+  // Demux find ports
+  //---------------------------------------------------------
+  wire [KEY_WIDTH-1:0]          find_key, find_key_reg;
+  wire                          find_key_stb;
+  wire [$clog2(NUM_PORTS)-1:0]  find_dest, find_dest_reg;
+  wire                          find_key_valid, find_key_valid_reg;
+  wire                          find_ready;
+  reg                           find_in_progress = 1'b0;
+  wire                          insert_stb;
+  wire                          insert_busy;
+  wire                          find_res_stb;
+  wire [VAL_WIDTH-1:0]          find_res_val;
+  wire                          find_res_match, find_res_ready;
+
+  wire [(MUX_W*NUM_PORTS)-1:0] mux_tdata;
+  generate for (i = 0; i < NUM_PORTS; i = i + 1) begin : gen_mux_input
+    assign mux_tdata[(MUX_W*i)+KEY_WIDTH-1:MUX_W*i] = axis_find_tdata[(KEY_WIDTH*i)+:KEY_WIDTH];
+    assign mux_tdata[(MUX_W*(i+1))-1:(MUX_W*i)+KEY_WIDTH] = i;
+  end endgenerate
+
+  axi_mux #(
+    .WIDTH(KEY_WIDTH+$clog2(NUM_PORTS)), .SIZE(NUM_PORTS),
+    .PRE_FIFO_SIZE(0), .POST_FIFO_SIZE($clog2(NUM_PORTS))
+  ) mux_i (
+    .clk(clk), .reset(reset), .clear(1'b0),
+    .i_tdata(mux_tdata), .i_tlast({NUM_PORTS{1'b1}}),
+    .i_tvalid(axis_find_tvalid), .i_tready(axis_find_tready),
+    .o_tdata({find_dest_reg, find_key_reg}), .o_tlast(),
+    .o_tvalid(find_key_valid_reg), .o_tready(find_ready)
+  );
+
+  axi_fifo #(
+    .WIDTH(KEY_WIDTH+$clog2(NUM_PORTS)), .SIZE(1)
+  ) mux_reg_i (
+    .clk(clk), .reset(reset), .clear(1'b0),
+    .i_tdata({find_dest_reg, find_key_reg}),
+    .i_tvalid(find_key_valid_reg), .i_tready(find_ready),
+    .o_tdata({find_dest, find_key}),
+    .o_tvalid(find_key_valid), .o_tready(find_res_stb),
+    .space(), .occupied()
+  );
+
+  always @(posedge clk) begin
+    if (reset) begin
+      find_in_progress <= 1'b0;
+    end else begin
+      if (find_key_stb) begin
+        find_in_progress <= 1'b1;
+      end else if (find_res_stb) begin
+        find_in_progress <= 1'b0;
+      end
+    end
+  end
+
+  // find_key_stb indicates when to begin a new KV map lookup. We must wait
+  // until the output mux is ready before starting a lookup.
+  assign find_key_stb = find_key_valid & find_res_ready & ~find_in_progress;
+
+  //---------------------------------------------------------
+  // Insert logic
+  //---------------------------------------------------------
+  reg [1:0] ins_state = ST_IDLE;
+  always @(posedge clk) begin
+    if (reset) begin
+      ins_state <= ST_IDLE;
+    end else begin
+      case (ins_state)
+        ST_IDLE:
+          if (axis_insert_tvalid & ~insert_busy)
+            ins_state <= ST_REQUEST;
+        ST_REQUEST:
+          ins_state <= ST_PENDING;
+        ST_PENDING:
+          if (~insert_busy)
+            ins_state <= ST_IDLE;
+        default:
+          ins_state <= ST_IDLE;
+      endcase
+    end
+  end
+
+  assign axis_insert_tready = axis_insert_tvalid & (ins_state == ST_PENDING) & ~insert_busy;
+  assign insert_stb = axis_insert_tvalid & (ins_state == ST_REQUEST);
+
+  //---------------------------------------------------------
+  // KV map instantiation
+  //---------------------------------------------------------
+  kv_map #(
+    .KEY_WIDTH      (KEY_WIDTH),
+    .VAL_WIDTH      (VAL_WIDTH),
+    .SIZE           (SIZE)
+  ) map_i (
+    .clk            (clk),
+    .reset          (reset),
+    .insert_stb     (insert_stb),
+    .insert_key     (axis_insert_tdest),
+    .insert_val     (axis_insert_tdata),
+    .insert_busy    (insert_busy),
+    .find_key_stb   (find_key_stb),
+    .find_key       (find_key),
+    .find_res_stb   (find_res_stb),
+    .find_res_match (find_res_match),
+    .find_res_val   (find_res_val),
+    .count          (/* unused */)
+  );
+
+  //---------------------------------------------------------
+  // Mux results port
+  //---------------------------------------------------------
+  wire [(DEMUX_W*NUM_PORTS)-1:0] demux_tdata;
+  wire [DEMUX_W-1:0] hdr;
+  axi_demux #(
+    .WIDTH(DEMUX_W), .SIZE(NUM_PORTS),
+    .PRE_FIFO_SIZE(1), .POST_FIFO_SIZE(0)
+  ) demux_i (
+    .clk(clk), .reset(reset), .clear(1'b0),
+    .header(hdr), .dest(hdr[DEMUX_W-1:VAL_WIDTH+1]),
+    .i_tdata({find_dest, find_res_match, find_res_val}), .i_tlast(1'b1),
+    .i_tvalid(find_res_stb), .i_tready(find_res_ready),
+    .o_tdata(demux_tdata), .o_tlast(),
+    .o_tvalid(axis_result_tvalid), .o_tready(axis_result_tready)
+  );
+
+  generate for (i = 0; i < NUM_PORTS; i = i + 1) begin : gen_result_output
+    assign axis_result_tdata[(VAL_WIDTH*i)+:VAL_WIDTH] = demux_tdata[(DEMUX_W*i)+VAL_WIDTH-1:DEMUX_W*i];
+    assign axis_result_tkeep[i] = demux_tdata[(DEMUX_W*i)+VAL_WIDTH];
+  end endgenerate
+
+endmodule
diff --git a/fpga/usrp3/lib/control/map/cam.v b/fpga/usrp3/lib/control/map/cam.v
new file mode 100644
index 000000000..6b3237b6f
--- /dev/null
+++ b/fpga/usrp3/lib/control/map/cam.v
@@ -0,0 +1,103 @@
+/*
+
+Copyright (c) 2015-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * Content Addressable Memory
+ */
+module cam #(
+    // search data bus width
+    parameter DATA_WIDTH = 64,
+    // memory size in log2(words)
+    parameter ADDR_WIDTH = 5,
+    // CAM style (SRL, BRAM)
+    parameter CAM_STYLE = "SRL",
+    // width of data bus slices
+    parameter SLICE_WIDTH = 4
+)
+(
+    input  wire                     clk,
+    input  wire                     rst,
+
+    input  wire [ADDR_WIDTH-1:0]    write_addr,
+    input  wire [DATA_WIDTH-1:0]    write_data,
+    input  wire                     write_delete,
+    input  wire                     write_enable,
+    output wire                     write_busy,
+
+    input  wire [DATA_WIDTH-1:0]    compare_data,
+    output wire [2**ADDR_WIDTH-1:0] match_many,
+    output wire [2**ADDR_WIDTH-1:0] match_single,
+    output wire [ADDR_WIDTH-1:0]    match_addr,
+    output wire                     match
+);
+
+generate
+    if (CAM_STYLE == "SRL") begin
+        cam_srl #(
+            .DATA_WIDTH(DATA_WIDTH),
+            .ADDR_WIDTH(ADDR_WIDTH),
+            .SLICE_WIDTH(SLICE_WIDTH)
+        )
+        cam_inst (
+            .clk(clk),
+            .rst(rst),
+            .write_addr(write_addr),
+            .write_data(write_data),
+            .write_delete(write_delete),
+            .write_enable(write_enable),
+            .write_busy(write_busy),
+            .compare_data(compare_data),
+            .match_many(match_many),
+            .match_single(match_single),
+            .match_addr(match_addr),
+            .match(match)
+        );
+    end else if (CAM_STYLE == "BRAM") begin
+        cam_bram #(
+            .DATA_WIDTH(DATA_WIDTH),
+            .ADDR_WIDTH(ADDR_WIDTH),
+            .SLICE_WIDTH(SLICE_WIDTH)
+        )
+        cam_inst (
+            .clk(clk),
+            .rst(rst),
+            .write_addr(write_addr),
+            .write_data(write_data),
+            .write_delete(write_delete),
+            .write_enable(write_enable),
+            .write_busy(write_busy),
+            .compare_data(compare_data),
+            .match_many(match_many),
+            .match_single(match_single),
+            .match_addr(match_addr),
+            .match(match)
+        );
+    end
+endgenerate
+
+endmodule
diff --git a/fpga/usrp3/lib/control/map/cam_bram.v b/fpga/usrp3/lib/control/map/cam_bram.v
new file mode 100644
index 000000000..c18df1084
--- /dev/null
+++ b/fpga/usrp3/lib/control/map/cam_bram.v
@@ -0,0 +1,259 @@
+/*
+
+Copyright (c) 2015-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * Content Addressable Memory (block RAM based)
+ */
+module cam_bram #(
+    // search data bus width
+    parameter DATA_WIDTH = 64,
+    // memory size in log2(words)
+    parameter ADDR_WIDTH = 5,
+    // width of data bus slices
+    parameter SLICE_WIDTH = 9
+)
+(
+    input  wire                     clk,
+    input  wire                     rst,
+
+    input  wire [ADDR_WIDTH-1:0]    write_addr,
+    input  wire [DATA_WIDTH-1:0]    write_data,
+    input  wire                     write_delete,
+    input  wire                     write_enable,
+    output wire                     write_busy,
+
+    input  wire [DATA_WIDTH-1:0]    compare_data,
+    output wire [2**ADDR_WIDTH-1:0] match_many,
+    output wire [2**ADDR_WIDTH-1:0] match_single,
+    output wire [ADDR_WIDTH-1:0]    match_addr,
+    output wire                     match
+);
+
+// total number of slices (enough to cover DATA_WIDTH with address inputs)
+localparam SLICE_COUNT = (DATA_WIDTH + SLICE_WIDTH - 1) / SLICE_WIDTH;
+// depth of RAMs
+localparam RAM_DEPTH = 2**ADDR_WIDTH;
+
+localparam [2:0]
+    STATE_INIT = 3'd0,
+    STATE_IDLE = 3'd1,
+    STATE_DELETE_1 = 3'd2,
+    STATE_DELETE_2 = 3'd3,
+    STATE_WRITE_1 = 3'd4,
+    STATE_WRITE_2 = 3'd5;
+
+reg [2:0] state_reg = STATE_INIT, state_next;
+
+wire [SLICE_COUNT*SLICE_WIDTH-1:0] compare_data_padded = {{SLICE_COUNT*SLICE_WIDTH-DATA_WIDTH{1'b0}}, compare_data};
+wire [SLICE_COUNT*SLICE_WIDTH-1:0] write_data_padded = {{SLICE_COUNT*SLICE_WIDTH-DATA_WIDTH{1'b0}}, write_data};
+
+reg [SLICE_WIDTH-1:0] count_reg = {SLICE_WIDTH{1'b1}}, count_next;
+
+reg [SLICE_COUNT*SLICE_WIDTH-1:0] ram_addr = {SLICE_COUNT*SLICE_WIDTH{1'b0}};
+reg [RAM_DEPTH-1:0] set_bit;
+reg [RAM_DEPTH-1:0] clear_bit;
+reg wr_en;
+
+reg [ADDR_WIDTH-1:0] write_addr_reg = {ADDR_WIDTH{1'b0}}, write_addr_next;
+reg [SLICE_COUNT*SLICE_WIDTH-1:0] write_data_padded_reg = {SLICE_COUNT*SLICE_WIDTH{1'b0}}, write_data_padded_next;
+reg write_delete_reg = 1'b0, write_delete_next;
+
+reg write_busy_reg = 1'b1;
+
+assign write_busy = write_busy_reg;
+
+reg [RAM_DEPTH-1:0] match_raw_out[SLICE_COUNT-1:0];
+reg [RAM_DEPTH-1:0] match_many_raw;
+
+assign match_many = match_many_raw;
+
+reg [DATA_WIDTH-1:0] erase_ram [RAM_DEPTH-1:0];
+reg [DATA_WIDTH-1:0] erase_data = {DATA_WIDTH{1'b0}};
+reg erase_ram_wr_en;
+
+integer i;
+
+initial begin
+    for (i = 0; i < RAM_DEPTH; i = i + 1) begin
+        erase_ram[i] = {SLICE_COUNT*SLICE_WIDTH{1'b0}};
+    end
+end
+
+integer k;
+
+always @* begin
+    match_many_raw = {RAM_DEPTH{1'b1}};
+    for (k = 0; k < SLICE_COUNT; k = k + 1) begin
+        match_many_raw = match_many_raw & match_raw_out[k];
+    end
+end
+
+cam_priority_encoder #(
+    .WIDTH(RAM_DEPTH),
+    .LSB_PRIORITY("HIGH")
+)
+priority_encoder_inst (
+    .input_unencoded(match_many_raw),
+    .output_valid(match),
+    .output_encoded(match_addr),
+    .output_unencoded(match_single)
+);
+
+// BRAMs
+genvar slice_ind;
+generate
+    for (slice_ind = 0; slice_ind < SLICE_COUNT; slice_ind = slice_ind + 1) begin : slice
+        localparam W = slice_ind == SLICE_COUNT-1 ? DATA_WIDTH-SLICE_WIDTH*slice_ind : SLICE_WIDTH;
+
+        wire [RAM_DEPTH-1:0] match_data;
+        wire [RAM_DEPTH-1:0] ram_data;
+
+        ram_2port #(
+            .DWIDTH(RAM_DEPTH),
+            .AWIDTH(W)
+        )
+        ram_inst
+        (
+            .clka(clk),
+            .ena(1'b1),
+            .wea(1'b0),
+            .addra(compare_data[SLICE_WIDTH * slice_ind +: W]),
+            .dia({RAM_DEPTH{1'b0}}),
+            .doa(match_data),
+            .clkb(clk),
+            .enb(1'b1),
+            .web(wr_en),
+            .addrb(ram_addr[SLICE_WIDTH * slice_ind +: W]),
+            .dib((ram_data & ~clear_bit) | set_bit),
+            .dob(ram_data)
+        );
+
+        always @* begin
+            match_raw_out[slice_ind] <= match_data;
+        end
+    end
+endgenerate
+
+// erase
+always @(posedge clk) begin
+    erase_data <= erase_ram[write_addr_next];
+    if (erase_ram_wr_en) begin
+        erase_data <= write_data_padded_reg;
+        erase_ram[write_addr_next] <= write_data_padded_reg;
+    end
+end
+
+// write
+always @* begin
+    state_next = STATE_IDLE;
+
+    count_next = count_reg;
+    ram_addr = erase_data;
+    set_bit = {RAM_DEPTH{1'b0}};
+    clear_bit = {RAM_DEPTH{1'b0}};
+    wr_en = 1'b0;
+
+    erase_ram_wr_en = 1'b0;
+
+    write_addr_next = write_addr_reg;
+    write_data_padded_next = write_data_padded_reg;
+    write_delete_next = write_delete_reg;
+
+    case (state_reg)
+        STATE_INIT: begin
+            // zero out RAMs
+            ram_addr = {SLICE_COUNT{count_reg}} & {{SLICE_COUNT*SLICE_WIDTH-DATA_WIDTH{1'b0}}, {DATA_WIDTH{1'b1}}};
+            set_bit = {RAM_DEPTH{1'b0}};
+            clear_bit = {RAM_DEPTH{1'b1}};
+            wr_en = 1'b1;
+
+            if (count_reg == 0) begin
+                state_next = STATE_IDLE;
+            end else begin
+                count_next = count_reg - 1;
+                state_next = STATE_INIT;
+            end
+        end
+        STATE_IDLE: begin
+            // idle state
+            write_addr_next = write_addr;
+            write_data_padded_next = write_data_padded;
+            write_delete_next = write_delete;
+
+            if (write_enable) begin
+                // wait for read from erase_ram
+                state_next = STATE_DELETE_1;
+            end else begin
+                state_next = STATE_IDLE;
+            end
+        end
+        STATE_DELETE_1: begin
+            // wait for read
+            state_next = STATE_DELETE_2;
+        end
+        STATE_DELETE_2: begin
+            // clear bit and write back
+            clear_bit = 1'b1 << write_addr;
+            wr_en = 1'b1;
+            if (write_delete_reg) begin
+                state_next = STATE_IDLE;
+            end else begin
+                erase_ram_wr_en = 1'b1;
+                state_next = STATE_WRITE_1;
+            end
+        end
+        STATE_WRITE_1: begin
+            // wait for read
+            state_next = STATE_WRITE_2;
+        end
+        STATE_WRITE_2: begin
+            // set bit and write back
+            set_bit = 1'b1 << write_addr;
+            wr_en = 1'b1;
+            state_next = STATE_IDLE;
+        end
+    endcase
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        state_reg <= STATE_INIT;
+        count_reg <= {SLICE_WIDTH{1'b1}};
+        write_busy_reg <= 1'b1;
+    end else begin
+        state_reg <= state_next;
+        count_reg <= count_next;
+        write_busy_reg <= state_next != STATE_IDLE;
+    end
+
+    write_addr_reg <= write_addr_next;
+    write_data_padded_reg <= write_data_padded_next;
+    write_delete_reg <= write_delete_next;
+end
+
+endmodule
diff --git a/fpga/usrp3/lib/control/map/cam_priority_encoder.v b/fpga/usrp3/lib/control/map/cam_priority_encoder.v
new file mode 100644
index 000000000..5125134f6
--- /dev/null
+++ b/fpga/usrp3/lib/control/map/cam_priority_encoder.v
@@ -0,0 +1,94 @@
+/*
+
+Copyright (c) 2014-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * Priority encoder module
+ */
+module cam_priority_encoder #
+(
+    parameter WIDTH = 4,
+    // LSB priority: "LOW", "HIGH"
+    parameter LSB_PRIORITY = "LOW"
+)
+(
+    input  wire [WIDTH-1:0]         input_unencoded,
+    output wire                     output_valid,
+    output wire [$clog2(WIDTH)-1:0] output_encoded,
+    output wire [WIDTH-1:0]         output_unencoded
+);
+
+// power-of-two width
+parameter W1 = 2**$clog2(WIDTH);
+parameter W2 = W1/2;
+
+generate
+    if (WIDTH == 2) begin
+        // two inputs - just an OR gate
+        assign output_valid = |input_unencoded;
+        if (LSB_PRIORITY == "LOW") begin
+            assign output_encoded = input_unencoded[1];
+        end else begin
+            assign output_encoded = ~input_unencoded[0];
+        end
+    end else begin
+        // more than two inputs - split into two parts and recurse
+        // also pad input to correct power-of-two width
+        wire [$clog2(W2)-1:0] out1, out2;
+        wire valid1, valid2;
+        cam_priority_encoder #(
+            .WIDTH(W2),
+            .LSB_PRIORITY(LSB_PRIORITY)
+        )
+        priority_encoder_inst1 (
+            .input_unencoded(input_unencoded[W2-1:0]),
+            .output_valid(valid1),
+            .output_encoded(out1)
+        );
+        cam_priority_encoder #(
+            .WIDTH(W2),
+            .LSB_PRIORITY(LSB_PRIORITY)
+        )
+        priority_encoder_inst2 (
+            .input_unencoded({{W1-WIDTH{1'b0}}, input_unencoded[WIDTH-1:W2]}),
+            .output_valid(valid2),
+            .output_encoded(out2)
+        );
+        // multiplexer to select part
+        assign output_valid = valid1 | valid2;
+        if (LSB_PRIORITY == "LOW") begin
+            assign output_encoded = valid2 ? {1'b1, out2} : {1'b0, out1};
+        end else begin
+            assign output_encoded = valid1 ? {1'b0, out1} : {1'b1, out2};
+        end
+    end
+endgenerate
+
+// unencoded output
+assign output_unencoded = 1 << output_encoded;
+
+endmodule
diff --git a/fpga/usrp3/lib/control/map/cam_srl.v b/fpga/usrp3/lib/control/map/cam_srl.v
new file mode 100644
index 000000000..6bc4146b0
--- /dev/null
+++ b/fpga/usrp3/lib/control/map/cam_srl.v
@@ -0,0 +1,223 @@
+/*
+
+Copyright (c) 2015-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * Content Addressable Memory (shift register based)
+ */
+module cam_srl #(
+    // search data bus width
+    parameter DATA_WIDTH = 64,
+    // memory size in log2(words)
+    parameter ADDR_WIDTH = 5,
+    // width of data bus slices (4 for SRL16, 5 for SRL32)
+    parameter SLICE_WIDTH = 4
+)
+(
+    input  wire                     clk,
+    input  wire                     rst,
+
+    input  wire [ADDR_WIDTH-1:0]    write_addr,
+    input  wire [DATA_WIDTH-1:0]    write_data,
+    input  wire                     write_delete,
+    input  wire                     write_enable,
+    output wire                     write_busy,
+
+    input  wire [DATA_WIDTH-1:0]    compare_data,
+    output wire [2**ADDR_WIDTH-1:0] match_many,
+    output wire [2**ADDR_WIDTH-1:0] match_single,
+    output wire [ADDR_WIDTH-1:0]    match_addr,
+    output wire                     match
+);
+
+// total number of slices (enough to cover DATA_WIDTH with address inputs)
+localparam SLICE_COUNT = (DATA_WIDTH + SLICE_WIDTH - 1) / SLICE_WIDTH;
+// depth of RAMs
+localparam RAM_DEPTH = 2**ADDR_WIDTH;
+
+localparam [1:0]
+    STATE_INIT = 2'd0,
+    STATE_IDLE = 2'd1,
+    STATE_WRITE = 2'd2,
+    STATE_DELETE = 2'd3;
+
+reg [1:0] state_reg = STATE_INIT, state_next;
+
+wire [SLICE_COUNT*SLICE_WIDTH-1:0] compare_data_padded = {{SLICE_COUNT*SLICE_WIDTH-DATA_WIDTH{1'b0}}, compare_data};
+wire [SLICE_COUNT*SLICE_WIDTH-1:0] write_data_padded = {{SLICE_COUNT*SLICE_WIDTH-DATA_WIDTH{1'b0}}, write_data};
+
+reg [SLICE_WIDTH-1:0] count_reg = {SLICE_WIDTH{1'b1}}, count_next;
+
+reg [SLICE_COUNT-1:0] shift_data;
+reg [RAM_DEPTH-1:0] shift_en;
+
+reg [ADDR_WIDTH-1:0] write_addr_reg = {ADDR_WIDTH{1'b0}}, write_addr_next;
+reg [SLICE_COUNT*SLICE_WIDTH-1:0] write_data_padded_reg = {SLICE_COUNT*SLICE_WIDTH{1'b0}}, write_data_padded_next;
+
+reg write_busy_reg = 1'b1;
+
+assign write_busy = write_busy_reg;
+
+reg [RAM_DEPTH-1:0] match_raw_out[SLICE_COUNT-1:0];
+reg [RAM_DEPTH-1:0] match_many_raw;
+reg [RAM_DEPTH-1:0] match_many_reg = {RAM_DEPTH{1'b0}};
+
+assign match_many = match_many_reg;
+
+integer k;
+
+always @* begin
+    match_many_raw = ~shift_en;
+    for (k = 0; k < SLICE_COUNT; k = k + 1) begin
+        match_many_raw = match_many_raw & match_raw_out[k];
+    end
+end
+
+cam_priority_encoder #(
+    .WIDTH(RAM_DEPTH),
+    .LSB_PRIORITY("HIGH")
+)
+priority_encoder_inst (
+    .input_unencoded(match_many_reg),
+    .output_valid(match),
+    .output_encoded(match_addr),
+    .output_unencoded(match_single)
+);
+
+integer i;
+
+// SRLs
+genvar row_ind, slice_ind;
+generate
+    for (row_ind = 0; row_ind < RAM_DEPTH; row_ind = row_ind + 1) begin : row
+        for (slice_ind = 0; slice_ind < SLICE_COUNT; slice_ind = slice_ind + 1) begin : slice
+            reg [2**SLICE_WIDTH-1:0] srl_mem = {2**SLICE_WIDTH{1'b0}};
+
+            // match
+            always @* begin
+                match_raw_out[slice_ind][row_ind] = srl_mem[compare_data_padded[SLICE_WIDTH * slice_ind +: SLICE_WIDTH]];
+            end
+
+            // write
+            always @(posedge clk) begin
+                if (shift_en[row_ind]) begin
+                    srl_mem <= {srl_mem[2**SLICE_WIDTH-2:0], shift_data[slice_ind]};
+                end
+            end
+        end
+    end
+endgenerate
+
+// match
+always @(posedge clk) begin
+    match_many_reg <= match_many_raw;
+end
+
+// write
+always @* begin
+    state_next = STATE_IDLE;
+
+    count_next = count_reg;
+    shift_data = {SLICE_COUNT{1'b0}};
+    shift_en = {RAM_DEPTH{1'b0}};
+
+    write_addr_next = write_addr_reg;
+    write_data_padded_next = write_data_padded_reg;
+
+    case (state_reg)
+        STATE_INIT: begin
+            // zero out shift registers
+            shift_en = {RAM_DEPTH{1'b1}};
+            shift_data = {SLICE_COUNT{1'b0}};
+
+            if (count_reg == 0) begin
+                state_next = STATE_IDLE;
+            end else begin
+                count_next = count_reg - 1;
+                state_next = STATE_INIT;
+            end
+        end
+        STATE_IDLE: begin
+            if (write_enable) begin
+                write_addr_next = write_addr;
+                write_data_padded_next = write_data_padded;
+                count_next = {SLICE_WIDTH{1'b1}};
+                if (write_delete) begin
+                    state_next = STATE_DELETE;
+                end else begin
+                    state_next = STATE_WRITE;
+                end
+            end else begin
+                state_next = STATE_IDLE;
+            end
+        end
+        STATE_WRITE: begin
+            // write entry
+            shift_en = 1'b1 << write_addr;
+
+            for (i = 0; i < SLICE_COUNT; i = i + 1) begin
+                shift_data[i] = count_reg == write_data_padded_reg[SLICE_WIDTH * i +: SLICE_WIDTH];
+            end
+
+            if (count_reg == 0) begin
+                state_next = STATE_IDLE;
+            end else begin
+                count_next = count_reg - 1;
+                state_next = STATE_WRITE;
+            end
+        end
+        STATE_DELETE: begin
+            // delete entry
+            shift_en = 1'b1 << write_addr;
+            shift_data = {SLICE_COUNT{1'b0}};
+
+            if (count_reg == 0) begin
+                state_next = STATE_IDLE;
+            end else begin
+                count_next = count_reg - 1;
+                state_next = STATE_DELETE;
+            end
+        end
+    endcase
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        state_reg <= STATE_INIT;
+        count_reg <= {SLICE_WIDTH{1'b1}};
+        write_busy_reg <= 1'b1;
+    end else begin
+        state_reg <= state_next;
+        count_reg <= count_next;
+        write_busy_reg <= state_next != STATE_IDLE;
+    end
+
+    write_addr_reg <= write_addr_next;
+    write_data_padded_reg <= write_data_padded_next;
+end
+
+endmodule
diff --git a/fpga/usrp3/lib/control/map/kv_map.v b/fpga/usrp3/lib/control/map/kv_map.v
new file mode 100644
index 000000000..dfb0bca43
--- /dev/null
+++ b/fpga/usrp3/lib/control/map/kv_map.v
@@ -0,0 +1,253 @@
+//
+// Copyright 2018 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: kv_map
+
+module kv_map #(
+  parameter KEY_WIDTH = 16,
+  parameter VAL_WIDTH = 32,
+  parameter SIZE      = 6
+) (
+  // Clock and reset
+  input  wire                 clk,
+  input  wire                 reset,
+  // Insert port
+  input  wire                 insert_stb,
+  input  wire [KEY_WIDTH-1:0] insert_key,
+  input  wire [VAL_WIDTH-1:0] insert_val,
+  output wire                 insert_busy,
+  // Find port
+  input  wire                 find_key_stb,
+  input  wire [KEY_WIDTH-1:0] find_key,
+  output wire                 find_res_stb,
+  output wire                 find_res_match,
+  output wire [VAL_WIDTH-1:0] find_res_val,
+  // Count
+  output reg  [SIZE-1:0]      count = {SIZE{1'b0}}
+);
+
+  //-------------------------------------------------
+  // Instantiate a CAM and a RAM
+  //-------------------------------------------------
+  // The CAM serves as a "set" and the RAM serves as a
+  // random addressable "array". Using thse two data structures
+  // we can build a map. The role of the CAM is to compress
+  // the key to an address that can be used to lookup data
+  // stored in the RAM
+
+  wire                 cam_wr_en, cam_wr_busy, cam_rd_match;
+  wire [SIZE-1:0]      cam_wr_addr, cam_rd_addr;
+  wire [KEY_WIDTH-1:0] cam_wr_data, cam_rd_key;
+
+  wire                 ram_wr_en;
+  wire [SIZE-1:0]      ram_wr_addr;
+  reg  [SIZE-1:0]      ram_rd_addr;
+  wire [VAL_WIDTH-1:0] ram_wr_data, ram_rd_data;
+
+  cam #(
+    .DATA_WIDTH  (KEY_WIDTH),
+    .ADDR_WIDTH  (SIZE),
+    .CAM_STYLE   (SIZE > 8 ? "BRAM" : "SRL"),
+    .SLICE_WIDTH (SIZE > 8 ? 9 : 5)
+  ) cam_i (
+    .clk         (clk),
+    .rst         (reset),
+    .write_addr  (cam_wr_addr),
+    .write_data  (cam_wr_data),
+    .write_delete(1'b0),
+    .write_enable(cam_wr_en),
+    .write_busy  (cam_wr_busy),
+    .compare_data(cam_rd_key),
+    .match_addr  (cam_rd_addr),
+    .match       (cam_rd_match),
+    .match_many  (),
+    .match_single()
+  );
+
+  ram_2port #(
+    .DWIDTH(VAL_WIDTH),
+    .AWIDTH(SIZE)
+  ) mem_i (
+    .clka  (clk),
+    .ena   (ram_wr_en),
+    .wea   (1'b1),
+    .addra (ram_wr_addr),
+    .dia   (ram_wr_data),
+    .doa   (/* Write port only */),
+    .clkb  (clk),
+    .enb   (1'b1),
+    .web   (1'b0),
+    .addrb (ram_rd_addr),
+    .dib   (/* Read port only */),
+    .dob   (ram_rd_data)
+  );
+
+  // Pipeline read address into RAM
+  always @(posedge clk)
+    ram_rd_addr <= cam_rd_addr;
+
+  //-------------------------------------------------
+  // Find state machine
+  //-------------------------------------------------
+  // The lookup process has three cycles of latency
+  // - CAM lookup has a 1 cycle latency
+  // - The lookup address into the RAM is delayed by 1 cycle for timing
+  // - The RAM takes 1 cycle to produce data
+
+  localparam FIND_CYC = 3;
+
+  reg [FIND_CYC-1:0] find_key_stb_shreg = {FIND_CYC{1'b0}};
+  reg [FIND_CYC-2:0] find_match_shreg   = {(FIND_CYC-1){1'b0}};
+  reg                find_pending       = 1'b0;
+
+  wire find_busy = find_pending | find_key_stb;
+
+  // Delay the find valid signal to account for the latency 
+  // of the CAM and RAM
+  always @(posedge clk) begin
+    find_key_stb_shreg <= reset ? {FIND_CYC{1'b0}} :
+      {find_key_stb_shreg[FIND_CYC-2:0], find_key_stb};
+  end
+  assign find_res_stb = find_key_stb_shreg[FIND_CYC-1];
+
+  // Latch the find signal to compute pending
+  always @(posedge clk) begin
+    if (find_key_stb)
+      find_pending <= 1'b1;
+    else if (find_pending)
+      find_pending <= ~find_res_stb;
+  end
+
+  // Delay the match signal to account for the latency of the RAM
+  always @(posedge clk) begin
+    find_match_shreg <= reset ? {(FIND_CYC-1){1'b0}} :
+      {find_match_shreg[FIND_CYC-3:0], cam_rd_match};
+  end
+  assign find_res_match = find_match_shreg[FIND_CYC-2];
+
+
+  //-------------------------------------------------
+  // Insert state machine
+  //-------------------------------------------------
+
+  localparam [2:0] ST_IDLE            = 3'd0;
+  localparam [2:0] ST_WAIT_FIND       = 3'd1;
+  localparam [2:0] ST_CAM_READ        = 3'd2;
+  localparam [2:0] ST_CAM_CHECK_MATCH = 3'd3;
+  localparam [2:0] ST_CAM_RAM_WRITE   = 3'd4;
+  localparam [2:0] ST_CAM_WRITE_WAIT  = 3'd5;
+  localparam [2:0] ST_RAM_WRITE       = 3'd6;
+
+  reg [2:0] ins_state = ST_IDLE;
+
+  reg [KEY_WIDTH-1:0] ins_key_cached;
+  reg [VAL_WIDTH-1:0] ins_val_cached;
+  reg [SIZE-1:0]      write_addr = {SIZE{1'b0}};
+  reg [SIZE-1:0]      next_addr  = {SIZE{1'b0}};
+
+
+  always @(posedge clk) begin
+    if (reset) begin
+      ins_state <= ST_IDLE;
+      next_addr <= {SIZE{1'b0}};
+    end else begin
+      case (ins_state)
+
+        // Idle and waiting for an insert transaction 
+        //
+        ST_IDLE: begin
+          // Cache insertion parameters
+          if (insert_stb) begin
+            ins_key_cached <= insert_key;
+            ins_val_cached <= insert_val;
+            // Wait for find to finish
+            ins_state <= find_busy ? ST_WAIT_FIND : ST_CAM_READ;
+          end
+        end
+
+        // Wait for a find transaction to finish
+        //
+        ST_WAIT_FIND: begin
+          // Wait for find to finish
+          if (~find_busy)
+            ins_state <= ST_CAM_READ;
+        end
+
+        // Read the CAM to check if the key to insert already exists
+        //
+        ST_CAM_READ: begin
+          // Ensure that find always has priority
+          if (~find_key_stb)
+            ins_state <= ST_CAM_CHECK_MATCH;
+        end
+
+        // Look at the CAM match signal to evaluate if we skip writing the CAM
+        //
+        ST_CAM_CHECK_MATCH: begin
+          // If the CAM already has this key, then overwrite it
+          if (cam_rd_match) begin
+            ins_state <= ST_RAM_WRITE;
+            write_addr <= cam_rd_addr;
+          end else if (~cam_wr_busy) begin
+            ins_state <= ST_CAM_RAM_WRITE;
+            write_addr <= next_addr;
+            next_addr <= next_addr + 1'b1;
+          end
+        end
+
+        // Write the specified key to the CAM and value to the RAM
+        //
+        ST_CAM_RAM_WRITE: begin
+          ins_state <= ST_CAM_WRITE_WAIT;
+        end
+
+        // Wait for CAM write to finish
+        //
+        ST_CAM_WRITE_WAIT: begin
+          if (~cam_wr_busy) begin
+            ins_state <= ST_IDLE;
+            count <= next_addr;
+          end
+        end
+
+        // Write the specified value to the RAM
+        //
+        ST_RAM_WRITE: begin
+          ins_state <= ST_IDLE;
+          count <= next_addr;
+        end
+
+        default: begin
+          // We should not get here
+          ins_state <= ST_IDLE;
+        end
+      endcase
+    end
+  end
+
+  // CAM Read Port:
+  // - Find has priority so it can interrupt an insert
+  assign cam_rd_key = 
+    (ins_state != ST_CAM_READ || find_key_stb) ? find_key : ins_key_cached;
+
+  // RAM Write Port:
+  // - The RAM write enable is held high for 1 cycle
+  // - The address may come from a CAM lookup or could generated
+  assign ram_wr_en    = (ins_state == ST_RAM_WRITE || ins_state == ST_CAM_RAM_WRITE);
+  assign ram_wr_addr  = write_addr;
+  assign ram_wr_data  = ins_val_cached;
+
+  // CAM Write Port:
+  // - The CAM write enable is held high for 1 cycle
+  // - The address may come from a CAM lookup or could generated (same as RAM)
+  assign cam_wr_en    = (ins_state == ST_CAM_RAM_WRITE);
+  assign cam_wr_addr  = write_addr;
+  assign cam_wr_data  = ins_key_cached;
+
+  // Outputs
+  assign insert_busy  = (ins_state != ST_IDLE);
+  assign find_res_val = ram_rd_data;
+
+endmodule
diff --git a/fpga/usrp3/lib/control/mdio_master.v b/fpga/usrp3/lib/control/mdio_master.v
new file mode 100644
index 000000000..755fb94ce
--- /dev/null
+++ b/fpga/usrp3/lib/control/mdio_master.v
@@ -0,0 +1,772 @@
+//
+// Copyright 2016 Ettus Research
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module mdio_master #(
+   parameter        REG_AWIDTH  = 32,
+   parameter        REG_BASE    = 'h0,
+   parameter [7:0]  MDC_DIVIDER = 8'd200
+) (
+   // Clock and reset
+   input                  clk,
+   input                  rst,
+   // MDIO ports
+   output reg             mdc,
+   output reg             mdio_out,
+   output reg             mdio_tri,   // Assert to tristate driver.
+   input                  mdio_in,
+   // Register ports
+   input                  reg_wr_req,
+   input [REG_AWIDTH-1:0] reg_wr_addr,
+   input [31:0]           reg_wr_data,
+   input                  reg_rd_req,
+   input [REG_AWIDTH-1:0] reg_rd_addr,
+   output reg             reg_rd_resp,
+   output reg [31:0]      reg_rd_data
+);
+
+   localparam [7:0]
+      IDLE = 0,
+      PREAMBLE1 = 1,
+      PREAMBLE2 = 2,
+      PREAMBLE3 = 3,
+      PREAMBLE4 = 4,
+      PREAMBLE5 = 5,
+      PREAMBLE6 = 6,
+      PREAMBLE7 = 7,
+      PREAMBLE8 = 8,
+      PREAMBLE9 = 9,
+      PREAMBLE10 = 10,
+      PREAMBLE11 = 11,
+      PREAMBLE12 = 12,
+      PREAMBLE13 = 13,
+      PREAMBLE14 = 14,
+      PREAMBLE15 = 15,
+      PREAMBLE16 = 16,
+      PREAMBLE17 = 17,
+      PREAMBLE18 = 18,
+      PREAMBLE19 = 19,
+      PREAMBLE20 = 20,
+      PREAMBLE21 = 21,
+      PREAMBLE22 = 22,
+      PREAMBLE23 = 23,
+      PREAMBLE24 = 24,
+      PREAMBLE25 = 25,
+      PREAMBLE26 = 26,
+      PREAMBLE27 = 27,
+      PREAMBLE28 = 28,
+      PREAMBLE29 = 29,
+      PREAMBLE30 = 30,
+      PREAMBLE31 = 31,
+      PREAMBLE32 = 32,
+      START1 = 33,
+      C22_START2 = 34,
+      C45_START2 = 35,
+      OP1 = 36,
+      OP2 = 37,
+      PRTAD1 = 38,
+      PRTAD2 = 39,
+      PRTAD3 = 40,
+      PRTAD4 = 41,
+      PRTAD5 = 42,
+      DEVAD1 = 43,
+      DEVAD2 = 44,
+      DEVAD3 = 45,
+      DEVAD4 = 46,
+      DEVAD5 = 47,
+      TA1 = 48,
+      TA2 = 49,
+      TA3 = 50,
+      READ1 = 51,
+      READ2 = 52,
+      READ3 = 53,
+      READ4 = 54,
+      READ5 = 55,
+      READ6 = 56,
+      READ7 = 57,
+      READ8 = 58,
+      READ9 = 59,
+      READ10 = 60,
+      READ11 = 61,
+      READ12 = 62,
+      READ13 = 63,
+      READ14 = 64,
+      READ15 = 65,
+      READ16 = 66,
+      WRITE1 = 67,
+      WRITE2 = 68,
+      WRITE3 = 69,
+      WRITE4 = 70,
+      WRITE5 = 71,
+      WRITE6 = 72,
+      WRITE7 = 73,
+      WRITE8 = 74,
+      WRITE9 = 75,
+      WRITE10 = 76,
+      WRITE11 = 77,
+      WRITE12 = 78,
+      WRITE13 = 79,
+      WRITE14 = 80,
+      WRITE15 = 81,
+      WRITE16 = 82,
+      C45_ADDR1 = 83,
+      C45_ADDR2 = 84,
+      C45_ADDR3 = 85,
+      C45_ADDR4 = 86,
+      C45_ADDR5 = 87,
+      C45_ADDR6 = 88,
+      C45_ADDR7 = 89,
+      C45_ADDR8 = 90,
+      C45_ADDR9 = 91,
+      C45_ADDR10 = 92,
+      C45_ADDR11 = 93,
+      C45_ADDR12 = 94,
+      C45_ADDR13 = 95,
+      C45_ADDR14 = 96,
+      C45_ADDR15 = 97,
+      C45_ADDR16 = 98,
+      PREIDLE = 99
+   ;
+
+   localparam REG_MDIO_DATA         = REG_BASE + 'h0;
+   localparam REG_MDIO_ADDR         = REG_BASE + 'h4;
+   localparam REG_MDIO_OP           = REG_BASE + 'h8;
+   localparam REG_MDIO_CTRL_STATUS  = REG_BASE + 'hC;
+
+   reg [15:0]  mdio_read_data, mdio_write_data;
+   reg [15:0]  mdio_address;
+   reg [12:0]  mdio_operation;
+   reg [7:0]   mdc_clk_count;
+   reg         mdc_falling_edge;
+   reg         mdio_running;
+   reg         mdio_done;
+   reg [7:0]   state;
+
+   always @(posedge clk) begin
+      if (rst) begin
+         mdio_write_data <= 16'h0;
+         mdio_address    <= 16'h0;
+         mdio_operation  <= 13'h0;
+         mdio_running    <= 1'b0;
+      end else begin
+         // Handshake to MDIO state machine to reset running flag in status.
+         // Wait for falling MDC edge to prevent S/W race condition occuring
+         // where done flag still asserted but running flag now cleared (repeatedly).
+         if (mdio_done && mdc_falling_edge)
+            mdio_running <= 1'b0;
+
+         // Readable registers
+         if (reg_rd_req) begin
+            reg_rd_resp <= 1'b1;
+            case (reg_rd_addr)
+               REG_MDIO_DATA:
+                  reg_rd_data <= {16'h0, mdio_read_data};
+               REG_MDIO_ADDR:
+                  reg_rd_data <= {16'h0, mdio_address};
+               REG_MDIO_OP:
+                  reg_rd_data <= {16'h0, mdio_operation};
+               REG_MDIO_CTRL_STATUS:
+                  reg_rd_data <= {31'b0, mdio_running};
+               default:
+                  reg_rd_resp <= 1'b0;
+            endcase
+         end else if (reg_rd_resp) begin
+            reg_rd_resp <= 1'b0;
+         end
+
+         // Writable registers
+         if (reg_wr_req) begin
+            case(reg_wr_addr)
+               REG_MDIO_DATA:
+                  mdio_write_data <= reg_wr_data[15:0];
+               REG_MDIO_ADDR:
+                  mdio_address    <= reg_wr_data[15:0];
+               REG_MDIO_OP:
+                  mdio_operation  <= reg_wr_data[12:0];
+               REG_MDIO_CTRL_STATUS:
+                  if (reg_wr_data[0])
+                     mdio_running <= 1'b1;   // Trigger mdio operation here. Cleared by state machine at end of bus transaction.
+            endcase
+         end
+      end
+   end
+
+   //
+   // Produce mdc clock as a signal synchronously from Wishbone clock.
+   //
+   always @(posedge clk) begin
+      if (rst) begin
+         mdc_clk_count     <= 8'd1;
+         mdc               <= 1'b0;
+         mdc_falling_edge  <= 1'b0;
+      end else if (mdc_clk_count == (MDC_DIVIDER/2)) begin
+         mdc_clk_count     <= 8'd1;
+         mdc               <= ~mdc;
+         mdc_falling_edge  <= mdc;
+      end else begin
+         mdc_clk_count     <= mdc_clk_count + 8'd1;
+         mdc_falling_edge  <= 1'b0;
+      end
+   end
+
+   //
+   // MDIO state machine
+   //
+   always @(posedge clk) begin
+      if (rst) begin
+         mdio_tri <= 1'b1;
+         mdio_out <= 1'b0;
+         mdio_done <= 1'b0;
+         mdio_read_data <= 16'b0;
+         state <= IDLE;
+      end else if (mdc_falling_edge) begin
+         // This is the MDIO bus controller. Use falling edge of MDC.
+         mdio_tri <= 1'b1;
+         mdio_out <= 1'b0;
+         mdio_done <= 1'b0;
+         case(state)
+            // IDLE.
+            // In Clause 22 & 45 the master of the MDIO bus is tristate during idle.
+            IDLE: begin
+               mdio_tri <= 1'b1;
+               mdio_out <= 1'b0;
+               if (mdio_running)
+                  state <= PREAMBLE1;
+            end
+            // Preamble. All MDIO transactions begin witrh 32bits of 1 bits as a preamble.
+            PREAMBLE1: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= 1'b1;
+               state <= PREAMBLE2;
+            end
+            PREAMBLE2: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= 1'b1;
+               state <= PREAMBLE3;
+            end
+            PREAMBLE3: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= 1'b1;
+               state <= PREAMBLE4;
+            end
+            PREAMBLE4: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= 1'b1;
+               state <= PREAMBLE5;
+            end
+            PREAMBLE5: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= 1'b1;
+               state <= PREAMBLE6;
+            end
+            PREAMBLE6: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= 1'b1;
+               state <= PREAMBLE7;
+            end
+            PREAMBLE7: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= 1'b1;
+               state <= PREAMBLE8;
+            end
+            PREAMBLE8: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= 1'b1;
+               state <= PREAMBLE9;
+            end
+            PREAMBLE9: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= 1'b1;
+               state <= PREAMBLE10;
+            end
+            PREAMBLE10: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= 1'b1;
+               state <= PREAMBLE11;
+            end
+            PREAMBLE11: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= 1'b1;
+               state <= PREAMBLE12;
+            end
+            PREAMBLE12: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= 1'b1;
+               state <= PREAMBLE13;
+            end
+            PREAMBLE13: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= 1'b1;
+               state <= PREAMBLE14;
+            end
+            PREAMBLE14: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= 1'b1;
+               state <= PREAMBLE15;
+            end
+            PREAMBLE15: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= 1'b1;
+               state <= PREAMBLE16;
+            end
+            PREAMBLE16: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= 1'b1;
+               state <= PREAMBLE17;
+            end
+            PREAMBLE17: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= 1'b1;
+               state <= PREAMBLE18;
+            end
+            PREAMBLE18: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= 1'b1;
+               state <= PREAMBLE19;
+            end
+            PREAMBLE19: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= 1'b1;
+               state <= PREAMBLE20;
+            end
+            PREAMBLE20: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= 1'b1;
+               state <= PREAMBLE21;
+            end
+            PREAMBLE21: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= 1'b1;
+               state <= PREAMBLE22;
+            end
+            PREAMBLE22: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= 1'b1;
+               state <= PREAMBLE23;
+            end
+            PREAMBLE23: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= 1'b1;
+               state <= PREAMBLE24;
+            end
+            PREAMBLE24: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= 1'b1;
+               state <= PREAMBLE25;
+            end
+            PREAMBLE25: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= 1'b1;
+               state <= PREAMBLE26;
+            end
+            PREAMBLE26: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= 1'b1;
+               state <= PREAMBLE27;
+            end
+            PREAMBLE27: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= 1'b1;
+               state <= PREAMBLE28;
+            end
+            PREAMBLE28: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= 1'b1;
+               state <= PREAMBLE29;
+            end
+            PREAMBLE29: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= 1'b1;
+               state <= PREAMBLE30;
+            end
+            PREAMBLE30: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= 1'b1;
+               state <= PREAMBLE31;
+            end
+            PREAMBLE31: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= 1'b1;
+               state <= PREAMBLE32;
+            end
+            PREAMBLE32: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= 1'b1;
+               state <= START1;
+            end
+            // Start code for Clause 22 is 01 and Clause 45 is 00
+            START1: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= 1'b0;
+               if (mdio_operation[12])
+                  // Clause 45 bit set.
+                  state <= C45_START2;
+               else
+                  state <= C22_START2;
+            end
+            // 2nd Clause 22 start bit is a 1
+            C22_START2: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= 1'b1;
+               state <= OP1;
+            end
+            // 2nd Clause 45 start bit is a 0
+            C45_START2: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= 1'b0;
+               state <= OP1;
+            end
+            // Both Clause 22 & 45 use 2 bits for operation and are compatable.
+            // Note we don't screen here for illegal Clause 22 ops.
+            OP1: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= mdio_operation[11];
+               state <= OP2;
+            end
+            OP2: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= mdio_operation[10];
+               state <= PRTAD1;
+            end
+            // Both Clause 22 & 45 use 2 sucsessive 5 bit fields to form a hierarchical address
+            // though it's used slightly different between the 2 standards.
+            PRTAD1: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= mdio_operation[9];
+               state <= PRTAD2;
+            end
+            PRTAD2: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= mdio_operation[8];
+               state <= PRTAD3;
+            end
+            PRTAD3: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= mdio_operation[7];
+               state <= PRTAD4;
+            end
+            PRTAD4: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= mdio_operation[6];
+               state <= PRTAD5;
+            end
+            PRTAD5: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= mdio_operation[5];
+               state <= DEVAD1;
+            end
+            DEVAD1: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= mdio_operation[4];
+               state <= DEVAD2;
+            end
+            DEVAD2: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= mdio_operation[3];
+               state <= DEVAD3;
+            end
+            DEVAD3: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= mdio_operation[2];
+               state <= DEVAD4;
+            end
+            DEVAD4: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= mdio_operation[1];
+               state <= DEVAD5;
+            end
+            DEVAD5: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= mdio_operation[0];
+               state <= TA1;
+            end
+            // Both Clause 22 & Clause 45 use the same turn around on the bus.
+            // Reads have Z as the first bit and 0 driven by the slave for the 2nd bit.
+            // Note that slaves drive the bus on the rising edge of MDC.
+            // Writes and Address cycles have 10 driven by the master.
+            TA1: begin
+               if (mdio_operation[11] == 1'b0) // Write/Address
+               begin
+                  mdio_tri <= 1'b0;
+                  mdio_out <= 1'b1;
+                  state <= TA2;
+               end
+               else // Read
+               begin
+                  mdio_tri <= 1'b1;
+                  state <= TA3;
+               end
+            end
+            TA2: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= 1'b0;
+               if ( !mdio_operation[12]) // Clause 22 Write
+                  state <= WRITE1;
+               else if (mdio_operation[10]) // Clause 45 Write
+                  state <= WRITE1;
+               else // Clause 45 ADDRESS
+                  state <= C45_ADDR1;
+            end
+            TA3: begin
+               mdio_tri <= 1'b1;
+               state <= READ1;
+            end
+            // Clause 22 Reads and both forms of clause 45 Reads have the same bus transaction from here out.
+            READ1: begin
+               mdio_tri <= 1'b1;
+               mdio_read_data[15] <= mdio_in;
+               state <= READ2;
+            end
+            READ2: begin
+               mdio_tri <= 1'b1;
+               mdio_read_data[14] <= mdio_in;
+               state <= READ3;
+            end
+            READ3: begin
+               mdio_tri <= 1'b1;
+               mdio_read_data[13] <= mdio_in;
+               state <= READ4;
+            end
+            READ4: begin
+               mdio_tri <= 1'b1;
+               mdio_read_data[12] <= mdio_in;
+               state <= READ5;
+            end
+            READ5: begin
+               mdio_tri <= 1'b1;
+               mdio_read_data[11] <= mdio_in;
+               state <= READ6;
+            end
+            READ6: begin
+               mdio_tri <= 1'b1;
+               mdio_read_data[10] <= mdio_in;
+               state <= READ7;
+            end
+            READ7: begin
+               mdio_tri <= 1'b1;
+               mdio_read_data[9] <= mdio_in;
+               state <= READ8;
+            end
+            READ8: begin
+               mdio_tri <= 1'b1;
+               mdio_read_data[8] <= mdio_in;
+               state <= READ9;
+            end
+            READ9: begin
+               mdio_tri <= 1'b1;
+               mdio_read_data[7] <= mdio_in;
+               state <= READ10;
+            end
+            READ10: begin
+               mdio_tri <= 1'b1;
+               mdio_read_data[6] <= mdio_in;
+               state <= READ11;
+            end
+            READ11: begin
+               mdio_tri <= 1'b1;
+               mdio_read_data[5] <= mdio_in;
+               state <= READ12;
+            end
+            READ12: begin
+               mdio_tri <= 1'b1;
+               mdio_read_data[4] <= mdio_in;
+               state <= READ13;
+            end
+            READ13: begin
+               mdio_tri <= 1'b1;
+               mdio_read_data[3] <= mdio_in;
+               state <= READ14;
+            end
+            READ14: begin
+               mdio_tri <= 1'b1;
+               mdio_read_data[2] <= mdio_in;
+               state <= READ15;
+            end
+            READ15: begin
+               mdio_tri <= 1'b1;
+               mdio_read_data[1] <= mdio_in;
+               state <= READ16;
+            end
+            READ16: begin
+               mdio_tri <= 1'b1;
+               mdio_read_data[0] <= mdio_in;
+               state <= PREIDLE;
+               mdio_done <= 1'b1;
+            end
+            // Write 16bits of data for all types of Write.
+            WRITE1: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= mdio_write_data[15];
+               state <= WRITE2;
+            end
+            WRITE2: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= mdio_write_data[14];
+               state <= WRITE3;
+            end
+            WRITE3: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= mdio_write_data[13];
+               state <= WRITE4;
+            end
+            WRITE4: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= mdio_write_data[12];
+               state <= WRITE5;
+            end
+            WRITE5: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= mdio_write_data[11];
+               state <= WRITE6;
+            end
+            WRITE6: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= mdio_write_data[10];
+               state <= WRITE7;
+            end
+            WRITE7: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= mdio_write_data[9];
+               state <= WRITE8;
+            end
+            WRITE8: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= mdio_write_data[8];
+               state <= WRITE9;
+            end
+            WRITE9: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= mdio_write_data[7];
+               state <= WRITE10;
+            end
+            WRITE10: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= mdio_write_data[6];
+               state <= WRITE11;
+            end
+            WRITE11: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= mdio_write_data[5];
+               state <= WRITE12;
+            end
+            WRITE12: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= mdio_write_data[4];
+               state <= WRITE13;
+            end
+            WRITE13: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= mdio_write_data[3];
+               state <= WRITE14;
+            end
+            WRITE14: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= mdio_write_data[2];
+               state <= WRITE15;
+            end
+            WRITE15: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= mdio_write_data[1];
+               state <= WRITE16;
+            end
+            WRITE16: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= mdio_write_data[0];
+               state <= PREIDLE;
+               mdio_done <= 1'b1;
+            end
+            // Write 16bits of address for a Clause 45 Address transaction
+            C45_ADDR1: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= mdio_address[15];
+               state <= C45_ADDR2;
+            end
+            C45_ADDR2: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= mdio_address[14];
+               state <= C45_ADDR3;
+            end
+            C45_ADDR3: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= mdio_address[13];
+               state <= C45_ADDR4;
+            end
+            C45_ADDR4: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= mdio_address[12];
+               state <= C45_ADDR5;
+            end
+            C45_ADDR5: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= mdio_address[11];
+               state <= C45_ADDR6;
+            end
+            C45_ADDR6: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= mdio_address[10];
+               state <= C45_ADDR7;
+            end
+            C45_ADDR7: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= mdio_address[9];
+               state <= C45_ADDR8;
+            end
+            C45_ADDR8: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= mdio_address[8];
+               state <= C45_ADDR9;
+            end
+            C45_ADDR9: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= mdio_address[7];
+               state <= C45_ADDR10;
+            end
+            C45_ADDR10: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= mdio_address[6];
+               state <= C45_ADDR11;
+            end
+            C45_ADDR11: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= mdio_address[5];
+               state <= C45_ADDR12;
+            end
+            C45_ADDR12: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= mdio_address[4];
+               state <= C45_ADDR13;
+            end
+            C45_ADDR13: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= mdio_address[3];
+               state <= C45_ADDR14;
+            end
+            C45_ADDR14: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= mdio_address[2];
+               state <= C45_ADDR15;
+            end
+            C45_ADDR15: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= mdio_address[1];
+               state <= C45_ADDR16;
+            end
+            C45_ADDR16: begin
+               mdio_tri <= 1'b0;
+               mdio_out <= mdio_address[0];
+               state <= PREIDLE;
+               mdio_done <= 1'b1;
+            end
+            // PREIDLE allows the mdio_running bit to reset.
+            PREIDLE: begin
+               state <= IDLE;
+            end
+         endcase // case(state)
+      end // if (mdc_falling_edge)
+   end
+
+endmodule
+
diff --git a/fpga/usrp3/lib/control/por_gen.v b/fpga/usrp3/lib/control/por_gen.v
new file mode 100644
index 000000000..b16ceb5bf
--- /dev/null
+++ b/fpga/usrp3/lib/control/por_gen.v
@@ -0,0 +1,28 @@
+//
+// Copyright 2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+
+module por_gen
+  (input clk,
+   output reset_out);
+
+   reg 		por_rst;
+   reg [7:0] 	por_counter = 8'h0;
+
+   always @(posedge clk)
+     if (por_counter != 8'h55)
+       begin
+          por_counter <= por_counter + 8'h1;
+          por_rst <= 1'b1;
+       end
+     else
+       por_rst <= 1'b0;
+
+   assign reset_out = por_rst;
+
+endmodule // por_gen
diff --git a/fpga/usrp3/lib/control/priority_encoder.v b/fpga/usrp3/lib/control/priority_encoder.v
new file mode 100644
index 000000000..8e84fb57a
--- /dev/null
+++ b/fpga/usrp3/lib/control/priority_encoder.v
@@ -0,0 +1,55 @@
+//
+// Copyright 2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+`define log2(N) ( N < 2    ? 0 : \
+                  N < 4    ? 1 : \
+                  N < 8    ? 2 : \
+                  N < 16   ? 3 : \
+                  N < 32   ? 4 : \
+                  N < 64   ? 5 : \
+                  N < 128  ? 6 : \
+                  N < 256  ? 7 : \
+                  N < 512  ? 8 : \
+                  N < 1024 ? 9 : \
+                             10 \
+                )
+
+module priority_encoder
+#(
+  parameter WIDTH = 16
+)
+(
+  input  [WIDTH-1:0]        in,
+  output [`log2(WIDTH)-1:0] out
+);
+
+  wire [WIDTH-1:0] one_hot;
+
+  // the priority encoder spits out the position
+  // of the leading bit as one hot coding
+  priority_encoder_one_hot #
+  (
+    .WIDTH(WIDTH)
+  )
+  prio_one_hot0
+  (
+    .in(in),
+    .out(one_hot)
+  );
+
+  // binary encoder turns the one hot coding
+  // into binary encoding
+  binary_encoder #
+  (
+    .WIDTH(WIDTH)
+  )
+  binary_enc0
+  (
+    .in(one_hot),
+    .out(out)
+  );
+endmodule
diff --git a/fpga/usrp3/lib/control/priority_encoder_one_hot.v b/fpga/usrp3/lib/control/priority_encoder_one_hot.v
new file mode 100644
index 000000000..d2839ddde
--- /dev/null
+++ b/fpga/usrp3/lib/control/priority_encoder_one_hot.v
@@ -0,0 +1,34 @@
+//
+// Copyright 2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module priority_encoder_one_hot
+#(
+  parameter WIDTH = 16
+)
+(
+  input  [WIDTH-1:0]        in,
+  output [WIDTH-1:0]        out
+);
+
+  wire [WIDTH-1:0] in_rev;
+  wire [WIDTH-1:0] in_rev_inv_po = ~in_rev + 1;
+
+  wire [WIDTH-1:0] mask;
+
+  generate
+  genvar i,j;
+
+  for (i=0; i<WIDTH; i=i+1)
+      assign in_rev[i] = in[WIDTH-1-i];
+
+  for (j=0; j<WIDTH; j=j+1)
+      assign mask[j]  = in_rev_inv_po[WIDTH-1-j];
+  endgenerate
+
+  assign out = in & mask;
+
+endmodule
diff --git a/fpga/usrp3/lib/control/pulse_stretch.v b/fpga/usrp3/lib/control/pulse_stretch.v
new file mode 100644
index 000000000..2235286e1
--- /dev/null
+++ b/fpga/usrp3/lib/control/pulse_stretch.v
@@ -0,0 +1,79 @@
+//
+// Copyright 2017 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module:  pulse_stretch
+//
+// Description:
+//
+//   Pulse stretcher. Takes any input pulse that is SCALE+2 clock cycles or 
+//   less and outputs a pulse that is SCALE+1 clock cycles. However, if an 
+//   input pulse is longer than SCALE+2 clock cycles then the output pulse 
+//   repeats. If more than one pulse is input within SCALE+2 clock cycles then 
+//   additional pulses will be ignored.
+//
+// Examples (SCALE = 2):
+//
+//   Clock            _/‾\_/‾\_/‾\_/‾\_/‾\_/‾\_/‾\_/‾\_/‾\_/‾\_/‾\_/‾\_/‾\_/‾\_
+//
+//
+//   pulse            _/‾‾‾\_______________/‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾\___________________
+//
+//   pulse_stretched  _____/‾‾‾‾‾‾‾‾‾‾‾\_______/‾‾‾‾‾‾‾‾‾‾‾\___________________
+//
+//
+//   pulse            _/‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾\___________________________________
+//
+//   pulse_stretched  _____/‾‾‾‾‾‾‾‾‾‾‾\___/‾‾‾‾‾‾‾‾‾‾‾\_______________________
+//
+//
+//   pulse            _/‾‾‾\_______/‾‾‾\___/‾‾‾\_______/‾‾‾‾‾‾‾\_______________
+//
+//   pulse_stretched  _____/‾‾‾‾‾‾‾‾‾‾‾\_______/‾‾‾‾‾‾‾‾‾‾‾\___/‾‾‾‾‾‾‾‾‾‾‾\___
+
+// Parameters:
+//
+//   SCALE : The number of clock cycles to add to a single cycle pulse. Or, the
+//           number of clock cycles, minus 1, for the output pulse.
+//
+
+module pulse_stretch #(
+  parameter SCALE = 64'd12_500_000
+)(
+  input clk,
+  input rst,
+  input pulse,
+  output pulse_stretched
+);
+
+  reg [$clog2(SCALE+1)-1:0] count = 'd0;
+  reg             state = 1'b0;
+
+  always @ (posedge clk)
+    if (rst) begin
+      state <= 1'b0;
+      count <= 'd0;
+    end
+    else begin
+      case (state)
+
+      1'b0: begin
+        if (pulse) begin
+          state <= 1'b1;
+          count <= 'd0;
+        end
+      end
+
+      1'b1: begin
+        if (count == SCALE)
+          state <= 1'b0;
+        else
+          count <= count + 1'b1;
+      end
+      endcase
+    end
+
+  assign pulse_stretched = (state == 1'b1);
+
+endmodule
diff --git a/fpga/usrp3/lib/control/pulse_stretch_min.v b/fpga/usrp3/lib/control/pulse_stretch_min.v
new file mode 100644
index 000000000..84bf3ecd9
--- /dev/null
+++ b/fpga/usrp3/lib/control/pulse_stretch_min.v
@@ -0,0 +1,79 @@
+//
+// Copyright 2017 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: pulse_stretch_min
+//
+// Description:
+//
+//   Pulse stretcher, to guarantee a minimum pulse width. Takes a short input 
+//   pulse and outputs a pulse that is LENGTH clock cycles long. If the input 
+//   pulse is longer than LENGTH then the output pulse will be the same length 
+//   as the input pulse. The output is registered so the output is delayed by 
+//   one clock cycle relative to the input. If more than one pulse is input 
+//   within LENGTH+1 clock cycles, then the extra input pulses will not 
+//   generate output pulses.
+//
+// Examples:  (LENGTH = 3)
+//
+//   Clock      _/‾\_/‾\_/‾\_/‾\_/‾\_/‾\_/‾\_/‾\_/‾\_/‾\_/‾\_/‾\_/‾\_/‾\_/‾\_
+//
+//
+//   pulse_in   _/‾‾‾\_______________/‾‾‾‾‾‾‾\___________/‾‾‾‾‾‾‾‾‾‾‾\_______
+//
+//   pulse_out  _____/‾‾‾‾‾‾‾‾‾‾‾\_______/‾‾‾‾‾‾‾‾‾‾‾\_______/‾‾‾‾‾‾‾‾‾‾‾\___
+//
+//
+//   pulse_in   _/‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾\______________/‾‾‾\_______/‾‾‾\______
+//
+//   pulse_out  ______/‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾\______________/‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾\__
+//
+//
+// Parameters:
+//
+//   LENGTH : Length of the minimum pulse to output, in clock cycles.
+//
+
+module pulse_stretch_min #(
+  parameter LENGTH = 4
+) (
+  input  wire clk,
+  input  wire rst,
+  input  wire pulse_in,
+  output reg  pulse_out = 0
+);
+
+  reg [$clog2(LENGTH)-1:0] count = 0;
+  reg                      state = 0;
+
+  always @ (posedge clk)
+    if (rst) begin
+      state     <= 0;
+      count     <= 0;
+      pulse_out <= 0;
+    end
+    else begin
+      case (state)
+
+      1'b0: begin
+        if (pulse_in) begin
+          state     <= 1;
+          pulse_out <= 1;
+          count     <= 0;
+        end
+      end
+
+      1'b1: begin
+        if (count == LENGTH-1) begin
+          if (!pulse_in) begin
+            state     <= 0;
+            pulse_out <= 0;
+          end
+        end else
+          count <= count + 1;
+      end
+      endcase
+    end
+
+endmodule
diff --git a/fpga/usrp3/lib/control/pulse_synchronizer.v b/fpga/usrp3/lib/control/pulse_synchronizer.v
new file mode 100644
index 000000000..af3460878
--- /dev/null
+++ b/fpga/usrp3/lib/control/pulse_synchronizer.v
@@ -0,0 +1,70 @@
+//
+// Copyright 2018 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: pulse_synchronizer
+// Description:
+// - Synchronizes a single-cycle pulse or an edge from one
+//   clock domain to another
+// - Clocks A and B can be asynchronous
+//
+
+module pulse_synchronizer #(
+  parameter MODE   = "PULSE", // Capture mode {PULSE, POSEDGE, NEGEDGE}
+  parameter STAGES = 2        // Number of synchronizer stages
+) (
+  input   clk_a,    // Clock A
+  input   rst_a,    // Reset in clock domain A
+  input   pulse_a,  // Pulse in clock domain A to synchronize
+  output  busy_a,   // Synchronizer is busy (pulse_a ignored when asserted)
+  input   clk_b,    // Clock B
+  output  pulse_b   // Pulse in clock domain B
+);
+  // Trigger logic based on the capture mode
+  wire trigger;
+  generate if (MODE == "POSEDGE") begin
+    reg pulse_a_del_pe = 1'b0;
+    always @ (posedge clk_a)
+      pulse_a_del_pe <= rst_a ? 1'b0 : pulse_a;
+    assign trigger = pulse_a & ~pulse_a_del_pe;
+  end else if (MODE == "NEGEDGE") begin
+    reg pulse_a_del_ne = 1'b1;
+    always @ (posedge clk_a)
+      pulse_a_del_ne <= rst_a ? 1'b1 : pulse_a;
+    assign trigger = ~pulse_a & pulse_a_del_ne;
+  end else begin
+    assign trigger = pulse_a;
+  end endgenerate
+
+  // Translate pulse/edge to a level and synchronize that into the B domain
+  reg pulse_toggle_a = 1'b0;
+  always @(posedge clk_a) begin
+    pulse_toggle_a <= rst_a ? 1'b0 : (pulse_toggle_a ^ (trigger & ~busy_a));
+  end
+
+  wire pulse_toggle_b;
+  reg  pulse_toggle_b_del = 1'b0;
+  wire handshake_toggle_a;
+
+  synchronizer #(
+    .STAGES(STAGES), .INITIAL_VAL(0)
+  ) toggle_sync_i (
+    .clk(clk_b), .rst(1'b0), .in(pulse_toggle_a), .out(pulse_toggle_b)
+  );
+
+  // Handshake toggle signal back into the A domain to deassert busy
+  synchronizer #(
+    .STAGES(STAGES), .INITIAL_VAL(0)
+  ) handshake_sync_i (
+    .clk(clk_a), .rst(1'b0), .in(pulse_toggle_b_del), .out(handshake_toggle_a)
+  );
+
+  always @(posedge clk_b) begin
+    pulse_toggle_b_del <= pulse_toggle_b;
+  end
+
+  assign pulse_b = pulse_toggle_b_del ^ pulse_toggle_b;
+  assign busy_a = pulse_toggle_a ^ handshake_toggle_a;
+
+endmodule
\ No newline at end of file
diff --git a/fpga/usrp3/lib/control/ram_2port.v b/fpga/usrp3/lib/control/ram_2port.v
new file mode 100644
index 000000000..96db90061
--- /dev/null
+++ b/fpga/usrp3/lib/control/ram_2port.v
@@ -0,0 +1,120 @@
+//
+// Copyright 2011 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Description
+//  This code implements a parameterizable true dual port memory 
+//  (both ports can read and write). If an enable is not necessary
+//  it may be tied off.
+//
+// Note
+//  This module requires the ram_2port_impl.vh header file. The
+//  header is included multiple times with different values of
+//  the RAM_DIRECTIVE macro to create different implementations of the
+//  RAM. An implementation is chosen in ram_2port based on the 
+//  user parameter for RAM_TYPE.
+
+// Mode: AUTOMATIC
+`define RAM_DIRECTIVE
+`define RAM_MOD_NAME ram_2port_impl_auto
+`include "ram_2port_impl.vh"
+`undef RAM_MOD_NAME
+`undef RAM_DIRECTIVE
+
+// Mode: REG
+`define RAM_DIRECTIVE (* ram_style = "registers" *)
+`define RAM_MOD_NAME ram_2port_impl_reg
+`include "ram_2port_impl.vh"
+`undef RAM_MOD_NAME
+`undef RAM_DIRECTIVE
+
+// Mode: LUTRAM
+`define RAM_DIRECTIVE (* ram_style = "distributed" *)
+`define RAM_MOD_NAME ram_2port_impl_lutram
+`include "ram_2port_impl.vh"
+`undef RAM_MOD_NAME
+`undef RAM_DIRECTIVE
+
+// Mode: BRAM
+`define RAM_DIRECTIVE (* ram_style = "block" *)
+`define RAM_MOD_NAME ram_2port_impl_bram
+`include "ram_2port_impl.vh"
+`undef RAM_MOD_NAME
+`undef RAM_DIRECTIVE
+
+// Mode: URAM
+`define RAM_DIRECTIVE (* ram_style = "ultra" *)
+`define RAM_MOD_NAME ram_2port_impl_uram
+`include "ram_2port_impl.vh"
+`undef RAM_MOD_NAME
+`undef RAM_DIRECTIVE
+
+module ram_2port #(
+  parameter DWIDTH    = 32,           // Width of the memory block
+  parameter AWIDTH    = 9,            // log2 of the depth of the memory block
+  parameter RW_MODE   = "READ-FIRST", // Read-write mode {READ-FIRST, WRITE-FIRST, NO-CHANGE}
+  parameter RAM_TYPE  = "AUTOMATIC",  // Type of RAM to infer {AUTOMATIC, REG, LUTRAM, BRAM, URAM}
+  parameter OUT_REG   = 0,            // Instantiate an output register? (+1 cycle of read latency)
+  parameter INIT_FILE = ""            // Optionally initialize memory with this file
+) (
+  input  wire              clka,
+  input  wire              ena,
+  input  wire              wea,
+  input  wire [AWIDTH-1:0] addra,
+  input  wire [DWIDTH-1:0] dia,
+  output wire [DWIDTH-1:0] doa,
+
+  input  wire              clkb,
+  input  wire              enb,
+  input  wire              web,
+  input  wire [AWIDTH-1:0] addrb,
+  input  wire [DWIDTH-1:0] dib,
+  output wire [DWIDTH-1:0] dob
+);
+
+  generate
+    if (RAM_TYPE == "URAM")
+      ram_2port_impl_uram #(
+        .DWIDTH(DWIDTH), .AWIDTH(AWIDTH), .RW_MODE(RW_MODE),
+        .OUT_REG(OUT_REG), .INIT_FILE(INIT_FILE)
+      ) impl (
+        .clka(clka), .ena(ena), .wea(wea), .addra(addra), .dia(dia), .doa(doa),
+        .clkb(clkb), .enb(enb), .web(web), .addrb(addrb), .dib(dib), .dob(dob)
+      );
+    else if (RAM_TYPE == "BRAM")
+      ram_2port_impl_bram #(
+        .DWIDTH(DWIDTH), .AWIDTH(AWIDTH), .RW_MODE(RW_MODE),
+        .OUT_REG(OUT_REG), .INIT_FILE(INIT_FILE)
+      ) impl (
+        .clka(clka), .ena(ena), .wea(wea), .addra(addra), .dia(dia), .doa(doa),
+        .clkb(clkb), .enb(enb), .web(web), .addrb(addrb), .dib(dib), .dob(dob)
+      );
+    else if (RAM_TYPE == "LUTRAM")
+      ram_2port_impl_lutram #(
+        .DWIDTH(DWIDTH), .AWIDTH(AWIDTH), .RW_MODE(RW_MODE),
+        .OUT_REG(OUT_REG), .INIT_FILE(INIT_FILE)
+      ) impl (
+        .clka(clka), .ena(ena), .wea(wea), .addra(addra), .dia(dia), .doa(doa),
+        .clkb(clkb), .enb(enb), .web(web), .addrb(addrb), .dib(dib), .dob(dob)
+      );
+    else if (RAM_TYPE == "REG")
+      ram_2port_impl_reg #(
+        .DWIDTH(DWIDTH), .AWIDTH(AWIDTH), .RW_MODE(RW_MODE),
+        .OUT_REG(OUT_REG), .INIT_FILE(INIT_FILE)
+      ) impl (
+        .clka(clka), .ena(ena), .wea(wea), .addra(addra), .dia(dia), .doa(doa),
+        .clkb(clkb), .enb(enb), .web(web), .addrb(addrb), .dib(dib), .dob(dob)
+      );
+    else
+      ram_2port_impl_auto #(
+        .DWIDTH(DWIDTH), .AWIDTH(AWIDTH), .RW_MODE(RW_MODE),
+        .OUT_REG(OUT_REG), .INIT_FILE(INIT_FILE)
+      ) impl (
+        .clka(clka), .ena(ena), .wea(wea), .addra(addra), .dia(dia), .doa(doa),
+        .clkb(clkb), .enb(enb), .web(web), .addrb(addrb), .dib(dib), .dob(dob)
+      );
+  endgenerate
+
+endmodule
diff --git a/fpga/usrp3/lib/control/ram_2port_impl.vh b/fpga/usrp3/lib/control/ram_2port_impl.vh
new file mode 100644
index 000000000..8f8f3bab3
--- /dev/null
+++ b/fpga/usrp3/lib/control/ram_2port_impl.vh
@@ -0,0 +1,129 @@
+//
+// Copyright 2011 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Used by ram_2port.v
+// Requires `RAM_MOD_NAME and `RAM_DIRECTIVE to be defined
+
+module `RAM_MOD_NAME #(
+  parameter DWIDTH    = 32,           // Width of the memory block
+  parameter AWIDTH    = 9,            // log2 of the depth of the memory block
+  parameter RW_MODE   = "READ-FIRST", // Read-write mode {READ-FIRST, WRITE-FIRST, NO-CHANGE}
+  parameter OUT_REG   = 0,            // Instantiate an output register? (+1 cycle of read latency)
+  parameter INIT_FILE = ""            // Optionally initialize memory with this file
+) (
+  input  wire              clka,
+  input  wire              ena,
+  input  wire              wea,
+  input  wire [AWIDTH-1:0] addra,
+  input  wire [DWIDTH-1:0] dia,
+  output wire [DWIDTH-1:0] doa,
+
+  input  wire              clkb,
+  input  wire              enb,
+  input  wire              web,
+  input  wire [AWIDTH-1:0] addrb,
+  input  wire [DWIDTH-1:0] dib,
+  output wire [DWIDTH-1:0] dob
+);
+
+  `RAM_DIRECTIVE reg [DWIDTH-1:0] ram [(1<<AWIDTH)-1:0];
+
+  // Initialize ram to a specified file or to all zeros to match hardware
+  generate if (INIT_FILE != "") begin
+    initial
+      $readmemh(INIT_FILE, ram, 0, (1<<AWIDTH)-1);
+  end else begin
+    integer i;
+    initial
+      for (i = 0; i < (1<<AWIDTH); i = i + 1)
+        ram[i] = {DWIDTH{1'b0}};
+  end endgenerate
+
+  reg [DWIDTH-1:0] doa_r = 'h0, dob_r = 'h0;
+  generate if (OUT_REG == 1) begin
+    // A 2 clock cycle read latency with improve clock-to-out timing
+    reg [DWIDTH-1:0] doa_rr = 'h0, dob_rr = 'h0;
+
+    always @(posedge clka)
+      if (ena)
+        doa_rr <= doa_r;
+
+    always @(posedge clkb)
+      if (enb)
+        dob_rr <= dob_r;
+
+    assign doa = doa_rr;
+    assign dob = dob_rr;
+  end else begin
+    // A 1 clock cycle read latency at the cost of a longer clock-to-out timing
+    assign doa = doa_r;
+    assign dob = dob_r;
+  end endgenerate
+
+  generate if (RW_MODE == "READ-FIRST") begin
+    // When data is written, the prior memory contents at the write
+    // address are presented on the output port.
+    always @(posedge clka) begin
+      if (ena) begin
+        if (wea)
+          ram[addra] <= dia;
+        doa_r <= ram[addra];
+      end
+    end
+    always @(posedge clkb) begin
+      if (enb) begin
+        if (web)
+          ram[addrb] <= dib;
+        dob_r <= ram[addrb];
+      end
+    end
+
+  end else if (RW_MODE == "WRITE-FIRST") begin
+    // The data being written to the RAM also resides on the output port.
+    always @(posedge clka) begin
+      if (ena) begin
+        if (wea) begin
+          ram[addra] <= dia;
+          doa_r <= dia;
+        end else begin
+          doa_r <= ram[addra];
+        end
+      end
+    end
+    always @(posedge clkb) begin
+      if (enb) begin
+        if (web) begin
+          ram[addrb] <= dib;
+          dob_r <= dib;
+        end else begin
+          dob_r <= ram[addrb];
+        end
+      end
+    end
+
+  end else begin
+    // This is a no change RAM which retains the last read value on the output during writes
+    // which is the most power efficient mode.
+    always @(posedge clka) begin
+      if (ena) begin
+        if (wea)
+          ram[addra] <= dia;
+        else
+          doa_r <= ram[addra];
+      end
+    end
+    always @(posedge clkb) begin
+      if (enb) begin
+        if (web)
+          ram[addrb] <= dib;
+        else
+          dob_r <= ram[addrb];
+      end
+    end
+
+  end endgenerate
+
+endmodule
diff --git a/fpga/usrp3/lib/control/regport_resp_mux.v b/fpga/usrp3/lib/control/regport_resp_mux.v
new file mode 100644
index 000000000..93048bec8
--- /dev/null
+++ b/fpga/usrp3/lib/control/regport_resp_mux.v
@@ -0,0 +1,46 @@
+//
+// Copyright 2016 Ettus Research
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module regport_resp_mux #(
+  parameter WIDTH      = 32,
+  parameter NUM_SLAVES = 2
+)(
+  input                            clk,
+  input                            reset,
+
+  input [NUM_SLAVES-1:0]           sla_rd_resp,
+  input [(NUM_SLAVES*WIDTH)-1:0]   sla_rd_data,
+
+  output reg                       mst_rd_resp,
+  output reg [WIDTH-1:0]           mst_rd_data
+);
+  // Treat sla_rd_resp as a one-hot bus.
+  // If multiple resp lines are asserted at the same time, then
+  // it is a violation of the register port protocol
+
+  wire [NUM_SLAVES-1:0] bit_options[0:WIDTH-1];
+  wire [WIDTH-1:0]      data_out;
+
+  genvar i, b;
+  generate
+     for (b = 0; b < WIDTH; b = b + 1) begin
+        for (i = 0; i < NUM_SLAVES; i = i + 1) begin
+           assign bit_options[b][i] = sla_rd_data[(i*WIDTH)+b];
+        end
+        assign data_out[b] = |(bit_options[b] & sla_rd_resp);
+     end
+  endgenerate
+
+  always @(posedge clk) begin
+     mst_rd_data <= data_out;
+     if (reset)
+        mst_rd_resp <= 1'b0;
+     else
+        mst_rd_resp <= |(sla_rd_resp);
+  end
+
+endmodule
diff --git a/fpga/usrp3/lib/control/regport_to_settingsbus.v b/fpga/usrp3/lib/control/regport_to_settingsbus.v
new file mode 100644
index 000000000..532380ef3
--- /dev/null
+++ b/fpga/usrp3/lib/control/regport_to_settingsbus.v
@@ -0,0 +1,63 @@
+/////////////////////////////////////////////////////////////////////
+//
+// Copyright 2017 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: regport_to_settingsbus
+// Description:
+//   Converts regport write bus to the a setting bus
+//   ADDRESSING: Set to "WORD" in case of settings bus. The settings bus
+//   uses word addressing and hence the address needs to be shifted by
+//   to convert to set_addr.
+//
+/////////////////////////////////////////////////////////////////////
+
+module regport_to_settingsbus #(
+  parameter BASE   = 14'h0,
+  parameter END_ADDR = 14'h3FFF,
+  parameter DWIDTH = 32,
+  parameter AWIDTH = 14,
+  parameter SR_AWIDTH = 12,
+  // Dealign for settings bus by shifting by 2
+  parameter ADDRESSING = "WORD",
+  parameter SHIFT = $clog2(DWIDTH/8)
+)(
+  input reset,
+  input clk,
+  input reg_wr_req,
+  input [AWIDTH-1:0] reg_wr_addr,
+  input [DWIDTH-1:0] reg_wr_data,
+
+  output reg set_stb,
+  output reg [SR_AWIDTH-1:0] set_addr,
+  output reg [DWIDTH-1:0] set_data
+);
+
+  wire set_stb_int;
+  wire [DWIDTH-1:0] set_data_int;
+  wire [SR_AWIDTH-1:0] set_addr_base;
+  wire [SR_AWIDTH-1:0] set_addr_int;
+
+  // Strobe asserted only when address is between BASE and END ADDR
+  assign set_stb_int = reg_wr_req && (reg_wr_addr >= BASE) && (reg_wr_addr <= END_ADDR);
+  assign set_addr_base = reg_wr_addr - BASE;
+  // Shift by 2 in case of setting bus
+  assign set_addr_int = (ADDRESSING == "WORD") ? {{SHIFT{1'b0}}, set_addr_base[SR_AWIDTH-1:SHIFT]}
+                                               : set_addr_base[SR_AWIDTH-1:0];
+  assign set_data_int = reg_wr_data;
+
+  // Adding a pipeline stage
+  always @(posedge clk) begin
+    if (reset) begin
+      set_stb  <= 'b0;
+      set_addr <= 'h0;
+      set_data <= 'h0;
+    end else begin
+      set_stb  <= set_stb_int;
+      set_addr <= set_addr_int;
+      set_data <= set_data_int;
+    end
+  end
+
+endmodule // regport_to_settingsbus
diff --git a/fpga/usrp3/lib/control/regport_to_xbar_settingsbus.v b/fpga/usrp3/lib/control/regport_to_xbar_settingsbus.v
new file mode 100644
index 000000000..be050dd20
--- /dev/null
+++ b/fpga/usrp3/lib/control/regport_to_xbar_settingsbus.v
@@ -0,0 +1,113 @@
+/////////////////////////////////////////////////////////////////////
+//
+// Copyright 2017 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: regport_to_xbar_settingsbus
+// Description:
+//   Converts regport to xbar setting bus.
+//   The module is designed only for the crossbar. The readback bus for the
+//   rfnoc crossbar reads from the same address as it writes to. Also
+//   there is an extra cycle delay in read data in the crossbar, which is
+//   why the rb_stb needs to be delayed by a cycle.
+//
+//   ADDRESSING: Set to "WORD" in case of settings bus. The settings bus
+//   uses word addressing and hence the address needs to be shifted by
+//   to convert to set_addr.
+//
+/////////////////////////////////////////////////////////////////////
+
+module regport_to_xbar_settingsbus #(
+  parameter BASE   = 14'h0,
+  parameter END_ADDR = 14'h3FFF,
+  parameter DWIDTH = 32,
+  parameter AWIDTH = 14,
+  parameter SR_AWIDTH = 12,
+  // Dealign for settings bus by shifting by 2
+  parameter ADDRESSING = "WORD",
+  parameter SHIFT = $clog2(DWIDTH/8)
+  )(
+  input                   clk,
+  input                   reset,
+
+  input                   reg_wr_req,
+  input [AWIDTH-1:0]      reg_wr_addr,
+  input [DWIDTH-1:0]      reg_wr_data,
+
+  input                   reg_rd_req,
+  input [AWIDTH-1:0]      reg_rd_addr,
+  output [DWIDTH-1:0]     reg_rd_data,
+  output                  reg_rd_resp,
+
+  output                  set_stb,
+  output [SR_AWIDTH-1:0]  set_addr,
+  output [DWIDTH-1:0]     set_data,
+
+  output                  rb_stb,
+  output [SR_AWIDTH-1:0]  rb_addr,
+  input  [DWIDTH-1:0]     rb_data
+);
+
+  reg               reg_rd_req_delay;
+  reg               reg_rd_req_delay2;
+  wire [AWIDTH-1:0] set_addr_int;
+  reg [AWIDTH-1:0]  rb_addr_int;
+
+  always @(posedge clk) begin
+    if (reset) begin
+      reg_rd_req_delay <= 1'b0;
+      reg_rd_req_delay2 <= 1'b0;
+      rb_addr_int     <= 'd0;
+    end
+    else if (reg_rd_req) begin
+      rb_addr_int <= reg_rd_addr - BASE;
+      reg_rd_req_delay <= 1'b1;
+    end
+    else if (reg_rd_req_delay) begin
+      reg_rd_req_delay2 <= 1'b1;
+      reg_rd_req_delay <= 1'b0;
+    end
+    // Deassert after two clock cycles
+    else if (reg_rd_req_delay2) begin
+      reg_rd_req_delay <= 1'b0;
+      reg_rd_req_delay2 <= 1'b0;
+      rb_addr_int     <= 'd0;
+    end
+    else begin
+      reg_rd_req_delay <= 1'b0;
+      reg_rd_req_delay2 <= 1'b0;
+      rb_addr_int     <= 'd0;
+    end
+  end
+
+  // Write mode of settings bus
+  regport_to_settingsbus #(
+    .BASE(BASE),
+    .END_ADDR(END_ADDR),
+    .DWIDTH(DWIDTH),
+    .AWIDTH(AWIDTH),
+    .SR_AWIDTH(SR_AWIDTH),
+    .ADDRESSING(ADDRESSING)
+   ) xbar_write_settings_bus (
+    .clk(clk),
+    .reset(reset),
+    .reg_wr_req(reg_wr_req),
+    .reg_wr_addr(reg_wr_addr),
+    .reg_wr_data(reg_wr_data),
+
+    .set_stb(set_stb),
+    .set_addr(set_addr),
+    .set_data(set_data)
+  );
+
+  assign rb_addr = (ADDRESSING == "WORD") ? {{SHIFT{1'b0}}, rb_addr_int[SR_AWIDTH-1:SHIFT]}
+                                          : rb_addr_int[SR_AWIDTH-1:0];
+  // Strobe asserted two cycle after read request only when address is between BASE and END ADDR
+  // This is specific to the xbar as the xbar delays read data by an extra clock
+  // cycle to relax timing.
+  assign rb_stb  = reg_rd_req_delay2 && (reg_rd_addr >= BASE) && (reg_rd_addr <= END_ADDR);
+  assign reg_rd_resp = rb_stb;
+  assign reg_rd_data = rb_data;
+
+endmodule
diff --git a/fpga/usrp3/lib/control/reset_sync.v b/fpga/usrp3/lib/control/reset_sync.v
new file mode 100644
index 000000000..2e13abfd4
--- /dev/null
+++ b/fpga/usrp3/lib/control/reset_sync.v
@@ -0,0 +1,37 @@
+//
+// Copyright 2011 Ettus Research LLC
+// Copyright 2018-2019 Ettus Research, a National Instruments Brand
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// The purpose of this module is to synchronize a reset from one clock domain
+// to another. The reset_in signal must be driven by a glitch-free source.
+//
+
+module reset_sync (
+  // clock for the output reset
+  input  clk,
+  // glitch-free input reset
+  input  reset_in,
+  // output reset in the clk domain
+  output reg reset_out);
+
+  wire reset_c;
+
+  synchronizer #(
+    // The input reset is async to the output clk domain... so timing should not be
+    // analyzed here!
+    .FALSE_PATH_TO_IN(1),
+    // Assert reset_out by default. When clk starts toggling the downstream logic will
+    // be in reset for at least 10 clk cycles. This allows the clock to settle (if needed)
+    // and the reset to propagate fully to all logic.
+    .INITIAL_VAL(1),
+    .STAGES(10)
+  ) reset_double_sync (
+    .clk(clk), .rst(1'b0), .in(reset_in), .out(reset_c)
+  );
+
+  always @(posedge clk)
+      reset_out <= reset_c;
+
+endmodule // reset_sync
diff --git a/fpga/usrp3/lib/control/s7_icap_wb.v b/fpga/usrp3/lib/control/s7_icap_wb.v
new file mode 100644
index 000000000..114d370eb
--- /dev/null
+++ b/fpga/usrp3/lib/control/s7_icap_wb.v
@@ -0,0 +1,144 @@
+//
+// Copyright 2011-2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+//
+// Refer to SelectMAP and ICAP docs in UG470
+//
+
+module s7_icap_wb
+  (
+   input clk, 
+   input reset,
+   input cyc_i, 
+   input stb_i, 
+   input we_i, 
+   output ack_o,
+   input [31:0] dat_i, 
+   output [31:0] dat_o
+   );
+
+   reg 		 rdwrb, csib;
+   
+
+   reg [2:0]    icap_state;
+   localparam ICAP_IDLE  = 0;
+   localparam ICAP_WR0   = 1;
+   localparam ICAP_WR1   = 2;
+   localparam ICAP_RD0   = 3;
+   localparam ICAP_RD1   = 4;
+
+   localparam IDLE = 1'b1;
+   localparam ACTIVE = 1'b0;
+   localparam READ = 1'b1;
+   localparam WRITE = 1'b0;
+   
+
+   always @(posedge clk)
+     if(reset) begin
+	rdwrb <= READ;
+	csib <= IDLE;
+       icap_state <= ICAP_IDLE;
+     end
+     else
+       case(icap_state)
+	 //
+	 // In IDLE state waiting for a READ or WRITE to be signalled from the WB bus.
+	 // (In this state rdwrb can flip state without effect because ICAP is not selected)
+	 //
+         ICAP_IDLE :
+           begin
+              if(stb_i & cyc_i) begin
+                 if(we_i) begin
+		    // Start WRITE, assert RDWR_B LOW whilst CSI_B remains HIGH.
+		    rdwrb <= WRITE;
+		    csib <= IDLE;
+		    icap_state <= ICAP_WR0;
+		 end else begin
+		    // Start READ
+		    rdwrb <= READ;
+		    csib <= IDLE;
+		    icap_state <= ICAP_RD0;
+		 end
+	      end else begin
+		 // Stay IDLE
+		 rdwrb <= READ;
+		 csib <= IDLE;
+		 icap_state <= ICAP_IDLE;
+	      end
+	   end // case: ICAP_IDLE
+	 //
+	 // First cycle of WRITE.  
+	 // Next cycle assert RDWR_B LOW and assert CSI_B LOW. 
+	 //
+         ICAP_WR0 : begin
+	    rdwrb <= WRITE;
+	    csib <= ACTIVE;
+            icap_state <= ICAP_WR1;
+	 end
+	 //
+	 // Second cycle of WRITE.
+	 // Next cycle assert RDWR_B LOW and assert CSI_B HIGH whilst transitioning to IDLE state
+	 //
+         ICAP_WR1 : begin
+	    rdwrb <= WRITE;
+	    csib <= IDLE;
+            icap_state <= ICAP_IDLE;
+	 end
+	 //
+	 // First cycle of READ.
+	 // Next cycle assert RDWR_B HIGH and assert CSI_B LOW. 
+	 //
+         ICAP_RD0 : begin
+            rdwrb <= READ;
+	    csib <= ACTIVE;
+            icap_state <= ICAP_WR1;
+	 end
+	 //
+	 // Second cycle of READ.
+	 // Next cycle assert RDWR_B HIGH and assert CSI_B HIGH whilst transitioning to IDLE state
+	 //
+         ICAP_RD1 : begin
+	    rdwrb <= READ;
+	    csib <= IDLE;
+            icap_state <= ICAP_IDLE;
+	 end
+        
+       endcase // case (icap_state)
+
+   assign ack_o = (icap_state == ICAP_WR1) | (icap_state == ICAP_RD1);
+   //assign debug_out = {17'd0, BUSY, dat_i[7:0], ~CE, ICAPCLK, ~WRITE, icap_state};
+ 
+
+   ICAPE2  #(
+	     .DEVICE_ID(32'h03651093),
+	     .ICAP_WIDTH("X32"),
+	     .SIM_CFG_FILE_NAME("NONE")
+	     )
+     ICAPE2_inst  (
+		   .O(/*dat_o[31:0]*/),
+		   .CLK(clk),     // Rising edge referenced for both reads and writes.
+		   .CSIB(csib),        // CSIB = 0 to select ICAP
+		   .I(dat_i[31:0]),   // Bitswaped as per SELECTMAP (See UG470 page 40)
+		   .RDWRB(rdwrb)     // RDWB = 0 for WRITE, = 1 for READ
+		   );
+   
+   assign dat_0 = 32'h0;
+   
+endmodule // s3a_icap_wb
diff --git a/fpga/usrp3/lib/control/serial_to_settings.v b/fpga/usrp3/lib/control/serial_to_settings.v
new file mode 100644
index 000000000..180191fa5
--- /dev/null
+++ b/fpga/usrp3/lib/control/serial_to_settings.v
@@ -0,0 +1,126 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module serial_to_settings
+  (
+   input clk,
+   input reset,
+   // Serial signals (async)
+   input scl,
+   input sda,
+   // Settngs bus out
+   output reg set_stb,
+   output reg [7:0] set_addr,
+   output reg [31:0] set_data,
+   // Debug
+   output [31:0] debug
+   );
+
+   reg [2:0] 	 state;
+   
+   localparam 	 SEARCH = 3'h0;
+   localparam 	 ADDRESS = 3'h1;
+   localparam 	 DATA = 3'h2;
+   localparam 	 STOP1 = 3'h3;
+   localparam 	 STOP2 = 3'h4;
+ 	 
+   reg 		 scl_pre_reg, scl_reg, scl_reg2;
+   reg 		 sda_pre_reg, sda_reg, sda_reg2;
+   reg [4:0] 	 counter;
+
+ 
+     always @(posedge clk) begin
+      scl_reg2 <= scl_reg;
+      scl_reg <= scl_pre_reg;
+      scl_pre_reg <= scl;
+      sda_reg2 <= sda_reg;
+      sda_reg <= sda_pre_reg;
+      sda_pre_reg <= sda;
+   end
+
+   
+   always @(posedge clk)
+     if (reset) begin
+	state <= SEARCH;
+	counter <= 0;
+	set_addr <= 0;
+	set_data <= 0;
+	set_stb <= 0;
+     end else begin
+	case(state)
+	  //
+	  // Search for I2C like start indication: SDA goes low whilst clock is high.
+	  //
+	  SEARCH: begin
+	     set_stb <= 0;
+	     // Look for START.
+	     if (scl_reg && scl_reg2 && !sda_reg && sda_reg2) begin
+		state <= ADDRESS;
+		counter <= 0;
+	     end
+	  end
+	  //
+	  // Count 8 Address bits.
+	  // Master changes SDA on falling edge of SCL, we sample on the rising edge.
+	  //
+	  ADDRESS: begin
+	     if (scl_reg && !scl_reg2) begin
+		set_addr[7:0] <= {set_addr[6:0],sda_reg};
+		if (counter == 7) begin
+		   state <= DATA;
+		   counter <= 0;
+		end else
+		  counter <= counter + 1;		  
+	    end
+	  end
+	  //
+	  // Count 32 data bits.
+	  // Master changes SDA on falling edge of SCL, we sample on the rising edge.
+	  //
+	  DATA: begin
+	     if (scl_reg && !scl_reg2) begin
+		set_data[31:0] <= {set_data[30:0],sda_reg};
+		if (counter == 31) begin
+		   state <= STOP1;
+		   counter <= 0;
+		end else
+		  counter <= counter + 1;		  
+	    end
+	  end
+	  //
+	  // Looks for rising SCL edge before STOP bit.
+	  //
+	  STOP1: begin
+	     if (scl_reg && !scl_reg2) begin
+		state <= STOP2;
+	     end
+	  end
+	  //
+	  // Looks for STOP bit
+	  //
+	  STOP2: begin
+	     if (scl_reg && scl_reg2 && sda_reg && !sda_reg2) begin
+		state <= SEARCH;
+		counter <= 0;
+		set_stb <= 1;
+	     end
+	  end
+	  
+	endcase // case(state)
+     end // else: !if(reset)
+
+   assign debug =
+		 {
+		  counter[4:0],
+		  state[2:0],
+		  scl_reg,
+		  sda_reg
+		  };
+   
+
+
+endmodule // serial_to_settings
diff --git a/fpga/usrp3/lib/control/serial_to_settings_tb.v b/fpga/usrp3/lib/control/serial_to_settings_tb.v
new file mode 100644
index 000000000..d3688f216
--- /dev/null
+++ b/fpga/usrp3/lib/control/serial_to_settings_tb.v
@@ -0,0 +1,86 @@
+//
+// Copyright 2014 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module serial_to_settings_tb();
+
+
+
+   reg clk;
+   reg reset;
+
+   wire scl;
+   wire sda;
+   wire set_stb;
+   wire [7:0] set_addr;
+   wire [31:0] set_data;
+
+   //
+   // These registers optionaly used
+   // to drive nets through procedural assignments in test bench.
+   // These drivers default to tri-stated.
+   //
+   reg 	       scl_r;
+   reg 	       sda_r;
+
+   assign      scl = scl_r;
+   assign      sda = sda_r;
+
+   initial
+     begin
+	scl_r <= 1'bz;
+	sda_r <= 1'bz;
+     end
+   
+   
+
+     serial_to_settings   serial_to_settings_i
+     (
+      .clk(clk),
+      .reset(reset),
+      // Serial signals (async)
+      .scl(scl),
+      .sda(sda),
+      // Settngs bus out
+      .set_stb(set_stb),
+      .set_addr(set_addr),
+      .set_data(set_data)
+      );
+
+   // Nasty HAck to convert settings to wishbone crudely.
+   reg 	       wb_stb;
+   wire        wb_ack_o;
+   
+   
+   always @(posedge clk)
+     if (reset)
+       wb_stb <= 0;
+     else
+       wb_stb <= set_stb ? 1 : ((wb_ack_o) ? 0 : wb_stb);
+   
+     simple_uart debug_uart
+     (
+      .clk_i(clk), 
+      .rst_i(reset),
+      .we_i(wb_stb), 
+      .stb_i(wb_stb), 
+      .cyc_i(wb_stb), 
+      .ack_o(wb_ack_o),
+      .adr_i(set_addr[2:0]), 
+      .dat_i(set_data[31:0]), 
+      .dat_o(),
+      .rx_int_o(), 
+      .tx_int_o(), 
+      .tx_o(txd), 
+      .rx_i(rxd), 
+      .baud_o()
+      );
+   
+   //
+   // Bring in a simulation script here
+   //
+   `include "simulation_script.v"
+
+endmodule
diff --git a/fpga/usrp3/lib/control/setting_reg.v b/fpga/usrp3/lib/control/setting_reg.v
new file mode 100644
index 000000000..09bf66286
--- /dev/null
+++ b/fpga/usrp3/lib/control/setting_reg.v
@@ -0,0 +1,38 @@
+//
+// Copyright 2011-2012 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+//----------------------------------------------------------------------
+//-- A settings register is a peripheral for the settings register bus.
+//-- When the settings register sees strobe abd a matching address,
+//-- the outputs will be become registered to the given input bus.
+//----------------------------------------------------------------------
+
+module setting_reg
+  #(parameter my_addr = 0, 
+    parameter awidth = 8,
+    parameter width = 32,
+    parameter at_reset=0)
+    (input clk, input rst, input strobe, input wire [awidth-1:0] addr,
+     input wire [31:0] in, output reg [width-1:0] out, output reg changed);
+   
+   always @(posedge clk)
+     if(rst)
+       begin
+	  out <= at_reset;
+	  changed <= 1'b0;
+       end
+     else
+       if(strobe & (my_addr==addr))
+	 begin
+	    out <= in[width-1:0];
+	    changed <= 1'b1;
+	 end
+       else
+	 changed <= 1'b0;
+   
+endmodule // setting_reg
diff --git a/fpga/usrp3/lib/control/settings_bus_mux.v b/fpga/usrp3/lib/control/settings_bus_mux.v
new file mode 100644
index 000000000..8d120c9c7
--- /dev/null
+++ b/fpga/usrp3/lib/control/settings_bus_mux.v
@@ -0,0 +1,44 @@
+//
+// Copyright 2016 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Mux multiple settings buses
+
+module settings_bus_mux #(
+  parameter PRIO=0, // 0 = Round robin, 1 = Lower ports get priority (see axi_mux)
+  parameter AWIDTH=8,
+  parameter DWIDTH=32,
+  parameter FIFO_SIZE=1,
+  parameter NUM_BUSES=2)
+(
+  input clk, input reset, input clear,
+  input [NUM_BUSES-1:0] in_set_stb, input [NUM_BUSES*AWIDTH-1:0] in_set_addr, input [NUM_BUSES*DWIDTH-1:0] in_set_data,
+  output out_set_stb, output [AWIDTH-1:0] out_set_addr, output [DWIDTH-1:0] out_set_data, input ready
+);
+
+  wire [NUM_BUSES*(AWIDTH+DWIDTH)-1:0] i_tdata;
+  generate
+    if(NUM_BUSES <= 1) begin
+      assign out_set_stb = in_set_stb;
+      assign out_set_addr = in_set_addr;
+      assign out_set_data = in_set_data;
+    end else begin
+      genvar i;
+        for (i = 0; i < NUM_BUSES; i = i + 1) begin
+          assign i_tdata[(i+1)*(AWIDTH+DWIDTH)-1:i*(AWIDTH+DWIDTH)] = {in_set_addr[(i+1)*AWIDTH-1:i*AWIDTH],in_set_data[(i+1)*DWIDTH-1:i*DWIDTH]};
+        end
+      axi_mux #(
+        .PRIO(PRIO),
+        .WIDTH(AWIDTH+DWIDTH),
+        .PRE_FIFO_SIZE($clog2(NUM_BUSES)),
+        .POST_FIFO_SIZE(FIFO_SIZE),
+        .SIZE(NUM_BUSES))
+      axi_mux (
+        .clk(clk), .reset(reset), .clear(clear),
+        .i_tdata(i_tdata), .i_tlast({NUM_BUSES{1'b1}}), .i_tvalid(in_set_stb), .i_tready(),
+        .o_tdata({out_set_addr,out_set_data}), .o_tlast(), .o_tvalid(out_set_stb), .o_tready(ready));
+    end
+  endgenerate
+endmodule
\ No newline at end of file
diff --git a/fpga/usrp3/lib/control/settings_bus_timed_2clk.v b/fpga/usrp3/lib/control/settings_bus_timed_2clk.v
new file mode 100644
index 000000000..2b62ffd26
--- /dev/null
+++ b/fpga/usrp3/lib/control/settings_bus_timed_2clk.v
@@ -0,0 +1,170 @@
+//
+// Copyright 2018 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: settings_bus_timed_2clk
+// Description:
+// - Stores settings bus transaction in a FIFO and 
+//   releases them based on VITA time input
+// - Also moves the settings bus to the timebase
+//   clock domain
+//
+
+module settings_bus_timed_2clk #(
+  parameter SR_AWIDTH     = 8,
+  parameter SR_DWIDTH     = 32,
+  parameter RB_AWIDTH     = 8,
+  parameter RB_DWIDTH     = 64,
+  parameter TIMED_CMDS_EN = 0
+) (
+  input                  sb_clk,          // Settings bus clock
+  input                  sb_rst,          // Reset (sb_clk)
+  input                  tb_clk,          // Timebase clock
+  input                  tb_rst,          // Reset (tb_clk)
+
+  input  [63:0]          vita_time,       // Current timebase time
+                         
+  input                  s_set_stb,       // Settings bus strobe
+  input  [SR_AWIDTH-1:0] s_set_addr,      // Settings address
+  input  [SR_DWIDTH-1:0] s_set_data,      // Settings data
+  input                  s_set_has_time,  // Is this a timed command?
+  input  [63:0]          s_set_time,      // Command time
+  output                 s_set_pending,   // Is settings transaction pending?
+  input  [RB_AWIDTH-1:0] s_rb_addr,       // Readback address
+  output                 s_rb_stb,        // Readback data strobe
+  output [RB_DWIDTH-1:0] s_rb_data,       // Readback data value
+
+  output                 m_set_stb,       // Settings bus strobe
+  output [SR_AWIDTH-1:0] m_set_addr,      // Settings address
+  output [SR_DWIDTH-1:0] m_set_data,      // Settings data
+  output                 m_set_has_time,  // Is this a timed command?
+  output [63:0]          m_set_time,      // Command time
+  input                  m_set_pending,   // Is settings transaction pending?
+  output [RB_AWIDTH-1:0] m_rb_addr,       // Readback address
+  input                  m_rb_stb,        // Readback data strobe
+  input  [RB_DWIDTH-1:0] m_rb_data        // Readback data value
+);
+
+  // States for input and output state machines
+  localparam [2:0] ST_IDLE        = 3'd0; // Nothing is happening on the bus
+  localparam [2:0] ST_SET_ISSUED  = 3'd1; // A settings transaction has been issued
+  localparam [2:0] ST_SET_PENDING = 3'd2; // A settings transaction is pending
+  localparam [2:0] ST_RB_PENDING  = 3'd3; // Waiting for readback data
+  localparam [2:0] ST_RB_DONE     = 3'd4; // Readback data is valid
+  
+  wire rb_valid;
+
+  // Input state machine
+  reg [2:0] in_state = ST_IDLE;
+  always @(posedge sb_clk) begin
+    if (sb_rst) begin
+      in_state <= ST_IDLE;
+    end else begin
+      case (in_state)
+        ST_IDLE: begin
+          if (s_set_stb) begin
+            in_state <= ST_SET_PENDING;
+          end
+        end
+        ST_SET_PENDING: begin
+          if (rb_valid) begin
+            in_state <= ST_RB_DONE;
+          end
+        end
+        ST_RB_DONE: begin
+          in_state <= ST_IDLE;
+        end
+        default: begin
+          in_state <= ST_IDLE;
+        end
+      endcase
+    end
+  end
+  assign s_set_pending = (in_state == ST_SET_PENDING);
+  assign s_rb_stb = (in_state == ST_RB_DONE);
+
+  // Clock crossing FIFO (settings)
+  // TODO: Look into a more efficient implementation for a single element
+  //       clock crossing FIFO.
+  wire set_pending, set_finished;
+  axi_fifo_2clk #(
+    .WIDTH(SR_AWIDTH+SR_DWIDTH+1+64+RB_AWIDTH), .SIZE(0)
+  ) sb_2clk_fifo_i (
+    .i_aclk(sb_clk), .reset(sb_rst),
+    .i_tdata({s_set_addr, s_set_data, s_set_has_time, s_set_time, s_rb_addr}),
+    .i_tvalid(s_set_stb), .i_tready(/* Ignored: FIFO may not have an exact size*/),
+    .o_aclk(tb_clk),
+    .o_tdata({m_set_addr, m_set_data, m_set_has_time, m_set_time, m_rb_addr}),
+    .o_tvalid(set_pending), .o_tready(set_finished)
+  );
+
+  // Time compare logic
+  // If ~has_time then pass the transaction through, otherwise wait for time
+  // to tick up to command time
+  wire now, late;
+  wire go = ((TIMED_CMDS_EN == 1) && m_set_has_time) ? (now | late) : 1'b1;
+
+  // If this is a timed command then vita_time == m_set_time one cycle before
+  // strobe is asserted i.e. timed strobe assertion has a one cycle latency
+  time_compare time_compare (
+    .clk(tb_clk), .reset(tb_rst),
+    .time_now(vita_time), .trigger_time(m_set_time),
+    .now(now), .early(), .late(late), .too_early()
+  );
+
+  // Clock crossing FIFO (readback)
+  reg [RB_DWIDTH-1:0] cached_rb_data;
+  axi_fifo_2clk #(
+    .WIDTH(RB_DWIDTH), .SIZE(0)
+  ) rbdata_2clk_fifo_i (
+    .reset(tb_rst),
+    .i_aclk(tb_clk), .i_tdata(cached_rb_data), .i_tvalid(set_finished), .i_tready(),
+    .o_aclk(sb_clk), .o_tdata(s_rb_data), .o_tvalid(rb_valid), .o_tready(s_rb_stb)
+  );
+
+  // Output state machine
+  reg [2:0] out_state = ST_IDLE;
+  always @(posedge tb_clk) begin
+    if (tb_rst) begin
+      out_state <= ST_IDLE;
+    end else begin
+      case (out_state)
+        ST_IDLE: begin
+          if (go & set_pending) begin
+            out_state <= ST_SET_ISSUED;
+          end
+        end
+        ST_SET_ISSUED: begin
+          out_state <= ST_SET_PENDING;
+        end
+        ST_SET_PENDING: begin
+          if (~m_set_pending) begin
+            if (m_rb_stb) begin
+              out_state <= ST_RB_DONE;
+              cached_rb_data <= m_rb_data;
+            end else begin
+              out_state <= ST_RB_PENDING;
+            end
+          end
+        end
+        ST_RB_PENDING: begin
+          if (m_rb_stb) begin
+            out_state <= ST_RB_DONE;
+            cached_rb_data <= m_rb_data;
+          end
+        end
+        ST_RB_DONE: begin
+          out_state <= ST_IDLE;
+        end
+        default: begin
+          out_state <= ST_IDLE;
+        end
+      endcase
+    end
+  end
+
+  assign m_set_stb = (out_state == ST_SET_ISSUED);
+  assign set_finished = (out_state == ST_RB_DONE);
+
+endmodule
diff --git a/fpga/usrp3/lib/control/simple_i2c_core.v b/fpga/usrp3/lib/control/simple_i2c_core.v
new file mode 100644
index 000000000..fbbd2e5a1
--- /dev/null
+++ b/fpga/usrp3/lib/control/simple_i2c_core.v
@@ -0,0 +1,107 @@
+//
+// Copyright 2012 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+// Simple I2C core
+
+// Settings reg map:
+//
+// BASE+0 control register
+//   byte0 - control bits, data byte, or command bits, prescaler
+//   byte1 - what to do? (documented in cpp file)
+//      write prescaler lo
+//      write prescaler hi
+//      write control
+//      write data
+//      write command
+//      read data
+//      read status
+//
+
+// Readback:
+//
+// byte0 has readback value based on the last read command
+//
+
+module simple_i2c_core
+    #(
+        //settings register base address
+        parameter BASE = 0,
+
+        //i2c line level at reset
+        parameter ARST_LVL = 1
+    )
+    (
+        //clock and synchronous reset
+        input clock, input reset,
+
+        //32-bit settings bus inputs
+        input set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+        //32-bit data readback
+        output reg [31:0] readback,
+
+        //read is high when i2c core can begin another transaction
+        output reg ready,
+
+        // I2C signals
+        // i2c clock line
+        input  scl_pad_i,       // SCL-line input
+        output scl_pad_o,       // SCL-line output (always 1'b0)
+        output scl_padoen_o,    // SCL-line output enable (active low)
+
+        // i2c data line
+        input  sda_pad_i,       // SDA-line input
+        output sda_pad_o,       // SDA-line output (always 1'b0)
+        output sda_padoen_o,    // SDA-line output enable (active low)
+
+        //optional debug output
+        output [31:0] debug
+    );
+
+    //declare command settings register
+    wire [7:0] sr_what, sr_data;
+    wire sr_changed;
+    setting_reg #(.my_addr(BASE+0),.width(16)) i2c_cmd_sr(
+        .clk(clock),.rst(reset),.strobe(set_stb),.addr(set_addr),.in(set_data),
+        .out({sr_what, sr_data}),.changed(sr_changed));
+
+    //declare wb interface signals
+    wire [2:0] wb_addr;
+    wire [7:0] wb_data_mosi;
+    wire [7:0] wb_data_miso;
+    wire wb_we, wb_stb, wb_cyc;
+    wire wb_ack;
+
+    //create wishbone-based i2c core
+    i2c_master_top #(.ARST_LVL(ARST_LVL)) i2c 
+     (.wb_clk_i(clock),.wb_rst_i(reset),.arst_i(1'b0), 
+      .wb_adr_i(wb_addr),.wb_dat_i(wb_data_mosi),.wb_dat_o(wb_data_miso),
+      .wb_we_i(wb_we),.wb_stb_i(wb_stb),.wb_cyc_i(wb_cyc),
+      .wb_ack_o(wb_ack),.wb_inta_o(),
+      .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_padoen_o),
+      .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_padoen_o) );
+
+    //not ready between setting register and wishbone ack
+    always @(posedge clock) begin
+        if (reset || wb_ack) ready <= 1;
+        else if (sr_changed) ready <= 0;
+    end
+
+    //register wishbone data on every ack
+    always @(posedge clock) begin
+        if (wb_ack) readback <= {24'b0, wb_data_miso};
+    end
+
+    //assign wishbone signals
+    assign wb_addr = sr_what[2:0];
+    assign wb_stb = sr_changed;
+    assign wb_we = wb_stb && sr_what[3];
+    assign wb_cyc = wb_stb;
+    assign wb_data_mosi = sr_data;
+
+endmodule //simple_i2c_core
diff --git a/fpga/usrp3/lib/control/simple_spi_core.v b/fpga/usrp3/lib/control/simple_spi_core.v
new file mode 100644
index 000000000..dd94b1b2d
--- /dev/null
+++ b/fpga/usrp3/lib/control/simple_spi_core.v
@@ -0,0 +1,229 @@
+//
+// Copyright 2012 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+// Simple SPI core, the simplest, yet complete spi core I can think of
+
+// Settings register controlled.
+// 2 settings regs, control and data
+// 1 32-bit readback and status signal
+
+// Settings reg map:
+//
+// BASE+0 divider setting
+// bits [15:0] spi clock divider
+//
+// BASE+1 configuration input
+// bits [23:0] slave select, bit0 = slave0 enabled
+// bits [29:24] num bits (1 through 32)
+// bit [30] data input edge = in data bit latched on rising edge of clock
+// bit [31] data output edge = out data bit latched on rising edge of clock
+//
+// BASE+2 input data
+// Writing this register begins a spi transaction.
+// Bits are latched out from bit 0.
+// Therefore, load this register in reverse.
+//
+// Readback
+// Bits are latched into bit 0.
+// Therefore, data will be in-order.
+
+module simple_spi_core
+    #(
+        //settings register base address
+        parameter BASE = 0,
+
+        //width of serial enables (up to 24 is possible)
+        parameter WIDTH = 8,
+
+        //idle state of the spi clock
+        parameter CLK_IDLE = 0,
+
+        //idle state of the serial enables
+        parameter SEN_IDLE = 24'hffffff
+    )
+    (
+        //clock and synchronous reset
+        input clock, input reset,
+
+        //32-bit settings bus inputs
+        input set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+        //32-bit data readback
+        output [31:0] readback,
+        output reg readback_stb,
+
+        //read is high when spi core can begin another transaction
+        output ready,
+
+        //spi interface, slave selects, clock, data in, data out
+        output [WIDTH-1:0] sen,
+        output sclk,
+        output reg mosi,
+        input miso,
+
+        //optional debug output
+        output [31:0] debug
+    );
+
+    wire [15:0] sclk_divider;
+    setting_reg #(.my_addr(BASE+0),.width(16)) divider_sr(
+        .clk(clock),.rst(reset),.strobe(set_stb),.addr(set_addr),.in(set_data),
+        .out(sclk_divider),.changed());
+
+    wire [23:0] slave_select;
+    wire [5:0] num_bits;
+    wire datain_edge, dataout_edge;
+    setting_reg #(.my_addr(BASE+1),.width(32)) ctrl_sr(
+        .clk(clock),.rst(reset),.strobe(set_stb),.addr(set_addr),.in(set_data),
+        .out({dataout_edge, datain_edge, num_bits, slave_select}),.changed());
+
+    wire [31:0] mosi_data;
+    wire trigger_spi;
+    setting_reg #(.my_addr(BASE+2),.width(32)) data_sr(
+        .clk(clock),.rst(reset),.strobe(set_stb),.addr(set_addr),.in(set_data),
+        .out(mosi_data),.changed(trigger_spi));
+
+    localparam WAIT_TRIG = 0;
+    localparam PRE_IDLE = 1;
+    localparam CLK_REG = 2;
+    localparam CLK_INV = 3;
+    localparam POST_IDLE = 4;
+    localparam IDLE_SEN = 5;
+
+    reg [2:0] state;
+
+    reg ready_reg;
+    assign ready = ready_reg && ~trigger_spi;
+
+    //serial clock either idles or is in one of two clock states
+    reg sclk_reg;
+    assign sclk = sclk_reg;
+
+    //serial enables either idle or enabled based on state
+    // IJB. One pipeline stage to break critical path from register in I/O pads.
+    wire sen_is_idle = (state == WAIT_TRIG) || (state == IDLE_SEN);
+    wire [23:0] sen24 = (sen_is_idle)? SEN_IDLE : (SEN_IDLE ^ slave_select);
+    reg [WIDTH-1:0] sen_reg = SEN_IDLE;
+    always @(posedge clock) begin
+      if (reset) begin
+        sen_reg <= SEN_IDLE;
+      end else begin
+        sen_reg <= sen24[WIDTH-1:0];
+      end
+    end
+    assign sen = sen_reg;
+
+    //data output shift register
+   // IJB. One pipeline stage to break critical path from register in I/O pads.
+    reg [31:0] dataout_reg;
+    wire [31:0] dataout_next = {dataout_reg[30:0], 1'b0};
+   
+   always @(posedge clock)
+     mosi <= dataout_reg[31];
+
+    //data input shift register
+   // IJB. Two pipeline stages to break critical path from register in I/O pads.
+   reg 		miso_pipe, miso_pipe2;
+   always @(posedge clock) begin
+      miso_pipe2 <= miso;
+      miso_pipe <= miso_pipe2;
+   end
+   
+    reg [31:0] datain_reg;
+    wire [31:0] datain_next = {datain_reg[30:0], miso_pipe};
+    assign readback = datain_reg;
+
+    //counter for spi clock
+    reg [15:0] sclk_counter;
+    wire sclk_counter_done = (sclk_counter == sclk_divider);
+    wire [15:0] sclk_counter_next = (sclk_counter_done)? 0 : sclk_counter + 1;
+
+    //counter for latching bits miso/mosi
+    reg [6:0] bit_counter;
+    wire [6:0] bit_counter_next = bit_counter + 1;
+    wire bit_counter_done = (bit_counter_next == num_bits);
+
+    always @(posedge clock) begin
+        if (reset) begin
+            state <= WAIT_TRIG;
+            sclk_reg <= CLK_IDLE;
+            ready_reg <= 0;
+            readback_stb <= 1'b0;
+        end
+        else begin
+            case (state)
+
+            WAIT_TRIG: begin
+                if (trigger_spi) state <= PRE_IDLE;
+                readback_stb <= 1'b0;
+                ready_reg <= ~trigger_spi;
+                dataout_reg <= mosi_data;
+                sclk_counter <= 0;
+                bit_counter <= 0;
+                sclk_reg <= CLK_IDLE;
+            end
+
+            PRE_IDLE: begin
+                if (sclk_counter_done) state <= CLK_REG;
+                sclk_counter <= sclk_counter_next;
+                sclk_reg <= CLK_IDLE;
+            end
+
+            CLK_REG: begin
+                if (sclk_counter_done) begin
+                    state <= CLK_INV;
+                    if (datain_edge  != CLK_IDLE)                     datain_reg  <= datain_next;
+                    if (dataout_edge != CLK_IDLE && bit_counter != 0) dataout_reg <= dataout_next;
+                    sclk_reg <= ~CLK_IDLE; //transition to rising when CLK_IDLE == 0
+                end
+                sclk_counter <= sclk_counter_next;
+            end
+
+            CLK_INV: begin
+                if (sclk_counter_done) begin
+                    state <= (bit_counter_done)? POST_IDLE : CLK_REG;
+                    bit_counter <= bit_counter_next;
+                    if (datain_edge  == CLK_IDLE)                      datain_reg  <= datain_next;
+                    if (dataout_edge == CLK_IDLE && ~bit_counter_done) dataout_reg <= dataout_next;
+                    sclk_reg <= CLK_IDLE; //transition to falling when CLK_IDLE == 0
+                end
+                sclk_counter <= sclk_counter_next;
+            end
+
+            POST_IDLE: begin
+                if (sclk_counter_done) state <= IDLE_SEN;
+                sclk_counter <= sclk_counter_next;
+                sclk_reg <= CLK_IDLE;
+            end
+
+            IDLE_SEN: begin
+                if (sclk_counter_done) begin
+                  ready_reg <= 1'b1;
+                  readback_stb <= 1'b1;
+                  state <= WAIT_TRIG;
+                end
+                sclk_counter <= sclk_counter_next;
+                sclk_reg <= CLK_IDLE;
+            end
+
+            default: state <= WAIT_TRIG;
+
+            endcase //state
+        end
+    end
+
+    assign debug = {
+        trigger_spi, state, //4
+        sclk, mosi, miso, ready, //4
+        //sen[7:0], //8
+        1'b0, bit_counter[6:0], //8
+        sclk_counter_done, bit_counter_done, //2
+        sclk_counter[5:0] //6
+    };
+
+endmodule //simple_spi_core
diff --git a/fpga/usrp3/lib/control/synchronizer.v b/fpga/usrp3/lib/control/synchronizer.v
new file mode 100644
index 000000000..177b1219c
--- /dev/null
+++ b/fpga/usrp3/lib/control/synchronizer.v
@@ -0,0 +1,50 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module synchronizer #(
+   parameter WIDTH            = 1,
+   parameter STAGES           = 2,
+   parameter INITIAL_VAL      = 0,
+   parameter FALSE_PATH_TO_IN = 1
+)(
+   input              clk,
+   input              rst,
+   input  [WIDTH-1:0] in,
+   output [WIDTH-1:0] out
+);
+
+   //Q: Why do we have a separate impl and instantiate
+   //it with a different instance name based on this
+   //arbitrary parameter FALSE_PATH_TO_IN?
+   //A: To make constraining these synchronizers easier.
+   //We would like to write a single false path constraint
+   //for all synchronizers when the input is truly async.
+   //However other cases might require constraining the input
+   //of this module.
+   //To enable this, all clients that hook up async signals to
+   //the "in" port can set FALSE_PATH_TO_IN=1 (or use the default)
+   //and all clients that want the "in" delay to be constrained can
+   //set FALSE_PATH_TO_IN=0.
+   //In the XDC we can write the following async constraint:
+   //set_false_path -to [get_pins */synchronizer_false_path/stages[0].value_reg[0]/D]
+   //and this will take care of all instances of this module with FALSE_PATH_TO_IN==1
+
+   generate if (FALSE_PATH_TO_IN == 1) begin
+      synchronizer_impl #(
+        .WIDTH(WIDTH), .STAGES(STAGES), .INITIAL_VAL(INITIAL_VAL)
+      ) synchronizer_false_path (
+         .clk(clk), .rst(rst), .in(in), .out(out)
+      );
+   end else begin
+      synchronizer_impl #(
+        .WIDTH(WIDTH), .STAGES(STAGES), .INITIAL_VAL(INITIAL_VAL)
+      ) synchronizer_constrained (
+         .clk(clk), .rst(rst), .in(in), .out(out)
+      );
+   end endgenerate
+
+endmodule   //synchronizer
diff --git a/fpga/usrp3/lib/control/synchronizer_impl.v b/fpga/usrp3/lib/control/synchronizer_impl.v
new file mode 100644
index 000000000..1c4f77707
--- /dev/null
+++ b/fpga/usrp3/lib/control/synchronizer_impl.v
@@ -0,0 +1,47 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module synchronizer_impl #(
+   parameter WIDTH       = 1,
+   parameter STAGES      = 2,
+   parameter INITIAL_VAL = 0
+)(
+   input              clk,
+   input              rst,
+   input  [WIDTH-1:0] in,
+   output [WIDTH-1:0] out
+);
+
+   (* ASYNC_REG = "TRUE" *) reg [WIDTH-1:0] value[0:STAGES-1];
+
+   integer k;
+   initial begin
+     for (k = 0; k < STAGES; k = k + 1) begin
+       value[k] = INITIAL_VAL;
+     end
+   end
+
+   genvar i;
+   generate
+      for (i=0; i<STAGES; i=i+1) begin: stages
+         always @(posedge clk) begin
+            if (rst) begin
+               value[i] <= INITIAL_VAL;
+            end else begin
+               if (i == 0) begin
+                 value[i] <= in;
+               end else begin
+                 value[i] <= value[i-1];
+               end
+            end
+         end
+      end
+   endgenerate
+
+   assign out = value[STAGES-1];
+
+endmodule   //synchronizer_impl
diff --git a/fpga/usrp3/lib/control/user_settings.v b/fpga/usrp3/lib/control/user_settings.v
new file mode 100644
index 000000000..6f4641b33
--- /dev/null
+++ b/fpga/usrp3/lib/control/user_settings.v
@@ -0,0 +1,66 @@
+//
+// Copyright 2012 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+// User settings bus
+//
+// Provides 8-bit address, 32-bit data write only bus for user settings, consumes to addresses in
+// normal settings bus.
+//
+// Write user address to BASE
+// Write user data to BASE+1
+//
+// The user_set_stb will strobe after data write, must write new address even if same as previous one.
+
+module user_settings
+  #(parameter BASE=0)
+  (input clk,
+   input rst,
+
+   input         set_stb,
+   input [7:0]   set_addr,
+   input [31:0]  set_data,
+
+   output        set_stb_user,
+   output [7:0]  set_addr_user,
+   output [31:0] set_data_user
+   );
+
+   wire 	 addr_changed, data_changed;
+   reg 		 stb_int;
+   
+   setting_reg #(.my_addr(BASE+0),.width(8)) sr_0
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(set_addr_user),.changed(addr_changed) );
+   
+   setting_reg #(.my_addr(BASE+1)) sr_1
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(set_data_user),.changed(data_changed) );
+   
+   always @(posedge clk)
+     if (rst|set_stb_user)
+       stb_int <= 0;
+     else
+       if (addr_changed)
+         stb_int <= 1;
+   
+   assign set_stb_user = stb_int & data_changed;
+   
+endmodule // user_settings
+
diff --git a/fpga/usrp3/lib/control_200/Makefile.srcs b/fpga/usrp3/lib/control_200/Makefile.srcs
new file mode 100644
index 000000000..b4ab98f9d
--- /dev/null
+++ b/fpga/usrp3/lib/control_200/Makefile.srcs
@@ -0,0 +1,14 @@
+#
+# Copyright 2013 Ettus Research LLC
+# Copyright 2016 Ettus Research, a National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+##################################################
+# Control Lib Sources (2xx devices)
+##################################################
+CONTROL_LIB_200_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/control_200/, \
+cvita_uart.v \
+radio_ctrl_proc.v \
+))
diff --git a/fpga/usrp3/lib/control_200/cvita_uart.v b/fpga/usrp3/lib/control_200/cvita_uart.v
new file mode 100644
index 000000000..1afcbb5f0
--- /dev/null
+++ b/fpga/usrp3/lib/control_200/cvita_uart.v
@@ -0,0 +1,167 @@
+
+//
+// Copyright 2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+//create a compressed vita based uart data interface
+
+module cvita_uart
+#(
+    parameter SIZE = 0
+)
+(
+    //clocking interface
+    input clk, input rst,
+
+    //uart interface
+    input rxd, output txd,
+
+    //chdr fifo input
+    input [63:0] i_tdata,
+    input i_tlast,
+    input i_tvalid,
+    output i_tready,
+
+    //chdr fifo output
+    output [63:0] o_tdata,
+    output o_tlast,
+    output o_tvalid,
+    input o_tready
+);
+
+    reg [31:0] sid;
+
+    //baud clock divider
+    reg [15:0] clkdiv;
+
+    //hold rx in disable until a tx event
+    reg rxd_enable;
+
+    //==================================================================
+    //== RXD capture and packet generation interface
+    //==================================================================
+    wire [7:0] rx_char;
+    wire fifo_empty;
+    wire fifo_read;
+    reg [11:0] seqnum;
+    wire pgen_trigger;
+    wire pgen_done;
+
+    //rx uart capture
+    simple_uart_rx #(.SIZE(SIZE)) simple_uart_rx
+    (
+        .clk(clk), .rst(rst | ~rxd_enable),
+        .fifo_out(rx_char), .fifo_read(fifo_read), .fifo_level(), .fifo_empty(fifo_empty),
+        .clkdiv(clkdiv), .rx(rxd)
+    );
+
+    //packet generation - holds rx character
+    context_packet_gen context_packet_gen
+    (
+        .clk(clk), .reset(rst), .clear(1'b0),
+        .trigger(pgen_trigger),
+        .seqnum(seqnum),
+        .sid({sid[15:0], sid[31:16]}),
+        .body({56'b0, rx_char}),
+        .vita_time(64'b0),
+
+        .done(pgen_done),
+        .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready)
+    );
+
+    //state machine to manage pgen and rx uart
+    reg [1:0] rxd_state;
+    localparam RXD_STATE_RECV_CHAR = 0;
+    localparam RXD_STATE_PGEN_TRIG = 1;
+    localparam RXD_STATE_WAIT_DONE = 2;
+    localparam RXD_STATE_READ_FIFO = 3;
+
+    always @(posedge clk) begin
+        if (rst) begin
+            seqnum <= 12'b0;
+            rxd_state <= RXD_STATE_RECV_CHAR;
+        end
+        else case (rxd_state)
+
+        RXD_STATE_RECV_CHAR: begin
+            if (!fifo_empty && rxd_enable) rxd_state <= RXD_STATE_PGEN_TRIG;
+        end
+
+        RXD_STATE_PGEN_TRIG: begin
+            rxd_state <= RXD_STATE_WAIT_DONE;
+        end
+
+        RXD_STATE_WAIT_DONE: begin
+            if (pgen_done) rxd_state <= RXD_STATE_READ_FIFO;
+        end
+
+        RXD_STATE_READ_FIFO: begin
+            rxd_state <= RXD_STATE_RECV_CHAR;
+            seqnum <= seqnum + 1'b1;
+        end
+
+        endcase //rxd_state
+    end
+
+    assign fifo_read = (rxd_state == RXD_STATE_READ_FIFO) || (!rxd_enable);
+    assign pgen_trigger = (rxd_state == RXD_STATE_PGEN_TRIG);
+
+    //==================================================================
+    //== TXD generation and packet control interface
+    //==================================================================
+    wire [7:0] tx_char;
+    wire fifo_write;
+    wire fifo_full;
+
+    simple_uart_tx #(.SIZE(SIZE)) simple_uart_tx
+    (
+        .clk(clk), .rst(rst),
+        .fifo_in(tx_char), .fifo_write(fifo_write), .fifo_level(), .fifo_full(fifo_full),
+        .clkdiv(clkdiv), .baudclk(), .tx(txd)
+    );
+
+    //state machine to manage control and tx uart
+    reg [1:0] txd_state;
+    localparam TXD_STATE_RECV_CHDR = 0;
+    localparam TXD_STATE_RECV_TIME = 1;
+    localparam TXD_STATE_RECV_BODY = 2;
+    localparam TXD_STATE_DROP_FIFO = 3;
+
+    always @(posedge clk) begin
+        if (rst) begin;
+            txd_state <= TXD_STATE_RECV_CHDR;
+            rxd_enable <= 1'b0;
+        end
+        if (i_tvalid && i_tready) case (txd_state)
+
+        TXD_STATE_RECV_CHDR: begin
+            txd_state <= (i_tdata[61])? TXD_STATE_RECV_TIME : TXD_STATE_RECV_BODY;
+            sid <= i_tdata[31:0];
+        end
+
+        TXD_STATE_RECV_TIME: begin
+            txd_state <= TXD_STATE_RECV_BODY;
+        end
+
+        TXD_STATE_RECV_BODY: begin
+            txd_state <= (i_tlast)? TXD_STATE_RECV_CHDR : TXD_STATE_DROP_FIFO;
+            clkdiv <= i_tdata[47:32];
+            rxd_enable <= 1'b1;
+        end
+
+        TXD_STATE_DROP_FIFO: begin
+            if (i_tlast) txd_state <= TXD_STATE_RECV_CHDR;
+        end
+
+        endcase //txd_state
+    end
+
+    assign tx_char = i_tdata[7:0];
+    assign fifo_write = (txd_state == TXD_STATE_RECV_BODY) && i_tvalid && i_tready;
+    assign i_tready = !fifo_full;
+
+endmodule // cvita_uart
diff --git a/fpga/usrp3/lib/control_200/radio_ctrl_proc.v b/fpga/usrp3/lib/control_200/radio_ctrl_proc.v
new file mode 100644
index 000000000..069ea5d81
--- /dev/null
+++ b/fpga/usrp3/lib/control_200/radio_ctrl_proc.v
@@ -0,0 +1,151 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+// Radio Control Processor
+//  Accepts compressed vita extension context packets of the following form:
+//       { VITA Compressed Header, Stream ID }
+//       { Optional 64 bit time }
+//       { 16'h0, setting bus address [15:0], setting [31:0] }
+//
+//  If there is a timestamp, packet is held until that time comes.
+//  Goes immediately if there is no timestamp or if time has passed.
+//  Sends out setting to setting bus, and then generates a response packet
+//  with the same sequence number, the src/dest swapped streamid, and the actual time
+//  the setting was sent.
+//
+// Note -- if t0 is the requested time, the actual send time on the setting bus is t0 + 1 cycle.
+
+module radio_ctrl_proc
+  (input clk, input reset, input clear,
+   
+   input [63:0] ctrl_tdata, input ctrl_tlast, input ctrl_tvalid, output reg ctrl_tready,
+   output reg [63:0] resp_tdata, output reg resp_tlast, output resp_tvalid, input resp_tready,
+   
+   input [63:0] vita_time,
+
+   output set_stb, output [7:0] set_addr, output [31:0] set_data,
+   input ready,
+   
+   input [63:0] readback,
+   
+   output [31:0] debug);
+
+   localparam RC_HEAD   = 4'd0;
+   localparam RC_TIME   = 4'd1;
+   localparam RC_DATA   = 4'd2;
+   localparam RC_DUMP   = 4'd3;
+   localparam RC_RESP_HEAD = 4'd4;
+   localparam RC_RESP_TIME = 4'd5;
+   localparam RC_RESP_DATA = 4'd6;
+   
+   wire 	 IS_EC = ctrl_tdata[63];
+   wire 	 HAS_TIME = ctrl_tdata[61];
+   reg 		 HAS_TIME_reg;
+   
+   reg [3:0] 	 rc_state;
+   reg [63:0] 	 cmd_time;
+
+   wire 	 now, late, go;
+   reg [11:0] 	 seqnum;
+   reg [31:0] 	 sid;
+   
+   always @(posedge clk)
+     if(reset)
+       begin
+	  rc_state <= RC_HEAD;
+	  HAS_TIME_reg <= 1'b0;
+	  sid <= 32'd0;
+	  seqnum <= 12'd0;
+       end
+     else
+	 case(rc_state)
+	   RC_HEAD :
+	     if(ctrl_tvalid)
+	       begin
+		  sid <= ctrl_tdata[31:0];
+		  seqnum <= ctrl_tdata[59:48];
+		  HAS_TIME_reg <= HAS_TIME;
+		  if(IS_EC)
+		    if(HAS_TIME)
+		      rc_state <= RC_TIME;
+		    else
+		      rc_state <= RC_DATA;
+		  else
+		    if(~ctrl_tlast)
+		      rc_state <= RC_DUMP;
+	       end
+	   
+	   RC_TIME :
+	     if(ctrl_tvalid)
+	       if(ctrl_tlast)
+		 rc_state <= RC_RESP_HEAD;
+	       else if(go)
+		 rc_state <= RC_DATA;
+	   
+	   RC_DATA :
+	     if(ctrl_tvalid)
+	       if(ready)
+		 if(ctrl_tlast)
+		   rc_state <= RC_RESP_HEAD;
+		 else
+		   rc_state <= RC_DUMP;
+
+	   RC_DUMP :
+	     if(ctrl_tvalid)
+	       if(ctrl_tlast)
+		 rc_state <= RC_RESP_HEAD;
+
+	   RC_RESP_HEAD :
+	     if(resp_tready)
+	       rc_state <= RC_RESP_TIME;
+
+	   RC_RESP_TIME :
+	     if(resp_tready)
+	       rc_state <= RC_RESP_DATA;
+
+	   RC_RESP_DATA:
+	     if(resp_tready)
+	       rc_state <= RC_HEAD;
+	   
+	   default :
+	     rc_state <= RC_HEAD;
+	 endcase // case (rc_state)
+
+   always @*
+     case (rc_state)
+       RC_HEAD : ctrl_tready <= 1'b1;
+       RC_TIME : ctrl_tready <= ctrl_tlast | go;
+       RC_DATA : ctrl_tready <= ready;
+       RC_DUMP : ctrl_tready <= 1'b1;
+       default : ctrl_tready <= 1'b0;
+     endcase // case (rc_state)
+      
+   time_compare time_compare
+     (.clk(clk), .reset(reset), .time_now(vita_time), .trigger_time(ctrl_tdata), .now(now), .early(), .late(late), .too_early());
+
+   assign go = now | late;
+   
+   assign set_stb = (rc_state == RC_DATA) & ready & ctrl_tvalid;
+   assign set_addr = ctrl_tdata[39:32];
+   assign set_data = ctrl_tdata[31:0];
+
+   always @(posedge clk)
+      if (set_stb)
+         cmd_time <= vita_time;
+
+   always @*
+     case (rc_state)
+       RC_RESP_HEAD : { resp_tlast, resp_tdata } <= {1'b0, 4'hA, seqnum, 16'd24, sid[15:0], sid[31:16] };
+       RC_RESP_TIME : { resp_tlast, resp_tdata } <= {1'b0, cmd_time};
+       RC_RESP_DATA : { resp_tlast, resp_tdata } <= {1'b1, readback};
+       default :      { resp_tlast, resp_tdata } <= 65'h0;
+     endcase // case (rc_state)
+   
+   assign resp_tvalid = (rc_state == RC_RESP_HEAD) | (rc_state == RC_RESP_TIME) | (rc_state == RC_RESP_DATA);
+   
+endmodule // radio_ctrl_proc
+
diff --git a/fpga/usrp3/lib/control_200/radio_ctrl_proc_tb.v b/fpga/usrp3/lib/control_200/radio_ctrl_proc_tb.v
new file mode 100644
index 000000000..18d822e27
--- /dev/null
+++ b/fpga/usrp3/lib/control_200/radio_ctrl_proc_tb.v
@@ -0,0 +1,110 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+`timescale 1ns/1ps
+
+module radio_ctrl_proc_tb();
+
+   reg clk    = 0;
+   reg reset  = 1;
+
+   always #10 clk = ~clk;
+
+   initial $dumpfile("radio_ctrl_proc_tb.vcd");
+   initial $dumpvars(0,radio_ctrl_proc_tb);
+
+   initial
+     begin
+	#1000 reset = 0;
+	#20000;
+	$finish;
+     end
+   
+   reg [63:0] vita_time = 64'd0;
+   always @(posedge clk)
+     if(reset) vita_time <= 64'd0;
+     else vita_time <= vita_time + 64'd1;
+
+   reg [63:0]  tdata;
+   wire [63:0] tdata_int;
+   reg 	       tlast;
+   wire        tlast_int;
+   reg 	       tvalid = 1'b0;
+   wire        tvalid_int;
+   wire        tready, tready_int;
+   
+   wire [7:0]  set_addr;
+   wire [31:0] set_data;
+   wire        set_stb;
+   wire        ready = 1'b1;
+
+   task send_packet;
+      input ec;
+      input timed;
+      input [11:0] seqnum;
+      input [31:0] sid;
+      input [63:0] vtime;
+      input [15:0] addr;
+      input [31:0] data;
+      
+      begin
+	 // Send a packet
+	 @(posedge clk);
+	 tlast <= 1'b0;
+	 tdata <= { ec, 1'b0, timed, 1'b0, seqnum, timed ? 16'd6 : 16'd4, sid };
+	 tvalid <= 1;
+	 @(posedge clk);
+	 if(timed)
+	   begin
+	      tdata <= vtime;
+	      @(posedge clk);
+	   end
+	 tlast <= 1'b1;
+	 tdata <= { 16'h0, addr, data };
+	 @(posedge clk);
+	 tvalid <= 0;	 
+	 @(posedge clk);
+      end
+   endtask // send_packet
+   
+   initial
+     begin
+	tvalid <= 1'b0;
+	while(reset)
+	  @(posedge clk);
+	send_packet(1'b1,1'b0,12'h5,32'hDEAD_BEEF,64'h0,16'hB,32'hF00D_1234);
+	send_packet(1'b1,1'b1,12'h6,32'hDEAD_6789,64'h20,16'hC,32'hABCD_4321);
+	send_packet(1'b1,1'b1,12'h7,32'hDEAD_6789,64'h30,16'hC,32'hABCD_4321);
+	//send_packet(.ec(1), .timed(0), .seqnum(5), .sid(32'hDEAD_BEEF), .vtime(0), .addr(16'hB), .data(32'hF00D_1234));
+     end
+
+   axi_fifo_short #(.WIDTH(65)) axi_fifo_short
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata({tlast,tdata}), .i_tvalid(tvalid), .i_tready(tready),
+      .o_tdata({tlast_int,tdata_int}), .o_tvalid(tvalid_int), .o_tready(tready_int));
+
+   wire [63:0] resp_tdata;
+   wire        resp_tlast, resp_tvalid, resp_tready;
+   
+   radio_ctrl_proc radio_ctrl_proc
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .ctrl_tdata(tdata_int), .ctrl_tlast(tlast_int), .ctrl_tvalid(tvalid_int), .ctrl_tready(tready_int),
+      .resp_tdata(resp_tdata), .resp_tlast(resp_tlast), .resp_tvalid(resp_tvalid), .resp_tready(resp_tready),
+      .vita_time(vita_time), .ready(ready),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .debug()
+      );
+
+   assign resp_tready = 1'b1;
+   
+   always @(posedge clk)
+     if(resp_tvalid & resp_tready)
+       begin
+	  $display("%x",resp_tdata);
+	  if(resp_tlast)
+	    $display("TLAST");
+       end
+endmodule // radio_ctrl_proc_tb
diff --git a/fpga/usrp3/lib/dsp/Makefile.srcs b/fpga/usrp3/lib/dsp/Makefile.srcs
new file mode 100644
index 000000000..a32251109
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/Makefile.srcs
@@ -0,0 +1,47 @@
+#
+# Copyright 2013 Ettus Research LLC
+# Copyright 2016 Ettus Research, a National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+##################################################
+# DSP Sources
+##################################################
+DSP_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/dsp/, \
+acc.v \
+add2_and_clip_reg.v \
+add2_and_clip.v \
+add2_and_round_reg.v \
+add2_and_round.v \
+add2_reg.v \
+add2.v \
+add_then_mac.v \
+cic_decim.v \
+cic_dec_shifter.v \
+cic_interp.v \
+cic_int_shifter.v \
+cic_strober.v \
+clip_reg.v \
+clip.v \
+cordic_stage.v \
+cordic_z24.v \
+ddc_chain.v \
+duc_chain.v \
+hb47_int.v \
+hb_dec.v \
+hb_interp.v \
+Makefile.srcs \
+mult_add_clip.v \
+round_reg.v \
+round_sd.v \
+round.v \
+rx_dcoffset.v \
+rx_frontend.v \
+sign_extend.v \
+small_hb_dec.v \
+small_hb_int.v \
+srl.v \
+tx_frontend.v \
+variable_delay_line.v \
+))
diff --git a/fpga/usrp3/lib/dsp/acc.v b/fpga/usrp3/lib/dsp/acc.v
new file mode 100644
index 000000000..623b75da3
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/acc.v
@@ -0,0 +1,36 @@
+//
+// Copyright 2011 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+
+module acc
+  #(parameter IWIDTH=16, OWIDTH=30)
+    (input clk,
+     input clear,
+     input acc,
+     input [IWIDTH-1:0] in,
+     output reg [OWIDTH-1:0] out);
+
+   wire [OWIDTH-1:0] in_signext;
+   sign_extend #(.bits_in(IWIDTH),.bits_out(OWIDTH)) 
+     acc_signext (.in(in),.out(in_signext));
+   
+   //  CLEAR & ~ACC  -->  clears the accumulator
+   //  CLEAR & ACC -->    loads the accumulator
+   //  ~CLEAR & ACC -->   accumulates
+   //  ~CLEAR & ~ACC -->  hold
+   
+   wire [OWIDTH-1:0] addend1 = clear ? 0 : out;
+   wire [OWIDTH-1:0] addend2 = ~acc ? 0 : in_signext;
+   wire [OWIDTH-1:0] sum_int = addend1 + addend2;
+
+   always @(posedge clk)
+     out <= sum_int;
+   
+endmodule // acc
+
+
diff --git a/fpga/usrp3/lib/dsp/add2.v b/fpga/usrp3/lib/dsp/add2.v
new file mode 100644
index 000000000..0876b0320
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/add2.v
@@ -0,0 +1,19 @@
+//
+// Copyright 2011 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+
+module add2
+  #(parameter WIDTH=16)
+    (input [WIDTH-1:0] in1,
+     input [WIDTH-1:0] in2,
+     output [WIDTH-1:0] sum);
+
+   wire [WIDTH:0] 	sum_int = {in1[WIDTH-1],in1} + {in2[WIDTH-1],in2};
+   assign 		sum = sum_int[WIDTH:1];  // Note -- will have some bias
+   
+endmodule // add2
diff --git a/fpga/usrp3/lib/dsp/add2_and_clip.v b/fpga/usrp3/lib/dsp/add2_and_clip.v
new file mode 100644
index 000000000..86980e967
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/add2_and_clip.v
@@ -0,0 +1,18 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module add2_and_clip
+  #(parameter WIDTH=16)
+    (input [WIDTH-1:0] in1,
+     input [WIDTH-1:0] in2,
+     output [WIDTH-1:0] sum);
+
+   wire [WIDTH:0] 	sum_int = {in1[WIDTH-1],in1} + {in2[WIDTH-1],in2};
+   clip #(.bits_in(WIDTH+1),.bits_out(WIDTH)) clip
+     (.in(sum_int),.out(sum));
+   
+endmodule // add2_and_clip
diff --git a/fpga/usrp3/lib/dsp/add2_and_clip_reg.v b/fpga/usrp3/lib/dsp/add2_and_clip_reg.v
new file mode 100644
index 000000000..8fe343ab2
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/add2_and_clip_reg.v
@@ -0,0 +1,30 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module add2_and_clip_reg
+  #(parameter WIDTH=16)
+    (input clk,
+     input rst,
+     input [WIDTH-1:0] in1,
+     input [WIDTH-1:0] in2,
+     input strobe_in,
+     output reg [WIDTH-1:0] sum,
+     output reg strobe_out);
+
+   wire [WIDTH-1:0] sum_int;
+
+   add2_and_clip #(.WIDTH(WIDTH)) add2_and_clip (.in1(in1),.in2(in2),.sum(sum_int));
+
+   always @(posedge clk)
+     if(rst)
+       sum <= 0;
+     else if(strobe_in)
+       sum <= sum_int;
+
+   always @(posedge clk) strobe_out <= rst ? 1'b0 : strobe_in;
+
+endmodule // add2_and_clip_reg
diff --git a/fpga/usrp3/lib/dsp/add2_and_round.v b/fpga/usrp3/lib/dsp/add2_and_round.v
new file mode 100644
index 000000000..b15cb9987
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/add2_and_round.v
@@ -0,0 +1,19 @@
+//
+// Copyright 2011 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+
+module add2_and_round
+  #(parameter WIDTH=16)
+    (input [WIDTH-1:0] in1,
+     input [WIDTH-1:0] in2,
+     output [WIDTH-1:0] sum);
+
+   wire [WIDTH:0] 	sum_int = {in1[WIDTH-1],in1} + {in2[WIDTH-1],in2};
+   assign 		sum = sum_int[WIDTH:1] + (sum_int[WIDTH] & sum_int[0]);
+   
+endmodule // add2_and_round
diff --git a/fpga/usrp3/lib/dsp/add2_and_round_reg.v b/fpga/usrp3/lib/dsp/add2_and_round_reg.v
new file mode 100644
index 000000000..f64acd6ba
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/add2_and_round_reg.v
@@ -0,0 +1,24 @@
+//
+// Copyright 2011 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+
+module add2_and_round_reg
+  #(parameter WIDTH=16)
+    (input clk,
+     input [WIDTH-1:0] in1,
+     input [WIDTH-1:0] in2,
+     output reg [WIDTH-1:0] sum);
+
+   wire [WIDTH-1:0] sum_int;
+   
+   add2_and_round #(.WIDTH(WIDTH)) add2_n_rnd (.in1(in1),.in2(in2),.sum(sum_int));
+
+   always @(posedge clk)
+     sum <= sum_int;
+   
+endmodule // add2_and_round_reg
diff --git a/fpga/usrp3/lib/dsp/add2_reg.v b/fpga/usrp3/lib/dsp/add2_reg.v
new file mode 100644
index 000000000..44b2ed66e
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/add2_reg.v
@@ -0,0 +1,25 @@
+//
+// Copyright 2011 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+
+module add2_reg
+  #(parameter WIDTH=16)
+    (input clk,
+     input [WIDTH-1:0] in1,
+     input [WIDTH-1:0] in2,
+     output reg [WIDTH-1:0] sum);
+
+   wire [WIDTH-1:0] sum_int;
+   
+   add2 #(.WIDTH(WIDTH)) add2 (.in1(in1),.in2(in2),.sum(sum_int));
+
+   always @(posedge clk)
+     sum <= sum_int;
+   
+endmodule // add2_reg
+
diff --git a/fpga/usrp3/lib/dsp/add_then_mac.v b/fpga/usrp3/lib/dsp/add_then_mac.v
new file mode 100644
index 000000000..b56d9e9d4
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/add_then_mac.v
@@ -0,0 +1,164 @@
+//
+// Copyright 2015 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+`timescale  1 ps / 1 ps
+
+//
+// Implements acc=((a+d)*b)+c or acc=((a+d)*b)+acc'
+//
+
+module add_then_mac
+  #(parameter DEVICE = "VIRTEX6")
+    (
+     // Output ports
+     output [47:0] acc,
+
+     // Input ports
+     input carryin,
+     input ce,
+     input clk,
+     input [17:0] b,
+     input load,
+     input [47:0] c,
+     input [17:0] a,
+     input [17:0] d,
+     input rst
+     );
+
+
+   wire [24:0] a_in;
+   wire [24:0] d_in;
+
+   localparam  AREG_IN = 1;
+   localparam  BREG_IN = 1;
+   localparam  MREG_IN = 1;
+   localparam  PREG_IN = 1;
+   localparam  A1REG_IN = 1;
+   localparam  A0REG_IN = 0;
+   localparam  B1REG_IN = 1;
+   localparam  B0REG_IN = 1;
+
+   // Sign extend inputs
+   assign      a_in = (a[17] == 1'b1) ? {7'hff, a} : {7'h00, a};
+   assign      d_in = (d[17] == 1'b1) ? {7'hff, d} : {7'h00, d};
+
+   generate
+      case(DEVICE)
+	// begin generate virtex6
+	"VIRTEX6", "7SERIES" :
+	  begin
+	     DSP48E1 #(
+		       .ACASCREG(AREG_IN),
+		       .AREG(AREG_IN),
+		       .BCASCREG(BREG_IN),
+		       .BREG(BREG_IN),
+		       .MREG(MREG_IN),
+		       .PREG(PREG_IN),
+		       .USE_DPORT("TRUE")
+		       )
+	       DSP48E_BL (
+			  .ACOUT(),
+			  .BCOUT(),
+			  .CARRYCASCOUT(),
+			  .CARRYOUT(),
+			  .MULTSIGNOUT(),
+			  .OVERFLOW(),
+			  .P(acc),
+			  .PATTERNBDETECT(),
+			  .PATTERNDETECT(),
+			  .PCOUT(),
+			  .UNDERFLOW(),
+			  .A({5'b0, a_in[24:0]}),
+			  .ACIN(30'b0),
+			  .ALUMODE(4'b0000),
+			  .B(b[17:0]),
+			  .BCIN(18'b0),
+			  .C(c),
+			  .CARRYCASCIN(1'b0),
+			  .CARRYIN(carryin),
+			  .CARRYINSEL(3'b0),
+			  .CEA1(1'b0),
+			  .CEA2(ce),
+			  .CEAD(ce),
+			  .CEALUMODE(ce),
+			  .CEB1(1'b0),
+			  .CEB2(ce),
+			  .CEC(ce),
+			  .CECARRYIN(ce),
+			  .CECTRL(ce),
+			  .CED(ce),
+			  .CEINMODE(ce),
+			  .CEM(ce),
+			  .CEP(ce),
+			  .CLK(clk),
+			  .D(d_in[24:0]),
+			  .INMODE(5'b00100),
+			  .MULTSIGNIN(1'b0),
+			  .OPMODE({2'b01,load,4'b0101}),
+			  .PCIN(48'b0),
+			  .RSTA(rst),
+			  .RSTALLCARRYIN(rst),
+			  .RSTALUMODE(rst),
+			  .RSTB(rst),
+			  .RSTC(rst),
+			  .RSTCTRL(rst),
+			  .RSTD(rst),
+			  .RSTINMODE(rst),
+			  .RSTM(rst),
+			  .RSTP(rst)
+			  );
+	  end // end generate virtex6
+	// begin generate spartan6
+	"SPARTAN6" :
+	  begin
+	     // DSP48A1 has 18b+18b=18b pre-adder, must discard LSB of A and D and compensate by shifting ACC.
+	     wire discard;;
+	     assign acc[0] = 1'b0;
+	     
+	     DSP48A1 #(
+		       .A0REG(A0REG_IN),
+		       .A1REG(A1REG_IN),
+		       .B0REG(B0REG_IN),
+		       .B1REG(B1REG_IN),
+		       .MREG(MREG_IN),
+		       .PREG(PREG_IN)
+		       )
+	       DSP48AST (
+			 .BCOUT(),
+			 .CARRYOUT(),
+			 .CARRYOUTF(),
+			 .M(),
+			 .P({discard,acc[47:1]}),
+			 .PCOUT(),
+			 .A(b[17:0]),
+			 .B({a_in[17],a_in[17:1]}),
+			 .C(c),
+			 .CARRYIN(carryin),
+			 .CEA(ce),
+			 .CEB(ce),
+			 .CEC(ce),
+			 .CECARRYIN(ce),
+			 .CED(ce),
+			 .CEM(ce),
+			 .CEOPMODE(ce),
+			 .CEP(ce),
+			 .CLK(clk),
+			 .D({d_in[17],d_in[17:1]}),
+			 .OPMODE({5'b00011,load, 2'b01}),
+			 .PCIN(48'b0),
+			 .RSTA(rst),
+			 .RSTB(rst),
+			 .RSTC(rst),
+			 .RSTCARRYIN(rst),
+			 .RSTD(rst),
+			 .RSTM(rst),
+			 .RSTOPMODE(rst),
+			 .RSTP(rst)
+			 );
+	  end // end generate spartan6
+      endcase
+   endgenerate
+endmodule
diff --git a/fpga/usrp3/lib/dsp/cic_dec_shifter.v b/fpga/usrp3/lib/dsp/cic_dec_shifter.v
new file mode 100644
index 000000000..f4bab3469
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/cic_dec_shifter.v
@@ -0,0 +1,96 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003 Matt Ettus
+// 
+//  SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+//
+
+
+// NOTE   This only works for N=4, max decim rate of 128
+// NOTE   signal "rate" is EQUAL TO the actual rate, no more -1 BS
+
+module cic_dec_shifter(rate,signal_in,signal_out);
+   parameter bw = 16;
+   parameter maxbitgain = 28;
+
+   input [7:0] rate;
+   input       wire [bw+maxbitgain-1:0] signal_in;
+   output      reg [bw-1:0] signal_out;
+
+   function [4:0] bitgain;
+      input [7:0] rate;
+      case(rate)
+	// Exact Cases -- N*log2(rate)
+	8'd1 : bitgain = 0;
+	8'd2 : bitgain = 4;
+	8'd4 : bitgain = 8;
+	8'd8 : bitgain = 12;
+	8'd16 : bitgain = 16;
+	8'd32 : bitgain = 20;
+	8'd64 : bitgain = 24;
+	8'd128 : bitgain = 28;
+	
+	// Nearest without overflow -- ceil(N*log2(rate))
+	8'd3 : bitgain = 7;
+	8'd5 : bitgain = 10;
+	8'd6 : bitgain = 11;
+	8'd7 : bitgain = 12;
+	8'd9 : bitgain = 13;
+	8'd10,8'd11 : bitgain = 14;
+	8'd12,8'd13 : bitgain = 15;
+	8'd14,8'd15 : bitgain = 16;
+	8'd17,8'd18,8'd19 : bitgain = 17;
+	8'd20,8'd21,8'd22 : bitgain = 18;
+	8'd23,8'd24,8'd25,8'd26 : bitgain = 19;
+	8'd27,8'd28,8'd29,8'd30,8'd31 : bitgain = 20;
+	8'd33,8'd34,8'd35,8'd36,8'd37,8'd38 : bitgain = 21;
+	8'd39,8'd40,8'd41,8'd42,8'd43,8'd44,8'd45 : bitgain = 22;
+	8'd46,8'd47,8'd48,8'd49,8'd50,8'd51,8'd52,8'd53 : bitgain = 23;
+	8'd54,8'd55,8'd56,8'd57,8'd58,8'd59,8'd60,8'd61,8'd62,8'd63 : bitgain = 24;
+	8'd65,8'd66,8'd67,8'd68,8'd69,8'd70,8'd71,8'd72,8'd73,8'd74,8'd75,8'd76 : bitgain = 25;
+	8'd77,8'd78,8'd79,8'd80,8'd81,8'd82,8'd83,8'd84,8'd85,8'd86,8'd87,8'd88,8'd89,8'd90 : bitgain = 26;
+	8'd91,8'd92,8'd93,8'd94,8'd95,8'd96,8'd97,8'd98,8'd99,8'd100,8'd101,8'd102,8'd103,8'd104,8'd105,8'd106,8'd107 : bitgain = 27;
+	default : bitgain = 28;
+      endcase // case(rate)
+   endfunction // bitgain
+   
+   wire [4:0] 	  shift = bitgain(rate);
+   
+   // We should be able to do this, but can't ....
+   // assign 	  signal_out = signal_in[shift+bw-1:shift];
+   
+   always @*
+     case(shift)
+       5'd0  : signal_out = signal_in[0+bw-1:0];
+       5'd4  : signal_out = signal_in[4+bw-1:4];
+       5'd7  : signal_out = signal_in[7+bw-1:7];
+       5'd8  : signal_out = signal_in[8+bw-1:8];
+       5'd10 : signal_out = signal_in[10+bw-1:10];
+       5'd11 : signal_out = signal_in[11+bw-1:11];
+       5'd12 : signal_out = signal_in[12+bw-1:12];
+       5'd13 : signal_out = signal_in[13+bw-1:13];
+       5'd14 : signal_out = signal_in[14+bw-1:14];
+       5'd15 : signal_out = signal_in[15+bw-1:15];
+       5'd16 : signal_out = signal_in[16+bw-1:16];
+       5'd17 : signal_out = signal_in[17+bw-1:17];
+       5'd18 : signal_out = signal_in[18+bw-1:18];
+       5'd19 : signal_out = signal_in[19+bw-1:19];
+       5'd20 : signal_out = signal_in[20+bw-1:20];
+       5'd21 : signal_out = signal_in[21+bw-1:21];
+       5'd22 : signal_out = signal_in[22+bw-1:22];
+       5'd23 : signal_out = signal_in[23+bw-1:23];
+       5'd24 : signal_out = signal_in[24+bw-1:24];
+       5'd25 : signal_out = signal_in[25+bw-1:25];
+       5'd26 : signal_out = signal_in[26+bw-1:26];
+       5'd27 : signal_out = signal_in[27+bw-1:27];
+       5'd28 : signal_out = signal_in[28+bw-1:28];
+       
+       default : signal_out = signal_in[28+bw-1:28];
+     endcase // case(shift)
+
+endmodule // cic_dec_shifter
+
diff --git a/fpga/usrp3/lib/dsp/cic_decim.v b/fpga/usrp3/lib/dsp/cic_decim.v
new file mode 100644
index 000000000..747ef8d99
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/cic_decim.v
@@ -0,0 +1,78 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003 Matt Ettus
+// 
+//  SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+//
+
+
+module cic_decim
+  #(parameter bw = 16, parameter N = 4, parameter log2_of_max_rate = 7)
+    (input clock,
+     input reset,
+     input enable,
+     input [7:0] rate,
+     input strobe_in,
+     input strobe_out,
+     input [bw-1:0] signal_in,
+     output reg [bw-1:0] signal_out);
+
+   localparam 	     maxbitgain = N * log2_of_max_rate;
+   
+   wire [bw+maxbitgain-1:0] signal_in_ext;
+   reg [bw+maxbitgain-1:0]  integrator [0:N-1];
+   reg [bw+maxbitgain-1:0]  differentiator [0:N-1];
+   reg [bw+maxbitgain-1:0]  pipeline [0:N-1];
+   reg [bw+maxbitgain-1:0]  sampler;
+   
+   integer 		    i;
+   
+   sign_extend #(bw,bw+maxbitgain) 
+     ext_input (.in(signal_in),.out(signal_in_ext));
+   
+   always @(posedge clock)
+     if(~enable)
+       for(i=0;i<N;i=i+1)
+	 integrator[i] <= 0;
+     else if (strobe_in)
+       begin
+	  integrator[0] <= integrator[0] + signal_in_ext;
+	  for(i=1;i<N;i=i+1)
+	    integrator[i] <= integrator[i] + integrator[i-1];
+       end	
+   
+   always @(posedge clock)
+     if(~enable)
+       begin
+	  sampler <= 0;
+	  for(i=0;i<N;i=i+1)
+	    begin
+	       pipeline[i] <= 0;
+	       differentiator[i] <= 0;
+	    end
+       end
+     else if (strobe_out)
+       begin
+	  sampler <= integrator[N-1];
+	  differentiator[0] <= sampler;
+	  pipeline[0] <= sampler - differentiator[0];
+	  for(i=1;i<N;i=i+1)
+	    begin
+	       differentiator[i] <= pipeline[i-1];
+	       pipeline[i] <= pipeline[i-1] - differentiator[i];
+	    end
+       end // if (enable && strobe_out)
+   
+   wire [bw-1:0] signal_out_unreg;
+   
+   cic_dec_shifter #(bw)
+     cic_dec_shifter(rate,pipeline[N-1],signal_out_unreg);
+
+   always @(posedge clock)
+     signal_out <= signal_out_unreg;
+   
+endmodule // cic_decim
diff --git a/fpga/usrp3/lib/dsp/cic_int_shifter.v b/fpga/usrp3/lib/dsp/cic_int_shifter.v
new file mode 100644
index 000000000..f18cddf1e
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/cic_int_shifter.v
@@ -0,0 +1,90 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003 Matt Ettus
+// 
+//  SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+//
+
+
+// NOTE   This only works for N=4, max interp rate of 128
+// NOTE   signal "rate" is EQUAL TO the actual rate (no more -1 BS)
+
+module cic_int_shifter(rate,signal_in,signal_out);
+   parameter bw = 16;
+   parameter maxbitgain = 21;
+   
+   input [7:0] rate;
+   input       wire [bw+maxbitgain-1:0] signal_in;
+   output      reg [bw-1:0] signal_out;
+
+   function [4:0] bitgain;
+      input [7:0] rate;
+      case(rate)
+	// Exact Cases
+	8'd1 : bitgain = 0;
+	8'd2 : bitgain = 3;
+	8'd4 : bitgain = 6;
+	8'd8 : bitgain = 9;
+	8'd16 : bitgain = 12;
+	8'd32 : bitgain = 15;
+	8'd64 : bitgain = 18;
+	8'd128 : bitgain = 21;
+	
+	// Nearest without overflow	
+	8'd3 : bitgain = 5;
+	8'd5 : bitgain = 7;
+	8'd6 : bitgain = 8;
+	8'd7 : bitgain = 9;
+	8'd9,8'd10 : bitgain = 10;
+	8'd11,8'd12 : bitgain = 11;
+	8'd13,8'd14,8'd15 : bitgain = 12;
+	8'd17,8'd18,8'd19,8'd20 : bitgain = 13;
+	8'd21,8'd22,8'd23,8'd24,8'd25 : bitgain = 14;
+	8'd26,8'd27,8'd28,8'd29,8'd30,8'd31 : bitgain = 15;
+	8'd33,8'd34,8'd35,8'd36,8'd37,8'd38,8'd39,8'd40 : bitgain = 16;
+	8'd41,8'd42,8'd43,8'd44,8'd45,8'd46,8'd47,8'd48,8'd49,8'd50 : bitgain = 17;
+	8'd51,8'd52,8'd53,8'd54,8'd55,8'd56,8'd57,8'd58,8'd59,8'd60,8'd61,8'd62,8'd63 : bitgain = 18;
+	8'd65,8'd66,8'd67,8'd68,8'd69,8'd70,8'd71,8'd72,8'd73,8'd74,8'd75,8'd76,8'd77,8'd78,8'd79,8'd80 : bitgain = 19;
+	8'd81,8'd82,8'd83,8'd84,8'd85,8'd86,8'd87,8'd88,8'd89,8'd90,8'd91,8'd92,8'd93,8'd94,8'd95,8'd96,8'd97,8'd98,8'd99,8'd100,8'd101 : bitgain = 20;
+	
+	default : bitgain = 21;
+      endcase // case(rate)
+   endfunction // bitgain
+   
+   wire [4:0] 	  shift = bitgain(rate);
+   
+   // We should be able to do this, but can't ....
+   // assign 	  signal_out = signal_in[shift+bw-1:shift];
+   
+   always @*
+     case(shift)
+       5'd0  : signal_out = signal_in[0+bw-1:0];
+       5'd3  : signal_out = signal_in[3+bw-1:3];
+       5'd6  : signal_out = signal_in[6+bw-1:6];
+       5'd9  : signal_out = signal_in[9+bw-1:9];
+       5'd12 : signal_out = signal_in[12+bw-1:12];
+       5'd15 : signal_out = signal_in[15+bw-1:15];
+       5'd18 : signal_out = signal_in[18+bw-1:18];
+       5'd21 : signal_out = signal_in[21+bw-1:21];
+       
+       5'd5  : signal_out = signal_in[5+bw-1:5];
+       5'd7  : signal_out = signal_in[7+bw-1:7];
+       5'd8  : signal_out = signal_in[8+bw-1:8];
+       5'd10 : signal_out = signal_in[10+bw-1:10];
+       5'd11 : signal_out = signal_in[11+bw-1:11];
+       5'd13 : signal_out = signal_in[13+bw-1:13];
+       5'd14 : signal_out = signal_in[14+bw-1:14];
+       5'd16 : signal_out = signal_in[16+bw-1:16];
+       5'd17 : signal_out = signal_in[17+bw-1:17];
+       5'd19 : signal_out = signal_in[19+bw-1:19];
+       5'd20 : signal_out = signal_in[20+bw-1:20];
+       
+       default : signal_out = signal_in[21+bw-1:21];
+     endcase // case(shift)
+
+endmodule // cic_int_shifter
+
diff --git a/fpga/usrp3/lib/dsp/cic_interp.v b/fpga/usrp3/lib/dsp/cic_interp.v
new file mode 100644
index 000000000..b0fc74993
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/cic_interp.v
@@ -0,0 +1,77 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003 Matt Ettus
+// 
+//  SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+//
+
+
+module cic_interp
+  #(parameter bw = 16, parameter N = 4, parameter log2_of_max_rate = 7)
+    (input clock,
+     input reset,
+     input enable,
+     input [7:0] rate,
+     input strobe_in,
+     input strobe_out,
+     input [bw-1:0] signal_in,
+     output reg [bw-1:0] signal_out);
+   
+   integer 	     i;
+   localparam 	     maxbitgain = (N-1)*log2_of_max_rate;
+
+   wire [bw+maxbitgain-1:0] signal_in_ext;
+   reg [bw+maxbitgain-1:0]  integrator [0:N-1];
+   reg [bw+maxbitgain-1:0]  differentiator [0:N-1];
+   reg [bw+maxbitgain-1:0]  pipeline [0:N-1];
+   
+   sign_extend #(bw,bw+maxbitgain) 
+     ext_input (.in(signal_in),.out(signal_in_ext));
+   
+   //FIXME Note that this section has pipe and diff reversed
+   // It still works, but is confusing
+   always @(posedge clock)
+     if(reset | ~enable)
+       for(i=0;i<N;i=i+1)
+	 integrator[i] <= 0;
+     else if (enable & strobe_out)
+       begin
+	  if(strobe_in)
+	    integrator[0] <= integrator[0] + pipeline[N-1];
+	  for(i=1;i<N;i=i+1)
+	    integrator[i] <= integrator[i] + integrator[i-1];
+       end
+   
+   always @(posedge clock)
+     if(reset | ~enable)
+       begin
+	  for(i=0;i<N;i=i+1)
+	    begin
+	       differentiator[i] <= 0;
+	       pipeline[i] <= 0;
+ 	    end
+       end
+     else if (enable && strobe_in)
+       begin
+	  differentiator[0] <= signal_in_ext;
+	  pipeline[0] <= signal_in_ext - differentiator[0];
+	  for(i=1;i<N;i=i+1)
+	    begin
+	       differentiator[i] <= pipeline[i-1];
+	       pipeline[i] <= pipeline[i-1] - differentiator[i];
+	    end
+       end
+
+   wire [bw-1:0] signal_out_unreg;
+   cic_int_shifter #(bw)
+     cic_int_shifter(rate,integrator[N-1],signal_out_unreg);
+   
+   always @(posedge clock)
+     signal_out <= signal_out_unreg;
+   
+endmodule // cic_interp
+
diff --git a/fpga/usrp3/lib/dsp/cic_strober.v b/fpga/usrp3/lib/dsp/cic_strober.v
new file mode 100644
index 000000000..f37b11e6d
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/cic_strober.v
@@ -0,0 +1,35 @@
+//
+//  USRP2 - Universal Software Radio Peripheral Mk II
+//
+//  Copyright (C) 2008 Matt Ettus
+// 
+//  SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+//
+
+module cic_strober
+  #(parameter WIDTH=8)
+    ( input clock,
+      input reset,
+      input enable,
+      input [WIDTH-1:0] rate, // Rate should EQUAL to your desired divide ratio, no more -1 BS
+      input strobe_fast,
+      output wire strobe_slow );
+   
+   reg [WIDTH-1:0] counter;
+   wire      now = (counter==1);
+   assign    strobe_slow = now && enable && strobe_fast;
+   
+   always @(posedge clock)
+     if(reset)
+       counter <= 0; 
+     else if (~enable)
+       counter <= rate;
+     else if(strobe_fast)
+       if(now)
+	 counter <= rate;
+       else 
+	 counter <= counter - 1;
+   
+endmodule // cic_strober
diff --git a/fpga/usrp3/lib/dsp/clip.v b/fpga/usrp3/lib/dsp/clip.v
new file mode 100644
index 000000000..e68254e1f
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/clip.v
@@ -0,0 +1,26 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2008 Matt Ettus
+// 
+//  SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+//
+
+// Clipping "macro", keeps the bottom bits
+
+module clip
+  #(parameter bits_in=0,
+    parameter bits_out=0)
+    (input [bits_in-1:0] in,
+     output [bits_out-1:0] out);
+   
+   wire 		   overflow = |in[bits_in-1:bits_out-1] & ~(&in[bits_in-1:bits_out-1]);   
+   assign 		   out = overflow ? 
+			   (in[bits_in-1] ? {1'b1,{(bits_out-1){1'b0}}} : {1'b0,{(bits_out-1){1'b1}}}) :
+			   in[bits_out-1:0];
+   
+endmodule // clip
+
diff --git a/fpga/usrp3/lib/dsp/clip_reg.v b/fpga/usrp3/lib/dsp/clip_reg.v
new file mode 100644
index 000000000..b46491528
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/clip_reg.v
@@ -0,0 +1,36 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2008 Matt Ettus
+// 
+//  SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+//
+
+// Clipping "macro", keeps the bottom bits
+
+module clip_reg
+  #(parameter bits_in=0,
+    parameter bits_out=0,
+    parameter STROBED=1'b0)
+    (input clk,
+     input reset,
+     input [bits_in-1:0] in,
+     output reg [bits_out-1:0] out,
+     input strobe_in,
+     output reg strobe_out);
+   
+   wire [bits_out-1:0] temp;
+
+   clip #(.bits_in(bits_in),.bits_out(bits_out)) clip (.in(in),.out(temp));
+
+   always @(posedge clk) strobe_out <= reset ? 1'b0 : strobe_in;
+   
+   always @(posedge clk)
+     if(strobe_in | ~STROBED)
+       out <= temp;
+   
+endmodule // clip_reg
+
diff --git a/fpga/usrp3/lib/dsp/cordic_stage.v b/fpga/usrp3/lib/dsp/cordic_stage.v
new file mode 100644
index 000000000..64ce6ab62
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/cordic_stage.v
@@ -0,0 +1,50 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003 Matt Ettus
+// 
+//  SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+//
+
+module cordic_stage( clock, reset, enable, xi,yi,zi,constant,xo,yo,zo);
+   parameter bitwidth = 16;
+   parameter zwidth = 16;
+   parameter shift = 1;
+   
+   input     clock;
+   input     reset;
+   input     enable;
+   input [bitwidth-1:0] xi,yi;
+   input [zwidth-1:0] zi;
+   input [zwidth-1:0] constant;
+   output [bitwidth-1:0] xo,yo;
+   output [zwidth-1:0] zo;
+   
+   wire z_is_pos = ~zi[zwidth-1];
+
+   reg [bitwidth-1:0] 	 xo,yo;
+   reg [zwidth-1:0] zo;
+   
+   always @(posedge clock)
+     if(reset)
+       begin
+	  xo <= 0;
+	  yo <= 0;
+	  zo <= 0;
+       end
+     else //if(enable)
+       begin
+	  xo <= z_is_pos ?   
+		xi - {{shift+1{yi[bitwidth-1]}},yi[bitwidth-2:shift]} :
+		xi + {{shift+1{yi[bitwidth-1]}},yi[bitwidth-2:shift]};
+	  yo <= z_is_pos ?   
+		yi + {{shift+1{xi[bitwidth-1]}},xi[bitwidth-2:shift]} :
+		yi - {{shift+1{xi[bitwidth-1]}},xi[bitwidth-2:shift]};
+	  zo <= z_is_pos ?   
+		zi - constant :
+		zi + constant;
+       end
+endmodule
diff --git a/fpga/usrp3/lib/dsp/cordic_z24.v b/fpga/usrp3/lib/dsp/cordic_z24.v
new file mode 100644
index 000000000..7eab3478e
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/cordic_z24.v
@@ -0,0 +1,114 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003, 2007 Matt Ettus
+// 
+//  SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+//
+
+module cordic_z24(clock, reset, enable, xi, yi, zi, xo, yo, zo );
+   parameter bitwidth = 16;
+   parameter stages = 19;
+   localparam zwidth = 24;
+   
+   input clock;
+   input reset;
+   input enable;
+   input [bitwidth-1:0] xi, yi;
+   output [bitwidth-1:0] xo, yo;
+   input [zwidth-1:0] zi;
+   output [zwidth-1:0] zo;
+   
+   reg [bitwidth+1:0] 	 x0,y0;
+   reg [zwidth-2:0] 	 z0;
+   wire [bitwidth+1:0] 	 x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17,x18,x19,x20;
+   wire [bitwidth+1:0] 	 y1,y2,y3,y4,y5,y6,y7,y8,y9,y10,y11,y12,y13,y14,y15,y16,y17,y18,y19,y20;
+   wire [zwidth-2:0] 	 z1,z2,z3,z4,z5,z6,z7,z8,z9,z10,z11,z12,z13,z14,z15,z16,z17,z18,z19,z20;
+   
+   wire [bitwidth+1:0] xi_ext = {{2{xi[bitwidth-1]}},xi};
+   wire [bitwidth+1:0] yi_ext = {{2{yi[bitwidth-1]}},yi};
+
+   // Compute consts.  Would be easier if vlog had atan...
+   // see gen_cordic_consts.py
+
+   // constants for 24 bit wide phase
+   localparam 	       c00 = 23'd2097152;
+   localparam 	       c01 = 23'd1238021;
+   localparam 	       c02 = 23'd654136;
+   localparam 	       c03 = 23'd332050;
+   localparam 	       c04 = 23'd166669;
+   localparam 	       c05 = 23'd83416;
+   localparam 	       c06 = 23'd41718;
+   localparam 	       c07 = 23'd20860;
+   localparam 	       c08 = 23'd10430;
+   localparam 	       c09 = 23'd5215;
+   localparam 	       c10 = 23'd2608;
+   localparam 	       c11 = 23'd1304;
+   localparam 	       c12 = 23'd652;
+   localparam 	       c13 = 23'd326;
+   localparam 	       c14 = 23'd163;
+   localparam 	       c15 = 23'd81;
+   localparam 	       c16 = 23'd41;
+   localparam 	       c17 = 23'd20;
+   localparam 	       c18 = 23'd10;
+   localparam 	       c19 = 23'd5;
+   localparam 	       c20 = 23'd3;
+   localparam 	       c21 = 23'd1;
+   localparam 	       c22 = 23'd1;
+   localparam 	       c23 = 23'd0;
+
+   always @(posedge clock)
+     if(reset)
+       begin
+	  x0   <= 0; y0   <= 0;  z0   <= 0;
+       end
+     else// if(enable)
+       begin
+	  z0 <= zi[zwidth-2:0];
+	  case (zi[zwidth-1:zwidth-2])
+	    2'b00, 2'b11 : 
+	      begin
+		 x0 <= xi_ext;
+		 y0 <= yi_ext;
+	      end
+	    2'b01, 2'b10 :
+	      begin
+		 x0 <= -xi_ext;
+		 y0 <= -yi_ext;
+	      end
+	  endcase // case(zi[zwidth-1:zwidth-2])
+       end // else: !if(reset)
+   
+   // FIXME need to handle variable number of stages
+   // This would be easier if arrays worked better in vlog...
+   
+   cordic_stage #(bitwidth+2,zwidth-1,0) cordic_stage0 (clock,reset,enable,x0,y0,z0,c00,x1,y1,z1);
+   cordic_stage #(bitwidth+2,zwidth-1,1) cordic_stage1 (clock,reset,enable,x1,y1,z1,c01,x2,y2,z2);
+   cordic_stage #(bitwidth+2,zwidth-1,2) cordic_stage2 (clock,reset,enable,x2,y2,z2,c02,x3,y3,z3);
+   cordic_stage #(bitwidth+2,zwidth-1,3) cordic_stage3 (clock,reset,enable,x3,y3,z3,c03,x4,y4,z4);
+   cordic_stage #(bitwidth+2,zwidth-1,4) cordic_stage4 (clock,reset,enable,x4,y4,z4,c04,x5,y5,z5);
+   cordic_stage #(bitwidth+2,zwidth-1,5) cordic_stage5 (clock,reset,enable,x5,y5,z5,c05,x6,y6,z6);
+   cordic_stage #(bitwidth+2,zwidth-1,6) cordic_stage6 (clock,reset,enable,x6,y6,z6,c06,x7,y7,z7);
+   cordic_stage #(bitwidth+2,zwidth-1,7) cordic_stage7 (clock,reset,enable,x7,y7,z7,c07,x8,y8,z8);
+   cordic_stage #(bitwidth+2,zwidth-1,8) cordic_stage8 (clock,reset,enable,x8,y8,z8,c08,x9,y9,z9);
+   cordic_stage #(bitwidth+2,zwidth-1,9) cordic_stage9 (clock,reset,enable,x9,y9,z9,c09,x10,y10,z10);
+   cordic_stage #(bitwidth+2,zwidth-1,10) cordic_stage10 (clock,reset,enable,x10,y10,z10,c10,x11,y11,z11);
+   cordic_stage #(bitwidth+2,zwidth-1,11) cordic_stage11 (clock,reset,enable,x11,y11,z11,c11,x12,y12,z12);
+   cordic_stage #(bitwidth+2,zwidth-1,12) cordic_stage12 (clock,reset,enable,x12,y12,z12,c12,x13,y13,z13);
+   cordic_stage #(bitwidth+2,zwidth-1,13) cordic_stage13 (clock,reset,enable,x13,y13,z13,c13,x14,y14,z14);
+   cordic_stage #(bitwidth+2,zwidth-1,14) cordic_stage14 (clock,reset,enable,x14,y14,z14,c14,x15,y15,z15);
+   cordic_stage #(bitwidth+2,zwidth-1,15) cordic_stage15 (clock,reset,enable,x15,y15,z15,c15,x16,y16,z16);
+   cordic_stage #(bitwidth+2,zwidth-1,16) cordic_stage16 (clock,reset,enable,x16,y16,z16,c16,x17,y17,z17);
+   cordic_stage #(bitwidth+2,zwidth-1,17) cordic_stage17 (clock,reset,enable,x17,y17,z17,c17,x18,y18,z18);
+   cordic_stage #(bitwidth+2,zwidth-1,18) cordic_stage18 (clock,reset,enable,x18,y18,z18,c18,x19,y19,z19);
+   cordic_stage #(bitwidth+2,zwidth-1,19) cordic_stage19 (clock,reset,enable,x19,y19,z19,c19,x20,y20,z20);
+
+   assign xo = x20[bitwidth:1];  
+   assign yo = y20[bitwidth:1];
+   assign zo = z20;		  
+
+endmodule // cordic
+
diff --git a/fpga/usrp3/lib/dsp/ddc_chain.v b/fpga/usrp3/lib/dsp/ddc_chain.v
new file mode 100644
index 000000000..9c25d8e43
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/ddc_chain.v
@@ -0,0 +1,375 @@
+//
+// Copyright 2011-2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+//! The USRP digital down-conversion chain
+
+module ddc_chain
+  #(
+    parameter BASE = 0,
+    parameter DSPNO = 0,
+    parameter WIDTH = 24,
+    parameter NEW_HB_DECIM = 0,
+    parameter DEVICE = "SPARTAN6"
+  )
+  (input clk, input rst, input clr,
+   input 	     set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+   // From RX frontend
+   input [WIDTH-1:0] rx_fe_i,
+   input [WIDTH-1:0] rx_fe_q,
+
+   // To RX control
+   output [31:0] sample,
+   input 	     run,
+   output 	     strobe,
+   output [31:0]     debug
+   );
+
+   localparam  cwidth = 25;
+   localparam  zwidth = 24;
+
+   wire [31:0] phase_inc;
+   reg [31:0]  phase;
+
+   wire [17:0] scale_factor;
+   wire [cwidth-1:0] to_cordic_i, to_cordic_q;
+   wire [cwidth-1:0] i_cordic, q_cordic;
+   reg  [WIDTH-1:0] i_cordic_pipe, q_cordic_pipe;
+   wire [WIDTH-1:0] i_cic, q_cic;
+
+
+   wire        strobe_cic, strobe_hb1, strobe_hb2;
+   wire        enable_hb1, enable_hb2;
+   wire [7:0]  cic_decim_rate;
+
+   reg [WIDTH-1:0]  rx_fe_i_mux, rx_fe_q_mux;
+   wire        realmode;
+   wire        swap_iq;
+   wire        invert_i;
+   wire        invert_q;
+
+   setting_reg #(.my_addr(BASE+0)) sr_0
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(phase_inc),.changed());
+
+   setting_reg #(.my_addr(BASE+1), .width(18)) sr_1
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(scale_factor),.changed());
+
+   setting_reg #(.my_addr(BASE+2), .width(10)) sr_2
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({enable_hb1, enable_hb2, cic_decim_rate}),.changed());
+
+   setting_reg #(.my_addr(BASE+3), .width(4)) sr_3
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({invert_i,invert_q,realmode,swap_iq}),.changed());
+
+
+   // MUX so we can do realmode signals on either input
+
+   always @(posedge clk)
+     if(swap_iq)
+       begin
+          rx_fe_i_mux <= invert_i ? ~rx_fe_q : rx_fe_q;
+          rx_fe_q_mux <= realmode ? {WIDTH{1'b0}} : invert_q ? ~rx_fe_i : rx_fe_i;
+       end
+     else
+       begin
+	  rx_fe_i_mux <= invert_i ? ~rx_fe_i : rx_fe_i;
+          rx_fe_q_mux <= realmode ? {WIDTH{1'b0}} : invert_q ? ~rx_fe_q : rx_fe_q;
+       end
+
+   // NCO
+   always @(posedge clk)
+     if(rst)
+       phase <= 0;
+     else if(~run)
+       phase <= 0;
+     else
+       phase <= phase + phase_inc;
+
+   // CORDIC  24-bit I/O
+   // (Algorithmic gain through CORDIC => 1.647 * 0.5 = 0.8235)
+   // (Worst case gain through rotation => SQRT(2) = 1.4142)
+   // Total worst case gain => 0.8235 * 1.4142 = 1.1646
+   // So add an extra MSB bit for word growth.
+
+   sign_extend #(.bits_in(WIDTH), .bits_out(cwidth)) sign_extend_cordic_i (.in(rx_fe_i_mux), .out(to_cordic_i));
+   sign_extend #(.bits_in(WIDTH), .bits_out(cwidth)) sign_extend_cordic_q (.in(rx_fe_q_mux), .out(to_cordic_q));
+
+   cordic_z24 #(.bitwidth(cwidth))
+   cordic(.clock(clk), .reset(rst), .enable(run),
+	  .xi(to_cordic_i),. yi(to_cordic_q), .zi(phase[31:32-zwidth]),
+	  .xo(i_cordic),.yo(q_cordic),.zo() );
+
+   always @(posedge clk) begin
+      i_cordic_pipe[23:0] <= i_cordic[24:1];
+      q_cordic_pipe[23:0] <= q_cordic[24:1];
+   end
+
+
+   // CIC decimator  24 bit I/O
+   // Applies crude 1/(2^N) right shift gain compensation internally to prevent excesive downstream word growth.
+   // Output gain is = algo_gain/(POW(2,CEIL(LOG2(algo_gain))) where algo_gain is = cic_decim_rate^4
+   // Thus output gain is <= 1.0 and no word growth occurs.
+   cic_strober cic_strober(.clock(clk),.reset(rst),.enable(run),.rate(cic_decim_rate),
+			   .strobe_fast(1'b1),.strobe_slow(strobe_cic) );
+
+   cic_decim #(.bw(WIDTH))
+     decim_i (.clock(clk),.reset(rst),.enable(run),
+	      .rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic),
+	      .signal_in(i_cordic_pipe),.signal_out(i_cic));
+
+   cic_decim #(.bw(WIDTH))
+     decim_q (.clock(clk),.reset(rst),.enable(run),
+	      .rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic),
+	      .signal_in(q_cordic_pipe),.signal_out(q_cic));
+
+   //////////////////////////////////////////////////////////////////////////
+   //
+   // Conditional compilation of either:
+   // 1) New X300 style decimation filters, or
+   // 2) Traditional N210 style decimation filters.
+   //
+   //////////////////////////////////////////////////////////////////////////
+   generate
+      if (NEW_HB_DECIM == 1) begin: new_hb
+
+	 wire        reload_go, reload_we1, reload_we2,  reload_ld1, reload_ld2;
+	 wire [17:0] coef_din;
+
+	 setting_reg #(.my_addr(BASE+4), .width(22)) sr_4
+	   (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+	    .in(set_data),.out({reload_ld2,reload_we2,reload_ld1,reload_we1,coef_din[17:0]}),.changed(reload_go));
+
+	 // Halfbands
+	 wire 	     nd1, nd2, nd3;
+	 wire 	     rfd1, rfd2, rfd3;
+	 wire 	     rdy1, rdy2, rdy3;
+	 wire 	     data_valid1, data_valid2, data_valid3;
+	 wire [46:0] i_hb1, q_hb1;
+	 wire [46:0] i_hb2, q_hb2;
+	 localparam HB1_SCALE = 18;
+	 localparam HB2_SCALE = 18;
+
+
+	 assign strobe_hb1 = data_valid1;
+	 assign strobe_hb2 = data_valid2;
+
+	 assign nd1 = strobe_cic;
+	 assign nd2 = strobe_hb1;
+
+	 // Default Coeffs have gain of ~1.0
+	 hbdec1 hbdec1
+	   (.clk(clk), // input clk
+	    .sclr(rst), // input sclr
+	    .ce(enable_hb1), // input ce
+	    .coef_ld(reload_go & reload_ld1), // input coef_ld
+	    .coef_we(reload_go & reload_we1), // input coef_we
+	    .coef_din(coef_din), // input [17 : 0] coef_din
+	    .rfd(rfd1), // output rfd
+	    .nd(nd1), // input nd
+	    .din_1(i_cic), // input [23 : 0] din_1
+	    .din_2(q_cic), // input [23 : 0] din_2
+	    .rdy(rdy1), // output rdy
+	    .data_valid(data_valid1), // output data_valid
+	    .dout_1(i_hb1), // output [46 : 0] dout_1
+	    .dout_2(q_hb1)); // output [46 : 0] dout_2
+
+	 // Default Coeffs have gain of ~1.0
+	 hbdec2 hbdec2
+	   (.clk(clk), // input clk
+	    .sclr(rst), // input sclr
+	    .ce(enable_hb2), // input ce
+	    .coef_ld(reload_go & reload_ld2), // input coef_ld
+	    .coef_we(reload_go & reload_we2), // input coef_we
+	    .coef_din(coef_din), // input [17 : 0] coef_din
+	    .rfd(rfd2), // output rfd
+	    .nd(nd2), // input nd
+	    .din_1(i_hb1[23+HB1_SCALE:HB1_SCALE]), // input [23 : 0] din_1
+	    .din_2(q_hb1[23+HB1_SCALE:HB1_SCALE]), // input [23 : 0] din_2
+	    .rdy(rdy2), // output rdy
+	    .data_valid(data_valid2), // output data_valid
+	    .dout_1(i_hb2), // output [46 : 0] dout_1
+	    .dout_2(q_hb2)); // output [46 : 0] dout_2
+
+
+
+	 reg [18:0]  i_unscaled, q_unscaled;
+	 reg 	     strobe_unscaled;
+
+	 always @(posedge clk)
+	   case({enable_hb1,enable_hb2})
+	     // No Halfbands enabled, no decimation.
+	     2'd0 :
+	       begin
+		  strobe_unscaled <= strobe_cic;
+		  i_unscaled <= i_cic[23:5];
+		  q_unscaled <= q_cic[23:5];
+	       end
+	     // ILLEGAL. Only half sample rate half band enabled.
+	     2'd1 :
+	       begin
+		  strobe_unscaled <= strobe_cic;
+		  i_unscaled <= i_cic[23:5];
+		  q_unscaled <= q_cic[23:5];
+	       end
+	     // One Halfband enabled, decimate by 2.
+	     2'd2 :
+	       begin
+		  strobe_unscaled <= strobe_hb1;
+		  i_unscaled <= i_hb1[23+HB1_SCALE:5+HB1_SCALE];
+		  q_unscaled <= q_hb1[23+HB1_SCALE:5+HB1_SCALE];
+	       end
+	     // Both Halfbands enabled, decimate by 4.
+	     2'd3 :
+	       begin
+		  strobe_unscaled <= strobe_hb2;
+		  i_unscaled <= i_hb2[23+HB2_SCALE:5+HB2_SCALE];
+		  q_unscaled <= q_hb2[23+HB2_SCALE:5+HB2_SCALE];
+	     end
+	   endcase // case (hb_rate)
+
+	 // Need to clip 1 bit here or we loose small signal performance out the truncated LSB's for worst case CIC gain cases.
+	 // NOTE: We can only clip here with CORDIC rotating, CIC in it's highest gain configurations and an input signal thats
+	 // saturated.
+	 wire strobe_unscaled_clip;
+	 wire [17:0] i_unscaled_clip, q_unscaled_clip;
+
+	 clip_reg #(.bits_in(19), .bits_out(18), .STROBED(1)) unscaled_clip_i
+	   (.clk(clk), .in(i_unscaled[18:0]), .strobe_in(strobe_unscaled), .out(i_unscaled_clip[17:0]), .strobe_out(strobe_unscaled_clip));
+	 clip_reg #(.bits_in(19), .bits_out(18), .STROBED(1)) unscaled_clip_q
+	   (.clk(clk), .in(q_unscaled[18:0]), .strobe_in(strobe_unscaled), .out(q_unscaled_clip[17:0]), .strobe_out());
+
+	 // Apply scaling gain to compensate for CORDIC and CIC gain adjustments so that signal swing over network transport has
+	 // optimal dynamic range.
+	 wire [35:0] 	  prod_i, prod_q;
+
+	 MULT_MACRO #(.DEVICE(DEVICE),  // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6","7SERIES"
+		      .LATENCY(1),         // Desired clock cycle latency, 0-4
+		      .WIDTH_A(18),        // Multiplier A-input bus width, 1-25
+		      .WIDTH_B(18))        // Multiplier B-input bus width, 1-18
+	 mult_i (.P(prod_i),             // Multiplier output bus, width determined by WIDTH_P parameter
+		.A(i_unscaled_clip),         // Multiplier input A bus, width determined by WIDTH_A parameter
+		.B(scale_factor),       // Multiplier input B bus, width determined by WIDTH_B parameter
+		.CE(strobe_unscaled_clip),   // 1-bit active high input clock enable
+		.CLK(clk),              // 1-bit positive edge clock input
+		.RST(rst));             // 1-bit input active high reset
+
+	 MULT_MACRO #(.DEVICE(DEVICE),  // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6","7SERIES"
+		      .LATENCY(1),         // Desired clock cycle latency, 0-4
+		      .WIDTH_A(18),        // Multiplier A-input bus width, 1-25
+		      .WIDTH_B(18))        // Multiplier B-input bus width, 1-18
+	 mult_q (.P(prod_q),             // Multiplier output bus, width determined by WIDTH_P parameter
+		.A(q_unscaled_clip),         // Multiplier input A bus, width determined by WIDTH_A parameter
+		.B(scale_factor),       // Multiplier input B bus, width determined by WIDTH_B parameter
+		.CE(strobe_unscaled_clip),   // 1-bit active high input clock enable
+		.CLK(clk),              // 1-bit positive edge clock input
+		.RST(rst));             // 1-bit input active high reset
+
+	 reg 		  strobe_scaled;
+	 wire 		  strobe_clip;
+	 wire [32:0] 	  i_clip, q_clip;
+
+	 always @(posedge clk)  strobe_scaled <= strobe_unscaled_clip;
+
+	 clip_reg #(.bits_in(36), .bits_out(33), .STROBED(1)) clip_i
+	   (.clk(clk), .in(prod_i[35:0]), .strobe_in(strobe_scaled), .out(i_clip), .strobe_out(strobe_clip));
+	 clip_reg #(.bits_in(36), .bits_out(33), .STROBED(1)) clip_q
+	   (.clk(clk), .in(prod_q[35:0]), .strobe_in(strobe_scaled), .out(q_clip), .strobe_out());
+
+	 round_sd #(.WIDTH_IN(33), .WIDTH_OUT(16)) round_i
+	   (.clk(clk), .reset(rst), .in(i_clip), .strobe_in(strobe_clip), .out(sample[31:16]), .strobe_out(strobe));
+	 round_sd #(.WIDTH_IN(33), .WIDTH_OUT(16)) round_q
+	   (.clk(clk), .reset(rst), .in(q_clip), .strobe_in(strobe_clip), .out(sample[15:0]), .strobe_out());
+
+      end else begin: old_hb // block: new_hb
+	 ///////////////////////////////////////////////
+	 //
+	 // Legacy Decimation Filters from USRP2
+	 //
+	 ///////////////////////////////////////////////
+	 wire [WIDTH-1:0] i_hb1, q_hb1;
+	 wire [WIDTH-1:0] i_hb2, q_hb2;
+	 // First (small) halfband  24 bit I/O
+	 small_hb_dec #(.WIDTH(WIDTH),.DEVICE(DEVICE)) small_hb_i
+	   (.clk(clk),.rst(rst),.bypass(~enable_hb1),.run(run),
+	    .stb_in(strobe_cic),.data_in(i_cic),.stb_out(strobe_hb1),.data_out(i_hb1));
+
+	 small_hb_dec #(.WIDTH(WIDTH),.DEVICE(DEVICE)) small_hb_q
+	   (.clk(clk),.rst(rst),.bypass(~enable_hb1),.run(run),
+	    .stb_in(strobe_cic),.data_in(q_cic),.stb_out(),.data_out(q_hb1));
+
+	 // Second (large) halfband  24 bit I/O
+	 wire [8:0] 	  cpi_hb = enable_hb1 ? {cic_decim_rate,1'b0} : {1'b0,cic_decim_rate};
+	 hb_dec #(.WIDTH(WIDTH),.DEVICE(DEVICE)) hb_i
+	   (.clk(clk),.rst(rst),.bypass(~enable_hb2),.run(run),.cpi(cpi_hb),
+	    .stb_in(strobe_hb1),.data_in(i_hb1),.stb_out(strobe_hb2),.data_out(i_hb2));
+
+	 hb_dec #(.WIDTH(WIDTH),.DEVICE(DEVICE)) hb_q
+	   (.clk(clk),.rst(rst),.bypass(~enable_hb2),.run(run),.cpi(cpi_hb),
+	    .stb_in(strobe_hb1),.data_in(q_hb1),.stb_out(),.data_out(q_hb2));
+
+	 // Need to clip 1 bit here or we loose small signal performance out the truncated LSB's for worst case CIC gain cases.
+	 wire strobe_unscaled_clip;
+	 wire [17:0] i_unscaled_clip, q_unscaled_clip;
+
+	 clip_reg #(.bits_in(19), .bits_out(18), .STROBED(1)) unscaled_clip_i
+	   (.clk(clk), .in(i_hb2[WIDTH-1:WIDTH-19]), .strobe_in(strobe_hb2), .out(i_unscaled_clip[17:0]), .strobe_out(strobe_unscaled_clip));
+	 clip_reg #(.bits_in(19), .bits_out(18), .STROBED(1)) unscaled_clip_q
+	   (.clk(clk), .in(q_hb2[WIDTH-1:WIDTH-19]), .strobe_in(strobe_hb2), .out(q_unscaled_clip[17:0]), .strobe_out());
+
+	 //scalar operation (gain of 6 bits)
+	 wire [35:0] 	  prod_i, prod_q;
+
+	 MULT_MACRO #(.DEVICE(DEVICE),  // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6","7SERIES"
+		      .LATENCY(1),         // Desired clock cycle latency, 0-4
+		      .WIDTH_A(18),        // Multiplier A-input bus width, 1-25
+		      .WIDTH_B(18))        // Multiplier B-input bus width, 1-18
+	 mult_i (.P(prod_i),             // Multiplier output bus, width determined by WIDTH_P parameter
+		.A(i_unscaled_clip),// Multiplier input A bus, width determined by WIDTH_A parameter
+		.B(scale_factor),       // Multiplier input B bus, width determined by WIDTH_B parameter
+		.CE(strobe_unscaled_clip),        // 1-bit active high input clock enable
+		.CLK(clk),              // 1-bit positive edge clock input
+		.RST(rst));             // 1-bit input active high reset
+
+	 MULT_MACRO #(.DEVICE(DEVICE),  // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6","7SERIES"
+		      .LATENCY(1),         // Desired clock cycle latency, 0-4
+		      .WIDTH_A(18),        // Multiplier A-input bus width, 1-25
+		      .WIDTH_B(18))        // Multiplier B-input bus width, 1-18
+	 mult_q (.P(prod_q),             // Multiplier output bus, width determined by WIDTH_P parameter
+		.A(q_unscaled_clip),// Multiplier input A bus, width determined by WIDTH_A parameter
+		.B(scale_factor),       // Multiplier input B bus, width determined by WIDTH_B parameter
+		.CE(strobe_unscaled_clip),        // 1-bit active high input clock enable
+		.CLK(clk),              // 1-bit positive edge clock input
+		.RST(rst));             // 1-bit input active high reset
+
+	 reg 		  strobe_scaled;
+	 wire 		  strobe_clip;
+	 wire [32:0] 	  i_clip, q_clip;
+
+	 always @(posedge clk)  strobe_scaled <= strobe_unscaled_clip;
+
+	 clip_reg #(.bits_in(36), .bits_out(33), .STROBED(1)) clip_i
+	   (.clk(clk), .in(prod_i[35:0]), .strobe_in(strobe_scaled), .out(i_clip), .strobe_out(strobe_clip));
+	 clip_reg #(.bits_in(36), .bits_out(33), .STROBED(1)) clip_q
+	   (.clk(clk), .in(prod_q[35:0]), .strobe_in(strobe_scaled), .out(q_clip), .strobe_out());
+
+	 round_sd #(.WIDTH_IN(33), .WIDTH_OUT(16)) round_i
+	   (.clk(clk), .reset(rst), .in(i_clip), .strobe_in(strobe_clip), .out(sample[31:16]), .strobe_out(strobe));
+	 round_sd #(.WIDTH_IN(33), .WIDTH_OUT(16)) round_q
+	   (.clk(clk), .reset(rst), .in(q_clip), .strobe_in(strobe_clip), .out(sample[15:0]), .strobe_out());
+
+      end // block: old_hb
+   endgenerate
+
+
+
+   assign debug = {enable_hb1, enable_hb2, run, strobe, strobe_cic, strobe_hb1, strobe_hb2};
+
+endmodule // ddc_chain
diff --git a/fpga/usrp3/lib/dsp/duc_chain.v b/fpga/usrp3/lib/dsp/duc_chain.v
new file mode 100644
index 000000000..44931318c
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/duc_chain.v
@@ -0,0 +1,244 @@
+//
+// Copyright 2011-2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+//! The USRP digital up-conversion chain
+
+module duc_chain
+  #(
+    parameter BASE = 0,
+    parameter DSPNO = 0,
+    parameter WIDTH = 24,
+    parameter NEW_HB_INTERP = 0,
+    parameter DEVICE = "7SERIES"
+  )
+  (input clk, input rst, input clr,
+   input set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+   // To TX frontend
+   output [WIDTH-1:0] tx_fe_i,
+   output [WIDTH-1:0] tx_fe_q,
+
+   // From TX control
+   input [31:0] sample,
+   input run,
+   output strobe,
+   output [31:0] debug
+   );
+
+   genvar 	 i;
+
+
+   wire [17:0] scale_factor;
+   wire [31:0] phase_inc;
+   reg [31:0]  phase;
+   wire [7:0]  interp_rate;
+   wire [3:0]  tx_femux_a, tx_femux_b;
+   wire        enable_hb1, enable_hb2;
+   wire        rate_change;
+
+   setting_reg #(.my_addr(BASE+0)) sr_0
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(phase_inc),.changed());
+
+   setting_reg #(.my_addr(BASE+1), .width(18)) sr_1
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(scale_factor),.changed());
+
+   setting_reg #(.my_addr(BASE+2), .width(10)) sr_2
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({enable_hb1, enable_hb2, interp_rate}),.changed(rate_change));
+
+   // Strobes are all now delayed by 1 cycle for timing reasons
+   wire        strobe_cic_pre, strobe_hb1_pre, strobe_hb2_pre;
+   reg 	       strobe_cic = 1;
+   reg 	       strobe_hb1 = 1;
+   reg 	       strobe_hb2 = 1;
+
+  assign strobe = strobe_hb1;
+
+   cic_strober #(.WIDTH(8))
+     cic_strober(.clock(clk),.reset(rst),.enable(run & ~rate_change),.rate(interp_rate),
+		 .strobe_fast(1'b1),.strobe_slow(strobe_cic_pre) );
+   cic_strober #(.WIDTH(2))
+     hb2_strober(.clock(clk),.reset(rst),.enable(run & ~rate_change),.rate(enable_hb2 ? 2'd2 : 2'd1),
+		 .strobe_fast(strobe_cic_pre),.strobe_slow(strobe_hb2_pre) );
+   cic_strober #(.WIDTH(2))
+     hb1_strober(.clock(clk),.reset(rst),.enable(run & ~rate_change),.rate(enable_hb1 ? 2'd2 : 2'd1),
+		 .strobe_fast(strobe_hb2_pre),.strobe_slow(strobe_hb1_pre) );
+
+   always @(posedge clk) strobe_hb1 <= strobe_hb1_pre;
+   always @(posedge clk) strobe_hb2 <= strobe_hb2_pre;
+   always @(posedge clk) strobe_cic <= strobe_cic_pre;
+
+   // NCO
+   always @(posedge clk)
+     if(rst)
+       phase <= 0;
+     else if(~run)
+       phase <= 0;
+     else
+       phase <= phase + phase_inc;
+
+   wire        signed [17:0] da, db;
+   wire        signed [35:0] prod_i, prod_q;
+
+   wire [17:0] i_interp, q_interp;
+
+   wire [17:0] hb1_i, hb1_q, hb2_i, hb2_q;
+
+   wire [7:0]  cpo = enable_hb2 ? ({interp_rate,1'b0}) : interp_rate;
+   // Note that max CIC rate is 128, which would give an overflow on cpo if enable_hb2 is true,
+   //   but the default case inside hb_interp handles this
+   generate
+      if (NEW_HB_INTERP == 1) begin: new_hb
+	 // First stage of halfband interpolation filters. These run at a max CPO of 2 when CIC is bypassed and HB2 enabled.
+	 hb47_int
+	   #(.WIDTH(18),
+	     .DEVICE(DEVICE))
+	     hb1_i0
+	       (
+		.clk(clk),
+		.rst(rst),
+		.bypass(~enable_hb1),
+		.stb_in(strobe_hb1),
+		.data_in({sample[31:16],2'b00}),
+		.output_rate(cpo),
+		.stb_out(strobe_hb2),
+		.data_out(hb1_i)
+		);
+
+	 hb47_int
+	   #(.WIDTH(18),
+	     .DEVICE(DEVICE))
+	     hb1_q0
+	       (
+		.clk(clk),
+		.rst(rst),
+		.bypass(~enable_hb1),
+		.stb_in(strobe_hb1),
+		.data_in({sample[15:0],2'b00}),
+		.output_rate(cpo),
+		.stb_out(strobe_hb2),
+		.data_out(hb1_q)
+		);
+
+	 // Second stage of halfband interpolation filters. These run at a max CPO of 1 when CIC is bypassed.
+	 hb47_int
+	   #(.WIDTH(18),
+	     .DEVICE(DEVICE))
+	     hb2_i0
+	       (
+		.clk(clk),
+		.rst(rst),
+		.bypass(~enable_hb2),
+		.stb_in(strobe_hb2),
+		.data_in(hb1_i),
+		.output_rate(interp_rate),
+		.stb_out(strobe_cic),
+		.data_out(hb2_i)
+		);
+
+	 hb47_int
+	   #(.WIDTH(18),
+	     .DEVICE(DEVICE))
+	     hb2_q0
+	       (
+		.clk(clk),
+		.rst(rst),
+		.bypass(~enable_hb2),
+		.stb_in(strobe_hb2),
+		.data_in(hb1_q),
+		.output_rate(interp_rate),
+		.stb_out(strobe_cic),
+		.data_out(hb2_q)
+		);
+
+      end else begin: old_hb
+
+	 hb_interp #(.IWIDTH(18),.OWIDTH(18),.ACCWIDTH(WIDTH)) hb_interp_i
+	   (.clk(clk),.rst(rst),.bypass(~enable_hb1),.cpo(cpo),.stb_in(strobe_hb1),.data_in({sample[31:16], 2'b0}),.stb_out(strobe_hb2),.data_out(hb1_i));
+	 hb_interp #(.IWIDTH(18),.OWIDTH(18),.ACCWIDTH(WIDTH)) hb_interp_q
+	   (.clk(clk),.rst(rst),.bypass(~enable_hb1),.cpo(cpo),.stb_in(strobe_hb1),.data_in({sample[15:0], 2'b0}),.stb_out(strobe_hb2),.data_out(hb1_q));
+
+	 small_hb_int #(.WIDTH(18)) small_hb_interp_i
+	   (.clk(clk),.rst(rst),.bypass(~enable_hb2),.stb_in(strobe_hb2),.data_in(hb1_i),
+	    .output_rate(interp_rate),.stb_out(strobe_cic),.data_out(hb2_i));
+	 small_hb_int #(.WIDTH(18)) small_hb_interp_q
+	   (.clk(clk),.rst(rst),.bypass(~enable_hb2),.stb_in(strobe_hb2),.data_in(hb1_q),
+	    .output_rate(interp_rate),.stb_out(strobe_cic),.data_out(hb2_q));
+
+      end // block: old_hb
+   endgenerate
+
+   cic_interp  #(.bw(18),.N(4),.log2_of_max_rate(7))
+     cic_interp_i(.clock(clk),.reset(rst),.enable(run & ~rate_change),.rate(interp_rate),
+		  .strobe_in(strobe_cic),.strobe_out(1'd1),
+		  .signal_in(hb2_i),.signal_out(i_interp));
+
+   cic_interp  #(.bw(18),.N(4),.log2_of_max_rate(7))
+     cic_interp_q(.clock(clk),.reset(rst),.enable(run & ~rate_change),.rate(interp_rate),
+		  .strobe_in(strobe_cic),.strobe_out(1'd1),
+		  .signal_in(hb2_q),.signal_out(q_interp));
+
+   localparam  cwidth = WIDTH;  // was 18
+   localparam  zwidth = 24;  // was 16
+
+   wire [cwidth-1:0] da_c, db_c;
+   //
+   // Note. No head room has been added to the CORDIC to accomodate gain in excess of the input signals dynamic range.
+   // The CORDIC has algorithmic gain of 1.647, implementation gain of 0.5 and potential gain associated with rotation of 1.414.
+   // Thus the CORDIC will overflow when rotating and an input CW with (clipped) effective amplitude of 1.22 is applied.
+   //
+   cordic_z24 #(.bitwidth(cwidth))
+     cordic(.clock(clk), .reset(rst), .enable(run),
+	    .xi({i_interp,{(cwidth-18){1'b0}}}),.yi({q_interp,{(cwidth-18){1'b0}}}),
+	    .zi(phase[31:32-zwidth]),
+	    .xo(da_c),.yo(db_c),.zo() );
+
+   MULT_MACRO #(.DEVICE(DEVICE),  // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6","7SERIES"
+		.LATENCY(1),         // Desired clock cycle latency, 0-4
+		.WIDTH_A(18),        // Multiplier A-input bus width, 1-25
+		.WIDTH_B(18))        // Multiplier B-input bus width, 1-18
+   mult_i (.P(prod_i),             // Multiplier output bus, width determined by WIDTH_P parameter
+	   .A(da_c[cwidth-1:cwidth-18]),// Multiplier input A bus, width determined by WIDTH_A parameter
+	   .B(scale_factor),       // Multiplier input B bus, width determined by WIDTH_B parameter
+	   .CE(1'b1),              // 1-bit active high input clock enable
+	   .CLK(clk),              // 1-bit positive edge clock input
+	   .RST(rst));             // 1-bit input active high reset
+
+   MULT_MACRO #(.DEVICE(DEVICE),  // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6","7SERIES"
+		.LATENCY(1),         // Desired clock cycle latency, 0-4
+		.WIDTH_A(18),        // Multiplier A-input bus width, 1-25
+		.WIDTH_B(18))        // Multiplier B-input bus width, 1-18
+   mult_q (.P(prod_q),             // Multiplier output bus, width determined by WIDTH_P parameter
+	   .A(db_c[cwidth-1:cwidth-18]),// Multiplier input A bus, width determined by WIDTH_A parameter
+	   .B(scale_factor),       // Multiplier input B bus, width determined by WIDTH_B parameter
+	   .CE(1'b1),              // 1-bit active high input clock enable
+	   .CLK(clk),              // 1-bit positive edge clock input
+	   .RST(rst));             // 1-bit input active high reset
+
+
+   wire [32:0] 	     i_clip, q_clip;
+
+   // Cordic rotation coupled with a saturated input signal can cause overflow
+   // so we clip here rather than allow a wrap.
+   clip_reg #(.bits_in(36), .bits_out(33), .STROBED(1)) clip_i
+     (.clk(clk), .in(prod_i[35:0]), .strobe_in(1'b1), .out(i_clip), .strobe_out());
+   clip_reg #(.bits_in(36), .bits_out(33), .STROBED(1)) clip_q
+     (.clk(clk), .in(prod_q[35:0]), .strobe_in(1'b1), .out(q_clip), .strobe_out());
+
+   assign tx_fe_i = i_clip[32:33-WIDTH];
+   assign tx_fe_q = q_clip[32:33-WIDTH];
+
+
+   //
+   // Debug
+   //
+   assign 	     debug = {strobe_cic, strobe_hb1, strobe_hb2,run};
+
+endmodule // duc_chain
diff --git a/fpga/usrp3/lib/dsp/hb47_int.v b/fpga/usrp3/lib/dsp/hb47_int.v
new file mode 100644
index 000000000..3f69952cc
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/hb47_int.v
@@ -0,0 +1,180 @@
+//
+// Copyright 2011-2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+module hb47_int
+  #(parameter WIDTH=18,
+    parameter DEVICE="7SERIES")
+    (input clk,
+     input rst,
+     input bypass,
+     input stb_in,
+     input [WIDTH-1:0] data_in,
+     input [7:0] output_rate,
+     input stb_out,
+     output reg [WIDTH-1:0] data_out);
+
+   // Input data Pipeline
+   reg [WIDTH-1:0] data_in_pipe[0:23];
+
+   reg 		   stb_pipe0, stb_pipe1, stb_pipe2, stb_pipe3, stb_pipe4 ;
+   reg 		   stb_pipe5, stb_pipe6, stb_pipe7, stb_pipe8, stb_pipe9 ;
+   wire [WIDTH-1:0] sample_a[0:5], sample_b[0:5];
+   wire [17:0] coeff[0:5];
+   wire [47:0] 	    accumulator_out[0:5];
+   reg 	[47:0]	    partial_result_a, partial_result_b;
+   reg [47:0] 	    result;
+
+
+   // Implicit coeff23 of 131071
+   wire [17:0] 	   coeff_a[0:5];
+   wire [17:0] 	   coeff_b[0:5];
+
+   assign 	   coeff_a[0] = -62;
+   assign 	   coeff_b[0] = 194;
+   assign 	   coeff_a[1] = -440;
+   assign 	   coeff_b[1] = 855;
+   assign 	   coeff_a[2] = -1505;
+   assign 	   coeff_b[2] = 2478;
+   assign 	   coeff_a[3] = -3900;
+   assign 	   coeff_b[3] = 5990;
+   assign 	   coeff_a[4] = -9187;
+   assign 	   coeff_b[4] = 14632;
+   assign 	   coeff_a[5] = -26536;
+   assign 	   coeff_b[5] = 83009;
+
+   genvar 	   i;
+
+   always @(posedge clk)
+     if (rst)
+       data_in_pipe[0] <= 18'h0;
+     else if (stb_in)
+       data_in_pipe[0] <= data_in;
+
+   generate
+      for (i=0; i<23; i=i+1) begin: sample_pipeline
+   	 always @(posedge clk) if (rst)
+	   data_in_pipe[i+1] <= 0;
+	 else if (stb_in)
+	   data_in_pipe[i+1] <= data_in_pipe[i];
+      end
+   endgenerate
+
+   generate
+      for (i=0; i<6; i=i+1) begin: filter_core
+
+         assign sample_a[i] = stb_pipe0 ? data_in_pipe[(i*2)] : data_in_pipe[(2*i)+1];
+         assign sample_b[i] = stb_pipe0 ? data_in_pipe[23-(i*2)] : data_in_pipe[23-(2*i)-1];
+         // Coeffs are 1 pipeline downstream of sample input
+         assign coeff[i] = stb_pipe1 ? coeff_a[i] : coeff_b[i];
+
+	 add_then_mac
+	   #(.DEVICE(DEVICE))
+	     add_then_mac_i
+	       (
+		.acc(accumulator_out[i]),
+		.carryin(1'b0),
+		.ce(1'b1),
+		.clk(clk),
+		.b(coeff[i]),
+		.load(stb_pipe2),
+		.c(48'h0),
+		.a(sample_a[i]),
+		.d(sample_b[i]),
+		.rst(rst)
+		);
+
+     end // block: filter_core
+   endgenerate
+
+   //
+   // Dual 3:1 compressors
+   //
+   always @(posedge clk) if (stb_pipe5) begin
+      partial_result_a[47:0] <= accumulator_out[0] + accumulator_out[1] + accumulator_out[2];
+      partial_result_b[47:0] <= accumulator_out[3] + accumulator_out[4] + accumulator_out[5];
+   end
+
+   //
+   // Final Result Adder
+   //
+   always @(posedge clk) if (stb_pipe6) begin
+      result[47:0] <= partial_result_a[47:0] + partial_result_b[47:0];
+   end
+
+   //
+   // Now round unneed precision from accumulator result, and clip the unused dynamic range
+   //
+   wire [47:17] 	 result_rnd;
+   round_reg #(.bits_in(48),.bits_out(31))
+     final_round (.clk(clk),.in(result[47:0]),.out(result_rnd[47:17]),.err());
+
+   wire [34:17] 	 result_clip;
+   clip_reg #(.bits_in(31),.bits_out(18)) final_clip
+     (.clk(clk),.in(result_rnd[47:17]),.strobe_in(1'b1), .out(result_clip[34:17]), .strobe_out());
+
+   //
+   // Data enters the sample pipeline when stb_in is asserted.
+   // The clock cycle after is phase=0 with pipeline delay=0
+   //
+   always @(posedge clk)
+     if (rst) begin
+	stb_pipe0 <= 1'b0;   // New sample loaded into sample pipeline, setup on reg a
+	stb_pipe1 <= 1'b0;   // Sample n+0 presented to pre-adder, result to reg ad, coeff_a setup on input reg b
+	stb_pipe2 <= 1'b0;   // Sample n+1 presented to pre-adder, product of sample n+0 and coeff_a setup on reg m
+   	stb_pipe3 <= 1'b0;   // product of sample n+1 and coeff_b setup on reg m, previous product loaded into accumulator.
+	stb_pipe4 <= 1'b0;   // Add both products into accumulator
+   	stb_pipe5 <= 1'b0;   // Add 3 accumulator values into one partial result
+	stb_pipe6 <= 1'b0;   // Add both partial results into final full precision result.
+	stb_pipe7 <= 1'b0;   // Round result
+	stb_pipe8 <= 1'b0;   // Clip Result
+	stb_pipe9 <= 1'b0;
+
+     end else begin
+	stb_pipe0 <= stb_in;      // New sample loaded into sample pipeline, setup on reg a
+	stb_pipe1 <= stb_pipe0;   // Sample n+0 presented to pre-adder, result to reg ad, coeff_a setup on input reg b
+	stb_pipe2 <= stb_pipe1;   // Sample n+1 presented to pre-adder, product of sample n+0 and coeff_a setup on reg m
+   	stb_pipe3 <= stb_pipe2;   // product of sample n+1 and coeff_b setup on reg m, previous product loaded into accumulator.
+	stb_pipe4 <= stb_pipe3;   // Add both products into accumulator
+   	stb_pipe5 <= stb_pipe4;   // Add 3 accumulator values into one partial result
+	stb_pipe6 <= stb_pipe5;   // Add both partial results into final result.
+	stb_pipe7 <= stb_pipe6;   // Round result
+	stb_pipe8 <= stb_pipe7;   // Clip Result
+	stb_pipe9 <= stb_pipe8;
+
+     end // else: !if(rst)
+
+   //
+   // Interleave newly interpolated samples (odd taps) with raw input samples (even taps - All zero except center tap)
+   // Account for differences caused by various CPO settings and the pipeline advancing.
+   //
+   always @(posedge clk)
+     if (bypass)
+       data_out <= data_in;
+     else if (stb_in & stb_out)
+        data_out <= result_clip[34:17];
+      else if(stb_out)
+       case(output_rate)
+	 1: data_out <= data_in_pipe[16]; // Four input pipeline shifts since we calculated odd taps
+	 2: data_out <= data_in_pipe[14]; // Three input pipeline shifts since we calculated odd taps
+	 3,4: data_out <= data_in_pipe[13]; // Two input pipeline shifts since we calculated odd taps
+	 default: data_out <= data_in_pipe[12]; // One input pipeline shift since we calculated odd taps
+       endcase // case(output_rate)
+
+endmodule // hb47_int
diff --git a/fpga/usrp3/lib/dsp/hb47_int_tb.v b/fpga/usrp3/lib/dsp/hb47_int_tb.v
new file mode 100644
index 000000000..501fa682f
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/hb47_int_tb.v
@@ -0,0 +1,136 @@
+//
+// Copyright 2015 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+`timescale 1ns/1ps
+
+module hb47_int_tb();
+
+   wire GSR, GTS;
+   glbl glbl( );
+
+   reg 	clk = 0;
+   reg 	rst;
+   reg 	bypass;
+   reg 	run;
+
+   wire stb_in;
+   reg 	stb_out;
+   reg [7:0] cpo;
+
+   reg [17:0] data_in;
+
+   wire [17:0] data_out_dsp48a; 
+   wire [17:0] data_out_dsp48e;
+   
+   reg [15:0]  freq = 500;
+
+   integer     x = 0, y =0;
+
+
+
+   always #100 clk = ~clk;
+
+   // SPARTAN6 / DSP48A
+    hb47_int
+      #(.WIDTH(18),
+	.DEVICE("SPARTAN6"))
+	hb47_int_i0
+	(
+	 .clk(clk),
+	 .rst(rst),
+	 .bypass(bypass),
+	 .stb_in(stb_in),
+	 .data_in(data_in),
+	 .output_rate(cpo),
+	 .stb_out(stb_out),
+	 .data_out(data_out_dsp48a)
+	 );
+
+   // SERIES7 / DSP48E
+    hb47_int
+      #(.WIDTH(18),
+	.DEVICE("7SERIES"))
+	hb47_int_i1
+	(
+	 .clk(clk),
+	 .rst(rst),
+	 .bypass(bypass),
+	 .stb_in(stb_in),
+	 .data_in(data_in),
+	 .output_rate(cpo),
+	 .stb_out(stb_out),
+	 .data_out(data_out_dsp48e)
+	 );
+
+   always @(negedge clk)
+     if (data_out_dsp48a !== data_out_dsp48e)
+       $display("Output missmatch at %t",$time);
+   
+
+   
+  cic_strober #(.WIDTH(2))
+     hb1_strober(.clock(clk),.reset(rst),.enable(run),.rate(2'd2),
+		 .strobe_fast(stb_out),.strobe_slow(stb_in) );
+
+   initial
+     begin
+	rst <= 1;
+	bypass <= 0;
+	run <= 0;
+	data_in <= 0;
+	stb_out <= 1;
+	cpo <= 1;
+
+	repeat(10) @(posedge clk);
+	rst <= 0;
+	run <= 1;
+
+	for (x=0; x<100000; x=x+1) begin
+	   for (y=0; y<10000; y=y+1)
+	     begin
+		while (stb_in == 1'b0) @(posedge clk);
+		triangle_wave(freq,data_in);
+		@(posedge clk);
+
+	     end
+	   freq = freq * 2;
+	end
+
+	$finish;
+     end // initial begin
+
+
+
+
+   reg signed [18:0] phase_acc = 0;
+   reg 	      direction = 0;
+
+
+   task triangle_wave;
+      input [15:0] inc;
+      output [17:0] data_out;
+
+      begin
+	 if (direction) begin
+	    phase_acc = phase_acc - inc;
+	    if (phase_acc < -19'sh20000) begin
+	       direction = 0;
+	       phase_acc = phase_acc + inc;
+	    end
+	 end else begin
+	    phase_acc = phase_acc + inc;
+	    if (phase_acc > 19'sh1ffff) begin
+	       direction = 1;
+	       phase_acc = phase_acc - inc;
+	    end
+	 end
+	 data_out = phase_acc[17:0];
+      end
+
+   endtask // triangle_wave
+
+
+
+endmodule // hb47_int_tb
diff --git a/fpga/usrp3/lib/dsp/hb_dec.v b/fpga/usrp3/lib/dsp/hb_dec.v
new file mode 100644
index 000000000..0cae5c460
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/hb_dec.v
@@ -0,0 +1,202 @@
+//
+// Copyright 2011 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// NOTE: This module uses Xilinx IP that is not available in Spartan3 and older FPGA's
+
+// Final halfband decimator
+// Implements impulse responses of the form [A 0 B 0 C .. 0 H 0.5 H 0 .. C 0 B 0 A]
+// Strobe in cannot come faster than every 2nd clock cycle
+// These taps designed by halfgen4 from ldoolittle
+// myfilt = round(2^18 * halfgen4(.7/4,8))
+
+module hb_dec
+  #(parameter WIDTH=24,
+    parameter DEVICE = "SPARTAN6")
+    (input clk,
+     input rst,
+     input bypass,
+     input run,
+     input [8:0] cpi,  // Clocks per input -- equal to the decimation ratio ahead of this block
+     input stb_in,
+     input [WIDTH-1:0] data_in,
+     output reg stb_out,
+     output reg [WIDTH-1:0] data_out);
+
+   localparam INTWIDTH = 17;
+   localparam ACCWIDTH = WIDTH + 3;
+
+   // Round off inputs to 17 bits because of 18 bit multipliers
+   wire [INTWIDTH-1:0] 	     data_rnd;
+   wire 		     stb_rnd;
+
+   round_sd #(.WIDTH_IN(WIDTH),.WIDTH_OUT(INTWIDTH)) round_in
+     (.clk(clk),.reset(rst),.in(data_in),.strobe_in(stb_in),.out(data_rnd),.strobe_out(stb_rnd));
+
+   // Control
+   reg [3:0] 		addr_odd_a, addr_odd_b, addr_odd_c, addr_odd_d;
+   wire 		write_odd, write_even, do_mult;
+   reg 			odd;
+   reg [2:0] 		phase, phase_d1;
+   reg 			stb_out_int;
+   wire 		clear, do_acc;
+   assign 		do_mult = 1;
+
+   always @(posedge clk)
+     if(rst | ~run)
+       odd <= 0;
+     else if(stb_rnd)
+       odd <= ~odd;
+
+   assign 		write_odd = stb_rnd & odd;
+   assign 		write_even = stb_rnd & ~odd;
+
+   always @(posedge clk)
+     if(rst | ~run)
+       phase <= 0;
+     else if(stb_rnd & odd)
+       phase <= 1;
+     else if(phase == 4)
+       phase <= 0;
+     else if(phase != 0)
+       phase <= phase + 1;
+
+   always @(posedge clk)
+     phase_d1 <= phase;
+
+   reg [15:0] 		stb_out_pre;
+   always @(posedge clk)
+     if(rst)
+       stb_out_pre <= 0;
+     else
+       stb_out_pre <= {stb_out_pre[14:0],(stb_rnd & odd)};
+
+   always @*
+     case(phase)
+       1 : begin addr_odd_a = 0; addr_odd_b = 15; end
+       2 : begin addr_odd_a = 1; addr_odd_b = 14; end
+       3 : begin addr_odd_a = 2; addr_odd_b = 13; end
+       4 : begin addr_odd_a = 3; addr_odd_b = 12; end
+       default : begin addr_odd_a = 0; addr_odd_b = 15; end
+     endcase // case(phase)
+
+   always @*
+     case(phase)
+       1 : begin addr_odd_c = 4; addr_odd_d = 11; end
+       2 : begin addr_odd_c = 5; addr_odd_d = 10; end
+       3 : begin addr_odd_c = 6; addr_odd_d = 9; end
+       4 : begin addr_odd_c = 7; addr_odd_d = 8; end
+       default : begin addr_odd_c = 4; addr_odd_d = 11; end
+     endcase // case(phase)
+
+   assign do_acc = |stb_out_pre[6:3];
+   assign clear = stb_out_pre[3];
+
+   // Data
+   wire [INTWIDTH-1:0] data_odd_a, data_odd_b, data_odd_c, data_odd_d;
+   reg [INTWIDTH:0]    sum1, sum2;    // these are 18-bit inputs to mult
+   reg [WIDTH:0]       final_sum;
+   wire [WIDTH-1:0]    final_sum_clip;
+   reg [17:0] 	       coeff1, coeff2;
+   wire [35:0] 	       prod1, prod2;
+
+   always @*            // Outer coeffs
+     case(phase_d1)
+       1 : coeff1 = -107;
+       2 : coeff1 = 445;
+       3 : coeff1 = -1271;
+       4 : coeff1 = 2959;
+       default : coeff1 = -107;
+     endcase // case(phase)
+
+   always @*            //  Inner coeffs
+     case(phase_d1)
+       1 : coeff2 = -6107;
+       2 : coeff2 = 11953;
+       3 : coeff2 = -24706;
+       4 : coeff2 = 82359;
+       default : coeff2 = -6107;
+     endcase // case(phase)
+
+   srl #(.WIDTH(INTWIDTH)) srl_odd_a
+     (.clk(clk),.rst(rst),.write(write_odd),.in(data_rnd),.addr(addr_odd_a),.out(data_odd_a));
+   srl #(.WIDTH(INTWIDTH)) srl_odd_b
+     (.clk(clk),.rst(rst),.write(write_odd),.in(data_rnd),.addr(addr_odd_b),.out(data_odd_b));
+   srl #(.WIDTH(INTWIDTH)) srl_odd_c
+     (.clk(clk),.rst(rst),.write(write_odd),.in(data_rnd),.addr(addr_odd_c),.out(data_odd_c));
+   srl #(.WIDTH(INTWIDTH)) srl_odd_d
+     (.clk(clk),.rst(rst),.write(write_odd),.in(data_rnd),.addr(addr_odd_d),.out(data_odd_d));
+
+   always @(posedge clk) sum1 <= {data_odd_a[INTWIDTH-1],data_odd_a} + {data_odd_b[INTWIDTH-1],data_odd_b};
+   always @(posedge clk) sum2 <= {data_odd_c[INTWIDTH-1],data_odd_c} + {data_odd_d[INTWIDTH-1],data_odd_d};
+
+   wire [INTWIDTH-1:0] data_even;
+   reg [3:0] 	     addr_even;
+
+   always @(posedge clk)
+     case(cpi)
+       //  1 is an error
+       2 : addr_even <= 9;  // Maximum speed (overall decim by 4)
+       3, 4, 5, 6, 7 : addr_even <= 8;
+       default : addr_even <= 7;
+     endcase // case(cpi)
+
+   srl #(.WIDTH(INTWIDTH)) srl_even
+     (.clk(clk),.rst(rst),.write(write_even),.in(data_rnd),.addr(addr_even),.out(data_even));
+
+
+    MULT_MACRO #(.DEVICE(DEVICE),  // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6","7SERIES"
+		.LATENCY(1),         // Desired clock cycle latency, 0-4
+		.WIDTH_A(18),        // Multiplier A-input bus width, 1-25
+		.WIDTH_B(18))        // Multiplier B-input bus width, 1-18
+      mult1 (.P(prod1),     // Multiplier output bus, width determined by WIDTH_P parameter
+	       .A(coeff1),     // Multiplier input A bus, width determined by WIDTH_A parameter
+	       .B(sum1),                    // Multiplier input B bus, width determined by WIDTH_B parameter
+	       .CE(do_mult),   // 1-bit active high input clock enable
+	       .CLK(clk),              // 1-bit positive edge clock input
+	       .RST(rst));             // 1-bit input active high reset
+
+    MULT_MACRO #(.DEVICE(DEVICE),  // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6","7SERIES"
+		.LATENCY(1),         // Desired clock cycle latency, 0-4
+		.WIDTH_A(18),        // Multiplier A-input bus width, 1-25
+		.WIDTH_B(18))        // Multiplier B-input bus width, 1-18
+      mult2 (.P(prod2),     // Multiplier output bus, width determined by WIDTH_P parameter
+	       .A(coeff2),     // Multiplier input A bus, width determined by WIDTH_A parameter
+	       .B(sum2),                    // Multiplier input B bus, width determined by WIDTH_B parameter
+	       .CE(do_mult),   // 1-bit active high input clock enable
+	       .CLK(clk),              // 1-bit positive edge clock input
+	       .RST(rst));             // 1-bit input active high reset
+
+
+   reg [35:0] 	     sum_of_prod;
+   always @(posedge clk) sum_of_prod <= prod1 + prod2;   // Can't overflow
+
+   wire [ACCWIDTH-1:0] 	acc_out;
+   acc #(.IWIDTH(ACCWIDTH-2),.OWIDTH(ACCWIDTH))
+     acc (.clk(clk),.clear(clear),.acc(do_acc),.in(sum_of_prod[35:38-ACCWIDTH]),.out(acc_out));
+
+   wire [ACCWIDTH-1:0] 	data_even_signext;
+
+   localparam SHIFT_FACTOR = 6;
+
+   sign_extend #(.bits_in(INTWIDTH),.bits_out(ACCWIDTH-SHIFT_FACTOR)) signext_data_even
+     (.in(data_even),.out(data_even_signext[ACCWIDTH-1:SHIFT_FACTOR]));
+   assign 		data_even_signext[SHIFT_FACTOR-1:0] = 0;
+
+   always @(posedge clk) final_sum <= acc_out + data_even_signext;
+
+   clip #(.bits_in(WIDTH+1), .bits_out(WIDTH)) clip (.in(final_sum), .out(final_sum_clip));
+
+   // Output MUX to allow for bypass
+   wire 		selected_stb = bypass ? stb_in : stb_out_pre[8];
+
+   always @(posedge clk)
+     begin
+	stb_out  <= selected_stb;
+	if(selected_stb)
+	  data_out <= bypass ? data_in : final_sum_clip;
+     end
+
+endmodule // hb_dec
diff --git a/fpga/usrp3/lib/dsp/hb_interp.v b/fpga/usrp3/lib/dsp/hb_interp.v
new file mode 100644
index 000000000..6d8ef5174
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/hb_interp.v
@@ -0,0 +1,168 @@
+//
+// Copyright 2011 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+// First halfband iterpolator 
+// Implements impulse responses of the form [A 0 B 0 C .. 0 H 0.5 H 0 .. C 0 B 0 A]
+// Strobe in cannot come faster than every 4th clock cycle, 
+// Strobe out cannot come faster than every 2nd clock cycle
+
+// These taps designed by halfgen4 from ldoolittle
+// myfilt = round(2^18 * halfgen4(.7/4,8))
+
+module hb_interp
+  #(parameter IWIDTH=18, OWIDTH=18, ACCWIDTH=24)
+    (input clk,
+     input rst,
+     input bypass,
+     input [7:0] cpo, //  Clocks per output, must be at least 2
+     input stb_in,
+     input [IWIDTH-1:0] data_in,
+     input stb_out,
+     output reg [OWIDTH-1:0] data_out);
+
+   localparam MWIDTH = ACCWIDTH-2;
+   localparam CWIDTH = 18;
+
+   reg [CWIDTH-1:0] coeff1, coeff2;
+   reg [3:0] 	    addr_a, addr_b, addr_c, addr_d, addr_e;
+   wire [IWIDTH-1:0] data_a, data_b, data_c, data_d, data_e, sum1, sum2;
+   wire [35:0] 	     prod1, prod2;
+
+   reg [2:0] 	     phase, phase_d1, phase_d2, phase_d3, phase_d4, phase_d5;
+
+   always @(posedge clk)
+     if(rst)
+       phase <= 0;
+     else
+       if(stb_in)
+	 phase <= 1;
+       else if(phase==4)
+	 phase <= 0;
+       else if(phase!=0)
+	 phase <= phase + 1;
+   always @(posedge clk) phase_d1 <= phase;
+   always @(posedge clk) phase_d2 <= phase_d1;
+   always @(posedge clk) phase_d3 <= phase_d2;
+   always @(posedge clk) phase_d4 <= phase_d3;
+   always @(posedge clk) phase_d5 <= phase_d4;     
+   
+   srl #(.WIDTH(IWIDTH)) srl_a
+     (.clk(clk),.rst(rst),.write(stb_in),.in(data_in),.addr(addr_a),.out(data_a));
+   srl #(.WIDTH(IWIDTH)) srl_b
+     (.clk(clk),.rst(rst),.write(stb_in),.in(data_in),.addr(addr_b),.out(data_b));
+   srl #(.WIDTH(IWIDTH)) srl_c
+     (.clk(clk),.rst(rst),.write(stb_in),.in(data_in),.addr(addr_c),.out(data_c));
+   srl #(.WIDTH(IWIDTH)) srl_d
+     (.clk(clk),.rst(rst),.write(stb_in),.in(data_in),.addr(addr_d),.out(data_d));
+   srl #(.WIDTH(IWIDTH)) srl_e
+     (.clk(clk),.rst(rst),.write(stb_in),.in(data_in),.addr(addr_e),.out(data_e));
+
+   always @*
+     case(phase)
+       1 : begin addr_a = 0; addr_b = 15; end
+       2 : begin addr_a = 1; addr_b = 14; end
+       3 : begin addr_a = 2; addr_b = 13; end
+       4 : begin addr_a = 3; addr_b = 12; end
+       default : begin addr_a = 0; addr_b = 15; end
+     endcase // case(phase)
+
+   always @*
+     case(phase)
+       1 : begin addr_c = 4; addr_d = 11; end
+       2 : begin addr_c = 5; addr_d = 10; end
+       3 : begin addr_c = 6; addr_d = 9; end
+       4 : begin addr_c = 7; addr_d = 8; end
+       default : begin addr_c = 4; addr_d = 11; end
+     endcase // case(phase)
+
+   always @*
+     case(cpo)
+       2 : addr_e <= 9;
+       3,4,5,6,7,8 : addr_e <= 8;
+       default : addr_e <= 7;  // This case works for 256, which = 0 due to overflow outside this block
+     endcase // case(cpo)
+   
+   always @*            // Outer coeffs
+     case(phase_d1)
+       1 : coeff1 = -107;
+       2 : coeff1 = 445;
+       3 : coeff1 = -1271;
+       4 : coeff1 = 2959;
+       default : coeff1 = -107;
+     endcase // case(phase)
+   
+   always @*            //  Inner coeffs
+     case(phase_d1)
+       1 : coeff2 = -6107;
+       2 : coeff2 = 11953;
+       3 : coeff2 = -24706;
+       4 : coeff2 = 82359;
+       default : coeff2 = -6107;
+     endcase // case(phase)
+
+   add2_reg /*_and_round_reg*/ #(.WIDTH(IWIDTH)) add1 (.clk(clk),.in1(data_a),.in2(data_b),.sum(sum1));
+   add2_reg /*_and_round_reg*/ #(.WIDTH(IWIDTH)) add2 (.clk(clk),.in1(data_c),.in2(data_d),.sum(sum2));
+   // sum1, sum2 available on phase_d1
+
+   wire do_mult = 1;
+   MULT18X18S mult1(.C(clk), .CE(do_mult), .R(rst), .P(prod1), .A(coeff1), .B(sum1) );
+   MULT18X18S mult2(.C(clk), .CE(do_mult), .R(rst), .P(prod2), .A(coeff2), .B(sum2) );
+   // prod1, prod2 available on phase_d2
+   
+   wire [MWIDTH-1:0] sum_of_prod;
+   
+   add2_and_round_reg #(.WIDTH(MWIDTH)) 
+     add3 (.clk(clk),.in1(prod1[35:36-MWIDTH]),.in2(prod2[35:36-MWIDTH]),.sum(sum_of_prod));
+   // sum_of_prod available on phase_d3
+   
+   wire [ACCWIDTH-1:0] acc_out;
+ 
+   wire 	       clear = (phase_d3 == 1);
+   wire 	       do_acc = (phase_d3 != 0);
+   
+   acc #(.IWIDTH(MWIDTH),.OWIDTH(ACCWIDTH)) //IJB rst
+     acc (.clk(clk),.clear(rst|clear),.acc(do_acc),.in(sum_of_prod),.out(acc_out));   
+   // acc_out available on phase_d4
+   
+   wire [ACCWIDTH-6:0] clipped_acc;
+   clip #(.bits_in(ACCWIDTH),.bits_out(ACCWIDTH-5)) final_clip(.in(acc_out),.out(clipped_acc));
+   
+   reg [ACCWIDTH-6:0]   clipped_reg;
+   always @(posedge clk)
+     if (rst)
+       clipped_reg <= 0;
+     else  if(phase_d4 == 4)
+       clipped_reg <= clipped_acc;
+   // clipped_reg available on phase_d5
+   
+   wire [OWIDTH-1:0]   data_out_round;
+   round #(.bits_in(ACCWIDTH-5),.bits_out(OWIDTH)) final_round (.in(clipped_reg),.out(data_out_round));
+
+   reg 		      odd;
+   always @(posedge clk)
+     if(rst)
+       odd <= 0;
+     else if(stb_in)
+       odd <= 0;
+     else if(stb_out)
+       odd <= 1;
+
+   always @(posedge clk)
+     if (rst)
+       data_out <= 0;
+     else if(bypass)
+       data_out <= data_in;
+     else if(stb_out)
+       if(odd)
+	 data_out <= data_e;
+       else
+	 data_out <= data_out_round;
+
+   // data_out available on phase_d6
+   
+endmodule // hb_interp
diff --git a/fpga/usrp3/lib/dsp/mult_add_clip.v b/fpga/usrp3/lib/dsp/mult_add_clip.v
new file mode 100644
index 000000000..b1b49af8b
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/mult_add_clip.v
@@ -0,0 +1,260 @@
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// Write xilinx DSP48E1 primitive for mult-add-clip (signed)
+
+`default_nettype none
+
+module mult_add_clip #(
+  parameter WIDTH_A=25,  // Max 25
+  parameter BIN_PT_A=24,
+  parameter WIDTH_B=18,  // Max 18
+  parameter BIN_PT_B=17,
+  parameter WIDTH_C=43,  // Max 43
+
+  // Min (47-WIDTH_C-1)+BIN_PT_A+BIN_PT_B,
+  // Max WIDTH_C-1+BIN_PT_A+BIN_PT_B
+  parameter BIN_PT_C=42,
+
+  parameter WIDTH_O=43,  // Max 43-(BIN_PT_A+BIN_PT_B-BIN_PT_O)
+  parameter BIN_PT_O=42,
+  parameter LATENCY=2    // Maximum is 4
+) (
+  input wire clk,
+  input wire reset,
+  input wire CE, // Ordinarily set to 1'b1
+  input wire [WIDTH_A-1:0] A,
+  input wire [WIDTH_B-1:0] B,
+  input wire [WIDTH_C-1:0] C,
+  output reg  [WIDTH_O-1:0] O
+);
+  // DSP operations:
+  // O = clip(A * B + C)
+  // 
+  // Mux settings:
+  // X,Y (01,01) = M
+  // Z (011) = C
+ 
+  localparam MREG_IN = (LATENCY >= 1) ? 1 : 0;
+  localparam CREG_IN = MREG_IN;
+  localparam PREG_IN = (LATENCY >= 2) ? 1 : 0;
+  localparam A2REG_IN = (LATENCY >= 3) ? 1 : 0;
+  localparam A1REG_IN = (LATENCY == 4) ? 1 : 0;
+  localparam AREG_IN = A1REG_IN + A2REG_IN;
+  // See OPMODE Control Bits Settings, Table 2-7,2-8,2-9
+  localparam ZMUX_C = 3'b011;
+  localparam YMUX_M = 2'b01;
+  localparam XMUX_M = 2'b01;
+  localparam [6:0] OPMODE = {ZMUX_C, YMUX_M, XMUX_M};
+
+  // A_IN is 25 bits; B_IN is 18 bits. Product M's binary point shifts:
+  localparam BIN_PT_M = BIN_PT_A+(25-WIDTH_A) + BIN_PT_B+(18-WIDTH_B);
+
+  // Calculate shift for C to align binary point to A*B product (M)
+  // Determine top and bottom indices of C (in C_IN), normalized to M
+  // Divide by 2**BIN_PT_C then multiply up by 2**BIN_PT_M
+  localparam C_TOP = WIDTH_C-1 - BIN_PT_C + BIN_PT_M;
+  localparam C_BOT = 0 - BIN_PT_C + BIN_PT_M;
+  // Determine number of sign-extended bits above C_TOP
+  localparam C_EXT = 47 - C_TOP;
+
+  // P is a 43-bit fixed point number with bin pt BIN_PT_M
+  // O is extracted from those bits
+  // Sign extend if more bits to left of bin pt
+  localparam O_EXT = ((WIDTH_O-BIN_PT_O) > (43-BIN_PT_M)) ?
+                      (WIDTH_O-BIN_PT_O) - (43-BIN_PT_M) : 0;
+  // If extending, use highest bit of P, else extract bits based on bin pt
+  localparam P_TOP = (O_EXT > 0) ? 42 :
+                     (42 + (WIDTH_O-BIN_PT_O) - (43-BIN_PT_M));
+  // Pad bottom of O if remaining P not enough bits
+  localparam O_PAD = (WIDTH_O > P_TOP+1) ? (WIDTH_O-P_TOP-1) : 0;
+  // If padding O, grab lowest bit of P, else determine based on O's width
+  localparam P_BOT = (O_PAD > 0) ? 0 : (P_TOP+1-WIDTH_O);
+
+  //------------------------------------------------
+  // Normalize C input to A*B product's binary point
+  //------------------------------------------------
+  function automatic [47:0] align_c;
+    input [WIDTH_C-1:0] c;
+    begin
+      // Do sign extension
+      if (C_EXT > 0) begin
+        align_c[47 -: C_EXT] = {C_EXT{c[WIDTH_C-1]}};
+      end
+      if (C_BOT < 0) begin
+        // Chop off lower bits of C
+        align_c[C_TOP:0] = c[WIDTH_C-1:(-C_BOT)];
+      end else begin
+        // Place C and zero pad if necessary
+        align_c[C_TOP:C_BOT] = c;
+        if (C_BOT > 0) begin
+          align_c[C_BOT-1:0] = {C_BOT{1'b0}};
+        end
+      end
+    end
+  endfunction
+
+  wire [24:0] A_IN = (WIDTH_A < 25) ? { A, {(25-(WIDTH_A)){1'b0}}} : A;
+  wire [17:0] B_IN = (WIDTH_B < 18) ? { B, {(18-(WIDTH_B)){1'b0}}} : B;
+  wire [47:0] C_IN;
+  wire [47:0] P_OUT;
+
+  //--------------------------------------------------
+  // C needs more pipeline registers at higher latency
+  //--------------------------------------------------
+  generate if (AREG_IN > 0) begin
+    reg [AREG_IN*WIDTH_C-1:0] c_r;
+
+    if (AREG_IN > 1) begin
+      always @ (posedge clk)
+      begin
+        if (CE) begin
+          c_r <= {c_r[0 +: (AREG_IN-1)*WIDTH_C], C};
+        end
+      end
+    end else begin
+      always @ (posedge clk)
+      begin
+        if (CE) begin
+          c_r <= C;
+        end
+      end
+    end
+
+    wire [WIDTH_C-1:0] c_pre = c_r[AREG_IN*WIDTH_C-1 -: WIDTH_C];
+    assign C_IN = align_c(c_pre);
+  end else begin
+    assign C_IN = align_c(C);
+  end endgenerate
+
+  //----------------------------------------------
+  // Track signs for overflow/underflow processing
+  //----------------------------------------------
+  reg  [LATENCY-1:0]     mult_sign;
+  reg  [LATENCY-1:0]     c_sign;
+  wire                   bin_pt_overflow;
+  wire                   adder_overflow;
+  wire [WIDTH_O-1:0]     p_extract;
+
+  generate if (LATENCY > 1) begin
+    always @ (posedge clk)
+    begin
+      if (CE) begin
+        mult_sign <= {mult_sign[0 +: LATENCY-1], A[WIDTH_A-1] ^ B[WIDTH_B-1]};
+        c_sign <= {c_sign[0 +: LATENCY-1], C[WIDTH_C-1]};
+      end
+    end
+  end else begin
+    always @ (posedge clk)
+    begin
+      if (CE) begin
+        mult_sign <= A[WIDTH_A-1] ^ B[WIDTH_B-1];
+        c_sign <= C[WIDTH_C-1];
+      end
+    end
+  end endgenerate
+
+  assign adder_overflow = (mult_sign[LATENCY-1] == c_sign[LATENCY-1]) &&
+                          (P_OUT[42] != c_sign[LATENCY-1]);
+
+  //----------------------------------------------
+  // Extract renormalized bits from P_OUT
+  //----------------------------------------------
+  generate 
+    if (P_TOP < 42) begin
+      assign bin_pt_overflow = (|P_OUT[42:P_TOP]) != (&P_OUT[42:P_TOP]);
+    end else begin
+      assign bin_pt_overflow = 1'b0;
+    end
+
+    if (O_EXT > 0) begin
+      assign p_extract[WIDTH_O-1 -: O_EXT] = {O_EXT{P_OUT[42]}};
+    end
+
+    if (O_PAD > 0) begin
+      assign p_extract[O_PAD-1:0] = {O_PAD{1'b0}};
+    end
+  endgenerate
+
+  assign p_extract[WIDTH_O-1-O_EXT:O_PAD] = P_OUT[P_TOP:P_BOT];
+
+  //----------------------------------
+  // Clip if underflowed or overflowed
+  //----------------------------------
+  always @ (*)
+  begin
+    if (bin_pt_overflow || adder_overflow) begin
+      O <= {c_sign[LATENCY-1], {WIDTH_O-1{!c_sign[LATENCY-1]}}};
+    end else begin
+      O <= p_extract;
+    end
+  end
+
+  
+  DSP48E1 #(
+    .ACASCREG(AREG_IN),
+    .AREG(AREG_IN),
+    .ADREG(0),
+    .DREG(0),
+    .BCASCREG(AREG_IN),
+    .BREG(AREG_IN),
+    .MREG(MREG_IN),
+    .CREG(CREG_IN),
+    .PREG(PREG_IN)
+  ) DSP48_inst (
+    // Outputs
+    .ACOUT(),
+    .BCOUT(),
+    .CARRYCASCOUT(),
+    .CARRYOUT(),
+    .MULTSIGNOUT(),
+    .OVERFLOW(),
+    .P(P_OUT),
+    .PATTERNBDETECT(),
+    .PATTERNDETECT(),
+    .PCOUT(),
+    .UNDERFLOW(),
+
+    // Inputs
+    .A({5'b0,A_IN}),
+    .ACIN(30'b0),
+    .ALUMODE(4'b0000),
+    .B(B_IN),
+    .BCIN(18'b0),
+    .C(C_IN),
+    .CARRYCASCIN(1'b0),
+    .CARRYIN(1'b0),
+    .CARRYINSEL(3'b0),
+    .CEA1(CE),
+    .CEA2(CE),
+    .CEAD(1'b0),
+    .CEALUMODE(1'b1),
+    .CEB1(CE),
+    .CEB2(CE),
+    .CEC(CE),
+    .CECARRYIN(CE),
+    .CECTRL(CE),
+    .CED(1'b0),
+    .CEINMODE(CE),
+    .CEM(CE),
+    .CEP(CE),
+    .CLK(clk),
+    .D({25{1'b1}}),
+    .INMODE(5'b0),
+    .MULTSIGNIN(1'b0),
+    .OPMODE(OPMODE),
+    .PCIN(48'b0),
+    .RSTA(reset),
+    .RSTALLCARRYIN(reset),
+    .RSTALUMODE(reset),
+    .RSTB(reset),
+    .RSTC(reset),
+    .RSTD(reset),
+    .RSTCTRL(reset),
+    .RSTINMODE(reset),
+    .RSTM(reset),
+    .RSTP(reset)
+  );
+
+endmodule // mult_add_clip
+`default_nettype wire
diff --git a/fpga/usrp3/lib/dsp/round.v b/fpga/usrp3/lib/dsp/round.v
new file mode 100644
index 000000000..4d3cf5521
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/round.v
@@ -0,0 +1,49 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2011 Matt Ettus
+// 
+//  SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+//
+
+// Rounding "macro"
+// Keeps the topmost bits, does proper 2s comp round to zero (unbiased truncation)
+
+module round
+  #(parameter bits_in=0,
+    parameter bits_out=0,
+    parameter round_to_zero=0,       // original behavior
+    parameter round_to_nearest=1,    // lowest noise
+    parameter trunc=0)               // round to negative infinity
+    (input [bits_in-1:0] in,
+     output [bits_out-1:0] out,
+     output [bits_in-bits_out:0] err);
+
+   wire 			 round_corr,round_corr_trunc,round_corr_rtz,round_corr_nearest,round_corr_nearest_safe;
+
+   assign 			 round_corr_trunc = 0;
+   assign 			 round_corr_rtz = (in[bits_in-1] & |in[bits_in-bits_out-1:0]);
+   assign 			 round_corr_nearest = in[bits_in-bits_out-1];
+
+   generate
+      if(bits_in-bits_out > 1)
+	assign 			 round_corr_nearest_safe = (~in[bits_in-1] & (&in[bits_in-2:bits_in-bits_out])) ? 1'b0 :
+				 round_corr_nearest;
+      else
+	assign round_corr_nearest_safe = round_corr_nearest;
+   endgenerate
+
+
+   assign round_corr = round_to_nearest ? round_corr_nearest_safe :
+		       trunc ? round_corr_trunc :
+		       round_to_zero ? round_corr_rtz :
+		       0;  // default to trunc
+
+   assign out = in[bits_in-1:bits_in-bits_out] + round_corr;
+
+   assign err = in - {out,{(bits_in-bits_out){1'b0}}};
+
+endmodule // round
diff --git a/fpga/usrp3/lib/dsp/round_reg.v b/fpga/usrp3/lib/dsp/round_reg.v
new file mode 100644
index 000000000..d1bc6a848
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/round_reg.v
@@ -0,0 +1,34 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2008 Matt Ettus
+// 
+//  SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+//
+
+// Rounding "macro"
+// Keeps the topmost bits, does proper 2s comp rounding (round-to-zero)
+
+module round_reg
+  #(parameter bits_in=0,
+    parameter bits_out=0)
+    (input clk,
+     input [bits_in-1:0] in,
+     output reg [bits_out-1:0] out,
+     output reg [bits_in-bits_out:0] err);
+
+   wire [bits_out-1:0] temp;
+   wire [bits_in-bits_out:0] err_temp;
+   
+   round #(.bits_in(bits_in),.bits_out(bits_out)) round (.in(in),.out(temp), .err(err_temp));
+   
+   always @(posedge clk)
+     out <= temp;
+
+   always @(posedge clk)
+     err <= err_temp;
+   
+endmodule // round_reg
diff --git a/fpga/usrp3/lib/dsp/round_sd.v b/fpga/usrp3/lib/dsp/round_sd.v
new file mode 100644
index 000000000..37aef53f0
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/round_sd.v
@@ -0,0 +1,43 @@
+//
+// Copyright 2016 Ettus Research
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module round_sd #(
+  parameter WIDTH_IN=18,
+  parameter WIDTH_OUT=16,
+  parameter DISABLE_SD=0
+)(
+  input clk, input reset,
+  input [WIDTH_IN-1:0] in, input strobe_in,
+  output reg [WIDTH_OUT-1:0] out, output reg strobe_out
+);
+
+  localparam ERR_WIDTH = WIDTH_IN - WIDTH_OUT + 1;
+
+  wire [ERR_WIDTH-1:0] err;
+  wire [WIDTH_IN-1:0]  err_ext, sum;
+  wire [WIDTH_OUT-1:0] out_pre;
+  wire                 strobe_pre;
+
+  sign_extend #(.bits_in(ERR_WIDTH),.bits_out(WIDTH_IN)) ext_err (.in(err), .out(err_ext));
+
+  add2_and_clip_reg #(.WIDTH(WIDTH_IN)) add2_and_clip_reg (
+    .clk(clk), .rst(reset), .in1(in), .in2((DISABLE_SD == 0) ? err_ext : {WIDTH_IN{1'b0}}), .strobe_in(strobe_in), .sum(sum), .strobe_out(strobe_pre));
+
+  round #(.bits_in(WIDTH_IN),.bits_out(WIDTH_OUT)) round_sum (.in(sum), .out(out_pre), .err(err));
+
+  always @(posedge clk) begin
+    if (reset) begin
+      strobe_out <= 1'b0;
+    end else begin
+      strobe_out <= strobe_pre;
+      if (strobe_pre) begin
+        out <= out_pre;
+      end
+    end
+  end
+
+endmodule // round_sd
diff --git a/fpga/usrp3/lib/dsp/rx_dcoffset.v b/fpga/usrp3/lib/dsp/rx_dcoffset.v
new file mode 100644
index 000000000..02950fbd5
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/rx_dcoffset.v
@@ -0,0 +1,50 @@
+//
+// Copyright 2015 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module rx_dcoffset 
+  #(parameter WIDTH=16,
+    parameter ADDR=8'd0,
+    parameter alpha_shift=20)
+   (input clk, input rst,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    input in_stb, input [WIDTH-1:0] in,
+    output out_stb, output [WIDTH-1:0] out);
+
+   wire 	      set_now = set_stb & (ADDR == set_addr);
+   reg 		      fixed;  // uses fixed offset
+   wire [WIDTH-1:0]   fixed_dco;
+
+   localparam int_width = WIDTH + alpha_shift;
+   reg [int_width-1:0] integrator;
+   reg                 integ_in_stb;
+   wire [WIDTH-1:0]    quantized;
+
+   always @(posedge clk) begin
+     if(rst)
+       begin
+       integ_in_stb <= 0;
+	  fixed <= 0;
+	  integrator <= {int_width{1'b0}};
+       end
+     else if(set_now)
+       begin
+	  fixed <= set_data[31];
+	  if(set_data[30])
+	    integrator <= {set_data[29:0],{(int_width-30){1'b0}}};
+       end
+     else if(~fixed & in_stb)
+       integrator <= integrator +  {{(alpha_shift){out[WIDTH-1]}},out};
+     integ_in_stb <= in_stb;
+   end
+
+   round_sd #(.WIDTH_IN(int_width),.WIDTH_OUT(WIDTH)) round_sd
+     (.clk(clk), .reset(rst), .in(integrator), .strobe_in(integ_in_stb), .out(quantized), .strobe_out());
+
+   add2_and_clip_reg #(.WIDTH(WIDTH)) add2_and_clip_reg
+     (.clk(clk), .rst(rst), .in1(in), .in2(-quantized), .strobe_in(in_stb), .sum(out), .strobe_out(out_stb));
+
+endmodule // rx_dcoffset
diff --git a/fpga/usrp3/lib/dsp/rx_frontend.v b/fpga/usrp3/lib/dsp/rx_frontend.v
new file mode 100644
index 000000000..45c701688
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/rx_frontend.v
@@ -0,0 +1,87 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+module rx_frontend
+  #(parameter BASE = 0,
+    parameter IQCOMP_EN = 1)
+   (input clk, input rst,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+    input [15:0] adc_a, input adc_ovf_a,
+    input [15:0] adc_b, input adc_ovf_b,
+
+    output [23:0] i_out, output [23:0] q_out,
+    input run,
+    output [31:0] debug
+    );
+   
+   reg [15:0] 	  adc_i, adc_q;
+   wire [23:0] 	  adc_i_ofs, adc_q_ofs;
+   wire [35:0] 	  corr_i, corr_q; 
+   wire [17:0] 	  mag_corr,phase_corr;
+   wire 	  swap_iq;
+   
+   setting_reg #(.my_addr(BASE), .width(1)) sr_8
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(swap_iq),.changed());
+
+   always @(posedge clk)
+     if(swap_iq) // Swap
+       {adc_i,adc_q} <= {adc_b,adc_a};
+     else
+       {adc_i,adc_q} <= {adc_a,adc_b};
+       
+   setting_reg #(.my_addr(BASE+1),.width(18)) sr_1
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(mag_corr),.changed());
+   
+   setting_reg #(.my_addr(BASE+2),.width(18)) sr_2
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(phase_corr),.changed());
+
+   rx_dcoffset #(.WIDTH(24),.ADDR(BASE+3)) rx_dcoffset_i
+     (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .in({adc_i,8'b00}), .in_stb(1'b1),
+      .out(adc_i_ofs), .out_stb());
+   
+   rx_dcoffset #(.WIDTH(24),.ADDR(BASE+4)) rx_dcoffset_q
+     (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .in({adc_q,8'b00}), .in_stb(1'b1),
+      .out(adc_q_ofs), .out_stb());
+   
+   generate
+      if(IQCOMP_EN == 1)
+	begin
+	   reg [23:0] adc_i_ofs_dly, adc_q_ofs_dly;
+	   always @(posedge clk) begin
+	     adc_i_ofs_dly <= adc_i_ofs;
+	     adc_q_ofs_dly <= adc_q_ofs;
+	   end
+
+	   MULT18X18S mult_mag_corr
+	     (.P(corr_i), .A(adc_i_ofs[23:6]), .B(mag_corr), .C(clk), .CE(1'b1), .R(rst) ); 
+	   
+	   MULT18X18S mult_phase_corr
+	     (.P(corr_q), .A(adc_i_ofs[23:6]), .B(phase_corr), .C(clk), .CE(1'b1), .R(rst) );
+	   
+	   add2_and_clip_reg #(.WIDTH(24)) add_clip_i
+	     (.clk(clk), .rst(rst), 
+	      .in1(adc_i_ofs_dly), .in2(corr_i[35:12]), .strobe_in(1'b1),
+	      .sum(i_out), .strobe_out());
+	   
+	   add2_and_clip_reg #(.WIDTH(24)) add_clip_q
+	     (.clk(clk), .rst(rst), 
+	      .in1(adc_q_ofs_dly), .in2(corr_q[35:12]), .strobe_in(1'b1),
+	      .sum(q_out), .strobe_out());
+	end // if (IQCOMP_EN == 1)
+      else
+	begin
+	   assign i_out = adc_i_ofs;
+	   assign q_out = adc_q_ofs;
+	end // else: !if(IQCOMP_EN == 1)
+   endgenerate
+   
+endmodule // rx_frontend
diff --git a/fpga/usrp3/lib/dsp/rx_frontend_tb.v b/fpga/usrp3/lib/dsp/rx_frontend_tb.v
new file mode 100644
index 000000000..c7e88da11
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/rx_frontend_tb.v
@@ -0,0 +1,50 @@
+//
+// Copyright 2013 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+`timescale 1ns/1ns
+module rx_frontend_tb();
+   
+   reg clk, rst;
+
+   initial rst = 1;
+   initial #1000 rst = 0;
+   initial clk = 0;
+   always #5 clk = ~clk;
+   
+   initial $dumpfile("rx_frontend_tb.vcd");
+   initial $dumpvars(0,rx_frontend_tb);
+
+   reg [15:0] adc_in;
+   wire [23:0] adc_out;
+
+   always @(posedge clk)
+     begin
+	if(adc_in[15])
+	  $write("-%d,",-adc_in);
+	else
+	  $write("%d,",adc_in);
+	if(adc_out[23])
+	  $write("-%d\n",-adc_out);
+	else
+	  $write("%d\n",adc_out);
+     end	
+   
+   rx_frontend #(.BASE(0), .IQCOMP_EN(1)) rx_frontend
+     (.clk(clk),.rst(rst),
+      .set_stb(0),.set_addr(0),.set_data(0),
+      .adc_a(adc_in), .adc_ovf_a(0),
+      .adc_b(0), .adc_ovf_b(0),
+      .i_out(adc_out),.q_out(),
+      .run(), .debug());
+
+   always @(posedge clk)
+     if(rst)
+       adc_in <= 0;
+     else
+       adc_in <= adc_in + 4;
+   //adc_in <= (($random % 473) + 23)/4;
+   
+endmodule // rx_frontend_tb
diff --git a/fpga/usrp3/lib/dsp/sign_extend.v b/fpga/usrp3/lib/dsp/sign_extend.v
new file mode 100644
index 000000000..e1c24b717
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/sign_extend.v
@@ -0,0 +1,25 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003 Matt Ettus
+// 
+//  SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+//
+
+
+// Sign extension "macro"
+// bits_out should be greater than bits_in
+
+module sign_extend (in,out);
+	parameter bits_in=0;  // FIXME Quartus insists on a default
+	parameter bits_out=0;
+	
+	input [bits_in-1:0] in;
+	output [bits_out-1:0] out;
+	
+	assign out = {{(bits_out-bits_in){in[bits_in-1]}},in};
+	
+endmodule
diff --git a/fpga/usrp3/lib/dsp/sim/sim_ddc_chain/dc_in_cordic_decim_2/gtk.conf.gtkw b/fpga/usrp3/lib/dsp/sim/sim_ddc_chain/dc_in_cordic_decim_2/gtk.conf.gtkw
new file mode 100644
index 000000000..27c2c836e
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/sim/sim_ddc_chain/dc_in_cordic_decim_2/gtk.conf.gtkw
@@ -0,0 +1,64 @@
+[*]
+[*] GTKWave Analyzer v3.3.40 (w)1999-2012 BSI
+[*] Wed Jul 15 02:18:40 2015
+[*]
+[dumpfile] "/disk2/ianb/ettus/fpgadev-b200/fpgadev/usrp3/lib/dsp/sim/sim_ddc_chain/dc_in_cordic_run/waves.vcd"
+[dumpfile_mtime] "Wed Jul 15 02:13:19 2015"
+[dumpfile_size] 238141440
+[savefile] "/disk2/ianb/ettus/fpgadev-b200/fpgadev/usrp3/lib/dsp/sim/sim_ddc_chain/dc_in_cordic_run/gtk.conf.gtkw"
+[timestart] 0
+[size] 2488 1221
+[pos] -1 -1
+*-24.083374 129800000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] ddc_chain_tb.
+[treeopen] ddc_chain_tb.dut_i0.
+[sst_width] 331
+[signals_width] 280
+[sst_expanded] 1
+[sst_vpaned_height] 370
+@28
+ddc_chain_tb.dut_i0.clk
+ddc_chain_tb.dut_i0.rst
+ddc_chain_tb.dut_i0.set_stb
+@22
+#{ddc_chain_tb.dut_i0.set_addr[7:0]} ddc_chain_tb.dut_i0.set_addr[7] ddc_chain_tb.dut_i0.set_addr[6] ddc_chain_tb.dut_i0.set_addr[5] ddc_chain_tb.dut_i0.set_addr[4] ddc_chain_tb.dut_i0.set_addr[3] ddc_chain_tb.dut_i0.set_addr[2] ddc_chain_tb.dut_i0.set_addr[1] ddc_chain_tb.dut_i0.set_addr[0]
+#{ddc_chain_tb.dut_i0.set_data[31:0]} ddc_chain_tb.dut_i0.set_data[31] ddc_chain_tb.dut_i0.set_data[30] ddc_chain_tb.dut_i0.set_data[29] ddc_chain_tb.dut_i0.set_data[28] ddc_chain_tb.dut_i0.set_data[27] ddc_chain_tb.dut_i0.set_data[26] ddc_chain_tb.dut_i0.set_data[25] ddc_chain_tb.dut_i0.set_data[24] ddc_chain_tb.dut_i0.set_data[23] ddc_chain_tb.dut_i0.set_data[22] ddc_chain_tb.dut_i0.set_data[21] ddc_chain_tb.dut_i0.set_data[20] ddc_chain_tb.dut_i0.set_data[19] ddc_chain_tb.dut_i0.set_data[18] ddc_chain_tb.dut_i0.set_data[17] ddc_chain_tb.dut_i0.set_data[16] ddc_chain_tb.dut_i0.set_data[15] ddc_chain_tb.dut_i0.set_data[14] ddc_chain_tb.dut_i0.set_data[13] ddc_chain_tb.dut_i0.set_data[12] ddc_chain_tb.dut_i0.set_data[11] ddc_chain_tb.dut_i0.set_data[10] ddc_chain_tb.dut_i0.set_data[9] ddc_chain_tb.dut_i0.set_data[8] ddc_chain_tb.dut_i0.set_data[7] ddc_chain_tb.dut_i0.set_data[6] ddc_chain_tb.dut_i0.set_data[5] ddc_chain_tb.dut_i0.set_data[4] ddc_chain_tb.dut_i0.set_data[3] ddc_chain_tb.dut_i0.set_data[2] ddc_chain_tb.dut_i0.set_data[1] ddc_chain_tb.dut_i0.set_data[0]
+@10420
+#{ddc_chain_tb.dut_i0.rx_fe_i[23:0]} ddc_chain_tb.dut_i0.rx_fe_i[23] ddc_chain_tb.dut_i0.rx_fe_i[22] ddc_chain_tb.dut_i0.rx_fe_i[21] ddc_chain_tb.dut_i0.rx_fe_i[20] ddc_chain_tb.dut_i0.rx_fe_i[19] ddc_chain_tb.dut_i0.rx_fe_i[18] ddc_chain_tb.dut_i0.rx_fe_i[17] ddc_chain_tb.dut_i0.rx_fe_i[16] ddc_chain_tb.dut_i0.rx_fe_i[15] ddc_chain_tb.dut_i0.rx_fe_i[14] ddc_chain_tb.dut_i0.rx_fe_i[13] ddc_chain_tb.dut_i0.rx_fe_i[12] ddc_chain_tb.dut_i0.rx_fe_i[11] ddc_chain_tb.dut_i0.rx_fe_i[10] ddc_chain_tb.dut_i0.rx_fe_i[9] ddc_chain_tb.dut_i0.rx_fe_i[8] ddc_chain_tb.dut_i0.rx_fe_i[7] ddc_chain_tb.dut_i0.rx_fe_i[6] ddc_chain_tb.dut_i0.rx_fe_i[5] ddc_chain_tb.dut_i0.rx_fe_i[4] ddc_chain_tb.dut_i0.rx_fe_i[3] ddc_chain_tb.dut_i0.rx_fe_i[2] ddc_chain_tb.dut_i0.rx_fe_i[1] ddc_chain_tb.dut_i0.rx_fe_i[0]
+@20000
+-
+@10420
+#{ddc_chain_tb.dut_i0.rx_fe_q[23:0]} ddc_chain_tb.dut_i0.rx_fe_q[23] ddc_chain_tb.dut_i0.rx_fe_q[22] ddc_chain_tb.dut_i0.rx_fe_q[21] ddc_chain_tb.dut_i0.rx_fe_q[20] ddc_chain_tb.dut_i0.rx_fe_q[19] ddc_chain_tb.dut_i0.rx_fe_q[18] ddc_chain_tb.dut_i0.rx_fe_q[17] ddc_chain_tb.dut_i0.rx_fe_q[16] ddc_chain_tb.dut_i0.rx_fe_q[15] ddc_chain_tb.dut_i0.rx_fe_q[14] ddc_chain_tb.dut_i0.rx_fe_q[13] ddc_chain_tb.dut_i0.rx_fe_q[12] ddc_chain_tb.dut_i0.rx_fe_q[11] ddc_chain_tb.dut_i0.rx_fe_q[10] ddc_chain_tb.dut_i0.rx_fe_q[9] ddc_chain_tb.dut_i0.rx_fe_q[8] ddc_chain_tb.dut_i0.rx_fe_q[7] ddc_chain_tb.dut_i0.rx_fe_q[6] ddc_chain_tb.dut_i0.rx_fe_q[5] ddc_chain_tb.dut_i0.rx_fe_q[4] ddc_chain_tb.dut_i0.rx_fe_q[3] ddc_chain_tb.dut_i0.rx_fe_q[2] ddc_chain_tb.dut_i0.rx_fe_q[1] ddc_chain_tb.dut_i0.rx_fe_q[0]
+@20000
+-
+@10420
+#{ddc_chain_tb.dut_i0.i_cordic_clip[23:0]} ddc_chain_tb.dut_i0.i_cordic_clip[23] ddc_chain_tb.dut_i0.i_cordic_clip[22] ddc_chain_tb.dut_i0.i_cordic_clip[21] ddc_chain_tb.dut_i0.i_cordic_clip[20] ddc_chain_tb.dut_i0.i_cordic_clip[19] ddc_chain_tb.dut_i0.i_cordic_clip[18] ddc_chain_tb.dut_i0.i_cordic_clip[17] ddc_chain_tb.dut_i0.i_cordic_clip[16] ddc_chain_tb.dut_i0.i_cordic_clip[15] ddc_chain_tb.dut_i0.i_cordic_clip[14] ddc_chain_tb.dut_i0.i_cordic_clip[13] ddc_chain_tb.dut_i0.i_cordic_clip[12] ddc_chain_tb.dut_i0.i_cordic_clip[11] ddc_chain_tb.dut_i0.i_cordic_clip[10] ddc_chain_tb.dut_i0.i_cordic_clip[9] ddc_chain_tb.dut_i0.i_cordic_clip[8] ddc_chain_tb.dut_i0.i_cordic_clip[7] ddc_chain_tb.dut_i0.i_cordic_clip[6] ddc_chain_tb.dut_i0.i_cordic_clip[5] ddc_chain_tb.dut_i0.i_cordic_clip[4] ddc_chain_tb.dut_i0.i_cordic_clip[3] ddc_chain_tb.dut_i0.i_cordic_clip[2] ddc_chain_tb.dut_i0.i_cordic_clip[1] ddc_chain_tb.dut_i0.i_cordic_clip[0]
+@20000
+-
+@10420
+#{ddc_chain_tb.dut_i0.q_cordic_clip[23:0]} ddc_chain_tb.dut_i0.q_cordic_clip[23] ddc_chain_tb.dut_i0.q_cordic_clip[22] ddc_chain_tb.dut_i0.q_cordic_clip[21] ddc_chain_tb.dut_i0.q_cordic_clip[20] ddc_chain_tb.dut_i0.q_cordic_clip[19] ddc_chain_tb.dut_i0.q_cordic_clip[18] ddc_chain_tb.dut_i0.q_cordic_clip[17] ddc_chain_tb.dut_i0.q_cordic_clip[16] ddc_chain_tb.dut_i0.q_cordic_clip[15] ddc_chain_tb.dut_i0.q_cordic_clip[14] ddc_chain_tb.dut_i0.q_cordic_clip[13] ddc_chain_tb.dut_i0.q_cordic_clip[12] ddc_chain_tb.dut_i0.q_cordic_clip[11] ddc_chain_tb.dut_i0.q_cordic_clip[10] ddc_chain_tb.dut_i0.q_cordic_clip[9] ddc_chain_tb.dut_i0.q_cordic_clip[8] ddc_chain_tb.dut_i0.q_cordic_clip[7] ddc_chain_tb.dut_i0.q_cordic_clip[6] ddc_chain_tb.dut_i0.q_cordic_clip[5] ddc_chain_tb.dut_i0.q_cordic_clip[4] ddc_chain_tb.dut_i0.q_cordic_clip[3] ddc_chain_tb.dut_i0.q_cordic_clip[2] ddc_chain_tb.dut_i0.q_cordic_clip[1] ddc_chain_tb.dut_i0.q_cordic_clip[0]
+@20000
+-
+@10420
+#{ddc_chain_tb.dut_i0.i_cic[23:0]} ddc_chain_tb.dut_i0.i_cic[23] ddc_chain_tb.dut_i0.i_cic[22] ddc_chain_tb.dut_i0.i_cic[21] ddc_chain_tb.dut_i0.i_cic[20] ddc_chain_tb.dut_i0.i_cic[19] ddc_chain_tb.dut_i0.i_cic[18] ddc_chain_tb.dut_i0.i_cic[17] ddc_chain_tb.dut_i0.i_cic[16] ddc_chain_tb.dut_i0.i_cic[15] ddc_chain_tb.dut_i0.i_cic[14] ddc_chain_tb.dut_i0.i_cic[13] ddc_chain_tb.dut_i0.i_cic[12] ddc_chain_tb.dut_i0.i_cic[11] ddc_chain_tb.dut_i0.i_cic[10] ddc_chain_tb.dut_i0.i_cic[9] ddc_chain_tb.dut_i0.i_cic[8] ddc_chain_tb.dut_i0.i_cic[7] ddc_chain_tb.dut_i0.i_cic[6] ddc_chain_tb.dut_i0.i_cic[5] ddc_chain_tb.dut_i0.i_cic[4] ddc_chain_tb.dut_i0.i_cic[3] ddc_chain_tb.dut_i0.i_cic[2] ddc_chain_tb.dut_i0.i_cic[1] ddc_chain_tb.dut_i0.i_cic[0]
+@20000
+-
+@10420
+#{ddc_chain_tb.dut_i0.q_cic[23:0]} ddc_chain_tb.dut_i0.q_cic[23] ddc_chain_tb.dut_i0.q_cic[22] ddc_chain_tb.dut_i0.q_cic[21] ddc_chain_tb.dut_i0.q_cic[20] ddc_chain_tb.dut_i0.q_cic[19] ddc_chain_tb.dut_i0.q_cic[18] ddc_chain_tb.dut_i0.q_cic[17] ddc_chain_tb.dut_i0.q_cic[16] ddc_chain_tb.dut_i0.q_cic[15] ddc_chain_tb.dut_i0.q_cic[14] ddc_chain_tb.dut_i0.q_cic[13] ddc_chain_tb.dut_i0.q_cic[12] ddc_chain_tb.dut_i0.q_cic[11] ddc_chain_tb.dut_i0.q_cic[10] ddc_chain_tb.dut_i0.q_cic[9] ddc_chain_tb.dut_i0.q_cic[8] ddc_chain_tb.dut_i0.q_cic[7] ddc_chain_tb.dut_i0.q_cic[6] ddc_chain_tb.dut_i0.q_cic[5] ddc_chain_tb.dut_i0.q_cic[4] ddc_chain_tb.dut_i0.q_cic[3] ddc_chain_tb.dut_i0.q_cic[2] ddc_chain_tb.dut_i0.q_cic[1] ddc_chain_tb.dut_i0.q_cic[0]
+@20000
+-
+@10420
+#{ddc_chain_tb.dut_i0.\new_hb.i_hb1[46:0]} ddc_chain_tb.dut_i0.\new_hb.i_hb1[46] ddc_chain_tb.dut_i0.\new_hb.i_hb1[45] ddc_chain_tb.dut_i0.\new_hb.i_hb1[44] ddc_chain_tb.dut_i0.\new_hb.i_hb1[43] ddc_chain_tb.dut_i0.\new_hb.i_hb1[42] ddc_chain_tb.dut_i0.\new_hb.i_hb1[41] ddc_chain_tb.dut_i0.\new_hb.i_hb1[40] ddc_chain_tb.dut_i0.\new_hb.i_hb1[39] ddc_chain_tb.dut_i0.\new_hb.i_hb1[38] ddc_chain_tb.dut_i0.\new_hb.i_hb1[37] ddc_chain_tb.dut_i0.\new_hb.i_hb1[36] ddc_chain_tb.dut_i0.\new_hb.i_hb1[35] ddc_chain_tb.dut_i0.\new_hb.i_hb1[34] ddc_chain_tb.dut_i0.\new_hb.i_hb1[33] ddc_chain_tb.dut_i0.\new_hb.i_hb1[32] ddc_chain_tb.dut_i0.\new_hb.i_hb1[31] ddc_chain_tb.dut_i0.\new_hb.i_hb1[30] ddc_chain_tb.dut_i0.\new_hb.i_hb1[29] ddc_chain_tb.dut_i0.\new_hb.i_hb1[28] ddc_chain_tb.dut_i0.\new_hb.i_hb1[27] ddc_chain_tb.dut_i0.\new_hb.i_hb1[26] ddc_chain_tb.dut_i0.\new_hb.i_hb1[25] ddc_chain_tb.dut_i0.\new_hb.i_hb1[24] ddc_chain_tb.dut_i0.\new_hb.i_hb1[23] ddc_chain_tb.dut_i0.\new_hb.i_hb1[22] ddc_chain_tb.dut_i0.\new_hb.i_hb1[21] ddc_chain_tb.dut_i0.\new_hb.i_hb1[20] ddc_chain_tb.dut_i0.\new_hb.i_hb1[19] ddc_chain_tb.dut_i0.\new_hb.i_hb1[18] ddc_chain_tb.dut_i0.\new_hb.i_hb1[17] ddc_chain_tb.dut_i0.\new_hb.i_hb1[16] ddc_chain_tb.dut_i0.\new_hb.i_hb1[15] ddc_chain_tb.dut_i0.\new_hb.i_hb1[14] ddc_chain_tb.dut_i0.\new_hb.i_hb1[13] ddc_chain_tb.dut_i0.\new_hb.i_hb1[12] ddc_chain_tb.dut_i0.\new_hb.i_hb1[11] ddc_chain_tb.dut_i0.\new_hb.i_hb1[10] ddc_chain_tb.dut_i0.\new_hb.i_hb1[9] ddc_chain_tb.dut_i0.\new_hb.i_hb1[8] ddc_chain_tb.dut_i0.\new_hb.i_hb1[7] ddc_chain_tb.dut_i0.\new_hb.i_hb1[6] ddc_chain_tb.dut_i0.\new_hb.i_hb1[5] ddc_chain_tb.dut_i0.\new_hb.i_hb1[4] ddc_chain_tb.dut_i0.\new_hb.i_hb1[3] ddc_chain_tb.dut_i0.\new_hb.i_hb1[2] ddc_chain_tb.dut_i0.\new_hb.i_hb1[1] ddc_chain_tb.dut_i0.\new_hb.i_hb1[0]
+@20000
+-
+@10420
+#{ddc_chain_tb.dut_i0.\new_hb.q_hb1[46:0]} ddc_chain_tb.dut_i0.\new_hb.q_hb1[46] ddc_chain_tb.dut_i0.\new_hb.q_hb1[45] ddc_chain_tb.dut_i0.\new_hb.q_hb1[44] ddc_chain_tb.dut_i0.\new_hb.q_hb1[43] ddc_chain_tb.dut_i0.\new_hb.q_hb1[42] ddc_chain_tb.dut_i0.\new_hb.q_hb1[41] ddc_chain_tb.dut_i0.\new_hb.q_hb1[40] ddc_chain_tb.dut_i0.\new_hb.q_hb1[39] ddc_chain_tb.dut_i0.\new_hb.q_hb1[38] ddc_chain_tb.dut_i0.\new_hb.q_hb1[37] ddc_chain_tb.dut_i0.\new_hb.q_hb1[36] ddc_chain_tb.dut_i0.\new_hb.q_hb1[35] ddc_chain_tb.dut_i0.\new_hb.q_hb1[34] ddc_chain_tb.dut_i0.\new_hb.q_hb1[33] ddc_chain_tb.dut_i0.\new_hb.q_hb1[32] ddc_chain_tb.dut_i0.\new_hb.q_hb1[31] ddc_chain_tb.dut_i0.\new_hb.q_hb1[30] ddc_chain_tb.dut_i0.\new_hb.q_hb1[29] ddc_chain_tb.dut_i0.\new_hb.q_hb1[28] ddc_chain_tb.dut_i0.\new_hb.q_hb1[27] ddc_chain_tb.dut_i0.\new_hb.q_hb1[26] ddc_chain_tb.dut_i0.\new_hb.q_hb1[25] ddc_chain_tb.dut_i0.\new_hb.q_hb1[24] ddc_chain_tb.dut_i0.\new_hb.q_hb1[23] ddc_chain_tb.dut_i0.\new_hb.q_hb1[22] ddc_chain_tb.dut_i0.\new_hb.q_hb1[21] ddc_chain_tb.dut_i0.\new_hb.q_hb1[20] ddc_chain_tb.dut_i0.\new_hb.q_hb1[19] ddc_chain_tb.dut_i0.\new_hb.q_hb1[18] ddc_chain_tb.dut_i0.\new_hb.q_hb1[17] ddc_chain_tb.dut_i0.\new_hb.q_hb1[16] ddc_chain_tb.dut_i0.\new_hb.q_hb1[15] ddc_chain_tb.dut_i0.\new_hb.q_hb1[14] ddc_chain_tb.dut_i0.\new_hb.q_hb1[13] ddc_chain_tb.dut_i0.\new_hb.q_hb1[12] ddc_chain_tb.dut_i0.\new_hb.q_hb1[11] ddc_chain_tb.dut_i0.\new_hb.q_hb1[10] ddc_chain_tb.dut_i0.\new_hb.q_hb1[9] ddc_chain_tb.dut_i0.\new_hb.q_hb1[8] ddc_chain_tb.dut_i0.\new_hb.q_hb1[7] ddc_chain_tb.dut_i0.\new_hb.q_hb1[6] ddc_chain_tb.dut_i0.\new_hb.q_hb1[5] ddc_chain_tb.dut_i0.\new_hb.q_hb1[4] ddc_chain_tb.dut_i0.\new_hb.q_hb1[3] ddc_chain_tb.dut_i0.\new_hb.q_hb1[2] ddc_chain_tb.dut_i0.\new_hb.q_hb1[1] ddc_chain_tb.dut_i0.\new_hb.q_hb1[0]
+@20000
+-
+@10420
+#{ddc_chain_tb.dut_i0.\new_hb.i_hb2[46:0]} ddc_chain_tb.dut_i0.\new_hb.i_hb2[46] ddc_chain_tb.dut_i0.\new_hb.i_hb2[45] ddc_chain_tb.dut_i0.\new_hb.i_hb2[44] ddc_chain_tb.dut_i0.\new_hb.i_hb2[43] ddc_chain_tb.dut_i0.\new_hb.i_hb2[42] ddc_chain_tb.dut_i0.\new_hb.i_hb2[41] ddc_chain_tb.dut_i0.\new_hb.i_hb2[40] ddc_chain_tb.dut_i0.\new_hb.i_hb2[39] ddc_chain_tb.dut_i0.\new_hb.i_hb2[38] ddc_chain_tb.dut_i0.\new_hb.i_hb2[37] ddc_chain_tb.dut_i0.\new_hb.i_hb2[36] ddc_chain_tb.dut_i0.\new_hb.i_hb2[35] ddc_chain_tb.dut_i0.\new_hb.i_hb2[34] ddc_chain_tb.dut_i0.\new_hb.i_hb2[33] ddc_chain_tb.dut_i0.\new_hb.i_hb2[32] ddc_chain_tb.dut_i0.\new_hb.i_hb2[31] ddc_chain_tb.dut_i0.\new_hb.i_hb2[30] ddc_chain_tb.dut_i0.\new_hb.i_hb2[29] ddc_chain_tb.dut_i0.\new_hb.i_hb2[28] ddc_chain_tb.dut_i0.\new_hb.i_hb2[27] ddc_chain_tb.dut_i0.\new_hb.i_hb2[26] ddc_chain_tb.dut_i0.\new_hb.i_hb2[25] ddc_chain_tb.dut_i0.\new_hb.i_hb2[24] ddc_chain_tb.dut_i0.\new_hb.i_hb2[23] ddc_chain_tb.dut_i0.\new_hb.i_hb2[22] ddc_chain_tb.dut_i0.\new_hb.i_hb2[21] ddc_chain_tb.dut_i0.\new_hb.i_hb2[20] ddc_chain_tb.dut_i0.\new_hb.i_hb2[19] ddc_chain_tb.dut_i0.\new_hb.i_hb2[18] ddc_chain_tb.dut_i0.\new_hb.i_hb2[17] ddc_chain_tb.dut_i0.\new_hb.i_hb2[16] ddc_chain_tb.dut_i0.\new_hb.i_hb2[15] ddc_chain_tb.dut_i0.\new_hb.i_hb2[14] ddc_chain_tb.dut_i0.\new_hb.i_hb2[13] ddc_chain_tb.dut_i0.\new_hb.i_hb2[12] ddc_chain_tb.dut_i0.\new_hb.i_hb2[11] ddc_chain_tb.dut_i0.\new_hb.i_hb2[10] ddc_chain_tb.dut_i0.\new_hb.i_hb2[9] ddc_chain_tb.dut_i0.\new_hb.i_hb2[8] ddc_chain_tb.dut_i0.\new_hb.i_hb2[7] ddc_chain_tb.dut_i0.\new_hb.i_hb2[6] ddc_chain_tb.dut_i0.\new_hb.i_hb2[5] ddc_chain_tb.dut_i0.\new_hb.i_hb2[4] ddc_chain_tb.dut_i0.\new_hb.i_hb2[3] ddc_chain_tb.dut_i0.\new_hb.i_hb2[2] ddc_chain_tb.dut_i0.\new_hb.i_hb2[1] ddc_chain_tb.dut_i0.\new_hb.i_hb2[0]
+#{ddc_chain_tb.dut_i0.\new_hb.q_hb2[46:0]} ddc_chain_tb.dut_i0.\new_hb.q_hb2[46] ddc_chain_tb.dut_i0.\new_hb.q_hb2[45] ddc_chain_tb.dut_i0.\new_hb.q_hb2[44] ddc_chain_tb.dut_i0.\new_hb.q_hb2[43] ddc_chain_tb.dut_i0.\new_hb.q_hb2[42] ddc_chain_tb.dut_i0.\new_hb.q_hb2[41] ddc_chain_tb.dut_i0.\new_hb.q_hb2[40] ddc_chain_tb.dut_i0.\new_hb.q_hb2[39] ddc_chain_tb.dut_i0.\new_hb.q_hb2[38] ddc_chain_tb.dut_i0.\new_hb.q_hb2[37] ddc_chain_tb.dut_i0.\new_hb.q_hb2[36] ddc_chain_tb.dut_i0.\new_hb.q_hb2[35] ddc_chain_tb.dut_i0.\new_hb.q_hb2[34] ddc_chain_tb.dut_i0.\new_hb.q_hb2[33] ddc_chain_tb.dut_i0.\new_hb.q_hb2[32] ddc_chain_tb.dut_i0.\new_hb.q_hb2[31] ddc_chain_tb.dut_i0.\new_hb.q_hb2[30] ddc_chain_tb.dut_i0.\new_hb.q_hb2[29] ddc_chain_tb.dut_i0.\new_hb.q_hb2[28] ddc_chain_tb.dut_i0.\new_hb.q_hb2[27] ddc_chain_tb.dut_i0.\new_hb.q_hb2[26] ddc_chain_tb.dut_i0.\new_hb.q_hb2[25] ddc_chain_tb.dut_i0.\new_hb.q_hb2[24] ddc_chain_tb.dut_i0.\new_hb.q_hb2[23] ddc_chain_tb.dut_i0.\new_hb.q_hb2[22] ddc_chain_tb.dut_i0.\new_hb.q_hb2[21] ddc_chain_tb.dut_i0.\new_hb.q_hb2[20] ddc_chain_tb.dut_i0.\new_hb.q_hb2[19] ddc_chain_tb.dut_i0.\new_hb.q_hb2[18] ddc_chain_tb.dut_i0.\new_hb.q_hb2[17] ddc_chain_tb.dut_i0.\new_hb.q_hb2[16] ddc_chain_tb.dut_i0.\new_hb.q_hb2[15] ddc_chain_tb.dut_i0.\new_hb.q_hb2[14] ddc_chain_tb.dut_i0.\new_hb.q_hb2[13] ddc_chain_tb.dut_i0.\new_hb.q_hb2[12] ddc_chain_tb.dut_i0.\new_hb.q_hb2[11] ddc_chain_tb.dut_i0.\new_hb.q_hb2[10] ddc_chain_tb.dut_i0.\new_hb.q_hb2[9] ddc_chain_tb.dut_i0.\new_hb.q_hb2[8] ddc_chain_tb.dut_i0.\new_hb.q_hb2[7] ddc_chain_tb.dut_i0.\new_hb.q_hb2[6] ddc_chain_tb.dut_i0.\new_hb.q_hb2[5] ddc_chain_tb.dut_i0.\new_hb.q_hb2[4] ddc_chain_tb.dut_i0.\new_hb.q_hb2[3] ddc_chain_tb.dut_i0.\new_hb.q_hb2[2] ddc_chain_tb.dut_i0.\new_hb.q_hb2[1] ddc_chain_tb.dut_i0.\new_hb.q_hb2[0]
+@20000
+-
+[pattern_trace] 1
+[pattern_trace] 0
diff --git a/fpga/usrp3/lib/dsp/sim/sim_ddc_chain/dc_in_cordic_decim_2/simulation_script.v b/fpga/usrp3/lib/dsp/sim/sim_ddc_chain/dc_in_cordic_decim_2/simulation_script.v
new file mode 100644
index 000000000..0eeb661da
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/sim/sim_ddc_chain/dc_in_cordic_decim_2/simulation_script.v
@@ -0,0 +1,82 @@
+//
+// Copyright 2015 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// 10MHz master_clock_rate
+always #50 clk <= ~clk;
+
+   initial
+     begin
+	reset <= 1'b0;
+	i_in <= 0;
+	q_in <= 0;
+	run <= 0;
+	set_stb <= 0;
+	set_addr <= 0;
+	set_data <= 0;
+
+
+	@(posedge clk);
+	// Into Reset...
+	reset <= 1'b1;
+	repeat(10) @(posedge clk);
+	// .. and back out of reset.
+	reset <= 1'b0;
+	repeat(10) @(posedge clk);
+	// Now program DSP configuration via settings regs.
+	write_setting_bus(SR_DSP_RX_FREQ,42949672); // 100kHz @ 10MHz MCR
+	//  (1 << 15) * std::pow(2, ceil_log2(rate_pow))*2./(1.648*rate_pow)
+	write_setting_bus(SR_DSP_RX_SCALE_IQ, 39767); // Should include CORDIC and CIC gain compensation.
+	write_setting_bus(SR_DSP_RX_DECIM, 1<<9|1); // Decim = 2
+	write_setting_bus(SR_DSP_RX_MUX, 0);
+	write_setting_bus(SR_DSP_RX_COEFFS,0);
+	repeat(10) @(posedge clk);
+
+	// Set complex data inputs to DC unit circle position.
+	i_in <= 12'h7ff;
+	q_in <= 12'h0;
+	run <= 1'b1;
+	repeat(100) @(posedge clk);
+	// Set complex data inputs to simulate ADC saturation of front end
+	i_in <= 12'h7ff;
+	q_in <= 12'h100;
+	repeat(1000) @(posedge clk);
+	i_in <= 12'h7ff;
+	q_in <= 12'h200;
+	repeat(1000) @(posedge clk);
+	i_in <= 12'h7ff;
+	q_in <= 12'h300;
+	repeat(1000) @(posedge clk);
+	i_in <= 12'h7ff;
+	q_in <= 12'h400;
+	repeat(1000) @(posedge clk);
+	i_in <= 12'h7ff;
+	q_in <= 12'h500;
+	repeat(1000) @(posedge clk);
+	i_in <= 12'h7ff;
+	q_in <= 12'h600;
+	repeat(1000) @(posedge clk);
+	i_in <= 12'h7ff;
+	q_in <= 12'h700;
+	repeat(1000) @(posedge clk);
+ 	i_in <= 12'h7ff;
+	q_in <= 12'h7FF;
+	// Now test small signal performance
+	repeat(1000) @(posedge clk);
+	i_in <= 12'h001;
+	q_in <= 12'h000;
+	repeat(1000) @(posedge clk);
+ 	i_in <= 12'h000;
+	q_in <= 12'h001;
+	repeat(1000) @(posedge clk);
+	i_in <= 12'hfff;
+	q_in <= 12'h000;
+	repeat(1000) @(posedge clk);
+ 	i_in <= 12'h000;
+	q_in <= 12'hfff;
+
+	repeat(100000) @(posedge clk);
+	$finish();
+
+     end // initial begin
diff --git a/fpga/usrp3/lib/dsp/sim/sim_ddc_chain/dc_in_cordic_decim_6/gtk.conf.gtkw b/fpga/usrp3/lib/dsp/sim/sim_ddc_chain/dc_in_cordic_decim_6/gtk.conf.gtkw
new file mode 100644
index 000000000..27c2c836e
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/sim/sim_ddc_chain/dc_in_cordic_decim_6/gtk.conf.gtkw
@@ -0,0 +1,64 @@
+[*]
+[*] GTKWave Analyzer v3.3.40 (w)1999-2012 BSI
+[*] Wed Jul 15 02:18:40 2015
+[*]
+[dumpfile] "/disk2/ianb/ettus/fpgadev-b200/fpgadev/usrp3/lib/dsp/sim/sim_ddc_chain/dc_in_cordic_run/waves.vcd"
+[dumpfile_mtime] "Wed Jul 15 02:13:19 2015"
+[dumpfile_size] 238141440
+[savefile] "/disk2/ianb/ettus/fpgadev-b200/fpgadev/usrp3/lib/dsp/sim/sim_ddc_chain/dc_in_cordic_run/gtk.conf.gtkw"
+[timestart] 0
+[size] 2488 1221
+[pos] -1 -1
+*-24.083374 129800000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] ddc_chain_tb.
+[treeopen] ddc_chain_tb.dut_i0.
+[sst_width] 331
+[signals_width] 280
+[sst_expanded] 1
+[sst_vpaned_height] 370
+@28
+ddc_chain_tb.dut_i0.clk
+ddc_chain_tb.dut_i0.rst
+ddc_chain_tb.dut_i0.set_stb
+@22
+#{ddc_chain_tb.dut_i0.set_addr[7:0]} ddc_chain_tb.dut_i0.set_addr[7] ddc_chain_tb.dut_i0.set_addr[6] ddc_chain_tb.dut_i0.set_addr[5] ddc_chain_tb.dut_i0.set_addr[4] ddc_chain_tb.dut_i0.set_addr[3] ddc_chain_tb.dut_i0.set_addr[2] ddc_chain_tb.dut_i0.set_addr[1] ddc_chain_tb.dut_i0.set_addr[0]
+#{ddc_chain_tb.dut_i0.set_data[31:0]} ddc_chain_tb.dut_i0.set_data[31] ddc_chain_tb.dut_i0.set_data[30] ddc_chain_tb.dut_i0.set_data[29] ddc_chain_tb.dut_i0.set_data[28] ddc_chain_tb.dut_i0.set_data[27] ddc_chain_tb.dut_i0.set_data[26] ddc_chain_tb.dut_i0.set_data[25] ddc_chain_tb.dut_i0.set_data[24] ddc_chain_tb.dut_i0.set_data[23] ddc_chain_tb.dut_i0.set_data[22] ddc_chain_tb.dut_i0.set_data[21] ddc_chain_tb.dut_i0.set_data[20] ddc_chain_tb.dut_i0.set_data[19] ddc_chain_tb.dut_i0.set_data[18] ddc_chain_tb.dut_i0.set_data[17] ddc_chain_tb.dut_i0.set_data[16] ddc_chain_tb.dut_i0.set_data[15] ddc_chain_tb.dut_i0.set_data[14] ddc_chain_tb.dut_i0.set_data[13] ddc_chain_tb.dut_i0.set_data[12] ddc_chain_tb.dut_i0.set_data[11] ddc_chain_tb.dut_i0.set_data[10] ddc_chain_tb.dut_i0.set_data[9] ddc_chain_tb.dut_i0.set_data[8] ddc_chain_tb.dut_i0.set_data[7] ddc_chain_tb.dut_i0.set_data[6] ddc_chain_tb.dut_i0.set_data[5] ddc_chain_tb.dut_i0.set_data[4] ddc_chain_tb.dut_i0.set_data[3] ddc_chain_tb.dut_i0.set_data[2] ddc_chain_tb.dut_i0.set_data[1] ddc_chain_tb.dut_i0.set_data[0]
+@10420
+#{ddc_chain_tb.dut_i0.rx_fe_i[23:0]} ddc_chain_tb.dut_i0.rx_fe_i[23] ddc_chain_tb.dut_i0.rx_fe_i[22] ddc_chain_tb.dut_i0.rx_fe_i[21] ddc_chain_tb.dut_i0.rx_fe_i[20] ddc_chain_tb.dut_i0.rx_fe_i[19] ddc_chain_tb.dut_i0.rx_fe_i[18] ddc_chain_tb.dut_i0.rx_fe_i[17] ddc_chain_tb.dut_i0.rx_fe_i[16] ddc_chain_tb.dut_i0.rx_fe_i[15] ddc_chain_tb.dut_i0.rx_fe_i[14] ddc_chain_tb.dut_i0.rx_fe_i[13] ddc_chain_tb.dut_i0.rx_fe_i[12] ddc_chain_tb.dut_i0.rx_fe_i[11] ddc_chain_tb.dut_i0.rx_fe_i[10] ddc_chain_tb.dut_i0.rx_fe_i[9] ddc_chain_tb.dut_i0.rx_fe_i[8] ddc_chain_tb.dut_i0.rx_fe_i[7] ddc_chain_tb.dut_i0.rx_fe_i[6] ddc_chain_tb.dut_i0.rx_fe_i[5] ddc_chain_tb.dut_i0.rx_fe_i[4] ddc_chain_tb.dut_i0.rx_fe_i[3] ddc_chain_tb.dut_i0.rx_fe_i[2] ddc_chain_tb.dut_i0.rx_fe_i[1] ddc_chain_tb.dut_i0.rx_fe_i[0]
+@20000
+-
+@10420
+#{ddc_chain_tb.dut_i0.rx_fe_q[23:0]} ddc_chain_tb.dut_i0.rx_fe_q[23] ddc_chain_tb.dut_i0.rx_fe_q[22] ddc_chain_tb.dut_i0.rx_fe_q[21] ddc_chain_tb.dut_i0.rx_fe_q[20] ddc_chain_tb.dut_i0.rx_fe_q[19] ddc_chain_tb.dut_i0.rx_fe_q[18] ddc_chain_tb.dut_i0.rx_fe_q[17] ddc_chain_tb.dut_i0.rx_fe_q[16] ddc_chain_tb.dut_i0.rx_fe_q[15] ddc_chain_tb.dut_i0.rx_fe_q[14] ddc_chain_tb.dut_i0.rx_fe_q[13] ddc_chain_tb.dut_i0.rx_fe_q[12] ddc_chain_tb.dut_i0.rx_fe_q[11] ddc_chain_tb.dut_i0.rx_fe_q[10] ddc_chain_tb.dut_i0.rx_fe_q[9] ddc_chain_tb.dut_i0.rx_fe_q[8] ddc_chain_tb.dut_i0.rx_fe_q[7] ddc_chain_tb.dut_i0.rx_fe_q[6] ddc_chain_tb.dut_i0.rx_fe_q[5] ddc_chain_tb.dut_i0.rx_fe_q[4] ddc_chain_tb.dut_i0.rx_fe_q[3] ddc_chain_tb.dut_i0.rx_fe_q[2] ddc_chain_tb.dut_i0.rx_fe_q[1] ddc_chain_tb.dut_i0.rx_fe_q[0]
+@20000
+-
+@10420
+#{ddc_chain_tb.dut_i0.i_cordic_clip[23:0]} ddc_chain_tb.dut_i0.i_cordic_clip[23] ddc_chain_tb.dut_i0.i_cordic_clip[22] ddc_chain_tb.dut_i0.i_cordic_clip[21] ddc_chain_tb.dut_i0.i_cordic_clip[20] ddc_chain_tb.dut_i0.i_cordic_clip[19] ddc_chain_tb.dut_i0.i_cordic_clip[18] ddc_chain_tb.dut_i0.i_cordic_clip[17] ddc_chain_tb.dut_i0.i_cordic_clip[16] ddc_chain_tb.dut_i0.i_cordic_clip[15] ddc_chain_tb.dut_i0.i_cordic_clip[14] ddc_chain_tb.dut_i0.i_cordic_clip[13] ddc_chain_tb.dut_i0.i_cordic_clip[12] ddc_chain_tb.dut_i0.i_cordic_clip[11] ddc_chain_tb.dut_i0.i_cordic_clip[10] ddc_chain_tb.dut_i0.i_cordic_clip[9] ddc_chain_tb.dut_i0.i_cordic_clip[8] ddc_chain_tb.dut_i0.i_cordic_clip[7] ddc_chain_tb.dut_i0.i_cordic_clip[6] ddc_chain_tb.dut_i0.i_cordic_clip[5] ddc_chain_tb.dut_i0.i_cordic_clip[4] ddc_chain_tb.dut_i0.i_cordic_clip[3] ddc_chain_tb.dut_i0.i_cordic_clip[2] ddc_chain_tb.dut_i0.i_cordic_clip[1] ddc_chain_tb.dut_i0.i_cordic_clip[0]
+@20000
+-
+@10420
+#{ddc_chain_tb.dut_i0.q_cordic_clip[23:0]} ddc_chain_tb.dut_i0.q_cordic_clip[23] ddc_chain_tb.dut_i0.q_cordic_clip[22] ddc_chain_tb.dut_i0.q_cordic_clip[21] ddc_chain_tb.dut_i0.q_cordic_clip[20] ddc_chain_tb.dut_i0.q_cordic_clip[19] ddc_chain_tb.dut_i0.q_cordic_clip[18] ddc_chain_tb.dut_i0.q_cordic_clip[17] ddc_chain_tb.dut_i0.q_cordic_clip[16] ddc_chain_tb.dut_i0.q_cordic_clip[15] ddc_chain_tb.dut_i0.q_cordic_clip[14] ddc_chain_tb.dut_i0.q_cordic_clip[13] ddc_chain_tb.dut_i0.q_cordic_clip[12] ddc_chain_tb.dut_i0.q_cordic_clip[11] ddc_chain_tb.dut_i0.q_cordic_clip[10] ddc_chain_tb.dut_i0.q_cordic_clip[9] ddc_chain_tb.dut_i0.q_cordic_clip[8] ddc_chain_tb.dut_i0.q_cordic_clip[7] ddc_chain_tb.dut_i0.q_cordic_clip[6] ddc_chain_tb.dut_i0.q_cordic_clip[5] ddc_chain_tb.dut_i0.q_cordic_clip[4] ddc_chain_tb.dut_i0.q_cordic_clip[3] ddc_chain_tb.dut_i0.q_cordic_clip[2] ddc_chain_tb.dut_i0.q_cordic_clip[1] ddc_chain_tb.dut_i0.q_cordic_clip[0]
+@20000
+-
+@10420
+#{ddc_chain_tb.dut_i0.i_cic[23:0]} ddc_chain_tb.dut_i0.i_cic[23] ddc_chain_tb.dut_i0.i_cic[22] ddc_chain_tb.dut_i0.i_cic[21] ddc_chain_tb.dut_i0.i_cic[20] ddc_chain_tb.dut_i0.i_cic[19] ddc_chain_tb.dut_i0.i_cic[18] ddc_chain_tb.dut_i0.i_cic[17] ddc_chain_tb.dut_i0.i_cic[16] ddc_chain_tb.dut_i0.i_cic[15] ddc_chain_tb.dut_i0.i_cic[14] ddc_chain_tb.dut_i0.i_cic[13] ddc_chain_tb.dut_i0.i_cic[12] ddc_chain_tb.dut_i0.i_cic[11] ddc_chain_tb.dut_i0.i_cic[10] ddc_chain_tb.dut_i0.i_cic[9] ddc_chain_tb.dut_i0.i_cic[8] ddc_chain_tb.dut_i0.i_cic[7] ddc_chain_tb.dut_i0.i_cic[6] ddc_chain_tb.dut_i0.i_cic[5] ddc_chain_tb.dut_i0.i_cic[4] ddc_chain_tb.dut_i0.i_cic[3] ddc_chain_tb.dut_i0.i_cic[2] ddc_chain_tb.dut_i0.i_cic[1] ddc_chain_tb.dut_i0.i_cic[0]
+@20000
+-
+@10420
+#{ddc_chain_tb.dut_i0.q_cic[23:0]} ddc_chain_tb.dut_i0.q_cic[23] ddc_chain_tb.dut_i0.q_cic[22] ddc_chain_tb.dut_i0.q_cic[21] ddc_chain_tb.dut_i0.q_cic[20] ddc_chain_tb.dut_i0.q_cic[19] ddc_chain_tb.dut_i0.q_cic[18] ddc_chain_tb.dut_i0.q_cic[17] ddc_chain_tb.dut_i0.q_cic[16] ddc_chain_tb.dut_i0.q_cic[15] ddc_chain_tb.dut_i0.q_cic[14] ddc_chain_tb.dut_i0.q_cic[13] ddc_chain_tb.dut_i0.q_cic[12] ddc_chain_tb.dut_i0.q_cic[11] ddc_chain_tb.dut_i0.q_cic[10] ddc_chain_tb.dut_i0.q_cic[9] ddc_chain_tb.dut_i0.q_cic[8] ddc_chain_tb.dut_i0.q_cic[7] ddc_chain_tb.dut_i0.q_cic[6] ddc_chain_tb.dut_i0.q_cic[5] ddc_chain_tb.dut_i0.q_cic[4] ddc_chain_tb.dut_i0.q_cic[3] ddc_chain_tb.dut_i0.q_cic[2] ddc_chain_tb.dut_i0.q_cic[1] ddc_chain_tb.dut_i0.q_cic[0]
+@20000
+-
+@10420
+#{ddc_chain_tb.dut_i0.\new_hb.i_hb1[46:0]} ddc_chain_tb.dut_i0.\new_hb.i_hb1[46] ddc_chain_tb.dut_i0.\new_hb.i_hb1[45] ddc_chain_tb.dut_i0.\new_hb.i_hb1[44] ddc_chain_tb.dut_i0.\new_hb.i_hb1[43] ddc_chain_tb.dut_i0.\new_hb.i_hb1[42] ddc_chain_tb.dut_i0.\new_hb.i_hb1[41] ddc_chain_tb.dut_i0.\new_hb.i_hb1[40] ddc_chain_tb.dut_i0.\new_hb.i_hb1[39] ddc_chain_tb.dut_i0.\new_hb.i_hb1[38] ddc_chain_tb.dut_i0.\new_hb.i_hb1[37] ddc_chain_tb.dut_i0.\new_hb.i_hb1[36] ddc_chain_tb.dut_i0.\new_hb.i_hb1[35] ddc_chain_tb.dut_i0.\new_hb.i_hb1[34] ddc_chain_tb.dut_i0.\new_hb.i_hb1[33] ddc_chain_tb.dut_i0.\new_hb.i_hb1[32] ddc_chain_tb.dut_i0.\new_hb.i_hb1[31] ddc_chain_tb.dut_i0.\new_hb.i_hb1[30] ddc_chain_tb.dut_i0.\new_hb.i_hb1[29] ddc_chain_tb.dut_i0.\new_hb.i_hb1[28] ddc_chain_tb.dut_i0.\new_hb.i_hb1[27] ddc_chain_tb.dut_i0.\new_hb.i_hb1[26] ddc_chain_tb.dut_i0.\new_hb.i_hb1[25] ddc_chain_tb.dut_i0.\new_hb.i_hb1[24] ddc_chain_tb.dut_i0.\new_hb.i_hb1[23] ddc_chain_tb.dut_i0.\new_hb.i_hb1[22] ddc_chain_tb.dut_i0.\new_hb.i_hb1[21] ddc_chain_tb.dut_i0.\new_hb.i_hb1[20] ddc_chain_tb.dut_i0.\new_hb.i_hb1[19] ddc_chain_tb.dut_i0.\new_hb.i_hb1[18] ddc_chain_tb.dut_i0.\new_hb.i_hb1[17] ddc_chain_tb.dut_i0.\new_hb.i_hb1[16] ddc_chain_tb.dut_i0.\new_hb.i_hb1[15] ddc_chain_tb.dut_i0.\new_hb.i_hb1[14] ddc_chain_tb.dut_i0.\new_hb.i_hb1[13] ddc_chain_tb.dut_i0.\new_hb.i_hb1[12] ddc_chain_tb.dut_i0.\new_hb.i_hb1[11] ddc_chain_tb.dut_i0.\new_hb.i_hb1[10] ddc_chain_tb.dut_i0.\new_hb.i_hb1[9] ddc_chain_tb.dut_i0.\new_hb.i_hb1[8] ddc_chain_tb.dut_i0.\new_hb.i_hb1[7] ddc_chain_tb.dut_i0.\new_hb.i_hb1[6] ddc_chain_tb.dut_i0.\new_hb.i_hb1[5] ddc_chain_tb.dut_i0.\new_hb.i_hb1[4] ddc_chain_tb.dut_i0.\new_hb.i_hb1[3] ddc_chain_tb.dut_i0.\new_hb.i_hb1[2] ddc_chain_tb.dut_i0.\new_hb.i_hb1[1] ddc_chain_tb.dut_i0.\new_hb.i_hb1[0]
+@20000
+-
+@10420
+#{ddc_chain_tb.dut_i0.\new_hb.q_hb1[46:0]} ddc_chain_tb.dut_i0.\new_hb.q_hb1[46] ddc_chain_tb.dut_i0.\new_hb.q_hb1[45] ddc_chain_tb.dut_i0.\new_hb.q_hb1[44] ddc_chain_tb.dut_i0.\new_hb.q_hb1[43] ddc_chain_tb.dut_i0.\new_hb.q_hb1[42] ddc_chain_tb.dut_i0.\new_hb.q_hb1[41] ddc_chain_tb.dut_i0.\new_hb.q_hb1[40] ddc_chain_tb.dut_i0.\new_hb.q_hb1[39] ddc_chain_tb.dut_i0.\new_hb.q_hb1[38] ddc_chain_tb.dut_i0.\new_hb.q_hb1[37] ddc_chain_tb.dut_i0.\new_hb.q_hb1[36] ddc_chain_tb.dut_i0.\new_hb.q_hb1[35] ddc_chain_tb.dut_i0.\new_hb.q_hb1[34] ddc_chain_tb.dut_i0.\new_hb.q_hb1[33] ddc_chain_tb.dut_i0.\new_hb.q_hb1[32] ddc_chain_tb.dut_i0.\new_hb.q_hb1[31] ddc_chain_tb.dut_i0.\new_hb.q_hb1[30] ddc_chain_tb.dut_i0.\new_hb.q_hb1[29] ddc_chain_tb.dut_i0.\new_hb.q_hb1[28] ddc_chain_tb.dut_i0.\new_hb.q_hb1[27] ddc_chain_tb.dut_i0.\new_hb.q_hb1[26] ddc_chain_tb.dut_i0.\new_hb.q_hb1[25] ddc_chain_tb.dut_i0.\new_hb.q_hb1[24] ddc_chain_tb.dut_i0.\new_hb.q_hb1[23] ddc_chain_tb.dut_i0.\new_hb.q_hb1[22] ddc_chain_tb.dut_i0.\new_hb.q_hb1[21] ddc_chain_tb.dut_i0.\new_hb.q_hb1[20] ddc_chain_tb.dut_i0.\new_hb.q_hb1[19] ddc_chain_tb.dut_i0.\new_hb.q_hb1[18] ddc_chain_tb.dut_i0.\new_hb.q_hb1[17] ddc_chain_tb.dut_i0.\new_hb.q_hb1[16] ddc_chain_tb.dut_i0.\new_hb.q_hb1[15] ddc_chain_tb.dut_i0.\new_hb.q_hb1[14] ddc_chain_tb.dut_i0.\new_hb.q_hb1[13] ddc_chain_tb.dut_i0.\new_hb.q_hb1[12] ddc_chain_tb.dut_i0.\new_hb.q_hb1[11] ddc_chain_tb.dut_i0.\new_hb.q_hb1[10] ddc_chain_tb.dut_i0.\new_hb.q_hb1[9] ddc_chain_tb.dut_i0.\new_hb.q_hb1[8] ddc_chain_tb.dut_i0.\new_hb.q_hb1[7] ddc_chain_tb.dut_i0.\new_hb.q_hb1[6] ddc_chain_tb.dut_i0.\new_hb.q_hb1[5] ddc_chain_tb.dut_i0.\new_hb.q_hb1[4] ddc_chain_tb.dut_i0.\new_hb.q_hb1[3] ddc_chain_tb.dut_i0.\new_hb.q_hb1[2] ddc_chain_tb.dut_i0.\new_hb.q_hb1[1] ddc_chain_tb.dut_i0.\new_hb.q_hb1[0]
+@20000
+-
+@10420
+#{ddc_chain_tb.dut_i0.\new_hb.i_hb2[46:0]} ddc_chain_tb.dut_i0.\new_hb.i_hb2[46] ddc_chain_tb.dut_i0.\new_hb.i_hb2[45] ddc_chain_tb.dut_i0.\new_hb.i_hb2[44] ddc_chain_tb.dut_i0.\new_hb.i_hb2[43] ddc_chain_tb.dut_i0.\new_hb.i_hb2[42] ddc_chain_tb.dut_i0.\new_hb.i_hb2[41] ddc_chain_tb.dut_i0.\new_hb.i_hb2[40] ddc_chain_tb.dut_i0.\new_hb.i_hb2[39] ddc_chain_tb.dut_i0.\new_hb.i_hb2[38] ddc_chain_tb.dut_i0.\new_hb.i_hb2[37] ddc_chain_tb.dut_i0.\new_hb.i_hb2[36] ddc_chain_tb.dut_i0.\new_hb.i_hb2[35] ddc_chain_tb.dut_i0.\new_hb.i_hb2[34] ddc_chain_tb.dut_i0.\new_hb.i_hb2[33] ddc_chain_tb.dut_i0.\new_hb.i_hb2[32] ddc_chain_tb.dut_i0.\new_hb.i_hb2[31] ddc_chain_tb.dut_i0.\new_hb.i_hb2[30] ddc_chain_tb.dut_i0.\new_hb.i_hb2[29] ddc_chain_tb.dut_i0.\new_hb.i_hb2[28] ddc_chain_tb.dut_i0.\new_hb.i_hb2[27] ddc_chain_tb.dut_i0.\new_hb.i_hb2[26] ddc_chain_tb.dut_i0.\new_hb.i_hb2[25] ddc_chain_tb.dut_i0.\new_hb.i_hb2[24] ddc_chain_tb.dut_i0.\new_hb.i_hb2[23] ddc_chain_tb.dut_i0.\new_hb.i_hb2[22] ddc_chain_tb.dut_i0.\new_hb.i_hb2[21] ddc_chain_tb.dut_i0.\new_hb.i_hb2[20] ddc_chain_tb.dut_i0.\new_hb.i_hb2[19] ddc_chain_tb.dut_i0.\new_hb.i_hb2[18] ddc_chain_tb.dut_i0.\new_hb.i_hb2[17] ddc_chain_tb.dut_i0.\new_hb.i_hb2[16] ddc_chain_tb.dut_i0.\new_hb.i_hb2[15] ddc_chain_tb.dut_i0.\new_hb.i_hb2[14] ddc_chain_tb.dut_i0.\new_hb.i_hb2[13] ddc_chain_tb.dut_i0.\new_hb.i_hb2[12] ddc_chain_tb.dut_i0.\new_hb.i_hb2[11] ddc_chain_tb.dut_i0.\new_hb.i_hb2[10] ddc_chain_tb.dut_i0.\new_hb.i_hb2[9] ddc_chain_tb.dut_i0.\new_hb.i_hb2[8] ddc_chain_tb.dut_i0.\new_hb.i_hb2[7] ddc_chain_tb.dut_i0.\new_hb.i_hb2[6] ddc_chain_tb.dut_i0.\new_hb.i_hb2[5] ddc_chain_tb.dut_i0.\new_hb.i_hb2[4] ddc_chain_tb.dut_i0.\new_hb.i_hb2[3] ddc_chain_tb.dut_i0.\new_hb.i_hb2[2] ddc_chain_tb.dut_i0.\new_hb.i_hb2[1] ddc_chain_tb.dut_i0.\new_hb.i_hb2[0]
+#{ddc_chain_tb.dut_i0.\new_hb.q_hb2[46:0]} ddc_chain_tb.dut_i0.\new_hb.q_hb2[46] ddc_chain_tb.dut_i0.\new_hb.q_hb2[45] ddc_chain_tb.dut_i0.\new_hb.q_hb2[44] ddc_chain_tb.dut_i0.\new_hb.q_hb2[43] ddc_chain_tb.dut_i0.\new_hb.q_hb2[42] ddc_chain_tb.dut_i0.\new_hb.q_hb2[41] ddc_chain_tb.dut_i0.\new_hb.q_hb2[40] ddc_chain_tb.dut_i0.\new_hb.q_hb2[39] ddc_chain_tb.dut_i0.\new_hb.q_hb2[38] ddc_chain_tb.dut_i0.\new_hb.q_hb2[37] ddc_chain_tb.dut_i0.\new_hb.q_hb2[36] ddc_chain_tb.dut_i0.\new_hb.q_hb2[35] ddc_chain_tb.dut_i0.\new_hb.q_hb2[34] ddc_chain_tb.dut_i0.\new_hb.q_hb2[33] ddc_chain_tb.dut_i0.\new_hb.q_hb2[32] ddc_chain_tb.dut_i0.\new_hb.q_hb2[31] ddc_chain_tb.dut_i0.\new_hb.q_hb2[30] ddc_chain_tb.dut_i0.\new_hb.q_hb2[29] ddc_chain_tb.dut_i0.\new_hb.q_hb2[28] ddc_chain_tb.dut_i0.\new_hb.q_hb2[27] ddc_chain_tb.dut_i0.\new_hb.q_hb2[26] ddc_chain_tb.dut_i0.\new_hb.q_hb2[25] ddc_chain_tb.dut_i0.\new_hb.q_hb2[24] ddc_chain_tb.dut_i0.\new_hb.q_hb2[23] ddc_chain_tb.dut_i0.\new_hb.q_hb2[22] ddc_chain_tb.dut_i0.\new_hb.q_hb2[21] ddc_chain_tb.dut_i0.\new_hb.q_hb2[20] ddc_chain_tb.dut_i0.\new_hb.q_hb2[19] ddc_chain_tb.dut_i0.\new_hb.q_hb2[18] ddc_chain_tb.dut_i0.\new_hb.q_hb2[17] ddc_chain_tb.dut_i0.\new_hb.q_hb2[16] ddc_chain_tb.dut_i0.\new_hb.q_hb2[15] ddc_chain_tb.dut_i0.\new_hb.q_hb2[14] ddc_chain_tb.dut_i0.\new_hb.q_hb2[13] ddc_chain_tb.dut_i0.\new_hb.q_hb2[12] ddc_chain_tb.dut_i0.\new_hb.q_hb2[11] ddc_chain_tb.dut_i0.\new_hb.q_hb2[10] ddc_chain_tb.dut_i0.\new_hb.q_hb2[9] ddc_chain_tb.dut_i0.\new_hb.q_hb2[8] ddc_chain_tb.dut_i0.\new_hb.q_hb2[7] ddc_chain_tb.dut_i0.\new_hb.q_hb2[6] ddc_chain_tb.dut_i0.\new_hb.q_hb2[5] ddc_chain_tb.dut_i0.\new_hb.q_hb2[4] ddc_chain_tb.dut_i0.\new_hb.q_hb2[3] ddc_chain_tb.dut_i0.\new_hb.q_hb2[2] ddc_chain_tb.dut_i0.\new_hb.q_hb2[1] ddc_chain_tb.dut_i0.\new_hb.q_hb2[0]
+@20000
+-
+[pattern_trace] 1
+[pattern_trace] 0
diff --git a/fpga/usrp3/lib/dsp/sim/sim_ddc_chain/dc_in_cordic_decim_6/simulation_script.v b/fpga/usrp3/lib/dsp/sim/sim_ddc_chain/dc_in_cordic_decim_6/simulation_script.v
new file mode 100644
index 000000000..091162a5a
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/sim/sim_ddc_chain/dc_in_cordic_decim_6/simulation_script.v
@@ -0,0 +1,83 @@
+//
+// Copyright 2015 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// 10MHz master_clock_rate
+always #50 clk <= ~clk;
+
+   initial
+     begin
+	reset <= 1'b0;
+	i_in <= 0;
+	q_in <= 0;
+	run <= 0;
+	set_stb <= 0;
+	set_addr <= 0;
+	set_data <= 0;
+
+
+	@(posedge clk);
+	// Into Reset...
+	reset <= 1'b1;
+	repeat(10) @(posedge clk);
+	// .. and back out of reset.
+	reset <= 1'b0;
+	repeat(10) @(posedge clk);
+	// Now program DSP configuration via settings regs.
+	write_setting_bus(SR_DSP_RX_FREQ,42949672); // 100kHz @ 10MHz MCR
+	write_setting_bus(SR_DSP_RX_SCALE_IQ, 62842); // Should include CORDIC and CIC gain compensation.
+       // write_setting_bus(SR_DSP_RX_SCALE_IQ, ((1<<16) * 1.647 * 0.5 * 1.22)); // Should include CORDIC and CIC gain compensation.
+	write_setting_bus(SR_DSP_RX_DECIM, 1<<9|3); // Decim = 6
+	write_setting_bus(SR_DSP_RX_MUX, 0);
+	write_setting_bus(SR_DSP_RX_COEFFS,0);
+	repeat(10) @(posedge clk);
+
+	// Set complex data inputs to DC unit circle position.
+	i_in <= 12'h7ff;
+	q_in <= 12'h0;
+	run <= 1'b1;
+	repeat(100) @(posedge clk);
+	// Set complex data inputs to simulate ADC saturation of front end
+	i_in <= 12'h7ff;
+	q_in <= 12'h100;
+	repeat(1000) @(posedge clk);
+	i_in <= 12'h7ff;
+	q_in <= 12'h200;
+	repeat(1000) @(posedge clk);
+	i_in <= 12'h7ff;
+	q_in <= 12'h300;
+	repeat(1000) @(posedge clk);
+	i_in <= 12'h7ff;
+	q_in <= 12'h400;
+	repeat(1000) @(posedge clk);
+	i_in <= 12'h7ff;
+	q_in <= 12'h500;
+	repeat(1000) @(posedge clk);
+	i_in <= 12'h7ff;
+	q_in <= 12'h600;
+	repeat(1000) @(posedge clk);
+	i_in <= 12'h7ff;
+	q_in <= 12'h700;
+	repeat(1000) @(posedge clk);
+ 	i_in <= 12'h7ff;
+	q_in <= 12'h7FF;
+	// Now test small signal performance
+	repeat(1000) @(posedge clk);
+	i_in <= 12'h001;
+	q_in <= 12'h000;
+	repeat(1000) @(posedge clk);
+ 	i_in <= 12'h000;
+	q_in <= 12'h001;
+	repeat(1000) @(posedge clk);
+	i_in <= 12'hfff;
+	q_in <= 12'h000;
+	repeat(1000) @(posedge clk);
+ 	i_in <= 12'h000;
+	q_in <= 12'hfff;
+
+
+	repeat(100000) @(posedge clk);
+	$finish();
+
+     end // initial begin
diff --git a/fpga/usrp3/lib/dsp/sim/sim_ddc_chain/ddc_chain_tb.v b/fpga/usrp3/lib/dsp/sim/sim_ddc_chain/ddc_chain_tb.v
new file mode 100644
index 000000000..76f0db300
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/sim/sim_ddc_chain/ddc_chain_tb.v
@@ -0,0 +1,94 @@
+//
+// Copyright 2015 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+`timescale 1ns/1ps
+
+module ddc_chain_tb();
+
+   initial $dumpfile("waves.vcd");
+   initial $dumpvars(2,ddc_chain_tb.dut_i0);
+
+
+   // Need these declarations to use the task libarary.
+`ifndef CHDR_IN_NUMBER
+ `define CHDR_IN_NUMBER 1
+`endif
+`ifndef CHDR_OUT_NUMBER
+ `define CHDR_OUT_NUMBER 1
+`endif
+
+   reg [63:0] data_in[`CHDR_IN_NUMBER-1:0];
+   reg 	      last_in[`CHDR_IN_NUMBER-1:0];
+   reg 	      valid_in[`CHDR_IN_NUMBER-1:0];
+   wire       ready_in[`CHDR_IN_NUMBER-1:0];
+   wire [63:0] data_out[`CHDR_OUT_NUMBER-1:0];
+   wire 	      last_out[`CHDR_OUT_NUMBER-1:0];
+   wire 	      valid_out[`CHDR_OUT_NUMBER-1:0];
+   reg        ready_out[`CHDR_OUT_NUMBER-1:0];
+   //
+
+`include "../../../../../sim/radio_setting_regs.v"
+`include "../../../../../sim/task_library.v"
+
+   localparam DSPNO = 0;
+   localparam WIDTH = 24;
+   localparam NEW_HB_DECIM = 1;
+   localparam DEVICE = "SPARTAN6";
+
+   reg clk = 0;
+   reg reset;
+
+   reg set_stb;
+   reg [7:0] set_addr;
+   reg [31:0] set_data;
+
+   wire [WIDTH-1:0] rx_fe_i, rx_fe_q;
+   wire [31:0] 	    sample;
+   reg 		    run;
+   wire 	    strobe;
+
+   reg [11:0] 	    i_in, q_in;
+
+   assign rx_fe_i = {i_in,12'h0};
+   assign rx_fe_q = {q_in,12'h0};
+
+   //
+   // DUT
+   //
+   ddc_chain
+     #(
+     .BASE(SR_RX_DSP),
+     .DSPNO(DSPNO),
+     .WIDTH(WIDTH),
+     .NEW_HB_DECIM(NEW_HB_DECIM),
+     .DEVICE("SPARTAN6")
+       )
+   dut_i0 (
+     .clk(clk),
+     .rst(reset),
+     .clr(1'b0),
+     .set_stb(set_stb),
+     .set_addr(set_addr),
+     .set_data(set_data),
+
+     // From RX frontend
+     .rx_fe_i(rx_fe_i),
+     .rx_fe_q(rx_fe_q),
+
+     // To RX control
+     .sample(sample),
+     .run(run),
+     .strobe(strobe),
+     .debug()
+     );
+
+
+
+   //
+   // Include testbench
+   //
+`include "simulation_script.v"
+
+endmodule //
diff --git a/fpga/usrp3/lib/dsp/sim/sim_ddc_chain/run_isim b/fpga/usrp3/lib/dsp/sim/sim_ddc_chain/run_isim
new file mode 100755
index 000000000..4beb08ed3
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/sim/sim_ddc_chain/run_isim
@@ -0,0 +1,18 @@
+rm -rf fuse* *.exe isim
+vlogcomp -work work ${XILINX}/verilog/src/glbl.v
+vlogcomp -work work --sourcelibext .v \
+	 --sourcelibdir ../../.. \
+	  --sourcelibdir ../../../../control \
+	 --sourcelibdir ../../../../../top/b200/coregen_dsp \
+	 --sourcelibdir ../../../../../top/b200/coregen \
+	 --sourcelibdir ${XILINX}/verilog/src/unimacro \
+	 ../ddc_chain_tb.v
+
+
+
+fuse work.ddc_chain_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o testbench.exe
+
+# run the simulation script
+./testbench.exe #-gui   #-tclbatch simcmds.tcl 
+
+
diff --git a/fpga/usrp3/lib/dsp/small_hb_dec.v b/fpga/usrp3/lib/dsp/small_hb_dec.v
new file mode 100644
index 000000000..25a635bc1
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/small_hb_dec.v
@@ -0,0 +1,139 @@
+//
+// Copyright 2011 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+// NOTE: This module uses Xilinx IP that is not available in Spartan3 and older FPGA's
+
+// Short halfband decimator (intended to be followed by another stage)
+// Implements impulse responses of the form [A 0 B 0.5 B 0 A]
+//
+// These taps designed by halfgen4 from ldoolittle:
+//   2 * 131072 * halfgen4(.75/8,2)
+module small_hb_dec
+  #(parameter WIDTH=18,
+    parameter DEVICE = "SPARTAN6")
+    (input clk,
+     input rst,
+     input bypass,
+     input run,
+     input stb_in,
+     input [WIDTH-1:0] data_in,
+     output reg stb_out,
+     output reg [WIDTH-1:0] data_out);
+
+   // Round off inputs to 17 bits because of 18 bit multipliers
+   localparam INTWIDTH = 17;
+   wire [INTWIDTH-1:0] 	data_rnd;
+   wire 		stb_rnd;
+
+   round_sd #(.WIDTH_IN(WIDTH),.WIDTH_OUT(INTWIDTH)) round_in
+     (.clk(clk),.reset(rst),.in(data_in),.strobe_in(stb_in),.out(data_rnd),.strobe_out(stb_rnd));
+
+
+   reg 			stb_rnd_d1;
+   reg [INTWIDTH-1:0] 	data_rnd_d1;
+   always @(posedge clk) stb_rnd_d1 <= stb_rnd;
+   always @(posedge clk) data_rnd_d1 <= data_rnd;
+
+   wire 		go;
+   reg 			phase, go_d1, go_d2, go_d3, go_d4;
+   always @(posedge clk)
+     if(rst | ~run)
+       phase <= 0;
+     else if(stb_rnd_d1)
+       phase <= ~phase;
+   assign 		go = stb_rnd_d1 & phase;
+   always @(posedge clk)
+     if(rst | ~run)
+       begin
+	  go_d1 <= 0;
+	  go_d2 <= 0;
+	  go_d3 <= 0;
+	  go_d4 <= 0;
+       end
+     else
+       begin
+	  go_d1 <= go;
+	  go_d2 <= go_d1;
+	  go_d3 <= go_d2;
+	  go_d4 <= go_d3;
+       end
+
+   wire [17:0] 		coeff_a = -10690;
+   wire [17:0] 		coeff_b = 75809;
+
+   reg [INTWIDTH-1:0] 	d1, d2, d3, d4 , d5, d6;
+   always @(posedge clk)
+     if(stb_rnd_d1 | rst)
+       begin
+	  d1 <= data_rnd_d1;
+	  d2 <= d1;
+	  d3 <= d2;
+	  d4 <= d3;
+	  d5 <= d4;
+	  d6 <= d5;
+       end
+
+   reg [17:0] sum_a, sum_b, middle, middle_d1;
+
+   always @(posedge clk)
+     if(go)
+       begin
+	  sum_a <= {data_rnd_d1[INTWIDTH-1],data_rnd_d1} + {d6[INTWIDTH-1],d6};
+	  sum_b <= {d2[INTWIDTH-1],d2} + {d4[INTWIDTH-1],d4};
+	  //middle <= {d3[INTWIDTH-1],d3};
+	  middle <= {d3,1'b0};
+       end
+
+   always @(posedge clk)
+     if(go_d1)
+       middle_d1 <= middle;
+
+   wire [17:0] sum = go_d1 ? sum_b : sum_a;
+   wire [17:0] coeff = go_d1 ? coeff_b : coeff_a;
+   wire [35:0] 	 prod;
+
+    MULT_MACRO #(.DEVICE(DEVICE),  // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6","7SERIES"
+		.LATENCY(1),         // Desired clock cycle latency, 0-4
+		.WIDTH_A(18),        // Multiplier A-input bus width, 1-25
+		.WIDTH_B(18))        // Multiplier B-input bus width, 1-18
+      mult (.P(prod),     // Multiplier output bus, width determined by WIDTH_P parameter
+	       .A(coeff),     // Multiplier input A bus, width determined by WIDTH_A parameter
+	       .B(sum),                    // Multiplier input B bus, width determined by WIDTH_B parameter
+	       .CE(go_d1 | go_d2),   // 1-bit active high input clock enable
+	       .CLK(clk),              // 1-bit positive edge clock input
+	       .RST(rst));             // 1-bit input active high reset
+
+   localparam ACCWIDTH = 30;
+   reg [ACCWIDTH-1:0] 	 accum;
+
+   always @(posedge clk)
+     if(rst)
+       accum <= 0;
+     else if(go_d2)
+       accum <= {middle_d1[17],middle_d1[17],middle_d1,{(16+ACCWIDTH-36){1'b0}}} + {prod[35:36-ACCWIDTH]};
+     else if(go_d3)
+       accum <= accum + {prod[35:36-ACCWIDTH]};
+
+   wire [WIDTH:0] 	 accum_rnd;
+   wire [WIDTH-1:0] 	 accum_rnd_clip;
+
+   wire 	 stb_round;
+
+   round_sd #(.WIDTH_IN(ACCWIDTH),.WIDTH_OUT(WIDTH+1)) round_acc
+     (.clk(clk), .reset(rst), .in(accum), .strobe_in(go_d4), .out(accum_rnd), .strobe_out(stb_round));
+
+   clip #(.bits_in(WIDTH+1),.bits_out(WIDTH)) clip (.in(accum_rnd), .out(accum_rnd_clip));
+
+   // Output
+   always @(posedge clk)
+     begin
+	stb_out  <= bypass ? stb_in : stb_round;
+	data_out <= bypass ? data_in : accum_rnd_clip;
+     end
+
+
+endmodule // small_hb_dec
diff --git a/fpga/usrp3/lib/dsp/small_hb_int.v b/fpga/usrp3/lib/dsp/small_hb_int.v
new file mode 100644
index 000000000..e34b34eb5
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/small_hb_int.v
@@ -0,0 +1,102 @@
+//
+// Copyright 2011 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+// Short halfband decimator (intended to be followed by another stage)
+// Implements impulse responses of the form [A 0 B 0.5 B 0 A]
+//
+// These taps designed by halfgen4 from ldoolittle:
+//   2 * 131072 * halfgen4(.75/8,2)
+
+module small_hb_int
+  #(parameter WIDTH=18)
+    (input clk,
+     input rst,
+     input bypass,
+     input stb_in,
+     input [WIDTH-1:0] data_in,
+     input [7:0] output_rate,
+     input stb_out,
+     output reg [WIDTH-1:0] data_out);
+
+  
+   reg [WIDTH-1:0] d1, d2, d3, d4, d5, d6;
+
+   localparam 	   MWIDTH = 36;
+   wire [MWIDTH-1:0] prod;
+
+   reg [6:0] 	     stbin_d;
+   
+   always @(posedge clk)
+     stbin_d <= {stbin_d[5:0],stb_in};
+   
+   always @(posedge clk)
+     if (rst) 
+       begin
+	  d1 <= 0;
+	  d2 <= 0;
+	  d3 <= 0;
+	  d4 <= 0;
+	  d5 <= 0;
+	  d6 <= 0;
+       end
+     else if(stb_in)
+       begin
+	  d1 <= data_in;
+	  d2 <= d1;
+	  d3 <= d2;
+	  d4 <= d3;
+	  d5 <= d4;
+	  d6 <= d5;
+       end
+
+   wire [WIDTH-1:0] sum_outer, sum_inner;
+   add2_and_round_reg #(.WIDTH(WIDTH)) add_outer (.clk(clk),.in1(d1),.in2(d4),.sum(sum_outer));
+   add2_and_round_reg #(.WIDTH(WIDTH)) add_inner (.clk(clk),.in1(d2),.in2(d3),.sum(sum_inner));
+
+   wire [17:0] 	   coeff_outer = -10690;
+   wire [17:0] 	   coeff_inner = 75809;
+
+   MULT18X18S mult(.C(clk), .CE(1), .R(rst), .P(prod), .A(stbin_d[1] ? coeff_outer : coeff_inner), 
+		   .B(stbin_d[1] ? sum_outer : sum_inner) );
+
+   wire [MWIDTH:0] accum;
+   acc #(.IWIDTH(MWIDTH),.OWIDTH(MWIDTH+1)) 
+     acc (.clk(clk),.clear(stbin_d[2]),.acc(|stbin_d[3:2]),.in(prod),.out(accum));
+   
+   wire [WIDTH+2:0] 	 accum_rnd;
+   round_reg #(.bits_in(MWIDTH+1),.bits_out(WIDTH+3))
+     final_round (.clk(clk),.in(accum),.out(accum_rnd));
+
+   wire [WIDTH-1:0] 	 clipped;
+   clip_reg #(.bits_in(WIDTH+3),.bits_out(WIDTH)) final_clip
+     (.clk(clk),.in(accum_rnd),.strobe_in(1'b1), .out(clipped));
+
+   reg [WIDTH-1:0] 	 saved, saved_d3;
+   always @(posedge clk)
+     if(stbin_d[6])
+       saved <= clipped;
+
+   always @(posedge clk)
+     if(stbin_d[3])
+       saved_d3 <= d3;
+	   
+   always @(posedge clk)
+     if(bypass)
+       data_out <= data_in;
+     else if(stb_in & stb_out)
+       case(output_rate)
+	 1 : data_out <= d6; 
+	 2 : data_out <= d4;
+	 3, 4, 5, 6, 7 : data_out <= d3;
+	 default : data_out <= d2;
+       endcase // case(output_rate)
+     else if(stb_out)
+       data_out <= saved;
+
+endmodule // small_hb_int
+
diff --git a/fpga/usrp3/lib/dsp/srl.v b/fpga/usrp3/lib/dsp/srl.v
new file mode 100644
index 000000000..9bea98a09
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/srl.v
@@ -0,0 +1,30 @@
+//
+// Copyright 2011 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+
+module srl
+  #(parameter WIDTH=18)
+    (input clk,
+     input rst,
+     input write,
+     input [WIDTH-1:0] in,
+     input [3:0] addr,
+     output [WIDTH-1:0] out);
+   
+   genvar 		i;
+   generate
+      for (i=0;i<WIDTH;i=i+1)
+	begin : gen_srl
+	   SRL16E
+	     srl16e(.Q(out[i]),
+		    .A0(addr[0]),.A1(addr[1]),.A2(addr[2]),.A3(addr[3]),
+		    .CE(write|rst),.CLK(clk),.D(in[i]));
+	end
+   endgenerate
+
+endmodule // srl
diff --git a/fpga/usrp3/lib/dsp/tx_frontend.v b/fpga/usrp3/lib/dsp/tx_frontend.v
new file mode 100644
index 000000000..5484b80d4
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/tx_frontend.v
@@ -0,0 +1,108 @@
+//
+// Copyright 2014 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module tx_frontend
+  #(parameter BASE=0,
+    parameter WIDTH_OUT=16,
+    parameter IQCOMP_EN=1)
+   (input clk, input rst,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    input [23:0] tx_i, input [23:0] tx_q, input run,
+    output reg [WIDTH_OUT-1:0] dac_a, output reg [WIDTH_OUT-1:0] dac_b
+    );
+
+   // IQ balance --> DC offset --> rounding --> mux
+
+   wire [23:0] i_dco, q_dco, i_ofs, q_ofs;
+   wire [WIDTH_OUT-1:0] i_final, q_final;
+   wire [7:0]  mux_ctrl;
+   wire [35:0] corr_i, corr_q;
+   wire [23:0] i_bal, q_bal;
+   wire [17:0] mag_corr, phase_corr;
+   
+   setting_reg #(.my_addr(BASE+0), .width(24)) sr_0
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(i_dco),.changed());
+
+   setting_reg #(.my_addr(BASE+1), .width(24)) sr_1
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(q_dco),.changed());
+
+   setting_reg #(.my_addr(BASE+2),.width(18)) sr_2
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(mag_corr),.changed());
+   
+   setting_reg #(.my_addr(BASE+3),.width(18)) sr_3
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(phase_corr),.changed());
+  
+   setting_reg #(.my_addr(BASE+4), .width(8)) sr_4
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(mux_ctrl),.changed());
+
+   generate
+      if(IQCOMP_EN==1)
+	begin
+	   reg [23:0] tx_i_dly, tx_q_dly;
+	   always @(posedge clk) begin
+	     tx_i_dly <= tx_i;
+	     tx_q_dly <= tx_q;
+	   end
+
+	   // IQ Balance
+	   MULT18X18S mult_mag_corr
+	     (.P(corr_i), .A(tx_i[23:6]), .B(mag_corr), .C(clk), .CE(1), .R(rst) ); 
+	   
+	   MULT18X18S mult_phase_corr
+	     (.P(corr_q), .A(tx_i[23:6]), .B(phase_corr), .C(clk), .CE(1), .R(rst) );
+	   
+	   add2_and_clip_reg #(.WIDTH(24)) add_clip_i
+	     (.clk(clk), .rst(rst), 
+	      .in1(tx_i_dly), .in2(corr_i[35:12]), .strobe_in(1'b1),
+	      .sum(i_bal), .strobe_out());
+	   
+	   add2_and_clip_reg #(.WIDTH(24)) add_clip_q
+	     (.clk(clk), .rst(rst), 
+	      .in1(tx_q_dly), .in2(corr_q[35:12]), .strobe_in(1'b1),
+	      .sum(q_bal), .strobe_out());
+	end // if (IQCOMP_EN==1)
+      else
+	begin
+	   assign i_bal = tx_i;
+	   assign q_bal = tx_q;
+	end // else: !if(IQCOMP_EN==1)
+   endgenerate
+   
+   // DC Offset
+   add2_and_clip_reg #(.WIDTH(24)) add_dco_i
+     (.clk(clk), .rst(rst), .in1(i_dco), .in2(i_bal), .strobe_in(1'b1), .sum(i_ofs), .strobe_out());
+   
+   add2_and_clip_reg #(.WIDTH(24)) add_dco_q
+     (.clk(clk), .rst(rst), .in1(q_dco), .in2(q_bal), .strobe_in(1'b1), .sum(q_ofs), .strobe_out());
+   
+   // Rounding
+   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(WIDTH_OUT)) round_i
+     (.clk(clk), .reset(rst), .in(i_ofs),.strobe_in(1'b1), .out(i_final), .strobe_out());
+
+   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(WIDTH_OUT)) round_q
+     (.clk(clk), .reset(rst), .in(q_ofs),.strobe_in(1'b1), .out(q_final), .strobe_out());
+
+   // Mux
+   always @(posedge clk)
+     case(mux_ctrl[3:0])
+       0 : dac_a <= i_final;
+       1 : dac_a <= q_final;
+       default : dac_a <= 0;
+     endcase // case (mux_ctrl[3:0])
+      
+   always @(posedge clk)
+     case(mux_ctrl[7:4])
+       0 : dac_b <= i_final;
+       1 : dac_b <= q_final;
+       default : dac_b <= 0;
+     endcase // case (mux_ctrl[7:4])
+      
+endmodule // tx_frontend
diff --git a/fpga/usrp3/lib/dsp/variable_delay_line.v b/fpga/usrp3/lib/dsp/variable_delay_line.v
new file mode 100644
index 000000000..ccef6172f
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/variable_delay_line.v
@@ -0,0 +1,144 @@
+//
+// Copyright 2018 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: variable_delay_line
+// Description: 
+//   This module implements a variable length delay line. It can be used
+//   in filter implementation where the delay is either variable and/or
+//   longer than a few flip-flops
+//
+// Parameters:
+//   - WIDTH: Width of data_in and data_out
+//   - DYNAMIC_DELAY: Is the delay variable (configurable at runtime)
+//   - DEPTH: The depth of the delay line. Must be greater than 2.
+//            The output delay can be between 0 and DEPTH-1.
+//            If DYNAMIC_DELAY==0, then this is the static delay
+//   - DEFAULT_DATA: Data to output if time post-delay is negative 
+//   - OUT_REG: Add an output register. This adds a cycle of latency
+//   - DEVICE: FPGA device family
+// Signals:
+//   - data_in  : Input sample value
+//   - stb_in   : Is input sample valid?
+//   - delay    : Delay value for output (Must be between 0 and DEPTH-1)
+//   - data_out : Output sample value. data_out is updated 1 clock
+//                cycle (2 if OUT_REG == 1) after assertion of delay
+//
+
+module variable_delay_line #(
+  parameter             WIDTH         = 18,
+  parameter             DEPTH         = 256,
+  parameter             DYNAMIC_DELAY = 0,
+  parameter [WIDTH-1:0] DEFAULT_DATA  = 0,
+  parameter             OUT_REG       = 0,
+  parameter             DEVICE        = "7SERIES"
+) (
+  input  wire                     clk,
+  input  wire                     clk_en,
+  input  wire                     reset,
+  input  wire [WIDTH-1:0]         data_in,
+  input  wire                     stb_in,
+  input  wire [$clog2(DEPTH)-1:0] delay,
+  output wire [WIDTH-1:0]         data_out
+);
+   //FIXME: Change to localparam when Vivado doesn't freak out
+   //       about the use of clog2.
+  parameter  ADDR_W = $clog2(DEPTH+1);
+  localparam DATA_W = WIDTH;
+
+  //-----------------------------------------------------------
+  // RAM State Machine: FIFO write, random access read
+  //-----------------------------------------------------------
+  wire              w_en;
+  wire [DATA_W-1:0] r_data, w_data;
+  wire [ADDR_W-1:0] r_addr;
+  reg  [ADDR_W-1:0] w_addr = {ADDR_W{1'b0}}, occupied = {ADDR_W{1'b0}};
+  reg  [1:0]        use_default = 2'b11;
+
+  // FIFO write, random access read
+  always @(posedge clk) begin
+    if (reset) begin
+      w_addr <= {ADDR_W{1'b0}};
+      occupied <= {ADDR_W{1'b0}};
+    end else if (w_en) begin
+      w_addr <= w_addr + 1'b1;
+      if (occupied != DEPTH) begin
+        occupied <= occupied + 1'b1;
+      end
+    end
+  end
+
+  // Logic to handle negative delays
+  always @(posedge clk) begin
+    if (reset) begin
+      use_default <= 2'b11;
+    end else if (clk_en && (occupied != 0)) begin
+      use_default <= {use_default[0], (r_addr >= occupied ? 1'b1 : 1'b0)};
+    end
+  end
+
+  assign w_en     = stb_in & clk_en;
+  assign w_data   = data_in;
+  assign r_addr   = (DYNAMIC_DELAY == 0) ? DEPTH : delay;
+  assign data_out = use_default[OUT_REG] ? DEFAULT_DATA : r_data;
+
+  //-----------------------------------------------------------
+  // Delay Line RAM Implementation
+  //-----------------------------------------------------------
+  // Use a delay line implementation based on the depth. 
+  // The DEVICE parameter is passed in but SPARTAN6,
+  // 7Series, Ultrascale and Ultrascale+ have the same 
+  // MACROs for SRLs so we don't use the param quite yet.
+
+  genvar i;
+  generate
+    if (ADDR_W == 4 || ADDR_W == 5) begin
+      // SRLs don't have an output register to instantiate
+      // that plus the pipeline register manually
+      wire [DATA_W-1:0] r_data_srl;
+      reg  [DATA_W-1:0] r_data_shreg[0:1];
+      always @(posedge clk) begin
+        if (clk_en)
+          {r_data_shreg[1], r_data_shreg[0]} <= {r_data_shreg[0], r_data_srl};
+      end
+      assign r_data = r_data_shreg[OUT_REG];
+
+      for (i = 0; i < DATA_W; i = i + 1) begin: bits
+        // Pick SRL based on address width
+        if (ADDR_W == 4) begin
+          SRL16E #(
+            .INIT(16'h0000), .IS_CLK_INVERTED(1'b0)
+          ) srl16e_i (
+            .CLK(clk), .CE(w_en),
+            .D(w_data[i]),
+            .A0(r_addr[0]),.A1(r_addr[1]),.A2(r_addr[2]),.A3(r_addr[3]),
+            .Q(r_data_srl[i])
+          );
+        end else begin
+          SRLC32E #(
+            .INIT(32'h00000000), .IS_CLK_INVERTED(1'b0)
+          ) srlc32e_i (
+            .CLK(clk), .CE(w_en),
+            .D(w_data[i]),
+            .A(r_addr),
+            .Q(r_data_srl[i]), .Q31()
+         );
+        end
+      end
+    end else begin
+      // For ADDR_W < 4, the RAM should ideally get 
+      // synthesized down to flip-flops.
+      ram_2port #(
+        .DWIDTH (DATA_W), .AWIDTH(ADDR_W),
+        .RW_MODE("NO-CHANGE"), .OUT_REG(OUT_REG)
+      ) ram_i (
+        .clka (clk), .ena(clk_en), .wea(w_en),
+        .addra(w_addr), .dia(w_data), .doa(),
+        .clkb (clk), .enb(clk_en), .web(1'b0),
+        .addrb(w_addr - r_addr - 1), .dib(), .dob(r_data)
+      );
+    end
+  endgenerate
+
+endmodule // delay_line
\ No newline at end of file
diff --git a/fpga/usrp3/lib/extramfifo/.gitignore b/fpga/usrp3/lib/extramfifo/.gitignore
new file mode 100644
index 000000000..94bbf6dcc
--- /dev/null
+++ b/fpga/usrp3/lib/extramfifo/.gitignore
@@ -0,0 +1,3 @@
+fifo_extram36_tb
+fifo_extram_tb
+*.vcd
diff --git a/fpga/usrp3/lib/extramfifo/Makefile.srcs b/fpga/usrp3/lib/extramfifo/Makefile.srcs
new file mode 100644
index 000000000..c0f5e1097
--- /dev/null
+++ b/fpga/usrp3/lib/extramfifo/Makefile.srcs
@@ -0,0 +1,17 @@
+#
+# Copyright 2010 Ettus Research LLC
+# Copyright 2015 Ettus Research, a National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+#
+
+##################################################
+# Extram Sources
+##################################################
+EXTRAM_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/extramfifo/, \
+ext_fifo.v \
+nobl_if.v \
+nobl_fifo.v \
+refill_randomizer.v \
+))
diff --git a/fpga/usrp3/lib/extramfifo/ext_fifo.v b/fpga/usrp3/lib/extramfifo/ext_fifo.v
new file mode 100644
index 000000000..8ec32b45d
--- /dev/null
+++ b/fpga/usrp3/lib/extramfifo/ext_fifo.v
@@ -0,0 +1,166 @@
+//
+// Copyright 2011 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+//
+// FIFO backed by an off chip ZBT/NoBL SRAM.
+//
+// This module and its sub-hierarchy implment a FIFO capable of sustaining 
+// a data throughput rate of at least int_clk/2 * 36bits and bursts of int_clk * 36bits.
+//
+// This has been designed and tested for an int_clk of 100MHz and an ext_clk of 125MHz,
+// your milage may vary with other clock ratio's especially those where int_clk < ext_clk.
+// Testing has also exclusively used a rst signal synchronized to int_clk.
+//
+// Interface operation mimics a Xilinx FIFO configured as "First Word Fall Through",
+// though signal naming differs.
+//
+// For FPGA use registers interfacing directly with signals prefixed "RAM_*" should be 
+// packed into the IO ring.
+//
+
+module ext_fifo
+  #(parameter INT_WIDTH=36,EXT_WIDTH=18,RAM_DEPTH=19,FIFO_DEPTH=19)
+    (
+     input int_clk,
+     input ext_clk,
+     input rst,
+     input [EXT_WIDTH-1:0] RAM_D_pi,
+     output [EXT_WIDTH-1:0] RAM_D_po,
+     output RAM_D_poe,
+     output [RAM_DEPTH-1:0] RAM_A,
+     output RAM_WEn,
+     output RAM_CENn,
+     output RAM_LDn,
+     output RAM_OEn,
+     output RAM_CE1n,
+     input [INT_WIDTH-1:0] datain,
+     input src_rdy_i,                // WRITE
+     output dst_rdy_o,               // not FULL
+     output [INT_WIDTH-1:0] dataout,
+     output src_rdy_o,               // not EMPTY
+     input dst_rdy_i                  // READ
+     );
+
+   wire [EXT_WIDTH-1:0] write_data;
+   wire [EXT_WIDTH-1:0] read_data;
+   wire 		full1, empty1;
+   wire 		almost_full2, almost_full2_spread, full2, empty2;
+   wire [FIFO_DEPTH-1:0] capacity;
+   wire 		 space_avail;
+   wire 		 data_avail;
+		 
+   // These next 2 lines here purely because ICARUS is crap at handling generate statements.
+   // Empirically this has been determined to make simulations work.
+   wire 		 read_input_fifo = space_avail & ~empty1;
+   wire 		 write_output_fifo = data_avail;
+   
+   assign 		 src_rdy_o = ~empty2;
+   assign 		 dst_rdy_o = ~full1;
+
+   // External FIFO running at ext clock rate  and 18 or 36 bit width.
+   nobl_fifo  #(.WIDTH(EXT_WIDTH),.RAM_DEPTH(RAM_DEPTH),.FIFO_DEPTH(FIFO_DEPTH))
+     nobl_fifo_i1
+       (   
+	   .clk(ext_clk),
+	   .rst(rst),
+	   .RAM_D_pi(RAM_D_pi),
+	   .RAM_D_po(RAM_D_po),
+	   .RAM_D_poe(RAM_D_poe),
+	   .RAM_A(RAM_A),
+	   .RAM_WEn(RAM_WEn),
+	   .RAM_CENn(RAM_CENn),
+	   .RAM_LDn(RAM_LDn),
+	   .RAM_OEn(RAM_OEn),
+	   .RAM_CE1n(RAM_CE1n),
+	   .write_data(write_data),
+	   .write_strobe(~empty1 ),
+	   .space_avail(space_avail),
+	   .read_data(read_data),
+	   .read_strobe(~almost_full2_spread),
+	   .data_avail(data_avail),
+	   .capacity(capacity)
+	   );
+
+   generate
+      if (EXT_WIDTH == 18 && INT_WIDTH == 36) begin: fifo_g1
+	 // FIFO buffers data from UDP engine into external FIFO clock domain.
+	 fifo_xlnx_512x36_2clk_36to18 fifo_xlnx_512x36_2clk_36to18_i1 (
+								       .rst(rst),
+								       .wr_clk(int_clk),
+								       .rd_clk(ext_clk),
+								       .din(datain), // Bus [35 : 0] 
+								       .wr_en(src_rdy_i), 
+								       .rd_en(read_input_fifo),    		
+								       .dout(write_data), // Bus [17 : 0]
+								       .full(full1),			
+							               .empty(empty1));
+
+	 
+	 // FIFO buffers data read from external FIFO into DSP clk domain and to TX DSP.
+	 fifo_xlnx_512x36_2clk_18to36 fifo_xlnx_512x36_2clk_18to36_i1 (
+								       .rst(rst),
+								       .wr_clk(ext_clk),
+								       .rd_clk(int_clk),
+								       .din(read_data), // Bus [17 : 0]
+								       .wr_en(write_output_fifo),
+								       .rd_en(dst_rdy_i),
+								       .dout(dataout), // Bus [35 : 0]
+								       .full(full2),
+								       .prog_full(almost_full2),
+								       .empty(empty2));
+      end // block: fifo_g1
+      else if (EXT_WIDTH == 36 && INT_WIDTH == 36) begin: fifo_g1
+	 // FIFO buffers data from UDP engine into external FIFO clock domain.
+	 fifo_xlnx_32x36_2clk fifo_xlnx_32x36_2clk_i1 (
+						       .rst(rst),
+						       .wr_clk(int_clk),
+						       .rd_clk(ext_clk),
+						       .din(datain), // Bus [35 : 0] 
+						       .wr_en(src_rdy_i),
+						       .rd_en(read_input_fifo),
+						       .dout(write_data), // Bus [35 : 0] 
+						       .full(full1),
+						       .empty(empty1));
+	 
+	 // FIFO buffers data read from external FIFO into DSP clk domain and to TX DSP.
+	 fifo_xlnx_512x36_2clk_prog_full fifo_xlnx_32x36_2clk_prog_full_i1 (
+									    .rst(rst),
+									    .wr_clk(ext_clk),
+									    .rd_clk(int_clk),
+									    .din(read_data), // Bus [35 : 0] 
+									    .wr_en(write_output_fifo),
+									    .rd_en(dst_rdy_i),
+									    .dout(dataout), // Bus [35 : 0] 
+									    .full(full2),
+									    .empty(empty2),
+									    .prog_full(almost_full2));
+
+      end    
+   endgenerate
+
+   refill_randomizer #(.BITS(7))
+     refill_randomizer_i1 (
+			   .clk(ext_clk),
+			   .rst(rst),
+			   .full_in(almost_full2),
+			   .full_out(almost_full2_spread)
+			   );
+   
+endmodule // ext_fifo
diff --git a/fpga/usrp3/lib/extramfifo/ext_fifo_tb.v b/fpga/usrp3/lib/extramfifo/ext_fifo_tb.v
new file mode 100644
index 000000000..a4e5ea164
--- /dev/null
+++ b/fpga/usrp3/lib/extramfifo/ext_fifo_tb.v
@@ -0,0 +1,435 @@
+//
+// Copyright 2011 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+`timescale 1ns / 1ps
+`define USRP2
+//`define USRP2PLUS
+
+`ifdef USRP2
+ `define INT_WIDTH 36
+ `define EXT_WIDTH 18
+ `define RAM_DEPTH 19
+ `define FIFO_DEPTH 8
+ `define DUMP_VCD_FULL
+ `define INT_CLK_PERIOD 5
+ `define EXT_CLK_PERIOD 4
+`elsif USRP2PLUS
+ `define INT_WIDTH 36
+ `define EXT_WIDTH 36
+ `define RAM_DEPTH 18
+ `define FIFO_DEPTH 8
+ `define DUMP_VCD_FULL
+ `define INT_CLK_PERIOD 5
+ `define EXT_CLK_PERIOD 5
+`endif //  `ifdef USRP2
+   
+
+module ext_fifo_tb();
+  
+   reg int_clk;
+   reg ext_clk;
+   reg rst;
+
+   wire [`EXT_WIDTH-1:0] RAM_D_pi;
+   wire [`EXT_WIDTH-1:0] RAM_D_po;
+   wire [`EXT_WIDTH-1:0] RAM_D;
+   wire 		RAM_D_poe;
+   wire [`RAM_DEPTH-1:0] 	RAM_A;
+   wire 		RAM_WEn;
+   wire 		RAM_CENn;
+   wire 		RAM_LDn;
+   wire 		RAM_OEn;
+   wire 		RAM_CE1n;
+   reg [`INT_WIDTH-1:0] datain;
+   reg 			src_rdy_i;                // WRITE
+   wire 		dst_rdy_o;               // not FULL
+   wire [`INT_WIDTH-1:0] dataout;
+   reg [`INT_WIDTH-1:0]  ref_dataout;
+   wire 		src_rdy_o;               // not EMPTY
+   reg 			dst_rdy_i;
+   integer 		ether_frame;
+   
+   // Clocks
+   // Int clock is 100MHz
+   // Ext clock is 125MHz
+   initial 
+     begin
+	int_clk <= 0;
+	ext_clk <= 0;
+	ref_dataout <= 1;
+	src_rdy_i <= 0;
+	dst_rdy_i <= 0;
+     end
+
+   always
+     #(`INT_CLK_PERIOD/2) int_clk <= ~int_clk;
+
+   always
+     #(`EXT_CLK_PERIOD/2) ext_clk <= ~ext_clk;
+
+   initial
+     begin
+	datain <= 0;
+	ether_frame <= 0;
+	
+	rst <= 1;
+	repeat (5) @(negedge int_clk);
+	rst <= 0;
+	@(negedge int_clk);
+	while (datain < 10000)
+	  begin
+	     @(negedge int_clk);
+	     datain <= datain + dst_rdy_o;
+	     src_rdy_i <= dst_rdy_o;
+	     // Simulate inter-frame time	     
+	     if (ether_frame == 1500)
+	       begin
+		  ether_frame <= 0;
+		  repeat(1600)
+		    begin
+		       @(negedge int_clk);
+		       src_rdy_i <= 0;
+		    end
+	       end
+	     else
+	       ether_frame <= ether_frame + dst_rdy_o;
+	  end
+     end // initial begin
+
+   
+   initial
+     begin
+	repeat (5) @(negedge int_clk);
+	dst_rdy_i <= 1;
+
+	while (src_rdy_o !== 1)
+	  @(negedge int_clk);
+	  
+	// Fall through fifo, first output already valid
+	if (dataout !== ref_dataout)
+	  $display("Error: Expected %x, got %x @%d",ref_dataout, dataout, $time);
+	ref_dataout <= ref_dataout + src_rdy_o ;
+	
+	// Decimate by 16 rate
+	while (ref_dataout < 2000)
+	  begin
+	     @(negedge int_clk);
+	     ref_dataout <= ref_dataout + src_rdy_o ;
+	     dst_rdy_i <= src_rdy_o;
+	     if ((dataout !== ref_dataout) && src_rdy_o)
+	       $display("Error: Expected %x, got %x @%d",ref_dataout, dataout, $time);
+	     @(negedge int_clk);
+	     dst_rdy_i <= 0;
+	     repeat(14) @(negedge int_clk);
+	  end // while (ref_dataout < 10000)
+	// Decimate by 8 rate
+	while (ref_dataout < 4000)
+	  begin
+	     @(negedge int_clk);
+	     ref_dataout <= ref_dataout + src_rdy_o ;
+	     dst_rdy_i <= src_rdy_o;
+	     if ((dataout !== ref_dataout) && src_rdy_o)
+	       $display("Error: Expected %x, got %x @%d",ref_dataout, dataout, $time);
+	     @(negedge int_clk);
+	     dst_rdy_i <= 0;
+	     repeat(6) @(negedge int_clk);
+	  end // while (ref_dataout < 10000)
+	// Decimate by 4 rate
+	while (ref_dataout < 6000)
+	  begin
+	     @(negedge int_clk);
+	     ref_dataout <= ref_dataout + src_rdy_o ;
+	     dst_rdy_i <= src_rdy_o;
+	     if ((dataout !== ref_dataout) && src_rdy_o)
+	       $display("Error: Expected %x, got %x @%d",ref_dataout, dataout, $time);
+	     @(negedge int_clk);
+	     dst_rdy_i <= 0;
+	     repeat(2) @(negedge int_clk);
+	  end // while (ref_dataout < 10000)
+	// Max rate
+	while (ref_dataout < 10000)
+	  begin
+	     @(negedge int_clk);
+	     ref_dataout <= ref_dataout + src_rdy_o ;
+	     dst_rdy_i <= src_rdy_o;
+	     if ((dataout !== ref_dataout) && src_rdy_o)
+	       $display("Error: Expected %x, got %x @%d",ref_dataout, dataout, $time);
+	     
+	  end // while (ref_dataout < 10000)
+	
+	 @(negedge int_clk);
+	$finish;
+	
+     end
+   
+
+/* -----\/----- EXCLUDED -----\/-----
+ 
+   initial
+     begin
+	rst <= 1;
+	repeat (5) @(negedge int_clk);
+	rst <= 0;
+	@(negedge int_clk);
+	repeat (4000)
+	  begin
+	     @(negedge int_clk);
+	     datain <= datain + dst_rdy_o;
+	     src_rdy_i <= dst_rdy_o;
+//	     @(negedge int_clk);
+//	     src_rdy_i <= 0;
+//	     @(negedge int_clk);
+//	     dst_rdy_i <= src_rdy_o;
+//	     @(negedge int_clk);
+//	     dst_rdy_i <= 0;
+//	     repeat (2) @(negedge int_clk);
+	  end // repeat (1000)
+	// Fall through fifo, first output already valid
+	if (dataout !== ref_dataout)
+	  $display("Error: Expected %x, got %x",ref_dataout, dataout);
+	repeat (1000)
+	  begin
+	     @(negedge int_clk);
+	     datain <= datain + dst_rdy_o ;
+	     src_rdy_i <= dst_rdy_o;
+	     @(negedge int_clk);
+	     src_rdy_i <= 0;
+	     @(negedge int_clk);
+	     ref_dataout <= ref_dataout + src_rdy_o ;
+	     dst_rdy_i <= src_rdy_o;
+	     if ((dataout !== ref_dataout) && src_rdy_o)
+	       $display("Error: Expected %x, got %x",ref_dataout, dataout);
+	     @(negedge int_clk);
+	     dst_rdy_i <= 0;
+//	     repeat (2) @(negedge int_clk);
+	  end // repeat (1000)
+	repeat (1000)
+	  begin
+//	     @(negedge int_clk);
+//	     datain <= datain + 1;
+//	     src_rdy_i <= 1;
+//	     @(negedge int_clk);
+//	     src_rdy_i <= 0;
+	     @(negedge int_clk);
+	     ref_dataout <= ref_dataout + src_rdy_o;
+	     dst_rdy_i <= src_rdy_o;
+	     if ((dataout !== ref_dataout) && src_rdy_o)
+	       $display("Error: Expected %x, got %x",ref_dataout, dataout);
+	     @(negedge int_clk);
+	     dst_rdy_i <= 0;
+//	     repeat (2) @(negedge int_clk);
+	  end // repeat (1000)
+	
+	$finish;
+	
+     end // initial begin
+
+
+ -----/\----- EXCLUDED -----/\----- */
+   ///////////////////////////////////////////////////////////////////////////////////
+   // Simulation control                                                            //
+   ///////////////////////////////////////////////////////////////////////////////////
+   `ifdef DUMP_LX2_TOP
+   // Set up output files
+   initial begin
+      $dumpfile("ext_fifo_tb.lx2");
+      $dumpvars(1,ext_fifo_tb);
+   end
+   `endif
+
+   `ifdef DUMP_LX2_FULL
+   // Set up output files
+   initial begin
+      $dumpfile("ext_fifo_tb.lx2");
+      $dumpvars(0,ext_fifo_tb);
+   end
+   `endif
+
+   `ifdef DUMP_VCD_TOP
+   // Set up output files
+   initial begin
+      $dumpfile("ext_fifo_tb.vcd");
+      $dumpvars(1,ext_fifo_tb);
+   end
+   `endif
+
+   `ifdef DUMP_VCD_TOP_PLUS_NEXT
+   // Set up output files
+   initial begin
+      $dumpfile("ext_fifo_tb.vcd");
+      $dumpvars(2,ext_fifo_tb);
+   end
+   `endif
+
+   
+   `ifdef DUMP_VCD_FULL
+   // Set up output files
+   initial begin
+      $dumpfile("ext_fifo_tb.vcd");
+      $dumpvars(0,ext_fifo_tb);
+   end
+   `endif
+
+   // Update display every 10 us
+   always #10000 $monitor("Time in uS ",$time/1000);
+
+   wire [`EXT_WIDTH-1:0] RAM_D_pi_ext;
+   wire [`EXT_WIDTH-1:0] RAM_D_po_ext;
+   wire [`EXT_WIDTH-1:0] RAM_D_ext;
+   wire 		 RAM_D_poe_ext;
+   
+   genvar      i;
+
+   //
+   // Instantiate IO for Bidirectional bus to SRAM
+   //
+   
+   generate  
+      for (i=0;i<`EXT_WIDTH;i=i+1)
+        begin : gen_RAM_D_IO
+
+	   IOBUF #(
+		   .DRIVE(12),
+		   .IOSTANDARD("LVCMOS25"),
+		   .SLEW("FAST")
+		   )
+	     RAM_D_i (
+		      .O(RAM_D_pi_ext[i]),
+		      .I(RAM_D_po_ext[i]),
+		      .IO(RAM_D[i]),
+		      .T(RAM_D_poe_ext)
+		      );
+	end // block: gen_RAM_D_IO
+      
+   endgenerate
+
+   wire [`RAM_DEPTH-1:0] 	RAM_A_ext;
+   wire 		RAM_WEn_ext,RAM_LDn_ext,RAM_CE1n_ext,RAM_OEn_ext,RAM_CENn_ext;
+
+   assign 		#1 RAM_D_pi = RAM_D_pi_ext;
+   
+   assign 		#1 RAM_D_po_ext = RAM_D_po;
+
+   assign 		#1 RAM_D_poe_ext = RAM_D_poe;
+   
+   assign 		#2 RAM_WEn_ext = RAM_WEn;
+   
+   assign 		#2 RAM_LDn_ext = RAM_LDn;
+   
+   assign 		#2 RAM_CE1n_ext = RAM_CE1n;
+   
+   assign 		#2 RAM_OEn_ext = RAM_OEn;
+   
+   assign 		#2 RAM_CENn_ext = RAM_CENn;
+
+   assign 		#2 RAM_A_ext = RAM_A;
+   
+   
+   generate
+      if (`EXT_WIDTH==18) begin: ram_tb_g1
+	 idt71v65603s150  idt71v65603s150_i1
+	   (
+	    .A(RAM_A_ext[17:0]),
+	    .adv_ld_(RAM_LDn_ext),                  // advance (high) / load (low)
+	    .bw1_(1'b0), 
+	    .bw2_(1'b0),
+	    .bw3_(1'b1), 
+	    .bw4_(1'b1),   // byte write enables (low)
+	    .ce1_(RAM_CE1n_ext), 
+	    .ce2(1'b1), 
+	    .ce2_(1'b0),          // chip enables
+	    .cen_(RAM_CENn_ext),                     // clock enable (low)
+	    .clk(ext_clk),                      // clock
+	    .IO({RAM_D[16:9],RAM_D[7:0]}), 
+	    .IOP({RAM_D[17],RAM_D[8]}),                  // data bus
+	    .lbo_(1'b0),                     // linear burst order (low)
+	    .oe_(RAM_OEn_ext),                      // output enable (low)
+	    .r_w_(RAM_WEn_ext)
+	    );                    // read (high) / write (low)
+      end // block: ram_tb_g1
+      else if (`EXT_WIDTH==36) begin: ram_tb_g1
+	 idt71v65603s150  idt71v65603s150_i1
+	   (
+	    .A(RAM_A_ext[17:0]),
+	    .adv_ld_(RAM_LDn_ext),                  // advance (high) / load (low)
+	    .bw1_(1'b0), 
+	    .bw2_(1'b0),
+	    .bw3_(1'b0), 
+	    .bw4_(1'b0),   // byte write enables (low)
+	    .ce1_(RAM_CE1n_ext), 
+	    .ce2(1'b1), 
+	    .ce2_(1'b0),          // chip enables
+	    .cen_(RAM_CENn_ext),                     // clock enable (low)
+	    .clk(ext_clk),                      // clock
+	    .IO(RAM_D[31:0]), 
+	    .IOP(RAM_D[35:32]),                  // data bus
+	    .lbo_(1'b0),                     // linear burst order (low)
+	    .oe_(RAM_OEn_ext),                      // output enable (low)
+	    .r_w_(RAM_WEn_ext)
+	    );                    // read (high) / write (low)
+      end // block: ram_tb_g1
+ 
+   endgenerate
+   
+/* -----\/----- EXCLUDED -----\/-----
+
+	 
+   cy1356 cy1356_i1
+     ( .d(RAM_D),
+       .clk(ext_clk), 
+       .a(RAM_A_ext), 
+       .bws(2'b00), 
+       .we_b(RAM_WEn_ext), 
+       .adv_lb(RAM_LDn_ext), 
+       .ce1b(RAM_CE1n_ext), 
+       .ce2(1'b1), 
+       .ce3b(1'b0), 
+       .oeb(RAM_OEn_ext), 
+       .cenb(RAM_CENn_ext),
+       .mode(1'b0)
+       );
+ -----/\----- EXCLUDED -----/\----- */
+
+   
+   ext_fifo
+     #(.INT_WIDTH(`INT_WIDTH),.EXT_WIDTH(`EXT_WIDTH),.RAM_DEPTH(`RAM_DEPTH),.FIFO_DEPTH(`FIFO_DEPTH))
+       ext_fifo_i1
+	 (
+	  .int_clk(int_clk),
+	  .ext_clk(ext_clk),
+	  .rst(rst),
+	  .RAM_D_pi(RAM_D_pi),
+	  .RAM_D_po(RAM_D_po),
+	  .RAM_D_poe(RAM_D_poe),
+	  .RAM_A(RAM_A),
+	  .RAM_WEn(RAM_WEn),
+	  .RAM_CENn(RAM_CENn),
+	  .RAM_LDn(RAM_LDn),
+	  .RAM_OEn(RAM_OEn),
+	  .RAM_CE1n(RAM_CE1n),
+	  .datain(datain),
+	  .src_rdy_i(src_rdy_i),                // WRITE
+	  .dst_rdy_o(dst_rdy_o),               // not FULL
+	  .dataout(dataout),
+	  .src_rdy_o(src_rdy_o),               // not EMPTY
+	  .dst_rdy_i(dst_rdy_i)
+	  );
+
+endmodule // ext_fifo_tb
diff --git a/fpga/usrp3/lib/extramfifo/nobl_fifo.v b/fpga/usrp3/lib/extramfifo/nobl_fifo.v
new file mode 100644
index 000000000..e4fa1422e
--- /dev/null
+++ b/fpga/usrp3/lib/extramfifo/nobl_fifo.v
@@ -0,0 +1,117 @@
+//
+// Copyright 2011 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+// Since this FIFO uses a ZBT/NoBL SRAM for its storage which is a since port 
+// device it can only sustain data throughput at half the RAM clock rate.
+// Fair arbitration to ensure this occurs is included in this logic and
+// requests for transactions that can not be completed are held off.
+// This FIFO requires a an external signal driving read_strobe that assures space for at least 6
+// reads since this the theopretical maximum number in flight due to pipeling.
+
+module nobl_fifo
+  #(parameter WIDTH=18,RAM_DEPTH=19,FIFO_DEPTH=19)
+    (   
+	input clk,
+	input rst,
+	input [WIDTH-1:0] RAM_D_pi,
+	output [WIDTH-1:0] RAM_D_po,
+	output RAM_D_poe,
+	output [RAM_DEPTH-1:0] RAM_A,
+	output RAM_WEn,
+	output RAM_CENn,
+	output RAM_LDn,
+	output RAM_OEn,
+	output RAM_CE1n,
+	input [WIDTH-1:0] write_data,
+	input write_strobe,
+	output reg space_avail,
+	output  [WIDTH-1:0] read_data,
+	input read_strobe,                    // Triggers a read, result in approximately 6 cycles.
+	output  data_avail,                    // Qulaifys read data available this cycle on read_data.
+	output reg [FIFO_DEPTH-1:0] capacity
+	);
+
+   //reg [FIFO_DEPTH-1:0] capacity;
+   reg [FIFO_DEPTH-1:0] wr_pointer;
+   reg [FIFO_DEPTH-1:0] rd_pointer;
+   wire [RAM_DEPTH-1:0] address;
+   reg 			data_avail_int;  // Internal not empty flag.
+   
+   assign 	    read = read_strobe && data_avail_int;
+   assign 	    write = write_strobe && space_avail;
+
+   // When a read and write collision occur, supress the space_avail flag next cycle
+   // and complete write followed by read over 2 cycles. This forces balanced arbitration
+   // and makes for a simple logic design.
+
+   always @(posedge clk)
+     if (rst)
+       begin
+	  capacity <= (1 << FIFO_DEPTH) - 1;
+	  wr_pointer <= 0;
+	  rd_pointer <= 0;
+	  space_avail <= 1;
+	  data_avail_int <= 0;
+       end
+     else	  
+       begin
+	  // No space available if:
+	  // Capacity is already zero; Capacity is 1 and write is asserted (lookahead); both read and write are asserted (collision)
+	  space_avail <= ~((capacity == 0) || (read&&write) || ((capacity == 1) && write) );
+	  // Capacity has 1 cycle delay so look ahead here for corner case of read of last item in FIFO.
+	  data_avail_int <= ~((capacity == ((1 << FIFO_DEPTH)-1))  || ((capacity == ((1 << FIFO_DEPTH)-2)) && (~write && read))  );
+	  wr_pointer <= wr_pointer + write;
+	  rd_pointer <= rd_pointer + (~write && read); 
+	  capacity <= capacity - write + (~write && read) ;
+       end // else: !if(rst)
+
+   assign address = write ? wr_pointer : rd_pointer;
+   assign enable = write || read; 
+
+
+   //
+   // Simple NoBL SRAM interface, 4 cycle read latency.
+   // Read/Write arbitration via temprary application of empty/full flags.
+   //
+   nobl_if #(.WIDTH(WIDTH),.DEPTH(RAM_DEPTH))
+     nobl_if_i1
+       (
+	.clk(clk),
+	.rst(rst),
+	.RAM_D_pi(RAM_D_pi),
+	.RAM_D_po(RAM_D_po),
+	.RAM_D_poe(RAM_D_poe),
+	.RAM_A(RAM_A),
+	.RAM_WEn(RAM_WEn),
+	.RAM_CENn(RAM_CENn),
+	.RAM_LDn(RAM_LDn),
+	.RAM_OEn(RAM_OEn),
+	.RAM_CE1n(RAM_CE1n),
+	.address(address),
+	.data_out(write_data),
+	.data_in(read_data),
+	.data_in_valid(data_avail),
+	.write(write),
+	.enable(enable)
+	);
+
+   
+
+endmodule // nobl_fifo
diff --git a/fpga/usrp3/lib/extramfifo/nobl_if.v b/fpga/usrp3/lib/extramfifo/nobl_if.v
new file mode 100644
index 000000000..a0126bbe3
--- /dev/null
+++ b/fpga/usrp3/lib/extramfifo/nobl_if.v
@@ -0,0 +1,168 @@
+//
+// Copyright 2011 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+// Tested against an IDT 71v65603s150 in simulation and a Cypress 7C1356C in the real world.
+
+module nobl_if
+  #(parameter WIDTH=18,DEPTH=19)  
+    (
+     input clk,
+     input rst,
+     input [WIDTH-1:0] RAM_D_pi,
+     output [WIDTH-1:0] RAM_D_po,
+     output reg RAM_D_poe,
+     output [DEPTH-1:0] RAM_A,
+     output reg RAM_WEn,
+     output RAM_CENn,
+     output RAM_LDn,
+     output RAM_OEn,
+     output reg RAM_CE1n,
+     input [DEPTH-1:0] address,
+     input [WIDTH-1:0] data_out,
+     output reg [WIDTH-1:0] data_in,
+     output reg data_in_valid,
+     input write,
+     input enable
+     );
+   
+
+   reg 	   enable_pipe1;
+   reg [DEPTH-1:0] address_pipe1;
+   reg 		   write_pipe1;
+   reg [WIDTH-1:0] data_out_pipe1;
+   
+   reg 		   enable_pipe2;
+   reg 		   write_pipe2;
+   reg [WIDTH-1:0] data_out_pipe2;
+
+   reg 		   enable_pipe3;
+   reg 		   write_pipe3;
+   reg [WIDTH-1:0] data_out_pipe3;
+
+   assign 	   RAM_LDn = 0;
+   // ZBT/NoBL RAM actually manages its own output enables very well.
+   assign 	   RAM_OEn = 0;
+
+   // gray code the address to reduce EMI
+   wire [DEPTH-1:0] address_gray;
+   
+   bin2gray #(.WIDTH(DEPTH)) bin2gray (.bin(address),.gray(address_gray));
+   
+   
+   //
+   // Pipeline stage 1
+   //
+   always @(posedge clk)
+     if (rst)
+       begin
+	  enable_pipe1 <= 0;
+	  address_pipe1 <= 0;
+	  write_pipe1 <= 0;
+	  data_out_pipe1  <= 0;
+	  RAM_WEn <= 1;
+	  RAM_CE1n <= 1;
+	  
+       end
+     else
+       begin
+	  enable_pipe1 <= enable;
+	  RAM_CE1n <= ~enable;  // Creates IOB flop
+	  RAM_WEn <= ~write;  // Creates IOB flop
+	  
+	  if (enable)
+	    begin
+	       address_pipe1 <= address_gray;
+	       write_pipe1 <= write;
+//	       RAM_WEn <= ~write;  // Creates IOB flop
+	       
+	       
+	       if (write)
+		 data_out_pipe1 <= data_out;
+	    end
+       end // always @ (posedge clk)
+
+   // Pipeline 1 drives address, write_enable, chip_select on NoBL SRAM
+   assign RAM_A = address_pipe1;
+   assign RAM_CENn = 1'b0;
+ //  assign RAM_WEn = ~write_pipe1;
+//   assign RAM_CE1n = ~enable_pipe1;
+
+   //
+   // Pipeline stage2
+   //
+   always @(posedge clk)
+     if (rst)
+       begin
+	  enable_pipe2 <= 0;
+	  data_out_pipe2 <= 0;
+	  write_pipe2 <= 0;   
+       end
+     else
+       begin
+	  data_out_pipe2 <= data_out_pipe1;
+	  write_pipe2 <= write_pipe1;
+	  enable_pipe2 <= enable_pipe1;
+       end
+   
+   //
+   // Pipeline stage3
+   //
+   always @(posedge clk)
+     if (rst)
+       begin
+	  enable_pipe3 <= 0;
+	  data_out_pipe3 <= 0;
+	  write_pipe3 <= 0;
+	  RAM_D_poe <= 0;	  
+       end
+     else
+       begin
+	  data_out_pipe3 <= data_out_pipe2;
+	  write_pipe3 <= write_pipe2;
+	  enable_pipe3 <= enable_pipe2;
+	  RAM_D_poe <= ~(write_pipe2 & enable_pipe2); // Active low driver enable in Xilinx.	
+       end
+
+   // Pipeline 3 drives write data on NoBL SRAM
+   assign RAM_D_po = data_out_pipe3;
+   
+   
+   //
+   // Pipeline stage4
+   //
+   always @(posedge clk)
+     if (rst)
+       begin
+	  data_in_valid <= 0;
+	  data_in <= 0;
+       end
+     else
+       begin
+	  data_in <= RAM_D_pi;
+	  if (enable_pipe3 & ~write_pipe3)
+	    begin
+	       // Read data now available to be registered.
+	       data_in_valid <= 1'b1;
+	    end
+	  else
+	    data_in_valid <= 1'b0;
+       end // always @ (posedge clk)
+     
+endmodule // nobl_if
diff --git a/fpga/usrp3/lib/extramfifo/refill_randomizer.v b/fpga/usrp3/lib/extramfifo/refill_randomizer.v
new file mode 100644
index 000000000..f3208e983
--- /dev/null
+++ b/fpga/usrp3/lib/extramfifo/refill_randomizer.v
@@ -0,0 +1,86 @@
+//
+// Copyright 2011 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+//
+// EMI mitigation.
+// Process FULL flag from FIFO so that de-assertion
+// (FIFO now not FULL) is delayed by a pseudo random
+// value, but assertion is passed straight through.
+// 
+
+
+module refill_randomizer
+  #(parameter BITS=7)
+    (
+     input clk,
+     input rst,
+     input full_in,
+     output full_out
+     );
+   
+   wire 	    feedback;
+   reg 	    full_last;
+   wire     full_deasserts;
+   reg [6:0] shift_reg;
+   reg [6:0] count;
+   reg 	     delayed_fall;
+   
+
+   always @(posedge clk)
+     full_last <= full_in;
+   
+   assign    full_deasserts = full_last & ~full_in;
+
+   // 7 bit LFSR
+   always @(posedge clk)
+     if (rst)
+       shift_reg <= 7'b1;
+     else
+       if (full_deasserts)
+	 shift_reg <= {shift_reg[5:0],feedback};
+
+   assign    feedback = ^(shift_reg & 7'h41);
+
+   always @(posedge clk)
+     if (rst)
+       begin
+	  count <= 1;
+	  delayed_fall  <= 1;
+       end
+     else if (full_deasserts)
+       begin
+	  count <= shift_reg;
+	  delayed_fall <= 1;
+       end
+     else if (count == 1)
+       begin
+	  count <= 1;
+	  delayed_fall <= 0;
+       end
+     else
+       begin
+	  count <= count - 1;
+	  delayed_fall <= 1;
+       end
+   
+   // Full_out goes instantly high if full_in does. However its fall is delayed.
+   assign    full_out = (full_in == 1) || (full_last == 1) || delayed_fall;
+
+endmodule
\ No newline at end of file
diff --git a/fpga/usrp3/lib/extramfifo/test_sram_if.v b/fpga/usrp3/lib/extramfifo/test_sram_if.v
new file mode 100644
index 000000000..26b805804
--- /dev/null
+++ b/fpga/usrp3/lib/extramfifo/test_sram_if.v
@@ -0,0 +1,195 @@
+//
+// Copyright 2011 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+// Instantiate this block at the core level to conduct closed 
+// loop testing of the AC performance of the USRP2 SRAM interface
+
+
+`define WIDTH 18
+`define DEPTH 19
+
+module   test_sram_if
+  (
+   input clk,
+   input rst,
+   input [`WIDTH-1:0] RAM_D_pi,
+   output [`WIDTH-1:0] RAM_D_po,
+   output RAM_D_poe,
+   output [`DEPTH-1:0] RAM_A,
+   output RAM_WEn,
+   output RAM_CENn,
+   output RAM_LDn,
+   output RAM_OEn,
+   output RAM_CE1n,
+   output reg correct
+   );
+   
+   reg [`DEPTH-1:0] write_count;
+   reg [`DEPTH-1:0] read_count;
+   reg 		    enable;
+   reg 		    write;
+   reg 		    write_cycle;
+   reg 		    read_cycle;
+   reg 		    enable_reads;
+   reg [18:0] 	    address;
+   reg [17:0] 	    data_out;
+   wire [17:0] 	    data_in;
+   wire 	    data_in_valid;
+   
+   reg [17:0] 	    check_data;
+   reg [17:0] 	    check_data_old;
+   reg [17:0] 	    check_data_old2;
+    
+  //
+  // Create counter that generates both external modulo 2^19 address and modulo 2^18 data to test RAM.
+  //
+
+   always @(posedge clk)
+     if (rst)
+       begin
+	  write_count <= 19'h0;
+	  read_count <= 19'h0; 
+       end
+     else if (write_cycle) // Write cycle
+       if (write_count == 19'h7FFFF)
+	 begin
+	    write_count <= 19'h0;
+	 end
+       else
+	 begin
+	    write_count <= write_count + 1'b1;
+	 end
+     else if (read_cycle) // Read cycle
+       if (read_count == 19'h7FFFF)
+	 begin
+	    read_count <= 19'h0;
+	 end
+       else
+	 begin
+	    read_count <= read_count + 1'b1;
+	 end
+   
+   always @(posedge clk)
+     if (rst)
+       begin
+	  enable_reads <= 0;
+	  read_cycle <= 0;
+	  write_cycle <= 0;
+       end
+     else
+       begin
+	  write_cycle <= ~write_cycle;
+	  if (enable_reads)
+	    read_cycle <= write_cycle;
+	  if (write_count == 15) // Enable reads 15 writes after reset terminates.
+	    enable_reads <= 1;
+       end // else: !if(rst)
+   
+   always @(posedge clk)
+     if (rst)
+       begin
+	  enable <= 0;
+       end
+     else if (write_cycle)
+       begin
+	  address <= write_count;
+	  data_out <= write_count[17:0];
+	  enable <= 1;
+	  write <= 1;
+       end
+     else if (read_cycle)
+       begin
+	  address <= read_count;
+	  check_data <= read_count[17:0];
+	  check_data_old <= check_data;
+	  check_data_old2 <= check_data_old;
+	  enable <= 1;
+	  write <= 0;
+       end
+     else
+       enable <= 0;
+
+   always @(posedge clk)
+     if (data_in_valid)
+       begin
+	  correct <= (data_in == check_data_old2);
+       end
+	  
+    
+   nobl_if nobl_if_i1
+     (
+      .clk(clk),
+      .rst(rst),
+      .RAM_D_pi(RAM_D_pi),
+      .RAM_D_po(RAM_D_po),
+      .RAM_D_poe(RAM_D_poe),
+      .RAM_A(RAM_A),
+      .RAM_WEn(RAM_WEn),
+      .RAM_CENn(RAM_CENn),
+      .RAM_LDn(RAM_LDn),
+      .RAM_OEn(RAM_OEn),
+      .RAM_CE1n(RAM_CE1n),
+      .address(address),
+      .data_out(data_out),
+      .data_in(data_in),
+      .data_in_valid(data_in_valid),
+      .write(write),
+      .enable(enable)
+      );
+
+
+   wire [35:0] CONTROL0;
+   reg [7:0]   data_in_reg, data_out_reg, address_reg;
+   reg 	       data_in_valid_reg,write_reg,enable_reg,correct_reg;
+
+   always @(posedge clk)
+     begin
+	data_in_reg <= data_in[7:0];
+	data_out_reg <= data_out[7:0];
+	data_in_valid_reg <= data_in_valid;
+	write_reg <= write;
+	enable_reg <= enable;
+	correct_reg <= correct;
+	address_reg <= address;
+	
+     end
+   
+   
+   icon icon_i1
+     (
+      .CONTROL0(CONTROL0)
+      );
+   
+   ila ila_i1
+     (    
+	  .CLK(clk), 
+	  .CONTROL(CONTROL0), 
+	  //    .TRIG0(address_reg), 
+	  .TRIG0(data_in_reg[7:0]), 
+	  .TRIG1(data_out_reg[7:0]),
+	  .TRIG2(address_reg[7:0]),
+	  .TRIG3({data_in_valid_reg,write_reg,enable_reg,correct_reg})
+	  );
+ 
+
+   
+endmodule // test_sram_if
+
+   
\ No newline at end of file
diff --git a/fpga/usrp3/lib/fifo/Makefile.srcs b/fpga/usrp3/lib/fifo/Makefile.srcs
new file mode 100644
index 000000000..8b48f6586
--- /dev/null
+++ b/fpga/usrp3/lib/fifo/Makefile.srcs
@@ -0,0 +1,37 @@
+#
+# Copyright 2012-2013 Ettus Research LLC
+# Copyright 2016 Ettus Research, a National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+##################################################
+# FIFO Sources
+##################################################
+FIFO_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/fifo/, \
+axi_demux4.v \
+axi_demux8.v \
+axi_demux.v \
+axi_fifo_2clk.v \
+axi_fifo32_to_fifo64.v \
+axi_fifo64_to_fifo32.v \
+axi_fifo32_to_fifo16.v \
+axi_fifo16_to_fifo32.v \
+axi_fifo_bram.v \
+axi_fifo_cascade.v \
+axi_fifo_flop2.v \
+axi_fifo_flop.v \
+axi_fifo_short.v \
+axi_fifo.v \
+axi_filter_mux4.v \
+axi_loopback.v \
+axi_mux4.v \
+axi_mux8.v \
+axi_mux_select.v \
+axi_mux.v \
+axi_packet_gate.v \
+fifo64_to_axi4lite.v \
+shortfifo.v \
+axis_fifo_monitor.v \
+axis_strm_monitor.v \
+))
diff --git a/fpga/usrp3/lib/fifo/axi_demux.v b/fpga/usrp3/lib/fifo/axi_demux.v
new file mode 100644
index 000000000..965fb95f0
--- /dev/null
+++ b/fpga/usrp3/lib/fifo/axi_demux.v
@@ -0,0 +1,75 @@
+
+// Copyright 2012 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// axi_demux -- takes 1 AXI stream, demuxes to up to 16 output streams
+//  One bubble cycle between each packet
+
+module axi_demux
+  #(parameter WIDTH=64,
+    parameter SIZE=4,
+    parameter PRE_FIFO_SIZE=0,
+    parameter POST_FIFO_SIZE=0)
+   (input clk, input reset, input clear,
+    output [WIDTH-1:0] header, input [$clog2(SIZE)-1:0] dest,
+    input [WIDTH-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
+    output [(WIDTH*SIZE)-1:0] o_tdata, output [SIZE-1:0] o_tlast, output [SIZE-1:0] o_tvalid, input [SIZE-1:0] o_tready);
+
+   wire i_tlast_int, i_tready_int, i_tvalid_int;
+   wire [WIDTH-1:0] i_tdata_int;
+   generate
+     if (PRE_FIFO_SIZE == 0) begin
+       assign i_tlast_int = i_tlast;
+       assign i_tdata_int = i_tdata;
+       assign i_tvalid_int = i_tvalid;
+       assign i_tready = i_tready_int;
+     end else begin
+       axi_fifo #(.WIDTH(WIDTH+1),.SIZE(PRE_FIFO_SIZE)) axi_fifo (
+         .clk(clk), .reset(reset), .clear(clear),
+         .i_tdata({i_tlast,i_tdata}), .i_tvalid(i_tvalid), .i_tready(i_tready),
+         .o_tdata({i_tlast_int,i_tdata_int}), .o_tvalid(i_tvalid_int), .o_tready(i_tready_int),
+         .space(), .occupied());
+     end
+   endgenerate
+
+   reg [SIZE-1:0] 	      st;
+
+   assign header = i_tdata_int;
+
+   always @(posedge clk)
+     if(reset | clear)
+       st <= {SIZE{1'b0}};
+     else
+       if(st == 0)
+	 if(i_tvalid_int)
+	   st[dest] <= 1'b1;
+	 else
+	   ;
+       else
+	 if(i_tready_int & i_tvalid_int & i_tlast_int)
+	   st <= {SIZE{1'b0}};
+   
+   wire [SIZE-1:0]  o_tlast_int, o_tready_int, o_tvalid_int;
+   wire [WIDTH-1:0] o_tdata_int[0:SIZE-1];
+   genvar n;
+   generate
+     if (POST_FIFO_SIZE == 0) begin
+       assign o_tdata = {SIZE{i_tdata_int}};
+       assign o_tlast = {SIZE{i_tlast_int}};
+       assign o_tvalid = {SIZE{i_tvalid_int}} & st;
+       assign i_tready_int = |(o_tready & st);
+     end else begin
+       wire [SIZE-1:0] o_tready_fifo;
+       assign i_tready_int = |(o_tready_fifo & st);
+       for (n = 0; n < SIZE; n = n + 1) begin
+         axi_fifo #(.WIDTH(WIDTH+1),.SIZE(POST_FIFO_SIZE)) axi_fifo (
+           .clk(clk), .reset(reset), .clear(clear),
+           .i_tdata({i_tlast_int,i_tdata_int}), .i_tvalid(i_tvalid_int & st[n]), .i_tready(o_tready_fifo[n]),
+           .o_tdata({o_tlast[n],o_tdata[WIDTH*(n+1)-1:WIDTH*n]}), .o_tvalid(o_tvalid[n]), .o_tready(o_tready[n]),
+           .space(), .occupied());
+       end
+     end
+   endgenerate
+
+endmodule // axi_demux
diff --git a/fpga/usrp3/lib/fifo/axi_demux4.v b/fpga/usrp3/lib/fifo/axi_demux4.v
new file mode 100644
index 000000000..09f017dd1
--- /dev/null
+++ b/fpga/usrp3/lib/fifo/axi_demux4.v
@@ -0,0 +1,80 @@
+
+// Copyright 2012 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// axi_demux -- takes one AXI stream, sends to one of 4 output channels
+//   Choice of output channel is by external logic based on first line of packet ("header" port)
+//   If compressed vita data, this line contains vita header and streamid.
+
+module axi_demux4
+  #(parameter ACTIVE_CHAN = 4'b1111,  // ACTIVE_CHAN is a map of connected outputs
+    parameter WIDTH = 64,
+    parameter BUFFER=0)
+   (input clk, input reset, input clear,
+    output [WIDTH-1:0] header, input [1:0] dest,
+    input [WIDTH-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
+    output [WIDTH-1:0] o0_tdata, output o0_tlast, output o0_tvalid, input o0_tready,
+    output [WIDTH-1:0] o1_tdata, output o1_tlast, output o1_tvalid, input o1_tready,
+    output [WIDTH-1:0] o2_tdata, output o2_tlast, output o2_tvalid, input o2_tready,
+    output [WIDTH-1:0] o3_tdata, output o3_tlast, output o3_tvalid, input o3_tready);
+
+   wire [WIDTH-1:0]    i_tdata_int;
+   wire 	       i_tlast_int, i_tvalid_int, i_tready_int;
+
+   generate
+      if(BUFFER == 0)
+	begin
+	   assign i_tdata_int = i_tdata;
+	   assign i_tlast_int = i_tlast;
+	   assign i_tvalid_int = i_tvalid;
+	   assign i_tready = i_tready_int;
+	end
+      else
+	axi_fifo_flop2 #(.WIDTH(WIDTH+1)) axi_fifo_flop2
+	  (.clk(clk), .reset(reset), .clear(clear),
+	   .i_tdata({i_tlast,i_tdata}), .i_tvalid(i_tvalid), .i_tready(i_tready),
+	   .o_tdata({i_tlast_int,i_tdata_int}), .o_tvalid(i_tvalid_int), .o_tready(i_tready_int),
+	   .space(), .occupied());
+   endgenerate
+
+   reg [3:0] 	  dm_state;
+   localparam DM_IDLE = 4'b0000;
+   localparam DM_0    = 4'b0001;
+   localparam DM_1    = 4'b0010;
+   localparam DM_2    = 4'b0100;
+   localparam DM_3    = 4'b1000;
+
+   assign header = i_tdata_int;
+   
+   always @(posedge clk)
+     if(reset | clear)
+       dm_state <= DM_IDLE;
+     else
+       case (dm_state)
+	 DM_IDLE :
+	   if(i_tvalid_int)
+	     case(dest)
+	       2'b00 : dm_state <= DM_0;
+	       2'b01 : dm_state <= DM_1;
+	       2'b10 : dm_state <= DM_2;
+	       2'b11 : dm_state <= DM_3;
+	     endcase // case (i_tdata[1:0])
+	 
+	 DM_0, DM_1, DM_2, DM_3 :
+	   if(i_tvalid_int & i_tready_int & i_tlast_int)
+	     dm_state <= DM_IDLE;
+	 
+	 default :
+	   dm_state <= DM_IDLE;
+       endcase // case (dm_state)
+
+   assign {o3_tvalid, o2_tvalid, o1_tvalid, o0_tvalid} = dm_state & {4{i_tvalid_int}};
+   assign i_tready_int = |(dm_state & ({o3_tready, o2_tready, o1_tready, o0_tready} | ~ACTIVE_CHAN));
+      
+   assign {o0_tlast, o0_tdata} = {i_tlast_int, i_tdata_int};
+   assign {o1_tlast, o1_tdata} = {i_tlast_int, i_tdata_int};
+   assign {o2_tlast, o2_tdata} = {i_tlast_int, i_tdata_int};
+   assign {o3_tlast, o3_tdata} = {i_tlast_int, i_tdata_int};
+   
+endmodule // axi_demux4
diff --git a/fpga/usrp3/lib/fifo/axi_demux8.v b/fpga/usrp3/lib/fifo/axi_demux8.v
new file mode 100644
index 000000000..2ee18040b
--- /dev/null
+++ b/fpga/usrp3/lib/fifo/axi_demux8.v
@@ -0,0 +1,63 @@
+
+// Copyright 2012 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// axi_demux -- takes one AXI stream, sends to one of 8 output channels
+//   Choice of output channel is by external logic based on first line of packet ("header" port)
+//   If compressed vita data, this line contains vita header and streamid.
+
+module axi_demux8 #(
+   parameter ACTIVE_CHAN = 8'b11111111,  // ACTIVE_CHAN is a map of connected outputs
+   parameter WIDTH = 64,
+   parameter BUFFER=0
+) (
+   input clk, input reset, input clear,
+   output [WIDTH-1:0] header, input [2:0] dest,
+   input [WIDTH-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
+   output [WIDTH-1:0] o0_tdata, output o0_tlast, output o0_tvalid, input o0_tready,
+   output [WIDTH-1:0] o1_tdata, output o1_tlast, output o1_tvalid, input o1_tready,
+   output [WIDTH-1:0] o2_tdata, output o2_tlast, output o2_tvalid, input o2_tready,
+   output [WIDTH-1:0] o3_tdata, output o3_tlast, output o3_tvalid, input o3_tready,
+   output [WIDTH-1:0] o4_tdata, output o4_tlast, output o4_tvalid, input o4_tready,
+   output [WIDTH-1:0] o5_tdata, output o5_tlast, output o5_tvalid, input o5_tready,
+   output [WIDTH-1:0] o6_tdata, output o6_tlast, output o6_tvalid, input o6_tready,
+   output [WIDTH-1:0] o7_tdata, output o7_tlast, output o7_tvalid, input o7_tready
+);
+
+   wire [WIDTH-1:0]  i_tdata_int0, i_tdata_int1;
+   wire              i_tlast_int0, i_tlast_int1;
+   wire              i_tvalid_int0, i_tvalid_int1;
+   wire              i_tready_int0, i_tready_int1;
+
+   axi_demux4 #(.ACTIVE_CHAN({2'b00, (|(ACTIVE_CHAN[7:4])), (|(ACTIVE_CHAN[3:0]))}), .WIDTH(WIDTH), .BUFFER(BUFFER)) demux2 (
+      .clk(clk), .reset(reset), .clear(clear),
+      .header(header), .dest({1'b0, dest[2]}),
+      .i_tdata(i_tdata), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready),
+      .o0_tdata(i_tdata_int0), .o0_tlast(i_tlast_int0), .o0_tvalid(i_tvalid_int0), .o0_tready(i_tready_int0),
+      .o1_tdata(i_tdata_int1), .o1_tlast(i_tlast_int1), .o1_tvalid(i_tvalid_int1), .o1_tready(i_tready_int1),
+      .o2_tdata(), .o2_tlast(), .o2_tvalid(), .o2_tready(1'b0),
+      .o3_tdata(), .o3_tlast(), .o3_tvalid(), .o3_tready(1'b0)
+   );
+
+   axi_demux4 #(.ACTIVE_CHAN(ACTIVE_CHAN[3:0]), .WIDTH(WIDTH), .BUFFER(0)) demux4_int0 (
+      .clk(clk), .reset(reset), .clear(clear),
+      .header(), .dest(dest[1:0]),
+      .i_tdata(i_tdata_int0), .i_tlast(i_tlast_int0), .i_tvalid(i_tvalid_int0), .i_tready(i_tready_int0),
+      .o0_tdata(o0_tdata), .o0_tlast(o0_tlast), .o0_tvalid(o0_tvalid), .o0_tready(o0_tready),
+      .o1_tdata(o1_tdata), .o1_tlast(o1_tlast), .o1_tvalid(o1_tvalid), .o1_tready(o1_tready),
+      .o2_tdata(o2_tdata), .o2_tlast(o2_tlast), .o2_tvalid(o2_tvalid), .o2_tready(o2_tready),
+      .o3_tdata(o3_tdata), .o3_tlast(o3_tlast), .o3_tvalid(o3_tvalid), .o3_tready(o3_tready)
+   );
+
+   axi_demux4 #(.ACTIVE_CHAN(ACTIVE_CHAN[7:4]), .WIDTH(WIDTH), .BUFFER(0)) demux4_int1 (
+      .clk(clk), .reset(reset), .clear(clear),
+      .header(), .dest(dest[1:0]),
+      .i_tdata(i_tdata_int1), .i_tlast(i_tlast_int1), .i_tvalid(i_tvalid_int1), .i_tready(i_tready_int1),
+      .o0_tdata(o4_tdata), .o0_tlast(o4_tlast), .o0_tvalid(o4_tvalid), .o0_tready(o4_tready),
+      .o1_tdata(o5_tdata), .o1_tlast(o5_tlast), .o1_tvalid(o5_tvalid), .o1_tready(o5_tready),
+      .o2_tdata(o6_tdata), .o2_tlast(o6_tlast), .o2_tvalid(o6_tvalid), .o2_tready(o6_tready),
+      .o3_tdata(o7_tdata), .o3_tlast(o7_tlast), .o3_tvalid(o7_tvalid), .o3_tready(o7_tready)
+   );
+   
+endmodule // axi_demux4
diff --git a/fpga/usrp3/lib/fifo/axi_fifo.v b/fpga/usrp3/lib/fifo/axi_fifo.v
new file mode 100644
index 000000000..3a99c4c31
--- /dev/null
+++ b/fpga/usrp3/lib/fifo/axi_fifo.v
@@ -0,0 +1,71 @@
+//
+// Copyright 2012-2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+// General FIFO block
+//  Size == 0: Uses a single stage flop (axi_fifo_flop).
+//  Size == 1: Uses a two stage flop (axi_fifo_flop2). Best choice for single stage pipelining.
+//             Breaks combinatorial paths on the AXI stream data / control lines at the cost of
+//             additional registers. Maps to SLICELs (i.e. does not use distributed RAM).
+//  Size <= 5: Uses SRL32 to efficient maps a 32 deep FIFO to SLICEMs (axi_fifo_short). Not
+//             recommended for pipelining as most devices have twice as many SLICELs as SLICEMs.
+//  Size  > 5: Uses BRAM fifo (axi_fifo_bram)
+
+module axi_fifo
+  #(parameter WIDTH=32, SIZE=5)
+   (input clk, input reset, input clear,
+    input [WIDTH-1:0] i_tdata,
+    input i_tvalid,
+    output i_tready,
+    output [WIDTH-1:0] o_tdata,
+    output o_tvalid,
+    input o_tready,
+    
+    output [15:0] space,
+    output [15:0] occupied);
+   
+   generate
+   if(SIZE==0)
+   begin
+      axi_fifo_flop #(.WIDTH(WIDTH)) fifo_flop
+        (.clk(clk), .reset(reset), .clear(clear),
+         .i_tdata(i_tdata), .i_tvalid(i_tvalid), .i_tready(i_tready),
+         .o_tdata(o_tdata), .o_tvalid(o_tvalid), .o_tready(o_tready),
+         .space(space[0]), .occupied(occupied[0]));
+      assign space[15:1] = 15'd0;
+      assign occupied[15:1] = 15'd0;
+   end
+   else if(SIZE==1)
+   begin
+      axi_fifo_flop2 #(.WIDTH(WIDTH)) fifo_flop2
+        (.clk(clk), .reset(reset), .clear(clear),
+         .i_tdata(i_tdata), .i_tvalid(i_tvalid), .i_tready(i_tready),
+         .o_tdata(o_tdata), .o_tvalid(o_tvalid), .o_tready(o_tready),
+         .space(space[1:0]), .occupied(occupied[1:0]));
+      assign space[15:2] = 14'd0;
+      assign occupied[15:2] = 14'd0;
+   end
+   else if(SIZE<=5)
+   begin
+      axi_fifo_short #(.WIDTH(WIDTH)) fifo_short
+        (.clk(clk), .reset(reset), .clear(clear),
+         .i_tdata(i_tdata), .i_tvalid(i_tvalid), .i_tready(i_tready),
+         .o_tdata(o_tdata), .o_tvalid(o_tvalid), .o_tready(o_tready),
+         .space(space[5:0]), .occupied(occupied[5:0]));
+      assign space[15:6] = 10'd0;
+      assign occupied[15:6] = 10'd0;
+   end
+   else
+   begin
+      axi_fifo_bram #(.WIDTH(WIDTH), .SIZE(SIZE)) fifo_bram
+        (.clk(clk), .reset(reset), .clear(clear),
+         .i_tdata(i_tdata), .i_tvalid(i_tvalid), .i_tready(i_tready),
+         .o_tdata(o_tdata), .o_tvalid(o_tvalid), .o_tready(o_tready),
+         .space(space), .occupied(occupied));
+   end
+   endgenerate
+      
+endmodule // axi_fifo
diff --git a/fpga/usrp3/lib/fifo/axi_fifo16_to_fifo32.v b/fpga/usrp3/lib/fifo/axi_fifo16_to_fifo32.v
new file mode 100644
index 000000000..d22c825c5
--- /dev/null
+++ b/fpga/usrp3/lib/fifo/axi_fifo16_to_fifo32.v
@@ -0,0 +1,43 @@
+//
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module axi_fifo16_to_fifo32
+  (input clk, input reset, input clear,
+   input [15:0] i_tdata, input [1:0] i_tuser, input i_tlast, input i_tvalid, output i_tready,
+   output [31:0] o_tdata, output [2:0] o_tuser, output o_tlast, output o_tvalid, input o_tready
+   );
+
+   reg [15:0] 	 holding;
+
+   reg 		 state;
+
+   always @(posedge clk)
+     if(reset | clear)
+       state <= 0;
+     else
+       if(i_tvalid & i_tready)
+       case(state)
+	 0 : if(~i_tlast) state <= 1'b1;
+    	 1 : state <= 1'b0;
+	 default : state <= 1'b0;
+       endcase // case (state)
+
+   always @(posedge clk)
+     if(i_tvalid & i_tready)
+       holding <= i_tdata;
+   
+   assign i_tready = (state == 0 && !i_tlast)? 1'b1 : o_tready;
+   assign o_tvalid = (state == 0 && !i_tlast)? 1'b0 : i_tvalid;
+   
+   assign o_tdata = (state == 0) ? {i_tdata, 16'h0} : { holding, i_tdata };
+   assign o_tlast = i_tlast;
+
+   wire [2:0] 	 occ_in = (i_tuser == 0) ? 3'd4 : {1'b0, i_tuser};
+   wire [2:0] 	 occ_out = (state == 0) ? occ_in : (occ_in + 3'd4);
+   
+   assign o_tuser = ~o_tlast ? 3'd0 : occ_out;
+   	 
+endmodule // axi_fifo32_to_fifo64
diff --git a/fpga/usrp3/lib/fifo/axi_fifo32_to_fifo16.v b/fpga/usrp3/lib/fifo/axi_fifo32_to_fifo16.v
new file mode 100644
index 000000000..b4e7ec618
--- /dev/null
+++ b/fpga/usrp3/lib/fifo/axi_fifo32_to_fifo16.v
@@ -0,0 +1,36 @@
+//
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module axi_fifo32_to_fifo16
+  (input clk, input reset, input clear,
+   input [31:0] i_tdata, input [2:0] i_tuser, input i_tlast, input i_tvalid, output i_tready,
+   output [15:0] o_tdata, output [1:0] o_tuser, output o_tlast, output o_tvalid, input o_tready
+   );
+
+   wire 	 short_last = i_tlast & ((i_tuser == 3'd1) | (i_tuser == 3'd2) | (i_tuser == 3'd3) | (i_tuser == 3'd4));
+   
+   reg 		 state;
+   always @(posedge clk)
+     if(reset | clear)
+       state <= 1'b0;
+     else
+       if(i_tvalid & o_tready)
+	 case(state)
+	   1'b0 :
+	     if(~short_last)
+	       state <= 1'b1;
+	   1'b1 :
+	     state <= 1'b0;
+	 endcase // case (state)
+   
+   assign o_tdata = (state == 0) ? i_tdata[31:16] : i_tdata[15:0];
+   assign o_tuser = o_tlast ? i_tuser[1:0] : 2'd0;
+   assign o_tlast = i_tlast & ((state == 1'b1) | short_last);
+
+   assign o_tvalid = i_tvalid;
+   assign i_tready = o_tready & ((state == 1'b1) | short_last);
+   		    
+endmodule // axi_fifo64_to_fifo32
diff --git a/fpga/usrp3/lib/fifo/axi_fifo32_to_fifo64.v b/fpga/usrp3/lib/fifo/axi_fifo32_to_fifo64.v
new file mode 100644
index 000000000..1f168420d
--- /dev/null
+++ b/fpga/usrp3/lib/fifo/axi_fifo32_to_fifo64.v
@@ -0,0 +1,44 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module axi_fifo32_to_fifo64
+  (input clk, input reset, input clear,
+   input [31:0] i_tdata, input [1:0] i_tuser, input i_tlast, input i_tvalid, output i_tready,
+   output [63:0] o_tdata, output [2:0] o_tuser, output o_tlast, output o_tvalid, input o_tready
+   );
+
+   reg [31:0] 	 holding;
+
+   reg 		 state;
+
+   always @(posedge clk)
+     if(reset | clear)
+       state <= 0;
+     else
+       if(i_tvalid & i_tready)
+       case(state)
+	 0 : if(~i_tlast) state <= 1'b1;
+    	 1 : state <= 1'b0;
+	 default : state <= 1'b0;
+       endcase // case (state)
+
+   always @(posedge clk)
+     if(i_tvalid & i_tready)
+       holding <= i_tdata;
+   
+   assign i_tready = (state == 0 && !i_tlast)? 1'b1 : o_tready;
+   assign o_tvalid = (state == 0 && !i_tlast)? 1'b0 : i_tvalid;
+   
+   assign o_tdata = (state == 0) ? {i_tdata, 32'h0} : { holding, i_tdata };
+   assign o_tlast = i_tlast;
+
+   wire [2:0] 	 occ_in = (i_tuser == 0) ? 3'd4 : {1'b0, i_tuser};
+   wire [2:0] 	 occ_out = (state == 0) ? occ_in : (occ_in + 3'd4);
+   
+   assign o_tuser = ~o_tlast ? 3'd0 : occ_out;
+   	 
+endmodule // axi_fifo32_to_fifo64
diff --git a/fpga/usrp3/lib/fifo/axi_fifo64_to_fifo32.v b/fpga/usrp3/lib/fifo/axi_fifo64_to_fifo32.v
new file mode 100644
index 000000000..f9c12ef33
--- /dev/null
+++ b/fpga/usrp3/lib/fifo/axi_fifo64_to_fifo32.v
@@ -0,0 +1,37 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module axi_fifo64_to_fifo32
+  (input clk, input reset, input clear,
+   input [63:0] i_tdata, input [2:0] i_tuser, input i_tlast, input i_tvalid, output i_tready,
+   output [31:0] o_tdata, output [1:0] o_tuser, output o_tlast, output o_tvalid, input o_tready
+   );
+
+   wire 	 short_last = i_tlast & ((i_tuser == 3'd1) | (i_tuser == 3'd2) | (i_tuser == 3'd3) | (i_tuser == 3'd4));
+   
+   reg 		 state;
+   always @(posedge clk)
+     if(reset | clear)
+       state <= 1'b0;
+     else
+       if(i_tvalid & o_tready)
+	 case(state)
+	   1'b0 :
+	     if(~short_last)
+	       state <= 1'b1;
+	   1'b1 :
+	     state <= 1'b0;
+	 endcase // case (state)
+   
+   assign o_tdata = (state == 0) ? i_tdata[63:32] : i_tdata[31:0];
+   assign o_tuser = o_tlast ? i_tuser[1:0] : 2'd0;
+   assign o_tlast = i_tlast & ((state == 1'b1) | short_last);
+
+   assign o_tvalid = i_tvalid;
+   assign i_tready = o_tready & ((state == 1'b1) | short_last);
+   		    
+endmodule // axi_fifo64_to_fifo32
diff --git a/fpga/usrp3/lib/fifo/axi_fifo_2clk.v b/fpga/usrp3/lib/fifo/axi_fifo_2clk.v
new file mode 100644
index 000000000..1f3eee924
--- /dev/null
+++ b/fpga/usrp3/lib/fifo/axi_fifo_2clk.v
@@ -0,0 +1,184 @@
+/////////////////////////////////////////////////////////////////////
+//
+// Copyright 2017 Ettus Research, A National Instruments Company
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: axi_fifo_2clk.v
+//
+// Purpose:
+// An asynchronous clock crossing for AXI-Stream buses
+// The width (WIDTH) and depth (SIZE) of the FIFO is configurable
+// For depths less than the technology's SRL threshold, an SRL
+// will be instantiated. For depths less the minimum RAM block
+// depth (that corresponds to the max width), a single BRAM block
+// will be instantiated. For other larger depths, a BRAM block
+// plus a regular axi_fifo will be instantiated. The depth of the
+// combined FIFO in that case will be larger than the user request.
+//
+// Requirements:
+// Implementation for fifo_short_2clk, fifo_4k_2clk that infer SRL
+// and BRAM based clock-crossing FIFOs respectively
+//
+//////////////////////////////////////////////////////////////////////
+
+module axi_fifo_2clk #(
+  parameter WIDTH     = 69,       // Width of input/output data word
+  parameter SIZE      = 9,        // log2 of the depth of the FIFO
+  parameter PIPELINE  = "NONE",   // Which ports to pipeline? {NONE, IN, OUT, INOUT}
+  parameter DEVICE    = "7SERIES" // FPGA technology identifier (for optimal inference)
+)(
+  input  wire             reset,
+  input  wire             i_aclk,
+  input  wire [WIDTH-1:0] i_tdata,
+  input  wire             i_tvalid,
+  output wire             i_tready,
+  input  wire             o_aclk,
+  output wire [WIDTH-1:0] o_tdata,
+  output wire             o_tvalid,
+  input  wire             o_tready
+);
+
+  wire i_arst, o_arst;
+  synchronizer #(.INITIAL_VAL(1'b1)) i_rst_sync_i (
+    .clk(i_aclk), .rst(1'b0), .in(reset), .out(i_arst)
+  );
+  synchronizer #(.INITIAL_VAL(1'b1)) o_rst_sync_i (
+    .clk(o_aclk), .rst(1'b0), .in(reset), .out(o_arst)
+  );
+
+  //----------------------------------------------
+  // Pipeline Logic
+  //----------------------------------------------
+
+  wire [WIDTH-1:0] i_pipe_tdata,  o_pipe_tdata;
+  wire             i_pipe_tvalid, o_pipe_tvalid;
+  wire             i_pipe_tready, o_pipe_tready;
+
+  generate
+    if (PIPELINE == "IN" || PIPELINE == "INOUT") begin
+      axi_fifo_flop2 #(.WIDTH(WIDTH)) in_pipe_i (
+        .clk(i_aclk), .reset(i_arst), .clear(1'b0),
+        .i_tdata(i_tdata), .i_tvalid(i_tvalid), .i_tready(i_tready),
+        .o_tdata(i_pipe_tdata), .o_tvalid(i_pipe_tvalid), .o_tready(i_pipe_tready),
+        .space(), .occupied()
+      );
+    end else begin
+      assign {i_pipe_tdata, i_pipe_tvalid} = {i_tdata, i_tvalid}; 
+      assign i_tready = i_pipe_tready;
+    end
+
+    if (PIPELINE == "OUT" || PIPELINE == "INOUT") begin
+      axi_fifo_flop2 #(.WIDTH(WIDTH)) out_pipe_i (
+        .clk(o_aclk), .reset(o_arst), .clear(1'b0),
+        .i_tdata(o_pipe_tdata), .i_tvalid(o_pipe_tvalid), .i_tready(o_pipe_tready),
+        .o_tdata(o_tdata), .o_tvalid(o_tvalid), .o_tready(o_tready),
+        .space(), .occupied()
+      );
+    end else begin
+      assign {o_tdata, o_tvalid} = {o_pipe_tdata, o_pipe_tvalid};
+      assign o_pipe_tready = o_tready;
+    end
+  endgenerate
+
+  //----------------------------------------------
+  // FIFO Logic
+  //----------------------------------------------
+
+  wire [WIDTH-1:0] o_ext_tdata;
+  wire             o_ext_tvalid;
+  wire             o_ext_tready;
+
+  // Ideally the following parameters should be technology
+  // specific. For now these values have been optimized for
+  // 7Series FPGAs. They also work for Spartan6 but may not
+  // be optimal. For future generations, make these values
+  // depend on the DEVICE parameter.
+  localparam BASE_WIDTH     = 72;
+  localparam SRL_THRESHOLD  = 5;
+  localparam RAM_THRESHOLD  = 9;
+
+  // How many parallel FIFOs to instantiate to fit WIDTH
+  localparam NUM_FIFOS = ((WIDTH-1)/BASE_WIDTH)+1;
+  localparam INT_WIDTH = BASE_WIDTH * NUM_FIFOS;
+
+  wire [INT_WIDTH-1:0] wr_data, rd_data;
+  wire [NUM_FIFOS-1:0] full, empty;
+  wire                 wr_en, rd_en;
+
+  // Read/write logic for FIFO sections
+  assign wr_data       = {{(INT_WIDTH-WIDTH){1'b0}}, i_pipe_tdata};
+  assign wr_en         = i_pipe_tready & i_pipe_tvalid;
+  assign i_pipe_tready = &(~full);
+  assign o_ext_tdata   = rd_data[WIDTH-1:0];
+  assign o_ext_tvalid  = &(~empty);
+  assign rd_en         = o_ext_tready & o_ext_tvalid;
+
+  // FIFO IP instantiation
+  genvar i;
+  generate
+    for (i = 0; i < NUM_FIFOS; i = i + 1) begin: fifo_section
+      if (SIZE <= SRL_THRESHOLD) begin
+        fifo_short_2clk impl_srl_i (
+          .rst          (i_arst),
+          .wr_clk       (i_aclk),
+          .din          (wr_data[((i+1)*BASE_WIDTH)-1:i*BASE_WIDTH]),
+          .wr_en        (wr_en),
+          .full         (full[i]),
+          .wr_data_count(),
+          .rd_clk       (o_aclk),
+          .dout         (rd_data[((i+1)*BASE_WIDTH)-1:i*BASE_WIDTH]),
+          .rd_en        (rd_en),
+          .empty        (empty[i]),
+          .rd_data_count()
+        );
+      end else begin
+        fifo_4k_2clk impl_bram_i (
+          .rst          (i_arst),
+          .wr_clk       (i_aclk),
+          .din          (wr_data[((i+1)*BASE_WIDTH)-1:i*BASE_WIDTH]),
+          .wr_en        (wr_en),
+          .full         (full[i]),
+          .wr_data_count(),
+          .rd_clk       (o_aclk),
+          .dout         (rd_data[((i+1)*BASE_WIDTH)-1:i*BASE_WIDTH]),
+          .rd_en        (rd_en),
+          .empty        (empty[i]),
+          .rd_data_count()
+        );
+      end
+    end
+  endgenerate
+
+  //----------------------------------------------
+  // Extension FIFO (for large sizes)
+  //----------------------------------------------
+
+  generate
+    if (SIZE > RAM_THRESHOLD) begin
+      wire [WIDTH-1:0] ext_pipe_tdata;
+      wire             ext_pipe_tvalid;
+      wire             ext_pipe_tready;
+
+      // Add a register slice between BRAM cascades
+      axi_fifo_flop2 #(.WIDTH(WIDTH)) ext_fifo_pipe_i (
+        .clk(o_aclk), .reset(o_arst), .clear(1'b0),
+        .i_tdata(o_ext_tdata), .i_tvalid(o_ext_tvalid), .i_tready(o_ext_tready),
+        .o_tdata(ext_pipe_tdata), .o_tvalid(ext_pipe_tvalid), .o_tready(ext_pipe_tready),
+        .space(), .occupied()
+      );
+
+      // Bolt on an extension FIFO if the requested depth is larger than the BRAM
+      // 2clk FIFO primitive (IP)
+      axi_fifo_bram #(.WIDTH(WIDTH), .SIZE(SIZE)) ext_fifo_i (
+        .clk(o_aclk), .reset(o_arst), .clear(1'b0),
+        .i_tdata(ext_pipe_tdata), .i_tvalid(ext_pipe_tvalid), .i_tready(ext_pipe_tready),
+        .o_tdata(o_pipe_tdata), .o_tvalid(o_pipe_tvalid), .o_tready(o_pipe_tready),
+        .space(), .occupied()
+      );
+    end else begin
+      assign {o_pipe_tdata, o_pipe_tvalid} = {o_ext_tdata, o_ext_tvalid};
+      assign o_ext_tready = o_pipe_tready;
+    end
+  endgenerate
+
+endmodule
diff --git a/fpga/usrp3/lib/fifo/axi_fifo_32_64_tb.v b/fpga/usrp3/lib/fifo/axi_fifo_32_64_tb.v
new file mode 100644
index 000000000..792538361
--- /dev/null
+++ b/fpga/usrp3/lib/fifo/axi_fifo_32_64_tb.v
@@ -0,0 +1,119 @@
+//
+// Copyright 2013 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+`timescale 1ns/1ps
+
+module axi_fifo_32_64_tb();
+
+   reg clk    = 0;
+   reg reset  = 1;
+   
+   always #10 clk = ~clk;
+   
+   initial $dumpfile("axi_fifo_32_64_tb.vcd");
+   initial $dumpvars(0,axi_fifo_32_64_tb);
+
+   task send_packet;
+      input [63:0] data_start;
+      input [2:0]  user;
+      input [31:0] len;
+      
+      begin
+	 @(posedge clk);
+	 {i_tuser, i_tlast, i_tdata} <= { 3'd0, 1'b0, data_start };
+	 repeat(len-1)
+	   begin
+	      i_tvalid <= 1;
+	      @(posedge clk);
+	      i_tdata <= i_tdata + 64'h0000_0002_0000_0002;
+	   end
+	 i_tuser <= user;
+	 i_tlast <= 1;
+	 @(posedge clk);
+	 i_tvalid <= 1'b0;
+	 @(posedge clk);
+      end
+   endtask // send_packet
+   
+   initial
+     begin
+	#1000 reset = 0;
+	#200000;
+	$finish;
+     end
+   
+   reg [63:0] i_tdata;
+   reg [2:0]  i_tuser;
+   reg 	      i_tlast;
+   reg 	      i_tvalid;
+   wire       i_tready;
+
+   wire [63:0] i_tdata_int;
+   wire [2:0]  i_tuser_int;
+   wire        i_tlast_int, i_tvalid_int, i_tready_int;
+
+   wire [63:0] o_tdata;
+   wire [31:0] o_tdata_int, o_tdata_int2;
+   wire [2:0]  o_tuser;
+   wire [1:0]  o_tuser_int, o_tuser_int2;
+   wire        o_tlast, o_tlast_int, o_tvalid, o_tvalid_int, o_tready, o_tready_int;
+   wire        o_tlast_int2, o_tvalid_int2, o_tready_int2;
+   
+   localparam RPT_COUNT = 16;
+   
+   initial
+     begin
+	i_tvalid <= 0;
+	
+	while(reset)
+	  @(posedge clk);
+	@(posedge clk);
+
+	send_packet(64'hA0000000_A0000001, 3'd7, 4);
+	@(posedge clk);
+     end // initial begin
+
+   axi_fifo #(.WIDTH(68), .SIZE(10)) fifo
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata({i_tlast,i_tuser,i_tdata}), .i_tvalid(i_tvalid), .i_tready(i_tready),
+      .o_tdata({i_tlast_int,i_tuser_int,i_tdata_int}), .o_tvalid(i_tvalid_int), .o_tready(i_tready_int));
+
+   axi_fifo64_to_fifo32 dut
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata(i_tdata_int), .i_tuser(i_tuser_int), .i_tlast(i_tlast_int), .i_tvalid(i_tvalid_int), .i_tready(i_tready_int),
+      .o_tdata(o_tdata_int), .o_tuser(o_tuser_int), .o_tlast(o_tlast_int), .o_tvalid(o_tvalid_int), .o_tready(o_tready_int));
+
+   /*
+   axi_fifo #(.WIDTH(35), .SIZE(10)) fifo_middle
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata({o_tlast_int,o_tuser_int,o_tdata_int}), .i_tvalid(o_tvalid_int), .i_tready(o_tready_int),
+      .o_tdata({o_tlast_int2,o_tuser_int2,o_tdata_int2}), .o_tvalid(o_tvalid_int2), .o_tready(o_tready_int2));
+*/
+   assign o_tdata_int2 = o_tdata_int;
+   assign o_tlast_int2 = o_tlast_int;
+   assign o_tuser_int2 = o_tuser_int;
+   assign o_tvalid_int2 = o_tvalid_int;
+   assign o_tready_int = o_tready_int2;
+   
+   axi_fifo32_to_fifo64 dut2
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata(o_tdata_int2), .i_tuser(o_tuser_int2), .i_tlast(o_tlast_int2), .i_tvalid(o_tvalid_int2), .i_tready(o_tready_int2),
+      .o_tdata(o_tdata), .o_tuser(o_tuser), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready));
+
+   assign o_tready = 1'b1;
+   
+   always @(posedge clk)
+     if(i_tvalid & i_tready)
+       $display("IN: TUSER %x\tTLAST %x\tTDATA %x", i_tuser, i_tlast, i_tdata);
+
+   always @(posedge clk)
+     if(o_tvalid_int & o_tready_int)
+       $display("\t\t\t\t\t\tMIDDLE: TUSER %x\tTLAST %x\tTDATA %x", o_tuser_int, o_tlast_int, o_tdata_int);
+
+   always @(posedge clk)
+     if(o_tvalid & o_tready)
+       $display("\t\t\t\t\t\t\t\t\t\t\tOUT: TUSER %x\tTLAST %x\tTDATA %x", o_tuser, o_tlast, o_tdata);
+
+endmodule // axi_fifo_32_64_tb
diff --git a/fpga/usrp3/lib/fifo/axi_fifo_bram.v b/fpga/usrp3/lib/fifo/axi_fifo_bram.v
new file mode 100644
index 000000000..173468129
--- /dev/null
+++ b/fpga/usrp3/lib/fifo/axi_fifo_bram.v
@@ -0,0 +1,174 @@
+//
+// Copyright 2012-2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+
+// Block RAM AXI fifo
+
+
+module axi_fifo_bram
+  #(parameter WIDTH=32, SIZE=9)
+   (input clk, input reset, input clear,
+    input [WIDTH-1:0] i_tdata,
+    input i_tvalid,
+    output i_tready,
+    output reg [WIDTH-1:0] o_tdata = 'd0,
+    output reg o_tvalid = 1'b0,
+    input o_tready,
+    
+    output reg [15:0] space,
+    output reg [15:0] occupied);
+
+   wire [WIDTH-1:0]   int_tdata;
+   wire 	      int_tready;
+
+   wire full, empty;
+   wire write     = i_tvalid & i_tready;
+   // read_int will assert when either a read occurs or the output register is empty (and there is data in the shift register fifo)
+   wire read_int  = ~empty & int_tready;
+   // read will only assert when an actual 1read request occurs at the interface
+   wire read      = o_tready & o_tvalid;
+
+   assign i_tready  = ~full;
+
+   // Read side states
+   localparam 	  ST_EMPTY = 0;
+   localparam 	  PRE_READ = 1;
+   localparam 	  READING = 2;
+
+   reg [SIZE-1:0] wr_addr, rd_addr;
+   reg [1:0] 	  read_state;
+
+   reg 	  empty_reg = 1'b1, full_reg = 1'b0;
+   always @(posedge clk)
+     if(reset)
+       wr_addr <= 0;
+     else if(clear)
+       wr_addr <= 0;
+     else if(write)
+       wr_addr <= wr_addr + 1;
+
+   ram_2port #(.DWIDTH(WIDTH),.AWIDTH(SIZE))
+     ram (.clka(clk),
+	  .ena(1'b1),
+	  .wea(write),
+	  .addra(wr_addr),
+	  .dia(i_tdata),
+	  .doa(),
+
+	  .clkb(clk),
+	  .enb((read_state==PRE_READ)|read_int),
+	  .web(1'b0),
+	  .addrb(rd_addr),
+	  .dib({WIDTH{1'b1}}),
+	  .dob(int_tdata));
+
+   always @(posedge clk)
+     if(reset)
+       begin
+	  read_state <= ST_EMPTY;
+	  rd_addr <= 0;
+	  empty_reg <= 1;
+       end
+     else
+       if(clear)
+	 begin
+	    read_state <= ST_EMPTY;
+	    rd_addr <= 0;
+	    empty_reg <= 1;
+	 end
+       else 
+	 case(read_state)
+	   ST_EMPTY :
+	     if(write)
+	       begin
+		  //rd_addr <= wr_addr;
+		  read_state <= PRE_READ;
+	       end
+	   PRE_READ :
+	     begin
+		read_state <= READING;
+		empty_reg <= 0;
+		rd_addr <= rd_addr + 1;
+	     end
+	   
+	   READING :
+	     if(read_int)
+	       if(rd_addr == wr_addr)
+		 begin
+		    empty_reg <= 1; 
+		    if(write)
+		      read_state <= PRE_READ;
+		    else
+		      read_state <= ST_EMPTY;
+		 end
+	       else
+		 rd_addr <= rd_addr + 1;
+	 endcase // case(read_state)
+
+   wire [SIZE-1:0] dont_write_past_me = rd_addr - 2;
+   wire 	   becoming_full = wr_addr == dont_write_past_me;
+     
+   always @(posedge clk)
+     if(reset)
+       full_reg <= 0;
+     else if(clear)
+       full_reg <= 0;
+     else if(read_int & ~write)
+       full_reg <= 0;
+     //else if(write & ~read_int & (wr_addr == (rd_addr-3)))
+     else if(write & ~read_int & becoming_full)
+       full_reg <= 1;
+
+   //assign empty = (read_state != READING);
+   assign empty = empty_reg;
+
+   // assign full = ((rd_addr - 1) == wr_addr);
+   assign full = full_reg;
+
+   // Output registered stage
+   always @(posedge clk)
+   begin
+      // Valid flag
+      if (reset | clear)
+         o_tvalid <= 1'b0;
+      else if (int_tready)
+         o_tvalid <= ~empty;
+
+      // Data
+      if (int_tready)
+         o_tdata <= int_tdata;
+   end
+
+   assign int_tready = o_tready | ~o_tvalid;
+
+   //////////////////////////////////////////////
+   // space and occupied are for diagnostics only
+   // not guaranteed exact
+
+   localparam NUMLINES = (1<<SIZE)+1;   //Output register increases capacity by 1
+   always @(posedge clk)
+     if(reset)
+       space <= NUMLINES;
+     else if(clear)
+       space <= NUMLINES;
+     else if(read & ~write)
+       space <= space + 16'b1;
+     else if(write & ~read)
+       space <= space - 16'b1;
+   
+   always @(posedge clk)
+     if(reset)
+       occupied <= 16'b0;
+     else if(clear)
+       occupied <= 16'b0;
+     else if(read & ~write)
+       occupied <= occupied - 16'b1;
+     else if(write & ~read)
+       occupied <= occupied + 16'b1;
+
+endmodule // fifo_long
diff --git a/fpga/usrp3/lib/fifo/axi_fifo_cascade.v b/fpga/usrp3/lib/fifo/axi_fifo_cascade.v
new file mode 100644
index 000000000..84c009c42
--- /dev/null
+++ b/fpga/usrp3/lib/fifo/axi_fifo_cascade.v
@@ -0,0 +1,48 @@
+//
+// Copyright 2012-2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+
+// Cascade FIFO :  ShortFIFO -> Block RAM fifo -> ShortFIFO for timing and placement help
+
+// Special case SIZE <= 5 uses a short fifo in the middle, which is not too useful in this case
+
+module axi_fifo_cascade
+  #(parameter WIDTH=32, SIZE=9)
+   (input clk, input reset, input clear,
+    input [WIDTH-1:0] i_tdata,
+    input i_tvalid,
+    output i_tready,
+    output [WIDTH-1:0] o_tdata,
+    output o_tvalid,
+    input o_tready,
+    
+    output [15:0] space,
+    output [15:0] occupied);
+
+   wire [WIDTH-1:0]   int1_tdata, int2_tdata;
+   wire 	      int1_tvalid, int1_tready, int2_tvalid, int2_tready;
+   
+   axi_fifo_flop2 #(.WIDTH(WIDTH)) pre_fifo
+     (.clk(clk), .reset(reset), .clear(clear),
+      .i_tdata(i_tdata), .i_tvalid(i_tvalid), .i_tready(i_tready),
+      .o_tdata(int1_tdata), .o_tvalid(int1_tvalid), .o_tready(int1_tready),
+      .space(), .occupied());
+
+   axi_fifo #(.WIDTH(WIDTH), .SIZE(SIZE)) main_fifo
+     (.clk(clk), .reset(reset), .clear(clear),
+      .i_tdata(int1_tdata), .i_tvalid(int1_tvalid), .i_tready(int1_tready),
+      .o_tdata(int2_tdata), .o_tvalid(int2_tvalid), .o_tready(int2_tready),
+      .space(space), .occupied(occupied));   // May change unexpectedly, but are always conservative
+  
+   axi_fifo_flop2 #(.WIDTH(WIDTH)) post_fifo
+     (.clk(clk), .reset(reset), .clear(clear),
+      .i_tdata(int2_tdata), .i_tvalid(int2_tvalid), .i_tready(int2_tready),
+      .o_tdata(o_tdata), .o_tvalid(o_tvalid), .o_tready(o_tready),
+      .space(), .occupied());
+
+endmodule // axi_fifo_cascade
diff --git a/fpga/usrp3/lib/fifo/axi_fifo_flop.v b/fpga/usrp3/lib/fifo/axi_fifo_flop.v
new file mode 100644
index 000000000..a2e058cc1
--- /dev/null
+++ b/fpga/usrp3/lib/fifo/axi_fifo_flop.v
@@ -0,0 +1,43 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+//
+// Single FIFO (register) with AXI4-STREAM interface
+//
+
+module axi_fifo_flop
+  #(parameter WIDTH=32)
+   (input clk,
+    input reset,
+    input clear,
+    input [WIDTH-1:0] i_tdata,
+    input i_tvalid,
+    output i_tready,
+    output reg [WIDTH-1:0] o_tdata = 'd0,
+    output reg o_tvalid = 1'b0,
+    input o_tready,
+    output space,
+    output occupied);
+
+   assign i_tready = ~reset & (~o_tvalid | o_tready);
+
+   always @(posedge clk)
+     if(reset | clear)
+       o_tvalid <= 1'b0;
+     else
+       o_tvalid <= (i_tready & i_tvalid) | (o_tvalid & ~o_tready);
+
+   always @(posedge clk)
+     if(i_tvalid & i_tready)
+       o_tdata <= i_tdata;
+
+   // These aren't terribly useful, but include them for consistency
+   assign space = i_tready;
+   assign occupied = o_tvalid;
+
+endmodule // axi_fifo_flop
diff --git a/fpga/usrp3/lib/fifo/axi_fifo_flop2.v b/fpga/usrp3/lib/fifo/axi_fifo_flop2.v
new file mode 100644
index 000000000..381253e56
--- /dev/null
+++ b/fpga/usrp3/lib/fifo/axi_fifo_flop2.v
@@ -0,0 +1,59 @@
+//
+// Copyright 2015 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Single cycle latency, depth of 2 "Flip flop" with no end to end combinatorial paths on
+// AXI control signals (such as i_tready depends on o_tready). Breaking the combinatorial
+// paths requires an additional register stage.
+//
+// Note: Once i_tvalid is asserted, it cannot be deasserted without i_tready having asserted
+//       indicating i_tdata has been read. This is an AXI stream requirement.
+
+module axi_fifo_flop2 #(
+  parameter WIDTH = 32
+)(
+  input clk,
+  input reset,
+  input clear,
+  input [WIDTH-1:0] i_tdata,
+  input i_tvalid,
+  output i_tready,
+  output reg [WIDTH-1:0] o_tdata = 'h0,
+  output reg o_tvalid = 1'b0,
+  input o_tready,
+  output [1:0] space,
+  output [1:0] occupied);
+
+  reg [WIDTH-1:0] i_tdata_temp = 'h0;
+  reg             i_tvalid_temp = 1'b0;
+
+  assign i_tready = ~i_tvalid_temp;
+
+  always @(posedge clk) begin
+    if (~o_tvalid | o_tready) begin
+      if (i_tvalid_temp) begin
+        o_tvalid      <= 1'b1;
+        o_tdata       <= i_tdata_temp;
+      end else begin
+        o_tvalid      <= i_tvalid;
+        o_tdata       <= i_tdata;
+      end
+      i_tvalid_temp   <= 1'b0;
+    end else begin
+      if (~i_tvalid_temp) begin
+        i_tvalid_temp <= i_tvalid;
+        i_tdata_temp  <= i_tdata;
+      end
+    end
+    if (reset | clear) begin
+      o_tvalid      <= 1'b0;
+      i_tvalid_temp <= 1'b0;
+    end
+  end
+
+  assign occupied = i_tvalid_temp + o_tvalid;
+  assign space    = 2 - occupied;
+
+endmodule
diff --git a/fpga/usrp3/lib/fifo/axi_fifo_short.v b/fpga/usrp3/lib/fifo/axi_fifo_short.v
new file mode 100644
index 000000000..465be28bb
--- /dev/null
+++ b/fpga/usrp3/lib/fifo/axi_fifo_short.v
@@ -0,0 +1,113 @@
+//
+// Copyright 2012 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+//
+// 32 word FIFO with AXI4-STREAM interface.
+//
+// NOTE: This module uses the SRLC32E primitive explicitly and as such
+// can only be used with Xilinx technology of the VIRTEX-6/SPARTAN-6/SIERIES-7 or newer.
+//
+
+module axi_fifo_short
+  #(parameter WIDTH=32)
+   (
+    input clk, 
+    input reset, 
+    input clear,
+    input [WIDTH-1:0] i_tdata,
+    input i_tvalid,
+    output i_tready,
+    output [WIDTH-1:0] o_tdata,
+    output o_tvalid,
+    input o_tready,
+    
+    output reg [5:0] space,
+    output reg [5:0] occupied
+    );
+
+   reg full = 1'b0, empty = 1'b1;
+   wire write 	     = i_tvalid & i_tready;
+   wire read 	     = o_tready & o_tvalid;
+
+   assign i_tready  = ~full;
+   assign o_tvalid  = ~empty;
+   
+   reg [4:0] 	  a;
+   genvar 	  i; 
+   
+   generate
+      for (i=0;i<WIDTH;i=i+1)
+	begin : gen_srlc32e
+	   SRLC32E
+	     srlc32e(.Q(o_tdata[i]), .Q31(),
+		     .A(a), //.A0(a[0]),.A1(a[1]),.A2(a[2]),.A3(a[3]),.A4(a[4]),
+		    .CE(write),.CLK(clk),.D(i_tdata[i]));
+	end
+   endgenerate
+   
+   always @(posedge clk)
+     if(reset)
+       begin
+	  a <= 0;
+	  empty <= 1;
+	  full <= 0;
+       end
+     else if(clear)
+       begin
+	  a <= 0;
+	  empty <= 1;
+	  full<= 0;
+       end
+     else if(read & ~write)
+       begin
+	  full <= 0;
+	  if(a==0)
+	    empty <= 1;
+	  else
+	    a <= a - 1;
+       end
+     else if(write & ~read)
+       begin
+	  empty <= 0;
+	  if(~empty)
+	    a <= a + 1;
+	  if(a == 30)
+	    full <= 1;
+       end
+
+   // NOTE will fail if you write into a full fifo or read from an empty one
+
+   //////////////////////////////////////////////////////////////
+   // space and occupied are used for diagnostics, not 
+   // guaranteed correct
+   
+   //assign space = full ? 0 : empty ? 16 : 15-a;
+   //assign occupied = empty ? 0 : full ? 16 : a+1;
+
+   always @(posedge clk)
+     if(reset)
+       space <= 6'd32;
+     else if(clear)
+       space <= 6'd32;
+     else if(read & ~write)
+       space <= space + 6'd1;
+     else if(write & ~read)
+       space <= space - 6'd1;
+   
+   always @(posedge clk)
+     if(reset)
+       occupied <= 6'd0;
+     else if(clear)
+       occupied <= 6'd0;
+     else if(read & ~write)
+       occupied <= occupied - 6'd1;
+     else if(write & ~read)
+       occupied <= occupied + 6'd1;
+      
+endmodule // axi_fifo_short
+
diff --git a/fpga/usrp3/lib/fifo/axi_fifo_tb.v b/fpga/usrp3/lib/fifo/axi_fifo_tb.v
new file mode 100644
index 000000000..69529c7af
--- /dev/null
+++ b/fpga/usrp3/lib/fifo/axi_fifo_tb.v
@@ -0,0 +1,328 @@
+//
+// Copyright 2015 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module axi_fifo_tb();
+
+  /*********************************************
+  ** User variables
+  *********************************************/
+  localparam FIFO_SIZE = 1;
+  localparam TEST_VECTOR_SIZE = 10;
+
+  /*********************************************
+  ** Clocks & Reset
+  *********************************************/
+  `define CLOCK_FREQ    200e6
+  `define RESET_TIME    100
+
+  reg clk;
+  initial clk = 1'b0;
+  localparam CLOCK_PERIOD = 1e9/`CLOCK_FREQ;
+  always
+    #(CLOCK_PERIOD) clk = ~clk;
+
+  reg reset;
+  initial begin
+    reset = 1'b1;
+    #(`RESET_TIME);
+    @(posedge clk);
+    reset = 1'b0;
+  end
+
+  /*********************************************
+  ** DUT
+  *********************************************/
+  reg [31:0] i_tdata;
+  reg i_tvalid, o_tready;
+  wire i_tready, o_tvalid;
+  wire [31:0] o_tdata;
+  reg clear;
+
+  axi_fifo #(
+    .SIZE(FIFO_SIZE),
+    .WIDTH(32))
+  dut_axi_fifo (
+    .clk(clk), .reset(reset), .clear(clear),
+    .i_tdata(i_tdata), .i_tvalid(i_tvalid), .i_tready(i_tready),
+    .o_tdata(o_tdata), .o_tvalid(o_tvalid), .o_tready(o_tready),
+    .space(), .occupied());
+
+  /*********************************************
+  ** Testbench
+  *********************************************/
+  reg [TEST_VECTOR_SIZE-1:0] i_tvalid_sequence;
+  reg [TEST_VECTOR_SIZE-1:0] o_tready_sequence;
+  integer i,k,n,i_tready_timeout;
+  reg [31:0] o_tdata_check;
+
+  initial begin
+    i_tdata = {32{1'b1}};
+    i_tvalid = 1'b0;
+    o_tready = 1'b0;
+    i_tready_timeout = 0;
+    clear = 1'b0;
+    @(negedge reset);
+    #(10*CLOCK_PERIOD)
+    @(posedge clk);
+    $display("*****************************************************");
+    $display("**              Begin Assertion Tests              **");
+    $display("*****************************************************");
+    $display("Test 1 -- Check filling FIFO");
+    // Note, if REG_OUTPUT is enabled, the FIFO has space for 1 extra entry
+    for (i = 0; i < 2**FIFO_SIZE; i = i + 1) begin
+      if (~i_tready) begin
+          $display("Test 1 FAILED!");
+          $error("FIFO size should be %d entries, but detected %d!",2**FIFO_SIZE,i);
+          $stop;
+      end
+      i_tvalid = 1'b1;
+      i_tdata = i_tdata + 32'd1;
+      @(posedge clk);
+    end
+    i_tvalid = 1'b0;
+    @(posedge clk);
+    if (i_tready) begin
+      $display("Test 1 warning!");
+      $warning("i_tready still asserted after filling FIFO with %d entries! Might be due to output registering.",i);
+      //$stop;
+    end
+    $display("Test 1 Passed!");
+    //////////////////////////////////////////////////////////////////////////////
+    //////////////////////////////////////////////////////////////////////////////
+    $display("Test 2 -- Check emptying FIFO");
+    for (i = 0; i < 2**FIFO_SIZE; i = i + 1) begin
+      if (~o_tvalid) begin
+          $display("Test 2 FAILED!");
+          $error("FIFO o_tvalid not asserted! Occured at entry %d",2**FIFO_SIZE-i+1);
+          $stop;
+      end
+      o_tready = 1'b1;
+      @(posedge clk);
+    end
+    o_tready = 1'b0;
+    @(posedge clk);
+    if (o_tvalid) begin
+      $display("Test 1 FAILED!");
+      $error("o_tvalid still asserted after emptying FIFO!");
+      $stop;
+    end
+    $display("Test 2 Passed!");
+    //////////////////////////////////////////////////////////////////////////////
+    //////////////////////////////////////////////////////////////////////////////
+    $display("Test 3 -- Check for o_tready / i_tready dropping unexpectantly");
+    clear = 1'b1;
+    i_tdata = {32{1'b1}};
+    i_tvalid = 1'b0;
+    o_tready = 1'b0;
+    @(posedge clk);
+    clear = 1'b0;
+    @(posedge clk);
+    for (i = 0; i < 2**FIFO_SIZE-1; i = i + 1) begin
+      i_tvalid = 1'b1;
+      i_tdata = i_tdata + 32'd1;
+      @(posedge clk);
+      i_tvalid = 1'b0;
+      // Give some time to propogate
+      @(posedge clk);
+      @(posedge clk);
+      @(posedge clk);
+      if (~i_tready) begin
+          $display("Test 3 FAILED!");
+          $error("i_tready deasserted unexpectantly after writing %d entries!",i+1);
+          $stop;
+      end
+      if (~o_tvalid) begin
+          $display("Test 3 FAILED!");
+          $error("o_tvalid deasserted unexpectantly after writing %d entries!",i+1);
+          $stop;
+      end
+    end
+    // Write final entry
+    i_tvalid = 1'b1;
+    i_tdata = i_tdata + 32'd1;
+    @(posedge clk);
+    i_tvalid = 1'b0;
+    @(posedge clk);
+    if (i_tready) begin
+        $display("Test 3 warning!");
+        $warning("i_tready still asserted after writing %d entries! Might be due to output registering.",i+1);
+        //$stop;
+    end
+    @(posedge clk);
+    for (i = 0; i < 2**FIFO_SIZE-1; i = i + 1) begin
+      o_tready = 1'b1;
+      @(posedge clk);
+      o_tready = 1'b0;
+      // Give some time to propogate
+      @(posedge clk);
+      @(posedge clk);
+      @(posedge clk);
+      if (~i_tready) begin
+          $display("Test 3 FAILED!");
+          $error("i_tready deasserted unexpectantly after reading %d entries!",i+1);
+          $stop;
+      end
+      if (~o_tvalid) begin
+          $display("Test 3 FAILED!");
+          $error("o_tvalid deasserted unexpectantly after reading %d entries!",i+1);
+          $stop;
+      end
+    end
+    // Read final entry
+    o_tready = 1'b1;
+    @(posedge clk);
+    o_tready = 1'b0;
+    @(posedge clk);
+    if (o_tvalid) begin
+        $display("Test 3 FAILED!");
+        $error("o_tvalid still asserted after reading %d entries!",i+1);
+        $stop;
+    end
+    @(posedge clk);
+    //////////////////////////////////////////////////////////////////////////////
+    //////////////////////////////////////////////////////////////////////////////
+    $display("Test 4 -- Check for bubble states");
+    clear = 1'b1;
+    i_tdata = {32{1'b1}};
+    i_tvalid = 1'b0;
+    o_tready = 1'b0;
+    @(posedge clk);
+    clear = 1'b0;
+    @(posedge clk);
+    // Fill up half way
+    for (i = 0; i < (2**FIFO_SIZE + 1)/2; i = i + 1) begin
+      i_tvalid = 1'b1;
+      i_tdata = i_tdata + 32'd1;
+      @(posedge clk);
+    end
+    // Start reading
+    o_tready = 1'b1;
+    i_tdata = i_tdata + 32'd1;
+    @(posedge clk);
+    // Give a clock cycle for latency, but no bubbles should occur after this
+    i_tdata = i_tdata + 32'd1;
+    @(posedge clk);
+    // Continue to write and read at full rate
+    for (i = 0; i < (2**FIFO_SIZE + 1)/2; i = i + 1) begin
+      if (~i_tready) begin
+          $display("Test 4 FAILED!");
+          $error("FIFO bubble state detected when writing & reading at full rate!");
+          $stop;
+      end
+      i_tvalid = 1'b1;
+      i_tdata = i_tdata + 32'd1;
+      @(posedge clk);
+    end
+    // Read at full, write at half rate
+    for (i = 0; i < (2**FIFO_SIZE + 1)/2; i = i + 1) begin
+      if (~i_tready | ~o_tvalid) begin
+          $display("Test 4 FAILED!");
+          $error("FIFO bubble state detected when write at half rate, reading at full rate!");
+          $stop;
+      end
+      i_tvalid = ~i_tvalid;
+      if (i_tvalid) i_tdata = i_tdata + 32'd1;
+      @(posedge clk);
+    end
+    // Read at half rate, write at full rate
+    for (i = 0; i < (2**FIFO_SIZE + 1)/2; i = i + 1) begin
+      if (~i_tready | ~o_tvalid) begin
+          $display("Test 4 FAILED!");
+          $error("FIFO bubble state detected when write at half rate, reading at full rate!");
+          $stop;
+      end
+      o_tready = ~o_tready;
+      i_tvalid = 1'b1;
+      i_tdata = i_tdata + 32'd1;
+      @(posedge clk);
+    end
+    $display("Test 4 Passed!");
+    //////////////////////////////////////////////////////////////////////////////
+    // Tests combinations of i_tvalid / o_tready sequences.
+    // Test space depends on TEST_VECTOR_SIZE.
+    // Example: TEST_VECTOR_SIZE = 10 => 1024*1024 number of test sequences,
+    //          which is every possible 10 bit sequence of i_tvalid / o_tready.
+    $display("Test 5 -- Check combinations of i_tvalid / o_tready");
+    clear = 1'b1;
+    i_tdata = {32{1'b1}};
+    i_tvalid = 1'b0;
+    o_tready = 1'b0;
+    i_tready_timeout = 0;
+    i_tvalid_sequence = {TEST_VECTOR_SIZE{1'd0}};
+    o_tready_sequence = {TEST_VECTOR_SIZE{1'd0}};
+    @(posedge clk);
+    clear = 1'b0;
+    @(posedge clk);
+    for (i = 0; i < 2**TEST_VECTOR_SIZE; i = i + 1) begin
+      i_tvalid_sequence = i_tvalid_sequence + 1;
+      for (k = 0; k < 2**TEST_VECTOR_SIZE; k = k + 1) begin
+        o_tready_sequence = o_tready_sequence + 1;
+        for (n = 0; n < TEST_VECTOR_SIZE; n = n + 1) begin
+          if (o_tready_sequence[n]) begin
+            o_tready = 1'b1;
+          end else begin
+            o_tready = 1'b0;
+          end
+          // Special Case: If i_tready timed out, then i_tvalid is still asserted and we cannot
+          //               deassert i_tvalid until we see a corresponding i_tready. This is a basic
+          //               AXI stream requirement, so we will continue to assert i_tvalid regardless
+          //               of what i_tvalid_sequence would have set i_tvalid for this loop.
+          if (i_tvalid_sequence[n] | (i_tready_timeout == TEST_VECTOR_SIZE)) begin
+            i_tvalid = 1'b1;
+            if (i_tready_timeout < TEST_VECTOR_SIZE) begin
+              i_tdata = i_tdata + 32'd1;
+            end
+            @(posedge clk);
+            i_tready_timeout = 0;
+            // Wait for i_tready until timeout. Timeouts may occur when o_tready_sequence
+            // has o_tready not asserted for several clock cycles.
+            while(~i_tready & (i_tready_timeout < TEST_VECTOR_SIZE)) begin
+              @(posedge clk)
+              i_tready_timeout = i_tready_timeout + 1;
+            end
+          end else begin
+            i_tvalid = 1'b0;
+            @(posedge clk);
+          end
+        end
+      end
+      // Reset starting conditions for the test sequences
+      clear = 1'b1;
+      i_tdata = {32{1'b1}};
+      i_tvalid = 1'b0;
+      o_tready = 1'b0;
+      i_tready_timeout = 0;
+      @(posedge clk);
+      clear = 1'b0;
+      @(posedge clk);
+    end
+    $display("Test 5 Passed!");
+    $display("All tests PASSED!");
+    $stop;
+  end
+
+  // Check the input counting sequence independent of
+  // i_tvalid / o_tready sequences.
+  always @(posedge clk) begin
+    if (reset) begin
+      o_tdata_check <= 32'd0;
+    end else begin
+      if (clear) begin
+        o_tdata_check <= 32'd0;
+      end
+      if (o_tready & o_tvalid) begin
+        o_tdata_check <= o_tdata_check + 32'd1;
+        if (o_tdata != o_tdata_check) begin
+          $display("Test FAILED!");
+          $error("Incorrect output!");
+          $stop;
+        end
+      end
+    end
+  end
+
+endmodule
diff --git a/fpga/usrp3/lib/fifo/axi_filter_mux4.v b/fpga/usrp3/lib/fifo/axi_filter_mux4.v
new file mode 100644
index 000000000..4c9d76003
--- /dev/null
+++ b/fpga/usrp3/lib/fifo/axi_filter_mux4.v
@@ -0,0 +1,158 @@
+//
+// Copyright 2014 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// axi_filter_mux -- takes 4 64-bit AXI stream of CHDR data, merges them to 1 output channel
+// Round-robin if PRIO=0, priority if PRIO=1 (lower number ports get priority)
+// Bubble cycles are inserted after each packet in PRIO mode, or on wraparound in Round Robin mode.
+// Filter forces specific destination SID to pass per port, else dump data to /dev/null
+
+module axi_filter_mux4
+  #(parameter PRIO=0,
+    parameter WIDTH=64,
+    parameter BUFFER=0,
+    parameter FILTER0 =0,
+    parameter FILTER1 =0,
+    parameter FILTER2 =0,
+    parameter FILTER3 =0
+    )
+   (input clk, input reset, input clear,
+    input [WIDTH-1:0] i0_tdata, input i0_tlast, input i0_tvalid, output i0_tready,
+    input [WIDTH-1:0] i1_tdata, input i1_tlast, input i1_tvalid, output i1_tready,
+    input [WIDTH-1:0] i2_tdata, input i2_tlast, input i2_tvalid, output i2_tready,
+    input [WIDTH-1:0] i3_tdata, input i3_tlast, input i3_tvalid, output i3_tready,
+    output [WIDTH-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready);
+
+   wire [WIDTH-1:0]    o_tdata_int;
+   wire 	       o_tlast_int, o_tvalid_int, o_tready_int;
+   
+   reg [3:0] 	  mx_state;
+   reg 		  filter_packet;
+   
+   localparam MX_IDLE = 4'b0000;
+   localparam MX_0    = 4'b0001;
+   localparam MX_1    = 4'b0010;
+   localparam MX_2    = 4'b0100;
+   localparam MX_3    = 4'b1000;
+ 
+
+   assign     good0 = i0_tdata[15:0]==FILTER0;
+   assign     good1 = i1_tdata[15:0]==FILTER1;
+   assign     good2 = i2_tdata[15:0]==FILTER2;
+   assign     good3 = i3_tdata[15:0]==FILTER3;
+ 
+   always @(posedge clk)
+     if(reset | clear)
+       mx_state <= MX_IDLE;
+     else
+       case (mx_state)
+	 MX_IDLE :
+	   if(i0_tvalid) begin
+	      mx_state <= MX_0;
+	      filter_packet <= !good0;
+	   end
+	   else if(i1_tvalid) begin    
+	      mx_state <= MX_1;
+	      filter_packet <= !good1;
+	   end	 
+	   else if(i2_tvalid) begin
+	      mx_state <= MX_2;
+	      filter_packet <= !good2;
+	   end
+	   else if(i3_tvalid) begin
+	      mx_state <= MX_3;
+	      filter_packet <= !good3;
+	   end
+
+	 MX_0 :
+	   if(o_tready_int & o_tvalid_int & o_tlast_int)
+	     if(PRIO)
+	       mx_state <= MX_IDLE;
+	     else if(i1_tvalid) begin    
+		mx_state <= MX_1;
+		filter_packet <= !good1;
+	     end
+	     else if(i2_tvalid) begin    
+		mx_state <= MX_2;
+		filter_packet <= !good2;
+	     end
+	     else if(i3_tvalid) begin    
+		mx_state <= MX_3;
+		filter_packet <= !good3;
+	     end
+	     else begin
+		mx_state <= MX_IDLE;
+		filter_packet <= 0;
+	     end
+	 
+	 MX_1 :
+	   if(o_tready_int & o_tvalid_int & o_tlast_int)
+	     if(PRIO)
+	       mx_state <= MX_IDLE;
+	     else if(i2_tvalid) begin    
+		mx_state <= MX_2;
+		filter_packet <= !good2;
+	     end
+	     else if(i3_tvalid) begin    
+		mx_state <= MX_3;
+		filter_packet <= !good3;
+	     end
+	     else begin
+		mx_state <= MX_IDLE;
+		filter_packet <= 0;
+	     end
+	 MX_2 :
+	   if(o_tready_int & o_tvalid_int & o_tlast_int)
+	     if(PRIO)
+	       mx_state <= MX_IDLE;
+	     else if(i3_tvalid) begin    
+		mx_state <= MX_3;
+		filter_packet <= !good3;
+	     end
+	     else begin
+		mx_state <= MX_IDLE;
+	 	filter_packet <= 0;
+	     end
+	 MX_3 :
+	   if(o_tready_int & o_tvalid_int & o_tlast_int)
+	     begin
+		mx_state <= MX_IDLE;
+		filter_packet <= 0;
+	     end
+	 	 
+	 default :
+	   mx_state <= MX_IDLE;
+       endcase // case (mx_state)
+
+   assign {i3_tready, i2_tready, i1_tready, i0_tready} = mx_state & {4{o_tready_int}};
+
+   assign o_tvalid_int = |(mx_state & ({i3_tvalid, i2_tvalid, i1_tvalid, i0_tvalid}));
+         
+   assign {o_tlast_int, o_tdata_int} = mx_state[3] ? {i3_tlast, i3_tdata} :
+				       mx_state[2] ? {i2_tlast, i2_tdata} :
+				       mx_state[1] ? {i1_tlast, i1_tdata} :
+				       {i0_tlast, i0_tdata};
+
+   generate
+      if(BUFFER == 0)
+	begin
+	   assign o_tdata = o_tdata_int;
+	   assign o_tlast = o_tlast_int;
+	   assign o_tvalid = o_tvalid_int & !filter_packet;
+	   assign o_tready_int = o_tready | filter_packet;
+	end
+      else
+	begin
+	   wire o_tready_int_fifo;
+	   assign o_tready_int =  o_tready_int_fifo | filter_packet;
+	   
+           axi_fifo_short #(.WIDTH(WIDTH+1)) axi_fifo_short
+	     (.clk(clk), .reset(reset), .clear(clear),
+	      .i_tdata({o_tlast_int,o_tdata_int}), .i_tvalid(o_tvalid_int & !filter_packet), .i_tready(o_tready_int_fifo),
+	      .o_tdata({o_tlast,o_tdata}), .o_tvalid(o_tvalid), .o_tready(o_tready),
+	      .space(), .occupied());
+	end
+   endgenerate
+   
+endmodule // axi__mux4
diff --git a/fpga/usrp3/lib/fifo/axi_loopback.v b/fpga/usrp3/lib/fifo/axi_loopback.v
new file mode 100644
index 000000000..f80288a73
--- /dev/null
+++ b/fpga/usrp3/lib/fifo/axi_loopback.v
@@ -0,0 +1,75 @@
+//
+// Copyright 2012 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+//
+// axi_loopback.v
+//
+// Loopback all data assuming it's in CHDR format, and swap SRC/DST in the SID in the process
+// thus reflecting it back to it's origin...in theory!
+//
+
+module axi_loopback
+ #(
+   parameter WIDTH = 64
+  )
+  (
+   input clk,
+   input reset,
+   // Input AXIS
+   input [WIDTH-1:0] i_tdata,
+   input i_tlast,
+   input i_tvalid,
+   output i_tready,
+   // Output AXIS
+   output [WIDTH-1:0] o_tdata,
+   output o_tlast,
+   output o_tvalid,
+   input o_tready
+   );
+
+   wire [WIDTH-1:0]     fifoin_tdata,fifoout_tdata,dmux_tdata;
+   wire                 fifoin_tlast,dmux_tlast;
+   wire                 fifoin_tvalid,dmux_tvalid;
+   wire                 fifoin_tready,dmux_tready;
+   
+   // Since most real endpoints go via Demux4 place one in here to look for bugs.
+   axi_demux4 #(.ACTIVE_CHAN(4'b0001), .WIDTH(WIDTH)) demux
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .header(), .dest(2'b00),
+      .i_tdata(i_tdata), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready),
+      .o0_tdata(dmux_tdata), .o0_tlast(dmux_tlast), .o0_tvalid(dmux_tvalid), .o0_tready(dmux_tready), 
+      .o1_tdata(), .o1_tlast(), .o1_tvalid(), .o1_tready(1'b1), 
+      .o2_tdata(), .o2_tlast(), .o2_tvalid(), .o2_tready(1'b1), 
+      .o3_tdata(), .o3_tlast(), .o3_tvalid(), .o3_tready(1'b1));
+
+   axi_fifo_short #(.WIDTH(WIDTH+1)) axi_fifo_short1
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata({dmux_tlast,dmux_tdata}), .i_tvalid(dmux_tvalid), .i_tready(dmux_tready),
+      .o_tdata({fifoin_tlast,fifoin_tdata}), .o_tvalid(fifoin_tvalid), .o_tready(fifoin_tready),
+      .space(), .occupied());
+
+   reg header;
+   always @(posedge clk) begin
+     if(reset) begin
+       header <= 1'b1;
+     end else if (header) begin
+       if(fifoin_tvalid & fifoin_tready & ~fifoin_tlast) header <= 1'b0;
+     end else begin
+       if(fifoin_tvalid & fifoin_tready & fifoin_tlast) header <= 1'b1;
+     end
+   end
+
+   assign fifoout_tdata = header ? 
+			       {fifoin_tdata[63:32] ,fifoin_tdata[15:0],fifoin_tdata[31:16]} :
+			       fifoin_tdata;
+   
+   axi_fifo_short #(.WIDTH(WIDTH+1)) axi_fifo_short2
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata({fifoin_tlast,fifoout_tdata}), .i_tvalid(fifoin_tvalid), .i_tready(fifoin_tready),
+      .o_tdata({o_tlast,o_tdata}), .o_tvalid(o_tvalid), .o_tready(o_tready),
+      .space(), .occupied());
+
+endmodule // axi_loopback
diff --git a/fpga/usrp3/lib/fifo/axi_mux.v b/fpga/usrp3/lib/fifo/axi_mux.v
new file mode 100644
index 000000000..72a771348
--- /dev/null
+++ b/fpga/usrp3/lib/fifo/axi_mux.v
@@ -0,0 +1,110 @@
+
+// Copyright 2016 Ettus Research
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+
+// axi_mux -- takes arbitrary number of AXI stream, merges them to 1 output channel
+// Round-robin if PRIO=0, priority if PRIO=1 (lower number ports get priority)
+// Bubble cycles are inserted after each packet
+
+module axi_mux
+  #(parameter PRIO=0,
+    parameter WIDTH=64,
+    parameter PRE_FIFO_SIZE=0,
+    parameter POST_FIFO_SIZE=0,
+    parameter SIZE=4)
+   (input clk, input reset, input clear,
+    input [(WIDTH*SIZE)-1:0] i_tdata, input [SIZE-1:0] i_tlast, input [SIZE-1:0] i_tvalid, output [SIZE-1:0] i_tready,
+    output [WIDTH-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready);
+
+   wire [WIDTH*SIZE-1:0] i_tdata_int;
+   wire [SIZE-1:0] i_tlast_int, i_tvalid_int, i_tready_int;
+
+   wire [WIDTH-1:0] o_tdata_int;
+   wire o_tlast_int, o_tvalid_int, o_tready_int;
+
+   reg [$clog2(SIZE)-1:0] 	       st_port;
+   reg 		       st_active;
+
+  genvar n;
+  generate
+    if (PRE_FIFO_SIZE == 0) begin
+      assign i_tdata_int  = i_tdata;
+      assign i_tlast_int  = i_tlast;
+      assign i_tvalid_int = i_tvalid;
+      assign i_tready     = i_tready_int;
+    end else begin
+      for (n = 0; n < SIZE; n = n + 1) begin
+        axi_fifo #(.WIDTH(WIDTH+1), .SIZE(PRE_FIFO_SIZE)) axi_fifo (
+          .clk(clk), .reset(reset), .clear(clear),
+          .i_tdata({i_tlast[n],i_tdata[WIDTH*(n+1)-1:WIDTH*n]}), .i_tvalid(i_tvalid[n]), .i_tready(i_tready[n]),
+          .o_tdata({i_tlast_int[n],i_tdata_int[WIDTH*(n+1)-1:WIDTH*n]}), .o_tvalid(i_tvalid_int[n]), .o_tready(i_tready_int[n]),
+          .space(), .occupied());
+      end
+    end
+  endgenerate
+
+   always @(posedge clk)
+     if(reset)
+       begin
+	  st_port <= 0;
+	  st_active <= 1'b0;
+       end
+     else
+       if(st_active)
+	 begin
+	    if(o_tlast_int & o_tvalid_int & o_tready_int)
+	      begin
+		 st_active <= 1'b0;
+		 if((PRIO != 0) | (st_port == (SIZE-1)))
+		   st_port <= 0;
+		 else
+		   st_port <= st_port + 1;
+	      end
+	 end // if (st_active)
+       else
+	 if(i_tvalid_int[st_port])
+	   st_active <= 1'b1;
+	 else
+	   if(st_port == (SIZE-1))
+	     st_port <= 0;
+	   else
+	     st_port <= st_port + 1;
+   
+   genvar 		 i;
+   generate
+      for(i=0;i<SIZE;i=i+1)
+	begin : gen1
+	   assign i_tready_int[i] = st_active & o_tready_int & (st_port == i);
+	end
+   endgenerate
+
+   assign o_tvalid_int = st_active & i_tvalid_int[st_port];
+   assign o_tlast_int = i_tlast_int[st_port];
+
+   genvar 		 j;
+   generate
+      for (j=0;j<WIDTH;j=j+1)
+	begin : gen2
+	   assign o_tdata_int[j] = i_tdata_int[st_port*WIDTH+j];
+	end
+   endgenerate
+   
+   generate
+      if(POST_FIFO_SIZE == 0)
+	begin
+	   assign o_tdata = o_tdata_int;
+	   assign o_tlast = o_tlast_int;
+	   assign o_tvalid = o_tvalid_int;
+	   assign o_tready_int = o_tready;
+	end
+      else
+	axi_fifo #(.WIDTH(WIDTH+1),.SIZE(POST_FIFO_SIZE)) axi_fifo
+	  (.clk(clk), .reset(reset), .clear(clear),
+	   .i_tdata({o_tlast_int,o_tdata_int}), .i_tvalid(o_tvalid_int), .i_tready(o_tready_int),
+	   .o_tdata({o_tlast,o_tdata}), .o_tvalid(o_tvalid), .o_tready(o_tready),
+	   .space(), .occupied());
+   endgenerate
+   
+endmodule // axi__mux
diff --git a/fpga/usrp3/lib/fifo/axi_mux4.v b/fpga/usrp3/lib/fifo/axi_mux4.v
new file mode 100644
index 000000000..1bc603e90
--- /dev/null
+++ b/fpga/usrp3/lib/fifo/axi_mux4.v
@@ -0,0 +1,115 @@
+
+// Copyright 2012 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// axi_mux -- takes 4 64-bit AXI stream, merges them to 1 output channel
+// Round-robin if PRIO=0, priority if PRIO=1 (lower number ports get priority)
+// Bubble cycles are inserted after each packet in PRIO mode, or on wraparound in Round Robin mode
+
+module axi_mux4
+  #(parameter PRIO=0,
+    parameter WIDTH=64,
+    parameter BUFFER=0)
+   (input clk, input reset, input clear,
+    input [WIDTH-1:0] i0_tdata, input i0_tlast, input i0_tvalid, output i0_tready,
+    input [WIDTH-1:0] i1_tdata, input i1_tlast, input i1_tvalid, output i1_tready,
+    input [WIDTH-1:0] i2_tdata, input i2_tlast, input i2_tvalid, output i2_tready,
+    input [WIDTH-1:0] i3_tdata, input i3_tlast, input i3_tvalid, output i3_tready,
+    output [WIDTH-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready);
+
+   wire [WIDTH-1:0]    o_tdata_int;
+   wire 	       o_tlast_int, o_tvalid_int, o_tready_int;
+   
+   reg [3:0] 	  mx_state;
+   localparam MX_IDLE = 4'b0000;
+   localparam MX_0    = 4'b0001;
+   localparam MX_1    = 4'b0010;
+   localparam MX_2    = 4'b0100;
+   localparam MX_3    = 4'b1000;
+
+   always @(posedge clk)
+     if(reset | clear)
+       mx_state <= MX_IDLE;
+     else
+       case (mx_state)
+	 MX_IDLE :
+	   if(i0_tvalid)
+	     mx_state <= MX_0;
+	   else if(i1_tvalid)
+	     mx_state <= MX_1;
+	   else if(i2_tvalid)
+	     mx_state <= MX_2;
+	   else if(i3_tvalid)
+	     mx_state <= MX_3;
+
+	 MX_0 :
+	   if(o_tready_int & o_tvalid_int & o_tlast_int)
+	     if(PRIO)
+	       mx_state <= MX_IDLE;
+	     else if(i1_tvalid)
+	       mx_state <= MX_1;
+	     else if(i2_tvalid)
+	       mx_state <= MX_2;
+	     else if(i3_tvalid)
+	       mx_state <= MX_3;
+	     else
+	       mx_state <= MX_IDLE;
+	 	 
+	 MX_1 :
+	   if(o_tready_int & o_tvalid_int & o_tlast_int)
+	     if(PRIO)
+	       mx_state <= MX_IDLE;
+	     else if(i2_tvalid)
+	       mx_state <= MX_2;
+	     else if(i3_tvalid)
+	       mx_state <= MX_3;
+	     else
+	       mx_state <= MX_IDLE;
+
+	 MX_2 :
+	   if(o_tready_int & o_tvalid_int & o_tlast_int)
+	     if(PRIO)
+	       mx_state <= MX_IDLE;
+	     else if(i3_tvalid)
+	       mx_state <= MX_3;
+	     else
+	       mx_state <= MX_IDLE;
+	 	 
+	 MX_3 :
+	   if(o_tready_int & o_tvalid_int & o_tlast_int)
+	     if(PRIO)
+	       mx_state <= MX_IDLE;
+	     else
+	       mx_state <= MX_IDLE;
+	 	 
+	 default :
+	   mx_state <= MX_IDLE;
+       endcase // case (mx_state)
+
+   assign {i3_tready, i2_tready, i1_tready, i0_tready} = mx_state & {4{o_tready_int}};
+
+   assign o_tvalid_int = |(mx_state & ({i3_tvalid, i2_tvalid, i1_tvalid, i0_tvalid}));
+         
+   assign {o_tlast_int, o_tdata_int} = mx_state[3] ? {i3_tlast, i3_tdata} :
+				       mx_state[2] ? {i2_tlast, i2_tdata} :
+				       mx_state[1] ? {i1_tlast, i1_tdata} :
+				       {i0_tlast, i0_tdata};
+
+   generate
+      if(BUFFER == 0)
+	begin
+	   assign o_tdata = o_tdata_int;
+	   assign o_tlast = o_tlast_int;
+	   assign o_tvalid = o_tvalid_int;
+	   assign o_tready_int = o_tready;
+	end
+      else
+	axi_fifo_flop2 #(.WIDTH(WIDTH+1)) axi_fifo_flop2
+	  (.clk(clk), .reset(reset), .clear(clear),
+	   .i_tdata({o_tlast_int,o_tdata_int}), .i_tvalid(o_tvalid_int), .i_tready(o_tready_int),
+	   .o_tdata({o_tlast,o_tdata}), .o_tvalid(o_tvalid), .o_tready(o_tready),
+	   .space(), .occupied());
+   endgenerate
+   
+endmodule // axi__mux4
diff --git a/fpga/usrp3/lib/fifo/axi_mux8.v b/fpga/usrp3/lib/fifo/axi_mux8.v
new file mode 100644
index 000000000..cfcce6f8f
--- /dev/null
+++ b/fpga/usrp3/lib/fifo/axi_mux8.v
@@ -0,0 +1,59 @@
+
+// Copyright 2012 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// axi_mux -- takes 8 64-bit AXI stream, merges them to 1 output channel
+// Round-robin if PRIO=0, priority if PRIO=1 (lower number ports get priority)
+// Bubble cycles are inserted after each packet in PRIO mode, or on wraparound in Round Robin mode
+
+module axi_mux8 #(
+   parameter PRIO=0,
+   parameter WIDTH=64,
+   parameter BUFFER=0
+) (
+   input clk, input reset, input clear,
+   input [WIDTH-1:0] i0_tdata, input i0_tlast, input i0_tvalid, output i0_tready,
+   input [WIDTH-1:0] i1_tdata, input i1_tlast, input i1_tvalid, output i1_tready,
+   input [WIDTH-1:0] i2_tdata, input i2_tlast, input i2_tvalid, output i2_tready,
+   input [WIDTH-1:0] i3_tdata, input i3_tlast, input i3_tvalid, output i3_tready,
+   input [WIDTH-1:0] i4_tdata, input i4_tlast, input i4_tvalid, output i4_tready,
+   input [WIDTH-1:0] i5_tdata, input i5_tlast, input i5_tvalid, output i5_tready,
+   input [WIDTH-1:0] i6_tdata, input i6_tlast, input i6_tvalid, output i6_tready,
+   input [WIDTH-1:0] i7_tdata, input i7_tlast, input i7_tvalid, output i7_tready,
+   output [WIDTH-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready
+);
+
+   wire [WIDTH-1:0]  o_tdata_int0, o_tdata_int1;
+   wire              o_tlast_int0, o_tlast_int1;
+   wire              o_tvalid_int0, o_tvalid_int1;
+   wire              o_tready_int0, o_tready_int1;
+
+   axi_mux4 #(.PRIO(PRIO), .WIDTH(WIDTH), .BUFFER(0)) mux4_int0 (
+      .clk(clk), .reset(reset), .clear(clear),
+      .i0_tdata(i0_tdata), .i0_tlast(i0_tlast), .i0_tvalid(i0_tvalid), .i0_tready(i0_tready),
+      .i1_tdata(i1_tdata), .i1_tlast(i1_tlast), .i1_tvalid(i1_tvalid), .i1_tready(i1_tready),
+      .i2_tdata(i2_tdata), .i2_tlast(i2_tlast), .i2_tvalid(i2_tvalid), .i2_tready(i2_tready),
+      .i3_tdata(i3_tdata), .i3_tlast(i3_tlast), .i3_tvalid(i3_tvalid), .i3_tready(i3_tready),
+      .o_tdata(o_tdata_int0), .o_tlast(o_tlast_int0), .o_tvalid(o_tvalid_int0), .o_tready(o_tready_int0)
+   );
+
+   axi_mux4 #(.PRIO(PRIO), .WIDTH(WIDTH), .BUFFER(0)) mux4_int1 (
+      .clk(clk), .reset(reset), .clear(clear),
+      .i0_tdata(i4_tdata), .i0_tlast(i4_tlast), .i0_tvalid(i4_tvalid), .i0_tready(i4_tready),
+      .i1_tdata(i5_tdata), .i1_tlast(i5_tlast), .i1_tvalid(i5_tvalid), .i1_tready(i5_tready),
+      .i2_tdata(i6_tdata), .i2_tlast(i6_tlast), .i2_tvalid(i6_tvalid), .i2_tready(i6_tready),
+      .i3_tdata(i7_tdata), .i3_tlast(i7_tlast), .i3_tvalid(i7_tvalid), .i3_tready(i7_tready),
+      .o_tdata(o_tdata_int1), .o_tlast(o_tlast_int1), .o_tvalid(o_tvalid_int1), .o_tready(o_tready_int1)
+   );
+
+   axi_mux4 #(.PRIO(PRIO), .WIDTH(WIDTH), .BUFFER(BUFFER)) mux2 (
+      .clk(clk), .reset(reset), .clear(clear),
+      .i0_tdata(o_tdata_int0), .i0_tlast(o_tlast_int0), .i0_tvalid(o_tvalid_int0), .i0_tready(o_tready_int0),
+      .i1_tdata(o_tdata_int1), .i1_tlast(o_tlast_int1), .i1_tvalid(o_tvalid_int1), .i1_tready(o_tready_int1),
+      .i2_tdata(0), .i2_tlast(1'b0), .i2_tvalid(1'b0), .i2_tready(),
+      .i3_tdata(0), .i3_tlast(1'b0), .i3_tvalid(1'b0), .i3_tready(),
+      .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready)
+   );
+
+endmodule // axi_mux8
diff --git a/fpga/usrp3/lib/fifo/axi_mux_select.v b/fpga/usrp3/lib/fifo/axi_mux_select.v
new file mode 100644
index 000000000..d3c38ba30
--- /dev/null
+++ b/fpga/usrp3/lib/fifo/axi_mux_select.v
@@ -0,0 +1,104 @@
+//
+// Copyright 2016 Ettus Research
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// AXI-Stream multipler with select line
+//
+
+module axi_mux_select #(
+  parameter WIDTH = 32,
+  parameter PRE_FIFO_SIZE = 0,
+  parameter POST_FIFO_SIZE = 0,
+  parameter SWITCH_ON_LAST = 0, // Wait until tlast is asserted before updating
+  parameter SIZE = 4)
+(
+  input clk, input reset, input clear,
+  input [$clog2(SIZE)-1:0] select,
+  input [SIZE*WIDTH-1:0] i_tdata, input [SIZE-1:0] i_tlast, input [SIZE-1:0] i_tvalid, output [SIZE-1:0] i_tready,
+  output [WIDTH-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready
+);
+
+  wire [WIDTH*SIZE-1:0] i_tdata_int;
+  wire [WIDTH-1:0] i_tdata_arr[0:SIZE-1];
+  wire [SIZE-1:0] i_tlast_int, i_tvalid_int, i_tready_int;
+
+  wire [WIDTH-1:0] o_tdata_int;
+  wire o_tlast_int, o_tvalid_int, o_tready_int;
+
+  genvar n;
+  generate
+    if (PRE_FIFO_SIZE == 0) begin
+      assign i_tdata_int  = i_tdata;
+      assign i_tlast_int  = i_tlast;
+      assign i_tvalid_int = i_tvalid;
+      assign i_tready     = i_tready_int;
+    end else begin
+      for (n = 0; n < SIZE; n = n + 1) begin
+        axi_fifo #(.WIDTH(WIDTH+1), .SIZE(PRE_FIFO_SIZE)) axi_fifo (
+          .clk(clk), .reset(reset), .clear(clear),
+          .i_tdata({i_tlast[n],i_tdata[WIDTH*(n+1)-1:WIDTH*n]}), .i_tvalid(i_tvalid[n]), .i_tready(i_tready[n]),
+          .o_tdata({i_tlast_int[n],i_tdata_int[WIDTH*(n+1)-1:WIDTH*n]}), .o_tvalid(i_tvalid_int[n]), .o_tready(i_tready_int[n]),
+          .space(), .occupied());
+      end
+    end
+  endgenerate
+
+  // Make arrays for easier muxing
+  genvar i;
+  generate
+    for (i = 0; i < SIZE; i = i + 1) begin
+      assign i_tdata_arr[i] = i_tdata_int[WIDTH*(i+1)-1:WIDTH*i];
+    end
+  endgenerate
+
+  // Switch select line either immediately or after the last word in a packet
+  reg [$clog2(SIZE)-1:0] select_hold;
+  generate
+    if (SWITCH_ON_LAST) begin
+      reg init;
+      always @(posedge clk) begin
+        if (reset | clear) begin
+          init        <= 1'b0;
+          select_hold <= 'd0;
+        end else begin
+          if (|i_tvalid) begin
+            init        <= 1'b1;
+          end
+          // Set select any time after reset and before the first packet OR
+          // at the end of a packet
+          if (~init | (o_tlast_int & o_tvalid_int & o_tready_int)) begin
+            select_hold <= select;
+          end
+        end
+      end
+    end else begin
+      always @(*) begin
+        select_hold <= select;
+      end
+    end
+  endgenerate
+
+  // Mux
+  assign o_tdata_int  = i_tdata_arr[select_hold];
+  assign o_tlast_int  = i_tlast_int[select_hold];
+  assign o_tvalid_int = i_tvalid_int[select_hold];
+  assign i_tready_int = (1'b1 << select_hold) & {SIZE{o_tready_int}};
+
+  generate
+    if(POST_FIFO_SIZE == 0) begin
+      assign o_tdata = o_tdata_int;
+      assign o_tlast = o_tlast_int;
+      assign o_tvalid = o_tvalid_int;
+      assign o_tready_int = o_tready;
+    end else begin
+      axi_fifo #(.WIDTH(WIDTH+1),.SIZE(POST_FIFO_SIZE)) axi_fifo (
+        .clk(clk), .reset(reset), .clear(clear),
+        .i_tdata({o_tlast_int,o_tdata_int}), .i_tvalid(o_tvalid_int), .i_tready(o_tready_int),
+        .o_tdata({o_tlast,o_tdata}), .o_tvalid(o_tvalid), .o_tready(o_tready),
+        .space(), .occupied());
+    end
+  endgenerate
+
+endmodule
\ No newline at end of file
diff --git a/fpga/usrp3/lib/fifo/axi_packet_gate.v b/fpga/usrp3/lib/fifo/axi_packet_gate.v
new file mode 100644
index 000000000..771fb2200
--- /dev/null
+++ b/fpga/usrp3/lib/fifo/axi_packet_gate.v
@@ -0,0 +1,229 @@
+//
+// Copyright 2012 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Description:
+//   Holds packets in a FIFO until they are complete. This allows buffering 
+//   slowly-built packets so they don't clog up downstream logic. If o_tready
+//   is held high, this module guarantees that o_tvalid will not be deasserted
+//   until a full packet is transferred. This module can also optionally drop
+//   a packet if the i_terror bit is asserted along with i_tlast. This allows
+//   discarding packet, say, if a CRC check fails.
+//   NOTE:
+//   - The maximum size of a packet that can pass through this module is
+//     2^SIZE lines. If a larger packet is sent, this module will lock up.
+//   - Assuming that upstream is valid and downstream is ready, the maximum 
+//     in to out latency per packet  is (2^SIZE + 2) clock cycles. 
+//     2^SIZE because this module gates a packet, 1 cycle for the RAM read and
+//     1 more cycle for the output register. This is not guaranteed behavior though.
+//   - The USE_AS_BUFF parameter can be used to treat this packet gate as
+//     a multi-packet buffer. When USE_AS_BUFF=0, the max number of packets 
+//     (regardless of size) that the module can store is 2. When USE_AS_BUFF=1,
+//     the entire storage of this module can be used to buffer packets but at
+//     the cost of some additional RAM. Beware the sequence of (big packet,
+//     small packet, small packet), as some outside buffering may be needed
+//     to handle this case if USE_AS_BUFF=0.
+
+module axi_packet_gate #(
+  parameter WIDTH       = 64,   // Width of datapath
+  parameter SIZE        = 10,   // log2 of the buffer size (must be >= MTU of packet)
+  parameter USE_AS_BUFF = 0,    // Allow the packet gate to be used as a buffer (uses more RAM)
+  parameter MIN_PKT_SIZE= 0     // log2 of minimum valid packet size (rounded down, used to reduce addr fifo size)
+) (
+  input  wire             clk, 
+  input  wire             reset, 
+  input  wire             clear,
+  input  wire [WIDTH-1:0] i_tdata,
+  input  wire             i_tlast,
+  input  wire             i_terror,
+  input  wire             i_tvalid,
+  output wire             i_tready,
+  output reg  [WIDTH-1:0] o_tdata = {WIDTH{1'b0}},
+  output reg              o_tlast = 1'b0,
+  output reg              o_tvalid = 1'b0,
+  input  wire             o_tready
+);
+
+  localparam [SIZE-1:0] ADDR_ZERO = {SIZE{1'b0}};
+  localparam [SIZE-1:0] ADDR_ONE  = {{(SIZE-1){1'b0}}, 1'b1};
+
+  // -------------------------------------------
+  // RAM block that will hold pkts
+  // -------------------------------------------
+  wire            wr_en, rd_en;
+  wire [WIDTH:0]  wr_data, rd_data;
+  reg  [SIZE-1:0] wr_addr = ADDR_ZERO, rd_addr = ADDR_ZERO;
+
+  // Threshold to explicitly instantiate LUTRAM
+  localparam LUTRAM_THRESH = 5;
+
+  // We need to instantiate a simple dual-port RAM here so
+  // we use the ram_2port module with one read port and one
+  // write port and "NO-CHANGE" mode.
+  ram_2port #(
+    .DWIDTH (WIDTH+1), .AWIDTH(SIZE),
+    .RW_MODE("NO-CHANGE"), .OUT_REG(0),
+    .RAM_TYPE(SIZE <= LUTRAM_THRESH ? "LUTRAM" : "AUTOMATIC")
+  ) ram_i (
+    .clka (clk), .ena(1'b1), .wea(wr_en),
+    .addra(wr_addr), .dia(wr_data), .doa(),
+    .clkb (clk), .enb(rd_en), .web(1'b0),
+    .addrb(rd_addr), .dib({WIDTH{1'b0}}), .dob(rd_data)
+  );
+
+  // FIFO empty/full logic. The condition for both
+  // empty and full is when rd_addr == wr_addr. However,
+  // it matters if we approach that case from the low side
+  // or the high side. So keep track of the almost empty/full
+  // state for determine if the next transaction will cause
+  // the FIFO to be truly empty or full.
+  reg  ram_full = 1'b0, ram_empty = 1'b1;
+  wire almost_full  = (wr_addr == rd_addr - ADDR_ONE);
+  wire almost_empty = (wr_addr == rd_addr + ADDR_ONE);
+
+  always @(posedge clk) begin
+    if (reset | clear) begin
+      ram_full <= 1'b0;
+    end else begin
+      if (almost_full) begin
+        if (wr_en & ~rd_en)
+          ram_full <= 1'b1;
+      end else begin
+        if (~wr_en & rd_en)
+          ram_full <= 1'b0;
+      end
+    end
+  end
+
+  always @(posedge clk) begin
+    if (reset | clear) begin
+      ram_empty <= 1'b1;
+    end else begin
+      if (almost_empty) begin
+        if (rd_en & ~wr_en)
+          ram_empty <= 1'b1;
+      end else begin
+        if (~rd_en & wr_en)
+          ram_empty <= 1'b0;
+      end
+    end
+  end
+
+  // -------------------------------------------
+  // Address FIFO
+  // -------------------------------------------
+  // The address FIFO will hold the write address
+  // for the last line in a non-errant packet
+  
+  wire [SIZE-1:0] afifo_i_tdata, afifo_o_tdata, afifo_p_tdata;
+  wire            afifo_i_tvalid, afifo_i_tready;
+  wire            afifo_o_tvalid, afifo_o_tready;
+  wire            afifo_p_tvalid, afifo_p_tready;
+
+  axi_fifo #(.WIDTH(SIZE), .SIZE(USE_AS_BUFF==1 ? SIZE-MIN_PKT_SIZE : 1)) addr_fifo_i (
+    .clk(clk), .reset(reset), .clear(clear),
+    .i_tdata(afifo_i_tdata), .i_tvalid(afifo_i_tvalid), .i_tready(afifo_i_tready),
+    .o_tdata(afifo_p_tdata), .o_tvalid(afifo_p_tvalid), .o_tready(afifo_p_tready),
+    .space(), .occupied()
+  );
+
+  axi_fifo #(.WIDTH(SIZE), .SIZE(1)) addr_fifo_pipe_i (
+    .clk(clk), .reset(reset), .clear(clear),
+    .i_tdata(afifo_p_tdata), .i_tvalid(afifo_p_tvalid), .i_tready(afifo_p_tready),
+    .o_tdata(afifo_o_tdata), .o_tvalid(afifo_o_tvalid), .o_tready(afifo_o_tready),
+    .space(), .occupied()
+  );
+
+  // -------------------------------------------
+  // Write state machine
+  // -------------------------------------------
+  reg  [SIZE-1:0] wr_head_addr  = ADDR_ZERO;
+
+  assign i_tready = ~ram_full & afifo_i_tready;
+  assign wr_en    = i_tvalid & i_tready;
+  assign wr_data  = {i_tlast, i_tdata};
+
+  always @(posedge clk) begin
+    if (reset | clear) begin
+      wr_addr <= ADDR_ZERO;
+      wr_head_addr <= ADDR_ZERO;
+    end else begin
+      if (wr_en) begin
+        if (i_tlast) begin
+          if (i_terror) begin
+            // Incoming packet had an error. Rewind the write
+            // pointer and pretend that a packet never came in.
+            wr_addr <= wr_head_addr;
+          end else begin
+            // Incoming packet had no error, advance wr_addr and
+            // wr_head_addr for the next packet.
+            wr_addr <= wr_addr + ADDR_ONE;
+            wr_head_addr <= wr_addr + ADDR_ONE;
+          end
+        end else begin
+          // Packet is still in progress, only update wr_addr
+          wr_addr <= wr_addr + ADDR_ONE;
+        end
+      end
+    end
+  end
+
+  // Push the write address to the address FIFO if
+  // - It is the last one in the packet
+  // - The packet has no errors
+  assign afifo_i_tdata  = wr_addr;
+  assign afifo_i_tvalid = ~ram_full & i_tvalid & i_tlast & ~i_terror;
+
+  // -------------------------------------------
+  // Read state machine
+  // -------------------------------------------
+  reg    rd_data_valid = 1'b0;
+  wire   update_out_reg;
+  // Data can be read if there is a valid last address in the
+  // address FIFO (signifying the end of an input packet) and
+  // if there is data available in RAM
+  wire   ready_to_read = (~ram_empty) & afifo_o_tvalid;
+  // Pop from address FIFO once we have see the end of the pkt
+  assign afifo_o_tready = rd_en & (afifo_o_tdata == rd_addr);
+
+  // Read from RAM if
+  // - A full packet has been written AND
+  // - Output data is not valid OR is currently being transferred
+  assign rd_en = ready_to_read & (update_out_reg | ~rd_data_valid);
+
+  always @(posedge clk) begin
+    if (reset | clear) begin
+      rd_data_valid <= 1'b0;
+      rd_addr <= ADDR_ZERO;
+    end else begin
+      if (update_out_reg | ~rd_data_valid) begin
+        // Output data is not valid OR is currently being transferred
+        if (ready_to_read) begin
+          rd_data_valid <= 1'b1;
+          rd_addr <= rd_addr + ADDR_ONE;
+        end else begin
+          rd_data_valid <= 1'b0;  // Don't read
+        end
+      end
+    end
+  end
+
+  // Instantiate an output register to break critical paths starting
+  // at the RAM module. When ram_2port is inferred as BRAM, the tools
+  // should absorb this register into the BRAM block without using
+  // SLICE resources.
+  always @(posedge clk) begin
+    if (reset | clear) begin
+      o_tvalid <= 1'b0;
+    end else if (update_out_reg) begin
+      o_tvalid <= rd_data_valid;
+      {o_tlast, o_tdata} <= rd_data;
+    end
+  end
+  // Update the output reg only *after* the downstream
+  // block has consumed the current value
+  assign update_out_reg = o_tready | ~o_tvalid;
+
+endmodule
diff --git a/fpga/usrp3/lib/fifo/axis_fifo_monitor.v b/fpga/usrp3/lib/fifo/axis_fifo_monitor.v
new file mode 100644
index 000000000..e3bb2c633
--- /dev/null
+++ b/fpga/usrp3/lib/fifo/axis_fifo_monitor.v
@@ -0,0 +1,66 @@
+//
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Description:
+//   This module is instantiated in parallel with a FIFO with AXI4-STREAM interfaces.
+//   It tracks how many complete packets are contained within the FIFO, and also indicates
+//   when the first word of a packet is presented on the FIFO outputs.
+
+module axis_fifo_monitor #(
+  parameter COUNT_W = 32
+)(
+  // Clocks and resets
+  input  wire               clk,
+  input  wire               reset,
+  // FIFO Input      
+  input  wire               i_tlast,
+  input  wire               i_tvalid,
+  input  wire               i_tready,
+  // FIFO Output      
+  input  wire               o_tlast,
+  input  wire               o_tvalid,
+  input  wire               o_tready,
+  // FIFO Stats
+  output wire               i_sop,
+  output wire               i_eop,
+  output wire               o_sop,
+  output wire               o_eop,
+  output wire [COUNT_W-1:0] occupied,
+  output wire [COUNT_W-1:0] occupied_pkts
+);
+
+  wire [COUNT_W-1:0] i_pkt_count, o_pkt_count;
+  wire [COUNT_W-1:0] i_xfer_count, o_xfer_count;
+
+  axis_strm_monitor #(
+    .WIDTH(1), .COUNT_W(COUNT_W),
+    .PKT_LENGTH_EN(0), .PKT_CHKSUM_EN(0),
+    .PKT_COUNT_EN(1), .XFER_COUNT_EN(1)
+  ) input_monitor (
+    .clk(clk), .reset(reset),
+    .axis_tdata(1'b0), .axis_tlast(i_tlast), .axis_tvalid(i_tvalid), .axis_tready(i_tready),
+    .sop(i_sop), .eop(i_eop),
+    .pkt_length(), .pkt_chksum(),
+    .pkt_count(i_pkt_count), .xfer_count(i_xfer_count)
+  );
+
+  axis_strm_monitor #(
+    .WIDTH(1), .COUNT_W(COUNT_W),
+    .PKT_LENGTH_EN(0), .PKT_CHKSUM_EN(0),
+    .PKT_COUNT_EN(1), .XFER_COUNT_EN(1)
+  ) output_monitor (
+    .clk(clk), .reset(reset),
+    .axis_tdata(1'b0), .axis_tlast(o_tlast), .axis_tvalid(o_tvalid), .axis_tready(o_tready),
+    .sop(o_sop), .eop(o_eop),
+    .pkt_length(), .pkt_chksum(),
+    .pkt_count(o_pkt_count), .xfer_count(o_xfer_count)
+  );
+
+  // Count packets in FIFO.
+  // No protection on counter wrap, 
+  assign occupied      = (i_xfer_count - o_xfer_count);
+  assign occupied_pkts = (i_pkt_count  - o_pkt_count);
+
+ endmodule
\ No newline at end of file
diff --git a/fpga/usrp3/lib/fifo/axis_strm_monitor.v b/fpga/usrp3/lib/fifo/axis_strm_monitor.v
new file mode 100644
index 000000000..68e4cf5bf
--- /dev/null
+++ b/fpga/usrp3/lib/fifo/axis_strm_monitor.v
@@ -0,0 +1,110 @@
+//
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Description:
+//   A module to monitor a an AXI-Stream link and gather various
+//   metric about packets and the stream in general
+
+module axis_strm_monitor #(
+  parameter WIDTH         = 64,
+  parameter COUNT_W       = 32,
+  parameter PKT_LENGTH_EN = 0,
+  parameter PKT_CHKSUM_EN = 0,
+  parameter PKT_COUNT_EN  = 0,
+  parameter XFER_COUNT_EN = 0
+)(
+  // Clocks and resets
+  input  wire               clk,
+  input  wire               reset,
+  // Stream to monitor      
+  input  wire [WIDTH-1:0]   axis_tdata,
+  input  wire               axis_tlast,
+  input  wire               axis_tvalid,
+  input  wire               axis_tready,
+  // Packet Stats
+  output wire               sop,
+  output wire               eop,
+  output reg  [15:0]        pkt_length = 16'd0,
+  output wire [WIDTH-1:0]   pkt_chksum,
+  // Stream Stats
+  output reg  [COUNT_W-1:0] pkt_count  = {COUNT_W{1'b0}},
+  output reg  [COUNT_W-1:0] xfer_count = {COUNT_W{1'b0}}
+);
+
+  //----------------------------
+  // Packet specific
+  //----------------------------
+
+  reg pkt_head = 1'b1;
+  wire xfer = axis_tvalid & axis_tready;
+
+  assign sop = pkt_head & xfer;
+  assign eop = xfer & axis_tlast;
+
+  always @(posedge clk) begin
+    if (reset) begin
+      pkt_head <= 1'b1;
+    end else begin
+      if (pkt_head) begin
+        if (xfer)
+          pkt_head <= ~eop;
+      end else begin
+        if (eop)
+          pkt_head <= 1'b0;
+      end
+    end
+  end
+
+  generate if (PKT_LENGTH_EN == 0) begin
+    // Count the number of lines (transfers) in a packet
+    always @(posedge clk) begin
+      if (reset | eop) begin
+        pkt_length <= 16'd1;
+      end else if (xfer) begin
+        pkt_length <= pkt_length + 1'b1;
+      end
+    end
+  end else begin
+    // Default packet length is 0
+    always @(*) pkt_length <= 16'd0;
+  end endgenerate
+
+  generate if (PKT_LENGTH_EN == 0) begin
+    // Compute the XOR checksum of the lines in a packet
+    reg [WIDTH-1:0] chksum_prev = {WIDTH{1'b0}};
+    always @(posedge clk) begin
+      if (reset) begin
+        chksum_prev <= {WIDTH{1'b0}};
+      end else if (xfer) begin
+        chksum_prev <= pkt_chksum;
+      end
+    end
+    assign pkt_chksum = chksum_prev ^ axis_tdata;
+  end else begin
+    // Default checksum is 0
+    assign pkt_chksum = {WIDTH{1'b0}};
+  end endgenerate
+
+  //----------------------------
+  // Stream specific
+  //----------------------------
+
+  always @(posedge clk) begin
+    if (reset | (PKT_COUNT_EN == 0)) begin
+      pkt_count <= {COUNT_W{1'b0}};
+    end else if (eop) begin
+      pkt_count <= pkt_count + 1'b1;
+    end
+  end
+
+  always @(posedge clk) begin
+    if (reset | (XFER_COUNT_EN == 0)) begin
+      xfer_count <= {COUNT_W{1'b0}};
+    end else if (xfer) begin
+      xfer_count <= xfer_count + 1'b1;
+    end
+  end
+
+ endmodule
\ No newline at end of file
diff --git a/fpga/usrp3/lib/fifo/fifo64_to_axi4lite.v b/fpga/usrp3/lib/fifo/fifo64_to_axi4lite.v
new file mode 100644
index 000000000..3ba451a63
--- /dev/null
+++ b/fpga/usrp3/lib/fifo/fifo64_to_axi4lite.v
@@ -0,0 +1,140 @@
+/////////////////////////////////////////////////////////////////////
+//
+// Copyright 2016-2017 Ettus Research
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+//////////////////////////////////////////////////////////////////////
+
+module fifo64_to_axi4lite
+(
+  input         s_axi_aclk,
+  input         s_axi_areset,
+
+  input [31:0]  s_axi_awaddr,
+  input         s_axi_awvalid,
+  output        s_axi_awready,
+  input [31:0]  s_axi_wdata,
+  input [3:0]   s_axi_wstrb,
+  input         s_axi_wvalid,
+  output        s_axi_wready,
+  output [1:0]  s_axi_bresp,
+  output        s_axi_bvalid,
+  input         s_axi_bready,
+  input [31:0]  s_axi_araddr,
+  input         s_axi_arvalid,
+  output        s_axi_arready,
+  output [31:0] s_axi_rdata,
+  output [1:0]  s_axi_rresp,
+  output        s_axi_rvalid,
+  input         s_axi_rready,
+
+  output        m_axis_tvalid,
+  output        m_axis_tlast,
+  output [63:0] m_axis_tdata,
+  input         m_axis_tready,
+  output [3:0]  m_axis_tuser,
+
+  input         s_axis_tvalid,
+  input         s_axis_tlast,
+  input [63:0]  s_axis_tdata,
+  output        s_axis_tready,
+  input [3:0]   s_axis_tuser,
+  output        irq
+);
+
+  wire        clear_txn;
+  wire [31:0] tx_tdata;
+  wire        tx_tlast;
+  wire        tx_tvalid;
+  wire        tx_tready;
+  wire [3:0]  tx_tkeep;
+  wire [1:0]  tx_tuser = (tx_tkeep == 4'b1111) ? 2'd0 :
+                        (tx_tkeep == 4'b0001) ? 2'd1 :
+                        (tx_tkeep == 4'b0011) ? 2'd2 :
+                        (tx_tkeep == 4'b0111) ? 2'd3 : 2'd0;
+
+  axi_fifo32_to_fifo64 inst_axi_fifo32_to_fifo64
+  (
+    .clk(s_axi_aclk),
+    .reset(s_axi_areset | ~clear_txn),
+    .i_tdata({tx_tdata[7:0], tx_tdata[15:8], tx_tdata[23:16], tx_tdata[31:24]}), // endian swap
+    .i_tuser(tx_tuser),
+    .i_tlast(tx_tlast),
+    .i_tvalid(tx_tvalid),
+    .i_tready(tx_tready),
+    .o_tdata(m_axis_tdata),
+    .o_tuser(m_axis_tuser),
+    .o_tlast(m_axis_tlast),
+    .o_tvalid(m_axis_tvalid),
+    .o_tready(m_axis_tready)
+  );
+
+
+  wire        clear_rxn;
+  wire [31:0] rx_tdata;
+  wire        rx_tlast;
+  wire        rx_tvalid;
+  wire        rx_tready;
+  wire [1:0]  rx_tuser;
+
+  axi_fifo64_to_fifo32 inst_axi_fifo64_to_fifo32
+  (
+    .clk(s_axi_aclk),
+    .reset(s_axi_areset || ~clear_rxn),
+    .i_tdata(s_axis_tdata),
+    .i_tuser(s_axis_tuser[2:0]),
+    .i_tlast(s_axis_tlast),
+    .i_tvalid(s_axis_tvalid),
+    .i_tready(s_axis_tready),
+    .o_tdata({rx_tdata[7:0], rx_tdata[15:8], rx_tdata[23:16], rx_tdata[31:24]}), // endian swap
+    .o_tuser(rx_tuser),
+    .o_tlast(rx_tlast),
+    .o_tvalid(rx_tvalid),
+    .o_tready(rx_tready)
+  );
+
+  wire [3:0] rx_tkeep = ~rx_tlast ? 4'b1111 : (rx_tuser == 2'd0) ? 4'b1111 :
+             (rx_tuser == 2'd1) ? 4'b0001 :
+             (rx_tuser == 2'd2) ? 4'b0011 :
+             (rx_tuser == 2'd3) ? 4'b0111 :
+                                  4'b1111;
+
+  axis_fifo_to_axi4lite inst_axis_fifo_to_axi4lite0
+  (
+    .interrupt(irq),
+    .s_axi_aclk(s_axi_aclk),
+    .s_axi_aresetn(~s_axi_areset),
+    .s_axi_awaddr({16'h0000, s_axi_awaddr}),
+    .s_axi_awvalid(s_axi_awvalid),
+    .s_axi_awready(s_axi_awready),
+    .s_axi_wdata(s_axi_wdata),
+    .s_axi_wstrb(s_axi_wstrb),
+    .s_axi_wvalid(s_axi_wvalid),
+    .s_axi_wready(s_axi_wready),
+    .s_axi_bresp(s_axi_bresp),
+    .s_axi_bvalid(s_axi_bvalid),
+    .s_axi_bready(s_axi_bready),
+    .s_axi_araddr({16'h0000, s_axi_araddr}),
+    .s_axi_arvalid(s_axi_arvalid),
+    .s_axi_arready(s_axi_arready),
+    .s_axi_rdata(s_axi_rdata),
+    .s_axi_rresp(s_axi_rresp),
+    .s_axi_rvalid(s_axi_rvalid),
+    .s_axi_rready(s_axi_rready),
+    .mm2s_prmry_reset_out_n(clear_txn),
+    .axi_str_txd_tvalid(tx_tvalid),
+    .axi_str_txd_tready(tx_tready),
+    .axi_str_txd_tlast(tx_tlast),
+    .axi_str_txd_tdata(tx_tdata),
+    .axi_str_txd_tkeep(tx_tkeep),
+    .s2mm_prmry_reset_out_n(clear_rxn),
+    .axi_str_rxd_tvalid(rx_tvalid),
+    .axi_str_rxd_tready(rx_tready),
+    .axi_str_rxd_tlast(rx_tlast),
+    .axi_str_rxd_tdata(rx_tdata),
+    .axi_str_rxd_tkeep(rx_tkeep)
+);
+
+endmodule
diff --git a/fpga/usrp3/lib/fifo/shortfifo.v b/fpga/usrp3/lib/fifo/shortfifo.v
new file mode 100644
index 000000000..ca8cc4ae6
--- /dev/null
+++ b/fpga/usrp3/lib/fifo/shortfifo.v
@@ -0,0 +1,95 @@
+//
+// Copyright 2011 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+
+module shortfifo
+  #(parameter WIDTH=32)
+    (input clk, input rst,
+     input [WIDTH-1:0] datain,
+     output [WIDTH-1:0] dataout,
+     input read,
+     input write,
+     input clear,
+     output reg full,
+     output reg empty,
+     output reg [4:0] space,
+     output reg [4:0] occupied);
+   
+   reg [3:0] 	  a;
+   genvar 	  i;
+   
+   generate
+      for (i=0;i<WIDTH;i=i+1)
+	begin : gen_srl16
+	   SRL16E
+	     srl16e(.Q(dataout[i]),
+		    .A0(a[0]),.A1(a[1]),.A2(a[2]),.A3(a[3]),
+		    .CE(write),.CLK(clk),.D(datain[i]));
+	end
+   endgenerate
+   
+   always @(posedge clk)
+     if(rst)
+       begin
+	  a <= 0;
+	  empty <= 1;
+	  full <= 0;
+       end
+     else if(clear)
+       begin
+	  a <= 0;
+	  empty <= 1;
+	  full<= 0;
+       end
+     else if(read & ~write)
+       begin
+	  full <= 0;
+	  if(a==0)
+	    empty <= 1;
+	  else
+	    a <= a - 1;
+       end
+     else if(write & ~read)
+       begin
+	  empty <= 0;
+	  if(~empty)
+	    a <= a + 1;
+	  if(a == 14)
+	    full <= 1;
+       end
+
+   // NOTE will fail if you write into a full fifo or read from an empty one
+
+   //////////////////////////////////////////////////////////////
+   // space and occupied are used for diagnostics, not 
+   // guaranteed correct
+   
+   //assign space = full ? 0 : empty ? 16 : 15-a;
+   //assign occupied = empty ? 0 : full ? 16 : a+1;
+
+   always @(posedge clk)
+     if(rst)
+       space <= 16;
+     else if(clear)
+       space <= 16;
+     else if(read & ~write)
+       space <= space + 1;
+     else if(write & ~read)
+       space <= space - 1;
+   
+   always @(posedge clk)
+     if(rst)
+       occupied <= 0;
+     else if(clear)
+       occupied <= 0;
+     else if(read & ~write)
+       occupied <= occupied - 1;
+     else if(write & ~read)
+       occupied <= occupied + 1;
+      
+endmodule // shortfifo
diff --git a/fpga/usrp3/lib/fifo_200/Makefile.srcs b/fpga/usrp3/lib/fifo_200/Makefile.srcs
new file mode 100644
index 000000000..09c440852
--- /dev/null
+++ b/fpga/usrp3/lib/fifo_200/Makefile.srcs
@@ -0,0 +1,13 @@
+#
+# Copyright 2012-2013 Ettus Research LLC
+# Copyright 2016 Ettus Research, a National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+##################################################
+# FIFO 200 Sources
+##################################################
+FIFO_200_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/fifo_200/, \
+axi_fifo_legacy.v \
+))
diff --git a/fpga/usrp3/lib/fifo_200/axi_fifo_legacy.v b/fpga/usrp3/lib/fifo_200/axi_fifo_legacy.v
new file mode 100644
index 000000000..28c578954
--- /dev/null
+++ b/fpga/usrp3/lib/fifo_200/axi_fifo_legacy.v
@@ -0,0 +1,172 @@
+//
+// Copyright 2012-2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+
+// Block RAM AXI fifo
+
+// Special case SIZE <= 5 uses a short fifo
+
+module axi_fifo_legacy
+  #(parameter WIDTH=32, SIZE=9)
+   (input clk, input reset, input clear,
+    input [WIDTH-1:0] i_tdata,
+    input i_tvalid,
+    output i_tready,
+    output [WIDTH-1:0] o_tdata,
+    output o_tvalid,
+    input o_tready,
+    
+    output reg [15:0] space,
+    output reg [15:0] occupied);
+
+    generate
+    if(SIZE<=5) begin
+        wire [5:0] space_short, occupied_short;
+        axi_fifo_short #(.WIDTH(WIDTH)) fifo_short
+        (
+            .clk(clk), .reset(reset), .clear(clear),
+            .i_tdata(i_tdata), .i_tvalid(i_tvalid), .i_tready(i_tready),
+            .o_tdata(o_tdata), .o_tvalid(o_tvalid), .o_tready(o_tready),
+            .space(space_short), .occupied(occupied_short)
+        );
+        always @* space <= {10'b0, space_short};
+        always @* occupied <= {10'b0, occupied_short};
+    end
+    else begin
+
+   wire 	      write 	     = i_tvalid & i_tready;
+   wire 	      read 	     = o_tvalid & o_tready;
+   wire 	      full, empty;
+   
+   assign i_tready  = ~full;
+   assign o_tvalid  = ~empty;
+   
+   // Read side states
+   localparam 	  EMPTY = 0;
+   localparam 	  PRE_READ = 1;
+   localparam 	  READING = 2;
+
+   reg [SIZE-1:0] wr_addr, rd_addr;
+   reg [1:0] 	  read_state;
+
+   reg 	  empty_reg = 1'b1, full_reg = 1'b0;
+   always @(posedge clk)
+     if(reset)
+       wr_addr <= 0;
+     else if(clear)
+       wr_addr <= 0;
+     else if(write)
+       wr_addr <= wr_addr + 1;
+
+   ram_2port #(.DWIDTH(WIDTH),.AWIDTH(SIZE))
+     ram (.clka(clk),
+	  .ena(1'b1),
+	  .wea(write),
+	  .addra(wr_addr),
+	  .dia(i_tdata),
+	  .doa(),
+
+	  .clkb(clk),
+	  .enb((read_state==PRE_READ)|read),
+	  .web(1'b0),
+	  .addrb(rd_addr),
+	  .dib({WIDTH{1'b1}}),
+	  .dob(o_tdata));
+
+   always @(posedge clk)
+     if(reset)
+       begin
+	  read_state <= EMPTY;
+	  rd_addr <= 0;
+	  empty_reg <= 1;
+       end
+     else
+       if(clear)
+	 begin
+	    read_state <= EMPTY;
+	    rd_addr <= 0;
+	    empty_reg <= 1;
+	 end
+       else 
+	 case(read_state)
+	   EMPTY :
+	     if(write)
+	       begin
+		  //rd_addr <= wr_addr;
+		  read_state <= PRE_READ;
+	       end
+	   PRE_READ :
+	     begin
+		read_state <= READING;
+		empty_reg <= 0;
+		rd_addr <= rd_addr + 1;
+	     end
+	   
+	   READING :
+	     if(read)
+	       if(rd_addr == wr_addr)
+		 begin
+		    empty_reg <= 1; 
+		    if(write)
+		      read_state <= PRE_READ;
+		    else
+		      read_state <= EMPTY;
+		 end
+	       else
+		 rd_addr <= rd_addr + 1;
+	 endcase // case(read_state)
+
+   wire [SIZE-1:0] dont_write_past_me = rd_addr - 2;
+   wire 	   becoming_full = wr_addr == dont_write_past_me;
+     
+   always @(posedge clk)
+     if(reset)
+       full_reg <= 0;
+     else if(clear)
+       full_reg <= 0;
+     else if(read & ~write)
+       full_reg <= 0;
+     //else if(write & ~read & (wr_addr == (rd_addr-3)))
+     else if(write & ~read & becoming_full)
+       full_reg <= 1;
+
+   //assign empty = (read_state != READING);
+   assign empty = empty_reg;
+
+   // assign full = ((rd_addr - 1) == wr_addr);
+   assign full = full_reg;
+
+   //////////////////////////////////////////////
+   // space and occupied are for diagnostics only
+   // not guaranteed exact
+
+   localparam NUMLINES = (1<<SIZE);
+   always @(posedge clk)
+     if(reset)
+       space <= NUMLINES;
+     else if(clear)
+       space <= NUMLINES;
+     else if(read & ~write)
+       space <= space + 16'b1;
+     else if(write & ~read)
+       space <= space - 16'b1;
+   
+   always @(posedge clk)
+     if(reset)
+       occupied <= 16'b0;
+     else if(clear)
+       occupied <= 16'b0;
+     else if(read & ~write)
+       occupied <= occupied - 16'b1;
+     else if(write & ~read)
+       occupied <= occupied + 16'b1;
+
+    end
+    endgenerate
+
+endmodule // axi_fifo_legacy
diff --git a/fpga/usrp3/lib/gpif2/Makefile.srcs b/fpga/usrp3/lib/gpif2/Makefile.srcs
new file mode 100644
index 000000000..f621d3c3c
--- /dev/null
+++ b/fpga/usrp3/lib/gpif2/Makefile.srcs
@@ -0,0 +1,16 @@
+#
+# Copyright 2010-2013 Ettus Research LLC
+# Copyright 2016 Ettus Research, a National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+##################################################
+# SERDES Sources
+##################################################
+GPIF2_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/gpif2/, \
+gpif2_slave_fifo32.v \
+gpif2_to_fifo64.v \
+fifo64_to_gpif2.v \
+gpif2_error_checker.v \
+))
diff --git a/fpga/usrp3/lib/gpif2/fifo64_to_gpif2.v b/fpga/usrp3/lib/gpif2/fifo64_to_gpif2.v
new file mode 100644
index 000000000..45375f98b
--- /dev/null
+++ b/fpga/usrp3/lib/gpif2/fifo64_to_gpif2.v
@@ -0,0 +1,68 @@
+//
+// Copyright 2012-2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+module fifo64_to_gpif2
+#(
+    parameter FIFO_SIZE = 9,
+    parameter MTU = 12
+)
+(
+    //input fifo interface
+    input fifo_clk, input fifo_rst,
+    input [63:0] i_tdata,
+    input i_tlast,
+    input i_tvalid,
+    output i_tready,
+
+    //output interface
+    input gpif_clk, input gpif_rst,
+    output [31:0] o_tdata,
+    output o_tlast,
+    output o_tvalid,
+    input o_tready
+);
+
+    wire [31:0] i32_tdata;
+    wire i32_tlast;
+    wire i32_tvalid, i32_tready;
+
+    axi_fifo64_to_fifo32 fifo64_to_fifo32
+    (
+        .clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
+        .i_tdata(i_tdata), .i_tuser(3'b0/*done care*/), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready),
+        .o_tdata(i32_tdata), .o_tuser(/*ignored cuz vita has len*/), .o_tlast(i32_tlast), .o_tvalid(i32_tvalid), .o_tready(i32_tready)
+    );
+
+    wire [31:0] gate_tdata;
+    wire gate_tlast;
+    wire gate_tvalid, gate_tready;
+
+    axi_fifo_2clk #(.WIDTH(33), .SIZE(FIFO_SIZE)) cross_clock_fifo
+    (
+        .reset(fifo_rst | gpif_rst),
+        .i_aclk(fifo_clk), .i_tdata({i32_tlast, i32_tdata}), .i_tvalid(i32_tvalid), .i_tready(i32_tready),
+        .o_aclk(gpif_clk), .o_tdata({gate_tlast, gate_tdata}), .o_tvalid(gate_tvalid), .o_tready(gate_tready)
+    );
+
+    wire [31:0] int0_tdata; wire int0_tlast, int0_tvalid, int0_tready;
+
+    axi_packet_gate #(.WIDTH(32), .SIZE(MTU), .USE_AS_BUFF(0)) buffer_whole_pkt
+    (
+        .clk(gpif_clk), .reset(gpif_rst), .clear(1'b0),
+        .i_tdata(gate_tdata), .i_tlast(gate_tlast), .i_terror(1'b0), .i_tvalid(gate_tvalid), .i_tready(gate_tready),
+        .o_tdata(int0_tdata), .o_tlast(int0_tlast), .o_tvalid(int0_tvalid), .o_tready(int0_tready)
+    );
+
+    axi_fifo #(.WIDTH(33), .SIZE(1)) outgress_timing_fifo
+    (
+        .clk(gpif_clk), .reset(gpif_rst), .clear(1'b0),
+        .i_tdata({int0_tlast, int0_tdata}), .i_tvalid(int0_tvalid), .i_tready(int0_tready), .space(),
+        .o_tdata({o_tlast, o_tdata}), .o_tvalid(o_tvalid), .o_tready(o_tready), .occupied()
+    );
+
+endmodule //fifo_to_gpmc16
diff --git a/fpga/usrp3/lib/gpif2/gpif2_error_checker.v b/fpga/usrp3/lib/gpif2/gpif2_error_checker.v
new file mode 100644
index 000000000..412253213
--- /dev/null
+++ b/fpga/usrp3/lib/gpif2/gpif2_error_checker.v
@@ -0,0 +1,129 @@
+
+// Copyright 2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+
+// inspect the input for invalid conditions
+// when bad - drain input, flag error, and insert error msg packet
+//
+// Packets alignment errors are searched for in two different ways:
+// 1) Blatently illegal values in what is assumed to be the PACKET_LENGTH field
+// in the CHDR header
+// (We could probably improve this by looking at other fields of the header that 
+// have a limited range of values)
+// 2) Packet length indicating an EOF word that doesn't have TLAST set in the FIFO.
+// (Upstream can howvever legally insert TLAST in the FIFO for words that are not EOF)
+// 
+// Packet allignment recovery strategy is to wait for TLAST asserted and then decode the 
+// following data assuming it is the start of new CHDR headers.
+//
+//TODO - insert bad packet
+
+module gpif2_error_checker
+  #(parameter SIZE = 9)
+  (input clk, input reset, input clear,
+   input [31:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
+   output [31:0] o_tdata, output o_tlast, output o_tvalid, input o_tready,
+   output bus_error, output [63:0] debug);
+
+    wire [31:0] gate_tdata;
+    wire gate_tlast, gate_terror;
+    wire gate_tvalid, gate_tready;
+
+    localparam STATE_HDR = 0;
+    localparam STATE_FWD = 1;
+    localparam STATE_EOF = 2;
+    localparam STATE_WAIT = 3;
+    reg [1:0] state;
+
+    reg [15:0] lines32;
+    reg [11:0] seq_id_ref;
+    reg        seq_id_bad;
+    reg        seq_id_wayoff;
+   
+
+    wire [15:0] hdr_bytes = i_tdata[15:0] + 3; //round up to multiple of 4
+    wire [15:0] hdr_lines32 = {2'b0, hdr_bytes[15:2]}; //convert to lines32 count
+    wire [11:0] seq_id_actual = i_tdata[27:16];
+   
+   
+    wire obviously_bad_hdr = (hdr_lines32 == 16'h0) || (hdr_lines32 > (1 << SIZE));
+
+    always @(posedge clk) begin
+        if (reset | clear) begin
+            state <= STATE_HDR;
+            lines32 <= 16'b0;
+	    seq_id_ref <= 12'h0;
+	    seq_id_bad <= 0;
+	    seq_id_wayoff <= 0;
+	   
+	   
+        end
+        else case (state)
+
+        STATE_HDR: begin //forward header and grab vita length
+            if (i_tvalid && i_tready) begin
+                if (obviously_bad_hdr)           state <= STATE_WAIT;
+                else if (hdr_lines32 == 16'h1)  state <= STATE_HDR;
+                else if (hdr_lines32 == 16'h2)  state <= STATE_EOF;
+                else                            state <= STATE_FWD;
+	        seq_id_bad <= (seq_id_actual != seq_id_ref);
+	        seq_id_wayoff <= (seq_id_actual != seq_id_ref) |
+				(seq_id_actual != seq_id_ref+1) |
+				(seq_id_actual != seq_id_ref+2) |
+				(seq_id_actual != seq_id_ref+3);
+	        if (seq_id_actual != seq_id_ref)
+		 seq_id_ref <= seq_id_actual + 1;
+	        else
+		 seq_id_ref <= seq_id_ref + 1;
+            end
+            lines32 <= hdr_lines32;
+	    
+        end
+
+        STATE_FWD: begin //forward the rest of vita packet
+            if (i_tvalid && i_tready) begin
+                if (lines32 == 16'h3) state <= STATE_EOF;
+                lines32 <= lines32 - 1'b1;
+            end
+        end
+
+        STATE_EOF: begin //do last line of vita frame + eof
+	   if (i_tvalid && i_tready) 
+	     if (gate_tlast) state <= STATE_HDR;
+	     else state <= STATE_WAIT; // Try somehow to get synchronized again.
+        end
+
+        STATE_WAIT: begin //drop until idle
+            if (i_tvalid && i_tready && i_tlast) state <= STATE_HDR;
+        end
+
+        endcase //state
+    end
+
+    assign bus_error = (gate_terror && gate_tvalid && gate_tready) || ((state == STATE_HDR) && i_tvalid && i_tready && obviously_bad_hdr);
+    assign gate_tlast = (state == STATE_HDR)? (hdr_lines32 == 16'h1) : (state == STATE_EOF);
+    assign gate_tdata = i_tdata;
+    assign gate_tvalid = i_tvalid && ((state == STATE_HDR)? !obviously_bad_hdr : (state != STATE_WAIT));
+    assign i_tready = gate_tready;
+
+    axi_packet_gate #(.WIDTH(32), .SIZE(SIZE), .USE_AS_BUFF(0)) gate_xfer
+    (
+        .clk(clk), .reset(reset), .clear(clear),
+        .i_tdata(gate_tdata), .i_tlast(gate_tlast), .i_terror(1'b0), .i_tvalid(gate_tvalid), .i_tready(gate_tready),
+        .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready)
+    );
+   assign  debug = {13'b0,
+		    seq_id_wayoff, //[50]      [114]
+		    gate_terror,  // [49]      [113]
+		    obviously_bad_hdr, // [48] [112]
+		    seq_id_bad,   // [47]      [111]
+		    seq_id_ref,   // [46:35]   [110:99]
+		    i_tlast,      // [34]      [98]
+		    i_tready,     // [33]      [97]
+		    i_tvalid,     // [32]      [96]
+		    i_tdata};     // [31:0]    [95:64]
+   
+
+endmodule // gpif2_error_checker
diff --git a/fpga/usrp3/lib/gpif2/gpif2_slave_fifo32.v b/fpga/usrp3/lib/gpif2/gpif2_slave_fifo32.v
new file mode 100644
index 000000000..8f936cf9d
--- /dev/null
+++ b/fpga/usrp3/lib/gpif2/gpif2_slave_fifo32.v
@@ -0,0 +1,590 @@
+//
+// Copyright 2011-2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+//////////////////////////////////////////////////////////////////////////////////
+
+//this is a FIFO master interface for the FX3 in "slave fifo" mode.
+
+module gpif2_slave_fifo32
+#(
+    //sizes for fifo64 2 clock cascade fifos
+    parameter DATA_RX_FIFO_SIZE = 12, //max vita pkt size
+    parameter DATA_TX_FIFO_SIZE = 12, //max vita pkt size
+    parameter CTRL_RX_FIFO_SIZE = 5,  //small resp packets
+    parameter CTRL_TX_FIFO_SIZE = 5, //small ctrl packets
+
+    //address constants for the endpoints
+    parameter ADDR_DATA_TX = 2'b00,
+    parameter ADDR_DATA_RX = 2'b01,
+    parameter ADDR_CTRL_TX = 2'b10,
+    parameter ADDR_CTRL_RX = 2'b11
+)
+   (
+    // GPIF signals
+    input gpif_clk,
+    input gpif_rst,
+    input gpif_enb,
+    inout [31:0] gpif_d,
+    input [3:0] gpif_ctl,
+    output reg sloe,
+    output reg slrd,
+    output reg slwr,
+    output slcs,
+    output reg pktend,
+    output reg [1:0] fifoadr,
+    // FIFO interfaces
+    input fifo_clk,
+    input fifo_rst,
+    // TX Data interface to DSP
+    output [63:0] tx_tdata, output tx_tlast, output tx_tvalid, input tx_tready,
+    // RX Data interface to DSP
+    input [63:0] rx_tdata, input rx_tlast, input rx_tvalid, output rx_tready,
+    // Incomming control interface
+    output [63:0] ctrl_tdata, output ctrl_tlast, output ctrl_tvalid, input ctrl_tready,
+    // Outgoing control interface
+    input [63:0] resp_tdata, input resp_tlast, input resp_tvalid, output resp_tready,
+    // Debug Signals
+    output [31:0] debug
+    );
+
+   reg 		  fifo_nearly_full;
+   wire 	  ctrl_tx_fifo_nearly_full, data_tx_fifo_nearly_full;
+   wire 	  ctrl_tx_fifo_has_space, data_tx_fifo_has_space;
+
+
+    assign slcs = 1'b0;
+
+    //
+    // DMA FIFO ready and watermark flags
+    // These are double registered not for meta stability protection, but to make timing closure easier
+    // since the first register is locked in the I/O pad.
+    //
+    reg fx3_ready, fx3_ready1, fx3_wmark, fx3_wmark1;
+    always @(posedge gpif_clk) fx3_ready <= gpif_ctl[0];
+    always @(posedge gpif_clk) fx3_wmark <= gpif_ctl[1];
+    always @(posedge gpif_clk) fx3_ready1 <= fx3_ready;
+    always @(posedge gpif_clk) fx3_wmark1 <= fx3_wmark;
+
+    //
+    // GPIF input and output data lines, tristate
+    //
+    reg [31:0] gpif_data_in, gpif_data_out;
+
+    always @(posedge gpif_clk)
+      if (~slrd2)
+	// Update data register only when something useful is read.
+	// Hold values until we know if they are end of packets for single beat reads.
+    gpif_data_in <= gpif_d;
+
+    assign gpif_d = sloe ? gpif_data_out[31:0] : 32'bz;
+
+   // ////////////////////////////////////////////////////////////////////
+   // GPIF bus master state machine
+
+    wire wr_fifo_xfer, wr_fifo_eop;
+    wire [31:0] wr_fifo_data;
+    reg read_ready_go, write_ready_go;
+
+    reg [3:0] state; //state machine current state
+    localparam STATE_IDLE  = 0;
+    localparam STATE_THINK = 1;
+    localparam STATE_READ  = 2;
+    localparam STATE_WRITE = 3;
+    localparam STATE_WAIT = 4;
+    localparam STATE_READ_FLUSH = 5;
+    localparam STATE_WRITE_FLUSH = 6;
+    localparam STATE_READ_SINGLE = 7;
+
+
+    // General purpose pseudo-state counter.
+    reg [2:0] idle_cycles;
+
+    // Select next address (endpoint) to be processed
+    reg [1:0] last_addr, next_addr;
+
+    wire      local_fifo_ready;
+
+    // Track size of a wriet burst to look for FX3 corner cases related to 2^n sized bursts.
+    reg [15:0] transfer_size;
+
+    // Read strobe pipeline.
+    reg slrd1, slrd2, slrd3, slrd4, slrd5;
+
+    always @(posedge gpif_clk)
+     if (gpif_rst) begin
+        slrd1 <= 1'b1;
+        slrd2 <= 1'b1;
+        slrd3 <= 1'b1;
+        slrd4 <= 1'b1;
+        slrd5 <= 1'b1;
+     end else begin
+        slrd1 <= slrd;
+        slrd2 <= slrd1;
+        slrd3 <= slrd2;
+        slrd4 <= slrd3;
+        slrd5 <= slrd4;
+     end
+
+   // End of packet pipeline for reads.
+   reg 	rx_eop, rx_eop1, rx_eop2;
+
+   // This pipeline tracks the end of a CHDR TX packet seperately from the local FIFO becoming full.
+   // This is because a true packet end causes a tlast assertion to the FIFO, where as a full local FIFO only requires
+   // the GPIF transaction to be ended before local FIFO overflow occurs.
+    always @(posedge gpif_clk)
+      if (gpif_rst) begin
+        rx_eop1 <= 1;
+        rx_eop2 <= 1;
+      end else begin
+        rx_eop2 <= rx_eop1;
+        rx_eop1 <= rx_eop;
+    end
+
+   reg first_read;
+   reg pad = 0;
+
+   // //////////////////////////////////////////////////////////////
+   // FX2 slave FIFO bus master state machine
+   //
+    always @(posedge gpif_clk)
+    if(gpif_rst) begin
+        state <= STATE_IDLE;
+        sloe <= 1;
+        slrd <= 1;
+        slwr <= 1;
+        pktend <= 1;
+        gpif_data_out <= 32'b0;
+        idle_cycles <= 3'h0;
+        fifoadr <= 0;
+        first_read <= 1'b0;
+        last_addr <= 2'b0;
+        rx_eop <= 1'b0;
+        transfer_size <= 1;
+        pad <= 0;
+
+    end
+    else if (gpif_enb) begin
+      case (state)
+
+      //
+      // Increment fifoadr to point at next thread, set all strobes to idle,
+      //
+        STATE_IDLE: begin
+          sloe <= 1;
+          slrd <= 1;
+          slwr <= 1;
+          pktend <= 1;
+          gpif_data_out <= 32'b0;
+          fifoadr <= next_addr;
+          state <= STATE_WAIT;
+          idle_cycles <= 3'h0;
+       	  rx_eop <= 1'b0;
+          first_read <= 1'b0;
+        end
+
+      //
+      // If the current thread we are pointing at (fifoadr) can not immediately proceed
+      // then quickly move to the next thread. Once we are pointing at a thread that can proceed locally
+      // wait for 8 clock cycles to allow fifoadr to propogate to FX3, and corresponding flag state to
+      // propogate back to FPGA and through resampling flops. At this point transition to STATE_THINK
+      // to evaluate remote flag.
+      //
+        STATE_WAIT: begin
+       // Current thread can proceed locally
+          if (local_fifo_ready) begin
+            idle_cycles <= idle_cycles + 1'b1;
+          if (idle_cycles == 3'b111) state <= STATE_THINK; // Could shorten this delay, flags now stable for several clocks.
+          end
+       // ....move onto next thread.
+          else begin
+            idle_cycles <= 3'b0;
+            //fifoadr <= fifoadr + 2'b1;
+            fifoadr <= next_addr;
+
+          end
+        end
+
+      //
+      // Flags from FX3 now stable. Make a decision about what type of transaction to start.
+      //
+        STATE_THINK: begin
+        // This is written like a priority encoder but in reality read_ready_go and
+        // write_ready_go are mutually exclusive by design.
+          if (fx3_ready1 && fx3_wmark1 && read_ready_go) begin
+            state <= STATE_READ;
+            slrd <= 0;
+            rx_eop <= 1'b0;
+            first_read <= 1'b1; // Set unconditional read flag to kick off transaction
+            sloe <= 0; // FX3 drives the data bus.
+          end else if (fx3_ready1 && ~fx3_wmark1 && read_ready_go) begin
+            state <= STATE_READ_SINGLE;
+            slrd <= 0;
+            sloe <= 0; // FX3 drives the data bus.
+          end else if (fx3_ready1 && write_ready_go && wr_fifo_eop && (transfer_size[7:0] == 0)) begin // remember that write_ready_go shows 1 cycle old status.
+            // If an exact multiple of the native USB packet size (1K USB3, 512B USB2) has been transfered
+            // and TLAST is asserted (but the transfer is less than a full FX3 DMA buffer - this is
+            // indicated when the watermark will terminate the transfer in this case) then we will pad the packet
+            // for one more cycle to ensure it does not get stuck in the FX3.
+            pktend <= 1'b1; // Active low - De-asserted
+            slwr <= 1'b0; //Active low - Asserted, write to FX3.
+            transfer_size <= transfer_size + 1; // Increment transfer_size.
+            gpif_data_out <= wr_fifo_data; // Always latch data from FIFO's into output register
+            pad <= 1;
+          end else if ((fx3_ready1 && write_ready_go && wr_fifo_eop) | pad) begin  // remember that write_ready_go shows 1 cycle old status.
+            // Its the end of a CHDR packet and we are not on a FX3 corner case size.
+            // Go IDLE with pktend and slwr asserted to write the last data.
+            pktend <= 1'b0; // Active low - Asserted,
+            state <= STATE_WRITE_FLUSH;
+            idle_cycles <= 3'd5; // Stay in flush 3 cycles
+            slwr <= 1'b0; // Active low - Asserted, write to FX3
+            transfer_size <= 1; // End of packet will release FX3 DMA buffer, reset transfer size count.
+            gpif_data_out <= wr_fifo_data; // Always latch data from FIFO's into output register
+            pad <= 0; // Reset pad
+          end else if (fx3_ready1 && write_ready_go) begin // remember that write_ready_go shows 1 cycle old status.
+           // There is (an unknown amount of) data ready to send to FX from local FIFO.
+            state <= STATE_WRITE;
+            slwr <= 1'b0;  // Active low - Write strobe active
+            gpif_data_out <= wr_fifo_data; // Always latch data from FIFO's into output register
+            transfer_size <= transfer_size + 1; // Account for current cycles transfer
+          end
+          else begin
+            state <= STATE_IDLE;
+          end
+
+            idle_cycles <= 3'h0;
+            last_addr <= fifoadr;
+        end // case: STATE_THINK
+
+      // Got here because READY flag asserted but watermark deaaserted...QED there's less than the watermarks
+      // worth of data to read from FX remaining in this DMA page. Need to do that with single beat reads
+      // followed by rechecking the READY flag to see if it deassserted indicating that the page emptied.
+      // Since we have the read data from FX3 earlier than we have a flag to inspect we keep the data in
+      // gpif_data_in until we know if we are commiting it to the FIFO with or without an asserted TLAST.
+      //
+      STATE_READ_SINGLE: begin
+        if (idle_cycles == 0) begin
+    	// Deassert read strobe after reading single 32bit word
+          slrd <= 1'b1;
+          idle_cycles <= idle_cycles + 1;
+	      end else if (idle_cycles == 5) begin
+		// READY1 flag now reflect effects of last read.
+        if (!fx3_ready1) begin
+           state <= STATE_IDLE;
+           sloe <= 1'b1;
+        end else begin
+        // Initiate another READ beat.
+           state <= STATE_READ_SINGLE;
+           slrd <= 1'b0;
+        end
+        idle_cycles <= 0;
+        end else begin
+          // All other idle_cycles counts.
+          idle_cycles <= idle_cycles + 1;
+        end
+      end // case: STATE_READ_SINGLE
+
+
+      // If flag first_read and ~slrd3 have gone deasserted
+      // (meaning that the watermark deasserted 5 clock cycles ago or local FIFO full) transition to STATE_IDLE.
+      // If watermark deasserted 2 cycles ago de-assert slrd ...read data is still traveling in the pipeline.
+      // Whilst ~slrd3 stays asserted keep the first_read flag armed.
+      // Trigger TLAST only for transfer ended by watermark (Which indicates a true packet end), not local full FIFO.
+      STATE_READ: begin
+
+        if (~fx3_wmark1 | fifo_nearly_full) begin
+          // Either end of packet or local FIFO full is imminent, start shutting down this read burst.
+          slrd <= 1'b1;  // Active low - Take read strobe inactive
+          state <= STATE_READ_FLUSH;
+        end else begin
+           slrd <= 1'b0; // Active low - Keep read strobe active.
+        end
+
+        if (~fx3_wmark1)
+          // Put TLAST into pipeline to mark end of packet
+          rx_eop <= 1'b1;
+
+        if (~slrd3)
+          // Reset first_read flag as slrd assertion progresses down pipeline
+         first_read <= 1'b0;
+      end // case: STATE_READ
+
+      // SLRD has been deasserted but data continues to flow from FX3 into FPGA until pipeline empties.
+      STATE_READ_FLUSH: begin
+        slrd <= 1'b1; // Active low - Keep read strobe inactive.
+        rx_eop <= 1'b0; // EOP indication can be reset now - Already traveling in the pipeline if it was active.
+        if (~slrd3)
+          // Reset first_read flag as slrd assertion progresses down pipeline
+          first_read <= 1'b0;
+        if (!first_read && slrd3) begin // Active low signal
+          // Last data of burst will be written to FIFO next clock edge so transition to IDLE also.
+          state <= STATE_IDLE;
+          sloe <= 1'b1; // Active low - Resume parking bus with FPGA driving.
+        end
+      end
+
+
+      // Now in potential write burst. Exit this sate immediately if we are only doing a single beat write.
+      // Can exit this state in several ways:
+      // At EOP and on a USB packet boundery (1K for USB3, 512B for USB2) must pad packet for 1 clock cycle in
+      // addition to simply asserting pktend.
+      // Otherwise at EOP just send a short packet.
+      // If local FIFO goes empty then we terminatethe burst without asserting pktend.
+      STATE_WRITE: begin
+        if (wr_fifo_eop && wr_fifo_xfer && (transfer_size[7:0] == 0)) begin
+
+          // If an exact multiple of the native USB packet size (1K USB3, 512B USB2) has been transfered
+          // and TLAST is asserted (but the transfer is less than a full FX3 DMA buffer - this is
+          // indicated when the watermark will terminate the transfer in this case) then we will pad the packet
+          // for one more cycle to ensure it does not get stuck in the FX3.
+          pktend <= 1'b1; // Active low - De-asserted,
+          slwr <= 1'b0; // Active low - Asserted, write to FX3
+          transfer_size <= transfer_size + 1; // Increment transfer_size.
+          pad <= 1;
+       end else if ((wr_fifo_eop && wr_fifo_xfer) | pad) begin
+          // Its the end of a CHDR packet and we are not on a FX3 corner case size.
+          // Go IDLE with pktend and slwr asserted to write the last data.
+          pktend <= 1'b0; // Active low - Asserted,
+          state <= STATE_WRITE_FLUSH;
+          idle_cycles <= 3'd5; // Stay in flush 3 cycles
+          slwr <= 1'b0; // Active low - Asserted, write to FX3
+          transfer_size <= 1; // End of packet will release FX3 DMA buffer, reset transfer size count.
+          pad <= 0; //Reset pad
+       end else if (wr_fifo_xfer) begin
+          // Regular write beat as part of a burst.
+          pktend <= 1'b1; // Active low - De-asserted,
+          slwr <= 1'b0; // Active low - Asserted, write to FX3
+          transfer_size <= transfer_size + 1; // Account for current cycles transfer
+       end else begin // Implicit if (~wr_fifo_xfer)
+          // This was either a single beat write (watermark was never asserted)
+          // or the water mark just deasserted or we ran out of local data to send.
+          // slwr will be deasserted and we transition to the flush state.
+          state <= STATE_WRITE_FLUSH;
+          idle_cycles <= 3'd6; // Stay in flush 2 cycles.
+          pktend <= 1'b1; // Active low - De-asserted,
+          slwr <= 1'b1; // Active low - Deasserted, don't write to FX3
+       end
+
+        gpif_data_out <= wr_fifo_data; // Always latch data from FIFO's into output register
+
+       end // case: STATE_WRITE
+
+      // Some FX3 timing diagrams seem to imply address should be held stable after transaction
+      STATE_WRITE_FLUSH: begin
+        slrd <= 1;
+        slwr <= 1;
+        pktend <= 1;
+        gpif_data_out <= 32'b0;
+        idle_cycles <= idle_cycles + 1'b1;
+        if (idle_cycles == 3'b111) begin
+          state <= STATE_IDLE;
+        end
+      end
+
+
+        default: state <= STATE_IDLE;
+        endcase
+    end
+
+   // ///////////////////////////////////////////////////////////////////
+   // fifo signal assignments and enables
+
+    //output from fifos - ready to xfer
+    wire data_tx_tready, ctrl_tx_tready;
+    wire ctrl_rx_tvalid, data_rx_tvalid;
+
+    //Priority encoding for the the next address to service:
+    //The next address to service is based on the readiness
+    //of the internal fifos and last serviced fairness metric.
+/* -----\/----- EXCLUDED -----\/-----
+    always @(posedge gpif_clk) next_addr <=
+        ((ctrl_rx_tvalid && (last_addr != ADDR_CTRL_RX))? ADDR_CTRL_RX :
+        ((ctrl_tx_fifo_has_space && (last_addr != ADDR_CTRL_TX))? ADDR_CTRL_TX :
+        ((data_rx_tvalid && (last_addr != ADDR_DATA_RX))? ADDR_DATA_RX :
+        ((data_tx_fifo_has_space && (last_addr != ADDR_DATA_TX))? ADDR_DATA_TX :
+        (fifoadr + 2'b1)
+    ))));
+ -----/\----- EXCLUDED -----/\----- */
+   //always @(posedge gpif_clk) next_addr <= (fifoadr + 2'b1);
+
+   // Sequence addresses 0->2->1->3->0......
+   always @(posedge gpif_clk) {next_addr[0],next_addr[1]} <= ({fifoadr[0],fifoadr[1]} + 2'b1);
+
+    //Help the FPGA search to only look for addrs that the FPGA is ready for
+    assign local_fifo_ready =
+        (ctrl_rx_tvalid && (fifoadr == ADDR_CTRL_RX)) ||
+        (ctrl_tx_fifo_has_space && (fifoadr == ADDR_CTRL_TX)) ||
+        (data_rx_tvalid && (fifoadr == ADDR_DATA_RX)) ||
+        (data_tx_fifo_has_space && (fifoadr == ADDR_DATA_TX));
+
+    // Local TX FIFO imminantly about to fill.
+    always @(posedge gpif_clk) fifo_nearly_full <=
+        (ctrl_tx_fifo_nearly_full && (fifoadr == ADDR_CTRL_TX)) ||
+        (data_tx_fifo_nearly_full && (fifoadr == ADDR_DATA_TX));
+
+    // There is enough space in local FIFO to RX an entire CHDR packet (sized for channel type)
+    always @(posedge gpif_clk) read_ready_go <=
+        (ctrl_tx_fifo_has_space && (fifoadr == ADDR_CTRL_TX)) ||
+        (data_tx_fifo_has_space && (fifoadr == ADDR_DATA_TX));
+
+    // The is data waiting to be sent to FX3 in local FIFO's
+    always @(posedge gpif_clk) write_ready_go <=
+        (ctrl_rx_tvalid && (fifoadr == ADDR_CTRL_RX)) ||
+        (data_rx_tvalid && (fifoadr == ADDR_DATA_RX));
+
+    //fifo xfer enable
+    wire data_rx_tready = (
+               ((state == STATE_WRITE) && fx3_wmark1 && ~pad) || // Sustain burst
+               ((state == STATE_THINK) && fx3_ready1)    // First beat
+               ) && (fifoadr == ADDR_DATA_RX) ;
+
+    wire ctrl_rx_tready = (
+               ((state == STATE_WRITE) && fx3_wmark1) || // Sustain burst
+               ((state == STATE_THINK) && fx3_ready1)    // First beat
+               ) && (fifoadr == ADDR_CTRL_RX) ;
+
+    // Burst reads tap the read strobe pipeline at stage3, single beat reads at stage5.
+    wire data_tx_tvalid = (
+               (((state == STATE_READ) || (state == STATE_READ_FLUSH)) && ~slrd3) |
+               ((state == STATE_READ_SINGLE) && ~slrd5)
+               ) && (fifoadr == ADDR_DATA_TX);
+    wire ctrl_tx_tvalid = (
+               (((state == STATE_READ) || (state == STATE_READ_FLUSH)) && ~slrd3) |
+               ((state == STATE_READ_SINGLE) && ~slrd5)
+               ) && (fifoadr == ADDR_CTRL_TX);
+
+    // The position of RX TLAST is known well in advance for bursts by monitoring the watermark. However for
+    // single beat reads it can only be deduced after a read that causes the ready flag to go inactive.
+    wire  data_ctrl_tx_tlast = ((state == STATE_READ_FLUSH) && rx_eop2) || ((state == STATE_READ_SINGLE) && ~fx3_ready1);
+
+
+    //outputs from rx fifo paths
+    wire ctrl_rx_tlast, data_rx_tlast;
+    wire [31:0] ctrl_rx_tdata, data_rx_tdata;
+
+    // There will be a RX FIFO transaction this cycle
+    assign wr_fifo_xfer = (fifoadr == ADDR_CTRL_RX)? (ctrl_rx_tvalid && ctrl_rx_tready) : (data_rx_tvalid && data_rx_tready);
+    // The RX FIFO transaction this cycle has TLAST set
+    assign wr_fifo_eop =  (fifoadr == ADDR_CTRL_RX)? ctrl_rx_tlast : data_rx_tlast;
+    // Route data from addressed RX FIFO towards FX3
+    assign wr_fifo_data = (fifoadr == ADDR_CTRL_RX)? ctrl_rx_tdata : data_rx_tdata;
+
+    wire ctrl_bus_error, tx_bus_error;
+
+   // ////////////////////////////////////////////////////////////////////
+   // TX Data Path
+   wire [31:0] debug_data_fifo;
+
+    gpif2_to_fifo64 #(.FIFO_SIZE(DATA_TX_FIFO_SIZE)) gpif2_to_fifo64_tx(
+        .gpif_clk(gpif_clk), .gpif_rst(gpif_rst),
+        .i_tdata(gpif_data_in), .i_tlast(data_ctrl_tx_tlast), .i_tvalid(data_tx_tvalid), .i_tready(data_tx_tready), // IJB. NOTE data_tx_tready currently unused.
+        .fifo_clk(fifo_clk), .fifo_rst(fifo_rst),
+        .fifo_nearly_full(data_tx_fifo_nearly_full), .fifo_has_space(data_tx_fifo_has_space),
+        .o_tdata(tx_tdata), .o_tlast(tx_tlast), .o_tvalid(tx_tvalid), .o_tready(tx_tready),
+        .bus_error(tx_bus_error), .debug(debug_data_fifo)
+    );
+
+   // ////////////////////////////////////////////
+   // RX Data Path
+
+    fifo64_to_gpif2 #(.FIFO_SIZE(DATA_RX_FIFO_SIZE)) fifo64_to_gpif2_rx(
+        .fifo_clk(fifo_clk), .fifo_rst(fifo_rst),
+        .i_tdata(rx_tdata), .i_tlast(rx_tlast), .i_tvalid(rx_tvalid), .i_tready(rx_tready),
+        .gpif_clk(gpif_clk), .gpif_rst(gpif_rst),
+        .o_tdata(data_rx_tdata), .o_tlast(data_rx_tlast), .o_tvalid(data_rx_tvalid), .o_tready(data_rx_tready)
+    );
+
+    // ////////////////////////////////////////////////////////////////////
+    // CTRL path
+    wire [31:0] debug_ctrl_fifo;
+
+    gpif2_to_fifo64 #(.FIFO_SIZE(CTRL_TX_FIFO_SIZE)) gpif2_to_fifo64_ctrl(
+        .gpif_clk(gpif_clk), .gpif_rst(gpif_rst),
+        .i_tdata(gpif_data_in), .i_tlast(data_ctrl_tx_tlast), .i_tvalid(ctrl_tx_tvalid), .i_tready(ctrl_tx_tready), // IJB. NOTE data_tx_tready currently unused.
+        .fifo_clk(fifo_clk), .fifo_rst(fifo_rst),
+        .fifo_nearly_full(ctrl_tx_fifo_nearly_full), .fifo_has_space(ctrl_tx_fifo_has_space),
+        .o_tdata(ctrl_tdata), .o_tlast(ctrl_tlast), .o_tvalid(ctrl_tvalid), .o_tready(ctrl_tready),
+        .bus_error(ctrl_bus_error), .debug(debug_ctrl_fifo)
+    );
+
+   // ////////////////////////////////////////////////////////////////////
+   // RESP path
+
+    fifo64_to_gpif2 #(.FIFO_SIZE(CTRL_RX_FIFO_SIZE)) fifo64_to_gpif2_resp(
+        .fifo_clk(fifo_clk), .fifo_rst(fifo_rst),
+        .i_tdata(resp_tdata), .i_tlast(resp_tlast), .i_tvalid(resp_tvalid), .i_tready(resp_tready),
+        .gpif_clk(gpif_clk), .gpif_rst(gpif_rst),
+        .o_tdata(ctrl_rx_tdata), .o_tlast(ctrl_rx_tlast), .o_tvalid(ctrl_rx_tvalid), .o_tready(ctrl_rx_tready)
+    );
+
+   // ////////////////////////////////////////////
+   //    DEBUG
+/* -----\/----- EXCLUDED -----\/-----
+
+   wire [35:0] CONTROL0;
+   reg 	       wr_fifo_eop_debug;
+   reg 	       read_ready_go_debug;
+   reg 	       fifo_nearly_full_debug;
+   reg 	       local_fifo_ready_debug;
+   reg 	       slwr_debug;
+   reg 	       slrd_debug;
+   reg 	       sloe_debug;
+   reg 	       pktend_debug;
+   reg [1:0]   fifoadr_debug;
+   reg 	       ep_wmark1_debug;
+   reg 	       ep_ready1_debug;
+   reg [3:0]   state_debug;
+   reg 	       wr_fifo_xfer_debug;
+
+
+
+   always @(posedge gpif_clk) begin
+      wr_fifo_eop_debug <= wr_fifo_eop;
+      read_ready_go_debug <= read_ready_go;
+      fifo_nearly_full_debug <= fifo_nearly_full;
+      local_fifo_ready_debug <= local_fifo_ready;
+      wr_fifo_xfer_debug <= wr_fifo_xfer;
+      slwr_debug <= slwr;
+      slrd_debug <= slrd;
+      sloe_debug <= sloe;
+      pktend_debug <= pktend;
+      fifoadr_debug[1:0] <= fifoadr;
+      ep_wmark1_debug <= fx3_wmark1;
+      ep_ready1_debug <= fx3_ready1;
+      state_debug[3:0] <= state;
+   end
+
+   chipscope_ila_32 chipscope_ila_32_0 (
+				      .CONTROL(CONTROL0), // INOUT BUS [35:0]
+				      .CLK(gpif_clk), // IN
+				      .TRIG0({
+					      debug_data_fifo[5:0],
+					      debug_ctrl_fifo[5:0],
+ 					      wr_fifo_eop_debug,
+   					      read_ready_go_debug,
+   					      fifo_nearly_full_debug,
+   					      local_fifo_ready_debug,
+					      wr_fifo_xfer_debug,
+   					      slwr_debug,
+   					      slrd_debug,
+   					      sloe_debug,
+   					      pktend_debug,
+					      fifoadr_debug[1:0],
+   					      ep_wmark1_debug,
+   					      ep_ready1_debug,
+					      state_debug[3:0]
+   					      }) // IN BUS [31:0]
+				      );
+
+   chipscope_icon chipscope_icon_i0
+     (
+      .CONTROL0(CONTROL0) // INOUT BUS [35:0]
+      );
+ -----/\----- EXCLUDED -----/\----- */
+
+
+endmodule // gpif2_slave_fifo32
diff --git a/fpga/usrp3/lib/gpif2/gpif2_to_fifo64.v b/fpga/usrp3/lib/gpif2/gpif2_to_fifo64.v
new file mode 100644
index 000000000..7281275a3
--- /dev/null
+++ b/fpga/usrp3/lib/gpif2/gpif2_to_fifo64.v
@@ -0,0 +1,152 @@
+//
+// Copyright 2012-2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+module gpif2_to_fifo64
+  #(
+    parameter FIFO_SIZE = 9,
+    parameter MTU = 12
+    )
+    (
+     //input interface
+     input gpif_clk,
+     input gpif_rst,
+     input [31:0] i_tdata,
+     input i_tlast,
+     input i_tvalid,
+     output i_tready,
+     output fifo_has_space,
+     output fifo_nearly_full,
+
+     //output fifo interface
+     input fifo_clk,
+     input fifo_rst,
+     output [63:0] o_tdata,
+     output o_tlast,
+     output o_tvalid,
+     input o_tready,
+
+     output bus_error,
+     output [31:0] debug
+     );
+
+   wire [31:0] 	    int_tdata;
+   wire 	    int_tlast;
+   wire 	    int_tvalid, int_tready;
+
+   wire [31:0] 	    int0_tdata;
+   wire 	    int0_tlast, int0_tvalid, int0_tready;
+
+   //
+   // Generate flags that show if initial FIFO's can accept a maximum sized burst from the FX3
+   // or if the FIFO is about to fill.
+   //
+   wire [15:0] 	    space;
+   assign 	    fifo_has_space = space >= (1 << MTU);
+   assign 	    fifo_nearly_full = (space < 6); // 5 spaces left.
+
+   //
+   // This FIFO is provdied purely to ease FPGA timing closure as data is coming from I/O pins.
+   //
+   axi_fifo #(.WIDTH(33), .SIZE(5)) ingress_timing_fifo
+     (
+      .clk(gpif_clk), .reset(gpif_rst), .clear(1'b0),
+      .i_tdata({i_tlast, i_tdata}), .i_tvalid(i_tvalid), .i_tready(i_tready), .space(),
+      .o_tdata({int0_tlast, int0_tdata}), .o_tvalid(int0_tvalid), .o_tready(int0_tready), .occupied()
+      );
+
+   //
+   // This FIFO provides space to accept a single burst from FX3 and it's fullness drives flags to GPIF2 logic
+   //
+   axi_fifo_legacy #(.WIDTH(33), .SIZE(MTU)) min_read_buff
+     (
+      .clk(gpif_clk), .reset(gpif_rst), .clear(1'b0),
+      .i_tdata({int0_tlast, int0_tdata}), .i_tvalid(int0_tvalid), .i_tready(int0_tready), .space(space),
+      .o_tdata({int_tlast, int_tdata}), .o_tvalid(int_tvalid), .o_tready(int_tready), .occupied()
+      );
+
+   //
+   // This logic allows signals to cross from the GPIF2 clock domain to the BUS clock domain.
+   // It may now be obselete if bus_clk and gpif_clk are merged
+   //
+   wire [31:0] 	    chk_tdata;
+   wire 	    chk_tlast;
+   wire 	    chk_tvalid, chk_tready;
+
+   axi_fifo_2clk #(.WIDTH(33), .SIZE(FIFO_SIZE)) cross_clock_fifo
+     (
+      .reset(fifo_rst | gpif_rst),
+      .i_aclk(gpif_clk), .i_tdata({int_tlast, int_tdata}), .i_tvalid(int_tvalid), .i_tready(int_tready),
+      .o_aclk(fifo_clk), .o_tdata({chk_tlast, chk_tdata}), .o_tvalid(chk_tvalid), .o_tready(chk_tready)
+      );
+
+   //
+   // Performs basic tests on incomming packets such as testing if size on the wire patches
+   // the internal size field. Uses axi_packet_gate internally so can back pressure upstream if
+   // packet needs to be dropped.
+   //
+   wire [31:0] 	    o32_tdata;
+   wire 	    o32_tlast;
+   wire 	    o32_tvalid, o32_tready;
+
+   gpif2_error_checker #(.SIZE(MTU)) checker
+     (
+      .clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
+      .i_tdata(chk_tdata), .i_tlast(chk_tlast), .i_tvalid(chk_tvalid), .i_tready(chk_tready),
+      .o_tdata(o32_tdata), .o_tlast(o32_tlast), .o_tvalid(o32_tvalid), .o_tready(o32_tready),
+      .bus_error(bus_error), .debug()
+      );
+
+   //assign o32_tdata = chk_tdata;
+   //assign o32_tlast = chk_tlast;
+   //assign o32_tvalid = chk_tvalid;
+   //assign chk_tready = o32_tready;
+
+   //
+   // Convert 32bit AXIS bus to 64bit
+   //
+   axi_fifo32_to_fifo64 fifo32_to_fifo64
+     (
+      .clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
+      .i_tdata(o32_tdata), .i_tuser(2'b0/*always 32 bits*/), .i_tlast(o32_tlast), .i_tvalid(o32_tvalid), .i_tready(o32_tready),
+      .o_tdata(o_tdata), .o_tuser(/*ignored cuz vita has len*/), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready)
+      );
+
+
+   /////////////////////////////////////////////
+   //
+   // Debug logic only
+   //
+   /////////////////////////////////////////////
+
+   reg 		    o_tready_debug;
+   reg 		    o_tvalid_debug;
+   reg 		    o_tlast_debug;
+   reg 		    i_tready_debug;
+   reg 		    i_tvalid_debug;
+   reg 		    i_tlast_debug;
+
+   always @(posedge gpif_clk) begin
+   	    o_tready_debug <= o_tready;
+ 	    o_tvalid_debug <= o_tvalid;
+ 	    o_tlast_debug <= o_tlast;
+  	    i_tready_debug <= i_tready;
+  	    i_tvalid_debug <= i_tvalid;
+	    i_tlast_debug <= i_tlast;
+   end
+
+   assign debug = {26'h0,
+		   o_tready_debug,
+    		   o_tvalid_debug,
+    		   o_tlast_debug,
+    		   i_tready_debug,
+    		   i_tvalid_debug,
+    		   i_tlast_debug
+		   };
+
+
+endmodule //fifo_to_gpif2
diff --git a/fpga/usrp3/lib/hls/Makefile.inc b/fpga/usrp3/lib/hls/Makefile.inc
new file mode 100644
index 000000000..83a552c39
--- /dev/null
+++ b/fpga/usrp3/lib/hls/Makefile.inc
@@ -0,0 +1,10 @@
+#
+# Copyright 2015-2017 Ettus Research
+#
+include $(TOOLS_DIR)/make/viv_hls_ip_builder.mak
+
+# Add HLS IP to build
+include $(HLS_IP_DIR)/addsub_hls/Makefile.inc
+
+LIB_HLS_IP_SRCS = \
+$(HLS_IP_ADDSUB_HLS_OUTS)
diff --git a/fpga/usrp3/lib/hls/addsub_hls/Makefile.inc b/fpga/usrp3/lib/hls/addsub_hls/Makefile.inc
new file mode 100644
index 000000000..0e2f0737a
--- /dev/null
+++ b/fpga/usrp3/lib/hls/addsub_hls/Makefile.inc
@@ -0,0 +1,22 @@
+#
+# Copyright 2015-2017 Ettus Research
+# Copyright 2016 Ettus Research, a National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+# Add C/C++/tcl files relative to usrp3/lib/hls/<ip> directory
+HLS_IP_ADDSUB_HLS_SRCS = \
+addsub_hls.cpp \
+addsub_hls.tcl
+
+HLS_IP_ADDSUB_HLS_OUTS = $(addprefix $(IP_BUILD_DIR)/addsub_hls/, \
+solution/impl/verilog/addsub_hls.v \
+)
+
+# Sources in lib directory
+HLS_IP_ADDSUB_HLS_LIB_SRCS = $(addprefix $(HLS_IP_DIR)/addsub_hls/, $(HLS_IP_ADDSUB_HLS_SRCS))
+
+# Build with HLS
+$(HLS_IP_ADDSUB_HLS_OUTS) : $(HLS_IP_ADDSUB_HLS_LIB_SRCS)
+	$(call BUILD_VIVADO_HLS_IP,addsub_hls,$(PART_ID),$(HLS_IP_ADDSUB_HLS_LIB_SRCS),$(HLS_IP_DIR),$(IP_BUILD_DIR),)
diff --git a/fpga/usrp3/lib/hls/addsub_hls/addsub_hls.cpp b/fpga/usrp3/lib/hls/addsub_hls/addsub_hls.cpp
new file mode 100644
index 000000000..1cb27c119
--- /dev/null
+++ b/fpga/usrp3/lib/hls/addsub_hls/addsub_hls.cpp
@@ -0,0 +1,41 @@
+//
+// Copyright 2016 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+#include <complex>
+#include "ap_int.h"
+
+struct axis_cplx {
+    std::complex<short int> data;
+    ap_uint<1> last;
+};
+
+// AXI-Stream port type is compatible with pointer, reference, & array input / ouputs only
+// See UG902 Vivado High Level Synthesis guide (2014.4) pg 157 Figure 1-49
+void addsub_hls (axis_cplx &a, axis_cplx &b, axis_cplx &add, axis_cplx &sub) {
+
+    // Remove ap ctrl ports (ap_start, ap_ready, ap_idle, etc) since we only use the AXI-Stream ports
+    #pragma HLS INTERFACE ap_ctrl_none port=return
+    // Set ports as AXI-Stream
+    #pragma HLS INTERFACE axis port=sub
+    #pragma HLS INTERFACE axis port=add
+    #pragma HLS INTERFACE axis port=a
+    #pragma HLS INTERFACE axis port=b
+    // Need to pack our complex<short int> into a 32-bit word
+    // Otherwise, compiler complains that our AXI-Stream interfaces have two data fields (i.e. data.real, data.imag)
+    #pragma HLS DATA_PACK variable=sub.data
+    #pragma HLS DATA_PACK variable=add.data
+    #pragma HLS DATA_PACK variable=a.data
+    #pragma HLS DATA_PACK variable=b.data
+
+    // Complex add / subtract
+    add.data.real() = a.data.real() + b.data.real();
+    add.data.imag() = a.data.imag() + b.data.imag();
+    sub.data.real() = a.data.real() - b.data.real();
+    sub.data.imag() = a.data.imag() - b.data.imag();
+    // Pass through tlast
+    add.last = a.last;
+    sub.last = a.last;
+}
diff --git a/fpga/usrp3/lib/hls/addsub_hls/addsub_hls.tcl b/fpga/usrp3/lib/hls/addsub_hls/addsub_hls.tcl
new file mode 100644
index 000000000..a089fb628
--- /dev/null
+++ b/fpga/usrp3/lib/hls/addsub_hls/addsub_hls.tcl
@@ -0,0 +1,2 @@
+# Set target clock rate to 200 MHz
+create_clock -period 5 -name default
diff --git a/fpga/usrp3/lib/io_cap_gen/Makefile.srcs b/fpga/usrp3/lib/io_cap_gen/Makefile.srcs
new file mode 100644
index 000000000..a068103cd
--- /dev/null
+++ b/fpga/usrp3/lib/io_cap_gen/Makefile.srcs
@@ -0,0 +1,23 @@
+#
+# Copyright 2014 Ettus Research LLC
+# Copyright 2016 Ettus Research, a National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+##################################################
+# IO Capture and Generation Sources
+##################################################
+CAT_CAP_GEN_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/io_cap_gen/, \
+./catcap_ddr_cmos.v \
+./catgen_ddr_cmos.v \
+./catcodec_ddr_cmos.v \
+./cat_input_lvds.v \
+./cat_output_lvds.v \
+./cat_io_lvds.v \
+./cat_io_lvds_dual_mode.v \
+))
+
+CAP_GEN_GENERIC_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/io_cap_gen/, \
+./cap_pattern_verifier.v \
+))
diff --git a/fpga/usrp3/lib/io_cap_gen/cap_pattern_verifier.v b/fpga/usrp3/lib/io_cap_gen/cap_pattern_verifier.v
new file mode 100644
index 000000000..0d4877187
--- /dev/null
+++ b/fpga/usrp3/lib/io_cap_gen/cap_pattern_verifier.v
@@ -0,0 +1,125 @@
+//
+// Copyright 2015 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+//
+// Synthesizable test pattern checker
+//
+
+module cap_pattern_verifier #(
+  parameter WIDTH       = 16,       //Width of data bus
+  parameter PATTERN     = "RAMP",   //Pattern to detect. Choose from {RAMP, ONES, ZEROS, TOGGLE, LEFT_BARREL, RIGHT_BARREL}
+  parameter RAMP_START  = 'h0000,   //Start value for ramp (PATTERN=RAMP only)
+  parameter RAMP_STOP   = 'hFFFF,   //Stop value for ramp (PATTERN=RAMP only)
+  parameter RAMP_INCR   = 'h0001,   //Increment for ramp (PATTERN=RAMP only)
+  parameter BARREL_INIT = 'h0001,   //Initial value for the barrel shifter (PATTERN=*_BARREL only)
+  parameter HOLD_CYCLES = 1         //Number of cycles to hold each value in the pattern
+) (
+  input             clk,
+  input             rst,
+
+  //Data input
+  input             valid,
+  input [WIDTH-1:0] data,
+
+  //Status output (2 cycle latency)
+  output reg [31:0] count,
+  output reg [31:0] errors,
+  output            locked,
+  output            failed
+);
+
+  //Create a synchronous version of rst
+  wire sync_rst;
+  reset_sync reset_sync_i (
+    .clk(clk), .reset_in(rst), .reset_out(sync_rst));
+
+  // Register the data to minimize fanout at source
+  reg [WIDTH-1:0] data_reg;
+  reg             valid_reg;
+  always @(posedge clk)
+    {data_reg, valid_reg} <= {data, valid};
+
+  // Define pattern start and next states
+  wire [WIDTH-1:0]  patt_start, patt_next;
+  reg [WIDTH-1:0]   patt_next_reg;
+  generate if (PATTERN == "RAMP") begin
+    assign patt_start = RAMP_START;
+    assign patt_next  = (data_reg==RAMP_STOP) ? RAMP_START : data_reg+RAMP_INCR;
+  end else if (PATTERN == "ZEROS") begin
+    assign patt_start = {WIDTH{1'b0}};
+    assign patt_next  = {WIDTH{1'b0}};
+  end else if (PATTERN == "ONES") begin
+    assign patt_start = {WIDTH{1'b1}};
+    assign patt_next  = {WIDTH{1'b1}};
+  end else if (PATTERN == "TOGGLE") begin
+    assign patt_start = {(WIDTH/2){2'b10}};
+    assign patt_next  = ~data_reg;
+  end else if (PATTERN == "LEFT_BARREL") begin
+    assign patt_start = BARREL_INIT;
+    assign patt_next  = {data_reg[WIDTH-2:0],data_reg[WIDTH-1]};
+  end else if (PATTERN == "RIGHT_BARREL") begin
+    assign patt_start = BARREL_INIT;
+    assign patt_next  = {data_reg[0],data_reg[WIDTH-1:1]};
+  end endgenerate
+
+  reg [1:0] state;
+  localparam ST_IDLE    = 2'd0;
+  localparam ST_LOCKED  = 2'd1;
+
+  reg [7:0] cyc_count;
+
+  //All registers in this state machine need to have an
+  //asynchronous reset because the "data" and "valid" can
+  //be metastable coming into this module, and can possibly
+  //corrupt "state".
+  always @(posedge clk or posedge rst) begin
+    if (rst) begin            //Asynchronous reset
+      count         <= 32'd0;
+      errors        <= 32'd0;
+      state         <= ST_IDLE;
+      cyc_count     <= 8'd0;
+      patt_next_reg <= {WIDTH{1'b0}};
+    end else begin
+      //Only do something if data is valid
+      if (valid_reg & ~sync_rst) begin
+        case (state)
+          ST_IDLE: begin
+            //Trigger on start of pattern
+            //We use a case equality here to ensure that this module
+            //does the right thing in simulation. In HW this should
+            //infer a "=="
+            if (data_reg === patt_start) begin
+              state     <= ST_LOCKED;
+              count     <= 32'd1;
+              cyc_count <= HOLD_CYCLES - 1;
+            end
+          end
+          ST_LOCKED: begin
+            if (cyc_count == 0) begin           //Hold counter has expired. Check next word
+              count <= count + 32'd1;
+              //We use a case equality here to ensure that this module
+              //does the right thing in simulation. In HW this should
+              //infer a "!="
+              if (data_reg !== patt_next_reg) begin
+                errors <= errors + 32'd1;
+              end
+              cyc_count <= HOLD_CYCLES - 1;
+            end else begin                      //Hold until the next update
+              cyc_count <= cyc_count - 1;
+            end
+          end
+        endcase
+        patt_next_reg <= patt_next;             //Update next pattern
+      end
+    end
+  end  
+
+  assign locked = (state == ST_LOCKED);
+  assign failed = (errors != 32'd0) && locked;
+
+endmodule
+
+
+
diff --git a/fpga/usrp3/lib/io_cap_gen/cat_input_lvds.v b/fpga/usrp3/lib/io_cap_gen/cat_input_lvds.v
new file mode 100644
index 000000000..9b24ca6ca
--- /dev/null
+++ b/fpga/usrp3/lib/io_cap_gen/cat_input_lvds.v
@@ -0,0 +1,609 @@
+//
+// Copyright 2016 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: cat_input_lvds
+//
+// Description:
+//
+// Receive interface to AD9361 (Catalina) in LVDS mode.
+//
+// Use Xilinx SERDES to deserialize interleaved sample data off
+// half-word-width LVDS differential data bus from the Catalina.
+//
+// Use FRAME signal to initially synchronize to incoming data after reset
+// de-asserts.
+//
+// In all modes (SISO or MIMO) we output a clock of 1/4 the frequency
+// of the Catalina source-synchronous bus clock to be used as the radio_clk.
+//
+// In SISO mode, every cycle of the radio_clk supplies a new RX sample which
+// is routed to both radios, even if only one is actively receiving.
+//
+// In MIMO mode, every cycle of the radio clock supplies a pair of
+// time aligned MIMO samples which are routed to different radios.
+//
+// The frame_sample signal controls the expected frame signal timing. When 
+// frame_sample is 0, the period of the ddr_frame signal is expected to equal 
+// two samples (e.g., one from each channel). When frame_sample is 1, the frame 
+// period is expected to equal the length of one sample. This allows the module 
+// to be used for 2R2T (frame_sample = 1) or 1R1T mode (frame_sample = 0).
+//
+
+
+module cat_input_lvds #(
+  parameter INVERT_FRAME_RX  = 0,
+  parameter INVERT_DATA_RX   = 6'b00_0000,
+  parameter USE_CLOCK_DELAY  = 1,
+  parameter USE_DATA_DELAY   = 1,
+  parameter CLOCK_DELAY_MODE = "VAR_LOAD",
+  parameter DATA_DELAY_MODE  = "VAR_LOAD",
+  parameter CLOCK_DELAY      = 0,
+  parameter DATA_DELAY       = 0,
+  parameter WIDTH            = 6,
+  parameter GROUP            = "DEFAULT",
+  parameter USE_BUFG         = 1
+) (
+  input clk200,
+  input rst,
+
+  // Data and frame timing (synchronous to radio_clk)
+  input mimo,          // Output one channel (MIMO=0) or two (MIMO=1)
+  input frame_sample,  // Two samples per frame period (frame_sample=0) or one sample per frame (frame_sample=1)
+
+  // Region local Clocks for I/O cells.
+  output ddr_clk,
+  output sdr_clk,
+
+  // Source Synchronous external input clock
+  input ddr_clk_p,
+  input ddr_clk_n,
+
+  // Source Synchronous data lines
+  input [WIDTH-1:0] ddr_data_p,
+  input [WIDTH-1:0] ddr_data_n,
+  input             ddr_frame_p,
+  input             ddr_frame_n,
+
+  // Delay control interface
+  input       ctrl_clk,
+  input [4:0] ctrl_data_delay,
+  input [4:0] ctrl_clk_delay,
+  input       ctrl_ld_data_delay,
+  input       ctrl_ld_clk_delay,
+
+  // Global output clocks, ddr_clk/4 & ddr_clk/2
+  output radio_clk,
+  output radio_clk_2x,
+
+  // SDR Data buses
+  output reg [(WIDTH*2)-1:0] i0,
+  output reg [(WIDTH*2)-1:0] q0,
+  output reg [(WIDTH*2)-1:0] i1,
+  output reg [(WIDTH*2)-1:0] q1,
+  output reg                 rx_aligned
+
+);
+
+  //------------------------------------------------------------------
+  // UG471 says take reset high asynchronously, and de-assert
+  // synchronized to CLKDIV (sdr_clk) for SERDES.
+  //------------------------------------------------------------------
+  (* ASYNC_REG = "TRUE" *) reg rst_sdr_sync, rst_sdr_sync_ms;
+
+  always @(posedge sdr_clk or posedge rst)
+    if (rst) begin
+      rst_sdr_sync_ms <= 1'b1;
+      rst_sdr_sync    <= 1'b1;
+    end else begin
+      rst_sdr_sync_ms <= 1'b0;
+      rst_sdr_sync    <= rst_sdr_sync_ms;
+    end
+
+
+  //------------------------------------------------------------------
+  // IDELAY is calibrated using (mandatory) IDELAYCTRL cell.
+  // Must be feed stable free running clock specified by: FIDELAYCTRL_REF.(200MHz)
+  // Mandatory async reset required, min pulse of: TIDELAYCTRL_RPW (~60nS)
+  //------------------------------------------------------------------
+  (* IODELAY_GROUP = GROUP *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL
+  IDELAYCTRL IDELAYCTRL_i0 (
+    .REFCLK (clk200),
+    .RST    (rst_sdr_sync),
+    .RDY    ()
+  );
+
+
+  //------------------------------------------------------------------
+  // Clock input
+  //------------------------------------------------------------------
+  wire ddr_clk_dly, ddr_clk_unbuf;
+
+  IBUFDS #(
+    .DIFF_TERM("TRUE")
+  ) clk_ibufds (
+    .O(ddr_clk_unbuf),
+    .I(ddr_clk_p),
+    .IB(ddr_clk_n)
+  );
+
+  generate
+    if (USE_CLOCK_DELAY) begin : gen_clock_delay
+      (* IODELAY_GROUP = GROUP *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL
+      IDELAYE2 #(
+        .CINVCTRL_SEL          ("FALSE"),     // Enable dynamic clock inversion (FALSE, TRUE)
+        .DELAY_SRC             ("IDATAIN"),   // Delay input (IDATAIN, DATAIN)
+        .HIGH_PERFORMANCE_MODE ("FALSE"),     // Reduced jitter ("TRUE"), Reduced power ("FALSE")
+        .IDELAY_TYPE           (CLOCK_DELAY_MODE),
+        .IDELAY_VALUE          (CLOCK_DELAY),
+        .PIPE_SEL              ("FALSE"),
+        .REFCLK_FREQUENCY      (200.0),
+        .SIGNAL_PATTERN        ("CLOCK")
+      ) ddr_clk_idelaye2 (
+        .CNTVALUEOUT (),                  // 5-bit output: Counter value output
+        .DATAOUT     (ddr_clk_dly),       // 1-bit output: Delayed data output
+        .C           (ctrl_clk),          // 1-bit input: Clock input
+        .CE          (1'b0),              // 1-bit input: Active high enable increment/decrement input
+        .CINVCTRL    (1'b0),              // 1-bit input: Dynamic clock inversion input
+        .CNTVALUEIN  (ctrl_clk_delay),    // 5-bit input: Counter value input
+        .DATAIN      (1'b0),              // 1-bit input: Internal delay data input
+        .IDATAIN     (ddr_clk_unbuf),     // 1-bit input: Data input from the I/O
+        .INC         (1'b0),              // 1-bit input: Increment / Decrement tap delay input
+        .LD          (ctrl_ld_clk_delay), // 1-bit input: Load IDELAY_VALUE input
+        .LDPIPEEN    (1'b0),              // 1-bit input: Enable PIPELINE register to load data input
+        .REGRST      (1'b0)               // 1-bit input: Active-high reset tap-delay input
+      ); 
+    end
+    else begin
+      assign ddr_clk_dly = ddr_clk_unbuf;
+    end
+
+  endgenerate
+
+  // IO CLock is DDR freq. This drives SERDES and other I/O elements with minimal clock skew.
+  BUFIO ddr_clk_bufio (.O(ddr_clk),.I(ddr_clk_dly));
+
+  // SDR clock is one quarter DDR freq and local to regio using BUFR
+  // BUFR is a constraint of the SERDES since we need frequency agnostic clock division.
+  // UG471 states can use BUFIO and BUFR divided to directly drive a SERDES legally.
+  // (Other option is pair of BUFG's plus an MMCM - But MMCM has fixed frequency)
+  wire sdr_clk_2x;
+
+  BUFR #(
+    .BUFR_DIVIDE ("2"),
+    .SIM_DEVICE  ("7SERIES")
+  ) sdr_clk_2x_bufr (
+    .O   (sdr_clk_2x),
+    .CE  (1'b1),
+    .CLR (1'b0),
+    .I   (ddr_clk_dly)
+  );
+
+  BUFR #(
+    .BUFR_DIVIDE("4"),
+    .SIM_DEVICE("7SERIES")
+  ) sdr_clk_bufr (
+    .O(sdr_clk),
+    .CE(1'b1),
+    .CLR(1'b0),
+    .I(ddr_clk_dly)
+  );
+
+  generate
+    if (USE_BUFG) begin : gen_BUFG
+      // radio_clock is sdr_clk re-buffered with BUFG, and radio_clk_2x is
+      // sdr_clk_2x re-buffered, so both can be used globally. This introduces skew
+      // between sdr_clk -> radio_clock so we must hand data between them carefully
+      // even though they have a fixed phase relationship.
+      BUFG radio_clk_1x_bufg (.O(radio_clk), .I(sdr_clk));
+      BUFG radio_clk_2x_bufg (.O(radio_clk_2x), .I(sdr_clk_2x));  
+    end else begin
+      assign radio_clk = sdr_clk;
+      assign radio_clk_2x = sdr_clk_2x;
+    end
+  endgenerate
+
+
+
+  //------------------------------------------------------------------
+  // Frame Signal
+  //------------------------------------------------------------------
+  wire       ddr_frame, ddr_frame_dly;
+  wire [7:0] des_frame; // deserialized  frame signal
+  reg        bitslip;
+  reg        aligned;
+
+
+  //
+  // Use FRAME signal to get bitstream word aligned.
+  //
+  // In MIMO mode, FRAME is asserted during the entirety of channel 0, and
+  // deasserts during the entirety of channel 1.
+  //
+  localparam IDLE   = 0;
+  localparam SEARCH = 1;
+  localparam SLIP1  = 3;
+  localparam SLIP2  = 2;
+  localparam SLIP3  = 4;
+  localparam SLIP4  = 5;
+  localparam SYNC   = 6;
+
+
+  reg [2:0] frame_state;
+
+  //
+  // Delay start of framesync operation for 64 clocks after reset de-asserts to
+  // SERDES to be sure they are in a steady state.
+  //
+  // Each time we assert bitslip we then have to wait 2 cycles before we can
+  // examine the results.
+  //
+  // Checking for 0xF0 and 0xCC allows us to support 1R1T and 2R2T timing, 
+  // which have different frame periods.
+  wire frame_is_aligned = 
+          (!frame_sample && (des_frame[7:0] == (INVERT_FRAME_RX ? 8'h0F : 8'hF0))) ||
+          ( frame_sample && (des_frame[7:0] == (INVERT_FRAME_RX ? 8'h33 : 8'hCC)));
+
+  reg [5:0] sync_delay;
+  reg       run_sync;
+
+
+  always @(posedge sdr_clk)
+    if (rst_sdr_sync) begin
+      sync_delay <= 6'h0;
+      run_sync <= 1'b0;
+    end else if (sync_delay == 6'h3F)
+      run_sync <= 1'b1;
+    else
+      sync_delay <= sync_delay + 1'b1;
+
+  always @(posedge sdr_clk)
+  begin
+    if (!run_sync) begin
+      frame_state <= IDLE;
+      bitslip <= 1'b0;
+      aligned <= 1'b0;
+    end else begin
+      case (frame_state)
+        IDLE: begin
+          bitslip <= 1'b0;
+          aligned <= 1'b0;
+          frame_state <= SEARCH;
+        end
+
+        SEARCH: begin
+          if (frame_is_aligned) begin
+            frame_state <= SYNC;
+            bitslip <= 1'b0;
+            aligned <= 1'b1;
+          end else begin
+            // Bitslip until captured frame is aligned
+            bitslip <= 1'b1;
+            frame_state <= SLIP1;
+            aligned <= 1'b0;
+          end
+        end
+
+        SLIP1: begin
+          frame_state <= SLIP2;
+          bitslip <= 1'b0;
+          aligned <= 1'b0;
+        end
+
+        SLIP2: begin
+          frame_state <= SLIP3;
+          bitslip <= 1'b0;
+          aligned <= 1'b0;
+        end
+
+        SLIP3: begin
+          frame_state <= SLIP4;
+          bitslip <= 1'b0;
+          aligned <= 1'b0;
+        end
+
+        SLIP4: begin
+          frame_state <= SEARCH;
+          bitslip <= 1'b0;
+          aligned <= 1'b0;
+        end
+
+        SYNC: begin
+          if (frame_is_aligned) begin
+            frame_state <= SYNC;
+            aligned <= 1'b1;
+          end else begin
+            frame_state <= SEARCH;
+            aligned <= 1'b0;
+          end
+        end
+
+      endcase // case(frame_state)
+
+    end
+  end
+
+
+  IBUFDS #(
+    .DIFF_TERM ("TRUE")
+  ) ddr_frame_ibufds (
+    .O  (ddr_frame),
+    .I  (ddr_frame_p),
+    .IB (ddr_frame_n)
+  );
+
+  generate
+    if (USE_DATA_DELAY) begin : gen_frame_delay
+      (* IODELAY_GROUP = GROUP *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL
+      IDELAYE2 #(
+        .CINVCTRL_SEL          ("FALSE"),    // Enable dynamic clock inversion (FALSE, TRUE)
+        .DELAY_SRC             ("IDATAIN"),  // Delay input (IDATAIN, DATAIN)
+        .HIGH_PERFORMANCE_MODE ("FALSE"),    // Reduced jitter ("TRUE"), Reduced power ("FALSE")
+        .IDELAY_TYPE           (DATA_DELAY_MODE),
+        .IDELAY_VALUE          (DATA_DELAY),
+        .PIPE_SEL              ("FALSE"),
+        .REFCLK_FREQUENCY      (200.0),
+        .SIGNAL_PATTERN        ("DATA")
+      ) ddr_frame_idelaye2 (
+        .CNTVALUEOUT (),                   // 5-bit output: Counter value output
+        .DATAOUT     (ddr_frame_dly),      // 1-bit output: Delayed data output
+        .C           (ctrl_clk),           // 1-bit input: Clock input
+        .CE          (1'b0),               // 1-bit input: Active high enable increment/decrement input
+        .CINVCTRL    (1'b0),               // 1-bit input: Dynamic clock inversion input
+        .CNTVALUEIN  (ctrl_data_delay),    // 5-bit input: Counter value input
+        .DATAIN      (1'b0),               // 1-bit input: Internal delay data input
+        .IDATAIN     (ddr_frame),          // 1-bit input: Data input from the I/O
+        .INC         (1'b0),               // 1-bit input: Increment / Decrement tap delay input
+        .LD          (ctrl_ld_data_delay), // 1-bit input: Load IDELAY_VALUE input
+        .LDPIPEEN    (1'b0),               // 1-bit input: Enable PIPELINE register to load data input
+        .REGRST      (1'b0)                // 1-bit input: Active-high reset tap-delay input
+      );
+    end
+    else begin
+      assign ddr_frame_dly = ddr_frame;
+    end
+  endgenerate
+
+  ISERDESE2 #(
+    .DATA_RATE         ("DDR"),        // DDR, SDR
+    .DATA_WIDTH        (8),            // Parallel data width (2-8,10,14)
+    .DYN_CLKDIV_INV_EN ("FALSE"),      // Enable DYNCLKDIVINVSEL inversion (FALSE, TRUE)
+    .DYN_CLK_INV_EN    ("FALSE"),      // Enable DYNCLKINVSEL inversion (FALSE, TRUE)
+    // INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1)
+    .INIT_Q1           (1'b0),
+    .INIT_Q2           (1'b0),
+    .INIT_Q3           (1'b0),
+    .INIT_Q4           (1'b0),
+    .INTERFACE_TYPE    ("NETWORKING"),
+    .IOBDELAY          ("BOTH"),
+    .NUM_CE            (1),
+    .OFB_USED          ("FALSE"),
+    .SERDES_MODE       ("MASTER"),
+    // SRVAL_Q1 - SRVAL_Q4: Q output values when SR is used (0/1)
+    .SRVAL_Q1          (1'b0),
+    .SRVAL_Q2          (1'b0),
+    .SRVAL_Q3          (1'b0),
+    .SRVAL_Q4          (1'b0)
+  ) ddr_frame_serdese2 (
+    .O            (),              // 1-bit output: Combinatorial output
+    // Q1 - Q8: 1-bit (each) output: Registered data outputs
+    .Q1           (des_frame[0]),
+    .Q2           (des_frame[1]),
+    .Q3           (des_frame[2]),
+    .Q4           (des_frame[3]),
+    .Q5           (des_frame[4]),
+    .Q6           (des_frame[5]),
+    .Q7           (des_frame[6]),
+    .Q8           (des_frame[7]),
+    // SHIFTOUT1, SHIFTOUT2: 1-bit (each) output: Data width expansion output ports
+    .SHIFTOUT1    (),
+    .SHIFTOUT2    (),
+    // 1-bit input: The BITSLIP pin performs a Bitslip operation synchronous to
+    // CLKDIV when asserted (active High). Subsequently, the data seen on the Q1
+    // to Q8 output ports will shift, as in a barrel-shifter operation, one
+    // position every time Bitslip is invoked (DDR operation is different from SDR)
+    .BITSLIP      (bitslip),
+    // CE1, CE2: 1-bit (each) input: Data register clock enable inputs
+    .CE1          (1'b1),
+    .CE2          (1'b1),
+    .CLKDIVP      (1'b0),          // 1-bit input: TBD
+    // Clocks: 1-bit (each) input: ISERDESE2 clock input ports
+    .CLK          (ddr_clk),       // 1-bit input: High-speed clock
+    .CLKB         (~ddr_clk),      // 1-bit input: High-speed secondary clock
+    .CLKDIV       (sdr_clk),       // 1-bit input: Divided clock
+    .OCLK         (1'b0),          // 1-bit input: High-speed output clock used when INTERFACE_TYPE="MEMORY"
+    // Dynamic Clock Inversions: 1-bit (each) input: Dynamic clock inversion pins to switch clock polarity
+    .DYNCLKDIVSEL (1'b0),          // 1-bit input: Dynamic CLKDIV inversion
+    .DYNCLKSEL    (1'b0),          // 1-bit input: Dynamic CLK/CLKB inversion
+    // Input Data: 1-bit (each) input: ISERDESE2 data input ports
+    .D            (1'b0),          // 1-bit input: Data input
+    .DDLY         (ddr_frame_dly), // 1-bit input: Serial data from IDELAYE2
+    .OFB          (1'b0),          // 1-bit input: Data feedback from OSERDESE2
+    .OCLKB        (1'b0),          // 1-bit input: High-speed negative edge output clock
+    .RST          (rst_sdr_sync),  // 1-bit input: Active high asynchronous reset
+    // SHIFTIN1, SHIFTIN2: 1-bit (each) input: Data width expansion input ports
+    .SHIFTIN1     (1'b0),
+    .SHIFTIN2     (1'b0)
+  );
+
+
+  //------------------------------------------------------------------
+  // Data Bus
+  //------------------------------------------------------------------
+  wire [WIDTH-1:0] ddr_data;
+  wire [WIDTH-1:0] ddr_data_dly;
+  wire [(WIDTH*2)-1:0] data_i0, data_i1;
+  wire [(WIDTH*2)-1:0] data_q0, data_q1;
+
+
+  genvar i;
+  generate
+    for (i=0 ; i<WIDTH ; i=i+1) begin : generate_data_bus
+
+      IBUFDS #(
+        .DIFF_TERM ("TRUE")
+      ) ddr_data_ibufds (
+        .O  (ddr_data[i]),
+        .I  (ddr_data_p[i]),
+        .IB (ddr_data_n[i])
+      );
+
+      if (USE_DATA_DELAY) begin : gen_data_delay
+        (* IODELAY_GROUP = GROUP *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL
+        IDELAYE2 #(
+          .CINVCTRL_SEL          ("FALSE"),    // Enable dynamic clock inversion (FALSE, TRUE)
+          .DELAY_SRC             ("IDATAIN"),  // Delay input (IDATAIN, DATAIN)
+          .HIGH_PERFORMANCE_MODE ("FALSE"),    // Reduced jitter ("TRUE"), Reduced power ("FALSE")
+          .IDELAY_TYPE           (DATA_DELAY_MODE),
+          .IDELAY_VALUE          (DATA_DELAY),
+          .PIPE_SEL              ("FALSE"),
+          .REFCLK_FREQUENCY      (200.0),
+          .SIGNAL_PATTERN        ("DATA")
+        ) ddr_data_idelaye2 (
+          .CNTVALUEOUT (),                   // 5-bit output: Counter value output
+          .DATAOUT     (ddr_data_dly[i]),    // 1-bit output: Delayed data output
+          .C           (ctrl_clk),           // 1-bit input: Clock input
+          .CE          (1'b0),               // 1-bit input: Active high enable increment/decrement input
+          .CINVCTRL    (1'b0),               // 1-bit input: Dynamic clock inversion input
+          .CNTVALUEIN  (ctrl_data_delay),    // 5-bit input: Counter value input
+          .DATAIN      (1'b0),               // 1-bit input: Internal delay data input
+          .IDATAIN     (ddr_data[i]),        // 1-bit input: Data input from the I/O
+          .INC         (1'b0),               // 1-bit input: Increment / Decrement tap delay input
+          .LD          (ctrl_ld_data_delay), // 1-bit input: Load IDELAY_VALUE input
+          .LDPIPEEN    (1'b0),               // 1-bit input: Enable PIPELINE register to load data input
+          .REGRST      (1'b0)                // 1-bit input: Active-high reset tap-delay input
+        );
+      end
+      else begin
+        assign ddr_data_dly[i] = ddr_data[i];
+      end
+
+      ISERDESE2 #(
+        .DATA_RATE         ("DDR"),        // DDR, SDR
+        .DATA_WIDTH        (8),            // Parallel data width (2-8,10,14)
+        .DYN_CLKDIV_INV_EN ("FALSE"),      // Enable DYNCLKDIVINVSEL inversion (FALSE, TRUE)
+        .DYN_CLK_INV_EN    ("FALSE"),      // Enable DYNCLKINVSEL inversion (FALSE, TRUE)
+        // INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1)
+        .INIT_Q1           (1'b0),
+        .INIT_Q2           (1'b0),
+        .INIT_Q3           (1'b0),
+        .INIT_Q4           (1'b0),
+        .INTERFACE_TYPE    ("NETWORKING"),
+        .IOBDELAY          ("BOTH"),
+        .NUM_CE            (1),
+        .OFB_USED          ("FALSE"),
+        .SERDES_MODE       ("MASTER"),
+        // SRVAL_Q1 - SRVAL_Q4: Q output values when SR is used (0/1)
+        .SRVAL_Q1          (1'b0),
+        .SRVAL_Q2          (1'b0),
+        .SRVAL_Q3          (1'b0),
+        .SRVAL_Q4          (1'b0)
+      ) ddr_data_serdese2 (
+        .O            (),                 // 1-bit output: Combinatorial output
+        // Q1 - Q8: 1-bit (each) output: Registered data outputs
+        .Q1           (data_q1[i]),
+        .Q2           (data_i1[i]),
+        .Q3           (data_q1[WIDTH+i]),
+        .Q4           (data_i1[WIDTH+i]),
+        .Q5           (data_q0[i]),
+        .Q6           (data_i0[i]),
+        .Q7           (data_q0[WIDTH+i]),
+        .Q8           (data_i0[WIDTH+i]),
+        // SHIFTOUT1, SHIFTOUT2: 1-bit (each) output: Data width expansion output ports
+        .SHIFTOUT1    (),
+        .SHIFTOUT2    (),
+        // 1-bit input: The BITSLIP pin performs a Bitslip operation synchronous to
+        // CLKDIV when asserted (active High). Subsequently, the data seen on the Q1
+        // to Q8 output ports will shift, as in a barrel-shifter operation, one
+        // position every time Bitslip is invoked (DDR operation is different from SDR)
+        .BITSLIP      (bitslip),
+        // CE1, CE2: 1-bit (each) input: Data register clock enable inputs
+        .CE1          (1'b1),
+        .CE2          (1'b1),
+        .CLKDIVP      (1'b0),             // 1-bit input: TBD
+        // Clocks: 1-bit (each) input: ISERDESE2 clock input ports
+        .CLK          (ddr_clk),          // 1-bit input: High-speed clock
+        .CLKB         (~ddr_clk),         // 1-bit input: High-speed secondary clock
+        .CLKDIV       (sdr_clk),          // 1-bit input: Divided clock
+        .OCLK         (1'b0),             // 1-bit input: High-speed output clock used when INTERFACE_TYPE="MEMORY"
+        // Dynamic Clock Inversions: 1-bit (each) input: Dynamic clock inversion pins to switch clock polarity
+        .DYNCLKDIVSEL (1'b0),             // 1-bit input: Dynamic CLKDIV inversion
+        .DYNCLKSEL    (1'b0),             // 1-bit input: Dynamic CLK/CLKB inversion
+        // Input Data: 1-bit (each) input: ISERDESE2 data input ports
+        .D            (1'b0),             // 1-bit input: Data input
+        .DDLY         (ddr_data_dly[i]),  // 1-bit input: Serial data from IDELAYE2
+        .OFB          (1'b0),             // 1-bit input: Data feedback from OSERDESE2
+        .OCLKB        (1'b0),             // 1-bit input: High-speed negative edge output clock
+        .RST          (rst_sdr_sync),     // 1-bit input: Active high asynchronous reset
+        // SHIFTIN1, SHIFTIN2: 1-bit (each) input: Data width expansion input ports
+        .SHIFTIN1     (1'b0),
+        .SHIFTIN2     (1'b0)
+      );
+
+    end // block: generate_data_bus
+  endgenerate
+
+  //
+  // Cross these cycles to radio_clk using negative edge. This give 1/2 a radio
+  // clock period + BUFG insertion delay for signals to propagate. Thats > 6nS.
+  //
+  reg [(WIDTH*2)-1:0] radio_data_i0, radio_data_i1, radio_data_q0, radio_data_q1;
+  reg                 radio_aligned;
+
+  always @(negedge radio_clk)
+    begin
+      radio_data_i0[(WIDTH*2)-1:0] <= data_i0[(WIDTH*2)-1:0] ^ {INVERT_DATA_RX,INVERT_DATA_RX};
+      radio_data_q0[(WIDTH*2)-1:0] <= data_q0[(WIDTH*2)-1:0] ^ {INVERT_DATA_RX,INVERT_DATA_RX};
+      radio_data_i1[(WIDTH*2)-1:0] <= data_i1[(WIDTH*2)-1:0] ^ {INVERT_DATA_RX,INVERT_DATA_RX};
+      radio_data_q1[(WIDTH*2)-1:0] <= data_q1[(WIDTH*2)-1:0] ^ {INVERT_DATA_RX,INVERT_DATA_RX};
+      radio_aligned                <= aligned;
+    end
+
+  always @(posedge radio_clk)
+    begin
+      i0 <= radio_data_i0;
+      q0 <= radio_data_q0;
+      if (mimo) { i1, q1 } <= { radio_data_i1, radio_data_q1 };
+      else { i1, q1 } <= { radio_data_i0, radio_data_q0 }; // dup single valid channel to both radios
+      rx_aligned <= radio_aligned;
+    end
+
+  /*******************************************************************
+   * Debug only logic below here.
+   ******************************************************************/
+/*-----\/----- EXCLUDED -----\/-----
+  (* keep = "true", max_fanout = 10 *) reg [7:0] des_frame_reg;
+  (* keep = "true", max_fanout = 10 *) reg rst_sdr_sync_reg;
+  (* keep = "true", max_fanout = 10 *) reg run_sync_reg;
+  (* keep = "true", max_fanout = 10 *) reg bitslip_reg;
+  (* keep = "true", max_fanout = 10 *) reg aligned_reg;
+  (* keep = "true", max_fanout = 10 *) reg [2:0] frame_state_reg;
+
+  always @(posedge sdr_clk)
+    begin
+      des_frame_reg    <= des_frame;
+      rst_sdr_sync_reg <= rst_sdr_sync;
+      run_sync_reg     <= run_sync;
+      bitslip_reg      <= bitslip;
+      aligned_reg      <= aligned;
+      frame_state_reg  <= frame_state;
+    end
+
+  ila64 ila64_i (
+    .clk(sdr_clk),        // input clk
+    .probe0(
+      {
+        des_frame_reg,
+        rst_sdr_sync_reg,
+        run_sync_reg,
+        bitslip_reg,
+        aligned_reg,
+        frame_state_reg
+      }
+    )
+  );
+  -----/\----- EXCLUDED -----/\----- */
+
+endmodule
+
diff --git a/fpga/usrp3/lib/io_cap_gen/cat_io_lvds.v b/fpga/usrp3/lib/io_cap_gen/cat_io_lvds.v
new file mode 100644
index 000000000..e43e26e00
--- /dev/null
+++ b/fpga/usrp3/lib/io_cap_gen/cat_io_lvds.v
@@ -0,0 +1,200 @@
+//
+// Copyright 2016 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: cat_io_lvds
+//
+// Description:
+//
+// This is an LVDS interface for the AD9361 (Catalina). It consists of of an
+// input module for Rx and an output module for Tx. See the AD9361 Interface
+// Specification and the AD9361 data sheet for details.
+//
+// This module assumes a dual-port, full-duplex topology, in 2R2T timing mode.
+// The mimo signal allows you to support one (mimo = 0) or two channels (mimo =
+// 1). When mimo = 0, the data from one channel is simply ignored and radio_clk
+// frequency remains equal to rx_clk_p / 4.
+//
+
+module cat_io_lvds #(
+  parameter INVERT_FRAME_RX    = 0,
+  parameter INVERT_DATA_RX     = 6'b00_0000,
+  parameter INVERT_FRAME_TX    = 0,
+  parameter INVERT_DATA_TX     = 6'b00_0000,
+  parameter USE_CLOCK_IDELAY   = 1,
+  parameter USE_DATA_IDELAY    = 1,
+  parameter DATA_IDELAY_MODE   = "VAR_LOAD",
+  parameter CLOCK_IDELAY_MODE  = "VAR_LOAD",
+  parameter INPUT_CLOCK_DELAY  = 16,
+  parameter INPUT_DATA_DELAY   = 0,
+  parameter USE_CLOCK_ODELAY   = 0,
+  parameter USE_DATA_ODELAY    = 0,
+  parameter DATA_ODELAY_MODE   = "VAR_LOAD",
+  parameter CLOCK_ODELAY_MODE  = "VAR_LOAD",
+  parameter OUTPUT_CLOCK_DELAY = 16,
+  parameter OUTPUT_DATA_DELAY  = 0,
+  parameter USE_BUFG           = 1
+) (
+  input rst,
+  input clk200,
+
+  // Data and frame timing (synchronous to radio_clk)
+  input mimo,
+  input frame_sample,
+
+  // Delay Control Interface
+  input       ctrl_clk,
+  input [4:0] ctrl_in_data_delay,
+  input [4:0] ctrl_in_clk_delay,
+  input       ctrl_ld_in_data_delay,
+  input       ctrl_ld_in_clk_delay,
+  input [4:0] ctrl_out_data_delay,
+  input [4:0] ctrl_out_clk_delay,
+  input       ctrl_ld_out_data_delay,
+  input       ctrl_ld_out_clk_delay,
+
+  // Baseband sample interface
+  output        radio_clk,
+  output        radio_clk_2x,
+  output        rx_aligned,
+  output [11:0] rx_i0,
+  output [11:0] rx_q0,
+  output [11:0] rx_i1,
+  output [11:0] rx_q1,
+  input  [11:0] tx_i0,
+  input  [11:0] tx_q0,
+  input  [11:0] tx_i1,
+  input  [11:0] tx_q1,
+
+  // Catalina LVDS interface
+  input        rx_clk_p,
+  input        rx_clk_n,
+  input        rx_frame_p,
+  input        rx_frame_n,
+  input  [5:0] rx_d_p,
+  input  [5:0] rx_d_n,
+  output       tx_clk_p,
+  output       tx_clk_n,
+  output       tx_frame_p,
+  output       tx_frame_n,
+  output [5:0] tx_d_p,
+  output [5:0] tx_d_n
+);
+
+  wire sdr_clk, ddr_clk;
+
+  //---------------------------------------------------------------------------
+  // Input (Rx) Interface
+  //---------------------------------------------------------------------------
+
+  cat_input_lvds #(
+    .INVERT_FRAME_RX  (INVERT_FRAME_RX),
+    .INVERT_DATA_RX   (INVERT_DATA_RX),
+    .USE_CLOCK_DELAY  (USE_CLOCK_IDELAY),
+    .USE_DATA_DELAY   (USE_DATA_IDELAY),
+    .CLOCK_DELAY_MODE (CLOCK_IDELAY_MODE),
+    .DATA_DELAY_MODE  (DATA_IDELAY_MODE),
+    .CLOCK_DELAY      (INPUT_CLOCK_DELAY),
+    .DATA_DELAY       (INPUT_DATA_DELAY),
+    .WIDTH            (6),
+    .GROUP            ("CATALINA"),
+    .USE_BUFG         (USE_BUFG)
+  ) cat_input_lvds_i0 (
+    .clk200 (clk200),
+    .rst    (rst),
+
+    // Data and frame timing
+    .mimo         (mimo),
+    .frame_sample (frame_sample),
+
+    // Region local Clocks for I/O cells.
+    .ddr_clk (ddr_clk),
+    .sdr_clk (sdr_clk),
+
+    // Source Synchronous external input clock
+    .ddr_clk_p (rx_clk_p),
+    .ddr_clk_n (rx_clk_n),
+
+    // Source Synchronous data lines
+    .ddr_data_p  (rx_d_p),
+    .ddr_data_n  (rx_d_n),
+    .ddr_frame_p (rx_frame_p),
+    .ddr_frame_n (rx_frame_n),
+
+    // Delay control interface
+    .ctrl_clk           (ctrl_clk),
+    .ctrl_data_delay    (ctrl_in_data_delay),
+    .ctrl_clk_delay     (ctrl_in_clk_delay),
+    .ctrl_ld_data_delay (ctrl_ld_in_data_delay),
+    .ctrl_ld_clk_delay  (ctrl_ld_in_clk_delay),
+
+    // SDR output clock(s)
+    .radio_clk    (radio_clk),
+    .radio_clk_2x (radio_clk_2x),
+
+    // SDR Data buses
+    .i0         (rx_i0),
+    .q0         (rx_q0),
+    .i1         (rx_i1),
+    .q1         (rx_q1),
+    .rx_aligned (rx_aligned)
+  );
+
+
+  //---------------------------------------------------------------------------
+  // Output (Tx) Interface
+  //---------------------------------------------------------------------------
+
+  cat_output_lvds #(
+    .INVERT_FRAME_TX  (INVERT_FRAME_TX),
+    .INVERT_DATA_TX   (INVERT_DATA_TX),
+    .USE_CLOCK_DELAY  (USE_CLOCK_ODELAY),
+    .USE_DATA_DELAY   (USE_DATA_ODELAY),
+    .CLOCK_DELAY_MODE (CLOCK_ODELAY_MODE),
+    .DATA_DELAY_MODE  (DATA_ODELAY_MODE),
+    .CLOCK_DELAY      (OUTPUT_CLOCK_DELAY),
+    .DATA_DELAY       (OUTPUT_DATA_DELAY),
+    .WIDTH            (6),
+    .GROUP            ("CATALINA")
+  ) cat_output_lvds_i0 (
+    .clk200 (clk200),
+    .rst    (rst),
+
+    // Two samples per frame period (frame_sample=0; e.g., for two-channel
+    // mode) or one sample per frame (frame_sample=1)
+    .frame_sample(frame_sample),
+
+    // Region local Clocks for I/O cells.
+    .ddr_clk (ddr_clk),
+    .sdr_clk (sdr_clk),
+
+    // Source Synchronous external input clock
+    .ddr_clk_p (tx_clk_p),
+    .ddr_clk_n (tx_clk_n),
+
+    // Source Synchronous data lines
+    .ddr_data_p  (tx_d_p),
+    .ddr_data_n  (tx_d_n),
+    .ddr_frame_p (tx_frame_p),
+    .ddr_frame_n (tx_frame_n),
+
+    // Delay control interface
+    .ctrl_clk           (ctrl_clk),
+    .ctrl_data_delay    (ctrl_out_data_delay),
+    .ctrl_clk_delay     (ctrl_out_clk_delay),
+    .ctrl_ld_data_delay (ctrl_ld_out_data_delay),
+    .ctrl_ld_clk_delay  (ctrl_ld_out_clk_delay),
+
+    // SDR global input clock
+    .radio_clk (radio_clk),
+
+    // SDR Data buses
+    .i0 (tx_i0),
+    .q0 (tx_q0),
+    .i1 (tx_i1),
+    .q1 (tx_q1)
+  );
+
+
+endmodule  // cat_io_lvds
diff --git a/fpga/usrp3/lib/io_cap_gen/cat_io_lvds_dual_mode.v b/fpga/usrp3/lib/io_cap_gen/cat_io_lvds_dual_mode.v
new file mode 100644
index 000000000..13b6ae1f9
--- /dev/null
+++ b/fpga/usrp3/lib/io_cap_gen/cat_io_lvds_dual_mode.v
@@ -0,0 +1,397 @@
+//
+// Copyright 2016 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: cat_io_lvds_dual_mode
+//
+// Description:
+//
+// This is an LVDS interface for the AD9361 (Catalina). It uses the cat_io_lvds 
+// module to implement the interface, but supports both 1R1T and 2R2T timing 
+// modes while using full LVDS bandwidth. That is, it can support 1R1T at twice 
+// the sample rate of 2R2T.
+//
+// This is controlled by the a_mimo control signal. When MIMO = 0 (1R1T mode), 
+// the radio_clk frequency equals that of rx_clk/2 and the data is output to 
+// both radio channels. If MIMO = 1 (2R2T), the frequency of radio_clk equals 
+// rx_clk/4 and the data stream is split between channel 0 and channel 1. This is used 
+// for 2R2T mode.
+//
+
+module cat_io_lvds_dual_mode #(
+  parameter INVERT_FRAME_RX    = 0,
+  parameter INVERT_DATA_RX     = 6'b00_0000,
+  parameter INVERT_FRAME_TX    = 0,
+  parameter INVERT_DATA_TX     = 6'b00_0000,
+  parameter USE_CLOCK_IDELAY   = 1,
+  parameter USE_DATA_IDELAY    = 1,
+  parameter DATA_IDELAY_MODE   = "FIXED",
+  parameter CLOCK_IDELAY_MODE  = "FIXED",
+  parameter INPUT_CLOCK_DELAY  = 16,
+  parameter INPUT_DATA_DELAY   = 0,
+  parameter USE_CLOCK_ODELAY   = 0,
+  parameter USE_DATA_ODELAY    = 0,
+  parameter DATA_ODELAY_MODE   = "FIXED",
+  parameter CLOCK_ODELAY_MODE  = "FIXED",
+  parameter OUTPUT_CLOCK_DELAY = 16,
+  parameter OUTPUT_DATA_DELAY  = 0
+) (
+  input rst,
+  input clk200,
+
+  // Data and frame timing (asynchronous, glitch free)
+  input a_mimo,     // MIMO vs. SISO mode
+  input a_tx_ch,    // Which channel to transmit when MIMO=0
+
+  // Delay Control Interface
+  input       ctrl_clk,
+  input [4:0] ctrl_in_data_delay,
+  input [4:0] ctrl_in_clk_delay,
+  input       ctrl_ld_in_data_delay,
+  input       ctrl_ld_in_clk_delay,
+  input [4:0] ctrl_out_data_delay,
+  input [4:0] ctrl_out_clk_delay,  
+  input       ctrl_ld_out_data_delay,
+  input       ctrl_ld_out_clk_delay,
+
+  // Baseband sample interface
+  output radio_clk,
+  //
+  output reg        rx_aligned,
+  output reg [11:0] rx_i0,
+  output reg [11:0] rx_q0,
+  output reg [11:0] rx_i1,
+  output reg [11:0] rx_q1,
+  //
+  input  [11:0] tx_i0,
+  input  [11:0] tx_q0,
+  input  [11:0] tx_i1,
+  input  [11:0] tx_q1,
+
+  // Catalina LVDS interface
+  input        rx_clk_p,
+  input        rx_clk_n,
+  input        rx_frame_p,
+  input        rx_frame_n,
+  input  [5:0] rx_d_p,
+  input  [5:0] rx_d_n,
+  //
+  output       tx_clk_p,
+  output       tx_clk_n,
+  output       tx_frame_p,
+  output       tx_frame_n,
+  output [5:0] tx_d_p,
+  output [5:0] tx_d_n
+);
+  
+  wire radio_clk_1x;    // rx_clk_p divided by 4
+  wire radio_clk_2x;    // rx_clk_p divided by 2
+
+
+  //---------------------------------------------------------------------------
+  // Mode Selection
+  //---------------------------------------------------------------------------
+
+  wire r_mimo;
+  wire r_tx_ch;
+
+  // Double synchronize the MIMO signal
+  synchronizer mimo_sync (
+    .clk(radio_clk_1x),
+    .rst(1'b0),
+    .in(a_mimo),
+    .out(r_mimo));
+
+  // Double synchronize the Tx channel signal
+  synchronizer tx_ch_sync (
+    .clk(radio_clk_1x),
+    .rst(1'b0),
+    .in(a_tx_ch),
+    .out(r_tx_ch));
+
+
+  //---------------------------------------------------------------------------
+  // Clock Mux
+  //---------------------------------------------------------------------------
+
+  // Use radio_clk_1x when MIMO = 1, radio_clk_2x when MIMO = 0
+  BUFGCTRL BUFGCTRL_radio_clk (
+    .I0      (radio_clk_1x),
+    .I1      (radio_clk_2x),
+    .S0      (r_mimo),
+    .S1      (~r_mimo),
+    .CE0     (1),
+    .CE1     (1),
+    .O       (radio_clk),
+    .IGNORE0 (0),
+    .IGNORE1 (0)
+  );
+
+
+  //---------------------------------------------------------------------------
+  // Generate Alignment Strobes
+  //---------------------------------------------------------------------------
+  //
+  // The LVDS input logic generates the following two clocks:
+  //
+  //   radio_clk_1x   |‾‾‾‾‾|_____|‾‾‾‾‾|_____|‾‾‾‾‾|_____|‾‾‾‾‾|_____|‾‾‾‾‾|
+  //
+  //   radio_clk_2x   |‾‾|__|‾‾|__|‾‾|__|‾‾|__|‾‾|__|‾‾|__|‾‾|__|‾‾|__|‾‾|__|
+  //
+  //
+  // Using simple logic, we create the following two signals from these clocks:
+  //
+  //   align_1x       |‾‾‾‾‾‾‾‾‾‾‾|___________|‾‾‾‾‾‾‾‾‾‾‾|___________|‾‾‾‾‾‾
+  //
+  //   align_2x       ______|‾‾‾‾‾‾‾‾‾‾‾|___________|‾‾‾‾‾‾‾‾‾‾‾|___________|
+  //
+  // These two alignment signals allow us to tell where in the frame period we 
+  // are so that we can deserialize in the correct order.
+  //
+  //---------------------------------------------------------------------------
+
+  reg align_1x = 0;
+  reg align_2x = 0;
+
+  always @(posedge radio_clk_1x)
+  begin
+    align_1x <= ~align_1x;
+  end
+
+  always @(posedge radio_clk_2x)
+  begin
+    // Align data capture to 1x clock so that we stay in sync with data. 
+    // Otherwise, the data might be serialized in the wrong order.
+    align_2x <= align_1x;
+  end
+
+
+  //---------------------------------------------------------------------------
+  // Rx MIMO/SISO Serialization
+  //---------------------------------------------------------------------------
+  //
+  // This block of code takes the dual outputs when in SISO mode and serializes 
+  // them. Because we use the 2x clock when in SISO mode, this allows us to 
+  // double the data rate when using a single channel.
+  //
+  //---------------------------------------------------------------------------
+
+  reg [11:0] rx_i0_ser;
+  reg [11:0] rx_q0_ser;
+  reg [11:0] rx_i1_ser;
+  reg [11:0] rx_q1_ser;
+
+  reg [11:0] rx_i0_out;
+  reg [11:0] rx_q0_out;
+  reg [11:0] rx_i1_out;
+  reg [11:0] rx_q1_out;
+
+  always @(posedge radio_clk_2x)
+  begin
+    rx_aligned <= rx_aligned_t;
+
+    if (align_1x ^ align_2x) begin
+      // This clock cycle corresponds to the first 1x cycle in which two 
+      // samples are output, so grab data from port 0.
+      rx_i0_ser <= rx_i0_t;
+      rx_q0_ser <= rx_q0_t;
+      rx_i1_ser <= rx_i0_t;
+      rx_q1_ser <= rx_q0_t;
+    end else begin
+      // This radio_clk_2x cycle corresponds to the second 1x cycle in which 
+      // two samples are output, so grab data from port 1.
+      rx_i0_ser <= rx_i1_t;
+      rx_q0_ser <= rx_q1_t;
+      rx_i1_ser <= rx_i1_t;
+      rx_q1_ser <= rx_q1_t;
+    end
+
+    // Select the correct Rx output based on MIMO setting
+    if (r_mimo) begin
+      rx_i0_out <= rx_i0_t;
+      rx_q0_out <= rx_q0_t;
+      rx_i1_out <= rx_i1_t;
+      rx_q1_out <= rx_q1_t;
+    end else begin
+      rx_i0_out <= rx_i0_ser;
+      rx_q0_out <= rx_q0_ser;
+      rx_i1_out <= rx_i1_ser;
+      rx_q1_out <= rx_q1_ser;
+    end
+  end
+
+
+  //---------------------------------------------------------------------------
+  // Synchronize Rx to radio_clk Domain
+  //---------------------------------------------------------------------------
+  //
+  //  This crosses the radio data from the radio_clk_1x domain to the radio_clk 
+  //  domain. We use the falling edge of radio_clk to allow for the BUFG 
+  //  insertion delay.
+  //
+  //---------------------------------------------------------------------------
+
+  reg [11:0] rx_i0_fall;
+  reg [11:0] rx_q0_fall;
+  reg [11:0] rx_i1_fall;
+  reg [11:0] rx_q1_fall;
+   
+  always @(negedge radio_clk)
+  begin
+    rx_i0_fall <= rx_i0_out;
+    rx_q0_fall <= rx_q0_out;
+    rx_i1_fall <= rx_i1_out;
+    rx_q1_fall <= rx_q1_out;
+  end
+
+  // Re-clock data on the rising edge to present the whole period to external IP
+  always @(posedge radio_clk)
+  begin
+    rx_i0 <= rx_i0_fall;
+    rx_q0 <= rx_q0_fall;
+    rx_i1 <= rx_i1_fall;
+    rx_q1 <= rx_q1_fall;
+  end
+
+
+  //---------------------------------------------------------------------------
+  // Tx MIMO/SISO Deserialization
+  //---------------------------------------------------------------------------
+  //
+  // This block of code takes the serialized output from the radios and 
+  // parallelizes it onto the two radio ports of the Catalina interface. It 
+  // also takes the radio data, output on the radio_clk domain, and crosses it 
+  // to the radio_clk_1x domain.
+  //
+  //---------------------------------------------------------------------------
+
+  reg [11:0] tx_i0_del;
+  reg [11:0] tx_q0_del;
+  reg [11:0] tx_i1_del;
+  reg [11:0] tx_q1_del;
+
+  always @(posedge radio_clk_2x)
+  begin
+    // Capture copy of the data delayed by one radio_clk_2c cycle.
+    tx_i0_del <= tx_i0;
+    tx_q0_del <= tx_q0;
+    tx_i1_del <= tx_i1;
+    tx_q1_del <= tx_q1;
+  end
+
+  always @(posedge radio_clk_1x)
+  begin
+    if (r_mimo) begin
+      // In MIMO mode, radio_clk is radio_clk_1x, so we just capture the same 
+      // data for each radio_clk_1x cycle.
+      tx_i0_t <= tx_i0;
+      tx_q0_t <= tx_q0;
+      tx_i1_t <= tx_i1;
+      tx_q1_t <= tx_q1;
+    end else begin
+      // In SISO mode, data is updated every radio_clk_2x cycle, so we output 
+      // the data from the previous radio_clk_2x cycle onto channel 0 and the 
+      // data from the current radio_clk_2x cycle onto channel 1. This puts the 
+      // data in the correct order when in 1R1T mode.
+      if (r_tx_ch == 0) begin
+        tx_i0_t <= tx_i0_del;
+        tx_q0_t <= tx_q0_del;
+        tx_i1_t <= tx_i0;
+        tx_q1_t <= tx_q0;
+      end else begin
+        tx_i0_t <= tx_i1_del;
+        tx_q0_t <= tx_q1_del;
+        tx_i1_t <= tx_i1;
+        tx_q1_t <= tx_q1;
+      end
+    end
+  end
+
+
+  //---------------------------------------------------------------------------
+  // Catalina TX/RX Interface
+  //---------------------------------------------------------------------------
+
+  wire        rx_aligned_t;
+  wire [11:0] rx_i0_t;
+  wire [11:0] rx_q0_t;
+  wire [11:0] rx_i1_t;
+  wire [11:0] rx_q1_t;
+
+  reg [11:0] tx_i0_t;
+  reg [11:0] tx_q0_t;
+  reg [11:0] tx_i1_t;
+  reg [11:0] tx_q1_t;
+  
+  cat_io_lvds #(
+    .INVERT_FRAME_RX    (0),
+    .INVERT_DATA_RX     (6'b00_0000),
+    .INVERT_FRAME_TX    (0),
+    .INVERT_DATA_TX     (6'b00_0000),
+    .USE_CLOCK_IDELAY   (USE_CLOCK_IDELAY),
+    .USE_DATA_IDELAY    (USE_DATA_IDELAY),
+    .DATA_IDELAY_MODE   (DATA_IDELAY_MODE),
+    .CLOCK_IDELAY_MODE  (CLOCK_IDELAY_MODE),
+    .INPUT_CLOCK_DELAY  (INPUT_CLOCK_DELAY),
+    .INPUT_DATA_DELAY   (INPUT_DATA_DELAY),
+    .USE_CLOCK_ODELAY   (USE_CLOCK_ODELAY),
+    .USE_DATA_ODELAY    (USE_DATA_ODELAY),
+    .DATA_ODELAY_MODE   (DATA_ODELAY_MODE),
+    .CLOCK_ODELAY_MODE  (CLOCK_ODELAY_MODE),
+    .OUTPUT_CLOCK_DELAY (OUTPUT_CLOCK_DELAY),
+    .OUTPUT_DATA_DELAY  (OUTPUT_DATA_DELAY),
+    .USE_BUFG           (0)
+  ) cat_io_lvds_i0 (
+    .rst    (rst),
+    .clk200 (clk200),
+    
+    // Data and frame timing
+    .mimo         (1),       // Set to 1 to always return all samples
+    .frame_sample (~r_mimo), // Frame timing corresponds to SISO/MIMO setting
+    
+    // Delay control interface
+    .ctrl_clk               (ctrl_clk),
+    //
+    .ctrl_in_data_delay     (ctrl_in_data_delay),
+    .ctrl_in_clk_delay      (ctrl_in_clk_delay),
+    .ctrl_ld_in_data_delay  (ctrl_ld_in_data_delay),
+    .ctrl_ld_in_clk_delay   (ctrl_ld_in_clk_delay),
+    //
+    .ctrl_out_data_delay    (ctrl_out_data_delay),
+    .ctrl_out_clk_delay     (ctrl_out_clk_delay),
+    .ctrl_ld_out_data_delay (ctrl_ld_out_data_delay),
+    .ctrl_ld_out_clk_delay  (ctrl_ld_out_clk_delay),
+    
+    // Baseband sample interface
+    .radio_clk    (radio_clk_1x),
+    .radio_clk_2x (radio_clk_2x),
+    .rx_aligned   (rx_aligned_t),
+    //
+    .rx_i0        (rx_i0_t),
+    .rx_q0        (rx_q0_t),
+    .rx_i1        (rx_i1_t),
+    .rx_q1        (rx_q1_t),
+    //
+    .tx_i0        (tx_i0_t),
+    .tx_q0        (tx_q0_t),
+    .tx_i1        (tx_i1_t),
+    .tx_q1        (tx_q1_t),
+    
+    // Catalina interface
+    .rx_clk_p   (rx_clk_p),
+    .rx_clk_n   (rx_clk_n),
+    .rx_frame_p (rx_frame_p),
+    .rx_frame_n (rx_frame_n),
+    .rx_d_p     (rx_d_p),
+    .rx_d_n     (rx_d_n),
+    //
+    .tx_clk_p   (tx_clk_p),
+    .tx_clk_n   (tx_clk_n),
+    .tx_frame_p (tx_frame_p),
+    .tx_frame_n (tx_frame_n),
+    .tx_d_p     (tx_d_p),
+    .tx_d_n     (tx_d_n)
+  );
+
+endmodule  // cat_io_lvds_dual_mode
diff --git a/fpga/usrp3/lib/io_cap_gen/cat_output_lvds.v b/fpga/usrp3/lib/io_cap_gen/cat_output_lvds.v
new file mode 100644
index 000000000..2c412d7f3
--- /dev/null
+++ b/fpga/usrp3/lib/io_cap_gen/cat_output_lvds.v
@@ -0,0 +1,396 @@
+//
+// Copyright 2016 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: cat_output_lvds
+// Description: Transmit interface to AD9361 in LVDS mode.
+//
+// The frame_sample signal controls the expected frame signal timing. When 
+// frame_sample is 0, the period of the ddr_frame signal will be equal to two 
+// samples (e.g., one from each channel). When frame_sample is 1, the frame 
+// period will be equal to the length of one sample. This allows the module to 
+// be used for 2R2T (frame_sample = 1) or 1R1T mode (frame_sample = 0).
+
+
+module cat_output_lvds #(
+  parameter INVERT_FRAME_TX   = 0,
+  parameter INVERT_DATA_TX    = 6'b00_0000,
+  parameter USE_CLOCK_DELAY   = 1,
+  parameter USE_DATA_DELAY    = 1,
+  parameter CLOCK_DELAY_MODE = "VAR_LOAD",
+  parameter DATA_DELAY_MODE  = "VAR_LOAD",
+  parameter CLOCK_DELAY       = 0,
+  parameter DATA_DELAY        = 0,
+  parameter WIDTH             = 6,
+  parameter GROUP             = "DEFAULT"
+) (
+  input clk200,
+  input rst,
+
+  // Data and frame timing (synchronous to radio_clk)
+  input frame_sample,  // Two samples per frame period (frame_sample=0) or one sample per frame (frame_sample=1)
+
+  // Region local Clocks for I/O cells.
+  input ddr_clk,
+  input sdr_clk,
+
+  // Source synchronous external input clock
+  output ddr_clk_p,
+  output ddr_clk_n,
+
+  // Source synchronous data lines
+  output [WIDTH-1:0] ddr_data_p,
+  output [WIDTH-1:0] ddr_data_n,
+  output             ddr_frame_p,
+  output             ddr_frame_n,
+
+  // Delay control interface
+  input       ctrl_clk,
+  input [4:0] ctrl_data_delay,
+  input [4:0] ctrl_clk_delay,
+  input       ctrl_ld_data_delay,
+  input       ctrl_ld_clk_delay,
+
+  // Global input clock
+  input radio_clk,
+
+  // SDR data buses
+  input [(WIDTH*2)-1:0] i0,
+  input [(WIDTH*2)-1:0] q0,
+  input [(WIDTH*2)-1:0] i1,
+  input [(WIDTH*2)-1:0] q1
+
+);
+
+
+  //------------------------------------------------------------------
+  // UG471 says take reset high asynchronously, and de-assert
+  // synchronized to CLKDIV (sdr_clk) for SERDES.
+  //------------------------------------------------------------------
+  reg rst_sdr_sync;
+
+  always @(posedge sdr_clk or posedge rst)
+    if (rst)
+      rst_sdr_sync <= 1'b1;
+    else
+      rst_sdr_sync <= 1'b0;
+
+  //------------------------------------------------------------------
+  // Route radio data to SERDES for SISO and MIMO modes.
+  //------------------------------------------------------------------
+  reg [(WIDTH*2)-1:0] radio_data_i0, radio_data_q0;
+  reg [(WIDTH*2)-1:0] radio_data_i1, radio_data_q1;
+  reg [(WIDTH*2)-1:0] data_i0, data_q0, data_i1, data_q1;
+  //
+  //
+  always @(posedge radio_clk)
+  begin
+    // When in 2R2T mode, data mapping is the same for SISO and MIMO. The data
+    // for channel 1 will be ignored.
+    radio_data_i0 <= i0;
+    radio_data_q0 <= q0;
+    radio_data_i1 <= i1;
+    radio_data_q1 <= q1;
+  end
+
+  //
+  // Cross data into sdr_clock domain.
+  // sdr_clock leads radio_clk in phase by insertion delay of BUFG.
+  // We can transfer data in this direction with no special logic.
+  // Path length must be radio_clk period - BUFG delay to make timing.
+  //
+  always @(posedge sdr_clk)
+  begin
+    data_i0 <= radio_data_i0 ^ {INVERT_DATA_TX,INVERT_DATA_TX};
+    data_q0 <= radio_data_q0 ^ {INVERT_DATA_TX,INVERT_DATA_TX};
+    data_i1 <= radio_data_i1 ^ {INVERT_DATA_TX,INVERT_DATA_TX};
+    data_q1 <= radio_data_q1 ^ {INVERT_DATA_TX,INVERT_DATA_TX};
+  end
+
+  //------------------------------------------------------------------
+  // Clock output
+  //------------------------------------------------------------------
+  wire ddr_clk_out, ddr_clk_dly;
+
+  OSERDESE2 #(
+    .DATA_RATE_OQ   ("DDR"),    // DDR, SDR
+    .DATA_RATE_TQ   ("DDR"),    // DDR, BUF, SDR
+    .DATA_WIDTH     (8),        // Parallel data width (2-8,10,14)
+    .INIT_OQ        (1'b0),     // Initial value of OQ output (1'b0,1'b1)
+    .INIT_TQ        (1'b0),     // Initial value of TQ output (1'b0,1'b1)
+    .SERDES_MODE    ("MASTER"), // MASTER, SLAVE
+    .SRVAL_OQ       (1'b0),     // OQ output value when SR is used (1'b0,1'b1)
+    .SRVAL_TQ       (1'b0),     // TQ output value when SR is used (1'b0,1'b1)
+    .TBYTE_CTL      ("FALSE"),  // Enable tristate byte operation (FALSE, TRUE)
+    .TBYTE_SRC      ("FALSE"),  // Tristate byte source (FALSE, TRUE)
+    .TRISTATE_WIDTH (1)         // 3-state converter width (1,4)
+  ) ddr_clk_oserdese2 (
+    .OFB       (),             // High-speed data output to ODELAYE2
+    .OQ        (ddr_clk_out),  // High-speed data output direct to OBUF
+    // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
+    .SHIFTOUT1 (),
+    .SHIFTOUT2 (),
+    .TBYTEOUT  (),
+    .TFB       (),
+    .TQ        (),
+    .CLK       (ddr_clk),
+    .CLKDIV    (sdr_clk),
+    // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
+    .D1        (1'b1),         // Canned Clock waveform synthesized as data.
+    .D2        (1'b0),
+    .D3        (1'b1),
+    .D4        (1'b0),
+    .D5        (1'b1),
+    .D6        (1'b0),
+    .D7        (1'b1),
+    .D8        (1'b0),
+    .OCE       (1'b1),         // Active high clock enable
+    .RST       (rst_sdr_sync),
+    // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
+    .SHIFTIN1  (1'b0),
+    .SHIFTIN2  (1'b0),
+    // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
+    .T1        (1'b0),
+    .T2        (1'b0),
+    .T3        (1'b0),
+    .T4        (1'b0),
+    .TBYTEIN   (1'b0),
+    .TCE       (1'b0)
+  );
+
+  generate
+    if (USE_CLOCK_DELAY) begin : gen_clock_odelay
+      (* IODELAY_GROUP = GROUP *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL
+      ODELAYE2 #(
+        .CINVCTRL_SEL          ("FALSE"),          // Enable dynamic clock inversion (FALSE, TRUE)
+        .DELAY_SRC             ("ODATAIN"),        // Delay input (ODATAIN, CLKIN)
+        .HIGH_PERFORMANCE_MODE ("FALSE"),          // Reduced jitter ("TRUE"), Reduced power ("FALSE")
+        .ODELAY_TYPE           (CLOCK_DELAY_MODE), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
+        .ODELAY_VALUE          (CLOCK_DELAY),      // Output delay tap setting (0-31)
+        .PIPE_SEL              ("FALSE"),          // Select pipelined mode, FALSE, TRUE
+        .REFCLK_FREQUENCY      (200.0),            // IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0).
+        .SIGNAL_PATTERN        ("CLOCK")           // DATA, CLOCK input signal
+      ) ddr_clk_odelaye2 (
+        .CNTVALUEOUT (),                  // 5-bit output: Counter value output
+        .DATAOUT     (ddr_clk_dly),       // 1-bit output: Delayed data/clock output
+        .C           (ctrl_clk),          // 1-bit input: Clock input
+        .CE          (1'b0),              // 1-bit input: Active high enable increment/decrement input
+        .CINVCTRL    (1'b0),              // 1-bit input: Dynamic clock inversion input
+        .CLKIN       (1'b0),              // 1-bit input: Clock delay input
+        .CNTVALUEIN  (ctrl_clk_delay),    // 5-bit input: Counter value input
+        .INC         (1'b0),              // 1-bit input: Increment / Decrement tap delay input
+        .LD          (ctrl_ld_clk_delay), // 1-bit input: Loads ODELAY_VALUE tap delay in VARIABLE mode, in VAR_LOAD or
+                                          //              VAR_LOAD_PIPE mode, loads the value of CNTVALUEIN
+        .LDPIPEEN    (1'b0),              // 1-bit input: Enables the pipeline register to load data
+        .ODATAIN     (ddr_clk_out),       // 1-bit input: Output delay data input
+        .REGRST      (1'b0)               // 1-bit input: Active-high reset tap-delay input
+      );
+    end else begin
+      assign ddr_clk_dly = ddr_clk_out;
+    end
+  endgenerate
+
+
+
+  OBUFDS ddr_clk_obuf (
+    .O  (ddr_clk_p),   // Diff_p output (connect directly to top-level port)
+    .OB (ddr_clk_n),   // Diff_n output (connect directly to top-level port)
+    .I  (ddr_clk_dly)  // Buffer input
+  );
+
+
+
+  //------------------------------------------------------------------
+  // Frame Signal
+  //------------------------------------------------------------------
+  wire ddr_frame, ddr_frame_dly;
+
+  OSERDESE2 #(
+    .DATA_RATE_OQ   ("DDR"),    // DDR, SDR
+    .DATA_RATE_TQ   ("DDR"),    // DDR, BUF, SDR
+    .DATA_WIDTH     (8),        // Parallel data width (2-8,10,14)
+    .INIT_OQ        (1'b0),     // Initial value of OQ output (1'b0,1'b1)
+    .INIT_TQ        (1'b0),     // Initial value of TQ output (1'b0,1'b1)
+    .SERDES_MODE    ("MASTER"), // MASTER, SLAVE
+    .SRVAL_OQ       (1'b0),     // OQ output value when SR is used (1'b0,1'b1)
+    .SRVAL_TQ       (1'b0),     // TQ output value when SR is used (1'b0,1'b1)
+    .TBYTE_CTL      ("FALSE"),  // Enable tristate byte operation (FALSE, TRUE)
+    .TBYTE_SRC      ("FALSE"),  // Tristate byte source (FALSE, TRUE)
+    .TRISTATE_WIDTH (1)         // 3-state converter width (1,4)
+  ) ddr_frame_oserdese2 (
+    .OFB       (),                 // High-speed data output to ODELAYE2
+    .OQ        (ddr_frame),        // High-speed data output direct to OBUF
+    // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
+    .SHIFTOUT1 (),
+    .SHIFTOUT2 (),
+    .TBYTEOUT  (),
+    .TFB       (),
+    .TQ        (),
+    .CLK       (ddr_clk),
+    .CLKDIV    (sdr_clk),
+    // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each). Frame is 
+    // either 11110000 or 11001100 depending on if frame_sample is true or 
+    // false, respectively, and it can be inverted by INVERT_FRAME_TX, becoming 
+    // 00001111 or 00110011.
+    .D1        (~INVERT_FRAME_TX[0]),
+    .D2        (~INVERT_FRAME_TX[0]),
+    .D3        (INVERT_FRAME_TX[0] ~^ frame_sample),
+    .D4        (INVERT_FRAME_TX[0] ~^ frame_sample),
+    .D5        (INVERT_FRAME_TX[0]  ^ frame_sample),
+    .D6        (INVERT_FRAME_TX[0]  ^ frame_sample),
+    .D7        (INVERT_FRAME_TX[0]),
+    .D8        (INVERT_FRAME_TX[0]),
+    .OCE       (1'b1),             // Active high clock enable
+    .RST       (rst_sdr_sync),
+    // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
+    .SHIFTIN1  (1'b0),
+    .SHIFTIN2  (1'b0),
+    // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
+    .T1        (1'b0),
+    .T2        (1'b0),
+    .T3        (1'b0),
+    .T4        (1'b0),
+    .TBYTEIN   (1'b0),
+    .TCE       (1'b0)
+  );
+
+  generate
+    if (USE_DATA_DELAY) begin : gen_frame_odelay
+      (* IODELAY_GROUP = GROUP *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL
+      ODELAYE2 #(
+        .CINVCTRL_SEL          ("FALSE"),         // Enable dynamic clock inversion (FALSE, TRUE)
+        .DELAY_SRC             ("ODATAIN"),       // Delay input (ODATAIN, CLKIN)
+        .HIGH_PERFORMANCE_MODE ("FALSE"),         // Reduced jitter ("TRUE"), Reduced power ("FALSE")
+        .ODELAY_TYPE           (DATA_DELAY_MODE), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
+        .ODELAY_VALUE          (DATA_DELAY),      // Output delay tap setting (0-31)
+        .PIPE_SEL              ("FALSE"),         // Select pipelined mode, FALSE, TRUE
+        .REFCLK_FREQUENCY      (200.0),           // IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0).
+        .SIGNAL_PATTERN        ("DATA")           // DATA, CLOCK input signal
+      ) ddr_frame_odelaye2 (
+        .CNTVALUEOUT (),                   // 5-bit output: Counter value output
+        .DATAOUT     (ddr_frame_dly),      // 1-bit output: Delayed data/clock output
+        .C           (ctrl_clk),           // 1-bit input: Clock input
+        .CE          (1'b0),               // 1-bit input: Active high enable increment/decrement input
+        .CINVCTRL    (1'b0),               // 1-bit input: Dynamic clock inversion input
+        .CLKIN       (1'b0),               // 1-bit input: Clock delay input
+        .CNTVALUEIN  (ctrl_data_delay),    // 5-bit input: Counter value input
+        .INC         (1'b0),               // 1-bit input: Increment / Decrement tap delay input
+        .LD          (ctrl_ld_data_delay), // 1-bit input: Loads ODELAY_VALUE tap delay in VARIABLE mode, in VAR_LOAD or
+                                           //              VAR_LOAD_PIPE mode, loads the value of CNTVALUEIN
+        .LDPIPEEN    (1'b0),               // 1-bit input: Enables the pipeline register to load data
+        .ODATAIN     (ddr_frame),          // 1-bit input: Output delay data input
+        .REGRST      (1'b0)                // 1-bit input: Active-high reset tap-delay input
+      );
+    end else begin
+      assign ddr_frame_dly = ddr_frame;
+    end
+  endgenerate
+
+  OBUFDS ddr_frame_obuf (
+    .O  (ddr_frame_p),   // Diff_p output (connect directly to top-level port)
+    .OB (ddr_frame_n),   // Diff_n output (connect directly to top-level port)
+    .I  (ddr_frame_dly)  // Buffer input
+  );
+
+
+  //------------------------------------------------------------------
+  // Data Bus
+  //------------------------------------------------------------------
+  wire [WIDTH-1:0] ddr_data;
+  wire [WIDTH-1:0] ddr_data_dly ;
+
+
+  // wire [(WIDTH*2)-1:0] sdr_data_i;
+  // wire [(WIDTH*2)-1:0] sdr_data_q;
+
+  genvar i;
+  generate
+    for (i=0 ; i<WIDTH ; i=i+1) begin : generate_data_bus
+
+      OSERDESE2 #(
+        .DATA_RATE_OQ   ("DDR"),    // DDR, SDR
+        .DATA_RATE_TQ   ("DDR"),    // DDR, BUF, SDR
+        .DATA_WIDTH     (8),        // Parallel data width (2-8,10,14)
+        .INIT_OQ        (1'b0),     // Initial value of OQ output (1'b0,1'b1)
+        .INIT_TQ        (1'b0),     // Initial value of TQ output (1'b0,1'b1)
+        .SERDES_MODE    ("MASTER"), // MASTER, SLAVE
+        .SRVAL_OQ       (1'b0),     // OQ output value when SR is used (1'b0,1'b1)
+        .SRVAL_TQ       (1'b0),     // TQ output value when SR is used (1'b0,1'b1)
+        .TBYTE_CTL      ("FALSE"),  // Enable tristate byte operation (FALSE, TRUE)
+        .TBYTE_SRC      ("FALSE"),  // Tristate byte source (FALSE, TRUE)
+        .TRISTATE_WIDTH (1)         // 3-state converter width (1,4)
+      ) ddr_data_oserdese2 (
+        .OFB       (),                 // High-speed data output to ODELAYE2
+        .OQ        (ddr_data[i]),      // High-speed data output direct to OBUF
+        // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
+        .SHIFTOUT1 (),
+        .SHIFTOUT2 (),
+        .TBYTEOUT  (),
+        .TFB       (),
+        .TQ        (),
+        .CLK       (ddr_clk),
+        .CLKDIV    (sdr_clk),
+        // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
+        .D1        (data_i0[WIDTH+i]),
+        .D2        (data_q0[WIDTH+i]),
+        .D3        (data_i0[i]),
+        .D4        (data_q0[i]),
+        .D5        (data_i1[WIDTH+i]),
+        .D6        (data_q1[WIDTH+i]),
+        .D7        (data_i1[i]),
+        .D8        (data_q1[i]),
+        .OCE       (1'b1),             // Active high clock enable
+        .RST       (rst_sdr_sync),
+        // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
+        .SHIFTIN1  (1'b0),
+        .SHIFTIN2  (1'b0),
+        // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
+        .T1        (1'b0),
+        .T2        (1'b0),
+        .T3        (1'b0),
+        .T4        (1'b0),
+        .TBYTEIN   (1'b0),
+        .TCE       (1'b0)
+      );
+
+      if (USE_DATA_DELAY) begin : gen_data_odelay
+        (* IODELAY_GROUP = GROUP *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL
+        ODELAYE2 #(
+          .CINVCTRL_SEL          ("FALSE"),         // Enable dynamic clock inversion (FALSE, TRUE)
+          .DELAY_SRC             ("ODATAIN"),       // Delay input (ODATAIN, CLKIN)
+          .HIGH_PERFORMANCE_MODE ("FALSE"),         // Reduced jitter ("TRUE"), Reduced power ("FALSE")
+          .ODELAY_TYPE           (DATA_DELAY_MODE), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
+          .ODELAY_VALUE          (DATA_DELAY),      // Output delay tap setting (0-31)
+          .PIPE_SEL              ("FALSE"),         // Select pipelined mode, FALSE, TRUE
+          .REFCLK_FREQUENCY      (200.0),           // IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0).
+          .SIGNAL_PATTERN        ("DATA")           // DATA, CLOCK input signal
+        ) ddr_data_odelaye2 (
+          .CNTVALUEOUT (),                   // 5-bit output: Counter value output
+          .DATAOUT     (ddr_data_dly[i]),    // 1-bit output: Delayed data/clock output
+          .C           (ctrl_clk),           // 1-bit input: Clock input
+          .CE          (1'b0),               // 1-bit input: Active high enable increment/decrement input
+          .CINVCTRL    (1'b0),               // 1-bit input: Dynamic clock inversion input
+          .CLKIN       (1'b0),               // 1-bit input: Clock delay input
+          .CNTVALUEIN  (ctrl_data_delay),    // 5-bit input: Counter value input
+          .INC         (1'b0),               // 1-bit input: Increment / Decrement tap delay input
+          .LD          (ctrl_ld_data_delay), // 1-bit input: Loads ODELAY_VALUE tap delay in VARIABLE mode, in VAR_LOAD or
+                                             //              VAR_LOAD_PIPE mode, loads the value of CNTVALUEIN
+          .LDPIPEEN    (1'b0),               // 1-bit input: Enables the pipeline register to load data
+          .ODATAIN     (ddr_data[i]),        // 1-bit input: Output delay data input
+          .REGRST      (1'b0)                // 1-bit input: Active-high reset tap-delay input
+        );
+      end else begin
+        assign ddr_data_dly[i] = ddr_data[i];
+      end
+
+      OBUFDS ddr_data_obuf (
+        .O  (ddr_data_p[i]),   // Diff_p output (connect directly to top-level port)
+        .OB (ddr_data_n[i]),   // Diff_n output (connect directly to top-level port)
+        .I  (ddr_data_dly[i])  // Buffer input
+      );
+    end // block: generate_data_bus
+
+  endgenerate
+
+endmodule // cat_output_lvds
diff --git a/fpga/usrp3/lib/io_cap_gen/catcap_ddr_cmos.v b/fpga/usrp3/lib/io_cap_gen/catcap_ddr_cmos.v
new file mode 100644
index 000000000..bb4c77f0d
--- /dev/null
+++ b/fpga/usrp3/lib/io_cap_gen/catcap_ddr_cmos.v
@@ -0,0 +1,95 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module catcap_ddr_cmos
+#(
+  parameter DEVICE = "7SERIES" // "7SERIES" or "SPARTAN6"
+)
+(
+  input             data_clk,
+  input             mimo,
+  input             rx_frame,
+  input [11:0]      rx_d,
+  output            rx_clk, output rx_strobe,
+  output reg [11:0] i0, output reg [11:0] q0,
+  output reg [11:0] i1, output reg [11:0] q1
+);
+
+  wire [11:0]       i,q;
+  wire              frame_0, frame_1;
+
+  genvar            z;
+
+  generate
+    for(z = 0; z < 12; z = z + 1)
+      begin : gen_pins
+        if (DEVICE == "SPARTAN6") begin
+          // i[] & q[] swapped
+          IDDR2 #(
+            .DDR_ALIGNMENT("C0"))
+          iddr2 (
+            .Q0(q[z]), .Q1(i[z]), .C0(data_clk), .C1(~data_clk),
+            .CE(1'b1), .D(rx_d[z]), .R(1'b0), .S(1'b0));
+        end
+        else if (DEVICE == "7SERIES") begin
+          IDDR #(
+            .DDR_CLK_EDGE("SAME_EDGE"))
+          iddr (
+            .Q1(q[z]), .Q2(i[z]), .C(data_clk),
+            .CE(1'b1), .D(rx_d[z]), .R(1'b0), .S(1'b0));
+        end
+      end
+  endgenerate
+
+  generate
+    if (DEVICE == "SPARTAN6") begin
+      IDDR2 #(
+        .DDR_ALIGNMENT("C0"))
+      iddr2_frame (
+        .Q0(frame_0), .Q1(frame_1), .C0(data_clk), .C1(~data_clk),
+        .CE(1'b1), .D(rx_frame), .R(1'b0), .S(1'b0));
+    end
+    else if (DEVICE == "7SERIES") begin
+      IDDR #(
+        .DDR_CLK_EDGE("SAME_EDGE"))
+      iddr_frame (
+        .Q1(frame_0), .Q2(frame_1), .C(data_clk),
+        .CE(1'b1), .D(rx_frame), .R(1'b0), .S(1'b0));
+    end
+  endgenerate
+
+  reg frame_d1, frame_d2;
+  always @(posedge data_clk)
+    if(~mimo)
+      { frame_d2, frame_d1 } <= { frame_1, 1'b0 };
+    else
+      { frame_d2, frame_d1 } <= { frame_d1, frame_1 };
+
+  assign rx_strobe = frame_d2;
+
+  reg [11:0] i_del, q_del;
+  always @(posedge data_clk)
+    if(mimo)
+      if(frame_0) begin
+        i_del <= i;
+        q_del <= q;
+      end
+      else begin
+        i1 <= i;
+        q1 <= q;
+        i0 <= i_del;
+        q0 <= q_del;
+    end
+    else begin
+      i0 <= i;
+      q0 <= q;
+      i1 <= i;
+      q1 <= q;
+    end
+  assign rx_clk = data_clk;
+
+endmodule // catcap_ddr_cmos
diff --git a/fpga/usrp3/lib/io_cap_gen/catcodec_ddr_cmos.v b/fpga/usrp3/lib/io_cap_gen/catcodec_ddr_cmos.v
new file mode 100644
index 000000000..44aa4d8f9
--- /dev/null
+++ b/fpga/usrp3/lib/io_cap_gen/catcodec_ddr_cmos.v
@@ -0,0 +1,123 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module catcodec_ddr_cmos
+#(
+  parameter DEVICE = "SPARTAN6"  // "7SERIES" or "SPARTAN6", determines device specific implementation of clock divider
+)
+(
+  //output source sync clock for baseband data
+  output radio_clk,
+
+  //async reset for clocking
+  input arst,
+
+  //control mimo mode
+  input mimo,
+
+  //baseband sample interface
+  output reg [31:0] rx1,
+  output reg [31:0] rx2,
+  input [31:0] tx1,
+  input [31:0] tx2,
+
+  //capture interface
+  input rx_clk,
+  input rx_frame,
+  input [11:0] rx_d,
+
+  //generate interface
+  output tx_clk,
+  output tx_frame,
+  output [11:0] tx_d
+);
+
+  wire clk0, clkdv;
+  wire codec_clk, half_clk;
+  wire radio_clk_locked;
+
+  // Synchronize MIMO signal into codec_clk domain
+  wire mimo_r;
+  synchronizer mimo_sync (
+    .clk(codec_clk),
+    .rst(1'b0),
+    .in(mimo),
+    .out(mimo_r));
+
+  generate
+    if (DEVICE == "SPARTAN6") begin
+      DCM_SP #(
+        .CLKDV_DIVIDE(2),
+        .CLK_FEEDBACK("1X"))
+      DCM_SP_codec_clk (
+        .RST(arst),
+        .CLKIN(rx_clk), .CLKFB(clk0),
+        .CLK0(clk0), .CLKDV(clkdv),
+        .LOCKED(radio_clk_locked));
+      BUFG BUFG_codec_clk(.I(clk0), .O(codec_clk));
+      BUFG BUFG_half_clk(.I(clkdv), .O(half_clk));
+      BUFGMUX BUFGMUX_radio_clk (.I0(codec_clk), .I1(half_clk), .S(mimo_r), .O(radio_clk));
+    end
+    else if (DEVICE == "7SERIES") begin
+      wire rx_clk_ibufg, clkfb_out, clkfb_in;
+      // Create clocks for source synchronous interface
+      // Goal is to create a capture clock (codec_clk) and a sample clock (radio_clk).
+      // - Capture clock's and source clock's (rx_clk) phase are aligned due to
+      //   the MMCM's deskew ability (see the BUFG in the feedback clock path).
+      // - BUFGCTRL muxes between the 1x and 1/2x clocks depending on MIMO mode. In MIMO mode, the 1/2x
+      //   clock is used, because the sample clock rate is half the source clock rate.
+      // - Locked signal is used to ensure the BUFG's output is disabled if the MMCM is not locked.
+      // - Avoided cascading BUFGs to ensure minimal skew between codec_clk and radio_clk.
+      catcodec_mmcm inst_catcodec_mmcm (
+        .CLK_IN1(rx_clk_ibufg),
+        .CLK_OUT(clk0),
+        .CLK_OUT_DIV2(clkdv),
+        .CLKFB_IN(clkfb_in),
+        .CLKFB_OUT(clkfb_out),
+        .RESET(arst),
+        .LOCKED(radio_clk_locked));
+      IBUFG (.I(rx_clk), .O(rx_clk_ibufg));
+      BUFG (.I(clkfb_out), .O(clkfb_in));
+      BUFGCE (.I(clk0), .O(codec_clk), .CE(radio_clk_locked));
+      BUFGCTRL BUFGCTRL_radio_clk (.I0(clk0), .I1(clkdv), .S0(~mimo_r), .S1(mimo_r), .CE0(radio_clk_locked), .CE1(radio_clk_locked), .O(radio_clk));
+    end
+  endgenerate
+
+  //assign baseband sample interfaces
+  //all samples are registered on strobe
+  wire rx_strobe, tx_strobe;
+  wire [11:0] rx_i0, rx_q0, rx_i1, rx_q1;
+  reg [11:0] tx_i0, tx_q0, tx_i1, tx_q1;
+  //tx mux to feed single channel mode from either input
+  wire [31:0] txm = (mimo_r || (tx1 != 32'b0))? tx1: tx2;
+  always @(posedge codec_clk) begin
+    if (rx_strobe) rx2 <= {rx_i1, 4'b0, rx_q1, 4'b0};
+    if (rx_strobe) rx1 <= {rx_i0, 4'b0, rx_q0, 4'b0};
+    if (tx_strobe) {tx_i0, tx_q0} <= {txm[31:20], txm[15:4]};
+    if (tx_strobe) {tx_i1, tx_q1} <= {tx2[31:20], tx2[15:4]};
+  end
+
+  // CMOS Data interface to AD9361
+  catcap_ddr_cmos #(
+    .DEVICE(DEVICE))
+  catcap (
+    .data_clk(codec_clk), .mimo(mimo_r),
+    .rx_frame(rx_frame), .rx_d(rx_d),
+    .rx_clk(/*out*/), .rx_strobe(rx_strobe),
+    .i0(rx_i0), .q0(rx_q0),
+    .i1(rx_i1), .q1(rx_q1));
+
+   catgen_ddr_cmos #(
+    .DEVICE(DEVICE))
+   catgen (
+    .data_clk(tx_clk), .mimo(mimo_r),
+    .tx_frame(tx_frame), .tx_d(tx_d),
+    .tx_clk(codec_clk), .tx_strobe(tx_strobe),
+    .i0(tx_i0), .q0(tx_q0),
+    .i1(tx_i1), .q1(tx_q1));
+
+endmodule // catcodec_ddr_cmos
diff --git a/fpga/usrp3/lib/io_cap_gen/catgen_ddr_cmos.v b/fpga/usrp3/lib/io_cap_gen/catgen_ddr_cmos.v
new file mode 100644
index 000000000..017a2f432
--- /dev/null
+++ b/fpga/usrp3/lib/io_cap_gen/catgen_ddr_cmos.v
@@ -0,0 +1,90 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module catgen_ddr_cmos
+#(
+  parameter DEVICE = "7SERIES" // "7SERIES" or "SPARTAN6"
+)
+(
+  output        data_clk,
+  input         mimo,
+  output        tx_frame,
+  output [11:0] tx_d,
+  input         tx_clk,
+  output reg    tx_strobe,
+  input [11:0]  i0,
+  input [11:0]  q0,
+  input [11:0]  i1,
+  input [11:0]  q1
+);
+
+  reg [11:0]      i,q;
+  genvar          z;
+  reg             tx_strobe_d;
+
+  generate
+    for(z = 0; z < 12; z = z + 1)
+    begin : gen_pins
+      if (DEVICE == "SPARTAN6") begin
+        ODDR2 #(
+          .DDR_ALIGNMENT("C0"), .SRTYPE("ASYNC"))
+        oddr2 (
+          .Q(tx_d[z]), .C0(tx_clk), .C1(~tx_clk),
+          .CE(1'b1), .D0(i[z]), .D1(q[z]), .R(1'b0), .S(1'b0));
+      end
+      else if (DEVICE == "7SERIES") begin
+        ODDR #(
+          .DDR_CLK_EDGE("SAME_EDGE"), .SRTYPE("ASYNC"))
+        oddr (
+          .Q(tx_d[z]), .C(tx_clk),
+          .CE(1'b1), .D1(i[z]), .D2(q[z]), .R(1'b0), .S(1'b0));
+      end
+    end
+  endgenerate
+
+  generate
+    if (DEVICE == "SPARTAN6") begin
+      ODDR2 #(
+        .DDR_ALIGNMENT("C0"), .SRTYPE("ASYNC"))
+      oddr2_frame (
+        .Q(tx_frame), .C0(tx_clk), .C1(~tx_clk),
+        .CE(1'b1), .D0(tx_strobe_d), .D1(mimo&tx_strobe_d), .R(1'b0), .S(1'b0));
+
+      ODDR2 #(
+        .DDR_ALIGNMENT("C0"), .SRTYPE("ASYNC"))
+      oddr2_clk (
+        .Q(data_clk), .C0(tx_clk), .C1(~tx_clk),
+        .CE(1'b1), .D0(1'b1), .D1(1'b0), .R(1'b0), .S(1'b0));
+    end
+    else if (DEVICE == "7SERIES") begin
+      ODDR #(
+        .DDR_CLK_EDGE("SAME_EDGE"), .SRTYPE("ASYNC"))
+      oddr_frame (
+        .Q(tx_frame), .C(tx_clk),
+        .CE(1'b1), .D1(tx_strobe_d), .D2(mimo&tx_strobe_d), .R(1'b0), .S(1'b0));
+
+      ODDR #(
+        .DDR_CLK_EDGE("SAME_EDGE"), .SRTYPE("ASYNC"))
+      oddr_clk (
+        .Q(data_clk), .C(tx_clk),
+        .CE(1'b1), .D1(1'b1), .D2(1'b0), .R(1'b0), .S(1'b0));
+    end
+  endgenerate
+
+  always @(posedge tx_clk)
+    tx_strobe <= (mimo)? ~tx_strobe : 1'b1;
+
+  always @(posedge tx_clk)
+    tx_strobe_d <= tx_strobe;
+
+  always @(posedge tx_clk)
+    if(tx_strobe)
+      {i,q} <= {i0,q0};
+    else
+      {i,q} <= {i1,q1};
+
+endmodule // catgen_ddr_cmos
diff --git a/fpga/usrp3/lib/io_port2/.gitignore b/fpga/usrp3/lib/io_port2/.gitignore
new file mode 100644
index 000000000..796b96d1c
--- /dev/null
+++ b/fpga/usrp3/lib/io_port2/.gitignore
@@ -0,0 +1 @@
+/build
diff --git a/fpga/usrp3/lib/io_port2/LvFpga_Chinch_Interface.ngc b/fpga/usrp3/lib/io_port2/LvFpga_Chinch_Interface.ngc
new file mode 100644
index 000000000..f6d3e0d38
--- /dev/null
+++ b/fpga/usrp3/lib/io_port2/LvFpga_Chinch_Interface.ngc
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
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462k=0ni;>4H0254`=O99?h56*k6d`9042<am<h57>5;hf5gd<722em8:l50;9~f4e1i3:1?7>50z&240e328:=<i5G1143a>N68<i27d;nc;29?lcb=>0;66ai46`94?=zj8i>;7>54;294~"68<i?6hk9c:J2436b3A;;9n74i4c`>5<<a?:oo7>5;hd51f<722em8:l50;9~f4e183:1?7>50z&240e32lo=<6F>072f?M77=j30(i8jb;620>oc>j31<75fd7ab>5<<go><n7>5;|`2a3>=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl>e7594?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th:i;;50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd6m?>1<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`2a35=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl>e7094?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th:i;?50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd6m?:1<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`2a0`=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl>e4g94?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th:i8j50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd6m<i1<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`2a0g=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl>e4;94?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th:i8650;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd6m<=1<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`2a00=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl>e4794?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th:i8:50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd6m<91<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`2a04=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl>e4394?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th:i;k50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd6m?n1<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`2a3e=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl>e7`94?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th:i;o50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd6m?31<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`2a30=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl>e4`94?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th:i8>50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd6m=l1<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`2a53=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl>e1694?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th:i=<50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd6m9;1<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`2a56=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl>dgd94?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th:hkk50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd6lon1<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`2`ce=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl>dg`94?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th:hko50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd6lo31<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`2`c1=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl>dg494?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th:hk;50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd6lo>1<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`2`c5=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl>dg094?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th:hk?50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd6lo:1<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`2```=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl>ddg94?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th:i=l50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd6m9k1<7:50;2x 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462k=0ni;>4H0254`=O99?h56*k6d`9042<am<h57>5;hf5gd<722em8:l50;9~f402j3:1?7>50z&240e328:=<i5G1143a>N68<i27d;nc;29?lcb=>0;66ai46`94?=zj8<?47>54;294~"68<i?6hk9c:J2436b3A;;9n74i4c`>5<<a?:oo7>5;hd51f<722em8:l50;9~f40293:1?7>50z&240e32lo=<6F>072f?M77=j30(i8jb;620>oc>j31<75fd7ab>5<<go><n7>5;|`2<0>=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl>84594?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th:48;50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd60<>1<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`2<05=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl>84094?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th:48?50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd60<:1<7:50;2x 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462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`2<14=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl>85394?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th:48k50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd60<n1<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`2<0e=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl>84`94?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th:48o50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd60<31<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`2<00=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl>85`94?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th:49>50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd60:l1<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`23c3=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl>7g694?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th:;k<50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd6?o;1<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`23c6=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl>7dd94?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th:;hk50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd6?ln1<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`23`e=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl>7d`94?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th:;ho50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd6?l31<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`23`1=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl>7d494?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th:;h;50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd6?l>1<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`23`5=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl>7d094?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th:;h?50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd6?l:1<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`23a`=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl>7eg94?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th:;kl50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd6?ok1<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`23c?=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl>7g:94?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th:;k950;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd6?o<1<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`23c5=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl>7d:94?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th:;ij50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd6?mi1<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`23<6=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl>79d94?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th:;5k50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd6?1n1<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`23=e=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl>79`94?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th:;5o50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd6?131<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`23=>=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl>79594?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th::om50;194?6|,8:>o94k5ba8L4618l1C==;l9:k6<=<722c=<5m50;9lb1d?2900qo?9bc83>6<729q/==;l4;f6gf=O99<;i6F>04a:?l3?03:17d8?8b83>>ia<k21<75rb04ae?6=;3:1<v*>04a7>a3dk2B:<;>j;I331f?<a<236=44i72;g?6=3fl?n54?::a53d>29086=4?{%331f2=l<ih7E??61g8L462k01b95650;9j25>d2900ck:m8;29?xd6>k21<7=50;2x 462k=0o9nm4H0254`=O99?h56g:8983>>o181i1<75`f5`;>5<<uk;=n:4?:283>5}#99?h87j:cb9K5507m2B:<8m6;h7;<?6=3`<;4n4?::me0g>=831vn<8m6;297?6=8r.:<8m;:e7`g>N68?:n7E??5b;8m0>?2900e;>7c;29?j`3j10;66sm17`6>5<4290;w)??5b69`0ed3A;;:=k4H026g<=n=121<75f61:`>5<<go>i47>5;|`22g2=8391<7>t$026g1<c=ji0D<>90d9K553d12c>454?::k54=e=831dj9l7:188yg71j:0;6>4?:1y'553d<3n>on5G1143a>N68<i27d;78;29?l070j0;66ai4c:94?=zj8>9?7>54;294~"68<i?6i;kc:J2436b3A;;9n74i4:;>5<<a?:3o7>5;hd7g7<722em8o650;9~f410<3:187>50z&240e32m?o96F>072f?M77=j30(i8jb;28m0>?2900e87i:188m36?k3:17bh;b983>>{e9>=86=4;:183!77=j>1h8j:;I3325c<@8:>o45+d7ga>5=n=121<75f58d94?=n>92h6=44og6a<?6=3th:;:<50;694?6|,8:>o94k5e78L4618l1C==;l9:&g2`d=82c>454?::k6=c<722c=<5m50;9lb1d?2900qo?87083>1<729q/==;l4;f6`0=O99<;i6F>04a:?!b1mk0;7d;78;29?l3>n3:17d8?8b83>>ia<k21<75rb0544?6=<3:1<v*>04a7>a3c=2B:<;>j;I331f?<,m<nn7>4i4:;>5<<a<3m6=44i72;g?6=3fl?n54?::a520a290?6=4?{%331f2=l<n>7E??61g8L462k01/h;km:19j1=>=831b94h50;9j25>d2900ck:m8;29?xd6?>i1<7:50;2x 462k=0o9i;4H0254`=O99?h56*k6d`9f7=n=121<75f58d94?=n>92h6=44og6a<?6=3th:;:l50;694?6|,8:>o94k5e78L4618l1C==;l9:&g2`d=82c>454?::k6=c<722c=<5m50;9lb1d?2900qo?87`83>1<729q/==;l4;f6`0=O99<;i6F>04a:?!b1mk0;7d;78;29?l3>n3:17d8?8b83>>ia<k21<75rb054=?6=<3:1<v*>04a7>a3c=2B:<;>j;I331f?<,m<nn7>4i4:;>5<<a<3m6=44i72;g?6=3fl?n54?::a521?290?6=4?{%331f2=l<n>7E??61g8L462k01/h;km:19j1=>=831b94h50;9j25>d2900ck:m8;29?xd6?>=1<7:50;2x 462k=0o9i;4H0254`=O99?h56*k6d`94>o2010;66g:9g83>>o181i1<75`f5`;>5<<uk;<;;4?:583>5}#99?h87j:d49K5507m2B:<8m6;%f5ag<73`?347>5;h7:b?6=3`<;4n4?::me0g>=831vn<985;290?6=8r.:<8m;:e7g1>N68?:n7E??5b;8 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462k=0o9ij4H0254`=O99?h56g:8983>>o21o0;66g909a94?=nn=i96=44og6a<?6=3th:;?<50;794?6|,8:>o94k5ef8L4618l1C==;l9:k6<=<722c>5k4?::k54=e=831bj9m=:188kc2e03:17pl>73294?3=83:p(<>:c58g1ab<@8:=<h5G117`=>o2010;66g:9g83>>o181i1<75ff5a1>5<<go>i47>5;|`234`=83?1<7>t$026g1<c=mn0D<>90d9K553d12c>454?::k6=c<722c=<5m50;9jb1e52900ck:m8;29?xd6?8o1<7;50;2x 462k=0o9ij4H0254`=O99?h56g:8983>>o21o0;66g909a94?=nn=i96=44og6a<?6=3th:;<j50;794?6|,8:>o94k5ef8L4618l1C==;l9:k6<=<722c>5k4?::k54=e=831bj9m=:188kc2e03:17pl>70a94?3=83:p(<>:c58g1ab<@8:=<h5G117`=>o2010;66g:9g83>>o181i1<75ff5a1>5<<go>i47>5;|`234d=83?1<7>t$026g1<c=mn0D<>90d9K553d12c>454?::k6=c<722c=<5m50;9jb1e52900ck:m8;29?xd6?8k1<7;50;2x 462k=0o9ij4H0254`=O99?h56g:8983>>o21o0;66g909a94?=nn=i96=44og6a<?6=3th:;<750;794?6|,8:>o94k5ef8L4618l1C==;l9:k6<=<722c>5k4?::k54=e=831bj9m=:188kc2e03:17pl>70:94?3=83:p(<>:c58g1ab<@8:=<h5G117`=>o2010;66g:9g83>>o181i1<75ff5a1>5<<go>i47>5;|`2341=83?1<7>t$026g1<c=mn0D<>90d9K553d12c>454?::k6=c<722c=<5m50;9jb1e52900ck:m8;29?xd6?8?1<7;50;2x 462k=0o9ij4H0254`=O99?h56g:8983>>o21o0;66g909a94?=nn=i96=44og6a<?6=3th:;<:50;794?6|,8:>o94k5ef8L4618l1C==;l9:k6<=<722c>5k4?::k54=e=831bj9m=:188kc2e03:17pl>70194?3=83:p(<>:c58g1ab<@8:=<h5G117`=>o2010;66g:9g83>>o181i1<75ff5a1>5<<go>i47>5;|`2344=83?1<7>t$026g1<c=mn0D<>90d9K553d12c>454?::k6=c<722c=<5m50;9jb1e52900ck:m8;29?xd6?8;1<7;50;2x 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462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`6a02=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl:e4194?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th>i8?50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd2m<:1<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`6a1`=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl:e5g94?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th>i9j50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd2m=i1<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`6a1d=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl:e5c94?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th>i9750;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd2m=21<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`6a10=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl:e5794?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th>i9:50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd2m=91<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`6a14=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl:e5394?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th>i9>50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd2m:l1<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`6a6c=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl:e2f94?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th>i8o50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd2m<31<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`6a0>=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl:e4594?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th>i8850;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd2m<?1<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`6a04=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl:e5594?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th>i>m50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd2m:h1<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`6`c6=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl:ddd94?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th>hhk50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd2lln1<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`6``e=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl:dd`94?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th>hho50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd2ll31<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`6``>=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl:dd594?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th>h<m50;194?6|,8:>o94k5ba8L4618l1C==;l9:k6<=<722c=<5m50;9lb1d?2900qo;k1c83>6<729q/==;l4;f6gf=O99<;i6F>04a:?l3?03:17d8?8b83>>ia<k21<75rb4f2e?6=;3:1<v*>04a7>a3dk2B:<;>j;I331f?<a<236=44i72;g?6=3fl?n54?::a1a7>29086=4?{%331f2=l<ih7E??61g8L462k01b95650;9j25>d2900ck:m8;29?xd2l821<7=50;2x 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462k=0o9ij4H0254`=O99?h56g:8983>>o21o0;66g909a94?=nn=i96=44og6a<?6=3th>h5<50;794?6|,8:>o94k5ef8L4618l1C==;l9:k6<=<722c>5k4?::k54=e=831bj9m=:188kc2e03:17pl:d9294?3=83:p(<>:c58g1ab<@8:=<h5G117`=>o2010;66g:9g83>>o181i1<75ff5a1>5<<go>i47>5;|`6`2`=83?1<7>t$026g1<c=mn0D<>90d9K553d12c>454?::k6=c<722c=<5m50;9jb1e52900ck:m8;29?xd2l>o1<7;50;2x 462k=0o9ij4H0254`=O99?h56g:8983>>o21o0;66g909a94?=nn=i96=44og6a<?6=3th>h:j50;794?6|,8:>o94k5ef8L4618l1C==;l9:k6<=<722c>5k4?::k54=e=831bj9m=:188kc2e03:17pl:d6a94?3=83:p(<>:c58g1ab<@8:=<h5G117`=>o2010;66g:9g83>>o181i1<75ff5a1>5<<go>i47>5;|`6`2d=83?1<7>t$026g1<c=mn0D<>90d9K553d12c>454?::k6=c<722c=<5m50;9jb1e52900ck:m8;29?xd2l>k1<7;50;2x 462k=0o9ij4H0254`=O99?h56g:8983>>o21o0;66g909a94?=nn=i96=44og6a<?6=3th>h:750;794?6|,8:>o94k5ef8L4618l1C==;l9:k6<=<722c>5k4?::k54=e=831bj9m=:188kc2e03:17pl:d6:94?3=83:p(<>:c58g1ab<@8:=<h5G117`=>o2010;66g:9g83>>o181i1<75ff5a1>5<<go>i47>5;|`6`21=83?1<7>t$026g1<c=mn0D<>90d9K553d12c>454?::k6=c<722c=<5m50;9jb1e52900ck:m8;29?xd2l>?1<7;50;2x 462k=0o9ij4H0254`=O99?h56g:8983>>o21o0;66g909a94?=nn=i96=44og6a<?6=3th>h::50;794?6|,8:>o94k5ef8L4618l1C==;l9:k6<=<722c>5k4?::k54=e=831bj9m=:188kc2e03:17pl:d6194?3=83:p(<>:c58g1ab<@8:=<h5G117`=>o2010;66g:9g83>>o181i1<75ff5a1>5<<go>i47>5;|`6`24=83?1<7>t$026g1<c=mn0D<>90d9K553d12c>454?::k6=c<722c=<5m50;9jb1e52900ck:m8;29?xd2l>;1<7;50;2x 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462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`6<1g=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl:85;94?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th>49950;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd20=<1<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`6<13=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl:85694?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th>49=50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd20=81<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`6<17=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl:85294?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th>4>h50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd20:o1<7:50;2x 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462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`6<1c=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl:85f94?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th>49m50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd20=h1<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`6<1>=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl:82f94?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th>4><50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd20:;1<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`63`0=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl:7d794?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th>;h:50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd2?l91<7:50;2x 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462k=0ni;>4H0254`=O99?h56*k6d`9042<am<h57>5;hf5gd<722em8:l50;9~f1g>13:1?7>50z&240e328:=<i5G1143a>N68<i27d;nc;29?lcb=>0;66ai46`94?=zj=k3:7>54;294~"68<i?6hk9c:J2436b3A;;9n74i4c`>5<<a?:oo7>5;hd51f<722em8:l50;9~f1g?n3:1?7>50z&240e32lo=<6F>072f?M77=j30(i8jb;620>oc>j31<75fd7ab>5<<go><n7>5;|`7g<3=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl;c8694?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th?o4<50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd3k0;1<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`7g<6=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl;c9d94?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th?o5k50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd3k1n1<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`7g=e=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl;c9`94?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th?o5o50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd3k131<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`7g=1=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl;c9494?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th?o5;50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd3k1>1<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`7g=5=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl;c9094?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th?o5?50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd3k1:1<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`7g2`=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl;c6g94?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th?o4l50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd3k0k1<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`7g<?=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl;c8:94?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th?o4950;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd3k0<1<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`7g<5=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl;c9:94?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th?o:j50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd3k>i1<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`7g64=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl;c2394?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th?o?h50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd3k;o1<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`7g7b=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl;c3a94?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th?o?l50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd3k;k1<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`7g7?=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl;c3:94?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th?o?950;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd3k;<1<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`7g72=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl;c3194?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th?o?<50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd3k;;1<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`7g76=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl;c0d94?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th?o<k50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd3k8n1<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`7g4e=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl;c0`94?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th?o>650;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd3k:=1<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`7g60=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl;c2794?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th?o>:50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd3k:91<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`7g66=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl;c3794?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th?o<o50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd3k831<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`7ffc=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl;bbf94?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th?nnm50;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd3jjh1<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`7ffg=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl;bb;94?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th?nn650;694?6|,8:>o94k5ea8L4618l1C==;l9:k6<=<722c=<5m50;9jb1e52900ck:m8;29?xd3jj=1<7:50;2x 462k=0o9im4H0254`=O99?h56g:8983>>o181i1<75ff5a1>5<<go>i47>5;|`7ff0=83>1<7>t$026g1<c=mi0D<>90d9K553d12c>454?::k54=e=831bj9m=:188kc2e03:17pl;bb794?2=83:p(<>:c58g1ae<@8:=<h5G117`=>o2010;66g909a94?=nn=i96=44og6a<?6=3th?mko50;194?6|,8:>o94k5ba8L4618l1C==;l9:k6<=<722c=<5m50;9lb1d?2900qo:nf883>6<729q/==;l4;f6gf=O99<;i6F>04a:?l3?03:17d8?8b83>>ia<k21<75rb5ce<?6=;3:1<v*>04a7>a3dk2B:<;>j;I331f?<a<236=44i72;g?6=3fl?n54?::a0d`029086=4?{%331f2=l<ih7E??61g8L462k01b95650;9j25>d2900ck:m8;29?xd3io<1<7=50;2x 462k=0o9nm4H0254`=O99?h56g:8983>>o181i1<75`f5`;>5<<uk>jj84?:283>5}#99?h87j:cb9K5507m2B:<8m6;h7;<?6=3`<;4n4?::me0g>=831vn9oi4;297?6=8r.:<8m;:e7`g>N68?:n7E??5b;8m0>?2900e;>7c;29?j`3j10;66sm4`d0>5<4290;w)??5b69`0ed3A;;:=k4H026g<=n=121<75f61:`>5<<go>i47>5;|`7ec4=8391<7>t$026g1<c=ji0D<>90d9K553d12c>454?::k54=e=831dj9l7:188yg2fn80;6>4?:1y'553d<3n>on5G1143a>N68<i27d;78;29?l070j0;66ai4c:94?=zj=2==7>54;294~"68<i?6i;kc:J2436b3A;;9n74i4:;>5<<a?:3o7>5;hd7g7<722em8o650;9~f1de:3:187>50z&240e32m?o96F>072f?M77=j30(i8jb;28m0>?2900e87i:188m36?k3:17bh;b983>>{e<kh:6=4;:183!77=j>1h8j:;I3325c<@8:>o45+d7ga>5=n=121<75f58d94?=n>92h6=44og6a<?6=3th?no>50;694?6|,8:>o94k5e78L4618l1C==;l9:&g2`d=82c>454?::k6=c<722c=<5m50;9lb1d?2900qo:mag83>1<729q/==;l4;f6`0=O99<;i6F>04a:?!b1mk0;7d;78;29?l3>n3:17d8?8b83>>ia<k21<75rb5`ba?6=<3:1<v*>04a7>a3c=2B:<;>j;I331f?<,m<nn7>4i4:;>5<<a<3m6=44i72;g?6=3fl?n54?::a0ggc290?6=4?{%331f2=l<n>7E??61g8L462k01/h;km:19j1=>=831b94h50;9j25>d2900ck:m8;29?xd3jkk1<7:50;2x 462k=0o9i;4H0254`=O99?h56*k6d`9f7=n=121<75f58d94?=n>92h6=44og6a<?6=3th?no750;694?6|,8:>o94k5e78L4618l1C==;l9:&g2`d=82c>454?::k6=c<722c=<5m50;9lb1d?2900qo:mb983>1<729q/==;l4;f6`0=O99<;i6F>04a:?!b1mk0;7d;78;29?l3>n3:17d8?8b83>>ia<k21<75rb5`a3?6=<3:1<v*>04a7>a3c=2B:<;>j;I331f?<,m<nn7>4i4:;>5<<a<3m6=44i72;g?6=3fl?n54?::a0gd1290?6=4?{%331f2=l<n>7E??61g8L462k01/h;km:19j1=>=831b94h50;9j25>d2900ck:m8;29?xd3jk?1<7:50;2x 462k=0o9i;4H0254`=O99?h56*k6d`94>o2010;66g:9g83>>o181i1<75`f5`;>5<<uk>in94?:583>5}#99?h87j:d49K5507m2B:<8m6;%f5ag<73`?347>5;h7:b?6=3`<;4n4?::me0g>=831vn9lm3;290?6=8r.:<8m;:e7g1>N68?:n7E??5b;8 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462k=0o9ij4H0254`=O99?h56g:8983>>o21o0;66g909a94?=nn=i96=44og6a<?6=3th?n;>50;794?6|,8:>o94k5ef8L4618l1C==;l9:k6<=<722c>5k4?::k54=e=831bj9m=:188kc2e03:17pl;b4g94?3=83:p(<>:c58g1ab<@8:=<h5G117`=>o2010;66g:9g83>>o181i1<75ff5a1>5<<go>i47>5;|`7f0b=83?1<7>t$026g1<c=mn0D<>90d9K553d12c>454?::k6=c<722c=<5m50;9jb1e52900ck:m8;29?xd3j<i1<7;50;2x 462k=0o9ij4H0254`=O99?h56g:8983>>o21o0;66g909a94?=nn=i96=44og6a<?6=3th?n8l50;794?6|,8:>o94k5ef8L4618l1C==;l9:k6<=<722c>5k4?::k54=e=831bj9m=:188kc2e03:17pl;b4c94?3=83:p(<>:c58g1ab<@8:=<h5G117`=>o2010;66g:9g83>>o181i1<75ff5a1>5<<go>i47>5;|`7f0?=83?1<7>t$026g1<c=mn0D<>90d9K553d12c>454?::k6=c<722c=<5m50;9jb1e52900ck:m8;29?xd3j<21<7;50;2x 462k=0o9ij4H0254`=O99?h56g:8983>>o21o0;66g909a94?=nn=i96=44og6a<?6=3th?n8950;794?6|,8:>o94k5ef8L4618l1C==;l9:k6<=<722c>5k4?::k54=e=831bj9m=:188kc2e03:17pl;b4494?3=83:p(<>:c58g1ab<@8:=<h5G117`=>o2010;66g:9g83>>o181i1<75ff5a1>5<<go>i47>5;|`7f03=83?1<7>t$026g1<c=mn0D<>90d9K553d12c>454?::k6=c<722c=<5m50;9jb1e52900ck:m8;29?xd3j<91<7;50;2x 462k=0o9ij4H0254`=O99?h56g:8983>>o21o0;66g909a94?=nn=i96=44og6a<?6=3th?n8<50;794?6|,8:>o94k5ef8L4618l1C==;l9:k6<=<722c>5k4?::k54=e=831bj9m=:188kc2e03:17pl;b4394?3=83:p(<>:c58g1ab<@8:=<h5G117`=>o2010;66g:9g83>>o181i1<75ff5a1>5<<go>i47>5;|`7f06=83?1<7>t$026g1<c=mn0D<>90d9K553d12c>454?::k6=c<722c=<5m50;9jb1e52900ck:m8;29?xd3j=l1<7;50;2x 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\ No newline at end of file
diff --git a/fpga/usrp3/lib/io_port2/LvFpga_Chinch_Interface.v b/fpga/usrp3/lib/io_port2/LvFpga_Chinch_Interface.v
new file mode 100644
index 000000000..169e9a7ec
--- /dev/null
+++ b/fpga/usrp3/lib/io_port2/LvFpga_Chinch_Interface.v
@@ -0,0 +1,81 @@
+/*
+-------------------------------------------------------------------------------
+--
+-- File: LvFpga_Chinch_Interface.vhd
+-- Author: Ashish Chaudhari
+-- Original Project: EttusUsrpB250Top
+-- Date: 1 Oct 2013
+--
+-------------------------------------------------------------------------------
+-- (c) 2013 Copyright National Instruments Corporation
+-- All Rights Reserved
+-- National Instruments Internal Information
+-------------------------------------------------------------------------------
+*/
+
+`include "LvFpga_Chinch_Interface.vh"
+
+module  LvFpga_Chinch_Interface
+(
+    input   aIoResetIn_n,
+    output  bBusReset,
+
+    input   BusClk,
+    input   Rio40Clk,
+    input   IDelayRefClk,
+    input   aRioClkPllLocked,
+    output  aRioClkPllReset,
+
+    output  aIoReadyOut,
+    input   aIoReadyIn,
+    output  aIoPort2Restart,
+
+    input                                   IoRxClock,
+    input                                   IoRxClock_n,
+    input [`LVFPGA_IFACE_LINK_WIDTH-1:0]    irIoRxData,
+    input [`LVFPGA_IFACE_LINK_WIDTH-1:0]    irIoRxData_n,
+    input                                   irIoRxHeader,
+    input                                   irIoRxHeader_n,
+        
+    output                                  IoTxClock,
+    output                                  IoTxClock_n,
+    output [`LVFPGA_IFACE_LINK_WIDTH-1:0]   itIoTxData,
+    output [`LVFPGA_IFACE_LINK_WIDTH-1:0]   itIoTxData_n,
+    output                                  itIoTxHeader,
+    output                                  itIoTxHeader_n,
+    
+    input [(`LVFPGA_IFACE_NUM_RX_DMA_CNT*`LVFPGA_IFACE_DMA_CHAN_WIDTH)-1:0]  bDmaRxData,
+    input [`LVFPGA_IFACE_NUM_RX_DMA_CNT-1:0]                                 bDmaRxValid,
+    output [`LVFPGA_IFACE_NUM_RX_DMA_CNT-1:0]                                bDmaRxReady,
+    output [`LVFPGA_IFACE_NUM_RX_DMA_CNT-1:0]                                bDmaRxEnabled,
+    output [(`LVFPGA_IFACE_NUM_RX_DMA_CNT*`LVFPGA_IFACE_DMA_SIZE_WIDTH)-1:0] bDmaRxFifoFreeCnt,
+    
+    output [(`LVFPGA_IFACE_NUM_TX_DMA_CNT*`LVFPGA_IFACE_DMA_CHAN_WIDTH)-1:0] bDmaTxData,
+    output [`LVFPGA_IFACE_NUM_TX_DMA_CNT-1:0]                                bDmaTxValid,
+    input [`LVFPGA_IFACE_NUM_TX_DMA_CNT-1:0]                                 bDmaTxReady,
+    output [`LVFPGA_IFACE_NUM_TX_DMA_CNT-1:0]                                bDmaTxEnabled,
+    output [(`LVFPGA_IFACE_NUM_TX_DMA_CNT*`LVFPGA_IFACE_DMA_SIZE_WIDTH)-1:0] bDmaTxFifoFullCnt,
+    
+    output                                      bUserRegPortInWt,
+    output                                      bUserRegPortInRd,
+    output [`LVFPGA_IFACE_UREG_ADDR_WIDTH-1:0]  bUserRegPortInAddr,
+    output [`LVFPGA_IFACE_UREG_DATA_WIDTH-1:0]  bUserRegPortInData,
+    output [`LVFPGA_IFACE_UREG_SIZE_WIDTH-1:0]  bUserRegPortInSize,
+    input [`LVFPGA_IFACE_UREG_DATA_WIDTH-1:0]   bUserRegPortOutData,
+    input                                       bUserRegPortOutDataValid,
+    input                                       bUserRegPortOutReady,
+    
+    input                                       bChinchRegPortOutWt,
+    input                                       bChinchRegPortOutRd,
+    input [`LVFPGA_IFACE_CREG_ADDR_WIDTH-1:0]   bChinchRegPortOutAddr,
+    input [`LVFPGA_IFACE_CREG_DATA_WIDTH-1:0]   bChinchRegPortOutData,
+    input [`LVFPGA_IFACE_CREG_SIZE_WIDTH-1:0]   bChinchRegPortOutSize,
+    output [`LVFPGA_IFACE_CREG_DATA_WIDTH-1:0]  bChinchRegPortInData,
+    output                                      bChinchRegPortInDataValid,
+    output                                      bChinchRegPortInReady,
+    
+    output  aIrq
+) /* synthesis syn_black_box syn_noprune=1 */;
+// This module serves as an API wrapper for LvFpga_Chinch_Interface.ngc and we don't want
+// the tool to accidentally prune out it contents. Hence the syn_black_box syn_noprune=1 directives.
+endmodule
diff --git a/fpga/usrp3/lib/io_port2/LvFpga_Chinch_Interface.vh b/fpga/usrp3/lib/io_port2/LvFpga_Chinch_Interface.vh
new file mode 100644
index 000000000..47dcfb807
--- /dev/null
+++ b/fpga/usrp3/lib/io_port2/LvFpga_Chinch_Interface.vh
@@ -0,0 +1,35 @@
+/*
+-------------------------------------------------------------------------------
+--
+-- File: LvFpga_Chinch_Interface.vh
+-- Author: Ashish Chaudhari
+-- Original Project: EttusUsrpB250Top
+-- Date: 1 Oct 2013
+--
+-------------------------------------------------------------------------------
+-- (c) 2013 Copyright National Instruments Corporation
+-- All Rights Reserved
+-- National Instruments Internal Information
+-------------------------------------------------------------------------------
+*/
+
+//Physical link width for the IoPort2 interface to the STC3
+`define LVFPGA_IFACE_LINK_WIDTH         16
+
+//DMA Related Constants
+`define LVFPGA_IFACE_DMA_CHAN_WIDTH     64	//DMA data bus width
+`define LVFPGA_IFACE_DMA_SIZE_WIDTH     11	//DMA FIFO fullness count width
+`define LVFPGA_IFACE_NUM_RX_DMA_CNT     6	//Number of RX DMA channels
+`define LVFPGA_IFACE_NUM_TX_DMA_CNT     6	//Number of TX DMA channels
+`define LVFPGA_IFACE_RX_DMA_INDEX       0	//Index for the first RX DMA channel
+`define LVFPGA_IFACE_TX_DMA_INDEX       6	//Index for the first TX DMA channel
+
+//User register port constants
+`define LVFPGA_IFACE_UREG_ADDR_WIDTH    20	//Address width
+`define LVFPGA_IFACE_UREG_DATA_WIDTH    32	//Payload width
+`define LVFPGA_IFACE_UREG_SIZE_WIDTH    2	//Transaction size width
+
+//Chinch register port constants
+`define LVFPGA_IFACE_CREG_ADDR_WIDTH    32	//Address width
+`define LVFPGA_IFACE_CREG_DATA_WIDTH    64	//Payload width
+`define LVFPGA_IFACE_CREG_SIZE_WIDTH    2	//Transaction size width
\ No newline at end of file
diff --git a/fpga/usrp3/lib/io_port2/Makefile.srcs b/fpga/usrp3/lib/io_port2/Makefile.srcs
new file mode 100644
index 000000000..a5664f6a7
--- /dev/null
+++ b/fpga/usrp3/lib/io_port2/Makefile.srcs
@@ -0,0 +1,19 @@
+#
+# Copyright 2012-2013 Ettus Research LLC
+#
+
+##################################################
+# io_port2
+##################################################
+IOPORT2_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/io_port2/, \
+./LvFpga_Chinch_Interface.v \
+./LvFpga_Chinch_Interface.ngc \
+./ioport2_msg_codec.v \
+./pcie_pkt_route_specifier.v \
+./pcie_axi_wb_conv.v \
+./pcie_wb_reg_core.v \
+./pcie_iop2_msg_arbiter.v \
+./pcie_basic_regs.v \
+./pcie_dma_ctrl.v \
+./pcie_lossy_samp_gate.v \
+))
diff --git a/fpga/usrp3/lib/io_port2/create-lvbitx.py b/fpga/usrp3/lib/io_port2/create-lvbitx.py
new file mode 100644
index 000000000..ea8231292
--- /dev/null
+++ b/fpga/usrp3/lib/io_port2/create-lvbitx.py
@@ -0,0 +1,153 @@
+#!/usr/bin/python
+"""
+Generate lvbitx from template and bitfile
+"""
+
+from __future__ import print_function
+from xml.etree import ElementTree
+import optparse
+import base64
+import os
+from hashlib import md5
+
+def to_native_str(str_or_bstr):
+    """
+    Returns a native string, regardless of the input string type (binary or
+    UTF-8), and the Python version (2 or 3).
+    Note that the native string type is actually not the same in Python 2 and
+    3: In the former, it's a binary string, in the latter, it's Unicode.
+    >>> to_native_str(b'foo')
+    'foo'
+    >>> to_native_str(u'foo')
+    'foo'
+    """
+    if isinstance(str_or_bstr, str):
+        return str_or_bstr
+    try:
+        # This will either fail because we're running Python 2 (which doesn't)
+        # have the encoding argument) or because we're not passing in a bytes-
+        # like object (e.g., an integer)
+        return str(str_or_bstr, encoding='ascii')
+    except TypeError:
+        return str(str_or_bstr)
+
+def get_parser():
+    """Parse args."""
+    parser = optparse.OptionParser()
+    parser.add_option(
+        "--device",
+        type="string",
+        dest="device_type",
+        help="Device Type. (Has to match the LVFPGA target plugin)",
+        default=None
+    )
+    parser.add_option(
+        "--input-bin",
+        type="string",
+        dest="input_bin",
+        help="Path to bin file that needs to be merged with the LVBITX before exporting",
+        default=None
+    )
+    parser.add_option(
+        "--output-bin",
+        type="string",
+        dest="output_bin",
+        help="Create a binary configuration bitstream",
+        default=None
+    )
+    parser.add_option(
+        "--output-lvbitx",
+        type="string",
+        dest="output_lvbitx_path",
+        help="Output path for autogenerated LVBITX file",
+        default=None
+    )
+    parser.add_option(
+        "--output-src-path",
+        type="string",
+        dest="output_src_path",
+        help="Output path for autogenerated src file",
+        default=None
+    )
+    return parser
+
+def main():
+    """Go, go, go!"""
+    parser = get_parser()
+    options, args = parser.parse_args()
+    # Args
+    if len(args) < 1:
+        print('ERROR: Please specify the input LVBITX file name')
+        parser.print_help()
+        exit(1)
+
+    lvbitx_filename = args[0]
+    input_filename = os.path.abspath(lvbitx_filename)
+
+    if not os.path.isfile(input_filename):
+        print("ERROR: LVBITX File `{}' could not be accessed or is not a file."
+              .format(input_filename))
+        parser.print_help()
+        exit(1)
+
+    if options.input_bin is not None and \
+            not os.path.isfile(os.path.abspath(options.input_bin)):
+        print("ERROR: FPGA Bin File `{}' could not be accessed or is not a file."
+              .format(options.input_bin))
+        parser.print_help()
+        exit(1)
+
+    if options.output_lvbitx_path is not None and \
+            input_filename == options.output_lvbitx_path:
+        print('ERROR: Input and output LVBITX files were the same. '
+              'Choose a difference input or output file.')
+        parser.print_help()
+        exit(1)
+
+    # Get XML Tree Node
+    tree = ElementTree.parse(input_filename)
+    root = tree.getroot()
+
+    # Update device type
+    if options.device_type is not None:
+        root.find('Project').find('TargetClass').text += '; ' + options.device_type
+
+    # Merge bitstream into LVBITX
+    if options.input_bin is not None:
+        with open(os.path.abspath(options.input_bin), 'rb') as bin_file:
+            bitstream = bin_file.read()
+            bitstream_md5 = md5(bitstream).hexdigest()
+            bitstream_b64 = base64.b64encode(bitstream)
+            bitstream_b64_lb = b'\n'.join([
+                bitstream_b64[i:i+76]
+                for i in range(0, len(bitstream_b64), 76)
+            ]) + b'\n'
+            root.find('Bitstream').text = to_native_str(bitstream_b64_lb)
+            root.find('BitstreamMD5').text = bitstream_md5
+
+    # Write BIN file
+    bitstream = base64.b64decode(root.find('Bitstream').text)
+    if options.output_lvbitx_path is not None \
+            and md5(bitstream).hexdigest() != root.find('BitstreamMD5').text:
+        print('ERROR: The MD5 sum for the output LVBITX was incorrect. '
+              'Make sure that the bitstream in the input LVBITX or BIN file is valid.')
+        exit(1)
+
+    if options.output_bin is not None:
+        fpga_bin_file = open(options.output_bin, 'wb')
+        fpga_bin_file.write(bitstream)
+        fpga_bin_file.close()
+
+    # Save LVBITX
+    if options.output_lvbitx_path is not None:
+        with open(options.output_lvbitx_path, 'wb') as lvbitx_file:
+            tree.write(
+                lvbitx_file,
+                encoding="utf-8",
+                xml_declaration=True,
+                default_namespace=None,
+                method="xml"
+            )
+
+if __name__ == "__main__":
+    main()
diff --git a/fpga/usrp3/lib/io_port2/ioport2_msg_codec.v b/fpga/usrp3/lib/io_port2/ioport2_msg_codec.v
new file mode 100644
index 000000000..d983bb2c7
--- /dev/null
+++ b/fpga/usrp3/lib/io_port2/ioport2_msg_codec.v
@@ -0,0 +1,52 @@
+//
+// Copyright 2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+//Message format:
+//  msg[63]:    Completion {1 -> Read Completion, 0 -> Transaction Request}
+//  msg[62]:    Write request*
+//  msg[61]:    Read request*
+//  msg[60]:    Half word {1 -> 16-bit transaction, 0 -> 32-bit transaction}*
+//  msg[59:52]: Reserved
+//  msg[51:32]: Address*
+//  msg[31:0]:  Data
+//
+//  * Field only valid when the word is a transaction request.
+
+module ioport2_msg_decode(
+    input  [63:0]   message,
+    output          rd_response,
+    output          wr_request,
+    output          rd_request,
+    output          half_word,
+    output [19:0]   address,
+    output [31:0]   data,
+    output [31:0]   control    
+);
+    assign rd_response  = message[63];
+    assign wr_request   = message[62];
+    assign rd_request   = message[61];
+    assign half_word    = message[60];
+    assign address      = message[51:32];
+    assign data         = message[31:0];
+    assign control      = message[63:32];
+endmodule
+
+
+module ioport2_msg_encode(
+    input          rd_response,
+    input          wr_request,
+    input          rd_request,
+    input          half_word,
+    input  [19:0]  address,
+    input  [31:0]  data,
+    output [31:0]  control,
+    output [63:0]  message
+);
+    assign control = rd_response ? {rd_response, 31'h0} : {rd_response, wr_request, rd_request, half_word, 8'h00, address};
+    assign message = {control, data};
+endmodule
diff --git a/fpga/usrp3/lib/io_port2/pcie_axi_wb_conv.v b/fpga/usrp3/lib/io_port2/pcie_axi_wb_conv.v
new file mode 100644
index 000000000..f6a0f10af
--- /dev/null
+++ b/fpga/usrp3/lib/io_port2/pcie_axi_wb_conv.v
@@ -0,0 +1,199 @@
+//
+// Copyright 2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+module pcie_axi_wb_conv #(
+    parameter WB_ADDRW  = 16,
+    parameter WB_DATAW  = 32
+)(
+    input                   clk, 
+    input                   rst,
+
+    input                   wb_stb_i,
+    input                   wb_we_i,
+    input  [WB_ADDRW-1:0]   wb_adr_i,
+    input  [WB_DATAW-1:0]   wb_dat_i,
+    output                  wb_ack_o,
+    output [WB_DATAW-1:0]   wb_dat_o,
+
+    input  [63:0]           msgi_tdata,
+    input                   msgi_tvalid,
+    output                  msgi_tready,
+
+    output [63:0]           msgo_tdata,
+    output                  msgo_tvalid,
+    input                   msgo_tready,
+    
+    output                  wb_monitor_active,
+    output reg              wb_req_pending,
+    output reg              wb_resp_pending,
+    output reg              pcie_resp_pending
+);
+
+    localparam SB_ADDRW                 = 4;
+    localparam SB_DATAW                 = 32;
+    localparam MONITOR_TIMEOUTW         = 20;   //20bits@175MHz ~ 6ms
+
+    localparam SR_PCIE_DATA_REG         = 4'd0;
+    localparam SR_PCIE_CTRL_REG         = 4'd1;
+    localparam RB_PCIE_DATA_REG         = 4'd0;
+    localparam RB_PCIE_CTRL_REG         = 4'd1;
+    localparam RB_PCIE_RESP_DATA_REG    = 4'd2;
+    localparam RB_PCIE_STATUS_REG       = 4'd3;
+
+    //------------------------------------------
+    // Settings and readback bus
+    //
+    wire [SB_DATAW-1:0]     set_data, rb_data;
+    wire [SB_ADDRW-1:0]     set_addr, rb_addr;
+    wire                    set_stb, rb_stb;
+
+    settings_bus #(.AWIDTH(WB_ADDRW), .DWIDTH(WB_DATAW)) settings_bus (
+        .wb_clk(clk), .wb_rst(rst),
+        .wb_adr_i(wb_adr_i), .wb_dat_i(wb_dat_i),
+        .wb_stb_i(wb_stb_i), .wb_we_i(wb_we_i), .wb_ack_o(wb_ack_o),
+        .strobe(set_stb), .addr(set_addr), .data(set_data)
+    );
+
+    settings_readback #(.AWIDTH(WB_ADDRW), .DWIDTH(WB_DATAW), .RB_ADDRW(SB_ADDRW)) settings_readback (
+        .wb_clk(clk), .wb_rst(rst), 
+        .wb_adr_i(wb_adr_i), .wb_stb_i(wb_stb_i), .wb_we_i(wb_we_i),
+        .rb_data(rb_data), .rb_addr(rb_addr), .rb_rd_stb(rb_stb),
+        .wb_dat_o(wb_dat_o)
+    );
+    //------------------------------------------
+    
+    //------------------------------------------
+    // Settings/Readback Registers
+    //
+    wire [31:0]     axi_out_data, axi_out_ctrl;
+    wire            axi_out_stb;
+
+    setting_reg #(.my_addr(SR_PCIE_DATA_REG), .awidth(SB_ADDRW), .width(SB_DATAW)) set_pcie_out_data_reg (
+        .clk(clk), .rst(rst),
+        .strobe(set_stb), .addr(set_addr), .in(set_data),
+        .out(axi_out_data)
+    );
+
+    setting_reg #(.my_addr(SR_PCIE_CTRL_REG), .awidth(SB_ADDRW), .width(SB_DATAW)) set_pcie_out_ctrl_reg (
+        .clk(clk), .rst(rst),
+        .strobe(set_stb), .addr(set_addr), .in(set_data),
+        .out(axi_out_ctrl), .changed(axi_out_stb)
+    );
+
+    reg [31:0]      axi_in_data_reg, axi_in_ctrl_reg, axi_in_resp_reg;
+    wire            msgo_fifo_tready;
+
+    // Readback MUX
+    assign rb_data = (
+        (rb_addr == RB_PCIE_STATUS_REG)    ? {27'h0, ~msgo_fifo_tready, 1'b0, wb_resp_pending, wb_req_pending, pcie_resp_pending} : (
+        (rb_addr == RB_PCIE_RESP_DATA_REG) ? axi_in_resp_reg : (
+        (rb_addr == RB_PCIE_DATA_REG)      ? axi_in_data_reg : (
+        (rb_addr == RB_PCIE_CTRL_REG)      ? axi_in_ctrl_reg : 32'h0))));
+    //------------------------------------------
+
+    //------------------------------------------
+    // Output message handler
+    //
+    wire [63:0]     msgo_fifo_tdata;
+    wire            axi_out_rd, axi_out_wr, axi_out_rr;
+
+    assign msgo_fifo_tdata = {axi_out_ctrl, axi_out_data};
+
+    axi_fifo_short #(.WIDTH(64)) wb_out_msg_fifo (
+        .clk(clk), .reset(rst), .clear(1'b0),
+        .i_tdata(msgo_fifo_tdata), .i_tvalid(axi_out_stb), .i_tready(msgo_fifo_tready),
+        .o_tdata(msgo_tdata), .o_tvalid(msgo_tvalid), .o_tready(msgo_tready),
+        .space(), .occupied());
+
+    ioport2_msg_decode axi_out_decoder (
+        .message(msgo_fifo_tdata),
+        .rd_response(axi_out_rr), .wr_request(axi_out_wr), .rd_request(axi_out_rd)
+    );
+    //------------------------------------------
+    
+    //------------------------------------------
+    // Input message handler
+    //
+    wire [63:0]     msgi_fifo_tdata;
+    wire            axi_in_valid, axi_in_stb;
+
+    wire [31:0]     axi_in_data, axi_in_ctrl;
+    wire            axi_in_rd, axi_in_wr, axi_in_rr;
+    
+    axi_fifo_short #(.WIDTH(64)) wb_in_msg_fifo (
+        .clk(clk), .reset(rst), .clear(1'b0),
+        .i_tdata(msgi_tdata), .i_tvalid(msgi_tvalid), .i_tready(msgi_tready),
+        .o_tdata(msgi_fifo_tdata), .o_tvalid(axi_in_valid), .o_tready(axi_in_stb),
+        .space(), .occupied());
+
+    ioport2_msg_decode axi_in_decoder (
+        .message(msgi_fifo_tdata),
+        .rd_response(axi_in_rr), .wr_request(axi_in_wr), .rd_request(axi_in_rd),
+        .data(axi_in_data), .control(axi_in_ctrl)
+    );
+
+    assign axi_in_stb = axi_in_valid & (axi_in_rr | ((axi_in_wr | axi_in_rd) &  ~(wb_req_pending | wb_resp_pending)));
+
+    always @(posedge clk) begin
+        if (rst) begin
+            axi_in_data_reg     <= 32'h0;
+            axi_in_ctrl_reg     <= 32'h0;
+            axi_in_resp_reg     <= 32'h0;
+        end else begin
+            if (axi_in_stb & axi_in_rr) begin
+                axi_in_resp_reg <= axi_in_data;
+            end else if (axi_in_stb & (axi_in_wr | axi_in_rd)) begin
+                axi_in_data_reg <= axi_in_data;
+                axi_in_ctrl_reg <= axi_in_ctrl;
+            end
+        end
+    end
+    //------------------------------------------
+    
+    //------------------------------------------
+    // State handler
+    //
+    //wb_monitor_active
+    reg [MONITOR_TIMEOUTW-1:0]  wb_monitor_timeout;
+    assign wb_monitor_active = (wb_monitor_timeout != {(MONITOR_TIMEOUTW){1'b0}});
+    always @(posedge clk) begin
+        if (rst) 
+            wb_monitor_timeout  <= {(MONITOR_TIMEOUTW){1'b0}}; //Monitor disabled on rst
+        else if (rb_stb && (rb_addr == RB_PCIE_STATUS_REG)) 
+            wb_monitor_timeout  <= {(MONITOR_TIMEOUTW){1'b1}}; //Reset counter when the ZPU queries the status reg
+        else if (wb_monitor_active)
+            wb_monitor_timeout  <= wb_monitor_timeout - 1;  //Decrement counter when idle
+    end
+
+    //wb_req_pending
+    always @(posedge clk) begin
+        if (rst || (rb_stb && (rb_addr == RB_PCIE_CTRL_REG)))
+            wb_req_pending  <= 1'b0;
+        else if (axi_in_stb & (axi_in_rd | axi_in_wr)) 
+            wb_req_pending  <= 1'b1;
+    end
+    
+    //wb_resp_pending
+    always @(posedge clk) begin
+        if (rst | (axi_out_stb & msgo_fifo_tready & axi_out_rr))
+            wb_resp_pending  <= 1'b0;
+        else if (axi_in_stb & axi_in_rd) 
+            wb_resp_pending  <= 1'b1;
+    end
+
+    //pcie_resp_pending
+    always @(posedge clk) begin
+        if (rst | (axi_in_stb & axi_in_rr))
+            pcie_resp_pending  <= 1'b0;
+        else if (axi_out_stb & msgo_fifo_tready & axi_out_rd) 
+            pcie_resp_pending  <= 1'b1;
+    end
+    //------------------------------------------
+
+
+endmodule
diff --git a/fpga/usrp3/lib/io_port2/pcie_basic_regs.v b/fpga/usrp3/lib/io_port2/pcie_basic_regs.v
new file mode 100644
index 000000000..8fbff2122
--- /dev/null
+++ b/fpga/usrp3/lib/io_port2/pcie_basic_regs.v
@@ -0,0 +1,109 @@
+//
+// Copyright 2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+module pcie_basic_regs #(
+    parameter SIGNATURE = 32'h0,
+    parameter CLK_FREQ  = 32'h0
+) (
+    input           clk,
+    input           reset,
+
+    input [63:0]    regi_tdata,
+    input           regi_tvalid,
+    output          regi_tready,
+    output [63:0]   rego_tdata,
+    output          rego_tvalid,
+    input           rego_tready,
+    
+    input [31:0]    misc_status
+);
+    localparam PCIE_FPGA_SIG_VAL                = SIGNATURE;
+    localparam PCIE_FPGA_COUNTER_FREQ           = CLK_FREQ;
+
+    localparam PCIE_REG_ADDR_MASK               = 20'h001FF;
+
+    localparam PCIE_FPGA_SIG_REG_ADDR           = 20'h00000;    //32-bit
+    localparam PCIE_FPGA_COUNTER_LO_REG_ADDR    = 20'h00004;    //32-bit
+    localparam PCIE_FPGA_COUNTER_HI_REG_ADDR    = 20'h00008;    //32-bit
+    localparam PCIE_FPGA_COUNTER_FREQ_ADDR      = 20'h0000C;    //32-bit
+    localparam PCIE_FPGA_SCRATCH0_ADDR          = 20'h00010;    //32-bit
+    localparam PCIE_FPGA_SCRATCH1_ADDR          = 20'h00014;    //32-bit
+    localparam PCIE_FPGA_MISC_STATUS_ADDR       = 20'h00020;    //32-bit
+    localparam PCIE_FPGA_USR_SIG_REG_ADDR       = 20'h00030;    //128-bit
+
+    wire            regi_wr, regi_rd;
+    wire [19:0]     regi_addr, regi_addr_local;
+    wire [31:0]     regi_payload;
+    reg  [31:0]     rego_payload;
+
+    ioport2_msg_decode regi_decoder (
+        .message(regi_tdata), .wr_request(regi_wr), .rd_request(regi_rd),
+        .address(regi_addr), .data(regi_payload)
+    );
+
+    ioport2_msg_encode  rego_encoder (
+        .rd_response(1'b1), .data(rego_payload), .message(rego_tdata)
+    );
+
+    assign regi_tready = (regi_tvalid & regi_wr) | rego_tready;
+    assign rego_tvalid = regi_tvalid & regi_rd;
+    assign regi_addr_local = regi_addr & PCIE_REG_ADDR_MASK;
+
+    //Counter counting bus_clk cycles
+    reg [63:0]  bus_counter;
+    always @(posedge clk) begin
+        if (reset)  bus_counter <= 64'h0;
+        else        bus_counter <= bus_counter + 1;
+    end
+
+    //Scratch registers
+    reg [63:0]  scratch;
+    always @(posedge clk) begin
+        if (reset)  
+            scratch <= 64'h0;
+        else if (regi_tvalid & regi_tready & regi_wr)
+            if (regi_addr_local == PCIE_FPGA_SCRATCH0_ADDR)
+                scratch[31:0]  <= regi_payload;
+            else if (regi_addr_local == PCIE_FPGA_SCRATCH1_ADDR)
+                scratch[63:32] <= regi_payload;
+    end
+    
+    //User signature register
+    reg [127:0]  usr_signature;
+    always @(posedge clk) begin
+        if (reset)
+            usr_signature <= 128'h0;
+        else if (regi_tvalid & regi_tready & regi_wr)
+            if (regi_addr_local == (PCIE_FPGA_USR_SIG_REG_ADDR + 20'h00000))
+                usr_signature[31:0]  <= regi_payload;
+            else if (regi_addr_local == (PCIE_FPGA_USR_SIG_REG_ADDR + 20'h00004))
+                usr_signature[63:32]  <= regi_payload;
+            else if (regi_addr_local == (PCIE_FPGA_USR_SIG_REG_ADDR + 20'h00008))
+                usr_signature[95:64]  <= regi_payload;
+            else if (regi_addr_local == (PCIE_FPGA_USR_SIG_REG_ADDR + 20'h0000C))
+                usr_signature[127:96]  <= regi_payload;
+    end
+
+    always @(*) begin
+        case (regi_addr_local)
+            PCIE_FPGA_SIG_REG_ADDR:                 rego_payload = PCIE_FPGA_SIG_VAL;
+            PCIE_FPGA_COUNTER_LO_REG_ADDR:          rego_payload = bus_counter[31:0];
+            PCIE_FPGA_COUNTER_HI_REG_ADDR:          rego_payload = bus_counter[63:32];
+            PCIE_FPGA_COUNTER_FREQ_ADDR:            rego_payload = PCIE_FPGA_COUNTER_FREQ;
+            PCIE_FPGA_SCRATCH0_ADDR:                rego_payload = scratch[31:0];
+            PCIE_FPGA_SCRATCH1_ADDR:                rego_payload = scratch[63:32];
+            PCIE_FPGA_MISC_STATUS_ADDR:             rego_payload = misc_status;
+            PCIE_FPGA_USR_SIG_REG_ADDR + 20'h00000: rego_payload = usr_signature[31:0];
+            PCIE_FPGA_USR_SIG_REG_ADDR + 20'h00004: rego_payload = usr_signature[63:32];
+            PCIE_FPGA_USR_SIG_REG_ADDR + 20'h00008: rego_payload = usr_signature[95:64];
+            PCIE_FPGA_USR_SIG_REG_ADDR + 20'h0000C: rego_payload = usr_signature[127:96];
+            default:                                rego_payload = 32'hFFFFFFFF;
+        endcase
+    end
+
+endmodule
diff --git a/fpga/usrp3/lib/io_port2/pcie_dma_ctrl.v b/fpga/usrp3/lib/io_port2/pcie_dma_ctrl.v
new file mode 100644
index 000000000..d575226fc
--- /dev/null
+++ b/fpga/usrp3/lib/io_port2/pcie_dma_ctrl.v
@@ -0,0 +1,157 @@
+//
+// Copyright 2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+`define BIT_WIDTH(N) (\
+                 N <= 2    ? 1 : \
+                 N <= 4    ? 2 : \
+                 N <= 8    ? 3 : \
+                 N <= 16   ? 4 : \
+                 N <= 32   ? 5 : \
+                 N <= 64   ? 6 : \
+                 N <= 128  ? 7 : \
+                 N <= 256  ? 8 : \
+                 N <= 512  ? 9 : \
+                 10)
+`define GET_REG_OFFSET(reg_addr, chan_idx) (((chan_idx * (1<<DMA_REG_GRP_W)) + reg_addr) + REG_BASE_ADDR)
+`define EXTRACT_CHAN_NUM(reg_addr) regi_addr[`BIT_WIDTH(NUM_STREAMS)+DMA_REG_GRP_W-1:DMA_REG_GRP_W]
+
+module pcie_dma_ctrl #(
+    parameter NUM_STREAMS   = 4,
+    parameter FRAME_SIZE_W  = 16,
+    parameter REG_BASE_ADDR = 20'h00000,
+    parameter ENABLE_ROUTER = 0,
+    parameter ROUTER_SID_W  = 8,
+    parameter ROUTER_DST_W  = 2    
+) (
+    input           clk,
+    input           reset,
+
+    input [63:0]    regi_tdata,
+    input           regi_tvalid,
+    output          regi_tready,
+    output [63:0]   rego_tdata,
+    output          rego_tvalid,
+    input           rego_tready,
+    
+    output reg [NUM_STREAMS-1:0]            set_enabled,
+    output reg [NUM_STREAMS-1:0]            set_clear,
+    output [(NUM_STREAMS*FRAME_SIZE_W)-1:0] set_frame_size,
+    
+    input  [NUM_STREAMS-1:0]                packet_stb,
+    input  [NUM_STREAMS-1:0]                sample_stb,
+    input  [NUM_STREAMS-1:0]                stream_busy,
+    input  [NUM_STREAMS-1:0]                stream_err,
+
+    input  [ROUTER_SID_W-1:0]               rtr_sid,
+    output [ROUTER_DST_W-1:0]               rtr_dst    
+);
+    
+    localparam DMA_REG_GRP_W        = 4;
+    localparam DMA_CTRL_STATUS_REG  = 4'h0; //[RW] R: Stream Status, W: Stream Control
+    localparam DMA_FSIZE_REG        = 4'h4; //[RW] R: Frame Size, W: Frame Size
+    localparam DMA_SAMP_CNT_REG     = 4'h8; //[RW] R: Sample Count, W: Reset Count to 0
+    localparam DMA_PKT_CNT_REG      = 4'hC; //[RW] R: Packet Count, W: Reset Count to 0
+    
+    localparam DEFAULT_FSIZE        = 32;
+
+    //NOTE: Although this module supports these, the 8 and 16 bit modes will be disabled for efficiency
+    localparam DMA_CTRL_BUF_SIZE_8  = 2'b00;    // 8-bit wide SW buffer
+    localparam DMA_CTRL_BUF_SIZE_16 = 2'b01;    //16-bit wide SW buffer
+    localparam DMA_CTRL_BUF_SIZE_32 = 2'b10;    //32-bit wide SW buffer
+    localparam DMA_CTRL_BUF_SIZE_64 = 2'b11;    //64-bit wide SW buffer
+
+    wire            regi_wr, regi_rd;
+    wire [19:0]     regi_addr;
+    wire [31:0]     regi_payload;
+    wire [31:0]     rego_payload;
+
+    ioport2_msg_decode regi_decoder (
+        .message(regi_tdata), .wr_request(regi_wr), .rd_request(regi_rd),
+        .address(regi_addr), .data(regi_payload)
+    );
+
+    ioport2_msg_encode  rego_encoder (
+        .rd_response(1'b1), .data(rego_payload), .message(rego_tdata)
+    );
+
+    reg [31:0]              pkt_count_mem[0:NUM_STREAMS-1];
+    reg [31:0]              samp_count_mem[0:NUM_STREAMS-1];
+    reg [FRAME_SIZE_W-1:0]  frame_size_mem[0:NUM_STREAMS-1];
+
+    genvar i;
+    generate
+        for (i=0; i<NUM_STREAMS; i=i+1) begin: dma_ctrl_logic_generator
+            //Memory -> output translations
+            assign set_frame_size[(FRAME_SIZE_W*(i+1))-1:(FRAME_SIZE_W*i)] = frame_size_mem[i];
+        
+            //Setting registers
+            always @(posedge clk) begin
+                if (reset) begin
+                    frame_size_mem[i] <= DEFAULT_FSIZE;
+                    set_clear[i] <= 0;
+                    set_enabled[i] <= 0;
+                end else if (regi_tready & regi_tvalid & regi_wr) begin
+                    if (regi_addr == `GET_REG_OFFSET(DMA_CTRL_STATUS_REG, i)) begin
+                        set_clear[i]        <= regi_payload[0];                 //DMA_CTRL_STATUS_REG[0] == Clear DMA queues
+                        set_enabled[i]      <= regi_payload[1];                 //DMA_CTRL_STATUS_REG[1] == Enable DMA channel
+                    end else if (regi_addr == `GET_REG_OFFSET(DMA_FSIZE_REG, i)) begin
+                        frame_size_mem[i] <= regi_payload[FRAME_SIZE_W-1:0];    //DMA_FSIZE_REG[14:0] == DMA Frame size
+                    end
+                end else begin
+                    set_clear[i] <= 0;                                          //set_clear should be "self-clearing"
+                end
+            end
+
+            //Packet counter
+            always @(posedge clk) begin
+                if (reset | (regi_tvalid && regi_wr && (regi_addr == `GET_REG_OFFSET(DMA_PKT_CNT_REG, i)))) begin
+                    pkt_count_mem[i] <= 0;
+                end else if (packet_stb[i]) begin
+                    pkt_count_mem[i] <= pkt_count_mem[i] + 1;
+                end
+            end
+
+            //Sample counter
+            always @(posedge clk) begin
+                if (reset | (regi_tvalid && regi_wr && (regi_addr == `GET_REG_OFFSET(DMA_SAMP_CNT_REG, i)))) begin
+                    samp_count_mem[i] <= 0;
+                end else if (sample_stb[i]) begin
+                    samp_count_mem[i] <= samp_count_mem[i] + 1;
+                end
+            end
+        end
+    endgenerate
+    
+    //Readback
+    assign rego_payload =
+        (regi_addr[DMA_REG_GRP_W-1:0] == DMA_PKT_CNT_REG)     ?      pkt_count_mem[`EXTRACT_CHAN_NUM(regi_addr)]  : (
+        (regi_addr[DMA_REG_GRP_W-1:0] == DMA_SAMP_CNT_REG)    ?     samp_count_mem[`EXTRACT_CHAN_NUM(regi_addr)]  : (
+        (regi_addr[DMA_REG_GRP_W-1:0] == DMA_FSIZE_REG)       ?     frame_size_mem[`EXTRACT_CHAN_NUM(regi_addr)]  : (
+        (regi_addr[DMA_REG_GRP_W-1:0] == DMA_CTRL_STATUS_REG) ? {30'h0, stream_busy[`EXTRACT_CHAN_NUM(regi_addr)], stream_err[`EXTRACT_CHAN_NUM(regi_addr)]} : (
+        32'hFFFFFFFF))));
+
+    assign rego_tvalid = regi_tvalid && regi_rd;
+    assign regi_tready = rego_tready || (regi_tvalid && regi_wr);
+    
+    //Optional router
+    generate if (ENABLE_ROUTER == 1) begin
+        pcie_pkt_route_specifier #(
+            .BASE_ADDR((1<<ROUTER_SID_W) + REG_BASE_ADDR), .ADDR_MASK(20'hFFFFF^((1<<ROUTER_SID_W)-1)),
+            .SID_WIDTH(ROUTER_SID_W), .DST_WIDTH(ROUTER_DST_W)
+        ) route_specifier (
+            .clk(clk), .reset(reset),
+            .regi_tdata(regi_tdata), .regi_tvalid(regi_tvalid), .regi_tready(),
+            .local_sid(rtr_sid), .fifo_dst(rtr_dst)
+        );
+    end endgenerate
+    
+endmodule
+
+`undef EXTRACT_CHAN_NUM
+`undef GET_REG_OFFSET
+`undef BIT_WIDTH
diff --git a/fpga/usrp3/lib/io_port2/pcie_dma_ctrl_tb.v b/fpga/usrp3/lib/io_port2/pcie_dma_ctrl_tb.v
new file mode 100644
index 000000000..2b6c40bdd
--- /dev/null
+++ b/fpga/usrp3/lib/io_port2/pcie_dma_ctrl_tb.v
@@ -0,0 +1,92 @@
+//
+// Copyright 2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+`timescale 500ps/1ps
+
+module pcie_dma_ctrl_tb();
+    reg clk    = 0;
+    reg reset  = 1;
+
+    always #10 clk = ~clk;
+
+    initial begin
+        #100 reset = 0;
+        #200000;
+        $finish;
+    end
+   
+    function [63:0] iop2_msg_write;
+        input [19:0]    address;
+        input [31:0]    data;
+        input           half_wd;
+    begin
+        //            {rd_response, wr_request, rd_request, half_word, 8'h00, address, data};
+        iop2_msg_write = {1'b0,        1'b1,       1'b0,       half_wd,   8'h00, address, data};
+    end
+    endfunction // iop2_msg_write
+
+    function [63:0] iop2_msg_read;
+        input [19:0]    address;
+        input           half_wd;
+    begin
+        //            {rd_response, wr_request, rd_request, half_word, 8'h00, address, data};
+        iop2_msg_read = {1'b0,        1'b0,       1'b1,       half_wd,   8'h00, address, 32'h0};
+    end
+    endfunction // iop2_msg_read
+
+    wire [3:0]      clear;
+    wire [63:0]     frame_size;
+    reg [3:0]       pkt_stb = 0;
+    reg [3:0]       samp_stb = 0;
+    reg [3:0]       error = 0;
+    reg [7:0]       rtr_sid = 4;
+    wire [3:0]      rtr_dst;
+
+    reg [63:0]  regi_tdata;
+    reg         regi_tvalid;
+    wire        regi_tready;
+    wire [63:0] rego_tdata;
+    wire        rego_tvalid;
+    reg         rego_tready;
+    reg [31:0]  rego_payload;
+    
+    always @(posedge clk)
+        if (rego_tdata[63] & rego_tvalid & rego_tready)
+            rego_payload <= rego_tdata[31:0];
+
+    initial begin
+        regi_tvalid <= 0;
+        rego_tready <= 0;
+        while (reset) @(posedge clk);
+    
+        rego_tready <= 1;
+        @(posedge clk);
+        
+        regi_tdata <= iop2_msg_write(20'h304, 32'hA, 0);
+        regi_tvalid <= 1;
+        @(posedge clk);
+        while (~regi_tready) @(posedge clk);
+        regi_tvalid <= 0;
+        @(posedge clk);
+    
+    end // initial begin
+    
+    pcie_dma_ctrl #(
+        .NUM_STREAMS(4), .FRAME_SIZE_W(16),
+        .REG_BASE_ADDR(20'h00200), .ENABLE_ROUTER(1),
+        .ROUTER_SID_W(8), .ROUTER_DST_W(4)
+    ) dut (
+        .clk(clk), .reset(reset),
+        .regi_tdata(regi_tdata), .regi_tvalid(regi_tvalid), .regi_tready(regi_tready),
+        .rego_tdata(rego_tdata), .rego_tvalid(rego_tvalid), .rego_tready(rego_tready),
+        .set_clear(clear), .set_frame_size(frame_size), .sample_stb(samp_stb), .packet_stb(pkt_stb), 
+        .stream_err(error), .rtr_sid(rtr_sid), .rtr_dst(rtr_dst)
+    );
+    
+
+endmodule
diff --git a/fpga/usrp3/lib/io_port2/pcie_iop2_msg_arbiter.v b/fpga/usrp3/lib/io_port2/pcie_iop2_msg_arbiter.v
new file mode 100644
index 000000000..59e7b8ef9
--- /dev/null
+++ b/fpga/usrp3/lib/io_port2/pcie_iop2_msg_arbiter.v
@@ -0,0 +1,134 @@
+//
+// Copyright 2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+module pcie_iop2_msg_arbiter #(
+    parameter E0_ADDR = 20'h0,
+    parameter E0_MASK = 20'h0,
+    parameter E1_ADDR = 20'h0,
+    parameter E1_MASK = 20'h0,
+    parameter E2_ADDR = 20'h0,
+    parameter E2_MASK = 20'h0,
+    parameter E3_ADDR = 20'h0,
+    parameter E3_MASK = 20'h0
+) (
+    //Clocks and resets
+    input           clk,
+    input           reset,
+
+    input [63:0]    regi_tdata,
+    input           regi_tvalid,
+    output          regi_tready,
+    output [63:0]   rego_tdata,
+    output          rego_tvalid,    
+    input           rego_tready,
+
+    output [63:0]   e0_regi_tdata,
+    output          e0_regi_tvalid,
+    input           e0_regi_tready,
+    input [63:0]    e0_rego_tdata,
+    input           e0_rego_tvalid,    
+    output          e0_rego_tready,
+    
+    output [63:0]   e1_regi_tdata,
+    output          e1_regi_tvalid,
+    input           e1_regi_tready,
+    input [63:0]    e1_rego_tdata,
+    input           e1_rego_tvalid,    
+    output          e1_rego_tready,
+
+    output [63:0]   e2_regi_tdata,
+    output          e2_regi_tvalid,
+    input           e2_regi_tready,
+    input [63:0]    e2_rego_tdata,
+    input           e2_rego_tvalid,    
+    output          e2_rego_tready,
+
+    output [63:0]   e3_regi_tdata,
+    output          e3_regi_tvalid,
+    input           e3_regi_tready,
+    input [63:0]    e3_rego_tdata,
+    input           e3_rego_tvalid,    
+    output          e3_rego_tready
+);
+
+    //*******************************************************************************
+    // PCIe output message arbiter
+    //
+    axi_mux4 #(.PRIO(0), .WIDTH(64), .BUFFER(0)) rego_arbiter_mux (
+        .clk(clk), .reset(reset), .clear(1'b0),
+        .i0_tdata(e0_rego_tdata), .i0_tlast(e0_rego_tvalid), .i0_tvalid(e0_rego_tvalid), .i0_tready(e0_rego_tready),
+        .i1_tdata(e1_rego_tdata), .i1_tlast(e1_rego_tvalid), .i1_tvalid(e1_rego_tvalid), .i1_tready(e1_rego_tready),
+        .i2_tdata(e2_rego_tdata), .i2_tlast(e2_rego_tvalid), .i2_tvalid(e2_rego_tvalid), .i2_tready(e2_rego_tready),
+        .i3_tdata(e3_rego_tdata), .i3_tlast(e3_rego_tvalid), .i3_tvalid(e3_rego_tvalid), .i3_tready(e3_rego_tready),
+        .o_tdata(rego_tdata), .o_tlast(), .o_tvalid(rego_tvalid), .o_tready(rego_tready)
+    );
+    //
+    //*******************************************************************************
+
+    //*******************************************************************************
+    // PCIe input message arbiter
+    //
+    wire [63:0]     regi_msg;
+    wire            regi_rc;
+    wire [19:0]     regi_addr;
+    wire            e0_rego_rd, e1_rego_rd, e2_rego_rd, e3_rego_rd;
+
+    ioport2_msg_decode e0_rego_decoder (.message(e0_rego_tdata), .rd_request(e0_rego_rd));
+    ioport2_msg_decode e1_rego_decoder (.message(e1_rego_tdata), .rd_request(e1_rego_rd));
+    ioport2_msg_decode e2_rego_decoder (.message(e2_rego_tdata), .rd_request(e2_rego_rd));
+    ioport2_msg_decode e3_rego_decoder (.message(e3_rego_tdata), .rd_request(e3_rego_rd));
+
+    localparam DEST_E0   = 2'd0;
+    localparam DEST_E1   = 2'd1;
+    localparam DEST_E2   = 2'd2;
+    localparam DEST_E3   = 2'd3;
+
+    reg  [1:0]  regi_resp_dest;
+    wire [1:0]  regi_req_dest, regi_dest;
+    
+    assign regi_req_dest = 
+        ((regi_addr & E0_MASK) == E0_ADDR) ? DEST_E0 : (
+        ((regi_addr & E1_MASK) == E1_ADDR) ? DEST_E1 : (
+        ((regi_addr & E2_MASK) == E2_ADDR) ? DEST_E2 : (
+        ((regi_addr & E3_MASK) == E3_ADDR) ? DEST_E3 : (
+        DEST_E0))));
+    
+    //A response must be routed to the port with the last read request 
+    always @(posedge clk) begin
+        if (reset)
+            regi_resp_dest <= DEST_E0;  //Default 0
+        else if (e0_rego_tvalid & e0_rego_tready & e0_rego_rd)
+            regi_resp_dest <= DEST_E0;
+        else if (e1_rego_tvalid & e1_rego_tready & e1_rego_rd)
+            regi_resp_dest <= DEST_E1;
+        else if (e2_rego_tvalid & e2_rego_tready & e2_rego_rd)
+            regi_resp_dest <= DEST_E2;
+        else if (e3_rego_tvalid & e3_rego_tready & e3_rego_rd)
+            regi_resp_dest <= DEST_E3;
+    end
+
+    ioport2_msg_decode regi_decoder (
+        .message(regi_msg), .rd_response(regi_rc), .address(regi_addr));
+
+    //If request, get destination from msg. 
+    //If response, get destination from last read location. 
+    assign regi_dest = regi_rc ? regi_resp_dest : regi_req_dest;
+
+    axi_demux4 #(.ACTIVE_CHAN(4'b1111), .WIDTH(64), .BUFFER(0)) regi_arbiter_demux (
+        .clk(clk), .reset(reset), .clear(1'b0),
+        .header(regi_msg), .dest(regi_dest),
+        .i_tdata(regi_tdata), .i_tlast(regi_tvalid), .i_tvalid(regi_tvalid), .i_tready(regi_tready),
+        .o0_tdata(e0_regi_tdata), .o0_tlast(), .o0_tvalid(e0_regi_tvalid), .o0_tready(e0_regi_tready),
+        .o1_tdata(e1_regi_tdata), .o1_tlast(), .o1_tvalid(e1_regi_tvalid), .o1_tready(e1_regi_tready),
+        .o2_tdata(e2_regi_tdata), .o2_tlast(), .o2_tvalid(e2_regi_tvalid), .o2_tready(e2_regi_tready),
+        .o3_tdata(e3_regi_tdata), .o3_tlast(), .o3_tvalid(e3_regi_tvalid), .o3_tready(e3_regi_tready)
+    );
+    //
+    //*******************************************************************************
+
+endmodule
diff --git a/fpga/usrp3/lib/io_port2/pcie_iop2_msg_arbiter_tb.v b/fpga/usrp3/lib/io_port2/pcie_iop2_msg_arbiter_tb.v
new file mode 100644
index 000000000..fe566b1aa
--- /dev/null
+++ b/fpga/usrp3/lib/io_port2/pcie_iop2_msg_arbiter_tb.v
@@ -0,0 +1,110 @@
+//
+// Copyright 2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+`timescale 500ps/1ps
+
+module pcie_iop2_msg_arbiter_tb();
+    reg clk    = 0;
+    reg reset  = 1;
+
+    always #10 clk = ~clk;
+
+    initial begin
+        #100 reset = 0;
+        #200000;
+        $finish;
+    end
+   
+    function [63:0] iop2_msg_write;
+        input [19:0]    address;
+        input [31:0]    data;
+        input           half_wd;
+    begin
+        //            {rd_response, wr_request, rd_request, half_word, 8'h00, address, data};
+        iop2_msg_write = {1'b0,        1'b1,       1'b0,       half_wd,   8'h00, address, data};
+    end
+    endfunction // iop2_msg_write
+
+    function [63:0] iop2_msg_read;
+        input [19:0]    address;
+        input           half_wd;
+    begin
+        //            {rd_response, wr_request, rd_request, half_word, 8'h00, address, data};
+        iop2_msg_read = {1'b0,        1'b0,       1'b1,       half_wd,   8'h00, address, 32'h0};
+    end
+    endfunction // iop2_msg_read
+
+    reg [63:0]  msgi_tdata;
+    wire [63:0] msgo_tdata;
+    wire        msgo_tvalid, msgi_tready;
+    reg         msgo_tready, msgi_tvalid;
+
+    wire [63:0] basic_regi_tdata, zpu_regi_tdata;
+    wire        basic_regi_tvalid, zpu_regi_tvalid;
+    reg         basic_regi_tready, zpu_regi_tready;
+    reg [63:0]  basic_rego_tdata, zpu_rego_tdata;
+    reg         basic_rego_tvalid, zpu_rego_tvalid;
+    wire        basic_rego_tready, zpu_rego_tready;
+
+    initial begin
+        //@TODO: Make this a self-checking TB
+        while (reset) @(posedge clk);
+    
+        msgo_tready <= 1;
+        basic_regi_tready <= 1;
+        @(posedge clk);
+        
+        
+        msgi_tdata <= iop2_msg_write(20'h0, 32'hDEAD, 0);
+        msgi_tvalid <= 1;
+        while (~msgi_tready) @(posedge clk);
+        msgi_tvalid <= 0;
+        @(posedge clk);
+        
+        
+        msgi_tdata <= iop2_msg_read(20'h00000, 0);
+        msgi_tvalid <= 1;
+        while (~msgi_tready) @(posedge clk);
+        msgi_tvalid <= 0;
+        @(posedge clk);
+
+        zpu_rego_tdata <= {1, 31'h0, 32'h12345678};
+        zpu_rego_tvalid <= 1;
+        while (~zpu_rego_tready) @(posedge clk);
+        zpu_rego_tvalid <= 0;
+        
+
+
+    end // initial begin
+    
+    pcie_iop2_msg_arbiter #(
+        .E0_ADDR(20'h00000), .E0_MASK(20'hFFF00),     //0x00000 - 0x000FF: Basic PCIe registers
+        .E1_ADDR(20'h00100), .E1_MASK(20'hFFF00),     //0x00100 - 0x001FF: PCIe router registers
+        .E2_ADDR(20'h00200), .E2_MASK(20'hFFE00),     //0x00200 - 0x003FF: DMA stream registers
+        .E3_ADDR(20'h40000), .E3_MASK(20'hC0000)      //0x40000 - 0x7FFFF: Client address space 
+    ) iop2_msg_arbiter (
+        .clk(clk), .reset(reset),
+        //Master
+        .regi_tdata(msgi_tdata), .regi_tvalid(msgi_tvalid), .regi_tready(msgi_tready),
+        .rego_tdata(msgo_tdata), .rego_tvalid(msgo_tvalid), .rego_tready(msgo_tready),
+        //Endpoint 0
+        .e0_regi_tdata(basic_regi_tdata), .e0_regi_tvalid(basic_regi_tvalid), .e0_regi_tready(basic_regi_tready),
+        .e0_rego_tdata(basic_rego_tdata), .e0_rego_tvalid(basic_rego_tvalid), .e0_rego_tready(basic_rego_tready),
+        //Endpoint 1
+        .e1_regi_tdata(), .e1_regi_tvalid(), .e1_regi_tready(1'b1),
+        .e1_rego_tdata(64'h0), .e1_rego_tvalid(1'b0), .e1_rego_tready(),
+        //Endpoint 2
+        .e2_regi_tdata(), .e2_regi_tvalid(), .e2_regi_tready(1'b1),
+        .e2_rego_tdata(64'h0), .e2_rego_tvalid(1'b0), .e2_rego_tready(),
+        //Endpoint 3
+        .e3_regi_tdata(zpu_regi_tdata), .e3_regi_tvalid(zpu_regi_tvalid), .e3_regi_tready(zpu_regi_tready),
+        .e3_rego_tdata(zpu_rego_tdata), .e3_rego_tvalid(zpu_rego_tvalid), .e3_rego_tready(zpu_rego_tready)
+    );
+    
+
+endmodule
diff --git a/fpga/usrp3/lib/io_port2/pcie_lossy_samp_gate.v b/fpga/usrp3/lib/io_port2/pcie_lossy_samp_gate.v
new file mode 100644
index 000000000..7f479e3ad
--- /dev/null
+++ b/fpga/usrp3/lib/io_port2/pcie_lossy_samp_gate.v
@@ -0,0 +1,29 @@
+//
+// Copyright 2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+module pcie_lossy_samp_gate
+(
+   input [63:0]   i_tdata,
+   input          i_tvalid,
+   output         i_tready,
+   
+   output [63:0]  o_tdata,
+   output         o_tvalid,
+   input          o_tready,
+   
+   input          drop,
+   output         dropping
+);
+
+   assign o_tdata    = i_tdata;
+   assign o_tvalid   = i_tvalid & ~drop;
+   assign i_tready   = o_tready | drop;
+   
+   assign dropping   = drop & i_tvalid;
+   
+endmodule // pcie_lossy_samp_gate
diff --git a/fpga/usrp3/lib/io_port2/pcie_pkt_route_specifier.v b/fpga/usrp3/lib/io_port2/pcie_pkt_route_specifier.v
new file mode 100644
index 000000000..f6a2a9ab3
--- /dev/null
+++ b/fpga/usrp3/lib/io_port2/pcie_pkt_route_specifier.v
@@ -0,0 +1,46 @@
+//
+// Copyright 2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+module pcie_pkt_route_specifier #(
+    parameter BASE_ADDR = 20'h0,
+    parameter ADDR_MASK = 20'hFFF00,
+    parameter SID_WIDTH = 8,
+    parameter DST_WIDTH = 4
+) (
+    input           clk,
+    input           reset,
+
+    input [63:0]    regi_tdata,
+    input           regi_tvalid,
+    output          regi_tready,
+
+    input  [SID_WIDTH-1:0]  local_sid,
+    output [DST_WIDTH-1:0]  fifo_dst
+);
+    // Routing table
+    reg [DST_WIDTH-1:0] routing_table[0:(1<<SID_WIDTH)-1];
+    assign fifo_dst = routing_table[local_sid];
+    
+    wire        reg_wr;
+    wire [19:0] reg_addr;
+    wire [31:0] reg_data;
+    
+    // Routing table configuration
+    ioport2_msg_decode config_message_decoder (
+        .message(regi_tdata), .wr_request(reg_wr), .rd_request(reg_rd), .address(reg_addr), .data(reg_data)
+    );
+
+    always @(posedge clk) begin
+      if (regi_tvalid && regi_tready && reg_wr && ((reg_addr & ADDR_MASK) == BASE_ADDR)) begin
+        routing_table[reg_data[SID_WIDTH+15:16]] <= reg_data[DST_WIDTH-1:0];
+      end
+    end
+    
+    assign regi_tready = 1;
+    
+endmodule
diff --git a/fpga/usrp3/lib/io_port2/pcie_wb_reg_core.v b/fpga/usrp3/lib/io_port2/pcie_wb_reg_core.v
new file mode 100644
index 000000000..4a55e9c9a
--- /dev/null
+++ b/fpga/usrp3/lib/io_port2/pcie_wb_reg_core.v
@@ -0,0 +1,129 @@
+//
+// Copyright 2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+module pcie_wb_reg_core #(
+    parameter WB_ADDRW  = 16,
+    parameter WB_DATAW  = 32
+)(
+    input                   clk, 
+    input                   rst,
+
+    input                   wb_stb_i,
+    input                   wb_we_i,
+    input  [WB_ADDRW-1:0]   wb_adr_i,
+    input  [WB_DATAW-1:0]   wb_dat_i,
+    output                  wb_ack_o,
+    output [WB_DATAW-1:0]   wb_dat_o,
+
+    input  [63:0]           msgi_tdata,
+    input                   msgi_tvalid,
+    output                  msgi_tready,
+
+    output [63:0]           msgo_tdata,
+    output                  msgo_tvalid,
+    input                   msgo_tready,
+
+    output [31:0]           debug 
+);
+    // Parameters
+    localparam PCIE_REGPORT_ADDR_MASK   = 20'h0FFFF;
+    localparam PCIE_REGPORT_DATA_ADDR   = 20'h70000;
+    localparam PCIE_REGPORT_READ_ADDR   = 20'h60000;
+    localparam PCIE_REGPORT_STATUS_ADDR = 20'h60000;
+
+    //------------------------------------------
+    // WB AXI interface
+    //
+    wire  [63:0]    wb_msgi_tdata, wb_msgo_tdata;
+    wire            wb_msgi_tvalid, wb_msgi_tready, wb_msgo_tvalid, wb_msgo_tready;
+    wire            wb_monitor_active, wb_req_pending, wb_resp_pending;
+
+    pcie_axi_wb_conv #( .WB_ADDRW(WB_ADDRW), .WB_DATAW(WB_DATAW) ) axi_wb_translator (
+        .clk(clk), .rst(rst),
+        .wb_stb_i(wb_stb_i), .wb_we_i(wb_we_i), .wb_adr_i(wb_adr_i),
+        .wb_dat_i(wb_dat_i), .wb_ack_o(wb_ack_o), .wb_dat_o(wb_dat_o),
+        .msgi_tdata(wb_msgo_tdata), .msgi_tvalid(wb_msgo_tvalid), .msgi_tready(wb_msgo_tready),
+        .msgo_tdata(wb_msgi_tdata), .msgo_tvalid(wb_msgi_tvalid), .msgo_tready(wb_msgi_tready),
+        .wb_monitor_active(wb_monitor_active), .wb_req_pending(wb_req_pending), .wb_resp_pending(wb_resp_pending)
+    );
+    //------------------------------------------
+
+    //------------------------------------------
+    // PCIe In -> WB Out
+    //
+    wire            pcie_in_wr, pcie_in_rd, wb_out_wr, wb_out_rd; 
+    wire            pcie2wb_rr, pcie2wb_hword;
+    wire            pcie_in_status_read, pcie_in_data_read;
+    wire [19:0]     pcie_in_addr;
+    wire [31:0]     pcie2wb_payload;
+    
+    ioport2_msg_decode pcie_in_decoder (
+        .message(msgi_tdata),
+        .rd_response(pcie2wb_rr), .wr_request(pcie_in_wr), .rd_request(pcie_in_rd),
+        .half_word(pcie2wb_hword), .address(pcie_in_addr), .data(pcie2wb_payload)
+    );
+
+    ioport2_msg_encode wb_out_decoder (
+        .rd_response(pcie2wb_rr), .wr_request(wb_out_wr), .rd_request(wb_out_rd), 
+        .half_word(pcie2wb_hword), .address(pcie_in_addr & PCIE_REGPORT_ADDR_MASK), .data(pcie2wb_payload),
+        .message(wb_msgo_tdata)
+    );
+    
+    assign wb_out_wr      = pcie_in_wr && ((pcie_in_addr & ~PCIE_REGPORT_ADDR_MASK) == PCIE_REGPORT_DATA_ADDR);
+    assign wb_out_rd      = pcie_in_wr && ((pcie_in_addr & ~PCIE_REGPORT_ADDR_MASK) == PCIE_REGPORT_READ_ADDR);
+    assign wb_msgo_tvalid = msgi_tvalid & (wb_out_wr | wb_out_rd | pcie2wb_rr);
+    assign msgi_tready    = pcie_out_auto_resp_valid ? pcie_out_auto_resp_ready : wb_msgo_tready;
+
+    //------------------------------------------
+    
+    //------------------------------------------
+    // WB In -> PCIe Out
+    //
+    assign pcie_in_status_read = pcie_in_rd && ((pcie_in_addr & ~PCIE_REGPORT_ADDR_MASK) == PCIE_REGPORT_STATUS_ADDR);
+    assign pcie_in_data_read   = pcie_in_rd && ((pcie_in_addr & ~PCIE_REGPORT_ADDR_MASK) == PCIE_REGPORT_DATA_ADDR);
+
+    reg  [31:0]     wb_in_resp_payload_reg;
+
+    wire            wb_in_rr, wb_msgi_tready_int;
+    wire [63:0]     pcie_out_auto_resp_data;
+    wire            pcie_out_auto_resp_valid, pcie_out_auto_resp_ready;
+    wire [31:0]     wb_in_resp_payload;
+
+    ioport2_msg_decode wb_in_decoder (
+        .message(wb_msgi_tdata), .rd_response(wb_in_rr), .data(wb_in_resp_payload)
+    );
+
+    assign pcie_out_auto_resp_valid = (msgi_tvalid & (pcie_in_status_read | pcie_in_data_read));
+    
+    ioport2_msg_encode auto_response_encoder (
+        .rd_response(1'b1), 
+        .data(pcie_in_data_read ? wb_in_resp_payload_reg : {~wb_monitor_active, 30'h0, (wb_req_pending | wb_resp_pending)}),
+        .message(pcie_out_auto_resp_data)
+    );
+
+    always @(posedge clk) begin
+        if (rst)
+            wb_in_resp_payload_reg <= 32'h0;
+        else if (wb_msgi_tvalid & wb_msgi_tready & wb_in_rr)
+            wb_in_resp_payload_reg <= wb_in_resp_payload;
+    end
+
+    axi_mux4 #(.PRIO(0), .WIDTH(64), .BUFFER(1)) msgo_arbiter_mux (
+        .clk(clk), .reset(rst), .clear(1'b0),
+        .i0_tdata(wb_msgi_tdata), .i0_tlast(1'b1), .i0_tvalid(wb_msgi_tvalid & ~wb_in_rr), .i0_tready(wb_msgi_tready_int),
+        .i1_tdata(pcie_out_auto_resp_data), .i1_tlast(1'b1), .i1_tvalid(pcie_out_auto_resp_valid), .i1_tready(pcie_out_auto_resp_ready),
+        .i2_tdata(0), .i2_tlast(1'b0), .i2_tvalid(1'b0), .i2_tready(),
+        .i3_tdata(0), .i3_tlast(1'b0), .i3_tvalid(1'b0), .i3_tready(),
+        .o_tdata(msgo_tdata), .o_tlast(), .o_tvalid(msgo_tvalid), .o_tready(msgo_tready)
+    );
+
+    assign wb_msgi_tready = wb_msgi_tready_int | (wb_msgi_tvalid & wb_in_rr);
+    
+    //------------------------------------------
+
+endmodule
diff --git a/fpga/usrp3/lib/io_port2/pcie_wb_reg_core_tb.v b/fpga/usrp3/lib/io_port2/pcie_wb_reg_core_tb.v
new file mode 100644
index 000000000..62bec9eb4
--- /dev/null
+++ b/fpga/usrp3/lib/io_port2/pcie_wb_reg_core_tb.v
@@ -0,0 +1,243 @@
+//
+// Copyright 2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+`timescale 500ps/1ps
+`define CHECK_VALUE(val, expected, report) \
+        if (val == expected) \
+            $display("%s...Passed",report); \
+        else \
+            $display("%s...FAILED!!! (Val=0x%x, Exp=0x%x)",report,val,expected); \
+
+module pcie_wb_reg_core_tb();
+    reg         clk = 0, reset = 1; 
+    reg         wb_stb_i = 0;
+    reg         wb_we_i = 0;
+    reg  [15:0] wb_adr_i = 0;
+    reg  [31:0] wb_dat_i = 0;
+    wire        wb_ack_o;
+    wire [31:0] wb_dat_o;
+
+    wire [63:0] msgo_data;
+    wire        msgo_valid;
+    reg         msgo_ready = 0;
+    reg  [63:0] msgi_data = 0;
+    reg         msgi_valid = 0;
+    wire        msgi_ready;
+    
+    reg  [31:0] msgo_payload = 32'h0;
+    reg  [31:0] msgo_ctrl = 32'h0;
+    
+    reg  [31:0] it;
+
+    always #10 clk = ~clk;
+
+    initial begin
+        #100 reset = 0;
+        #200000;
+        $finish;
+    end
+   
+    localparam READ     = 3'b001;
+    localparam WRITE    = 3'b010;
+    localparam RESPONSE = 3'b100;
+   
+    task pcie_send;
+        input [2:0]     op;
+        input [19:0]    address;
+        input [31:0]    data;
+    begin
+        //{rd_resp, wr_request, rd_request, half_word, 8'h00, address, data};
+        msgi_data  <= {op, 1'b0, 8'h00, address, data};
+        msgi_valid <= 1'b1;
+
+        @(posedge clk);
+        while (~msgi_ready) @(posedge clk);
+        
+        msgi_valid <= 1'b0;
+        @(posedge clk);
+    end
+    endtask // pcie_send
+
+    task pcie_recv;
+        input [2:0]     op;
+        input [19:0]    address;
+        input [31:0]    data;
+    begin
+        while (~msgo_valid) @(posedge clk);
+
+        msgo_ready <= 1'b1;
+        @(posedge clk);
+        
+        if (msgo_data[63] == op[2] || (msgo_data[62:61] == op[1:0] && msgo_data[51:32] == address))
+            msgo_payload <= msgo_data[31:0];
+            msgo_ctrl <= msgo_data[63:32];
+
+        msgo_ready <= 1'b0;
+        @(posedge clk);
+    end
+    endtask // pcie_recv
+
+    task wb_send;
+        input [2:0]     op;
+        input [15:0]    address;
+        input [31:0]    data;
+    begin
+        wb_adr_i <= address;
+        wb_dat_i <= data;
+        wb_we_i <= op[1];
+        wb_stb_i <= 1'b1;
+        
+        @(posedge clk);
+        while (~wb_ack_o) @(posedge clk);
+        
+        wb_stb_i <= 1'b0;
+    end
+    endtask // pcie_send
+
+
+    initial begin
+        msgo_ready <= 1'b0;
+        msgi_valid <= 1'b0;
+        while (reset) @(posedge clk);    
+        @(posedge clk);
+        
+        $display("\n[TEST] ZPU Read from PCIe");
+        pcie_send(WRITE, 20'h6a000, 32'h0);
+        `CHECK_VALUE(msgo_payload, 32'h0, "Verify PCIe readback before initiating read request");
+        pcie_send(READ, 20'h6a000, 32'h0);
+        pcie_recv(RESPONSE, 20'h0, 20'h0);
+        `CHECK_VALUE(msgo_payload, 32'h1, "Verify PCIe status after initiating read");
+        pcie_send(READ, 20'h6a000, 32'h0);
+        pcie_recv(RESPONSE, 20'h0, 20'h0);
+        `CHECK_VALUE(msgo_payload, 32'h1, "Verify PCIe status after initiating second read");
+        wb_send(READ, 16'hC, 32'h0);
+        `CHECK_VALUE(wb_dat_o, 32'h6, "Verify WB status after PCIe read request");
+        wb_send(READ, 16'h4, 32'h0);
+        `CHECK_VALUE(wb_dat_o, 32'h2000a000, "Verify WB control value after PCIe read request");
+        wb_send(READ, 16'hC, 32'h0);
+        `CHECK_VALUE(wb_dat_o, 32'h4, "Verify WB status value after consuming PCIe read request");
+        pcie_send(READ, 20'h6a000, 32'h0);
+        pcie_recv(RESPONSE, 20'h0, 20'h0);
+        `CHECK_VALUE(msgo_payload, 32'h1, "Verify PCIe status after WB consumes request only");
+        wb_send(WRITE, 16'h0, 32'hDEADBEEF);
+        wb_send(WRITE, 16'h4, 32'h80000000);
+        wb_send(READ, 16'hC, 32'h0);
+        `CHECK_VALUE(wb_dat_o, 32'h0, "Verify WB status value after responding to PCIe read request");
+        pcie_send(READ, 20'h6a000, 32'h0);
+        pcie_recv(RESPONSE, 20'h0, 20'h0);
+        `CHECK_VALUE(msgo_payload, 32'h0, "Verify PCIe status after WB responds to read request");
+        pcie_send(READ, 20'h7a000, 32'h0);
+        pcie_recv(RESPONSE, 20'h0, 20'h0);
+        `CHECK_VALUE(msgo_payload, 32'hdeadbeef, "Verify PCIe read data");
+    
+        $display("\n[TEST] ZPU Write from PCIe");
+        pcie_send(WRITE, 20'h7b000, 32'h12345678);
+        pcie_send(READ, 20'h7a000, 32'h0);
+        pcie_recv(RESPONSE, 20'h0, 20'h0);
+        `CHECK_VALUE(msgo_payload, 32'hdeadbeef, "Verify that PCIe read data is still intact after write");
+        wb_send(READ, 16'hC, 32'h0);
+        `CHECK_VALUE(wb_dat_o, 32'h2, "Verify WB status value after PCIe write request");
+        wb_send(READ, 16'h0, 32'h0);
+        `CHECK_VALUE(wb_dat_o, 32'h12345678, "Verify WB data value after PCIe read request");
+        wb_send(READ, 16'h4, 32'h0);
+        `CHECK_VALUE(wb_dat_o, 32'h4000b000, "Verify WB control value after PCIe read request");
+        wb_send(READ, 16'hC, 32'h0);
+        `CHECK_VALUE(wb_dat_o, 32'h0, "Verify WB status value after consuming PCIe write request");
+        pcie_send(READ, 20'h6a000, 32'h0);
+        pcie_recv(RESPONSE, 20'h0, 20'h0);
+        `CHECK_VALUE(msgo_payload, 32'h0, "Verify PCIe status after WB consumes request");
+
+        $display("\n[TEST] Chinch Write from ZPU");
+        wb_send(READ, 16'hC, 32'h0);
+        `CHECK_VALUE(wb_dat_o, 32'h0, "Verify WB status value before initiating write request");
+        wb_send(WRITE, 16'h0, 32'h00beef00);
+        wb_send(READ, 16'hC, 32'h0);
+        `CHECK_VALUE(wb_dat_o, 32'h0, "Verify WB status value after writing just the data reg");
+        wb_send(WRITE, 16'h4, 32'h40000200);
+        wb_send(READ, 16'hC, 32'h0);
+        `CHECK_VALUE(wb_dat_o, 32'h0, "Verify WB status value after initiating write");
+        pcie_recv(WRITE, 20'h200, 20'h0);
+        `CHECK_VALUE(msgo_payload, 32'h00beef00, "Verify received PCIe data");
+        `CHECK_VALUE(msgo_ctrl, 32'h40000200, "Verify received PCIe control");
+        wb_send(WRITE, 16'h0, 32'h00feeb00);
+        wb_send(WRITE, 16'h4, 32'h400002fc);
+        pcie_recv(WRITE, 20'h200, 20'h0);
+        `CHECK_VALUE(msgo_payload, 32'h00feeb00, "Verify second received PCIe data");
+        `CHECK_VALUE(msgo_ctrl, 32'h400002fc, "Verify second received PCIe control");
+
+        $display("\n[TEST] Chinch Read from ZPU");
+        wb_send(READ, 16'hC, 32'h0);
+        `CHECK_VALUE(wb_dat_o, 32'h0, "Verify WB status value before initiating read request");
+        wb_send(WRITE, 16'h0, 32'hffffffff);
+        wb_send(READ, 16'hC, 32'h0);
+        `CHECK_VALUE(wb_dat_o, 32'h0, "Verify WB status value after writing just the data reg");
+        wb_send(WRITE, 16'h4, 32'h20000400);
+        wb_send(READ, 16'hC, 32'h0);
+        `CHECK_VALUE(wb_dat_o, 32'h1, "Verify WB status value after initiating read request");
+        pcie_recv(READ, 20'h400, 20'h0);
+        `CHECK_VALUE(msgo_payload, 32'hffffffff, "Verify received PCIe data");
+        `CHECK_VALUE(msgo_ctrl, 32'h20000400, "Verify received PCIe control");
+        wb_send(READ, 16'hC, 32'h0);
+        wb_send(READ, 16'hC, 32'h0);
+        `CHECK_VALUE(wb_dat_o, 32'h1, "Verify WB status value before PCIe responds");
+        pcie_send(RESPONSE, 20'h000, 32'hace06666);
+        wb_send(READ, 16'hC, 32'h0);
+        `CHECK_VALUE(wb_dat_o, 32'h0, "Verify WB status value after PCIe responds");
+        wb_send(READ, 16'h8, 32'h0);
+        `CHECK_VALUE(wb_dat_o, 32'hace06666, "Verify WB read value after PCIe responds");
+
+        $display("\n[TEST] WB Outbound flood");
+        wb_send(READ, 16'hC, 32'h0);
+        `CHECK_VALUE(wb_dat_o, 32'h0, "Verify WB status before request flood");
+        for (it = 0; it < 64; it = it + 1) begin
+            wb_send(WRITE, 16'h4, 32'h20000400);
+        end
+        wb_send(READ, 16'hC, 32'h0);
+        `CHECK_VALUE(wb_dat_o, 32'h11, "Verify WB status after request flood");
+        for (it = 0; it < 64; it = it + 1) begin
+            pcie_recv(READ, 20'h400, 20'h0);
+        end
+        wb_send(READ, 16'hC, 32'h0);
+        `CHECK_VALUE(wb_dat_o, 32'h1, "Verify WB status after consuming requests");
+
+        $display("\n[TEST] PCIe Transaction Status");
+        pcie_send(READ, 20'h6a000, 32'h0);
+        pcie_recv(RESPONSE, 20'h0, 20'h0);
+        `CHECK_VALUE(msgo_payload, 32'h0, "Verify PCIe status before multiple reads");
+        pcie_send(WRITE, 20'h6a000, 32'h0);
+        pcie_send(WRITE, 20'h6a000, 32'h0);
+        pcie_send(WRITE, 20'h6a000, 32'h0);
+        pcie_send(READ, 20'h6a000, 32'h0);
+        pcie_recv(RESPONSE, 20'h0, 20'h0);
+        pcie_send(READ, 20'h6a000, 32'h0);
+        pcie_recv(RESPONSE, 20'h0, 20'h0);
+        pcie_send(READ, 20'h6a000, 32'h0);
+        pcie_recv(RESPONSE, 20'h0, 20'h0);
+        `CHECK_VALUE(msgo_payload, 32'h1, "Verify PCIe status before multiple read requests and status queries");
+        wb_send(READ, 16'h4, 32'h0);
+        wb_send(WRITE, 16'h0, 32'hDEADBEEF);
+        wb_send(WRITE, 16'h4, 32'h80000000);
+        pcie_send(READ, 20'h6a000, 32'h0);
+        pcie_recv(RESPONSE, 20'h0, 20'h0);
+        `CHECK_VALUE(msgo_payload, 32'h0, "Verify PCIe status after response");
+        
+        $display("\n[DONE]");
+
+
+    end // initial begin
+    
+    pcie_wb_reg_core #(.WB_ADDRW(16), .WB_DATAW(32)) dut (
+        .clk(clk), .rst(reset),
+        .wb_stb_i(wb_stb_i), .wb_we_i(wb_we_i), .wb_adr_i(wb_adr_i),
+        .wb_dat_i(wb_dat_i), .wb_ack_o(wb_ack_o), .wb_dat_o(wb_dat_o),
+        .msgi_tdata(msgi_data), .msgi_tvalid(msgi_valid), .msgi_tready(msgi_ready),
+        .msgo_tdata(msgo_data), .msgo_tvalid(msgo_valid), .msgo_tready(msgo_ready),
+        .debug());
+    
+
+endmodule
diff --git a/fpga/usrp3/lib/ip/Makefile.inc b/fpga/usrp3/lib/ip/Makefile.inc
new file mode 100644
index 000000000..6baaa0852
--- /dev/null
+++ b/fpga/usrp3/lib/ip/Makefile.inc
@@ -0,0 +1,69 @@
+#
+# Copyright 2016 Ettus Research, a National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+include $(LIB_IP_DIR)/axi_fft/Makefile.inc
+include $(LIB_IP_DIR)/axi_hb31/Makefile.inc
+include $(LIB_IP_DIR)/axi_hb47/Makefile.inc
+include $(LIB_IP_DIR)/complex_to_magphase/Makefile.inc
+include $(LIB_IP_DIR)/complex_to_magphase_int16_int24/Makefile.inc
+include $(LIB_IP_DIR)/complex_to_magphase_int32/Makefile.inc
+include $(LIB_IP_DIR)/complex_multiplier/Makefile.inc
+include $(LIB_IP_DIR)/complex_multiplier_dds/Makefile.inc
+include $(LIB_IP_DIR)/cordic_rotator/Makefile.inc
+include $(LIB_IP_DIR)/cordic_rotator24/Makefile.inc
+include $(LIB_IP_DIR)/cordic_rotate_int24_int16/Makefile.inc
+include $(LIB_IP_DIR)/cordic_rotate_int24/Makefile.inc
+include $(LIB_IP_DIR)/divide_int16/Makefile.inc
+include $(LIB_IP_DIR)/divide_int24/Makefile.inc
+include $(LIB_IP_DIR)/divide_int32/Makefile.inc
+include $(LIB_IP_DIR)/divide_uint32/Makefile.inc
+include $(LIB_IP_DIR)/divide_int16_int32/Makefile.inc
+include $(LIB_IP_DIR)/dds_sin_cos_lut_only/Makefile.inc
+
+LIB_IP_XCI_SRCS = \
+$(LIB_IP_AXI_FFT_SRCS) \
+$(LIB_IP_AXI_HB31_SRCS) \
+$(LIB_IP_AXI_HB47_SRCS) \
+$(LIB_IP_COMPLEX_TO_MAGPHASE_SRCS) \
+$(LIB_IP_COMPLEX_TO_MAGPHASE_INT16_INT24_SRCS) \
+$(LIB_IP_COMPLEX_TO_MAGPHASE_INT32_SRCS) \
+$(LIB_IP_COMPLEX_MULTIPLIER_SRCS) \
+$(LIB_IP_COMPLEX_MULTIPLIER_DDS_SRCS) \
+$(LIB_IP_CORDIC_ROTATOR_SRCS) \
+$(LIB_IP_CORDIC_ROTATOR24_SRCS) \
+$(LIB_IP_CORDIC_ROTATE_INT24_INT16_SRCS) \
+$(LIB_IP_CORDIC_ROTATE_INT24_SRCS) \
+$(LIB_IP_DIVIDE_INT16_SRCS) \
+$(LIB_IP_DIVIDE_INT24_SRCS) \
+$(LIB_IP_DIVIDE_INT32_SRCS) \
+$(LIB_IP_DIVIDE_UINT32_SRCS) \
+$(LIB_IP_DIVIDE_INT16_INT32_SRCS) \
+$(LIB_IP_DDS_SIN_COS_LUT_ONLY_SRCS)
+
+LIB_IP_SYNTH_OUTPUTS = \
+$(LIB_IP_AXI_FFT_OUTS) \
+$(LIB_IP_AXI_HB31_OUTS) \
+$(LIB_IP_AXI_HB47_OUTS) \
+$(LIB_IP_COMPLEX_TO_MAGPHASE_OUTS) \
+$(LIB_IP_COMPLEX_TO_MAGPHASE_INT16_INT24_OUTS) \
+$(LIB_IP_COMPLEX_TO_MAGPHASE_INT32_OUTS) \
+$(LIB_IP_COMPLEX_MULTIPLIER_OUTS) \
+$(LIB_IP_COMPLEX_MULTIPLIER_DDS_OUTS) \
+$(LIB_IP_CORDIC_ROTATOR_OUTS) \
+$(LIB_IP_CORDIC_ROTATOR24_OUTS) \
+$(LIB_IP_CORDIC_ROTATE_INT24_INT16_OUTS) \
+$(LIB_IP_CORDIC_ROTATE_INT24_OUTS) \
+$(LIB_IP_DIVIDE_INT16_OUTS) \
+$(LIB_IP_DIVIDE_INT24_OUTS) \
+$(LIB_IP_DIVIDE_INT32_OUTS) \
+$(LIB_IP_DIVIDE_UINT32_OUTS) \
+$(LIB_IP_DIVIDE_INT16_INT32_OUTS) \
+$(LIB_IP_COMPLEX_MULTIPLIER_DDS_OUTS) \
+$(LIB_IP_DDS_SIN_COS_LUT_OUTS)
+
+lib_ip: $(LIB_IP_SYNTH_OUTPUTS)
+
+.PHONY: lib_ip
diff --git a/fpga/usrp3/lib/ip/axi_fft/Makefile.inc b/fpga/usrp3/lib/ip/axi_fft/Makefile.inc
new file mode 100644
index 000000000..92eb64e64
--- /dev/null
+++ b/fpga/usrp3/lib/ip/axi_fft/Makefile.inc
@@ -0,0 +1,17 @@
+#
+# Copyright 2015 Ettus Research, a National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+include $(TOOLS_DIR)/make/viv_ip_builder.mak
+
+LIB_IP_AXI_FFT_SRCS = $(IP_BUILD_DIR)/axi_fft/axi_fft.xci
+
+LIB_IP_AXI_FFT_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_fft/, \
+axi_fft.xci.out \
+synth/axi_fft.vhd \
+) 
+
+$(LIB_IP_AXI_FFT_SRCS) $(LIB_IP_AXI_FFT_OUTS) : $(LIB_IP_DIR)/axi_fft/axi_fft.xci
+	$(call BUILD_VIVADO_IP,axi_fft,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0)
diff --git a/fpga/usrp3/lib/ip/axi_fft/axi_fft.xci b/fpga/usrp3/lib/ip/axi_fft/axi_fft.xci
new file mode 100644
index 000000000..8de860b98
--- /dev/null
+++ b/fpga/usrp3/lib/ip/axi_fft/axi_fft.xci
@@ -0,0 +1,207 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>axi_fft</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="xfft" spirit:version="9.1"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLKEN_INTF.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ARESETN_INTF.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_DATA_IN_CHANNEL_HALT_INTF.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_DATA_OUT_CHANNEL_HALT_INTF.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_FFT_OVERFLOW_INTF.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_FRAME_STARTED_INTF.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_STATUS_CHANNEL_HALT_INTF.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_TLAST_MISSING_INTF.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_TLAST_UNEXPECTED_INTF.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.HAS_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TDATA_NUM_BYTES">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TUSER_WIDTH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_STATUS.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_STATUS.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_STATUS.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_STATUS.HAS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_STATUS.HAS_TREADY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_STATUS.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_STATUS.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_STATUS.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_STATUS.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_STATUS.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_STATUS.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_STATUS.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_STATUS.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.HAS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TDATA_NUM_BYTES">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.HAS_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.TDATA_NUM_BYTES">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ARCH">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_BFLY_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_BRAM_STAGES">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CHANNELS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CMPY_TYPE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_MEM_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ACLKEN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ARESETN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_BFP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_CYCLIC_PREFIX">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_NATURAL_INPUT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_NATURAL_OUTPUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_NFFT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVFLO">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ROUNDING">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SCALING">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_XK_INDEX">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INPUT_WIDTH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXIS_DATA_TDATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXIS_DATA_TUSER_WIDTH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXIS_STATUS_TDATA_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NFFT_MAX">12</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZE_GOAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTPUT_WIDTH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REORDER_MEM_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_CONFIG_TDATA_WIDTH">24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_DATA_TDATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_THROTTLE_SCHEME">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TWIDDLE_MEM_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TWIDDLE_WIDTH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FLT_PT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_HYBRID_RAM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">axi_fft</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.aclken">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.aresetn">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.butterfly_type">use_xtremedsp_slices</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.channels">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.complex_mult_type">use_mults_performance</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cyclic_prefix_insertion">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.data_format">fixed_point</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.implementation_options">pipelined_streaming_io</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.input_width">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.memory_options_data">block_ram</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.memory_options_hybrid">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.memory_options_phase_factors">block_ram</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.memory_options_reorder">block_ram</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.number_of_stages_using_block_ram_for_data_and_phase_factors">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.output_ordering">bit_reversed_order</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ovflo">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.phase_factor_width">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rounding_modes">convergent_rounding</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.run_time_configurable_transform_length">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.scaling_options">scaled</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.target_clock_frequency">200</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.target_data_throughput">50</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.throttle_scheme">nonrealtime</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.transform_length">4096</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.xk_index">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.HAS_TLAST" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TUSER_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_STATUS.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_STATUS.HAS_TLAST" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_STATUS.HAS_TREADY" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_STATUS.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_STATUS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_STATUS.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_STATUS.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_STATUS.TUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.HAS_TLAST" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.HAS_TREADY" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.HAS_TLAST" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.HAS_TREADY" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.TUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.aresetn" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.butterfly_type" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.complex_mult_type" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.implementation_options" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.number_of_stages_using_block_ram_for_data_and_phase_factors" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.rounding_modes" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.run_time_configurable_transform_length" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.target_clock_frequency" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.transform_length" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.xk_index" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/fpga/usrp3/lib/ip/axi_hb31/Makefile.inc b/fpga/usrp3/lib/ip/axi_hb31/Makefile.inc
new file mode 100644
index 000000000..66728d202
--- /dev/null
+++ b/fpga/usrp3/lib/ip/axi_hb31/Makefile.inc
@@ -0,0 +1,16 @@
+#
+# Copyright 2016 Ettus Research, a National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+include $(TOOLS_DIR)/make/viv_ip_builder.mak
+
+LIB_IP_AXI_HB31_SRCS = $(IP_BUILD_DIR)/axi_hb31/axi_hb31.xci
+
+LIB_IP_AXI_HB31_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_hb31/, \
+axi_hb31.xci.out \
+) 
+
+$(LIB_IP_AXI_HB31_SRCS) $(LIB_IP_AXI_HB31_OUTS) : $(LIB_IP_DIR)/axi_hb31/axi_hb31.xci
+	$(call BUILD_VIVADO_IP,axi_hb31,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0)
diff --git a/fpga/usrp3/lib/ip/axi_hb31/axi_hb31.xci b/fpga/usrp3/lib/ip/axi_hb31/axi_hb31.xci
new file mode 100644
index 000000000..3af4dbaa9
--- /dev/null
+++ b/fpga/usrp3/lib/ip/axi_hb31/axi_hb31.xci
@@ -0,0 +1,307 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>axi_hb31</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fir_compiler" spirit:version="7.2"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLKEN_INTF.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ARESETN_INTF.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_S_CONFIG_TLAST_MISSING_INTF.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_S_CONFIG_TLAST_UNEXPECTED_INTF.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_S_DATA_CHANID_INCORRECT_INTF.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_S_DATA_TLAST_MISSING_INTF.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_S_DATA_TLAST_UNEXPECTED_INTF.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_S_RELOAD_TLAST_MISSING_INTF.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_S_RELOAD_TLAST_UNEXPECTED_INTF.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.HAS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TDATA_NUM_BYTES">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.HAS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.HAS_TREADY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.HAS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.TDATA_NUM_BYTES">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.HAS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.HAS_TREADY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ACCUM_OP_PATH_WIDTHS">34,34</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ACCUM_PATH_WIDTHS">34,34</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CHANNEL_PATTERN">fixed</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COEF_FILE">axi_hb31.mif</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COEF_FILE_LINES">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COEF_MEMTYPE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COEF_MEM_PACKING">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COEF_PATH_SIGN">0,0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COEF_PATH_SRC">0,0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COEF_PATH_WIDTHS">18,18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COEF_RELOAD">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COEF_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COL_CONFIG">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COL_MODE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COL_PIPE_LEN">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMPONENT_NAME">axi_hb31</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CONFIG_PACKET_SIZE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CONFIG_SYNC_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CONFIG_TDATA_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATAPATH_MEMTYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_HAS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_IP_PATH_WIDTHS">16,16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_MEMTYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_MEM_PACKING">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_PATH_PSAMP_SRC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_PATH_SIGN">0,0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_PATH_SRC">0,1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_PATH_WIDTHS">16,16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_PX_PATH_WIDTHS">16,16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_WIDTH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DECIM_RATE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ELABORATION_DIR">./</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EXT_MULT_CNFG">none</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FILTER_TYPE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FILTS_PACKED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ACLKEN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ARESETn">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_CONFIG_CHANNEL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INPUT_RATE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERP_RATE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IPBUFF_MEMTYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LATENCY">15</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEM_ARRANGEMENT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_DATA_HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_DATA_HAS_TUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_DATA_TDATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_DATA_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_CHANNELS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_FILTS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_MADDS">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_RELOAD_SLOTS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_TAPS">31</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPBUFF_MEMTYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPT_MADDS">none</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OP_PATH_PSAMP_SRC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTPUT_PATH_WIDTHS">16,16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTPUT_RATE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTPUT_WIDTH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERSAMPLING_RATE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PX_PATH_SRC">0,1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RELOAD_TDATA_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ROUND_MODE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYMMETRY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_DATA_HAS_FIFO">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_DATA_HAS_TUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_DATA_TDATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_DATA_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ZERO_PACKING_FACTOR">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BestPrecision">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Blank_Output">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Channel_Sequence">Basic</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Frequency">200</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CoefficientSource">Vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CoefficientVector">-581,  0,  1053,  -0,  -1759,  0,  2814,  -0,  -4434,  0,  7193,  -0,  -13190,  0,  41478,  65536,  41478,  0,  -13190,  -0,  7193,  0,  -4434,  -0,  2814,  0,  -1759,  -0,  1053,  0,  -581</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coefficient_Buffer_Type">Automatic</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coefficient_File">no_coe_file_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coefficient_Fractional_Bits">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coefficient_Reload">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coefficient_Sets">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coefficient_Sign">Signed</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coefficient_Structure">Inferred</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coefficient_Width">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ColumnConfig">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">axi_hb31</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_Has_TLAST">Not_Required</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_TUSER_Width">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Buffer_Type">Automatic</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Fractional_Bits">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Sign">Signed</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Width">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Decimation_Rate">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DisplayReloadOrder">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Filter_Architecture">Systolic_Multiply_Accumulate</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Filter_Selection">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Filter_Type">Interpolation</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GUI_Behaviour">Coregen</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Gen_MIF_Files">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Gen_MIF_from_COE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Gen_MIF_from_Spec">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HardwareOversamplingRate">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Has_ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Has_ARESETn">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Buffer_Type">Automatic</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inter_Column_Pipe_Length">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Interpolation_Rate">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M_DATA_Has_TREADY">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M_DATA_Has_TUSER">Not_Required</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Multi_Column_Support">Automatic</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Num_Reload_Slots">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Number_Channels">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Number_Paths">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Optimization_Goal">Area</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Optimization_List">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Optimization_Selection">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Buffer_Type">Automatic</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Rounding_Mode">Truncate_LSBs</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Width">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Passband_Max">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Passband_Min">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pattern_List">P4-0,P4-1,P4-2,P4-3,P4-4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Preference_For_Other_Storage">Automatic</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Quantization">Integer_Coefficients</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RateSpecification">Frequency_Specification</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Rate_Change_Type">Integer</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reload_File">no_coe_file_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Data_Vector">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S_CONFIG_Method">Single</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S_CONFIG_Sync_Mode">On_Vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S_DATA_Has_FIFO">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S_DATA_Has_TUSER">Not_Required</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SamplePeriod">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Sample_Frequency">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Select_Pattern">All</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Stopband_Max">1.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Stopband_Min">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Zero_Pack_Factor">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">12</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.HAS_TREADY" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.HAS_TREADY" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.HAS_TREADY" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.TUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Blank_Output" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Channel_Sequence" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Clock_Frequency" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CoefficientSource" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CoefficientVector" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Coefficient_Fractional_Bits" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Coefficient_Reload" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Coefficient_Sets" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Coefficient_Sign" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Coefficient_Structure" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Coefficient_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ColumnConfig" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DATA_Has_TLAST" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Data_Fractional_Bits" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Decimation_Rate" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Filter_Architecture" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Filter_Type" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Has_ARESETn" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Buffer_Type" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Interpolation_Rate" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M_DATA_Has_TREADY" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M_DATA_Has_TUSER" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Number_Channels" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Number_Paths" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Optimization_Goal" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Rounding_Mode" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Preference_For_Other_Storage" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Quantization" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RateSpecification" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Reset_Data_Vector" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.S_DATA_Has_TUSER" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SamplePeriod" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Sample_Frequency" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Select_Pattern" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Zero_Pack_Factor" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/fpga/usrp3/lib/ip/axi_hb47/Makefile.inc b/fpga/usrp3/lib/ip/axi_hb47/Makefile.inc
new file mode 100644
index 000000000..b5ebb427c
--- /dev/null
+++ b/fpga/usrp3/lib/ip/axi_hb47/Makefile.inc
@@ -0,0 +1,14 @@
+#
+# Copyright 2016 Ettus Research
+#
+
+include $(TOOLS_DIR)/make/viv_ip_builder.mak
+
+LIB_IP_AXI_HB47_SRCS = $(IP_BUILD_DIR)/axi_hb47/axi_hb47.xci
+
+LIB_IP_AXI_HB47_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_hb47/, \
+axi_hb47.xci.out \
+) 
+
+$(LIB_IP_AXI_HB47_SRCS) $(LIB_IP_AXI_HB47_OUTS) : $(LIB_IP_DIR)/axi_hb47/axi_hb47.xci
+	$(call BUILD_VIVADO_IP,axi_hb47,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0)
diff --git a/fpga/usrp3/lib/ip/axi_hb47/axi_hb47.xci b/fpga/usrp3/lib/ip/axi_hb47/axi_hb47.xci
new file mode 100644
index 000000000..749a3f952
--- /dev/null
+++ b/fpga/usrp3/lib/ip/axi_hb47/axi_hb47.xci
@@ -0,0 +1,297 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>axi_hb47</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fir_compiler" spirit:version="7.2"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLKEN_INTF.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ARESETN_INTF.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_S_CONFIG_TLAST_MISSING_INTF.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_S_CONFIG_TLAST_UNEXPECTED_INTF.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_S_DATA_CHANID_INCORRECT_INTF.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_S_DATA_TLAST_MISSING_INTF.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_S_DATA_TLAST_UNEXPECTED_INTF.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_S_RELOAD_TLAST_MISSING_INTF.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_S_RELOAD_TLAST_UNEXPECTED_INTF.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.HAS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TDATA_NUM_BYTES">6</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COEF_FILE">axi_hb47.mif</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COEF_PATH_SIGN">0,0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COEF_PATH_SRC">0,0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COEF_RELOAD">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COL_CONFIG">6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COL_MODE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COL_PIPE_LEN">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMPONENT_NAME">axi_hb47</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CONFIG_PACKET_SIZE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CONFIG_SYNC_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CONFIG_TDATA_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATAPATH_MEMTYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_HAS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_IP_PATH_WIDTHS">24,24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_MEMTYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_MEM_PACKING">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_PATH_PSAMP_SRC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_PATH_SIGN">0,0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_PATH_WIDTHS">24,24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_PX_PATH_WIDTHS">24,24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_WIDTH">24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DECIM_RATE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ELABORATION_DIR">./</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EXT_MULT_CNFG">none</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FILTER_TYPE">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FILTS_PACKED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ACLKEN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ARESETn">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_CONFIG_CHANNEL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INPUT_RATE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERP_RATE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IPBUFF_MEMTYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LATENCY">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEM_ARRANGEMENT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_DATA_HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_DATA_HAS_TUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_DATA_TDATA_WIDTH">48</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_DATA_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_CHANNELS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_FILTS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_MADDS">6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_RELOAD_SLOTS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_TAPS">47</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPBUFF_MEMTYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPT_MADDS">none</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OP_PATH_PSAMP_SRC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTPUT_PATH_WIDTHS">24,24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTPUT_RATE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTPUT_WIDTH">24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERSAMPLING_RATE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PX_PATH_SRC">0,1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RELOAD_TDATA_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ROUND_MODE">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYMMETRY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_DATA_HAS_FIFO">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_DATA_HAS_TUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_DATA_TDATA_WIDTH">48</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_DATA_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ZERO_PACKING_FACTOR">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BestPrecision">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Blank_Output">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Channel_Sequence">Basic</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Frequency">200</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CoefficientSource">Vector</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coefficient_File">no_coe_file_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coefficient_Fractional_Bits">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coefficient_Reload">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coefficient_Sets">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coefficient_Sign">Signed</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coefficient_Structure">Half_Band</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coefficient_Width">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ColumnConfig">6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">axi_hb47</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_Has_TLAST">Not_Required</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_TUSER_Width">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Buffer_Type">Automatic</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Fractional_Bits">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Sign">Signed</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Width">24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Decimation_Rate">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DisplayReloadOrder">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Filter_Architecture">Systolic_Multiply_Accumulate</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Filter_Selection">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Filter_Type">Interpolation</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GUI_Behaviour">Coregen</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Gen_MIF_Files">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Gen_MIF_from_COE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Gen_MIF_from_Spec">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HardwareOversamplingRate">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Has_ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Has_ARESETn">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Buffer_Type">Automatic</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inter_Column_Pipe_Length">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Interpolation_Rate">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M_DATA_Has_TREADY">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M_DATA_Has_TUSER">Not_Required</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Multi_Column_Support">Automatic</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Num_Reload_Slots">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Number_Channels">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Number_Paths">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Optimization_Goal">Area</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Optimization_List">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Optimization_Selection">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Buffer_Type">Automatic</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Rounding_Mode">Non_Symmetric_Rounding_Up</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Width">24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Passband_Max">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Passband_Min">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pattern_List">P4-0,P4-1,P4-2,P4-3,P4-4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Preference_For_Other_Storage">Automatic</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Quantization">Integer_Coefficients</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RateSpecification">Frequency_Specification</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Rate_Change_Type">Integer</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reload_File">no_coe_file_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Data_Vector">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S_CONFIG_Method">Single</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S_CONFIG_Sync_Mode">On_Vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S_DATA_Has_FIFO">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S_DATA_Has_TUSER">Not_Required</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SamplePeriod">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Sample_Frequency">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Select_Pattern">All</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Stopband_Max">1.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Stopband_Min">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Zero_Pack_Factor">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">12</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
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+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.HAS_TREADY" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.HAS_TREADY" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.HAS_TREADY" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.TUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Blank_Output" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Clock_Frequency" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CoefficientVector" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Coefficient_Fractional_Bits" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Coefficient_Sets" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Coefficient_Sign" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Coefficient_Structure" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Coefficient_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ColumnConfig" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Data_Fractional_Bits" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Decimation_Rate" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Filter_Architecture" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Filter_Type" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Has_ACLKEN" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Has_ARESETn" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Interpolation_Rate" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M_DATA_Has_TREADY" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Number_Channels" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Number_Paths" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Rounding_Mode" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Quantization" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RateSpecification" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Reset_Data_Vector" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Sample_Frequency" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Zero_Pack_Factor" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/fpga/usrp3/lib/ip/complex_multiplier/Makefile.inc b/fpga/usrp3/lib/ip/complex_multiplier/Makefile.inc
new file mode 100644
index 000000000..502982b84
--- /dev/null
+++ b/fpga/usrp3/lib/ip/complex_multiplier/Makefile.inc
@@ -0,0 +1,18 @@
+#
+# Copyright 2015 Ettus Research
+# Copyright 2016 Ettus Research, a National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+include $(TOOLS_DIR)/make/viv_ip_builder.mak
+
+LIB_IP_COMPLEX_MULTIPLIER_SRCS = $(IP_BUILD_DIR)/complex_multiplier/complex_multiplier.xci
+
+LIB_IP_COMPLEX_MULTIPLIER_OUTS = $(addprefix $(IP_BUILD_DIR)/complex_multiplier/, \
+complex_multiplier.xci.out \
+synth/complex_multiplier.vhd \
+) 
+
+$(LIB_IP_COMPLEX_MULTIPLIER_SRCS) $(LIB_IP_COMPLEX_MULTIPLIER_OUTS) : $(LIB_IP_DIR)/complex_multiplier/complex_multiplier.xci
+	$(call BUILD_VIVADO_IP,complex_multiplier,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0)
diff --git a/fpga/usrp3/lib/ip/complex_multiplier/complex_multiplier.xci b/fpga/usrp3/lib/ip/complex_multiplier/complex_multiplier.xci
new file mode 100644
index 000000000..48966fa5a
--- /dev/null
+++ b/fpga/usrp3/lib/ip/complex_multiplier/complex_multiplier.xci
@@ -0,0 +1,184 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>complex_multiplier</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="cmpy" spirit:version="6.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLKEN_INTF.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.FREQ_HZ">10000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ARESETN_INTF.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDATA_NUM_BYTES">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_A.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_A.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_A.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_A.HAS_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_A.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_A.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_A.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_A.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_A.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_A.TDATA_NUM_BYTES">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_A.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_A.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_A.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_B.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_B.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_B.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_B.HAS_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_B.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_B.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_B.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_B.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_B.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_B.TDATA_NUM_BYTES">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_B.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_B.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_B.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CTRL.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CTRL.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CTRL.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CTRL.HAS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CTRL.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CTRL.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CTRL.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CTRL.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CTRL.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CTRL.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CTRL.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CTRL.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CTRL.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_A_WIDTH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_B_WIDTH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ACLKEN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ARESETN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_A_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_A_TUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_B_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_B_TUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_CTRL_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_CTRL_TUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LATENCY">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MULT_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXIS_DOUT_TDATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXIS_DOUT_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZE_GOAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUT_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_A_TDATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_A_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_B_TDATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_B_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_CTRL_TDATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_CTRL_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_THROTTLE_SCHEME">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TLAST_RESOLUTION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VERBOSITY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICE">xc7k410t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.HAS_NEGATE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ROUND">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SINGLE_OUTPUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.USE_DSP_CASCADES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.APortWidth">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARESETN">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ATUSERWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BPortWidth">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BTUSERWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CTRLTUSERWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">complex_multiplier</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FlowControl">Blocking</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HasATLAST">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HasATUSER">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HasBTLAST">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HasBTUSER">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HasCTRLTLAST">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HasCTRLTUSER">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LatencyConfig">Automatic</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MinimumLatency">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MultType">Use_Mults</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OptimizeGoal">Performance</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OutTLASTBehv">Pass_A_TLAST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OutputWidth">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RoundMode">Random_Rounding</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">17</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TLAST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_A.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_A.HAS_TLAST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_A.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_A.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_A.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_A.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_B.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_B.HAS_TLAST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_B.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_B.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_B.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_B.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CTRL.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CTRL.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CTRL.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CTRL.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ARESETN" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FlowControl" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.HasATLAST" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.HasBTLAST" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MinimumLatency" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.OptimizeGoal" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.OutTLASTBehv" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.OutputWidth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RoundMode" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/fpga/usrp3/lib/ip/complex_multiplier_dds/Makefile.inc b/fpga/usrp3/lib/ip/complex_multiplier_dds/Makefile.inc
new file mode 100644
index 000000000..e0d0ba0c5
--- /dev/null
+++ b/fpga/usrp3/lib/ip/complex_multiplier_dds/Makefile.inc
@@ -0,0 +1,17 @@
+#
+# Copyright 2018 Ettus Research, a National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+include $(TOOLS_DIR)/make/viv_ip_builder.mak
+
+LIB_IP_COMPLEX_MULTIPLIER_DDS_SRCS = $(IP_BUILD_DIR)/complex_multiplier_dds/complex_multiplier_dds.xci
+
+LIB_IP_COMPLEX_MULTIPLIER_DDS_OUTS = $(addprefix $(IP_BUILD_DIR)/complex_multiplier_dds/, \
+complex_multiplier_dds.xci.out \
+synth/complex_multiplier_dds.vhd \
+) 
+
+$(LIB_IP_COMPLEX_MULTIPLIER_DDS_SRCS) $(LIB_IP_COMPLEX_MULTIPLIER_DDS_OUTS) : $(LIB_IP_DIR)/complex_multiplier_dds/complex_multiplier_dds.xci
+	$(call BUILD_VIVADO_IP,complex_multiplier_dds,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0)
diff --git a/fpga/usrp3/lib/ip/complex_multiplier_dds/complex_multiplier_dds.xci b/fpga/usrp3/lib/ip/complex_multiplier_dds/complex_multiplier_dds.xci
new file mode 100644
index 000000000..13a739a59
--- /dev/null
+++ b/fpga/usrp3/lib/ip/complex_multiplier_dds/complex_multiplier_dds.xci
@@ -0,0 +1,188 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>complex_multiplier_dds</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="cmpy" spirit:version="6.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLKEN_INTF.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.FREQ_HZ">10000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ARESETN_INTF.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDATA_NUM_BYTES">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_A.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_A.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_A.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_A.HAS_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_A.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_A.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_A.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_A.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_A.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_A.TDATA_NUM_BYTES">6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_A.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_A.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_A.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_B.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_B.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_B.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_B.HAS_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_B.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_B.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_B.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_B.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_B.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_B.TDATA_NUM_BYTES">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_B.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_B.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_B.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CTRL.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CTRL.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CTRL.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CTRL.HAS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CTRL.HAS_TREADY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CTRL.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CTRL.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CTRL.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CTRL.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CTRL.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CTRL.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CTRL.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CTRL.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_A_WIDTH">21</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_B_WIDTH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ACLKEN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ARESETN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_A_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_A_TUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_B_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_B_TUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_CTRL_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_CTRL_TUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LATENCY">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MULT_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXIS_DOUT_TDATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXIS_DOUT_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZE_GOAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUT_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_A_TDATA_WIDTH">48</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_A_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_B_TDATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_B_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_CTRL_TDATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_CTRL_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_THROTTLE_SCHEME">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TLAST_RESOLUTION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VERBOSITY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICE">xc7k410t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.HAS_NEGATE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ROUND">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SINGLE_OUTPUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.USE_DSP_CASCADES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.APortWidth">21</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARESETN">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ATUSERWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BPortWidth">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BTUSERWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CTRLTUSERWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">complex_multiplier_dds</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FlowControl">Blocking</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HasATLAST">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HasATUSER">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HasBTLAST">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HasBTUSER">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HasCTRLTLAST">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HasCTRLTUSER">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LatencyConfig">Automatic</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MinimumLatency">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MultType">Use_Mults</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OptimizeGoal">Performance</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OutTLASTBehv">Pass_A_TLAST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OutputWidth">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RoundMode">Truncate</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">17</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TLAST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_A.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_A.HAS_TLAST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_A.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_A.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_A.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_A.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_B.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_B.HAS_TLAST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_B.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_B.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_B.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_B.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CTRL.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CTRL.HAS_TREADY" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CTRL.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CTRL.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CTRL.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CTRL.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.APortWidth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ARESETN" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FlowControl" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.HasATLAST" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.HasBTLAST" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.LatencyConfig" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MinimumLatency" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.OptimizeGoal" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.OutTLASTBehv" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.OutputWidth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RoundMode" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/fpga/usrp3/lib/ip/complex_to_magphase/Makefile.inc b/fpga/usrp3/lib/ip/complex_to_magphase/Makefile.inc
new file mode 100644
index 000000000..0223f8be8
--- /dev/null
+++ b/fpga/usrp3/lib/ip/complex_to_magphase/Makefile.inc
@@ -0,0 +1,18 @@
+#
+# Copyright 2015 Ettus Research
+# Copyright 2016 Ettus Research, a National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+include $(TOOLS_DIR)/make/viv_ip_builder.mak
+
+LIB_IP_COMPLEX_TO_MAGPHASE_SRCS = $(IP_BUILD_DIR)/complex_to_magphase/complex_to_magphase.xci
+
+LIB_IP_COMPLEX_TO_MAGPHASE_OUTS = $(addprefix $(IP_BUILD_DIR)/complex_to_magphase/, \
+complex_to_magphase.xci.out \
+synth/complex_to_magphase.vhd \
+) 
+
+$(LIB_IP_COMPLEX_TO_MAGPHASE_SRCS) $(LIB_IP_COMPLEX_TO_MAGPHASE_OUTS) : $(LIB_IP_DIR)/complex_to_magphase/complex_to_magphase.xci
+	$(call BUILD_VIVADO_IP,complex_to_magphase,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0)
diff --git a/fpga/usrp3/lib/ip/complex_to_magphase/complex_to_magphase.xci b/fpga/usrp3/lib/ip/complex_to_magphase/complex_to_magphase.xci
new file mode 100644
index 000000000..825bf67f8
--- /dev/null
+++ b/fpga/usrp3/lib/ip/complex_to_magphase/complex_to_magphase.xci
@@ -0,0 +1,169 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>complex_to_magphase</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="cordic" spirit:version="6.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLKEN_INTF.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.FREQ_HZ">1000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ARESETN_INTF.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDATA_NUM_BYTES">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.HAS_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.TDATA_NUM_BYTES">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TREADY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ARCHITECTURE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COARSE_ROTATE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CORDIC_FUNCTION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_FORMAT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ACLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ACLKEN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ARESETN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_CARTESIAN">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_PHASE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_PHASE_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_PHASE_TUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INPUT_WIDTH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ITERATIONS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXIS_DOUT_TDATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXIS_DOUT_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTPUT_WIDTH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PHASE_FORMAT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PIPELINE_MODE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRECISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ROUND_MODE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SCALE_COMP">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_CARTESIAN_TDATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_CARTESIAN_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_PHASE_TDATA_WIDTH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_PHASE_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_THROTTLE_SCHEME">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TLAST_RESOLUTION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARESETN">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Architectural_Configuration">Parallel</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coarse_Rotation">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Compensation_Scaling">Embedded_Multiplier</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">complex_to_magphase</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Format">SignedFraction</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Functional_Selection">Translate</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Width">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Iterations">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Width">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phase_Format">Scaled_Radians</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pipelining_Mode">Maximum</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Precision">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Round_Mode">Round_Pos_Neg_Inf</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cartesian_has_tlast">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cartesian_has_tuser">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cartesian_tuser_width">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.flow_control">Blocking</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.optimize_goal">Performance</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.out_tlast_behv">Pass_Cartesian_TLAST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.out_tready">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.phase_has_tlast">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.phase_has_tuser">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.phase_tuser_width">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
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+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Compensation_Scaling" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Functional_Selection" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Phase_Format" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Round_Mode" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.cartesian_has_tlast" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.flow_control" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.out_tlast_behv" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.out_tready" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/fpga/usrp3/lib/ip/complex_to_magphase_int16_int24/Makefile.inc b/fpga/usrp3/lib/ip/complex_to_magphase_int16_int24/Makefile.inc
new file mode 100644
index 000000000..a87103991
--- /dev/null
+++ b/fpga/usrp3/lib/ip/complex_to_magphase_int16_int24/Makefile.inc
@@ -0,0 +1,15 @@
+#
+# Copyright 2015 Ettus Research
+#
+
+include $(TOOLS_DIR)/make/viv_ip_builder.mak
+
+LIB_IP_COMPLEX_TO_MAGPHASE_INT16_INT24_SRCS = $(IP_BUILD_DIR)/complex_to_magphase_int16_int24/complex_to_magphase_int16_int24.xci
+
+LIB_IP_COMPLEX_TO_MAGPHASE_INT16_INT24_OUTS = $(addprefix $(IP_BUILD_DIR)/complex_to_magphase_int16_int24/, \
+complex_to_magphase_int16_int24.xci.out \
+synth/complex_to_magphase_int16_int24.vhd \
+) 
+
+$(LIB_IP_COMPLEX_TO_MAGPHASE_INT16_INT24_SRCS) $(LIB_IP_COMPLEX_TO_MAGPHASE_INT16_INT24_OUTS) : $(LIB_IP_DIR)/complex_to_magphase_int16_int24/complex_to_magphase_int16_int24.xci
+	$(call BUILD_VIVADO_IP,complex_to_magphase_int16_int24,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0)
diff --git a/fpga/usrp3/lib/ip/complex_to_magphase_int16_int24/complex_to_magphase_int16_int24.xci b/fpga/usrp3/lib/ip/complex_to_magphase_int16_int24/complex_to_magphase_int16_int24.xci
new file mode 100644
index 000000000..fb19e47d3
--- /dev/null
+++ b/fpga/usrp3/lib/ip/complex_to_magphase_int16_int24/complex_to_magphase_int16_int24.xci
@@ -0,0 +1,171 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>complex_to_magphase_int16_int24</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="cordic" spirit:version="6.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLKEN_INTF.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.FREQ_HZ">1000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ARESETN_INTF.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDATA_NUM_BYTES">6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.HAS_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.TDATA_NUM_BYTES">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TREADY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ARCHITECTURE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COARSE_ROTATE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CORDIC_FUNCTION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_FORMAT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ACLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ACLKEN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ARESETN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_CARTESIAN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_CARTESIAN_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_CARTESIAN_TUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_PHASE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_PHASE_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_PHASE_TUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INPUT_WIDTH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ITERATIONS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXIS_DOUT_TDATA_WIDTH">48</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXIS_DOUT_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTPUT_WIDTH">24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PHASE_FORMAT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PIPELINE_MODE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRECISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ROUND_MODE">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SCALE_COMP">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_CARTESIAN_TDATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_CARTESIAN_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_PHASE_TDATA_WIDTH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_PHASE_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_THROTTLE_SCHEME">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TLAST_RESOLUTION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARESETN">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Architectural_Configuration">Parallel</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coarse_Rotation">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Compensation_Scaling">Embedded_Multiplier</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">complex_to_magphase_int16_int24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Format">SignedFraction</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Functional_Selection">Translate</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Width">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Iterations">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Width">24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phase_Format">Scaled_Radians</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pipelining_Mode">Optimal</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Precision">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Round_Mode">Nearest_Even</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cartesian_has_tlast">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cartesian_has_tuser">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cartesian_tuser_width">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.flow_control">Blocking</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.optimize_goal">Performance</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.out_tlast_behv">Pass_Cartesian_TLAST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.out_tready">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.phase_has_tlast">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.phase_has_tuser">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.phase_tuser_width">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">15</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TLAST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.HAS_TLAST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TREADY" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ARESETN" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Compensation_Scaling" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Functional_Selection" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Phase_Format" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Pipelining_Mode" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Round_Mode" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.cartesian_has_tlast" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.flow_control" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.out_tlast_behv" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.out_tready" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/fpga/usrp3/lib/ip/complex_to_magphase_int32/Makefile.inc b/fpga/usrp3/lib/ip/complex_to_magphase_int32/Makefile.inc
new file mode 100644
index 000000000..359cd0cac
--- /dev/null
+++ b/fpga/usrp3/lib/ip/complex_to_magphase_int32/Makefile.inc
@@ -0,0 +1,15 @@
+#
+# Copyright 2015 Ettus Research
+#
+
+include $(TOOLS_DIR)/make/viv_ip_builder.mak
+
+LIB_IP_COMPLEX_TO_MAGPHASE_INT32_SRCS = $(IP_BUILD_DIR)/complex_to_magphase_int32/complex_to_magphase_int32.xci
+
+LIB_IP_COMPLEX_TO_MAGPHASE_INT32_OUTS = $(addprefix $(IP_BUILD_DIR)/complex_to_magphase_int32/, \
+complex_to_magphase_int32.xci.out \
+synth/complex_to_magphase_int32.vhd \
+) 
+
+$(LIB_IP_COMPLEX_TO_MAGPHASE_INT32_SRCS) $(LIB_IP_COMPLEX_TO_MAGPHASE_INT32_OUTS) : $(LIB_IP_DIR)/complex_to_magphase_int32/complex_to_magphase_int32.xci
+	$(call BUILD_VIVADO_IP,complex_to_magphase_int32,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0)
diff --git a/fpga/usrp3/lib/ip/complex_to_magphase_int32/complex_to_magphase_int32.xci b/fpga/usrp3/lib/ip/complex_to_magphase_int32/complex_to_magphase_int32.xci
new file mode 100644
index 000000000..a9c96316b
--- /dev/null
+++ b/fpga/usrp3/lib/ip/complex_to_magphase_int32/complex_to_magphase_int32.xci
@@ -0,0 +1,171 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>complex_to_magphase_int32</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="cordic" spirit:version="6.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLKEN_INTF.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.FREQ_HZ">1000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ARESETN_INTF.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDATA_NUM_BYTES">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.HAS_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.TDATA_NUM_BYTES">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TREADY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ARCHITECTURE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COARSE_ROTATE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CORDIC_FUNCTION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_FORMAT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ACLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ACLKEN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ARESETN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_CARTESIAN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_CARTESIAN_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_CARTESIAN_TUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_PHASE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_PHASE_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_PHASE_TUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INPUT_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ITERATIONS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXIS_DOUT_TDATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXIS_DOUT_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTPUT_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PHASE_FORMAT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PIPELINE_MODE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRECISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ROUND_MODE">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SCALE_COMP">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_CARTESIAN_TDATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_CARTESIAN_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_PHASE_TDATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_PHASE_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_THROTTLE_SCHEME">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TLAST_RESOLUTION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARESETN">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Architectural_Configuration">Parallel</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coarse_Rotation">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Compensation_Scaling">Embedded_Multiplier</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">complex_to_magphase_int32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Format">SignedFraction</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Functional_Selection">Translate</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Width">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Iterations">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Width">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phase_Format">Scaled_Radians</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pipelining_Mode">Maximum</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Precision">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Round_Mode">Nearest_Even</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cartesian_has_tlast">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cartesian_has_tuser">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cartesian_tuser_width">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.flow_control">Blocking</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.optimize_goal">Performance</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.out_tlast_behv">Pass_Cartesian_TLAST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.out_tready">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.phase_has_tlast">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.phase_has_tuser">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.phase_tuser_width">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">15</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TLAST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.HAS_TLAST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TREADY" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ARESETN" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Compensation_Scaling" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Functional_Selection" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Phase_Format" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Round_Mode" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.cartesian_has_tlast" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.flow_control" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.out_tlast_behv" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.out_tready" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/fpga/usrp3/lib/ip/cordic_rotate_int24/Makefile.inc b/fpga/usrp3/lib/ip/cordic_rotate_int24/Makefile.inc
new file mode 100644
index 000000000..a825448fa
--- /dev/null
+++ b/fpga/usrp3/lib/ip/cordic_rotate_int24/Makefile.inc
@@ -0,0 +1,15 @@
+#
+# Copyright 2015 Ettus Research
+#
+
+include $(TOOLS_DIR)/make/viv_ip_builder.mak
+
+LIB_IP_CORDIC_ROTATE_INT24_SRCS = $(IP_BUILD_DIR)/cordic_rotate_int24/cordic_rotate_int24.xci
+
+LIB_IP_CORDIC_ROTATE_INT24_OUTS = $(addprefix $(IP_BUILD_DIR)/cordic_rotate_int24/, \
+cordic_rotate_int24.xci.out \
+synth/cordic_rotate_int24.vhd \
+) 
+
+$(LIB_IP_CORDIC_ROTATE_INT24_SRCS) $(LIB_IP_CORDIC_ROTATE_INT24_OUTS) : $(LIB_IP_DIR)/cordic_rotate_int24/cordic_rotate_int24.xci
+	$(call BUILD_VIVADO_IP,cordic_rotate_int24,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0)
diff --git a/fpga/usrp3/lib/ip/cordic_rotate_int24/cordic_rotate_int24.xci b/fpga/usrp3/lib/ip/cordic_rotate_int24/cordic_rotate_int24.xci
new file mode 100644
index 000000000..2e1f47fff
--- /dev/null
+++ b/fpga/usrp3/lib/ip/cordic_rotate_int24/cordic_rotate_int24.xci
@@ -0,0 +1,171 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>cordic_rotate_int24</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="cordic" spirit:version="6.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLKEN_INTF.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.FREQ_HZ">1000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ARESETN_INTF.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDATA_NUM_BYTES">6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.HAS_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.TDATA_NUM_BYTES">6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TDATA_NUM_BYTES">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ARCHITECTURE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COARSE_ROTATE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CORDIC_FUNCTION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_FORMAT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ACLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ACLKEN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ARESETN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_CARTESIAN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_CARTESIAN_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_CARTESIAN_TUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_PHASE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_PHASE_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_PHASE_TUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INPUT_WIDTH">24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ITERATIONS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXIS_DOUT_TDATA_WIDTH">48</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXIS_DOUT_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTPUT_WIDTH">24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PHASE_FORMAT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PIPELINE_MODE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRECISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ROUND_MODE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SCALE_COMP">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_CARTESIAN_TDATA_WIDTH">48</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_CARTESIAN_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_PHASE_TDATA_WIDTH">24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_PHASE_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_THROTTLE_SCHEME">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TLAST_RESOLUTION">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARESETN">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Architectural_Configuration">Parallel</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coarse_Rotation">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Compensation_Scaling">Embedded_Multiplier</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">cordic_rotate_int24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Format">SignedFraction</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Functional_Selection">Rotate</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Width">24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Iterations">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Width">24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phase_Format">Scaled_Radians</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pipelining_Mode">Maximum</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Precision">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Round_Mode">Round_Pos_Neg_Inf</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cartesian_has_tlast">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cartesian_has_tuser">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cartesian_tuser_width">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.flow_control">Blocking</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.optimize_goal">Performance</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.out_tlast_behv">OR_all_TLASTs</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.out_tready">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.phase_has_tlast">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.phase_has_tuser">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.phase_tuser_width">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">15</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TLAST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.HAS_TLAST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TLAST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ARESETN" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Compensation_Scaling" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Phase_Format" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Round_Mode" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.cartesian_has_tlast" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.flow_control" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.out_tlast_behv" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.out_tready" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.phase_has_tlast" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/fpga/usrp3/lib/ip/cordic_rotate_int24_int16/Makefile.inc b/fpga/usrp3/lib/ip/cordic_rotate_int24_int16/Makefile.inc
new file mode 100644
index 000000000..ae87990e3
--- /dev/null
+++ b/fpga/usrp3/lib/ip/cordic_rotate_int24_int16/Makefile.inc
@@ -0,0 +1,15 @@
+#
+# Copyright 2015 Ettus Research
+#
+
+include $(TOOLS_DIR)/make/viv_ip_builder.mak
+
+LIB_IP_CORDIC_ROTATE_INT24_INT16_SRCS = $(IP_BUILD_DIR)/cordic_rotate_int24_int16/cordic_rotate_int24_int16.xci
+
+LIB_IP_CORDIC_ROTATE_INT24_INT16_OUTS = $(addprefix $(IP_BUILD_DIR)/cordic_rotate_int24_int16/, \
+cordic_rotate_int24_int16.xci.out \
+synth/cordic_rotate_int24_int16.vhd \
+) 
+
+$(LIB_IP_CORDIC_ROTATE_INT24_INT16_SRCS) $(LIB_IP_CORDIC_ROTATE_INT24_INT16_OUTS) : $(LIB_IP_DIR)/cordic_rotate_int24_int16/cordic_rotate_int24_int16.xci
+	$(call BUILD_VIVADO_IP,cordic_rotate_int24_int16,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0)
diff --git a/fpga/usrp3/lib/ip/cordic_rotate_int24_int16/cordic_rotate_int24_int16.xci b/fpga/usrp3/lib/ip/cordic_rotate_int24_int16/cordic_rotate_int24_int16.xci
new file mode 100644
index 000000000..46d5fee55
--- /dev/null
+++ b/fpga/usrp3/lib/ip/cordic_rotate_int24_int16/cordic_rotate_int24_int16.xci
@@ -0,0 +1,170 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>cordic_rotate_int24_int16</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="cordic" spirit:version="6.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLKEN_INTF.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.FREQ_HZ">1000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ARESETN_INTF.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDATA_NUM_BYTES">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.HAS_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.TDATA_NUM_BYTES">6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TDATA_NUM_BYTES">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ARCHITECTURE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COARSE_ROTATE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CORDIC_FUNCTION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_FORMAT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ACLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ACLKEN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ARESETN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_CARTESIAN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_CARTESIAN_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_CARTESIAN_TUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_PHASE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_PHASE_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_PHASE_TUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INPUT_WIDTH">24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ITERATIONS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXIS_DOUT_TDATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXIS_DOUT_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTPUT_WIDTH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PHASE_FORMAT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PIPELINE_MODE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRECISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ROUND_MODE">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SCALE_COMP">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_CARTESIAN_TDATA_WIDTH">48</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_CARTESIAN_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_PHASE_TDATA_WIDTH">24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_PHASE_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_THROTTLE_SCHEME">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TLAST_RESOLUTION">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARESETN">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Architectural_Configuration">Parallel</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coarse_Rotation">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Compensation_Scaling">Embedded_Multiplier</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">cordic_rotate_int24_int16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Format">SignedFraction</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Functional_Selection">Rotate</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Width">24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Iterations">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Width">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phase_Format">Scaled_Radians</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pipelining_Mode">Maximum</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Precision">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Round_Mode">Nearest_Even</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cartesian_has_tlast">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cartesian_has_tuser">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cartesian_tuser_width">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.flow_control">Blocking</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.optimize_goal">Performance</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.out_tlast_behv">OR_all_TLASTs</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.out_tready">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.phase_has_tlast">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.phase_has_tuser">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.phase_tuser_width">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">15</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TLAST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.HAS_TLAST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TLAST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ARESETN" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Compensation_Scaling" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Phase_Format" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Round_Mode" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.cartesian_has_tlast" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.flow_control" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.out_tlast_behv" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.out_tready" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.phase_has_tlast" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/fpga/usrp3/lib/ip/cordic_rotator/Makefile.inc b/fpga/usrp3/lib/ip/cordic_rotator/Makefile.inc
new file mode 100644
index 000000000..b202818ed
--- /dev/null
+++ b/fpga/usrp3/lib/ip/cordic_rotator/Makefile.inc
@@ -0,0 +1,17 @@
+#
+# Copyright 2015 Ettus Research, a National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+include $(TOOLS_DIR)/make/viv_ip_builder.mak
+
+LIB_IP_CORDIC_ROTATOR_SRCS = $(IP_BUILD_DIR)/cordic_rotator/cordic_rotator.xci
+
+LIB_IP_CORDIC_ROTATOR_OUTS = $(addprefix $(IP_BUILD_DIR)/cordic_rotator/, \
+cordic_rotator.xci.out \
+synth/cordic_rotator.vhd \
+) 
+
+$(LIB_IP_CORDIC_ROTATOR_SRCS) $(LIB_IP_CORDIC_ROTATOR_OUTS) : $(LIB_IP_DIR)/cordic_rotator/cordic_rotator.xci
+	$(call BUILD_VIVADO_IP,cordic_rotator,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0)
diff --git a/fpga/usrp3/lib/ip/cordic_rotator/cordic_rotator.xci b/fpga/usrp3/lib/ip/cordic_rotator/cordic_rotator.xci
new file mode 100644
index 000000000..63b7aafb3
--- /dev/null
+++ b/fpga/usrp3/lib/ip/cordic_rotator/cordic_rotator.xci
@@ -0,0 +1,166 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>cordic_rotator</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="cordic" spirit:version="6.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLKEN_INTF.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.FREQ_HZ">1000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ARESETN_INTF.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDATA_NUM_BYTES">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.HAS_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.TDATA_NUM_BYTES">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TDATA_NUM_BYTES">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ARCHITECTURE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COARSE_ROTATE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CORDIC_FUNCTION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_FORMAT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ACLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ACLKEN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ARESETN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_CARTESIAN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_CARTESIAN_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_CARTESIAN_TUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_PHASE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_PHASE_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_PHASE_TUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INPUT_WIDTH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ITERATIONS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXIS_DOUT_TDATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXIS_DOUT_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTPUT_WIDTH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PHASE_FORMAT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PIPELINE_MODE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRECISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ROUND_MODE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SCALE_COMP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_CARTESIAN_TDATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_CARTESIAN_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_PHASE_TDATA_WIDTH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_PHASE_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_THROTTLE_SCHEME">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TLAST_RESOLUTION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARESETN">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Architectural_Configuration">Parallel</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coarse_Rotation">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Compensation_Scaling">No_Scale_Compensation</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">cordic_rotator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Format">SignedFraction</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Functional_Selection">Rotate</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Width">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Iterations">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Width">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phase_Format">Scaled_Radians</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pipelining_Mode">Maximum</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Precision">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Round_Mode">Round_Pos_Neg_Inf</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cartesian_has_tlast">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cartesian_has_tuser">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cartesian_tuser_width">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.flow_control">Blocking</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.optimize_goal">Performance</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.out_tlast_behv">Pass_Cartesian_TLAST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.out_tready">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.phase_has_tlast">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.phase_has_tuser">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.phase_tuser_width">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">15</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TLAST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.HAS_TLAST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ARESETN" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Phase_Format" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Round_Mode" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.cartesian_has_tlast" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.flow_control" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.out_tlast_behv" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.out_tready" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/fpga/usrp3/lib/ip/cordic_rotator24/Makefile.inc b/fpga/usrp3/lib/ip/cordic_rotator24/Makefile.inc
new file mode 100644
index 000000000..822d97b87
--- /dev/null
+++ b/fpga/usrp3/lib/ip/cordic_rotator24/Makefile.inc
@@ -0,0 +1,15 @@
+#
+# Copyright 2016 Ettus Research
+#
+
+include $(TOOLS_DIR)/make/viv_ip_builder.mak
+
+LIB_IP_CORDIC_ROTATOR24_SRCS = $(IP_BUILD_DIR)/cordic_rotator24/cordic_rotator24.xci
+
+LIB_IP_CORDIC_ROTATOR24_OUTS = $(addprefix $(IP_BUILD_DIR)/cordic_rotator24/, \
+cordic_rotator24.xci.out \
+synth/cordic_rotator24.vhd \
+) 
+
+$(LIB_IP_CORDIC_ROTATOR24_SRCS) $(LIB_IP_CORDIC_ROTATOR24_OUTS) : $(LIB_IP_DIR)/cordic_rotator24/cordic_rotator24.xci
+	$(call BUILD_VIVADO_IP,cordic_rotator24,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0)
diff --git a/fpga/usrp3/lib/ip/cordic_rotator24/cordic_rotator24.xci b/fpga/usrp3/lib/ip/cordic_rotator24/cordic_rotator24.xci
new file mode 100644
index 000000000..970220f6e
--- /dev/null
+++ b/fpga/usrp3/lib/ip/cordic_rotator24/cordic_rotator24.xci
@@ -0,0 +1,169 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>cordic_rotator24</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="cordic" spirit:version="6.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLKEN_INTF.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.FREQ_HZ">1000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ARESETN_INTF.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDATA_NUM_BYTES">6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.HAS_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.TDATA_NUM_BYTES">6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TDATA_NUM_BYTES">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ARCHITECTURE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COARSE_ROTATE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CORDIC_FUNCTION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_FORMAT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ACLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ACLKEN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ARESETN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_CARTESIAN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_CARTESIAN_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_CARTESIAN_TUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_PHASE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_PHASE_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_PHASE_TUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INPUT_WIDTH">24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ITERATIONS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXIS_DOUT_TDATA_WIDTH">48</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXIS_DOUT_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTPUT_WIDTH">24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PHASE_FORMAT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PIPELINE_MODE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRECISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ROUND_MODE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SCALE_COMP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_CARTESIAN_TDATA_WIDTH">48</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_CARTESIAN_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_PHASE_TDATA_WIDTH">24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_PHASE_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_THROTTLE_SCHEME">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TLAST_RESOLUTION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARESETN">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Architectural_Configuration">Parallel</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coarse_Rotation">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Compensation_Scaling">No_Scale_Compensation</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">cordic_rotator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Format">SignedFraction</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Functional_Selection">Rotate</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Width">24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Iterations">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Width">24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phase_Format">Scaled_Radians</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pipelining_Mode">Maximum</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Precision">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Round_Mode">Round_Pos_Neg_Inf</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cartesian_has_tlast">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cartesian_has_tuser">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cartesian_tuser_width">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.flow_control">Blocking</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.optimize_goal">Performance</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.out_tlast_behv">Pass_Cartesian_TLAST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.out_tready">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.phase_has_tlast">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.phase_has_tuser">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.phase_tuser_width">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">15</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TLAST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.HAS_TLAST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ARESETN" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Component_Name" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Phase_Format" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Round_Mode" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.cartesian_has_tlast" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.flow_control" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.out_tlast_behv" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.out_tready" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/fpga/usrp3/lib/ip/dds/Makefile.inc b/fpga/usrp3/lib/ip/dds/Makefile.inc
new file mode 100644
index 000000000..2345822cc
--- /dev/null
+++ b/fpga/usrp3/lib/ip/dds/Makefile.inc
@@ -0,0 +1,15 @@
+#
+# Copyright 2018 Ettus Research
+#
+
+include $(TOOLS_DIR)/make/viv_ip_builder.mak
+
+LIB_IP_DDS_SRCS = $(IP_BUILD_DIR)/dds/dds.xci
+
+LIB_IP_DDS_OUTS = $(addprefix $(IP_BUILD_DIR)/dds/, \
+dds.xci.out \
+synth/dds.vhd \
+) 
+
+$(LIB_IP_DDS_SRCS) $(LIB_IP_DDS_OUTS) : $(LIB_IP_DIR)/dds/dds.xci
+	$(call BUILD_VIVADO_IP,dds,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0)
diff --git a/fpga/usrp3/lib/ip/dds/dds.xci b/fpga/usrp3/lib/ip/dds/dds.xci
new file mode 100644
index 000000000..0af68af47
--- /dev/null
+++ b/fpga/usrp3/lib/ip/dds/dds.xci
@@ -0,0 +1,305 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>dds</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="dds_compiler" spirit:version="6.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLKEN_INTF.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ARESETN_INTF.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_PHASE_IN_INVALID_INTF.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_PINC_INVALID_INTF.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_POFF_INVALID_INTF.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_S_CONFIG_TLAST_MISSING_INTF.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_S_CONFIG_TLAST_UNEXPECTED_INTF.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_S_PHASE_CHANID_INCORRECT_INTF.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_S_PHASE_TLAST_MISSING_INTF.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_S_PHASE_TLAST_UNEXPECTED_INTF.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.HAS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TDATA_NUM_BYTES">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_PHASE.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_PHASE.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_PHASE.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_PHASE.HAS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_PHASE.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_PHASE.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_PHASE.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_PHASE.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_PHASE.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_PHASE.TDATA_NUM_BYTES">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_PHASE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_PHASE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_PHASE.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.HAS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TDATA_NUM_BYTES">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TREADY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ACCUMULATOR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AMPLITUDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CHANNELS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CHAN_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEBUG_INTERFACE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ACLKEN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ARESETN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_M_DATA">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_M_PHASE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PHASEGEN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PHASE_OUT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SINCOS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_CONFIG">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_PHASE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LATENCY">15</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEM_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MODE_OF_OPERATION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MODULUS">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_DATA_HAS_TUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_DATA_TDATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_DATA_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_PHASE_HAS_TUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_PHASE_TDATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_PHASE_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NEGATIVE_COSINE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NEGATIVE_SINE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NOISE_SHAPING">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMISE_GOAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTPUTS_REQUIRED">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTPUT_FORM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTPUT_WIDTH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PHASE_ANGLE_WIDTH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PHASE_INCREMENT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PHASE_INCREMENT_VALUE">0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PHASE_OFFSET">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PHASE_OFFSET_VALUE">0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POR_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESYNC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_CONFIG_SYNC_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_CONFIG_TDATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_PHASE_HAS_TUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_PHASE_TDATA_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_PHASE_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DSP48">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Amplitude_Mode">Unit_Circle</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Channels">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">dds</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_Has_TLAST">Not_Required</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DDS_Clock_Rate">214</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DSP48_Use">Maximal</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Frequency_Resolution">0.4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GUI_Behaviour">Coregen</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Has_ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Has_ARESETn">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Has_Phase_Out">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Has_TREADY">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Latency">15</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Latency_Configuration">Auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M_DATA_Has_TUSER">Not_Required</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M_PHASE_Has_TUSER">Not_Required</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Memory_Type">Block_ROM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Mode_of_Operation">Standard</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Modulus">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Negative_Cosine">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Negative_Sine">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Noise_Shaping">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OUTPUT_FORM">Twos_Complement</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Optimization_Goal">Area</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Frequency1">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Frequency10">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Frequency11">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Frequency12">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Frequency13">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Frequency14">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Frequency15">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Frequency16">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Frequency2">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Frequency3">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Frequency4">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Frequency5">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Frequency6">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Frequency7">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Frequency8">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Frequency9">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Selection">Sine_and_Cosine</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Width">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PINC1">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PINC10">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PINC11">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PINC12">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PINC13">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PINC14">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PINC15">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PINC16">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PINC2">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PINC3">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PINC4">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PINC5">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PINC6">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PINC7">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PINC8">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PINC9">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POFF1">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POFF10">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POFF11">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POFF12">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POFF13">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POFF14">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POFF15">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POFF16">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POFF2">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POFF3">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POFF4">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POFF5">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POFF6">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POFF7">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POFF8">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POFF9">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POR_mode">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Parameter_Entry">Hardware_Parameters</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PartsPresent">Phase_Generator_and_SIN_COS_LUT</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phase_Increment">Programmable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phase_Offset_Angles1">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phase_Offset_Angles10">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phase_Offset_Angles11">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phase_Offset_Angles12">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phase_Offset_Angles13">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phase_Offset_Angles14">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phase_Offset_Angles15">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phase_Offset_Angles16">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phase_Offset_Angles2">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phase_Offset_Angles3">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phase_Offset_Angles4">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phase_Offset_Angles5">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phase_Offset_Angles6">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phase_Offset_Angles7">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phase_Offset_Angles8">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phase_Offset_Angles9">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phase_Width">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phase_offset">Programmable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Resync">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S_CONFIG_Sync_Mode">On_Vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S_PHASE_Has_TUSER">Not_Required</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S_PHASE_TUSER_Width">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Spurious_Free_Dynamic_Range">45</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.explicit_period">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.period">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_PHASE.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_PHASE.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_PHASE.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_PHASE.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_PHASE.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TREADY" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Amplitude_Mode" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Channels" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DATA_Has_TLAST" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DDS_Clock_Rate" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DSP48_Use" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Frequency_Resolution" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Has_ARESETn" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Has_Phase_Out" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Has_TREADY" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Latency" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M_DATA_Has_TUSER" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M_PHASE_Has_TUSER" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Memory_Type" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Mode_of_Operation" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Noise_Shaping" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Optimization_Goal" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Frequency1" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PINC1" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Parameter_Entry" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PartsPresent" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Phase_Increment" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Phase_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Phase_offset" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.S_PHASE_Has_TUSER" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/fpga/usrp3/lib/ip/dds_sin_cos_lut_only/Makefile.inc b/fpga/usrp3/lib/ip/dds_sin_cos_lut_only/Makefile.inc
new file mode 100644
index 000000000..6e141206f
--- /dev/null
+++ b/fpga/usrp3/lib/ip/dds_sin_cos_lut_only/Makefile.inc
@@ -0,0 +1,17 @@
+#
+# Copyright 2018 Ettus Research, a National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+include $(TOOLS_DIR)/make/viv_ip_builder.mak
+
+LIB_IP_DDS_SIN_COS_LUT_ONLY_SRCS = $(IP_BUILD_DIR)/dds_sin_cos_lut_only/dds_sin_cos_lut_only.xci
+
+LIB_IP_DDS_SIN_COS_LUT_ONLY_OUTS = $(addprefix $(IP_BUILD_DIR)/dds_sin_cos_lut_only/, \
+dds_sin_cos_lut_only.xci.out \
+synth/dds_sin_cos_lut_only.vhd \
+) 
+
+$(LIB_IP_DDS_SIN_COS_LUT_ONLY_SRCS) $(LIB_IP_DDS_SIN_COS_LUT_ONLY_OUTS) : $(LIB_IP_DIR)/dds_sin_cos_lut_only/dds_sin_cos_lut_only.xci
+	$(call BUILD_VIVADO_IP,dds_sin_cos_lut_only,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0)
diff --git a/fpga/usrp3/lib/ip/dds_sin_cos_lut_only/dds_sin_cos_lut_only.xci b/fpga/usrp3/lib/ip/dds_sin_cos_lut_only/dds_sin_cos_lut_only.xci
new file mode 100644
index 000000000..4220fa7c4
--- /dev/null
+++ b/fpga/usrp3/lib/ip/dds_sin_cos_lut_only/dds_sin_cos_lut_only.xci
@@ -0,0 +1,309 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>dds_sin_cos_lut_only</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="dds_compiler" spirit:version="6.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLKEN_INTF.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ARESETN_INTF.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_PHASE_IN_INVALID_INTF.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_PINC_INVALID_INTF.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_POFF_INVALID_INTF.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_S_CONFIG_TLAST_MISSING_INTF.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_S_CONFIG_TLAST_UNEXPECTED_INTF.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_S_PHASE_CHANID_INCORRECT_INTF.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_S_PHASE_TLAST_MISSING_INTF.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_S_PHASE_TLAST_UNEXPECTED_INTF.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.HAS_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TDATA_NUM_BYTES">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_PHASE.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_PHASE.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_PHASE.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_PHASE.HAS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_PHASE.HAS_TREADY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_PHASE.HAS_TSTRB">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.CLK_DOMAIN"/>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TUSER_WIDTH">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AMPLITUDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CHANNELS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CHAN_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEBUG_INTERFACE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ACLKEN">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_M_DATA">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_M_PHASE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PHASEGEN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PHASE_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SINCOS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_CONFIG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_PHASE">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LATENCY">12</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEM_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MODE_OF_OPERATION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MODULUS">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_DATA_HAS_TUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_DATA_TDATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_DATA_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_PHASE_HAS_TUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_PHASE_TDATA_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_PHASE_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NEGATIVE_COSINE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NEGATIVE_SINE">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTPUT_FORM">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PHASE_ANGLE_WIDTH">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PHASE_INCREMENT">2</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POR_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESYNC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_CONFIG_SYNC_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_CONFIG_TDATA_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_PHASE_HAS_TUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_PHASE_TDATA_WIDTH">24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_PHASE_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DSP48">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Amplitude_Mode">Unit_Circle</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Channels">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">dds_sin_cos_lut_only</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_Has_TLAST">Packet_Framing</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DDS_Clock_Rate">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DSP48_Use">Minimal</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Frequency_Resolution">0.4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GUI_Behaviour">Coregen</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Has_ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Has_ARESETn">true</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Has_TREADY">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Latency">12</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Latency_Configuration">Configurable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M_DATA_Has_TUSER">Not_Required</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M_PHASE_Has_TUSER">Not_Required</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Memory_Type">Block_ROM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Mode_of_Operation">Standard</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Modulus">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Negative_Cosine">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Negative_Sine">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Noise_Shaping">Taylor_Series_Corrected</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OUTPUT_FORM">Twos_Complement</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Optimization_Goal">Area</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Frequency9">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Selection">Sine_and_Cosine</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Width">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PINC1">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PINC9">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POR_mode">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Parameter_Entry">Hardware_Parameters</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PartsPresent">SIN_COS_LUT_only</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phase_Increment">Fixed</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phase_Offset_Angles3">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phase_Offset_Angles5">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phase_Offset_Angles6">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phase_Offset_Angles7">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phase_Offset_Angles8">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phase_Offset_Angles9">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phase_Width">24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phase_offset">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Resync">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S_CONFIG_Sync_Mode">On_Vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S_PHASE_Has_TUSER">Not_Required</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S_PHASE_TUSER_Width">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Spurious_Free_Dynamic_Range">45</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.explicit_period">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.period">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
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+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_PHASE.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_PHASE.HAS_TREADY" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_PHASE.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_PHASE.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_PHASE.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_PHASE.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.HAS_TREADY" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TLAST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Amplitude_Mode" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Channels" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DATA_Has_TLAST" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DDS_Clock_Rate" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DSP48_Use" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Frequency_Resolution" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Has_ARESETn" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Has_Phase_Out" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Has_TREADY" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Latency" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Latency_Configuration" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M_DATA_Has_TUSER" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M_PHASE_Has_TUSER" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Memory_Type" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Mode_of_Operation" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Noise_Shaping" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Optimization_Goal" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Frequency1" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PINC1" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Parameter_Entry" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PartsPresent" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Phase_Increment" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Phase_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Phase_offset" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.S_PHASE_Has_TUSER" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/fpga/usrp3/lib/ip/divide_int16/Makefile.inc b/fpga/usrp3/lib/ip/divide_int16/Makefile.inc
new file mode 100644
index 000000000..103dfc52d
--- /dev/null
+++ b/fpga/usrp3/lib/ip/divide_int16/Makefile.inc
@@ -0,0 +1,18 @@
+#
+# Copyright 2015 Ettus Research
+# Copyright 2016 Ettus Research, a National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+include $(TOOLS_DIR)/make/viv_ip_builder.mak
+
+LIB_IP_DIVIDE_INT16_SRCS = $(IP_BUILD_DIR)/divide_int16/divide_int16.xci
+
+LIB_IP_DIVIDE_INT16_OUTS = $(addprefix $(IP_BUILD_DIR)/divide_int16/, \
+divide_int16.xci.out \
+synth/divide_int16.vhd \
+) 
+
+$(LIB_IP_DIVIDE_INT16_SRCS) $(LIB_IP_DIVIDE_INT16_OUTS) : $(LIB_IP_DIR)/divide_int16/divide_int16.xci
+	$(call BUILD_VIVADO_IP,divide_int16,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0)
diff --git a/fpga/usrp3/lib/ip/divide_int16/divide_int16.xci b/fpga/usrp3/lib/ip/divide_int16/divide_int16.xci
new file mode 100644
index 000000000..b052c0615
--- /dev/null
+++ b/fpga/usrp3/lib/ip/divide_int16/divide_int16.xci
@@ -0,0 +1,162 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>divide_int16</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="div_gen" spirit:version="5.1"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLKEN_INTF.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.FREQ_HZ">1000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ARESETN_INTF.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDATA_NUM_BYTES">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.HAS_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.TDATA_NUM_BYTES">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.HAS_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.TDATA_NUM_BYTES">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ALGORITHM_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ACLKEN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ARESETN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DIV_BY_ZERO">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_DIVIDEND_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_DIVIDEND_TUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_DIVISOR_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_DIVISOR_TUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LATENCY">39</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXIS_DOUT_TDATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXIS_DOUT_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_DIVIDEND_TDATA_WIDTH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_DIVIDEND_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_DIVISOR_TDATA_WIDTH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_DIVISOR_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_THROTTLE_SCHEME">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TLAST_RESOLUTION">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DIVCLK_SEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DIVIDEND_WIDTH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DIVISOR_WIDTH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.FRACTIONAL_B">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.FRACTIONAL_WIDTH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SIGNED_B">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARESETN">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">divide_int16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FlowControl">Blocking</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OptimizeGoal">Performance</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OutTLASTBehv">OR_all_TLASTs</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OutTready">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.algorithm_type">Radix2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.clocks_per_division">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.divide_by_zero_detect">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dividend_and_quotient_width">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dividend_has_tlast">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dividend_has_tuser">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dividend_tuser_width">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.divisor_has_tlast">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.divisor_has_tuser">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.divisor_tuser_width">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.divisor_width">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.fractional_width">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.latency">39</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.latency_configuration">Automatic</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.operand_sign">Signed</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.remainder_type">Fractional</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">15</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TLAST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TUSER_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.HAS_TLAST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.HAS_TLAST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ARESETN" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FlowControl" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.OutTLASTBehv" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.OutTready" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.divide_by_zero_detect" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.dividend_has_tlast" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.divisor_has_tlast" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.latency" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.remainder_type" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/fpga/usrp3/lib/ip/divide_int16_int32/Makefile.inc b/fpga/usrp3/lib/ip/divide_int16_int32/Makefile.inc
new file mode 100644
index 000000000..9aab78f8b
--- /dev/null
+++ b/fpga/usrp3/lib/ip/divide_int16_int32/Makefile.inc
@@ -0,0 +1,17 @@
+#
+# Copyright 2015 Ettus Research, a National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+include $(TOOLS_DIR)/make/viv_ip_builder.mak
+
+LIB_IP_DIVIDE_INT16_INT32_SRCS = $(IP_BUILD_DIR)/divide_int16_int32/divide_int16_int32.xci
+
+LIB_IP_DIVIDE_INT16_INT32_OUTS = $(addprefix $(IP_BUILD_DIR)/divide_int16_int32/, \
+divide_int16_int32.xci.out \
+synth/divide_int16_int32.vhd \
+) 
+
+$(LIB_IP_DIVIDE_INT16_INT32_SRCS) $(LIB_IP_DIVIDE_INT16_INT32_OUTS) : $(LIB_IP_DIR)/divide_int16_int32/divide_int16_int32.xci
+	$(call BUILD_VIVADO_IP,divide_int16_int32,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0)
diff --git a/fpga/usrp3/lib/ip/divide_int16_int32/divide_int16_int32.xci b/fpga/usrp3/lib/ip/divide_int16_int32/divide_int16_int32.xci
new file mode 100644
index 000000000..fb85b0fa5
--- /dev/null
+++ b/fpga/usrp3/lib/ip/divide_int16_int32/divide_int16_int32.xci
@@ -0,0 +1,164 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>divide_int16_int32</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="div_gen" spirit:version="5.1"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLKEN_INTF.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.FREQ_HZ">1000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ARESETN_INTF.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDATA_NUM_BYTES">6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.HAS_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.TDATA_NUM_BYTES">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.HAS_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.TDATA_NUM_BYTES">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ALGORITHM_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ACLKEN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ARESETN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DIV_BY_ZERO">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_DIVIDEND_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_DIVIDEND_TUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_DIVISOR_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_DIVISOR_TUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LATENCY">55</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXIS_DOUT_TDATA_WIDTH">48</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXIS_DOUT_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_DIVIDEND_TDATA_WIDTH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_DIVIDEND_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_DIVISOR_TDATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_DIVISOR_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_THROTTLE_SCHEME">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TLAST_RESOLUTION">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DIVCLK_SEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DIVIDEND_WIDTH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DIVISOR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.FRACTIONAL_B">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.FRACTIONAL_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SIGNED_B">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARESETN">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">divide_int16_int32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FlowControl">Blocking</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OptimizeGoal">Performance</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OutTLASTBehv">OR_all_TLASTs</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OutTready">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.algorithm_type">Radix2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.clocks_per_division">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.divide_by_zero_detect">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dividend_and_quotient_width">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dividend_has_tlast">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dividend_has_tuser">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dividend_tuser_width">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.divisor_has_tlast">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.divisor_has_tuser">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.divisor_tuser_width">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.divisor_width">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.fractional_width">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.latency">55</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.latency_configuration">Automatic</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.operand_sign">Signed</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.remainder_type">Fractional</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">15</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TLAST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TUSER_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.HAS_TLAST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.HAS_TLAST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ARESETN" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FlowControl" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.OutTLASTBehv" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.OutTready" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.divide_by_zero_detect" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.dividend_has_tlast" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.divisor_has_tlast" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.divisor_width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.fractional_width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.latency" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.remainder_type" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/fpga/usrp3/lib/ip/divide_int24/Makefile.inc b/fpga/usrp3/lib/ip/divide_int24/Makefile.inc
new file mode 100644
index 000000000..94a5a8a2b
--- /dev/null
+++ b/fpga/usrp3/lib/ip/divide_int24/Makefile.inc
@@ -0,0 +1,17 @@
+#
+# Copyright 2015 Ettus Research, a National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+include $(TOOLS_DIR)/make/viv_ip_builder.mak
+
+LIB_IP_DIVIDE_INT24_SRCS = $(IP_BUILD_DIR)/divide_int24/divide_int24.xci
+
+LIB_IP_DIVIDE_INT24_OUTS = $(addprefix $(IP_BUILD_DIR)/divide_int24/, \
+divide_int24.xci.out \
+synth/divide_int24.vhd \
+) 
+
+$(LIB_IP_DIVIDE_INT24_SRCS) $(LIB_IP_DIVIDE_INT24_OUTS) : $(LIB_IP_DIR)/divide_int24/divide_int24.xci
+	$(call BUILD_VIVADO_IP,divide_int24,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0)
diff --git a/fpga/usrp3/lib/ip/divide_int24/divide_int24.xci b/fpga/usrp3/lib/ip/divide_int24/divide_int24.xci
new file mode 100644
index 000000000..d98c7359f
--- /dev/null
+++ b/fpga/usrp3/lib/ip/divide_int24/divide_int24.xci
@@ -0,0 +1,165 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>divide_int24</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="div_gen" spirit:version="5.1"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLKEN_INTF.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.FREQ_HZ">1000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ARESETN_INTF.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDATA_NUM_BYTES">6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.HAS_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.TDATA_NUM_BYTES">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.HAS_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.TDATA_NUM_BYTES">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ALGORITHM_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ACLKEN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ARESETN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DIV_BY_ZERO">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_DIVIDEND_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_DIVIDEND_TUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_DIVISOR_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_DIVISOR_TUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LATENCY">55</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXIS_DOUT_TDATA_WIDTH">48</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXIS_DOUT_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_DIVIDEND_TDATA_WIDTH">24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_DIVIDEND_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_DIVISOR_TDATA_WIDTH">24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_DIVISOR_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_THROTTLE_SCHEME">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TLAST_RESOLUTION">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DIVCLK_SEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DIVIDEND_WIDTH">24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DIVISOR_WIDTH">24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.FRACTIONAL_B">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.FRACTIONAL_WIDTH">24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SIGNED_B">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARESETN">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">divide_int24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FlowControl">Blocking</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OptimizeGoal">Performance</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OutTLASTBehv">OR_all_TLASTs</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OutTready">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.algorithm_type">Radix2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.clocks_per_division">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.divide_by_zero_detect">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dividend_and_quotient_width">24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dividend_has_tlast">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dividend_has_tuser">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dividend_tuser_width">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.divisor_has_tlast">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.divisor_has_tuser">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.divisor_tuser_width">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.divisor_width">24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.fractional_width">24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.latency">55</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.latency_configuration">Automatic</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.operand_sign">Signed</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.remainder_type">Fractional</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">15</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TLAST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TUSER_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.HAS_TLAST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.HAS_TLAST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ARESETN" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FlowControl" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.OutTLASTBehv" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.OutTready" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.divide_by_zero_detect" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.dividend_and_quotient_width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.dividend_has_tlast" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.divisor_has_tlast" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.divisor_width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.fractional_width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.latency" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.remainder_type" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/fpga/usrp3/lib/ip/divide_int32/Makefile.inc b/fpga/usrp3/lib/ip/divide_int32/Makefile.inc
new file mode 100644
index 000000000..c4eacf68f
--- /dev/null
+++ b/fpga/usrp3/lib/ip/divide_int32/Makefile.inc
@@ -0,0 +1,15 @@
+#
+# Copyright 2015 Ettus Research
+#
+
+include $(TOOLS_DIR)/make/viv_ip_builder.mak
+
+LIB_IP_DIVIDE_INT32_SRCS = $(IP_BUILD_DIR)/divide_int32/divide_int32.xci
+
+LIB_IP_DIVIDE_INT32_OUTS = $(addprefix $(IP_BUILD_DIR)/divide_int32/, \
+divide_int32.xci.out \
+synth/divide_int32.vhd \
+) 
+
+$(LIB_IP_DIVIDE_INT32_SRCS) $(LIB_IP_DIVIDE_INT32_OUTS) : $(LIB_IP_DIR)/divide_int32/divide_int32.xci
+	$(call BUILD_VIVADO_IP,divide_int32,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0)
diff --git a/fpga/usrp3/lib/ip/divide_int32/divide_int32.xci b/fpga/usrp3/lib/ip/divide_int32/divide_int32.xci
new file mode 100644
index 000000000..b57c10a58
--- /dev/null
+++ b/fpga/usrp3/lib/ip/divide_int32/divide_int32.xci
@@ -0,0 +1,165 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>divide_int32</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="div_gen" spirit:version="5.1"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLKEN_INTF.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.FREQ_HZ">1000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ARESETN_INTF.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDATA_NUM_BYTES">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.HAS_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.TDATA_NUM_BYTES">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.HAS_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.TDATA_NUM_BYTES">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ALGORITHM_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ACLKEN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ARESETN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DIV_BY_ZERO">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_DIVIDEND_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_DIVIDEND_TUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_DIVISOR_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_DIVISOR_TUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LATENCY">71</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXIS_DOUT_TDATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXIS_DOUT_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_DIVIDEND_TDATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_DIVIDEND_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_DIVISOR_TDATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_DIVISOR_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_THROTTLE_SCHEME">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TLAST_RESOLUTION">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DIVCLK_SEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DIVIDEND_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DIVISOR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.FRACTIONAL_B">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.FRACTIONAL_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SIGNED_B">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARESETN">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">divide_int32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FlowControl">Blocking</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OptimizeGoal">Performance</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OutTLASTBehv">OR_all_TLASTs</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OutTready">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.algorithm_type">Radix2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.clocks_per_division">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.divide_by_zero_detect">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dividend_and_quotient_width">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dividend_has_tlast">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dividend_has_tuser">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dividend_tuser_width">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.divisor_has_tlast">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.divisor_has_tuser">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.divisor_tuser_width">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.divisor_width">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.fractional_width">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.latency">71</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.latency_configuration">Automatic</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.operand_sign">Signed</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.remainder_type">Fractional</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">15</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TLAST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TUSER_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.HAS_TLAST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.HAS_TLAST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ARESETN" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FlowControl" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.OutTLASTBehv" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.OutTready" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.divide_by_zero_detect" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.dividend_and_quotient_width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.dividend_has_tlast" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.divisor_has_tlast" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.divisor_width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.fractional_width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.latency" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.remainder_type" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/fpga/usrp3/lib/ip/divide_uint32/Makefile.inc b/fpga/usrp3/lib/ip/divide_uint32/Makefile.inc
new file mode 100644
index 000000000..054296981
--- /dev/null
+++ b/fpga/usrp3/lib/ip/divide_uint32/Makefile.inc
@@ -0,0 +1,17 @@
+#
+# Copyright 2015 Ettus Research, a National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+include $(TOOLS_DIR)/make/viv_ip_builder.mak
+
+LIB_IP_DIVIDE_UINT32_SRCS = $(IP_BUILD_DIR)/divide_uint32/divide_uint32.xci
+
+LIB_IP_DIVIDE_UINT32_OUTS = $(addprefix $(IP_BUILD_DIR)/divide_uint32/, \
+divide_uint32.xci.out \
+synth/divide_uint32.vhd \
+) 
+
+$(LIB_IP_DIVIDE_UINT32_SRCS) $(LIB_IP_DIVIDE_UINT32_OUTS) : $(LIB_IP_DIR)/divide_uint32/divide_uint32.xci
+	$(call BUILD_VIVADO_IP,divide_uint32,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0)
diff --git a/fpga/usrp3/lib/ip/divide_uint32/divide_uint32.xci b/fpga/usrp3/lib/ip/divide_uint32/divide_uint32.xci
new file mode 100644
index 000000000..12d19d75b
--- /dev/null
+++ b/fpga/usrp3/lib/ip/divide_uint32/divide_uint32.xci
@@ -0,0 +1,166 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>divide_uint32</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="div_gen" spirit:version="5.1"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLKEN_INTF.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.FREQ_HZ">1000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ARESETN_INTF.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDATA_NUM_BYTES">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.HAS_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.TDATA_NUM_BYTES">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.HAS_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.TDATA_NUM_BYTES">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ALGORITHM_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ACLKEN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ARESETN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DIV_BY_ZERO">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_DIVIDEND_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_DIVIDEND_TUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_DIVISOR_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_DIVISOR_TUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LATENCY">69</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXIS_DOUT_TDATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXIS_DOUT_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_DIVIDEND_TDATA_WIDTH">32</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TLAST_RESOLUTION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DIVCLK_SEL">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DIVISOR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.FRACTIONAL_B">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.FRACTIONAL_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SIGNED_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARESETN">true</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OptimizeGoal">Performance</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OutTLASTBehv">Pass_Dividend_TLAST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OutTready">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.algorithm_type">Radix2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.clocks_per_division">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.divide_by_zero_detect">true</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dividend_has_tuser">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dividend_tuser_width">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.divisor_has_tlast">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.divisor_has_tuser">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.divisor_tuser_width">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.latency_configuration">Automatic</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.operand_sign">Unsigned</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.remainder_type">Fractional</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">15</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TLAST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TUSER_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.HAS_TLAST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.HAS_TKEEP" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.HAS_TLAST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ARESETN" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FlowControl" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.OutTLASTBehv" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.OutTready" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.divide_by_zero_detect" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.dividend_and_quotient_width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.dividend_has_tlast" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.divisor_has_tlast" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.divisor_width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.fractional_width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.latency" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.operand_sign" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.remainder_type" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/fpga/usrp3/lib/packet_proc/.gitignore b/fpga/usrp3/lib/packet_proc/.gitignore
new file mode 100644
index 000000000..ca543057c
--- /dev/null
+++ b/fpga/usrp3/lib/packet_proc/.gitignore
@@ -0,0 +1,3 @@
+vita.txt
+xo.txt
+zpu.txt
diff --git a/fpga/usrp3/lib/packet_proc/Makefile.srcs b/fpga/usrp3/lib/packet_proc/Makefile.srcs
new file mode 100644
index 000000000..07a357965
--- /dev/null
+++ b/fpga/usrp3/lib/packet_proc/Makefile.srcs
@@ -0,0 +1,19 @@
+#
+# Copyright 2013 Ettus Research LLC
+# Copyright 2016 Ettus Research, a National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+##################################################
+# Packet Processing Sources
+##################################################
+PACKET_PROC_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/packet_proc/, \
+chdr_chunker.v \
+chdr_dechunker.v \
+cvita_dest_lookup.v \
+ip_hdr_checksum.v \
+arm_deframer.v \
+arp_responder/arp_responder.vhd \
+))
+
diff --git a/fpga/usrp3/lib/packet_proc/arm_deframer.v b/fpga/usrp3/lib/packet_proc/arm_deframer.v
new file mode 100644
index 000000000..c4f77edf7
--- /dev/null
+++ b/fpga/usrp3/lib/packet_proc/arm_deframer.v
@@ -0,0 +1,119 @@
+/////////////////////////////////////////////////////////////////////
+//
+// Copyright 2017 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: arm_deframer
+// Description:
+//   Adds 6 bytes of Zeros at the beginning of every packet. It aligns the
+//   64-bit words of the ethernet packet to be used later for classifying the
+//   packets. The module is based on xge64_to_axi64 and has lesser
+//   functionality.
+//   Note that the block only works for padding 6 bytes.
+//
+/////////////////////////////////////////////////////////////////////
+
+module arm_deframer (
+  // Clocks and Reset
+  input wire clk,
+  input wire reset,
+  input wire clear,
+  // Slave AXI Interface
+  input wire [63:0] s_axis_tdata,
+  input wire [3:0]  s_axis_tuser, //used as tkeep here
+  input wire        s_axis_tlast,
+  input wire        s_axis_tvalid,
+  output reg        s_axis_tready,
+  // Master AXI Interface
+  output reg [63:0] m_axis_tdata,
+  output reg [3:0]  m_axis_tuser, //used as tkeep here
+  output reg        m_axis_tlast,
+  output reg        m_axis_tvalid,
+  input wire        m_axis_tready
+);
+  // State Machine States
+  localparam START = 2'b00;
+  localparam BODY = 2'b01;
+  localparam EXTRA = 2'b10;
+  localparam PAD_BYTES = 3'b110; //6 bytes
+  wire       new_line;
+  wire       valid_beat;
+  reg [1:0]  state = 2'b00, next_state=2'b00;
+  reg [47:0] holding_reg;
+  reg [2:0]  holding_user;
+  // New line will be created by padding 6 bytes if the valid bytes on the
+  // last line are greater than 2 bytes(3 to 7 bytes) or all 8 bytes are valid.
+  assign new_line = (s_axis_tuser[2:0] > 3'b010) || (s_axis_tuser[2:0] == 3'b000);
+  assign valid_beat = s_axis_tvalid & m_axis_tready;
+  always @(posedge clk) begin
+    if (reset | clear) begin
+      state <= START;
+    end else begin
+      state <=next_state;
+    end
+  end
+  // holding last 48 bits from input tdata on every valid_beat.
+  always @(posedge clk)begin
+    if (s_axis_tvalid & s_axis_tready) begin
+      // Register the last 6 bytes of data for one cycle
+      holding_reg  <= s_axis_tdata[63:16];
+      // Register the tuser in case there is a new line
+      // tuser should be valid for one extra cycle in that case
+      holding_user <= s_axis_tuser[2:0];
+    end
+  end
+  // Outputs
+  always @(*) begin
+    m_axis_tdata  = 64'b0;
+    m_axis_tvalid = 1'b0;
+    m_axis_tlast  = 1'b0;
+    m_axis_tuser  = 4'b0;
+    s_axis_tready = 1'b1;
+    case (state)
+      START : begin
+        // Pad with 6 bytes of Zeros at the beginning of the packet
+        // Shift the first 2 bytes to the end
+        m_axis_tdata  = {s_axis_tdata[15:0], 48'b0};
+        m_axis_tvalid = s_axis_tvalid;
+        m_axis_tlast  = s_axis_tlast;
+        m_axis_tuser  = 4'b0;
+        s_axis_tready = m_axis_tready;
+        if(valid_beat) next_state = BODY;
+        else next_state = START;
+      end
+      BODY : begin
+        // Shift the remaining packet by 6 bytes.
+        // Here we're using register version of data and tvalid.
+        m_axis_tdata  = {s_axis_tdata[15:0], holding_reg};
+        m_axis_tvalid = s_axis_tvalid;
+        m_axis_tlast  = new_line? 1'b0: s_axis_tvalid & s_axis_tlast;
+        // Modify the tuser according to the new packet i.e. add 6 to it.
+        m_axis_tuser  = (new_line & s_axis_tlast) ? 4'b0: {1'b0, s_axis_tuser[2:0] + PAD_BYTES};
+        s_axis_tready = m_axis_tready;
+        if (valid_beat & s_axis_tlast) next_state  =  new_line ? EXTRA : START;
+        else next_state = BODY;
+      end
+      EXTRA : begin
+        m_axis_tdata  = {16'b0, holding_reg};
+        m_axis_tvalid = 1'b1;
+        m_axis_tlast  = 1'b1;
+        // Modify the tuser according to the new shifted packet i.e. add 6 to it.
+        m_axis_tuser  = {1'b0, holding_user + PAD_BYTES};
+        // We need to hold off any comming upstream data i.e not ready until
+        // downstream done consuming this data
+        s_axis_tready = 1'b0;
+        if (m_axis_tready) next_state = START;
+        else next_state = EXTRA;
+      end
+      default : begin
+        m_axis_tdata  = 64'b0;
+        m_axis_tvalid = 1'b0;
+        m_axis_tlast  = 1'b0;
+        m_axis_tuser  = 4'b0;
+        s_axis_tready = 1'b1;
+        next_state = START;
+      end
+    endcase
+  end
+endmodule // arm_deframer
diff --git a/fpga/usrp3/lib/packet_proc/arp_responder/arp_responder.vhd b/fpga/usrp3/lib/packet_proc/arp_responder/arp_responder.vhd
new file mode 100644
index 000000000..8481132c6
--- /dev/null
+++ b/fpga/usrp3/lib/packet_proc/arp_responder/arp_responder.vhd
@@ -0,0 +1,204 @@
+--
+-- Copyright 2019 Ettus Research, A National Instruments brand
+--
+-- SPDX-License-Identifier: LGPL-3.0
+--
+-- Module: arp_responder
+-- Description: Processing IP to send replies for ARP frames (for IPv4)
+-- arp_responder checks the incoming ARP frame against the input port ip_addr,
+-- and if the frame is a request for this module's ip_addr, the module will
+-- format an ARP reply and send it on the outgoing AXI-S interface.
+--
+-- mac_addr and ip_addr must be kept stable for this module to function. They
+-- are not registered within the IP.
+--
+-- s_axis_tuser indicates there is an error in the packet, and it should be discarded
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity arp_responder is
+port (
+  aclk          : in std_logic;
+  aresetn       : in std_logic;
+  mac_addr      : in std_logic_vector(47 downto 0);
+  ip_addr       : in std_logic_vector(31 downto 0);
+  s_axis_tdata  : in std_logic_vector(63 downto 0);
+  s_axis_tvalid : in std_logic;
+  s_axis_tready : out std_logic;
+  s_axis_tkeep  : in std_logic_vector(7 downto 0);
+  s_axis_tlast  : in std_logic;
+  s_axis_tuser  : in std_logic;
+  m_axis_tdata  : out std_logic_vector(63 downto 0);
+  m_axis_tvalid : out std_logic;
+  m_axis_tready : in std_logic;
+  m_axis_tkeep  : out std_logic_vector(7 downto 0);
+  m_axis_tlast  : out std_logic;
+  m_axis_tuser  : out std_logic
+);
+end arp_responder;
+
+architecture arch of arp_responder is
+  type pkt_state_t is (PKT_IDLE, PKT_RECV, PKT_SEND, PKT_DROP);
+  signal pkt_state : pkt_state_t;
+  signal pkt_recv_count : unsigned(3 downto 0);
+  signal pkt_send_count : unsigned(3 downto 0);
+
+  --All of these are LSB-0 for bits, but first byte transmitted is byte 0
+  --  In ChipScope, bytes will appear swapped versus typical diagrams
+  signal src_mac_be : std_logic_vector(47 downto 0);
+  signal sender_hw_addr_be : std_logic_vector(47 downto 0);
+  signal sender_protocol_addr_be : std_logic_vector(31 downto 0);
+  signal target_protocol_addr_be : std_logic_vector(31 downto 0);
+  signal ip_addr_be : std_logic_vector(31 downto 0);
+begin
+  m_axis_tuser <= '0';
+  m_axis_tvalid <= '1' when (pkt_state = PKT_SEND) else '0';
+  ip_addr_be <= ip_addr(7 downto 0) & ip_addr(15 downto 8) &
+                ip_addr(23 downto 16) & ip_addr(31 downto 24);
+
+  s_axis_tready <= '1' when (pkt_state = PKT_IDLE) or (pkt_state = PKT_RECV) or (pkt_state = PKT_DROP)
+                   else '0';
+
+  tx_reply : process (src_mac_be, mac_addr, ip_addr, sender_hw_addr_be,
+                      sender_protocol_addr_be, pkt_send_count)
+  begin
+    m_axis_tdata <= (others => 'X');
+    m_axis_tkeep <= (others => '1');
+    m_axis_tlast <= '0';
+    case (to_integer(pkt_send_count)) is
+    when 0 =>
+      m_axis_tdata(47 downto 0)  <= src_mac_be;
+      m_axis_tdata(63 downto 48) <= mac_addr(39 downto 32) & mac_addr(47 downto 40);
+      m_axis_tkeep <= X"FF";
+      m_axis_tlast <= '0';
+    when 1 =>
+      m_axis_tdata(31 downto 0)  <= mac_addr(7 downto 0) & mac_addr(15 downto 8) &
+                                    mac_addr(23 downto 16) & mac_addr(31 downto 24);
+      m_axis_tdata(47 downto 32) <= X"0608";
+      m_axis_tdata(63 downto 48) <= X"0100";
+      m_axis_tkeep <= X"FF";
+      m_axis_tlast <= '0';
+    when 2 =>
+      m_axis_tdata(15 downto 0)  <= X"0008"; --PTYPE
+      m_axis_tdata(23 downto 16) <= X"06";   --HLEN
+      m_axis_tdata(31 downto 24) <= X"04";   --PLEN
+      m_axis_tdata(47 downto 32) <= X"0200"; --OPER
+      m_axis_tdata(63 downto 48) <= mac_addr(39 downto 32) & mac_addr(47 downto 40); --SHA
+      m_axis_tkeep <= X"FF";
+      m_axis_tlast <= '0';
+    when 3 =>
+      m_axis_tdata(31 downto 0)  <= mac_addr(7 downto 0) & mac_addr(15 downto 8) &
+                                    mac_addr(23 downto 16) & mac_addr(31 downto 24); --SHA
+      m_axis_tdata(63 downto 32) <= ip_addr(7 downto 0) & ip_addr(15 downto 8) &
+                                    ip_addr(23 downto 16) & ip_addr(31 downto 24);  --SPA
+      m_axis_tkeep <= X"FF";
+      m_axis_tlast <= '0';
+    when 4 =>
+      m_axis_tdata(47 downto 0)  <= sender_hw_addr_be; --THA
+      m_axis_tdata(63 downto 48) <= sender_protocol_addr_be(15 downto 0); --TPA
+      m_axis_tkeep <= X"FF";
+      m_axis_tlast <= '0';
+    when 5 =>
+      m_axis_tdata(15 downto 0)  <= sender_protocol_addr_be(31 downto 16); --TPA
+      m_axis_tdata(63 downto 16) <= (others => '0');
+      m_axis_tkeep <= X"03";
+      m_axis_tlast <= '1';
+    when others =>
+      null;
+    end case;
+  end process;
+
+  process (aclk)
+    variable pkt_nonmatch : boolean := false;
+  begin
+  if rising_edge(aclk) then
+    case (pkt_state) is
+    when PKT_IDLE =>
+      if (s_axis_tvalid = '1') and (s_axis_tlast = '0') and (s_axis_tuser = '0') then
+        pkt_state <= PKT_RECV;
+        pkt_recv_count <= to_unsigned(1, pkt_recv_count'length);
+        src_mac_be(15 downto 0) <= s_axis_tdata(63 downto 48);
+      end if;
+    when PKT_RECV =>
+      pkt_nonmatch := false;
+
+      pkt_send_count <= to_unsigned(0, pkt_send_count'length);
+
+      if (s_axis_tvalid = '1') and (s_axis_tuser = '1') then
+        pkt_nonmatch := true;
+      elsif (s_axis_tvalid = '1') and (s_axis_tuser = '0') then
+        if (to_integer(pkt_recv_count) < 7) then
+          pkt_recv_count <= pkt_recv_count + 1;
+        end if;
+
+        case (to_integer(pkt_recv_count)) is
+        when 1 =>
+          src_mac_be(47 downto 16) <= s_axis_tdata(31 downto 0);
+          if (s_axis_tdata(47 downto 32) /= X"0608") or --eth_type
+             (s_axis_tdata(63 downto 48) /= X"0100") or --HTYPE
+             (s_axis_tlast = '1') then
+            pkt_nonmatch := true;
+          end if;
+        when 2 =>
+          sender_hw_addr_be(15 downto 0) <= s_axis_tdata(63 downto 48);
+          if (s_axis_tdata(15 downto 0) /= X"0008") or --PTYPE
+             (s_axis_tdata(23 downto 16) /= X"06") or --HLEN
+             (s_axis_tdata(31 downto 24) /= X"04") or --PLEN
+             (s_axis_tdata(47 downto 32) /= X"0100") or --OPER
+             (s_axis_tlast = '1') then
+            pkt_nonmatch := true;
+          end if;
+        when 3 =>
+          sender_hw_addr_be(47 downto 16) <= s_axis_tdata(31 downto 0);
+          sender_protocol_addr_be <= s_axis_tdata(63 downto 32);
+          if (s_axis_tlast = '1') then
+            pkt_nonmatch := true;
+          end if;
+        when 4 =>
+          --THA = s_axis_tdata(47 downto 0)
+          target_protocol_addr_be(15 downto 0) <= s_axis_tdata(63 downto 48);
+          if (s_axis_tdata(63 downto 48) /= ip_addr_be(15 downto 0)) or
+             (s_axis_tlast = '1') then
+            pkt_nonmatch := true;
+          end if;
+        when 5 =>
+          target_protocol_addr_be(31 downto 16) <= s_axis_tdata(15 downto 0);
+          if (s_axis_tdata(15 downto 0) /= ip_addr_be(31 downto 16)) then
+            pkt_nonmatch := true;
+          end if;
+        when others =>
+          null;
+        end case;
+      end if;
+      if (pkt_nonmatch) then
+        if (s_axis_tlast = '1') then
+          pkt_state <= PKT_IDLE;
+        else
+          pkt_state <= PKT_DROP;
+        end if;
+      elsif (s_axis_tlast = '1') then
+        pkt_state <= PKT_SEND;
+      end if;
+    when PKT_SEND =>
+      if (m_axis_tready = '1') then
+        pkt_send_count <= pkt_send_count + 1;
+
+        if (pkt_send_count = 5) then
+          pkt_state <= PKT_IDLE;
+        end if;
+      end if;
+    when PKT_DROP =>
+      if (s_axis_tvalid = '1') and (s_axis_tlast = '1') then
+        pkt_state <= PKT_IDLE;
+      end if;
+    end case;
+
+    if aresetn = '0' then
+      pkt_state <= PKT_IDLE;
+    end if;
+  end if;
+  end process;
+end arch;
+
diff --git a/fpga/usrp3/lib/packet_proc/arp_responder/test/arp_responder_test.vhd b/fpga/usrp3/lib/packet_proc/arp_responder/test/arp_responder_test.vhd
new file mode 100644
index 000000000..ef2e62980
--- /dev/null
+++ b/fpga/usrp3/lib/packet_proc/arp_responder/test/arp_responder_test.vhd
@@ -0,0 +1,185 @@
+--
+-- Copyright 2019 Ettus Research, A National Instruments brand
+--
+-- SPDX-License-Identifier: LGPL-3.0
+--
+-- Module: arp_responder_test
+-- Description: Simulation module to check the arp_responder IP
+-- Sends a request to the arp_responder and checks for the expected reply
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.arp_responder;
+
+entity arp_responder_test is
+end arp_responder_test;
+
+architecture sim of arp_responder_test is
+  signal test_fail     : boolean := false;
+  signal aclk          : std_logic := '0';
+  signal aresetn       : std_logic;
+  signal mac_addr      : std_logic_vector(47 downto 0) := X"017136E7BE02";
+  signal ip_addr       : std_logic_vector(31 downto 0) := X"04030201";
+  signal s_axis_tdata  : std_logic_vector(63 downto 0);
+  signal s_axis_tvalid : std_logic;
+  signal s_axis_tready : std_logic;
+  signal s_axis_tkeep  : std_logic_vector(7 downto 0);
+  signal s_axis_tlast  : std_logic;
+  signal s_axis_tuser  : std_logic;
+  signal m_axis_tdata  : std_logic_vector(63 downto 0);
+  signal m_axis_tvalid : std_logic;
+  signal m_axis_tready : std_logic;
+  signal m_axis_tkeep  : std_logic_vector(7 downto 0);
+  signal m_axis_tlast  : std_logic;
+  signal m_axis_tuser  : std_logic;
+
+  constant HALFCYCLE : time := 4 ns;
+  constant CYCLE : time := 2*HALFCYCLE;
+  constant ARP_REQUEST_VECTOR : std_logic_vector(64*8-1 downto 0) :=
+      X"0000000000000000" & --Padding
+      X"0000000000000000" & --Padding
+      X"000000000000" & --Packet filler
+      X"04030201" &   --
+      X"000000000000" &
+      X"020B010A" &
+      X"00D00D010101" &
+      X"0100" &
+      X"04" &
+      X"06" &
+      X"0008" &
+      X"0100" &
+      X"0608" &
+      X"00D00D010101" &
+      X"FFFFFFFFFFFF";
+  constant ARP_REPLY_VECTOR : std_logic_vector(64*8-1 downto 0) :=
+      X"0000000000000000" & --Padding
+      X"0000000000000000" & --Padding
+      X"000000000000" & --Packet filler
+      X"020B010A" &
+      X"00D00D010101" &
+      X"04030201" &   --
+      X"017136E7BE02" &
+      X"0200" &
+      X"04" &
+      X"06" &
+      X"0008" &
+      X"0100" &
+      X"0608" &
+      X"017136E7BE02" &
+      X"00D00D010101";
+  --Dest --6
+  --Src  --6
+  --Ethertype --2
+  --HTYPE = 0x0001 --2
+  --PTYPE = 0x0800 --2
+  --HLEN  = 0x06 --1
+  --PLEN  = 0x04 --1
+  --OPER  = 0x0001 --2
+  --SHA   = --6
+  --SPA   = --4
+  --THA   = --6
+  --TPA   = --4
+  --Need to check...
+  --  ARP request to us
+  --  ARP request not to us
+  --  Malformed packet
+begin
+
+  process
+  begin
+    wait for HALFCYCLE;
+    aclk <= not aclk;
+  end process;
+
+  process
+  begin
+    wait for CYCLE;
+    aresetn <= '0';
+    wait for 3*CYCLE;
+    aresetn <= '1';
+    s_axis_tvalid <= '0';
+    s_axis_tkeep <= X"00";
+    s_axis_tlast <= '0';
+    s_axis_tuser <= '0';
+    m_axis_tready <= '0';
+    wait for CYCLE;
+    for i in 0 to 7 loop
+      s_axis_tdata <= ARP_REQUEST_VECTOR(64*i+63 downto 64*i);
+      s_axis_tkeep <= X"FF";
+      s_axis_tvalid <= '1';
+      if (i = 7) then
+        s_axis_tlast <= '1';
+      else
+        s_axis_tlast <= '0';
+      end if;
+      if (i >= 3) then
+        s_axis_tuser <= '1';
+      else
+        s_axis_tuser <= '0';
+      end if;
+      wait for CYCLE;
+      s_axis_tvalid <= '0';
+      wait for 7*CYCLE;
+      --wait until s_axis_tready = '1';
+    end loop;
+    wait for CYCLE;
+    s_axis_tvalid <= '0';
+    s_axis_tuser <= '0';
+    wait for CYCLE;
+    for i in 0 to 7 loop
+      s_axis_tdata <= ARP_REQUEST_VECTOR(64*i+63 downto 64*i);
+      s_axis_tkeep <= X"FF";
+      s_axis_tvalid <= '1';
+      if (i = 7) then
+        s_axis_tlast <= '1';
+      else
+        s_axis_tlast <= '0';
+      end if;
+      wait for CYCLE;
+      s_axis_tvalid <= '0';
+      wait for 7*CYCLE;
+      --wait until s_axis_tready = '1';
+    end loop;
+    wait for CYCLE;
+    s_axis_tvalid <= '0';
+    wait for CYCLE;
+    for i in 0 to 7 loop
+      m_axis_tready <= '1';
+      if (m_axis_tdata /= ARP_REPLY_VECTOR(64*i+63 downto 64*i)) then
+        test_fail <= true;
+        report "Reply vector mismatch";
+      end if;
+      wait for CYCLE;
+      m_axis_tready <= '0';
+      wait for 7*CYCLE;
+    end loop;
+    wait for CYCLE;
+    if (test_fail) then
+      report "Test FAILED" severity failure;
+    else
+      report "PASS: End of test" severity failure;
+    end if;
+  end process;
+
+dut : entity arp_responder
+port map (
+  aclk          => aclk,
+  aresetn       => aresetn,
+  mac_addr      => mac_addr,
+  ip_addr       => ip_addr,
+  s_axis_tdata  => s_axis_tdata,
+  s_axis_tvalid => s_axis_tvalid,
+  s_axis_tready => s_axis_tready,
+  s_axis_tkeep  => s_axis_tkeep,
+  s_axis_tlast  => s_axis_tlast,
+  s_axis_tuser  => s_axis_tuser,
+  m_axis_tdata  => m_axis_tdata,
+  m_axis_tvalid => m_axis_tvalid,
+  m_axis_tready => m_axis_tready,
+  m_axis_tkeep  => m_axis_tkeep,
+  m_axis_tlast  => m_axis_tlast,
+  m_axis_tuser  => m_axis_tuser
+);
+end sim;
diff --git a/fpga/usrp3/lib/packet_proc/axis_to_cvita.v b/fpga/usrp3/lib/packet_proc/axis_to_cvita.v
new file mode 100644
index 000000000..e2f0eed66
--- /dev/null
+++ b/fpga/usrp3/lib/packet_proc/axis_to_cvita.v
@@ -0,0 +1,32 @@
+//
+// Copyright 2017 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+`default_nettype none
+
+module axis_to_cvita
+(
+        input wire           clk,
+
+	input wire [63:0]    s_axis_tdata,
+        input wire           s_axis_tlast,
+        input wire           s_axis_tvalid,
+        output wire          s_axis_tready,
+
+	output wire [63:0]   o_tdata,
+        output wire          o_tlast,
+        output wire          o_tvalid,
+        input wire           o_tready
+);
+
+	assign s_axis_tready = o_tready;
+
+	assign o_tdata = {s_axis_tdata[31:0], s_axis_tdata[63:32]};
+	assign o_tlast = s_axis_tlast;
+	assign o_tvalid = s_axis_tvalid;
+
+endmodule // axis_to_cvita
+
+`default_nettype wire
+
diff --git a/fpga/usrp3/lib/packet_proc/chdr_chunker.v b/fpga/usrp3/lib/packet_proc/chdr_chunker.v
new file mode 100644
index 000000000..434919466
--- /dev/null
+++ b/fpga/usrp3/lib/packet_proc/chdr_chunker.v
@@ -0,0 +1,135 @@
+//
+// Copyright 2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+// Copyright 2019 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+// Quantize chdr packets to a configurable quantum value. o_tlast and
+// i_tready will be held off until the entire quantized packet is xferred.
+// If quantum is changed, it is the responsibility of the client to clear
+// this module. error is asserted if a packet is larger than the quantum
+// error can be reset by asserting reset or clear.
+
+`default_nettype none
+module chdr_chunker # (
+   parameter PAD_VALUE = 64'hFFFFFFFF_FFFFFFFF,
+             HOLD_ERROR = 1'b1 // If high, hold error until reset, else pulse
+) (
+   input wire          clk,
+   input wire          reset,
+   input wire          clear,
+   input wire [15:0]   frame_size,
+
+   input wire [63:0]   i_tdata,
+   input wire          i_tlast,
+   input wire          i_tvalid,
+   output reg          i_tready,
+
+   output wire [63:0]  o_tdata,
+   output wire         o_tlast,
+   output reg          o_tvalid,
+   input  wire         o_tready,
+
+   output wire         error
+);
+
+   localparam ST_HEADER  = 2'd0;
+   localparam ST_DATA    = 2'd1;
+   localparam ST_PADDING = 2'd2;
+   localparam ST_ERROR   = 2'd3;
+
+   reg [1:0]   state;
+   reg [15:0]  frame_rem;
+
+   // axi_len = ceil(length / 8)
+   wire [15:0] chdr_len_ceil = i_tdata[31:16] + 16'd7;
+   wire [15:0] axi_len = {3'b000, chdr_len_ceil[15:3]};
+
+   always @(posedge clk) begin
+      if (reset | clear) begin
+         state <= ST_HEADER;
+         frame_rem <= 16'd0;
+      end else if ((state == ST_ERROR) & i_tlast & i_tvalid & !HOLD_ERROR) begin
+         state <= ST_HEADER;
+         frame_rem <= 16'd0;
+      end else if (o_tready) begin
+         case (state)
+            ST_HEADER: begin
+               if (i_tvalid) begin
+                  if ((axi_len > frame_size) | (axi_len == 16'd0))
+                     state <= ST_ERROR;
+                  else if (i_tlast)
+                     state <= ST_PADDING;
+                  else
+                     state <= ST_DATA;
+
+                  frame_rem <= frame_size - 16'd1;
+               end
+            end
+
+            ST_DATA: begin
+               if (i_tvalid) begin
+                  if (i_tlast) begin
+                     state   <= o_tlast ? ST_HEADER : ST_PADDING;
+                     frame_rem <= o_tlast ? 16'd0 : (frame_rem - 16'd1);
+                  end else begin
+                     state <= ST_DATA;
+                     frame_rem <= frame_rem - 16'd1;
+                  end
+               end
+            end
+
+            ST_PADDING: begin
+               if (o_tlast) begin
+                  state   <= ST_HEADER;
+                  frame_rem <= 16'd0;
+               end else begin
+                  state   <= ST_PADDING;
+                  frame_rem <= frame_rem - 16'd1;
+               end
+            end
+
+         endcase
+      end
+   end
+
+   always @(*) begin
+      case (state)
+         ST_HEADER: begin
+            i_tready = o_tready;
+            o_tvalid = (axi_len <= frame_size) & (axi_len > 16'd0) & i_tvalid;
+         end
+
+         ST_DATA: begin
+            i_tready = o_tready;
+            o_tvalid = i_tvalid;
+         end
+
+         ST_PADDING: begin
+            i_tready = 1'b0;
+            o_tvalid = 1'b1;
+         end
+
+         ST_ERROR: begin
+            i_tready = 1'b1;
+            o_tvalid = 1'b0;
+         end
+
+         default: begin
+            i_tready = 1'b0;
+            o_tvalid = 1'b0;
+         end
+      endcase
+   end
+
+   assign o_tlast = (frame_rem != 16'd0) ? (frame_rem == 16'd1) : (axi_len == 16'd1);
+   assign o_tdata = (state == ST_PADDING) ? PAD_VALUE : i_tdata;
+
+   assign error = (state == ST_ERROR);
+
+endmodule // chdr_chunker
+
+`default_nettype wire
+
diff --git a/fpga/usrp3/lib/packet_proc/chdr_dechunker.v b/fpga/usrp3/lib/packet_proc/chdr_dechunker.v
new file mode 100644
index 000000000..3cae23fc6
--- /dev/null
+++ b/fpga/usrp3/lib/packet_proc/chdr_dechunker.v
@@ -0,0 +1,101 @@
+//
+// Copyright 2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+module chdr_dechunker # (
+   parameter PAD_VALUE = 64'hFFFFFFFF_FFFFFFFF
+) (
+   input          clk,
+   input          reset,
+   input          clear,
+   input [15:0]   frame_size,
+
+   input [63:0]   i_tdata,
+   input          i_tvalid,
+   output         i_tready,
+
+   output [63:0]  o_tdata,
+   output         o_tlast,
+   output         o_tvalid,
+   input          o_tready,
+
+   output         error
+);
+
+   localparam ST_HEADER  = 2'd0;
+   localparam ST_DATA    = 2'd1;
+   localparam ST_PADDING = 2'd2;
+   localparam ST_ERROR   = 2'd3;
+
+   reg [1:0]   state;
+   reg [15:0]  frame_rem, pkt_rem;
+   wire        i_tlast;
+
+   // axi_len = ceil(length / 8)
+   wire [15:0] cvita_len_ceil = i_tdata[31:16] + 7;
+   wire [15:0] axi_len = {3'b000, cvita_len_ceil[15:3]};
+
+   always @(posedge clk) begin
+      if (reset | clear) begin
+         state <= ST_HEADER;
+         frame_rem <= 16'd0;
+         pkt_rem   <= 16'd0;
+      end else if (i_tvalid & i_tready) begin
+         case (state)
+            ST_HEADER: begin
+               if (axi_len > frame_size)
+                  state <= ST_ERROR;
+               else if (~o_tlast)
+                  state <= ST_DATA;
+               else
+                  state <= ST_PADDING;
+
+               frame_rem <= frame_size - 16'd1;
+               pkt_rem   <= axi_len - 16'd1;
+            end
+
+            ST_DATA: begin
+               if (o_tlast) begin
+                  state   <= i_tlast ? ST_HEADER : ST_PADDING;
+                  pkt_rem <= 16'd0;
+               end else begin
+                  state   <= ST_DATA;
+                  pkt_rem <= pkt_rem - 16'd1;
+               end
+               frame_rem <= frame_rem - 16'd1;
+            end
+
+            ST_PADDING: begin
+               if (i_tlast) begin
+                  state   <= ST_HEADER;
+                  frame_rem <= 16'd0;
+               end else begin
+                  state   <= ST_PADDING;
+                  frame_rem <= frame_rem - 16'd1;
+               end
+            end
+
+            ST_ERROR: begin
+               // We never leave the error state. However, we can't reach it
+               // with PCIe if we configure our transport according to the
+               // NI-RIO configuration.
+               state <= ST_ERROR;
+            end
+         endcase
+      end
+   end
+
+   assign i_tready = o_tready | (state == ST_PADDING);
+   assign i_tlast = (frame_rem == 16'd1); //Temp signal
+
+   assign o_tvalid = i_tvalid & (state != ST_PADDING);
+   assign o_tlast = (pkt_rem != 0) ? (pkt_rem == 16'd1) : (axi_len == 16'd1);
+   assign o_tdata  = i_tdata;
+
+   assign error = (state == ST_ERROR);
+
+endmodule // chdr_dechunker
diff --git a/fpga/usrp3/lib/packet_proc/cvita_dest_lookup.v b/fpga/usrp3/lib/packet_proc/cvita_dest_lookup.v
new file mode 100644
index 000000000..c19fd8b1a
--- /dev/null
+++ b/fpga/usrp3/lib/packet_proc/cvita_dest_lookup.v
@@ -0,0 +1,53 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Map the endpoint dest part of the SID in the CVITA header to a destination
+// This destination (o_tdest) signal will be valid with o_tdata
+// This only works with VALID CVITA frames
+
+module cvita_dest_lookup
+#(
+    parameter DEST_WIDTH = 4
+)
+(
+    input clk, input rst,
+    input set_stb, input [7:0] set_addr, input [DEST_WIDTH-1:0] set_data,
+    input [63:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
+    output [63:0] o_tdata, output o_tlast, output o_tvalid, input o_tready,
+    output [DEST_WIDTH-1:0] o_tdest
+);
+
+    reg [7:0] endpoint;
+    ram_2port #(.DWIDTH(DEST_WIDTH), .AWIDTH(8)) dest_lut
+    (
+        .clka(clk), .ena(1'b1), .wea(set_stb), .addra(set_addr), .dia(set_data), .doa(),
+        .clkb(clk), .enb(1'b1), .web(1'b0), .addrb(endpoint), .dib(8'hff), .dob(o_tdest)
+    );
+
+    reg forward;
+    reg [1:0] count;
+    always @(posedge clk) begin
+        if (rst) begin
+            forward <= 1'b0;
+            count <= 2'b0;
+        end
+        else if (forward == 1'b0 && i_tvalid) begin
+            if (count == 2'b11) forward <= 1'b1;
+              endpoint <= i_tdata[7:0];
+            count <= count + 1'b1;
+        end
+        else if (forward == 1'b1 && i_tvalid && i_tready && i_tlast) begin
+            forward <= 1'b0;
+            count <= 2'b0;
+        end
+    end
+
+    assign o_tdata = i_tdata;
+    assign o_tlast = i_tlast;
+    assign o_tvalid = i_tvalid && forward;
+    assign i_tready = o_tready && forward;
+
+endmodule // cvita_dest_lookup
diff --git a/fpga/usrp3/lib/packet_proc/cvita_to_axis.v b/fpga/usrp3/lib/packet_proc/cvita_to_axis.v
new file mode 100644
index 000000000..9a346a059
--- /dev/null
+++ b/fpga/usrp3/lib/packet_proc/cvita_to_axis.v
@@ -0,0 +1,32 @@
+//
+// Copyright 2017 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+`default_nettype none
+
+module cvita_to_axis
+(
+	input wire           clk,
+
+	input wire [63:0]    i_tdata,
+        input wire           i_tlast,
+        input wire           i_tvalid,
+        output wire          i_tready,
+
+	output wire [63:0]   m_axis_tdata,
+        output wire          m_axis_tlast,
+        output wire          m_axis_tvalid,
+        input wire           m_axis_tready
+);
+
+	assign i_tready = m_axis_tready;
+
+	assign m_axis_tdata = {i_tdata[31:0], i_tdata[63:32]};
+	assign m_axis_tlast = i_tlast;
+	assign m_axis_tvalid = i_tvalid;
+
+endmodule // cvita_to_axis
+
+`default_nettype wire
+
diff --git a/fpga/usrp3/lib/packet_proc/ip_hdr_checksum.v b/fpga/usrp3/lib/packet_proc/ip_hdr_checksum.v
new file mode 100644
index 000000000..7e2e0f88e
--- /dev/null
+++ b/fpga/usrp3/lib/packet_proc/ip_hdr_checksum.v
@@ -0,0 +1,29 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Compute IP header checksum.  2 cycles of latency.
+module ip_hdr_checksum
+  (input clk, input [159:0] in, output reg [15:0] out);
+
+   wire [18:0] padded [0:9];
+   reg [18:0]  sum_a, sum_b;
+   
+   genvar     i;
+   generate
+      for(i=0 ; i<10 ; i=i+1)
+	assign padded[i] = {3'b000,in[i*16+15:i*16]};
+   endgenerate
+
+   always @(posedge clk)  sum_a = padded[0] + padded[1] + padded[2] + padded[3] + padded[4];
+   always @(posedge clk)  sum_b = padded[5] + padded[6] + padded[7] + padded[8] + padded[9];
+
+   wire [18:0] sum = sum_a + sum_b;
+
+   always @(posedge clk)
+     out <= ~(sum[15:0] + {13'd0,sum[18:16]});
+   
+   
+endmodule // ip_hdr_checksum
diff --git a/fpga/usrp3/lib/packet_proc/ip_hdr_checksum_tb.v b/fpga/usrp3/lib/packet_proc/ip_hdr_checksum_tb.v
new file mode 100644
index 000000000..de52a0049
--- /dev/null
+++ b/fpga/usrp3/lib/packet_proc/ip_hdr_checksum_tb.v
@@ -0,0 +1,43 @@
+//
+// Copyright 2013 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module ip_hdr_checksum_tb();
+   
+   initial $dumpfile("ip_hdr_checksum_tb.vcd");
+   initial $dumpvars(0,ip_hdr_checksum_tb);
+
+   reg clk;
+   
+   wire [159:0] in = {
+		      16'h4500,
+		      16'h0030,
+		      16'h4422,
+		      16'h4000,
+		      16'h8006,
+		      16'h0000,
+		      16'h8c7c,
+		      16'h19ac,
+		      16'hae24,
+		      16'h1e2b
+		      };
+   
+   wire [15:0] 	out;
+   ip_hdr_checksum ip_hdr_checksum
+     (.clk(clk), 
+      .in(in),
+      .out(out));
+
+   initial
+     begin
+	clk <= 0;
+	#100 clk <= 1;
+	#100 clk <= 0;
+	#100 clk <= 1;
+	#100 $display("Computed 0x%x, should be 0x442e", out);
+	#100 $finish;
+     end
+   
+endmodule // ip_hdr_checksum_tb
diff --git a/fpga/usrp3/lib/packet_proc_200/Makefile.srcs b/fpga/usrp3/lib/packet_proc_200/Makefile.srcs
new file mode 100644
index 000000000..3f0834df9
--- /dev/null
+++ b/fpga/usrp3/lib/packet_proc_200/Makefile.srcs
@@ -0,0 +1,14 @@
+#
+# Copyright 2013 Ettus Research LLC
+# Copyright 2016 Ettus Research, a National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+##################################################
+# Packet Processing Sources
+##################################################
+PACKET_PROC_200_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/packet_proc_200/, \
+cvita_dest_lookup_legacy.v \
+source_flow_control_legacy.v \
+))
diff --git a/fpga/usrp3/lib/packet_proc_200/cvita_dest_lookup_legacy.v b/fpga/usrp3/lib/packet_proc_200/cvita_dest_lookup_legacy.v
new file mode 100644
index 000000000..17954baaa
--- /dev/null
+++ b/fpga/usrp3/lib/packet_proc_200/cvita_dest_lookup_legacy.v
@@ -0,0 +1,53 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Map the endpoint dest part of the SID in the CVITA header to a destination
+// This destination (o_tdest) signal will be valid with o_tdata
+// This only works with VALID CVITA frames
+
+module cvita_dest_lookup_legacy
+#(
+    parameter DEST_WIDTH = 4
+)
+(
+    input clk, input rst,
+    input set_stb, input [7:0] set_addr, input [DEST_WIDTH-1:0] set_data,
+    input [63:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
+    output [63:0] o_tdata, output o_tlast, output o_tvalid, input o_tready,
+    output [DEST_WIDTH-1:0] o_tdest
+);
+
+    reg [7:0] endpoint;
+    ram_2port #(.DWIDTH(DEST_WIDTH), .AWIDTH(8)) dest_lut
+    (
+        .clka(clk), .ena(1'b1), .wea(set_stb), .addra(set_addr), .dia(set_data), .doa(),
+        .clkb(clk), .enb(1'b1), .web(1'b0), .addrb(endpoint), .dib(8'hff), .dob(o_tdest)
+    );
+
+    reg forward;
+    reg [1:0] count;
+    always @(posedge clk) begin
+        if (rst) begin
+            forward <= 1'b0;
+            count <= 2'b0;
+        end
+        else if (forward == 1'b0 && i_tvalid) begin
+            if (count == 2'b11) forward <= 1'b1;
+            endpoint <= i_tdata[23:16];
+            count <= count + 1'b1;
+        end
+        else if (forward == 1'b1 && i_tvalid && i_tready && i_tlast) begin
+            forward <= 1'b0;
+            count <= 2'b0;
+        end
+    end
+
+    assign o_tdata = i_tdata;
+    assign o_tlast = i_tlast;
+    assign o_tvalid = i_tvalid && forward;
+    assign i_tready = o_tready && forward;
+
+endmodule // cvita_dest_lookup_legacy
diff --git a/fpga/usrp3/lib/packet_proc_200/source_flow_control_legacy.v b/fpga/usrp3/lib/packet_proc_200/source_flow_control_legacy.v
new file mode 100644
index 000000000..46906f97d
--- /dev/null
+++ b/fpga/usrp3/lib/packet_proc_200/source_flow_control_legacy.v
@@ -0,0 +1,150 @@
+//
+// Copyright 2014-2016 Ettus Research
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+//  This block passes the in_* AXI port to the out_* AXI port only when it has
+//  enough flow control credits. Data is held when there are not enough credits.
+//  Credits are replenished with extension context packets which update the 
+//  last_consumed packet register. Max credits are controlled by settings regs.
+//  The 2nd line of the packet contains the sequence number in the low 12 bits.
+//  These packets should not have a time value, but if they do it will be ignored.
+
+module source_flow_control_legacy #(
+   parameter BASE=0
+) (
+   input clk, input reset, input clear,
+   input set_stb, input [7:0] set_addr, input [31:0] set_data,
+   input [63:0] fc_tdata, input fc_tlast, input fc_tvalid, output fc_tready,
+   input [63:0] in_tdata, input in_tlast, input in_tvalid, output in_tready,
+   output [63:0] out_tdata, output out_tlast, output out_tvalid, input out_tready,
+   output busy
+);
+   reg [31:0]     last_seqnum_consumed;
+   wire [31:0]    window_size;
+   wire [31:0]    go_until_seqnum = last_seqnum_consumed + window_size + 1;
+   reg [31:0]     current_seqnum;
+   wire           window_reset;
+   wire           window_enable;
+
+   //Sets the size of the flow control window
+   setting_reg #(.my_addr(BASE)) sr_window_size
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),.in(set_data),
+      .out(window_size),.changed());
+
+   //Setting to enable/disable the flow control window
+   //When this register is hit, the window will reset.
+   //As a part of the reset process, all FC blocked data upstream will be
+   //dropped by this module and it will reset to the SFC_HEAD head state.
+   //The reset sequence can take more than one cycle during which this
+   //module will hold off all flow control data.
+   setting_reg #(.my_addr(BASE+1), .width(1)) sr_window_enable
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),.in(set_data),
+      .out(window_enable),.changed(window_reset));
+
+   reg         go;
+   reg         window_reseting;
+   reg [11:0]  window_reset_cnt; //Counter to make reset tolerant to bubble cycles
+   reg [1:0]   sfc_state;
+   
+   always @(posedge clk) begin
+      if (reset | clear) begin
+         window_reseting  <= 1'b0;
+      end else if (window_reset) begin                  //Reset start
+         window_reseting  <= 1'b1;
+         window_reset_cnt <= 12'd0;
+      end else if (window_reseting & ~in_tvalid) begin  //Reset end
+         window_reset_cnt <= window_reset_cnt + 12'd1;
+         window_reseting  <= (window_reset_cnt == 12'hFFF);
+      end
+   end
+   
+   localparam SFC_HEAD = 2'd0;
+   localparam SFC_TIME = 2'd1;
+   localparam SFC_BODY = 2'd2;
+   localparam SFC_DUMP = 2'd3;
+
+   always @(posedge clk)
+     if (reset | clear | window_reset) begin
+         last_seqnum_consumed <= 32'hFFFFFFFF;
+         sfc_state <= SFC_HEAD;
+     end else if (fc_tvalid & fc_tready)
+         case(sfc_state)
+         SFC_HEAD :
+            if(fc_tlast)
+               sfc_state <= SFC_HEAD; // Error. CHDR packet with only a header is an error.
+            else if(~fc_tdata[63])   // Is this NOT an extension context packet?
+               sfc_state <= SFC_DUMP; // Error. Only extension context packets should come in on this interface.
+            else if(fc_tdata[61])    // Does this packet have time?
+               sfc_state <= SFC_TIME;
+            else
+               sfc_state <= SFC_BODY;
+
+         SFC_TIME :
+            if(fc_tlast)
+               sfc_state <= SFC_HEAD; // Error, CHDR packet with only header and time is an error.
+            else
+               sfc_state <= SFC_BODY;
+         
+         SFC_BODY :
+         begin
+            last_seqnum_consumed <= fc_tdata[31:0]; // Sequence number is in lower 32bits.
+            if(fc_tlast)
+               sfc_state <= SFC_HEAD;
+            else
+               sfc_state <= SFC_DUMP; // Error. Not expecting any more data in a CHDR packet.
+         end
+
+         SFC_DUMP :   // shouldn't ever need to be here, this is an error condition
+           if(fc_tlast)
+             sfc_state <= SFC_HEAD;
+
+         endcase // case (sfc_state)
+
+   assign busy       = window_reseting;
+   assign fc_tready  = ~window_reseting;      // Consume FC if not in reset
+   assign out_tdata  = in_tdata;              // CHDR data flows through combinatorially.
+   assign out_tlast  = in_tlast;
+   assign in_tready  = (go ? out_tready : 1'b0) | window_reseting;
+   assign out_tvalid = (go & ~window_reseting) ? in_tvalid : 1'b0;
+
+   //
+   // Each time we receive the end of an IF data packet increment the current_seqnum.
+   // We bravely assume that no packets go missing...or at least that they will be detected elsewhere
+   // and then handled appropriately.
+   // The SEQNUM needs to be initialized every time we start a new stream. In new_rx_framer this is done
+   // as a side effect of writing a new SID value to the setting reg.
+   //
+   // By incrementing current_seqnum on the last signal we get the nice effect that packet flow is 
+   // always suspended between packets rather than within a packet.
+   //
+   always @(posedge clk)
+      if(reset | clear | window_reseting)
+         current_seqnum <= 32'd0;
+      else if (in_tvalid && in_tready && in_tlast)
+         current_seqnum <= current_seqnum + 32'd1;
+
+   always @(posedge clk)
+      if(reset | clear) begin
+         go <= 1'b0;
+      end else begin
+         if(~window_enable)
+            go <= 1'b1;
+         else
+            case(go)
+            1'b0:
+               // This test assumes the host is well behaved in sending good numbers for packets consumed
+               // and that current_seqnum increments always by 1 only.
+               // This way wraps are dealt with without a large logic penalty.
+               if (in_tvalid & (go_until_seqnum - current_seqnum != 0))
+                  go <= 1'b1;
+                  //if(in_tvalid & (go_until_seqnum > current_seqnum))  // FIXME will need to handle wrap of 32-bit seqnum
+
+            1'b1:
+               if(in_tvalid & in_tready & in_tlast)
+                  go <= 1'b0;
+            endcase // case (go)      
+      end
+
+endmodule // source_flow_control_legacy
diff --git a/fpga/usrp3/lib/packet_proc_200/source_flow_control_legacy_tb.v b/fpga/usrp3/lib/packet_proc_200/source_flow_control_legacy_tb.v
new file mode 100644
index 000000000..e8f7cccdf
--- /dev/null
+++ b/fpga/usrp3/lib/packet_proc_200/source_flow_control_legacy_tb.v
@@ -0,0 +1,254 @@
+//
+// Copyright 2016 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+`timescale 1ns/1ps
+
+module source_flow_control_legacy_tb();
+
+   reg clk    = 0;
+   reg reset  = 1;
+   
+   always #10 clk = ~clk;
+   
+   initial $dumpfile("source_flow_control_legacy_tb.vcd");
+   initial $dumpvars(0,source_flow_control_legacy_tb);
+
+   initial
+     begin
+	#1000 reset = 0;
+	#20000;
+	$finish;
+     end
+   
+   reg [63:0]  tdata;
+   wire [63:0] tdata_int;
+   reg 	       tlast;
+   wire        tlast_int;
+   reg 	       tvalid = 1'b0;
+   wire        tvalid_int;
+   wire        tready, tready_int;
+   
+   reg [63:0]  fc_tdata;
+   reg 	       fc_tlast, fc_tvalid;
+   wire        fc_tready;
+
+   wire [63:0] out_tdata;
+   wire        out_tlast, out_tready, out_tvalid;
+
+   wire [15:0] occ_in, occ_out;
+   reg 	       set_stb = 0;
+   reg [7:0]   set_addr;
+   reg [31:0]  set_data;
+   
+   
+   task send_fc_packet;
+      input [31:0] seqnum;
+      input [31:0] sid;
+      input always_go;
+      
+      begin
+	 @(posedge clk);
+	 fc_tlast <= 1'b0;
+	 fc_tdata <= { 1'b1, 1'b0, 1'b0, 1'b0, 12'hABC, 16'd4, sid };
+	 fc_tvalid <= 1;
+	 @(posedge clk);
+	 fc_tlast <= 1'b1;
+	 //fc_tdata <= { 52'h0,seqnum };
+	 fc_tdata <= { 31'h0,always_go, seqnum };
+	 @(posedge clk);
+	 fc_tvalid <= 0;	 
+	 @(posedge clk);
+      end
+   endtask // send_packet
+
+   task send_packet;
+      input ec;
+      input timed;
+      input [11:0] seqnum;
+      input [31:0] sid;
+      input [63:0] vtime;
+      input [15:0] addr;
+      input [31:0] data;
+      
+      begin
+	 // Send a packet
+	 @(posedge clk);
+	 tlast <= 1'b0;
+	 tdata <= { ec, 1'b0, timed, 1'b0, seqnum, timed ? 16'd6 : 16'd4, sid };
+	 tvalid <= 1;
+	 @(posedge clk);
+	 if(timed)
+	   begin
+	      tdata <= vtime;
+	      @(posedge clk);
+	   end
+	 tlast <= 1'b1;
+	 tdata <= { 16'h0, addr, data };
+	 @(posedge clk);
+	 tlast <= 1'b0;
+	 tvalid <= 0;	 
+	 @(posedge clk);
+      end
+   endtask // send_packet
+   
+   initial
+     begin
+	tvalid <= 1'b0;
+	while(reset)
+	  @(posedge clk);
+	@(posedge clk);
+	// Set flow control window to be 2
+	set_stb <= 1;
+	set_addr <= 0;
+	set_data <= 2;
+	@(posedge clk);
+	set_stb <= 0;
+	// ExtContext. Time. Seq=0, SID=DEAD_6789, Time=10
+	send_packet(1'b1,1'b1,12'h0,32'hDEAD_6789,64'h10,16'hB,32'hF00D_1234);
+	send_packet(1'b1,1'b1,12'h1,32'hDEAD_6789,64'h20,16'hC,32'hABCD_4321);
+	send_packet(1'b1,1'b1,12'h2,32'hDEAD_6789,64'h30,16'hC,32'hABCD_4321);
+	send_packet(1'b1,1'b1,12'h3,32'hDEAD_6789,64'h30,16'hC,32'hABCD_4321);
+	send_packet(1'b1,1'b1,12'h4,32'hDEAD_6789,64'h30,16'hC,32'hABCD_4321);
+	send_packet(1'b1,1'b1,12'h5,32'hDEAD_6789,64'h30,16'hC,32'hABCD_4321);
+	send_packet(1'b1,1'b1,12'h6,32'hDEAD_6789,64'h30,16'hC,32'hABCD_4321);
+	send_packet(1'b1,1'b1,12'h7,32'hDEAD_6789,64'h30,16'hC,32'hABCD_4321);
+	send_packet(1'b1,1'b1,12'h8,32'hDEAD_6789,64'h30,16'hC,32'hABCD_4321);
+	#500;
+	// Consumed 2 packets
+	send_fc_packet(32'd1,32'h3,1'b0);
+	#300;
+	// Consumed 1 packet
+	send_fc_packet(32'd2,32'h3,1'b0);
+	#500;	
+	// Consumed 2 packets
+	send_fc_packet(32'd4,32'h3,1'b0);
+	#400;	
+	// Send same SEQ ID again to test it causes no changes.
+	send_fc_packet(32'd4,32'h3,1'b0);
+	#300;
+	// Consumed 1 packet
+	send_fc_packet(32'd5,32'h3,1'b0);
+	#500;	
+	// Consumed 2 packets
+	send_fc_packet(32'd7,32'h3,1'b0);
+	#500;	
+	send_packet(1'b1,1'b1,12'h9,32'hDEAD_6789,64'h30,16'hC,32'hABCD_4321);
+	send_packet(1'b1,1'b1,12'hA,32'hDEAD_6789,64'h30,16'hC,32'hABCD_4321);
+	#300;
+	// Consumed 1 packet
+	send_fc_packet(32'd8,32'h3,1'b0);
+	//
+	// Now force internal sequence count to close to wrap value to test corner case
+	//
+	#100;
+	source_flow_control_legacy.current_seqnum <= 32'hFFFF_FFFC;
+	#100;
+	send_fc_packet(32'hFFFF_FFFA,32'h3,1'b0);
+	#100;
+	send_packet(1'b1,1'b1,12'hFFC,32'hDEAD_6789,64'h40,16'hC,32'hABCD_4321);
+	#200;
+	send_packet(1'b1,1'b1,12'hFFD,32'hDEAD_6789,64'h40,16'hC,32'hABCD_4321);
+	send_packet(1'b1,1'b1,12'hFFE,32'hDEAD_6789,64'h40,16'hC,32'hABCD_4321);
+	send_packet(1'b1,1'b1,12'hFFF,32'hDEAD_6789,64'h40,16'hC,32'hABCD_4321);
+	send_packet(1'b1,1'b1,12'h000,32'hDEAD_6789,64'h40,16'hC,32'hABCD_4321);
+	send_packet(1'b1,1'b1,12'h001,32'hDEAD_6789,64'h40,16'hC,32'hABCD_4321);
+	send_packet(1'b1,1'b1,12'h002,32'hDEAD_6789,64'h40,16'hC,32'hABCD_4321);
+	#200;
+	// Consumed 2 packets
+	send_fc_packet(32'hFFFF_FFFC,32'h3,1'b0);
+	#200;
+	// Consumed 2 packets
+	send_fc_packet(32'hFFFF_FFFE,32'h3,1'b0);
+	send_packet(1'b1,1'b1,12'h003,32'hDEAD_6789,64'h40,16'hC,32'hABCD_4321);
+	send_packet(1'b1,1'b1,12'h004,32'hDEAD_6789,64'h40,16'hC,32'hABCD_4321);
+	#200;
+	// Consumed 2 packets
+	send_fc_packet(32'h0,32'h3,1'b0);
+	#200;
+	// Consumed 2 packets
+	send_fc_packet(32'h2,32'h3,1'b0);
+	#500;
+	//
+	// Again force internal sequence count to close to wrap value to test new corner case
+	//
+	#100;
+	source_flow_control_legacy.current_seqnum <= 32'hFFFF_FFFC;
+	#100;
+	send_fc_packet(32'hFFFF_FFFA,32'h3,1'b0);
+	#100;
+	send_packet(1'b1,1'b1,12'hFFC,32'hDEAD_6789,64'h40,16'hC,32'hABCD_4321);
+	#200;
+	send_packet(1'b1,1'b1,12'hFFD,32'hDEAD_6789,64'h40,16'hC,32'hABCD_4321);
+	send_packet(1'b1,1'b1,12'hFFE,32'hDEAD_6789,64'h40,16'hC,32'hABCD_4321);
+	send_packet(1'b1,1'b1,12'hFFF,32'hDEAD_6789,64'h40,16'hC,32'hABCD_4321);
+	send_packet(1'b1,1'b1,12'h000,32'hDEAD_6789,64'h40,16'hC,32'hABCD_4321);
+	send_packet(1'b1,1'b1,12'h001,32'hDEAD_6789,64'h40,16'hC,32'hABCD_4321);
+	send_packet(1'b1,1'b1,12'h002,32'hDEAD_6789,64'h40,16'hC,32'hABCD_4321);
+	#200;
+	// Consumed 1 packets
+	send_fc_packet(32'hFFFF_FFFB,32'h3,1'b0);
+	#200;
+	// Consumed 1 packets
+	send_fc_packet(32'hFFFF_FFFC,32'h3,1'b0);
+	send_packet(1'b1,1'b1,12'h003,32'hDEAD_6789,64'h40,16'hC,32'hABCD_4321);
+	send_packet(1'b1,1'b1,12'h004,32'hDEAD_6789,64'h40,16'hC,32'hABCD_4321);
+	#200;
+	// Consumed 1 packets
+	send_fc_packet(32'hFFFF_FFFD,32'h3,1'b0);
+	#200;
+	// Consumed 1 packets
+	send_fc_packet(32'hFFFF_FFFE,32'h3,1'b0);
+	#200;
+	// Consumed 1 packets
+	send_fc_packet(32'hFFFF_FFFF,32'h3,1'b0);
+	#200;	
+	// Consumed 1 packets
+	send_fc_packet(32'h0,32'h3,1'b0);
+	#200;	
+	// Consumed 1 packets
+	send_fc_packet(32'h1,32'h3,1'b0);
+	#200;	
+	// Consumed 1 packets
+	send_fc_packet(32'h2,32'h3,1'b0);
+	#500;
+	
+
+
+	
+     end
+
+   axi_fifo #(.WIDTH(65), .SIZE(10)) fifo_in
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata({tlast,tdata}), .i_tvalid(tvalid), .i_tready(tready),
+      .o_tdata({tlast_int,tdata_int}), .o_tvalid(tvalid_int), .o_tready(tready_int),
+      .occupied(occ_in));
+
+   source_flow_control_legacy source_flow_control_legacy
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .fc_tdata(fc_tdata), .fc_tlast(fc_tlast), .fc_tvalid(fc_tvalid), .fc_tready(fc_tready),
+      .in_tdata(tdata_int), .in_tlast(tlast_int), .in_tvalid(tvalid_int), .in_tready(tready_int),
+      .out_tdata(out_tdata), .out_tlast(out_tlast), .out_tvalid(out_tvalid), .out_tready(out_tready)
+      );
+
+   wire [63:0] dump_tdata;
+   wire        dump_tlast, dump_tvalid, dump_tready;
+   
+   axi_fifo #(.WIDTH(65), .SIZE(10)) fifo_out
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata({out_tlast,out_tdata}), .i_tvalid(out_tvalid), .i_tready(out_tready),
+      .o_tdata({dump_tlast,dump_tdata}), .o_tvalid(dump_tvalid), .o_tready(dump_tready),
+      .occupied(occ_out));
+
+   assign dump_tready = 0;
+   
+   always @(posedge clk)
+     if(out_tvalid & out_tready)
+       begin
+	  $display("%x",out_tdata);
+	  if(out_tlast)
+	    $display("TLAST");
+       end
+endmodule // source_flow_control_legacy_tb
diff --git a/fpga/usrp3/lib/radio_200/Makefile.srcs b/fpga/usrp3/lib/radio_200/Makefile.srcs
new file mode 100644
index 000000000..04a28ad95
--- /dev/null
+++ b/fpga/usrp3/lib/radio_200/Makefile.srcs
@@ -0,0 +1,13 @@
+#
+# Copyright 2014 Ettus Research LLC
+# Copyright 2016 Ettus Research, a National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+##################################################
+# radio library
+##################################################
+RADIO_200_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/radio_200/, \
+./radio_legacy.v \
+))
diff --git a/fpga/usrp3/lib/radio_200/radio_legacy.v b/fpga/usrp3/lib/radio_200/radio_legacy.v
new file mode 100644
index 000000000..06970f446
--- /dev/null
+++ b/fpga/usrp3/lib/radio_200/radio_legacy.v
@@ -0,0 +1,496 @@
+//
+// Copyright 2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+// radio top level module for b200
+//  Contains all clock-rate DSP components, all radio and hardware controls and settings
+
+module radio_legacy
+  #(
+    parameter RADIO_FIFO_SIZE = 13,
+    parameter SAMPLE_FIFO_SIZE = 11,
+    parameter FP_GPIO = 0,
+    parameter NEW_HB_INTERP = 0,
+    parameter NEW_HB_DECIM = 0,
+    parameter SOURCE_FLOW_CONTROL = 0,
+    parameter USER_SETTINGS = 0,
+    parameter DEVICE = "SPARTAN6"
+  )
+  (input radio_clk, input radio_rst,
+   input [31:0] rx, output reg [31:0] tx,
+   input [31:0] fe_gpio_in, output [31:0] fe_gpio_out, output [31:0] fe_gpio_ddr,
+   input [9:0] fp_gpio_in, output [9:0] fp_gpio_out, output [9:0] fp_gpio_ddr,
+   input pps, input time_sync,
+   input bus_clk, input bus_rst,
+   input [63:0]  tx_tdata, input tx_tlast, input tx_tvalid, output tx_tready,
+   output [63:0] rx_tdata, output rx_tlast, output rx_tvalid, input rx_tready,
+   input [63:0]  ctrl_tdata, input ctrl_tlast, input ctrl_tvalid, output ctrl_tready,
+   output [63:0] resp_tdata, output resp_tlast, output resp_tvalid, input resp_tready,
+
+   output reg [63:0] vita_time_b,
+
+   output [63:0] debug
+   );
+
+
+   // ///////////////////////////////////////////////////////////////////////////////
+   // FIFO Interfacing to the bus clk domain
+   // in_tdata splits to tx_tdata and ctrl_tdata
+   // rx_tdata and resp_tdata get muxed to out_tdata
+   // Everything except rx flow control must cross in to radio_clk domain before further use
+   // _b signifies bus_clk domain, _r signifies radio_clk domain
+
+   wire [63:0] 	 ctrl_tdata_r;
+   wire 	 ctrl_tready_r, ctrl_tvalid_r;
+   wire 	 ctrl_tlast_r;
+
+   wire [63:0] 	 resp_tdata_r;
+   wire 	 resp_tready_r, resp_tvalid_r;
+   wire 	 resp_tlast_r;
+
+   wire [63:0] 	 rx_tdata_r;
+   wire 	 rx_tready_r, rx_tvalid_r;
+   wire 	 rx_tlast_r;
+
+   wire [63:0] 	 rx_err_tdata_r;
+   wire 	 rx_err_tready_r, rx_err_tvalid_r;
+   wire 	 rx_err_tlast_r;
+
+   wire [63:0]     rx_prefc_tdata_r;
+   wire   rx_prefc_tready_r, rx_prefc_tvalid_r;
+   wire   rx_prefc_tlast_r;
+
+   wire [63:0]     rx_postfc_tdata_r;
+   wire   rx_postfc_tready_r, rx_postfc_tvalid_r;
+   wire   rx_postfc_tlast_r;
+
+   wire [63:0] 	 tx_tdata_r;
+   wire 	 tx_tready_r, tx_tvalid_r;
+   wire 	 tx_tlast_r;
+
+   wire [63:0] 	 txresp_tdata, txresp_tdata_r;
+   wire 	 txresp_tready, txresp_tready_r, txresp_tvalid, txresp_tvalid_r;
+   wire 	 txresp_tlast, txresp_tlast_r;
+
+   wire [63:0] 	 rmux_tdata_r;
+   wire 	 rmux_tlast_r, rmux_tvalid_r, rmux_tready_r;
+
+   wire [31:0] 	 tx_idle;
+   wire [3:0] 	 ibs_state;
+   wire [63:0] 	 rx_tdata_int;
+   wire 	 rx_tready_int, rx_tvalid_int;
+   wire 	 rx_tlast_int;
+
+
+   axi_fifo_2clk #(.WIDTH(65), .SIZE(0/*minimal*/)) ctrl_fifo
+     (.reset(bus_rst),
+      .i_aclk(bus_clk), .i_tvalid(ctrl_tvalid), .i_tready(ctrl_tready), .i_tdata({ctrl_tlast, ctrl_tdata}),
+      .o_aclk(radio_clk), .o_tvalid(ctrl_tvalid_r), .o_tready(ctrl_tready_r), .o_tdata({ctrl_tlast_r, ctrl_tdata_r}));
+
+   axi_fifo_2clk #(.WIDTH(65), .SIZE(RADIO_FIFO_SIZE)) tx_fifo
+     (.reset(bus_rst),
+      .i_aclk(bus_clk), .i_tvalid(tx_tvalid), .i_tready(tx_tready), .i_tdata({tx_tlast, tx_tdata}),
+      .o_aclk(radio_clk), .o_tvalid(tx_tvalid_r), .o_tready(tx_tready_r), .o_tdata({tx_tlast_r, tx_tdata_r}));
+
+   axi_fifo_2clk #(.WIDTH(65), .SIZE(0/*minimal*/)) resp_fifo
+     (.reset(radio_rst),
+      .i_aclk(radio_clk), .i_tvalid(rmux_tvalid_r), .i_tready(rmux_tready_r), .i_tdata({rmux_tlast_r, rmux_tdata_r}),
+      .o_aclk(bus_clk), .o_tvalid(resp_tvalid), .o_tready(resp_tready), .o_tdata({resp_tlast, resp_tdata}));
+
+   axi_fifo_2clk #(.WIDTH(65), .SIZE(RADIO_FIFO_SIZE)) rx_fifo
+     (.reset(radio_rst),
+      .i_aclk(radio_clk), .i_tvalid(rx_tvalid_r), .i_tready(rx_tready_r), .i_tdata({rx_tlast_r, rx_tdata_r}),
+      .o_aclk(bus_clk), .o_tvalid(rx_tvalid_int), .o_tready(rx_tready_int), .o_tdata({rx_tlast_int, rx_tdata_int}));
+
+   axi_packet_gate #(.WIDTH(64), .SIZE(SAMPLE_FIFO_SIZE), .USE_AS_BUFF(0)) buffer_whole_pkt
+     (
+      .clk(bus_clk), .reset(bus_rst), .clear(1'b0),
+      .i_tdata(rx_tdata_int), .i_tlast(rx_tlast_int), .i_terror(1'b0), .i_tvalid(rx_tvalid_int), .i_tready(rx_tready_int),
+      .o_tdata(rx_tdata), .o_tlast(rx_tlast), .o_tvalid(rx_tvalid), .o_tready(rx_tready));
+
+   ///////////////////////////////////////////////////////////////////////////////////////
+   // Setting bus and controls
+
+   wire [63:0]    ctrl_tdata_proc;
+   wire           ctrl_tready_proc, ctrl_tvalid_proc;
+   wire           ctrl_tlast_proc;
+
+   localparam SR_LOOPBACK     = 8'd6;
+   localparam SR_SPI          = 8'd8;
+   localparam SR_ATR          = 8'd12; // thorugh 8'd18
+   localparam SR_TEST         = 8'd21;
+   localparam SR_CODEC_IDLE   = 8'd22;
+   localparam SR_READBACK     = 8'd32;
+   localparam SR_TX_CTRL      = 8'd64;
+   localparam SR_RX_CTRL      = 8'd96;
+   localparam SR_TIME         = 8'd128;
+   localparam SR_RX_FMT       = 8'd136;
+   localparam SR_TX_FMT       = 8'd138;
+   localparam SR_RX_DSP       = 8'd144;
+   localparam SR_TX_DSP       = 8'd184;
+   localparam SR_FP_GPIO      = 8'd200; // thorugh 8'd206
+   localparam SR_USER_SR_BASE = 8'd253;
+   localparam SR_USER_RB_ADDR = 8'd255;
+
+   wire           set_stb;
+   wire [7:0]     set_addr;
+   wire [31:0]    set_data;
+   wire [31:0]    test_readback;
+   wire [9:0] 	  fp_gpio_readback;
+   wire           run_rx, run_tx;
+   wire           rx_flow_ctrl_busy;
+
+   reg [63:0]     rb_data;
+   wire [2:0]     rb_addr;
+
+   wire [63:0] vita_time, vita_time_lastpps;
+   timekeeper #(.SR_TIME_HI(SR_TIME), .SR_TIME_LO(SR_TIME+1), .SR_TIME_CTRL(SR_TIME+2)) timekeeper
+     (.clk(radio_clk), .reset(radio_rst), .pps(pps), .sync_in(time_sync), .strobe(1'b1),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .vita_time(vita_time), .vita_time_lastpps(vita_time_lastpps),
+      .sync_out());
+
+   wire [31:0] debug_radio_ctrl_proc;
+   radio_ctrl_proc radio_ctrl_proc
+     (.clk(radio_clk), .reset(radio_rst), .clear(1'b0),
+      .ctrl_tdata(ctrl_tdata_proc), .ctrl_tlast(ctrl_tlast_proc), .ctrl_tvalid(ctrl_tvalid_proc), .ctrl_tready(ctrl_tready_proc),
+      .resp_tdata(resp_tdata_r), .resp_tlast(resp_tlast_r), .resp_tvalid(resp_tvalid_r), .resp_tready(resp_tready_r),
+      .vita_time(vita_time),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .ready(1'b1), .readback(rb_data),
+      .debug(debug_radio_ctrl_proc));
+
+   reg [63:0]     rb_data_user;
+generate
+   if (USER_SETTINGS == 1) begin
+      wire           set_stb_user;
+      wire [7:0]     set_addr_user;
+      wire [31:0]    set_data_user;
+      wire [7:0]     rb_addr_user;
+
+      user_settings #(.BASE(SR_USER_SR_BASE)) user_settings
+        (.clk(radio_clk), .rst(radio_rst),
+         .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+         .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user));
+
+      setting_reg #(.my_addr(SR_USER_RB_ADDR), .awidth(8), .width(8)) user_rb_addr
+        (.clk(radio_clk), .rst(radio_rst), .strobe(set_stb), .addr(set_addr), .in(set_data),
+         .out(rb_addr_user), .changed());
+
+      // ----------------------------------
+      // Enter user settings registers here
+      // ----------------------------------
+
+      // Example code for 32-bit settings registers and 64-bit readback registers
+      //
+      // To test this, modify the *_core.v file for your specific USRP and set
+      // USER_SETTINGS=1 for the parameters for the radio_legacy instantiation.
+      //
+      // You can then use the get_user_settings_iface() like this:
+      //
+      // auto usrp = multi_usrp::make("type=b200,enable_user_regs");
+      // auto regs = usrp->get_user_settings_iface(0);
+      // regs->poke32(0, 0xCAFE);
+      // regs->poke32(4, 0xBEEF);
+      // std::cout << boost::format("0x%016X") % regs->peek64(0) << std::endl;
+      wire [31:0] user_reg_0_value, user_reg_1_value;
+
+      setting_reg #(.my_addr(8'd0), .awidth(8), .width(32)) user_reg_0
+        (.clk(radio_clk), .rst(radio_rst), .strobe(set_stb_user), .addr(set_addr_user), .in(set_data_user),
+         .out(user_reg_0_value), .changed());
+
+      setting_reg #(.my_addr(8'd1), .awidth(8), .width(32)) user_reg_1
+        (.clk(radio_clk), .rst(radio_rst), .strobe(set_stb_user), .addr(set_addr_user), .in(set_data_user),
+         .out(user_reg_1_value), .changed());
+
+      always @* begin
+         case(rb_addr_user)
+            8'd0 : rb_data_user <= {user_reg_1_value, user_reg_0_value};
+            default : rb_data_user <= 64'd0;
+         endcase
+      end
+
+   end else begin    //for USER_SETTINGS == 1
+      always @* rb_data_user <= 64'd0;
+   end
+endgenerate
+
+   always @*
+     case(rb_addr)
+       3'd0 : rb_data <= { 32'b0, test_readback };
+       3'd1 : rb_data <= vita_time;
+       3'd2 : rb_data <= vita_time_lastpps;
+       3'd3 : rb_data <= {tx, rx};
+       3'd4 : rb_data <= {54'h0,fp_gpio_readback};
+       3'd5 : rb_data <= {59'h0,rx_flow_ctrl_busy,ibs_state[3:0]}; // Monitor state of RX state machine.
+//     3'd6 : rb_data <= <unused>;
+       3'd7 : rb_data <= rb_data_user;
+       default : rb_data <= 64'd0;
+     endcase // case (rb_addr)
+
+   //
+   // Sample VITA_TIME into the bus_clk domain for use by instrumentation.
+   //
+   wire [63:0] vita_time_b_int;
+   wire        vita_time_b_valid;
+
+    axi_fifo_2clk #(.WIDTH(64), .SIZE(0)) vita_time_fifo
+     (.reset(radio_rst),
+      .i_aclk(radio_clk), .i_tvalid(1'b1), .i_tready(), .i_tdata(vita_time),
+      .o_aclk(bus_clk), .o_tvalid(vita_time_b_valid), .o_tready(1'b1), .o_tdata(vita_time_b_int));
+
+   always @(posedge bus_clk)
+     if (vita_time_b_valid)
+       vita_time_b <= vita_time_b_int;
+
+   // Set this register to loop TX data directly to RX data.
+   setting_reg #(.my_addr(SR_LOOPBACK), .awidth(8), .width(1)) sr_loopback
+     (.clk(radio_clk), .rst(radio_rst), .strobe(set_stb), .addr(set_addr), .in(set_data),
+      .out(loopback), .changed());
+
+   setting_reg #(.my_addr(SR_TEST), .awidth(8), .width(32)) sr_test
+     (.clk(radio_clk), .rst(radio_rst), .strobe(set_stb), .addr(set_addr), .in(set_data),
+      .out(test_readback), .changed());
+
+   setting_reg #(.my_addr(SR_CODEC_IDLE), .awidth(8), .width(32)) sr_codec_idle
+     (.clk(radio_clk), .rst(radio_rst), .strobe(set_stb), .addr(set_addr), .in(set_data),
+      .out(tx_idle), .changed());
+
+   setting_reg #(.my_addr(SR_READBACK), .awidth(8), .width(3)) sr_rdback
+     (.clk(radio_clk), .rst(radio_rst), .strobe(set_stb), .addr(set_addr), .in(set_data),
+      .out(rb_addr), .changed());
+
+   //The fe_atr pins driven by this module are always configured as outputs so default
+   //the DDR (data direction register) to be all ones (outputs) so that the drive direction
+   //these lines does not change during/after resets.
+   gpio_atr #(.BASE(SR_ATR), .WIDTH(32), .FAB_CTRL_EN(0), .DEFAULT_DDR(32'hFFFFFFFF), .DEFAULT_IDLE(32'h00000000)) fe_gpio_atr
+     (.clk(radio_clk),.reset(radio_rst),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .rx(run_rx), .tx(run_tx),
+      .gpio_in(fe_gpio_in), .gpio_out(fe_gpio_out), .gpio_ddr(fe_gpio_ddr),
+      .gpio_out_fab(32'h00000000 /* no fabric control */), .gpio_sw_rb() );
+
+   generate
+      if (FP_GPIO != 0) begin: add_fp_gpio
+         gpio_atr #(.BASE(SR_FP_GPIO), .WIDTH(10), .FAB_CTRL_EN(0)) fp_gpio_atr
+            (.clk(radio_clk),.reset(radio_rst),
+            .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+            .rx(run_rx), .tx(run_tx),
+            .gpio_in(fp_gpio_in), .gpio_out(fp_gpio_out), .gpio_ddr(fp_gpio_ddr), 
+            .gpio_out_fab(10'h000 /* no fabric control */), .gpio_sw_rb(fp_gpio_readback));
+      end
+   endgenerate
+
+
+
+   ///////////////////////////////////////////////////////////////////////////////////////
+   // Source flow control
+
+generate
+   if (SOURCE_FLOW_CONTROL == 1) begin
+
+      localparam SID_PREFIX_CTRL = 2'd0;
+      localparam SID_PREFIX_FC   = 2'd1;
+
+      wire [63:0]    ctrl_tdata_fc;
+      wire           ctrl_tready_fc, ctrl_tvalid_fc;
+      wire           ctrl_tlast_fc;
+
+      wire [63:0]    ctrl_hdr;
+      wire [1:0]     ctrl_dest;
+
+      assign ctrl_dest = (ctrl_hdr[1:0] == SID_PREFIX_FC) ? 2'd1 : 2'd0;
+
+      axi_demux4 #(.ACTIVE_CHAN(4'b0011), .WIDTH(64), .BUFFER(1)) demux_proc_fc
+        (.clk(radio_clk), .reset(radio_rst), .clear(1'b0),
+         .header(ctrl_hdr), .dest(ctrl_dest),
+         .i_tdata(ctrl_tdata_r), .i_tlast(ctrl_tlast_r), .i_tvalid(ctrl_tvalid_r), .i_tready(ctrl_tready_r),                  //Input
+         .o0_tdata(ctrl_tdata_proc), .o0_tlast(ctrl_tlast_proc), .o0_tvalid(ctrl_tvalid_proc), .o0_tready(ctrl_tready_proc),  //Settings/Readback
+         .o1_tdata(ctrl_tdata_fc), .o1_tlast(ctrl_tlast_fc), .o1_tvalid(ctrl_tvalid_fc), .o1_tready(ctrl_tready_fc),          //Flow control
+         .o2_tdata(), .o2_tlast(), .o2_tvalid(), .o2_tready(1'b0),                                                            //Unused
+         .o3_tdata(), .o3_tlast(), .o3_tvalid(), .o3_tready(1'b0));                                                           //Unused
+
+      source_flow_control_legacy #(.BASE(SR_RX_CTRL+6)) rx_sfc
+        (.clk(radio_clk), .reset(radio_rst), .clear(1'b0),
+         .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+         .fc_tdata(ctrl_tdata_fc), .fc_tlast(ctrl_tlast_fc), .fc_tvalid(ctrl_tvalid_fc), .fc_tready(ctrl_tready_fc),                      //Flow control In
+         .in_tdata(rx_prefc_tdata_r), .in_tlast(rx_prefc_tlast_r), .in_tvalid(rx_prefc_tvalid_r), .in_tready(rx_prefc_tready_r),          //RX Input
+         .out_tdata(rx_postfc_tdata_r), .out_tlast(rx_postfc_tlast_r), .out_tvalid(rx_postfc_tvalid_r), .out_tready(rx_postfc_tready_r),  //RX Output
+         .busy(rx_flow_ctrl_busy));
+
+   end else begin    //for SOURCE_FLOW_CONTROL == 1
+
+      assign ctrl_tdata_proc  = ctrl_tdata_r;
+      assign ctrl_tlast_proc  = ctrl_tlast_r;
+      assign ctrl_tvalid_proc = ctrl_tvalid_r;
+      assign ctrl_tready_r    = ctrl_tready_proc;
+
+      assign rx_postfc_tdata_r   = rx_prefc_tdata_r;
+      assign rx_postfc_tlast_r   = rx_prefc_tlast_r;
+      assign rx_postfc_tvalid_r  = rx_prefc_tvalid_r;
+      assign rx_prefc_tready_r   = rx_postfc_tready_r;
+
+      assign rx_flow_ctrl_busy   = 1'b0;
+
+   end
+
+endgenerate
+
+   // /////////////////////////////////////////////////////////////////////////////////
+   //  TX Chain
+
+   wire [175:0] txsample_tdata;
+   wire 	txsample_tvalid, txsample_tready;
+   wire [31:0] 	sample_tx;
+   wire 	ack_or_error, packet_consumed;
+   wire [11:0] 	seqnum;
+   wire [63:0] 	error_code;
+   wire [31:0] 	sid;
+   wire [23:0] tx_fe_i, tx_fe_q;
+
+   wire [31:0] debug_tx_control;
+
+   always @(posedge radio_clk) begin
+      tx[31:16] <= (run_tx) ? tx_fe_i[23:8] : tx_idle[31:16];
+      tx[15:0]  <= (run_tx) ? tx_fe_q[23:8] : tx_idle[15:0];
+   end
+
+   wire [63:0] tx_tdata_i; wire tx_tlast_i, tx_tvalid_i, tx_tready_i;
+
+   new_tx_deframer tx_deframer
+     (.clk(radio_clk), .reset(radio_rst), .clear(1'b0),
+      .i_tdata(tx_tdata_i), .i_tlast(tx_tlast_i), .i_tvalid(tx_tvalid_i), .i_tready(tx_tready_i),
+      .sample_tdata(txsample_tdata), .sample_tvalid(txsample_tvalid), .sample_tready(txsample_tready),
+      .debug());
+
+   new_tx_control #(.BASE(SR_TX_CTRL)) tx_control
+     (.clk(radio_clk), .reset(radio_rst), .clear(1'b0),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .vita_time(vita_time),
+      .ack_or_error(ack_or_error), .packet_consumed(packet_consumed),
+      .seqnum(seqnum), .error_code(error_code), .sid(sid),
+      .sample_tdata(txsample_tdata), .sample_tvalid(txsample_tvalid), .sample_tready(txsample_tready),
+      .sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
+      .debug(debug_tx_control));
+
+   tx_responder #(.BASE(SR_TX_CTRL+2)) tx_responder
+     (.clk(radio_clk), .reset(radio_rst), .clear(1'b0),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .ack_or_error(ack_or_error), .packet_consumed(packet_consumed),
+      .seqnum(seqnum), .error_code(error_code), .sid(sid),
+      .vita_time(vita_time),
+      .o_tdata(txresp_tdata_r), .o_tlast(txresp_tlast_r), .o_tvalid(txresp_tvalid_r), .o_tready(txresp_tready_r));
+
+   wire [31:0]       debug_duc_chain;
+   duc_chain #(.BASE(SR_TX_DSP), .DSPNO(0), .WIDTH(24), .NEW_HB_INTERP(NEW_HB_INTERP),.DEVICE(DEVICE)) duc_chain
+     (.clk(radio_clk), .rst(radio_rst), .clr(1'b0),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .tx_fe_i(tx_fe_i),.tx_fe_q(tx_fe_q),
+      .sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
+      .debug(debug_duc_chain) );
+
+`ifdef DELETE_FORMAT_CONVERSION
+   assign 	     tx_tdata_i = tx_tdata_r;
+   assign 	     tx_tlast_i = tx_tlast_r;
+   assign 	     tx_tvalid_i = tx_tvalid_r;
+   assign 	     tx_tready_r = tx_tready_i;
+`else
+    chdr_xxxx_to_16sc_chain #(.BASE(SR_TX_FMT)) convert_xxxx_to_16sc
+     (.clk(radio_clk), .reset(radio_rst),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .i_tdata(tx_tdata_r), .i_tlast(tx_tlast_r), .i_tvalid(tx_tvalid_r), .i_tready(tx_tready_r),
+      .o_tdata(tx_tdata_i), .o_tlast(tx_tlast_i), .o_tvalid(tx_tvalid_i), .o_tready(tx_tready_i),
+      .debug());
+`endif // !`ifdef DELETE_FORMAT_CONVERSION
+
+   // /////////////////////////////////////////////////////////////////////////////////
+   //  RX Chain
+
+   wire 	full, eob_rx;
+   wire 	strobe_rx;
+   wire [31:0] 	sample_rx;
+   wire [31:0] 	  rx_sid;
+   wire [11:0] 	  rx_seqnum;
+   wire [63:0] rx_tdata_i; wire rx_tlast_i, rx_tvalid_i, rx_tready_i;
+
+   wire [31:0] debug_rx_framer;
+   new_rx_framer #(.BASE(SR_RX_CTRL+4),.SAMPLE_FIFO_SIZE(SAMPLE_FIFO_SIZE)) new_rx_framer
+     (.clk(radio_clk), .reset(radio_rst), .clear(1'b0),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .vita_time(vita_time),
+      .strobe(strobe_rx), .sample(sample_rx), .run(run_rx), .eob(eob_rx), .full(full),
+      .sid(rx_sid), .seqnum(rx_seqnum),
+      .o_tdata(rx_tdata_i), .o_tlast(rx_tlast_i), .o_tvalid(rx_tvalid_i), .o_tready(rx_tready_i),
+      .debug(debug_rx_framer));
+
+   wire [31:0]       debug_rx_control;
+   new_rx_control #(.BASE(SR_RX_CTRL)) new_rx_control
+     (.clk(radio_clk), .reset(radio_rst), .clear(1'b0),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .vita_time(vita_time),
+      .strobe(strobe_rx), .run(run_rx), .eob(eob_rx), .full(full),
+      .sid(rx_sid), .seqnum(rx_seqnum),
+      .err_tdata(rx_err_tdata_r), .err_tlast(rx_err_tlast_r), .err_tvalid(rx_err_tvalid_r), .err_tready(rx_err_tready_r),
+      .ibs_state(ibs_state),
+      .debug(debug_rx_control));
+
+   wire [31:0] 	     debug_ddc_chain;
+
+   // Digital Loopback TX -> RX (Pipeline immediately inside rx_frontend).
+   wire [31:0] 	     rx_fe = loopback ? tx : rx;
+
+   ddc_chain #(.BASE(SR_RX_DSP), .DSPNO(0), .WIDTH(24), .NEW_HB_DECIM(NEW_HB_DECIM), .DEVICE(DEVICE)) ddc_chain
+     (.clk(radio_clk), .rst(radio_rst), .clr(1'b0),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .rx_fe_i({rx_fe[31:16],8'd0}),.rx_fe_q({rx_fe[15:0],8'd0}),
+      .sample(sample_rx), .run(run_rx), .strobe(strobe_rx),
+      .debug(debug_ddc_chain) );
+
+`ifdef DELETE_FORMAT_CONVERSION
+   assign 	     rx_prefc_tdata_r = rx_tdata_i;
+   assign 	     rx_prefc_tlast_r = rx_tlast_i;
+   assign 	     rx_prefc_tvalid_r = rx_tvalid_i;
+   assign 	     rx_tready_i = rx_prefc_tready_r;
+`else
+   chdr_16sc_to_xxxx_chain #(.BASE(SR_RX_FMT)) convert_16sc_to_xxxx
+     (.clk(radio_clk), .reset(radio_rst),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .i_tdata(rx_tdata_i), .i_tlast(rx_tlast_i), .i_tvalid(rx_tvalid_i), .i_tready(rx_tready_i),
+      .o_tdata(rx_prefc_tdata_r), .o_tlast(rx_prefc_tlast_r), .o_tvalid(rx_prefc_tvalid_r), .o_tready(rx_prefc_tready_r),
+      .debug());
+`endif
+   // /////////////////////////////////////////////////////////////////////////////////
+   //  RX Channel Muxing
+
+   axi_mux4 #(.PRIO(1), .WIDTH(64), .BUFFER(1)) rx_mux
+     (.clk(radio_clk), .reset(radio_rst), .clear(1'b0),
+      .i0_tdata(rx_postfc_tdata_r), .i0_tlast(rx_postfc_tlast_r), .i0_tvalid(rx_postfc_tvalid_r), .i0_tready(rx_postfc_tready_r),
+      .i1_tdata(rx_err_tdata_r), .i1_tlast(rx_err_tlast_r), .i1_tvalid(rx_err_tvalid_r), .i1_tready(rx_err_tready_r),
+      .i2_tdata(64'h0), .i2_tlast(1'b0), .i2_tvalid(1'b0), .i2_tready(),
+      .i3_tdata(64'h0), .i3_tlast(1'b0), .i3_tvalid(1'b0), .i3_tready(),
+      .o_tdata(rx_tdata_r), .o_tlast(rx_tlast_r), .o_tvalid(rx_tvalid_r), .o_tready(rx_tready_r));
+
+   // /////////////////////////////////////////////////////////////////////////////////
+   //  Response Channel Muxing
+
+   axi_mux4 #(.PRIO(0), .WIDTH(64)) response_mux
+     (.clk(radio_clk), .reset(radio_rst), .clear(1'b0),
+      .i0_tdata(txresp_tdata_r), .i0_tlast(txresp_tlast_r), .i0_tvalid(txresp_tvalid_r), .i0_tready(txresp_tready_r),
+      .i1_tdata(resp_tdata_r), .i1_tlast(resp_tlast_r), .i1_tvalid(resp_tvalid_r), .i1_tready(resp_tready_r),
+      .i2_tdata(64'h0), .i2_tlast(1'b0), .i2_tvalid(1'b0), .i2_tready(),
+      .i3_tdata(64'h0), .i3_tlast(1'b0), .i3_tvalid(1'b0), .i3_tready(),
+      .o_tdata(rmux_tdata_r), .o_tlast(rmux_tlast_r), .o_tvalid(rmux_tvalid_r), .o_tready(rmux_tready_r));
+
+
+
+
+   /*******************************************************************
+    * Debug only logic below here.
+    ******************************************************************/
+ assign debug = 0;
+
+endmodule // radio_legacy
diff --git a/fpga/usrp3/lib/rfnoc/.gitignore b/fpga/usrp3/lib/rfnoc/.gitignore
new file mode 100644
index 000000000..8b13fff0f
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/.gitignore
@@ -0,0 +1,15 @@
+noc_shell_tb
+moving_sum_tb
+noc_dsp_flow_tb
+simple_axi_wrapper_tb
+simple_fir_tb
+schmidl_cox_tb
+coregen.log
+top_block.py
+test.dat
+output.dat
+isim
+#*
+axi_wrapper_tb
+*.dat
+*.sav
diff --git a/fpga/usrp3/lib/rfnoc/Makefile.srcs b/fpga/usrp3/lib/rfnoc/Makefile.srcs
new file mode 100644
index 000000000..cb97542ce
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/Makefile.srcs
@@ -0,0 +1,112 @@
+#
+# Copyright 2019 Ettus Research, A National Instruments Brand
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+##################################################
+# RFNoC Includes
+##################################################
+include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs
+include $(BASE_DIR)/../lib/rfnoc/crossbar/Makefile.srcs
+include $(BASE_DIR)/../lib/rfnoc/utils/Makefile.srcs
+include $(BASE_DIR)/../lib/rfnoc/xport/Makefile.srcs
+
+RFNOC_FRAMEWORK_SRCS = $(RFNOC_CORE_SRCS) $(RFNOC_XBAR_SRCS) $(RFNOC_UTIL_SRCS) $(RFNOC_XPORT_SRCS)
+
+##################################################
+# RFNoC Sources
+##################################################
+RFNOC_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/rfnoc/, \
+chdr_fifo_large.v \
+chdr_framer.v \
+chdr_framer_2clk.v \
+chdr_deframer.v \
+chdr_deframer_2clk.v \
+chdr_pkt_types.vh \
+axi_packet_mux.v \
+axi_wrapper.v \
+axi_bit_reduce.v \
+null_source.v \
+split_stream.v \
+split_stream_fifo.v \
+conj.v \
+delay_fifo.v \
+delay_type2.v \
+delay_type3.v \
+delay_type4.v \
+complex_to_magsq.v \
+phase_accum.v \
+complex_invert.v \
+periodic_framer.v \
+moving_sum.v \
+counter.v \
+ram_to_fifo.v \
+const.v \
+const_sreg.v \
+cmul.v \
+cadd.v \
+keep_one_in_n.v \
+vector_iir.v \
+addsub.v \
+packet_resizer.v \
+axi_pipe.v \
+multiply.v \
+mult.v \
+mult_add.v \
+mult_rc.v \
+mult_add_rc.v \
+fft_shift.v \
+axi_pipe_join.v \
+axi_pipe_mac.v \
+axi_round_and_clip_complex.v \
+axi_round_complex.v \
+axi_clip_complex.v \
+axi_join.v \
+axi_sync.v \
+split_complex.v \
+axi_round_and_clip.v \
+join_complex.v \
+axi_round.v \
+axi_clip.v \
+axi_clip_unsigned.v \
+axi_serializer.v \
+axi_deserializer.v \
+axi_packer.v \
+complex_to_mag_approx.v \
+file_source.v \
+fosphor/delay.v \
+fosphor/fifo_srl.v \
+fosphor/rng.v \
+fosphor/f15_avg.v \
+fosphor/f15_binmap.v \
+fosphor/f15_core.v \
+fosphor/f15_eoseq.v \
+fosphor/f15_histo_mem.v \
+fosphor/f15_line_mem.v \
+fosphor/f15_logpwr.v \
+fosphor/f15_maxhold.v \
+fosphor/f15_packetizer.v \
+fosphor/f15_rise_decay.v \
+fosphor/f15_wf_agg.v \
+fosphor/axi_logpwr.v \
+cvita_hdr_parser.v \
+cvita_hdr_encoder.v \
+cvita_hdr_decoder.v \
+cvita_hdr_modify.v \
+axi_async_stream.v \
+axi_rate_change.v \
+axi_tag_time.v \
+axi_drop_partial_packet.v \
+ddc.v \
+duc.v \
+cic_decimate.v \
+cic_interpolate.v \
+axi_fir_filter.v \
+fir_filter_slice.v \
+axi_fir_filter_dec.v \
+addsub.vhd \
+dds_freq_tune.v \
+dds_timed.v \
+datapath_gatekeeper.v \
+))
diff --git a/fpga/usrp3/lib/rfnoc/addsub.v b/fpga/usrp3/lib/rfnoc/addsub.v
new file mode 100644
index 000000000..46492bf8f
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/addsub.v
@@ -0,0 +1,41 @@
+//
+// Copyright 2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Demonstration of two input, two output block
+
+module addsub
+  #(parameter WIDTH = 16)
+   (input clk, input reset,
+    input [WIDTH*2-1:0] i0_tdata, input i0_tlast, input i0_tvalid, output i0_tready,
+    input [WIDTH*2-1:0] i1_tdata, input i1_tlast, input i1_tvalid, output i1_tready,
+    output [WIDTH*2-1:0] sum_tdata, output sum_tlast, output sum_tvalid, input sum_tready,
+    output [WIDTH*2-1:0] diff_tdata, output diff_tlast, output diff_tvalid, input diff_tready);
+
+   wire [WIDTH*4-1:0] 	 dummy;
+   wire [WIDTH*4-1:0] 	 int_tdata;
+   wire 		 int_tlast, int_tvalid, int_tready;
+
+   assign int_tvalid = i0_tvalid & i1_tvalid;
+   assign i0_tready = int_tvalid & int_tready;
+   assign i1_tready = int_tvalid & int_tready;
+
+   wire [WIDTH-1:0] 	 sum_a = i0_tdata[WIDTH*2-1:WIDTH] + i1_tdata[WIDTH*2-1:WIDTH];
+   wire [WIDTH-1:0] 	 diff_a = i0_tdata[WIDTH*2-1:WIDTH] - i1_tdata[WIDTH*2-1:WIDTH];
+   
+   wire [WIDTH-1:0] 	 sum_b = i0_tdata[WIDTH-1:0] + i1_tdata[WIDTH-1:0];
+   wire [WIDTH-1:0] 	 diff_b = i0_tdata[WIDTH-1:0] - i1_tdata[WIDTH-1:0];
+
+   assign int_tdata = { sum_a,sum_b,diff_a,diff_b };
+   assign int_tlast = i0_tlast;  // Follow first input.
+   
+   split_stream_fifo #(.WIDTH(4*WIDTH), .ACTIVE_MASK(4'b0011)) splitter
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata(int_tdata), .i_tlast(int_tlast), .i_tvalid(int_tvalid), .i_tready(int_tready),
+      .o0_tdata({sum_tdata,dummy[WIDTH*2-1:0]}), .o0_tlast(sum_tlast), .o0_tvalid(sum_tvalid), .o0_tready(sum_tready),
+      .o1_tdata({dummy[WIDTH*4-1:WIDTH*2],diff_tdata}), .o1_tlast(diff_tlast), .o1_tvalid(diff_tvalid), .o1_tready(diff_tready),
+      .o2_tready(1'b1), .o3_tready(1'b1));
+   
+endmodule // addsub
diff --git a/fpga/usrp3/lib/rfnoc/addsub.vhd b/fpga/usrp3/lib/rfnoc/addsub.vhd
new file mode 100644
index 000000000..3f93db028
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/addsub.vhd
@@ -0,0 +1,142 @@
+--
+-- Copyright 2015 National Instruments
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity addsub_vhdl is
+  generic (
+    width_g : natural := 16);
+  port (
+    clk_i : in std_ulogic;
+    rst_i : in std_ulogic;
+
+    i0_tdata  : in  std_ulogic_vector(width_g * 2 - 1 downto 0);
+    i0_tlast  : in  std_ulogic;
+    i0_tvalid : in  std_ulogic;
+    i0_tready : out std_ulogic;
+
+    i1_tdata  : in  std_ulogic_vector(width_g * 2 - 1 downto 0);
+    i1_tlast  : in  std_ulogic;
+    i1_tvalid : in  std_ulogic;
+    i1_tready : out std_ulogic;
+
+    sum_tdata  : out std_ulogic_vector(width_g * 2 - 1 downto 0);
+    sum_tlast  : out std_ulogic;
+    sum_tvalid : out std_ulogic;
+    sum_tready : in  std_ulogic;
+
+    diff_tdata  : out std_ulogic_vector(width_g * 2 - 1 downto 0);
+    diff_tlast  : out std_ulogic;
+    diff_tvalid : out std_ulogic;
+    diff_tready : in  std_ulogic);
+end entity addsub_vhdl;
+
+architecture rtl of addsub_vhdl is
+
+  component split_stream_fifo is
+    generic (
+      WIDTH       : natural := 16;
+      ACTIVE_MASK : std_ulogic_vector(3 downto 0);
+      FIFO_SIZE    : natural := 6);
+    port (
+      clk       : in std_ulogic;
+      reset     : in std_ulogic;
+      clear     : in std_ulogic;
+      i_tdata   : in std_ulogic_vector(WIDTH - 1 downto 0);
+      i_tlast   : in std_ulogic;
+      i_tvalid  : in std_ulogic;
+      i_tready  : out std_ulogic;
+      o0_tdata  : out std_ulogic_vector(WIDTH - 1 downto 0);
+      o0_tlast  : out std_ulogic;
+      o0_tvalid : out std_ulogic;
+      o0_tready : in  std_ulogic;
+      o1_tdata  : out std_ulogic_vector(WIDTH - 1 downto 0);
+      o1_tlast  : out std_ulogic;
+      o1_tvalid : out std_ulogic;
+      o1_tready : in  std_ulogic;
+      o2_tdata  : out std_ulogic_vector(WIDTH - 1 downto 0);
+      o2_tlast  : out std_ulogic;
+      o2_tvalid : out std_ulogic;
+      o2_tready : in  std_ulogic;
+      o3_tdata  : out std_ulogic_vector(WIDTH - 1 downto 0);
+      o3_tlast  : out std_ulogic;
+      o3_tvalid : out std_ulogic;
+      o3_tready : in  std_ulogic);
+  end component split_stream_fifo;
+
+  signal sum_a : unsigned(width_g - 1 downto 0);
+  signal sum_b : unsigned(width_g - 1 downto 0);
+
+  signal diff_a : unsigned(width_g - 1 downto 0);
+  signal diff_b : unsigned(width_g - 1 downto 0);
+
+  signal int_tdata  : std_ulogic_vector(width_g * 4 - 1 downto 0);
+  signal int_tlast  : std_ulogic;
+  signal int_tvalid : std_ulogic;
+  signal int_tready : std_ulogic;
+
+  signal sum  : std_ulogic_vector(width_g * 4 - 1 downto 0);
+  signal diff : std_ulogic_vector(width_g * 4 - 1 downto 0);
+
+begin
+
+  i0_tready <= int_tvalid and int_tready;
+  i1_tready <= int_tvalid and int_tready;
+
+  sum_a <= unsigned(i0_tdata(width_g * 2 - 1 downto width_g)) +
+           unsigned(i1_tdata(width_g * 2 - 1 downto width_g));
+
+  sum_b <= unsigned(i0_tdata(width_g - 1 downto 0)) +
+           unsigned(i1_tdata(width_g - 1 downto 0));
+
+  diff_a <= unsigned(i0_tdata(width_g * 2 - 1 downto width_g)) -
+            unsigned(i1_tdata(width_g * 2 - 1 downto width_g));
+
+  diff_b <= unsigned(i0_tdata(width_g - 1 downto 0)) -
+            unsigned(i1_tdata(width_g - 1 downto 0));
+
+  int_tdata <= std_ulogic_vector(sum_a) &
+               std_ulogic_vector(sum_b) &
+               std_ulogic_vector(diff_a) &
+               std_ulogic_vector(diff_b);
+
+  int_tlast  <= i0_tlast; -- Follow first input
+  int_tvalid <= i0_tvalid and i1_tvalid;
+
+  splitter : split_stream_fifo
+    generic map (
+      WIDTH       => 4 * width_g,
+      ACTIVE_MASK => "0011",
+      FIFO_SIZE    => 6)
+    port map (
+      clk       => clk_i,
+      reset     => rst_i,
+      clear     => '0',
+      i_tdata   => int_tdata,
+      i_tlast   => int_tlast,
+      i_tvalid  => int_tvalid,
+      i_tready  => int_tready,
+      o0_tdata  => sum,
+      o0_tlast  => sum_tlast,
+      o0_tvalid => sum_tvalid,
+      o0_tready => sum_tready,
+      o1_tdata  => diff,
+      o1_tlast  => diff_tlast,
+      o1_tvalid => diff_tvalid,
+      o1_tready => diff_tready,
+      o2_tdata  => open,
+      o2_tlast  => open,
+      o2_tvalid => open,
+      o2_tready => '1',
+      o3_tdata  => open,
+      o3_tlast  => open,
+      o3_tvalid => open,
+      o3_tready => '1');
+
+  sum_tdata  <= sum(sum'high downto width_g * 2);
+  diff_tdata <= diff(width_g * 2 - 1 downto diff'low);
+
+end architecture rtl;
diff --git a/fpga/usrp3/lib/rfnoc/axi_async_stream.v b/fpga/usrp3/lib/rfnoc/axi_async_stream.v
new file mode 100644
index 000000000..ee4746436
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/axi_async_stream.v
@@ -0,0 +1,204 @@
+//
+// Copyright 2016 Ettus Research
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// - Tracks and fills out header information for an axi stream that is
+//   asynchronous or does not have a 1:1 input / output ratio.
+// - User must pass through **ALL** received words and use the tkeep
+//   signal to flag which words to keep.
+// - This module is not intended to work with decimation / interpolation blocks.
+//
+// Open design questions:
+// - If a tkeep burst occurs between packet boundaries, an internal tlast is
+//   generated splitting the burst up into two (or more) packets. This is
+//   an easy way to make sure the packet sizes are bounded and the VITA
+//   time is correct. Is this desirable, since the downstream block
+//   will likely want the full burst and is then forced to aggregate packets?
+//
+
+module axi_async_stream #(
+  parameter WIDTH            = 32,
+  parameter HEADER_WIDTH     = 128,
+  parameter HEADER_FIFO_SIZE = 5,
+  parameter MAX_TICK_RATE    = 2**16-1)
+(
+  input clk,
+  input reset,
+  input clear,
+  input [15:0] src_sid,
+  input [15:0] dst_sid,
+  input [$clog2(MAX_TICK_RATE)-1:0] tick_rate,
+  output header_fifo_full,
+  // From AXI Wrapper
+  input [WIDTH-1:0] s_axis_data_tdata,
+  input [HEADER_WIDTH-1:0] s_axis_data_tuser,
+  input s_axis_data_tlast,
+  input s_axis_data_tvalid,
+  output s_axis_data_tready,
+  // To AXI Wrapper
+  output [WIDTH-1:0] m_axis_data_tdata,
+  output [HEADER_WIDTH-1:0] m_axis_data_tuser,
+  output m_axis_data_tlast,
+  output m_axis_data_tvalid,
+  input m_axis_data_tready,
+  // To User
+  output [WIDTH-1:0] o_tdata,
+  output o_tlast,
+  output o_tvalid,
+  input o_tready,
+  // From User
+  input [WIDTH-1:0] i_tdata,
+  input i_tlast,
+  input i_tvalid,
+  input i_tkeep,
+  output i_tready
+);
+
+  wire [WIDTH-1:0] i_reg_tdata;
+  wire i_reg_tvalid, i_reg_tlast, i_reg_tkeep, i_reg_tready;
+
+  reg [WIDTH-1:0] pipe_tdata;
+  reg pipe_tvalid, pipe_tlast, pipe_tkeep;
+  wire pipe_tready;
+
+  /********************************************************
+  ** Register user input
+  ** - The output logic in some cases needs to wait for
+  **   i_tvalid to assert before asserting i_tready.
+  **   However, users may implement logic that waits for
+  **   i_tready to assert before asserting i_tvalid.
+  **   Without this register, that would result in a
+  **   deadlock.
+  ** - Note: Technically, the user waiting for i_tready
+  **   violates the AXI specification that a master cannot
+  **   wait for ready from the slave. However, it is common
+  **   for users to accidentally break this rule and this is
+  **   a cheap workaround.
+  ********************************************************/
+  axi_fifo_flop #(.WIDTH(WIDTH+2)) axi_fifo_flop (
+    .clk(clk), .reset(reset), .clear(clear),
+    .i_tdata({i_tkeep,i_tlast,i_tdata}), .i_tvalid(i_tvalid), .i_tready(i_tready),
+    .o_tdata({i_reg_tkeep,i_reg_tlast,i_reg_tdata}), .o_tvalid(i_reg_tvalid), .o_tready(i_reg_tready));
+
+  /********************************************************
+  ** Keep track of headers for user
+  ********************************************************/
+  wire header_in_tready, header_in_tvalid, header_out_tvalid, header_out_tready;
+  wire [HEADER_WIDTH-1:0] header_in_tdata, header_out_tdata;
+
+  reg first_word = 1'b1;
+  reg [15:0] word_cnt;
+  reg [16+$clog2(MAX_TICK_RATE)-1:0] time_cnt; // 16 bit payload length + max tick rate increment
+
+  wire [63:0] vita_time;
+  wire [15:0] payload_length;
+
+  // Track first word to make sure header is read only once per packet
+  always @(posedge clk) begin
+    if (reset | clear) begin
+      first_word <= 1'b1;
+    end else begin
+      if (s_axis_data_tvalid & s_axis_data_tready) begin
+        if (s_axis_data_tlast) begin
+          first_word <= 1'b1;
+        end else if (first_word) begin
+          first_word <= 1'b0;
+        end
+      end
+    end
+  end
+
+  // Header FIFO
+  axi_fifo #(.WIDTH(HEADER_WIDTH), .SIZE(HEADER_FIFO_SIZE)) axi_fifo (
+    .clk(clk), .reset(reset), .clear(clear),
+    .i_tdata(header_in_tdata), .i_tvalid(header_in_tvalid), .i_tready(header_in_tready),
+    .o_tdata(header_out_tdata), .o_tvalid(header_out_tvalid), .o_tready(header_out_tready),
+    .space(), .occupied());
+
+  assign header_in_tdata   = s_axis_data_tuser;
+  assign header_in_tvalid  = s_axis_data_tvalid & o_tready & first_word;
+  assign header_out_tready = i_reg_tvalid & i_reg_tready & (word_cnt >= payload_length);
+  assign header_fifo_full  = ~header_in_tready;
+
+  // Track VITA time offset and word count for emptying header FIFO
+  always @(posedge clk) begin
+    if (reset | clear) begin
+      word_cnt       <= WIDTH/8;
+      time_cnt       <= 0;
+    end else begin
+      if (pipe_tvalid & pipe_tready) begin
+        if (word_cnt >= payload_length) begin
+          word_cnt <= WIDTH/8;
+          time_cnt <= 0;
+        end else begin
+          word_cnt <= word_cnt + WIDTH/8;
+          time_cnt <= time_cnt + tick_rate;
+        end
+      end
+    end
+  end
+
+  // Form output header
+  cvita_hdr_decoder cvita_hdr_decoder (
+    .header(header_out_tdata),
+    .pkt_type(), .eob(), .has_time(),
+    .seqnum(), .payload_length(payload_length),
+    .src_sid(), .dst_sid(),
+    .vita_time(vita_time));
+
+  cvita_hdr_modify cvita_hdr_modify (
+    .header_in(header_out_tdata),
+    .header_out(m_axis_data_tuser),
+    .use_pkt_type(1'b0),       .pkt_type(),
+    .use_has_time(1'b0),       .has_time(),
+    .use_eob(1'b0),            .eob(),
+    .use_seqnum(1'b0),         .seqnum(), // AXI Wrapper handles this
+    .use_length(1'b0),         .length(), // AXI Wrapper handles this
+    .use_payload_length(1'b0), .payload_length(),
+    .use_src_sid(1'b1),        .src_sid(src_sid),
+    .use_dst_sid(1'b1),        .dst_sid(dst_sid),
+    .use_vita_time(1'b1),      .vita_time(vita_time + time_cnt));
+
+  /********************************************************
+  ** Data to user from AXI Wrapper
+  ** - Throttles if header FIFO is full
+  ********************************************************/
+  assign o_tdata            = s_axis_data_tdata;
+  assign o_tvalid           = s_axis_data_tvalid & header_in_tready;
+  assign o_tlast            = s_axis_data_tlast;
+  assign s_axis_data_tready = o_tready & header_in_tready;
+
+  /********************************************************
+  ** Data from user to AXI Wrapper
+  ** - Handles asserting tlast
+  ** - Asserts tlast in three cases:
+  **   1) User asserts tlast
+  **   2) End of a burst of samples (i.e. when tkeep deasserts).
+  **   3) End of a packet, in case VITA is different between packets
+  ********************************************************/
+  wire ready;
+  always @(posedge clk) begin
+    if (reset | clear) begin
+      pipe_tdata      <= 'd0;
+      pipe_tvalid     <= 1'b0;
+      pipe_tlast      <= 1'b0;
+      pipe_tkeep      <= 1'b0;
+    end else begin
+      if (pipe_tready) begin
+        pipe_tdata    <= i_reg_tdata;
+        pipe_tvalid   <= i_reg_tvalid;
+        pipe_tlast    <= i_reg_tlast;
+        pipe_tkeep    <= i_reg_tkeep;
+      end
+    end
+  end
+
+  assign pipe_tready        = ~pipe_tvalid | (m_axis_data_tready & header_out_tvalid & (i_reg_tvalid | (m_axis_data_tvalid & m_axis_data_tlast)));
+  assign i_reg_tready       = pipe_tready;
+  assign m_axis_data_tdata  = pipe_tdata;
+  assign m_axis_data_tvalid = pipe_tvalid & pipe_tkeep & (i_reg_tvalid | m_axis_data_tlast) & header_out_tvalid;
+  assign m_axis_data_tlast  = pipe_tlast | (i_reg_tvalid & ~i_reg_tkeep) | (word_cnt >= payload_length);
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/axi_bit_reduce.v b/fpga/usrp3/lib/rfnoc/axi_bit_reduce.v
new file mode 100644
index 000000000..cb6290ff0
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/axi_bit_reduce.v
@@ -0,0 +1,27 @@
+//
+// Copyright Ettus Research, 2014
+// Copyright 2014 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// no logic, just wires
+
+module axi_bit_reduce
+  #(parameter WIDTH_IN=48,
+    parameter WIDTH_OUT=25,
+    parameter DROP_TOP=6,
+    parameter VECTOR_WIDTH=1)   // vector_width = 2 for complex, 1 for real
+   (input [VECTOR_WIDTH*WIDTH_IN-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
+    output [VECTOR_WIDTH*WIDTH_OUT-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready);
+
+   genvar 				i;
+   generate
+      for(i=0; i<VECTOR_WIDTH; i=i+1)
+	assign o_tdata[(i+1)*WIDTH_OUT-1:i*WIDTH_OUT] = i_tdata[(i+1)*WIDTH_IN-DROP_TOP-1:i*WIDTH_IN+(WIDTH_IN-WIDTH_OUT)-DROP_TOP];
+   endgenerate
+
+   assign o_tlast = i_tlast;
+   assign o_tvalid = i_tvalid;
+   assign i_tready = o_tready;
+
+endmodule // axi_bit_sel
diff --git a/fpga/usrp3/lib/rfnoc/axi_clip.v b/fpga/usrp3/lib/rfnoc/axi_clip.v
new file mode 100644
index 000000000..4ae776f95
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/axi_clip.v
@@ -0,0 +1,35 @@
+//
+// Copyright 2016 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module axi_clip
+  #(parameter WIDTH_IN=24,
+    parameter WIDTH_OUT=16,
+    parameter FIFOSIZE=0)  // leave at 0 for a normal single flop
+   (input clk, input reset,
+    input [WIDTH_IN-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
+    output [WIDTH_OUT-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready);
+
+   generate
+     if (WIDTH_IN == WIDTH_OUT) begin
+      assign o_tdata  = i_tdata;
+      assign o_tlast  = i_tlast;
+      assign o_tvalid = i_tvalid;
+      assign i_tready = o_tready;
+     end else begin
+       wire overflow = |i_tdata[WIDTH_IN-1:WIDTH_OUT-1] & ~(&i_tdata[WIDTH_IN-1:WIDTH_OUT-1]);
+       wire [WIDTH_OUT-1:0] out = overflow ?
+         (i_tdata[WIDTH_IN-1] ? {1'b1,{(WIDTH_OUT-1){1'b0}}} : {1'b0,{(WIDTH_OUT-1){1'b1}}}) :
+          i_tdata[WIDTH_OUT-1:0];
+
+       axi_fifo #(.WIDTH(WIDTH_OUT+1), .SIZE(FIFOSIZE)) flop
+         (.clk(clk), .reset(reset), .clear(1'b0),
+          .i_tdata({i_tlast, out}), .i_tvalid(i_tvalid), .i_tready(i_tready),
+          .o_tdata({o_tlast, o_tdata}), .o_tvalid(o_tvalid), .o_tready(o_tready),
+          .occupied(), .space());
+     end
+   endgenerate
+
+endmodule // axi_clip
diff --git a/fpga/usrp3/lib/rfnoc/axi_clip_complex.v b/fpga/usrp3/lib/rfnoc/axi_clip_complex.v
new file mode 100644
index 000000000..439345990
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/axi_clip_complex.v
@@ -0,0 +1,43 @@
+//
+// Copyright 2016 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module axi_clip_complex #(
+  parameter WIDTH_IN  = 24,
+  parameter WIDTH_OUT = 16,
+  parameter FIFOSIZE  = 0)  // leave at 0 for a single flop
+(
+  input clk, input reset,
+  input [2*WIDTH_IN-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
+  output [2*WIDTH_OUT-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready
+);
+
+  wire [WIDTH_IN-1:0]  ii_tdata, iq_tdata;
+  wire                 ii_tlast, ii_tvalid, ii_tready, iq_tlast, iq_tvalid, iq_tready;
+
+  wire [WIDTH_OUT-1:0] oi_tdata, oq_tdata;
+  wire                 oi_tlast, oi_tvalid, oi_tready, oq_tlast, oq_tvalid, oq_tready;
+
+  split_complex #(.WIDTH(WIDTH_IN)) split_complex (
+    .i_tdata(i_tdata), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready),
+    .oi_tdata(ii_tdata), .oi_tlast(ii_tlast), .oi_tvalid(ii_tvalid), .oi_tready(ii_tready),
+    .oq_tdata(iq_tdata), .oq_tlast(iq_tlast), .oq_tvalid(iq_tvalid), .oq_tready(iq_tready));
+
+  axi_clip #(.WIDTH_IN(WIDTH_IN), .WIDTH_OUT(WIDTH_OUT), .FIFOSIZE(FIFOSIZE)) axi_clip_i (
+    .clk(clk), .reset(reset),
+    .i_tdata(ii_tdata), .i_tlast(ii_tlast), .i_tvalid(ii_tvalid), .i_tready(ii_tready),
+    .o_tdata(oi_tdata), .o_tlast(oi_tlast), .o_tvalid(oi_tvalid), .o_tready(oi_tready));
+
+  axi_clip #(.WIDTH_IN(WIDTH_IN), .WIDTH_OUT(WIDTH_OUT), .FIFOSIZE(FIFOSIZE)) axi_clip_q (
+    .clk(clk), .reset(reset),
+    .i_tdata(iq_tdata), .i_tlast(iq_tlast), .i_tvalid(iq_tvalid), .i_tready(iq_tready),
+    .o_tdata(oq_tdata), .o_tlast(oq_tlast), .o_tvalid(oq_tvalid), .o_tready(oq_tready));
+
+  join_complex #(.WIDTH(WIDTH_OUT)) join_complex (
+    .ii_tdata(oi_tdata), .ii_tlast(oi_tlast), .ii_tvalid(oi_tvalid), .ii_tready(oi_tready),
+    .iq_tdata(oq_tdata), .iq_tlast(oq_tlast), .iq_tvalid(oq_tvalid), .iq_tready(oq_tready),
+    .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready));
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/axi_clip_unsigned.v b/fpga/usrp3/lib/rfnoc/axi_clip_unsigned.v
new file mode 100644
index 000000000..4ad393693
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/axi_clip_unsigned.v
@@ -0,0 +1,24 @@
+//
+// Copyright 2015, Ettus Research
+//
+// Reduces bit width by removing MSBs. Input assumed to be unsigned.
+
+module axi_clip_unsigned
+  #(parameter WIDTH_IN=24,
+    parameter WIDTH_OUT=16,
+    parameter FIFOSIZE=0)  // leave at 0 for a normal single flop
+   (input clk, input reset,
+    input [WIDTH_IN-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
+    output [WIDTH_OUT-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready);
+
+   wire overflow = |i_tdata[WIDTH_IN-1:WIDTH_OUT];
+
+   wire [WIDTH_OUT-1:0] out = overflow ? {1'b0,{(WIDTH_OUT-1){1'b1}}} : i_tdata[WIDTH_OUT-1:0];
+
+   axi_fifo #(.WIDTH(WIDTH_OUT+1), .SIZE(FIFOSIZE)) flop
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata({i_tlast, out}), .i_tvalid(i_tvalid), .i_tready(i_tready),
+      .o_tdata({o_tlast, o_tdata}), .o_tvalid(o_tvalid), .o_tready(o_tready),
+      .occupied(), .space());
+
+endmodule // clip
diff --git a/fpga/usrp3/lib/rfnoc/axi_deserializer.v b/fpga/usrp3/lib/rfnoc/axi_deserializer.v
new file mode 100644
index 000000000..ba2736315
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/axi_deserializer.v
@@ -0,0 +1,62 @@
+//
+// Copyright 2015 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module axi_deserializer #(
+  parameter WIDTH = 32)
+(
+  input clk, input rst, input reverse_output,
+  input i_tdata, input  i_tlast, input i_tvalid,  output i_tready,
+  output [WIDTH-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready
+);
+
+  reg flop_tlast, flop_tlast_latch;
+  reg  [WIDTH-1:0] flop_tdata;
+  wire [WIDTH-1:0] flop_tdata_reverse, flop_tdata_int;
+  reg flop_tvalid;
+  reg [$clog2(WIDTH)-1:0] i;
+
+  always @(posedge clk) begin
+    if (rst) begin
+      flop_tdata       <= 'd0;
+      flop_tvalid      <= 1'b0;
+      flop_tlast       <= 1'b0;
+      flop_tlast_latch <= 1'b0;
+      i                <= WIDTH-1;
+    end else begin
+      flop_tvalid      <= 1'b0;
+      if (i_tvalid & i_tready) begin
+        flop_tdata[i]  <= i_tdata;
+        if (i_tlast) begin
+          flop_tlast_latch <= 1'b1;
+        end
+        if (i == 0) begin
+          flop_tvalid      <= 1'b1;
+          flop_tlast       <= flop_tlast_latch;
+          flop_tlast_latch <= 1'b0;
+          i                <= WIDTH-1;
+        end else begin
+          i                <= i - 1;
+        end
+      end
+    end
+  end
+
+  // Reverse flop_tdata
+  genvar k;
+  generate
+    for (k = 0; k < WIDTH; k = k + 1) assign flop_tdata_reverse[WIDTH-1-k] = flop_tdata;
+  endgenerate
+
+  assign flop_tdata_int = reverse_output ? flop_tdata_reverse : flop_tdata;
+
+  axi_fifo_flop2 #(.WIDTH(WIDTH)) axi_fifo_flop (
+    .clk(clk), .reset(rst), .clear(1'b0),
+    .i_tdata({flop_tlast,flop_tdata_int}), .i_tvalid(flop_tvalid), .i_tready(i_tready),
+    .o_tdata({o_tlast,o_tdata}),       .o_tvalid(o_tvalid),    .o_tready(o_tready),
+    .space(), .occupied());
+
+endmodule
\ No newline at end of file
diff --git a/fpga/usrp3/lib/rfnoc/axi_drop_partial_packet.v b/fpga/usrp3/lib/rfnoc/axi_drop_partial_packet.v
new file mode 100644
index 000000000..a4dbae654
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/axi_drop_partial_packet.v
@@ -0,0 +1,140 @@
+//
+// Copyright 2016 Ettus Research
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Drop packets that are larger or smaller than the allowed packet size.
+//
+
+module axi_drop_partial_packet #(
+  parameter WIDTH = 32,
+  parameter MAX_PKT_SIZE = 1024,
+  parameter HOLD_LAST_WORD = 0,       // Hold off sending last word until next full packet arrives
+  parameter SR_PKT_SIZE_ADDR = 1
+)(
+  input clk, input reset, input clear,
+  input flush,  // If using HOLD_LAST_WORD, will forcibly release all words in FIFO
+  input set_stb, input [7:0] set_addr, input [31:0] set_data,
+  input [WIDTH-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
+  output [WIDTH-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready
+);
+
+  generate
+    // Packet size of 1 means it is impossible to form a partial packet, so this module does nothing...
+    if (MAX_PKT_SIZE == 1) begin
+      assign o_tdata  = i_tdata;
+      assign o_tlast  = i_tlast;
+      assign o_tvalid = i_tvalid;
+      assign i_tready = o_tready;
+    // All other packet sizes
+    end else begin
+      // Settings register
+      wire [$clog2(MAX_PKT_SIZE+1)-1:0] sr_pkt_size;
+      setting_reg #(.my_addr(SR_PKT_SIZE_ADDR), .width($clog2(MAX_PKT_SIZE+1)), .at_reset(1)) set_pkt_size (
+        .clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
+        .out(sr_pkt_size), .changed());
+
+      // Do not change n unless block is not active
+      reg active;
+      reg [$clog2(MAX_PKT_SIZE+1)-1:0] pkt_size = 1;
+      always @(posedge clk) begin
+        if (reset | clear) begin
+          active <= 1'b0;
+        end else begin
+          if (i_tready & i_tvalid) begin
+            active <= 1'b1;
+          end
+        end
+        if (clear | ~active) begin
+          pkt_size <= (sr_pkt_size == 0) ? 1 : sr_pkt_size;
+        end
+      end
+
+      wire [WIDTH-1:0] int_tdata;
+      wire int_tlast, int_tvalid, int_tready;
+      wire i_tlast_int, i_terror;
+
+      reg small_pkt, large_pkt;
+      wire hold_last_sample;
+      reg release_last;
+      reg [$clog2(MAX_PKT_SIZE+1)-1:0] in_cnt;
+      reg [15:0] in_pkt_cnt, in_pkt_cnt_hold, out_pkt_cnt;
+      always @(posedge clk) begin
+        if (reset | clear) begin
+          small_pkt             <= 1'b0;
+          large_pkt             <= 1'b0;
+          release_last          <= 1'b0;
+          in_cnt                <= 1;
+          in_pkt_cnt            <= 0;
+          in_pkt_cnt_hold       <= 0;
+          out_pkt_cnt           <= 0;
+        end else begin
+          if (i_tvalid & i_tready) begin
+            if (in_cnt == pkt_size | i_tlast_int) begin
+              in_cnt     <= 1;
+            end else begin
+              in_cnt     <= in_cnt + 1;
+            end
+          end
+          if (pkt_size == 1) begin
+            small_pkt      <= 1'b0;
+            large_pkt      <= 1'b0;
+          end else begin
+            if (i_tvalid & i_tready) begin
+              if ((in_cnt == pkt_size-1'b1) & ~i_tlast) begin
+                small_pkt  <= 1'b0;
+              end else begin
+                small_pkt  <= 1'b1;
+              end
+              if ((in_cnt == pkt_size) & ~i_tlast) begin
+                large_pkt  <= 1'b1;
+              end
+              if (large_pkt) begin
+                large_pkt  <= 1'b0;
+              end
+            end
+          end
+          if (i_tvalid & i_tready & i_tlast & ~i_terror) begin
+            in_pkt_cnt     <= in_pkt_cnt + 1'b1;
+          end
+          if (int_tvalid & int_tready & int_tlast & ~hold_last_sample) begin
+            out_pkt_cnt    <= out_pkt_cnt + 1'b1;
+          end
+          if ((i_tvalid & i_tready & i_terror) | flush) begin
+            release_last         <= 1'b1;
+            in_pkt_cnt_hold      <= in_pkt_cnt;
+          end else if (in_pkt_cnt_hold == out_pkt_cnt) begin
+            release_last         <= 1'b0;
+          end
+        end
+      end
+
+      assign hold_last_sample = ((in_pkt_cnt == out_pkt_cnt) | ((in_pkt_cnt == out_pkt_cnt+1) & ~release_last)) & (pkt_size != 1);
+
+      assign i_tlast_int = i_tlast | large_pkt;
+      assign i_terror    = i_tlast & i_tvalid & (small_pkt | large_pkt);
+
+      // FIFO with ability to rewind write pointer back if input packet is flagged as bad
+      axi_packet_gate #(.WIDTH(WIDTH+1), .SIZE($clog2(MAX_PKT_SIZE+1)), .USE_AS_BUFF(1)) pkt_gate_i (
+        .clk(clk), .reset(reset), .clear(clear),
+        .i_tdata({i_tlast,i_tdata}), .i_tvalid(i_tvalid), .i_tlast(i_tlast_int), .i_terror(i_terror), .i_tready(i_tready),
+        .o_tdata({int_tlast,int_tdata}), .o_tvalid(int_tvalid), .o_tlast(), .o_tready(int_tready & ~(hold_last_sample & int_tlast)));
+
+      // Generate output register to hold on to last word
+      if (HOLD_LAST_WORD) begin
+        axi_fifo_flop2 #(.WIDTH(WIDTH+1)) axi_fifo_flop2 (
+          .clk(clk), .reset(reset), .clear(clear),
+          .i_tdata({int_tlast,int_tdata}), .i_tvalid(int_tvalid & ~(hold_last_sample & int_tlast)), .i_tready(int_tready),
+          .o_tdata({o_tlast,o_tdata}), .o_tvalid(o_tvalid), .o_tready(o_tready),
+          .space(), .occupied());
+      end else begin
+        assign o_tdata    = int_tdata;
+        assign o_tlast    = int_tlast;
+        assign o_tvalid   = int_tvalid;
+        assign int_tready = o_tready;
+      end
+    end
+  endgenerate
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/axi_fir_filter.v b/fpga/usrp3/lib/rfnoc/axi_fir_filter.v
new file mode 100644
index 000000000..4fffab8af
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/axi_fir_filter.v
@@ -0,0 +1,307 @@
+//
+// Copyright 2017 Ettus Research
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Parameterized FIR filter with AXI stream interface.
+// Has several optimizations to resource utilization such as
+// using half the number of DSP slices for symmetric coefficients,
+// skipping coefficients that are always set to zero, and using
+// internal DSP slice registers to hold coefficients.
+//
+// For the most efficient DSP slice inference use these settings:
+// - IN_WIDTH < 25, COEFF_WIDTH < 18, ACCUM_WIDTH < 48
+//
+// Parameters:
+//   IN_WIDTH                 - Input width
+//   COEFF_WIDTH              - Coefficient width
+//   OUT_WIDTH                - Output width
+//   NUM_COEFFS               - Number of coefficients / taps
+//   CLIP_BITS                - If IN_WIDTH != OUT_WIDTH, number of MSBs to drop
+//   ACCUM_WIDTH              - Accumulator width
+//   COEFFS_VEC               - Vector of NUM_COEFFS values each of width COEFF_WIDTH to
+//                              initialize coeffs. Defaults to an impulse.
+//   RELOADABLE_COEFFS        - Enable (1) or disable (0) reloading coefficients at runtime (via reload bus)
+//   BLANK_OUTPUT             - Disable (1) or enable (0) output when filling internal pipeline
+//   SYMMETRIC_COEFFS         - Reduce multiplier usage by approx half if coefficients are symmetric
+//   SKIP_ZERO_COEFFS         - Reduce multiplier usage by assuming zero valued coefficients in
+//                              DEFAULT_COEFFS are always zero. Useful for halfband filters.
+//   USE_EMBEDDED_REGS_COEFFS - Reduce register usage by only using embedded registers in DSP slices.
+//                              Updating taps while streaming will cause temporary output corruption!
+//
+// Notes:
+// - If using USE_EMBEDDED_REGS_COEFFS, coefficients must be written at least once as COEFFS_VEC is ignored!
+// - If using SYMMETRIC_COEFFS, only send half the coeffients! i.e. NUM_COEFFS = 11, send the first 6.
+//
+module axi_fir_filter #(
+  parameter IN_WIDTH                  = 16,
+  parameter COEFF_WIDTH               = 16,
+  parameter OUT_WIDTH                 = 16,
+  parameter NUM_COEFFS                = 41,
+  parameter CLIP_BITS                 = $clog2(NUM_COEFFS),
+  parameter ACCUM_WIDTH               = IN_WIDTH+COEFF_WIDTH+$clog2(NUM_COEFFS)-1,
+  parameter [NUM_COEFFS*COEFF_WIDTH-1:0] COEFFS_VEC =
+      {{1'b0,{(COEFF_WIDTH-1){1'b1}}},{(COEFF_WIDTH*(NUM_COEFFS-1)){1'b0}}},
+  parameter RELOADABLE_COEFFS         = 1,
+  parameter BLANK_OUTPUT              = 1,
+  // Optimizations
+  parameter SYMMETRIC_COEFFS          = 1,
+  parameter SKIP_ZERO_COEFFS          = 0,
+  parameter USE_EMBEDDED_REGS_COEFFS  = 1
+)(
+  input clk,
+  input reset,
+  input clear,
+  input [IN_WIDTH-1:0] s_axis_data_tdata,
+  input s_axis_data_tlast,
+  input s_axis_data_tvalid,
+  output s_axis_data_tready,
+  output [OUT_WIDTH-1:0] m_axis_data_tdata,
+  output m_axis_data_tlast,
+  output m_axis_data_tvalid,
+  input m_axis_data_tready,
+  input [COEFF_WIDTH-1:0] s_axis_reload_tdata,
+  input s_axis_reload_tvalid,
+  input s_axis_reload_tlast,
+  output s_axis_reload_tready
+);
+
+  localparam NUM_SLICES       = SYMMETRIC_COEFFS ?
+                                    NUM_COEFFS/2 + NUM_COEFFS[0] :  // Manual round up, Vivado complains when using $ceil()
+                                    NUM_COEFFS;
+  localparam ODD_LEN          = NUM_COEFFS[0];
+  localparam PIPELINE_DELAY   = NUM_SLICES+4; // +4 pipeline depth in fir_filter_slice.v
+
+  wire [ACCUM_WIDTH-1:0] m_axis_data_tdata_int;
+  wire m_axis_data_tvalid_int, m_axis_data_tready_int, m_axis_data_tlast_int;
+
+  ///////////////////////////////////////////////////////
+  //
+  // Coefficient loading / reloading
+  //
+  ///////////////////////////////////////////////////////
+  reg [COEFF_WIDTH-1:0] coeffs[0:NUM_SLICES-1];
+  reg coeff_load_stb = 1'b1;
+  generate
+    integer k;
+    if (RELOADABLE_COEFFS) begin
+      // Use DSP slice registers to hold coefficients. While loading
+      // coefficients, input sample data should be throttled if corrupted
+      // output samples are unacceptable.
+      if (USE_EMBEDDED_REGS_COEFFS) begin
+        always @(*) begin
+          coeff_load_stb <= s_axis_reload_tvalid & s_axis_reload_tready;
+        end
+      // Use shift register to hold coefficients. Coefficients are loaded
+      // into fir filter slice on tlast.
+      end else begin
+        always @(posedge clk) begin
+          if (reset | clear) begin
+            for (k = 0; k < NUM_SLICES; k = k + 1) begin
+              coeffs[k] <= COEFFS_VEC[COEFF_WIDTH*k +: COEFF_WIDTH];
+            end
+            // Initialize coefficients at reset
+            coeff_load_stb <= 1'b1;
+          end else begin
+            if (s_axis_reload_tvalid & s_axis_reload_tready) begin
+              for (k = NUM_SLICES-1; k > 0; k = k - 1) begin
+                coeffs[k-1] <= coeffs[k];
+              end
+              coeffs[NUM_SLICES-1] <= s_axis_reload_tdata;
+            end
+            coeff_load_stb <= s_axis_reload_tvalid & s_axis_reload_tready & s_axis_reload_tlast;
+          end
+        end
+      end
+    // Coefficients are static
+    end else begin
+      always @(*) begin
+        for (k = 0; k < NUM_SLICES; k = k + 1) begin
+          coeffs[k]      <= COEFFS_VEC[COEFF_WIDTH*k +: COEFF_WIDTH];
+          coeff_load_stb <= 1'b1;
+        end
+      end
+    end
+  endgenerate
+
+  assign s_axis_reload_tready = 1'b1;
+
+  ///////////////////////////////////////////////////////
+  //
+  // Systolic FIR Filter
+  //
+  ///////////////////////////////////////////////////////
+  //
+  // Block Diagram
+  // - Configuration: SYMMETRIC_COEFFS = 1 and USE_EMBEDDED_REGS_COEFFS = 1
+  //
+  //           +-------+
+  // Sample In | Shift | Sample In delayed NUM_COEFF
+  // +-------->|  Reg  |------------------------------------------------------------->
+  //       |   +-------+             |                                |
+  //       |                         v                                v
+  //       |                      +-----+                          +-----+
+  //       |                      |     |                          |     |
+  //       |                      +-----+                          +-----+
+  //       |                         |                                |
+  //       |   +--+   +--+           |  Sample   +--+   +--+          |
+  //       |   |  |   |  |           |  Forward  |  |   |  |          |
+  //       '-->|  |-->|  |-----------^---------->|  |-->|  |----------^-------------->
+  //           |  |   |  |       |   |           |  |   |  |      |   |
+  //           +--+   +--+       v   v           +--+   +--+      v   v
+  //                         +------------+                   +------------+
+  //                         | Pre-Adder  |                   | Pre-Adder  |
+  //                         +------------+                   +------------+
+  //                               |                                |
+  //                               v                                v
+  //                            +-----+                          +-----+
+  // *----------------------*   |     |                          |     |
+  // | Note: Coeffs are     |   +-----+                          +-----+
+  // | loaded backwards     |      |                                |
+  // | for proper alignment |      |         .----------------------^----------------<
+  // *----------------------*      |         |                      |
+  //           +--+   +--+         v         |   +--+   +--+        v
+  //  Coeff In |  |   |  |   +------------+  |   |  |   |  |  +------------+
+  //      .--->|  |-->|  |-->| Multiplier |  '-->|  |-->|  |->| Multiplier |
+  //      |    |  |   |  |   +------------+      |  | | |  |  +------------+
+  //      |    +--+   +--+         |             +--+ | +--+        |
+  //      |                        |                  |             |
+  //      '------------------------^------------------'             |
+  //                               |           Coeff                |
+  //                               v           Forward              v
+  //                            +-----+                          +-----+
+  //                            |     |                          |     |
+  //                            +-----+                          +-----+
+  //                               |                                |
+  //                               v          +--+ Sample           v          +--+
+  //                         +------------+   |  | Out        +------------+   |  |
+  //                         |   Adder    |-->|  |----------->|   Adder    |-->|  |-->
+  //                         +------------+   |  |            +------------+   |  |
+  //                                          +--+                             +--+
+  //
+  ///////////////////////////////////////////////////////
+  genvar i, l;
+  generate
+    // Counter to track pipeline fullness
+    reg [$clog2(PIPELINE_DELAY):0] cnt;
+    always @(posedge clk) begin
+      if (reset | clear) begin
+        cnt <= 0;
+      end else if (s_axis_data_tvalid & s_axis_data_tready) begin
+        if (cnt < PIPELINE_DELAY) begin
+          cnt <= cnt + 1;
+        end
+      end
+    end
+
+    // Sample delay shift register for efficient implementation
+    // when using symmetric coefficients
+    reg [IN_WIDTH-1:0] sample_shift_reg[0:NUM_COEFFS-1];
+    integer n;
+    initial begin
+      for (n = 0; n < NUM_COEFFS; n = n + 1) begin
+        sample_shift_reg[n] <= 0;
+      end
+    end
+    always @(posedge clk) begin
+      if (s_axis_data_tvalid & s_axis_data_tready) begin
+        for (n = 1; n < NUM_COEFFS; n = n + 1) begin
+          sample_shift_reg[n] <= sample_shift_reg[n-1];
+        end
+          sample_shift_reg[0] <= s_axis_data_tdata;
+      end
+    end
+
+    // tlast shift register
+    reg [PIPELINE_DELAY-1:0] tlast_shift_reg = 0;
+    integer m;
+    always @(posedge clk) begin
+      if (s_axis_data_tvalid & s_axis_data_tready) begin
+        for (m = 1; m < PIPELINE_DELAY; m = m + 1) begin
+          tlast_shift_reg[m] <= tlast_shift_reg[m-1];
+        end
+        tlast_shift_reg[0]   <= s_axis_data_tlast;
+      end
+    end
+
+    wire [IN_WIDTH-1:0] sample_in[0:NUM_SLICES];        // Use [0:NUM_SLICES] instead of
+    wire [ACCUM_WIDTH-1:0] sample_accum[0:NUM_SLICES];  //   [0:NUM_SLICES-1] to make the
+    wire [COEFF_WIDTH-1:0] coeff_forward[0:NUM_SLICES]; //   generate loop easier to read
+    assign sample_in[0]              = s_axis_data_tdata;
+    assign sample_accum[0]           = 0;
+    assign coeff_forward[NUM_SLICES] = s_axis_reload_tdata;
+
+    // Build up FIR filter with multiply-accumulate slices (fir_filter_slice)
+    for (i = 0; i < NUM_SLICES; i = i + 1) begin
+      // Map zero'd out coefficients to simple register delays.
+      if ((SKIP_ZERO_COEFFS == 1) && (COEFFS_VEC[COEFF_WIDTH*i +: COEFF_WIDTH] == 0)) begin
+        reg [ACCUM_WIDTH-1:0] sample_accum_reg;
+        reg [IN_WIDTH-1:0] sample_in_reg[0:1];
+        reg [COEFF_WIDTH-1:0] coeff_in_reg;
+        always @(posedge clk) begin
+          if (reset | clear) begin
+            sample_in_reg[0] <= 0;
+            sample_in_reg[1] <= 0;
+            sample_accum_reg <= 0;
+            coeff_in_reg     <= 0;
+          end else begin
+            if (s_axis_data_tvalid & s_axis_data_tready) begin
+              sample_in_reg[0] <= sample_in[i];
+              sample_in_reg[1] <= sample_in_reg[0];
+              sample_accum_reg <= sample_accum[i];
+            end
+            if (coeff_load_stb) begin
+              coeff_in_reg     <= coeff_forward[i+1];
+            end
+          end
+        end
+        assign sample_in[i+1]    = sample_in_reg[1];
+        assign sample_accum[i+1] = sample_accum_reg;
+        assign coeff_forward[i]  = coeff_in_reg;
+      end else begin
+        fir_filter_slice #(
+          .IN_WIDTH(IN_WIDTH),
+          .COEFF_WIDTH(COEFF_WIDTH),
+          .ACCUM_WIDTH(ACCUM_WIDTH),
+          .OUT_WIDTH(ACCUM_WIDTH))
+        fir_filter_slice (
+          .clk(clk),
+          .reset(reset),
+          .clear(clear),
+          .sample_in_stb(s_axis_data_tvalid & s_axis_data_tready),
+          .sample_in_a(sample_in[i]),
+          // sample_in_b is used to implement symmetric coefficients, always 0 if SYMMETRIC_COEFFS = 0
+          .sample_in_b(((SYMMETRIC_COEFFS == 0) || ((ODD_LEN == 1) && (i == NUM_SLICES-1))) ? {IN_WIDTH{1'b0}} : sample_shift_reg[NUM_COEFFS-1]),
+          .sample_forward(sample_in[i+1]),
+          // For proper coeffient loading, coeff_forward must be shifted in backwards. coeffs[] is already backwards.
+          .coeff_in(((USE_EMBEDDED_REGS_COEFFS == 1) && (RELOADABLE_COEFFS == 1)) ? coeff_forward[i+1] : coeffs[i]),
+          .coeff_forward(coeff_forward[i]),
+          .coeff_load_stb(coeff_load_stb),
+          .sample_accum(sample_accum[i]),
+          .sample_out(sample_accum[i+1]));
+      end
+    end
+    assign m_axis_data_tdata_int  = (BLANK_OUTPUT == 1) & (cnt < PIPELINE_DELAY) ? 0    : sample_accum[NUM_SLICES];
+    assign m_axis_data_tvalid_int = (BLANK_OUTPUT == 1) & (cnt < PIPELINE_DELAY) ? 1'b0 : s_axis_data_tvalid;
+    assign m_axis_data_tlast_int  = (BLANK_OUTPUT == 1) ? ((cnt < PIPELINE_DELAY) ? 1'b0 : tlast_shift_reg[PIPELINE_DELAY-1]) : s_axis_data_tlast;
+    assign s_axis_data_tready     = m_axis_data_tready_int;
+  endgenerate
+
+  axi_round_and_clip #(
+    .WIDTH_IN(ACCUM_WIDTH),
+    .WIDTH_OUT(OUT_WIDTH),
+    .CLIP_BITS(CLIP_BITS))
+  inst_axi_round_and_clip (
+    .clk(clk),
+    .reset(reset | clear),
+    .i_tdata(m_axis_data_tdata_int),
+    .i_tlast(m_axis_data_tlast_int),
+    .i_tvalid(m_axis_data_tvalid_int),
+    .i_tready(m_axis_data_tready_int),
+    .o_tdata(m_axis_data_tdata),
+    .o_tlast(m_axis_data_tlast),
+    .o_tvalid(m_axis_data_tvalid),
+    .o_tready(m_axis_data_tready));
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/axi_fir_filter_dec.v b/fpga/usrp3/lib/rfnoc/axi_fir_filter_dec.v
new file mode 100644
index 000000000..30be7501e
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/axi_fir_filter_dec.v
@@ -0,0 +1,83 @@
+//
+// Copyright 2018 Ettus Research, a National Instruments Brand
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+
+// Generic FIR filter with decimator
+
+module axi_fir_filter_dec #(
+  parameter WIDTH         = 24,
+  parameter COEFF_WIDTH  = 18,
+  parameter NUM_COEFFS    = 47,
+  parameter [NUM_COEFFS*COEFF_WIDTH-1:0] COEFFS_VEC =
+      {{1'b0,{(COEFF_WIDTH-1){1'b1}}},{(COEFF_WIDTH*(NUM_COEFFS-1)){1'b0}}},
+  parameter BLANK_OUTPUT  = 0
+)(
+  input clk,
+  input reset,
+
+  input [2*WIDTH-1:0] i_tdata,
+  input i_tlast,
+  input i_tvalid,
+  output i_tready,
+
+  output [2*WIDTH-1:0] o_tdata,
+  output o_tlast,
+  output o_tvalid,
+  input o_tready
+);
+
+wire [WIDTH-1:0]  tdata_fir0_dec0;
+wire              tvalid_fir0_dec0;
+wire              tlast_fir0_dec0;
+wire              tready_fir0_dec0;
+
+wire [WIDTH-1:0]  tdata_fir1_dec1;
+wire              tvalid_fir1_dec1;
+wire              tlast_fir1_dec1;
+wire              tready_fir1_dec1;
+
+wire [WIDTH-1:0] tdata_fir0;
+wire [WIDTH-1:0] tdata_fir1;
+wire [WIDTH-1:0] tdata_dec0;
+wire [WIDTH-1:0] tdata_dec1;
+
+// Split input data into real and imag. part.
+assign tdata_fir0 = i_tdata[2*WIDTH-1:WIDTH];
+assign tdata_fir1 = i_tdata[WIDTH-1:0];
+
+// FIR filter for real part
+axi_fir_filter #(.IN_WIDTH(WIDTH), .COEFF_WIDTH(COEFF_WIDTH), .OUT_WIDTH(WIDTH), .NUM_COEFFS(NUM_COEFFS), .COEFFS_VEC(COEFFS_VEC),
+  .RELOADABLE_COEFFS(0), .BLANK_OUTPUT(0), .SYMMETRIC_COEFFS(1), .SKIP_ZERO_COEFFS(1), .USE_EMBEDDED_REGS_COEFFS(0)
+) hbfir0(
+  .clk(clk), .reset(reset), .clear(reset),
+  .s_axis_data_tdata(tdata_fir0), .s_axis_data_tlast(i_tlast), .s_axis_data_tvalid(i_tvalid), .s_axis_data_tready(i_tready),
+  .m_axis_data_tdata(tdata_fir0_dec0), .m_axis_data_tlast(tlast_fir0_dec0), .m_axis_data_tvalid(tvalid_fir0_dec0), .m_axis_data_tready(tready_fir0_dec0),
+  .s_axis_reload_tdata(18'd0), .s_axis_reload_tvalid(1'b0), .s_axis_reload_tlast(1'b0), .s_axis_reload_tready());
+
+// FIR filter for imag. part
+axi_fir_filter #(.IN_WIDTH(WIDTH), .COEFF_WIDTH(COEFF_WIDTH), .OUT_WIDTH(WIDTH), .NUM_COEFFS(NUM_COEFFS), .COEFFS_VEC(COEFFS_VEC),
+  .RELOADABLE_COEFFS(0), .BLANK_OUTPUT(0), .SYMMETRIC_COEFFS(1), .SKIP_ZERO_COEFFS(1), .USE_EMBEDDED_REGS_COEFFS(0)
+) hbfir1(
+  .clk(clk), .reset(reset), .clear(reset),
+  .s_axis_data_tdata(tdata_fir1), .s_axis_data_tlast(i_tlast), .s_axis_data_tvalid(i_tvalid), .s_axis_data_tready(),
+  .m_axis_data_tdata(tdata_fir1_dec1), .m_axis_data_tlast(tlast_fir1_dec1), .m_axis_data_tvalid(tvalid_fir1_dec1), .m_axis_data_tready(tready_fir1_dec1),
+  .s_axis_reload_tdata(18'd0), .s_axis_reload_tvalid(1'b0), .s_axis_reload_tlast(1'b0), .s_axis_reload_tready());
+
+// Decimator for real part
+keep_one_in_n #(.KEEP_FIRST(1), .WIDTH(WIDTH), .MAX_N(4)
+) dec0 (
+  .clk(clk), .reset(reset), .vector_mode(1'b0), .n(2),
+  .i_tdata(tdata_fir0_dec0), .i_tlast(tlast_fir0_dec0), .i_tvalid(tvalid_fir0_dec0), .i_tready(tready_fir0_dec0),
+  .o_tdata(tdata_dec0), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready));
+
+// Decimator for imag. part
+keep_one_in_n #(.KEEP_FIRST(1), .WIDTH(WIDTH), .MAX_N(4)
+) dec1 (
+  .clk(clk), .reset(reset), .vector_mode(1'b0), .n(2),
+  .i_tdata(tdata_fir1_dec1), .i_tlast(tlast_fir1_dec1), .i_tvalid(tvalid_fir1_dec1), .i_tready(tready_fir1_dec1),
+  .o_tdata(tdata_dec1), .o_tlast(), .o_tvalid(), .o_tready(o_tready));
+
+assign o_tdata = {tdata_dec0, tdata_dec1};
+
+endmodule // axi_fir_filter_dec
diff --git a/fpga/usrp3/lib/rfnoc/axi_join.v b/fpga/usrp3/lib/rfnoc/axi_join.v
new file mode 100644
index 000000000..a2f7c567d
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/axi_join.v
@@ -0,0 +1,18 @@
+
+
+// Copyright 2014 Ettus Research
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+
+module axi_join
+  #(parameter INPUTS=2)
+  (input [INPUTS-1:0] i_tlast, input [INPUTS-1:0] i_tvalid, output [INPUTS-1:0] i_tready,
+   output o_tlast, output o_tvalid, input o_tready);
+
+   wire   all_here = &i_tvalid;
+   assign o_tvalid = all_here;
+   assign o_tlast = |i_tlast;
+   assign i_tready = {INPUTS{o_tready & all_here}};
+   
+endmodule // axi_join
diff --git a/fpga/usrp3/lib/rfnoc/axi_packer.v b/fpga/usrp3/lib/rfnoc/axi_packer.v
new file mode 100644
index 000000000..fbed250f6
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/axi_packer.v
@@ -0,0 +1,67 @@
+//
+// Copyright 2015 Ettus Research
+//
+// Increases AXI stream bit width by concatenating inputs across multiple clock cycles.
+// Note: WIDTH_IN must be a multiple of WIDTH_OUT
+
+module axi_packer #(
+  parameter WIDTH_IN          = 8,   // Input bit width
+  parameter WIDTH_OUT         = 32,  // Output bit width
+  parameter REVERSE           = 0)   // 0: Fill LSB to MSB, 1: Fill MSB to LSB
+(
+  input clk, input reset, input clear,
+  input [WIDTH_IN-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
+  output [WIDTH_OUT-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready
+);
+
+  localparam M = WIDTH_OUT/WIDTH_IN;
+
+  reg packed_tlast, packed_tvalid;
+  reg [WIDTH_OUT-1:0] packed_tdata;
+  reg [$clog2(M)-1:0] cnt;
+  reg i_tlast_hold;
+  integer i;
+  always @(posedge clk) begin
+    if (reset | clear) begin
+      i_tlast_hold      <= 1'b0;
+      cnt               <= 'd0;
+      packed_tdata      <= 'd0;
+      packed_tvalid     <= 1'b0;
+      packed_tlast      <= 1'b0;
+    end else begin
+      packed_tvalid     <= 1'b0;
+      packed_tlast      <= 1'b0;
+      if (i_tvalid & i_tready) begin
+        if (i_tlast) begin
+          i_tlast_hold  <= 1'b1;
+        end
+        if (cnt > M-1) begin
+          cnt           <= 'd0;
+          packed_tlast  <= i_tlast_hold;
+          packed_tvalid <= 1'b1;
+        end else begin
+          cnt           <= cnt + 1;
+        end
+        if (REVERSE) begin
+          packed_tdata[WIDTH_OUT-1:WIDTH_OUT-WIDTH_IN] <= i_tdata;
+          for (i = 0; i < M-1; i = i + 1) begin
+            packed_tdata[WIDTH_OUT-(i+1)*WIDTH_IN-1 -: WIDTH_IN] <= packed_tdata[WIDTH_OUT-i*WIDTH_IN-1 -: WIDTH_IN];
+          end
+        end else begin
+          packed_tdata[WIDTH_IN-1:0] <= i_tdata;
+          for (i = 0; i < M-1; i = i + 1) begin
+            packed_tdata[(i+2)*WIDTH_IN-1 -: WIDTH_IN] <= packed_tdata[(i+1)*WIDTH_IN-1 -: WIDTH_IN];
+          end
+        end
+      end
+    end
+  end
+
+  axi_fifo_flop #(.WIDTH(WIDTH_OUT+1)) axi_fifo_flop_pack (
+    .clk(clk), .reset(reset), .clear(clear),
+    .i_tdata({packed_tlast,packed_tdata}), .i_tvalid(packed_tvalid), .i_tready(i_tready),
+    .o_tdata({o_tlast,o_tdata}), .o_tvalid(o_tvalid), .o_tready(o_tready),
+    .space(), .occupied());
+
+endmodule
+
diff --git a/fpga/usrp3/lib/rfnoc/axi_packet_mux.v b/fpga/usrp3/lib/rfnoc/axi_packet_mux.v
new file mode 100644
index 000000000..53ce890ba
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/axi_packet_mux.v
@@ -0,0 +1,41 @@
+//
+// Copyright 2016 Ettus Research
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Muxes and packetizes input AXI-streams. Assumes header on tuser. 
+
+module axi_packet_mux #(
+  parameter NUM_INPUTS = 1,
+  parameter MUX_PRE_FIFO_SIZE = 0,  // Use 0 (most efficient) unless there is need to compensate for unbalanced input path latencies
+  parameter MUX_POST_FIFO_SIZE = 0, // Generally leave at 0, similar effect as FIFO_SIZE
+  parameter FIFO_SIZE = 5           // Size of FIFO in CHDR framer
+)(
+  input clk, input reset, input clear,
+  input [NUM_INPUTS*64-1:0] i_tdata, input [NUM_INPUTS-1:0] i_tlast, input [NUM_INPUTS-1:0] i_tvalid, output [NUM_INPUTS-1:0] i_tready, input [NUM_INPUTS*128-1:0] i_tuser,
+  output [63:0] o_tdata, output o_tlast, output o_tvalid, input o_tready
+);
+
+  wire [NUM_INPUTS*(64+128)-1:0] i_tdata_flat;
+  genvar i;
+  generate
+    for (i = 0; i < NUM_INPUTS; i = i + 1) begin
+      assign i_tdata_flat[(128+64)*(i+1)-1:(128+64)*i] = {i_tuser[128*(i+1)-1:128*i],i_tdata[64*(i+1)-1:64*i]};
+    end
+  endgenerate
+
+  wire [63:0] int_tdata;
+  wire [127:0] int_tuser;
+  wire int_tlast, int_tvalid, int_tready;
+  axi_mux #(.PRIO(0), .WIDTH(128+64), .PRE_FIFO_SIZE(MUX_PRE_FIFO_SIZE), .POST_FIFO_SIZE(MUX_POST_FIFO_SIZE), .SIZE(NUM_INPUTS)) axi_mux (
+    .clk(clk), .reset(reset), .clear(1'b0),
+    .i_tdata(i_tdata_flat), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready),
+    .o_tdata({int_tuser, int_tdata}), .o_tlast(int_tlast), .o_tvalid(int_tvalid), .o_tready(int_tready));
+
+  chdr_framer #(.SIZE(FIFO_SIZE), .WIDTH(64)) chdr_framer (
+    .clk(clk), .reset(reset), .clear(1'b0),
+    .i_tdata(int_tdata), .i_tuser(int_tuser), .i_tlast(int_tlast), .i_tvalid(int_tvalid), .i_tready(int_tready),
+    .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready));
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/axi_pipe.v b/fpga/usrp3/lib/rfnoc/axi_pipe.v
new file mode 100644
index 000000000..4c635a5bf
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/axi_pipe.v
@@ -0,0 +1,67 @@
+
+// Copyright 2014 Ettus Research
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+
+
+module axi_pipe
+  #(parameter STAGES=3)
+   (input clk, input reset, input clear,
+    input i_tlast, input i_tvalid, output i_tready,
+    output o_tlast, output o_tvalid, input o_tready,
+    output [STAGES-1:0] enables,
+    output reg [STAGES-1:0] valids);
+
+   assign o_tvalid = valids[STAGES-1];
+   assign i_tready = enables[0];
+
+   // //////////////////////////////
+   // Valids
+   genvar 		    i;
+   generate
+      for(i=1; i<STAGES; i=i+1)
+	always @(posedge clk)
+	  if(reset | clear)
+	    valids[i] <= 1'b0;
+      	  else
+	    valids[i] <= valids[i-1] | (valids[i] & ~enables[i]);
+   endgenerate
+
+   always @(posedge clk)
+     if(reset | clear)
+       valids[0] <= 1'b0;
+     else
+       valids[0] <= i_tvalid | (valids[0] & ~enables[0]);
+
+   // //////////////////////////////
+   // Enables
+   genvar 		    j;
+   generate
+      for(j=0; j<STAGES; j=j+1)
+	assign enables[j] = o_tready | (|(~valids[STAGES-1:j]));
+   endgenerate
+
+   // /////////////////////////////
+   // tlast
+   reg [STAGES-1:0] 	    tlast;
+   
+   genvar 		    k;
+   generate
+      for(k=1; k<STAGES; k=k+1)
+	always @(posedge clk)
+	  if(reset | clear)
+	    tlast[k] <= 1'b0;
+	  else if(enables[k])
+	    tlast[k] <= tlast[k-1];
+   endgenerate
+
+   always @(posedge clk)
+	  if(reset | clear)
+	    tlast[0] <= 1'b0;
+	  else if(enables[0])
+	    tlast[0] <= i_tlast;
+
+   assign o_tlast = tlast[STAGES-1];
+   
+endmodule // axi_pipe
diff --git a/fpga/usrp3/lib/rfnoc/axi_pipe_join.v b/fpga/usrp3/lib/rfnoc/axi_pipe_join.v
new file mode 100644
index 000000000..635a7bf75
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/axi_pipe_join.v
@@ -0,0 +1,46 @@
+
+// Copyright 2014 Ettus Research
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+
+
+module axi_pipe_join
+  #(parameter PRE_JOIN_STAGES0=3,
+    parameter PRE_JOIN_STAGES1=3,
+    parameter POST_JOIN_STAGES=3)
+   (input clk, input reset, input clear,
+    input i0_tlast, input i0_tvalid, output i0_tready,
+    input i1_tlast, input i1_tvalid, output i1_tready,
+    output o_tlast, output o_tvalid, input o_tready,
+    output [PRE_JOIN_STAGES0-1:0] enables0,
+    output [PRE_JOIN_STAGES1-1:0] enables1,
+    output [POST_JOIN_STAGES-1:0] enables_post);
+
+   wire 			  join_tlast, join_tvalid, join_tready;
+   wire 			  int0_tlast, int0_tvalid, int0_tready;
+   wire 			  int1_tlast, int1_tvalid, int1_tready;
+   
+   axi_pipe #(.STAGES(PRE_JOIN_STAGES0)) pipe_pre_0
+     (.clk(clk), .reset(reset), .clear(clear),
+      .i_tlast(i0_tlast), .i_tvalid(i0_tvalid), .i_tready(i0_tready),
+      .o_tlast(int0_tlast), .o_tvalid(int0_tvalid), .o_tready(int0_tready),
+      .enables(enables0), .valids());
+   
+   axi_pipe #(.STAGES(PRE_JOIN_STAGES1)) pipe_pre_1
+     (.clk(clk), .reset(reset), .clear(clear),
+      .i_tlast(i1_tlast), .i_tvalid(i1_tvalid), .i_tready(i1_tready),
+      .o_tlast(int1_tlast), .o_tvalid(int1_tvalid), .o_tready(int1_tready),
+      .enables(enables1), .valids());
+   
+   axi_pipe #(.STAGES(POST_JOIN_STAGES)) pipe_post
+     (.clk(clk), .reset(reset), .clear(clear),
+      .i_tlast(join_tlast), .i_tvalid(join_tvalid), .i_tready(join_tready),
+      .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready),
+      .enables(enables_post), .valids());
+   
+   axi_join #(.INPUTS(2)) joiner
+     (.i_tlast({int1_tlast,int0_tlast}), .i_tvalid({int1_tvalid,int0_tvalid}), .i_tready({int1_tready,int0_tready}),
+      .o_tlast(join_tlast), .o_tvalid(join_tvalid), .o_tready(join_tready));
+   
+endmodule // axi_pipe_join
diff --git a/fpga/usrp3/lib/rfnoc/axi_pipe_mac.v b/fpga/usrp3/lib/rfnoc/axi_pipe_mac.v
new file mode 100644
index 000000000..de4ade51f
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/axi_pipe_mac.v
@@ -0,0 +1,79 @@
+
+// Copyright 2014 Ettus Research
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+
+// Latency must be 3 or 4
+
+module axi_pipe_mac
+  #(parameter LATENCY=3,
+    parameter CASCADE_IN=0)
+   (input clk, input reset, input clear,
+    input a_tlast, input a_tvalid, output a_tready,
+    input b_tlast, input b_tvalid, output b_tready,
+    input c_tlast, input c_tvalid, output c_tready,
+    output p_tlast, output p_tvalid, input p_tready,
+    output [LATENCY-3:0] enables_a,
+    output [LATENCY-3:0] enables_b,
+    output enable_c,
+    output enable_m,
+    output enable_p);
+   
+   wire 			  join_tlast, join_tvalid, join_tready;
+   wire 			  join1_tlast, join1_tvalid, join1_tready;
+   wire 			  int0_tlast, int0_tvalid, int0_tready;
+   wire 			  int1_tlast, int1_tvalid, int1_tready;
+   wire 			  int2_tlast, int2_tvalid, int2_tready;
+   wire 			  int3_tlast, int3_tvalid, int3_tready;
+   
+   axi_pipe #(.STAGES(LATENCY-2)) pipe_a
+     (.clk(clk), .reset(reset), .clear(clear),
+      .i_tlast(a_tlast), .i_tvalid(a_tvalid), .i_tready(a_tready),
+      .o_tlast(int0_tlast), .o_tvalid(int0_tvalid), .o_tready(int0_tready),
+      .enables(enables_a), .valids());
+   
+   axi_pipe #(.STAGES(LATENCY-2)) pipe_b
+     (.clk(clk), .reset(reset), .clear(clear),
+      .i_tlast(b_tlast), .i_tvalid(b_tvalid), .i_tready(b_tready),
+      .o_tlast(int1_tlast), .o_tvalid(int1_tvalid), .o_tready(int1_tready),
+      .enables(enables_b), .valids());
+   
+   axi_join #(.INPUTS(2)) join_ab
+     (.i_tlast({int1_tlast,int0_tlast}), .i_tvalid({int1_tvalid,int0_tvalid}), .i_tready({int1_tready,int0_tready}),
+      .o_tlast(join_tlast), .o_tvalid(join_tvalid), .o_tready(join_tready));
+   
+   axi_pipe #(.STAGES(1)) pipe_m
+     (.clk(clk), .reset(reset), .clear(clear),
+      .i_tlast(join_tlast), .i_tvalid(join_tvalid), .i_tready(join_tready),
+      .o_tlast(int2_tlast), .o_tvalid(int2_tvalid), .o_tready(int2_tready),
+      .enables(enable_m), .valids());
+
+   // If we use the cascade input, there is no flop in the input side adder
+   generate
+      if(CASCADE_IN)
+	begin
+	   assign int3_tlast = c_tlast;
+	   assign int3_tvalid = c_tvalid;
+	   assign c_tready = int3_tready;
+	   assign enable_c = 1'b0;
+	end
+      else
+	axi_pipe #(.STAGES(1)) pipe_c
+	  (.clk(clk), .reset(reset), .clear(clear),
+	   .i_tlast(c_tlast), .i_tvalid(c_tvalid), .i_tready(c_tready),
+	   .o_tlast(int3_tlast), .o_tvalid(int3_tvalid), .o_tready(int3_tready),
+	   .enables(enable_c), .valids());
+   endgenerate
+   
+   axi_join #(.INPUTS(2)) joiner_mc
+     (.i_tlast({int2_tlast,int3_tlast}), .i_tvalid({int2_tvalid,int3_tvalid}), .i_tready({int2_tready,int3_tready}),
+      .o_tlast(join1_tlast), .o_tvalid(join1_tvalid), .o_tready(join1_tready));
+   
+   axi_pipe #(.STAGES(1)) pipe_p
+     (.clk(clk), .reset(reset), .clear(clear),
+      .i_tlast(join1_tlast), .i_tvalid(join1_tvalid), .i_tready(join1_tready),
+      .o_tlast(p_tlast), .o_tvalid(p_tvalid), .o_tready(p_tready),
+      .enables(enable_p), .valids());
+   
+endmodule // axi_pipe_mac
diff --git a/fpga/usrp3/lib/rfnoc/axi_rate_change.v b/fpga/usrp3/lib/rfnoc/axi_rate_change.v
new file mode 100644
index 000000000..166e03c46
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/axi_rate_change.v
@@ -0,0 +1,491 @@
+//
+// Copyright 2016 Ettus Research
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// - Implements rate change of N:M (a.k.a. M/N), handles headers automatically
+// - Note: N should always be written before M in software to prevent false rate changes
+//         while the block is active
+// - User code is responsible for generating correct number of outputs per input
+//   > Example: When set 1/N, after N input samples block should output 1 sample. If
+//              user code's pipelining requires additional samples to "push" the 1
+//              sample out, it is the user's responsibility to make the mechanism
+//              (such as injecting extra samples) to do so.
+// - Will always send an integer multiple of N samples to user logic. This ensures
+//   the user will not need to manually clear a "partial output sample" stuck in their
+//   pipeline due to an uneven (in respect to decimation rate) number of input samples.
+// - Can optionally strobe clear_user after receiving packet with EOB
+//   > enable_clear_user must be enabled via CONFIG settings register
+//   > Warning: Input will be throttled until last packet has completely passed through
+//     user code to prevent clearing valid data. In certain conditions, this throttling
+//     can have a significant impact on throughput.
+// - Output packet size will be identical to input packet size. The only exception is
+//   the final output packet, which may be shorter due to a partial input packet.
+// Limitations:
+// - Rate changes are ignored while active. Block must be cleared or packet with EOB
+//   (and enable_clear_user is set) will cause new rates to be loaded.
+// - Can potentially use large amounts of block RAM when using large decimation rates
+//   (greater than 2K). This occurs due to the feature that the block always sends a multiple
+//   of N samples to the user. Implementing this feature requires N samples to be buffered.
+// - User code with long pipelines may need to increase HEADER_FIFOSIZE. The debug signal
+//   warning_header_fifo_full is useful in determining this case.
+//
+// Settings Registers:
+//   sr_n:       Number of input samples per M output samples (Always write N before M)
+//   sr_m:       Number of output samples per N input samples
+//   sr_config:  0: Enable clear_user signal.
+
+module axi_rate_change #(
+  parameter WIDTH                   = 32, // Input bit width, must be a power of 2 and greater than or equal to 8.
+  parameter MAX_N                   = 2**16,
+  parameter MAX_M                   = 2**16,
+  parameter MAXIMIZE_OUTPUT_PKT_LEN = 1,
+  // Settings registers
+  parameter SR_N_ADDR               = 0,
+  parameter SR_M_ADDR               = 1,
+  parameter SR_CONFIG_ADDR          = 2
+)(
+  input clk, input reset, input clear,
+  output clear_user,  // Strobed after end of burst. Throttles input. Useful for resetting user code between bursts.
+  input [15:0] src_sid, input [15:0] dst_sid,
+  input set_stb, input [7:0] set_addr, input [31:0] set_data,
+  input [WIDTH-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready, input [127:0] i_tuser,
+  output [WIDTH-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready, output [127:0] o_tuser,
+  output [WIDTH-1:0] m_axis_data_tdata, output m_axis_data_tlast, output m_axis_data_tvalid, input m_axis_data_tready,
+  input [WIDTH-1:0] s_axis_data_tdata, input s_axis_data_tlast, input s_axis_data_tvalid, output s_axis_data_tready,
+  // Debugging signals:
+  // - Warnings indicate there may be an issue with user code.
+  // - Errors mean the user code has violated a rule.
+  // - Signals latch once set and block must be reset to clear.
+  output reg warning_long_throttle,     // In the throttle state for a "long" time.
+  output reg error_extra_outputs,       // User code generated extra outputs, i.e. received more than the expected M outputs.
+  output reg error_drop_pkt_lockup      // Drop partial packet module is not accepting data even though user code is ready.
+);
+
+  reg [$clog2(MAX_N+1)-1:0] n = 1;
+  reg [$clog2(MAX_M+1)-1:0] m = 1;
+
+  wire [WIDTH-1:0] i_reg_tdata;
+  wire i_reg_tvalid, i_reg_tready, i_reg_tlast;
+  wire i_reg_tvalid_int, i_reg_tready_int, i_reg_tlast_int;
+
+  reg throttle = 1'b1, first_header, partial_first_word;
+  reg [15:0] word_cnt_div_n;
+  reg [$clog2(MAX_N+1)-1:0] word_cnt_div_n_frac = 1;
+  reg [$clog2(MAX_N+1)-1:0] in_pkt_cnt = 1;
+
+  reg send_done;
+  reg rate_changed;
+
+  /********************************************************
+  ** Settings Registers
+  ********************************************************/
+  wire [$clog2(MAX_N+1)-1:0] sr_n;
+  wire n_changed;
+  setting_reg #(.my_addr(SR_N_ADDR), .width($clog2(MAX_N+1)), .at_reset(1)) set_n (
+    .clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
+    .out(sr_n), .changed(n_changed));
+
+  wire [$clog2(MAX_M+1)-1:0] sr_m;
+  wire m_changed;
+  setting_reg #(.my_addr(SR_M_ADDR), .width($clog2(MAX_M+1)), .at_reset(1)) set_m (
+    .clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
+    .out(sr_m), .changed(m_changed));
+
+  wire sr_config;
+  wire enable_clear_user; // Enable strobing clear_user between bursts.
+  setting_reg #(.my_addr(SR_CONFIG_ADDR), .width(1), .at_reset(1'b1)) set_config (
+    .clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
+    .out(sr_config), .changed());
+  assign enable_clear_user = sr_config;
+
+  /********************************************************
+  ** Header, word count FIFOs
+  ** - Header provides VITA Time and payload length for
+  **   output packets
+  ** - Word count provides a normalized count for the
+  **   output state machine to know when it has consumed
+  **   the final input sample in a burst.
+  ********************************************************/
+  // Decode input header
+  wire [127:0] i_reg_tuser;
+  wire has_time_in, eob_in, eob_in_header;
+  wire [15:0] payload_length_in;
+  reg [15:0] payload_length_out;
+  wire [63:0] vita_time_in;
+  cvita_hdr_decoder cvita_hdr_decoder_in_header (
+    .header(i_reg_tuser), .pkt_type(), .eob(eob_in_header),
+    .has_time(has_time_in), .seqnum(), .length(), .payload_length(payload_length_in),
+    .src_sid(), .dst_sid(), .vita_time(vita_time_in));
+
+  assign eob_in = eob_in_header | rate_changed;
+
+  reg [15:0] word_cnt_div_n_tdata;
+  wire [15:0] word_cnt_div_n_fifo_tdata;
+  reg word_cnt_div_n_tvalid;
+  wire word_cnt_div_n_tready, word_cnt_div_n_fifo_tvalid, word_cnt_div_n_fifo_tready;
+  axi_fifo #(.WIDTH(16), .SIZE(0)) axi_fifo_word_cnt (
+    .clk(clk), .reset(reset), .clear(clear),
+    .i_tdata(word_cnt_div_n_tdata), .i_tvalid(word_cnt_div_n_tvalid), .i_tready(word_cnt_div_n_tready),
+    .o_tdata(word_cnt_div_n_fifo_tdata), .o_tvalid(word_cnt_div_n_fifo_tvalid), .o_tready(word_cnt_div_n_fifo_tready),
+    .space(), .occupied());
+
+  /********************************************************
+  ** Register input stream
+  ** - Upsteam will be throttled when clearing user logic
+  ********************************************************/
+  // Input register with header
+  axi_fifo_flop #(.WIDTH(WIDTH+1+128)) axi_fifo_flop_input (
+    .clk(clk), .reset(reset), .clear(clear),
+    .i_tdata({i_tlast,i_tdata,i_tuser}), .i_tvalid(i_tvalid), .i_tready(i_tready),
+    .o_tdata({i_reg_tlast,i_reg_tdata,i_reg_tuser}), .o_tvalid(i_reg_tvalid_int), .o_tready(i_reg_tready),
+    .space(), .occupied());
+
+  assign i_reg_tready     = i_reg_tready_int & word_cnt_div_n_tready & ~throttle;
+  assign i_reg_tvalid     = i_reg_tvalid_int & word_cnt_div_n_tready & ~throttle;
+  // Assert AXI Drop Partial Packet's i_tlast every N samples, which is used to detect and drop
+  // partial output samples.
+  assign i_reg_tlast_int  = (word_cnt_div_n_frac == n) | (eob_in & i_reg_tlast);
+
+  /********************************************************
+  ** Input state machine
+  ********************************************************/
+  reg [1:0] input_state;
+  localparam RECV_INIT                = 0;
+  localparam RECV                     = 1;
+  localparam RECV_WAIT_FOR_SEND_DONE  = 2;
+
+  always @(posedge clk) begin
+    if (reset | clear) begin
+      n                     <= 1;
+      m                     <= 1;
+      rate_changed          <= 1'b0;
+      first_header          <= 1'b1;
+      partial_first_word    <= 1'b1;
+      payload_length_out    <= 'd0;
+      word_cnt_div_n        <= 0;
+      word_cnt_div_n_frac   <= 1;
+      throttle              <= 1'b1;
+      word_cnt_div_n_tvalid <= 1'b0;
+      word_cnt_div_n_tdata  <= 'd0;
+      input_state           <= RECV_INIT;
+    end else begin
+      if (word_cnt_div_n_tvalid & word_cnt_div_n_tready) begin
+        word_cnt_div_n_tvalid <= 1'b0;
+      end
+      // Input state machine
+      case (input_state)
+        RECV_INIT : begin
+          n                      <= sr_n;
+          m                      <= sr_m;
+          rate_changed           <= 1'b0;
+          first_header           <= 1'b1;
+          partial_first_word     <= 1'b1;
+          payload_length_out     <= 'd0;
+          word_cnt_div_n         <= 0;
+          word_cnt_div_n_frac    <= 1;
+          if (i_reg_tvalid_int & word_cnt_div_n_tready) begin
+            throttle             <= 1'b0;
+            input_state          <= RECV;
+          end
+        end
+        // Logic used by the RECV state to track several variables:
+        // word_cnt_div_n:      Number of words received divided by n.
+        //                      Needed for tracking final sample in a burst.
+        // word_cnt_div_n_frac: Used to increment word_cnt_div_n. Can be
+        //                      thought of as the fractional part of
+        //                      word_cnt_div_n.
+        // in_pkt_cnt:          Similar to in_word_cnt, but for packets. Used
+        //                      to determine when a group of N packets has been
+        //                      received to store the next header.
+        // first_header:        We only use the header from the first packet in
+        //                      a group of N packets (this greatly reduces
+        //                      the header FIFO size).
+        RECV : begin
+          // If rate changed, force a EOB.
+          if (m_changed) begin
+            rate_changed           <= 1'b1;
+          end
+          if (i_reg_tvalid & i_reg_tready) begin
+            // Track the number of words sent to the user divided by N.
+            // At the end of a burst, this value is forwarded to the output
+            // state machine and used to determine when the final sample has
+            // arrived from the user code.
+            if (word_cnt_div_n_frac == n) begin
+              word_cnt_div_n       <= word_cnt_div_n + 1;
+              word_cnt_div_n_frac  <= 1;
+            end else begin
+              word_cnt_div_n_frac  <= word_cnt_div_n_frac + 1;
+            end
+            // Use payload length from first packet
+            first_header           <= 1'b0;
+            if (first_header) begin
+              payload_length_out   <= payload_length_in;
+            end else if (MAXIMIZE_OUTPUT_PKT_LEN) begin
+              if (payload_length_out < payload_length_in) begin
+                payload_length_out <= payload_length_in;
+              end
+            end
+            // Track when at least N input samples have been received in this burst
+            if (partial_first_word & (word_cnt_div_n_frac == n)) begin
+              partial_first_word   <= 1'b0;
+            end
+            // Burst ended before we received enough samples to form
+            // at least one full output sample.
+            // Note: axi_drop_partial_packet automatically handles
+            //       dropping the partial sample.
+            if (i_reg_tlast & eob_in & partial_first_word) begin
+              input_state          <= RECV_INIT;
+            end else begin
+              if (i_reg_tlast) begin
+                // At the end of a burst, forward the number of words divided by N to
+                // the output state machine via a FIFO. This allows the output state
+                // machine to know when it has received the final output word.
+                // We use a FIFO in case the bursts are very small and we
+                // need to store several of these values.
+                if (eob_in) begin
+                  word_cnt_div_n_tdata  <= word_cnt_div_n + (word_cnt_div_n_frac == n);
+                  word_cnt_div_n_tvalid <= 1'b1;
+                  throttle              <= 1'b1;
+                  if (enable_clear_user) begin
+                    input_state         <= RECV_WAIT_FOR_SEND_DONE;
+                  end else begin
+                    input_state         <= RECV_INIT;
+                  end
+                end
+              end
+            end
+          end
+        end
+        // Wait until last sample has been output and user logic is cleared
+        // WARNING: This can be a huge bubble state! However, since it only happens with
+        //          EOBs, it should be infrequent.
+        RECV_WAIT_FOR_SEND_DONE : begin
+          if (send_done) begin
+            input_state <= RECV_INIT;
+          end
+        end
+        default : begin
+          input_state   <= RECV_INIT;
+        end
+      endcase
+    end
+  end
+
+  assign clear_user = send_done & enable_clear_user;
+
+  /********************************************************
+  ** AXI Drop Partial Packet (to user)
+  ** - Enforces sending integer multiple of N samples
+  **   to user
+  ********************************************************/
+  axi_drop_partial_packet #(
+    .WIDTH(WIDTH+1),
+    .HOLD_LAST_WORD(1),
+    .MAX_PKT_SIZE(MAX_N),
+    .SR_PKT_SIZE_ADDR(SR_N_ADDR))
+  axi_drop_partial_packet (
+    .clk(clk), .reset(reset), .clear(clear | send_done),
+    .flush(word_cnt_div_n_tvalid & word_cnt_div_n_tready),  // Flush on EOB
+    .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+    .i_tdata({i_reg_tlast,i_reg_tdata}), .i_tvalid(i_reg_tvalid), .i_tlast(i_reg_tlast_int), .i_tready(i_reg_tready_int),
+    .o_tdata({m_axis_data_tlast,m_axis_data_tdata}), .o_tvalid(m_axis_data_tvalid), .o_tlast(/* Unused */), .o_tready(m_axis_data_tready));
+
+  /********************************************************
+  ** Output state machine
+  ********************************************************/
+  reg [1:0] output_state;
+  localparam SEND_INIT = 0;
+  localparam SEND      = 1;
+
+  wire [WIDTH-1:0] o_reg_tdata;
+  wire [127:0] o_reg_tuser;
+  wire o_reg_tvalid, o_reg_tready, o_reg_tlast, o_reg_tlast_int;
+
+  reg [15:0] out_payload_cnt = (WIDTH/8);
+  reg [15:0] word_cnt_div_m;
+  reg [$clog2(MAX_M+1)-1:0] word_cnt_div_m_frac = 1;
+  reg [$clog2(MAX_M+1)-1:0] out_pkt_cnt = 1;
+
+  // End of burst tracking. Compare the number of words sent to the user divided by N
+  // to the number of words received from the user divided by M. When they equal each other
+  // then we have received the last word from the user in this burst.
+  // Note: Using word_cnt_div_n_fifo_tdata to make sure the last word is identified before
+  //       it has been consumed.
+  wire last_word_in_burst = word_cnt_div_n_fifo_tvalid &
+                            (word_cnt_div_m == word_cnt_div_n_fifo_tdata) &
+                            (word_cnt_div_m_frac == m);
+
+  always @(posedge clk) begin
+    if (reset | clear) begin
+      word_cnt_div_m      <= 1;
+      word_cnt_div_m_frac <= 1;
+      out_payload_cnt     <= (WIDTH/8);
+      send_done           <= 1'b0;
+      output_state        <= SEND_INIT;
+    end else begin
+      // Track
+      case (output_state)
+        SEND_INIT : begin
+          word_cnt_div_m      <= 1;
+          word_cnt_div_m_frac <= 1;
+          out_payload_cnt     <= (WIDTH/8);
+          send_done           <= 1'b0;
+          output_state        <= SEND;
+        end
+        SEND : begin
+          if (o_reg_tvalid & o_reg_tready) begin
+            if (o_reg_tlast) begin
+              // Track number of samples from user to set tlast
+              out_payload_cnt <= (WIDTH/8);
+            end else begin
+              out_payload_cnt <= out_payload_cnt + (WIDTH/8);
+            end
+            // Track number of words consumed divided by M. This is used
+            // in conjunction with word_cnt_div_n to determine when we have received
+            // the last word in a burst from the user.
+            if (word_cnt_div_m_frac == m) begin
+              word_cnt_div_m      <= word_cnt_div_m + 1;
+              word_cnt_div_m_frac <= 1;
+            end else begin
+              word_cnt_div_m_frac <= word_cnt_div_m_frac + 1;
+            end
+            if (last_word_in_burst) begin
+              send_done    <= 1'b1;
+              output_state <= SEND_INIT;
+            end
+          end
+        end
+        default : begin
+          output_state <= SEND_INIT;
+        end
+      endcase
+    end
+  end
+
+  // Only pop this FIFO at EOB.
+  assign word_cnt_div_n_fifo_tready = o_reg_tvalid & o_reg_tready & last_word_in_burst;
+
+  /********************************************************
+  ** Adjust VITA time
+  ********************************************************/
+  localparam VT_INIT       = 0;
+  localparam VT_INCREMENT  = 1;
+  reg vt_state;
+
+  reg has_time_out, has_time_clear;
+  reg [63:0] vita_time_out, vita_time_accum;
+
+  always @(posedge clk) begin
+    if (reset | clear) begin
+      vt_state               <= VT_INIT;
+    end else begin
+      case (vt_state)
+        VT_INIT : begin
+          has_time_clear       <= 1'b0;
+          if (i_reg_tvalid & i_reg_tready & first_header) begin
+            vita_time_out      <= vita_time_in;
+            vita_time_accum    <= vita_time_in;
+            has_time_out       <= has_time_in;
+            vt_state           <= VT_INCREMENT;
+          end
+        end
+        VT_INCREMENT : begin
+          // Stop sending vita time if user does not send vita time
+          if (i_reg_tvalid & ~has_time_in) begin
+            has_time_clear     <= 1'b1;
+          end
+          if (o_reg_tvalid & o_reg_tready) begin
+            if (o_reg_tlast) begin
+              if (has_time_clear) begin
+                has_time_out   <= 1'b0;
+              end
+              vita_time_out    <= vita_time_accum + n;
+            end
+            vita_time_accum    <= vita_time_accum + n;
+            if (last_word_in_burst) begin
+              vt_state         <= VT_INIT;
+            end
+          end
+        end
+        default : begin
+          vt_state             <= VT_INIT;
+        end
+      endcase
+    end
+  end
+
+  // Create output header
+  cvita_hdr_encoder cvita_hdr_encoder (
+    .pkt_type(2'd0), .eob(last_word_in_burst), .has_time(has_time_out),
+    .seqnum(12'd0), .payload_length(16'd0), // Not needed, handled by AXI Wrapper
+    .src_sid(src_sid), .dst_sid(dst_sid),
+    .vita_time(vita_time_out),
+    .header(o_reg_tuser));
+
+  /********************************************************
+  ** Register input stream from user and output stream
+  ********************************************************/
+  assign o_reg_tlast      = o_reg_tlast_int |
+                            // End of packet
+                            (out_payload_cnt == payload_length_out) |
+                            // EOB, could be a partial packet
+                            last_word_in_burst;
+
+  axi_fifo_flop #(.WIDTH(WIDTH+1)) axi_fifo_flop_from_user_0 (
+    .clk(clk), .reset(reset), .clear(clear),
+    // FIXME: If user asserts tlast at the wrong time, it likely causes a deadlock. For now ignore tlast.
+    //.i_tdata({s_axis_data_tlast,s_axis_data_tdata}), .i_tvalid(s_axis_data_tvalid), .i_tready(s_axis_data_tready),
+    .i_tdata({1'b0,s_axis_data_tdata}), .i_tvalid(s_axis_data_tvalid), .i_tready(s_axis_data_tready),
+    .o_tdata({o_reg_tlast_int,o_reg_tdata}), .o_tvalid(o_reg_tvalid), .o_tready(o_reg_tready),
+    .space(), .occupied());
+
+  // Output register with header
+  axi_fifo_flop #(.WIDTH(WIDTH+1+128)) axi_fifo_flop_output (
+    .clk(clk), .reset(reset), .clear(clear),
+    .i_tdata({o_reg_tlast,o_reg_tdata,o_reg_tuser}), .i_tvalid(o_reg_tvalid), .i_tready(o_reg_tready),
+    .o_tdata({o_tlast,o_tdata,o_tuser}), .o_tvalid(o_tvalid), .o_tready(o_tready),
+    .space(), .occupied());
+
+  /********************************************************
+  ** Error / warning signals
+  ********************************************************/
+  reg [23:0] counter_header_fifo_full, counter_throttle, counter_drop_pkt_lockup;
+  reg [2:0] counter_header_fifo_empty;
+  always @(posedge clk) begin
+    if (reset) begin
+      warning_long_throttle       <= 1'b0;
+      error_extra_outputs         <= 1'b0;
+      error_drop_pkt_lockup       <= 1'b0;
+      counter_throttle            <= 0;
+      counter_header_fifo_full    <= 0;
+      counter_drop_pkt_lockup     <= 0;
+      counter_header_fifo_empty   <= 0;
+    end else begin
+      // In throttle state for a "long" time
+      if (throttle) begin
+        counter_throttle          <= counter_throttle + 1;
+        if (counter_throttle == 2**24-1) begin
+          warning_long_throttle   <= 1'b1;
+        end
+      end else begin
+        counter_throttle          <= 0;
+      end
+      // More than M outputs per N inputs
+      if (word_cnt_div_n_fifo_tvalid & (word_cnt_div_m > word_cnt_div_n_fifo_tdata)) begin
+        error_extra_outputs         <= 1'b1;
+      end
+      // Bad internal state. AXI drop partial packet is in a lockup condition.
+      if (~i_reg_tready_int & m_axis_data_tready) begin
+        counter_drop_pkt_lockup     <= counter_drop_pkt_lockup + 1;
+        if (counter_drop_pkt_lockup == 2**24-1) begin
+          error_drop_pkt_lockup     <= 1'b1;
+        end
+      end else begin
+        counter_drop_pkt_lockup     <= 0;
+      end
+    end
+  end
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/axi_repeat.v b/fpga/usrp3/lib/rfnoc/axi_repeat.v
new file mode 100644
index 000000000..c19d6962a
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/axi_repeat.v
@@ -0,0 +1,31 @@
+//
+// Copyright 2015 Ettus Research
+//
+// Output always valid (except in reset) and repeats last valid i_tdata & i_tlast value
+
+module axi_repeat
+#(
+  parameter WIDTH = 16) 
+(
+  input clk, input reset,
+  input [WIDTH-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
+  output reg [WIDTH-1:0] o_tdata, output reg o_tlast, output reg o_tvalid, input o_tready
+);
+
+  assign i_tready = 1'b1;
+
+  always @(posedge clk) begin
+    if (reset) begin
+      o_tdata  <= 'd0;
+      o_tlast  <= 'd0;
+      o_tvalid <= 'd0;
+    end else begin
+      if (i_tvalid) begin
+        o_tvalid <= 1'b1;
+        o_tlast  <= i_tlast;
+        o_tdata  <= o_tdata;
+      end
+    end
+  end
+
+endmodule
\ No newline at end of file
diff --git a/fpga/usrp3/lib/rfnoc/axi_round.v b/fpga/usrp3/lib/rfnoc/axi_round.v
new file mode 100644
index 000000000..75a343ba5
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/axi_round.v
@@ -0,0 +1,56 @@
+//
+// Copyright 2016 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module axi_round
+  #(parameter WIDTH_IN=17,
+    parameter WIDTH_OUT=16,
+    parameter round_to_zero=0,       // original behavior
+    parameter round_to_nearest=1,    // lowest noise
+    parameter trunc=0,               // round to negative infinity
+    parameter FIFOSIZE=0)  // leave at 0 for a normal single flop
+   (input clk, input reset,
+    input [WIDTH_IN-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
+    output [WIDTH_OUT-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready);
+
+  wire [WIDTH_OUT-1:0] out;
+
+  generate
+    if (WIDTH_IN == WIDTH_OUT) begin
+      assign o_tdata = i_tdata;
+      assign o_tlast = i_tlast;
+      assign o_tvalid = i_tvalid;
+      assign i_tready = o_tready;
+    end else begin
+      wire round_corr,round_corr_trunc,round_corr_rtz,round_corr_nearest,round_corr_nearest_safe;
+      wire [WIDTH_IN-WIDTH_OUT-1:0] err;
+
+      assign round_corr_trunc = 0;
+      assign round_corr_rtz = (i_tdata[WIDTH_IN-1] & |i_tdata[WIDTH_IN-WIDTH_OUT-1:0]);
+      assign round_corr_nearest = i_tdata[WIDTH_IN-WIDTH_OUT-1];
+
+      assign round_corr_nearest_safe =  (WIDTH_IN-WIDTH_OUT > 1) ? 
+                                        ((~i_tdata[WIDTH_IN-1] & (&i_tdata[WIDTH_IN-2:WIDTH_IN-WIDTH_OUT])) ? 1'b0 : round_corr_nearest) :
+                                        round_corr_nearest;
+
+      assign round_corr = round_to_nearest ? round_corr_nearest_safe :
+                          trunc ? round_corr_trunc : 
+                          round_to_zero ? round_corr_rtz :
+                          0;  // default to trunc
+
+      assign out = i_tdata[WIDTH_IN-1:WIDTH_IN-WIDTH_OUT] + round_corr;
+
+      assign err = i_tdata - {out,{(WIDTH_IN-WIDTH_OUT){1'b0}}};
+
+      axi_fifo #(.WIDTH(WIDTH_OUT+1), .SIZE(FIFOSIZE)) flop
+        (.clk(clk), .reset(reset), .clear(1'b0),
+         .i_tdata({i_tlast, out}), .i_tvalid(i_tvalid), .i_tready(i_tready),
+         .o_tdata({o_tlast, o_tdata}), .o_tvalid(o_tvalid), .o_tready(o_tready),
+         .occupied(), .space());
+
+   end
+  endgenerate
+
+endmodule // axi_round
diff --git a/fpga/usrp3/lib/rfnoc/axi_round_and_clip.v b/fpga/usrp3/lib/rfnoc/axi_round_and_clip.v
new file mode 100644
index 000000000..781e85ec3
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/axi_round_and_clip.v
@@ -0,0 +1,69 @@
+//
+// Copyright 2014, Ettus Research
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+//
+// Reduce the bitwidth of an input stream. This module will both round
+// and clip, meaning that the lower bits will be removed by rounding to
+// the nearest value, and the top bits will be snipped (but without
+// causing numerical overflows).
+//
+// Example: If WIDTH_IN==24, WIDTH_OUT==16, and CLIP_BITS==3, the output
+// Will remove the top 3 bits (by clipping), and remove the bottom 5
+// bits by rounding, leaving 24 - 3 - 5 == 16 bits.
+//
+// Note that this module has two stages (round, then clip) which will
+// both have a FIFO of length FIFOSIZE. However, when a stage is not
+// required it will have *no* FIFO, but instead just pass through the
+// data. In the extreme case where WIDTH_IN==WIDTH_OUT and CLIP_BITS==0,
+// there are no FIFOs and this module becomes an AXI stream passthrough.
+module axi_round_and_clip
+#(
+  parameter WIDTH_IN=24,
+  parameter WIDTH_OUT=16,
+  parameter CLIP_BITS=3,
+  parameter FIFOSIZE=1)  // FIFOSIZE = 1, single output register
+(
+  input clk, input reset,
+  input [WIDTH_IN-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
+  output [WIDTH_OUT-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready
+);
+
+  wire [WIDTH_OUT+CLIP_BITS-1:0] int_tdata;
+  wire int_tlast, int_tvalid, int_tready;
+
+  generate
+    if (WIDTH_IN == WIDTH_OUT+CLIP_BITS) begin
+       assign int_tdata    = i_tdata;
+       assign int_tlast    = i_tlast;
+       assign int_tvalid   = i_tvalid;
+       assign i_tready     = int_tready;
+    end else begin
+      axi_round #(
+        .WIDTH_IN(WIDTH_IN), .WIDTH_OUT(WIDTH_OUT+CLIP_BITS),
+        .round_to_nearest(1), .FIFOSIZE(FIFOSIZE))
+      axi_round (
+        .clk(clk), .reset(reset),
+        .i_tdata(i_tdata), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready),
+        .o_tdata(int_tdata), .o_tlast(int_tlast), .o_tvalid(int_tvalid), .o_tready(int_tready));
+    end
+
+    if (CLIP_BITS == 0) begin
+      assign o_tdata    = int_tdata;
+      assign o_tlast    = int_tlast;
+      assign o_tvalid   = int_tvalid;
+      assign int_tready = o_tready;
+    end else begin
+      axi_clip #(
+        .WIDTH_IN(WIDTH_OUT+CLIP_BITS), .WIDTH_OUT(WIDTH_OUT),
+        .FIFOSIZE(FIFOSIZE))
+      axi_clip (
+        .clk(clk), .reset(reset),
+        .i_tdata(int_tdata), .i_tlast(int_tlast), .i_tvalid(int_tvalid), .i_tready(int_tready),
+        .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready));
+    end
+  endgenerate
+
+endmodule // round_and_clip
diff --git a/fpga/usrp3/lib/rfnoc/axi_round_and_clip_complex.v b/fpga/usrp3/lib/rfnoc/axi_round_and_clip_complex.v
new file mode 100644
index 000000000..c3e446509
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/axi_round_and_clip_complex.v
@@ -0,0 +1,43 @@
+
+
+// Copyright 2014, Ettus Research
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+
+module axi_round_and_clip_complex
+  #(parameter WIDTH_IN=24,
+    parameter WIDTH_OUT=16,
+    parameter CLIP_BITS=3,
+    parameter FIFOSIZE=1)  // FIFOSIZE = 1, single output register
+   (input clk, input reset,
+    input [2*WIDTH_IN-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
+    output [2*WIDTH_OUT-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready);
+
+   wire [WIDTH_IN-1:0]      ii_tdata, iq_tdata;
+   wire                     ii_tlast, ii_tvalid, ii_tready, iq_tlast, iq_tvalid, iq_tready;
+
+   wire [WIDTH_OUT-1:0]     oi_tdata, oq_tdata;
+   wire                     oi_tlast, oi_tvalid, oi_tready, oq_tlast, oq_tvalid, oq_tready;
+
+   split_complex #(.WIDTH(WIDTH_IN)) split
+     (.i_tdata(i_tdata), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready),
+      .oi_tdata(ii_tdata), .oi_tlast(ii_tlast), .oi_tvalid(ii_tvalid), .oi_tready(ii_tready),
+      .oq_tdata(iq_tdata), .oq_tlast(iq_tlast), .oq_tvalid(iq_tvalid), .oq_tready(iq_tready));
+
+   axi_round_and_clip #(.WIDTH_IN(WIDTH_IN), .WIDTH_OUT(WIDTH_OUT), .CLIP_BITS(CLIP_BITS), .FIFOSIZE(FIFOSIZE)) r_and_c_i
+     (.clk(clk), .reset(reset),
+      .i_tdata(ii_tdata), .i_tlast(ii_tlast), .i_tvalid(ii_tvalid), .i_tready(ii_tready),
+      .o_tdata(oi_tdata), .o_tlast(oi_tlast), .o_tvalid(oi_tvalid), .o_tready(oi_tready));
+
+   axi_round_and_clip #(.WIDTH_IN(WIDTH_IN), .WIDTH_OUT(WIDTH_OUT), .CLIP_BITS(CLIP_BITS), .FIFOSIZE(FIFOSIZE)) r_and_c_q
+     (.clk(clk), .reset(reset),
+      .i_tdata(iq_tdata), .i_tlast(iq_tlast), .i_tvalid(iq_tvalid), .i_tready(iq_tready),
+      .o_tdata(oq_tdata), .o_tlast(oq_tlast), .o_tvalid(oq_tvalid), .o_tready(oq_tready));
+   
+   join_complex #(.WIDTH(WIDTH_OUT)) join_complex
+     (.ii_tdata(oi_tdata), .ii_tlast(oi_tlast), .ii_tvalid(oi_tvalid), .ii_tready(oi_tready),
+      .iq_tdata(oq_tdata), .iq_tlast(oq_tlast), .iq_tvalid(oq_tvalid), .iq_tready(oq_tready),
+      .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready));
+
+endmodule // round_and_clip_complex
diff --git a/fpga/usrp3/lib/rfnoc/axi_round_complex.v b/fpga/usrp3/lib/rfnoc/axi_round_complex.v
new file mode 100644
index 000000000..d108c6abd
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/axi_round_complex.v
@@ -0,0 +1,43 @@
+//
+// Copyright 2016 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module axi_round_complex #(
+  parameter WIDTH_IN  = 24,
+  parameter WIDTH_OUT = 16,
+  parameter FIFOSIZE  = 0)  // leave at 0 for a normal single flop
+(
+  input clk, input reset,
+  input [2*WIDTH_IN-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
+  output [2*WIDTH_OUT-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready
+);
+
+  wire [WIDTH_IN-1:0]  ii_tdata, iq_tdata;
+  wire                 ii_tlast, ii_tvalid, ii_tready, iq_tlast, iq_tvalid, iq_tready;
+
+  wire [WIDTH_OUT-1:0] oi_tdata, oq_tdata;
+  wire                 oi_tlast, oi_tvalid, oi_tready, oq_tlast, oq_tvalid, oq_tready;
+
+  split_complex #(.WIDTH(WIDTH_IN)) split_complex (
+    .i_tdata(i_tdata), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready),
+    .oi_tdata(ii_tdata), .oi_tlast(ii_tlast), .oi_tvalid(ii_tvalid), .oi_tready(ii_tready),
+    .oq_tdata(iq_tdata), .oq_tlast(iq_tlast), .oq_tvalid(iq_tvalid), .oq_tready(iq_tready));
+
+  axi_round #(.WIDTH_IN(WIDTH_IN), .WIDTH_OUT(WIDTH_OUT), .FIFOSIZE(FIFOSIZE)) axi_round_i (
+    .clk(clk), .reset(reset),
+    .i_tdata(ii_tdata), .i_tlast(ii_tlast), .i_tvalid(ii_tvalid), .i_tready(ii_tready),
+    .o_tdata(oi_tdata), .o_tlast(oi_tlast), .o_tvalid(oi_tvalid), .o_tready(oi_tready));
+
+  axi_round #(.WIDTH_IN(WIDTH_IN), .WIDTH_OUT(WIDTH_OUT), .FIFOSIZE(FIFOSIZE)) axi_round_q (
+    .clk(clk), .reset(reset),
+    .i_tdata(iq_tdata), .i_tlast(iq_tlast), .i_tvalid(iq_tvalid), .i_tready(iq_tready),
+    .o_tdata(oq_tdata), .o_tlast(oq_tlast), .o_tvalid(oq_tvalid), .o_tready(oq_tready));
+
+  join_complex #(.WIDTH(WIDTH_OUT)) join_complex (
+    .ii_tdata(oi_tdata), .ii_tlast(oi_tlast), .ii_tvalid(oi_tvalid), .ii_tready(oi_tready),
+    .iq_tdata(oq_tdata), .iq_tlast(oq_tlast), .iq_tvalid(oq_tvalid), .iq_tready(oq_tready),
+    .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready));
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/axi_serializer.v b/fpga/usrp3/lib/rfnoc/axi_serializer.v
new file mode 100644
index 000000000..f71a54767
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/axi_serializer.v
@@ -0,0 +1,72 @@
+//
+// Copyright 2015 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module axi_serializer #(
+  parameter WIDTH = 32)
+(
+  input clk, input rst, input reverse_input,
+  input [WIDTH-1:0] i_tdata, input  i_tlast, input i_tvalid,  output reg i_tready,
+  output reg o_tdata, output reg o_tlast, output reg o_tvalid, input o_tready
+);
+
+  reg i_tlast_latch;
+  reg [WIDTH-1:0] serial_data_reg;
+  reg [$clog2(WIDTH)-1:0] serial_cnt;
+  reg serializing;
+
+  always @(posedge clk) begin
+    if (rst) begin
+      i_tready        <= 1'b0;
+      i_tlast_latch   <= 1'b0;
+      o_tdata         <= 1'b0;
+      o_tlast         <= 1'b0;
+      o_tvalid        <= 1'b0;
+      serial_data_reg <= 'd0;
+      serializing     <= 1'b0;
+      serial_cnt      <= 0;
+    end else begin
+      i_tready <= 1'b0;
+      // Shift out a bit when downstream can consume it
+      if (serializing & o_tready) begin
+        o_tvalid <= 1'b1;
+        if (reverse_input) begin
+          o_tdata                    <= serial_data_reg[0];
+          serial_data_reg[WIDTH-2:0] <= serial_data_reg[WIDTH-1:1];
+        end else begin
+          o_tdata                    <= serial_data_reg[WIDTH-1];
+          serial_data_reg[WIDTH-1:1] <= serial_data_reg[WIDTH-2:0];
+        end
+        if (serial_cnt == WIDTH-1) begin
+          serial_cnt      <= 0;
+          serial_data_reg <= i_tdata;
+          i_tlast_latch   <= i_tlast;
+          o_tlast         <= i_tlast_latch;
+          if (~i_tvalid) begin
+            serializing <= 1'b0;
+          end else begin
+            i_tready <= 1'b1;
+          end
+        end else begin
+          serial_cnt <= serial_cnt + 1;
+        end
+      end else if (~serializing) begin
+        i_tready <= 1'b1;
+        if (o_tvalid && o_tready) begin
+          o_tvalid <= 1'b0;
+        end
+        // Serial shift register (serial_data_reg) is empty, load it 
+        if (i_tvalid) begin
+          i_tready        <= 1'b0;
+          serializing     <= 1'b1;
+          i_tlast_latch   <= i_tlast;
+          serial_data_reg <= i_tdata;
+        end
+      end
+    end
+  end
+
+endmodule
\ No newline at end of file
diff --git a/fpga/usrp3/lib/rfnoc/axi_sync.v b/fpga/usrp3/lib/rfnoc/axi_sync.v
new file mode 100644
index 000000000..a881a5556
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/axi_sync.v
@@ -0,0 +1,63 @@
+//
+// Copyright 2016 Ettus Research
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Synchronizes AXI stream buses so data is released on every port simultaneously.
+//
+// Note: If inputs have inequal bitwidths, use WIDTH_VEC instead of WIDTH to define
+//       the individual bit widths. Each bit width is defined with 8-bits stuffed
+//       into a vector of width 8*SIZE.
+//
+
+module axi_sync #(
+  parameter               SIZE      = 2,
+  parameter               WIDTH     = 32,
+  parameter [32*SIZE-1:0] WIDTH_VEC = {SIZE{WIDTH[31:0]}},
+  parameter               FIFO_SIZE = 0
+)(
+  input clk, input reset, input clear,
+  input [msb(SIZE,WIDTH_VEC)-1:0] i_tdata, input  [SIZE-1:0] i_tlast, input  [SIZE-1:0] i_tvalid, output [SIZE-1:0] i_tready,
+  output [msb(SIZE,WIDTH_VEC)-1:0] o_tdata, output [SIZE-1:0] o_tlast, output [SIZE-1:0] o_tvalid, input  [SIZE-1:0] o_tready
+);
+
+  // Helper function to calculate the MSB index based on widths stored in WIDTH_VEC.
+  // Note: If n is negative, returns 0
+  function automatic integer msb(input integer n, input [SIZE*32-1:0] bit_vec);
+    integer i, total;
+  begin
+    total = 0;
+    if (n >= 0) begin
+      for (i = 0; i <= n; i = i + 1) begin
+        total = total + ((bit_vec >> 32*i) & 32'hFF);
+      end
+    end
+    msb = total;
+  end
+  endfunction
+
+  wire [msb(SIZE,WIDTH_VEC)-1:0] int_tdata;
+  wire [SIZE-1:0] int_tlast, int_tvalid, int_tready;
+
+  genvar i;
+  generate
+    for (i = 0; i < SIZE; i = i + 1) begin
+      axi_fifo #(.WIDTH(msb(i,WIDTH_VEC)-msb(i-1,WIDTH_VEC)+1), .SIZE(FIFO_SIZE)) axi_fifo (
+        .clk(clk), .reset(reset), .clear(clear),
+        .i_tdata({i_tlast[i],i_tdata[msb(i,WIDTH_VEC)-1:msb(i-1,WIDTH_VEC)]}),
+        .i_tvalid(i_tvalid[i]), .i_tready(i_tready[i]),
+        .o_tdata({int_tlast[i],int_tdata[msb(i,WIDTH_VEC)-1:msb(i-1,WIDTH_VEC)]}),
+        .o_tvalid(int_tvalid[i]), .o_tready(int_tready[i]),
+        .space(), .occupied());
+    end
+  endgenerate
+
+  assign o_tdata    = int_tdata;
+  assign o_tlast    = int_tlast;
+
+  wire consume = (&int_tvalid) & (&o_tready);
+  assign int_tready = {SIZE{consume}};
+  assign o_tvalid   = {SIZE{consume}};
+
+endmodule
\ No newline at end of file
diff --git a/fpga/usrp3/lib/rfnoc/axi_tag_time.v b/fpga/usrp3/lib/rfnoc/axi_tag_time.v
new file mode 100644
index 000000000..35698ef72
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/axi_tag_time.v
@@ -0,0 +1,140 @@
+//
+// Copyright 2016 Ettus Research
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// - When the user executes a timed settings bus command,
+//   this module will tag the sample (on m_axis_data_tuser)
+//   that the command should apply on.
+// - Order of operation:
+//   1) Receives settings bus command
+//      a) If time != 0, output on non-timed settings bus
+//      b) If time != 0, output on timed settings bus and store time in FIFO
+//         It is assumed the user will use timed_settings_bus.v implementation.
+//   2) 
+
+module axi_tag_time #(
+  parameter WIDTH            = 32,
+  parameter HEADER_WIDTH     = 128,
+  parameter SR_AWIDTH        = 8,
+  parameter SR_DWIDTH        = 32,
+  parameter SR_TWIDTH        = 64,
+  parameter NUM_TAGS         = 1,
+  parameter [NUM_TAGS*SR_AWIDTH-1:0] SR_TAG_ADDRS = 0,
+  parameter CMD_FIFO_SIZE    = 5,
+  parameter MAX_TICK_RATE    = 2**16-1
+)(
+  input clk,
+  input reset,
+  input clear,
+  input [$clog2(MAX_TICK_RATE)-1:0] tick_rate,
+  output timed_cmd_fifo_full,
+  // From AXI Wrapper
+  input [WIDTH-1:0] s_axis_data_tdata,
+  input [HEADER_WIDTH-1:0] s_axis_data_tuser,
+  input s_axis_data_tlast,
+  input s_axis_data_tvalid,
+  output s_axis_data_tready,
+  // To user
+  output [WIDTH-1:0] m_axis_data_tdata,
+  output [HEADER_WIDTH-1:0] m_axis_data_tuser,
+  output [NUM_TAGS-1:0] m_axis_data_tag,
+  output m_axis_data_tlast,
+  output m_axis_data_tvalid,
+  input m_axis_data_tready,
+  // Settings bus from Noc Shell
+  input in_set_stb,
+  input [SR_AWIDTH-1:0] in_set_addr,
+  input [SR_DWIDTH-1:0] in_set_data,
+  input [SR_TWIDTH-1:0] in_set_time,
+  input in_set_has_time,
+  // Non-timed settings bus to user
+  output out_set_stb,
+  output [SR_AWIDTH-1:0] out_set_addr,
+  output [SR_DWIDTH-1:0] out_set_data,
+  // Timed settings bus to user
+  output timed_set_stb,
+  output [SR_AWIDTH-1:0] timed_set_addr,
+  output [SR_DWIDTH-1:0] timed_set_data
+);
+
+  assign out_set_addr = in_set_addr;
+  assign out_set_data = in_set_data;
+  assign out_set_stb  = in_set_stb & ~in_set_has_time;
+  assign timed_set_addr = in_set_addr;
+  assign timed_set_data = in_set_data;
+  assign timed_set_stb  = in_set_stb & in_set_has_time;
+
+  // Extract vita time from tuser
+  wire [63:0] vita_time_in;
+  cvita_hdr_decoder cvita_hdr_decoder_in (
+    .header(s_axis_data_tuser),
+    .pkt_type(), .eob(), .has_time(),
+    .seqnum(), .length(), .payload_length(),
+    .src_sid(), .dst_sid(),
+    .vita_time(vita_time_in));
+
+  // Track time
+  reg header_valid = 1'b1;
+  reg [63:0] vita_time_now = 64'd0, set_time_hold = 64'd0;
+  always @(posedge clk) begin
+    if (reset | clear) begin
+      header_valid     <= 1'b1;
+    end else begin
+      if (s_axis_data_tvalid & s_axis_data_tready) begin
+        if (s_axis_data_tlast) begin
+          header_valid <= 1'b1;
+        end else begin
+          header_valid <= 1'b0;
+        end
+        if (header_valid) begin
+          vita_time_now <= vita_time_in;
+        end else begin
+          vita_time_now <= vita_time_now + tick_rate;
+        end
+      end
+    end
+  end
+
+  genvar i;
+  wire [NUM_TAGS-1:0] tags;
+  generate
+    for (i = 0; i < NUM_TAGS; i = i + 1) begin
+      assign tags[i] = (in_set_addr == SR_TAG_ADDRS[SR_AWIDTH*(i+1)-1:SR_AWIDTH*i]);
+    end
+  endgenerate
+
+  // FIFO to hold tags + times
+  wire [SR_TWIDTH-1:0] fifo_set_time;
+  wire [NUM_TAGS-1:0] fifo_tags;
+  wire fifo_tvalid, fifo_tready;
+  wire timed_cmd_fifo_full_n;
+  axi_fifo #(.WIDTH(SR_TWIDTH+NUM_TAGS), .SIZE(CMD_FIFO_SIZE)) axi_fifo (
+    .clk(clk), .reset(reset), .clear(clear),
+    .i_tdata({in_set_time,tags}), .i_tvalid(timed_set_stb), .i_tready(timed_cmd_fifo_full_n),
+    .o_tdata({fifo_set_time,fifo_tags}), .o_tvalid(fifo_tvalid), .o_tready(fifo_tready),
+    .space(), .occupied());
+
+  // Extract has time from tuser
+  wire has_time;
+  cvita_hdr_decoder cvita_hdr_decoder_out (
+    .header(m_axis_data_tuser),
+    .pkt_type(), .eob(), .has_time(has_time),
+    .seqnum(), .length(), .payload_length(),
+    .src_sid(), .dst_sid(),
+    .vita_time());
+
+  assign timed_cmd_fifo_full = ~timed_cmd_fifo_full_n;
+  assign fifo_tready = m_axis_data_tvalid & m_axis_data_tready & fifo_tvalid & has_time & (vita_time_now >= fifo_set_time);
+  assign in_rb_stb = fifo_tready;
+
+  // Need a single cycle delay to allow vita_time_now to update at the start of a new packet
+  axi_fifo_flop #(.WIDTH(WIDTH+HEADER_WIDTH+1)) axi_fifo_flop (
+    .clk(clk), .reset(reset), .clear(clear),
+    .i_tdata({s_axis_data_tdata,s_axis_data_tuser,s_axis_data_tlast}), .i_tvalid(s_axis_data_tvalid), .i_tready(s_axis_data_tready),
+    .o_tdata({m_axis_data_tdata,m_axis_data_tuser,m_axis_data_tlast}), .o_tvalid(m_axis_data_tvalid), .o_tready(m_axis_data_tready));
+
+  assign m_axis_data_tag = ((vita_time_now >= fifo_set_time) & fifo_tvalid & has_time) ? fifo_tags : 'd0;
+
+endmodule
\ No newline at end of file
diff --git a/fpga/usrp3/lib/rfnoc/axi_wrapper.v b/fpga/usrp3/lib/rfnoc/axi_wrapper.v
new file mode 100644
index 000000000..f93a693b8
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/axi_wrapper.v
@@ -0,0 +1,217 @@
+//
+// Copyright 2015 Ettus Research
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Assumes 32-bit elements (such as sc16) carried over AXI-Stream
+// SIMPLE_MODE          -- Automatically handle header (s_axis_data_tuser), packets must be consumed / produced 1-to-1
+// RESIZE_INPUT_PACKET  -- Resize input packets. m_axis_data_tlast will be based on m_axis_pkt_len_tdata. Otherwise packet length based on actual input packet length (via i_tlast).
+// RESIZE_OUTPUT_PACKET -- Resize output packets. s_axis_data_tlast will be ignored and instead use packet length in s_axis_tuser_data. Otherwise use s_axis_data_tlast.
+//
+// Note: When SIMPLE_MODE = 1 and RESIZE_OUTPUT_PACKET = 1, s_axis_data_tlast is ignored and output packets are sized according to the length
+//       of the input packet (via the packet length field in the received header). Useful if the user design wants output packet length to 
+//       match the input packet length without having to drive s_axis_data_tlast.
+//
+// *** Warning: Care should be taken when using RESIZE_INPUT_PACKET and/or RESIZE_OUTPUT_PACKET along with SIMPLE_MODE
+//              as issues could arise if packets are not produced / consumed in a 1:1 ratio. For instance, the header
+//              FIFO could overflow or underflow.
+
+// _tuser bit definitions
+//  [127:64] == CHDR header
+//    [127:126] == Packet type -- 00 for data, 01 for flow control, 10 for command, 11 for response
+//    [125]     == Has time? (0 for no, 1 for time field on next line)
+//    [124]     == EOB (end of burst indicator)
+//    [123:112] == 12-bit sequence number
+//    [111: 96] == 16-bit length in bytes
+//    [ 95: 80] == SRC SID (stream ID)
+//    [ 79: 64] == DST SID
+//  [ 63: 0] == timestamp
+
+module axi_wrapper
+  #(parameter MTU=10,
+    parameter SR_AXI_CONFIG_BASE=129,   // AXI configuration bus base, settings bus address range size is 2*NUM_AXI_CONFIG_BUS
+    parameter NUM_AXI_CONFIG_BUS=1,     // Number of AXI configuration buses
+    parameter CONFIG_BUS_FIFO_DEPTH=1,  // Depth of AXI configuration bus FIFO. Note: AXI configuration bus lacks back pressure.
+    parameter SIMPLE_MODE=1,            // 0 = User handles CHDR insertion via tuser signals, 1 = Automatically save / insert CHDR with internal FIFO
+    parameter USE_SEQ_NUM=0,            // 0 = Frame will automatically handle sequence number, 1 = Use sequence number provided in s_axis_data_tuser
+    parameter RESIZE_INPUT_PACKET=0,    // 0 = Do not resize, packet length determined by i_tlast, 1 = Generate m_axis_data_tlast based on user input m_axis_pkt_len_tdata
+    parameter RESIZE_OUTPUT_PACKET=0,   // 0 = Do not resize, packet length determined by s_axis_data_tlast, 1 = Use packet length from user header (s_axis_data_tuser)
+    parameter WIDTH=32)                 // Specify the output width for the AXI stream data (can be 32 or 64)
+   (input clk, input reset,
+    input bus_clk, input bus_rst,
+
+    input clear_tx_seqnum,
+    input [15:0] next_dst,              // Used with SIMPLE_MODE=1
+
+    // To NoC Shell
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    input [63:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
+    output [63:0] o_tdata, output o_tlast, output o_tvalid, input o_tready,
+
+    // To AXI IP
+    output [WIDTH-1:0] m_axis_data_tdata, output [127:0] m_axis_data_tuser, output m_axis_data_tlast, output m_axis_data_tvalid, input m_axis_data_tready,
+    input [WIDTH-1:0] s_axis_data_tdata, input [127:0] s_axis_data_tuser, input s_axis_data_tlast, input s_axis_data_tvalid, output s_axis_data_tready, 
+    input [15:0] m_axis_pkt_len_tdata, input m_axis_pkt_len_tvalid, output m_axis_pkt_len_tready, // Used when RESIZE_INPUT_PACKET=1
+
+    // Variable number of AXI configuration buses
+    output [NUM_AXI_CONFIG_BUS*32-1:0] m_axis_config_tdata,
+    output [NUM_AXI_CONFIG_BUS-1:0] m_axis_config_tlast,
+    output [NUM_AXI_CONFIG_BUS-1:0] m_axis_config_tvalid,
+    input [NUM_AXI_CONFIG_BUS-1:0] m_axis_config_tready
+    );
+
+
+   wire clear_tx_seqnum_bclk;
+   pulse_synchronizer clear_tx_seqnum_sync_i (
+     .clk_a(clk), .rst_a(reset), .pulse_a(clear_tx_seqnum), .busy_a(/*Ignored: Pulses from SW are slow*/),
+     .clk_b(bus_clk), .pulse_b(clear_tx_seqnum_bclk)
+   );
+
+   // /////////////////////////////////////////////////////////
+   // Input side handling, chdr_deframer
+   wire [127:0] s_axis_data_tuser_int, m_axis_data_tuser_int;
+   wire         s_axis_data_tlast_int, m_axis_data_tlast_int;
+   reg [15:0]   m_axis_pkt_len_reg = 16'd8;
+   reg          sof_in = 1'b1;
+   wire [127:0] header_fifo_i_tdata  = {m_axis_data_tuser[127:96],m_axis_data_tuser[79:64],next_dst,m_axis_data_tuser[63:0]};
+   wire         header_fifo_i_tvalid = sof_in & m_axis_data_tvalid & m_axis_data_tready;
+
+   chdr_deframer_2clk #(.WIDTH(WIDTH)) chdr_deframer (
+      .samp_clk(clk), .samp_rst(reset | clear_tx_seqnum), .pkt_clk(bus_clk), .pkt_rst(bus_rst | clear_tx_seqnum_bclk),
+      .i_tdata(i_tdata), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready),
+      .o_tdata(m_axis_data_tdata), .o_tuser(m_axis_data_tuser_int), .o_tlast(m_axis_data_tlast_int), .o_tvalid(m_axis_data_tvalid), .o_tready(m_axis_data_tready)
+   );
+
+   assign m_axis_data_tuser[127:80] = m_axis_data_tuser_int[127:80];
+   assign m_axis_data_tuser[79:64]  = RESIZE_INPUT_PACKET ? (m_axis_data_tuser_int[125] ? m_axis_pkt_len_reg+16 : m_axis_pkt_len_reg+8) : m_axis_data_tuser_int[79:64];
+   assign m_axis_data_tuser[63:0]   = m_axis_data_tuser_int[63:0];
+
+   // Only store header once per packet
+   always @(posedge clk)
+     if(reset | clear_tx_seqnum)
+       sof_in     <= 1'b1;
+     else
+       if(m_axis_data_tvalid & m_axis_data_tready)
+         if(m_axis_data_tlast)
+           sof_in <= 1'b1;
+         else
+           sof_in <= 1'b0;
+
+   // SIMPLE MODE: Store input packet header to reuse as output packet header.
+   generate
+      if(SIMPLE_MODE)
+         begin
+            // FIFO 
+            axi_fifo #(.WIDTH(128), .SIZE(5)) header_fifo
+            (.clk(clk), .reset(reset), .clear(clear_tx_seqnum),
+             .i_tdata(header_fifo_i_tdata),
+             .i_tvalid(header_fifo_i_tvalid), .i_tready(),
+             .o_tdata(s_axis_data_tuser_int), .o_tvalid(), .o_tready(s_axis_data_tlast_int & s_axis_data_tvalid & s_axis_data_tready),
+             .occupied(), .space());
+      end else begin
+        assign s_axis_data_tuser_int = s_axis_data_tuser;
+      end
+   endgenerate
+
+   // RESIZE INPUT PACKET
+   // Size input packets based on m_axis_pkt_len_tdata (RESIZE_INPUT_PACKET=1) or based on i_tdata
+   generate
+     if (RESIZE_INPUT_PACKET) begin
+       reg m_axis_data_tlast_reg;
+       reg [15:0] m_axis_pkt_cnt;
+       always @(posedge clk) begin
+         if (reset | clear_tx_seqnum) begin
+           m_axis_data_tlast_reg <= 1'b0;
+           m_axis_pkt_cnt        <= (WIDTH/8);   // Number of bytes in packet
+           m_axis_pkt_len_reg    <= 2*(WIDTH/8); // Double size by default
+         end else begin
+           // Only update packet length at the beginning of a new packet
+           if (m_axis_pkt_len_tvalid & m_axis_pkt_len_tready) begin
+             m_axis_pkt_len_reg <= m_axis_pkt_len_tdata;
+           end
+           if (m_axis_data_tvalid & m_axis_data_tready) begin
+             if (m_axis_pkt_cnt >= m_axis_pkt_len_reg) begin
+               m_axis_pkt_cnt        <= (WIDTH/8);
+             end else begin
+               m_axis_pkt_cnt        <= m_axis_pkt_cnt + (WIDTH/8);
+             end
+             if (m_axis_pkt_cnt >= m_axis_pkt_len_reg-(WIDTH/8)) begin
+               m_axis_data_tlast_reg <= 1'b1;
+             end else begin
+               m_axis_data_tlast_reg <= 1'b0;
+             end
+           end
+         end
+       end
+       assign m_axis_data_tlast     = m_axis_data_tlast_reg;
+       assign m_axis_pkt_len_tready = sof_in;
+     end else begin
+       assign m_axis_data_tlast     = m_axis_data_tlast_int;
+       assign m_axis_pkt_len_tready = 1'b0;
+     end
+   endgenerate
+
+   // RESIZE OUTPUT PACKET
+   // Size output packets based on either s_axis_data_tlast (RESIZE_OUTPUT_PACKETS=1) or packet length from user header (s_axis_data_tuser)
+   // TODO: There could be a race condition on s_axis_data_tuser_int when
+   //       receiving very short packets, but latency in chdr_deframer
+   //       prevents this from occurring. Need to fix so it cannot
+   //       occur by design.
+   generate
+     if (RESIZE_OUTPUT_PACKET) begin
+       reg [15:0] s_axis_pkt_cnt;
+       reg [15:0] s_axis_pkt_len;
+       always @(posedge clk) begin
+         if (reset | clear_tx_seqnum) begin
+           s_axis_pkt_cnt        <= (WIDTH/8);
+           s_axis_pkt_len        <= 0;
+         end else begin
+           // Remove header
+           s_axis_pkt_len <= s_axis_data_tuser_int[125] ? s_axis_data_tuser_int[111:96]-16 : s_axis_data_tuser_int[111:96]-8;
+           if (s_axis_data_tvalid & s_axis_data_tready) begin
+             if ((s_axis_pkt_cnt >= s_axis_pkt_len) | s_axis_data_tlast) begin
+               s_axis_pkt_cnt        <= (WIDTH/8);
+             end else begin
+               s_axis_pkt_cnt        <= s_axis_pkt_cnt + (WIDTH/8);
+             end
+           end
+         end
+       end
+       assign s_axis_data_tlast_int = (s_axis_pkt_cnt >= s_axis_pkt_len) | s_axis_data_tlast;
+     end else begin
+       // chdr_framer will automatically fill in the packet length based on user provided tlast
+       assign s_axis_data_tlast_int = s_axis_data_tlast;
+     end
+   endgenerate
+
+   // /////////////////////////////////////////////////////////
+   // Output side handling, chdr_framer
+   chdr_framer_2clk #(.SIZE(MTU), .WIDTH(WIDTH), .USE_SEQ_NUM(USE_SEQ_NUM)) chdr_framer (
+      .samp_clk(clk), .samp_rst(reset | clear_tx_seqnum), .pkt_clk(bus_clk), .pkt_rst(bus_rst | clear_tx_seqnum_bclk),
+      .i_tdata(s_axis_data_tdata), .i_tuser(s_axis_data_tuser_int), .i_tlast(s_axis_data_tlast_int), .i_tvalid(s_axis_data_tvalid), .i_tready(s_axis_data_tready),
+      .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready)
+   );
+
+   // /////////////////////////////////////////////////////////
+   // Control bus handling
+   // FIXME we could put inline control here...
+   // Generate additional AXI stream interfaces for configuration. 
+   // FIXME need to make sure we don't overrun this if core can backpressure us
+   // Write to SR_AXI_CONFIG_BASE+1+2*(CONFIG BUS #) asserts tvalid, SR_AXI_CONFIG_BASE+1+2*(CONFIG BUS #)+1 asserts tvalid & tlast
+   genvar k;
+   generate
+      for (k = 0; k < NUM_AXI_CONFIG_BUS; k = k + 1) begin
+         axi_fifo #(.WIDTH(33), .SIZE(CONFIG_BUS_FIFO_DEPTH)) config_stream
+           (.clk(clk), .reset(reset), .clear(clear_tx_seqnum),
+            .i_tdata({(set_addr == (SR_AXI_CONFIG_BASE+2*k+1)),set_data}),
+            .i_tvalid(set_stb & ((set_addr == (SR_AXI_CONFIG_BASE+2*k))|(set_addr == (SR_AXI_CONFIG_BASE+2*k+1)))),
+            .i_tready(),
+            .o_tdata({m_axis_config_tlast[k],m_axis_config_tdata[32*k+31:32*k]}),
+            .o_tvalid(m_axis_config_tvalid[k]),
+            .o_tready(m_axis_config_tready[k]),
+            .occupied(), .space());
+      end
+   endgenerate
+   
+endmodule // axi_wrapper
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/Makefile b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/Makefile
new file mode 100644
index 000000000..acee50882
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/Makefile
@@ -0,0 +1,45 @@
+#
+# Copyright 2019 Ettus Research, A National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+#-------------------------------------------------
+# Top-of-Makefile
+#-------------------------------------------------
+# Define BASE_DIR to point to the "top" dir
+BASE_DIR = $(abspath ../../../../top)
+# Include viv_sim_preamble after defining BASE_DIR
+include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
+
+#-------------------------------------------------
+# Design Specific
+#-------------------------------------------------
+# Include makefiles and sources for the DUT and its dependencies
+include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs
+include $(BASE_DIR)/../lib/rfnoc/utils/Makefile.srcs
+include Makefile.srcs
+
+DESIGN_SRCS += $(abspath \
+$(RFNOC_CORE_SRCS) \
+$(RFNOC_UTIL_SRCS) \
+$(RFNOC_BLOCK_AXI_RAM_FIFO_SRCS) \
+)
+
+#-------------------------------------------------
+# Testbench Specific
+#-------------------------------------------------
+SIM_TOP = rfnoc_block_axi_ram_fifo_all_tb
+
+SIM_SRCS = \
+$(abspath sim_axi_ram.sv) \
+$(abspath rfnoc_block_axi_ram_fifo_tb.sv) \
+$(abspath rfnoc_block_axi_ram_fifo_all_tb.sv)
+
+#-------------------------------------------------
+# Bottom-of-Makefile
+#-------------------------------------------------
+# Include all simulator specific makefiles here
+# Each should define a unique target to simulate
+# e.g. xsim, vsim, etc and a common "clean" target
+include $(BASE_DIR)/../tools/make/viv_simulator.mak
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/Makefile.srcs b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/Makefile.srcs
new file mode 100644
index 000000000..9faa27321
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/Makefile.srcs
@@ -0,0 +1,18 @@
+#
+# Copyright 2019 Ettus Research, A National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+##################################################
+# RFNoC Utility Sources
+##################################################
+RFNOC_BLOCK_AXI_RAM_FIFO_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/, \
+noc_shell_axi_ram_fifo.v \
+axi_ram_fifo_regs.vh \
+axi_ram_fifo_regs.v \
+axi_ram_fifo_bist.v \
+axi_ram_fifo_bist_regs.v \
+axi_ram_fifo.v \
+rfnoc_block_axi_ram_fifo.v \
+))
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/axi_ram_fifo.v b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/axi_ram_fifo.v
new file mode 100644
index 000000000..5dd5f5ec4
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/axi_ram_fifo.v
@@ -0,0 +1,1228 @@
+//
+// Copyright 2019 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module:  axi_ram_fifo
+//
+// Description:
+//
+//   Implements a FIFO using a memory-mapped AXI interface as storage. This can 
+//   be connected to any memory-mapped AXI4 bus interface, such as DRAM, SRAM, 
+//   or AXI interconnect IP. The input and output interfaces to the FIFO are 
+//   AXI-Stream.
+//
+//   The logic is designed to buffer up multiple words so that writes and reads 
+//   can be implemented as efficient burst transactions on the AXI4 bus. This 
+//   core never crosses 4 KiB boundaries, per AXI4 rules (a burst must not 
+//   cross a 4 KiB boundary).
+//
+//   The FIFO must be at least 4 KiB in size so that the 4 KiB page boundary 
+//   protection also handles/prevents the FIFO wrap corner case.
+//
+// Parameters:
+//
+//   MEM_ADDR_W     : The width of the byte address to use for the AXI4 memory 
+//                    mapped interface.
+//
+//   MEM_DATA_W     : The width of the data port to use for the AXI4 memory 
+//                    mapped interface.
+//
+//   KEEP_W         : Width of tkeep on the AXI-Stream interface. Set to 1 if 
+//                    tkeep is not used.
+//
+//   FIFO_ADDR_BASE : Default base address to use for this FIFO.
+//
+//   FIFO_ADDR_MASK : Default byte address mask, which defines which memory 
+//                    address bits can be used for the FIFO. For example, an 64 
+//                    KiB memory region, or 2^16 bytes, would require the mask 
+//                    0xFFFF (16 ones). In other words, the mask should be the 
+//                    size of the memory region minus 1.
+//
+//   BURST_TIMEOUT  : Default number of memory clock cycles to wait for new 
+//                    data before performing a short, sub-optimal burst. One 
+//                    value per FIFO.
+//
+//   BIST           : If true, BIST logic will be included in the build.
+//
+//   CLK_RATE       : Frequency of clk in Hz
+//
+//   IN_FIFO_SIZE   : The input FIFO size will be 2**IN_FIFO_SIZE in depth.
+//
+//   OUT_FIFO_SIZE  : The output FIFO size will be 2**OUT_FIFO_SIZE in depth. 
+//                    This must be at least 9 so that there is enough space to 
+//                    accept a full AXI4 burst and then accept additional 
+//                    bursts while the FIFO is reading out.
+//
+
+module axi_ram_fifo #(
+  parameter                  MEM_ADDR_W     = 32,
+  parameter                  MEM_DATA_W     = 64,
+  parameter                  KEEP_W         = 1,
+  parameter [MEM_ADDR_W-1:0] FIFO_ADDR_BASE = 'h0,
+  parameter [MEM_ADDR_W-1:0] FIFO_ADDR_MASK = 'h00FFFFFF,
+  parameter                  BURST_TIMEOUT  = 256,
+  parameter                  BIST           = 1,
+  parameter                  CLK_RATE       = 200e6,
+  parameter                  IN_FIFO_SIZE   = 11,
+  parameter                  OUT_FIFO_SIZE  = 10
+) (
+  
+  input clk,
+  input rst,
+
+  //--------------------------------------------------------------------------
+  // CTRL Port
+  //--------------------------------------------------------------------------
+
+  input  wire        s_ctrlport_req_wr,
+  input  wire        s_ctrlport_req_rd,
+  input  wire [19:0] s_ctrlport_req_addr,
+  input  wire [31:0] s_ctrlport_req_data,
+  output wire        s_ctrlport_resp_ack,
+  output wire [31:0] s_ctrlport_resp_data,
+
+  //--------------------------------------------------------------------------
+  // AXI-Stream Interface
+  //--------------------------------------------------------------------------
+
+  // FIFO Input
+  input  wire [MEM_DATA_W-1:0] s_tdata,
+  input  wire [    KEEP_W-1:0] s_tkeep,
+  input  wire                  s_tlast,
+  input  wire                  s_tvalid,
+  output wire                  s_tready,
+
+  // FIFO Output
+  output wire [MEM_DATA_W-1:0] m_tdata,
+  output wire [    KEEP_W-1:0] m_tkeep,
+  output wire                  m_tlast,
+  output wire                  m_tvalid,
+  input  wire                  m_tready,
+
+  //--------------------------------------------------------------------------
+  // AXI4 Memory Interface
+  //--------------------------------------------------------------------------
+
+  // AXI Write Address Channel
+  output wire [             0:0] m_axi_awid,     // Write address ID. This signal is the identification tag for the write address signals.
+  output wire [  MEM_ADDR_W-1:0] m_axi_awaddr,   // Write address. The write address gives the address of the first transfer in a write burst.
+  output wire [             7:0] m_axi_awlen,    // Burst length. The burst length gives the exact number of transfers in a burst.
+  output wire [             2:0] m_axi_awsize,   // Burst size. This signal indicates the size of each transfer in the burst.
+  output wire [             1:0] m_axi_awburst,  // Burst type. The burst type and the size information, determine how the address is calculated.
+  output wire [             0:0] m_axi_awlock,   // Lock type. Provides additional information about the atomic characteristics of the transfer.
+  output wire [             3:0] m_axi_awcache,  // Memory type. This signal indicates how transactions are required to progress.
+  output wire [             2:0] m_axi_awprot,   // Protection type. This signal indicates the privilege and security level of the transaction.
+  output wire [             3:0] m_axi_awqos,    // Quality of Service, QoS. The QoS identifier sent for each write transaction.
+  output wire [             3:0] m_axi_awregion, // Region identifier. Permits a single physical interface on a slave to be re-used.
+  output wire [             0:0] m_axi_awuser,   // User signal. Optional User-defined signal in the write address channel.
+  output wire                    m_axi_awvalid,  // Write address valid. This signal indicates that the channel is signaling valid write addr.
+  input  wire                    m_axi_awready,  // Write address ready. This signal indicates that the slave is ready to accept an address.
+  //
+  // AXI Write Data Channel
+  output wire [  MEM_DATA_W-1:0] m_axi_wdata,    // Write data
+  output wire [MEM_DATA_W/8-1:0] m_axi_wstrb,    // Write strobes. This signal indicates which byte lanes hold valid data.
+  output wire                    m_axi_wlast,    // Write last. This signal indicates the last transfer in a write burst.
+  output wire [             0:0] m_axi_wuser,    // User signal. Optional User-defined signal in the write data channel.
+  output wire                    m_axi_wvalid,   // Write valid. This signal indicates that valid write data and strobes are available.
+  input  wire                    m_axi_wready,   // Write ready. This signal indicates that the slave can accept the write data.
+  //
+  // AXI Write Response Channel
+  input  wire [             0:0] m_axi_bid,      // Response ID tag. This signal is the ID tag of the write response.
+  input  wire [             1:0] m_axi_bresp,    // Write response. This signal indicates the status of the write transaction.
+  input  wire [             0:0] m_axi_buser,    // User signal. Optional User-defined signal in the write response channel.
+  input  wire                    m_axi_bvalid,   // Write response valid. This signal indicates that the channel is signaling a valid response.
+  output wire                    m_axi_bready,   // Response ready. This signal indicates that the master can accept a write response.
+  //
+  // AXI Read Address Channel
+  output wire [             0:0] m_axi_arid,     // Read address ID. This signal is the identification tag for the read address group of signals.
+  output wire [  MEM_ADDR_W-1:0] m_axi_araddr,   // Read address. The read address gives the address of the first transfer in a read burst.
+  output wire [             7:0] m_axi_arlen,    // Burst length. This signal indicates the exact number of transfers in a burst.
+  output wire [             2:0] m_axi_arsize,   // Burst size. This signal indicates the size of each transfer in the burst.
+  output wire [             1:0] m_axi_arburst,  // Burst type. The burst type and the size information determine how the address for each transfer.
+  output wire [             0:0] m_axi_arlock,   // Lock type. This signal provides additional information about the atomic characteristics.
+  output wire [             3:0] m_axi_arcache,  // Memory type. This signal indicates how transactions are required to progress.
+  output wire [             2:0] m_axi_arprot,   // Protection type. This signal indicates the privilege and security level of the transaction.
+  output wire [             3:0] m_axi_arqos,    // Quality of Service, QoS. QoS identifier sent for each read transaction.
+  output wire [             3:0] m_axi_arregion, // Region identifier. Permits a single physical interface on a slave to be re-used.
+  output wire [             0:0] m_axi_aruser,   // User signal. Optional User-defined signal in the read address channel.
+  output wire                    m_axi_arvalid,  // Read address valid. This signal indicates that the channel is signaling valid read addr.
+  input  wire                    m_axi_arready,  // Read address ready. This signal indicates that the slave is ready to accept an address.
+  //
+  // AXI Read Data Channel
+  input  wire [             0:0] m_axi_rid,      // Read ID tag. This signal is the identification tag for the read data group of signals.
+  input  wire [  MEM_DATA_W-1:0] m_axi_rdata,    // Read data.
+  input  wire [             1:0] m_axi_rresp,    // Read response. This signal indicates the status of the read transfer.
+  input  wire                    m_axi_rlast,    // Read last. This signal indicates the last transfer in a read burst.
+  input  wire [             0:0] m_axi_ruser,    // User signal. Optional User-defined signal in the read data channel.
+  input  wire                    m_axi_rvalid,   // Read valid. This signal indicates that the channel is signaling the required read data.
+  output wire                    m_axi_rready    // Read ready. This signal indicates that the master can accept the read data and response.
+);
+
+  `include "axi_ram_fifo_regs.vh"
+
+
+  //---------------------------------------------------------------------------
+  // Parameter Checking
+  //---------------------------------------------------------------------------
+
+  // The input FIFO size must be at least 9 so that there is enough space to 
+  // hold an entire burst and be able to accept new data while that burst is 
+  // waiting to be ready out.
+  if (IN_FIFO_SIZE < 9) begin
+    IN_FIFO_SIZE_must_be_at_least_9();
+  end
+
+  // The output FIFO size must be at least 9 so that there is enough space to 
+  // accept a full AXI4 burst (255 words) and then accept additional bursts 
+  // while the FIFO is waiting to be read out.
+  if (OUT_FIFO_SIZE < 9) begin
+    OUT_FIFO_SIZE_must_be_at_least_9();
+  end
+
+  // The memory must be at least as big as the default FIFO mask
+  if (2.0**MEM_ADDR_W < FIFO_ADDR_MASK+1) begin
+    MEM_ADDR_W_must_be_larger_than_size_indicated_by_FIFO_ADDR_MASK();
+  end
+
+  // The FIFO memory must be large enough for a full AXI4 burst + 64 words 
+  // that's allocated to allow for read/write reordering.
+  // TODO: Is the 64-word extra needed? Why 64?
+  //
+  // Min size allowed for memory region in bytes
+  localparam FIFO_MIN_RAM_SIZE  = (256+64) * (MEM_DATA_W/8); 
+  //
+  // Equivalent mask
+  localparam FIFO_ADDR_MASK_MIN = 2**($clog2(FIFO_MIN_RAM_SIZE))-1;
+  //
+  // Check the parameter
+  if (FIFO_ADDR_MASK < FIFO_ADDR_MASK_MIN) begin
+    FIFO_ADDR_MASK_must_be_at_least_256_plus_64_words();
+  end
+
+  // The 4 KiB page-crossing detection logic assumes that the memory is more 
+  // than 4 kiB in size. This could be fixed in the code, but 8 KiB is already 
+  // pretty small for an external memory.
+  if (2.0**MEM_ADDR_W < 8192) begin
+    MEM_ADDR_W_must_be_at_least_8_KiB();
+  end
+
+  // Make sure the default burst timeout is not too big for the register
+  if ($clog2(BURST_TIMEOUT+1) > REG_TIMEOUT_W) begin
+    BURST_TIMEOUT_must_not_exceed_the_range_of_REG_TIMEOUT_W();
+  end
+
+
+  //---------------------------------------------------------------------------
+  // Local Parameters
+  //---------------------------------------------------------------------------
+
+  // Width of the timeout counter
+  localparam TIMEOUT_W = REG_TIMEOUT_W;
+
+  // Address widths. Each memory byte address can be broken up into the word 
+  // address portion (the upper bits) and the byte address portion (lower 
+  // bits). Although the memory is byte addressable, we only read/write whole 
+  // words.
+  localparam BYTE_ADDR_W = $clog2(MEM_DATA_W/8);
+  localparam WORD_ADDR_W = MEM_ADDR_W - BYTE_ADDR_W;
+
+
+  //---------------------------------------------------------------------------
+  // Functions
+  //---------------------------------------------------------------------------
+
+  function automatic integer min(input integer a, b);
+    min = a < b ? a : b;
+  endfunction
+
+
+  //---------------------------------------------------------------------------
+  // Signal Declarations
+  //---------------------------------------------------------------------------
+
+  // Track RAM FIFO state, in number of words
+  reg [WORD_ADDR_W:0] space;
+  reg [WORD_ADDR_W:0] occupied;
+  reg [WORD_ADDR_W:0] occupied_minus_one; // Maintain a -1 version to break critical timing paths
+
+  reg [31:0] out_pkt_count = 0;
+
+  //
+  // Input Side
+  //
+  reg  [MEM_DATA_W-1:0] s_tdata_fifo;
+  reg                   s_tvalid_fifo;
+  wire                  s_tready_fifo;
+
+  wire [MEM_DATA_W-1:0] m_tdata_fifo;
+  wire                  m_tvalid_fifo;
+  reg                   m_tready_fifo;
+
+  wire [MEM_DATA_W-1:0] s_tdata_i1;
+  wire [    KEEP_W-1:0] s_tkeep_i1;
+  wire                  s_tvalid_i1, s_tready_i1, s_tlast_i1;
+
+  wire [MEM_DATA_W-1:0] s_tdata_i2;
+  wire                  s_tvalid_i2, s_tready_i2;
+
+  wire [MEM_DATA_W-1:0] s_tdata_i3;
+  wire                  s_tvalid_i3;
+  reg                   s_tready_i3;
+
+  wire [MEM_DATA_W-1:0] s_tdata_input;
+  wire                  s_tvalid_input, s_tready_input;
+
+  wire [15:0] space_input, occupied_input;
+  reg  [15:0] space_input_reg;
+  reg         suppress_reads;
+
+  //
+  // Output Side
+  //
+  wire [MEM_DATA_W-1:0] m_tdata_output;
+  wire                  m_tvalid_output, m_tready_output;
+
+  reg [MEM_DATA_W-1:0] m_tdata_i0;
+  reg                  m_tvalid_i0;
+  wire                 m_tready_i0;
+  
+  wire [MEM_DATA_W-1:0] m_tdata_i1;
+  wire                  m_tvalid_i1, m_tready_i1;
+  
+  wire [MEM_DATA_W-1:0] m_tdata_i2;
+  wire                  m_tvalid_i2, m_tready_i2;
+  
+  wire [MEM_DATA_W-1:0] m_tdata_i3;
+  wire [    KEEP_W-1:0] m_tkeep_i3;
+  wire                  m_tvalid_i3, m_tready_i3, m_tlast_i3;
+
+  wire [15:0] space_output;
+
+
+  //---------------------------------------------------------------------------
+  // Registers
+  //---------------------------------------------------------------------------
+
+  wire [          15:0] set_suppress_threshold;
+  wire [ TIMEOUT_W-1:0] set_timeout;
+  wire                  set_clear = 1'b0;       // Clear no longer needed in RFNoC
+  wire [MEM_ADDR_W-1:0] set_fifo_addr_base;
+  wire [MEM_ADDR_W-1:0] set_fifo_addr_mask;
+
+  wire        s_ctrlport_resp_ack_regs;
+  wire [31:0] s_ctrlport_resp_data_regs;
+
+  axi_ram_fifo_regs #(
+    .MEM_ADDR_W         (MEM_ADDR_W),
+    .MEM_DATA_W         (MEM_DATA_W),
+    .FIFO_ADDR_BASE     (FIFO_ADDR_BASE),
+    .FIFO_ADDR_MASK     (FIFO_ADDR_MASK),
+    .FIFO_ADDR_MASK_MIN (FIFO_ADDR_MASK_MIN),
+    .BIST               (BIST),
+    .IN_FIFO_SIZE       (IN_FIFO_SIZE),
+    .WORD_ADDR_W        (WORD_ADDR_W),
+    .BURST_TIMEOUT      (BURST_TIMEOUT),
+    .TIMEOUT_W          (TIMEOUT_W)
+  ) axi_ram_fifo_regs_i (
+    .clk                    (clk),
+    .rst                    (rst),
+    .s_ctrlport_req_wr      (s_ctrlport_req_wr),
+    .s_ctrlport_req_rd      (s_ctrlport_req_rd),
+    .s_ctrlport_req_addr    (s_ctrlport_req_addr),
+    .s_ctrlport_req_data    (s_ctrlport_req_data),
+    .s_ctrlport_resp_ack    (s_ctrlport_resp_ack_regs),
+    .s_ctrlport_resp_data   (s_ctrlport_resp_data_regs),
+    .rb_out_pkt_count       (out_pkt_count),
+    .rb_occupied            (occupied),
+    .set_suppress_threshold (set_suppress_threshold),
+    .set_timeout            (set_timeout),
+    .set_fifo_addr_base     (set_fifo_addr_base),
+    .set_fifo_addr_mask     (set_fifo_addr_mask)
+  );
+
+  //synthesis translate_off
+  // Check the address mask at run-time
+  always @(set_fifo_addr_mask) begin
+    if (set_fifo_addr_mask < FIFO_ADDR_MASK_MIN) begin
+      $display("ERROR: set_fifo_addr_mask was set too small!");
+    end
+    if (2**$clog2(set_fifo_addr_mask)-1 != set_fifo_addr_mask) begin
+      $display("ERROR: set_fifo_addr_mask must be a power of 2, minus 1!");
+    end
+  end
+  //synthesis translate_on
+
+
+  //---------------------------------------------------------------------------
+  // BIST for production testing
+  //---------------------------------------------------------------------------
+
+  if (BIST) begin : gen_bist
+    wire                  s_ctrlport_resp_ack_bist;
+    wire [          31:0] s_ctrlport_resp_data_bist;
+    wire [MEM_DATA_W-1:0] m_tdata_bist;
+    wire                  m_tvalid_bist;
+    reg                   m_tready_bist;
+    reg  [MEM_DATA_W-1:0] s_tdata_bist;
+    reg                   s_tvalid_bist;
+    wire                  s_tready_bist;
+
+    wire bist_running;
+
+    axi_ram_fifo_bist #(
+      .DATA_W   (MEM_DATA_W),
+      .COUNT_W  (48),
+      .CLK_RATE (CLK_RATE),
+      .RAND     (1)
+    ) axi_ram_fifo_bist_i (
+      .clk                  (clk),
+      .rst                  (rst),
+      .s_ctrlport_req_wr    (s_ctrlport_req_wr),
+      .s_ctrlport_req_rd    (s_ctrlport_req_rd),
+      .s_ctrlport_req_addr  (s_ctrlport_req_addr),
+      .s_ctrlport_req_data  (s_ctrlport_req_data),
+      .s_ctrlport_resp_ack  (s_ctrlport_resp_ack_bist),
+      .s_ctrlport_resp_data (s_ctrlport_resp_data_bist),
+      .m_tdata              (m_tdata_bist),
+      .m_tvalid             (m_tvalid_bist),
+      .m_tready             (m_tready_bist),
+      .s_tdata              (s_tdata_bist),
+      .s_tvalid             (s_tvalid_bist),
+      .s_tready             (s_tready_bist),
+      .running              (bist_running)
+    );
+
+    // Use a multiplexer to decide where the data flows, using the BIST when 
+    // ever the BIST is running.
+    always @(*) begin
+      if (bist_running) begin
+        // Insert the BIST logic
+        s_tdata_fifo  = m_tdata_bist;
+        s_tvalid_fifo = m_tvalid_bist;
+        m_tready_bist = s_tready_fifo;
+        //
+        s_tdata_bist  = m_tdata_fifo;
+        s_tvalid_bist = m_tvalid_fifo;
+        m_tready_fifo = s_tready_bist;
+
+        // Disable output-logic
+        s_tready_i3 = 0;
+        m_tdata_i0  = m_tdata_fifo;
+        m_tvalid_i0 = 0;
+      end else begin
+        // Disable BIST
+        m_tready_bist = 0;
+        s_tdata_bist  = m_tdata_fifo;
+        s_tvalid_bist = 0;
+        
+        // Bypass BIST
+        s_tdata_fifo  = s_tdata_i3;
+        s_tvalid_fifo = s_tvalid_i3;
+        s_tready_i3   = s_tready_fifo;
+        //
+        m_tdata_i0    = m_tdata_fifo;
+        m_tvalid_i0   = m_tvalid_fifo;
+        m_tready_fifo = m_tready_i0;
+      end
+    end
+
+    // Combine register responses
+    ctrlport_resp_combine #(
+      .NUM_SLAVES (2)
+    ) ctrlport_resp_combine_i (
+      .ctrlport_clk           (clk),
+      .ctrlport_rst           (rst),
+      .m_ctrlport_resp_ack    ({s_ctrlport_resp_ack_bist, s_ctrlport_resp_ack_regs}),
+      .m_ctrlport_resp_status ({2{2'b00}}),
+      .m_ctrlport_resp_data   ({s_ctrlport_resp_data_bist, s_ctrlport_resp_data_regs}),
+      .s_ctrlport_resp_ack    (s_ctrlport_resp_ack),
+      .s_ctrlport_resp_status (),
+      .s_ctrlport_resp_data   (s_ctrlport_resp_data)
+    );
+
+  end else begin : gen_no_bist
+    assign s_ctrlport_resp_ack  = s_ctrlport_resp_ack_regs;
+    assign s_ctrlport_resp_data = s_ctrlport_resp_data_regs;
+    always @(*) begin
+      // Bypass the BIST logic
+      s_tdata_fifo  = s_tdata_i3;
+      s_tvalid_fifo = s_tvalid_i3;
+      s_tready_i3   = s_tready_fifo;
+      //
+      m_tdata_i0    = m_tdata_fifo;
+      m_tvalid_i0   = m_tvalid_fifo;
+      m_tready_fifo = m_tready_i0;
+      //
+    end
+  end
+
+
+  //---------------------------------------------------------------------------
+  // Input Handling and Buffer
+  //---------------------------------------------------------------------------
+  //
+  // This block embeds TLAST into the data stream using an escape code and 
+  // buffers up input data.
+  //
+  //---------------------------------------------------------------------------
+
+  // Insert flops to improve timing
+  axi_fifo_flop2 #(
+    .WIDTH (MEM_DATA_W+1+KEEP_W)
+  ) input_pipe_i0 (
+    .clk      (clk),
+    .reset    (rst),
+    .clear    (set_clear),
+    //
+    .i_tdata  ({s_tkeep, s_tlast, s_tdata}),
+    .i_tvalid (s_tvalid),
+    .i_tready (s_tready),
+    //
+    .o_tdata  ({s_tkeep_i1, s_tlast_i1, s_tdata_i1}),
+    .o_tvalid (s_tvalid_i1),
+    .o_tready (s_tready_i1),
+    //
+    .space    (),
+    .occupied ()
+  );
+
+  axi_embed_tlast_tkeep #(
+    .DATA_W (MEM_DATA_W),
+    .KEEP_W (KEEP_W)
+  ) axi_embed_tlast_tkeep_i (
+    .clk      (clk),
+    .rst      (rst | set_clear),
+    //
+    .i_tdata  (s_tdata_i1),
+    .i_tkeep  (s_tkeep_i1),
+    .i_tlast  (s_tlast_i1),
+    .i_tvalid (s_tvalid_i1),
+    .i_tready (s_tready_i1),
+    //
+    .o_tdata  (s_tdata_i2),
+    .o_tvalid (s_tvalid_i2),
+    .o_tready (s_tready_i2)
+  );
+
+  // Insert flops to improve timing
+  axi_fifo_flop2 #(
+    .WIDTH (MEM_DATA_W)
+  ) input_pipe_i1 (
+    .clk      (clk),
+    .reset    (rst),
+    .clear    (set_clear),
+    //
+    .i_tdata  (s_tdata_i2),
+    .i_tvalid (s_tvalid_i2),
+    .i_tready (s_tready_i2),
+    //
+    .o_tdata  (s_tdata_i3),
+    .o_tvalid (s_tvalid_i3),
+    .o_tready (s_tready_i3),
+    //
+    .space    (),
+    .occupied ()
+  );
+
+  axi_fifo #(
+    .WIDTH (MEM_DATA_W),
+    .SIZE  (IN_FIFO_SIZE)
+  ) input_fifo (
+    .clk      (clk),
+    .reset    (rst),
+    .clear    (set_clear),
+    //
+    .i_tdata  (s_tdata_fifo),
+    .i_tvalid (s_tvalid_fifo),
+    .i_tready (s_tready_fifo),
+    //
+    .o_tdata  (s_tdata_input),
+    .o_tvalid (s_tvalid_input),
+    .o_tready (s_tready_input),
+    //
+    .space    (space_input),
+    .occupied (occupied_input)
+  );
+
+
+  //---------------------------------------------------------------------------
+  // Input (Memory Write) Logic
+  //---------------------------------------------------------------------------
+  //
+  // The input state machine waits for enough entries in input FIFO to trigger 
+  // RAM write burst. A timeout can also trigger a burst so that smaller chunks
+  // of data are not left to rot in the input FIFO. Also, if enough data is 
+  // present in the input FIFO to complete a burst up to the edge of a 4 KiB 
+  // page then we do a burst up to the 4 KiB boundary.
+  //
+  //---------------------------------------------------------------------------
+
+  //
+  // Input side declarations
+  //
+  localparam [2:0] INPUT_IDLE = 0;
+  localparam [2:0] INPUT1 = 1;
+  localparam [2:0] INPUT2 = 2;
+  localparam [2:0] INPUT3 = 3;  
+  localparam [2:0] INPUT4 = 4;
+  localparam [2:0] INPUT5 = 5;
+  localparam [2:0] INPUT6 = 6;
+
+  wire write_ctrl_ready;
+
+  reg [           2:0] input_state;
+  reg                  input_timeout_triggered;
+  reg                  input_timeout_reset;
+  reg [ TIMEOUT_W-1:0] input_timeout_count;
+  reg [MEM_ADDR_W-1:0] write_addr;
+  reg                  write_ctrl_valid;
+  reg [           7:0] write_count             = 0;
+  reg [           8:0] write_count_plus_one    = 1; // Maintain a +1 version to break critical timing paths
+  reg                  update_write;
+
+  reg [WORD_ADDR_W-1:0] input_page_boundary;
+
+  //
+  // Input timeout counter. Timeout count only increments when there is some 
+  // data waiting to be written to the RAM.
+  //
+  always @(posedge clk) begin
+    if (rst | set_clear) begin
+      input_timeout_count     <= 0;
+      input_timeout_triggered <= 0;
+    end else if (input_timeout_reset) begin
+      input_timeout_count     <= 0;
+      input_timeout_triggered <= 0;
+    end else if (input_timeout_count == set_timeout) begin
+      input_timeout_triggered <= 1;
+    end else if (input_state == INPUT_IDLE) begin
+      input_timeout_count <= input_timeout_count + ((occupied_input != 0) ? 1 : 0);
+    end
+  end
+
+  //
+  // Input State Machine
+  //
+  always @(posedge clk)
+    if (rst | set_clear) begin
+      input_state          <= INPUT_IDLE;
+      write_addr           <= set_fifo_addr_base & ~set_fifo_addr_mask;
+      input_timeout_reset  <= 1'b0;
+      write_ctrl_valid     <= 1'b0;
+      write_count          <= 8'd0;
+      write_count_plus_one <= 9'd1;
+      update_write         <= 1'b0;
+    end else begin
+      case (input_state)
+      //
+      // INPUT_IDLE.
+      // To start an input transfer to DRAM need:
+      // 1) Space in the RAM
+      // and either
+      // 2) 256 entries in the input FIFO
+      // or
+      // 3) Timeout occurred while waiting for more data, which can only happen 
+      //    if there's at least one word in the input FIFO).
+      //
+      INPUT_IDLE: begin
+        write_ctrl_valid    <= 1'b0;
+        update_write        <= 1'b0;
+        input_timeout_reset <= 1'b0;
+        if (space[WORD_ADDR_W:8] != 'd0) begin    // (space > 255): 256 or more slots in the RAM
+          if (occupied_input[15:8] != 'd0) begin  // (occupied_input > 255): 256 or more words in input FIFO
+            input_state         <= INPUT1;
+            input_timeout_reset <= 1'b1;
+
+            // Calculate the number of entries remaining until next 4 KiB page 
+            // boundary is crossed, minus 1. The units of calculation are 
+            // words. The address is always word aligned.
+            input_page_boundary <= { write_addr[MEM_ADDR_W-1:12], {12-BYTE_ADDR_W{1'b1}} } - 
+                                   write_addr[MEM_ADDR_W-1 : BYTE_ADDR_W];
+          end else if (input_timeout_triggered) begin  // input FIFO timeout waiting for new data.
+            input_state         <= INPUT2;
+            input_timeout_reset <= 1'b1;
+            // Calculate the number of entries remaining until next 4 KiB page 
+            // boundary is crossed, minus 1. The units of calculation are 
+            // words. The address is always word-aligned.
+            input_page_boundary <= { write_addr[MEM_ADDR_W-1:12], {12-BYTE_ADDR_W{1'b1}} } - 
+                                   write_addr[MEM_ADDR_W-1 : BYTE_ADDR_W];  
+          end
+        end
+      end
+      //
+      // INPUT1.
+      // Caused by input FIFO reaching 256 entries.
+      // Request write burst of lesser of:
+      // 1) Entries until page boundary crossed
+      // 2) 256
+      //
+      INPUT1: begin
+        // Replicated write logic to break a read timing critical path for 
+        // write_count.
+        write_count          <= input_page_boundary[min(12, WORD_ADDR_W)-1:8] == 0 ? 
+                                input_page_boundary[7:0] :
+                                255;
+        write_count_plus_one <= input_page_boundary[min(12, WORD_ADDR_W)-1:8] == 0 ? 
+                                input_page_boundary[7:0] + 1 :
+                                256;
+        write_ctrl_valid     <= 1'b1;
+        if (write_ctrl_ready)
+          input_state <= INPUT4; // Preemptive ACK
+        else
+          input_state <= INPUT3; // Wait for ACK
+      end
+      //
+      // INPUT2.
+      // Caused by timeout of input FIFO (occupied_input must now be 256 or 
+      // less since it was 255 or less in the INPUT_IDLE state; otherwise we 
+      // would have gone to INPUT1). Request write burst of lesser of:
+      // 1) Entries until page boundary crossed
+      // 2) Entries in input FIFO
+      //
+      INPUT2: begin
+        // Replicated write logic to break a read timing critical path for 
+        // write_count.
+        write_count          <= input_page_boundary < occupied_input[8:0] - 1 ?
+                                input_page_boundary[7:0] : 
+                                occupied_input[8:0] - 1;  // Max result of 255
+        write_count_plus_one <= input_page_boundary < occupied_input[8:0] - 1 ? 
+                                input_page_boundary[7:0] + 1 :
+                                occupied_input[8:0];
+        write_ctrl_valid     <= 1'b1;
+        if (write_ctrl_ready)
+          input_state <= INPUT4; // Preemptive ACK
+        else
+          input_state <= INPUT3; // Wait for ACK
+      end
+      //
+      // INPUT3.
+      // Wait in this state for AXI4 DMA engine to accept transaction.
+      //
+      INPUT3: begin
+        if (write_ctrl_ready) begin
+          write_ctrl_valid <= 1'b0;
+          input_state      <= INPUT4; // ACK
+        end else begin
+          write_ctrl_valid <= 1'b1;
+          input_state      <= INPUT3; // Wait for ACK
+        end
+      end
+      //
+      // INPUT4.
+      // Wait here until write_ctrl_ready_deasserts. This is important as the 
+      // next time it asserts we know that a write response was received.
+      INPUT4: begin
+        write_ctrl_valid <= 1'b0;
+        if (!write_ctrl_ready)
+          input_state <= INPUT5; // Move on
+        else
+          input_state <= INPUT4; // Wait for deassert
+      end  
+      //
+      // INPUT5.
+      // Transaction has been accepted by AXI4 DMA engine. Now we wait for the 
+      // re-assertion of write_ctrl_ready which signals that the AXI4 DMA 
+      // engine has received a response for the whole write transaction and we 
+      // assume that this means it is committed to DRAM. We are now free to 
+      // update write_addr pointer and go back to idle state.
+      // 
+      INPUT5: begin
+        write_ctrl_valid <= 1'b0;
+        if (write_ctrl_ready) begin
+          write_addr <= ((write_addr + (write_count_plus_one << $clog2(MEM_DATA_W/8))) & set_fifo_addr_mask) | (write_addr & ~set_fifo_addr_mask);
+          input_state <= INPUT6;
+          update_write <= 1'b1;
+        end else begin
+          input_state <= INPUT5;
+        end
+      end
+      //
+      // INPUT6:
+      // Need to let space update before looking if there's more to do.
+      //
+      INPUT6: begin
+        input_state  <= INPUT_IDLE;
+        update_write <= 1'b0;
+      end
+
+      default: 
+        input_state <= INPUT_IDLE;
+    endcase // case(input_state)
+  end
+
+
+  //---------------------------------------------------------------------------
+  // Read Suppression Logic
+  //---------------------------------------------------------------------------
+  //
+  // Monitor occupied_input to deduce when DRAM FIFO is running short of 
+  // bandwidth and there is a danger of back-pressure passing upstream of the 
+  // DRAM FIFO. In this situation, we suppress read requests to the DRAM FIFO 
+  // so that more bandwidth is available to writes.
+  //
+  // However, not reading can actually cause the FIFO to fill up and stall, so 
+  // if the input is stalled, allow switching back to reads. This allows the 
+  // memory to fill up without causing deadlock.
+  //
+  //---------------------------------------------------------------------------
+
+  reg input_idle, input_idle_d1, input_stalled;
+
+  always @(posedge clk) begin
+    // We consider the input to be stalled when the input state machine is idle 
+    // for 2 or more clock cycles.
+    input_idle    <= (input_state == INPUT_IDLE);
+    input_idle_d1 <= input_idle;
+    input_stalled <= input_idle && input_idle_d1;
+
+    space_input_reg <= space_input;
+    if (space_input_reg < set_suppress_threshold && !input_stalled)
+      suppress_reads <= 1'b1;
+    else 
+      suppress_reads <= 1'b0;
+  end
+
+
+  //---------------------------------------------------------------------------
+  // Output Handling and Buffer
+  //---------------------------------------------------------------------------
+  //
+  // This block buffers output data and extracts the TLAS signal that was 
+  // embedded into the data stream. 
+  //
+  //---------------------------------------------------------------------------
+
+  // Large FIFO to buffer data read from DRAM. This FIFO must be large enough 
+  // to accept a full burst read.
+  axi_fifo #(
+    .WIDTH (MEM_DATA_W),
+    .SIZE  (OUT_FIFO_SIZE)
+  ) output_fifo (
+    .clk      (clk),
+    .reset    (rst),
+    .clear    (set_clear),
+    //
+    .i_tdata  (m_tdata_output),
+    .i_tvalid (m_tvalid_output),
+    .i_tready (m_tready_output),
+    //
+    .o_tdata  (m_tdata_fifo),
+    .o_tvalid (m_tvalid_fifo),
+    .o_tready (m_tready_fifo),
+    //
+    .space    (space_output),
+    .occupied ()
+  );
+
+  // Place flops right after FIFO to improve timing
+  axi_fifo_flop2 #(
+    .WIDTH (MEM_DATA_W)
+  ) output_pipe_i0 (
+    .clk      (clk),
+    .reset    (rst),
+    .clear    (set_clear),
+    //
+    .i_tdata  (m_tdata_i0),
+    .i_tvalid (m_tvalid_i0),
+    .i_tready (m_tready_i0),
+    //
+    .o_tdata  (m_tdata_i1),
+    .o_tvalid (m_tvalid_i1),
+    .o_tready (m_tready_i1),
+    //
+    .space    (),
+    .occupied ()
+  );
+
+  // Pipeline flop before TLAST extraction logic
+  axi_fifo_flop2 #(
+    .WIDTH (MEM_DATA_W)
+  ) output_pipe_i1 (
+    .clk      (clk),
+    .reset    (rst),
+    .clear    (set_clear),
+    //
+    .i_tdata  (m_tdata_i1),
+    .i_tvalid (m_tvalid_i1),
+    .i_tready (m_tready_i1),
+    //
+    .o_tdata  (m_tdata_i2),
+    .o_tvalid (m_tvalid_i2),
+    .o_tready (m_tready_i2),
+    //
+    .space    (),
+    .occupied ()
+  );
+
+  axi_extract_tlast_tkeep #(
+    .DATA_W (MEM_DATA_W),
+    .KEEP_W (KEEP_W)
+  ) axi_extract_tlast_tkeep_i (
+    .clk      (clk),
+    .rst      (rst | set_clear),
+    //
+    .i_tdata  (m_tdata_i2),
+    .i_tvalid (m_tvalid_i2),
+    .i_tready (m_tready_i2),
+    //
+    .o_tdata  (m_tdata_i3),
+    .o_tkeep  (m_tkeep_i3),
+    .o_tlast  (m_tlast_i3),
+    .o_tvalid (m_tvalid_i3),
+    .o_tready (m_tready_i3)
+  );
+
+  // Pipeline flop after TLAST extraction logic
+  axi_fifo_flop2 #(
+    .WIDTH (MEM_DATA_W+1+KEEP_W)
+  ) output_pipe_i3 (
+    .clk      (clk),
+    .reset    (rst),
+    .clear    (set_clear),
+    //
+    .i_tdata  ({m_tkeep_i3, m_tlast_i3, m_tdata_i3}),
+    .i_tvalid (m_tvalid_i3),
+    .i_tready (m_tready_i3),
+    //
+    .o_tdata  ({m_tkeep, m_tlast, m_tdata}),
+    .o_tvalid (m_tvalid),
+    .o_tready (m_tready),
+    //
+    .space    (),
+    .occupied ()
+  );
+
+
+  //-------------------------------------------------------------------------
+  // Output (Memory Read) Logic
+  //-------------------------------------------------------------------------
+  //
+  // The output state machine Wait for enough entries in RAM to trigger read 
+  // burst. A timeout can also trigger a burst so that smaller chunks of data 
+  // are not left to rot in the RAM. Also, if enough data is present in the RAM 
+  // to complete a burst up to the edge of a 4 KiB page boundary then we do a 
+  // burst up to the 4 KiB boundary.
+  //
+  //---------------------------------------------------------------------------
+  
+  //
+  // Output side declarations
+  //
+  localparam [2:0] OUTPUT_IDLE = 0;
+  localparam [2:0] OUTPUT1 = 1;
+  localparam [2:0] OUTPUT2 = 2;
+  localparam [2:0] OUTPUT3 = 3;  
+  localparam [2:0] OUTPUT4 = 4;
+  localparam [2:0] OUTPUT5 = 5;
+  localparam [2:0] OUTPUT6 = 6;
+
+  reg  [           2:0] output_state;
+  reg                   output_timeout_triggered;
+  reg                   output_timeout_reset;
+  reg  [ TIMEOUT_W-1:0] output_timeout_count;
+  reg  [MEM_ADDR_W-1:0] read_addr;
+  reg                   read_ctrl_valid;
+  wire                  read_ctrl_ready;
+  reg  [           7:0] read_count          = 0;
+  reg  [           8:0] read_count_plus_one = 1; // Maintain a +1 version to break critical timing paths
+  reg                   update_read;
+
+  reg [WORD_ADDR_W-1:0] output_page_boundary; // Cache in a register to break critical timing paths
+
+  //
+  // Output Packet Counter
+  //
+  always @(posedge clk) begin
+    if (rst) begin
+      out_pkt_count <= 0;
+    end else if (m_tlast & m_tvalid & m_tready) begin
+      out_pkt_count <= out_pkt_count + 1;
+    end
+  end
+
+  //
+  // Output timeout counter. Timeout count only increments when there is some 
+  // data waiting to be read from the RAM.
+  //
+  always @(posedge clk) begin
+    if (rst | set_clear) begin
+      output_timeout_count     <= 0;
+      output_timeout_triggered <= 0;
+    end else if (output_timeout_reset) begin
+      output_timeout_count     <= 0;
+      output_timeout_triggered <= 0;
+    end else if (output_timeout_count == set_timeout) begin
+      output_timeout_triggered <= 1;
+    end else if (output_state == OUTPUT_IDLE) begin
+      output_timeout_count <= output_timeout_count + ((occupied != 0) ? 1 : 0);
+    end
+  end
+
+  //
+  // Output State Machine
+  //
+  always @(posedge clk)
+    if (rst | set_clear) begin
+      output_state         <= OUTPUT_IDLE;
+      read_addr            <= set_fifo_addr_base & ~set_fifo_addr_mask;
+      output_timeout_reset <= 1'b0;
+      read_ctrl_valid      <= 1'b0;
+      read_count           <= 8'd0;
+      read_count_plus_one  <= 9'd1;
+      update_read          <= 1'b0;
+    end else begin
+      case (output_state)
+      //
+      // OUTPUT_IDLE.
+      // To start an output transfer from DRAM
+      // 1) Space in the output FIFO 
+      // and either
+      // 2) 256 entries in the RAM
+      // or
+      // 3) Timeout occurred while waiting for more data, which can only happen 
+      //    if there's at least one word in the RAM.
+      //
+      OUTPUT_IDLE: begin
+        read_ctrl_valid      <= 1'b0;
+        update_read          <= 1'b0;
+        output_timeout_reset <= 1'b0;
+        if (space_output[15:8] != 'd0 && !suppress_reads) begin // (space_output > 255): 256 or more words in the output FIFO
+          if (occupied[WORD_ADDR_W:8] != 'd0) begin             // (occupied > 255): 256 or more words in RAM
+            output_state         <= OUTPUT1;
+            output_timeout_reset <= 1'b1;
+
+            // Calculate the number of entries remaining until next 4 KiB page 
+            // boundary is crossed, minus 1. The units of calculation are 
+            // words. The address is always word-aligned.
+            output_page_boundary <= { read_addr[MEM_ADDR_W-1:12], {12-BYTE_ADDR_W{1'b1}} } - 
+                                    read_addr[MEM_ADDR_W-1 : BYTE_ADDR_W];
+          end else if (output_timeout_triggered) begin   // output FIFO timeout waiting for new data.
+            output_state         <= OUTPUT2;
+            output_timeout_reset <= 1'b1;
+            // Calculate the number of entries remaining until next 4 KiB page 
+            // boundary is crossed, minus 1. The units of calculation are 
+            // words. The address is always word-aligned.
+            output_page_boundary <= { read_addr[MEM_ADDR_W-1:12], {12-BYTE_ADDR_W{1'b1}} } - 
+                                    read_addr[MEM_ADDR_W-1 : BYTE_ADDR_W];
+          end
+        end
+      end
+      //
+      // OUTPUT1.
+      // Caused by RAM FIFO reaching 256 entries.
+      // Request read burst of lesser of lesser of:
+      // 1) Entries until page boundary crossed
+      // 2) 256
+      //
+      OUTPUT1: begin
+        // Replicated write logic to break a read timing critical path for read_count
+        read_count          <= output_page_boundary[min(12, WORD_ADDR_W)-1:8] == 0 ? 
+                               output_page_boundary[7:0] : 
+                               255;
+        read_count_plus_one <= output_page_boundary[min(12, WORD_ADDR_W)-1:8] == 0 ?
+                               output_page_boundary[7:0] + 1 :
+                               256;
+        read_ctrl_valid     <= 1'b1;
+        if (read_ctrl_ready)
+          output_state <= OUTPUT4; // Preemptive ACK
+        else
+          output_state <= OUTPUT3; // Wait for ACK
+      end
+      //
+      // OUTPUT2.
+      // Caused by timeout of main FIFO
+      // Request read burst of lesser of:
+      // 1) Entries until page boundary crossed
+      // 2) Entries in main FIFO
+      //
+      OUTPUT2: begin
+        // Replicated write logic to break a read timing critical path for read_count
+        read_count          <= output_page_boundary < occupied_minus_one ? 
+                               output_page_boundary[7:0] :
+                               occupied_minus_one[7:0];
+        read_count_plus_one <= output_page_boundary < occupied_minus_one ?
+                               output_page_boundary[7:0] + 1 :
+                               occupied[7:0];
+        read_ctrl_valid     <= 1'b1;
+        if (read_ctrl_ready)
+          output_state <= OUTPUT4; // Preemptive ACK
+        else
+          output_state <= OUTPUT3; // Wait for ACK
+      end
+      //
+      // OUTPUT3.
+      // Wait in this state for AXI4 DMA engine to accept transaction.
+      //
+      OUTPUT3: begin
+        if (read_ctrl_ready) begin
+          read_ctrl_valid <= 1'b0;
+          output_state    <= OUTPUT4; // ACK
+        end else begin
+          read_ctrl_valid <= 1'b1;
+          output_state    <= OUTPUT3; // Wait for ACK
+        end
+      end
+      //
+      // OUTPUT4.
+      // Wait here until read_ctrl_ready_deasserts. This is important as the 
+      // next time it asserts we know that a read response was received.
+      OUTPUT4: begin
+        read_ctrl_valid <= 1'b0;
+        if (!read_ctrl_ready)
+          output_state <= OUTPUT5; // Move on
+        else
+          output_state <= OUTPUT4; // Wait for deassert
+      end  
+      //
+      // OUTPUT5.
+      // Transaction has been accepted by AXI4 DMA engine. Now we wait for the 
+      // re-assertion of read_ctrl_ready which signals that the AXI4 DMA engine 
+      // has received a last signal and good response for the whole read 
+      // transaction. We are now free to update read_addr pointer and go back 
+      // to idle state.
+      // 
+      OUTPUT5: begin
+        read_ctrl_valid <= 1'b0;
+        if (read_ctrl_ready) begin
+          read_addr <= ((read_addr + (read_count_plus_one << $clog2(MEM_DATA_W/8))) & set_fifo_addr_mask) | (read_addr & ~set_fifo_addr_mask);
+          output_state <= OUTPUT6;
+          update_read <= 1'b1;
+        end else begin
+          output_state <= OUTPUT5;
+        end
+      end
+      //
+      // OUTPUT6.
+      // Need to get occupied value updated before checking if there's more to do.
+      //
+      OUTPUT6: begin
+        update_read  <= 1'b0;
+        output_state <= OUTPUT_IDLE;
+      end
+
+      default: 
+        output_state <= OUTPUT_IDLE;
+    endcase // case(output_state)
+  end
+
+
+  //---------------------------------------------------------------------------
+  // Shared Read/Write Logic
+  //---------------------------------------------------------------------------
+
+  //
+  // Count number of words stored in the RAM FIFO.
+  //
+  always @(posedge clk) begin
+    if (rst | set_clear) begin
+      occupied           <=  0;
+      occupied_minus_one <= -1;
+    end else begin
+      occupied           <= occupied           + (update_write ? write_count_plus_one : 0) - (update_read ? read_count_plus_one : 0);
+      occupied_minus_one <= occupied_minus_one + (update_write ? write_count_plus_one : 0) - (update_read ? read_count_plus_one : 0);
+    end
+  end
+
+  //
+  // Count amount of space in the RAM FIFO, in words. 
+  //
+  always @(posedge clk) begin
+    if (rst | set_clear) begin
+      // Set to the FIFO size minus 64 words to make allowance for read/write 
+      // reordering in DRAM controller.
+      // TODO: Is the 64-word extra needed? Why 64?
+      space <= set_fifo_addr_mask[MEM_ADDR_W-1 -: WORD_ADDR_W] & ~('d63);
+    end else begin
+      space <= space - (update_write ? write_count_plus_one : 0) + (update_read ? read_count_plus_one : 0);
+    end
+  end
+  
+
+  //---------------------------------------------------------------------------
+  // AXI4 DMA Master
+  //---------------------------------------------------------------------------
+
+  axi_dma_master #(
+     .AWIDTH (MEM_ADDR_W),
+     .DWIDTH (MEM_DATA_W)
+  ) axi_dma_master_i (
+     .aclk             (clk),
+     .areset           (rst | set_clear),
+     // Write Address
+     .m_axi_awid       (m_axi_awid),
+     .m_axi_awaddr     (m_axi_awaddr),
+     .m_axi_awlen      (m_axi_awlen),
+     .m_axi_awsize     (m_axi_awsize),
+     .m_axi_awburst    (m_axi_awburst),
+     .m_axi_awvalid    (m_axi_awvalid),
+     .m_axi_awready    (m_axi_awready),
+     .m_axi_awlock     (m_axi_awlock),
+     .m_axi_awcache    (m_axi_awcache),
+     .m_axi_awprot     (m_axi_awprot),
+     .m_axi_awqos      (m_axi_awqos),
+     .m_axi_awregion   (m_axi_awregion),
+     .m_axi_awuser     (m_axi_awuser),
+     // Write Data
+     .m_axi_wdata      (m_axi_wdata),
+     .m_axi_wstrb      (m_axi_wstrb),
+     .m_axi_wlast      (m_axi_wlast),
+     .m_axi_wvalid     (m_axi_wvalid),
+     .m_axi_wready     (m_axi_wready),
+     .m_axi_wuser      (m_axi_wuser),
+     // Write Response
+     .m_axi_bid        (m_axi_bid),
+     .m_axi_bresp      (m_axi_bresp),
+     .m_axi_bvalid     (m_axi_bvalid),
+     .m_axi_bready     (m_axi_bready),
+     .m_axi_buser      (m_axi_buser),
+     // Read Address
+     .m_axi_arid       (m_axi_arid),
+     .m_axi_araddr     (m_axi_araddr),
+     .m_axi_arlen      (m_axi_arlen),
+     .m_axi_arsize     (m_axi_arsize),
+     .m_axi_arburst    (m_axi_arburst),
+     .m_axi_arvalid    (m_axi_arvalid),
+     .m_axi_arready    (m_axi_arready),
+     .m_axi_arlock     (m_axi_arlock),
+     .m_axi_arcache    (m_axi_arcache),
+     .m_axi_arprot     (m_axi_arprot),
+     .m_axi_arqos      (m_axi_arqos),
+     .m_axi_arregion   (m_axi_arregion),
+     .m_axi_aruser     (m_axi_aruser),
+     // Read Data
+     .m_axi_rid        (m_axi_rid),
+     .m_axi_rdata      (m_axi_rdata),
+     .m_axi_rresp      (m_axi_rresp),
+     .m_axi_rlast      (m_axi_rlast),
+     .m_axi_rvalid     (m_axi_rvalid),
+     .m_axi_rready     (m_axi_rready),
+     .m_axi_ruser      (m_axi_ruser),
+     //
+     // DMA interface for Write transactions
+     //
+     .write_addr       (write_addr),       // Byte address for start of write transaction (should be 64-bit aligned)
+     .write_count      (write_count),      // Count of 64-bit words to write.
+     .write_ctrl_valid (write_ctrl_valid),
+     .write_ctrl_ready (write_ctrl_ready),
+     .write_data       (s_tdata_input),
+     .write_data_valid (s_tvalid_input),
+     .write_data_ready (s_tready_input),
+     //
+     // DMA interface for Read transactions
+     //
+     .read_addr        (read_addr),        // Byte address for start of read transaction (should be 64-bit aligned)
+     .read_count       (read_count),       // Count of 64-bit words to read.
+     .read_ctrl_valid  (read_ctrl_valid),
+     .read_ctrl_ready  (read_ctrl_ready),
+     .read_data        (m_tdata_output),
+     .read_data_valid  (m_tvalid_output),
+     .read_data_ready  (m_tready_output),
+     //
+     // Debug
+     //
+     .debug            ()
+  );
+
+endmodule
+
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/axi_ram_fifo_bist.v b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/axi_ram_fifo_bist.v
new file mode 100644
index 000000000..2dd3f99d3
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/axi_ram_fifo_bist.v
@@ -0,0 +1,294 @@
+//
+// Copyright 2019 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: axi_ram_fifo_bist
+//
+// Description:
+//
+//   Implements a built-in self test for the RAM FIFO. It can generate random
+//   or sequential data that it outputs as quickly as possible. The output of
+//   the RAM is verified to make sure that it matches what was input to the RAM.
+//
+// Parameters:
+//
+//   DATA_W   : The width of the data port to use for the AXI4-Stream interface
+//
+//   COUNT_W  : Width of internal counters. This must be wide enough so that
+//              word, cycle, and and error counters don't overflow during a
+//              test.
+//
+//   CLK_RATE : The frequency of clk in Hz
+//
+//   RAND     : Set to 1 for random data, 0 for sequential data.
+//
+
+module axi_ram_fifo_bist #(
+  parameter DATA_W   = 64,
+  parameter COUNT_W  = 48,
+  parameter CLK_RATE = 200e6,
+  parameter RAND     = 1
+) (
+  input clk,
+  input rst,
+
+  //--------------------------------------------------------------------------
+  // CTRL Port
+  //--------------------------------------------------------------------------
+
+  input  wire        s_ctrlport_req_wr,
+  input  wire        s_ctrlport_req_rd,
+  input  wire [19:0] s_ctrlport_req_addr,
+  input  wire [31:0] s_ctrlport_req_data,
+  output wire        s_ctrlport_resp_ack,
+  output wire [31:0] s_ctrlport_resp_data,
+
+  //--------------------------------------------------------------------------
+  // AXI-Stream Interface
+  //--------------------------------------------------------------------------
+
+  // Output to RAM FIFO
+  output wire [DATA_W-1:0] m_tdata,
+  output reg               m_tvalid,
+  input  wire              m_tready,
+
+  // Input from RAM FIFO
+  input  wire [DATA_W-1:0] s_tdata,
+  input  wire              s_tvalid,
+  output wire              s_tready,
+
+  //---------------------------------------------------------------------------
+  // Status
+  //---------------------------------------------------------------------------
+
+  output reg running
+
+);
+
+  //---------------------------------------------------------------------------
+  // Local Parameters
+  //---------------------------------------------------------------------------
+
+  // Internal word size to use for data generation. The output word will be a
+  // multiple of this size.
+  localparam WORD_W = 32;
+
+  // Random number seed (must not be 0)
+  localparam [WORD_W-1:0] SEED = 'h012345678;
+
+  // Test data reset value
+  localparam [WORD_W-1:0] INIT = RAND ? SEED : 0;
+
+
+  //---------------------------------------------------------------------------
+  // Assertions
+  //---------------------------------------------------------------------------
+
+  if (DATA_W % WORD_W != 0) begin
+    DATA_W_must_be_a_multiple_of_WORD_W();
+  end
+
+  // LFSR only supports 8, 16, and 32 bits
+  if (WORD_W != 32 && WORD_W != 16 && WORD_W != 8) begin
+    WORD_W_not_supported();
+  end
+
+  //---------------------------------------------------------------------------
+  // Functions
+  //---------------------------------------------------------------------------
+
+  // Linear-feedback Shift Register for random number generation.
+  function [WORD_W-1:0] lfsr(input [WORD_W-1:0] din);
+    reg new_bit;
+    begin
+      case (WORD_W)
+        8  : new_bit = din[7]  ^ din[5]  ^ din[4]  ^ din[3];
+        16 : new_bit = din[15] ^ din[14] ^ din[12] ^ din[3];
+        32 : new_bit = din[31] ^ din[21] ^ din[1]  ^ din[0];
+      endcase
+      lfsr = { din[WORD_W-2:0], new_bit };
+    end
+  endfunction
+
+  function [WORD_W-1:0] next(input [WORD_W-1:0] din);
+    next = RAND ? lfsr(din) : din + 1;
+  endfunction
+
+
+  //---------------------------------------------------------------------------
+  // Signal Declarations
+  //---------------------------------------------------------------------------
+
+  reg [COUNT_W-1:0] tx_count;    // Number of words transmitted to FIFO
+  reg [COUNT_W-1:0] rx_count;    // Number of words received back from FIFO
+  reg [COUNT_W-1:0] error_count; // Number of words that show errors
+
+  reg [WORD_W-1:0]  tx_data = next(INIT); // Transmitted data word
+  reg [DATA_W-1:0]  rx_data = INIT;       // Received data words
+  reg [WORD_W-1:0]  exp_data;             // Expected data word
+  reg               rx_valid;             // Received word is value (strobe)
+
+  wire [COUNT_W-1:0] num_words;   // Number of words to test
+  reg  [COUNT_W-1:0] cycle_count; // Number of clock cycles test has been running for
+  wire               start;       // Start test
+  wire               stop;        // Stop test
+  wire               clear;       // Clear the counters
+  wire               continuous;  // Continuous test mode
+
+
+  //---------------------------------------------------------------------------
+  // Registers
+  //---------------------------------------------------------------------------
+
+  axi_ram_fifo_bist_regs #(
+    .DATA_W   (DATA_W),
+    .COUNT_W  (COUNT_W),
+    .CLK_RATE (CLK_RATE)
+  ) axi_ram_fifo_bist_regs_i (
+    .clk                  (clk),
+    .rst                  (rst),
+    .s_ctrlport_req_wr    (s_ctrlport_req_wr),
+    .s_ctrlport_req_rd    (s_ctrlport_req_rd),
+    .s_ctrlport_req_addr  (s_ctrlport_req_addr),
+    .s_ctrlport_req_data  (s_ctrlport_req_data),
+    .s_ctrlport_resp_ack  (s_ctrlport_resp_ack),
+    .s_ctrlport_resp_data (s_ctrlport_resp_data),
+    .tx_count             (tx_count),
+    .rx_count             (rx_count),
+    .error_count          (error_count),
+    .cycle_count          (cycle_count),
+    .num_words            (num_words),
+    .start                (start),
+    .stop                 (stop),
+    .clear                (clear),
+    .continuous           (continuous),
+    .running              (running)
+  );
+
+
+  //---------------------------------------------------------------------------
+  // State Machine
+  //---------------------------------------------------------------------------
+
+  localparam ST_IDLE      = 0;
+  localparam ST_ACTIVE    = 1;
+  localparam ST_WAIT_DONE = 2;
+
+  reg [        1:0] state;
+  reg [COUNT_W-1:0] num_words_m1;
+
+  always @(posedge clk) begin
+    if (rst) begin
+      state    <= ST_IDLE;
+      m_tvalid <= 0;
+      running  <= 0;
+    end else begin
+      m_tvalid <= 0;
+
+      case (state)
+        ST_IDLE : begin
+          num_words_m1 <= num_words-1;
+          if (start) begin
+            running <= 1;
+            state   <= ST_ACTIVE;
+          end
+        end
+
+        ST_ACTIVE : begin
+          if (stop || (tx_count == num_words_m1 && m_tvalid && m_tready && !continuous)) begin
+            m_tvalid <= 0;
+            state    <= ST_WAIT_DONE;
+          end else begin
+            m_tvalid <= 1;
+            running  <= 1;
+          end
+        end
+
+        ST_WAIT_DONE : begin
+          if (rx_count >= tx_count) begin
+            running <= 0;
+            state   <= ST_IDLE;
+          end
+        end
+      endcase
+    end
+  end
+
+
+  //---------------------------------------------------------------------------
+  // Data Generator
+  //---------------------------------------------------------------------------
+
+  reg count_en;
+
+  // Output data is the concatenation of our generated test word.
+  assign m_tdata = {(DATA_W/WORD_W){ tx_data }};
+
+  // We were born ready
+  assign s_tready = 1;
+
+  always @(posedge clk) begin
+    if (rst) begin
+      tx_data     <= next(INIT);
+      exp_data    <= INIT;
+      rx_valid    <= 0;
+      tx_count    <= 0;
+      rx_count    <= 0;
+      error_count <= 0;
+      cycle_count <= 0;
+      count_en    <= 0;
+    end else begin
+      //
+      // Output Data generation
+      //
+      if (m_tvalid && m_tready) begin
+        tx_data  <= next(tx_data);
+        tx_count <= tx_count + 1;
+      end
+
+      //
+      // Expected Data Generation
+      //
+      if (s_tvalid & s_tready) begin
+        rx_valid <= 1;
+        exp_data <= next(exp_data);
+        rx_count <= rx_count + 1;
+        rx_data  <= s_tdata;
+      end else begin
+        rx_valid <= 0;
+      end
+
+      //
+      // Data checker
+      //
+      if (rx_valid) begin
+        if (rx_data !== {(DATA_W/WORD_W){exp_data}}) begin
+          error_count <= error_count + 1;
+        end
+      end
+
+      //
+      // Cycle Counter
+      //
+      // Start counting after get the first word back so that we measure
+      // throughput and not latency.
+      if (state == ST_IDLE) count_en <= 0;
+      else if (s_tvalid) count_en <= 1;
+
+      if (count_en) cycle_count <= cycle_count + 1; 
+
+      //
+      // Clear counters upon request
+      //
+      if (clear) begin
+        tx_count    <= 0;
+        rx_count    <= 0;
+        error_count <= 0;
+        cycle_count <= 0;
+      end
+    end
+  end
+
+endmodule
+
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/axi_ram_fifo_bist_regs.v b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/axi_ram_fifo_bist_regs.v
new file mode 100644
index 000000000..c161c10f5
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/axi_ram_fifo_bist_regs.v
@@ -0,0 +1,206 @@
+//
+// Copyright 2019 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: axi_ram_fifo_bist_regs
+//
+// Description:
+//
+//   Implements the registers for the RAM FIFO BIST logic.
+//
+// Parameters:
+//
+//   DATA_W   : The width of the data port to use for the AXI4-Stream 
+//              interface.
+//
+//   COUNT_W  : Width of internal counters. This must be wide enough so that 
+//              word, cycle, and and error counters don't overflow during a 
+//              test.
+//
+//   CLK_RATE : The frequency of clk in Hz
+//
+
+module axi_ram_fifo_bist_regs #(
+  parameter DATA_W    = 64,
+  parameter COUNT_W   = 48,
+  parameter CLK_RATE  = 200e6
+) (
+  input clk,
+  input rst,
+
+  //--------------------------------------------------------------------------
+  // CTRL Port
+  //--------------------------------------------------------------------------
+
+  input  wire        s_ctrlport_req_wr,
+  input  wire        s_ctrlport_req_rd,
+  input  wire [19:0] s_ctrlport_req_addr,
+  input  wire [31:0] s_ctrlport_req_data,
+  output reg         s_ctrlport_resp_ack,
+  output reg  [31:0] s_ctrlport_resp_data,
+
+  //--------------------------------------------------------------------------
+  // Control and Status
+  //--------------------------------------------------------------------------
+
+  input wire [COUNT_W-1:0] tx_count,
+  input wire [COUNT_W-1:0] rx_count,
+  input wire [COUNT_W-1:0] error_count,
+  input wire [COUNT_W-1:0] cycle_count,
+
+  output wire [COUNT_W-1:0] num_words,
+  
+  output reg                start,
+  output reg                stop,
+  output reg                clear,
+  output reg                continuous,
+  input wire                running
+);
+
+  `include "axi_ram_fifo_regs.vh"
+
+  localparam BYTES_PER_WORD = DATA_W/8;
+  localparam WORD_SHIFT     = $clog2(BYTES_PER_WORD);
+
+  // Make sure DATA_W is a power of 2, or else the word/byte count conversion 
+  // logic won't be correct.
+  if (2**$clog2(DATA_W) != DATA_W) begin
+    DATA_W_must_be_a_power_of_2();
+  end
+
+  // The register logic currently assumes that COUNT_W is at least 33 bits.
+  if (COUNT_W <= 32) begin
+    COUNT_W_must_be_larger_than_32();
+  end
+
+  wire [19:0] word_addr;
+  wire [63:0] tx_byte_count;
+  wire [63:0] rx_byte_count;
+  reg  [63:0] num_bytes = 0;
+
+  reg [31:0] tx_byte_count_hi = 0;
+  reg [31:0] rx_byte_count_hi = 0;
+  reg [31:0] error_count_hi   = 0;
+  reg [31:0] cycle_count_hi   = 0;
+
+  // Only use the word address to simplify address decoding logic
+  assign word_addr = {s_ctrlport_req_addr[19:2], 2'b00 };
+
+  // Convert between words and bytes
+  assign tx_byte_count = tx_count  << WORD_SHIFT;
+  assign rx_byte_count = rx_count  << WORD_SHIFT;
+  assign num_words     = num_bytes >> WORD_SHIFT;
+
+
+  always @(posedge clk) begin
+    if (rst) begin
+      s_ctrlport_resp_ack <= 0;
+      start               <= 0;
+      stop                <= 0;
+      continuous          <= 0;
+      clear               <= 0;
+      num_bytes           <= 0;
+    end else begin
+      // Default values
+      s_ctrlport_resp_ack <= 0;
+      start <= 0;
+      stop  <= 0;
+      clear <= 0;
+
+      //-----------------------------------------------------------------------
+      // Read Logic
+      //-----------------------------------------------------------------------
+
+      if (s_ctrlport_req_rd) begin
+        case (word_addr)
+          REG_BIST_CTRL : begin
+            s_ctrlport_resp_data                       <= 0;
+            s_ctrlport_resp_data[REG_BIST_RUNNING_POS] <= running;
+            s_ctrlport_resp_data[REG_BIST_CONT_POS]    <= continuous;
+            s_ctrlport_resp_ack                        <= 1;
+          end
+          REG_BIST_CLK_RATE : begin
+            s_ctrlport_resp_data <= CLK_RATE;
+            s_ctrlport_resp_ack  <= 1;
+          end
+          REG_BIST_NUM_BYTES_LO : begin
+            s_ctrlport_resp_data <= num_bytes[31:0];
+            s_ctrlport_resp_ack  <= 1;
+          end
+          REG_BIST_NUM_BYTES_HI : begin
+            s_ctrlport_resp_data <= num_bytes[63:32];
+            s_ctrlport_resp_ack  <= 1;
+          end
+          REG_BIST_TX_BYTE_COUNT_LO : begin
+            s_ctrlport_resp_data <= tx_byte_count[31:0];
+            tx_byte_count_hi     <= tx_byte_count[63:32];
+            s_ctrlport_resp_ack  <= 1;
+          end
+          REG_BIST_TX_BYTE_COUNT_HI : begin
+            s_ctrlport_resp_data <= tx_byte_count_hi;
+            s_ctrlport_resp_ack  <= 1;            
+          end
+          REG_BIST_RX_BYTE_COUNT_LO : begin
+            s_ctrlport_resp_data           <= rx_byte_count[31:0];
+            rx_byte_count_hi[COUNT_W-33:0] <= rx_byte_count[COUNT_W-1:32];
+            s_ctrlport_resp_ack            <= 1;
+          end
+          REG_BIST_RX_BYTE_COUNT_HI : begin
+            s_ctrlport_resp_data <= rx_byte_count_hi;
+            s_ctrlport_resp_ack  <= 1;  
+          end
+          REG_BIST_ERROR_COUNT_LO : begin
+            s_ctrlport_resp_data         <= error_count[31:0];
+            error_count_hi[COUNT_W-33:0] <= error_count[COUNT_W-1:32];
+            s_ctrlport_resp_ack          <= 1;  
+          end
+          REG_BIST_ERROR_COUNT_HI : begin
+            s_ctrlport_resp_data <= 0;
+            s_ctrlport_resp_data <= error_count_hi;
+            s_ctrlport_resp_ack  <= 1;  
+          end
+          REG_BIST_CYCLE_COUNT_LO : begin
+            s_ctrlport_resp_data         <= cycle_count[31:0];
+            cycle_count_hi[COUNT_W-33:0] <= cycle_count[COUNT_W-1:32];
+            s_ctrlport_resp_ack          <= 1;  
+          end
+          REG_BIST_CYCLE_COUNT_HI : begin
+            s_ctrlport_resp_data <= 0;
+            s_ctrlport_resp_data <= cycle_count_hi;
+            s_ctrlport_resp_ack  <= 1;  
+          end
+        endcase
+      end
+
+
+      //-----------------------------------------------------------------------
+      // Write Logic
+      //-----------------------------------------------------------------------
+
+      if (s_ctrlport_req_wr) begin
+        case (word_addr)
+          REG_BIST_CTRL : begin
+            start      <= s_ctrlport_req_data[REG_BIST_START_POS];
+            stop       <= s_ctrlport_req_data[REG_BIST_STOP_POS];
+            clear      <= s_ctrlport_req_data[REG_BIST_CLEAR_POS];
+            continuous <= s_ctrlport_req_data[REG_BIST_CONT_POS];
+            s_ctrlport_resp_ack <= 1;
+          end
+          REG_BIST_NUM_BYTES_LO : begin
+            // Update only the word-count portion
+            num_bytes[31:WORD_SHIFT] <= s_ctrlport_req_data[31:WORD_SHIFT];
+            s_ctrlport_resp_ack <= 1;
+          end
+          REG_BIST_NUM_BYTES_HI : begin
+            num_bytes[COUNT_W-1:32] <= s_ctrlport_req_data[COUNT_W-33:0];
+            s_ctrlport_resp_ack <= 1;
+          end
+        endcase
+      end
+
+    end
+  end
+
+endmodule
+
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/axi_ram_fifo_regs.v b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/axi_ram_fifo_regs.v
new file mode 100644
index 000000000..4496d172d
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/axi_ram_fifo_regs.v
@@ -0,0 +1,207 @@
+//
+// Copyright 2019 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module:  axi_ram_fifo_regs
+//
+// Description:  
+//
+//   Implements the software-accessible registers for the axi_ram_fifo block.
+//
+
+
+module axi_ram_fifo_regs #(
+  parameter                  MEM_ADDR_W         = 32,
+  parameter                  MEM_DATA_W         = 64,
+  parameter [MEM_ADDR_W-1:0] FIFO_ADDR_BASE     = 'h0,
+  parameter [MEM_ADDR_W-1:0] FIFO_ADDR_MASK     = 'h0000FFFF,
+  parameter [MEM_ADDR_W-1:0] FIFO_ADDR_MASK_MIN = 'h00000FFF,
+  parameter                  BIST               = 1,
+  parameter                  IN_FIFO_SIZE       = 10,
+  parameter                  WORD_ADDR_W        = 29,
+  parameter                  BURST_TIMEOUT      = 128,
+  parameter                  TIMEOUT_W          = 12
+) (
+
+  input wire clk,
+  input wire rst,
+
+  //--------------------------------------------------------------------------
+  // CTRL Port
+  //--------------------------------------------------------------------------
+
+  input  wire        s_ctrlport_req_wr,
+  input  wire        s_ctrlport_req_rd,
+  input  wire [19:0] s_ctrlport_req_addr,
+  input  wire [31:0] s_ctrlport_req_data,
+  output reg         s_ctrlport_resp_ack,
+  output reg  [31:0] s_ctrlport_resp_data,
+
+  //---------------------------------------------------------------------------
+  // Register Inputs and Outputs
+  //---------------------------------------------------------------------------
+
+  // Read-back Registers
+  input wire [         31:0] rb_out_pkt_count,
+  input wire [WORD_ADDR_W:0] rb_occupied,
+
+  // Settings Registers
+  output reg [          15:0] set_suppress_threshold,
+  output reg [ TIMEOUT_W-1:0] set_timeout,
+  output reg [MEM_ADDR_W-1:0] set_fifo_addr_base = FIFO_ADDR_BASE,
+  output reg [MEM_ADDR_W-1:0] set_fifo_addr_mask = FIFO_ADDR_MASK
+);
+
+  `include "axi_ram_fifo_regs.vh"
+
+  function automatic integer min(input integer a, b);
+    min = a < b ? a : b;
+  endfunction
+
+  function automatic integer max(input integer a, b);
+    max = a > b ? a : b;
+  endfunction
+
+  wire [19:0] word_addr;
+  wire [63:0] reg_fifo_fullness;
+  reg  [31:0] reg_fifo_fullness_hi;
+
+  // Only use the word address to simplify address decoding logic
+  assign word_addr = {s_ctrlport_req_addr[19:2], 2'b00 };
+
+  // Convert the "occupied" word count to a 64-bit byte value
+  assign reg_fifo_fullness = {
+    {64-MEM_ADDR_W{1'b0}},            // Set unused upper bits to 0
+    rb_occupied,
+    {(MEM_ADDR_W-WORD_ADDR_W){1'b0}}  // Set byte offset bits to 0
+  };
+
+  always @(posedge clk) begin
+    if (rst) begin
+      s_ctrlport_resp_ack    <= 0;
+      set_suppress_threshold <= 0;
+      set_timeout            <= BURST_TIMEOUT;
+      set_fifo_addr_base     <= FIFO_ADDR_BASE;
+      set_fifo_addr_mask     <= FIFO_ADDR_MASK;
+    end else begin
+      s_ctrlport_resp_ack <= 0;
+
+      //-----------------------------------------------------------------------
+      // Write Logic
+      //-----------------------------------------------------------------------
+
+      if (s_ctrlport_req_wr) begin
+        case (word_addr)
+          REG_FIFO_READ_SUPPRESS : begin
+            set_suppress_threshold <= s_ctrlport_req_data[REG_FIFO_SUPPRESS_THRESH_POS +: REG_FIFO_SUPPRESS_THRESH_W];
+            s_ctrlport_resp_ack    <= 1;
+          end
+          REG_FIFO_TIMEOUT : begin
+            set_timeout[REG_TIMEOUT_W-1:0] <= s_ctrlport_req_data[REG_TIMEOUT_W-1:0];
+            s_ctrlport_resp_ack <= 1;
+          end
+          REG_FIFO_ADDR_BASE_LO : begin
+            set_fifo_addr_base[min(32, MEM_ADDR_W)-1:0] <= s_ctrlport_req_data[min(32, MEM_ADDR_W)-1:0];
+            s_ctrlport_resp_ack  <= 1;
+          end
+          REG_FIFO_ADDR_BASE_HI : begin
+            if (MEM_ADDR_W > 32) begin
+              set_fifo_addr_base[max(32, MEM_ADDR_W-1):32] <= s_ctrlport_req_data[max(0, MEM_ADDR_W-33):0];
+            end
+            s_ctrlport_resp_ack  <= 1;
+          end
+          REG_FIFO_ADDR_MASK_LO : begin
+            // Coerce the lower bits so we are guaranteed to meet the minimum mask size requirement.
+            set_fifo_addr_mask[min(32, MEM_ADDR_W)-1:0] <= 
+              s_ctrlport_req_data[min(32, MEM_ADDR_W)-1:0] | FIFO_ADDR_MASK_MIN;
+            s_ctrlport_resp_ack  <= 1;
+          end
+          REG_FIFO_ADDR_MASK_HI : begin
+            if (MEM_ADDR_W > 32) begin
+              set_fifo_addr_mask[max(32, MEM_ADDR_W-1):32] <= s_ctrlport_req_data[max(0, MEM_ADDR_W-33):0];
+            end
+            s_ctrlport_resp_ack  <= 1;
+          end
+        endcase
+      end
+      
+
+      //-----------------------------------------------------------------------
+      // Read Logic
+      //-----------------------------------------------------------------------
+
+      if (s_ctrlport_req_rd) begin
+        case (word_addr)
+          REG_FIFO_INFO : begin
+            s_ctrlport_resp_data <= 0;
+            s_ctrlport_resp_data[REG_FIFO_MAGIC_POS +: REG_FIFO_MAGIC_W] <= 16'hF1F0;
+            s_ctrlport_resp_data[REG_FIFO_BIST_PRSNT_POS] <= (BIST != 0);
+            s_ctrlport_resp_ack  <= 1;
+          end
+          REG_FIFO_READ_SUPPRESS : begin
+            s_ctrlport_resp_data <= 0;
+            s_ctrlport_resp_data[REG_FIFO_IN_FIFO_SIZE_POS +: REG_FIFO_IN_FIFO_SIZE_W] 
+              <= IN_FIFO_SIZE;
+            s_ctrlport_resp_data[REG_FIFO_SUPPRESS_THRESH_POS +: REG_FIFO_SUPPRESS_THRESH_W]
+              <= set_suppress_threshold;
+            s_ctrlport_resp_ack <= 1;
+          end
+          REG_FIFO_MEM_SIZE : begin
+            s_ctrlport_resp_data <= 0;
+            s_ctrlport_resp_data[REG_FIFO_DATA_SIZE_POS +: REG_FIFO_DATA_SIZE_W]
+              <= MEM_DATA_W;
+            s_ctrlport_resp_data[REG_FIFO_ADDR_SIZE_POS +: REG_FIFO_ADDR_SIZE_W]
+              <= MEM_ADDR_W;
+            s_ctrlport_resp_ack  <= 1;
+          end
+          REG_FIFO_TIMEOUT : begin
+            s_ctrlport_resp_data <= 0;
+            s_ctrlport_resp_data[REG_TIMEOUT_W-1:0] <= set_timeout[REG_TIMEOUT_W-1:0];
+            s_ctrlport_resp_ack  <= 1;
+          end
+          REG_FIFO_FULLNESS_LO : begin
+            s_ctrlport_resp_data <= reg_fifo_fullness[31:0];
+            reg_fifo_fullness_hi <= reg_fifo_fullness[63:32];
+            s_ctrlport_resp_ack  <= 1;
+          end
+          REG_FIFO_FULLNESS_HI : begin
+            s_ctrlport_resp_data <= reg_fifo_fullness_hi;
+            s_ctrlport_resp_ack  <= 1;
+          end
+          REG_FIFO_ADDR_BASE_LO : begin
+            s_ctrlport_resp_data <= 0;
+            s_ctrlport_resp_data[min(32, MEM_ADDR_W)-1:0] <= set_fifo_addr_base[min(32, MEM_ADDR_W)-1:0];
+            s_ctrlport_resp_ack  <= 1;
+          end
+          REG_FIFO_ADDR_BASE_HI : begin
+            s_ctrlport_resp_data <= 0;
+            if (MEM_ADDR_W > 32) begin
+              s_ctrlport_resp_data[max(0,MEM_ADDR_W-33):0] <= set_fifo_addr_base[max(32, MEM_ADDR_W-1):32];
+            end
+            s_ctrlport_resp_ack  <= 1;
+          end
+          REG_FIFO_ADDR_MASK_LO : begin
+            s_ctrlport_resp_data <= 0;
+            s_ctrlport_resp_data[min(32, MEM_ADDR_W)-1:0] <= set_fifo_addr_mask[min(32, MEM_ADDR_W)-1:0];
+            s_ctrlport_resp_ack  <= 1;
+          end
+          REG_FIFO_ADDR_MASK_HI : begin
+            s_ctrlport_resp_data <= 0;
+            if (MEM_ADDR_W > 32) begin
+              s_ctrlport_resp_data[max(0, MEM_ADDR_W-33):0] <= set_fifo_addr_mask[max(32, MEM_ADDR_W-1):32];
+            end
+            s_ctrlport_resp_ack  <= 1;
+          end
+          REG_FIFO_PACKET_CNT : begin
+            s_ctrlport_resp_data <= 0;
+            s_ctrlport_resp_data <= rb_out_pkt_count;
+            s_ctrlport_resp_ack  <= 1;
+          end
+        endcase
+      end
+
+    end
+  end
+  
+endmodule
\ No newline at end of file
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/axi_ram_fifo_regs.vh b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/axi_ram_fifo_regs.vh
new file mode 100644
index 000000000..ccb942552
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/axi_ram_fifo_regs.vh
@@ -0,0 +1,228 @@
+//
+// Copyright 2019 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module:  axi_ram_fifo_regs (Header)
+//
+// Description:  Header file for axi_ram_fifo_regs. All registers are 32-bit 
+//               words from software's perspective.
+//
+
+// Address space size, per FIFO. That is, each FIFO is separated in the CTRL 
+// Port address space by 2^FIFO_ADDR_W bytes.
+localparam RAM_FIFO_ADDR_W = 7;
+
+
+// REG_FIFO_INFO (R|W)
+//
+// Contains info/control bits for the FIFO.
+//
+// [31:16] : Returns the magic number 0xF1F0 (read-only)
+//     [0] : Indicates if BIST logic is present (read-only)
+//
+localparam REG_FIFO_INFO = 'h0;
+//
+localparam REG_FIFO_MAGIC_POS      = 16;
+localparam REG_FIFO_BIST_PRSNT_POS = 0;
+//
+localparam REG_FIFO_MAGIC_W = 16;
+
+
+// REG_FIFO_READ_SUPPRESS (R|W)
+//
+// Controls the read suppression threshold. RAM reads will be disabled whenever
+// the amount of free space in the input buffer (in units of RAM words) falls
+// below this threshold. This is intended to prevent input buffer overflows
+// caused by the RAM being too busy with reads. To disable the read suppression
+// feature, set the threshold to 0. In general, the threshold should be set to
+// a small value relative to the input FIFO buffer size (the IN_FIFO_SIZE
+// field) so that it is only enabled when the input FIFO buffer is close to
+// overflowing.
+//
+
+// [31:16] : Address width of input buffer. In other words, the input buffer is 
+//           2**REG_FIFO_IN_FIFO_SIZE RAM words deep. (read-only)
+// [15: 0] : Read suppression threshold, in RAM words (read/write)
+//
+localparam REG_FIFO_READ_SUPPRESS = 'h4;
+//
+localparam REG_FIFO_IN_FIFO_SIZE_POS    = 16;
+localparam REG_FIFO_SUPPRESS_THRESH_POS = 0;
+//
+localparam REG_FIFO_IN_FIFO_SIZE_W    = 16;
+localparam REG_FIFO_SUPPRESS_THRESH_W = 16;
+
+
+// REG_FIFO_MEM_SIZE (R)
+//
+// Returns information about the size of the attached memory. The address size 
+// allows software to determine what mask and base address values are valid.
+//
+// [31:16] : Returns the bit width of the RAM word size.
+// [15: 0] : Returns the bit width of the RAM byte address size. That is, the 
+//           addressable portion of the attached memory is 
+//           2**REG_FIFO_ADDR_SIZE bytes.
+//
+localparam REG_FIFO_MEM_SIZE = 'h8;
+//
+localparam REG_FIFO_DATA_SIZE_POS = 16;
+localparam REG_FIFO_ADDR_SIZE_POS = 0;
+//
+localparam REG_FIFO_DATA_SIZE_W = 16;
+localparam REG_FIFO_ADDR_SIZE_W = 16;
+
+
+// REG_FIFO_TIMEOUT (R/W)
+//
+// Programs the FIFO timeout, in memory interface clock cycles. For efficiency,
+// we want the memory to read and write full bursts. But we also don't want
+// smaller amounts of data to be stuck in the FIFO. This timeout determines how
+// long we wait for new data before we go ahead and perform a smaller
+// read/write. A longer timeout will make more efficient use of the memory, but
+// will increase latency. The default value is set by a module parameter.
+//
+// [31:12] : <Reserved>
+// [11: 0] : Timeout
+//
+localparam REG_FIFO_TIMEOUT = 'hC;
+//
+localparam REG_TIMEOUT_POS = 0;
+localparam REG_TIMEOUT_W   = 12;
+
+
+// REG_FIFO_FULLNESS (R)
+//
+// Returns the fullness of the FIFO in bytes. This is is a 64-bit register in 
+// which the least-significant 32-bit word must be read first.
+//
+localparam REG_FIFO_FULLNESS_LO = 'h10;
+localparam REG_FIFO_FULLNESS_HI = 'h14;
+
+
+// REG_FIFO_ADDR_BASE (R|W)
+//
+// Sets the base byte address to use for this FIFO. This should only be updated 
+// when the FIFO is idle. This should be set to a multiple of 
+// REG_FIFO_ADDR_MASK+1. Depending on the size of the memory connected, upper 
+// bits might be ignored. 
+//
+localparam REG_FIFO_ADDR_BASE_LO = 'h18;
+localparam REG_FIFO_ADDR_BASE_HI = 'h1C;
+
+
+// REG_FIFO_ADDR_MASK (R|W)
+//
+// The byte address mask that controls the portion of the memory address that 
+// is allocated to this FIFO. For example, set to 0xFFFF for a 64 KiB memory. 
+//
+// This should only be updated when the FIFO is idle. It must be equal to a 
+// power-of-2 minus 1. It should be no smaller than FIFO_ADDR_MASK_MIN, defined 
+// in axi_ram_fifo.v, otherwise it will be coerced up to that size. 
+//
+// This is is a 64-bit register in which the least-significant 32-bit word must 
+// be read/written first. Depending on the size of the memory connected, the 
+// upper bits might be ignored.
+//
+localparam REG_FIFO_ADDR_MASK_LO = 'h20;
+localparam REG_FIFO_ADDR_MASK_HI = 'h24;
+
+
+// REG_FIFO_PACKET_CNT (R)
+//
+// Returns the number of packets transferred out of the FIFO block.
+//
+localparam REG_FIFO_PACKET_CNT = 'h28;
+
+
+//-----------------------------------------------------------------------------
+// BIST Registers
+//-----------------------------------------------------------------------------
+//
+// Only read these registers if the BIST component is included.
+//
+//-----------------------------------------------------------------------------
+
+// REG_BIST_CTRL (R|W)
+//
+// Control register for the BIST component. 
+//
+// [4] : BIST is running. Changes to 1 after a test is started, then returns to 
+//       0 when BIST is complete.
+//
+// [3] : Continuous mode (run until stopped). When set to 1, test will continue 
+//       to run until Stop bit is set.
+//
+// [2] : Clear the BIST counters (i.e., the TX, RX, cycle, and error counters)
+//
+// [1] : Stop BIST  (strobe). Write a 1 to this bit to stop the test that is 
+//       currently running 
+//
+// [0] : Start BIST (strobe). Write a 1 to this bit to start a test using the 
+//       configured NUM_BYTES and continuous mode setting.
+//
+localparam REG_BIST_CTRL = 'h30;
+//
+localparam REG_BIST_RUNNING_POS = 4;
+localparam REG_BIST_CONT_POS    = 3;
+localparam REG_BIST_CLEAR_POS   = 2;  // Strobe
+localparam REG_BIST_STOP_POS    = 1;  // Strobe
+localparam REG_BIST_START_POS   = 0;  // Strobe
+
+
+// REG_BIST_CLOCK_RATE (R)
+//
+// Reports the clock rate of the BIST component in Hz. This can be used with 
+// REG_BIST_CYCLE_COUNT to calculate throughput.
+//
+localparam REG_BIST_CLK_RATE = 'h34;
+
+
+// REG_BIST_NUM_BYTES (R|W)
+//
+// Number of bytes to generate for the next BIST run. THis is not used if the 
+// REG_BIST_CONT_POS bit is set. This register should not be updated while the 
+// BIST is running.
+//
+localparam REG_BIST_NUM_BYTES_LO = 'h38;
+localparam REG_BIST_NUM_BYTES_HI = 'h3C;
+
+
+// REG_BIST_TX_BYTE_COUNT (R)
+//
+// Reports the number of bytes transmitted by the BIST component. This should 
+// always be read least-significant word first to ensure coherency. Once BIST 
+// is complete, the TX count will equal the RX count.
+//
+localparam REG_BIST_TX_BYTE_COUNT_LO = 'h40;
+localparam REG_BIST_TX_BYTE_COUNT_HI = 'h44;
+
+
+// REG_BIST_RX_BYTE_COUNT (R)
+//
+// Reports the number of bytes received by the BIST component. This should 
+// always be read least-significant word first to ensure coherency. Once BIST 
+// is complete, the TX count will equal the RX count.
+//
+localparam REG_BIST_RX_BYTE_COUNT_LO = 'h48;
+localparam REG_BIST_RX_BYTE_COUNT_HI = 'h4C;
+
+
+// REG_BIST_ERROR_COUNT (R)
+//
+// Reports the number of words in which the BIST component detected errors.
+// This should always be read least-significant word first to ensure coherency.
+//
+localparam REG_BIST_ERROR_COUNT_LO = 'h50;
+localparam REG_BIST_ERROR_COUNT_HI = 'h54;
+
+
+// REG_BIST_CYCLE_COUNT (R)
+//
+// Reports the number of clock cycles that have elapsed while the BIST was 
+// running. This can be used to calculate throughput. This should always be 
+// read least-significant word first to ensure coherency.
+//
+localparam REG_BIST_CYCLE_COUNT_LO = 'h58;
+localparam REG_BIST_CYCLE_COUNT_HI = 'h5C;
+
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/noc_shell_axi_ram_fifo.v b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/noc_shell_axi_ram_fifo.v
new file mode 100644
index 000000000..fc353595d
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/noc_shell_axi_ram_fifo.v
@@ -0,0 +1,319 @@
+//
+// Copyright 2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: noc_shell_axi_ram_fifo
+//
+// Description: A NoC Shell for the RFNoC AXI RAM FIFO. This NoC Shell 
+//              implements the control port interface but does nothing to the 
+//              data path other than moving it to the requested clock domain.
+//
+
+`define MAX(X,Y) ((X) > (Y) ? (X) : (Y))
+
+
+module noc_shell_axi_ram_fifo #(
+  parameter [31:0] NOC_ID           = 32'h0,
+  parameter [ 9:0] THIS_PORTID      = 10'd0,
+  parameter        CHDR_W           = 64,
+  parameter        DATA_W           = 64,
+  parameter [ 5:0] CTRL_FIFO_SIZE   = 0,
+  parameter [ 0:0] CTRLPORT_MST_EN  = 1,
+  parameter [ 0:0] CTRLPORT_SLV_EN  = 1,
+  parameter [ 5:0] NUM_DATA_I       = 1,
+  parameter [ 5:0] NUM_DATA_O       = 1,
+  parameter [ 5:0] MTU              = 10,
+  parameter        SYNC_DATA_CLOCKS = 0
+) (
+  //---------------------------------------------------------------------------
+  // Framework Interface
+  //---------------------------------------------------------------------------
+
+  // RFNoC Framework Clocks and Resets
+  input  wire                           rfnoc_chdr_clk,
+  output wire                           rfnoc_chdr_rst,
+  input  wire                           rfnoc_ctrl_clk,
+  output wire                           rfnoc_ctrl_rst,
+  // RFNoC Backend Interface
+  input  wire [                  511:0] rfnoc_core_config,
+  output wire [                  511:0] rfnoc_core_status,
+  // CHDR Input Ports (from framework)
+  input  wire [(CHDR_W*NUM_DATA_I)-1:0] s_rfnoc_chdr_tdata,
+  input  wire [         NUM_DATA_I-1:0] s_rfnoc_chdr_tlast,
+  input  wire [         NUM_DATA_I-1:0] s_rfnoc_chdr_tvalid,
+  output wire [         NUM_DATA_I-1:0] s_rfnoc_chdr_tready,
+  // CHDR Output Ports (to framework)
+  output wire [(CHDR_W*NUM_DATA_O)-1:0] m_rfnoc_chdr_tdata,
+  output wire [         NUM_DATA_O-1:0] m_rfnoc_chdr_tlast,
+  output wire [         NUM_DATA_O-1:0] m_rfnoc_chdr_tvalid,
+  input  wire [         NUM_DATA_O-1:0] m_rfnoc_chdr_tready,
+  // AXIS-Ctrl Input Port (from framework)
+  input  wire [                   31:0] s_rfnoc_ctrl_tdata,
+  input  wire                           s_rfnoc_ctrl_tlast,
+  input  wire                           s_rfnoc_ctrl_tvalid,
+  output wire                           s_rfnoc_ctrl_tready,
+  // AXIS-Ctrl Output Port (to framework)
+  output wire [                   31:0] m_rfnoc_ctrl_tdata,
+  output wire                           m_rfnoc_ctrl_tlast,
+  output wire                           m_rfnoc_ctrl_tvalid,
+  input  wire                           m_rfnoc_ctrl_tready,
+
+  //---------------------------------------------------------------------------
+  // Client Control Port Interface
+  //---------------------------------------------------------------------------
+
+  // Clock
+  input  wire        ctrlport_clk,
+  input  wire        ctrlport_rst,
+  // Master
+  output wire        m_ctrlport_req_wr,
+  output wire        m_ctrlport_req_rd,
+  output wire [19:0] m_ctrlport_req_addr,
+  output wire [31:0] m_ctrlport_req_data,
+  output wire [ 3:0] m_ctrlport_req_byte_en,
+  output wire        m_ctrlport_req_has_time,
+  output wire [63:0] m_ctrlport_req_time,
+  input  wire        m_ctrlport_resp_ack,
+  input  wire [ 1:0] m_ctrlport_resp_status,
+  input  wire [31:0] m_ctrlport_resp_data,
+  // Slave
+  input  wire        s_ctrlport_req_wr,
+  input  wire        s_ctrlport_req_rd,
+  input  wire [19:0] s_ctrlport_req_addr,
+  input  wire [ 9:0] s_ctrlport_req_portid,
+  input  wire [15:0] s_ctrlport_req_rem_epid,
+  input  wire [ 9:0] s_ctrlport_req_rem_portid,
+  input  wire [31:0] s_ctrlport_req_data,
+  input  wire [ 3:0] s_ctrlport_req_byte_en,
+  input  wire        s_ctrlport_req_has_time,
+  input  wire [63:0] s_ctrlport_req_time,
+  output wire        s_ctrlport_resp_ack,
+  output wire [ 1:0] s_ctrlport_resp_status,
+  output wire [31:0] s_ctrlport_resp_data,
+
+  //---------------------------------------------------------------------------
+  // Client Data Interface
+  //---------------------------------------------------------------------------
+
+  // Clock
+  input wire axis_data_clk,
+  input wire axis_data_rst,
+
+  // Output data stream (to user logic)
+  output wire [                (NUM_DATA_I*DATA_W)-1:0] m_axis_tdata,
+  output wire [(NUM_DATA_I*`MAX(DATA_W/CHDR_W, 1))-1:0] m_axis_tkeep,
+  output wire [                         NUM_DATA_I-1:0] m_axis_tlast,
+  output wire [                         NUM_DATA_I-1:0] m_axis_tvalid,
+  input  wire [                         NUM_DATA_I-1:0] m_axis_tready,
+
+  // Input data stream (from user logic)
+  input  wire [                (NUM_DATA_O*DATA_W)-1:0] s_axis_tdata,
+  input  wire [(NUM_DATA_O*`MAX(DATA_W/CHDR_W, 1))-1:0] s_axis_tkeep,
+  input  wire [                         NUM_DATA_O-1:0] s_axis_tlast,
+  input  wire [                         NUM_DATA_O-1:0] s_axis_tvalid,
+  output wire [                         NUM_DATA_O-1:0] s_axis_tready
+);
+
+  //---------------------------------------------------------------------------
+  //  Backend Interface
+  //---------------------------------------------------------------------------
+  wire         data_i_flush_en;
+  wire [31:0]  data_i_flush_timeout;
+  wire [63:0]  data_i_flush_active;
+  wire [63:0]  data_i_flush_done;
+  wire         data_o_flush_en;
+  wire [31:0]  data_o_flush_timeout;
+  wire [63:0]  data_o_flush_active;
+  wire [63:0]  data_o_flush_done;
+
+  backend_iface #(
+    .NOC_ID        (NOC_ID),
+    .NUM_DATA_I    (NUM_DATA_I),
+    .NUM_DATA_O    (NUM_DATA_O),
+    .CTRL_FIFOSIZE (CTRL_FIFO_SIZE),
+    .MTU           (MTU)
+  ) backend_iface_i (
+    .rfnoc_chdr_clk       (rfnoc_chdr_clk),
+    .rfnoc_ctrl_clk       (rfnoc_ctrl_clk),
+    .rfnoc_core_config    (rfnoc_core_config),
+    .rfnoc_core_status    (rfnoc_core_status),
+    .rfnoc_chdr_rst       (rfnoc_chdr_rst),
+    .rfnoc_ctrl_rst       (rfnoc_ctrl_rst),
+    .data_i_flush_en      (data_i_flush_en),
+    .data_i_flush_timeout (data_i_flush_timeout),
+    .data_i_flush_active  (data_i_flush_active),
+    .data_i_flush_done    (data_i_flush_done),
+    .data_o_flush_en      (data_o_flush_en),
+    .data_o_flush_timeout (data_o_flush_timeout),
+    .data_o_flush_active  (data_o_flush_active),
+    .data_o_flush_done    (data_o_flush_done)
+  );
+
+  //---------------------------------------------------------------------------
+  //  Control Path
+  //---------------------------------------------------------------------------
+
+  ctrlport_endpoint #(
+    .THIS_PORTID              (THIS_PORTID    ),
+    .SYNC_CLKS                (0              ),
+    .AXIS_CTRL_MST_EN         (CTRLPORT_SLV_EN),
+    .AXIS_CTRL_SLV_EN         (CTRLPORT_MST_EN),
+    .SLAVE_FIFO_SIZE          (CTRL_FIFO_SIZE )
+  ) ctrlport_ep_i (
+    .rfnoc_ctrl_clk           (rfnoc_ctrl_clk           ),
+    .rfnoc_ctrl_rst           (rfnoc_ctrl_rst           ),
+    .ctrlport_clk             (ctrlport_clk             ),
+    .ctrlport_rst             (ctrlport_rst             ),
+    .s_rfnoc_ctrl_tdata       (s_rfnoc_ctrl_tdata       ),
+    .s_rfnoc_ctrl_tlast       (s_rfnoc_ctrl_tlast       ),
+    .s_rfnoc_ctrl_tvalid      (s_rfnoc_ctrl_tvalid      ),
+    .s_rfnoc_ctrl_tready      (s_rfnoc_ctrl_tready      ),
+    .m_rfnoc_ctrl_tdata       (m_rfnoc_ctrl_tdata       ),
+    .m_rfnoc_ctrl_tlast       (m_rfnoc_ctrl_tlast       ),
+    .m_rfnoc_ctrl_tvalid      (m_rfnoc_ctrl_tvalid      ),
+    .m_rfnoc_ctrl_tready      (m_rfnoc_ctrl_tready      ),
+    .m_ctrlport_req_wr        (m_ctrlport_req_wr        ),
+    .m_ctrlport_req_rd        (m_ctrlport_req_rd        ),
+    .m_ctrlport_req_addr      (m_ctrlport_req_addr      ),
+    .m_ctrlport_req_data      (m_ctrlport_req_data      ),
+    .m_ctrlport_req_byte_en   (m_ctrlport_req_byte_en   ),
+    .m_ctrlport_req_has_time  (m_ctrlport_req_has_time  ),
+    .m_ctrlport_req_time      (m_ctrlport_req_time      ),
+    .m_ctrlport_resp_ack      (m_ctrlport_resp_ack      ),
+    .m_ctrlport_resp_status   (m_ctrlport_resp_status   ),
+    .m_ctrlport_resp_data     (m_ctrlport_resp_data     ),
+    .s_ctrlport_req_wr        (s_ctrlport_req_wr        ),
+    .s_ctrlport_req_rd        (s_ctrlport_req_rd        ),
+    .s_ctrlport_req_addr      (s_ctrlport_req_addr      ),
+    .s_ctrlport_req_portid    (s_ctrlport_req_portid    ),
+    .s_ctrlport_req_rem_epid  (s_ctrlport_req_rem_epid  ),
+    .s_ctrlport_req_rem_portid(s_ctrlport_req_rem_portid),
+    .s_ctrlport_req_data      (s_ctrlport_req_data      ),
+    .s_ctrlport_req_byte_en   (s_ctrlport_req_byte_en   ),
+    .s_ctrlport_req_has_time  (s_ctrlport_req_has_time  ),
+    .s_ctrlport_req_time      (s_ctrlport_req_time      ),
+    .s_ctrlport_resp_ack      (s_ctrlport_resp_ack      ),
+    .s_ctrlport_resp_status   (s_ctrlport_resp_status   ),
+    .s_ctrlport_resp_data     (s_ctrlport_resp_data     )
+  );
+
+  //---------------------------------------------------------------------------
+  // Data Path
+  //---------------------------------------------------------------------------
+
+  // Set WORD_W to the smaller of DATA_W and CHDR_W. This will be our common 
+  // word size between the CHDR and user data ports.
+  localparam WORD_W = DATA_W < CHDR_W ? DATA_W : CHDR_W;
+  localparam KEEP_W = `MAX(DATA_W/CHDR_W, 1);
+
+  genvar i;
+
+  for (i = 0; i < NUM_DATA_I; i = i + 1) begin : gen_in
+    wire [CHDR_W-1:0] temp_in_tdata;
+    wire              temp_in_tlast;
+    wire              temp_in_tvalid;
+    wire              temp_in_tready;
+
+    axis_packet_flush #(
+      .WIDTH              (CHDR_W),
+      .FLUSH_PARTIAL_PKTS (0),
+      .TIMEOUT_W          (32),
+      .PIPELINE           ("IN")
+    ) in_packet_flush_i (
+      .clk           (rfnoc_chdr_clk),
+      .reset         (rfnoc_chdr_rst),
+      .enable        (data_i_flush_en),
+      .timeout       (data_i_flush_timeout),
+      .flushing      (data_i_flush_active[i]),
+      .done          (data_i_flush_done[i]),
+      .s_axis_tdata  (s_rfnoc_chdr_tdata[i*CHDR_W +: CHDR_W]),
+      .s_axis_tlast  (s_rfnoc_chdr_tlast[i]),
+      .s_axis_tvalid (s_rfnoc_chdr_tvalid[i]),
+      .s_axis_tready (s_rfnoc_chdr_tready[i]),
+      .m_axis_tdata  (temp_in_tdata),
+      .m_axis_tlast  (temp_in_tlast),
+      .m_axis_tvalid (temp_in_tvalid),
+      .m_axis_tready (temp_in_tready)
+    );
+
+    axis_width_conv #(
+      .WORD_W    (WORD_W),
+      .IN_WORDS  (CHDR_W/WORD_W),
+      .OUT_WORDS (DATA_W/WORD_W),
+      .SYNC_CLKS (SYNC_DATA_CLOCKS),
+      .PIPELINE  ("NONE")
+    ) in_width_conv_i (
+      .s_axis_aclk   (rfnoc_chdr_clk),
+      .s_axis_rst    (rfnoc_chdr_rst),
+      .s_axis_tdata  (temp_in_tdata),
+      .s_axis_tkeep  ({CHDR_W/WORD_W{1'b1}}),
+      .s_axis_tlast  (temp_in_tlast),
+      .s_axis_tvalid (temp_in_tvalid),
+      .s_axis_tready (temp_in_tready),
+      .m_axis_aclk   (axis_data_clk),
+      .m_axis_rst    (axis_data_rst),
+      .m_axis_tdata  (m_axis_tdata[i*DATA_W +: DATA_W]),
+      .m_axis_tkeep  (m_axis_tkeep[i*KEEP_W +: KEEP_W]),
+      .m_axis_tlast  (m_axis_tlast[i]),
+      .m_axis_tvalid (m_axis_tvalid[i]),
+      .m_axis_tready (m_axis_tready[i])
+    );
+  end
+
+
+  for (i = 0; i < NUM_DATA_O; i = i + 1) begin : gen_out
+    wire [       CHDR_W-1:0] temp_out_tdata;
+    wire [CHDR_W/WORD_W-1:0] temp_out_tkeep;
+    wire                     temp_out_tlast;
+    wire                     temp_out_tvalid;
+    wire                     temp_out_tready;
+
+    axis_width_conv #(
+      .WORD_W    (WORD_W),
+      .IN_WORDS  (DATA_W/WORD_W),
+      .OUT_WORDS (CHDR_W/WORD_W),
+      .SYNC_CLKS (SYNC_DATA_CLOCKS),
+      .PIPELINE  ("NONE")
+    ) out_width_conv_i (
+      .s_axis_aclk   (axis_data_clk),
+      .s_axis_rst    (axis_data_rst),
+      .s_axis_tdata  (s_axis_tdata[i*DATA_W +: DATA_W]),
+      .s_axis_tkeep  (s_axis_tkeep[i*KEEP_W +: KEEP_W]),
+      .s_axis_tlast  (s_axis_tlast[i]),
+      .s_axis_tvalid (s_axis_tvalid[i]),
+      .s_axis_tready (s_axis_tready[i]),
+      .m_axis_aclk   (rfnoc_chdr_clk),
+      .m_axis_rst    (rfnoc_chdr_rst),
+      .m_axis_tdata  (temp_out_tdata),
+      .m_axis_tkeep  (),
+      .m_axis_tlast  (temp_out_tlast),
+      .m_axis_tvalid (temp_out_tvalid),
+      .m_axis_tready (temp_out_tready)
+    );
+
+    axis_packet_flush #(
+      .WIDTH              (CHDR_W),
+      .FLUSH_PARTIAL_PKTS (0),
+      .TIMEOUT_W          (32),
+      .PIPELINE           ("OUT")
+    ) out_packet_flush_i (
+      .clk           (rfnoc_chdr_clk),
+      .reset         (rfnoc_chdr_rst),
+      .enable        (data_o_flush_en),
+      .timeout       (data_o_flush_timeout),
+      .flushing      (data_o_flush_active[i]),
+      .done          (data_o_flush_done[i]),
+      .s_axis_tdata  (temp_out_tdata),
+      .s_axis_tlast  (temp_out_tlast),
+      .s_axis_tvalid (temp_out_tvalid),
+      .s_axis_tready (temp_out_tready),
+      .m_axis_tdata  (m_rfnoc_chdr_tdata[i*CHDR_W +: CHDR_W]),
+      .m_axis_tlast  (m_rfnoc_chdr_tlast[i]),
+      .m_axis_tvalid (m_rfnoc_chdr_tvalid[i]),
+      .m_axis_tready (m_rfnoc_chdr_tready[i])
+    );
+
+  end
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/rfnoc_block_axi_ram_fifo.v b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/rfnoc_block_axi_ram_fifo.v
new file mode 100644
index 000000000..04d942ce0
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/rfnoc_block_axi_ram_fifo.v
@@ -0,0 +1,485 @@
+//
+// Copyright 2019 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: rfnoc_block_axi_ram_fifo
+//
+// Description: 
+//
+//   Implements a FIFO using an AXI memory-mapped interface to an external 
+//   memory.
+//
+// Parameters:
+//
+//   THIS_PORTID    : Control crossbar port to which this block is connected
+//   
+//   CHDR_W         : CHDR AXI-Stream data bus width
+//
+//   NUM_PORTS      : Number of independent FIFOs to support, all sharing the 
+//                    same memory.
+//   
+//   MTU            : Maximum transfer unit (maximum packet size) to support, 
+//                    in CHDR_W-sized words.
+//
+//   MEM_DATA_W     : Width of the data bus to use for the AXI memory-mapped 
+//                    interface. This must be no bigger than CHDR_W and it must 
+//                    evenly divide CHDR_W.
+//
+//   MEM_ADDR_W     : Width of the byte address to use for RAM addressing. This
+//                    effectively sets the maximum combined size of all FIFOs.
+//                    This must be less than or equal to AWIDTH.
+//
+//   AWIDTH         : Width of the address bus for the AXI memory-mapped
+//                    interface. This must be at least as big as MEM_DATA_W.
+//
+//   FIFO_ADDR_BASE : Default base byte address of each FIFO. When NUM_PORTS > 
+//                    1, this should be the concatenation of all the FIFO base 
+//                    addresses. These values can be reconfigured by software.
+//
+//   FIFO_ADDR_MASK : Default byte address mask used by each FIFO. It must be 
+//                    all ones. The size of the FIFO in bytes will be this 
+//                    minus one. These values can be reconfigured by software.
+//
+//   BURST_TIMEOUT  : Default number of memory clock cycles to wait for new 
+//                    data before performing a short, sub-optimal burst. One 
+//                    value per FIFO.
+//
+//   IN_FIFO_SIZE   : Size of the input buffer. This is used to mitigate the 
+//                    effects of memory write latency, which can be significant 
+//                    when the external memory is DRAM.
+//
+//   OUT_FIFO_SIZE  : Size of the output buffer. This is used to mitigate the 
+//                    effects of memory read latency, which can be significant 
+//                    when the external memory is DRAM.
+//
+//   BIST           : Includes BIST logic when true.
+//
+//   MEM_CLK_RATE   : Frequency of mem_clk in Hz. This is used by BIST for 
+//                    throughput calculation.
+//
+
+module rfnoc_block_axi_ram_fifo #(
+  parameter                            THIS_PORTID    = 0,
+  parameter                            CHDR_W         = 64,
+  parameter                            NUM_PORTS      = 1,
+  parameter                            MTU            = 10,
+  parameter                            MEM_DATA_W     = CHDR_W,
+  parameter                            MEM_ADDR_W     = 32,
+  parameter                            AWIDTH         = 32,
+  parameter [NUM_PORTS*MEM_ADDR_W-1:0] FIFO_ADDR_BASE = {NUM_PORTS{ {MEM_ADDR_W{1'b0}} }},
+  parameter [NUM_PORTS*MEM_ADDR_W-1:0] FIFO_ADDR_MASK = {NUM_PORTS{ {(MEM_ADDR_W-$clog2(NUM_PORTS)){1'b1}} }},
+  parameter [        NUM_PORTS*32-1:0] BURST_TIMEOUT  = {NUM_PORTS{ 32'd256 }},
+  parameter                            IN_FIFO_SIZE   = 11,
+  parameter                            OUT_FIFO_SIZE  = 11,
+  parameter                            BIST           = 1,
+  parameter                            MEM_CLK_RATE   = 200e6
+) (
+  //---------------------------------------------------------------------------
+  // AXIS CHDR Port
+  //---------------------------------------------------------------------------
+
+  input wire rfnoc_chdr_clk,
+
+  // CHDR inputs from framework
+  input  wire [NUM_PORTS*CHDR_W-1:0] s_rfnoc_chdr_tdata,
+  input  wire [       NUM_PORTS-1:0] s_rfnoc_chdr_tlast,
+  input  wire [       NUM_PORTS-1:0] s_rfnoc_chdr_tvalid,
+  output wire [       NUM_PORTS-1:0] s_rfnoc_chdr_tready,
+
+  // CHDR outputs to framework
+  output wire [NUM_PORTS*CHDR_W-1:0] m_rfnoc_chdr_tdata,
+  output wire [       NUM_PORTS-1:0] m_rfnoc_chdr_tlast,
+  output wire [       NUM_PORTS-1:0] m_rfnoc_chdr_tvalid,
+  input  wire [       NUM_PORTS-1:0] m_rfnoc_chdr_tready,
+
+  // Backend interface
+  input  wire [511:0] rfnoc_core_config,
+  output wire [511:0] rfnoc_core_status,
+
+
+  //---------------------------------------------------------------------------
+  // AXIS CTRL Port
+  //---------------------------------------------------------------------------
+
+  input wire rfnoc_ctrl_clk,
+
+  // CTRL port requests from framework
+  input  wire [31:0] s_rfnoc_ctrl_tdata,
+  input  wire        s_rfnoc_ctrl_tlast,
+  input  wire        s_rfnoc_ctrl_tvalid,
+  output wire        s_rfnoc_ctrl_tready,
+
+  // CTRL port requests to framework
+  output wire [31:0] m_rfnoc_ctrl_tdata,
+  output wire        m_rfnoc_ctrl_tlast,
+  output wire        m_rfnoc_ctrl_tvalid,
+  input  wire        m_rfnoc_ctrl_tready,
+
+
+  //---------------------------------------------------------------------------
+  // AXI Memory Mapped Interface
+  //---------------------------------------------------------------------------
+
+  // AXI Interface Clock and Reset
+  input wire mem_clk,
+  input wire axi_rst,
+
+  // AXI Write Address Channel
+  output wire [         NUM_PORTS*1-1:0] m_axi_awid,     // Write address ID. This signal is the identification tag for the write address signals
+  output wire [    NUM_PORTS*AWIDTH-1:0] m_axi_awaddr,   // Write address. The write address gives the address of the first transfer in a write burst
+  output wire [         NUM_PORTS*8-1:0] m_axi_awlen,    // Burst length. The burst length gives the exact number of transfers in a burst.
+  output wire [         NUM_PORTS*3-1:0] m_axi_awsize,   // Burst size. This signal indicates the size of each transfer in the burst.
+  output wire [         NUM_PORTS*2-1:0] m_axi_awburst,  // Burst type. The burst type and the size information, determine how the address is calculated
+  output wire [         NUM_PORTS*1-1:0] m_axi_awlock,   // Lock type. Provides additional information about the atomic characteristics of the transfer.
+  output wire [         NUM_PORTS*4-1:0] m_axi_awcache,  // Memory type. This signal indicates how transactions are required to progress
+  output wire [         NUM_PORTS*3-1:0] m_axi_awprot,   // Protection type. This signal indicates the privilege and security level of the transaction
+  output wire [         NUM_PORTS*4-1:0] m_axi_awqos,    // Quality of Service, QoS. The QoS identifier sent for each write transaction
+  output wire [         NUM_PORTS*4-1:0] m_axi_awregion, // Region identifier. Permits a single physical interface on a slave to be re-used.
+  output wire [         NUM_PORTS*1-1:0] m_axi_awuser,   // User signal. Optional User-defined signal in the write address channel.
+  output wire [         NUM_PORTS*1-1:0] m_axi_awvalid,  // Write address valid. This signal indicates that the channel is signaling valid write addr
+  input  wire [         NUM_PORTS*1-1:0] m_axi_awready,  // Write address ready. This signal indicates that the slave is ready to accept an address
+  
+  // AXI Write Data Channel
+  output wire [  NUM_PORTS*MEM_DATA_W-1:0] m_axi_wdata,  // Write data
+  output wire [NUM_PORTS*MEM_DATA_W/8-1:0] m_axi_wstrb,  // Write strobes. This signal indicates which byte lanes hold valid data.
+  output wire [           NUM_PORTS*1-1:0] m_axi_wlast,  // Write last. This signal indicates the last transfer in a write burst
+  output wire [           NUM_PORTS*1-1:0] m_axi_wuser,  // User signal. Optional User-defined signal in the write data channel.
+  output wire [           NUM_PORTS*1-1:0] m_axi_wvalid, // Write valid. This signal indicates that valid write data and strobes are available.
+  input  wire [           NUM_PORTS*1-1:0] m_axi_wready, // Write ready. This signal indicates that the slave can accept the write data.
+  
+  // AXI Write Response Channel
+  input  wire [         NUM_PORTS*1-1:0] m_axi_bid,      // Response ID tag. This signal is the ID tag of the write response.
+  input  wire [         NUM_PORTS*2-1:0] m_axi_bresp,    // Write response. This signal indicates the status of the write transaction.
+  input  wire [         NUM_PORTS*1-1:0] m_axi_buser,    // User signal. Optional User-defined signal in the write response channel.
+  input  wire [         NUM_PORTS*1-1:0] m_axi_bvalid,   // Write response valid. This signal indicates that the channel is signaling a valid response
+  output wire [         NUM_PORTS*1-1:0] m_axi_bready,   // Response ready. This signal indicates that the master can accept a write response
+  
+  // AXI Read Address Channel
+  output wire [         NUM_PORTS*1-1:0] m_axi_arid,     // Read address ID. This signal is the identification tag for the read address group of signals
+  output wire [    NUM_PORTS*AWIDTH-1:0] m_axi_araddr,   // Read address. The read address gives the address of the first transfer in a read burst
+  output wire [         NUM_PORTS*8-1:0] m_axi_arlen,    // Burst length. This signal indicates the exact number of transfers in a burst.
+  output wire [         NUM_PORTS*3-1:0] m_axi_arsize,   // Burst size. This signal indicates the size of each transfer in the burst.
+  output wire [         NUM_PORTS*2-1:0] m_axi_arburst,  // Burst type. The burst type and the size information determine how the address for each transfer
+  output wire [         NUM_PORTS*1-1:0] m_axi_arlock,   // Lock type. This signal provides additional information about the atomic characteristics
+  output wire [         NUM_PORTS*4-1:0] m_axi_arcache,  // Memory type. This signal indicates how transactions are required to progress
+  output wire [         NUM_PORTS*3-1:0] m_axi_arprot,   // Protection type. This signal indicates the privilege and security level of the transaction
+  output wire [         NUM_PORTS*4-1:0] m_axi_arqos,    // Quality of Service, QoS. QoS identifier sent for each read transaction.
+  output wire [         NUM_PORTS*4-1:0] m_axi_arregion, // Region identifier. Permits a single physical interface on a slave to be re-used
+  output wire [         NUM_PORTS*1-1:0] m_axi_aruser,   // User signal. Optional User-defined signal in the read address channel.
+  output wire [         NUM_PORTS*1-1:0] m_axi_arvalid,  // Read address valid. This signal indicates that the channel is signaling valid read addr
+  input  wire [         NUM_PORTS*1-1:0] m_axi_arready,  // Read address ready. This signal indicates that the slave is ready to accept an address
+  
+  // AXI Read Data Channel
+  input  wire [         NUM_PORTS*1-1:0] m_axi_rid,      // Read ID tag. This signal is the identification tag for the read data group of signals
+  input  wire [NUM_PORTS*MEM_DATA_W-1:0] m_axi_rdata,    // Read data.
+  input  wire [         NUM_PORTS*2-1:0] m_axi_rresp,    // Read response. This signal indicates the status of the read transfer
+  input  wire [         NUM_PORTS*1-1:0] m_axi_rlast,    // Read last. This signal indicates the last transfer in a read burst.
+  input  wire [         NUM_PORTS*1-1:0] m_axi_ruser,    // User signal. Optional User-defined signal in the read data channel.
+  input  wire [         NUM_PORTS*1-1:0] m_axi_rvalid,   // Read valid. This signal indicates that the channel is signaling the required read data.
+  output wire [         NUM_PORTS*1-1:0] m_axi_rready    // Read ready. This signal indicates that the master can accept the read data and response
+);
+
+  `include "axi_ram_fifo_regs.vh"
+
+  localparam NOC_ID = 'hF1F0_0000;
+
+  // If the memory width is larger than the CHDR width, then we need to use 
+  // tkeep to track which CHDR words are valid as they go through the FIFO. 
+  // Calculate the TKEEP width here. Set to 1 if it's not needed.
+  localparam KEEP_W = (MEM_DATA_W/CHDR_W) > 1 ? (MEM_DATA_W/CHDR_W) : 1;
+
+
+  //---------------------------------------------------------------------------
+  // Parameter Checks
+  //---------------------------------------------------------------------------
+  
+  if (CHDR_W % MEM_DATA_W != 0 && MEM_DATA_W % CHDR_W != 0)
+    CHDR_W_must_be_a_multiple_of_MEM_DATA_W_or_vice_versa();
+
+  if (MEM_ADDR_W > AWIDTH)
+    MEM_ADDR_W_must_be_greater_than_AWIDTH();
+
+
+  //---------------------------------------------------------------------------
+  // NoC Shell
+  //---------------------------------------------------------------------------
+
+  wire        rfnoc_chdr_rst;
+
+  wire        ctrlport_req_wr;
+  wire        ctrlport_req_rd;
+  wire [19:0] ctrlport_req_addr;
+  wire [31:0] ctrlport_req_data;
+  wire        ctrlport_resp_ack;
+  wire [31:0] ctrlport_resp_data;
+
+  wire [NUM_PORTS*MEM_DATA_W-1:0] m_axis_data_tdata;
+  wire [    NUM_PORTS*KEEP_W-1:0] m_axis_data_tkeep;
+  wire [           NUM_PORTS-1:0] m_axis_data_tlast;
+  wire [           NUM_PORTS-1:0] m_axis_data_tvalid;
+  wire [           NUM_PORTS-1:0] m_axis_data_tready;
+
+  wire [NUM_PORTS*MEM_DATA_W-1:0] s_axis_data_tdata;
+  wire [    NUM_PORTS*KEEP_W-1:0] s_axis_data_tkeep;
+  wire [           NUM_PORTS-1:0] s_axis_data_tlast;
+  wire [           NUM_PORTS-1:0] s_axis_data_tvalid;
+  wire [           NUM_PORTS-1:0] s_axis_data_tready;
+
+  noc_shell_axi_ram_fifo #(
+    .NOC_ID           (NOC_ID),
+    .THIS_PORTID      (THIS_PORTID),
+    .CHDR_W           (CHDR_W),
+    .DATA_W           (MEM_DATA_W),
+    .CTRL_FIFO_SIZE   (5),
+    .CTRLPORT_MST_EN  (1),
+    .CTRLPORT_SLV_EN  (0),
+    .NUM_DATA_I       (NUM_PORTS),
+    .NUM_DATA_O       (NUM_PORTS),
+    .MTU              (MTU),
+    .SYNC_DATA_CLOCKS (0)
+  ) noc_shell_axi_ram_fifo_i (
+    .rfnoc_chdr_clk            (rfnoc_chdr_clk),
+    .rfnoc_chdr_rst            (rfnoc_chdr_rst),
+    .rfnoc_ctrl_clk            (rfnoc_ctrl_clk),
+    .rfnoc_ctrl_rst            (),
+    .rfnoc_core_config         (rfnoc_core_config),
+    .rfnoc_core_status         (rfnoc_core_status),
+    .s_rfnoc_chdr_tdata        (s_rfnoc_chdr_tdata),
+    .s_rfnoc_chdr_tlast        (s_rfnoc_chdr_tlast),
+    .s_rfnoc_chdr_tvalid       (s_rfnoc_chdr_tvalid),
+    .s_rfnoc_chdr_tready       (s_rfnoc_chdr_tready),
+    .m_rfnoc_chdr_tdata        (m_rfnoc_chdr_tdata),
+    .m_rfnoc_chdr_tlast        (m_rfnoc_chdr_tlast),
+    .m_rfnoc_chdr_tvalid       (m_rfnoc_chdr_tvalid),
+    .m_rfnoc_chdr_tready       (m_rfnoc_chdr_tready),
+    .s_rfnoc_ctrl_tdata        (s_rfnoc_ctrl_tdata),
+    .s_rfnoc_ctrl_tlast        (s_rfnoc_ctrl_tlast),
+    .s_rfnoc_ctrl_tvalid       (s_rfnoc_ctrl_tvalid),
+    .s_rfnoc_ctrl_tready       (s_rfnoc_ctrl_tready),
+    .m_rfnoc_ctrl_tdata        (m_rfnoc_ctrl_tdata),
+    .m_rfnoc_ctrl_tlast        (m_rfnoc_ctrl_tlast),
+    .m_rfnoc_ctrl_tvalid       (m_rfnoc_ctrl_tvalid),
+    .m_rfnoc_ctrl_tready       (m_rfnoc_ctrl_tready),
+    .ctrlport_clk              (mem_clk),
+    .ctrlport_rst              (axi_rst),
+    .m_ctrlport_req_wr         (ctrlport_req_wr),
+    .m_ctrlport_req_rd         (ctrlport_req_rd),
+    .m_ctrlport_req_addr       (ctrlport_req_addr),
+    .m_ctrlport_req_data       (ctrlport_req_data),
+    .m_ctrlport_req_byte_en    (),
+    .m_ctrlport_req_has_time   (),
+    .m_ctrlport_req_time       (),
+    .m_ctrlport_resp_ack       (ctrlport_resp_ack),
+    .m_ctrlport_resp_status    (2'b0),
+    .m_ctrlport_resp_data      (ctrlport_resp_data),
+    .s_ctrlport_req_wr         (1'b0),
+    .s_ctrlport_req_rd         (1'b0),
+    .s_ctrlport_req_addr       (20'b0),
+    .s_ctrlport_req_portid     (10'b0),
+    .s_ctrlport_req_rem_epid   (16'b0),
+    .s_ctrlport_req_rem_portid (10'b0),
+    .s_ctrlport_req_data       (32'b0),
+    .s_ctrlport_req_byte_en    (4'b0),
+    .s_ctrlport_req_has_time   (1'b0),
+    .s_ctrlport_req_time       (64'b0),
+    .s_ctrlport_resp_ack       (),
+    .s_ctrlport_resp_status    (),
+    .s_ctrlport_resp_data      (),
+    .axis_data_clk             (mem_clk),
+    .axis_data_rst             (axi_rst),
+    .m_axis_tdata              (m_axis_data_tdata),
+    .m_axis_tkeep              (m_axis_data_tkeep),
+    .m_axis_tlast              (m_axis_data_tlast),
+    .m_axis_tvalid             (m_axis_data_tvalid),
+    .m_axis_tready             (m_axis_data_tready),
+    .s_axis_tdata              (s_axis_data_tdata),
+    .s_axis_tkeep              (s_axis_data_tkeep),
+    .s_axis_tlast              (s_axis_data_tlast),
+    .s_axis_tvalid             (s_axis_data_tvalid),
+    .s_axis_tready             (s_axis_data_tready)
+  );
+
+  wire rfnoc_chdr_rst_mem_clk;
+  reg  mem_rst_block;
+
+  // Cross the CHDR reset to the mem_clk domain
+  pulse_synchronizer #(
+    .MODE ("POSEDGE")
+  ) ctrl_rst_sync_i (
+    .clk_a   (rfnoc_chdr_clk),
+    .rst_a   (1'b0),
+    .pulse_a (rfnoc_chdr_rst),
+    .busy_a  (),
+    .clk_b   (mem_clk),
+    .pulse_b (rfnoc_chdr_rst_mem_clk)
+  );
+
+  // Combine the resets in a glitch-free manner
+  always @(posedge mem_clk) begin
+    mem_rst_block <= axi_rst | rfnoc_chdr_rst_mem_clk;
+  end
+
+
+  //---------------------------------------------------------------------------
+  // CTRL Port Splitter
+  //---------------------------------------------------------------------------
+
+  wire [   NUM_PORTS-1:0] m_ctrlport_req_wr;
+  wire [   NUM_PORTS-1:0] m_ctrlport_req_rd;
+  wire [20*NUM_PORTS-1:0] m_ctrlport_req_addr;
+  wire [32*NUM_PORTS-1:0] m_ctrlport_req_data;
+  wire [   NUM_PORTS-1:0] m_ctrlport_resp_ack;
+  wire [32*NUM_PORTS-1:0] m_ctrlport_resp_data;
+
+  ctrlport_decoder #(
+    .NUM_SLAVES   (NUM_PORTS),
+    .BASE_ADDR    (0),
+    .SLAVE_ADDR_W (RAM_FIFO_ADDR_W)
+  ) ctrlport_splitter_i (
+    .ctrlport_clk            (mem_clk),
+    .ctrlport_rst            (mem_rst_block),
+    .s_ctrlport_req_wr       (ctrlport_req_wr),
+    .s_ctrlport_req_rd       (ctrlport_req_rd),
+    .s_ctrlport_req_addr     (ctrlport_req_addr),
+    .s_ctrlport_req_data     (ctrlport_req_data),
+    .s_ctrlport_req_byte_en  (4'b1111),
+    .s_ctrlport_req_has_time (1'b0),
+    .s_ctrlport_req_time     (64'b0),
+    .s_ctrlport_resp_ack     (ctrlport_resp_ack),
+    .s_ctrlport_resp_status  (),
+    .s_ctrlport_resp_data    (ctrlport_resp_data),
+    .m_ctrlport_req_wr       (m_ctrlport_req_wr),
+    .m_ctrlport_req_rd       (m_ctrlport_req_rd),
+    .m_ctrlport_req_addr     (m_ctrlport_req_addr),
+    .m_ctrlport_req_data     (m_ctrlport_req_data),
+    .m_ctrlport_req_byte_en  (),
+    .m_ctrlport_req_has_time (),
+    .m_ctrlport_req_time     (),
+    .m_ctrlport_resp_ack     (m_ctrlport_resp_ack),
+    .m_ctrlport_resp_status  ({NUM_PORTS*2{1'b0}}),
+    .m_ctrlport_resp_data    (m_ctrlport_resp_data)
+  );
+
+
+  //---------------------------------------------------------------------------
+  // FIFO Instances
+  //---------------------------------------------------------------------------
+
+  genvar i;
+  for (i = 0; i < NUM_PORTS; i = i + 1) begin : gen_ram_fifos
+
+    wire [MEM_ADDR_W-1:0] m_axi_awaddr_int;
+    wire [MEM_ADDR_W-1:0] m_axi_araddr_int;
+
+    // Resize the addresses from MEM_ADDR_W to AWIDTH
+    assign m_axi_awaddr[(AWIDTH*(i+1))-1:AWIDTH*i] = m_axi_awaddr_int;
+    assign m_axi_araddr[(AWIDTH*(i+1))-1:AWIDTH*i] = m_axi_araddr_int;
+
+    axi_ram_fifo #(
+      .MEM_ADDR_W     (MEM_ADDR_W),
+      .MEM_DATA_W     (MEM_DATA_W),
+      .KEEP_W         (KEEP_W),
+      .FIFO_ADDR_BASE (FIFO_ADDR_BASE[MEM_ADDR_W*i +: MEM_ADDR_W]),
+      .FIFO_ADDR_MASK (FIFO_ADDR_MASK[MEM_ADDR_W*i +: MEM_ADDR_W]),
+      .BURST_TIMEOUT  (BURST_TIMEOUT[32*i +: 32]),
+      .BIST           (BIST),
+      .CLK_RATE       (MEM_CLK_RATE),
+      .IN_FIFO_SIZE   (IN_FIFO_SIZE),
+      .OUT_FIFO_SIZE  (OUT_FIFO_SIZE)
+    ) axi_ram_fifo_i (
+
+      .clk(mem_clk),
+      .rst(mem_rst_block),
+
+      //-----------------------------------------------------------------------
+      // Control Port
+      //-----------------------------------------------------------------------
+
+      .s_ctrlport_req_wr      (m_ctrlport_req_wr[i]),
+      .s_ctrlport_req_rd      (m_ctrlport_req_rd[i]),
+      .s_ctrlport_req_addr    (m_ctrlport_req_addr[20*i +: 20]),
+      .s_ctrlport_req_data    (m_ctrlport_req_data[32*i +: 32]),
+      .s_ctrlport_resp_ack    (m_ctrlport_resp_ack[i]),
+      .s_ctrlport_resp_data   (m_ctrlport_resp_data[32*i +: 32]),
+
+      //-----------------------------------------------------------------------
+      // AXI-Stream FIFO Interface
+      //-----------------------------------------------------------------------
+
+      // AXI-Stream Input
+      .s_tdata        (m_axis_data_tdata[MEM_DATA_W*i +: MEM_DATA_W]),
+      .s_tkeep        (m_axis_data_tkeep[KEEP_W*i +: KEEP_W]),
+      .s_tlast        (m_axis_data_tlast[i]),
+      .s_tvalid       (m_axis_data_tvalid[i]),
+      .s_tready       (m_axis_data_tready[i]),
+      //
+      //  AXI-Stream Output
+      .m_tdata        (s_axis_data_tdata[MEM_DATA_W*i +: MEM_DATA_W]),
+      .m_tkeep        (s_axis_data_tkeep[KEEP_W*i +: KEEP_W]),
+      .m_tlast        (s_axis_data_tlast[i]),
+      .m_tvalid       (s_axis_data_tvalid[i]),
+      .m_tready       (s_axis_data_tready[i]),
+
+      //-----------------------------------------------------------------------
+      // AXI4 Memory Interface
+      //-----------------------------------------------------------------------
+
+      // AXI Write address channel
+      .m_axi_awid     (m_axi_awid[i]),
+      .m_axi_awaddr   (m_axi_awaddr_int),
+      .m_axi_awlen    (m_axi_awlen[(8*(i+1))-1:8*i]),
+      .m_axi_awsize   (m_axi_awsize[(3*(i+1))-1:3*i]),
+      .m_axi_awburst  (m_axi_awburst[(2*(i+1))-1:2*i]),
+      .m_axi_awlock   (m_axi_awlock[i]),
+      .m_axi_awcache  (m_axi_awcache[(4*(i+1))-1:4*i]),
+      .m_axi_awprot   (m_axi_awprot[(3*(i+1))-1:3*i]),
+      .m_axi_awqos    (m_axi_awqos[(4*(i+1))-1:4*i]),
+      .m_axi_awregion (m_axi_awregion[(4*(i+1))-1:4*i]),
+      .m_axi_awuser   (m_axi_awuser[i]),
+      .m_axi_awvalid  (m_axi_awvalid[i]),
+      .m_axi_awready  (m_axi_awready[i]),
+      //
+      // AXI Write data channel.
+      .m_axi_wdata    (m_axi_wdata[(MEM_DATA_W*(i+1))-1:MEM_DATA_W*i]),
+      .m_axi_wstrb    (m_axi_wstrb[((MEM_DATA_W/8)*(i+1))-1:(MEM_DATA_W/8)*i]),
+      .m_axi_wlast    (m_axi_wlast[i]),
+      .m_axi_wuser    (m_axi_wuser[i]),
+      .m_axi_wvalid   (m_axi_wvalid[i]),
+      .m_axi_wready   (m_axi_wready[i]),
+      //
+      // AXI Write response channel signals
+      .m_axi_bid      (m_axi_bid[i]),
+      .m_axi_bresp    (m_axi_bresp[(2*(i+1))-1:2*i]),
+      .m_axi_buser    (m_axi_buser[i]),
+      .m_axi_bvalid   (m_axi_bvalid[i]),
+      .m_axi_bready   (m_axi_bready[i]),
+      //
+      // AXI Read address channel
+      .m_axi_arid     (m_axi_arid[i]),
+      .m_axi_araddr   (m_axi_araddr_int),
+      .m_axi_arlen    (m_axi_arlen[(8*(i+1))-1:8*i]),
+      .m_axi_arsize   (m_axi_arsize[(3*(i+1))-1:3*i]),
+      .m_axi_arburst  (m_axi_arburst[(2*(i+1))-1:2*i]),
+      .m_axi_arlock   (m_axi_arlock[i]),
+      .m_axi_arcache  (m_axi_arcache[(4*(i+1))-1:4*i]),
+      .m_axi_arprot   (m_axi_arprot[(3*(i+1))-1:3*i]),
+      .m_axi_arqos    (m_axi_arqos[(4*(i+1))-1:4*i]),
+      .m_axi_arregion (m_axi_arregion[(4*(i+1))-1:4*i]),
+      .m_axi_aruser   (m_axi_aruser[i]),
+      .m_axi_arvalid  (m_axi_arvalid[i]),
+      .m_axi_arready  (m_axi_arready[i]),
+      //
+      // AXI Read data channel
+      .m_axi_rid      (m_axi_rid[i]),
+      .m_axi_rdata    (m_axi_rdata[(MEM_DATA_W*(i+1))-1:MEM_DATA_W*i]),
+      .m_axi_rresp    (m_axi_rresp[(2*(i+1))-1:2*i]),
+      .m_axi_rlast    (m_axi_rlast[i]),
+      .m_axi_ruser    (m_axi_ruser[i]),
+      .m_axi_rvalid   (m_axi_rvalid[i]),
+      .m_axi_rready   (m_axi_rready[i])
+    );
+
+  end
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/rfnoc_block_axi_ram_fifo_all_tb.sv b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/rfnoc_block_axi_ram_fifo_all_tb.sv
new file mode 100644
index 000000000..575c600f9
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/rfnoc_block_axi_ram_fifo_all_tb.sv
@@ -0,0 +1,70 @@
+//
+// Copyright 2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: rfnoc_block_axi_ram_fifo_all_tb
+//
+// Description:
+//
+//   This is the testbench for rfnoc_block_axi_ram_fifo that instantiates 
+//   several variations of rfnoc_block_axi_ram_fifo_tb to test different 
+//   configurations.
+//
+
+
+module rfnoc_block_axi_ram_fifo_all_tb;
+
+  timeunit 1ns;
+  timeprecision 1ps;
+
+  import PkgTestExec::*;
+
+
+  //---------------------------------------------------------------------------
+  // Test Definitions
+  //---------------------------------------------------------------------------
+
+  typedef struct {
+    int CHDR_W;
+    int NUM_PORTS;
+    int MEM_DATA_W;
+    int MEM_ADDR_W;
+    int FIFO_ADDR_W;
+    int IN_FIFO_SIZE;
+    int OUT_FIFO_SIZE;
+    bit OVERFLOW;
+    bit BIST;
+  } test_config_t;
+
+  localparam NUM_TESTS = 4;
+
+  localparam test_config_t test[NUM_TESTS] = '{
+    '{CHDR_W:  64, NUM_PORTS: 2, MEM_DATA_W:  64, MEM_ADDR_W: 13, FIFO_ADDR_W: 12, IN_FIFO_SIZE:  9, OUT_FIFO_SIZE:  9, OVERFLOW: 1, BIST: 1 },
+    '{CHDR_W:  64, NUM_PORTS: 1, MEM_DATA_W: 128, MEM_ADDR_W: 14, FIFO_ADDR_W: 13, IN_FIFO_SIZE:  9, OUT_FIFO_SIZE:  9, OVERFLOW: 1, BIST: 1 },
+    '{CHDR_W: 128, NUM_PORTS: 1, MEM_DATA_W:  64, MEM_ADDR_W: 13, FIFO_ADDR_W: 12, IN_FIFO_SIZE:  9, OUT_FIFO_SIZE: 10, OVERFLOW: 0, BIST: 1 },
+    '{CHDR_W: 128, NUM_PORTS: 1, MEM_DATA_W: 128, MEM_ADDR_W: 16, FIFO_ADDR_W: 14, IN_FIFO_SIZE: 12, OUT_FIFO_SIZE: 12, OVERFLOW: 0, BIST: 0 }
+  };
+
+
+  //---------------------------------------------------------------------------
+  // DUT Instances
+  //---------------------------------------------------------------------------
+
+  genvar i;
+  for (i = 0; i < NUM_TESTS; i++) begin : gen_test_config
+    rfnoc_block_axi_ram_fifo_tb #(
+      .CHDR_W        (test[i].CHDR_W),
+      .NUM_PORTS     (test[i].NUM_PORTS),
+      .MEM_DATA_W    (test[i].MEM_DATA_W),
+      .MEM_ADDR_W    (test[i].MEM_ADDR_W),
+      .FIFO_ADDR_W   (test[i].FIFO_ADDR_W),
+      .IN_FIFO_SIZE  (test[i].IN_FIFO_SIZE),
+      .OUT_FIFO_SIZE (test[i].OUT_FIFO_SIZE),
+      .OVERFLOW      (test[i].OVERFLOW),
+      .BIST          (test[i].BIST)
+    ) rfnoc_block_radio_tb_i ();
+  end : gen_test_config
+
+
+endmodule : rfnoc_block_axi_ram_fifo_all_tb
\ No newline at end of file
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/rfnoc_block_axi_ram_fifo_tb.sv b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/rfnoc_block_axi_ram_fifo_tb.sv
new file mode 100644
index 000000000..49e184ce0
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/rfnoc_block_axi_ram_fifo_tb.sv
@@ -0,0 +1,1114 @@
+//
+// Copyright 2019 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: rfnoc_block_axi_ram_fifo_tb
+//
+// Description:  Testbench for rfnoc_block_axi_ram_fifo
+//
+
+
+module rfnoc_block_axi_ram_fifo_tb #(
+  parameter int CHDR_W        = 64,
+  parameter int NUM_PORTS     = 2,
+  parameter int MEM_DATA_W    = 64,
+  parameter int MEM_ADDR_W    = 13,
+  parameter int FIFO_ADDR_W   = 12,
+  parameter int IN_FIFO_SIZE  = 9,
+  parameter int OUT_FIFO_SIZE = 9,
+  parameter bit OVERFLOW      = 1,
+  parameter bit BIST          = 1
+);
+
+  // Include macros and time declarations for use with PkgTestExec
+  `include "test_exec.svh"
+
+  import PkgTestExec::*;
+  import PkgChdrUtils::*;
+  import PkgRfnocBlockCtrlBfm::*;
+
+  `include "axi_ram_fifo_regs.vh"
+
+
+  //---------------------------------------------------------------------------
+  // Local Parameters
+  //---------------------------------------------------------------------------
+
+  // Simulation parameters
+  localparam int  USE_RANDOM     = 1;        // Use random simulation data (not sequential)
+  localparam real CHDR_CLK_PER   = 5.333333; // CHDR clock rate
+  localparam real CTRL_CLK_PER   = 10.0;     // CTRL clock rate
+  localparam real MEM_CLK_PER    = 3.333333; // Memory clock rate
+  localparam int  SPP            = 256;      // Samples per packet
+  localparam int  PKT_SIZE_BYTES = SPP*4;    // Bytes per packet
+  localparam int  STALL_PROB     = 25;       // BFM stall probability
+
+  // Block configuration
+  localparam int THIS_PORTID   = 'h123;
+  localparam int MTU           = 12;
+  localparam int NUM_HB        = 3;
+  localparam int CIC_MAX_DECIM = 255;
+  localparam int BURST_TIMEOUT = 64;
+  localparam int MEM_CLK_RATE  = int'(1.0e9/MEM_CLK_PER);  // Frequency in Hz
+  localparam int AWIDTH        = MEM_ADDR_W+1;
+
+  // Put FIFO 0 at the bottom of the memory and FIFO 1 immediately above it.
+  localparam bit [MEM_ADDR_W-1:0] FIFO_ADDR_BASE_0 = 0;
+  localparam bit [MEM_ADDR_W-1:0] FIFO_ADDR_BASE_1 = 2**FIFO_ADDR_W;
+  localparam bit [MEM_ADDR_W-1:0] FIFO_ADDR_MASK   = 2**FIFO_ADDR_W-1;
+
+
+  //---------------------------------------------------------------------------
+  // Clocks
+  //---------------------------------------------------------------------------
+
+  bit rfnoc_chdr_clk;
+  bit rfnoc_ctrl_clk;
+  bit mem_clk, mem_rst;
+
+  // Don't start the clocks automatically (AUTOSTART=0), since we expect
+  // multiple instances of this testbench to run in sequence. They will be
+  // started before the first test.
+  sim_clock_gen #(.PERIOD(CHDR_CLK_PER), .AUTOSTART(0))
+    rfnoc_chdr_clk_gen (.clk(rfnoc_chdr_clk), .rst());
+  sim_clock_gen #(.PERIOD(CTRL_CLK_PER), .AUTOSTART(0))
+    rfnoc_ctrl_clk_gen (.clk(rfnoc_ctrl_clk), .rst());
+  sim_clock_gen #(.PERIOD(MEM_CLK_PER), .AUOSTART(0))
+    mem_clk_gen        (.clk(mem_clk),        .rst(mem_rst));
+
+
+  //---------------------------------------------------------------------------
+  // Bus Functional Models
+  //---------------------------------------------------------------------------
+
+  RfnocBackendIf        backend            (rfnoc_chdr_clk, rfnoc_ctrl_clk);
+  AxiStreamIf #(32)     m_ctrl             (rfnoc_ctrl_clk, 1'b0);
+  AxiStreamIf #(32)     s_ctrl             (rfnoc_ctrl_clk, 1'b0);
+  AxiStreamIf #(CHDR_W) m_chdr [NUM_PORTS] (rfnoc_chdr_clk, 1'b0);
+  AxiStreamIf #(CHDR_W) s_chdr [NUM_PORTS] (rfnoc_chdr_clk, 1'b0);
+
+  // Bus functional model for a software block controller
+  RfnocBlockCtrlBfm #(.CHDR_W(CHDR_W)) blk_ctrl = 
+    new(backend, m_ctrl, s_ctrl);
+
+  // Connect block controller to BFMs
+  for (genvar i = 0; i < NUM_PORTS; i++) begin : gen_bfm_connections
+    initial begin
+      blk_ctrl.connect_master_data_port(i, m_chdr[i], PKT_SIZE_BYTES);
+      blk_ctrl.connect_slave_data_port(i, s_chdr[i]);
+      blk_ctrl.set_master_stall_prob(i, STALL_PROB);
+      blk_ctrl.set_slave_stall_prob(i, STALL_PROB);
+    end
+  end
+
+
+  //---------------------------------------------------------------------------
+  // AXI Memory Model
+  //---------------------------------------------------------------------------
+
+  // AXI Write Address Channel
+  wire [         NUM_PORTS*1-1:0] m_axi_awid;
+  wire [    NUM_PORTS*AWIDTH-1:0] m_axi_awaddr;
+  wire [         NUM_PORTS*8-1:0] m_axi_awlen;
+  wire [         NUM_PORTS*3-1:0] m_axi_awsize;
+  wire [         NUM_PORTS*2-1:0] m_axi_awburst;
+  wire [         NUM_PORTS*1-1:0] m_axi_awlock;   // Unused master output
+  wire [         NUM_PORTS*4-1:0] m_axi_awcache;  // Unused master output
+  wire [         NUM_PORTS*3-1:0] m_axi_awprot;   // Unused master output
+  wire [         NUM_PORTS*4-1:0] m_axi_awqos;    // Unused master output
+  wire [         NUM_PORTS*4-1:0] m_axi_awregion; // Unused master output
+  wire [         NUM_PORTS*1-1:0] m_axi_awuser;   // Unused master output
+  wire [         NUM_PORTS*1-1:0] m_axi_awvalid;
+  wire [         NUM_PORTS*1-1:0] m_axi_awready;
+  // AXI Write Data Channel
+  wire [  NUM_PORTS*MEM_DATA_W-1:0] m_axi_wdata;
+  wire [NUM_PORTS*MEM_DATA_W/8-1:0] m_axi_wstrb;
+  wire [           NUM_PORTS*1-1:0] m_axi_wlast;
+  wire [           NUM_PORTS*1-1:0] m_axi_wuser;  // Unused master output
+  wire [           NUM_PORTS*1-1:0] m_axi_wvalid;
+  wire [           NUM_PORTS*1-1:0] m_axi_wready;
+  // AXI Write Response Channel
+  wire [         NUM_PORTS*1-1:0] m_axi_bid;
+  wire [         NUM_PORTS*2-1:0] m_axi_bresp;
+  wire [         NUM_PORTS*1-1:0] m_axi_buser;  // Unused master input
+  wire [         NUM_PORTS*1-1:0] m_axi_bvalid;
+  wire [         NUM_PORTS*1-1:0] m_axi_bready;
+  // AXI Read Address Channel
+  wire [         NUM_PORTS*1-1:0] m_axi_arid;
+  wire [    NUM_PORTS*AWIDTH-1:0] m_axi_araddr;
+  wire [         NUM_PORTS*8-1:0] m_axi_arlen;
+  wire [         NUM_PORTS*3-1:0] m_axi_arsize;
+  wire [         NUM_PORTS*2-1:0] m_axi_arburst;
+  wire [         NUM_PORTS*1-1:0] m_axi_arlock;   // Unused master output
+  wire [         NUM_PORTS*4-1:0] m_axi_arcache;  // Unused master output
+  wire [         NUM_PORTS*3-1:0] m_axi_arprot;   // Unused master output
+  wire [         NUM_PORTS*4-1:0] m_axi_arqos;    // Unused master output
+  wire [         NUM_PORTS*4-1:0] m_axi_arregion; // Unused master output
+  wire [         NUM_PORTS*1-1:0] m_axi_aruser;   // Unused master output
+  wire [         NUM_PORTS*1-1:0] m_axi_arvalid;
+  wire [         NUM_PORTS*1-1:0] m_axi_arready;
+  // AXI Read Data Channel
+  wire [         NUM_PORTS*1-1:0] m_axi_rid;
+  wire [NUM_PORTS*MEM_DATA_W-1:0] m_axi_rdata;
+  wire [         NUM_PORTS*2-1:0] m_axi_rresp;
+  wire [         NUM_PORTS*1-1:0] m_axi_rlast;
+  wire [         NUM_PORTS*1-1:0] m_axi_ruser;  // Unused master input
+  wire [         NUM_PORTS*1-1:0] m_axi_rvalid;
+  wire [         NUM_PORTS*1-1:0] m_axi_rready;
+
+  // Unused master input signals
+  assign m_axi_buser = {NUM_PORTS{1'b0}};
+  assign m_axi_ruser = {NUM_PORTS{1'b0}};
+
+  for (genvar i = 0; i < NUM_PORTS; i = i+1) begin : gen_sim_axi_ram
+    sim_axi_ram #(
+      .AWIDTH     (AWIDTH),
+      .DWIDTH     (MEM_DATA_W),
+      .IDWIDTH    (1),
+      .BIG_ENDIAN (0),
+      .STALL_PROB (STALL_PROB)
+    ) sim_axi_ram_i (
+      .s_aclk        (mem_clk),
+      .s_aresetn     (~mem_rst),
+      .s_axi_awid    (m_axi_awid[i]),
+      .s_axi_awaddr  (m_axi_awaddr[i*AWIDTH +: AWIDTH]),
+      .s_axi_awlen   (m_axi_awlen[i*8 +: 8]),
+      .s_axi_awsize  (m_axi_awsize[i*3 +: 3]),
+      .s_axi_awburst (m_axi_awburst[i*2 +: 2]),
+      .s_axi_awvalid (m_axi_awvalid[i]),
+      .s_axi_awready (m_axi_awready[i]),
+      .s_axi_wdata   (m_axi_wdata[i*MEM_DATA_W +: MEM_DATA_W]),
+      .s_axi_wstrb   (m_axi_wstrb[i*(MEM_DATA_W/8) +: (MEM_DATA_W/8)]),
+      .s_axi_wlast   (m_axi_wlast[i]),
+      .s_axi_wvalid  (m_axi_wvalid[i]),
+      .s_axi_wready  (m_axi_wready[i]),
+      .s_axi_bid     (m_axi_bid[i]),
+      .s_axi_bresp   (m_axi_bresp[i*2 +: 2]),
+      .s_axi_bvalid  (m_axi_bvalid[i]),
+      .s_axi_bready  (m_axi_bready[i]),
+      .s_axi_arid    (m_axi_arid[i]),
+      .s_axi_araddr  (m_axi_araddr[i*AWIDTH +: AWIDTH]),
+      .s_axi_arlen   (m_axi_arlen[i*8 +: 8]),
+      .s_axi_arsize  (m_axi_arsize[i*3 +: 3]),
+      .s_axi_arburst (m_axi_arburst[i*2 +: 2]),
+      .s_axi_arvalid (m_axi_arvalid[i]),
+      .s_axi_arready (m_axi_arready[i]),
+      .s_axi_rid     (m_axi_rid[i]),
+      .s_axi_rdata   (m_axi_rdata[i*MEM_DATA_W +: MEM_DATA_W]),
+      .s_axi_rresp   (m_axi_rresp[i*2 +: 2]),
+      .s_axi_rlast   (m_axi_rlast[i]),
+      .s_axi_rvalid  (m_axi_rvalid[i]),
+      .s_axi_rready  (m_axi_rready[i])
+    );
+  end
+
+
+  //---------------------------------------------------------------------------
+  // DUT
+  //---------------------------------------------------------------------------
+
+  logic [NUM_PORTS*CHDR_W-1:0] s_rfnoc_chdr_tdata;
+  logic [       NUM_PORTS-1:0] s_rfnoc_chdr_tlast;
+  logic [       NUM_PORTS-1:0] s_rfnoc_chdr_tvalid;
+  logic [       NUM_PORTS-1:0] s_rfnoc_chdr_tready;
+
+  logic [NUM_PORTS*CHDR_W-1:0] m_rfnoc_chdr_tdata;
+  logic [       NUM_PORTS-1:0] m_rfnoc_chdr_tlast;
+  logic [       NUM_PORTS-1:0] m_rfnoc_chdr_tvalid;
+  logic [       NUM_PORTS-1:0] m_rfnoc_chdr_tready;
+
+  // Map the array of BFMs to a flat vector for the DUT
+  for (genvar i = 0; i < NUM_PORTS; i++) begin : gen_dut_connections
+    // Connect BFM master to DUT slave port
+    assign s_rfnoc_chdr_tdata[CHDR_W*i+:CHDR_W] = m_chdr[i].tdata;
+    assign s_rfnoc_chdr_tlast[i]                = m_chdr[i].tlast;
+    assign s_rfnoc_chdr_tvalid[i]               = m_chdr[i].tvalid;
+    assign m_chdr[i].tready                     = s_rfnoc_chdr_tready[i];
+
+    // Connect BFM slave to DUT master port
+    assign s_chdr[i].tdata        = m_rfnoc_chdr_tdata[CHDR_W*i+:CHDR_W];
+    assign s_chdr[i].tlast        = m_rfnoc_chdr_tlast[i];
+    assign s_chdr[i].tvalid       = m_rfnoc_chdr_tvalid[i];
+    assign m_rfnoc_chdr_tready[i] = s_chdr[i].tready;
+  end
+
+  rfnoc_block_axi_ram_fifo #(
+    .THIS_PORTID    (THIS_PORTID),
+    .CHDR_W         (CHDR_W),
+    .NUM_PORTS      (NUM_PORTS),
+    .MTU            (MTU),
+    .MEM_DATA_W     (MEM_DATA_W),
+    .MEM_ADDR_W     (MEM_ADDR_W),
+    .AWIDTH         (AWIDTH),
+    .FIFO_ADDR_BASE ({ FIFO_ADDR_BASE_1, FIFO_ADDR_BASE_0 }),
+    .FIFO_ADDR_MASK ({NUM_PORTS{FIFO_ADDR_MASK}}),
+    .BURST_TIMEOUT  ({NUM_PORTS{BURST_TIMEOUT}}),
+    .IN_FIFO_SIZE   (IN_FIFO_SIZE),
+    .OUT_FIFO_SIZE  (OUT_FIFO_SIZE),
+    .BIST           (BIST),
+    .MEM_CLK_RATE   (MEM_CLK_RATE)
+  ) rfnoc_block_axi_ram_fifo_i (
+    .rfnoc_chdr_clk      (rfnoc_chdr_clk),
+    .s_rfnoc_chdr_tdata  (s_rfnoc_chdr_tdata),
+    .s_rfnoc_chdr_tlast  (s_rfnoc_chdr_tlast),
+    .s_rfnoc_chdr_tvalid (s_rfnoc_chdr_tvalid),
+    .s_rfnoc_chdr_tready (s_rfnoc_chdr_tready),
+    .m_rfnoc_chdr_tdata  (m_rfnoc_chdr_tdata),
+    .m_rfnoc_chdr_tlast  (m_rfnoc_chdr_tlast),
+    .m_rfnoc_chdr_tvalid (m_rfnoc_chdr_tvalid),
+    .m_rfnoc_chdr_tready (m_rfnoc_chdr_tready),
+    .rfnoc_core_config   (backend.cfg),
+    .rfnoc_core_status   (backend.sts),
+    .rfnoc_ctrl_clk      (rfnoc_ctrl_clk),
+    .s_rfnoc_ctrl_tdata  (m_ctrl.tdata),
+    .s_rfnoc_ctrl_tlast  (m_ctrl.tlast),
+    .s_rfnoc_ctrl_tvalid (m_ctrl.tvalid),
+    .s_rfnoc_ctrl_tready (m_ctrl.tready),
+    .m_rfnoc_ctrl_tdata  (s_ctrl.tdata),
+    .m_rfnoc_ctrl_tlast  (s_ctrl.tlast),
+    .m_rfnoc_ctrl_tvalid (s_ctrl.tvalid),
+    .m_rfnoc_ctrl_tready (s_ctrl.tready),
+    .mem_clk             (mem_clk),
+    .axi_rst             (mem_rst),
+    .m_axi_awid          (m_axi_awid),
+    .m_axi_awaddr        (m_axi_awaddr),
+    .m_axi_awlen         (m_axi_awlen),
+    .m_axi_awsize        (m_axi_awsize),
+    .m_axi_awburst       (m_axi_awburst),
+    .m_axi_awlock        (m_axi_awlock),
+    .m_axi_awcache       (m_axi_awcache),
+    .m_axi_awprot        (m_axi_awprot),
+    .m_axi_awqos         (m_axi_awqos),
+    .m_axi_awregion      (m_axi_awregion),
+    .m_axi_awuser        (m_axi_awuser),
+    .m_axi_awvalid       (m_axi_awvalid),
+    .m_axi_awready       (m_axi_awready),
+    .m_axi_wdata         (m_axi_wdata),
+    .m_axi_wstrb         (m_axi_wstrb),
+    .m_axi_wlast         (m_axi_wlast),
+    .m_axi_wuser         (m_axi_wuser),
+    .m_axi_wvalid        (m_axi_wvalid),
+    .m_axi_wready        (m_axi_wready),
+    .m_axi_bid           (m_axi_bid),
+    .m_axi_bresp         (m_axi_bresp),
+    .m_axi_buser         (m_axi_buser),
+    .m_axi_bvalid        (m_axi_bvalid),
+    .m_axi_bready        (m_axi_bready),
+    .m_axi_arid          (m_axi_arid),
+    .m_axi_araddr        (m_axi_araddr),
+    .m_axi_arlen         (m_axi_arlen),
+    .m_axi_arsize        (m_axi_arsize),
+    .m_axi_arburst       (m_axi_arburst),
+    .m_axi_arlock        (m_axi_arlock),
+    .m_axi_arcache       (m_axi_arcache),
+    .m_axi_arprot        (m_axi_arprot),
+    .m_axi_arqos         (m_axi_arqos),
+    .m_axi_arregion      (m_axi_arregion),
+    .m_axi_aruser        (m_axi_aruser),
+    .m_axi_arvalid       (m_axi_arvalid),
+    .m_axi_arready       (m_axi_arready),
+    .m_axi_rid           (m_axi_rid),
+    .m_axi_rdata         (m_axi_rdata),
+    .m_axi_rresp         (m_axi_rresp),
+    .m_axi_rlast         (m_axi_rlast),
+    .m_axi_ruser         (m_axi_ruser),
+    .m_axi_rvalid        (m_axi_rvalid),
+    .m_axi_rready        (m_axi_rready)
+  );
+
+ 
+  //---------------------------------------------------------------------------
+  // Helper Tasks
+  //---------------------------------------------------------------------------
+
+  task automatic write_reg(int port, bit [19:0] addr, bit [31:0] value);
+    blk_ctrl.reg_write((2**RAM_FIFO_ADDR_W)*port + addr, value);
+  endtask : write_reg
+
+  task automatic write_reg_64(int port, bit [19:0] addr, bit [63:0] value);
+    blk_ctrl.reg_write((2**RAM_FIFO_ADDR_W)*port + addr + 0, value[31: 0]);
+    blk_ctrl.reg_write((2**RAM_FIFO_ADDR_W)*port + addr + 4, value[63:32]);
+  endtask : write_reg_64
+
+  task automatic read_reg(int port, bit [19:0] addr, output logic [63:0] value);
+    blk_ctrl.reg_read((2**RAM_FIFO_ADDR_W)*port + addr, value[31: 0]);
+  endtask : read_reg
+
+  task automatic read_reg_64(int port, bit [19:0] addr, output logic [63:0] value);
+    blk_ctrl.reg_read((2**RAM_FIFO_ADDR_W)*port + addr + 0, value[31: 0]);
+    blk_ctrl.reg_read((2**RAM_FIFO_ADDR_W)*port + addr + 4, value[63:32]);
+  endtask : read_reg_64
+
+
+  // Generate a unique sequence of incrementing numbers
+  task automatic gen_test_data(int num_bytes, output chdr_word_t queue[$]);
+    int             num_chdr_words;
+    chdr_word_t     val64;
+
+    // Calculate the number of chdr_word_t size words
+    num_chdr_words = int'($ceil(real'(num_bytes) / ($bits(chdr_word_t) / 8)));
+
+    for (int i = 0; i < num_chdr_words; i++) begin
+      if (USE_RANDOM) begin
+        val64 = { $urandom(), $urandom() };   // Random data, for more rigorous testing
+      end else begin
+        val64 = i;                            // Sequential data, for easier debugging
+      end
+      queue.push_back(val64);
+    end
+  endtask : gen_test_data
+
+
+  //---------------------------------------------------------------------------
+  // Reset
+  //---------------------------------------------------------------------------
+  
+  task test_reset();
+    test.start_test("Wait for Reset", 10us);
+    mem_clk_gen.reset();
+    blk_ctrl.flush_and_reset();
+    wait(!mem_rst);
+    test.end_test();
+  endtask : test_reset
+
+
+  //---------------------------------------------------------------------------
+  // Check NoC ID and Block Info
+  //---------------------------------------------------------------------------
+  
+  task test_block_info();
+    test.start_test("Verify Block Info", 2us);
+    `ASSERT_ERROR(blk_ctrl.get_noc_id() == rfnoc_block_axi_ram_fifo_i.NOC_ID, "Incorrect NOC_ID Value");
+    `ASSERT_ERROR(blk_ctrl.get_num_data_i() == NUM_PORTS, "Incorrect NUM_DATA_I Value");
+    `ASSERT_ERROR(blk_ctrl.get_num_data_o() == NUM_PORTS, "Incorrect NUM_DATA_O Value");
+    `ASSERT_ERROR(blk_ctrl.get_mtu() == MTU, "Incorrect MTU Value");
+    test.end_test();
+  endtask : test_block_info
+
+
+  //---------------------------------------------------------------------------
+  // Check Unused Signals
+  //---------------------------------------------------------------------------
+
+  task test_unused();
+    test.start_test("Check unused/static signals");
+    for (int port = 0; port < NUM_PORTS; port++) begin
+      `ASSERT_ERROR(m_axi_awlock   [port*1 +: 1] == 1'b0, "m_axi_awlock value unexpected");
+      `ASSERT_ERROR(m_axi_awcache  [port*4 +: 4] == 4'hF, "m_axi_awcache value unexpected");
+      `ASSERT_ERROR(m_axi_awprot   [port*3 +: 3] == 3'h2, "m_axi_awprot value unexpected");
+      `ASSERT_ERROR(m_axi_awqos    [port*4 +: 4] == 4'h0, "m_axi_awqos value unexpected");
+      `ASSERT_ERROR(m_axi_awregion [port*4 +: 4] == 4'h0, "m_axi_awregion value unexpected");
+      `ASSERT_ERROR(m_axi_awuser   [port*1 +: 1] == 1'b0, "m_axi_awuser value unexpected");
+      //
+      `ASSERT_ERROR(m_axi_wuser    [port*1 +: 1] == 1'b0, "m_axi_wuser value unexpected");
+      //
+      `ASSERT_ERROR(m_axi_arlock   [port*1 +: 1] == 1'b0, "m_axi_arlock value unexpected");
+      `ASSERT_ERROR(m_axi_arcache  [port*4 +: 4] == 4'hF, "m_axi_arcache value unexpected");
+      `ASSERT_ERROR(m_axi_arprot   [port*3 +: 3] == 3'h2, "m_axi_arprot value unexpected");
+      `ASSERT_ERROR(m_axi_arqos    [port*4 +: 4] == 4'h0, "m_axi_arqos value unexpected");
+      `ASSERT_ERROR(m_axi_arregion [port*4 +: 4] == 4'h0, "m_axi_arregion value unexpected");
+      `ASSERT_ERROR(m_axi_aruser   [port*1 +: 1] == 1'b0, "m_axi_aruser value unexpected");
+    end
+    test.end_test();
+  endtask : test_unused
+
+
+  //---------------------------------------------------------------------------
+  // Test Registers
+  //---------------------------------------------------------------------------
+
+  task test_registers();
+    logic [63:0] val64, expected64, temp64;
+    logic [31:0] val32, expected32, temp32;
+
+    test.start_test("Test registers", 50us);
+
+    for (int port = 0; port < NUM_PORTS; port++) begin
+      //
+      // REG_FIFO_INFO
+      //
+      expected32 = 0;
+      expected32[REG_FIFO_MAGIC_POS +: REG_FIFO_MAGIC_W] = 16'hF1F0;
+      expected32[REG_FIFO_BIST_PRSNT_POS] = (BIST != 0);
+      read_reg(port, REG_FIFO_INFO, val32);
+      `ASSERT_ERROR(val32 == expected32, "Initial value for REG_FIFO_INFO is not correct");
+
+      //
+      // REG_FIFO_READ_SUPPRESS
+      //
+      expected32 = 0;
+      expected32[REG_FIFO_IN_FIFO_SIZE_POS+:REG_FIFO_IN_FIFO_SIZE_W] = IN_FIFO_SIZE;
+      expected32[REG_FIFO_SUPPRESS_THRESH_POS+:REG_FIFO_SUPPRESS_THRESH_W] = 0;
+      read_reg(port, REG_FIFO_READ_SUPPRESS, val32);
+      `ASSERT_ERROR(val32 == expected32, "Initial value for REG_FIFO_READ_SUPPRESS is not correct");
+
+      temp32 = expected32;
+      expected32[REG_FIFO_SUPPRESS_THRESH_POS+:REG_FIFO_SUPPRESS_THRESH_W] = 
+        ~val32[REG_FIFO_SUPPRESS_THRESH_POS+:REG_FIFO_SUPPRESS_THRESH_W];
+      write_reg(port, REG_FIFO_READ_SUPPRESS, expected32);
+      read_reg(port, REG_FIFO_READ_SUPPRESS, val32);
+      `ASSERT_ERROR(val32 == expected32, "REG_FIFO_READ_SUPPRESS did not update");
+
+      expected32 = temp32;
+      write_reg(port, REG_FIFO_READ_SUPPRESS, expected32);
+      read_reg(port, REG_FIFO_READ_SUPPRESS, val32);
+      `ASSERT_ERROR(val32 == expected32, "REG_FIFO_READ_SUPPRESS did not reset");
+
+      //
+      // REG_FIFO_MEM_SIZE
+      //
+      expected32 = 0;
+      expected32[REG_FIFO_DATA_SIZE_POS +: REG_FIFO_DATA_SIZE_W] = MEM_DATA_W;
+      expected32[REG_FIFO_ADDR_SIZE_POS +: REG_FIFO_ADDR_SIZE_W] = MEM_ADDR_W;
+      read_reg(port, REG_FIFO_MEM_SIZE, val32);
+      `ASSERT_ERROR(val32 == expected32, "Incorrect REG_FIFO_MEM_SIZE value!");
+
+      //
+      // REG_FIFO_TIMEOUT
+      //
+      expected32 = BURST_TIMEOUT;
+      read_reg(port, REG_FIFO_TIMEOUT, val32);
+      `ASSERT_ERROR(val32 == expected32, "Initial value for REG_FIFO_TIMEOUT is not correct");
+
+      write_reg(port, REG_FIFO_TIMEOUT, {REG_TIMEOUT_W{1'b1}});
+      read_reg(port, REG_FIFO_TIMEOUT, val32);
+      `ASSERT_ERROR(val32 == {REG_TIMEOUT_W{1'b1}}, "REG_FIFO_TIMEOUT did not update");
+
+      write_reg(port, REG_FIFO_TIMEOUT, expected32);
+      read_reg(port, REG_FIFO_TIMEOUT, val32);
+      `ASSERT_ERROR(val32 == expected32, "REG_FIFO_TIMEOUT did not reset");
+
+      //
+      // REG_FIFO_FULLNESS
+      //
+      read_reg_64(port, REG_FIFO_FULLNESS_LO, val64);
+      `ASSERT_ERROR(val64 == 0, "Incorrect REG_FIFO_FULLNESS value!");
+
+      //
+      // REG_FIFO_ADDR_BASE
+      //
+      expected64 = port * 2**FIFO_ADDR_W;
+      read_reg_64(port, REG_FIFO_ADDR_BASE_LO, val64);
+      `ASSERT_ERROR(val64 == expected64, "Initial value for REG_FIFO_ADDR_BASE is not correct");
+
+      write_reg_64(port, REG_FIFO_ADDR_BASE_LO, {MEM_ADDR_W{1'b1}});
+      read_reg_64(port, REG_FIFO_ADDR_BASE_LO, val64);
+      `ASSERT_ERROR(val64 == {MEM_ADDR_W{1'b1}}, "REG_FIFO_ADDR_BASE did not update");
+
+      write_reg_64(port, REG_FIFO_ADDR_BASE_LO, expected64);
+      read_reg_64(port, REG_FIFO_ADDR_BASE_LO, val64);
+      `ASSERT_ERROR(val64 == expected64, "REG_FIFO_ADDR_BASE did not reset");
+
+      //
+      // REG_FIFO_ADDR_MASK
+      //
+      expected64 = {FIFO_ADDR_W{1'b1}};
+      read_reg_64(port, REG_FIFO_ADDR_MASK_LO, val64);
+      `ASSERT_ERROR(val64 == expected64, "Initial value for REG_FIFO_ADDR_MASK_LO is not correct");
+
+      // Set to the max value
+      write_reg_64(port, REG_FIFO_ADDR_MASK_LO, {MEM_ADDR_W{1'b1}});
+      read_reg_64(port, REG_FIFO_ADDR_MASK_LO, val64);
+      `ASSERT_ERROR(val64 == {MEM_ADDR_W{1'b1}}, "REG_FIFO_ADDR_MASK_LO did not update");
+
+      // Set to the min value
+      write_reg_64(port, REG_FIFO_ADDR_MASK_LO, 0);
+      read_reg_64(port, REG_FIFO_ADDR_MASK_LO, val64);
+      // Coerce to the minimum allowed value
+      temp64 = rfnoc_block_axi_ram_fifo_i.gen_ram_fifos[0].axi_ram_fifo_i.FIFO_ADDR_MASK_MIN;
+      `ASSERT_ERROR(val64 == temp64, "REG_FIFO_ADDR_MASK_LO did not update");
+
+      write_reg_64(port, REG_FIFO_ADDR_MASK_LO, expected64);
+      read_reg_64(port, REG_FIFO_ADDR_MASK_LO, val64);
+      `ASSERT_ERROR(val64 == expected64, "REG_FIFO_ADDR_MASK_LO did not reset");
+
+      //
+      // REG_FIFO_PACKET_CNT
+      //
+      read_reg(port, REG_FIFO_PACKET_CNT, val32);
+      `ASSERT_ERROR(val32 == 0, "Incorrect REG_FIFO_PACKET_CNT value!");
+
+      if (BIST) begin
+        read_reg(port, REG_BIST_CTRL, val32);
+        `ASSERT_ERROR(val32 == 0, "Initial value for REG_BIST_CTRL is not correct");
+        read_reg(port, REG_BIST_CLK_RATE, val32);
+        `ASSERT_ERROR(val32 == MEM_CLK_RATE, "Initial value for REG_BIST_CLK_RATE is not correct");
+        read_reg_64(port, REG_BIST_NUM_BYTES_LO, val64);
+        `ASSERT_ERROR(val64 == 0, "Initial value for REG_BIST_NUM_BYTES is not correct");
+        read_reg_64(port, REG_BIST_TX_BYTE_COUNT_LO, val64);
+        `ASSERT_ERROR(val64 == 0, "Initial value for REG_BIST_TX_BYTE_COUNT is not correct");
+        read_reg_64(port, REG_BIST_RX_BYTE_COUNT_LO, val64);
+        `ASSERT_ERROR(val64 == 0, "Initial value for REG_BIST_RX_BYTE_COUNT is not correct");
+        read_reg_64(port, REG_BIST_ERROR_COUNT_LO, val64);
+        `ASSERT_ERROR(val64 == 0, "Initial value for REG_BIST_ERROR_COUNT is not correct");
+        read_reg_64(port, REG_BIST_CYCLE_COUNT_LO, val64);
+        `ASSERT_ERROR(val64 == 0, "Initial value for REG_BIST_CYCLE_COUNT is not correct");
+      end
+    end
+
+    test.end_test();
+  endtask : test_registers
+
+
+  //---------------------------------------------------------------------------
+  // Basic Test
+  //---------------------------------------------------------------------------
+  //
+  // Push a few packets through each FIFO.
+  //
+  //---------------------------------------------------------------------------
+
+  task test_basic();
+    logic [31:0] val32;
+
+    test.start_test("Basic test", NUM_PORTS*20us);
+
+    for (int port = 0; port < NUM_PORTS; port++) begin
+      chdr_word_t test_data[$];
+      logic [63:0] val64;
+      timeout_t timeout;
+
+      // Generate the test data to send
+      gen_test_data(PKT_SIZE_BYTES*3, test_data);
+
+      // Queue up the packets to send
+      blk_ctrl.send_packets(port, test_data);
+
+      // Make sure fullness increases
+      test.start_timeout(timeout, 4us, 
+        $sformatf("Waiting for fullness to increase on port %0d", port));
+      forever begin
+        read_reg_64(port, REG_FIFO_FULLNESS_LO, val64);
+        if (val64 != 0) break;
+      end
+      test.end_timeout(timeout);
+
+      // Verify the data, one packet at a time
+      for (int count = 0; count < test_data.size(); ) begin
+        chdr_word_t recv_data[$];
+        int data_bytes;
+        blk_ctrl.recv(port, recv_data, data_bytes);
+
+        `ASSERT_ERROR(
+          data_bytes == PKT_SIZE_BYTES, 
+          "Length didn't match expected value"
+        );
+
+        for (int i = 0; i < recv_data.size(); i++, count++) begin
+          if (recv_data[i] != test_data[count]) begin
+            $display("Expected %X, received %X on port %0d", test_data[count], recv_data[i], port);
+          end
+          `ASSERT_ERROR(
+            recv_data[i] == test_data[count], 
+            "Received data doesn't match expected value"
+          );
+        end
+      end
+
+      // Make sure the packet count updated
+      read_reg(port, REG_FIFO_PACKET_CNT, val32);
+      `ASSERT_ERROR(val32 > 0, "REG_FIFO_PACKET_CNT didn't update");
+    end
+
+    test.end_test();
+  endtask : test_basic
+
+
+  //---------------------------------------------------------------------------
+  // Single Byte Test
+  //---------------------------------------------------------------------------
+
+  task test_single_byte();
+    test.start_test("Single byte test", 20us);
+
+    for (int port = 0; port < NUM_PORTS; port++) begin
+      chdr_word_t test_data[$];
+      chdr_word_t recv_data[$];
+      int data_bytes;
+
+      gen_test_data(1, test_data);
+
+      blk_ctrl.send(port, test_data, 1);
+      blk_ctrl.recv(port, recv_data, data_bytes);
+
+      `ASSERT_ERROR(
+        data_bytes == 1 && recv_data.size() == CHDR_W/$bits(chdr_word_t), 
+        "Length didn't match expected value"
+      );
+      `ASSERT_ERROR(
+        recv_data[0][7:0] == test_data[0][7:0], 
+        "Received data doesn't match expected value"
+      );
+    end
+
+    test.end_test();
+  endtask : test_single_byte
+
+
+  //---------------------------------------------------------------------------
+  // Test Overflow
+  //---------------------------------------------------------------------------
+  // 
+  // Fill the FIFO on both ports to make sure if fills correctly and flow 
+  // control works correct at the limits.
+  //
+  //---------------------------------------------------------------------------
+
+  task test_overflow();
+    chdr_word_t test_data[NUM_PORTS][$];
+    int num_bytes, num_words;
+    bit [NUM_PORTS-1:0] full_bits;
+    logic [63:0] val64;
+    timeout_t timeout;
+    realtime start_time;
+
+    if (!OVERFLOW) return;
+
+    num_bytes = (MEM_DATA_W/8) * (2**IN_FIFO_SIZE + 2**OUT_FIFO_SIZE) + 2**MEM_ADDR_W;
+    num_bytes = num_bytes * 3 / 2;
+    num_words = num_bytes / (CHDR_W/8);
+
+    test.start_test("Overflow test", 10 * num_words * CHDR_CLK_PER);
+
+    // Stall the output of each FIFO, allow unrestricted input
+    for (int port = 0; port < NUM_PORTS; port++) begin
+      blk_ctrl.set_master_stall_prob(port, 0);
+      blk_ctrl.set_slave_stall_prob(port, 100);
+    end
+
+    // Input more packets into each FIFO than they can fit
+    for (int port = 0; port < NUM_PORTS; port++) begin
+      gen_test_data(num_bytes, test_data[port]);
+      blk_ctrl.send_packets(port, test_data[port]);
+    end
+
+    // Wait for both inputs to stall
+    test.start_timeout(timeout, (4 * num_words + 1000) * CHDR_CLK_PER, 
+      $sformatf("Waiting for input to stall"));
+    full_bits = 0;
+    forever begin
+      for (int port = 0; port < NUM_PORTS; port++) begin
+        full_bits[port] = ~s_rfnoc_chdr_tready[port];
+        if (!full_bits[port]) start_time = $realtime;
+      end
+
+      // Break as soon as all FIFOs have been stalled for 1000 clock cycles
+      if (full_bits == {NUM_PORTS{1'b1}} && $realtime-start_time > 1000 * CHDR_CLK_PER) break;
+      #(CHDR_CLK_PER*100);
+    end
+    test.end_timeout(timeout);
+
+    // Make sure all the FIFOs filled up
+    for (int port = 0; port < NUM_PORTS; port++) begin
+      read_reg_64(port, REG_FIFO_FULLNESS_LO, val64);
+      // FIFO is full once it comes within 256 words of being full
+      `ASSERT_ERROR(val64 >= (2**FIFO_ADDR_W / (MEM_DATA_W/8)) - 256, "FIFO not reading full");
+    end
+
+    // Restore the input/output rates
+    for (int port = 0; port < NUM_PORTS; port++) begin
+      blk_ctrl.set_master_stall_prob(port, STALL_PROB);
+      blk_ctrl.set_slave_stall_prob(port, STALL_PROB);
+    end
+
+    // Read out and verify the data
+    for (int port = 0; port < NUM_PORTS; port++) begin
+      for (int count = 0; count < test_data[port].size(); ) begin
+        chdr_word_t recv_data[$];
+        int data_bytes;
+        int expected_length;
+        blk_ctrl.recv(port, recv_data, data_bytes);
+
+        if (count*($bits(chdr_word_t)/8) + PKT_SIZE_BYTES <= num_bytes) begin
+          // Should be a full packet
+          expected_length = PKT_SIZE_BYTES;
+        end else begin
+          // Should be a partial packet
+          expected_length = num_bytes % PKT_SIZE_BYTES;
+        end
+
+        // Check the length
+        `ASSERT_ERROR(
+          data_bytes == expected_length, 
+          "Length didn't match expected value"
+        );
+
+        for (int i = 0; i < recv_data.size(); i++, count++) begin
+          `ASSERT_ERROR(
+            recv_data[i] == test_data[port][count], 
+            "Received data doesn't match expected value"
+          );
+        end
+      end
+    end
+
+    test.end_test();
+  endtask : test_overflow
+
+
+  //---------------------------------------------------------------------------
+  // Test Read Suppression
+  //---------------------------------------------------------------------------
+
+  task test_read_suppression();
+    chdr_word_t test_data[$];
+    logic [31:0] val32, save32;
+    int port;
+
+    test.start_test("Read suppression test", 100us);
+
+    port = 0; // Only test one port
+
+    // Turn on read suppression with the max threshold to cause it to 
+    // suppress everything.
+    read_reg(port, REG_FIFO_READ_SUPPRESS, save32);
+    val32 = save32;
+    val32[REG_FIFO_SUPPRESS_THRESH_POS +: REG_FIFO_SUPPRESS_THRESH_W] = {REG_FIFO_SUPPRESS_THRESH_W{1'b1}};
+    write_reg(port, REG_FIFO_READ_SUPPRESS, val32);
+
+    // Generate the test data to send (send 8 RAM bursts)
+    gen_test_data(MEM_DATA_W/8 * 256 * 8, test_data);
+
+    // Start sending packets then wait for the input to stall, either because 
+    // we've filled the FIFO or we've input everything.
+    blk_ctrl.set_master_stall_prob(port, 0);
+    blk_ctrl.send_packets(port, test_data);
+    wait (s_rfnoc_chdr_tvalid && s_rfnoc_chdr_tready);
+    wait (!s_rfnoc_chdr_tvalid || !s_rfnoc_chdr_tready);
+
+    // Make sure nothing made it through
+    `ASSERT_ERROR(blk_ctrl.num_received(port) == 0, "Read suppression failed");
+
+    // Turn down the threshold 
+    val32[REG_FIFO_SUPPRESS_THRESH_POS +: REG_FIFO_SUPPRESS_THRESH_W] = {REG_FIFO_SUPPRESS_THRESH_W{1'b0}};
+    write_reg(port, REG_FIFO_READ_SUPPRESS, val32);
+
+    blk_ctrl.set_master_stall_prob(port, STALL_PROB);
+
+    // Verify the data, one packet at a time
+    for (int count = 0; count < test_data.size(); ) begin
+      chdr_word_t recv_data[$];
+      int data_bytes;
+      blk_ctrl.recv(port, recv_data, data_bytes);
+
+      for (int i = 0; i < recv_data.size(); i++, count++) begin
+        if (recv_data[i] != test_data[count]) begin
+          $display("Expected %X, received %X on port %0d", test_data[count], recv_data[i], port);
+        end
+        `ASSERT_ERROR(
+          recv_data[i] == test_data[count], 
+          "Received data doesn't match expected value"
+        );
+      end
+    end
+
+    // Restore suppression settings
+    write_reg(port, REG_FIFO_READ_SUPPRESS, save32);
+
+    test.end_test();
+  endtask : test_read_suppression
+
+
+  //---------------------------------------------------------------------------
+  // Random Tests
+  //---------------------------------------------------------------------------
+  //
+  // Perform a series of random tests with different read/write probabilities 
+  // test unexpected conditions.
+  //
+  //---------------------------------------------------------------------------
+
+  class RandTrans;
+    chdr_word_t data[$];
+    int         num_bytes;
+  endclass;
+
+  task test_random();
+    localparam NUM_PACKETS = 256;
+
+    mailbox #(RandTrans) data_queue;
+    int port;
+
+    test.start_test("Random test", NUM_PACKETS * 2us);
+
+    data_queue = new();
+    port       = 0;         // Just check one port for this test
+
+    // Queue up a bunch of random packets
+    begin : data_gen
+      RandTrans trans;
+      $display("Generating %0d random packets...", NUM_PACKETS);
+
+      for (int packet_count = 0; packet_count < NUM_PACKETS; packet_count++) begin
+        trans = new();
+        trans.num_bytes = $urandom_range(1, PKT_SIZE_BYTES);
+        gen_test_data(trans.num_bytes, trans.data);
+        blk_ctrl.send(port, trans.data, trans.num_bytes);
+        data_queue.put(trans);
+      end
+    end
+
+    // Receive and check all the packets
+    fork
+      begin : stall_update
+        // Split the packets into four groups and use different stall 
+        // behavior for each. 
+        // 
+        //   1. Start filling up the FIFO
+        //   2. Let it run for a while
+        //   3. Start emptying the FIFO
+        //   4. Let it run until all the data gets through
+        //
+        for (int i = 0; i < 4; i++) begin
+          case (i)
+            0 : begin
+              $display("Test fast writer, slow reader");
+              blk_ctrl.set_master_stall_prob(port, 10);
+              blk_ctrl.set_slave_stall_prob(port, 80);
+            end
+            1 : begin
+              $display("Test matched reader/writer");
+              blk_ctrl.set_master_stall_prob(port, STALL_PROB);
+              blk_ctrl.set_slave_stall_prob(port, STALL_PROB);
+            end
+            2 : begin
+              $display("Test slow writer, fast reader");
+              blk_ctrl.set_master_stall_prob(port, 90);
+              blk_ctrl.set_slave_stall_prob(port, 10);
+            end
+            3 : begin
+              $display("Test matched reader/writer");
+              blk_ctrl.set_master_stall_prob(port, STALL_PROB);
+              blk_ctrl.set_slave_stall_prob(port, STALL_PROB);
+            end
+          endcase
+
+          // Wait for a quarter of the packets to be accepted by the RAM FIFO
+          blk_ctrl.wait_complete(port, NUM_PACKETS/4);
+        end
+      end
+      begin : data_check
+        RandTrans   trans;
+        chdr_word_t recv_data[$];
+        int         num_bytes;
+        int         num_words;
+
+
+        for (int packet_count = 0; packet_count < NUM_PACKETS; packet_count++) begin
+          //$display("Checking packet %0d/%0d...", packet_count, NUM_PACKETS);
+
+          blk_ctrl.recv(port, recv_data, num_bytes);
+          data_queue.get(trans);
+
+          // Check the length
+          `ASSERT_ERROR(
+            num_bytes == trans.num_bytes, 
+            "Length didn't match expected value"
+          );
+
+          // If the generated data was an odd number of chdr_word_t words, we 
+          // will get back an extra 0 word at the end. Calculate the correct 
+          // number of words so that we ignore any extra at the end.
+          num_words = int'($ceil(real'(num_bytes)/($bits(chdr_word_t)/8)));
+          for (int i = 0; i < num_words; i++) begin
+            `ASSERT_ERROR(
+              recv_data[i] == trans.data[i],
+              "Received data doesn't match expected value"
+            );
+          end
+        end
+      end
+    join
+
+    test.end_test();
+  endtask : test_random
+
+
+  //---------------------------------------------------------------------------
+  // Test Clearing FIFO Block
+  //---------------------------------------------------------------------------
+
+  task test_clear();
+   test.start_test("FIFO clear test", 100us);
+
+   // TODO:
+   $warning("Need to write a test flushing and resetting the block!");
+
+   test.end_test();
+  endtask : test_clear
+
+
+  //---------------------------------------------------------------------------
+  // Test BIST
+  //---------------------------------------------------------------------------
+
+  task test_bist();
+    logic [31:0] val32;
+    logic [63:0] val64;
+    int port;
+    int num_bytes;
+
+    if (!BIST) return;
+
+    test.start_test("BIST test", 100us);
+
+    port = 0;  // Test the first port
+    num_bytes = 2048;
+
+    // Start a test
+    write_reg(port, REG_BIST_CTRL, 1 << REG_BIST_CLEAR_POS);
+    write_reg(port, REG_BIST_NUM_BYTES_LO, num_bytes);
+    write_reg(port, REG_BIST_CTRL, 1 << REG_BIST_START_POS);
+
+    // Make sure running bit gets set
+    read_reg(port, REG_BIST_CTRL, val32);
+    `ASSERT_ERROR(val32[REG_BIST_RUNNING_POS] == 1'b1, "RUNNING bit not set");
+
+    // Wait for the test to complete
+    do begin
+      read_reg(port, REG_BIST_CTRL, val32);
+    end while(val32[REG_BIST_RUNNING_POS]);
+
+    // Check the results
+    read_reg_64(port, REG_BIST_TX_BYTE_COUNT_LO, val64);
+    `ASSERT_ERROR(val64 == num_bytes, "TX_BYTE_COUNT is not correct");
+    read_reg_64(port, REG_BIST_RX_BYTE_COUNT_LO, val64);
+    `ASSERT_ERROR(val64 == num_bytes, "RX_BYTE_COUNT is not correct");
+    read_reg_64(port, REG_BIST_ERROR_COUNT_LO, val64);
+    `ASSERT_ERROR(val64 == 0, "ERROR_COUNT is not zero");
+    read_reg_64(port, REG_BIST_CYCLE_COUNT_LO, val64);
+    `ASSERT_ERROR(val64 > 0, "CYCLE_COUNT did not update");
+
+    // TODO:
+    $warning("BIST Continuous mode is NOT being tested");
+    $warning("BIST error insertion is NOT being tested (errors might be ignored)");
+
+    test.end_test();
+  endtask : test_bist
+
+
+  //---------------------------------------------------------------------------
+  // BIST Throughput Test
+  //---------------------------------------------------------------------------
+  //
+  // This test sanity-checks the values returned by the BIST. If run with the
+  // other BIST test, it also tests clearing the BIST counters.
+  //
+  //---------------------------------------------------------------------------
+
+  task test_bist_throughput();
+    localparam   port = 0;  // Test the first port
+    logic [31:0] val32;
+    logic [63:0] val64;
+    int          num_bytes;
+    longint      rx_byte_count;
+    longint      cycle_count;
+    real         throughput;
+    real         efficiency;
+
+    if (!BIST) return;
+
+    test.start_test("BIST throughput test", 100us);
+
+    num_bytes = 64*1024;
+
+    // Reset the memory probability
+    gen_sim_axi_ram[port].sim_axi_ram_i.set_stall_prob(0);
+
+    // Start a test
+    write_reg(port, REG_BIST_CTRL, 1 << REG_BIST_CLEAR_POS);
+    write_reg(port, REG_BIST_NUM_BYTES_LO, num_bytes);
+    write_reg(port, REG_BIST_CTRL, 1 << REG_BIST_START_POS);
+
+    // Make sure running bit gets set
+    read_reg(port, REG_BIST_CTRL, val32);
+    `ASSERT_ERROR(val32[REG_BIST_RUNNING_POS] == 1'b1, "RUNNING bit not set");
+
+    // Wait for the test to complete
+    do begin
+      read_reg(port, REG_BIST_CTRL, val32);
+    end while(val32[REG_BIST_RUNNING_POS]);
+
+    // Check the results
+    read_reg_64(port, REG_BIST_TX_BYTE_COUNT_LO, val64);
+    `ASSERT_ERROR(val64 == num_bytes, "TX_BYTE_COUNT is not correct");
+    read_reg_64(port, REG_BIST_RX_BYTE_COUNT_LO, rx_byte_count);
+    `ASSERT_ERROR(rx_byte_count == num_bytes, "RX_BYTE_COUNT is not correct");
+    read_reg_64(port, REG_BIST_ERROR_COUNT_LO, val64);
+    `ASSERT_ERROR(val64 == 0, "ERROR_COUNT is not zero");
+    read_reg_64(port, REG_BIST_CYCLE_COUNT_LO, cycle_count);
+    `ASSERT_ERROR(cycle_count > 0, "CYCLE_COUNT did not update");
+
+    // Throughput = num_bytes / time = num_bytes / (num_cyles * period)
+    throughput = real'(rx_byte_count) / (real'(cycle_count) / real'(MEM_CLK_RATE));
+
+    // Efficiency is the actual throughput divided by the theoretical max. We
+    // use 0.5x in the calculation because we assume that the memory is a
+    // half-duplex read/write memory running at MEM_CLK_RATE, but we're
+    // measuring the full-duplex throughput.
+    efficiency = throughput / (0.5 * real'(MEM_CLK_RATE) * (MEM_DATA_W/8));
+
+    $display("BIST Throughput: %0.1f MB/s", throughput / 1.0e6);
+    $display("BIST Efficiency: %0.1f %%", efficiency * 100.0 );
+
+    `ASSERT_ERROR(efficiency > 0.95, "BIST efficiency was lower than expected");
+
+    // Restore the memory stall probability
+    gen_sim_axi_ram[port].sim_axi_ram_i.set_stall_prob(STALL_PROB);
+
+    test.end_test();
+  endtask;
+
+
+  //---------------------------------------------------------------------------
+  // Main Test Process
+  //---------------------------------------------------------------------------
+
+  initial begin : tb_main
+    const int port = 0;
+    string tb_name;
+
+    // Generate a string for the name of this instance of the testbench
+    tb_name = $sformatf(
+      "rfnoc_block_axi_ram_fifo_tb\nCHDR_W = %0D, NUM_PORTS = %0D, MEM_DATA_W = %0D, MEM_ADDR_W = %0D, FIFO_ADDR_W = %0D, IN_FIFO_SIZE = %0D, OUT_FIFO_SIZE = %0D, OVERFLOW = %0D, BIST = %0D",
+      CHDR_W, NUM_PORTS, MEM_DATA_W, MEM_ADDR_W, FIFO_ADDR_W, IN_FIFO_SIZE, OUT_FIFO_SIZE, OVERFLOW, BIST
+    );
+    test.start_tb(tb_name);
+
+    // Don't start the clocks until after start_tb() returns. This ensures that
+    // the clocks aren't toggling while other instances of this testbench are
+    // running, which speeds up simulation time.
+    rfnoc_chdr_clk_gen.start();
+    rfnoc_ctrl_clk_gen.start();
+    mem_clk_gen.start();
+
+    // Start the BFMs running
+    blk_ctrl.run();
+
+    //
+    // Run test procedures
+    //
+    test_reset();
+    test_block_info();
+    test_unused();
+    test_registers();
+    test_basic();
+    test_single_byte();
+    test_overflow();
+    test_read_suppression();
+    test_random();
+    test_clear();
+    test_bist();
+    test_bist_throughput();
+
+    // End the TB, but don't $finish, since we don't want to kill other 
+    // instances of this testbench that may be running.
+    test.end_tb(0);
+
+    // Kill the clocks to end this instance of the testbench
+    rfnoc_chdr_clk_gen.kill();
+    rfnoc_ctrl_clk_gen.kill();
+    mem_clk_gen.kill();
+  end
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/sim_axi_ram.sv b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/sim_axi_ram.sv
new file mode 100644
index 000000000..ee7ff5df8
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/sim_axi_ram.sv
@@ -0,0 +1,637 @@
+//
+// Copyright 2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: sim_axi_ram
+//
+// Description: 
+//
+//   Simulation model for a basic AXI4 memory mapped memory. A few notes on its 
+//   behavior:
+//
+//     - This model does not reorder requests (regardless of WID/RID). All 
+//       requests are evaluated strictly in order.
+//     - The only supported response is OKAY
+//     - This model supports misaligned memory accesses, which cause a 
+//       simulation warning.
+//     - A reset does not clear the memory contents
+//     - The memory itself is implemented using an associative array (sparse 
+//       matrix) so that large memories can be supported.
+//     - This model is half duplex, meaning read and write data transfers won't
+//       happen at the same time. A new data transfer won't begin until the
+//       previous one has completed.
+//
+
+module sim_axi_ram #(
+  parameter AWIDTH     = 32,
+  parameter DWIDTH     = 64,
+  parameter IDWIDTH    = 2,
+  parameter BIG_ENDIAN = 0,
+  parameter STALL_PROB = 25
+) (
+  input logic s_aclk,
+  input logic s_aresetn,
+
+  // Write Address Channel
+  input  logic [IDWIDTH-1:0] s_axi_awid,
+  input  logic [ AWIDTH-1:0] s_axi_awaddr,
+  input  logic [        7:0] s_axi_awlen,
+  input  logic [        2:0] s_axi_awsize,
+  input  logic [        1:0] s_axi_awburst,
+  input  logic               s_axi_awvalid,
+  output logic               s_axi_awready,
+
+  // Write Data Channel
+  input  logic [  DWIDTH-1:0] s_axi_wdata,
+  input  logic [DWIDTH/8-1:0] s_axi_wstrb,
+  input  logic                s_axi_wlast,
+  input  logic                s_axi_wvalid,
+  output logic                s_axi_wready,
+
+  // Write Response Channel
+  output logic [IDWIDTH-1:0] s_axi_bid,
+  output logic [        1:0] s_axi_bresp,
+  output logic               s_axi_bvalid,
+  input  logic               s_axi_bready,
+
+  // Read Address Channel
+  input  logic [IDWIDTH-1:0] s_axi_arid,
+  input  logic [ AWIDTH-1:0] s_axi_araddr,
+  input  logic [        7:0] s_axi_arlen,
+  input  logic [        2:0] s_axi_arsize,
+  input  logic [        1:0] s_axi_arburst,
+  input  logic               s_axi_arvalid,
+  output logic               s_axi_arready,
+
+  // Read Data Channel
+  output logic [       0:0] s_axi_rid,
+  output logic [DWIDTH-1:0] s_axi_rdata,
+  output logic [       1:0] s_axi_rresp,
+  output logic              s_axi_rlast,
+  output logic              s_axi_rvalid,
+  input  logic              s_axi_rready
+);
+
+  localparam DEBUG = 0;
+
+  //---------------------------------------------------------------------------
+  // Data Types
+  //---------------------------------------------------------------------------
+  
+  typedef enum logic [1:0] { FIXED, INCR, WRAP }            burst_t;
+  typedef enum logic [1:0] { OKAY, EXOKAY, SLVERR, DECERR } resp_t;
+
+  typedef struct packed {
+    longint             count;  // Number of requests to wait for before executing
+    logic [IDWIDTH-1:0] id;
+    logic [AWIDTH-1:0]  addr;
+    logic [8:0]         len;    // Add an extra bit, since actual true length is +1
+    logic [7:0]         size;   // Add extra bits to store size in bytes, instead of clog2(size)
+    burst_t             burst;
+  } req_t;
+
+  // Make the address type an extra bit wide so that we can detect 
+  // out-of-bounds accesses easily.
+  typedef bit [AWIDTH:0] addr_t;
+
+  // Data word type
+  typedef logic [DWIDTH-1:0] data_t;
+
+  // Mask to indicate which bits should be written.
+  typedef bit [DWIDTH/8-1:0] mask_t;
+
+
+  //---------------------------------------------------------------------------
+  // Data Structures
+  //---------------------------------------------------------------------------
+
+  byte             memory [addr_t];     // Byte addressable memory
+  mailbox #(req_t) read_req   = new();  // Read request queue
+  mailbox #(req_t) write_req  = new();  // Write request queue
+  mailbox #(req_t) write_resp = new();  // Write response queue
+
+  longint req_count;    // Number of requests received
+  longint compl_count;  // Number of requests completed
+
+
+  //---------------------------------------------------------------------------
+  // External Configuration Interface
+  //---------------------------------------------------------------------------
+
+  int waddr_stall_prob = STALL_PROB;
+  int wdata_stall_prob = STALL_PROB;
+  int wresp_stall_prob = STALL_PROB;
+  int raddr_stall_prob = STALL_PROB;
+  int rdata_stall_prob = STALL_PROB;
+
+  // Set ALL stall probabilities to the same value
+  function void set_stall_prob(int probability);
+    assert(probability >= 0 && probability <= 100) else begin
+      $error("Probability must be from 0 to 100");
+    end
+    waddr_stall_prob = probability;
+    wdata_stall_prob = probability;
+    wresp_stall_prob = probability;
+    raddr_stall_prob = probability;
+    rdata_stall_prob = probability;
+  endfunction : set_stall_prob
+
+  // Set WRITE stall probabilities to the same value
+  function void set_write_stall_prob(int probability);
+    assert(probability >= 0 && probability <= 100) else begin
+      $error("Probability must be from 0 to 100");
+    end
+    waddr_stall_prob = probability;
+    wdata_stall_prob = probability;
+    wresp_stall_prob = probability;
+  endfunction : set_write_stall_prob
+
+  // Set READ stall probabilities to the same value
+  function void set_read_stall_prob(int probability);
+    assert(probability >= 0 && probability <= 100) else begin
+      $error("Probability must be from 0 to 100");
+    end
+    raddr_stall_prob = probability;
+    rdata_stall_prob = probability;
+  endfunction : set_read_stall_prob
+
+  // Set Write Address Channel stall probability  
+  function void set_waddr_stall_prob(int probability);
+    assert(probability >= 0 && probability <= 100) else begin
+      $error("Probability must be from 0 to 100");
+    end
+    waddr_stall_prob = probability;
+  endfunction : set_waddr_stall_prob
+
+  // Set Write Data Channel stall probability
+  function void set_wdata_stall_prob(int probability);
+    assert(probability >= 0 && probability <= 100) else begin
+      $error("Probability must be from 0 to 100");
+    end
+    wdata_stall_prob = probability;
+  endfunction : set_wdata_stall_prob
+
+  // Set Write Response Channel stall probability
+  function void set_wresp_stall_prob(int probability);
+    assert(probability >= 0 && probability <= 100) else begin
+      $error("Probability must be from 0 to 100");
+    end
+    wresp_stall_prob = probability;
+  endfunction : set_wresp_stall_prob
+
+  // Set Read Address Channel stall probability
+  function void set_raddr_stall_prob(int probability);
+    assert(probability >= 0 && probability <= 100) else begin
+      $error("Probability must be from 0 to 100");
+    end
+    raddr_stall_prob = probability;
+  endfunction : set_raddr_stall_prob
+
+  // Set Read Data Channel stall probability
+  function void set_rdata_stall_prob(int probability);
+    assert(probability >= 0 && probability <= 100) else begin
+      $error("Probability must be from 0 to 100");
+    end
+    rdata_stall_prob = probability;
+  endfunction : set_rdata_stall_prob
+
+  // Get Write Address Channel stall probability  
+  function int get_waddr_stall_prob();
+    return waddr_stall_prob;
+  endfunction : get_waddr_stall_prob
+
+  // Get Write Data Channel stall probability
+  function int get_wdata_stall_prob();
+    return wdata_stall_prob;
+  endfunction : get_wdata_stall_prob
+
+  // Get Write Response Channel stall probability
+  function int get_wresp_stall_prob();
+    return wresp_stall_prob;
+  endfunction : get_wresp_stall_prob
+
+  // Get Read Address Channel stall probability
+  function int get_raddr_stall_prob();
+    return raddr_stall_prob;
+  endfunction : get_raddr_stall_prob
+
+  // Get Read Data Channel stall probability
+  function int get_rdata_stall_prob();
+    return rdata_stall_prob;
+  endfunction : get_rdata_stall_prob
+
+
+
+  //---------------------------------------------------------------------------
+  // Helper Functions
+  //---------------------------------------------------------------------------
+
+  function data_t read_mem(addr_t byte_addr, int num_bytes);
+    data_t data;
+    addr_t incr;
+
+    if (BIG_ENDIAN) begin
+      byte_addr = byte_addr + num_bytes-1;
+      incr      = -1;
+    end else begin
+      incr      = 1;
+    end
+
+    for (int i = 0; i < num_bytes; i++) begin
+      if (byte_addr >= 2**AWIDTH) begin
+        $fatal(1, "Read extends beyond memory range");
+      end
+      if (memory.exists(byte_addr)) data[i*8 +: 8] = memory[byte_addr];
+      else data[i*8 +: 8] = 'X;
+      byte_addr += incr;
+    end
+
+    return data;
+  endfunction : read_mem
+
+
+  function void write_mem(addr_t byte_addr, int num_bytes, data_t data, mask_t mask);
+    addr_t incr;
+
+    if (BIG_ENDIAN) begin
+      byte_addr = byte_addr + num_bytes-1;
+      incr      = -1;
+    end else begin
+      incr      = 1;
+    end
+
+    for (int i = 0; i < num_bytes; i++) begin
+      if (mask[i]) begin
+        if (byte_addr >= 2**AWIDTH) begin
+          $fatal(1, "Write extends beyond memory range");
+        end
+        memory[byte_addr] = data[i*8 +: 8];
+      end
+      byte_addr += incr;
+    end
+  endfunction : write_mem
+
+
+  //---------------------------------------------------------------------------
+  // Write Requests
+  //---------------------------------------------------------------------------
+
+  initial begin : write_req_proc
+    req_t   req;
+    burst_t burst;
+
+    s_axi_awready <= 0;
+
+    forever begin
+      @(posedge s_aclk);
+      if (!s_aresetn) continue;
+
+      if (s_axi_awvalid) begin
+        if (s_axi_awready) begin
+          req.count = req_count;
+          req.id    = s_axi_awid;
+          req.addr  = s_axi_awaddr;
+          req.len   = s_axi_awlen + 1;    // Per AXI4 spec, Burst_length = AxLEN[7:0] + 1
+          req.size  = 2**s_axi_awsize;    // Store as true size in bytes, not clog2(size)
+          req.burst = burst_t'(s_axi_awburst);
+
+          // Check that the request is valid
+          assert (!$isunknown(req)) else begin
+            $fatal(1, "Write request signals are unknown");
+          end
+          assert (s_axi_araddr % (DWIDTH/8) == 0) else begin
+            $warning("Unaligned memory write");
+          end
+          assert (2**s_axi_awsize <= DWIDTH/8) else begin
+            $fatal(1, "AWSIZE must not be larger than DWIDTH");
+          end
+          assert ($cast(burst, s_axi_awburst)) else begin
+            $fatal(1, "Invalid AWBURST value");
+          end
+
+          if (DEBUG) begin
+            $display("WRITE REQ: id=%X, addr=%X, len=%X, size=%X, burst=%s, %t, %m", 
+              req.id, req.addr, req.len, req.size, req.burst.name, $realtime);
+          end
+
+          req_count++;
+          write_req.put(req);
+        end
+
+        // Randomly deassert ready
+        s_axi_awready <= $urandom_range(99) < waddr_stall_prob ? 0 : 1;
+      end
+    end
+  end : write_req_proc
+
+
+  //---------------------------------------------------------------------------
+  // Read Requests
+  //---------------------------------------------------------------------------
+
+  initial begin : read_req_proc
+    req_t   req;
+    burst_t burst;
+
+    s_axi_arready <= 0;
+
+    forever begin
+      @(posedge s_aclk);
+      if (!s_aresetn) continue;
+
+      if (s_axi_arvalid) begin
+        if (s_axi_arready) begin
+          req.count = req_count;
+          req.id    = s_axi_arid;
+          req.addr  = s_axi_araddr;
+          req.len   = s_axi_arlen + 1;    // Per AXI4 spec, Burst_length = AxLEN[7:0] + 1
+          req.size  = 2**s_axi_arsize;    // Store as true size in bytes, not clog2(size)
+          req.burst = burst_t'(s_axi_arburst);
+
+          // Check that the request is valid
+          assert(!$isunknown(req)) else begin
+            $fatal(1, "Read request signals are unknown");
+          end
+          assert(s_axi_araddr % (DWIDTH/8) == 0) else begin
+            $warning("Unaligned memory read");
+          end
+          assert(2**s_axi_arsize <= DWIDTH/8) else begin
+            $fatal(1, "ARSIZE must not be larger than DWIDTH");
+          end
+          assert ($cast(burst, s_axi_awburst)) else begin
+            $fatal(1, "Invalid ARBURST value");
+          end
+
+          if (DEBUG) begin
+            $display("READ REQ:  id=%X, addr=%X, len=%X, size=%X, burst=%s, %t, %m", 
+              req.id, req.addr, req.len, req.size, req.burst.name, $realtime);
+          end
+
+          req_count++;
+          read_req.put(req);
+        end
+
+        // Randomly deassert ready to cause a stall
+        s_axi_arready <= $urandom_range(99) < raddr_stall_prob ? 0 : 1;
+      end
+    end
+  end : read_req_proc
+
+
+  //---------------------------------------------------------------------------
+  // Write Data
+  //---------------------------------------------------------------------------
+
+  initial begin : write_data_proc
+    req_t req;
+    bit [AWIDTH-1:0] addr;
+
+    forever begin
+      // Wait for the next write request
+      s_axi_wready <= 0;
+      write_req.get(req);
+
+      // Wait for previous requests to complete
+      while (compl_count < req.count) begin
+        @(posedge s_aclk);
+        if (!s_aresetn) break;
+      end
+
+      // If reset was asserted, clear the request queue and start over
+      if (!s_aresetn) begin
+        while(write_req.try_get(req));
+        continue;
+      end
+
+      // Iterate over the number of words in the request
+      for (int i = 0; i < req.len; ) begin
+        @(posedge s_aclk);
+        if (!s_aresetn) break;
+
+        // Check if we have a new data word
+        if (s_axi_wvalid) begin
+          if (s_axi_wready) begin
+            // Check the inputs
+            if ($isunknown(s_axi_wstrb)) begin
+              $fatal(1, "WSTRB is unknown");
+            end
+            if ($isunknown(s_axi_wdata)) begin
+              $warning(1, "WDATA is unknown; data will be changed to zero");
+            end
+
+            case (req.burst)
+              FIXED : begin
+                addr = req.addr;
+              end
+              INCR : begin
+                // If the address rolls over, we've reached the end of the 
+                // memory and we should stop here.
+                addr = req.addr + i*req.size;
+                if (addr < req.addr) break;
+              end
+              WRAP : begin
+                // Allow roll-over
+                addr = req.addr + i*req.size;
+              end
+            endcase
+
+            write_mem(addr, req.size, s_axi_wdata, s_axi_wstrb);
+
+            if (DEBUG) begin
+              $display("WRITE: count=%3X, ADDR=%X, DATA=%X, SIZE=%X, STRB=%X, %t, %m", 
+                i, addr, s_axi_wdata, req.size, s_axi_wstrb, $realtime);
+            end
+
+            i++;
+          end
+
+          // Randomly deassert ready to cause a stall
+          s_axi_wready <= $urandom_range(99) < wdata_stall_prob ? 0 : 1;
+        end
+      end // for
+
+      // If reset was asserted, clear the request queue and start over
+      if (!s_aresetn) begin
+        while(write_req.try_get(req));
+        continue;
+      end
+
+      compl_count++;
+
+      // Enqueue write response
+      write_resp.put(req);
+
+      // Make sure WLAST asserted for the last word. If not we report an error. 
+      // Per the AXI4 standard, "a slave is not required to use the WLAST 
+      // signal" because "a slave can calculate the last write data transfer 
+      // from the burst length AWLEN".
+      if (s_axi_wlast != 1'b1) begin
+        $error("WLAST not asserted on last word of burst");
+      end
+
+    end // forever
+  end : write_data_proc
+
+
+  //---------------------------------------------------------------------------
+  // Write Response
+  //---------------------------------------------------------------------------
+
+  initial begin : write_resp_proc
+    req_t resp;
+    bit [AWIDTH-1:0] addr;
+
+    forever begin
+      s_axi_bid    <= 'X;
+      s_axi_bresp  <= 'X;
+      s_axi_bvalid <= 0;
+
+      // Wait for the next write response
+      write_resp.get(resp);
+      @(posedge s_aclk);
+
+      // If there's a reset, clear the response queue and start over
+      if (!s_aresetn) begin
+        while(write_resp.try_get(resp));
+        continue;
+      end
+
+      // Randomly keep bvalid deasserted for next word to cause a stall
+      if ($urandom_range(99) < wresp_stall_prob) begin
+        do begin
+          @(posedge s_aclk);
+          if (!s_aresetn) break;
+        end while ($urandom_range(99) < wresp_stall_prob);
+
+        // If reset was asserted, clear the response queue and start over
+        if (!s_aresetn) begin
+          while(write_resp.try_get(resp));
+          continue;
+        end
+      end
+
+      // Output the next response
+      s_axi_bid    <= resp.id;
+      s_axi_bresp  <= OKAY;
+      s_axi_bvalid <= 1;
+
+      if (DEBUG) begin
+        $display("WRITE RESP: ID=%X, %t, %m", resp.id, $realtime);
+      end
+
+      // Wait for the response to be accepted
+      do begin
+        @(posedge s_aclk);
+        if (!s_aresetn) break;
+      end while (!s_axi_bready);
+
+      // Output the next response
+      s_axi_bid    <= 'X;
+      s_axi_bresp  <= 'X;
+      s_axi_bvalid <= 0;
+
+      // If reset was asserted, clear the response queue and start over
+      if (!s_aresetn) begin
+        while(write_resp.try_get(resp));
+        continue;
+      end
+    end // forever
+  end : write_resp_proc
+
+
+  //---------------------------------------------------------------------------
+  // Read Data
+  //---------------------------------------------------------------------------
+
+  initial begin : read_data_proc
+    req_t req;
+    bit   [AWIDTH-1:0] addr;
+    logic [DWIDTH-1:0] data;
+
+    forever begin
+      s_axi_rid    <= 'X;
+      s_axi_rdata  <= 'X;
+      s_axi_rresp  <= 'X;
+      s_axi_rlast  <= 'X;
+      s_axi_rvalid <= 0;
+
+      // Wait for the next read request
+      read_req.get(req);
+
+      // Wait for previous requests to complete
+      do begin
+        @(posedge s_aclk);
+        if (!s_aresetn) break;
+      end while (compl_count < req.count);
+
+      // If reset was asserted, clear the request queue and start over
+      if (!s_aresetn) begin
+        while(read_req.try_get(req));
+        continue;
+      end
+
+      for (int i = 0; i < req.len; i++) begin
+        // Randomly keep rvalid deasserted for next word to cause a stall
+        if ($urandom_range(99) < rdata_stall_prob) begin
+          do begin
+            @(posedge s_aclk);
+            if (!s_aresetn) break;
+          end while ($urandom_range(99) < rdata_stall_prob);
+          if (!s_aresetn) break;
+        end
+
+        case (req.burst)
+          FIXED : begin
+            addr = req.addr;
+          end
+          INCR : begin
+            // If the address rolls over, we've reached the end of the memory 
+            // and we should stop here.
+            addr = req.addr + i*req.size;
+            if (addr < req.addr) break;
+          end
+          WRAP : begin
+            // Allow roll-over
+            addr = req.addr + i*req.size;
+          end
+        endcase
+
+        // Read the memory
+        data = read_mem(addr, req.size);
+
+        // Output the next word
+        s_axi_rid    <= req.id;
+        s_axi_rdata  <= data;
+        s_axi_rresp  <= OKAY;
+        s_axi_rlast  <= (i == req.len-1);
+        s_axi_rvalid <= 1;
+
+        if (DEBUG) begin
+          $display("READ:  count=%3X, ADDR=%X, DATA=%X, SIZE=%X, %t, %m", i, addr, data, req.size, $realtime);
+        end
+
+        // Wait for the word to be captured
+        do begin
+          @(posedge s_aclk);
+          if (!s_aresetn) break;
+        end while (!s_axi_rready);
+
+        s_axi_rid    <= 'X;
+        s_axi_rdata  <= 'X;
+        s_axi_rresp  <= 'X;
+        s_axi_rlast  <= 'X;
+        s_axi_rvalid <= 0;
+      end // for
+
+      // If reset was asserted, clear the request queue and start over
+      if (!s_aresetn) begin
+        while(read_req.try_get(req));
+      end
+
+      compl_count++;
+
+    end // forever
+  end : read_data_proc
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/Makefile b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/Makefile
new file mode 100644
index 000000000..d574c9a01
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/Makefile
@@ -0,0 +1,68 @@
+#
+# Copyright 2019 Ettus Research, A National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+#-------------------------------------------------
+# Top-of-Makefile
+#-------------------------------------------------
+# Define BASE_DIR to point to the "top" dir
+BASE_DIR = $(abspath ../../../../top)
+# Include viv_sim_preamble after defining BASE_DIR
+include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
+
+#-------------------------------------------------
+# IP Specific
+#-------------------------------------------------
+# If simulation contains IP, define the IP_DIR and point
+# it to the base level IP directory
+LIB_IP_DIR = $(BASE_DIR)/../lib/ip
+
+# Include makefiles and sources for all IP components
+# *after* defining the LIB_IP_DIR
+#include $(LIB_IP_DIR)/axi_fft/Makefile.inc
+#include $(LIB_IP_DIR)/complex_to_magphase/Makefile.inc
+include $(LIB_IP_DIR)/complex_multiplier_dds/Makefile.inc
+include $(LIB_IP_DIR)/dds_sin_cos_lut_only/Makefile.inc
+include $(BASE_DIR)/x300/coregen_dsp/Makefile.srcs
+
+DESIGN_SRCS += $(abspath \
+$(LIB_IP_COMPLEX_MULTIPLIER_DDS_SRCS) \
+$(LIB_IP_DDS_SIN_COS_LUT_ONLY_SRCS) \
+$(COREGEN_DSP_SRCS) \
+)
+
+#-------------------------------------------------
+# Design Specific
+#-------------------------------------------------
+# Include makefiles and sources for the DUT and its dependencies
+include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs
+include $(BASE_DIR)/../lib/rfnoc/utils/Makefile.srcs
+include Makefile.srcs
+
+DESIGN_SRCS += $(abspath \
+$(RFNOC_CORE_SRCS) \
+$(RFNOC_UTIL_SRCS) \
+$(RFNOC_BLOCK_DDC_SRCS) \
+)
+
+#-------------------------------------------------
+# Testbench Specific
+#-------------------------------------------------
+# Define only one toplevel module
+SIM_TOP = rfnoc_block_ddc_tb
+
+# Add test bench, user design under test, and
+# additional user created files
+SIM_SRCS = \
+$(COREGEN_DSP_SRCS) \
+$(abspath rfnoc_block_ddc_tb.sv)
+
+#-------------------------------------------------
+# Bottom-of-Makefile
+#-------------------------------------------------
+# Include all simulator specific makefiles here
+# Each should define a unique target to simulate
+# e.g. xsim, vsim, etc and a common "clean" target
+include $(BASE_DIR)/../tools/make/viv_simulator.mak
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/Makefile.srcs b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/Makefile.srcs
new file mode 100644
index 000000000..28663f03c
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/Makefile.srcs
@@ -0,0 +1,11 @@
+#
+# Copyright 2019 Ettus Research, A National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+RFNOC_BLOCK_DDC_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/rfnoc/blocks/rfnoc_block_ddc/, \
+noc_shell_ddc.v \
+rfnoc_block_ddc_regs.vh \
+rfnoc_block_ddc.v \
+))
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/noc_shell_ddc.v b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/noc_shell_ddc.v
new file mode 100644
index 000000000..56a13ee0a
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/noc_shell_ddc.v
@@ -0,0 +1,291 @@
+//
+// Copyright 2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: noc_shell_ddc
+//
+// Description: A NoC Shell for RFNoC. This should eventually be replaced 
+// by an auto-generated NoC Shell.
+//
+
+module noc_shell_ddc #(
+  parameter [31:0] NOC_ID          = 32'h0,
+  parameter [ 9:0] THIS_PORTID     = 10'd0,
+  parameter        CHDR_W          = 64,
+  parameter [ 0:0] CTRLPORT_SLV_EN = 1,
+  parameter [ 0:0] CTRLPORT_MST_EN = 1,
+  parameter [ 5:0] CTRL_FIFO_SIZE  = 6,
+  parameter [ 5:0] NUM_DATA_I      = 1,
+  parameter [ 5:0] NUM_DATA_O      = 1,
+  parameter        ITEM_W          = 32,
+  parameter        NIPC            = 2,
+  parameter        PYLD_FIFO_SIZE  = 10,
+  parameter        MTU             = 10
+)(
+  //---------------------------------------------------------------------------
+  // Framework Interface
+  //---------------------------------------------------------------------------
+
+  // RFNoC Framework Clocks and Resets
+  input  wire                           rfnoc_chdr_clk,
+  output wire                           rfnoc_chdr_rst,
+  input  wire                           rfnoc_ctrl_clk,
+  output wire                           rfnoc_ctrl_rst,
+  // RFNoC Backend Interface
+  input  wire [                  511:0] rfnoc_core_config,
+  output wire [                  511:0] rfnoc_core_status,
+  // CHDR Input Ports (from framework)
+  input  wire [(CHDR_W*NUM_DATA_I)-1:0] s_rfnoc_chdr_tdata,
+  input  wire [         NUM_DATA_I-1:0] s_rfnoc_chdr_tlast,
+  input  wire [         NUM_DATA_I-1:0] s_rfnoc_chdr_tvalid,
+  output wire [         NUM_DATA_I-1:0] s_rfnoc_chdr_tready,
+  // CHDR Output Ports (to framework)
+  output wire [(CHDR_W*NUM_DATA_O)-1:0] m_rfnoc_chdr_tdata,
+  output wire [         NUM_DATA_O-1:0] m_rfnoc_chdr_tlast,
+  output wire [         NUM_DATA_O-1:0] m_rfnoc_chdr_tvalid,
+  input  wire [         NUM_DATA_O-1:0] m_rfnoc_chdr_tready,
+  // AXIS-Ctrl Input Port (from framework)
+  input  wire [                   31:0] s_rfnoc_ctrl_tdata,
+  input  wire                           s_rfnoc_ctrl_tlast,
+  input  wire                           s_rfnoc_ctrl_tvalid,
+  output wire                           s_rfnoc_ctrl_tready,
+  // AXIS-Ctrl Output Port (to framework)
+  output wire [                   31:0] m_rfnoc_ctrl_tdata,
+  output wire                           m_rfnoc_ctrl_tlast,
+  output wire                           m_rfnoc_ctrl_tvalid,
+  input  wire                           m_rfnoc_ctrl_tready,
+
+  //---------------------------------------------------------------------------
+  // Client Control Port Interface
+  //---------------------------------------------------------------------------
+
+  // Clock
+  input  wire        ctrlport_clk,
+  input  wire        ctrlport_rst,
+  // Master
+  output wire        m_ctrlport_req_wr,
+  output wire        m_ctrlport_req_rd,
+  output wire [19:0] m_ctrlport_req_addr,
+  output wire [31:0] m_ctrlport_req_data,
+  output wire [ 3:0] m_ctrlport_req_byte_en,
+  output wire        m_ctrlport_req_has_time,
+  output wire [63:0] m_ctrlport_req_time,
+  input  wire        m_ctrlport_resp_ack,
+  input  wire [ 1:0] m_ctrlport_resp_status,
+  input  wire [31:0] m_ctrlport_resp_data,
+  // Slave
+  input  wire        s_ctrlport_req_wr,
+  input  wire        s_ctrlport_req_rd,
+  input  wire [19:0] s_ctrlport_req_addr,
+  input  wire [ 9:0] s_ctrlport_req_portid,
+  input  wire [15:0] s_ctrlport_req_rem_epid,
+  input  wire [ 9:0] s_ctrlport_req_rem_portid,
+  input  wire [31:0] s_ctrlport_req_data,
+  input  wire [ 3:0] s_ctrlport_req_byte_en,
+  input  wire        s_ctrlport_req_has_time,
+  input  wire [63:0] s_ctrlport_req_time,
+  output wire        s_ctrlport_resp_ack,
+  output wire [ 1:0] s_ctrlport_resp_status,
+  output wire [31:0] s_ctrlport_resp_data,
+
+  //---------------------------------------------------------------------------
+  // Client Data Interface
+  //---------------------------------------------------------------------------
+
+  // Clock
+  input  wire                                axis_data_clk,
+  input  wire                                axis_data_rst,
+
+  // Output data stream (to user logic)
+  output wire [(NUM_DATA_I*ITEM_W*NIPC)-1:0] m_axis_tdata,
+  output wire [       (NUM_DATA_I*NIPC)-1:0] m_axis_tkeep,
+  output wire [              NUM_DATA_I-1:0] m_axis_tlast,
+  output wire [              NUM_DATA_I-1:0] m_axis_tvalid,
+  input  wire [              NUM_DATA_I-1:0] m_axis_tready,
+  // Sideband information
+  output wire [         (NUM_DATA_I*64)-1:0] m_axis_ttimestamp,
+  output wire [              NUM_DATA_I-1:0] m_axis_thas_time,
+  output wire [         (NUM_DATA_I*16)-1:0] m_axis_tlength,
+  output wire [              NUM_DATA_I-1:0] m_axis_teov,
+  output wire [              NUM_DATA_I-1:0] m_axis_teob,
+
+  // Input data stream (from user logic)
+  input  wire [(NUM_DATA_O*ITEM_W*NIPC)-1:0] s_axis_tdata,
+  input  wire [       (NUM_DATA_O*NIPC)-1:0] s_axis_tkeep,
+  input  wire [              NUM_DATA_O-1:0] s_axis_tlast,
+  input  wire [              NUM_DATA_O-1:0] s_axis_tvalid,
+  output wire [              NUM_DATA_O-1:0] s_axis_tready,
+  // Sideband info (sampled on the first cycle of the packet)
+  input  wire [         (NUM_DATA_O*64)-1:0] s_axis_ttimestamp,
+  input  wire [              NUM_DATA_O-1:0] s_axis_thas_time,
+  input  wire [              NUM_DATA_O-1:0] s_axis_teov,
+  input  wire [              NUM_DATA_O-1:0] s_axis_teob
+);
+  
+  localparam SNK_INFO_FIFO_SIZE = 4;
+  localparam SNK_PYLD_FIFO_SIZE = PYLD_FIFO_SIZE;
+  localparam SRC_INFO_FIFO_SIZE = 4;
+  localparam SRC_PYLD_FIFO_SIZE = (MTU > PYLD_FIFO_SIZE) ? MTU : PYLD_FIFO_SIZE;
+
+  //---------------------------------------------------------------------------
+  //  Backend Interface
+  //---------------------------------------------------------------------------
+
+  wire         data_i_flush_en;
+  wire [31:0]  data_i_flush_timeout;
+  wire [63:0]  data_i_flush_active;
+  wire [63:0]  data_i_flush_done;
+  wire         data_o_flush_en;
+  wire [31:0]  data_o_flush_timeout;
+  wire [63:0]  data_o_flush_active;
+  wire [63:0]  data_o_flush_done;
+
+  backend_iface #(
+    .NOC_ID        (NOC_ID),
+    .NUM_DATA_I    (NUM_DATA_I),
+    .NUM_DATA_O    (NUM_DATA_O),
+    .CTRL_FIFOSIZE (CTRL_FIFO_SIZE),
+    .MTU           (MTU)
+  ) backend_iface_i (
+    .rfnoc_chdr_clk       (rfnoc_chdr_clk),
+    .rfnoc_ctrl_clk       (rfnoc_ctrl_clk),
+    .rfnoc_core_config    (rfnoc_core_config),
+    .rfnoc_core_status    (rfnoc_core_status),
+    .rfnoc_chdr_rst       (rfnoc_chdr_rst),
+    .rfnoc_ctrl_rst       (rfnoc_ctrl_rst),
+    .data_i_flush_en      (data_i_flush_en),
+    .data_i_flush_timeout (data_i_flush_timeout),
+    .data_i_flush_active  (data_i_flush_active),
+    .data_i_flush_done    (data_i_flush_done),
+    .data_o_flush_en      (data_o_flush_en),
+    .data_o_flush_timeout (data_o_flush_timeout),
+    .data_o_flush_active  (data_o_flush_active),
+    .data_o_flush_done    (data_o_flush_done)
+  );
+
+  //---------------------------------------------------------------------------
+  //  Control Path
+  //---------------------------------------------------------------------------
+
+  ctrlport_endpoint #(
+    .THIS_PORTID              (THIS_PORTID    ),
+    .SYNC_CLKS                (0              ),
+    .AXIS_CTRL_MST_EN         (CTRLPORT_SLV_EN),
+    .AXIS_CTRL_SLV_EN         (CTRLPORT_MST_EN),
+    .SLAVE_FIFO_SIZE          (CTRL_FIFO_SIZE )
+  ) ctrlport_ep_i (
+    .rfnoc_ctrl_clk           (rfnoc_ctrl_clk           ),
+    .rfnoc_ctrl_rst           (rfnoc_ctrl_rst           ),
+    .ctrlport_clk             (ctrlport_clk             ),
+    .ctrlport_rst             (ctrlport_rst             ),
+    .s_rfnoc_ctrl_tdata       (s_rfnoc_ctrl_tdata       ),
+    .s_rfnoc_ctrl_tlast       (s_rfnoc_ctrl_tlast       ),
+    .s_rfnoc_ctrl_tvalid      (s_rfnoc_ctrl_tvalid      ),
+    .s_rfnoc_ctrl_tready      (s_rfnoc_ctrl_tready      ),
+    .m_rfnoc_ctrl_tdata       (m_rfnoc_ctrl_tdata       ),
+    .m_rfnoc_ctrl_tlast       (m_rfnoc_ctrl_tlast       ),
+    .m_rfnoc_ctrl_tvalid      (m_rfnoc_ctrl_tvalid      ),
+    .m_rfnoc_ctrl_tready      (m_rfnoc_ctrl_tready      ),
+    .m_ctrlport_req_wr        (m_ctrlport_req_wr        ),
+    .m_ctrlport_req_rd        (m_ctrlport_req_rd        ),
+    .m_ctrlport_req_addr      (m_ctrlport_req_addr      ),
+    .m_ctrlport_req_data      (m_ctrlport_req_data      ),
+    .m_ctrlport_req_byte_en   (m_ctrlport_req_byte_en   ),
+    .m_ctrlport_req_has_time  (m_ctrlport_req_has_time  ),
+    .m_ctrlport_req_time      (m_ctrlport_req_time      ),
+    .m_ctrlport_resp_ack      (m_ctrlport_resp_ack      ),
+    .m_ctrlport_resp_status   (m_ctrlport_resp_status   ),
+    .m_ctrlport_resp_data     (m_ctrlport_resp_data     ),
+    .s_ctrlport_req_wr        (s_ctrlport_req_wr        ),
+    .s_ctrlport_req_rd        (s_ctrlport_req_rd        ),
+    .s_ctrlport_req_addr      (s_ctrlport_req_addr      ),
+    .s_ctrlport_req_portid    (s_ctrlport_req_portid    ),
+    .s_ctrlport_req_rem_epid  (s_ctrlport_req_rem_epid  ),
+    .s_ctrlport_req_rem_portid(s_ctrlport_req_rem_portid),
+    .s_ctrlport_req_data      (s_ctrlport_req_data      ),
+    .s_ctrlport_req_byte_en   (s_ctrlport_req_byte_en   ),
+    .s_ctrlport_req_has_time  (s_ctrlport_req_has_time  ),
+    .s_ctrlport_req_time      (s_ctrlport_req_time      ),
+    .s_ctrlport_resp_ack      (s_ctrlport_resp_ack      ),
+    .s_ctrlport_resp_status   (s_ctrlport_resp_status   ),
+    .s_ctrlport_resp_data     (s_ctrlport_resp_data     )
+  );
+
+  //---------------------------------------------------------------------------
+  //  Data Path
+  //---------------------------------------------------------------------------
+
+  genvar i;
+  generate
+
+    for (i = 0; i < NUM_DATA_I; i = i + 1) begin: chdr_to_data
+      chdr_to_axis_data #(
+        .CHDR_W         (CHDR_W),
+        .ITEM_W         (ITEM_W),
+        .NIPC           (NIPC),
+        .SYNC_CLKS      (0),
+        .INFO_FIFO_SIZE (SNK_INFO_FIFO_SIZE),
+        .PYLD_FIFO_SIZE (SNK_PYLD_FIFO_SIZE)
+      ) chdr_to_axis_data_i (
+        .axis_chdr_clk      (rfnoc_chdr_clk),
+        .axis_chdr_rst      (rfnoc_chdr_rst),
+        .axis_data_clk      (axis_data_clk),
+        .axis_data_rst      (axis_data_rst),
+        .s_axis_chdr_tdata  (s_rfnoc_chdr_tdata  [(i*CHDR_W)+:CHDR_W]),
+        .s_axis_chdr_tlast  (s_rfnoc_chdr_tlast  [i]),
+        .s_axis_chdr_tvalid (s_rfnoc_chdr_tvalid [i]),
+        .s_axis_chdr_tready (s_rfnoc_chdr_tready [i]),
+        .m_axis_tdata       (m_axis_tdata  [i*ITEM_W*NIPC +: ITEM_W*NIPC]),
+        .m_axis_tkeep       (m_axis_tkeep  [i*NIPC +: NIPC]),
+        .m_axis_tlast       (m_axis_tlast  [i]),
+        .m_axis_tvalid      (m_axis_tvalid [i]),
+        .m_axis_tready      (m_axis_tready [i]),
+        .m_axis_ttimestamp  (m_axis_ttimestamp [i*64 +: 64]),
+        .m_axis_thas_time   (m_axis_thas_time  [i]),
+        .m_axis_tlength     (m_axis_tlength    [i*16 +: 16]),
+        .m_axis_teov        (m_axis_teov       [i]),
+        .m_axis_teob        (m_axis_teob       [i]),
+        .flush_en           (data_i_flush_en),
+        .flush_timeout      (data_i_flush_timeout),
+        .flush_active       (data_i_flush_active [i]),
+        .flush_done         (data_i_flush_done   [i])
+      );
+    end
+
+    for (i = 0; i < NUM_DATA_O; i = i + 1) begin: data_to_chdr
+      axis_data_to_chdr #(
+        .CHDR_W         (CHDR_W),
+        .ITEM_W         (ITEM_W),
+        .NIPC           (NIPC),
+        .SYNC_CLKS      (0),
+        .INFO_FIFO_SIZE (4),
+        .PYLD_FIFO_SIZE (SRC_INFO_FIFO_SIZE),
+        .MTU            (SRC_PYLD_FIFO_SIZE)
+      ) axis_data_to_chdr_i (
+        .axis_chdr_clk       (rfnoc_chdr_clk),
+        .axis_chdr_rst       (rfnoc_chdr_rst),
+        .axis_data_clk       (axis_data_clk),
+        .axis_data_rst       (axis_data_rst),
+        .m_axis_chdr_tdata   (m_rfnoc_chdr_tdata  [i*CHDR_W +: CHDR_W]),
+        .m_axis_chdr_tlast   (m_rfnoc_chdr_tlast  [i]),
+        .m_axis_chdr_tvalid  (m_rfnoc_chdr_tvalid [i]),
+        .m_axis_chdr_tready  (m_rfnoc_chdr_tready [i]),
+        .s_axis_tdata        (s_axis_tdata  [i*ITEM_W*NIPC +: ITEM_W*NIPC]),
+        .s_axis_tkeep        (s_axis_tkeep  [i*NIPC +: NIPC]),
+        .s_axis_tlast        (s_axis_tlast  [i]),
+        .s_axis_tvalid       (s_axis_tvalid [i]),
+        .s_axis_tready       (s_axis_tready [i]),
+        .s_axis_ttimestamp   (s_axis_ttimestamp [i*64 +: 64]),
+        .s_axis_thas_time    (s_axis_thas_time  [i]),
+        .s_axis_teov         (s_axis_teov       [i]),
+        .s_axis_teob         (s_axis_teob       [i]),
+        .flush_en            (data_o_flush_en),
+        .flush_timeout       (data_o_flush_timeout),
+        .flush_active        (data_o_flush_active [i]),
+        .flush_done          (data_o_flush_done   [i])
+      );
+    end
+  endgenerate
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/rfnoc_block_ddc.v b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/rfnoc_block_ddc.v
new file mode 100644
index 000000000..3162743b6
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/rfnoc_block_ddc.v
@@ -0,0 +1,420 @@
+//
+// Copyright 2019 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: rfnoc_block_ddc
+//
+// Description:  An digital down-converter block for RFNoC.
+//
+// Parameters:
+//
+//   THIS_PORTID    : Control crossbar port to which this block is connected
+//   CHDR_W         : AXIS CHDR interface data width
+//   NUM_PORTS      : Number of DDCs to instantiate
+//   MTU            : Maximum transmission unit (i.e., maximum packet size) in
+//                    CHDR words is 2**MTU.
+//   CTRL_FIFO_SIZE : Size of the Control Port slave FIFO. This affects the
+//                    number of outstanding commands that can be pending.
+//   NUM_HB         : Number of half-band decimation blocks to include (0-3)
+//   CIC_MAX_DECIM  : Maximum decimation to support in the CIC filter
+//
+
+module rfnoc_block_ddc #(
+  parameter THIS_PORTID    = 0,
+  parameter CHDR_W         = 64,
+  parameter NUM_PORTS      = 2,
+  parameter MTU            = 10,
+  parameter CTRL_FIFO_SIZE = 6,
+  parameter NUM_HB         = 3,
+  parameter CIC_MAX_DECIM  = 255
+) (
+  //---------------------------------------------------------------------------
+  // AXIS CHDR Port
+  //---------------------------------------------------------------------------
+
+  input wire rfnoc_chdr_clk,
+  input wire ce_clk,
+
+  // CHDR inputs from framework
+  input  wire [NUM_PORTS*CHDR_W-1:0] s_rfnoc_chdr_tdata,
+  input  wire [       NUM_PORTS-1:0] s_rfnoc_chdr_tlast,
+  input  wire [       NUM_PORTS-1:0] s_rfnoc_chdr_tvalid,
+  output wire [       NUM_PORTS-1:0] s_rfnoc_chdr_tready,
+
+  // CHDR outputs to framework
+  output wire [NUM_PORTS*CHDR_W-1:0] m_rfnoc_chdr_tdata,
+  output wire [       NUM_PORTS-1:0] m_rfnoc_chdr_tlast,
+  output wire [       NUM_PORTS-1:0] m_rfnoc_chdr_tvalid,
+  input  wire [       NUM_PORTS-1:0] m_rfnoc_chdr_tready,
+
+  // Backend interface
+  input  wire [511:0] rfnoc_core_config,
+  output wire [511:0] rfnoc_core_status,
+
+  //---------------------------------------------------------------------------
+  // AXIS CTRL Port
+  //---------------------------------------------------------------------------
+
+  input wire rfnoc_ctrl_clk,
+
+  // CTRL port requests from framework
+  input  wire [31:0] s_rfnoc_ctrl_tdata,
+  input  wire        s_rfnoc_ctrl_tlast,
+  input  wire        s_rfnoc_ctrl_tvalid,
+  output wire        s_rfnoc_ctrl_tready,
+
+  // CTRL port requests to framework
+  output wire [31:0] m_rfnoc_ctrl_tdata,
+  output wire        m_rfnoc_ctrl_tlast,
+  output wire        m_rfnoc_ctrl_tvalid,
+  input  wire        m_rfnoc_ctrl_tready
+);
+
+  // These are the only supported values for now
+  localparam ITEM_W = 32;
+  localparam NIPC   = 1;
+
+  localparam NOC_ID = 'hDDC0_0000;
+
+  localparam COMPAT_MAJOR  = 16'h0;
+  localparam COMPAT_MINOR  = 16'h0;
+
+  `include "rfnoc_block_ddc_regs.vh"
+  `include "../../core/rfnoc_axis_ctrl_utils.vh"
+
+
+  //---------------------------------------------------------------------------
+  // Signal Declarations
+  //---------------------------------------------------------------------------
+
+  wire rfnoc_chdr_rst;
+
+  wire        ctrlport_req_wr;
+  wire        ctrlport_req_rd;
+  wire [19:0] ctrlport_req_addr;
+  wire [31:0] ctrlport_req_data;
+  wire        ctrlport_req_has_time;
+  wire [63:0] ctrlport_req_time;
+  wire        ctrlport_resp_ack;
+  wire [31:0] ctrlport_resp_data;
+
+  wire [NUM_PORTS*ITEM_W-1:0] m_axis_data_tdata;
+  wire [       NUM_PORTS-1:0] m_axis_data_tlast;
+  wire [       NUM_PORTS-1:0] m_axis_data_tvalid;
+  wire [       NUM_PORTS-1:0] m_axis_data_tready;
+  wire [    NUM_PORTS*64-1:0] m_axis_data_ttimestamp;
+  wire [       NUM_PORTS-1:0] m_axis_data_thas_time;
+  wire [    16*NUM_PORTS-1:0] m_axis_data_tlength;
+  wire [       NUM_PORTS-1:0] m_axis_data_teob;
+  wire [   NUM_PORTS*128-1:0] m_axis_data_tuser;
+
+  wire [NUM_PORTS*ITEM_W-1:0] s_axis_data_tdata;
+  wire [       NUM_PORTS-1:0] s_axis_data_tlast;
+  wire [       NUM_PORTS-1:0] s_axis_data_tvalid;
+  wire [       NUM_PORTS-1:0] s_axis_data_tready;
+  wire [   NUM_PORTS*128-1:0] s_axis_data_tuser;
+  wire [       NUM_PORTS-1:0] s_axis_data_teob;
+  wire [    NUM_PORTS*64-1:0] s_axis_data_ttimestamp;
+  wire [       NUM_PORTS-1:0] s_axis_data_thas_time;
+
+  wire ddc_rst;
+
+  // Cross the CHDR reset to the ce_clk domain
+  synchronizer ddc_rst_sync_i (
+    .clk (ce_clk),
+    .rst (1'b0),
+    .in  (rfnoc_chdr_rst),
+    .out (ddc_rst)
+  );
+
+
+  //---------------------------------------------------------------------------
+  // NoC Shell
+  //---------------------------------------------------------------------------
+
+  noc_shell_ddc #(
+    .NOC_ID          (NOC_ID),
+    .THIS_PORTID     (THIS_PORTID),
+    .CHDR_W          (CHDR_W),
+    .CTRLPORT_SLV_EN (0),
+    .CTRLPORT_MST_EN (1),
+    .CTRL_FIFO_SIZE  (CTRL_FIFO_SIZE),
+    .NUM_DATA_I      (NUM_PORTS),
+    .NUM_DATA_O      (NUM_PORTS),
+    .ITEM_W          (ITEM_W),
+    .NIPC            (NIPC),
+    .PYLD_FIFO_SIZE  (MTU),
+    .MTU             (MTU)
+  ) noc_shell_ddc_i (
+    .rfnoc_chdr_clk            (rfnoc_chdr_clk),
+    .rfnoc_chdr_rst            (rfnoc_chdr_rst),
+    .rfnoc_ctrl_clk            (rfnoc_ctrl_clk),
+    .rfnoc_ctrl_rst            (),
+    .rfnoc_core_config         (rfnoc_core_config),
+    .rfnoc_core_status         (rfnoc_core_status),
+    .s_rfnoc_chdr_tdata        (s_rfnoc_chdr_tdata),
+    .s_rfnoc_chdr_tlast        (s_rfnoc_chdr_tlast),
+    .s_rfnoc_chdr_tvalid       (s_rfnoc_chdr_tvalid),
+    .s_rfnoc_chdr_tready       (s_rfnoc_chdr_tready),
+    .m_rfnoc_chdr_tdata        (m_rfnoc_chdr_tdata),
+    .m_rfnoc_chdr_tlast        (m_rfnoc_chdr_tlast),
+    .m_rfnoc_chdr_tvalid       (m_rfnoc_chdr_tvalid),
+    .m_rfnoc_chdr_tready       (m_rfnoc_chdr_tready),
+    .s_rfnoc_ctrl_tdata        (s_rfnoc_ctrl_tdata),
+    .s_rfnoc_ctrl_tlast        (s_rfnoc_ctrl_tlast),
+    .s_rfnoc_ctrl_tvalid       (s_rfnoc_ctrl_tvalid),
+    .s_rfnoc_ctrl_tready       (s_rfnoc_ctrl_tready),
+    .m_rfnoc_ctrl_tdata        (m_rfnoc_ctrl_tdata),
+    .m_rfnoc_ctrl_tlast        (m_rfnoc_ctrl_tlast),
+    .m_rfnoc_ctrl_tvalid       (m_rfnoc_ctrl_tvalid),
+    .m_rfnoc_ctrl_tready       (m_rfnoc_ctrl_tready),
+    .ctrlport_clk              (ce_clk),
+    .ctrlport_rst              (ddc_rst),
+    .m_ctrlport_req_wr         (ctrlport_req_wr),
+    .m_ctrlport_req_rd         (ctrlport_req_rd),
+    .m_ctrlport_req_addr       (ctrlport_req_addr),
+    .m_ctrlport_req_data       (ctrlport_req_data),
+    .m_ctrlport_req_byte_en    (),
+    .m_ctrlport_req_has_time   (ctrlport_req_has_time),
+    .m_ctrlport_req_time       (ctrlport_req_time),
+    .m_ctrlport_resp_ack       (ctrlport_resp_ack),
+    .m_ctrlport_resp_status    (AXIS_CTRL_STS_OKAY),
+    .m_ctrlport_resp_data      (ctrlport_resp_data),
+    .s_ctrlport_req_wr         (1'b0),
+    .s_ctrlport_req_rd         (1'b0),
+    .s_ctrlport_req_addr       (20'b0),
+    .s_ctrlport_req_portid     (10'b0),
+    .s_ctrlport_req_rem_epid   (16'b0),
+    .s_ctrlport_req_rem_portid (10'b0),
+    .s_ctrlport_req_data       (32'b0),
+    .s_ctrlport_req_byte_en    (4'b0),
+    .s_ctrlport_req_has_time   (1'b0),
+    .s_ctrlport_req_time       (64'b0),
+    .s_ctrlport_resp_ack       (),
+    .s_ctrlport_resp_status    (),
+    .s_ctrlport_resp_data      (),
+    .axis_data_clk             (ce_clk),
+    .axis_data_rst             (ddc_rst),
+    .m_axis_tdata              (m_axis_data_tdata),
+    .m_axis_tkeep              (),
+    .m_axis_tlast              (m_axis_data_tlast),
+    .m_axis_tvalid             (m_axis_data_tvalid),
+    .m_axis_tready             (m_axis_data_tready),
+    .m_axis_ttimestamp         (m_axis_data_ttimestamp),
+    .m_axis_thas_time          (m_axis_data_thas_time),
+    .m_axis_tlength            (m_axis_data_tlength),
+    .m_axis_teov               (),
+    .m_axis_teob               (m_axis_data_teob),
+    .s_axis_tdata              (s_axis_data_tdata),
+    .s_axis_tkeep              ({NUM_PORTS*NIPC{1'b1}}),
+    .s_axis_tlast              (s_axis_data_tlast),
+    .s_axis_tvalid             (s_axis_data_tvalid),
+    .s_axis_tready             (s_axis_data_tready),
+    .s_axis_ttimestamp         (s_axis_data_ttimestamp),
+    .s_axis_thas_time          (s_axis_data_thas_time),
+    .s_axis_teov               ({NUM_PORTS{1'b0}}),
+    .s_axis_teob               (s_axis_data_teob)
+  );
+
+
+  //---------------------------------------------------------------------------
+  // Register Translation
+  //---------------------------------------------------------------------------
+  //
+  // Each DDC block is allocated an address spaces. This block translates CTRL
+  // port transactions in that space to settings bus.
+  //
+  //---------------------------------------------------------------------------
+
+  wire [ 8*NUM_PORTS-1:0] set_addr;
+  wire [32*NUM_PORTS-1:0] set_data;
+  wire [   NUM_PORTS-1:0] set_has_time;
+  wire [   NUM_PORTS-1:0] set_stb;
+  wire [64*NUM_PORTS-1:0] set_time;
+  wire [ 8*NUM_PORTS-1:0] rb_addr;
+  reg  [64*NUM_PORTS-1:0] rb_data;
+  wire [   NUM_PORTS-1:0] rb_stb;
+
+  ctrlport_to_settings_bus # (
+    .NUM_PORTS (NUM_PORTS)
+  ) ctrlport_to_settings_bus_i (
+    .ctrlport_clk             (ce_clk),
+    .ctrlport_rst             (ddc_rst),
+    .s_ctrlport_req_wr        (ctrlport_req_wr),
+    .s_ctrlport_req_rd        (ctrlport_req_rd),
+    .s_ctrlport_req_addr      (ctrlport_req_addr),
+    .s_ctrlport_req_data      (ctrlport_req_data),
+    .s_ctrlport_req_has_time  (ctrlport_req_has_time),
+    .s_ctrlport_req_time      (ctrlport_req_time),
+    .s_ctrlport_resp_ack      (ctrlport_resp_ack),
+    .s_ctrlport_resp_data     (ctrlport_resp_data),
+    .set_data                 (set_data),
+    .set_addr                 (set_addr),
+    .set_stb                  (set_stb),
+    .set_time                 (set_time),
+    .set_has_time             (set_has_time),
+    .rb_stb                   (rb_stb),
+    .rb_addr                  (rb_addr),
+    .rb_data                  (rb_data));
+
+
+  //---------------------------------------------------------------------------
+  // DDC Implementation
+  //---------------------------------------------------------------------------
+
+  // Unused signals
+  wire [   NUM_PORTS-1:0] clear_tx_seqnum = 0;
+  wire [16*NUM_PORTS-1:0] src_sid         = 0;
+  wire [16*NUM_PORTS-1:0] next_dst_sid    = 0;
+
+  localparam MAX_N = CIC_MAX_DECIM * 2 << (NUM_HB-1);
+
+  genvar i;
+  generate
+    for (i = 0; i < NUM_PORTS; i = i + 1) begin : gen_ddc_chains
+      wire        set_stb_int      = set_stb[i];
+      wire [7:0]  set_addr_int     = set_addr[8*i+7:8*i];
+      wire [31:0] set_data_int     = set_data[32*i+31:32*i];
+      wire [63:0] set_time_int     = set_time[64*i+63:64*i];
+      wire        set_has_time_int = set_has_time[i];
+
+      // Build the expected tuser CHDR header
+      cvita_hdr_encoder cvita_hdr_encoder_i (
+        .pkt_type       (2'b0),
+        .eob            (m_axis_data_teob[i]),
+        .has_time       (m_axis_data_thas_time[i]),
+        .seqnum         (12'b0),
+        .payload_length (m_axis_data_tlength[16*i +: 16]),
+        .src_sid        (16'b0),
+        .dst_sid        (16'b0),
+        .vita_time      (m_axis_data_ttimestamp[64*i +: 64]),
+        .header         (m_axis_data_tuser[128*i+:128])
+      );
+
+      // Extract bit fields from outgoing tuser CHDR header
+      assign s_axis_data_teob[i]              = s_axis_data_tuser[128*i+124 +:  1];
+      assign s_axis_data_thas_time[i]         = s_axis_data_tuser[128*i+125 +:  1];
+      assign s_axis_data_ttimestamp[64*i+:64] = s_axis_data_tuser[128*i+  0 +: 64];
+
+      // TODO: Read-back register for number of FIR filter taps
+      always @(*) begin
+        case(rb_addr[8*i+7:8*i])
+          RB_COMPAT_NUM    : rb_data[64*i+63:64*i] <= {COMPAT_MAJOR, COMPAT_MINOR};
+          RB_NUM_HB        : rb_data[64*i+63:64*i] <= NUM_HB;
+          RB_CIC_MAX_DECIM : rb_data[64*i+63:64*i] <= CIC_MAX_DECIM;
+          default          : rb_data[64*i+63:64*i] <= 64'h0BADC0DE0BADC0DE;
+        endcase
+      end
+
+      ////////////////////////////////////////////////////////////
+      //
+      // Timed Commands
+      //
+      ////////////////////////////////////////////////////////////
+      wire [31:0]  m_axis_tagged_tdata;
+      wire         m_axis_tagged_tlast;
+      wire         m_axis_tagged_tvalid;
+      wire         m_axis_tagged_tready;
+      wire [127:0] m_axis_tagged_tuser;
+      wire         m_axis_tagged_tag;
+
+      wire         out_set_stb;
+      wire [7:0]   out_set_addr;
+      wire [31:0]  out_set_data;
+      wire         timed_set_stb;
+      wire [7:0]   timed_set_addr;
+      wire [31:0]  timed_set_data;
+
+      wire         timed_cmd_fifo_full;
+
+      axi_tag_time #(
+        .NUM_TAGS(1),
+        .SR_TAG_ADDRS(SR_FREQ_ADDR))
+      axi_tag_time (
+        .clk(ce_clk),
+        .reset(ddc_rst),
+        .clear(clear_tx_seqnum[i]),
+        .tick_rate(16'd1),
+        .timed_cmd_fifo_full(timed_cmd_fifo_full),
+        .s_axis_data_tdata(m_axis_data_tdata[i*ITEM_W+:ITEM_W]), .s_axis_data_tlast(m_axis_data_tlast[i]),
+        .s_axis_data_tvalid(m_axis_data_tvalid[i]), .s_axis_data_tready(m_axis_data_tready[i]),
+        .s_axis_data_tuser(m_axis_data_tuser[128*i+:128]),
+        .m_axis_data_tdata(m_axis_tagged_tdata), .m_axis_data_tlast(m_axis_tagged_tlast),
+        .m_axis_data_tvalid(m_axis_tagged_tvalid), .m_axis_data_tready(m_axis_tagged_tready),
+        .m_axis_data_tuser(m_axis_tagged_tuser), .m_axis_data_tag(m_axis_tagged_tag),
+        .in_set_stb(set_stb_int), .in_set_addr(set_addr_int), .in_set_data(set_data_int),
+        .in_set_time(set_time_int), .in_set_has_time(set_has_time_int),
+        .out_set_stb(out_set_stb), .out_set_addr(out_set_addr), .out_set_data(out_set_data),
+        .timed_set_stb(timed_set_stb), .timed_set_addr(timed_set_addr), .timed_set_data(timed_set_data));
+
+      // Hold off reading additional commands if internal FIFO is full
+      assign rb_stb[i] = ~timed_cmd_fifo_full;
+
+      ////////////////////////////////////////////////////////////
+      //
+      // Reduce Rate
+      //
+      ////////////////////////////////////////////////////////////
+      wire [31:0] sample_in_tdata, sample_out_tdata;
+      wire sample_in_tuser, sample_in_eob;
+      wire sample_in_tvalid, sample_in_tready, sample_in_tlast;
+      wire sample_out_tvalid, sample_out_tready;
+      wire clear_user;
+      wire nc;
+      axi_rate_change #(
+        .WIDTH(33),
+        .MAX_N(MAX_N),
+        .MAX_M(1),
+        .SR_N_ADDR(SR_N_ADDR),
+        .SR_M_ADDR(SR_M_ADDR),
+        .SR_CONFIG_ADDR(SR_CONFIG_ADDR))
+      axi_rate_change (
+        .clk(ce_clk), .reset(ddc_rst), .clear(clear_tx_seqnum[i]), .clear_user(clear_user),
+        .src_sid(src_sid[16*i+15:16*i]), .dst_sid(next_dst_sid[16*i+15:16*i]),
+        .set_stb(out_set_stb), .set_addr(out_set_addr), .set_data(out_set_data),
+        .i_tdata({m_axis_tagged_tag,m_axis_tagged_tdata}), .i_tlast(m_axis_tagged_tlast),
+        .i_tvalid(m_axis_tagged_tvalid), .i_tready(m_axis_tagged_tready),
+        .i_tuser(m_axis_tagged_tuser),
+        .o_tdata({nc,s_axis_data_tdata[i*ITEM_W+:ITEM_W]}), .o_tlast(s_axis_data_tlast[i]), .o_tvalid(s_axis_data_tvalid[i]),
+        .o_tready(s_axis_data_tready[i]), .o_tuser(s_axis_data_tuser[128*i+:128]),
+        .m_axis_data_tdata({sample_in_tuser,sample_in_tdata}), .m_axis_data_tlast(sample_in_tlast),
+        .m_axis_data_tvalid(sample_in_tvalid), .m_axis_data_tready(sample_in_tready),
+        .s_axis_data_tdata({1'b0,sample_out_tdata}), .s_axis_data_tlast(1'b0),
+        .s_axis_data_tvalid(sample_out_tvalid), .s_axis_data_tready(sample_out_tready),
+        .warning_long_throttle(),
+        .error_extra_outputs(),
+        .error_drop_pkt_lockup());
+
+      assign sample_in_eob = m_axis_tagged_tuser[124]; //this should align with last packet output from axi_rate_change
+
+      ////////////////////////////////////////////////////////////
+      //
+      // Digital Down Converter
+      //
+      ////////////////////////////////////////////////////////////
+
+      ddc #(
+        .SR_FREQ_ADDR(SR_FREQ_ADDR),
+        .SR_SCALE_IQ_ADDR(SR_SCALE_IQ_ADDR),
+        .SR_DECIM_ADDR(SR_DECIM_ADDR),
+        .SR_MUX_ADDR(SR_MUX_ADDR),
+        .SR_COEFFS_ADDR(SR_COEFFS_ADDR),
+        .NUM_HB(NUM_HB),
+        .CIC_MAX_DECIM(CIC_MAX_DECIM))
+      ddc (
+        .clk(ce_clk), .reset(ddc_rst),
+        .clear(clear_user | clear_tx_seqnum[i]), // Use AXI Rate Change's clear user to reset block to initial state after EOB
+        .set_stb(out_set_stb), .set_addr(out_set_addr), .set_data(out_set_data),
+        .timed_set_stb(timed_set_stb), .timed_set_addr(timed_set_addr), .timed_set_data(timed_set_data),
+        .sample_in_tdata(sample_in_tdata), .sample_in_tlast(sample_in_tlast),
+        .sample_in_tvalid(sample_in_tvalid), .sample_in_tready(sample_in_tready),
+        .sample_in_tuser(sample_in_tuser), .sample_in_eob(sample_in_eob),
+        .sample_out_tdata(sample_out_tdata), .sample_out_tlast(),
+        .sample_out_tvalid(sample_out_tvalid), .sample_out_tready(sample_out_tready)
+        );
+
+    end
+  endgenerate
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/rfnoc_block_ddc_regs.vh b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/rfnoc_block_ddc_regs.vh
new file mode 100644
index 000000000..bc1bf4c46
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/rfnoc_block_ddc_regs.vh
@@ -0,0 +1,27 @@
+//
+// Copyright 2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: rfnoc_block_ddc_regs (Header)
+//
+// Description: Header file for RFNoC DDC functionality. This includes 
+// register offsets, bitfields and constants for the radio components.
+//
+
+// For now, these offsets match the original DDC
+localparam DDC_BASE_ADDR = 'h00;
+localparam DDC_ADDR_W    = 8;
+
+localparam RB_COMPAT_NUM    = 0;
+localparam RB_NUM_HB        = 1;
+localparam RB_CIC_MAX_DECIM = 2;
+localparam SR_N_ADDR        = 128;
+localparam SR_M_ADDR        = 129;
+localparam SR_CONFIG_ADDR   = 130;
+localparam SR_FREQ_ADDR     = 132;
+localparam SR_SCALE_IQ_ADDR = 133;
+localparam SR_DECIM_ADDR    = 134;
+localparam SR_MUX_ADDR      = 135;
+localparam SR_COEFFS_ADDR   = 136;
+
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/rfnoc_block_ddc_tb.sv b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/rfnoc_block_ddc_tb.sv
new file mode 100644
index 000000000..8b0790909
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/rfnoc_block_ddc_tb.sv
@@ -0,0 +1,386 @@
+//
+// Copyright 2019 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: rfnoc_block_ddc_tb
+//
+// Description:  Testbench for rfnoc_block_ddc
+//
+
+
+module rfnoc_block_ddc_tb();
+
+  // Include macros and time declarations for use with PkgTestExec
+  `include "test_exec.svh"
+
+  import PkgTestExec::*;
+  import PkgChdrUtils::*;
+  import PkgRfnocBlockCtrlBfm::*;
+
+  `include "rfnoc_block_ddc_regs.vh"
+
+
+  //---------------------------------------------------------------------------
+  // Local Parameters
+  //---------------------------------------------------------------------------
+
+  // Simulation parameters
+  localparam real CHDR_CLK_PER   = 5.0;   // CHDR clock rate
+  localparam real DDC_CLK_PER    = 4.0;   // DUC IP clock rate
+  localparam int  EXTENDED_TEST  = 0;     // Perform a longer test
+  localparam int  SPP            = 256;   // Samples per packet
+  localparam int  PKT_SIZE_BYTES = SPP*4; // Bytes per packet
+  localparam int  STALL_PROB     = 25;    // BFM stall probability
+
+  // Block configuration
+  localparam int CHDR_W        = 64;
+  localparam int THIS_PORTID   = 'h123;
+  localparam int MTU           = 8;
+  localparam int NUM_PORTS     = 1;
+  localparam int NUM_HB        = 3;
+  localparam int CIC_MAX_DECIM = 255;
+
+
+  //---------------------------------------------------------------------------
+  // Clocks
+  //---------------------------------------------------------------------------
+
+  bit rfnoc_chdr_clk;
+  bit rfnoc_ctrl_clk;
+  bit ce_clk;
+
+  sim_clock_gen #(CHDR_CLK_PER) rfnoc_chdr_clk_gen (.clk(rfnoc_chdr_clk), .rst());
+  sim_clock_gen #(CHDR_CLK_PER) rfnoc_ctrl_clk_gen (.clk(rfnoc_ctrl_clk), .rst());
+  sim_clock_gen #(DDC_CLK_PER)  ddc_clk_gen        (.clk(ce_clk), .rst());
+
+
+  //---------------------------------------------------------------------------
+  // Bus Functional Models
+  //---------------------------------------------------------------------------
+
+  RfnocBackendIf        backend            (rfnoc_chdr_clk, rfnoc_ctrl_clk);
+  AxiStreamIf #(32)     m_ctrl             (rfnoc_ctrl_clk, 1'b0);
+  AxiStreamIf #(32)     s_ctrl             (rfnoc_ctrl_clk, 1'b0);
+  AxiStreamIf #(CHDR_W) m_chdr [NUM_PORTS] (rfnoc_chdr_clk, 1'b0);
+  AxiStreamIf #(CHDR_W) s_chdr [NUM_PORTS] (rfnoc_chdr_clk, 1'b0);
+
+  // Bus functional model for a software block controller
+  RfnocBlockCtrlBfm #(.CHDR_W(CHDR_W)) blk_ctrl =
+    new(backend, m_ctrl, s_ctrl);
+
+  // Connect block controller to BFMs
+  for (genvar i = 0; i < NUM_PORTS; i++) begin : gen_bfm_connections
+    initial begin
+      blk_ctrl.connect_master_data_port(i, m_chdr[i], PKT_SIZE_BYTES);
+      blk_ctrl.connect_slave_data_port(i, s_chdr[i]);
+      blk_ctrl.set_master_stall_prob(i, STALL_PROB);
+      blk_ctrl.set_slave_stall_prob(i, STALL_PROB);
+    end
+  end
+
+
+  //---------------------------------------------------------------------------
+  // DUT
+  //---------------------------------------------------------------------------
+
+  logic [NUM_PORTS*CHDR_W-1:0] s_rfnoc_chdr_tdata;
+  logic [       NUM_PORTS-1:0] s_rfnoc_chdr_tlast;
+  logic [       NUM_PORTS-1:0] s_rfnoc_chdr_tvalid;
+  logic [       NUM_PORTS-1:0] s_rfnoc_chdr_tready;
+
+  logic [NUM_PORTS*CHDR_W-1:0] m_rfnoc_chdr_tdata;
+  logic [       NUM_PORTS-1:0] m_rfnoc_chdr_tlast;
+  logic [       NUM_PORTS-1:0] m_rfnoc_chdr_tvalid;
+  logic [       NUM_PORTS-1:0] m_rfnoc_chdr_tready;
+
+  // Map the array of BFMs to a flat vector for the DUT
+  genvar i;
+  for (i = 0; i < NUM_PORTS; i++) begin : gen_dut_connections
+    // Connect BFM master to DUT slave port
+    assign s_rfnoc_chdr_tdata[CHDR_W*i+:CHDR_W] = m_chdr[i].tdata;
+    assign s_rfnoc_chdr_tlast[i]                = m_chdr[i].tlast;
+    assign s_rfnoc_chdr_tvalid[i]               = m_chdr[i].tvalid;
+    assign m_chdr[i].tready                     = s_rfnoc_chdr_tready[i];
+
+    // Connect BFM slave to DUT master port
+    assign s_chdr[i].tdata        = m_rfnoc_chdr_tdata[CHDR_W*i+:CHDR_W];
+    assign s_chdr[i].tlast        = m_rfnoc_chdr_tlast[i];
+    assign s_chdr[i].tvalid       = m_rfnoc_chdr_tvalid[i];
+    assign m_rfnoc_chdr_tready[i] = s_chdr[i].tready;
+  end
+
+  rfnoc_block_ddc #(
+    .THIS_PORTID    (THIS_PORTID),
+    .CHDR_W         (CHDR_W),
+    .NUM_PORTS      (NUM_PORTS),
+    .MTU            (MTU),
+    .NUM_HB         (NUM_HB),
+    .CIC_MAX_DECIM  (CIC_MAX_DECIM)
+  ) rfnoc_block_ddc_i (
+    .rfnoc_chdr_clk          (backend.chdr_clk),
+    .ce_clk                  (ce_clk),
+    .s_rfnoc_chdr_tdata      (s_rfnoc_chdr_tdata),
+    .s_rfnoc_chdr_tlast      (s_rfnoc_chdr_tlast),
+    .s_rfnoc_chdr_tvalid     (s_rfnoc_chdr_tvalid),
+    .s_rfnoc_chdr_tready     (s_rfnoc_chdr_tready),
+    .m_rfnoc_chdr_tdata      (m_rfnoc_chdr_tdata),
+    .m_rfnoc_chdr_tlast      (m_rfnoc_chdr_tlast),
+    .m_rfnoc_chdr_tvalid     (m_rfnoc_chdr_tvalid),
+    .m_rfnoc_chdr_tready     (m_rfnoc_chdr_tready),
+    .rfnoc_core_config       (backend.cfg),
+    .rfnoc_core_status       (backend.sts),
+    .rfnoc_ctrl_clk          (backend.ctrl_clk),
+    .s_rfnoc_ctrl_tdata      (m_ctrl.tdata),
+    .s_rfnoc_ctrl_tlast      (m_ctrl.tlast),
+    .s_rfnoc_ctrl_tvalid     (m_ctrl.tvalid),
+    .s_rfnoc_ctrl_tready     (m_ctrl.tready),
+    .m_rfnoc_ctrl_tdata      (s_ctrl.tdata),
+    .m_rfnoc_ctrl_tlast      (s_ctrl.tlast),
+    .m_rfnoc_ctrl_tvalid     (s_ctrl.tvalid),
+    .m_rfnoc_ctrl_tready     (s_ctrl.tready)
+  );
+
+
+  //---------------------------------------------------------------------------
+  // Helper Tasks
+  //---------------------------------------------------------------------------
+
+  // Translate the desired register access to a ctrlport write request.
+  task automatic write_reg(int port, byte addr, bit [31:0] value);
+    blk_ctrl.reg_write(256*8*port + addr*8, value);
+  endtask : write_reg
+
+
+  // Translate the desired register access to a ctrlport read request.
+  task automatic read_user_reg(int port, byte addr, output logic [63:0] value);
+    blk_ctrl.reg_read(256*8*port + addr*8 + 0, value[31: 0]);
+    blk_ctrl.reg_read(256*8*port + addr*8 + 4, value[63:32]);
+  endtask : read_user_reg
+
+
+  task automatic set_decim_rate(int port, input int decim_rate);
+    logic [7:0] cic_rate;
+    logic [1:0] hb_enables;
+    int _decim_rate;
+
+    cic_rate = 8'd0;
+    hb_enables = 2'b0;
+    _decim_rate = decim_rate;
+
+    // Calculate which half bands to enable and whatever is left over set the CIC
+    while ((_decim_rate[0] == 0) && (hb_enables < NUM_HB)) begin
+      hb_enables += 1'b1;
+      _decim_rate = _decim_rate >> 1;
+    end
+    // CIC rate cannot be set to 0
+    cic_rate = (_decim_rate[7:0] == 8'd0) ? 8'd1 : _decim_rate[7:0];
+    `ASSERT_ERROR(
+      hb_enables <= NUM_HB,
+      "Enabled halfbands may not exceed total number of half bands."
+    );
+    `ASSERT_ERROR(
+      cic_rate > 0 && cic_rate <= CIC_MAX_DECIM,
+      "CIC Decimation rate must be positive, not exceed the max cic decimation rate, and cannot equal 0!"
+    );
+
+    // Setup DDC
+    $display("Set decimation to %0d", decim_rate);
+    $display("- Number of enabled HBs: %0d", hb_enables);
+    $display("- CIC Rate:              %0d", cic_rate);
+    write_reg(port, SR_N_ADDR, decim_rate);                  // Set decimation rate in AXI rate change
+    write_reg(port, SR_DECIM_ADDR, {hb_enables,cic_rate});   // Enable HBs, set CIC rate
+  endtask
+
+
+  task automatic send_ramp (
+    input int unsigned port,
+    input int unsigned decim_rate,
+    // (Optional) For testing passing through partial packets
+    input logic drop_partial_packet = 1'b0,
+    input int unsigned extra_samples = 0
+  );
+    set_decim_rate(port, decim_rate);
+
+    // Setup DDC
+    write_reg(port, SR_CONFIG_ADDR, 32'd1);       // Enable clear EOB
+    write_reg(port, SR_FREQ_ADDR, 32'd0);         // Phase increment
+    write_reg(port, SR_SCALE_IQ_ADDR, (1 << 14)); // Scaling, set to 1
+
+    // Send a short ramp, should pass through unchanged
+    fork
+      begin
+        chdr_word_t send_payload[$];
+        packet_info_t pkt_info;
+
+        pkt_info = 0;
+        for (int i = 0; i < decim_rate*(PKT_SIZE_BYTES/8 + extra_samples); i++) begin
+          send_payload.push_back({16'(2*i/decim_rate), 16'(2*i/decim_rate), 16'((2*i+1)/decim_rate), 16'((2*i+1)/decim_rate)});
+        end
+        $display("Send ramp (%0d words)", send_payload.size());
+        pkt_info.eob = 1;
+        blk_ctrl.send_packets(port, send_payload, /*data_bytes*/, /*metadata*/, pkt_info);
+        blk_ctrl.wait_complete(port);
+        $display("Send ramp complete");
+      end
+      begin
+        string s;
+        logic [63:0]  samples, samples_old;
+        chdr_word_t   recv_payload[$], temp_payload[$];
+        chdr_word_t   metadata[$];
+        int           data_bytes;
+        packet_info_t pkt_info;
+
+        $display("Check ramp");
+        if (~drop_partial_packet && (extra_samples > 0)) begin
+          blk_ctrl.recv_adv(port, temp_payload, data_bytes, metadata, pkt_info);
+          $sformat(s, "Invalid EOB state! Expected %b, Received: %b", 1'b0, pkt_info.eob);
+          `ASSERT_ERROR(pkt_info.eob == 1'b0, s);
+        end
+        $display("Receiving packet");
+        blk_ctrl.recv_adv(port, recv_payload, data_bytes, metadata, pkt_info);
+        $display("Received!");
+        $sformat(s, "Invalid EOB state! Expected %b, Received: %b", 1'b1, pkt_info.eob);
+        `ASSERT_ERROR(pkt_info.eob == 1'b1, s);
+        recv_payload = {temp_payload, recv_payload};
+        if (drop_partial_packet) begin
+          $sformat(s, "Incorrect packet size! Expected: %0d, Actual: %0d", PKT_SIZE_BYTES/8, recv_payload.size());
+          `ASSERT_ERROR(recv_payload.size() == PKT_SIZE_BYTES/8, s);
+        end else begin
+          $sformat(s, "Incorrect packet size! Expected: %0d, Actual: %0d", PKT_SIZE_BYTES/8, recv_payload.size() + extra_samples);
+          `ASSERT_ERROR(recv_payload.size() == PKT_SIZE_BYTES/8 + extra_samples, s);
+        end
+        samples = 64'd0;
+        samples_old = 64'd0;
+        for (int i = 0; i < PKT_SIZE_BYTES/8; i++) begin
+          samples = recv_payload[i];
+          for (int j = 0; j < 4; j++) begin
+            // Need to check a range of values due to imperfect gain compensation
+            $sformat(s, "Ramp word %0d invalid! Expected: %0d-%0d, Received: %0d", 2*i,
+                samples_old[16*j +: 16], samples_old[16*j +: 16]+16'd4, samples[16*j +: 16]);
+            `ASSERT_ERROR((samples_old[16*j +: 16]+16'd4 >= samples[16*j +: 16]) && (samples >= samples_old[16*j +: 16]), s);
+          end
+          samples_old = samples;
+        end
+        $display("Check complete");
+      end
+    join
+  endtask
+
+
+  //---------------------------------------------------------------------------
+  // Test Process
+  //---------------------------------------------------------------------------
+
+  initial begin : tb_main
+    const int port = 0;
+    test.start_tb("rfnoc_block_ddc_tb");
+
+    // Start the BFMs running
+    blk_ctrl.run();
+
+
+    //-------------------------------------------------------------------------
+    // Reset
+    //-------------------------------------------------------------------------
+
+    test.start_test("Wait for Reset", 10us);
+    fork
+      blk_ctrl.reset_chdr();
+      blk_ctrl.reset_ctrl();
+    join;
+    test.end_test();
+
+
+    //-------------------------------------------------------------------------
+    // Check NoC ID and Block Info
+    //-------------------------------------------------------------------------
+
+    test.start_test("Verify Block Info", 2us);
+    `ASSERT_ERROR(blk_ctrl.get_noc_id() == rfnoc_block_ddc_i.NOC_ID, "Incorrect NOC_ID Value");
+    `ASSERT_ERROR(blk_ctrl.get_num_data_i() == NUM_PORTS, "Incorrect NUM_DATA_I Value");
+    `ASSERT_ERROR(blk_ctrl.get_num_data_o() == NUM_PORTS, "Incorrect NUM_DATA_O Value");
+    `ASSERT_ERROR(blk_ctrl.get_mtu() == MTU, "Incorrect MTU Value");
+    test.end_test();
+
+
+    //-------------------------------------------------------------------------
+    // Test read-back regs
+    //-------------------------------------------------------------------------
+
+    begin
+      logic [63:0] val64;
+      test.start_test("Test registers", 10us);
+      read_user_reg(port, RB_NUM_HB, val64);
+      `ASSERT_ERROR(val64 == NUM_HB, "Register NUM_HB didn't read back expected value");
+      read_user_reg(port, RB_CIC_MAX_DECIM, val64);
+      `ASSERT_ERROR(val64 == CIC_MAX_DECIM, "Register CIC_MAX_DECIM didn't read back expected value");
+      test.end_test();
+    end
+
+
+    //-------------------------------------------------------------------------
+    // Test various decimation rates
+    //-------------------------------------------------------------------------
+
+    begin
+      test.start_test("Decimate by 1, 2, 3, 4, 6, 8, 12, 13, 16, 24, 40, 255, 2040", 0.5ms);
+
+      $display("Note: This test will take a long time!");
+
+      // List of rates to catch most issues
+      send_ramp(port, 1);                       // HBs enabled: 0, CIC rate: 1
+      send_ramp(port, 2);                       // HBs enabled: 1, CIC rate: 1
+      send_ramp(port, 3);                       // HBs enabled: 0, CIC rate: 3
+      send_ramp(port, 4);                       // HBs enabled: 2, CIC rate: 1
+      if (EXTENDED_TEST) send_ramp(port, 6);    // HBs enabled: 1, CIC rate: 3
+      send_ramp(port, 8);                       // HBs enabled: 3, CIC rate: 1
+      send_ramp(port, 12);                      // HBs enabled: 2, CIC rate: 3
+      send_ramp(port, 13);                      // HBs enabled: 0, CIC rate: 13
+      if (EXTENDED_TEST) send_ramp(port, 16);   // HBs enabled: 3, CIC rate: 2
+      if (EXTENDED_TEST) send_ramp(port, 24);   // HBs enabled: 3, CIC rate: 3
+      send_ramp(port, 40);                      // HBs enabled: 3, CIC rate: 5
+      if (EXTENDED_TEST) send_ramp(port, 200);  // HBs enabled: 3, CIC rate: 25
+      send_ramp(port, 255);                     // HBs enabled: 0, CIC rate: 255
+      if (EXTENDED_TEST) send_ramp(port, 2040); // HBs enabled: 3, CIC rate: 255
+
+      test.end_test();
+    end
+
+
+    //-------------------------------------------------------------------------
+    // Test timed tune
+    //-------------------------------------------------------------------------
+
+    // This test has not been implemented because the RFNoC FFT has not been
+    // ported yet.
+
+
+    //-------------------------------------------------------------------------
+    // Test passing through a partial packet
+    //-------------------------------------------------------------------------
+
+    test.start_test("Pass through partial packet");
+    send_ramp(port, 2, 0, 4);
+    send_ramp(port, 3, 0, 4);
+    send_ramp(port, 4, 0, 4);
+    if (EXTENDED_TEST) send_ramp(port, 8, 0, 4);
+    send_ramp(port, 13, 0, 4);
+    if (EXTENDED_TEST) send_ramp(port, 24, 0, 4);
+    test.end_test();
+
+
+    //-------------------------------------------------------------------------
+    // Finish
+    //-------------------------------------------------------------------------
+
+    // End the TB, but don't $finish, since we don't want to kill other
+    // instances of this testbench that may be running.
+    test.end_tb(0);
+
+    // Kill the clocks to end this instance of the testbench
+    rfnoc_chdr_clk_gen.kill();
+    rfnoc_ctrl_clk_gen.kill();
+    ddc_clk_gen.kill();
+  end
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/Makefile b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/Makefile
new file mode 100644
index 000000000..6d1da3d60
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/Makefile
@@ -0,0 +1,67 @@
+#
+# Copyright 2019 Ettus Research, A National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+#-------------------------------------------------
+# Top-of-Makefile
+#-------------------------------------------------
+# Define BASE_DIR to point to the "top" dir
+BASE_DIR = $(abspath ../../../../top)
+# Include viv_sim_preamble after defining BASE_DIR
+include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
+
+#-------------------------------------------------
+# IP Specific
+#-------------------------------------------------
+# If simulation contains IP, define the IP_DIR and point
+# it to the base level IP directory
+LIB_IP_DIR = $(BASE_DIR)/../lib/ip
+
+# Include makefiles and sources for all IP components
+# *after* defining the LIB_IP_DIR
+include $(LIB_IP_DIR)/axi_hb47/Makefile.inc
+include $(LIB_IP_DIR)/complex_multiplier_dds/Makefile.inc
+include $(LIB_IP_DIR)/dds_sin_cos_lut_only/Makefile.inc
+include $(BASE_DIR)/x300/coregen_dsp/Makefile.srcs
+
+DESIGN_SRCS += $(abspath \
+$(LIB_IP_AXI_HB47_SRCS) \
+$(LIB_IP_COMPLEX_MULTIPLIER_DDS_SRCS) \
+$(LIB_IP_DDS_SIN_COS_LUT_ONLY_SRCS) \
+$(COREGEN_DSP_SRCS) \
+)
+
+#-------------------------------------------------
+# Design Specific
+#-------------------------------------------------
+# Include makefiles and sources for the DUT and its dependencies
+include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs
+include $(BASE_DIR)/../lib/rfnoc/utils/Makefile.srcs
+include Makefile.srcs
+
+DESIGN_SRCS += $(abspath \
+$(RFNOC_CORE_SRCS) \
+$(RFNOC_UTIL_SRCS) \
+$(RFNOC_BLOCK_DUC_SRCS) \
+)
+
+#-------------------------------------------------
+# Testbench Specific
+#-------------------------------------------------
+# Define only one toplevel module
+SIM_TOP = rfnoc_block_duc_tb
+
+# Add test bench, user design under test, and
+# additional user created files
+SIM_SRCS = \
+$(abspath rfnoc_block_duc_tb.sv)
+
+#-------------------------------------------------
+# Bottom-of-Makefile
+#-------------------------------------------------
+# Include all simulator specific makefiles here
+# Each should define a unique target to simulate
+# e.g. xsim, vsim, etc and a common "clean" target
+include $(BASE_DIR)/../tools/make/viv_simulator.mak
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/Makefile.srcs b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/Makefile.srcs
new file mode 100644
index 000000000..69b6eaece
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/Makefile.srcs
@@ -0,0 +1,11 @@
+#
+# Copyright 2019 Ettus Research, A National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+RFNOC_BLOCK_DUC_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/rfnoc/blocks/rfnoc_block_duc/, \
+../rfnoc_block_ddc/noc_shell_ddc.v \
+rfnoc_block_duc_regs.vh \
+rfnoc_block_duc.v \
+))
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/rfnoc_block_duc.v b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/rfnoc_block_duc.v
new file mode 100644
index 000000000..400e9d270
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/rfnoc_block_duc.v
@@ -0,0 +1,387 @@
+//
+// Copyright 2019 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: rfnoc_block_duc
+//
+// Description:  An digital up-converter block for RFNoC.
+//
+// Parameters:
+//
+//   THIS_PORTID    : Control crossbar port to which this block is connected
+//   CHDR_W         : AXIS CHDR interface data width
+//   NUM_PORTS      : Number of DUC signal processing chains
+//   MTU            : Maximum transmission unit (i.e., maximum packet size) in
+//                    CHDR words is 2**MTU.
+//   CTRL_FIFO_SIZE : Size of the Control Port slave FIFO. This affects the
+//                    number of outstanding commands that can be pending.
+//   NUM_HB         : Number of half-band filter blocks to include (0-3)
+//   CIC_MAX_INTERP : Maximum interpolation to support in the CIC filter
+//
+
+module rfnoc_block_duc #(
+  parameter THIS_PORTID    = 0,
+  parameter CHDR_W         = 64,
+  parameter NUM_PORTS      = 2,
+  parameter MTU            = 10,
+  parameter CTRL_FIFO_SIZE = 6,
+  parameter NUM_HB         = 2,
+  parameter CIC_MAX_INTERP = 128
+) (
+  //---------------------------------------------------------------------------
+  // AXIS CHDR Port
+  //---------------------------------------------------------------------------
+
+  input wire rfnoc_chdr_clk,
+  input wire ce_clk,
+
+  // CHDR inputs from framework
+  input  wire [NUM_PORTS*CHDR_W-1:0] s_rfnoc_chdr_tdata,
+  input  wire [       NUM_PORTS-1:0] s_rfnoc_chdr_tlast,
+  input  wire [       NUM_PORTS-1:0] s_rfnoc_chdr_tvalid,
+  output wire [       NUM_PORTS-1:0] s_rfnoc_chdr_tready,
+
+  // CHDR outputs to framework
+  output wire [NUM_PORTS*CHDR_W-1:0] m_rfnoc_chdr_tdata,
+  output wire [       NUM_PORTS-1:0] m_rfnoc_chdr_tlast,
+  output wire [       NUM_PORTS-1:0] m_rfnoc_chdr_tvalid,
+  input  wire [       NUM_PORTS-1:0] m_rfnoc_chdr_tready,
+
+  // Backend interface
+  input  wire [511:0] rfnoc_core_config,
+  output wire [511:0] rfnoc_core_status,
+
+  //---------------------------------------------------------------------------
+  // AXIS CTRL Port
+  //---------------------------------------------------------------------------
+
+  input wire rfnoc_ctrl_clk,
+
+  // CTRL port requests from framework
+  input  wire [31:0] s_rfnoc_ctrl_tdata,
+  input  wire        s_rfnoc_ctrl_tlast,
+  input  wire        s_rfnoc_ctrl_tvalid,
+  output wire        s_rfnoc_ctrl_tready,
+
+  // CTRL port requests to framework
+  output wire [31:0] m_rfnoc_ctrl_tdata,
+  output wire        m_rfnoc_ctrl_tlast,
+  output wire        m_rfnoc_ctrl_tvalid,
+  input  wire        m_rfnoc_ctrl_tready
+);
+
+  // These are the only supported values for now
+  localparam ITEM_W = 32;
+  localparam NIPC   = 1;
+
+  localparam NOC_ID = 'hD0C0_0000;
+
+  localparam COMPAT_MAJOR  = 16'h0;
+  localparam COMPAT_MINOR  = 16'h0;
+
+  `include "rfnoc_block_duc_regs.vh"
+  `include "../../core/rfnoc_axis_ctrl_utils.vh"
+
+
+  //---------------------------------------------------------------------------
+  // Signal Declarations
+  //---------------------------------------------------------------------------
+
+  wire rfnoc_chdr_rst;
+
+  wire        ctrlport_req_wr;
+  wire        ctrlport_req_rd;
+  wire [19:0] ctrlport_req_addr;
+  wire [31:0] ctrlport_req_data;
+  wire        ctrlport_req_has_time;
+  wire [63:0] ctrlport_req_time;
+  wire        ctrlport_resp_ack;
+  wire [31:0] ctrlport_resp_data;
+
+  wire [NUM_PORTS*ITEM_W-1:0] m_axis_data_tdata;
+  wire [       NUM_PORTS-1:0] m_axis_data_tlast;
+  wire [       NUM_PORTS-1:0] m_axis_data_tvalid;
+  wire [       NUM_PORTS-1:0] m_axis_data_tready;
+  wire [    NUM_PORTS*64-1:0] m_axis_data_ttimestamp;
+  wire [       NUM_PORTS-1:0] m_axis_data_thas_time;
+  wire [    NUM_PORTS*16-1:0] m_axis_data_tlength;
+  wire [       NUM_PORTS-1:0] m_axis_data_teob;
+  wire [   NUM_PORTS*128-1:0] m_axis_data_tuser;
+
+  wire [NUM_PORTS*ITEM_W-1:0] s_axis_data_tdata;
+  wire [       NUM_PORTS-1:0] s_axis_data_tlast;
+  wire [       NUM_PORTS-1:0] s_axis_data_tvalid;
+  wire [       NUM_PORTS-1:0] s_axis_data_tready;
+  wire [   NUM_PORTS*128-1:0] s_axis_data_tuser;
+  wire [       NUM_PORTS-1:0] s_axis_data_teob;
+  wire [    NUM_PORTS*64-1:0] s_axis_data_ttimestamp;
+  wire [       NUM_PORTS-1:0] s_axis_data_thas_time;
+
+  wire duc_rst;
+
+  // Cross the CHDR reset to the ce_clk domain
+  synchronizer duc_rst_sync_i (
+    .clk (ce_clk),
+    .rst (1'b0),
+    .in  (rfnoc_chdr_rst),
+    .out (duc_rst)
+  );
+
+
+  //---------------------------------------------------------------------------
+  // NoC Shell
+  //---------------------------------------------------------------------------
+
+  // TODO: Replace noc_shell_radio with a customized block
+  noc_shell_ddc #(
+    .NOC_ID          (NOC_ID),
+    .THIS_PORTID     (THIS_PORTID),
+    .CHDR_W          (CHDR_W),
+    .CTRLPORT_SLV_EN (0),
+    .CTRLPORT_MST_EN (1),
+    .CTRL_FIFO_SIZE  (CTRL_FIFO_SIZE),
+    .NUM_DATA_I      (NUM_PORTS),
+    .NUM_DATA_O      (NUM_PORTS),
+    .ITEM_W          (ITEM_W),
+    .NIPC            (NIPC),
+    .PYLD_FIFO_SIZE  (MTU),
+    .MTU             (MTU)
+  ) noc_shell_ddc_i (
+    .rfnoc_chdr_clk            (rfnoc_chdr_clk),
+    .rfnoc_chdr_rst            (rfnoc_chdr_rst),
+    .rfnoc_ctrl_clk            (rfnoc_ctrl_clk),
+    .rfnoc_ctrl_rst            (),
+    .rfnoc_core_config         (rfnoc_core_config),
+    .rfnoc_core_status         (rfnoc_core_status),
+    .s_rfnoc_chdr_tdata        (s_rfnoc_chdr_tdata),
+    .s_rfnoc_chdr_tlast        (s_rfnoc_chdr_tlast),
+    .s_rfnoc_chdr_tvalid       (s_rfnoc_chdr_tvalid),
+    .s_rfnoc_chdr_tready       (s_rfnoc_chdr_tready),
+    .m_rfnoc_chdr_tdata        (m_rfnoc_chdr_tdata),
+    .m_rfnoc_chdr_tlast        (m_rfnoc_chdr_tlast),
+    .m_rfnoc_chdr_tvalid       (m_rfnoc_chdr_tvalid),
+    .m_rfnoc_chdr_tready       (m_rfnoc_chdr_tready),
+    .s_rfnoc_ctrl_tdata        (s_rfnoc_ctrl_tdata),
+    .s_rfnoc_ctrl_tlast        (s_rfnoc_ctrl_tlast),
+    .s_rfnoc_ctrl_tvalid       (s_rfnoc_ctrl_tvalid),
+    .s_rfnoc_ctrl_tready       (s_rfnoc_ctrl_tready),
+    .m_rfnoc_ctrl_tdata        (m_rfnoc_ctrl_tdata),
+    .m_rfnoc_ctrl_tlast        (m_rfnoc_ctrl_tlast),
+    .m_rfnoc_ctrl_tvalid       (m_rfnoc_ctrl_tvalid),
+    .m_rfnoc_ctrl_tready       (m_rfnoc_ctrl_tready),
+    .ctrlport_clk              (ce_clk),
+    .ctrlport_rst              (duc_rst),
+    .m_ctrlport_req_wr         (ctrlport_req_wr),
+    .m_ctrlport_req_rd         (ctrlport_req_rd),
+    .m_ctrlport_req_addr       (ctrlport_req_addr),
+    .m_ctrlport_req_data       (ctrlport_req_data),
+    .m_ctrlport_req_byte_en    (),
+    .m_ctrlport_req_has_time   (ctrlport_req_has_time),
+    .m_ctrlport_req_time       (ctrlport_req_time),
+    .m_ctrlport_resp_ack       (ctrlport_resp_ack),
+    .m_ctrlport_resp_status    (AXIS_CTRL_STS_OKAY),
+    .m_ctrlport_resp_data      (ctrlport_resp_data),
+    .s_ctrlport_req_wr         (1'b0),
+    .s_ctrlport_req_rd         (1'b0),
+    .s_ctrlport_req_addr       (20'b0),
+    .s_ctrlport_req_portid     (10'b0),
+    .s_ctrlport_req_rem_epid   (16'b0),
+    .s_ctrlport_req_rem_portid (10'b0),
+    .s_ctrlport_req_data       (32'b0),
+    .s_ctrlport_req_byte_en    (4'b0),
+    .s_ctrlport_req_has_time   (1'b0),
+    .s_ctrlport_req_time       (64'b0),
+    .s_ctrlport_resp_ack       (),
+    .s_ctrlport_resp_status    (),
+    .s_ctrlport_resp_data      (),
+    .axis_data_clk             (ce_clk),
+    .axis_data_rst             (duc_rst),
+    .m_axis_tdata              (m_axis_data_tdata),
+    .m_axis_tkeep              (),
+    .m_axis_tlast              (m_axis_data_tlast),
+    .m_axis_tvalid             (m_axis_data_tvalid),
+    .m_axis_tready             (m_axis_data_tready),
+    .m_axis_ttimestamp         (m_axis_data_ttimestamp),
+    .m_axis_thas_time          (m_axis_data_thas_time),
+    .m_axis_tlength            (m_axis_data_tlength),
+    .m_axis_teov               (),
+    .m_axis_teob               (m_axis_data_teob),
+    .s_axis_tdata              (s_axis_data_tdata),
+    .s_axis_tkeep              ({NUM_PORTS*NIPC{1'b1}}),
+    .s_axis_tlast              (s_axis_data_tlast),
+    .s_axis_tvalid             (s_axis_data_tvalid),
+    .s_axis_tready             (s_axis_data_tready),
+    .s_axis_ttimestamp         (s_axis_data_ttimestamp),
+    .s_axis_thas_time          (s_axis_data_thas_time),
+    .s_axis_teov               ({NUM_PORTS{1'b0}}),
+    .s_axis_teob               (s_axis_data_teob)
+  );
+
+
+  //---------------------------------------------------------------------------
+  // Register Translation
+  //---------------------------------------------------------------------------
+  //
+  // Each DUC block is allocated an address spaces. This block translates CTRL
+  // port transactions in that space to settings bus.
+  //
+  //---------------------------------------------------------------------------
+
+  wire [ 8*NUM_PORTS-1:0] set_addr;
+  wire [32*NUM_PORTS-1:0] set_data;
+  wire [   NUM_PORTS-1:0] set_has_time;
+  wire [   NUM_PORTS-1:0] set_stb;
+  wire [64*NUM_PORTS-1:0] set_time;
+  wire [ 8*NUM_PORTS-1:0] rb_addr;
+  reg  [64*NUM_PORTS-1:0] rb_data;
+
+  ctrlport_to_settings_bus # (
+    .NUM_PORTS (NUM_PORTS)
+  ) ctrlport_to_settings_bus_i (
+    .ctrlport_clk             (ce_clk),
+    .ctrlport_rst             (duc_rst),
+    .s_ctrlport_req_wr        (ctrlport_req_wr),
+    .s_ctrlport_req_rd        (ctrlport_req_rd),
+    .s_ctrlport_req_addr      (ctrlport_req_addr),
+    .s_ctrlport_req_data      (ctrlport_req_data),
+    .s_ctrlport_req_has_time  (ctrlport_req_has_time),
+    .s_ctrlport_req_time      (ctrlport_req_time),
+    .s_ctrlport_resp_ack      (ctrlport_resp_ack),
+    .s_ctrlport_resp_data     (ctrlport_resp_data),
+    .set_data                 (set_data),
+    .set_addr                 (set_addr),
+    .set_stb                  (set_stb),
+    .set_time                 (set_time),
+    .set_has_time             (set_has_time),
+    .rb_stb                   ({NUM_PORTS{1'b1}}),
+    .rb_addr                  (rb_addr),
+    .rb_data                  (rb_data));
+
+
+  //---------------------------------------------------------------------------
+  // DUC Implementation
+  //---------------------------------------------------------------------------
+
+  // Unused signals
+  wire [   NUM_PORTS-1:0] clear_tx_seqnum = 0;
+  wire [16*NUM_PORTS-1:0] src_sid         = 0;
+  wire [16*NUM_PORTS-1:0] next_dst_sid    = 0;
+
+  localparam MAX_M = CIC_MAX_INTERP * 2<<(NUM_HB-1);
+
+  genvar i;
+  generate
+    for (i = 0; i < NUM_PORTS; i = i + 1) begin : gen_duc_chains
+      wire clear_user;
+      wire clear_duc = clear_tx_seqnum[i] | clear_user;
+
+      wire        set_stb_int      = set_stb[i];
+      wire [7:0]  set_addr_int     = set_addr[8*i+7:8*i];
+      wire [31:0] set_data_int     = set_data[32*i+31:32*i];
+      wire [63:0] set_time_int     = set_time[64*i+63:64*i];
+      wire        set_has_time_int = set_has_time[i];
+
+      // Build the expected tuser CHDR header
+      cvita_hdr_encoder cvita_hdr_encoder_i (
+        .pkt_type       (2'b0),
+        .eob            (m_axis_data_teob[i]),
+        .has_time       (m_axis_data_thas_time[i]),
+        .seqnum         (12'b0),
+        .payload_length (m_axis_data_tlength[16*i +: 16]),
+        .src_sid        (16'b0),
+        .dst_sid        (16'b0),
+        .vita_time      (m_axis_data_ttimestamp[64*i +: 64]),
+        .header         (m_axis_data_tuser[128*i+:128])
+      );
+
+      // Extract bit fields from outgoing tuser CHDR header
+      assign s_axis_data_teob[i]              = s_axis_data_tuser[128*i+124 +:  1];
+      assign s_axis_data_thas_time[i]         = s_axis_data_tuser[128*i+125 +:  1];
+      assign s_axis_data_ttimestamp[64*i+:64] = s_axis_data_tuser[128*i+  0 +: 64];
+
+      // TODO Readback register for number of FIR filter taps
+      always @(*) begin
+        case(rb_addr[i*8+7:i*8])
+          RB_COMPAT_NUM     : rb_data[i*64+63:i*64] <= {COMPAT_MAJOR, COMPAT_MINOR};
+          RB_NUM_HB         : rb_data[i*64+63:i*64] <= NUM_HB;
+          RB_CIC_MAX_INTERP : rb_data[i*64+63:i*64] <= CIC_MAX_INTERP;
+          default           : rb_data[i*64+63:i*64] <= 64'h0BADC0DE0BADC0DE;
+        endcase
+      end
+
+      ////////////////////////////////////////////////////////////
+      //
+      // Timed CORDIC
+      // - Implements timed cordic tunes. Placed between AXI Wrapper
+      //   and AXI Rate Change due to it needing access to the
+      //   vita time of the samples.
+      //
+      ////////////////////////////////////////////////////////////
+      wire [31:0]  m_axis_rc_tdata;
+      wire         m_axis_rc_tlast;
+      wire         m_axis_rc_tvalid;
+      wire         m_axis_rc_tready;
+      wire [127:0] m_axis_rc_tuser;
+
+      dds_timed #(
+        .SR_FREQ_ADDR(SR_FREQ_ADDR),
+        .SR_SCALE_IQ_ADDR(SR_SCALE_IQ_ADDR))
+      dds_timed (
+        .clk(ce_clk), .reset(duc_rst), .clear(clear_tx_seqnum[i]),
+        .timed_cmd_fifo_full(),
+        .set_stb(set_stb_int), .set_addr(set_addr_int), .set_data(set_data_int),
+        .set_time(set_time_int), .set_has_time(set_has_time_int),
+        .i_tdata(m_axis_rc_tdata), .i_tlast(m_axis_rc_tlast), .i_tvalid(m_axis_rc_tvalid),
+        .i_tready(m_axis_rc_tready), .i_tuser(m_axis_rc_tuser),
+        .o_tdata(s_axis_data_tdata[ITEM_W*i+:ITEM_W]), .o_tlast(s_axis_data_tlast[i]), .o_tvalid(s_axis_data_tvalid[i]),
+        .o_tready(s_axis_data_tready[i]), .o_tuser(s_axis_data_tuser[128*i+:128]));
+
+      ////////////////////////////////////////////////////////////
+      //
+      // Increase Rate
+      //
+      ////////////////////////////////////////////////////////////
+      wire [31:0] sample_tdata, sample_duc_tdata;
+      wire sample_tvalid, sample_tready;
+      wire sample_duc_tvalid, sample_duc_tready;
+      axi_rate_change #(
+        .WIDTH(32),
+        .MAX_N(1),
+        .MAX_M(MAX_M),
+        .SR_N_ADDR(SR_N_ADDR),
+        .SR_M_ADDR(SR_M_ADDR),
+        .SR_CONFIG_ADDR(SR_CONFIG_ADDR))
+      axi_rate_change (
+        .clk(ce_clk), .reset(duc_rst), .clear(clear_tx_seqnum[i]), .clear_user(clear_user),
+        .src_sid(src_sid[16*i+15:16*i]), .dst_sid(next_dst_sid[16*i+15:16*i]),
+        .set_stb(set_stb_int), .set_addr(set_addr_int), .set_data(set_data_int),
+        .i_tdata(m_axis_data_tdata[ITEM_W*i+:ITEM_W]), .i_tlast(m_axis_data_tlast[i]), .i_tvalid(m_axis_data_tvalid[i]),
+        .i_tready(m_axis_data_tready[i]), .i_tuser(m_axis_data_tuser[128*i+:128]),
+        .o_tdata(m_axis_rc_tdata), .o_tlast(m_axis_rc_tlast), .o_tvalid(m_axis_rc_tvalid),
+        .o_tready(m_axis_rc_tready), .o_tuser(m_axis_rc_tuser),
+        .m_axis_data_tdata({sample_tdata}), .m_axis_data_tlast(), .m_axis_data_tvalid(sample_tvalid),
+        .m_axis_data_tready(sample_tready),
+        .s_axis_data_tdata(sample_duc_tdata), .s_axis_data_tlast(1'b0), .s_axis_data_tvalid(sample_duc_tvalid),
+        .s_axis_data_tready(sample_duc_tready),
+        .warning_long_throttle(), .error_extra_outputs(), .error_drop_pkt_lockup());
+
+      ////////////////////////////////////////////////////////////
+      //
+      // Digital Up Converter
+      //
+      ////////////////////////////////////////////////////////////
+      duc #(
+        .SR_INTERP_ADDR(SR_INTERP_ADDR),
+        .NUM_HB(NUM_HB),
+        .CIC_MAX_INTERP(CIC_MAX_INTERP))
+      duc (
+        .clk(ce_clk), .reset(duc_rst), .clear(clear_duc),
+        .set_stb(set_stb_int), .set_addr(set_addr_int), .set_data(set_data_int),
+        .i_tdata(sample_tdata), .i_tuser(128'b0), .i_tvalid(sample_tvalid), .i_tready(sample_tready),
+        .o_tdata(sample_duc_tdata), .o_tuser(), .o_tvalid(sample_duc_tvalid), .o_tready(sample_duc_tready));
+
+    end
+  endgenerate
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/rfnoc_block_duc_regs.vh b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/rfnoc_block_duc_regs.vh
new file mode 100644
index 000000000..fa239857e
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/rfnoc_block_duc_regs.vh
@@ -0,0 +1,25 @@
+//
+// Copyright 2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: rfnoc_block_duc_regs (Header)
+//
+// Description: Header file for RFNoC DUC functionality. This includes 
+// register offsets, bitfields and constants for the radio components.
+//
+
+// For now, these offsets match the original DUC
+localparam DUC_BASE_ADDR = 'h00;
+localparam DUC_ADDR_W    = 8;
+
+localparam RB_COMPAT_NUM     = 0;
+localparam RB_NUM_HB         = 1;
+localparam RB_CIC_MAX_INTERP = 2;
+localparam SR_N_ADDR         = 128;
+localparam SR_M_ADDR         = 129;
+localparam SR_CONFIG_ADDR    = 130;
+localparam SR_INTERP_ADDR    = 131;
+localparam SR_FREQ_ADDR      = 132;
+localparam SR_SCALE_IQ_ADDR  = 133;
+
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/rfnoc_block_duc_tb.sv b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/rfnoc_block_duc_tb.sv
new file mode 100644
index 000000000..5bca3f03b
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/rfnoc_block_duc_tb.sv
@@ -0,0 +1,387 @@
+//
+// Copyright 2019 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: rfnoc_block_duc_tb
+//
+// Description:  Testbench for rfnoc_block_duc
+//
+
+
+module rfnoc_block_duc_tb();
+
+  // Include macros and time declarations for use with PkgTestExec
+  `include "test_exec.svh"
+
+  import PkgTestExec::*;
+  import PkgChdrUtils::*;
+  import PkgRfnocBlockCtrlBfm::*;
+
+  `include "rfnoc_block_duc_regs.vh"
+
+
+  //---------------------------------------------------------------------------
+  // Local Parameters
+  //---------------------------------------------------------------------------
+
+  // Simulation parameters
+  localparam real CHDR_CLK_PER   = 5.0;   // CHDR clock rate
+  localparam real DUC_CLK_PER    = 4.0;   // DUC IP clock rate
+  localparam int  EXTENDED_TEST  = 0;     // Perform a longer test
+  localparam int  SPP            = 128;   // Samples per packet
+  localparam int  PKT_SIZE_BYTES = SPP*4; // Bytes per packet
+  localparam int  STALL_PROB     = 25;    // BFM stall probability
+
+  // Block configuration
+  localparam int CHDR_W         = 64;
+  localparam int THIS_PORTID    = 'h123;
+  localparam int MTU            = 8;
+  localparam int NUM_PORTS      = 1;
+  localparam int NUM_HB         = 3;
+  localparam int CIC_MAX_INTERP = 128;
+
+
+  //---------------------------------------------------------------------------
+  // Clocks
+  //---------------------------------------------------------------------------
+
+  bit rfnoc_chdr_clk;
+  bit rfnoc_ctrl_clk;
+
+  sim_clock_gen #(CHDR_CLK_PER) rfnoc_chdr_clk_gen (.clk(rfnoc_chdr_clk), .rst());
+  sim_clock_gen #(CHDR_CLK_PER) rfnoc_ctrl_clk_gen (.clk(rfnoc_ctrl_clk), .rst());
+  sim_clock_gen #(DUC_CLK_PER)  duc_clk_gen        (.clk(ce_clk), .rst());
+
+
+  //---------------------------------------------------------------------------
+  // Bus Functional Models
+  //---------------------------------------------------------------------------
+
+  RfnocBackendIf        backend            (rfnoc_chdr_clk, rfnoc_ctrl_clk);
+  AxiStreamIf #(32)     m_ctrl             (rfnoc_ctrl_clk, 1'b0);
+  AxiStreamIf #(32)     s_ctrl             (rfnoc_ctrl_clk, 1'b0);
+  AxiStreamIf #(CHDR_W) m_chdr [NUM_PORTS] (rfnoc_chdr_clk, 1'b0);
+  AxiStreamIf #(CHDR_W) s_chdr [NUM_PORTS] (rfnoc_chdr_clk, 1'b0);
+
+  // Bus functional model for a software block controller
+  RfnocBlockCtrlBfm #(.CHDR_W(CHDR_W)) blk_ctrl =
+    new(backend, m_ctrl, s_ctrl);
+
+  // Connect block controller to BFMs
+  for (genvar i = 0; i < NUM_PORTS; i++) begin : gen_bfm_connections
+    initial begin
+      blk_ctrl.connect_master_data_port(i, m_chdr[i], PKT_SIZE_BYTES);
+      blk_ctrl.connect_slave_data_port(i, s_chdr[i]);
+      blk_ctrl.set_master_stall_prob(i, STALL_PROB);
+      blk_ctrl.set_slave_stall_prob(i, STALL_PROB);
+    end
+  end
+
+
+  //---------------------------------------------------------------------------
+  // DUT
+  //---------------------------------------------------------------------------
+
+  logic [NUM_PORTS*CHDR_W-1:0] s_rfnoc_chdr_tdata;
+  logic [       NUM_PORTS-1:0] s_rfnoc_chdr_tlast;
+  logic [       NUM_PORTS-1:0] s_rfnoc_chdr_tvalid;
+  logic [       NUM_PORTS-1:0] s_rfnoc_chdr_tready;
+
+  logic [NUM_PORTS*CHDR_W-1:0] m_rfnoc_chdr_tdata;
+  logic [       NUM_PORTS-1:0] m_rfnoc_chdr_tlast;
+  logic [       NUM_PORTS-1:0] m_rfnoc_chdr_tvalid;
+  logic [       NUM_PORTS-1:0] m_rfnoc_chdr_tready;
+
+  // Map the array of BFMs to a flat vector for the DUT
+  genvar i;
+  for (i = 0; i < NUM_PORTS; i++) begin : gen_dut_connections
+    // Connect BFM master to DUT slave port
+    assign s_rfnoc_chdr_tdata[CHDR_W*i+:CHDR_W] = m_chdr[i].tdata;
+    assign s_rfnoc_chdr_tlast[i]                = m_chdr[i].tlast;
+    assign s_rfnoc_chdr_tvalid[i]               = m_chdr[i].tvalid;
+    assign m_chdr[i].tready                     = s_rfnoc_chdr_tready[i];
+
+    // Connect BFM slave to DUT master port
+    assign s_chdr[i].tdata        = m_rfnoc_chdr_tdata[CHDR_W*i+:CHDR_W];
+    assign s_chdr[i].tlast        = m_rfnoc_chdr_tlast[i];
+    assign s_chdr[i].tvalid       = m_rfnoc_chdr_tvalid[i];
+    assign m_rfnoc_chdr_tready[i] = s_chdr[i].tready;
+  end
+
+  rfnoc_block_duc #(
+    .THIS_PORTID    (THIS_PORTID),
+    .CHDR_W         (CHDR_W),
+    .NUM_PORTS      (NUM_PORTS),
+    .MTU            (MTU),
+    .NUM_HB         (NUM_HB),
+    .CIC_MAX_INTERP (CIC_MAX_INTERP)
+  ) rfnoc_block_duc_i (
+    .rfnoc_chdr_clk          (backend.chdr_clk),
+    .ce_clk                  (ce_clk),
+    .s_rfnoc_chdr_tdata      (s_rfnoc_chdr_tdata),
+    .s_rfnoc_chdr_tlast      (s_rfnoc_chdr_tlast),
+    .s_rfnoc_chdr_tvalid     (s_rfnoc_chdr_tvalid),
+    .s_rfnoc_chdr_tready     (s_rfnoc_chdr_tready),
+    .m_rfnoc_chdr_tdata      (m_rfnoc_chdr_tdata),
+    .m_rfnoc_chdr_tlast      (m_rfnoc_chdr_tlast),
+    .m_rfnoc_chdr_tvalid     (m_rfnoc_chdr_tvalid),
+    .m_rfnoc_chdr_tready     (m_rfnoc_chdr_tready),
+    .rfnoc_core_config       (backend.cfg),
+    .rfnoc_core_status       (backend.sts),
+    .rfnoc_ctrl_clk          (backend.ctrl_clk),
+    .s_rfnoc_ctrl_tdata      (m_ctrl.tdata),
+    .s_rfnoc_ctrl_tlast      (m_ctrl.tlast),
+    .s_rfnoc_ctrl_tvalid     (m_ctrl.tvalid),
+    .s_rfnoc_ctrl_tready     (m_ctrl.tready),
+    .m_rfnoc_ctrl_tdata      (s_ctrl.tdata),
+    .m_rfnoc_ctrl_tlast      (s_ctrl.tlast),
+    .m_rfnoc_ctrl_tvalid     (s_ctrl.tvalid),
+    .m_rfnoc_ctrl_tready     (s_ctrl.tready)
+  );
+
+
+  //---------------------------------------------------------------------------
+  // Helper Tasks
+  //---------------------------------------------------------------------------
+
+  // Translate the desired register access to a ctrlport write request.
+  task automatic write_reg(int port, byte unsigned addr, bit [31:0] value);
+    blk_ctrl.reg_write(256*8*port + addr*8, value);
+  endtask : write_reg
+
+
+  // Translate the desired register access to a ctrlport read request.
+  task automatic read_user_reg(int port, byte unsigned addr, output logic [63:0] value);
+    blk_ctrl.reg_read(256*8*port + addr*8 + 0, value[31: 0]);
+    blk_ctrl.reg_read(256*8*port + addr*8 + 4, value[63:32]);
+  endtask : read_user_reg
+
+
+  // Set the interpolation rate
+  task automatic set_interp_rate(int port, int interp_rate);
+    begin
+      logic [7:0] cic_rate = 8'd0;
+      logic [7:0] hb_enables = 2'b0;
+
+      int _interp_rate = interp_rate;
+
+      // Calculate which half bands to enable and whatever is left over set the CIC
+      while ((_interp_rate[0] == 0) && (hb_enables < NUM_HB)) begin
+        hb_enables += 1'b1;
+        _interp_rate = _interp_rate >> 1;
+      end
+
+      // CIC rate cannot be set to 0
+      cic_rate = (_interp_rate[7:0] == 8'd0) ? 8'd1 : _interp_rate[7:0];
+      `ASSERT_ERROR(hb_enables <= NUM_HB, "Enabled halfbands may not exceed total number of half bands.");
+      `ASSERT_ERROR(cic_rate > 0 && cic_rate <= CIC_MAX_INTERP,
+       "CIC Interpolation rate must be positive, not exceed the max cic interpolation rate, and cannot equal 0!");
+
+      // Setup DUC
+      $display("Set interpolation to %0d", interp_rate);
+      $display("- Number of enabled HBs: %0d", hb_enables);
+      $display("- CIC Rate:              %0d", cic_rate);
+      write_reg(port, SR_M_ADDR, interp_rate);                 // Set interpolation rate in AXI rate change
+      write_reg(port, SR_INTERP_ADDR, {hb_enables, cic_rate}); // Enable HBs, set CIC rate
+    end
+  endtask
+
+
+  // Test sending packets of ones
+  task automatic send_ones(int port, int interp_rate, bit has_time);
+    begin
+      const bit [63:0] start_time = 64'h0123456789ABCDEF;
+
+      set_interp_rate(port, interp_rate);
+
+      // Setup DUC
+      write_reg(port, SR_CONFIG_ADDR, 32'd1);         // Enable clear EOB
+      write_reg(port, SR_FREQ_ADDR, 32'd0);           // CORDIC phase increment
+      write_reg(port, SR_SCALE_IQ_ADDR, (1 << 14));   // Scaling, set to 1
+
+      fork
+        begin
+          chdr_word_t send_payload[$];
+          packet_info_t pkt_info;
+
+          $display("Send ones");
+
+          // Generate a payload of all ones
+          send_payload = {};
+          for (int i = 0; i < PKT_SIZE_BYTES/8; i++) begin
+            send_payload.push_back({16'hffff, 16'hffff, 16'hffff, 16'hffff});
+          end
+
+          // Send two packets with EOB on the second packet
+          pkt_info = 0;
+          pkt_info.has_time  = has_time;
+          pkt_info.timestamp = start_time;
+          blk_ctrl.send_packets(port, send_payload, /*data_bytes*/, /*metadata*/, pkt_info);
+          pkt_info.timestamp = start_time + SPP;
+          pkt_info.eob = 1;
+          blk_ctrl.send_packets(port, send_payload, /*data_bytes*/, /*metadata*/, pkt_info);
+          
+          $display("Send ones complete");
+        end
+        begin
+          string s;
+          chdr_word_t samples;
+          int data_bytes;
+          chdr_word_t recv_payload[$];
+          chdr_word_t metadata[$];
+          packet_info_t pkt_info;
+
+          $display("Check incoming samples");
+          for (int i = 0; i < 2*interp_rate; i++) begin
+            blk_ctrl.recv_adv(port, recv_payload, data_bytes, metadata, pkt_info);
+
+            // Check the packet size
+            $sformat(s, "incorrect (drop) packet size! expected: %0d, actual: %0d", PKT_SIZE_BYTES/8, recv_payload.size());
+            `ASSERT_ERROR(recv_payload.size() == PKT_SIZE_BYTES/8, s);
+
+            // Check the timestamp
+            if (has_time) begin
+              bit [63:0] expected_time;
+              // Calculate what the timestamp should be
+              expected_time = start_time + i * SPP;
+              $sformat(s, "Incorrect timestamp: has_time = %0d, timestamp = 0x%0X, expected 0x%0X",
+                       pkt_info.has_time, pkt_info.timestamp, expected_time);
+              `ASSERT_ERROR(pkt_info.has_time == 1 && pkt_info.timestamp == expected_time, s);
+            end else begin
+              `ASSERT_ERROR(pkt_info.has_time == 0, "Packet has timestamp when it shouldn't");
+            end
+
+            // Check EOB
+            if (i == 2*interp_rate-1) begin
+              `ASSERT_ERROR(pkt_info.eob == 1, "EOB not set on last packet");
+            end else begin
+              `ASSERT_ERROR(pkt_info.eob == 0, 
+                $sformatf("EOB unexpectedly set on packet %0d", i));
+            end
+
+            // Check the sample values
+            samples = 64'd0;
+            for (int j = 0; j < PKT_SIZE_BYTES/8; j++) begin
+              samples = recv_payload[j];
+              $sformat(s, "Ramp word %0d invalid! Expected a real value, Received: %0d", 2*j, samples);
+              `ASSERT_ERROR(samples >= 0, s);
+            end
+          end
+          $display("Check complete");
+        end
+      join
+    end
+  endtask
+
+
+  //---------------------------------------------------------------------------
+  // Test Process
+  //---------------------------------------------------------------------------
+
+  initial begin : tb_main
+    const int port = 0;
+    test.start_tb("rfnoc_block_duc_tb");
+
+    // Start the BFMs running
+    blk_ctrl.run();
+
+
+    //-------------------------------------------------------------------------
+    // Reset
+    //-------------------------------------------------------------------------
+
+    test.start_test("Wait for Reset", 10us);
+    fork
+      blk_ctrl.reset_chdr();
+      blk_ctrl.reset_ctrl();
+    join;
+    test.end_test();
+
+
+    //-------------------------------------------------------------------------
+    // Check NoC ID and Block Info
+    //-------------------------------------------------------------------------
+
+    test.start_test("Verify Block Info", 2us);
+    `ASSERT_ERROR(blk_ctrl.get_noc_id() == rfnoc_block_duc_i.NOC_ID, "Incorrect NOC_ID value");
+    `ASSERT_ERROR(blk_ctrl.get_num_data_i() == NUM_PORTS, "Incorrect NUM_DATA_I value");
+    `ASSERT_ERROR(blk_ctrl.get_num_data_o() == NUM_PORTS, "Incorrect NUM_DATA_O value");
+    `ASSERT_ERROR(blk_ctrl.get_mtu() == MTU, "Incorrect MTU value");
+    test.end_test();
+
+
+    //-------------------------------------------------------------------------
+    // Test read-back regs
+    //-------------------------------------------------------------------------
+
+    begin
+      logic [63:0] val64;
+      test.start_test("Test registers", 10us);
+      read_user_reg(port, RB_NUM_HB, val64);
+      `ASSERT_ERROR(val64 == NUM_HB, "Register NUM_HB didn't read back expected value");
+      read_user_reg(port, RB_CIC_MAX_INTERP, val64);
+      `ASSERT_ERROR(val64 ==CIC_MAX_INTERP, "Register RB_CIC_MAX_INTERP didn't read back expected value");
+      test.end_test();
+    end
+
+
+    //-------------------------------------------------------------------------
+    // Test various interpolation rates (no timestamp)
+    //-------------------------------------------------------------------------
+
+    begin
+      test.start_test("Test interpolation rates (with timestamp)", 0.5ms);
+
+      $display("Note: This test will take a long time!");
+      send_ones(port, 1,  1);   // HBs enabled: 0, CIC rate: 1
+      send_ones(port, 2,  1);   // HBs enabled: 1, CIC rate: 1
+      send_ones(port, 3,  1);   // HBs enabled: 0, CIC rate: 3
+      send_ones(port, 4,  1);   // HBs enabled: 2, CIC rate: 1
+      send_ones(port, 6,  1);   // HBs enabled: 1, CIC rate: 3
+      send_ones(port, 8,  1);   // HBs enabled: 2, CIC rate: 2
+      send_ones(port, 12, 1);   // HBs enabled: 2, CIC rate: 3
+      send_ones(port, 13, 1);   // HBs enabled: 0, CIC rate: 13
+      send_ones(port, 16, 1);   // HBs enabled: 2, CIC rate: 3
+      send_ones(port, 40, 1);   // HBs enabled: 2, CIC rate: 20
+
+      test.end_test();
+    end
+
+
+    //-------------------------------------------------------------------------
+    // Test various interpolation rates (without timestamp)
+    //-------------------------------------------------------------------------
+
+    begin
+      test.start_test("Test interpolation rates (no timestamp)", 0.5ms);
+
+      send_ones(port, 1,  0);   // HBs enabled: 0, CIC rate: 1
+      send_ones(port, 3,  0);   // HBs enabled: 0, CIC rate: 3
+
+      test.end_test();
+    end
+
+
+    //-------------------------------------------------------------------------
+    // Test timed tune
+    //-------------------------------------------------------------------------
+
+    // This test has not been implemented because the RFNoC FFT has not been
+    // ported yet.
+
+
+    //-------------------------------------------------------------------------
+    // Finish
+    //-------------------------------------------------------------------------
+
+    // End the TB, but don't $finish, since we don't want to kill other
+    // instances of this testbench that may be running.
+    test.end_tb(0);
+
+    // Kill the clocks to end this instance of the testbench
+    rfnoc_chdr_clk_gen.kill();
+    rfnoc_ctrl_clk_gen.kill();
+    duc_clk_gen.kill();
+  end
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fft/Makefile b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fft/Makefile
new file mode 100644
index 000000000..868246fbd
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fft/Makefile
@@ -0,0 +1,62 @@
+#
+# Copyright 2019 Ettus Research, A National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+#-------------------------------------------------
+# Top-of-Makefile
+#-------------------------------------------------
+# Define BASE_DIR to point to the "top" dir
+BASE_DIR = $(abspath ../../../../top)
+# Include viv_sim_preamble after defining BASE_DIR
+include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
+
+#-------------------------------------------------
+# IP Specific
+#-------------------------------------------------
+# If simulation contains IP, define the IP_DIR and point
+# it to the base level IP directory
+LIB_IP_DIR = $(BASE_DIR)/../lib/ip
+
+# Include makefiles and sources for all IP components
+# *after* defining the LIB_IP_DIR
+include $(LIB_IP_DIR)/axi_fft/Makefile.inc
+include $(LIB_IP_DIR)/complex_to_magphase/Makefile.inc
+
+DESIGN_SRCS += $(abspath \
+$(LIB_IP_AXI_FFT_OUTS) \
+)
+
+#-------------------------------------------------
+# Design Specific
+#-------------------------------------------------
+# Include makefiles and sources for the DUT and its dependencies
+include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs
+include $(BASE_DIR)/../lib/rfnoc/utils/Makefile.srcs
+include Makefile.srcs
+
+DESIGN_SRCS += $(abspath \
+$(RFNOC_CORE_SRCS) \
+$(RFNOC_UTIL_SRCS) \
+$(RFNOC_OOT_SRCS) \
+)
+
+#-------------------------------------------------
+# Testbench Specific
+#-------------------------------------------------
+# Define only one toplevel module
+SIM_TOP = rfnoc_block_fft_tb
+
+# Add test bench, user design under test, and
+# additional user created files
+SIM_SRCS = \
+$(abspath rfnoc_block_fft_tb.sv)
+
+#-------------------------------------------------
+# Bottom-of-Makefile
+#-------------------------------------------------
+# Include all simulator specific makefiles here
+# Each should define a unique target to simulate
+# e.g. xsim, vsim, etc and a common "clean" target
+include $(BASE_DIR)/../tools/make/viv_simulator.mak
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fft/Makefile.srcs b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fft/Makefile.srcs
new file mode 100644
index 000000000..21ba967f2
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fft/Makefile.srcs
@@ -0,0 +1,10 @@
+#
+# Copyright 2019 Ettus Research, A National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+RFNOC_OOT_SRCS += $(abspath $(addprefix $(BASE_DIR)/../lib/rfnoc/blocks/rfnoc_block_fft/, \
+noc_shell_fft.v \
+rfnoc_block_fft.v \
+))
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fft/noc_shell_fft.v b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fft/noc_shell_fft.v
new file mode 100644
index 000000000..37a60ef31
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fft/noc_shell_fft.v
@@ -0,0 +1,294 @@
+//
+// Copyright 2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: noc_shell_fft
+//
+
+module noc_shell_fft #(
+  parameter [31:0] NOC_ID          = 32  'h0,
+  parameter [ 9:0] THIS_PORTID     = 10  'd0,
+  parameter        CHDR_W          = 64,
+  parameter [ 0:0] CTRLPORT_SLV_EN = 1,
+  parameter [ 0:0] CTRLPORT_MST_EN = 1,
+  parameter        SYNC_CLKS       = 0,
+  parameter [ 5:0] NUM_DATA_I      = 1,
+  parameter [ 5:0] NUM_DATA_O      = 1,
+  parameter        ITEM_W          = 32,
+  parameter        NIPC            = 2,
+  parameter        PYLD_FIFO_SIZE  = 5,
+  parameter        CTXT_FIFO_SIZE  = 5,
+  parameter        MTU             = 10
+) (
+  //---------------------------------------------------------------------------
+  // Framework Interface
+  //---------------------------------------------------------------------------
+
+  // RFNoC Framework Clocks and Resets
+  input  wire                           rfnoc_chdr_clk,
+  output wire                           rfnoc_chdr_rst,
+  input  wire                           rfnoc_ctrl_clk,
+  output wire                           rfnoc_ctrl_rst,
+  // RFNoC Backend Interface
+  input  wire [                  511:0] rfnoc_core_config,
+  output wire [                  511:0] rfnoc_core_status,
+  // CHDR Input Ports (from framework)
+  input  wire [(CHDR_W*NUM_DATA_I)-1:0] s_rfnoc_chdr_tdata,
+  input  wire [         NUM_DATA_I-1:0] s_rfnoc_chdr_tlast,
+  input  wire [         NUM_DATA_I-1:0] s_rfnoc_chdr_tvalid,
+  output wire [         NUM_DATA_I-1:0] s_rfnoc_chdr_tready,
+  // CHDR Output Ports (to framework)
+  output wire [(CHDR_W*NUM_DATA_O)-1:0] m_rfnoc_chdr_tdata,
+  output wire [         NUM_DATA_O-1:0] m_rfnoc_chdr_tlast,
+  output wire [         NUM_DATA_O-1:0] m_rfnoc_chdr_tvalid,
+  input  wire [         NUM_DATA_O-1:0] m_rfnoc_chdr_tready,
+  // AXIS-Ctrl Input Port (from framework)
+  input  wire [                   31:0] s_rfnoc_ctrl_tdata,
+  input  wire                           s_rfnoc_ctrl_tlast,
+  input  wire                           s_rfnoc_ctrl_tvalid,
+  output wire                           s_rfnoc_ctrl_tready,
+  // AXIS-Ctrl Output Port (to framework)
+  output wire [                   31:0] m_rfnoc_ctrl_tdata,
+  output wire                           m_rfnoc_ctrl_tlast,
+  output wire                           m_rfnoc_ctrl_tvalid,
+  input  wire                           m_rfnoc_ctrl_tready,
+
+  //---------------------------------------------------------------------------
+  // Client Control Port Interface
+  //---------------------------------------------------------------------------
+
+  // Clock
+  input  wire        ctrlport_clk,
+  input  wire        ctrlport_rst,
+  // Master
+  output wire        m_ctrlport_req_wr,
+  output wire        m_ctrlport_req_rd,
+  output wire [19:0] m_ctrlport_req_addr,
+  output wire [31:0] m_ctrlport_req_data,
+  output wire [ 3:0] m_ctrlport_req_byte_en,
+  output wire        m_ctrlport_req_has_time,
+  output wire [63:0] m_ctrlport_req_time,
+  input  wire        m_ctrlport_resp_ack,
+  input  wire [ 1:0] m_ctrlport_resp_status,
+  input  wire [31:0] m_ctrlport_resp_data,
+  // Slave
+  input  wire        s_ctrlport_req_wr,
+  input  wire        s_ctrlport_req_rd,
+  input  wire [19:0] s_ctrlport_req_addr,
+  input  wire [ 9:0] s_ctrlport_req_portid,
+  input  wire [15:0] s_ctrlport_req_rem_epid,
+  input  wire [ 9:0] s_ctrlport_req_rem_portid,
+  input  wire [31:0] s_ctrlport_req_data,
+  input  wire [ 3:0] s_ctrlport_req_byte_en,
+  input  wire        s_ctrlport_req_has_time,
+  input  wire [63:0] s_ctrlport_req_time,
+  output wire        s_ctrlport_resp_ack,
+  output wire [ 1:0] s_ctrlport_resp_status,
+  output wire [31:0] s_ctrlport_resp_data,
+
+  //---------------------------------------------------------------------------
+  // Client Data Interface
+  //---------------------------------------------------------------------------
+
+  // Clock
+  input wire axis_data_clk,
+  input wire axis_data_rst,
+
+  // Output data stream (to user logic)
+  output wire [(NUM_DATA_I*ITEM_W*NIPC)-1:0] m_axis_payload_tdata,
+  output wire [       (NUM_DATA_I*NIPC)-1:0] m_axis_payload_tkeep,
+  output wire [              NUM_DATA_I-1:0] m_axis_payload_tlast,
+  output wire [              NUM_DATA_I-1:0] m_axis_payload_tvalid,
+  input  wire [              NUM_DATA_I-1:0] m_axis_payload_tready,
+
+  // Input data stream (from user logic)
+  input  wire [(NUM_DATA_O*ITEM_W*NIPC)-1:0] s_axis_payload_tdata,
+  input  wire [       (NUM_DATA_O*NIPC)-1:0] s_axis_payload_tkeep,
+  input  wire [              NUM_DATA_O-1:0] s_axis_payload_tlast,
+  input  wire [              NUM_DATA_O-1:0] s_axis_payload_tvalid,
+  output wire [              NUM_DATA_O-1:0] s_axis_payload_tready,
+
+  // Output context stream (to user logic)
+  output wire [(NUM_DATA_I*CHDR_W)-1:0] m_axis_context_tdata,
+  output wire [     (4*NUM_DATA_I)-1:0] m_axis_context_tuser,
+  output wire [         NUM_DATA_I-1:0] m_axis_context_tlast,
+  output wire [         NUM_DATA_I-1:0] m_axis_context_tvalid,
+  input  wire [         NUM_DATA_I-1:0] m_axis_context_tready,
+
+  // Input context stream (from user logic)
+  input  wire [(NUM_DATA_O*CHDR_W)-1:0] s_axis_context_tdata,
+  input  wire [     (4*NUM_DATA_O)-1:0] s_axis_context_tuser,
+  input  wire [         NUM_DATA_O-1:0] s_axis_context_tlast,
+  input  wire [         NUM_DATA_O-1:0] s_axis_context_tvalid,
+  output wire [         NUM_DATA_O-1:0] s_axis_context_tready
+);
+  
+  localparam CTRL_FIFO_SIZE = 5;
+
+
+  //---------------------------------------------------------------------------
+  //  Backend Interface
+  //---------------------------------------------------------------------------
+
+  wire         data_i_flush_en;
+  wire [31:0]  data_i_flush_timeout;
+  wire [63:0]  data_i_flush_active;
+  wire [63:0]  data_i_flush_done;
+  wire         data_o_flush_en;
+  wire [31:0]  data_o_flush_timeout;
+  wire [63:0]  data_o_flush_active;
+  wire [63:0]  data_o_flush_done;
+
+  backend_iface #(
+    .NOC_ID        (NOC_ID),
+    .NUM_DATA_I    (NUM_DATA_I),
+    .NUM_DATA_O    (NUM_DATA_O),
+    .CTRL_FIFOSIZE (CTRL_FIFO_SIZE),
+    .MTU           (MTU)
+  ) backend_iface_i (
+    .rfnoc_chdr_clk       (rfnoc_chdr_clk),
+    .rfnoc_ctrl_clk       (rfnoc_ctrl_clk),
+    .rfnoc_core_config    (rfnoc_core_config),
+    .rfnoc_core_status    (rfnoc_core_status),
+    .rfnoc_chdr_rst       (rfnoc_chdr_rst),
+    .rfnoc_ctrl_rst       (rfnoc_ctrl_rst),
+    .data_i_flush_en      (data_i_flush_en),
+    .data_i_flush_timeout (data_i_flush_timeout),
+    .data_i_flush_active  (data_i_flush_active),
+    .data_i_flush_done    (data_i_flush_done),
+    .data_o_flush_en      (data_o_flush_en),
+    .data_o_flush_timeout (data_o_flush_timeout),
+    .data_o_flush_active  (data_o_flush_active),
+    .data_o_flush_done    (data_o_flush_done)
+  );
+
+  //---------------------------------------------------------------------------
+  //  Control Path
+  //---------------------------------------------------------------------------
+
+  ctrlport_endpoint #(
+    .THIS_PORTID              (THIS_PORTID    ),
+    .SYNC_CLKS                (0              ),
+    .AXIS_CTRL_MST_EN         (CTRLPORT_SLV_EN),
+    .AXIS_CTRL_SLV_EN         (CTRLPORT_MST_EN),
+    .SLAVE_FIFO_SIZE          (CTRL_FIFO_SIZE )
+  ) ctrlport_ep_i (
+    .rfnoc_ctrl_clk           (rfnoc_ctrl_clk           ),
+    .rfnoc_ctrl_rst           (rfnoc_ctrl_rst           ),
+    .ctrlport_clk             (ctrlport_clk             ),
+    .ctrlport_rst             (ctrlport_rst             ),
+    .s_rfnoc_ctrl_tdata       (s_rfnoc_ctrl_tdata       ),
+    .s_rfnoc_ctrl_tlast       (s_rfnoc_ctrl_tlast       ),
+    .s_rfnoc_ctrl_tvalid      (s_rfnoc_ctrl_tvalid      ),
+    .s_rfnoc_ctrl_tready      (s_rfnoc_ctrl_tready      ),
+    .m_rfnoc_ctrl_tdata       (m_rfnoc_ctrl_tdata       ),
+    .m_rfnoc_ctrl_tlast       (m_rfnoc_ctrl_tlast       ),
+    .m_rfnoc_ctrl_tvalid      (m_rfnoc_ctrl_tvalid      ),
+    .m_rfnoc_ctrl_tready      (m_rfnoc_ctrl_tready      ),
+    .m_ctrlport_req_wr        (m_ctrlport_req_wr        ),
+    .m_ctrlport_req_rd        (m_ctrlport_req_rd        ),
+    .m_ctrlport_req_addr      (m_ctrlport_req_addr      ),
+    .m_ctrlport_req_data      (m_ctrlport_req_data      ),
+    .m_ctrlport_req_byte_en   (m_ctrlport_req_byte_en   ),
+    .m_ctrlport_req_has_time  (m_ctrlport_req_has_time  ),
+    .m_ctrlport_req_time      (m_ctrlport_req_time      ),
+    .m_ctrlport_resp_ack      (m_ctrlport_resp_ack      ),
+    .m_ctrlport_resp_status   (m_ctrlport_resp_status   ),
+    .m_ctrlport_resp_data     (m_ctrlport_resp_data     ),
+    .s_ctrlport_req_wr        (s_ctrlport_req_wr        ),
+    .s_ctrlport_req_rd        (s_ctrlport_req_rd        ),
+    .s_ctrlport_req_addr      (s_ctrlport_req_addr      ),
+    .s_ctrlport_req_portid    (s_ctrlport_req_portid    ),
+    .s_ctrlport_req_rem_epid  (s_ctrlport_req_rem_epid  ),
+    .s_ctrlport_req_rem_portid(s_ctrlport_req_rem_portid),
+    .s_ctrlport_req_data      (s_ctrlport_req_data      ),
+    .s_ctrlport_req_byte_en   (s_ctrlport_req_byte_en   ),
+    .s_ctrlport_req_has_time  (s_ctrlport_req_has_time  ),
+    .s_ctrlport_req_time      (s_ctrlport_req_time      ),
+    .s_ctrlport_resp_ack      (s_ctrlport_resp_ack      ),
+    .s_ctrlport_resp_status   (s_ctrlport_resp_status   ),
+    .s_ctrlport_resp_data     (s_ctrlport_resp_data     )
+  );
+
+  //---------------------------------------------------------------------------
+  //  Data Path
+  //---------------------------------------------------------------------------
+
+  genvar i;
+  generate
+
+    for (i = 0; i < NUM_DATA_I; i = i + 1) begin: chdr_to_data
+      chdr_to_axis_pyld_ctxt #(
+        .CHDR_W               (CHDR_W        ),
+        .ITEM_W               (ITEM_W        ),
+        .NIPC                 (NIPC          ),
+        .SYNC_CLKS            (SYNC_CLKS     ),
+        .CONTEXT_FIFO_SIZE    (CTXT_FIFO_SIZE),
+        .PAYLOAD_FIFO_SIZE    (PYLD_FIFO_SIZE),
+        .CONTEXT_PREFETCH_EN  (1             )
+      ) chdr_to_axis_pyld_ctxt_i (
+        .axis_chdr_clk        (rfnoc_chdr_clk                                       ),
+        .axis_chdr_rst        (rfnoc_chdr_rst                                       ),
+        .axis_data_clk        (axis_data_clk                                        ),
+        .axis_data_rst        (axis_data_rst                                        ),
+        .s_axis_chdr_tdata    (s_rfnoc_chdr_tdata   [(i*CHDR_W)+:CHDR_W]            ),
+        .s_axis_chdr_tlast    (s_rfnoc_chdr_tlast   [i]                             ),
+        .s_axis_chdr_tvalid   (s_rfnoc_chdr_tvalid  [i]                             ),
+        .s_axis_chdr_tready   (s_rfnoc_chdr_tready  [i]                             ),
+        .m_axis_payload_tdata (m_axis_payload_tdata [(i*ITEM_W*NIPC)+:(ITEM_W*NIPC)]),
+        .m_axis_payload_tkeep (m_axis_payload_tkeep [(i*NIPC)+:NIPC]                ),
+        .m_axis_payload_tlast (m_axis_payload_tlast [i]                             ),
+        .m_axis_payload_tvalid(m_axis_payload_tvalid[i]                             ),
+        .m_axis_payload_tready(m_axis_payload_tready[i]                             ),
+        .m_axis_context_tdata (m_axis_context_tdata [(i*CHDR_W)+:(CHDR_W)]          ),
+        .m_axis_context_tuser (m_axis_context_tuser [(i*4)+:4]                      ),
+        .m_axis_context_tlast (m_axis_context_tlast [i]                             ),
+        .m_axis_context_tvalid(m_axis_context_tvalid[i]                             ),
+        .m_axis_context_tready(m_axis_context_tready[i]                             ),
+        .flush_en             (data_i_flush_en                                      ),
+        .flush_timeout        (data_i_flush_timeout                                 ),
+        .flush_active         (data_i_flush_active  [i]                             ),
+        .flush_done           (data_i_flush_done    [i]                             )
+      );
+    end
+
+    for (i = 0; i < NUM_DATA_O; i = i + 1) begin: data_to_chdr
+      axis_pyld_ctxt_to_chdr #(
+        .CHDR_W               (CHDR_W        ),
+        .ITEM_W               (ITEM_W        ),
+        .NIPC                 (NIPC          ),
+        .SYNC_CLKS            (SYNC_CLKS     ),
+        .CONTEXT_FIFO_SIZE    (CTXT_FIFO_SIZE),
+        .PAYLOAD_FIFO_SIZE    (PYLD_FIFO_SIZE),
+        .CONTEXT_PREFETCH_EN  (1             ),
+        .MTU                  (MTU           )
+      ) axis_pyld_ctxt_to_chdr_i (
+        .axis_chdr_clk        (rfnoc_chdr_clk                                       ),
+        .axis_chdr_rst        (rfnoc_chdr_rst                                       ),
+        .axis_data_clk        (axis_data_clk                                        ),
+        .axis_data_rst        (axis_data_rst                                        ),
+        .m_axis_chdr_tdata    (m_rfnoc_chdr_tdata   [(i*CHDR_W)+:CHDR_W]            ),
+        .m_axis_chdr_tlast    (m_rfnoc_chdr_tlast   [i]                             ),
+        .m_axis_chdr_tvalid   (m_rfnoc_chdr_tvalid  [i]                             ),
+        .m_axis_chdr_tready   (m_rfnoc_chdr_tready  [i]                             ),
+        .s_axis_payload_tdata (s_axis_payload_tdata [(i*ITEM_W*NIPC)+:(ITEM_W*NIPC)]),
+        .s_axis_payload_tkeep (s_axis_payload_tkeep [(i*NIPC)+:NIPC]                ),
+        .s_axis_payload_tlast (s_axis_payload_tlast [i]                             ),
+        .s_axis_payload_tvalid(s_axis_payload_tvalid[i]                             ),
+        .s_axis_payload_tready(s_axis_payload_tready[i]                             ),
+        .s_axis_context_tdata (s_axis_context_tdata [(i*CHDR_W)+:(CHDR_W)]          ),
+        .s_axis_context_tuser (s_axis_context_tuser [(i*4)+:4]                      ),
+        .s_axis_context_tlast (s_axis_context_tlast [i]                             ),
+        .s_axis_context_tvalid(s_axis_context_tvalid[i]                             ),
+        .s_axis_context_tready(s_axis_context_tready[i]                             ),
+        .framer_errors        (                                                     ),
+        .flush_en             (data_o_flush_en                                      ),
+        .flush_timeout        (data_o_flush_timeout                                 ),
+        .flush_active         (data_o_flush_active  [i]                             ),
+        .flush_done           (data_o_flush_done    [i]                             )
+      );
+    end
+  endgenerate
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fft/rfnoc_block_fft.v b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fft/rfnoc_block_fft.v
new file mode 100644
index 000000000..76ae37524
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fft/rfnoc_block_fft.v
@@ -0,0 +1,559 @@
+//
+// Copyright 2019 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: rfnoc_block_fft
+//
+// Description:  An FFT block for RFNoC.
+//
+// Parameters:
+//
+//   THIS_PORTID   : Control crossbar port to which this block is connected
+//   CHDR_W        : AXIS CHDR interface data width
+//   MTU           : Maximum transmission unit (i.e., maximum packet size) in
+//                   CHDR words is 2**MTU.
+//   EN_MAGNITUDE_OUT : CORDIC based magnitude calculation
+//   EN_MAGNITUDE_APPROX_OUT : Multipler-less, lower resource usage
+//   EN_MAGNITUDE_SQ_OUT : Magnitude squared
+//   EN_FFT_SHIFT : Center zero frequency bin
+//
+
+module rfnoc_block_fft #(
+  parameter THIS_PORTID   = 0,
+  parameter CHDR_W        = 64,
+  parameter MTU           = 10,
+
+  parameter EN_MAGNITUDE_OUT = 0,        
+  parameter EN_MAGNITUDE_APPROX_OUT = 1,
+  parameter EN_MAGNITUDE_SQ_OUT = 1,    
+  parameter EN_FFT_SHIFT = 1
+  )
+(
+  //---------------------------------------------------------------------------
+  // AXIS CHDR Port
+  //---------------------------------------------------------------------------
+
+  input wire rfnoc_chdr_clk,
+  input wire ce_clk,
+
+  // CHDR inputs from framework
+  input  wire [CHDR_W-1:0] s_rfnoc_chdr_tdata,
+  input  wire s_rfnoc_chdr_tlast,
+  input  wire s_rfnoc_chdr_tvalid,
+  output wire s_rfnoc_chdr_tready,
+
+  // CHDR outputs to framework
+  output wire [CHDR_W-1:0] m_rfnoc_chdr_tdata,
+  output wire m_rfnoc_chdr_tlast,
+  output wire m_rfnoc_chdr_tvalid,
+  input  wire m_rfnoc_chdr_tready,
+
+  // Backend interface
+  input  wire [511:0] rfnoc_core_config,
+  output wire [511:0] rfnoc_core_status,
+
+  //---------------------------------------------------------------------------
+  // AXIS CTRL Port
+  //---------------------------------------------------------------------------
+
+  input wire rfnoc_ctrl_clk,
+
+  // CTRL port requests from framework
+  input  wire [31:0] s_rfnoc_ctrl_tdata,
+  input  wire        s_rfnoc_ctrl_tlast,
+  input  wire        s_rfnoc_ctrl_tvalid,
+  output wire        s_rfnoc_ctrl_tready,
+
+  // CTRL port requests to framework
+  output wire [31:0] m_rfnoc_ctrl_tdata,
+  output wire        m_rfnoc_ctrl_tlast,
+  output wire        m_rfnoc_ctrl_tvalid,
+  input  wire        m_rfnoc_ctrl_tready
+);
+
+  // These are the only supported values for now
+  localparam ITEM_W = 32;
+  localparam NIPC   = 1;
+
+  localparam NOC_ID = 32'hFF70_0000;
+
+  `include "../../core/rfnoc_axis_ctrl_utils.vh"
+
+  //---------------------------------------------------------------------------
+  // Signal Declarations
+  //---------------------------------------------------------------------------
+
+  wire rfnoc_chdr_rst;
+
+  wire        ctrlport_req_wr;
+  wire        ctrlport_req_rd;
+  wire [19:0] ctrlport_req_addr;
+  wire [31:0] ctrlport_req_data;
+  wire        ctrlport_req_has_time;
+  wire [63:0] ctrlport_req_time;
+  wire        ctrlport_resp_ack;
+  wire [31:0] ctrlport_resp_data;
+
+  wire [ITEM_W-1:0] axis_to_fft_tdata;
+  wire  axis_to_fft_tlast;
+  wire  axis_to_fft_tvalid;
+  wire  axis_to_fft_tready;
+
+  wire [ITEM_W-1:0] axis_from_fft_tdata;
+  wire  axis_from_fft_tlast;
+  wire  axis_from_fft_tvalid;
+  wire  axis_from_fft_tready;
+
+  wire [CHDR_W-1:0] m_axis_context_tdata;
+  wire [       3:0] m_axis_context_tuser;
+  wire [       0:0] m_axis_context_tlast;
+  wire [       0:0] m_axis_context_tvalid;
+  wire [       0:0] m_axis_context_tready;
+
+  wire [CHDR_W-1:0] s_axis_context_tdata;
+  wire [       3:0] s_axis_context_tuser;
+  wire [       0:0] s_axis_context_tlast;
+  wire [       0:0] s_axis_context_tvalid;
+  wire [       0:0] s_axis_context_tready;
+
+  wire ce_rst;
+
+  // Cross the CHDR reset to the radio_clk domain
+  pulse_synchronizer #(
+    .MODE ("POSEDGE")
+  ) ctrl_rst_sync_i (
+    .clk_a   (rfnoc_chdr_clk),
+    .rst_a   (1'b0),
+    .pulse_a (rfnoc_chdr_rst),
+    .busy_a  (),
+    .clk_b   (ce_clk),
+    .pulse_b (ce_rst)
+  );
+
+  //---------------------------------------------------------------------------
+  // NoC Shell
+  //---------------------------------------------------------------------------
+
+  noc_shell_fft #(
+    .NOC_ID         (NOC_ID     ),
+    .THIS_PORTID    (THIS_PORTID),
+    .CHDR_W         (CHDR_W     ),
+    .CTRLPORT_SLV_EN(0          ),
+    .CTRLPORT_MST_EN(1          ),
+    .SYNC_CLKS      (0          ),
+    .NUM_DATA_I     (1          ),
+    .NUM_DATA_O     (1          ),
+    .ITEM_W         (ITEM_W     ),
+    .NIPC           (NIPC       ),
+    .PYLD_FIFO_SIZE (MTU        ),
+    .CTXT_FIFO_SIZE (1          ),
+    .MTU            (MTU        )
+  ) noc_shell_fft_i (
+    .rfnoc_chdr_clk           (rfnoc_chdr_clk       ),
+    .rfnoc_chdr_rst           (rfnoc_chdr_rst       ),
+    .rfnoc_ctrl_clk           (rfnoc_ctrl_clk       ),
+    .rfnoc_ctrl_rst           (                     ),
+    .rfnoc_core_config        (rfnoc_core_config    ),
+    .rfnoc_core_status        (rfnoc_core_status    ),
+    .s_rfnoc_chdr_tdata       (s_rfnoc_chdr_tdata   ),
+    .s_rfnoc_chdr_tlast       (s_rfnoc_chdr_tlast   ),
+    .s_rfnoc_chdr_tvalid      (s_rfnoc_chdr_tvalid  ),
+    .s_rfnoc_chdr_tready      (s_rfnoc_chdr_tready  ),
+    .m_rfnoc_chdr_tdata       (m_rfnoc_chdr_tdata   ),
+    .m_rfnoc_chdr_tlast       (m_rfnoc_chdr_tlast   ),
+    .m_rfnoc_chdr_tvalid      (m_rfnoc_chdr_tvalid  ),
+    .m_rfnoc_chdr_tready      (m_rfnoc_chdr_tready  ),
+    .s_rfnoc_ctrl_tdata       (s_rfnoc_ctrl_tdata   ),
+    .s_rfnoc_ctrl_tlast       (s_rfnoc_ctrl_tlast   ),
+    .s_rfnoc_ctrl_tvalid      (s_rfnoc_ctrl_tvalid  ),
+    .s_rfnoc_ctrl_tready      (s_rfnoc_ctrl_tready  ),
+    .m_rfnoc_ctrl_tdata       (m_rfnoc_ctrl_tdata   ),
+    .m_rfnoc_ctrl_tlast       (m_rfnoc_ctrl_tlast   ),
+    .m_rfnoc_ctrl_tvalid      (m_rfnoc_ctrl_tvalid  ),
+    .m_rfnoc_ctrl_tready      (m_rfnoc_ctrl_tready  ),
+    .ctrlport_clk             (ce_clk               ),
+    .ctrlport_rst             (ce_rst               ),
+    .m_ctrlport_req_wr        (ctrlport_req_wr      ),
+    .m_ctrlport_req_rd        (ctrlport_req_rd      ),
+    .m_ctrlport_req_addr      (ctrlport_req_addr    ),
+    .m_ctrlport_req_data      (ctrlport_req_data    ),
+    .m_ctrlport_req_byte_en   (                     ),
+    .m_ctrlport_req_has_time  (ctrlport_req_has_time),
+    .m_ctrlport_req_time      (ctrlport_req_time    ),
+    .m_ctrlport_resp_ack      (ctrlport_resp_ack    ),
+    .m_ctrlport_resp_status   (AXIS_CTRL_STS_OKAY   ),
+    .m_ctrlport_resp_data     (ctrlport_resp_data   ),
+    .s_ctrlport_req_wr        (1'b0                 ),
+    .s_ctrlport_req_rd        (1'b0                 ),
+    .s_ctrlport_req_addr      (20'b0                ),
+    .s_ctrlport_req_portid    (10'b0                ),
+    .s_ctrlport_req_rem_epid  (16'b0                ),
+    .s_ctrlport_req_rem_portid(10'b0                ),
+    .s_ctrlport_req_data      (32'b0                ),
+    .s_ctrlport_req_byte_en   (4'b0                 ),
+    .s_ctrlport_req_has_time  (1'b0                 ),
+    .s_ctrlport_req_time      (64'b0                ),
+    .s_ctrlport_resp_ack      (                     ),
+    .s_ctrlport_resp_status   (                     ),
+    .s_ctrlport_resp_data     (                     ),
+    .axis_data_clk            (ce_clk               ),
+    .axis_data_rst            (ce_rst               ),
+    .m_axis_payload_tdata     (axis_to_fft_tdata    ),
+    .m_axis_payload_tkeep     (                     ),
+    .m_axis_payload_tlast     (axis_to_fft_tlast    ),
+    .m_axis_payload_tvalid    (axis_to_fft_tvalid   ),
+    .m_axis_payload_tready    (axis_to_fft_tready   ),
+    .s_axis_payload_tdata     (axis_from_fft_tdata  ),
+    .s_axis_payload_tkeep     ({1*NIPC{1'b1}}       ),
+    .s_axis_payload_tlast     (axis_from_fft_tlast  ),
+    .s_axis_payload_tvalid    (axis_from_fft_tvalid ),
+    .s_axis_payload_tready    (axis_from_fft_tready ),
+    .m_axis_context_tdata     (m_axis_context_tdata ),
+    .m_axis_context_tuser     (m_axis_context_tuser ),
+    .m_axis_context_tlast     (m_axis_context_tlast ),
+    .m_axis_context_tvalid    (m_axis_context_tvalid),
+    .m_axis_context_tready    (m_axis_context_tready),
+    .s_axis_context_tdata     (s_axis_context_tdata ),
+    .s_axis_context_tuser     (s_axis_context_tuser ),
+    .s_axis_context_tlast     (s_axis_context_tlast ),
+    .s_axis_context_tvalid    (s_axis_context_tvalid),
+    .s_axis_context_tready    (s_axis_context_tready)
+  );
+
+  // The input packets are the same configuration as the output packets, so
+  // just use the header information for each incoming to create the header for
+  // each outgoing packet. This is done by connecting m_axis_context to
+  // directly to s_axis_context.
+  assign s_axis_context_tdata  = m_axis_context_tdata;
+  assign s_axis_context_tuser  = m_axis_context_tuser;
+  assign s_axis_context_tlast  = m_axis_context_tlast;
+  assign s_axis_context_tvalid = m_axis_context_tvalid;
+  assign m_axis_context_tready = s_axis_context_tready;
+
+  wire [ 8-1:0] set_addr;
+  wire [32-1:0] set_data;
+  wire  set_has_time;
+  wire  set_stb;
+  wire [ 8-1:0] rb_addr;
+  reg  [64-1:0] rb_data;
+
+  ctrlport_to_settings_bus # (
+    .NUM_PORTS (1)
+  ) ctrlport_to_settings_bus_i (
+    .ctrlport_clk             (ce_clk),
+    .ctrlport_rst             (ce_rst),
+    .s_ctrlport_req_wr        (ctrlport_req_wr),
+    .s_ctrlport_req_rd        (ctrlport_req_rd),
+    .s_ctrlport_req_addr      (ctrlport_req_addr),
+    .s_ctrlport_req_data      (ctrlport_req_data),
+    .s_ctrlport_req_has_time  (ctrlport_req_has_time),
+    .s_ctrlport_req_time      (ctrlport_req_time),
+    .s_ctrlport_resp_ack      (ctrlport_resp_ack),
+    .s_ctrlport_resp_data     (ctrlport_resp_data),
+    .set_data                 (set_data),
+    .set_addr                 (set_addr),
+    .set_stb                  (set_stb),
+    .set_time                 (),
+    .set_has_time             (set_has_time),
+    .rb_stb                   (1'b1),
+    .rb_addr                  (rb_addr),
+    .rb_data                  (rb_data));
+
+  localparam MAX_FFT_SIZE_LOG2          = 11;
+
+  localparam [31:0] SR_FFT_RESET        = 131;
+  localparam [31:0] SR_FFT_SIZE_LOG2    = 132;
+  localparam [31:0] SR_MAGNITUDE_OUT    = 133;
+  localparam [31:0] SR_FFT_DIRECTION    = 134;
+  localparam [31:0] SR_FFT_SCALING      = 135;
+  localparam [31:0] SR_FFT_SHIFT_CONFIG = 136;
+
+  // FFT Output
+  localparam [1:0] COMPLEX_OUT = 0;
+  localparam [1:0] MAG_OUT     = 1;
+  localparam [1:0] MAG_SQ_OUT  = 2;
+
+  // FFT Direction
+  localparam [0:0] FFT_REVERSE = 0;
+  localparam [0:0] FFT_FORWARD = 1;
+
+  wire [1:0]  magnitude_out;
+  wire [31:0] fft_data_o_tdata;
+  wire        fft_data_o_tlast;
+  wire        fft_data_o_tvalid;
+  wire        fft_data_o_tready;
+  wire [15:0] fft_data_o_tuser;
+  wire [31:0] fft_shift_o_tdata;
+  wire        fft_shift_o_tlast;
+  wire        fft_shift_o_tvalid;
+  wire        fft_shift_o_tready;
+  wire [31:0] fft_mag_i_tdata, fft_mag_o_tdata, fft_mag_o_tdata_int;
+  wire        fft_mag_i_tlast, fft_mag_o_tlast;
+  wire        fft_mag_i_tvalid, fft_mag_o_tvalid;
+  wire        fft_mag_i_tready, fft_mag_o_tready;
+  wire [31:0] fft_mag_sq_i_tdata, fft_mag_sq_o_tdata;
+  wire        fft_mag_sq_i_tlast, fft_mag_sq_o_tlast;
+  wire        fft_mag_sq_i_tvalid, fft_mag_sq_o_tvalid;
+  wire        fft_mag_sq_i_tready, fft_mag_sq_o_tready;
+  wire [31:0] fft_mag_round_i_tdata, fft_mag_round_o_tdata;
+  wire        fft_mag_round_i_tlast, fft_mag_round_o_tlast;
+  wire        fft_mag_round_i_tvalid, fft_mag_round_o_tvalid;
+  wire        fft_mag_round_i_tready, fft_mag_round_o_tready;
+
+  // Settings Registers
+  wire fft_reset;
+  setting_reg #(
+    .my_addr(SR_FFT_RESET), .awidth(8), .width(1))
+  sr_fft_reset (
+    .clk(ce_clk), .rst(ce_rst),
+    .strobe(set_stb), .addr(set_addr), .in(set_data), .out(fft_reset), .changed());
+
+  // Two instances of FFT size register, one for FFT core and one for FFT shift
+  localparam DEFAULT_FFT_SIZE = 8; // 256
+  wire [7:0] fft_size_log2_tdata ,fft_core_size_log2_tdata;
+  wire fft_size_log2_tvalid, fft_core_size_log2_tvalid, fft_size_log2_tready, fft_core_size_log2_tready;
+  axi_setting_reg #(
+    .ADDR(SR_FFT_SIZE_LOG2), .AWIDTH(8), .WIDTH(8), .DATA_AT_RESET(DEFAULT_FFT_SIZE), .VALID_AT_RESET(1))
+  sr_fft_size_log2 (
+    .clk(ce_clk), .reset(ce_rst),
+    .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+    .o_tdata(fft_size_log2_tdata), .o_tlast(), .o_tvalid(fft_size_log2_tvalid), .o_tready(fft_size_log2_tready));
+
+  axi_setting_reg #(
+    .ADDR(SR_FFT_SIZE_LOG2), .AWIDTH(8), .WIDTH(8), .DATA_AT_RESET(DEFAULT_FFT_SIZE), .VALID_AT_RESET(1))
+  sr_fft_size_log2_2 (
+    .clk(ce_clk), .reset(ce_rst),
+    .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+    .o_tdata(fft_core_size_log2_tdata), .o_tlast(), .o_tvalid(fft_core_size_log2_tvalid), .o_tready(fft_core_size_log2_tready));
+
+  // Forward = 0, Reverse = 1
+  localparam DEFAULT_FFT_DIRECTION = 0;
+  wire fft_direction_tdata;
+  wire fft_direction_tvalid, fft_direction_tready;
+  axi_setting_reg #(
+    .ADDR(SR_FFT_DIRECTION), .AWIDTH(8), .WIDTH(1), .DATA_AT_RESET(DEFAULT_FFT_DIRECTION), .VALID_AT_RESET(1))
+  sr_fft_direction (
+    .clk(ce_clk), .reset(ce_rst),
+    .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+    .o_tdata(fft_direction_tdata), .o_tlast(), .o_tvalid(fft_direction_tvalid), .o_tready(fft_direction_tready));
+
+  localparam [11:0] DEFAULT_FFT_SCALING = 12'b011010101010; // Conservative 1/N scaling
+  wire [11:0] fft_scaling_tdata;
+  wire fft_scaling_tvalid, fft_scaling_tready;
+  axi_setting_reg #(
+    .ADDR(SR_FFT_SCALING), .AWIDTH(8), .WIDTH(12), .DATA_AT_RESET(DEFAULT_FFT_SCALING), .VALID_AT_RESET(1))
+  sr_fft_scaling (
+    .clk(ce_clk), .reset(ce_rst),
+    .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+    .o_tdata(fft_scaling_tdata), .o_tlast(), .o_tvalid(fft_scaling_tvalid), .o_tready(fft_scaling_tready));
+
+  wire [1:0] fft_shift_config_tdata;
+  wire fft_shift_config_tvalid, fft_shift_config_tready;
+  axi_setting_reg #(
+    .ADDR(SR_FFT_SHIFT_CONFIG), .AWIDTH(8), .WIDTH(2))
+  sr_fft_shift_config (
+    .clk(ce_clk), .reset(ce_rst),
+    .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+    .o_tdata(fft_shift_config_tdata), .o_tlast(), .o_tvalid(fft_shift_config_tvalid), .o_tready(fft_shift_config_tready));
+
+  // Synchronize writing configuration to the FFT core
+  reg fft_config_ready;
+  wire fft_config_write = fft_config_ready & axis_to_fft_tvalid & axis_to_fft_tready;
+  always @(posedge ce_clk) begin
+    if (ce_rst | fft_reset) begin
+      fft_config_ready   <= 1'b1;
+    end else begin
+      if (fft_config_write) begin
+        fft_config_ready <= 1'b0;
+      end else if (axis_to_fft_tlast) begin
+        fft_config_ready <= 1'b1;
+      end
+    end
+  end
+
+  wire [23:0] fft_config_tdata     = {3'd0, fft_scaling_tdata, fft_direction_tdata, fft_core_size_log2_tdata};
+  wire fft_config_tvalid           = fft_config_write & (fft_scaling_tvalid | fft_direction_tvalid | fft_core_size_log2_tvalid);
+  wire fft_config_tready;
+  assign fft_core_size_log2_tready = fft_config_tready & fft_config_write;
+  assign fft_direction_tready      = fft_config_tready & fft_config_write;
+  assign fft_scaling_tready        = fft_config_tready & fft_config_write;
+  axi_fft inst_axi_fft (
+    .aclk(ce_clk), .aresetn(~(fft_reset)),
+    .s_axis_data_tvalid(axis_to_fft_tvalid),
+    .s_axis_data_tready(axis_to_fft_tready),
+    .s_axis_data_tlast(axis_to_fft_tlast),
+    .s_axis_data_tdata({axis_to_fft_tdata[15:0],axis_to_fft_tdata[31:16]}),
+    .m_axis_data_tvalid(fft_data_o_tvalid),
+    .m_axis_data_tready(fft_data_o_tready),
+    .m_axis_data_tlast(fft_data_o_tlast),
+    .m_axis_data_tdata({fft_data_o_tdata[15:0],fft_data_o_tdata[31:16]}),
+    .m_axis_data_tuser(fft_data_o_tuser), // FFT index
+    .s_axis_config_tdata(fft_config_tdata),
+    .s_axis_config_tvalid(fft_config_tvalid),
+    .s_axis_config_tready(fft_config_tready),
+    .event_frame_started(),
+    .event_tlast_unexpected(),
+    .event_tlast_missing(),
+    .event_status_channel_halt(),
+    .event_data_in_channel_halt(),
+    .event_data_out_channel_halt());
+
+  // Mux control signals
+  assign fft_shift_o_tready     = (magnitude_out == MAG_OUT)    ? fft_mag_i_tready         :
+                                  (magnitude_out == MAG_SQ_OUT) ? fft_mag_sq_i_tready      : axis_from_fft_tready;
+  assign fft_mag_i_tvalid       = (magnitude_out == MAG_OUT)    ? fft_shift_o_tvalid       : 1'b0;
+  assign fft_mag_i_tlast        = (magnitude_out == MAG_OUT)    ? fft_shift_o_tlast        : 1'b0;
+  assign fft_mag_i_tdata        = fft_shift_o_tdata;
+  assign fft_mag_o_tready       = (magnitude_out == MAG_OUT)    ? fft_mag_round_i_tready   : 1'b0;
+  assign fft_mag_sq_i_tvalid    = (magnitude_out == MAG_SQ_OUT) ? fft_shift_o_tvalid       : 1'b0;
+  assign fft_mag_sq_i_tlast     = (magnitude_out == MAG_SQ_OUT) ? fft_shift_o_tlast        : 1'b0;
+  assign fft_mag_sq_i_tdata     = fft_shift_o_tdata;
+  assign fft_mag_sq_o_tready    = (magnitude_out == MAG_SQ_OUT) ? fft_mag_round_i_tready   : 1'b0;
+  assign fft_mag_round_i_tvalid = (magnitude_out == MAG_OUT)    ? fft_mag_o_tvalid         :
+                                  (magnitude_out == MAG_SQ_OUT) ? fft_mag_sq_o_tvalid      : 1'b0;
+  assign fft_mag_round_i_tlast  = (magnitude_out == MAG_OUT)    ? fft_mag_o_tlast          :
+                                  (magnitude_out == MAG_SQ_OUT) ? fft_mag_sq_o_tlast       : 1'b0;
+  assign fft_mag_round_i_tdata  = (magnitude_out == MAG_OUT)    ? fft_mag_o_tdata          : fft_mag_sq_o_tdata;
+  assign fft_mag_round_o_tready = axis_from_fft_tready;
+  assign axis_from_fft_tvalid     = (magnitude_out == MAG_OUT | magnitude_out == MAG_SQ_OUT) ? fft_mag_round_o_tvalid : fft_shift_o_tvalid;
+  assign axis_from_fft_tlast      = (magnitude_out == MAG_OUT | magnitude_out == MAG_SQ_OUT) ? fft_mag_round_o_tlast  : fft_shift_o_tlast;
+  assign axis_from_fft_tdata      = (magnitude_out == MAG_OUT | magnitude_out == MAG_SQ_OUT) ? fft_mag_round_o_tdata  : fft_shift_o_tdata;
+
+  // Conditionally synth magnitude / magnitude^2 logic
+  generate
+    if (EN_MAGNITUDE_OUT | EN_MAGNITUDE_APPROX_OUT | EN_MAGNITUDE_SQ_OUT) begin : generate_magnitude_out
+      setting_reg #(
+        .my_addr(SR_MAGNITUDE_OUT), .awidth(8), .width(2))
+      sr_magnitude_out (
+        .clk(ce_clk), .rst(ce_rst),
+        .strobe(set_stb), .addr(set_addr), .in(set_data), .out(magnitude_out), .changed());
+    end else begin : generate_magnitude_out_else
+      // Magnitude calculation logic not included, so always bypass
+      assign magnitude_out = 2'd0;
+    end
+
+    if (EN_FFT_SHIFT) begin : generate_fft_shift
+      fft_shift #(
+        .MAX_FFT_SIZE_LOG2(MAX_FFT_SIZE_LOG2),
+        .WIDTH(32))
+      inst_fft_shift (
+        .clk(ce_clk), .reset(ce_rst | fft_reset),
+        .config_tdata(fft_shift_config_tdata),
+        .config_tvalid(fft_shift_config_tvalid),
+        .config_tready(fft_shift_config_tready),
+        .fft_size_log2_tdata(fft_size_log2_tdata[$clog2(MAX_FFT_SIZE_LOG2)-1:0]),
+        .fft_size_log2_tvalid(fft_size_log2_tvalid),
+        .fft_size_log2_tready(fft_size_log2_tready),
+        .i_tdata(fft_data_o_tdata),
+        .i_tlast(fft_data_o_tlast),
+        .i_tvalid(fft_data_o_tvalid),
+        .i_tready(fft_data_o_tready),
+        .i_tuser(fft_data_o_tuser[MAX_FFT_SIZE_LOG2-1:0]),
+        .o_tdata(fft_shift_o_tdata),
+        .o_tlast(fft_shift_o_tlast),
+        .o_tvalid(fft_shift_o_tvalid),
+        .o_tready(fft_shift_o_tready));
+    end 
+    else begin : generate_fft_shift_else 
+      assign fft_shift_o_tdata = fft_data_o_tdata;
+      assign fft_shift_o_tlast = fft_data_o_tlast;
+      assign fft_shift_o_tvalid = fft_data_o_tvalid;
+      assign fft_data_o_tready = fft_shift_o_tready;
+    end
+
+    // More accurate magnitude calculation takes precedence if enabled
+    if (EN_MAGNITUDE_OUT) begin : generate_complex_to_magphase 
+      complex_to_magphase
+      inst_complex_to_magphase (
+        .aclk(ce_clk), .aresetn(~(ce_rst | fft_reset)),
+        .s_axis_cartesian_tvalid(fft_mag_i_tvalid),
+        .s_axis_cartesian_tlast(fft_mag_i_tlast),
+        .s_axis_cartesian_tready(fft_mag_i_tready),
+        .s_axis_cartesian_tdata(fft_mag_i_tdata),
+        .m_axis_dout_tvalid(fft_mag_o_tvalid),
+        .m_axis_dout_tlast(fft_mag_o_tlast),
+        .m_axis_dout_tdata(fft_mag_o_tdata_int),
+        .m_axis_dout_tready(fft_mag_o_tready));
+      assign fft_mag_o_tdata = {1'b0, fft_mag_o_tdata_int[15:0], 15'd0};
+    end 
+    else if (EN_MAGNITUDE_APPROX_OUT) begin : generate_complex_to_mag_approx
+      complex_to_mag_approx
+      inst_complex_to_mag_approx (
+        .clk(ce_clk), .reset(ce_rst | fft_reset), .clear(1'b0),
+        .i_tvalid(fft_mag_i_tvalid),
+        .i_tlast(fft_mag_i_tlast),
+        .i_tready(fft_mag_i_tready),
+        .i_tdata(fft_mag_i_tdata),
+        .o_tvalid(fft_mag_o_tvalid),
+        .o_tlast(fft_mag_o_tlast),
+        .o_tready(fft_mag_o_tready),
+        .o_tdata(fft_mag_o_tdata_int[15:0]));
+      assign fft_mag_o_tdata = {1'b0, fft_mag_o_tdata_int[15:0], 15'd0};
+    end  
+    else begin : generate_complex_to_mag_approx_else
+      assign fft_mag_o_tdata = fft_mag_i_tdata;
+      assign fft_mag_o_tlast = fft_mag_i_tlast;
+      assign fft_mag_o_tvalid = fft_mag_i_tvalid;
+      assign fft_mag_i_tready = fft_mag_o_tready;
+    end
+
+    if (EN_MAGNITUDE_SQ_OUT) begin : generate_complex_to_magsq
+      complex_to_magsq
+      inst_complex_to_magsq (
+        .clk(ce_clk), .reset(ce_rst | fft_reset), .clear(1'b0),
+        .i_tvalid(fft_mag_sq_i_tvalid),
+        .i_tlast(fft_mag_sq_i_tlast),
+        .i_tready(fft_mag_sq_i_tready),
+        .i_tdata(fft_mag_sq_i_tdata),
+        .o_tvalid(fft_mag_sq_o_tvalid),
+        .o_tlast(fft_mag_sq_o_tlast),
+        .o_tready(fft_mag_sq_o_tready),
+        .o_tdata(fft_mag_sq_o_tdata));
+    end
+    else begin : generate_complex_to_magsq_else
+      assign fft_mag_sq_o_tdata = fft_mag_sq_i_tdata;
+      assign fft_mag_sq_o_tlast = fft_mag_sq_i_tlast;
+      assign fft_mag_sq_o_tvalid = fft_mag_sq_i_tvalid;
+      assign fft_mag_sq_i_tready = fft_mag_sq_o_tready;
+    end
+
+    // Convert to SC16
+    if (EN_MAGNITUDE_OUT | EN_MAGNITUDE_APPROX_OUT | EN_MAGNITUDE_SQ_OUT) begin : generate_axi_round_and_clip
+      axi_round_and_clip #(
+        .WIDTH_IN(32),
+        .WIDTH_OUT(16),
+        .CLIP_BITS(1))
+      inst_axi_round_and_clip (
+        .clk(ce_clk), .reset(ce_rst | fft_reset),
+        .i_tdata(fft_mag_round_i_tdata),
+        .i_tlast(fft_mag_round_i_tlast),
+        .i_tvalid(fft_mag_round_i_tvalid),
+        .i_tready(fft_mag_round_i_tready),
+        .o_tdata(fft_mag_round_o_tdata[31:16]),
+        .o_tlast(fft_mag_round_o_tlast),
+        .o_tvalid(fft_mag_round_o_tvalid),
+        .o_tready(fft_mag_round_o_tready));
+      assign fft_mag_round_o_tdata[15:0] = {16{16'd0}};
+    end 
+    else begin : generate_axi_round_and_clip_else
+      assign fft_mag_round_o_tdata = fft_mag_round_i_tdata;
+      assign fft_mag_round_o_tlast = fft_mag_round_i_tlast;
+      assign fft_mag_round_o_tvalid = fft_mag_round_i_tvalid;
+      assign fft_mag_round_i_tready = fft_mag_round_o_tready;
+    end 
+  endgenerate
+
+  // Readback registers
+  always @*
+    case(rb_addr)
+      3'd0    : rb_data <= {63'd0, fft_reset};
+      3'd1    : rb_data <= {62'd0, magnitude_out};
+      3'd2    : rb_data <= {fft_size_log2_tdata};
+      3'd3    : rb_data <= {63'd0, fft_direction_tdata};
+      3'd4    : rb_data <= {52'd0, fft_scaling_tdata};
+      3'd5    : rb_data <= {62'd0, fft_shift_config_tdata};
+      default : rb_data <= 64'h0BADC0DE0BADC0DE;
+  endcase
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fft/rfnoc_block_fft_tb.sv b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fft/rfnoc_block_fft_tb.sv
new file mode 100644
index 000000000..bb46e3cc7
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fft/rfnoc_block_fft_tb.sv
@@ -0,0 +1,263 @@
+//
+// Copyright 2019 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: rfnoc_block_fft_tb
+//
+// Description:  Testbench for rfnoc_block_fft
+//
+
+module rfnoc_block_fft_tb();
+
+  // Include macros and time declarations for use with PkgTestExec
+  `include "test_exec.svh"
+
+  import PkgTestExec::*;
+  import PkgChdrUtils::*;
+  import PkgRfnocBlockCtrlBfm::*;
+
+  //---------------------------------------------------------------------------
+  // Local Parameters
+  //---------------------------------------------------------------------------
+
+  // Simulation parameters
+  localparam real CHDR_CLK_PER   = 5.0;   // Clock rate
+  localparam int  SPP            = 256;   // Samples per packet
+  localparam int  PKT_SIZE_BYTES = SPP*4; // Bytes per packet
+  localparam int  STALL_PROB     = 25;    // BFM stall probability
+
+  // Block configuration
+  localparam int CHDR_W        = 64;
+  localparam int THIS_PORTID   = 'h123;
+  localparam int MTU           = 10;
+  localparam int NUM_PORTS     = 1;
+  localparam int NUM_HB        = 3;
+  localparam int CIC_MAX_DECIM = 255;
+
+  // FFT specific settings
+  // FFT settings
+  localparam [31:0] FFT_SIZE         = 256;
+  localparam [31:0] FFT_SIZE_LOG2    = $clog2(FFT_SIZE);
+  const logic [31:0] FFT_DIRECTION    = DUT.FFT_FORWARD;  // Forward
+  localparam [31:0] FFT_SCALING      = 12'b011010101010;           // Conservative scaling of 1/N
+  localparam [31:0] FFT_SHIFT_CONFIG = 0;                          // Normal FFT shift
+  localparam FFT_BIN                 = FFT_SIZE/8 + FFT_SIZE/2;    // 1/8 sample rate freq + FFT shift
+  localparam NUM_ITERATIONS  = 10;
+
+  //---------------------------------------------------------------------------
+  // Clocks
+  //---------------------------------------------------------------------------
+
+  bit rfnoc_chdr_clk;
+  bit rfnoc_ctrl_clk;
+
+  sim_clock_gen #(CHDR_CLK_PER)  rfnoc_chdr_clk_gen (.clk(rfnoc_chdr_clk), .rst());
+  sim_clock_gen #(CHDR_CLK_PER)  rfnoc_ctrl_clk_gen (.clk(rfnoc_ctrl_clk), .rst());
+
+  //---------------------------------------------------------------------------
+  // Bus Functional Models
+  //---------------------------------------------------------------------------
+
+  RfnocBackendIf        backend            (rfnoc_chdr_clk, rfnoc_ctrl_clk);
+  AxiStreamIf #(32)     m_ctrl             (rfnoc_ctrl_clk, 1'b0);
+  AxiStreamIf #(32)     s_ctrl             (rfnoc_ctrl_clk, 1'b0);
+  AxiStreamIf #(CHDR_W) m_chdr             (rfnoc_chdr_clk, 1'b0);
+  AxiStreamIf #(CHDR_W) s_chdr             (rfnoc_chdr_clk, 1'b0);
+
+  // Bus functional model for a software block controller
+  RfnocBlockCtrlBfm #(.CHDR_W(CHDR_W)) blk_ctrl = 
+    new(backend, m_ctrl, s_ctrl);
+
+  // Connect block controller to BFMs
+  initial begin
+    blk_ctrl.connect_master_data_port(0, m_chdr, PKT_SIZE_BYTES);
+    blk_ctrl.connect_slave_data_port(0, s_chdr);
+    blk_ctrl.set_master_stall_prob(0, STALL_PROB);
+    blk_ctrl.set_slave_stall_prob(0, STALL_PROB);
+  end
+
+  //---------------------------------------------------------------------------
+  // DUT
+  //---------------------------------------------------------------------------
+
+  rfnoc_block_fft #(
+    .THIS_PORTID            (0  ),
+    .CHDR_W                 (64 ),
+    .MTU                    (MTU),
+    
+    .EN_MAGNITUDE_OUT       (0  ),
+    .EN_MAGNITUDE_APPROX_OUT(1  ),
+    .EN_MAGNITUDE_SQ_OUT    (1  ),
+    .EN_FFT_SHIFT           (1  )
+  ) DUT (
+    .rfnoc_chdr_clk     (backend.chdr_clk),
+    .ce_clk             (backend.chdr_clk),
+    .s_rfnoc_chdr_tdata (m_chdr.tdata    ),
+    .s_rfnoc_chdr_tlast (m_chdr.tlast    ),
+    .s_rfnoc_chdr_tvalid(m_chdr.tvalid   ),
+    .s_rfnoc_chdr_tready(m_chdr.tready   ),
+    
+    .m_rfnoc_chdr_tdata (s_chdr.tdata    ),
+    .m_rfnoc_chdr_tlast (s_chdr.tlast    ),
+    .m_rfnoc_chdr_tvalid(s_chdr.tvalid   ),
+    .m_rfnoc_chdr_tready(s_chdr.tready   ),
+    
+    .rfnoc_core_config  (backend.cfg     ),
+    .rfnoc_core_status  (backend.sts     ),
+    .rfnoc_ctrl_clk     (backend.ctrl_clk),
+    
+    .s_rfnoc_ctrl_tdata (m_ctrl.tdata    ),
+    .s_rfnoc_ctrl_tlast (m_ctrl.tlast    ),
+    .s_rfnoc_ctrl_tvalid(m_ctrl.tvalid   ),
+    .s_rfnoc_ctrl_tready(m_ctrl.tready   ),
+    
+    .m_rfnoc_ctrl_tdata (s_ctrl.tdata    ),
+    .m_rfnoc_ctrl_tlast (s_ctrl.tlast    ),
+    .m_rfnoc_ctrl_tvalid(s_ctrl.tvalid   ),
+    .m_rfnoc_ctrl_tready(s_ctrl.tready   )
+  );
+
+  //---------------------------------------------------------------------------
+  // Helper Tasks
+  //---------------------------------------------------------------------------
+
+  // Translate the desired register access to a ctrlport write request.
+  task automatic write_reg(int port, byte addr, bit [31:0] value);
+    blk_ctrl.reg_write(256*8*port + addr*8, value);
+  endtask : write_reg
+
+  // Translate the desired register access to a ctrlport read request.
+  task automatic read_user_reg(int port, byte addr, output logic [63:0] value);
+    blk_ctrl.reg_read(256*8*port + addr*8 + 0, value[31: 0]);
+    blk_ctrl.reg_read(256*8*port + addr*8 + 4, value[63:32]);
+  endtask : read_user_reg
+
+  //---------------------------------------------------------------------------
+  // Test Process
+  //---------------------------------------------------------------------------
+
+  task automatic send_sine_wave (
+    input int unsigned port
+  );
+    // Send a sine wave
+    fork
+      begin
+        chdr_word_t send_payload[$];
+
+        for (int n = 0; n < NUM_ITERATIONS; n++) begin
+          for (int i = 0; i < (FFT_SIZE/8); i++) begin
+            send_payload.push_back({ 16'h5A82, 16'h5A82, 16'h7FFF, 16'h0000});
+            send_payload.push_back({-16'h5A82, 16'h5A82, 16'h0000, 16'h7FFF});
+            send_payload.push_back({-16'h5A82,-16'h5A82,-16'h7FFF, 16'h0000});
+            send_payload.push_back({ 16'h5A82,-16'h5A82, 16'h0000,-16'h7FFF});
+          end
+
+          blk_ctrl.send(port, send_payload);
+          blk_ctrl.wait_complete(port);
+          send_payload = {};
+        end
+      end
+
+      begin
+        string s;
+        chdr_word_t   recv_payload[$], temp_payload[$];
+        int           data_bytes;
+        logic [15:0] real_val;
+        logic [15:0] cplx_val;
+
+        for (int n = 0; n < NUM_ITERATIONS; n++) begin
+          blk_ctrl.recv(port, recv_payload, data_bytes);
+
+          `ASSERT_ERROR(recv_payload.size * 2 == FFT_SIZE, "received wrong amount of data");
+
+          for (int k = 0; k < FFT_SIZE/2; k++) begin
+            chdr_word_t payload_word;
+            payload_word = recv_payload.pop_front();
+
+            for (int i = 0; i < 2; i++) begin
+              {real_val, cplx_val} = payload_word;
+              payload_word = payload_word[63:32];
+
+              if (2*k+i == FFT_BIN) begin
+                // Assert that for the special case of a 1/8th sample rate sine wave input, 
+                // the real part of the corresponding 1/8th sample rate FFT bin should always be greater than 0 and
+                // the complex part equal to 0.
+                
+                `ASSERT_ERROR(real_val > 32'd0, "FFT bin real part is not greater than 0!");
+                `ASSERT_ERROR(cplx_val == 32'd0, "FFT bin complex part is not 0!");
+              end else begin
+                // Assert all other FFT bins should be 0 for both complex and real parts
+                `ASSERT_ERROR(real_val == 32'd0, "FFT bin real part is not 0!");
+                `ASSERT_ERROR(cplx_val == 32'd0, "FFT bin complex part is not 0!");
+              end
+            end
+          end
+        end
+      end
+    join
+  endtask
+
+  initial begin : tb_main
+    const int port = 0;
+    test.start_tb("rfnoc_block_fft_tb");
+
+    // Start the BFMs running
+    blk_ctrl.run();
+
+    //-------------------------------------------------------------------------
+    // Reset
+    //-------------------------------------------------------------------------
+    
+    test.start_test("Wait for Reset", 10us);
+    fork
+      blk_ctrl.reset_chdr();
+      blk_ctrl.reset_ctrl();
+    join;
+    test.end_test();
+
+    
+    //-------------------------------------------------------------------------
+    // Check NoC ID and Block Info
+    //-------------------------------------------------------------------------
+    
+    test.start_test("Verify Block Info", 2us);
+    `ASSERT_ERROR(blk_ctrl.get_noc_id() == DUT.NOC_ID, "Incorrect NOC_ID Value");
+    `ASSERT_ERROR(blk_ctrl.get_num_data_i() == NUM_PORTS, "Incorrect NUM_DATA_I Value");
+    `ASSERT_ERROR(blk_ctrl.get_num_data_o() == NUM_PORTS, "Incorrect NUM_DATA_O Value");
+    `ASSERT_ERROR(blk_ctrl.get_mtu() == MTU, "Incorrect MTU Value");
+    test.end_test();
+
+    //-------------------------------------------------------------------------
+    // Setup FFT
+    //-------------------------------------------------------------------------
+
+    test.start_test("Setup FFT", 10us);
+    write_reg(port, DUT.SR_FFT_SIZE_LOG2, FFT_SIZE_LOG2);
+    write_reg(port, DUT.SR_FFT_DIRECTION, FFT_DIRECTION);
+    write_reg(port, DUT.SR_FFT_SCALING, FFT_SCALING);
+    write_reg(port, DUT.SR_FFT_SHIFT_CONFIG, FFT_SHIFT_CONFIG);
+    write_reg(port, DUT.SR_MAGNITUDE_OUT, DUT.COMPLEX_OUT); // Enable real/imag out
+    test.end_test();
+
+    //-------------------------------------------------------------------------76
+    // Test sine wave
+    //-------------------------------------------------------------------------
+
+    test.start_test("Test sine wave", 20us);
+    send_sine_wave (port);
+    test.end_test();
+
+    //-------------------------------------------------------------------------
+    // Finish
+    //-------------------------------------------------------------------------
+
+    // End the TB, but don't $finish, since we don't want to kill other 
+    // instances of this testbench that may be running.
+    test.end_tb(0);
+
+    // Kill the clocks to end this instance of the testbench
+    rfnoc_chdr_clk_gen.kill();
+    rfnoc_ctrl_clk_gen.kill();
+  end
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/Makefile b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/Makefile
new file mode 100644
index 000000000..7d6d84f82
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/Makefile
@@ -0,0 +1,46 @@
+#
+# Copyright 2019 Ettus Research, A National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+#-------------------------------------------------
+# Top-of-Makefile
+#-------------------------------------------------
+# Define BASE_DIR to point to the "top" dir
+BASE_DIR = $(abspath ../../../../top)
+# Include viv_sim_preamble after defining BASE_DIR
+include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
+
+#-------------------------------------------------
+# Design Specific
+#-------------------------------------------------
+# Include makefiles and sources for the DUT and its dependencies
+include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs
+include $(BASE_DIR)/../lib/rfnoc/utils/Makefile.srcs
+include Makefile.srcs
+
+DESIGN_SRCS += $(abspath \
+$(RFNOC_CORE_SRCS) \
+$(RFNOC_UTIL_SRCS) \
+$(RFNOC_OOT_SRCS) \
+)
+
+#-------------------------------------------------
+# Testbench Specific
+#-------------------------------------------------
+# Define only one toplevel module
+SIM_TOP = rfnoc_block_fir_filter_tb
+
+# Add test bench, user design under test, and
+# additional user created files
+SIM_SRCS = \
+$(abspath rfnoc_block_fir_filter_tb.sv)
+
+#-------------------------------------------------
+# Bottom-of-Makefile
+#-------------------------------------------------
+# Include all simulator specific makefiles here
+# Each should define a unique target to simulate
+# e.g. xsim, vsim, etc and a common "clean" target
+include $(BASE_DIR)/../tools/make/viv_simulator.mak
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/Makefile.srcs b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/Makefile.srcs
new file mode 100644
index 000000000..f8c696096
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/Makefile.srcs
@@ -0,0 +1,12 @@
+#
+# Copyright 2019 Ettus Research, A National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+RFNOC_OOT_SRCS += $(abspath $(addprefix $(BASE_DIR)/../lib/rfnoc/blocks/rfnoc_block_fir_filter/, \
+noc_shell_fir_filter.v \
+rfnoc_fir_filter_regs.vh \
+rfnoc_fir_filter_core.v \
+rfnoc_block_fir_filter.v \
+))
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/noc_shell_fir_filter.v b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/noc_shell_fir_filter.v
new file mode 100644
index 000000000..ce9a66fd9
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/noc_shell_fir_filter.v
@@ -0,0 +1,297 @@
+//
+// Copyright 2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: noc_shell_fir_filter
+//
+// Description: A NoC Shell for RFNoC. This should eventually be replaced
+// by an auto-generated NoC Shell.
+//
+
+module noc_shell_fir_filter #(
+  parameter [31:0] NOC_ID          = 32  'h0,
+  parameter [ 9:0] THIS_PORTID     = 10  'd0,
+  parameter        CHDR_W          = 64,
+  parameter [ 0:0] CTRLPORT_SLV_EN = 1,
+  parameter [ 0:0] CTRLPORT_MST_EN = 1,
+  parameter        SYNC_CLKS       = 0,
+  parameter [ 5:0] NUM_DATA_I      = 1,
+  parameter [ 5:0] NUM_DATA_O      = 1,
+  parameter        ITEM_W          = 32,
+  parameter        NIPC            = 2,
+  parameter        PYLD_FIFO_SIZE  = 5,
+  parameter        CTXT_FIFO_SIZE  = 5,
+  parameter        MTU             = 10
+) (
+  //---------------------------------------------------------------------------
+  // Framework Interface
+  //---------------------------------------------------------------------------
+
+  // RFNoC Framework Clocks and Resets
+  input  wire                           rfnoc_chdr_clk,
+  output wire                           rfnoc_chdr_rst,
+  input  wire                           rfnoc_ctrl_clk,
+  output wire                           rfnoc_ctrl_rst,
+  // RFNoC Backend Interface
+  input  wire [                  511:0] rfnoc_core_config,
+  output wire [                  511:0] rfnoc_core_status,
+  // CHDR Input Ports (from framework)
+  input  wire [(CHDR_W*NUM_DATA_I)-1:0] s_rfnoc_chdr_tdata,
+  input  wire [         NUM_DATA_I-1:0] s_rfnoc_chdr_tlast,
+  input  wire [         NUM_DATA_I-1:0] s_rfnoc_chdr_tvalid,
+  output wire [         NUM_DATA_I-1:0] s_rfnoc_chdr_tready,
+  // CHDR Output Ports (to framework)
+  output wire [(CHDR_W*NUM_DATA_O)-1:0] m_rfnoc_chdr_tdata,
+  output wire [         NUM_DATA_O-1:0] m_rfnoc_chdr_tlast,
+  output wire [         NUM_DATA_O-1:0] m_rfnoc_chdr_tvalid,
+  input  wire [         NUM_DATA_O-1:0] m_rfnoc_chdr_tready,
+  // AXIS-Ctrl Input Port (from framework)
+  input  wire [                   31:0] s_rfnoc_ctrl_tdata,
+  input  wire                           s_rfnoc_ctrl_tlast,
+  input  wire                           s_rfnoc_ctrl_tvalid,
+  output wire                           s_rfnoc_ctrl_tready,
+  // AXIS-Ctrl Output Port (to framework)
+  output wire [                   31:0] m_rfnoc_ctrl_tdata,
+  output wire                           m_rfnoc_ctrl_tlast,
+  output wire                           m_rfnoc_ctrl_tvalid,
+  input  wire                           m_rfnoc_ctrl_tready,
+
+  //---------------------------------------------------------------------------
+  // Client Control Port Interface
+  //---------------------------------------------------------------------------
+
+  // Clock
+  input  wire        ctrlport_clk,
+  input  wire        ctrlport_rst,
+  // Master
+  output wire        m_ctrlport_req_wr,
+  output wire        m_ctrlport_req_rd,
+  output wire [19:0] m_ctrlport_req_addr,
+  output wire [31:0] m_ctrlport_req_data,
+  output wire [ 3:0] m_ctrlport_req_byte_en,
+  output wire        m_ctrlport_req_has_time,
+  output wire [63:0] m_ctrlport_req_time,
+  input  wire        m_ctrlport_resp_ack,
+  input  wire [ 1:0] m_ctrlport_resp_status,
+  input  wire [31:0] m_ctrlport_resp_data,
+  // Slave
+  input  wire        s_ctrlport_req_wr,
+  input  wire        s_ctrlport_req_rd,
+  input  wire [19:0] s_ctrlport_req_addr,
+  input  wire [ 9:0] s_ctrlport_req_portid,
+  input  wire [15:0] s_ctrlport_req_rem_epid,
+  input  wire [ 9:0] s_ctrlport_req_rem_portid,
+  input  wire [31:0] s_ctrlport_req_data,
+  input  wire [ 3:0] s_ctrlport_req_byte_en,
+  input  wire        s_ctrlport_req_has_time,
+  input  wire [63:0] s_ctrlport_req_time,
+  output wire        s_ctrlport_resp_ack,
+  output wire [ 1:0] s_ctrlport_resp_status,
+  output wire [31:0] s_ctrlport_resp_data,
+
+  //---------------------------------------------------------------------------
+  // Client Data Interface
+  //---------------------------------------------------------------------------
+
+  // Clock
+  input wire axis_data_clk,
+  input wire axis_data_rst,
+
+  // Output data stream (to user logic)
+  output wire [(NUM_DATA_I*ITEM_W*NIPC)-1:0] m_axis_payload_tdata,
+  output wire [       (NUM_DATA_I*NIPC)-1:0] m_axis_payload_tkeep,
+  output wire [              NUM_DATA_I-1:0] m_axis_payload_tlast,
+  output wire [              NUM_DATA_I-1:0] m_axis_payload_tvalid,
+  input  wire [              NUM_DATA_I-1:0] m_axis_payload_tready,
+
+  // Input data stream (from user logic)
+  input  wire [(NUM_DATA_O*ITEM_W*NIPC)-1:0] s_axis_payload_tdata,
+  input  wire [       (NUM_DATA_O*NIPC)-1:0] s_axis_payload_tkeep,
+  input  wire [              NUM_DATA_O-1:0] s_axis_payload_tlast,
+  input  wire [              NUM_DATA_O-1:0] s_axis_payload_tvalid,
+  output wire [              NUM_DATA_O-1:0] s_axis_payload_tready,
+
+  // Output context stream (to user logic)
+  output wire [(NUM_DATA_I*CHDR_W)-1:0] m_axis_context_tdata,
+  output wire [     (4*NUM_DATA_I)-1:0] m_axis_context_tuser,
+  output wire [         NUM_DATA_I-1:0] m_axis_context_tlast,
+  output wire [         NUM_DATA_I-1:0] m_axis_context_tvalid,
+  input  wire [         NUM_DATA_I-1:0] m_axis_context_tready,
+
+  // Input context stream (from user logic)
+  input  wire [(NUM_DATA_O*CHDR_W)-1:0] s_axis_context_tdata,
+  input  wire [     (4*NUM_DATA_O)-1:0] s_axis_context_tuser,
+  input  wire [         NUM_DATA_O-1:0] s_axis_context_tlast,
+  input  wire [         NUM_DATA_O-1:0] s_axis_context_tvalid,
+  output wire [         NUM_DATA_O-1:0] s_axis_context_tready
+);
+  
+  localparam CTRL_FIFO_SIZE = 5;
+
+
+  //---------------------------------------------------------------------------
+  //  Backend Interface
+  //---------------------------------------------------------------------------
+
+  wire         data_i_flush_en;
+  wire [31:0]  data_i_flush_timeout;
+  wire [63:0]  data_i_flush_active;
+  wire [63:0]  data_i_flush_done;
+  wire         data_o_flush_en;
+  wire [31:0]  data_o_flush_timeout;
+  wire [63:0]  data_o_flush_active;
+  wire [63:0]  data_o_flush_done;
+
+  backend_iface #(
+    .NOC_ID        (NOC_ID),
+    .NUM_DATA_I    (NUM_DATA_I),
+    .NUM_DATA_O    (NUM_DATA_O),
+    .CTRL_FIFOSIZE (CTRL_FIFO_SIZE),
+    .MTU           (MTU)
+  ) backend_iface_i (
+    .rfnoc_chdr_clk       (rfnoc_chdr_clk),
+    .rfnoc_ctrl_clk       (rfnoc_ctrl_clk),
+    .rfnoc_core_config    (rfnoc_core_config),
+    .rfnoc_core_status    (rfnoc_core_status),
+    .rfnoc_chdr_rst       (rfnoc_chdr_rst),
+    .rfnoc_ctrl_rst       (rfnoc_ctrl_rst),
+    .data_i_flush_en      (data_i_flush_en),
+    .data_i_flush_timeout (data_i_flush_timeout),
+    .data_i_flush_active  (data_i_flush_active),
+    .data_i_flush_done    (data_i_flush_done),
+    .data_o_flush_en      (data_o_flush_en),
+    .data_o_flush_timeout (data_o_flush_timeout),
+    .data_o_flush_active  (data_o_flush_active),
+    .data_o_flush_done    (data_o_flush_done)
+  );
+
+  //---------------------------------------------------------------------------
+  //  Control Path
+  //---------------------------------------------------------------------------
+
+  ctrlport_endpoint #(
+    .THIS_PORTID              (THIS_PORTID    ),
+    .SYNC_CLKS                (0              ),
+    .AXIS_CTRL_MST_EN         (CTRLPORT_SLV_EN),
+    .AXIS_CTRL_SLV_EN         (CTRLPORT_MST_EN),
+    .SLAVE_FIFO_SIZE          (CTRL_FIFO_SIZE )
+  ) ctrlport_ep_i (
+    .rfnoc_ctrl_clk           (rfnoc_ctrl_clk           ),
+    .rfnoc_ctrl_rst           (rfnoc_ctrl_rst           ),
+    .ctrlport_clk             (ctrlport_clk             ),
+    .ctrlport_rst             (ctrlport_rst             ),
+    .s_rfnoc_ctrl_tdata       (s_rfnoc_ctrl_tdata       ),
+    .s_rfnoc_ctrl_tlast       (s_rfnoc_ctrl_tlast       ),
+    .s_rfnoc_ctrl_tvalid      (s_rfnoc_ctrl_tvalid      ),
+    .s_rfnoc_ctrl_tready      (s_rfnoc_ctrl_tready      ),
+    .m_rfnoc_ctrl_tdata       (m_rfnoc_ctrl_tdata       ),
+    .m_rfnoc_ctrl_tlast       (m_rfnoc_ctrl_tlast       ),
+    .m_rfnoc_ctrl_tvalid      (m_rfnoc_ctrl_tvalid      ),
+    .m_rfnoc_ctrl_tready      (m_rfnoc_ctrl_tready      ),
+    .m_ctrlport_req_wr        (m_ctrlport_req_wr        ),
+    .m_ctrlport_req_rd        (m_ctrlport_req_rd        ),
+    .m_ctrlport_req_addr      (m_ctrlport_req_addr      ),
+    .m_ctrlport_req_data      (m_ctrlport_req_data      ),
+    .m_ctrlport_req_byte_en   (m_ctrlport_req_byte_en   ),
+    .m_ctrlport_req_has_time  (m_ctrlport_req_has_time  ),
+    .m_ctrlport_req_time      (m_ctrlport_req_time      ),
+    .m_ctrlport_resp_ack      (m_ctrlport_resp_ack      ),
+    .m_ctrlport_resp_status   (m_ctrlport_resp_status   ),
+    .m_ctrlport_resp_data     (m_ctrlport_resp_data     ),
+    .s_ctrlport_req_wr        (s_ctrlport_req_wr        ),
+    .s_ctrlport_req_rd        (s_ctrlport_req_rd        ),
+    .s_ctrlport_req_addr      (s_ctrlport_req_addr      ),
+    .s_ctrlport_req_portid    (s_ctrlport_req_portid    ),
+    .s_ctrlport_req_rem_epid  (s_ctrlport_req_rem_epid  ),
+    .s_ctrlport_req_rem_portid(s_ctrlport_req_rem_portid),
+    .s_ctrlport_req_data      (s_ctrlport_req_data      ),
+    .s_ctrlport_req_byte_en   (s_ctrlport_req_byte_en   ),
+    .s_ctrlport_req_has_time  (s_ctrlport_req_has_time  ),
+    .s_ctrlport_req_time      (s_ctrlport_req_time      ),
+    .s_ctrlport_resp_ack      (s_ctrlport_resp_ack      ),
+    .s_ctrlport_resp_status   (s_ctrlport_resp_status   ),
+    .s_ctrlport_resp_data     (s_ctrlport_resp_data     )
+  );
+
+  //---------------------------------------------------------------------------
+  //  Data Path
+  //---------------------------------------------------------------------------
+
+  genvar i;
+  generate
+
+    for (i = 0; i < NUM_DATA_I; i = i + 1) begin: chdr_to_data
+      chdr_to_axis_pyld_ctxt #(
+        .CHDR_W               (CHDR_W        ),
+        .ITEM_W               (ITEM_W        ),
+        .NIPC                 (NIPC          ),
+        .SYNC_CLKS            (SYNC_CLKS     ),
+        .CONTEXT_FIFO_SIZE    (CTXT_FIFO_SIZE),
+        .PAYLOAD_FIFO_SIZE    (PYLD_FIFO_SIZE),
+        .CONTEXT_PREFETCH_EN  (1             )
+      ) chdr_to_axis_pyld_ctxt_i (
+        .axis_chdr_clk        (rfnoc_chdr_clk                                       ),
+        .axis_chdr_rst        (rfnoc_chdr_rst                                       ),
+        .axis_data_clk        (axis_data_clk                                        ),
+        .axis_data_rst        (axis_data_rst                                        ),
+        .s_axis_chdr_tdata    (s_rfnoc_chdr_tdata   [(i*CHDR_W)+:CHDR_W]            ),
+        .s_axis_chdr_tlast    (s_rfnoc_chdr_tlast   [i]                             ),
+        .s_axis_chdr_tvalid   (s_rfnoc_chdr_tvalid  [i]                             ),
+        .s_axis_chdr_tready   (s_rfnoc_chdr_tready  [i]                             ),
+        .m_axis_payload_tdata (m_axis_payload_tdata [(i*ITEM_W*NIPC)+:(ITEM_W*NIPC)]),
+        .m_axis_payload_tkeep (m_axis_payload_tkeep [(i*NIPC)+:NIPC]                ),
+        .m_axis_payload_tlast (m_axis_payload_tlast [i]                             ),
+        .m_axis_payload_tvalid(m_axis_payload_tvalid[i]                             ),
+        .m_axis_payload_tready(m_axis_payload_tready[i]                             ),
+        .m_axis_context_tdata (m_axis_context_tdata [(i*CHDR_W)+:(CHDR_W)]          ),
+        .m_axis_context_tuser (m_axis_context_tuser [(i*4)+:4]                      ),
+        .m_axis_context_tlast (m_axis_context_tlast [i]                             ),
+        .m_axis_context_tvalid(m_axis_context_tvalid[i]                             ),
+        .m_axis_context_tready(m_axis_context_tready[i]                             ),
+        .flush_en             (data_i_flush_en                                      ),
+        .flush_timeout        (data_i_flush_timeout                                 ),
+        .flush_active         (data_i_flush_active  [i]                             ),
+        .flush_done           (data_i_flush_done    [i]                             )
+      );
+    end
+
+    for (i = 0; i < NUM_DATA_O; i = i + 1) begin: data_to_chdr
+      axis_pyld_ctxt_to_chdr #(
+        .CHDR_W               (CHDR_W        ),
+        .ITEM_W               (ITEM_W        ),
+        .NIPC                 (NIPC          ),
+        .SYNC_CLKS            (SYNC_CLKS     ),
+        .CONTEXT_FIFO_SIZE    (CTXT_FIFO_SIZE),
+        .PAYLOAD_FIFO_SIZE    (PYLD_FIFO_SIZE),
+        .CONTEXT_PREFETCH_EN  (1             ),
+        .MTU                  (MTU           )
+      ) axis_pyld_ctxt_to_chdr_i (
+        .axis_chdr_clk        (rfnoc_chdr_clk                                       ),
+        .axis_chdr_rst        (rfnoc_chdr_rst                                       ),
+        .axis_data_clk        (axis_data_clk                                        ),
+        .axis_data_rst        (axis_data_rst                                        ),
+        .m_axis_chdr_tdata    (m_rfnoc_chdr_tdata   [(i*CHDR_W)+:CHDR_W]            ),
+        .m_axis_chdr_tlast    (m_rfnoc_chdr_tlast   [i]                             ),
+        .m_axis_chdr_tvalid   (m_rfnoc_chdr_tvalid  [i]                             ),
+        .m_axis_chdr_tready   (m_rfnoc_chdr_tready  [i]                             ),
+        .s_axis_payload_tdata (s_axis_payload_tdata [(i*ITEM_W*NIPC)+:(ITEM_W*NIPC)]),
+        .s_axis_payload_tkeep (s_axis_payload_tkeep [(i*NIPC)+:NIPC]                ),
+        .s_axis_payload_tlast (s_axis_payload_tlast [i]                             ),
+        .s_axis_payload_tvalid(s_axis_payload_tvalid[i]                             ),
+        .s_axis_payload_tready(s_axis_payload_tready[i]                             ),
+        .s_axis_context_tdata (s_axis_context_tdata [(i*CHDR_W)+:(CHDR_W)]          ),
+        .s_axis_context_tuser (s_axis_context_tuser [(i*4)+:4]                      ),
+        .s_axis_context_tlast (s_axis_context_tlast [i]                             ),
+        .s_axis_context_tvalid(s_axis_context_tvalid[i]                             ),
+        .s_axis_context_tready(s_axis_context_tready[i]                             ),
+        .framer_errors        (                                                     ),
+        .flush_en             (data_o_flush_en                                      ),
+        .flush_timeout        (data_o_flush_timeout                                 ),
+        .flush_active         (data_o_flush_active  [i]                             ),
+        .flush_done           (data_o_flush_done    [i]                             )
+      );
+    end
+  endgenerate
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/rfnoc_block_fir_filter.v b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/rfnoc_block_fir_filter.v
new file mode 100644
index 000000000..f007049cc
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/rfnoc_block_fir_filter.v
@@ -0,0 +1,343 @@
+//
+// Copyright 2019 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Description:
+//
+//   Parameterized FIR filter RFNoC block with optional re-loadable
+//   coefficients.
+//
+//   It has several optimizations for resource utilization such as using half
+//   the number of DSP slices for symmetric coefficients, skipping coefficients
+//   that are always set to zero, and using internal DSP slice registers to
+//   hold coefficients.
+//
+//   For the most efficient DSP slice inference use these settings, set 
+//   COEFF_WIDTH to be less than 18.
+//
+// Parameters:
+// 
+//   COEFF_WIDTH              : Coefficient width
+//
+//   NUM_COEFFS               : Number of coefficients / filter taps
+//
+//   COEFFS_VEC               : Vector of NUM_COEFFS values, each of width
+//                              COEFF_WIDTH, to initialize the filter
+//                              coefficients. Defaults to an impulse.
+//
+//   RELOADABLE_COEFFS        : Enable (1) or disable (0) reloading
+//                              coefficients at runtime
+//
+//   SYMMETRIC_COEFFS         : Reduce multiplier usage by approximately half
+//                              if coefficients are symmetric
+//
+//   SKIP_ZERO_COEFFS         : Reduce multiplier usage by assuming zero valued
+//                              coefficients in DEFAULT_COEFFS are always zero.
+//                              Useful for halfband filters.
+//
+//   USE_EMBEDDED_REGS_COEFFS : Reduce register usage by only using embedded
+//                              registers in DSP slices. Updating taps while
+//                              streaming will cause temporary output
+//                              corruption!
+//
+//   Note: If using USE_EMBEDDED_REGS_COEFFS, coefficients must be written at 
+//   least once since COEFFS_VEC is ignored!
+//
+
+
+module rfnoc_block_fir_filter #(
+  // RFNoC Parameters
+  parameter THIS_PORTID              = 0,
+  parameter CHDR_W                   = 64,
+  parameter NUM_PORTS                = 2,
+  parameter MTU                      = 10,
+  // FIR Filter Parameters
+  parameter COEFF_WIDTH              = 16,
+  parameter NUM_COEFFS               = 41,
+  parameter [NUM_COEFFS*COEFF_WIDTH-1:0] COEFFS_VEC = // Make impulse by default
+    { 
+      {1'b0, {(COEFF_WIDTH-1){1'b1}} },        // Max positive value
+      {(COEFF_WIDTH*(NUM_COEFFS-1)){1'b0}}     // Zero for remaining coefficients
+    },
+  parameter RELOADABLE_COEFFS        = 1,
+  parameter SYMMETRIC_COEFFS         = 0,
+  parameter SKIP_ZERO_COEFFS         = 0,
+  parameter USE_EMBEDDED_REGS_COEFFS = 1
+)(
+  // Clock to use for signal processing
+  input wire ce_clk,
+
+
+  //---------------------------------------------------------------------------
+  // AXIS CHDR Port
+  //---------------------------------------------------------------------------
+
+  input wire rfnoc_chdr_clk,
+
+  // CHDR inputs from framework
+  input  wire [NUM_PORTS*CHDR_W-1:0] s_rfnoc_chdr_tdata,
+  input  wire [       NUM_PORTS-1:0] s_rfnoc_chdr_tlast,
+  input  wire [       NUM_PORTS-1:0] s_rfnoc_chdr_tvalid,
+  output wire [       NUM_PORTS-1:0] s_rfnoc_chdr_tready,
+
+  // CHDR outputs to framework
+  output wire [NUM_PORTS*CHDR_W-1:0] m_rfnoc_chdr_tdata,
+  output wire [       NUM_PORTS-1:0] m_rfnoc_chdr_tlast,
+  output wire [       NUM_PORTS-1:0] m_rfnoc_chdr_tvalid,
+  input  wire [       NUM_PORTS-1:0] m_rfnoc_chdr_tready,
+
+  // Backend interface
+  input  wire [511:0] rfnoc_core_config,
+  output wire [511:0] rfnoc_core_status,
+
+
+  //---------------------------------------------------------------------------
+  // AXIS CTRL Port
+  //---------------------------------------------------------------------------
+
+  input wire rfnoc_ctrl_clk,
+
+  // CTRL port requests from framework
+  input  wire [31:0] s_rfnoc_ctrl_tdata,
+  input  wire        s_rfnoc_ctrl_tlast,
+  input  wire        s_rfnoc_ctrl_tvalid,
+  output wire        s_rfnoc_ctrl_tready,
+
+  // CTRL port requests to framework
+  output wire [31:0] m_rfnoc_ctrl_tdata,
+  output wire        m_rfnoc_ctrl_tlast,
+  output wire        m_rfnoc_ctrl_tvalid,
+  input  wire        m_rfnoc_ctrl_tready
+);
+
+  `include "rfnoc_fir_filter_regs.vh"
+
+  // These are the only supported values for now
+  localparam ITEM_W = 32;
+  localparam NIPC   = 1;
+
+
+  //---------------------------------------------------------------------------
+  // NoC Shell
+  //---------------------------------------------------------------------------
+
+  wire        ctrlport_reg_req_wr;
+  wire        ctrlport_reg_req_rd;
+  wire [19:0] ctrlport_reg_req_addr;
+  wire [31:0] ctrlport_reg_req_data;
+  wire        ctrlport_reg_resp_ack;
+  wire [ 1:0] ctrlport_reg_resp_status;
+  wire [31:0] ctrlport_reg_resp_data;
+
+  wire [(NUM_PORTS*ITEM_W*NIPC)-1:0] axis_to_fir_tdata;
+  wire [              NUM_PORTS-1:0] axis_to_fir_tlast;
+  wire [              NUM_PORTS-1:0] axis_to_fir_tvalid;
+  wire [              NUM_PORTS-1:0] axis_to_fir_tready;
+
+  wire [(NUM_PORTS*ITEM_W*NIPC)-1:0] axis_from_fir_tdata;
+  wire [              NUM_PORTS-1:0] axis_from_fir_tlast;
+  wire [              NUM_PORTS-1:0] axis_from_fir_tvalid;
+  wire [              NUM_PORTS-1:0] axis_from_fir_tready;
+
+  wire [(NUM_PORTS*CHDR_W)-1:0] m_axis_context_tdata;
+  wire [     (4*NUM_PORTS)-1:0] m_axis_context_tuser;
+  wire [         NUM_PORTS-1:0] m_axis_context_tlast;
+  wire [         NUM_PORTS-1:0] m_axis_context_tvalid;
+  wire [         NUM_PORTS-1:0] m_axis_context_tready;
+
+  wire [(NUM_PORTS*CHDR_W)-1:0] s_axis_context_tdata;
+  wire [     (4*NUM_PORTS)-1:0] s_axis_context_tuser;
+  wire [         NUM_PORTS-1:0] s_axis_context_tlast;
+  wire [         NUM_PORTS-1:0] s_axis_context_tvalid;
+  wire [         NUM_PORTS-1:0] s_axis_context_tready;
+
+  wire rfnoc_chdr_rst;
+  wire ce_rst;
+
+  localparam NOC_ID = 32'hF112_0000;
+
+
+  // Cross the CHDR reset to the ddc_clk domain
+  synchronizer ce_rst_sync_i (
+    .clk (ce_clk),
+    .rst (1'b0),
+    .in  (rfnoc_chdr_rst),
+    .out (ce_rst)
+  );
+  
+
+  noc_shell_fir_filter #(
+    .NOC_ID          (NOC_ID),
+    .THIS_PORTID     (THIS_PORTID),
+    .CHDR_W          (CHDR_W),
+    .CTRLPORT_SLV_EN (0),
+    .CTRLPORT_MST_EN (1),
+    .NUM_DATA_I      (NUM_PORTS),
+    .NUM_DATA_O      (NUM_PORTS),
+    .ITEM_W          (ITEM_W),
+    .NIPC            (NIPC),
+    .PYLD_FIFO_SIZE  (5),
+    .CTXT_FIFO_SIZE  (5),
+    .MTU             (MTU)
+  ) noc_shell_fir_filter_i (
+    .rfnoc_chdr_clk            (rfnoc_chdr_clk),
+    .rfnoc_chdr_rst            (rfnoc_chdr_rst),
+    .rfnoc_ctrl_clk            (rfnoc_ctrl_clk),
+    .rfnoc_ctrl_rst            (),
+    .rfnoc_core_config         (rfnoc_core_config),
+    .rfnoc_core_status         (rfnoc_core_status),
+    .s_rfnoc_chdr_tdata        (s_rfnoc_chdr_tdata),
+    .s_rfnoc_chdr_tlast        (s_rfnoc_chdr_tlast),
+    .s_rfnoc_chdr_tvalid       (s_rfnoc_chdr_tvalid),
+    .s_rfnoc_chdr_tready       (s_rfnoc_chdr_tready),
+    .m_rfnoc_chdr_tdata        (m_rfnoc_chdr_tdata),
+    .m_rfnoc_chdr_tlast        (m_rfnoc_chdr_tlast),
+    .m_rfnoc_chdr_tvalid       (m_rfnoc_chdr_tvalid),
+    .m_rfnoc_chdr_tready       (m_rfnoc_chdr_tready),
+    .s_rfnoc_ctrl_tdata        (s_rfnoc_ctrl_tdata),
+    .s_rfnoc_ctrl_tlast        (s_rfnoc_ctrl_tlast),
+    .s_rfnoc_ctrl_tvalid       (s_rfnoc_ctrl_tvalid),
+    .s_rfnoc_ctrl_tready       (s_rfnoc_ctrl_tready),
+    .m_rfnoc_ctrl_tdata        (m_rfnoc_ctrl_tdata),
+    .m_rfnoc_ctrl_tlast        (m_rfnoc_ctrl_tlast),
+    .m_rfnoc_ctrl_tvalid       (m_rfnoc_ctrl_tvalid),
+    .m_rfnoc_ctrl_tready       (m_rfnoc_ctrl_tready),
+    .ctrlport_clk              (ce_clk),
+    .ctrlport_rst              (ce_rst),
+    .m_ctrlport_req_wr         (ctrlport_reg_req_wr),
+    .m_ctrlport_req_rd         (ctrlport_reg_req_rd),
+    .m_ctrlport_req_addr       (ctrlport_reg_req_addr),
+    .m_ctrlport_req_data       (ctrlport_reg_req_data),
+    .m_ctrlport_req_byte_en    (),
+    .m_ctrlport_req_has_time   (),
+    .m_ctrlport_req_time       (),
+    .m_ctrlport_resp_ack       (ctrlport_reg_resp_ack),
+    .m_ctrlport_resp_status    (ctrlport_reg_resp_status),
+    .m_ctrlport_resp_data      (ctrlport_reg_resp_data),
+    .s_ctrlport_req_wr         (1'b0),
+    .s_ctrlport_req_rd         (1'b0),
+    .s_ctrlport_req_addr       (20'b0),
+    .s_ctrlport_req_portid     (10'b0),
+    .s_ctrlport_req_rem_epid   (16'b0),
+    .s_ctrlport_req_rem_portid (10'b0),
+    .s_ctrlport_req_data       (32'b0),
+    .s_ctrlport_req_byte_en    (4'hF),
+    .s_ctrlport_req_has_time   (1'b0),
+    .s_ctrlport_req_time       (64'b0),
+    .s_ctrlport_resp_ack       (),
+    .s_ctrlport_resp_status    (),
+    .s_ctrlport_resp_data      (),
+    .axis_data_clk             (ce_clk),
+    .axis_data_rst             (ce_rst),
+    .m_axis_payload_tdata      (axis_to_fir_tdata),
+    .m_axis_payload_tkeep      (),
+    .m_axis_payload_tlast      (axis_to_fir_tlast),
+    .m_axis_payload_tvalid     (axis_to_fir_tvalid),
+    .m_axis_payload_tready     (axis_to_fir_tready),
+    .s_axis_payload_tdata      (axis_from_fir_tdata),
+    .s_axis_payload_tkeep      ({NUM_PORTS*NIPC{1'b1}}),
+    .s_axis_payload_tlast      (axis_from_fir_tlast),
+    .s_axis_payload_tvalid     (axis_from_fir_tvalid),
+    .s_axis_payload_tready     (axis_from_fir_tready),
+    .m_axis_context_tdata      (m_axis_context_tdata),
+    .m_axis_context_tuser      (m_axis_context_tuser),
+    .m_axis_context_tlast      (m_axis_context_tlast),
+    .m_axis_context_tvalid     (m_axis_context_tvalid),
+    .m_axis_context_tready     (m_axis_context_tready),
+    .s_axis_context_tdata      (s_axis_context_tdata),
+    .s_axis_context_tuser      (s_axis_context_tuser),
+    .s_axis_context_tlast      (s_axis_context_tlast),
+    .s_axis_context_tvalid     (s_axis_context_tvalid),
+    .s_axis_context_tready     (s_axis_context_tready)
+  );
+
+
+  // The input packets are the same configuration as the output packets, so
+  // just use the header information for each incoming to create the header for
+  // each outgoing packet. This is done by connecting m_axis_context to
+  // directly to s_axis_context.
+  assign s_axis_context_tdata  = m_axis_context_tdata;
+  assign s_axis_context_tuser  = m_axis_context_tuser;
+  assign s_axis_context_tlast  = m_axis_context_tlast;
+  assign s_axis_context_tvalid = m_axis_context_tvalid;
+  assign m_axis_context_tready = s_axis_context_tready;
+
+
+  //---------------------------------------------------------------------------
+  // Control Port Address Decoding
+  //---------------------------------------------------------------------------
+
+  wire [   NUM_PORTS-1:0] m_ctrlport_req_wr;
+  wire [   NUM_PORTS-1:0] m_ctrlport_req_rd;
+  wire [20*NUM_PORTS-1:0] m_ctrlport_req_addr;
+  wire [32*NUM_PORTS-1:0] m_ctrlport_req_data;
+  wire [   NUM_PORTS-1:0] m_ctrlport_resp_ack;
+  wire [32*NUM_PORTS-1:0] m_ctrlport_resp_data;
+
+  ctrlport_decoder #(
+    .NUM_SLAVES   (NUM_PORTS),
+    .BASE_ADDR    (0),
+    .SLAVE_ADDR_W (FIR_FILTER_ADDR_W)
+  ) ctrlport_deocder_i (
+    .ctrlport_clk            (ce_clk),
+    .ctrlport_rst            (ce_rst),
+    .s_ctrlport_req_wr       (ctrlport_reg_req_wr),
+    .s_ctrlport_req_rd       (ctrlport_reg_req_rd),
+    .s_ctrlport_req_addr     (ctrlport_reg_req_addr),
+    .s_ctrlport_req_data     (ctrlport_reg_req_data),
+    .s_ctrlport_req_byte_en  (4'b0),
+    .s_ctrlport_req_has_time (1'b0),
+    .s_ctrlport_req_time     (64'b0),
+    .s_ctrlport_resp_ack     (ctrlport_reg_resp_ack),
+    .s_ctrlport_resp_status  (ctrlport_reg_resp_status),
+    .s_ctrlport_resp_data    (ctrlport_reg_resp_data),
+    .m_ctrlport_req_wr       (m_ctrlport_req_wr),
+    .m_ctrlport_req_rd       (m_ctrlport_req_rd),
+    .m_ctrlport_req_addr     (m_ctrlport_req_addr),
+    .m_ctrlport_req_data     (m_ctrlport_req_data),
+    .m_ctrlport_req_byte_en  (),
+    .m_ctrlport_req_has_time (),
+    .m_ctrlport_req_time     (),
+    .m_ctrlport_resp_ack     (m_ctrlport_resp_ack),
+    .m_ctrlport_resp_status  ({NUM_PORTS{2'b0}}),
+    .m_ctrlport_resp_data    (m_ctrlport_resp_data)
+  );
+
+
+  //---------------------------------------------------------------------------
+  // FIR Core Instances
+  //---------------------------------------------------------------------------
+
+  genvar i;
+  for (i = 0; i < NUM_PORTS; i = i+1) begin : gen_rfnoc_fir_filter_cores
+    rfnoc_fir_filter_core #(
+      .DATA_W                   (ITEM_W*NIPC),
+      .COEFF_WIDTH              (COEFF_WIDTH),
+      .NUM_COEFFS               (NUM_COEFFS),
+      .COEFFS_VEC               (COEFFS_VEC),
+      .RELOADABLE_COEFFS        (RELOADABLE_COEFFS),
+      .SYMMETRIC_COEFFS         (SYMMETRIC_COEFFS),
+      .SKIP_ZERO_COEFFS         (SKIP_ZERO_COEFFS),
+      .USE_EMBEDDED_REGS_COEFFS (USE_EMBEDDED_REGS_COEFFS)
+    ) rfnoc_fir_filter_core_i (
+      .clk                  (ce_clk),
+      .rst                  (ce_rst),
+      .s_ctrlport_req_wr    (m_ctrlport_req_wr[i]),
+      .s_ctrlport_req_rd    (m_ctrlport_req_rd[i]),
+      .s_ctrlport_req_addr  (m_ctrlport_req_addr[20*i +: 20]),
+      .s_ctrlport_req_data  (m_ctrlport_req_data[32*i +: 32]),
+      .s_ctrlport_resp_ack  (m_ctrlport_resp_ack[i]),
+      .s_ctrlport_resp_data (m_ctrlport_resp_data[32*i +: 32]),
+      .s_axis_tdata         (axis_to_fir_tdata[i*(ITEM_W*NIPC) +: (ITEM_W*NIPC)]),
+      .s_axis_tlast         (axis_to_fir_tlast[i]),
+      .s_axis_tvalid        (axis_to_fir_tvalid[i]),
+      .s_axis_tready        (axis_to_fir_tready[i]),
+      .m_axis_tdata         (axis_from_fir_tdata[i*(ITEM_W*NIPC) +: (ITEM_W*NIPC)]),
+      .m_axis_tlast         (axis_from_fir_tlast[i]),
+      .m_axis_tvalid        (axis_from_fir_tvalid[i]),
+      .m_axis_tready        (axis_from_fir_tready[i])
+    );
+  end
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/rfnoc_block_fir_filter_tb.sv b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/rfnoc_block_fir_filter_tb.sv
new file mode 100644
index 000000000..28b5493ac
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/rfnoc_block_fir_filter_tb.sv
@@ -0,0 +1,524 @@
+//
+// Copyright 2019 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: rfnoc_block_fir_filter_tb
+//
+// Description: Testbench for rfnoc_block_fir_filter
+//
+
+
+module rfnoc_block_fir_filter_tb #(
+  parameter int NUM_PORTS = 2
+);
+
+  // Include macros and time declarations for use with PkgTestExec
+  `include "test_exec.svh"
+
+  import PkgTestExec::*;
+  import PkgChdrUtils::*;
+  import PkgRfnocBlockCtrlBfm::*;
+
+  `include "rfnoc_fir_filter_regs.vh"
+
+
+  //---------------------------------------------------------------------------
+  // Local Parameters
+  //---------------------------------------------------------------------------
+
+  // Simulation parameters
+  localparam real CHDR_CLK_PER = 6.0; // 166 MHz
+  localparam real CE_CLK_PER   = 5.0; // 200 MHz
+  localparam int  STALL_PROB   = 25;  // BFM stall probability
+
+  // DUT parameters to test
+  localparam int CHDR_W      = 64;
+  localparam int THIS_PORTID = 'h123;
+  localparam int MTU         = 8;
+  //
+  localparam int NUM_COEFFS               = 41;
+  localparam int COEFF_WIDTH              = 16;
+  localparam int RELOADABLE_COEFFS        = 1;
+  localparam int SYMMETRIC_COEFFS         = 1;
+  localparam int SKIP_ZERO_COEFFS         = 1;
+  localparam int USE_EMBEDDED_REGS_COEFFS = 1;
+
+  localparam logic [COEFF_WIDTH*NUM_COEFFS-1:0] COEFFS_VEC_0 = {
+     16'sd158,   16'sd0,     16'sd33,    -16'sd0,    -16'sd256,
+     16'sd553,   16'sd573,   -16'sd542,  -16'sd1012, 16'sd349,
+     16'sd1536,  16'sd123,   -16'sd2097, -16'sd1012, 16'sd1633,
+     16'sd1608,  -16'sd3077, -16'sd5946, 16'sd3370,  16'sd10513,
+     16'sd19295,
+     16'sd10513, 16'sd3370,  -16'sd5946, -16'sd3077, 16'sd1608,
+     16'sd1633,  -16'sd1012, -16'sd2097, 16'sd123,   16'sd1536,
+     16'sd349,   -16'sd1012, -16'sd542,  16'sd573,   16'sd553,
+     -16'sd256,  -16'sd0,    16'sd33,    16'sd0,     16'sd158
+  };
+
+  localparam logic [COEFF_WIDTH*NUM_COEFFS-1:0] COEFFS_VEC_1 = {
+    16'sd32767,  16'sd0,      -16'sd32767, 16'sd0,      16'sd32767,
+    -16'sd32767, 16'sd32767,  -16'sd32767, 16'sd32767,  -16'sd32767,
+    16'sd32767,  16'sd32767,  16'sd32767,  16'sd32767,  16'sd32767,
+    -16'sd32767, -16'sd32767, -16'sd32767, -16'sd32767, -16'sd32767,
+    16'sd32767,
+    -16'sd32767, -16'sd32767, -16'sd32767, -16'sd32767, -16'sd32767,
+    16'sd32767,  16'sd32767,  16'sd32767,  16'sd32767,  16'sd32767,
+    -16'sd32767, 16'sd32767,  -16'sd32767, 16'sd32767,  -16'sd32767,
+    16'sd32767,  16'sd0,      -16'sd32767, 16'sd0,      16'sd32767
+  };
+
+  //---------------------------------------------------------------------------
+  // Clocks
+  //---------------------------------------------------------------------------
+
+  bit rfnoc_chdr_clk;
+  bit rfnoc_ctrl_clk;
+
+  sim_clock_gen #(CHDR_CLK_PER) rfnoc_chdr_clk_gen (.clk(rfnoc_chdr_clk), .rst());
+  sim_clock_gen #(CHDR_CLK_PER) rfnoc_ctrl_clk_gen (.clk(rfnoc_ctrl_clk), .rst());
+  sim_clock_gen #(CE_CLK_PER)   ce_clk_gen         (.clk(ce_clk),         .rst());
+
+
+  //---------------------------------------------------------------------------
+  // Bus Functional Models
+  //---------------------------------------------------------------------------
+
+  RfnocBackendIf        backend            (rfnoc_chdr_clk, rfnoc_ctrl_clk);
+  AxiStreamIf #(32)     m_ctrl             (rfnoc_ctrl_clk, 1'b0);
+  AxiStreamIf #(32)     s_ctrl             (rfnoc_ctrl_clk, 1'b0);
+  AxiStreamIf #(CHDR_W) m_chdr [NUM_PORTS] (rfnoc_chdr_clk, 1'b0);
+  AxiStreamIf #(CHDR_W) s_chdr [NUM_PORTS] (rfnoc_chdr_clk, 1'b0);
+
+  // Bus functional model for a software block controller
+  RfnocBlockCtrlBfm #(.CHDR_W(CHDR_W)) blk_ctrl = new(backend, m_ctrl, s_ctrl);
+
+  // Connect block controller to BFMs
+  for (genvar i = 0; i < NUM_PORTS; i++) begin : gen_bfm_connections
+    initial begin
+      blk_ctrl.connect_master_data_port(i, m_chdr[i]);
+      blk_ctrl.connect_slave_data_port(i, s_chdr[i]);
+      blk_ctrl.set_master_stall_prob(i, STALL_PROB);
+      blk_ctrl.set_slave_stall_prob(i, STALL_PROB);
+    end
+  end
+
+
+  //---------------------------------------------------------------------------
+  // DUT
+  //---------------------------------------------------------------------------
+
+  logic [NUM_PORTS*CHDR_W-1:0] s_rfnoc_chdr_tdata;
+  logic [       NUM_PORTS-1:0] s_rfnoc_chdr_tlast;
+  logic [       NUM_PORTS-1:0] s_rfnoc_chdr_tvalid;
+  logic [       NUM_PORTS-1:0] s_rfnoc_chdr_tready;
+
+  logic [NUM_PORTS*CHDR_W-1:0] m_rfnoc_chdr_tdata;
+  logic [       NUM_PORTS-1:0] m_rfnoc_chdr_tlast;
+  logic [       NUM_PORTS-1:0] m_rfnoc_chdr_tvalid;
+  logic [       NUM_PORTS-1:0] m_rfnoc_chdr_tready;
+
+  // Map the array of BFMs to a flat vector for the DUT
+  genvar i;
+  for (i = 0; i < NUM_PORTS; i++) begin : gen_dut_connections
+    // Connect BFM master to DUT slave port
+    assign s_rfnoc_chdr_tdata[CHDR_W*i+:CHDR_W] = m_chdr[i].tdata;
+    assign s_rfnoc_chdr_tlast[i]                = m_chdr[i].tlast;
+    assign s_rfnoc_chdr_tvalid[i]               = m_chdr[i].tvalid;
+    assign m_chdr[i].tready                     = s_rfnoc_chdr_tready[i];
+
+    // Connect BFM slave to DUT master port
+    assign s_chdr[i].tdata        = m_rfnoc_chdr_tdata[CHDR_W*i+:CHDR_W];
+    assign s_chdr[i].tlast        = m_rfnoc_chdr_tlast[i];
+    assign s_chdr[i].tvalid       = m_rfnoc_chdr_tvalid[i];
+    assign m_rfnoc_chdr_tready[i] = s_chdr[i].tready;
+  end
+
+
+  rfnoc_block_fir_filter #(
+    .THIS_PORTID              (THIS_PORTID),
+    .CHDR_W                   (CHDR_W),
+    .NUM_PORTS                (NUM_PORTS),
+    .MTU                      (MTU),
+    .COEFF_WIDTH              (COEFF_WIDTH),
+    .NUM_COEFFS               (NUM_COEFFS),
+    .COEFFS_VEC               (COEFFS_VEC_0),
+    .RELOADABLE_COEFFS        (RELOADABLE_COEFFS),
+    .SYMMETRIC_COEFFS         (SYMMETRIC_COEFFS),
+    .SKIP_ZERO_COEFFS         (SKIP_ZERO_COEFFS),
+    .USE_EMBEDDED_REGS_COEFFS (USE_EMBEDDED_REGS_COEFFS)
+  ) rfnoc_block_fir_filter_i (
+    .ce_clk              (ce_clk),
+    .rfnoc_chdr_clk      (rfnoc_chdr_clk),
+    .s_rfnoc_chdr_tdata  (s_rfnoc_chdr_tdata),
+    .s_rfnoc_chdr_tlast  (s_rfnoc_chdr_tlast),
+    .s_rfnoc_chdr_tvalid (s_rfnoc_chdr_tvalid),
+    .s_rfnoc_chdr_tready (s_rfnoc_chdr_tready),
+    .m_rfnoc_chdr_tdata  (m_rfnoc_chdr_tdata),
+    .m_rfnoc_chdr_tlast  (m_rfnoc_chdr_tlast),
+    .m_rfnoc_chdr_tvalid (m_rfnoc_chdr_tvalid),
+    .m_rfnoc_chdr_tready (m_rfnoc_chdr_tready),
+    .rfnoc_core_config   (backend.cfg),
+    .rfnoc_core_status   (backend.sts),
+    .rfnoc_ctrl_clk      (backend.ctrl_clk),
+    .s_rfnoc_ctrl_tdata  (m_ctrl.tdata),
+    .s_rfnoc_ctrl_tlast  (m_ctrl.tlast),
+    .s_rfnoc_ctrl_tvalid (m_ctrl.tvalid),
+    .s_rfnoc_ctrl_tready (m_ctrl.tready),
+    .m_rfnoc_ctrl_tdata  (s_ctrl.tdata),
+    .m_rfnoc_ctrl_tlast  (s_ctrl.tlast),
+    .m_rfnoc_ctrl_tvalid (s_ctrl.tvalid),
+    .m_rfnoc_ctrl_tready (s_ctrl.tready)
+  );
+
+
+
+  //---------------------------------------------------------------------------
+  // Helper Tasks
+  //---------------------------------------------------------------------------
+
+  // Translate the desired register access to a ctrlport write request.
+  task automatic write_reg(int port, byte addr, bit [31:0] value);
+    blk_ctrl.reg_write(port * (2**FIR_FILTER_ADDR_W) + addr, value);
+  endtask : write_reg
+
+  // Translate the desired register access to a ctrlport read request.
+  task automatic read_reg(int port, byte addr, output logic [31:0] value);
+    blk_ctrl.reg_read(port * (2**FIR_FILTER_ADDR_W), value);
+  endtask : read_reg
+
+
+
+  //---------------------------------------------------------------------------
+  // Test Process
+  //---------------------------------------------------------------------------
+
+  initial begin : tb_main
+    // Display testbench start message
+    test.start_tb("rfnoc_block_fir_filter_tb");
+
+    // Start the BFMs running
+    blk_ctrl.run();
+
+
+    //-------------------------------------------------------------------------
+    // Reset
+    //-------------------------------------------------------------------------
+    
+    test.start_test("Wait for Reset", 10us);
+    fork
+      blk_ctrl.reset_chdr();
+      blk_ctrl.reset_ctrl();
+    join;
+    test.end_test();
+
+
+    //-------------------------------------------------------------------------
+    // Check NoC ID and Block Info
+    //-------------------------------------------------------------------------
+    
+    test.start_test("Verify Block Info", 2us);
+    `ASSERT_ERROR(blk_ctrl.get_noc_id() == rfnoc_block_fir_filter_i.NOC_ID, "Incorrect NOC_ID Value");
+    `ASSERT_ERROR(blk_ctrl.get_num_data_i() == NUM_PORTS, "Incorrect NUM_DATA_I Value");
+    `ASSERT_ERROR(blk_ctrl.get_num_data_o() == NUM_PORTS, "Incorrect NUM_DATA_O Value");
+    `ASSERT_ERROR(blk_ctrl.get_mtu() == MTU, "Incorrect MTU Value");
+    test.end_test();
+
+
+    // Test all ports
+    for (int port = 0; port < NUM_PORTS; port++) begin : port_loop
+
+      //-----------------------------------------------------------------------
+      // Check filter length
+      //-----------------------------------------------------------------------
+
+      begin
+        int num_coeffs, num_coeffs_to_send;
+
+        test.start_test("Check filter length", 20us);
+
+        read_reg(port, REG_FIR_NUM_COEFFS, num_coeffs);
+        `ASSERT_ERROR(num_coeffs, "Incorrect number of coefficients");
+
+        // If using symmetric coefficients, send just first half
+        if (SYMMETRIC_COEFFS) begin
+          num_coeffs_to_send = num_coeffs/2 + num_coeffs[0];
+        end else begin
+          num_coeffs_to_send = num_coeffs;
+        end
+
+        // If using embedded register, coefficients must be preloaded
+        if (USE_EMBEDDED_REGS_COEFFS) begin
+          int i;
+          for (i = 0; i < num_coeffs_to_send-1; i++) begin
+            write_reg(port, REG_FIR_LOAD_COEFF, COEFFS_VEC_0[COEFF_WIDTH*i +: COEFF_WIDTH]);
+          end
+          write_reg(port, REG_FIR_LOAD_COEFF_LAST, COEFFS_VEC_0[COEFF_WIDTH*i +: COEFF_WIDTH]);
+        end
+        
+        test.end_test();
+      end
+
+
+      //-----------------------------------------------------------------------
+      // Test impulse response with default coefficients
+      //-----------------------------------------------------------------------
+      //
+      // Sending an impulse should cause the coefficients to be output.
+      //
+      //-----------------------------------------------------------------------
+
+      begin
+        chdr_word_t send_payload[$];
+        chdr_word_t recv_payload[$];
+        int num_bytes;
+        logic signed [15:0] i_samp, q_samp, i_coeff, q_coeff;
+        string s;
+
+        test.start_test("Test impulse response (default coefficients)", 20us);
+
+        // Generate packet containing an impulse and enqueue it for transfer
+        send_payload = {};
+        send_payload.push_back({16'b0, 16'b0, 16'h7FFF, 16'h7FFF});
+        for (int i = 0; i < NUM_COEFFS/2; i++) begin
+          send_payload.push_back(0);
+        end
+        blk_ctrl.send(port, send_payload, NUM_COEFFS*4);
+
+        // Enqueue two packets with zeros to push out the impulse from the
+        // pipeline (one to push out the data and one to overcome some pipeline
+        // registering).
+        send_payload = {};
+        for (int i = 0; i < NUM_COEFFS/2+1; i++) begin
+          send_payload.push_back(0);
+        end
+        for (int n = 0; n < 2; n++) begin
+          blk_ctrl.send(port, send_payload, NUM_COEFFS*4);
+        end
+
+        // Receive the result
+        blk_ctrl.recv(port, recv_payload, num_bytes);
+
+        // Check the length of the packet
+        `ASSERT_ERROR(
+          num_bytes == NUM_COEFFS*4,
+          "Received packet didn't have expected length"
+        );
+
+        for (int i = 0; i < NUM_COEFFS; i++) begin
+          // Compute the expected sample
+          i_coeff = $signed(COEFFS_VEC_0[COEFF_WIDTH*i +: COEFF_WIDTH]);
+          q_coeff = i_coeff;
+
+          // Grab the next sample
+          {i_samp, q_samp} = recv_payload[i/2][i[0]*32 +: 32];
+
+          // Check I / Q values
+          $sformat(
+            s, "Incorrect I value received on sample %0d! Expected: %0d, Received: %0d", 
+            i, i_coeff, i_samp);
+          `ASSERT_ERROR(
+            (i_samp == i_coeff) || (i_samp-1 == i_coeff) || (i_samp+1 == i_coeff), s);
+          $sformat(
+            s, "Incorrect Q value received on sample %0d! Expected: %0d, Received: %0d", 
+            i, q_coeff, q_samp);
+          `ASSERT_ERROR(
+            (q_samp == q_coeff) || (q_samp-1 == q_coeff) || (q_samp+1 == q_coeff), s);
+        end
+
+        test.end_test();
+      end
+
+
+      //-----------------------------------------------------------------------
+      // Load new coefficients
+      //-----------------------------------------------------------------------
+
+      begin
+        int i;
+        int num_coeffs_to_send;
+
+        // If using symmetric coefficients, send just first half
+        if (SYMMETRIC_COEFFS) begin
+          num_coeffs_to_send = NUM_COEFFS/2 + NUM_COEFFS[0];
+        end else begin
+          num_coeffs_to_send = NUM_COEFFS;
+        end
+
+        test.start_test("Load new coefficients", 20us);
+        for (i = 0; i < num_coeffs_to_send-1; i++) begin
+          write_reg(port, REG_FIR_LOAD_COEFF, COEFFS_VEC_1[COEFF_WIDTH*i +: COEFF_WIDTH]);
+        end
+        write_reg(port, REG_FIR_LOAD_COEFF_LAST, COEFFS_VEC_1[COEFF_WIDTH*i +: COEFF_WIDTH]);
+        test.end_test();    
+      end
+
+
+      //-----------------------------------------------------------------------
+      // Test impulse response with new coefficients
+      //-----------------------------------------------------------------------
+      //
+      // Sending an impulse should cause the coefficients to be output.
+      //
+      //-----------------------------------------------------------------------
+
+      begin
+        chdr_word_t send_payload[$];
+        chdr_word_t recv_payload[$];
+        int num_bytes;
+        logic signed [15:0] i_samp, q_samp, i_coeff, q_coeff;
+        string s;
+
+        test.start_test("Test impulse response (loaded coefficients)", 20us);
+
+        // Generate packet containing an impulse and enqueue it for transfer
+        send_payload = {};
+        send_payload.push_back({16'b0, 16'b0, 16'h7FFF, 16'h7FFF});
+        for (int i = 0; i < NUM_COEFFS/2; i++) begin
+          send_payload.push_back(0);
+        end
+        blk_ctrl.send(port, send_payload, NUM_COEFFS*4);
+
+        // Enqueue two packets with zeros to push out the impulse from the
+        // pipeline (one to push out the data and one to overcome some pipeline
+        // registering).
+        send_payload = {};
+        for (int i = 0; i < NUM_COEFFS/2+1; i++) begin
+          send_payload.push_back(0);
+        end
+        for (int n = 0; n < 2; n++) begin
+          blk_ctrl.send(port, send_payload, NUM_COEFFS*4);
+        end
+
+        // Ignore the first two packets (discard the extra data we put in when
+        // we checked the default coefficients).
+        blk_ctrl.recv(port, recv_payload, num_bytes);
+        blk_ctrl.recv(port, recv_payload, num_bytes);
+
+        // Receive the result
+        blk_ctrl.recv(port, recv_payload, num_bytes);
+
+        // Check the length of the packet
+        `ASSERT_ERROR(
+          num_bytes == NUM_COEFFS*4,
+          "Received packet didn't have expected length"
+        );
+
+        for (int i = 0; i < NUM_COEFFS; i++) begin
+          // Compute the expected sample
+          i_coeff = $signed(COEFFS_VEC_1[COEFF_WIDTH*i +: COEFF_WIDTH]);
+          q_coeff = i_coeff;
+
+          // Grab the next sample
+          {i_samp, q_samp} = recv_payload[i/2][i[0]*32 +: 32];
+
+          // Check I / Q values
+          $sformat(
+            s, "Incorrect I value received on sample %0d! Expected: %0d, Received: %0d", 
+            i, i_coeff, i_samp);
+          `ASSERT_ERROR(
+            (i_samp == i_coeff) || (i_samp-1 == i_coeff) || (i_samp+1 == i_coeff), s);
+          $sformat(
+            s, "Incorrect Q value received on sample %0d! Expected: %0d, Received: %0d", 
+            i, q_coeff, q_samp);
+          `ASSERT_ERROR(
+            (q_samp == q_coeff) || (q_samp-1 == q_coeff) || (q_samp+1 == q_coeff), s);
+        end
+
+        test.end_test();
+      end
+
+
+      //-----------------------------------------------------------------------
+      // Test step response
+      //-----------------------------------------------------------------------
+
+      begin
+        chdr_word_t send_payload[$];
+        chdr_word_t recv_payload[$];
+        int num_bytes;
+        int coeff_sum;
+        logic signed [15:0] i_samp, q_samp;
+        string s;
+
+        test.start_test("Test step response", 20us);
+
+        // Generate a step function packet
+        send_payload = {};
+        for (int i = 0; i < NUM_COEFFS/2+1; i++) begin
+          send_payload.push_back({16'h7FFF,16'h7FFF,16'h7FFF,16'h7FFF});
+        end
+
+        // Enqueue step function two times, once to fill up the pipeline and
+        // another to get the actual response.
+        for (int n = 0; n < 2; n++) begin
+          blk_ctrl.send(port, send_payload, NUM_COEFFS*4);
+        end
+
+        // Enqueue two packets with zeros to push out the impulse from the
+        // pipeline (one to push out the data and one to overcome some pipeline
+        // registering).
+        send_payload = {};
+        for (int i = 0; i < NUM_COEFFS/2+1; i++) begin
+          send_payload.push_back(0);
+        end
+        for (int n = 0; n < 2; n++) begin
+          blk_ctrl.send(port, send_payload, NUM_COEFFS*4);
+        end
+
+        // Ignore the first two packets (discard the extra data we put in
+        // during the previous test).
+        for (int n = 0; n < 3; n++) begin
+          blk_ctrl.recv(port, recv_payload, num_bytes);
+        end
+
+        // Receive the result
+        blk_ctrl.recv(port, recv_payload, num_bytes);
+
+        // Check the length of the packet
+        `ASSERT_ERROR(
+          num_bytes == NUM_COEFFS*4,
+          "Received packet didn't have expected length"
+        );
+
+        // Calculate sum of all the coefficients
+        coeff_sum = 0;
+        for (int i = 0; i < NUM_COEFFS; i++) begin
+            coeff_sum += $signed(COEFFS_VEC_1[COEFF_WIDTH*i +: COEFF_WIDTH]);
+        end
+
+        for (int i = 0; i < NUM_COEFFS; i++) begin
+          // Grab the next sample
+          {i_samp, q_samp} = recv_payload[i/2][i[0]*32 +: 32];
+
+          // Check I / Q values
+          $sformat(
+            s, "Incorrect I value received on sample %0d! Expected: %0d, Received: %0d", 
+            i, coeff_sum, i_samp);
+          `ASSERT_ERROR(
+            (i_samp == coeff_sum) || (i_samp-1 == coeff_sum) || (i_samp+1 == coeff_sum),
+            s
+          );
+          $sformat(
+            s, "Incorrect Q value received on sample %0d! Expected: %0d, Received: %0d", 
+            i, coeff_sum, q_samp);
+          `ASSERT_ERROR(
+            (q_samp == coeff_sum) || (q_samp-1 == coeff_sum) || (q_samp+1 == coeff_sum),
+            s
+          );
+        end
+
+        test.end_test();
+      end
+
+    end : port_loop
+
+
+    //-------------------------------------------------------------------------
+    // All done!
+    //-------------------------------------------------------------------------
+
+    test.end_tb(1);
+
+  end : tb_main
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/rfnoc_fir_filter_core.v b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/rfnoc_fir_filter_core.v
new file mode 100644
index 000000000..774f43761
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/rfnoc_fir_filter_core.v
@@ -0,0 +1,228 @@
+//
+// Copyright 2019 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Description:
+//
+//   Core module for a single instance of an FIR filter, implementing the
+//   registers and signal processing for a single I/Q filter. It assumes the
+//   data stream is an IQ pair with I in the upper 32 bits and Q is the lower
+//   32 bits.
+//
+// Parameters:
+//
+//   DATA_W                   : Width of the input/output data stream to
+//                              process.
+//
+//   BASE_ADDR                : Control port base address to which this block
+//                              responds.
+// 
+//   COEFF_WIDTH              : Coefficient width
+//
+//   NUM_COEFFS               : Number of coefficients / filter taps
+//
+//   COEFFS_VEC               : Vector of NUM_COEFFS values, each of width
+//                              COEFF_WIDTH, to initialize the filter
+//                              coefficients. Defaults to an impulse.
+//
+//   RELOADABLE_COEFFS        : Enable (1) or disable (0) reloading
+//                              coefficients at runtime
+//
+//   SYMMETRIC_COEFFS         : Reduce multiplier usage by approximately half
+//                              if coefficients are symmetric
+//
+//   SKIP_ZERO_COEFFS         : Reduce multiplier usage by assuming zero valued
+//                              coefficients in DEFAULT_COEFFS are always zero.
+//                              Useful for halfband filters.
+//
+//   USE_EMBEDDED_REGS_COEFFS : Reduce register usage by only using embedded
+//                              registers in DSP slices. Updating taps while
+//                              streaming will cause temporary output
+//                              corruption!
+//
+//   Note: If using USE_EMBEDDED_REGS_COEFFS, coefficients must be written at 
+//   least once since COEFFS_VEC is ignored!
+
+
+module rfnoc_fir_filter_core #(
+  parameter        DATA_W            = 32,
+  parameter [19:0] BASE_ADDR         = 0,
+
+  // FIR Filter Parameters
+  parameter COEFF_WIDTH              = 16,
+  parameter NUM_COEFFS               = 41,
+  parameter [NUM_COEFFS*COEFF_WIDTH-1:0] COEFFS_VEC = // Make impulse by default
+    { 
+      {1'b0, {(COEFF_WIDTH-1){1'b1}} },        // Max positive value
+      {(COEFF_WIDTH*(NUM_COEFFS-1)){1'b0}}     // Zero for remaining coefficients
+    },
+  parameter RELOADABLE_COEFFS        = 1,
+  parameter SYMMETRIC_COEFFS         = 0,
+  parameter SKIP_ZERO_COEFFS         = 0,
+  parameter USE_EMBEDDED_REGS_COEFFS = 1
+) (
+
+  input  wire clk,
+  input  wire rst,
+
+  //---------------------------------------------------------------------------
+  // AXIS CTRL Port
+  //---------------------------------------------------------------------------
+
+  // Master
+  input  wire        s_ctrlport_req_wr,
+  input  wire        s_ctrlport_req_rd,
+  input  wire [19:0] s_ctrlport_req_addr,
+  input  wire [31:0] s_ctrlport_req_data,
+  output reg         s_ctrlport_resp_ack,
+  output reg  [31:0] s_ctrlport_resp_data,
+
+  //---------------------------------------------------------------------------
+  // Data Interface
+  //---------------------------------------------------------------------------
+
+  // Input data stream
+  input  wire [DATA_W-1:0] s_axis_tdata,
+  input  wire              s_axis_tlast,
+  input  wire              s_axis_tvalid,
+  output wire              s_axis_tready,
+
+  // Output data stream
+  output wire [DATA_W-1:0] m_axis_tdata,
+  output wire              m_axis_tlast,
+  output wire              m_axis_tvalid,
+  input  wire              m_axis_tready
+);
+
+  reg  [COEFF_WIDTH-1:0] m_axis_reload_tdata;
+  reg                    m_axis_reload_tvalid;
+  reg                    m_axis_reload_tlast;
+  wire                   m_axis_reload_tready;
+
+
+  //---------------------------------------------------------------------------
+  // Registers
+  //---------------------------------------------------------------------------
+
+  `include "rfnoc_fir_filter_regs.vh"
+
+  // Separate the address into the block and register portions. Ignore the byte
+  // offset.
+  wire [20:0] block_addr = s_ctrlport_req_addr[19:FIR_FILTER_ADDR_W];
+  wire [19:0] reg_addr   = { s_ctrlport_req_addr[FIR_FILTER_ADDR_W:2], 2'b0 };
+
+  always @(posedge clk) begin
+    if (rst) begin
+      s_ctrlport_resp_ack  <= 0;
+      m_axis_reload_tvalid <= 0;
+      s_ctrlport_resp_data <= {32{1'bX}};
+      m_axis_reload_tdata  <= {DATA_W{1'bX}};
+      m_axis_reload_tlast  <= 1'bX;
+    end else if (block_addr == BASE_ADDR) begin
+      // Default assignments
+      s_ctrlport_resp_ack  <= 0;
+      s_ctrlport_resp_data <= 0;
+
+      // Handle write acknowledgments. Don't ack the register write until it
+      // gets accepted by the FIR filter.
+      if (m_axis_reload_tvalid && m_axis_reload_tready) begin
+        m_axis_reload_tvalid <= 1'b0;
+        s_ctrlport_resp_ack  <= 1'b1;
+      end
+
+      // Handle register writes
+      if (s_ctrlport_req_wr) begin
+        if (reg_addr == REG_FIR_LOAD_COEFF) begin
+          m_axis_reload_tdata  <= s_ctrlport_req_data[COEFF_WIDTH-1:0];
+          m_axis_reload_tvalid <= 1'b1;
+          m_axis_reload_tlast  <= 1'b0;
+        end else if (reg_addr == REG_FIR_LOAD_COEFF_LAST) begin
+          m_axis_reload_tdata  <= s_ctrlport_req_data[COEFF_WIDTH-1:0];
+          m_axis_reload_tvalid <= 1'b1;
+          m_axis_reload_tlast  <= 1'b1;
+        end
+      end
+
+      // Handle register reads
+      if (s_ctrlport_req_rd) begin
+        // Ignore the upper bits so the we respond to any port
+        if (reg_addr == REG_FIR_NUM_COEFFS) begin
+          s_ctrlport_resp_data <= NUM_COEFFS;
+          s_ctrlport_resp_ack  <= 1;
+        end
+      end
+    end
+  end
+
+
+  //---------------------------------------------------------------------------
+  // FIR Filter Instances
+  //---------------------------------------------------------------------------
+
+  localparam IN_WIDTH  = DATA_W/2;
+  localparam OUT_WIDTH = DATA_W/2;
+
+  // I
+  axi_fir_filter #(
+    .IN_WIDTH                 (IN_WIDTH),
+    .COEFF_WIDTH              (COEFF_WIDTH),
+    .OUT_WIDTH                (OUT_WIDTH),
+    .NUM_COEFFS               (NUM_COEFFS),
+    .COEFFS_VEC               (COEFFS_VEC),
+    .RELOADABLE_COEFFS        (RELOADABLE_COEFFS),
+    .BLANK_OUTPUT             (1),
+    // Optional optimizations
+    .SYMMETRIC_COEFFS         (SYMMETRIC_COEFFS),
+    .SKIP_ZERO_COEFFS         (SKIP_ZERO_COEFFS),
+    .USE_EMBEDDED_REGS_COEFFS (USE_EMBEDDED_REGS_COEFFS)
+  ) inst_axi_fir_filter_i (
+    .clk                  (clk),
+    .reset                (rst),
+    .clear                (1'b0),
+    .s_axis_data_tdata    (s_axis_tdata[2*IN_WIDTH-1:IN_WIDTH]),
+    .s_axis_data_tlast    (s_axis_tlast),
+    .s_axis_data_tvalid   (s_axis_tvalid),
+    .s_axis_data_tready   (s_axis_tready),
+    .m_axis_data_tdata    (m_axis_tdata[2*OUT_WIDTH-1:OUT_WIDTH]),
+    .m_axis_data_tlast    (m_axis_tlast),
+    .m_axis_data_tvalid   (m_axis_tvalid),
+    .m_axis_data_tready   (m_axis_tready),
+    .s_axis_reload_tdata  (m_axis_reload_tdata),
+    .s_axis_reload_tlast  (m_axis_reload_tlast),
+    .s_axis_reload_tvalid (m_axis_reload_tvalid),
+    .s_axis_reload_tready (m_axis_reload_tready)
+  );
+
+  // Q
+  axi_fir_filter #(
+    .IN_WIDTH                 (IN_WIDTH),
+    .COEFF_WIDTH              (COEFF_WIDTH),
+    .OUT_WIDTH                (OUT_WIDTH),
+    .NUM_COEFFS               (NUM_COEFFS),
+    .COEFFS_VEC               (COEFFS_VEC),
+    .RELOADABLE_COEFFS        (RELOADABLE_COEFFS),
+    .BLANK_OUTPUT             (1),
+    // Optional optimizations
+    .SYMMETRIC_COEFFS         (SYMMETRIC_COEFFS),
+    .SKIP_ZERO_COEFFS         (SKIP_ZERO_COEFFS),
+    .USE_EMBEDDED_REGS_COEFFS (USE_EMBEDDED_REGS_COEFFS)
+  ) inst_axi_fir_filter_q (
+    .clk                  (clk),
+    .reset                (rst),
+    .clear                (1'b0),
+    .s_axis_data_tdata    (s_axis_tdata[IN_WIDTH-1:0]),
+    .s_axis_data_tlast    (s_axis_tlast),
+    .s_axis_data_tvalid   (s_axis_tvalid),
+    .s_axis_data_tready   (),
+    .m_axis_data_tdata    (m_axis_tdata[OUT_WIDTH-1:0]),
+    .m_axis_data_tlast    (),
+    .m_axis_data_tvalid   (),
+    .m_axis_data_tready   (m_axis_tready),
+    .s_axis_reload_tdata  (m_axis_reload_tdata),
+    .s_axis_reload_tlast  (m_axis_reload_tlast),
+    .s_axis_reload_tvalid (m_axis_reload_tvalid),
+    .s_axis_reload_tready ()
+  );
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/rfnoc_fir_filter_regs.vh b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/rfnoc_fir_filter_regs.vh
new file mode 100644
index 000000000..0e070e3a3
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/rfnoc_fir_filter_regs.vh
@@ -0,0 +1,51 @@
+//
+// Copyright 2019 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module:  fir_filter_regs (Header)
+//
+// Description:  Header file for rfnoc_block_fir_filter. All registers are 
+//               32-bit words from software's perspective.
+//
+
+// Address space size, per FIR filter. That is, each filter is separated in the 
+// CTRL Port address space by 2^FIR_FILTER_ADDR_W bytes.
+localparam FIR_FILTER_ADDR_W = 4;
+
+
+
+// REG_FIR_NUM_COEFFS (R)
+//
+// Contains the number of coefficients for the filter.
+//
+// [31:0] : Returns the number of coefficients (read-only)
+//
+localparam REG_FIR_NUM_COEFFS = 'h0;
+
+
+// REG_FIR_LOAD_COEFF (R)
+//
+// Register for inputting the next coefficient to be loaded into the filter. To
+// load a new set of filter coefficients, write NUM_COEFFS-1 coefficients to
+// this register, then write the last coefficient to REG_FIR_LOAD_COEFF_LAST.
+// The width of each coefficient is set by the COEFF_WIDTH parameter on the
+// block.
+//
+// [31:(32-COEFF_WIDTH)] : Reserved
+// [COEFF_WIDTH-1:0]     : The next coefficient to be loaded
+//
+localparam REG_FIR_LOAD_COEFF = 'h4;
+
+
+// REG_FIR_LOAD_COEFF_LAST (R)
+//
+// Register for inputting the last coefficient to be loaded into the filter. To
+// load a new set of filter coefficients, write NUM_COEFFS-1 coefficients to
+// REG_FIR_LOAD_COEFF, then write the last coefficient to this register. The
+// width of each coefficient is set by the COEFF_WIDTH parameter on the block.
+//
+// [31:(32-COEFF_WIDTH)] : Reserved
+// [COEFF_WIDTH-1:0]     : The next coefficient to be loaded
+//
+localparam REG_FIR_LOAD_COEFF_LAST = 'h8;
\ No newline at end of file
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_null_src_sink/Makefile b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_null_src_sink/Makefile
new file mode 100644
index 000000000..30ce14aec
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_null_src_sink/Makefile
@@ -0,0 +1,45 @@
+#
+# Copyright 2019 Ettus Research, A National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+#-------------------------------------------------
+# Top-of-Makefile
+#-------------------------------------------------
+# Define BASE_DIR to point to the "top" dir
+BASE_DIR = $(abspath ../../../../top)
+# Include viv_sim_preamble after defining BASE_DIR
+include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
+
+#-------------------------------------------------
+# Design Specific
+#-------------------------------------------------
+# Include makefiles and sources for the DUT and its dependencies
+include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs
+include $(BASE_DIR)/../lib/rfnoc/utils/Makefile.srcs
+include Makefile.srcs
+
+DESIGN_SRCS += $(abspath \
+$(RFNOC_CORE_SRCS) \
+$(RFNOC_UTIL_SRCS) \
+$(RFNOC_OOT_SRCS) \
+)
+
+#-------------------------------------------------
+# Testbench Specific
+#-------------------------------------------------
+SIM_TOP = rfnoc_block_null_src_sink_tb
+
+SIM_SRCS = \
+$(abspath rfnoc_block_null_src_sink_tb.sv) \
+
+# MODELSIM_USER_DO = $(abspath wave.do)
+
+#-------------------------------------------------
+# Bottom-of-Makefile
+#-------------------------------------------------
+# Include all simulator specific makefiles here
+# Each should define a unique target to simulate
+# e.g. xsim, vsim, etc and a common "clean" target
+include $(BASE_DIR)/../tools/make/viv_simulator.mak
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_null_src_sink/Makefile.srcs b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_null_src_sink/Makefile.srcs
new file mode 100644
index 000000000..a99bec7db
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_null_src_sink/Makefile.srcs
@@ -0,0 +1,12 @@
+#
+# Copyright 2019 Ettus Research, A National Instruments Brand
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+##################################################
+# RFNoC Utility Sources
+##################################################
+RFNOC_OOT_SRCS += $(abspath $(addprefix $(BASE_DIR)/../lib/rfnoc/blocks/rfnoc_block_null_src_sink/, \
+rfnoc_block_null_src_sink.v \
+))
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_null_src_sink/rfnoc_block_null_src_sink.v b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_null_src_sink/rfnoc_block_null_src_sink.v
new file mode 100644
index 000000000..f4f4d7651
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_null_src_sink/rfnoc_block_null_src_sink.v
@@ -0,0 +1,338 @@
+//
+// Copyright 2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: rfnoc_block_null_src_sink
+// Description:
+//
+// Parameters:
+//
+// Signals:
+
+module rfnoc_block_null_src_sink #(
+  parameter  [9:0] THIS_PORTID = 10'd0,
+  parameter        CHDR_W      = 64,
+  parameter        NIPC        = 2,
+  parameter  [5:0] MTU         = 10
+)(
+  // RFNoC Framework Clocks and Resets
+  input  wire                   rfnoc_chdr_clk,
+  input  wire                   rfnoc_ctrl_clk,
+  // RFNoC Backend Interface    
+  input  wire [511:0]           rfnoc_core_config,
+  output wire [511:0]           rfnoc_core_status,
+  // 2 CHDR Input Ports (from framework)        
+  input  wire [(CHDR_W*2)-1:0]  s_rfnoc_chdr_tdata,
+  input  wire [1:0]             s_rfnoc_chdr_tlast,
+  input  wire [1:0]             s_rfnoc_chdr_tvalid,
+  output wire [1:0]             s_rfnoc_chdr_tready,
+  // 2 CHDR Output Ports (to framework)         
+  output wire [(CHDR_W*2)-1:0]  m_rfnoc_chdr_tdata,
+  output wire [1:0]             m_rfnoc_chdr_tlast,
+  output wire [1:0]             m_rfnoc_chdr_tvalid,
+  input  wire [1:0]             m_rfnoc_chdr_tready,
+  // AXIS-Ctrl Input Port (from framework)
+  input  wire [31:0]            s_rfnoc_ctrl_tdata,
+  input  wire                   s_rfnoc_ctrl_tlast,
+  input  wire                   s_rfnoc_ctrl_tvalid,
+  output wire                   s_rfnoc_ctrl_tready,
+  // AXIS-Ctrl Output Port (to framework)
+  output wire [31:0]            m_rfnoc_ctrl_tdata,
+  output wire                   m_rfnoc_ctrl_tlast,
+  output wire                   m_rfnoc_ctrl_tvalid,
+  input  wire                   m_rfnoc_ctrl_tready
+);
+
+  `include "../../core/rfnoc_chdr_utils.vh"
+
+  localparam [19:0] REG_CTRL_STATUS       = 20'h00;
+  localparam [19:0] REG_SRC_LINES_PER_PKT = 20'h04;
+  localparam [19:0] REG_SRC_BYTES_PER_PKT = 20'h08;
+  localparam [19:0] REG_SRC_THROTTLE_CYC  = 20'h0C;
+  localparam [19:0] REG_SNK_LINE_CNT_LO   = 20'h10;
+  localparam [19:0] REG_SNK_LINE_CNT_HI   = 20'h14;
+  localparam [19:0] REG_SNK_PKT_CNT_LO    = 20'h18;
+  localparam [19:0] REG_SNK_PKT_CNT_HI    = 20'h1C;
+  localparam [19:0] REG_SRC_LINE_CNT_LO   = 20'h20;
+  localparam [19:0] REG_SRC_LINE_CNT_HI   = 20'h24;
+  localparam [19:0] REG_SRC_PKT_CNT_LO    = 20'h28;
+  localparam [19:0] REG_SRC_PKT_CNT_HI    = 20'h2C;
+  localparam [19:0] REG_LOOP_LINE_CNT_LO  = 20'h30;
+  localparam [19:0] REG_LOOP_LINE_CNT_HI  = 20'h34;
+  localparam [19:0] REG_LOOP_PKT_CNT_LO   = 20'h38;
+  localparam [19:0] REG_LOOP_PKT_CNT_HI   = 20'h3C;
+
+  wire                 rfnoc_chdr_rst;
+  wire                 rfnoc_ctrl_rst;
+
+  wire                 ctrlport_req_wr;
+  wire                 ctrlport_req_rd;
+  wire [19:0]          ctrlport_req_addr;
+  wire [31:0]          ctrlport_req_data;
+  reg                  ctrlport_resp_ack;
+  reg  [31:0]          ctrlport_resp_data;
+
+  wire [(32*NIPC)-1:0] src_pyld_tdata , snk_pyld_tdata , loop_pyld_tdata ;
+  wire [NIPC-1:0]      src_pyld_tkeep , snk_pyld_tkeep , loop_pyld_tkeep ;
+  wire                 src_pyld_tlast , snk_pyld_tlast , loop_pyld_tlast ;
+  wire                 src_pyld_tvalid, snk_pyld_tvalid, loop_pyld_tvalid;
+  wire                 src_pyld_tready, snk_pyld_tready, loop_pyld_tready;
+
+  wire [CHDR_W-1:0]    src_ctxt_tdata , snk_ctxt_tdata , loop_ctxt_tdata ;
+  wire [3:0]           src_ctxt_tuser , snk_ctxt_tuser , loop_ctxt_tuser ;
+  wire                 src_ctxt_tlast , snk_ctxt_tlast , loop_ctxt_tlast ;
+  wire                 src_ctxt_tvalid, snk_ctxt_tvalid, loop_ctxt_tvalid;
+  wire                 src_ctxt_tready, snk_ctxt_tready, loop_ctxt_tready;
+
+  // NoC Shell
+  // ---------------------------
+  noc_shell_generic_ctrlport_pyld_chdr #(
+    .NOC_ID                   (32'h0000_0001),
+    .THIS_PORTID              (THIS_PORTID),
+    .CHDR_W                   (CHDR_W),
+    .CTRL_FIFOSIZE            (5),
+    .CTRLPORT_SLV_EN          (0),
+    .NUM_DATA_I               (2),
+    .NUM_DATA_O               (2),
+    .ITEM_W                   (32),
+    .NIPC                     (NIPC),
+    .MTU                      (MTU),
+    .CTXT_FIFOSIZE            (1),
+    .PYLD_FIFOSIZE            (1)
+  ) noc_shell_i (
+    .rfnoc_chdr_clk           (rfnoc_chdr_clk                     ),
+    .rfnoc_chdr_rst           (rfnoc_chdr_rst                     ),
+    .rfnoc_ctrl_clk           (rfnoc_ctrl_clk                     ),
+    .rfnoc_ctrl_rst           (rfnoc_ctrl_rst                     ),
+    .rfnoc_core_config        (rfnoc_core_config                  ),
+    .rfnoc_core_status        (rfnoc_core_status                  ),
+    .s_rfnoc_chdr_tdata       (s_rfnoc_chdr_tdata                 ),
+    .s_rfnoc_chdr_tlast       (s_rfnoc_chdr_tlast                 ),
+    .s_rfnoc_chdr_tvalid      (s_rfnoc_chdr_tvalid                ),
+    .s_rfnoc_chdr_tready      (s_rfnoc_chdr_tready                ),
+    .m_rfnoc_chdr_tdata       (m_rfnoc_chdr_tdata                 ),
+    .m_rfnoc_chdr_tlast       (m_rfnoc_chdr_tlast                 ),
+    .m_rfnoc_chdr_tvalid      (m_rfnoc_chdr_tvalid                ),
+    .m_rfnoc_chdr_tready      (m_rfnoc_chdr_tready                ),
+    .s_rfnoc_ctrl_tdata       (s_rfnoc_ctrl_tdata                 ),
+    .s_rfnoc_ctrl_tlast       (s_rfnoc_ctrl_tlast                 ),
+    .s_rfnoc_ctrl_tvalid      (s_rfnoc_ctrl_tvalid                ),
+    .s_rfnoc_ctrl_tready      (s_rfnoc_ctrl_tready                ),
+    .m_rfnoc_ctrl_tdata       (m_rfnoc_ctrl_tdata                 ),
+    .m_rfnoc_ctrl_tlast       (m_rfnoc_ctrl_tlast                 ),
+    .m_rfnoc_ctrl_tvalid      (m_rfnoc_ctrl_tvalid                ),
+    .m_rfnoc_ctrl_tready      (m_rfnoc_ctrl_tready                ),
+    .m_ctrlport_req_wr        (ctrlport_req_wr                    ),
+    .m_ctrlport_req_rd        (ctrlport_req_rd                    ),
+    .m_ctrlport_req_addr      (ctrlport_req_addr                  ),
+    .m_ctrlport_req_data      (ctrlport_req_data                  ),
+    .m_ctrlport_req_byte_en   (                                   ),
+    .m_ctrlport_req_has_time  (                                   ),
+    .m_ctrlport_req_time      (                                   ),
+    .m_ctrlport_resp_ack      (ctrlport_resp_ack                  ),
+    .m_ctrlport_resp_status   (2'd0                               ),
+    .m_ctrlport_resp_data     (ctrlport_resp_data                 ),
+    .s_ctrlport_req_wr        ('h0                                ),
+    .s_ctrlport_req_rd        ('h0                                ),
+    .s_ctrlport_req_addr      ('h0                                ),
+    .s_ctrlport_req_portid    ('h0                                ),
+    .s_ctrlport_req_rem_epid  ('h0                                ),
+    .s_ctrlport_req_rem_portid('h0                                ),
+    .s_ctrlport_req_data      ('h0                                ),
+    .s_ctrlport_req_byte_en   ('h0                                ),
+    .s_ctrlport_req_has_time  ('h0                                ),
+    .s_ctrlport_req_time      ('h0                                ),
+    .s_ctrlport_resp_ack      (                                   ),
+    .s_ctrlport_resp_status   (                                   ),
+    .s_ctrlport_resp_data     (                                   ),
+    .m_axis_payload_tdata     ({loop_pyld_tdata , snk_pyld_tdata }),
+    .m_axis_payload_tkeep     ({loop_pyld_tkeep , snk_pyld_tkeep }),
+    .m_axis_payload_tlast     ({loop_pyld_tlast , snk_pyld_tlast }),
+    .m_axis_payload_tvalid    ({loop_pyld_tvalid, snk_pyld_tvalid}),
+    .m_axis_payload_tready    ({loop_pyld_tready, snk_pyld_tready}),
+    .m_axis_context_tdata     ({loop_ctxt_tdata , snk_ctxt_tdata }),
+    .m_axis_context_tuser     ({loop_ctxt_tuser , snk_ctxt_tuser }),
+    .m_axis_context_tlast     ({loop_ctxt_tlast , snk_ctxt_tlast }),
+    .m_axis_context_tvalid    ({loop_ctxt_tvalid, snk_ctxt_tvalid}),
+    .m_axis_context_tready    ({loop_ctxt_tready, snk_ctxt_tready}),
+    .s_axis_payload_tdata     ({loop_pyld_tdata , src_pyld_tdata }),
+    .s_axis_payload_tkeep     ({loop_pyld_tkeep , src_pyld_tkeep }),
+    .s_axis_payload_tlast     ({loop_pyld_tlast , src_pyld_tlast }),
+    .s_axis_payload_tvalid    ({loop_pyld_tvalid, src_pyld_tvalid}),
+    .s_axis_payload_tready    ({loop_pyld_tready, src_pyld_tready}),
+    .s_axis_context_tdata     ({loop_ctxt_tdata , src_ctxt_tdata }),
+    .s_axis_context_tuser     ({loop_ctxt_tuser , src_ctxt_tuser }),
+    .s_axis_context_tlast     ({loop_ctxt_tlast , src_ctxt_tlast }),
+    .s_axis_context_tvalid    ({loop_ctxt_tvalid, src_ctxt_tvalid}),
+    .s_axis_context_tready    ({loop_ctxt_tready, src_ctxt_tready})
+  );
+
+  // Packet Counters
+  // ---------------------------
+  reg        reg_clear_cnts = 1'b0;
+  reg [63:0] snk_line_cnt  = 64'd0, snk_pkt_cnt  = 64'd0;
+  reg [63:0] src_line_cnt  = 64'd0, src_pkt_cnt  = 64'd0;
+  reg [63:0] loop_line_cnt = 64'd0, loop_pkt_cnt = 64'd0;
+
+  always @(posedge rfnoc_chdr_clk) begin
+    if (rfnoc_chdr_rst | reg_clear_cnts) begin
+      snk_line_cnt  <= 64'd0;
+      snk_pkt_cnt   <= 64'd0;
+      src_line_cnt  <= 64'd0;
+      src_pkt_cnt   <= 64'd0;
+      loop_line_cnt <= 64'd0;
+      loop_pkt_cnt  <= 64'd0;
+    end else begin
+      if (snk_pyld_tvalid & snk_pyld_tready) begin
+        snk_line_cnt <= snk_line_cnt + 1;
+        if (snk_pyld_tlast)
+          snk_pkt_cnt <= snk_pkt_cnt + 1;
+      end
+      if (src_pyld_tvalid & src_pyld_tready) begin
+        src_line_cnt <= src_line_cnt + 1;
+        if (src_pyld_tlast)
+          src_pkt_cnt <= src_pkt_cnt + 1;
+      end
+      if (loop_pyld_tvalid & loop_pyld_tready) begin
+        loop_line_cnt <= loop_line_cnt + 1;
+        if (loop_pyld_tlast)
+          loop_pkt_cnt <= loop_pkt_cnt + 1;
+      end
+    end
+  end
+
+  // NULL Sink
+  // ---------------------------
+  assign snk_pyld_tready = 1'b1;
+  assign snk_ctxt_tready = 1'b1;
+
+  // NULL Source
+  // ---------------------------
+  reg        reg_src_en = 1'b0;
+  reg [11:0] reg_src_lpp = 12'd0;
+  reg [15:0] reg_src_bpp = 16'd0;
+  reg [9:0]  reg_throttle_cyc = 10'd0;
+
+  localparam [1:0] ST_HDR  = 2'd0;
+  localparam [1:0] ST_PYLD = 2'd1;
+  localparam [1:0] ST_WAIT = 2'd2;
+
+  reg  [1:0] state = ST_HDR;
+  reg [11:0] lines_left = 12'd0;
+  reg  [9:0] throttle_cntr = 10'd0;
+
+  always @(posedge rfnoc_chdr_clk) begin
+    if (rfnoc_chdr_rst) begin
+      state <= ST_HDR;
+    end else begin
+      case (state)
+        ST_HDR: begin
+          if (src_ctxt_tvalid && src_ctxt_tready) begin
+            state <= ST_PYLD;
+            lines_left <= reg_src_lpp;
+          end
+        end
+        ST_PYLD: begin
+          if (src_pyld_tvalid && src_pyld_tready) begin
+            if (src_pyld_tlast) begin
+              if (reg_throttle_cyc == 10'd0) begin
+                state <= ST_HDR;
+              end else begin
+                state <= ST_WAIT;
+                throttle_cntr <= reg_throttle_cyc;
+              end
+            end else begin
+              lines_left <= lines_left - 12'd1;
+            end
+          end
+        end
+        ST_WAIT: begin
+          if (throttle_cntr == 10'd0)
+            state <= ST_HDR;
+          else
+            throttle_cntr <= throttle_cntr - 10'd1;
+        end
+        default: begin
+          state <= ST_HDR;
+        end
+      endcase
+    end
+  end
+
+  assign src_pyld_tdata  = {NIPC{{~src_line_cnt[15:0], src_line_cnt[15:0]}}};
+  assign src_pyld_tkeep  = {NIPC{1'b1}};
+  assign src_pyld_tlast  = (lines_left == 12'd0);
+  assign src_pyld_tvalid = (state == ST_PYLD);
+
+  assign src_ctxt_tdata  = chdr_build_header(
+    6'd0, 1'b0, 1'b0, CHDR_PKT_TYPE_DATA, CHDR_NO_MDATA, src_pkt_cnt[15:0], reg_src_bpp, 16'd0);
+  assign src_ctxt_tuser  = CONTEXT_FIELD_HDR;
+  assign src_ctxt_tlast  = 1'b1;
+  assign src_ctxt_tvalid = (state == ST_HDR && reg_src_en);
+
+
+  // Register Interface
+  // ---------------------------
+  always @(posedge rfnoc_chdr_clk) begin
+    if (rfnoc_chdr_rst) begin
+      ctrlport_resp_ack <= 1'b0;
+    end else begin
+      // All transactions finish in 1 cycle
+      ctrlport_resp_ack <= ctrlport_req_wr | ctrlport_req_rd;
+      // Handle register writes
+      if (ctrlport_req_wr) begin
+        case(ctrlport_req_addr)
+          REG_CTRL_STATUS:
+            {reg_src_en, reg_clear_cnts} <= ctrlport_req_data[1:0];
+          REG_SRC_LINES_PER_PKT:
+            reg_src_lpp <= ctrlport_req_data[11:0];
+          REG_SRC_BYTES_PER_PKT:
+            reg_src_bpp <= ctrlport_req_data[15:0];
+          REG_SRC_THROTTLE_CYC:
+            reg_throttle_cyc <= ctrlport_req_data[9:0];
+        endcase
+      end
+      // Handle register reads
+      if (ctrlport_req_rd) begin
+        case(ctrlport_req_addr)
+          REG_CTRL_STATUS:
+            ctrlport_resp_data <= {NIPC[7:0], 8'd32, state, 12'h0, reg_src_en, reg_clear_cnts};
+          REG_SRC_LINES_PER_PKT:
+            ctrlport_resp_data <= {20'h0, reg_src_lpp};
+          REG_SRC_BYTES_PER_PKT:
+            ctrlport_resp_data <= {16'h0, reg_src_bpp};
+          REG_SRC_THROTTLE_CYC:
+            ctrlport_resp_data <= {22'h0, reg_throttle_cyc};
+          REG_SNK_LINE_CNT_LO:
+            ctrlport_resp_data <= snk_line_cnt[31:0];
+          REG_SNK_LINE_CNT_HI:
+            ctrlport_resp_data <= snk_line_cnt[63:32];
+          REG_SNK_PKT_CNT_LO:
+            ctrlport_resp_data <= snk_pkt_cnt[31:0];
+          REG_SNK_PKT_CNT_HI:
+            ctrlport_resp_data <= snk_pkt_cnt[63:32];
+          REG_SRC_LINE_CNT_LO:
+            ctrlport_resp_data <= src_line_cnt[31:0];
+          REG_SRC_LINE_CNT_HI:
+            ctrlport_resp_data <= src_line_cnt[63:32];
+          REG_SRC_PKT_CNT_LO:
+            ctrlport_resp_data <= src_pkt_cnt[31:0];
+          REG_SRC_PKT_CNT_HI:
+            ctrlport_resp_data <= src_pkt_cnt[63:32];
+          REG_LOOP_LINE_CNT_LO:
+            ctrlport_resp_data <= loop_line_cnt[31:0];
+          REG_LOOP_LINE_CNT_HI:
+            ctrlport_resp_data <= loop_line_cnt[63:32];
+          REG_LOOP_PKT_CNT_LO:
+            ctrlport_resp_data <= loop_pkt_cnt[31:0];
+          REG_LOOP_PKT_CNT_HI:
+            ctrlport_resp_data <= loop_pkt_cnt[63:32];
+          default:
+            ctrlport_resp_data <= 32'h0;
+        endcase
+      end
+    end
+  end
+
+endmodule // rfnoc_block_null_src_sink
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_null_src_sink/rfnoc_block_null_src_sink_tb.sv b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_null_src_sink/rfnoc_block_null_src_sink_tb.sv
new file mode 100644
index 000000000..f25e762b3
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_null_src_sink/rfnoc_block_null_src_sink_tb.sv
@@ -0,0 +1,268 @@
+//
+// Copyright 2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: rfnoc_block_null_src_sink_tb
+//
+
+`default_nettype none
+
+
+module rfnoc_block_null_src_sink_tb;
+
+  // Include macros and time declarations for use with PkgTestExec
+  `include "test_exec.svh"
+
+  import PkgTestExec::*;
+  import PkgChdrUtils::*;
+  import PkgRfnocBlockCtrlBfm::*;
+  import PkgRfnocItemUtils::*;
+
+  // Parameters
+  localparam [9:0]  THIS_PORTID = 10'h17;
+  localparam [15:0] THIS_EPID   = 16'hDEAD;
+  localparam int    CHDR_W      = 64;
+  localparam int    SPP         = 201;
+  localparam int    LPP         = ((SPP+1)/2);
+  localparam int    NUM_PKTS    = 50;
+
+  localparam int    PORT_SRCSNK = 0;
+  localparam int    PORT_LOOP   = 1;
+
+  // Clock and Reset Definition
+  bit rfnoc_chdr_clk;
+  sim_clock_gen #(2.5) rfnoc_chdr_clk_gen (rfnoc_chdr_clk); // 400 MHz
+
+  // ----------------------------------------
+  // Instantiate DUT
+  // ----------------------------------------
+
+  // Connections to DUT as interfaces:
+  RfnocBackendIf        backend (rfnoc_chdr_clk, rfnoc_chdr_clk); // Required backend iface
+  AxiStreamIf #(32)     m_ctrl  (rfnoc_chdr_clk);                 // Required control iface
+  AxiStreamIf #(32)     s_ctrl  (rfnoc_chdr_clk);                 // Required control iface
+  AxiStreamIf #(CHDR_W) m0_chdr (rfnoc_chdr_clk);                 // Optional data iface
+  AxiStreamIf #(CHDR_W) m1_chdr (rfnoc_chdr_clk);                 // Optional data iface
+  AxiStreamIf #(CHDR_W) s0_chdr (rfnoc_chdr_clk);                 // Optional data iface
+  AxiStreamIf #(CHDR_W) s1_chdr (rfnoc_chdr_clk);                 // Optional data iface
+
+  // Bus functional model for a software block controller
+  RfnocBlockCtrlBfm #(.CHDR_W(CHDR_W)) blk_ctrl;
+
+  // DUT
+  rfnoc_block_null_src_sink #(
+    .THIS_PORTID        (THIS_PORTID),
+    .CHDR_W             (CHDR_W),
+    .NIPC               (2),
+    .MTU                (10)
+  ) dut (
+    .rfnoc_chdr_clk     (backend.chdr_clk),
+    .rfnoc_ctrl_clk     (backend.ctrl_clk),
+    .rfnoc_core_config  (backend.slave.cfg),
+    .rfnoc_core_status  (backend.slave.sts),
+    .s_rfnoc_chdr_tdata ({m1_chdr.slave.tdata  , m0_chdr.slave.tdata  }),
+    .s_rfnoc_chdr_tlast ({m1_chdr.slave.tlast  , m0_chdr.slave.tlast  }),
+    .s_rfnoc_chdr_tvalid({m1_chdr.slave.tvalid , m0_chdr.slave.tvalid }),
+    .s_rfnoc_chdr_tready({m1_chdr.slave.tready , m0_chdr.slave.tready }),
+    .m_rfnoc_chdr_tdata ({s1_chdr.master.tdata , s0_chdr.master.tdata }),
+    .m_rfnoc_chdr_tlast ({s1_chdr.master.tlast , s0_chdr.master.tlast }),
+    .m_rfnoc_chdr_tvalid({s1_chdr.master.tvalid, s0_chdr.master.tvalid}),
+    .m_rfnoc_chdr_tready({s1_chdr.master.tready, s0_chdr.master.tready}),
+    .s_rfnoc_ctrl_tdata (m_ctrl.slave.tdata  ),
+    .s_rfnoc_ctrl_tlast (m_ctrl.slave.tlast  ),
+    .s_rfnoc_ctrl_tvalid(m_ctrl.slave.tvalid ),
+    .s_rfnoc_ctrl_tready(m_ctrl.slave.tready ),
+    .m_rfnoc_ctrl_tdata (s_ctrl.master.tdata ),
+    .m_rfnoc_ctrl_tlast (s_ctrl.master.tlast ),
+    .m_rfnoc_ctrl_tvalid(s_ctrl.master.tvalid),
+    .m_rfnoc_ctrl_tready(s_ctrl.master.tready)
+  );
+
+  // ----------------------------------------
+  // Test Process
+  // ----------------------------------------
+
+  initial begin
+    // Shared Variables
+    // ----------------------------------------
+    timeout_t    timeout;
+    ctrl_word_t  rvalue = 0;
+
+    // Initialize
+    // ----------------------------------------
+    test.start_tb("rfnoc_block_null_src_sink_tb");
+
+    // Start the stream endpoint BFM
+    blk_ctrl = new(backend, m_ctrl, s_ctrl);
+    blk_ctrl.add_master_data_port(m0_chdr);
+    blk_ctrl.add_slave_data_port(s0_chdr);
+    blk_ctrl.add_master_data_port(m1_chdr);
+    blk_ctrl.add_slave_data_port(s1_chdr);
+    blk_ctrl.run();
+
+    // Startup block (Software initialization)
+    // ----------------------------------------
+    test.start_test("Flush block then reset it");
+    begin
+      test.start_timeout(timeout, 10us, "Waiting for flush_and_reset");
+      #100;  //Wait for GSR to deassert
+      blk_ctrl.flush_and_reset();
+      test.end_timeout(timeout);
+    end
+    test.end_test();
+
+    // Run Tests
+    // ----------------------------------------
+    test.start_test("Read Block Info");
+    begin
+      test.start_timeout(timeout, 1us, "Waiting for block info response");
+      // Get static block info and validate it
+      `ASSERT_ERROR(blk_ctrl.get_noc_id() == 1, "Incorrect noc_id Value");
+      `ASSERT_ERROR(blk_ctrl.get_num_data_i() == 2, "Incorrect num_data_i Value");
+      `ASSERT_ERROR(blk_ctrl.get_num_data_o() == 2, "Incorrect num_data_o Value");
+      `ASSERT_ERROR(blk_ctrl.get_ctrl_fifosize() == 5, "Incorrect ctrl_fifosize Value");
+      `ASSERT_ERROR(blk_ctrl.get_mtu() == 10, "Incorrect mtu Value");
+
+      // Read status register and validate it
+      blk_ctrl.reg_read(dut.REG_CTRL_STATUS, rvalue);
+      `ASSERT_ERROR(rvalue[31:24] == 2, "Incorrect NIPC Value");
+      `ASSERT_ERROR(rvalue[23:16] == 32, "Incorrect ITEM_W Value");
+      test.end_timeout(timeout);
+    end
+    test.end_test();
+
+    test.start_test("Stream Data Through Loopback Port");
+    begin
+      // Send and receive packets
+      repeat (NUM_PKTS) begin
+        chdr_word_t rx_data[$];
+        int rx_bytes;
+        automatic ItemDataBuff #(logic[31:0]) tx_dbuff = new, rx_dbuff = new;
+        for (int i = 0; i < SPP; i++)
+          tx_dbuff.put($urandom());
+        test.start_timeout(timeout, 5us, "Waiting for pkt to loop back");
+        blk_ctrl.send(PORT_LOOP, tx_dbuff.to_chdr_payload(), tx_dbuff.get_bytes());
+        blk_ctrl.recv(PORT_LOOP, rx_data, rx_bytes);
+        rx_dbuff.from_chdr_payload(rx_data, rx_bytes);
+        `ASSERT_ERROR(rx_dbuff.equal(tx_dbuff), "Data mismatch");
+        test.end_timeout(timeout);
+      end
+
+      // Read item and packet counts on loopback port
+      blk_ctrl.reg_read(dut.REG_LOOP_LINE_CNT_LO, rvalue);
+      `ASSERT_ERROR(rvalue == (LPP*NUM_PKTS), "Incorrect REG_LOOP_LINE_CNT_LO value");
+      blk_ctrl.reg_read(dut.REG_LOOP_PKT_CNT_LO, rvalue);
+      `ASSERT_ERROR(rvalue == NUM_PKTS, "Incorrect REG_LOOP_PKT_CNT_LO value");
+
+      // Read item and packet counts on source port
+      blk_ctrl.reg_read(dut.REG_SRC_LINE_CNT_LO, rvalue);
+      `ASSERT_ERROR(rvalue == 0, "Incorrect REG_SRC_LINE_CNT_LO value");
+      blk_ctrl.reg_read(dut.REG_SRC_PKT_CNT_LO, rvalue);
+      `ASSERT_ERROR(rvalue == 0, "Incorrect REG_SRC_PKT_CNT_LO value");
+
+      // Read item and packet counts on sink port
+      blk_ctrl.reg_read(dut.REG_SNK_LINE_CNT_LO, rvalue);
+      `ASSERT_ERROR(rvalue == 0, "Incorrect REG_SNK_LINE_CNT_LO value");
+      blk_ctrl.reg_read(dut.REG_SNK_PKT_CNT_LO, rvalue);
+      `ASSERT_ERROR(rvalue == 0, "Incorrect REG_SNK_PKT_CNT_LO value");
+    end
+    test.end_test();
+
+    test.start_test("Stream Data To Sink Port");
+    begin
+      // Send packets
+      repeat (NUM_PKTS) begin
+        chdr_word_t rx_data[$];
+        int rx_bytes;
+        automatic ItemDataBuff #(logic[31:0]) tx_dbuff = new;
+        for (int i = 0; i < SPP; i++)
+          tx_dbuff.put($urandom());
+        test.start_timeout(timeout, 5us, "Waiting for pkt to loop back");
+        blk_ctrl.send(PORT_SRCSNK, tx_dbuff.to_chdr_payload(), tx_dbuff.get_bytes());
+        test.end_timeout(timeout);
+      end
+      repeat (NUM_PKTS * SPP * 2) @(posedge rfnoc_chdr_clk);
+
+      // Read item and packet counts on loopback port
+      blk_ctrl.reg_read(dut.REG_LOOP_LINE_CNT_LO, rvalue);
+      `ASSERT_ERROR(rvalue == (LPP*NUM_PKTS), "Incorrect REG_LOOP_LINE_CNT_LO value");
+      blk_ctrl.reg_read(dut.REG_LOOP_PKT_CNT_LO, rvalue);
+      `ASSERT_ERROR(rvalue == NUM_PKTS, "Incorrect REG_LOOP_PKT_CNT_LO value");
+
+      // Read item and packet counts on source port
+      blk_ctrl.reg_read(dut.REG_SRC_LINE_CNT_LO, rvalue);
+      `ASSERT_ERROR(rvalue == 0, "Incorrect REG_SRC_LINE_CNT_LO value");
+      blk_ctrl.reg_read(dut.REG_SRC_PKT_CNT_LO, rvalue);
+      `ASSERT_ERROR(rvalue == 0, "Incorrect REG_SRC_PKT_CNT_LO value");
+
+      // Read item and packet counts on sink port
+      blk_ctrl.reg_read(dut.REG_SNK_LINE_CNT_LO, rvalue);
+      `ASSERT_ERROR(rvalue == (LPP*NUM_PKTS), "Incorrect REG_SNK_LINE_CNT_LO value");
+      blk_ctrl.reg_read(dut.REG_SNK_PKT_CNT_LO, rvalue);
+      `ASSERT_ERROR(rvalue == NUM_PKTS, "Incorrect REG_SNK_PKT_CNT_LO value");
+    end
+    test.end_test();
+
+    test.start_test("Stream Data From Source Port");
+    begin
+      // Turn on the source for some time then stop it
+      blk_ctrl.reg_write(dut.REG_SRC_LINES_PER_PKT, LPP-1);
+      blk_ctrl.reg_write(dut.REG_SRC_BYTES_PER_PKT, (LPP+1)*8);
+      blk_ctrl.reg_write(dut.REG_CTRL_STATUS, 2'b10);
+      repeat ((NUM_PKTS / 10) * LPP) @(posedge rfnoc_chdr_clk);
+      blk_ctrl.reg_write(dut.REG_CTRL_STATUS, 2'b00);
+      blk_ctrl.reg_read(dut.REG_SRC_PKT_CNT_LO, rvalue);
+      repeat (rvalue * LPP * 2) @(posedge rfnoc_chdr_clk);
+      blk_ctrl.reg_read(dut.REG_SRC_PKT_CNT_LO, rvalue);
+
+      // Gather the accumulated packets and verify contents
+      for (int p = 0; p < rvalue; p++) begin
+        chdr_word_t exp_data[$];
+        chdr_word_t rx_data[$];
+        int rx_bytes;
+        test.start_timeout(timeout, 5us, "Waiting for pkt to arrive");
+        exp_data.delete();
+        for (int i = p*LPP; i < (p+1)*LPP; i++)
+          exp_data.push_back({~i[15:0], i[15:0], ~i[15:0], i[15:0]});
+        blk_ctrl.recv(PORT_SRCSNK, rx_data, rx_bytes);
+        `ASSERT_ERROR(blk_ctrl.compare_data(exp_data, rx_data), "Data mismatch");
+        test.end_timeout(timeout);
+      end
+    end
+    test.end_test();
+
+    test.start_test("Clear Counts");
+    begin
+      test.start_timeout(timeout, 1us, "Waiting for clear and readbacks");
+      // Clear
+      blk_ctrl.reg_write(dut.REG_CTRL_STATUS, 2'b01);
+
+      // Read item and packet counts on loopback port
+      blk_ctrl.reg_read(dut.REG_LOOP_LINE_CNT_LO, rvalue);
+      `ASSERT_ERROR(rvalue == 0, "Incorrect REG_LOOP_LINE_CNT_LO value");
+      blk_ctrl.reg_read(dut.REG_LOOP_PKT_CNT_LO, rvalue);
+      `ASSERT_ERROR(rvalue == 0, "Incorrect REG_LOOP_PKT_CNT_LO value");
+
+      // Read item and packet counts on source port
+      blk_ctrl.reg_read(dut.REG_SRC_LINE_CNT_LO, rvalue);
+      `ASSERT_ERROR(rvalue == 0, "Incorrect REG_SRC_LINE_CNT_LO value");
+      blk_ctrl.reg_read(dut.REG_SRC_PKT_CNT_LO, rvalue);
+      `ASSERT_ERROR(rvalue == 0, "Incorrect REG_SRC_PKT_CNT_LO value");
+
+      // Read item and packet counts on sink port
+      blk_ctrl.reg_read(dut.REG_SNK_LINE_CNT_LO, rvalue);
+      `ASSERT_ERROR(rvalue == 0, "Incorrect REG_SNK_LINE_CNT_LO value");
+      blk_ctrl.reg_read(dut.REG_SNK_PKT_CNT_LO, rvalue);
+      `ASSERT_ERROR(rvalue == 0, "Incorrect REG_SNK_PKT_CNT_LO value");
+      test.end_timeout(timeout);
+    end
+    test.end_test();
+
+    // Finish Up
+    // ----------------------------------------
+    // Display final statistics and results
+    test.end_tb();
+  end
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/Makefile b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/Makefile
new file mode 100644
index 000000000..63d6f1851
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/Makefile
@@ -0,0 +1,47 @@
+#
+# Copyright 2019 Ettus Research, A National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+#-------------------------------------------------
+# Top-of-Makefile
+#-------------------------------------------------
+# Define BASE_DIR to point to the "top" dir
+BASE_DIR = $(abspath ../../../../top)
+# Include viv_sim_preamble after defining BASE_DIR
+include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
+
+#-------------------------------------------------
+# Design Specific
+#-------------------------------------------------
+# Include makefiles and sources for the DUT and its dependencies
+include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs
+include $(BASE_DIR)/../lib/rfnoc/utils/Makefile.srcs
+include Makefile.srcs
+
+DESIGN_SRCS += $(abspath \
+$(RFNOC_CORE_SRCS) \
+$(RFNOC_UTIL_SRCS) \
+$(RFNOC_BLOCK_RADIO_SRCS) \
+)
+
+#-------------------------------------------------
+# Testbench Specific
+#-------------------------------------------------
+SIM_TOP = rfnoc_block_radio_all_tb
+
+SIM_SRCS = \
+$(abspath sim_radio_gen.sv) \
+$(abspath rfnoc_block_radio_tb.sv) \
+$(abspath rfnoc_block_radio_all_tb.sv)
+
+# MODELSIM_USER_DO = $(abspath wave.do)
+
+#-------------------------------------------------
+# Bottom-of-Makefile
+#-------------------------------------------------
+# Include all simulator specific makefiles here
+# Each should define a unique target to simulate
+# e.g. xsim, vsim, etc and a common "clean" target
+include $(BASE_DIR)/../tools/make/viv_simulator.mak
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/Makefile.srcs b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/Makefile.srcs
new file mode 100644
index 000000000..84dd01541
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/Makefile.srcs
@@ -0,0 +1,20 @@
+#
+# Copyright 2018 Ettus Research, A National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+##################################################
+# RFNoC Utility Sources
+##################################################
+RFNOC_BLOCK_RADIO_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/rfnoc/blocks/rfnoc_block_radio/, \
+rfnoc_block_radio_regs.vh \
+radio_rx_core.v \
+radio_tx_core.v \
+radio_core.v \
+noc_shell_radio.v \
+rfnoc_block_radio.v \
+rx_frontend_gen3.v \
+tx_frontend_gen3.v \
+quarter_rate_downconverter.v \
+))
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/noc_shell_radio.v b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/noc_shell_radio.v
new file mode 100644
index 000000000..32ab32b63
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/noc_shell_radio.v
@@ -0,0 +1,290 @@
+//
+// Copyright 2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: noc_shell_radio
+//
+// Description: A NoC Shell for RFNoC. This should eventually be replaced
+// by an auto-generated NoC Shell.
+//
+
+module noc_shell_radio #(
+  parameter [31:0] NOC_ID          = 32'h0,
+  parameter [ 9:0] THIS_PORTID     = 10'd0,
+  parameter        CHDR_W          = 64,
+  parameter [ 0:0] CTRLPORT_SLV_EN = 1,
+  parameter [ 0:0] CTRLPORT_MST_EN = 1,
+  parameter [ 5:0] CTRL_FIFO_SIZE  = 9,
+  parameter [ 5:0] NUM_DATA_I      = 1,
+  parameter [ 5:0] NUM_DATA_O      = 1,
+  parameter        ITEM_W          = 32,
+  parameter        NIPC            = 2,
+  parameter        PYLD_FIFO_SIZE  = 10,
+  parameter        MTU             = 10
+)(
+  //---------------------------------------------------------------------------
+  // Framework Interface
+  //---------------------------------------------------------------------------
+
+  // RFNoC Framework Clocks and Resets
+  input  wire                           rfnoc_chdr_clk,
+  output wire                           rfnoc_chdr_rst,
+  input  wire                           rfnoc_ctrl_clk,
+  output wire                           rfnoc_ctrl_rst,
+  // RFNoC Backend Interface
+  input  wire [                  511:0] rfnoc_core_config,
+  output wire [                  511:0] rfnoc_core_status,
+  // CHDR Input Ports (from framework)
+  input  wire [(CHDR_W*NUM_DATA_I)-1:0] s_rfnoc_chdr_tdata,
+  input  wire [         NUM_DATA_I-1:0] s_rfnoc_chdr_tlast,
+  input  wire [         NUM_DATA_I-1:0] s_rfnoc_chdr_tvalid,
+  output wire [         NUM_DATA_I-1:0] s_rfnoc_chdr_tready,
+  // CHDR Output Ports (to framework)
+  output wire [(CHDR_W*NUM_DATA_O)-1:0] m_rfnoc_chdr_tdata,
+  output wire [         NUM_DATA_O-1:0] m_rfnoc_chdr_tlast,
+  output wire [         NUM_DATA_O-1:0] m_rfnoc_chdr_tvalid,
+  input  wire [         NUM_DATA_O-1:0] m_rfnoc_chdr_tready,
+  // AXIS-Ctrl Input Port (from framework)
+  input  wire [                   31:0] s_rfnoc_ctrl_tdata,
+  input  wire                           s_rfnoc_ctrl_tlast,
+  input  wire                           s_rfnoc_ctrl_tvalid,
+  output wire                           s_rfnoc_ctrl_tready,
+  // AXIS-Ctrl Output Port (to framework)
+  output wire [                   31:0] m_rfnoc_ctrl_tdata,
+  output wire                           m_rfnoc_ctrl_tlast,
+  output wire                           m_rfnoc_ctrl_tvalid,
+  input  wire                           m_rfnoc_ctrl_tready,
+
+  //---------------------------------------------------------------------------
+  // Client Control Port Interface
+  //---------------------------------------------------------------------------
+
+  // Clock
+  input  wire        ctrlport_clk,
+  input  wire        ctrlport_rst,
+  // Master
+  output wire        m_ctrlport_req_wr,
+  output wire        m_ctrlport_req_rd,
+  output wire [19:0] m_ctrlport_req_addr,
+  output wire [31:0] m_ctrlport_req_data,
+  output wire [ 3:0] m_ctrlport_req_byte_en,
+  output wire        m_ctrlport_req_has_time,
+  output wire [63:0] m_ctrlport_req_time,
+  input  wire        m_ctrlport_resp_ack,
+  input  wire [ 1:0] m_ctrlport_resp_status,
+  input  wire [31:0] m_ctrlport_resp_data,
+  // Slave
+  input  wire        s_ctrlport_req_wr,
+  input  wire        s_ctrlport_req_rd,
+  input  wire [19:0] s_ctrlport_req_addr,
+  input  wire [ 9:0] s_ctrlport_req_portid,
+  input  wire [15:0] s_ctrlport_req_rem_epid,
+  input  wire [ 9:0] s_ctrlport_req_rem_portid,
+  input  wire [31:0] s_ctrlport_req_data,
+  input  wire [ 3:0] s_ctrlport_req_byte_en,
+  input  wire        s_ctrlport_req_has_time,
+  input  wire [63:0] s_ctrlport_req_time,
+  output wire        s_ctrlport_resp_ack,
+  output wire [ 1:0] s_ctrlport_resp_status,
+  output wire [31:0] s_ctrlport_resp_data,
+
+  //---------------------------------------------------------------------------
+  // Client Data Interface
+  //---------------------------------------------------------------------------
+
+  // Clock
+  input  wire                                axis_data_clk,
+  input  wire                                axis_data_rst,
+
+  // Output data stream (to user logic)
+  output wire [(NUM_DATA_I*ITEM_W*NIPC)-1:0] m_axis_tdata,
+  output wire [       (NUM_DATA_I*NIPC)-1:0] m_axis_tkeep,
+  output wire [              NUM_DATA_I-1:0] m_axis_tlast,
+  output wire [              NUM_DATA_I-1:0] m_axis_tvalid,
+  input  wire [              NUM_DATA_I-1:0] m_axis_tready,
+  // Sideband information
+  output wire [         (NUM_DATA_I*64)-1:0] m_axis_ttimestamp,
+  output wire [              NUM_DATA_I-1:0] m_axis_thas_time,
+  output wire [              NUM_DATA_I-1:0] m_axis_teov,
+  output wire [              NUM_DATA_I-1:0] m_axis_teob,
+
+  // Input data stream (from user logic)
+  input  wire [(NUM_DATA_O*ITEM_W*NIPC)-1:0] s_axis_tdata,
+  input  wire [       (NUM_DATA_O*NIPC)-1:0] s_axis_tkeep,
+  input  wire [              NUM_DATA_O-1:0] s_axis_tlast,
+  input  wire [              NUM_DATA_O-1:0] s_axis_tvalid,
+  output wire [              NUM_DATA_O-1:0] s_axis_tready,
+  // Sideband info (sampled on the first cycle of the packet)
+  input  wire [         (NUM_DATA_O*64)-1:0] s_axis_ttimestamp,
+  input  wire [              NUM_DATA_O-1:0] s_axis_thas_time,
+  input  wire [              NUM_DATA_O-1:0] s_axis_teov,
+  input  wire [              NUM_DATA_O-1:0] s_axis_teob
+);
+  
+  localparam SNK_INFO_FIFO_SIZE = 4;
+  localparam SNK_PYLD_FIFO_SIZE = PYLD_FIFO_SIZE;
+  localparam SRC_INFO_FIFO_SIZE = 4;
+  localparam SRC_PYLD_FIFO_SIZE = MTU;
+
+  //---------------------------------------------------------------------------
+  //  Backend Interface
+  //---------------------------------------------------------------------------
+
+  wire         data_i_flush_en;
+  wire [31:0]  data_i_flush_timeout;
+  wire [63:0]  data_i_flush_active;
+  wire [63:0]  data_i_flush_done;
+  wire         data_o_flush_en;
+  wire [31:0]  data_o_flush_timeout;
+  wire [63:0]  data_o_flush_active;
+  wire [63:0]  data_o_flush_done;
+
+  backend_iface #(
+    .NOC_ID        (NOC_ID),
+    .NUM_DATA_I    (NUM_DATA_I),
+    .NUM_DATA_O    (NUM_DATA_O),
+    .CTRL_FIFOSIZE (CTRL_FIFO_SIZE),
+    .MTU           (MTU)
+  ) backend_iface_i (
+    .rfnoc_chdr_clk       (rfnoc_chdr_clk),
+    .rfnoc_ctrl_clk       (rfnoc_ctrl_clk),
+    .rfnoc_core_config    (rfnoc_core_config),
+    .rfnoc_core_status    (rfnoc_core_status),
+    .rfnoc_chdr_rst       (rfnoc_chdr_rst),
+    .rfnoc_ctrl_rst       (rfnoc_ctrl_rst),
+    .data_i_flush_en      (data_i_flush_en),
+    .data_i_flush_timeout (data_i_flush_timeout),
+    .data_i_flush_active  (data_i_flush_active),
+    .data_i_flush_done    (data_i_flush_done),
+    .data_o_flush_en      (data_o_flush_en),
+    .data_o_flush_timeout (data_o_flush_timeout),
+    .data_o_flush_active  (data_o_flush_active),
+    .data_o_flush_done    (data_o_flush_done)
+  );
+
+  //---------------------------------------------------------------------------
+  //  Control Path
+  //---------------------------------------------------------------------------
+
+  ctrlport_endpoint #(
+    .THIS_PORTID              (THIS_PORTID    ),
+    .SYNC_CLKS                (0              ),
+    .AXIS_CTRL_MST_EN         (CTRLPORT_SLV_EN),
+    .AXIS_CTRL_SLV_EN         (CTRLPORT_MST_EN),
+    .SLAVE_FIFO_SIZE          (CTRL_FIFO_SIZE )
+  ) ctrlport_ep_i (
+    .rfnoc_ctrl_clk           (rfnoc_ctrl_clk           ),
+    .rfnoc_ctrl_rst           (rfnoc_ctrl_rst           ),
+    .ctrlport_clk             (ctrlport_clk             ),
+    .ctrlport_rst             (ctrlport_rst             ),
+    .s_rfnoc_ctrl_tdata       (s_rfnoc_ctrl_tdata       ),
+    .s_rfnoc_ctrl_tlast       (s_rfnoc_ctrl_tlast       ),
+    .s_rfnoc_ctrl_tvalid      (s_rfnoc_ctrl_tvalid      ),
+    .s_rfnoc_ctrl_tready      (s_rfnoc_ctrl_tready      ),
+    .m_rfnoc_ctrl_tdata       (m_rfnoc_ctrl_tdata       ),
+    .m_rfnoc_ctrl_tlast       (m_rfnoc_ctrl_tlast       ),
+    .m_rfnoc_ctrl_tvalid      (m_rfnoc_ctrl_tvalid      ),
+    .m_rfnoc_ctrl_tready      (m_rfnoc_ctrl_tready      ),
+    .m_ctrlport_req_wr        (m_ctrlport_req_wr        ),
+    .m_ctrlport_req_rd        (m_ctrlport_req_rd        ),
+    .m_ctrlport_req_addr      (m_ctrlport_req_addr      ),
+    .m_ctrlport_req_data      (m_ctrlport_req_data      ),
+    .m_ctrlport_req_byte_en   (m_ctrlport_req_byte_en   ),
+    .m_ctrlport_req_has_time  (m_ctrlport_req_has_time  ),
+    .m_ctrlport_req_time      (m_ctrlport_req_time      ),
+    .m_ctrlport_resp_ack      (m_ctrlport_resp_ack      ),
+    .m_ctrlport_resp_status   (m_ctrlport_resp_status   ),
+    .m_ctrlport_resp_data     (m_ctrlport_resp_data     ),
+    .s_ctrlport_req_wr        (s_ctrlport_req_wr        ),
+    .s_ctrlport_req_rd        (s_ctrlport_req_rd        ),
+    .s_ctrlport_req_addr      (s_ctrlport_req_addr      ),
+    .s_ctrlport_req_portid    (s_ctrlport_req_portid    ),
+    .s_ctrlport_req_rem_epid  (s_ctrlport_req_rem_epid  ),
+    .s_ctrlport_req_rem_portid(s_ctrlport_req_rem_portid),
+    .s_ctrlport_req_data      (s_ctrlport_req_data      ),
+    .s_ctrlport_req_byte_en   (s_ctrlport_req_byte_en   ),
+    .s_ctrlport_req_has_time  (s_ctrlport_req_has_time  ),
+    .s_ctrlport_req_time      (s_ctrlport_req_time      ),
+    .s_ctrlport_resp_ack      (s_ctrlport_resp_ack      ),
+    .s_ctrlport_resp_status   (s_ctrlport_resp_status   ),
+    .s_ctrlport_resp_data     (s_ctrlport_resp_data     )
+  );
+
+  //---------------------------------------------------------------------------
+  //  Data Path
+  //---------------------------------------------------------------------------
+
+  genvar i;
+  generate
+
+    for (i = 0; i < NUM_DATA_I; i = i + 1) begin: chdr_to_data
+      chdr_to_axis_data #(
+        .CHDR_W         (CHDR_W),
+        .ITEM_W         (ITEM_W),
+        .NIPC           (NIPC),
+        .SYNC_CLKS      (0),
+        .INFO_FIFO_SIZE (SNK_INFO_FIFO_SIZE),
+        .PYLD_FIFO_SIZE (SNK_PYLD_FIFO_SIZE)
+      ) chdr_to_axis_data_i (
+        .axis_chdr_clk      (rfnoc_chdr_clk),
+        .axis_chdr_rst      (rfnoc_chdr_rst),
+        .axis_data_clk      (axis_data_clk),
+        .axis_data_rst      (axis_data_rst),
+        .s_axis_chdr_tdata  (s_rfnoc_chdr_tdata  [(i*CHDR_W)+:CHDR_W]),
+        .s_axis_chdr_tlast  (s_rfnoc_chdr_tlast  [i]),
+        .s_axis_chdr_tvalid (s_rfnoc_chdr_tvalid [i]),
+        .s_axis_chdr_tready (s_rfnoc_chdr_tready [i]),
+        .m_axis_tdata       (m_axis_tdata  [i*ITEM_W*NIPC +: ITEM_W*NIPC]),
+        .m_axis_tkeep       (m_axis_tkeep  [i*NIPC +: NIPC]),
+        .m_axis_tlast       (m_axis_tlast  [i]),
+        .m_axis_tvalid      (m_axis_tvalid [i]),
+        .m_axis_tready      (m_axis_tready [i]),
+        .m_axis_ttimestamp  (m_axis_ttimestamp [i*64 +: 64]),
+        .m_axis_thas_time   (m_axis_thas_time  [i]),
+        .m_axis_tlength     (),
+        .m_axis_teov        (m_axis_teov       [i]),
+        .m_axis_teob        (m_axis_teob       [i]),
+        .flush_en           (data_i_flush_en),
+        .flush_timeout      (data_i_flush_timeout),
+        .flush_active       (data_i_flush_active [i]),
+        .flush_done         (data_i_flush_done   [i])
+      );
+    end
+
+    for (i = 0; i < NUM_DATA_O; i = i + 1) begin: data_to_chdr
+      axis_data_to_chdr #(
+        .CHDR_W         (CHDR_W),
+        .ITEM_W         (ITEM_W),
+        .NIPC           (NIPC),
+        .SYNC_CLKS      (0),
+        .INFO_FIFO_SIZE (4),
+        .PYLD_FIFO_SIZE (SRC_INFO_FIFO_SIZE),
+        .MTU            (SRC_PYLD_FIFO_SIZE)
+      ) axis_data_to_chdr_i (
+        .axis_chdr_clk       (rfnoc_chdr_clk),
+        .axis_chdr_rst       (rfnoc_chdr_rst),
+        .axis_data_clk       (axis_data_clk),
+        .axis_data_rst       (axis_data_rst),
+        .m_axis_chdr_tdata   (m_rfnoc_chdr_tdata  [i*CHDR_W +: CHDR_W]),
+        .m_axis_chdr_tlast   (m_rfnoc_chdr_tlast  [i]),
+        .m_axis_chdr_tvalid  (m_rfnoc_chdr_tvalid [i]),
+        .m_axis_chdr_tready  (m_rfnoc_chdr_tready [i]),
+        .s_axis_tdata        (s_axis_tdata  [i*ITEM_W*NIPC +: ITEM_W*NIPC]),
+        .s_axis_tkeep        (s_axis_tkeep  [i*NIPC +: NIPC]),
+        .s_axis_tlast        (s_axis_tlast  [i]),
+        .s_axis_tvalid       (s_axis_tvalid [i]),
+        .s_axis_tready       (s_axis_tready [i]),
+        .s_axis_ttimestamp   (s_axis_ttimestamp [i*64 +: 64]),
+        .s_axis_thas_time    (s_axis_thas_time  [i]),
+        .s_axis_teov         (s_axis_teov       [i]),
+        .s_axis_teob         (s_axis_teob       [i]),
+        .flush_en            (data_o_flush_en),
+        .flush_timeout       (data_o_flush_timeout),
+        .flush_active        (data_o_flush_active [i]),
+        .flush_done          (data_o_flush_done   [i])
+      );
+    end
+  endgenerate
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/quarter_rate_downconverter.v b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/quarter_rate_downconverter.v
new file mode 100644
index 000000000..ded9a8c0b
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/quarter_rate_downconverter.v
@@ -0,0 +1,138 @@
+//
+// Copyright 2018 Ettus Research, a National Instruments Brand
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+// mixer with 90 degree angles, i.e., multiplying the input signal with 1, i, -1, -i:
+
+// Let S(t) = I(t) + i*Q(t) be the input signal based on inputs i_in and q_in
+// Multiplying with (1,i,-1,-i) then becomes:
+// S(t) * 1  =  I(t) + i*Q(t)
+// S(t) * i  = -Q(t) + i*I(t)
+// S(t) * -1 = -I(t) - i*Q(t)
+// S(t) * -i =  Q(t) - i*I(t)
+
+// To control the direction of rotation, the dirctn input is used
+// When set to 0, the phase is increased with pi/2 every sample, i.e., rotating counter clock wise
+// When set to 1, the phase is increased with -pi/2 every sample, i.e., rotating clock wise
+
+// the input is the concatenation of the i and q signal: {i_in, q_in}
+
+module quarter_rate_downconverter #(
+  parameter WIDTH=24
+)(
+  input clk,
+  input reset,
+  input phase_sync,
+
+  input [2*WIDTH-1:0] i_tdata,
+  input i_tlast,
+  input i_tvalid,
+  output i_tready,
+
+  output [2*WIDTH-1:0] o_tdata,
+  output o_tlast,
+  output o_tvalid,
+  input o_tready,
+
+  input dirctn
+);
+
+  // temporary signals for i and q after rotation
+  reg [WIDTH-1:0] tmp_i = {WIDTH{1'b0}};
+  reg [WIDTH-1:0] tmp_q = {WIDTH{1'b0}};
+
+  // State machine types and reg
+  localparam S0=0, S1=1, S2=2, S3=3;
+  reg[1:0] cur_state;
+
+  // split input into i and q signal
+  wire[WIDTH-1:0] i_in, q_in;
+  assign i_in = i_tdata[2*WIDTH-1:WIDTH];
+  assign q_in = i_tdata[WIDTH-1:0];
+
+  // The state machine doing the rotations among states
+  always @(posedge clk) begin
+    if(reset || phase_sync) begin
+       cur_state <= S0;
+    end else begin
+      case (cur_state)
+        S0: begin
+            if(i_tvalid == 1'b1 && i_tready == 1'b1)
+              if(dirctn == 1'b0)
+                cur_state <= S1;
+              else
+                cur_state <= S3;
+            else
+              cur_state <= S0;
+          end
+        S1: begin
+            if(i_tvalid == 1'b1 && i_tready == 1'b1)
+              if(dirctn == 1'b0)
+                cur_state <= S2;
+              else
+                cur_state <= S0;
+            else
+              cur_state <= S1;
+          end
+        S2: begin
+            if(i_tvalid == 1'b1 && i_tready == 1'b1)
+              if(dirctn == 1'b0)
+                cur_state <= S3;
+              else
+                cur_state <= S1;
+            else
+              cur_state <= S2;
+          end
+        S3: begin
+            if(i_tvalid == 1'b1 && i_tready == 1'b1)
+              if(dirctn == 1'b0)
+                cur_state <= S0;
+              else
+                cur_state <= S2;
+            else
+              cur_state <= S3;
+          end
+      endcase
+    end
+  end
+
+  // Multiplication of input IQ signal with (1,i,-1,-i):
+  always @(*) begin
+    case (cur_state)
+      S0: begin
+          // S(t) * 1 = I(t) + iQ(t):
+          tmp_i = i_in;
+          tmp_q = q_in;
+        end
+      S1: begin
+          // S(t) * i = -Q(t) + iI(t):
+          tmp_i = -q_in;
+          tmp_q = i_in;
+        end
+      S2: begin
+          // S(t) * -1 = -I(t) - iQ(t):
+          tmp_i = -i_in;
+          tmp_q = -q_in;
+        end
+      S3: begin
+          // S(t) * -i = Q(t) - iI(t):
+          tmp_i = q_in;
+          tmp_q = -i_in;
+        end
+      default: begin
+          tmp_i = i_in;
+          tmp_q = q_in;
+        end
+    endcase
+  end
+
+  // Flop for valid and ready signals and shortening of comb. paths.
+  axi_fifo #(.WIDTH(2*WIDTH + 1), .SIZE(1)) flop (
+    .clk(clk), .reset(reset), .clear(1'b0),
+    .i_tdata({i_tlast, tmp_i, tmp_q}), .i_tvalid(i_tvalid), .i_tready(i_tready),
+    .o_tdata({o_tlast, o_tdata}), .o_tvalid(o_tvalid), .o_tready(o_tready),
+    .occupied(), .space());
+
+endmodule // quarter_rate_downconverter
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/radio_core.v b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/radio_core.v
new file mode 100644
index 000000000..9456fc398
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/radio_core.v
@@ -0,0 +1,370 @@
+//
+// Copyright 2019 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: radio_core
+//
+// Description:
+//
+// A radio core for RFNoC. This core contains all logic in the radio clock 
+// domain for interfacing to a single RX/TX radio. It includes registers shared 
+// by both Rx and Tx logic and instantiates Rx and Tx interface cores.
+//
+// Parameters:
+//
+//   BASE_ADDR : Base address for this radio block instance
+//   SAMP_W    : Width of a radio sample
+//   NSPC      : Number of radio samples per radio clock cycle
+//
+
+
+module radio_core #(
+  parameter SAMP_W    = 32,
+  parameter NSPC      = 1
+) (
+  input wire radio_clk,
+  input wire radio_rst,
+
+
+  //---------------------------------------------------------------------------
+  // Control Interface
+  //---------------------------------------------------------------------------
+
+  // Slave
+  input  wire        s_ctrlport_req_wr,
+  input  wire        s_ctrlport_req_rd,
+  input  wire [19:0] s_ctrlport_req_addr,
+  input  wire [31:0] s_ctrlport_req_data,
+  output wire        s_ctrlport_resp_ack,
+  output wire [31:0] s_ctrlport_resp_data,
+
+  // Master
+  output wire        m_ctrlport_req_wr,
+  output wire [19:0] m_ctrlport_req_addr,
+  output wire [ 9:0] m_ctrlport_req_portid,
+  output wire [15:0] m_ctrlport_req_rem_epid,
+  output wire [ 9:0] m_ctrlport_req_rem_portid,
+  output wire [31:0] m_ctrlport_req_data,
+  output wire        m_ctrlport_req_has_time,
+  output wire [63:0] m_ctrlport_req_time,
+  input  wire        m_ctrlport_resp_ack,
+
+
+  //---------------------------------------------------------------------------
+  // Data Interface
+  //---------------------------------------------------------------------------
+
+  // Tx Radio Data Stream
+  input  wire [(SAMP_W*NSPC)-1:0] s_axis_tdata,
+  input  wire                     s_axis_tlast,
+  input  wire                     s_axis_tvalid,
+  output wire                     s_axis_tready,
+  // Sideband info
+  input  wire [             63:0] s_axis_ttimestamp,
+  input  wire                     s_axis_thas_time,
+  input  wire                     s_axis_teob,
+
+  // Rx Radio Data Stream
+  output wire [(SAMP_W*NSPC)-1:0] m_axis_tdata,
+  output wire                     m_axis_tlast,
+  output wire                     m_axis_tvalid,
+  input  wire                     m_axis_tready,
+  // Sideband info
+  output wire [             63:0] m_axis_ttimestamp,
+  output wire                     m_axis_thas_time,
+  output wire                     m_axis_teob,
+
+
+  //---------------------------------------------------------------------------
+  // Radio Interface
+  //---------------------------------------------------------------------------
+
+  input wire [63:0] radio_time,
+
+  // Radio Rx Interface
+  input  wire [SAMP_W*NSPC-1:0] radio_rx_data,
+  input  wire                   radio_rx_stb,
+  output wire                   radio_rx_running,
+
+  // Radio Tx Interface
+  output wire [SAMP_W*NSPC-1:0] radio_tx_data,
+  input  wire                   radio_tx_stb,
+  output wire                   radio_tx_running
+);
+
+  `include "rfnoc_block_radio_regs.vh"
+
+
+  //---------------------------------------------------------------------------
+  // Split Control Port Interface
+  //---------------------------------------------------------------------------
+  //
+  // This block splits the single slave interface of the radio core into 
+  // multiple interfaces, one for each subcomponent. The responses from each 
+  // subcomponent are merged into a single response and sent back out the slave 
+  // interface.
+  //
+  //---------------------------------------------------------------------------
+
+  // Registers shared by Rx and Tx
+  wire        ctrlport_general_req_wr;
+  wire        ctrlport_general_req_rd;
+  wire [19:0] ctrlport_general_req_addr;
+  wire [31:0] ctrlport_general_req_data;
+  reg         ctrlport_general_resp_ack  = 1'b0;
+  reg  [31:0] ctrlport_general_resp_data = 0;
+
+  // Tx core registers
+  wire        ctrlport_tx_req_wr;
+  wire        ctrlport_tx_req_rd;
+  wire [19:0] ctrlport_tx_req_addr;
+  wire [31:0] ctrlport_tx_req_data;
+  wire        ctrlport_tx_resp_ack;
+  wire [31:0] ctrlport_tx_resp_data;
+
+  // Rx core registers
+  wire        ctrlport_rx_req_wr;
+  wire        ctrlport_rx_req_rd;
+  wire [19:0] ctrlport_rx_req_addr;
+  wire [31:0] ctrlport_rx_req_data;
+  wire        ctrlport_rx_resp_ack;
+  wire [31:0] ctrlport_rx_resp_data;
+
+  ctrlport_splitter #(
+    .NUM_SLAVES (3)
+  ) ctrlport_decoder_i (
+    .ctrlport_clk            (radio_clk),
+    .ctrlport_rst            (radio_rst),
+    .s_ctrlport_req_wr       (s_ctrlport_req_wr),
+    .s_ctrlport_req_rd       (s_ctrlport_req_rd),
+    .s_ctrlport_req_addr     (s_ctrlport_req_addr),
+    .s_ctrlport_req_data     (s_ctrlport_req_data),
+    .s_ctrlport_req_byte_en  (4'b0),
+    .s_ctrlport_req_has_time (1'b0),
+    .s_ctrlport_req_time     (64'b0),
+    .s_ctrlport_resp_ack     (s_ctrlport_resp_ack),
+    .s_ctrlport_resp_status  (),
+    .s_ctrlport_resp_data    (s_ctrlport_resp_data),
+    .m_ctrlport_req_wr       ({ctrlport_general_req_wr,
+                               ctrlport_tx_req_wr,
+                               ctrlport_rx_req_wr}),
+    .m_ctrlport_req_rd       ({ctrlport_general_req_rd,
+                               ctrlport_tx_req_rd,
+                               ctrlport_rx_req_rd}),
+    .m_ctrlport_req_addr     ({ctrlport_general_req_addr,
+                               ctrlport_tx_req_addr,
+                               ctrlport_rx_req_addr}),
+    .m_ctrlport_req_data     ({ctrlport_general_req_data,
+                               ctrlport_tx_req_data,
+                               ctrlport_rx_req_data}),
+    .m_ctrlport_req_byte_en  (),
+    .m_ctrlport_req_has_time (),
+    .m_ctrlport_req_time     (),
+    .m_ctrlport_resp_ack     ({ctrlport_general_resp_ack,
+                               ctrlport_tx_resp_ack,
+                               ctrlport_rx_resp_ack}),
+    .m_ctrlport_resp_status  (6'b0),
+    .m_ctrlport_resp_data    ({ctrlport_general_resp_data,
+                               ctrlport_tx_resp_data,
+                               ctrlport_rx_resp_data})
+  );
+
+
+  //---------------------------------------------------------------------------
+  // Merge Control Port Interfaces
+  //---------------------------------------------------------------------------
+  //
+  // This block merges the master control port interfaces of the Rx and Tx 
+  // cores into a single master control port interface. Both the Rx and Tx 
+  // cores support error reporting by writing to a control port interface. This 
+  // block arbitrates the requests between the Rx and Tx cores. Rx and Tx only 
+  // support writes for error reporting, not reads. Time and byte enables are 
+  // also not needed. Hence, several ports are unconnected.
+  //
+  //---------------------------------------------------------------------------
+
+  // Tx and Rx error reporting signals
+  wire        ctrlport_err_tx_req_wr,         ctrlport_err_rx_req_wr;
+  wire [19:0] ctrlport_err_tx_req_addr,       ctrlport_err_rx_req_addr;
+  wire [31:0] ctrlport_err_tx_req_data,       ctrlport_err_rx_req_data;
+  wire        ctrlport_err_tx_req_has_time,   ctrlport_err_rx_req_has_time;
+  wire [63:0] ctrlport_err_tx_req_time,       ctrlport_err_rx_req_time;
+  wire [ 9:0] ctrlport_err_tx_req_portid,     ctrlport_err_rx_req_portid;
+  wire [15:0] ctrlport_err_tx_req_rem_epid,   ctrlport_err_rx_req_rem_epid;
+  wire [ 9:0] ctrlport_err_tx_req_rem_portid, ctrlport_err_rx_req_rem_portid;
+  wire        ctrlport_err_tx_resp_ack,       ctrlport_err_rx_resp_ack;
+
+
+  ctrlport_combiner #(
+    .NUM_MASTERS (2),
+    .PRIORITY    (0)
+  ) ctrlport_req_combine_i (
+    .ctrlport_clk              (radio_clk),
+    .ctrlport_rst              (radio_rst),
+    .s_ctrlport_req_wr         ({ctrlport_err_tx_req_wr,         ctrlport_err_rx_req_wr}),
+    .s_ctrlport_req_rd         (2'b0),
+    .s_ctrlport_req_addr       ({ctrlport_err_tx_req_addr,       ctrlport_err_rx_req_addr}),
+    .s_ctrlport_req_portid     ({ctrlport_err_tx_req_portid,     ctrlport_err_rx_req_portid}),
+    .s_ctrlport_req_rem_epid   ({ctrlport_err_tx_req_rem_epid,   ctrlport_err_rx_req_rem_epid}),
+    .s_ctrlport_req_rem_portid ({ctrlport_err_tx_req_rem_portid, ctrlport_err_rx_req_rem_portid}),
+    .s_ctrlport_req_data       ({ctrlport_err_tx_req_data,       ctrlport_err_rx_req_data}),
+    .s_ctrlport_req_byte_en    (8'hFF),
+    .s_ctrlport_req_has_time   ({ctrlport_err_tx_req_has_time,   ctrlport_err_rx_req_has_time}),
+    .s_ctrlport_req_time       ({ctrlport_err_tx_req_time,       ctrlport_err_rx_req_time}),
+    .s_ctrlport_resp_ack       ({ctrlport_err_tx_resp_ack,       ctrlport_err_rx_resp_ack}),
+    .s_ctrlport_resp_status    (),
+    .s_ctrlport_resp_data      (),
+    .m_ctrlport_req_wr         (m_ctrlport_req_wr),
+    .m_ctrlport_req_rd         (),
+    .m_ctrlport_req_addr       (m_ctrlport_req_addr),
+    .m_ctrlport_req_portid     (m_ctrlport_req_portid),
+    .m_ctrlport_req_rem_epid   (m_ctrlport_req_rem_epid),
+    .m_ctrlport_req_rem_portid (m_ctrlport_req_rem_portid),
+    .m_ctrlport_req_data       (m_ctrlport_req_data),
+    .m_ctrlport_req_byte_en    (),
+    .m_ctrlport_req_has_time   (m_ctrlport_req_has_time),
+    .m_ctrlport_req_time       (m_ctrlport_req_time),
+    .m_ctrlport_resp_ack       (m_ctrlport_resp_ack),
+    .m_ctrlport_resp_status    (2'b0),
+    .m_ctrlport_resp_data      (0)
+  );
+
+
+  //---------------------------------------------------------------------------
+  // General Registers
+  //---------------------------------------------------------------------------
+  //
+  // These are registers that apply to both Rx and Tx and are shared by both.
+  //
+  //---------------------------------------------------------------------------
+
+  reg reg_loopback_en = 1'b0;
+
+  always @(posedge radio_clk) begin
+    if (radio_rst) begin
+      ctrlport_general_resp_ack  <= 0;
+      ctrlport_general_resp_data <= 0;
+      reg_loopback_en            <= 0;
+    end else begin
+      // Default assignments
+      ctrlport_general_resp_ack  <= 0;
+      ctrlport_general_resp_data <= 0;
+
+      // Handle register writes
+      if (ctrlport_general_req_wr) begin
+        case (ctrlport_general_req_addr)
+          REG_LOOPBACK_EN: begin
+            reg_loopback_en           <= ctrlport_general_req_data[0];
+            ctrlport_general_resp_ack <= 1;
+          end
+        endcase
+      end
+
+      // Handle register reads
+      if (ctrlport_general_req_rd) begin
+        case (ctrlport_general_req_addr)
+          REG_LOOPBACK_EN: begin
+            ctrlport_general_resp_data    <= 0;
+            ctrlport_general_resp_data[0] <= reg_loopback_en;
+            ctrlport_general_resp_ack     <= 1;
+          end
+          REG_RADIO_WIDTH: begin
+            ctrlport_general_resp_data <= { SAMP_W[15:0], NSPC[15:0] };
+            ctrlport_general_resp_ack  <= 1;
+          end
+        endcase
+      end
+    end
+  end
+
+
+  //---------------------------------------------------------------------------
+  // Tx to Rx Loopback
+  //---------------------------------------------------------------------------
+
+  wire [SAMP_W*NSPC-1:0] radio_rx_data_mux;
+  wire                   radio_rx_stb_mux;
+
+  assign radio_rx_data_mux = reg_loopback_en ? radio_tx_data : radio_rx_data;
+  assign radio_rx_stb_mux  = reg_loopback_en ? radio_tx_stb  : radio_rx_stb;
+
+
+  //---------------------------------------------------------------------------
+  // Tx Core
+  //---------------------------------------------------------------------------
+
+  radio_tx_core #(
+    .SAMP_W    (SAMP_W),
+    .NSPC      (NSPC)
+  ) radio_tx_core_i (
+    .radio_clk                 (radio_clk),
+    .radio_rst                 (radio_rst),
+    .s_ctrlport_req_wr         (ctrlport_tx_req_wr),
+    .s_ctrlport_req_rd         (ctrlport_tx_req_rd),
+    .s_ctrlport_req_addr       (ctrlport_tx_req_addr),
+    .s_ctrlport_req_data       (ctrlport_tx_req_data),
+    .s_ctrlport_resp_ack       (ctrlport_tx_resp_ack),
+    .s_ctrlport_resp_data      (ctrlport_tx_resp_data),
+    .m_ctrlport_req_wr         (ctrlport_err_tx_req_wr),
+    .m_ctrlport_req_addr       (ctrlport_err_tx_req_addr),
+    .m_ctrlport_req_data       (ctrlport_err_tx_req_data),
+    .m_ctrlport_req_has_time   (ctrlport_err_tx_req_has_time),
+    .m_ctrlport_req_time       (ctrlport_err_tx_req_time),
+    .m_ctrlport_req_portid     (ctrlport_err_tx_req_portid),
+    .m_ctrlport_req_rem_epid   (ctrlport_err_tx_req_rem_epid),
+    .m_ctrlport_req_rem_portid (ctrlport_err_tx_req_rem_portid),
+    .m_ctrlport_resp_ack       (ctrlport_err_tx_resp_ack),
+    .radio_time                (radio_time),
+    .radio_tx_data             (radio_tx_data),
+    .radio_tx_stb              (radio_tx_stb),
+    .radio_tx_running          (radio_tx_running),
+    .s_axis_tdata              (s_axis_tdata),
+    .s_axis_tlast              (s_axis_tlast),
+    .s_axis_tvalid             (s_axis_tvalid),
+    .s_axis_tready             (s_axis_tready),
+    .s_axis_ttimestamp         (s_axis_ttimestamp),
+    .s_axis_thas_time          (s_axis_thas_time),
+    .s_axis_teob               (s_axis_teob)
+  );
+
+
+  //---------------------------------------------------------------------------
+  // Rx Core
+  //---------------------------------------------------------------------------
+
+  radio_rx_core #(
+    .SAMP_W    (SAMP_W),
+    .NSPC      (NSPC)
+  ) radio_rx_core_i (
+    .radio_clk                 (radio_clk),
+    .radio_rst                 (radio_rst),
+    .s_ctrlport_req_wr         (ctrlport_rx_req_wr),
+    .s_ctrlport_req_rd         (ctrlport_rx_req_rd),
+    .s_ctrlport_req_addr       (ctrlport_rx_req_addr),
+    .s_ctrlport_req_data       (ctrlport_rx_req_data),
+    .s_ctrlport_resp_ack       (ctrlport_rx_resp_ack),
+    .s_ctrlport_resp_data      (ctrlport_rx_resp_data),
+    .m_ctrlport_req_wr         (ctrlport_err_rx_req_wr),
+    .m_ctrlport_req_addr       (ctrlport_err_rx_req_addr),
+    .m_ctrlport_req_data       (ctrlport_err_rx_req_data),
+    .m_ctrlport_req_has_time   (ctrlport_err_rx_req_has_time),
+    .m_ctrlport_req_time       (ctrlport_err_rx_req_time),
+    .m_ctrlport_req_portid     (ctrlport_err_rx_req_portid),
+    .m_ctrlport_req_rem_epid   (ctrlport_err_rx_req_rem_epid),
+    .m_ctrlport_req_rem_portid (ctrlport_err_rx_req_rem_portid),
+    .m_ctrlport_resp_ack       (ctrlport_err_rx_resp_ack),
+    .radio_time                (radio_time),
+    .radio_rx_data             (radio_rx_data_mux),
+    .radio_rx_stb              (radio_rx_stb_mux),
+    .radio_rx_running          (radio_rx_running),
+    .m_axis_tdata              (m_axis_tdata),
+    .m_axis_tlast              (m_axis_tlast),
+    .m_axis_tvalid             (m_axis_tvalid),
+    .m_axis_tready             (m_axis_tready),
+    .m_axis_ttimestamp         (m_axis_ttimestamp),
+    .m_axis_thas_time          (m_axis_thas_time),
+    .m_axis_teob               (m_axis_teob)
+  );
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/radio_rx_core.v b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/radio_rx_core.v
new file mode 100644
index 000000000..ee7774fd7
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/radio_rx_core.v
@@ -0,0 +1,521 @@
+//
+// Copyright 2019 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: radio_rx_core
+//
+// Description:
+//
+// This module contains the core Rx radio acquisition logic. It retrieves 
+// sample data from the radio interface, as indicated by the radio's strobe 
+// signal, and outputs the data via AXI-Stream.
+//
+// The receiver is operated by writing a time (optionally) to the 
+// REG_RX_CMD_TIME_* registers and a number of words (optionally) to 
+// REG_RX_CMD_NUM_WORDS_* registers followed by writing a command word to 
+// REG_RX_CMD. The command word indicates whether it is a finite ("num samps 
+// and done") or continuous acquisition and whether or not the acquisition 
+// should start at the time indicated byREG_RX_CMD_TIME_*. A stop command will 
+// stop any acquisition that's waiting to start or is in progress.
+//
+// The REG_RX_MAX_WORDS_PER_PKT and REG_RX_ERR_* registers should be 
+// initialized prior to the first acquisition.
+//
+// Parameters:
+//
+//   SAMP_W    : Width of a radio sample
+//   NSPC      : Number of radio samples per radio clock cycle
+//
+`default_nettype none
+
+
+module radio_rx_core #(
+  parameter SAMP_W    = 32,
+  parameter NSPC      = 1
+) (
+  input wire radio_clk,
+  input wire radio_rst,
+
+
+  //---------------------------------------------------------------------------
+  // Control Interface
+  //---------------------------------------------------------------------------
+
+  // Slave (Register Reads and Writes)
+  input  wire        s_ctrlport_req_wr,
+  input  wire        s_ctrlport_req_rd,
+  input  wire [19:0] s_ctrlport_req_addr,
+  input  wire [31:0] s_ctrlport_req_data,
+  output reg         s_ctrlport_resp_ack  = 1'b0,
+  output reg  [31:0] s_ctrlport_resp_data,
+
+  // Master (Error Reporting)
+  output reg         m_ctrlport_req_wr = 1'b0,
+  output reg  [19:0] m_ctrlport_req_addr,
+  output reg  [31:0] m_ctrlport_req_data,
+  output wire        m_ctrlport_req_has_time,
+  output reg  [63:0] m_ctrlport_req_time,
+  output wire [ 9:0] m_ctrlport_req_portid,
+  output wire [15:0] m_ctrlport_req_rem_epid,
+  output wire [ 9:0] m_ctrlport_req_rem_portid,
+  input  wire        m_ctrlport_resp_ack,
+
+
+  //---------------------------------------------------------------------------
+  // Radio Interface
+  //---------------------------------------------------------------------------
+
+  input wire [63:0] radio_time,
+
+  input  wire [SAMP_W*NSPC-1:0] radio_rx_data,
+  input  wire                   radio_rx_stb,
+
+  // Status indicator (true when receiving)
+  output wire radio_rx_running,
+
+
+  //---------------------------------------------------------------------------
+  // AXI-Stream Data Output
+  //---------------------------------------------------------------------------
+
+  output wire [SAMP_W*NSPC-1:0] m_axis_tdata,
+  output wire                   m_axis_tlast,
+  output wire                   m_axis_tvalid,
+  input  wire                   m_axis_tready,
+  // Sideband info
+  output wire [           63:0] m_axis_ttimestamp,
+  output wire                   m_axis_thas_time,
+  output wire                   m_axis_teob
+);
+
+  `include "rfnoc_block_radio_regs.vh"
+  `include "../../core/rfnoc_chdr_utils.vh"
+
+  localparam NUM_WORDS_LEN = RX_CMD_NUM_WORDS_LEN;
+
+
+  //---------------------------------------------------------------------------
+  // Register Read/Write Logic
+  //---------------------------------------------------------------------------
+
+  reg                      reg_cmd_valid        = 0;  // Indicates when the CMD_FIFO has been written
+  reg  [   RX_CMD_LEN-1:0] reg_cmd_word         = 0;  // Command to execute
+  reg  [NUM_WORDS_LEN-1:0] reg_cmd_num_words    = 0;  // Number of words for the command
+  reg  [             63:0] reg_cmd_time         = 0;  // Time for the command
+  reg                      reg_cmd_timed        = 0;  // Indicates if this is a timed command
+  reg  [             31:0] reg_max_pkt_len      = 64; // Maximum words per packet
+  reg  [              9:0] reg_error_portid     = 0;  // Port ID to use for error reporting
+  reg  [             15:0] reg_error_rem_epid   = 0;  // Remote EPID to use for error reporting
+  reg  [              9:0] reg_error_rem_portid = 0;  // Remote port ID to use for error reporting
+  reg  [             19:0] reg_error_addr       = 0;  // Address to use for error reporting
+  reg                      reg_has_time         = 1;  // Whether or not to use timestamps on data
+
+  wire [15:0] cmd_fifo_space;   // Empty space in the command FIFO
+  reg         cmd_stop     = 0; // Indicates a full stop request
+  wire        cmd_stop_ack;     // Acknowledgment that a stop has completed
+  reg         clear_fifo   = 0; // Signal to clear the command FIFO
+
+  assign m_axis_thas_time = reg_has_time;
+
+  always @(posedge radio_clk) begin
+    if (radio_rst) begin
+      s_ctrlport_resp_ack  <= 0;
+      reg_cmd_valid        <= 0;
+      reg_cmd_word         <= 0;
+      reg_cmd_num_words    <= 0;
+      reg_cmd_time         <= 0;
+      reg_cmd_timed        <= 0;
+      reg_max_pkt_len      <= 64;
+      reg_error_portid     <= 0;
+      reg_error_rem_epid   <= 0;
+      reg_error_rem_portid <= 0;
+      reg_error_addr       <= 0;
+      reg_has_time         <= 1;
+      clear_fifo           <= 0;
+      cmd_stop             <= 0;
+    end else begin
+      // Default assignments
+      s_ctrlport_resp_ack  <= 0;
+      s_ctrlport_resp_data <= 0;
+      reg_cmd_valid        <= 0;
+      clear_fifo           <= 0;
+
+      // Clear stop register when we enter the STOP state
+      if (cmd_stop_ack) cmd_stop <= 1'b0;
+
+      // Handle register writes
+      if (s_ctrlport_req_wr) begin
+        case (s_ctrlport_req_addr)
+          REG_RX_CMD: begin
+            // All commands go into the command FIFO except STOP
+            reg_cmd_valid       <= (s_ctrlport_req_data[RX_CMD_LEN-1:0] != RX_CMD_STOP);
+            reg_cmd_word        <=  s_ctrlport_req_data[RX_CMD_LEN-1:0];
+            reg_cmd_timed       <=  s_ctrlport_req_data[RX_CMD_TIMED_POS];
+            s_ctrlport_resp_ack <= 1;
+
+            // cmd_stop must remain asserted until it has completed
+            if (!cmd_stop || cmd_stop_ack) begin
+              cmd_stop <= (s_ctrlport_req_data[RX_CMD_LEN-1:0] == RX_CMD_STOP);
+            end
+            clear_fifo <= (s_ctrlport_req_data[RX_CMD_LEN-1:0] == RX_CMD_STOP);
+          end
+          REG_RX_CMD_NUM_WORDS_LO: begin
+            reg_cmd_num_words[31:0] <= s_ctrlport_req_data;
+            s_ctrlport_resp_ack     <= 1;
+          end
+          REG_RX_CMD_NUM_WORDS_HI: begin
+            reg_cmd_num_words[NUM_WORDS_LEN-1:32] <= s_ctrlport_req_data[NUM_WORDS_LEN-32-1:0];
+            s_ctrlport_resp_ack                   <= 1;
+          end
+          REG_RX_CMD_TIME_LO: begin
+            reg_cmd_time[31:0]  <= s_ctrlport_req_data;
+            s_ctrlport_resp_ack <= 1;
+          end
+          REG_RX_CMD_TIME_HI: begin
+            reg_cmd_time[63:32] <= s_ctrlport_req_data;
+            s_ctrlport_resp_ack <= 1;
+          end
+          REG_RX_MAX_WORDS_PER_PKT: begin
+            reg_max_pkt_len     <= s_ctrlport_req_data;
+            s_ctrlport_resp_ack <= 1;
+          end
+          REG_RX_ERR_PORT: begin
+            reg_error_portid    <= s_ctrlport_req_data[9:0];
+            s_ctrlport_resp_ack <= 1;
+          end
+          REG_RX_ERR_REM_PORT: begin
+            reg_error_rem_portid <= s_ctrlport_req_data[9:0];
+            s_ctrlport_resp_ack  <= 1;
+          end
+          REG_RX_ERR_REM_EPID: begin
+            reg_error_rem_epid  <= s_ctrlport_req_data[15:0];
+            s_ctrlport_resp_ack <= 1;
+          end
+          REG_RX_ERR_ADDR: begin
+            reg_error_addr      <= s_ctrlport_req_data[19:0];
+            s_ctrlport_resp_ack <= 1;
+          end
+          REG_RX_HAS_TIME: begin
+            reg_has_time        <= s_ctrlport_req_data[0:0];
+            s_ctrlport_resp_ack <= 1;
+          end
+        endcase
+      end
+
+      // Handle register reads
+      if (s_ctrlport_req_rd) begin
+        case (s_ctrlport_req_addr)
+          REG_RX_STATUS: begin
+            s_ctrlport_resp_data[CMD_FIFO_SPACE_POS+:CMD_FIFO_SPACE_LEN] 
+                                <= cmd_fifo_space[CMD_FIFO_SPACE_LEN-1:0];
+            s_ctrlport_resp_ack <= 1;
+          end
+          REG_RX_CMD: begin
+            s_ctrlport_resp_data[RX_CMD_LEN-1:0]   <= reg_cmd_word;
+            s_ctrlport_resp_data[RX_CMD_TIMED_POS] <= reg_cmd_timed;
+            s_ctrlport_resp_ack                    <= 1;
+          end
+          REG_RX_CMD_NUM_WORDS_LO: begin
+            s_ctrlport_resp_data <= reg_cmd_num_words[31:0];
+            s_ctrlport_resp_ack  <= 1;
+          end
+          REG_RX_CMD_NUM_WORDS_HI: begin
+            s_ctrlport_resp_data[NUM_WORDS_LEN-32-1:0] <= reg_cmd_num_words[NUM_WORDS_LEN-1:32];
+            s_ctrlport_resp_ack                        <= 1;
+          end
+          REG_RX_CMD_TIME_LO: begin
+            s_ctrlport_resp_data <= reg_cmd_time[31:0];
+            s_ctrlport_resp_ack  <= 1;
+          end
+          REG_RX_CMD_TIME_HI: begin
+            s_ctrlport_resp_data <= reg_cmd_time[63:32];
+            s_ctrlport_resp_ack  <= 1;
+          end
+          REG_RX_MAX_WORDS_PER_PKT: begin
+            s_ctrlport_resp_data <= reg_max_pkt_len;
+            s_ctrlport_resp_ack  <= 1;
+          end
+          REG_RX_ERR_PORT: begin
+            s_ctrlport_resp_data[9:0] <= reg_error_portid;
+            s_ctrlport_resp_ack       <= 1;
+          end
+          REG_RX_ERR_REM_PORT: begin
+            s_ctrlport_resp_data[9:0] <= reg_error_rem_portid;
+            s_ctrlport_resp_ack       <= 1;
+          end
+          REG_RX_ERR_REM_EPID: begin
+            s_ctrlport_resp_data[15:0] <= reg_error_rem_epid;
+            s_ctrlport_resp_ack        <= 1;
+          end
+          REG_RX_ERR_ADDR: begin
+            s_ctrlport_resp_data[19:0] <= reg_error_addr;
+            s_ctrlport_resp_ack        <= 1;
+          end
+          REG_RX_DATA: begin
+            s_ctrlport_resp_data <= radio_rx_data;
+            s_ctrlport_resp_ack  <= 1;
+          end
+          REG_RX_HAS_TIME: begin
+            s_ctrlport_resp_data[0] <= reg_has_time;
+            s_ctrlport_resp_ack     <= 1;
+          end
+        endcase
+      end
+
+    end
+  end
+
+
+  //---------------------------------------------------------------------------
+  // Command Queue
+  //---------------------------------------------------------------------------
+
+  wire [             63:0] cmd_time;        // Time for next start of command
+  wire                     cmd_timed;       // Command is timed (use cmd_time)
+  wire [NUM_WORDS_LEN-1:0] cmd_num_words;   // Number of words for next command
+  wire                     cmd_continuous;  // Command is continuous (ignore cmd_num_words)
+  wire                     cmd_valid;       // cmd_* is a valid command
+  wire                     cmd_done;        // Command has completed and can be popped from FIFO
+
+  axi_fifo #(
+    .WIDTH (64 + 1 + NUM_WORDS_LEN + 1),
+    .SIZE  (5)      // Ideally, this size will lead to an SRL-based FIFO
+  ) cmd_fifo (
+    .clk      (radio_clk),
+    .reset    (radio_rst),
+    .clear    (clear_fifo),
+    .i_tdata  ({ reg_cmd_time, reg_cmd_timed, reg_cmd_num_words, (reg_cmd_word == RX_CMD_CONTINUOUS) }),
+    .i_tvalid (reg_cmd_valid),
+    .i_tready (),
+    .o_tdata  ({ cmd_time, cmd_timed, cmd_num_words, cmd_continuous }),
+    .o_tvalid (cmd_valid),
+    .o_tready (cmd_done),
+    .space    (cmd_fifo_space),
+    .occupied ()
+  );
+
+
+  //---------------------------------------------------------------------------
+  // Receiver State Machine
+  //---------------------------------------------------------------------------
+
+  // FSM state values
+  localparam ST_IDLE               = 0;
+  localparam ST_TIME_CHECK         = 1;
+  localparam ST_RUNNING            = 2;
+  localparam ST_STOP               = 3;
+  localparam ST_REPORT_ERR         = 4;
+  localparam ST_REPORT_ERR_WAIT    = 5;
+
+  reg [              2:0] state   = ST_IDLE; // Current state
+  reg [NUM_WORDS_LEN-1:0] words_left;        // Words left in current command
+  reg [             31:0] words_left_pkt;    // Words left in current packet
+  reg                     first_word = 1'b1; // Next word is first in packet
+  reg [             15:0] seq_num = 0;       // Sequence number (packet count)
+  reg [             63:0] error_time;        // Time at which overflow occurred
+  reg [ERR_RX_CODE_W-1:0] error_code;        // Error code register
+
+  // Output FIFO signals
+  wire [           15:0] out_fifo_space;
+  reg  [SAMP_W*NSPC-1:0] out_fifo_tdata;
+  reg                    out_fifo_tlast;
+  reg                    out_fifo_tvalid = 1'b0;
+  reg  [           63:0] out_fifo_timestamp;
+  reg                    out_fifo_teob;
+  reg                    out_fifo_almost_full;
+
+  reg [63:0] radio_time_low_samp, radio_time_hi_samp;
+  reg        time_now, time_past;
+
+  // All ctrlport requests have a time
+  assign m_ctrlport_req_has_time = 1'b1;
+
+  // Acknowledge STOP requests and pop the command FIFO in the STOP state
+  assign cmd_stop_ack = (state == ST_STOP);
+  assign cmd_done     = (state == ST_STOP);
+
+  always @(posedge radio_clk) begin
+    if (radio_rst) begin
+      state             <= ST_IDLE;
+      out_fifo_tvalid   <= 1'b0;
+      seq_num           <=  'd0;
+      m_ctrlport_req_wr <= 1'b0;
+      first_word        <= 1'b1;
+    end else begin
+      // Default assignments
+      out_fifo_tvalid         <= 1'b0;
+      out_fifo_tlast          <= 1'b0;
+      out_fifo_teob           <= 1'b0;
+      m_ctrlport_req_wr       <= 1'b0;
+
+      if (radio_rx_stb) begin
+        // Get the time for the low sample and the high sample of the radio
+        // word (needed when NISPC > 1). Compensate for the delay required to
+        // check the time by adding 3 clock cycles worth of samples.
+        radio_time_low_samp <= (radio_time + 3*NSPC);
+        radio_time_hi_samp  <= (radio_time + 3*NSPC + (NSPC-1));
+
+        // Register the time comparisons so they don't become the critical path
+        time_now  <= (cmd_time >= radio_time_low_samp &&
+                      cmd_time <= radio_time_hi_samp);
+        time_past <= (cmd_time <  radio_time_low_samp);
+      end
+
+      case (state)
+        ST_IDLE : begin
+          // Wait for a new command to arrive and allow a cycle for the time 
+          // comparisons to update.
+          if (cmd_valid && radio_rx_stb) begin
+            state <= ST_TIME_CHECK;
+          end else if (cmd_stop) begin
+            state <= ST_STOP;
+          end
+          first_word <= 1'b1;
+        end
+
+        ST_TIME_CHECK : begin
+          if (cmd_stop) begin
+            // Nothing to do but stop (timed STOP commands are not supported)
+            state <= ST_STOP;
+          end else if (cmd_timed && time_past && radio_rx_stb) begin
+            // Got this command later than its execution time
+            //synthesis translate_off
+            $display("WARNING: radio_rx_core: Late command error");
+            //synthesis translate_on
+            error_code <= ERR_RX_LATE_CMD;
+            error_time <= radio_time;
+            state      <= ST_REPORT_ERR;
+          end else if (!cmd_timed || (time_now && radio_rx_stb)) begin
+            // Either it's time to run this command or it should run
+            // immediately.
+            words_left     <= cmd_num_words;
+            words_left_pkt <= reg_max_pkt_len;
+            state          <= ST_RUNNING;
+          end
+        end
+
+        ST_RUNNING : begin
+          if (radio_rx_stb) begin
+            // Output the next word
+            out_fifo_tvalid    <= 1'b1;
+            out_fifo_tdata     <= radio_rx_data;
+            if (first_word) begin
+              out_fifo_timestamp <= radio_time;
+              first_word         <= 1'b0;
+            end
+
+            // Update word counters
+            words_left     <= words_left - 1;
+            words_left_pkt <= words_left_pkt - 1;
+
+            if ((words_left == 1 && !cmd_continuous) || cmd_stop) begin
+              // This command has finished, or we've been asked to stop.
+              state          <= ST_STOP;
+              out_fifo_tlast <= 1'b1;
+              out_fifo_teob  <= 1'b1;
+              first_word     <= 1'b1;
+            end else if (words_left_pkt == 1) begin
+              // We've finished building a packet
+              seq_num        <= seq_num + 1;
+              words_left_pkt <= reg_max_pkt_len;
+              out_fifo_tlast <= 1'b1;
+              first_word     <= 1'b1;
+            end
+
+            // Check for overflow. Note that we've left enough room in the
+            // output FIFO so that we can end the packet cleanly.
+            if (out_fifo_almost_full) begin
+              // End the command and terminate packet early
+              //synthesis translate_off
+              $display("WARNING: radio_rx_core: Overrun error");
+              //synthesis translate_on
+              out_fifo_tlast <= 1'b1;
+              out_fifo_teob  <= 1'b1;
+              seq_num        <= seq_num + 1;
+              error_time     <= radio_time;
+              error_code     <= ERR_RX_OVERRUN;
+              state          <= ST_REPORT_ERR;
+            end
+
+          end
+        end
+
+        ST_STOP : begin
+          // This single-cycle state allows time for STOP to be acknowledged 
+          // and for the command FIFO to be popped.
+          state <= ST_IDLE;
+        end
+
+        ST_REPORT_ERR : begin
+          // Setup write of error code
+          m_ctrlport_req_wr                      <= 1'b1;
+          m_ctrlport_req_data                    <= 0;
+          m_ctrlport_req_data[ERR_RX_CODE_W-1:0] <= error_code;
+          m_ctrlport_req_addr                    <= reg_error_addr;
+          m_ctrlport_req_time                    <= error_time;
+          state                                  <= ST_REPORT_ERR_WAIT;
+        end
+
+        ST_REPORT_ERR_WAIT : begin
+          // Wait for write of error code and timestamp to complete
+          if (m_ctrlport_resp_ack) begin
+            state <= ST_STOP;
+          end
+        end
+
+        default : state <= ST_IDLE;
+      endcase
+    end
+  end
+
+
+  assign radio_rx_running = (state == ST_RUNNING);  // We're actively acquiring
+
+  // Directly connect the port ID, remote port ID, and remote EPID since they 
+  // are only used for error reporting.
+  assign m_ctrlport_req_portid     = reg_error_portid;
+  assign m_ctrlport_req_rem_epid   = reg_error_rem_epid;
+  assign m_ctrlport_req_rem_portid = reg_error_rem_portid;
+
+
+  //---------------------------------------------------------------------------
+  // Output FIFO
+  //---------------------------------------------------------------------------
+  //
+  // Here we buffer output samples and monitor FIFO fullness to be able to
+  // detect overflows.
+  //
+  //---------------------------------------------------------------------------
+
+  axi_fifo #(
+    .WIDTH (1+64+1+SAMP_W*NSPC),
+    .SIZE  (5)      // Ideally, this size will lead to an SRL-based FIFO
+  ) output_fifo (
+    .clk      (radio_clk),
+    .reset    (radio_rst),
+    .clear    (1'b0),
+    .i_tdata  ({out_fifo_teob, out_fifo_timestamp, out_fifo_tlast, out_fifo_tdata}),
+    .i_tvalid (out_fifo_tvalid),
+    .i_tready (),
+    .o_tdata  ({m_axis_teob, m_axis_ttimestamp, m_axis_tlast, m_axis_tdata}),
+    .o_tvalid (m_axis_tvalid),
+    .o_tready (m_axis_tready),
+    .space    (out_fifo_space),
+    .occupied ()
+  );
+
+  // Create a register to indicate if the output FIFO is about to overflow
+  always @(posedge radio_clk) begin
+    if (radio_rst) begin
+      out_fifo_almost_full <= 1'b0;
+    end else begin
+      out_fifo_almost_full <= (out_fifo_space < 5);
+    end
+  end
+
+
+endmodule
+
+
+`default_nettype wire
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/radio_tx_core.v b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/radio_tx_core.v
new file mode 100644
index 000000000..d40db5122
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/radio_tx_core.v
@@ -0,0 +1,417 @@
+//
+// Copyright 2019 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: radio_tx_core
+//
+// Description:
+//
+// This module contains the core Tx radio data-path logic. It receives samples 
+// over AXI-Stream that it then sends to the radio interface coincident with a 
+// strobe signal that must be provided by the radio interface.
+//
+// There are no registers for starting or stopping the transmitter. It is 
+// operated simply by providing data packets via its AXI-Stream data interface. 
+// The end-of-burst (EOB) signal is used to indicate when the transmitter is 
+// allowed to stop transmitting. Packet timestamps can be used to indicate when 
+// transmission should start.
+//
+// Care must be taken to provide data to the transmitter at a rate that is 
+// faster than the radio needs it so that underflows do not occur. Similarly, 
+// timed packets must be delivered before the timestamp expires. If a packet 
+// arrives late, then it will be dropped and the error will be reported via the 
+// CTRL port interface.
+//
+// Parameters:
+//
+//   SAMP_W : Width of a radio sample
+//   NSPC   : Number of radio samples per radio clock cycle
+//
+
+
+module radio_tx_core #(
+  parameter SAMP_W = 32,
+  parameter NSPC   = 1
+) (
+  input wire radio_clk,
+  input wire radio_rst,
+
+
+  //---------------------------------------------------------------------------
+  // Control Interface
+  //---------------------------------------------------------------------------
+
+  // Slave (Register Reads and Writes)
+  input  wire        s_ctrlport_req_wr,
+  input  wire        s_ctrlport_req_rd,
+  input  wire [19:0] s_ctrlport_req_addr,
+  input  wire [31:0] s_ctrlport_req_data,
+  output reg         s_ctrlport_resp_ack  = 1'b0,
+  output reg  [31:0] s_ctrlport_resp_data,
+
+  // Master (Error Reporting)
+  output reg         m_ctrlport_req_wr = 1'b0,
+  output reg  [19:0] m_ctrlport_req_addr,
+  output reg  [31:0] m_ctrlport_req_data,
+  output wire        m_ctrlport_req_has_time,
+  output reg  [63:0] m_ctrlport_req_time,
+  output wire [ 9:0] m_ctrlport_req_portid,
+  output wire [15:0] m_ctrlport_req_rem_epid,
+  output wire [ 9:0] m_ctrlport_req_rem_portid,
+  input  wire        m_ctrlport_resp_ack,
+
+
+  //---------------------------------------------------------------------------
+  // Radio Interface
+  //---------------------------------------------------------------------------
+
+  input wire [63:0] radio_time,
+
+  output wire [SAMP_W*NSPC-1:0] radio_tx_data,
+  input  wire                   radio_tx_stb,
+
+  // Status indicator (true when transmitting)
+  output wire radio_tx_running,
+
+
+  //---------------------------------------------------------------------------
+  // AXI-Stream Data Input
+  //---------------------------------------------------------------------------
+
+  input  wire [SAMP_W*NSPC-1:0] s_axis_tdata,
+  input  wire                   s_axis_tlast,
+  input  wire                   s_axis_tvalid,
+  output wire                   s_axis_tready,
+  // Sideband info
+  input  wire [           63:0] s_axis_ttimestamp,
+  input  wire                   s_axis_thas_time,
+  input  wire                   s_axis_teob
+);
+
+  `include "rfnoc_block_radio_regs.vh"
+  `include "../../core/rfnoc_chdr_utils.vh"
+
+
+  //---------------------------------------------------------------------------
+  // Register Read/Write Logic
+  //---------------------------------------------------------------------------
+
+  reg [SAMP_W-1:0] reg_idle_value       = 0; // Value to output when transmitter is idle
+  reg [       9:0] reg_error_portid     = 0; // Port ID to use for error reporting
+  reg [      15:0] reg_error_rem_epid   = 0; // Remote EPID to use for error reporting
+  reg [       9:0] reg_error_rem_portid = 0; // Remote port ID to use for error reporting
+  reg [      19:0] reg_error_addr       = 0; // Address to use for error reporting
+
+  reg [TX_ERR_POLICY_LEN-1:0] reg_policy = TX_ERR_POLICY_PACKET;
+
+  always @(posedge radio_clk) begin
+    if (radio_rst) begin
+      s_ctrlport_resp_ack  <= 0;
+      reg_idle_value       <= 0;
+      reg_error_portid     <= 0;
+      reg_error_rem_epid   <= 0;
+      reg_error_rem_portid <= 0;
+      reg_error_addr       <= 0;
+      reg_policy           <= TX_ERR_POLICY_PACKET;
+    end else begin
+      // Default assignments
+      s_ctrlport_resp_ack  <= 0;
+      s_ctrlport_resp_data <= 0;
+
+      // Handle register writes
+      if (s_ctrlport_req_wr) begin
+        case (s_ctrlport_req_addr)
+          REG_TX_IDLE_VALUE: begin
+            reg_idle_value      <= s_ctrlport_req_data[SAMP_W-1:0];
+            s_ctrlport_resp_ack <= 1;
+          end
+          REG_TX_ERROR_POLICY: begin
+            // Only allow valid configurations
+            case (s_ctrlport_req_data[TX_ERR_POLICY_LEN-1:0])
+              TX_ERR_POLICY_PACKET : reg_policy <= TX_ERR_POLICY_PACKET;
+              TX_ERR_POLICY_BURST  : reg_policy <= TX_ERR_POLICY_BURST;
+              default              : reg_policy <= TX_ERR_POLICY_PACKET;
+            endcase
+            s_ctrlport_resp_ack <= 1;
+          end
+          REG_TX_ERR_PORT: begin
+            reg_error_portid    <= s_ctrlport_req_data[9:0];
+            s_ctrlport_resp_ack <= 1;
+          end
+          REG_TX_ERR_REM_PORT: begin
+            reg_error_rem_portid <= s_ctrlport_req_data[9:0];
+            s_ctrlport_resp_ack  <= 1;
+          end
+          REG_TX_ERR_REM_EPID: begin
+            reg_error_rem_epid  <= s_ctrlport_req_data[15:0];
+            s_ctrlport_resp_ack <= 1;
+          end
+          REG_TX_ERR_ADDR: begin
+            reg_error_addr      <= s_ctrlport_req_data[19:0];
+            s_ctrlport_resp_ack <= 1;
+          end
+        endcase
+      end
+
+      // Handle register reads
+      if (s_ctrlport_req_rd) begin
+        case (s_ctrlport_req_addr)
+          REG_TX_IDLE_VALUE: begin
+            s_ctrlport_resp_data[SAMP_W-1:0] <= reg_idle_value;
+            s_ctrlport_resp_ack              <= 1;
+          end
+          REG_TX_ERROR_POLICY: begin
+            s_ctrlport_resp_data[TX_ERR_POLICY_LEN-1:0] <= reg_policy;
+            s_ctrlport_resp_ack                         <= 1;
+          end
+          REG_TX_ERR_PORT: begin
+            s_ctrlport_resp_data[9:0] <= reg_error_portid;
+            s_ctrlport_resp_ack       <= 1;
+          end
+          REG_TX_ERR_REM_PORT: begin
+            s_ctrlport_resp_data[9:0] <= reg_error_rem_portid;
+            s_ctrlport_resp_ack       <= 1;
+          end
+          REG_TX_ERR_REM_EPID: begin
+            s_ctrlport_resp_data[15:0] <= reg_error_rem_epid;
+            s_ctrlport_resp_ack        <= 1;
+          end
+          REG_TX_ERR_ADDR: begin
+            s_ctrlport_resp_data[19:0] <= reg_error_addr;
+            s_ctrlport_resp_ack        <= 1;
+          end
+        endcase
+      end
+    end
+  end
+
+
+  //---------------------------------------------------------------------------
+  // Transmitter State Machine
+  //---------------------------------------------------------------------------
+
+  // FSM state values
+  localparam ST_IDLE        = 0;
+  localparam ST_TIME_CHECK  = 1;
+  localparam ST_TRANSMIT    = 2;
+  localparam ST_POLICY_WAIT = 3;
+
+  reg [1:0] state = ST_IDLE;
+
+  reg sop = 1'b1;  // Start of packet
+
+  reg [ERR_TX_CODE_W-1:0] new_error_code;
+  reg [             63:0] new_error_time;
+  reg                     new_error_valid = 1'b0;
+
+  reg time_now, time_past;
+
+
+  always @(posedge radio_clk) begin
+    if (radio_rst) begin
+      state           <= ST_IDLE;
+      sop             <= 1'b1;
+      new_error_valid <= 1'b0;
+    end else begin
+      new_error_valid <= 1'b0;
+
+      // Register time comparisons so they don't become the critical path
+      time_now  <= (radio_time == s_axis_ttimestamp);
+      time_past <= (radio_time >  s_axis_ttimestamp);
+
+      // Track if the next word will be the start of a packet (sop)
+      if (s_axis_tvalid && s_axis_tready) begin
+        sop <= s_axis_tlast;
+      end
+
+      case (state)
+        ST_IDLE : begin
+          // Wait for a new packet to arrive and allow a cycle for the time 
+          // comparisons to update.
+          if (s_axis_tvalid) begin
+            state <= ST_TIME_CHECK;
+          end
+        end
+
+        ST_TIME_CHECK : begin
+          if (!s_axis_thas_time || time_now) begin
+            // We have a new packet without a timestamp, or a new packet
+            // whose time has arrived.
+            state <= ST_TRANSMIT;
+          end else if (time_past) begin
+            // We have a new packet with a timestamp, but the time has passed.
+            //synthesis translate off
+            $display("WARNING: radio_tx_core: Late data error");
+            //synthesis translate_on
+            new_error_code  <= ERR_TX_LATE_DATA;
+            new_error_time  <= radio_time;
+            new_error_valid <= 1'b1;
+            state           <= ST_POLICY_WAIT;
+          end
+        end
+
+        ST_TRANSMIT : begin
+          if (radio_tx_stb) begin
+            if (!s_axis_tvalid) begin
+              // The radio strobed for new data but we don't have any to give
+              //synthesis translate off
+              $display("WARNING: radio_tx_core: Underrun error");
+              //synthesis translate_on
+              new_error_code  <= ERR_TX_UNDERRUN;
+              new_error_time  <= radio_time;
+              new_error_valid <= 1'b1;
+              state           <= ST_POLICY_WAIT;
+            end else if (s_axis_tlast && s_axis_teob) begin
+              // We're done with this burst of packets, so acknowledge EOB and
+              // go back to idle.
+              new_error_code  <= ERR_TX_EOB_ACK;
+              new_error_time  <= radio_time;
+              new_error_valid <= 1'b1;
+              state <= ST_IDLE;
+            end
+          end
+        end
+
+        ST_POLICY_WAIT : begin
+          // If we came here from ST_TIME_CHECK or ST_TRANSMIT and we're in the
+          // middle of a packet then we just wait until we reach the end of the
+          // packet.
+          if (s_axis_tvalid && s_axis_tlast) begin
+            // We're either at the end of a packet or between packets
+            if (reg_policy == TX_ERR_POLICY_PACKET ||
+               (reg_policy == TX_ERR_POLICY_BURST  && s_axis_teob)) begin
+              state <= ST_IDLE;
+            end
+
+          // If we came from ST_TRANSMIT and we happen to already be between
+          // packets (i.e., we underflowed while waiting for the next packet).
+          end else if (!s_axis_tvalid && sop) begin
+            if (reg_policy == TX_ERR_POLICY_PACKET) state <= ST_IDLE;
+          end
+        end
+
+        default : state <= ST_IDLE;
+      endcase
+    end
+  end
+
+
+  // Output the current sample whenever we're transmitting and the sample is
+  // valid. Otherwise, output the idle value.
+  assign radio_tx_data = (s_axis_tvalid && state == ST_TRANSMIT) ?
+                         s_axis_tdata :
+                         {NSPC{reg_idle_value[SAMP_W-1:0]}};
+
+  // Read packet in the transmit state or dump it in the error state
+  assign s_axis_tready = (radio_tx_stb && (state == ST_TRANSMIT)) ||
+                         (state == ST_POLICY_WAIT);
+
+  // Indicate whether Tx interface is actively transmitting
+  assign radio_tx_running = (state == ST_TRANSMIT);
+
+
+  //---------------------------------------------------------------------------
+  // Error FIFO
+  //---------------------------------------------------------------------------
+  //
+  // This FIFO queues up errors in case we get multiple errors in a row faster
+  // than they can be reported. If the FIFO fills then new errors will be
+  // ignored.
+  //
+  //---------------------------------------------------------------------------
+
+  // Error information
+  wire [ERR_TX_CODE_W-1:0] next_error_code;
+  wire [             63:0] next_error_time;
+  wire                     next_error_valid;
+  reg                      next_error_ready = 1'b0;
+
+  wire new_error_ready;
+
+  axi_fifo_short #(
+    .WIDTH (64 + ERR_TX_CODE_W)
+  ) error_fifo (
+    .clk      (radio_clk),
+    .reset    (radio_rst),
+    .clear    (1'b0),
+    .i_tdata  ({new_error_time, new_error_code}),
+    .i_tvalid (new_error_valid & new_error_ready),   // Mask with ready to prevent FIFO corruption
+    .i_tready (new_error_ready),
+    .o_tdata  ({next_error_time, next_error_code}),
+    .o_tvalid (next_error_valid),
+    .o_tready (next_error_ready),
+    .space    (),
+    .occupied ()
+  );
+
+  //synthesis translate_off
+  // Output a message if the error FIFO overflows
+  always @(posedge radio_clk) begin
+    if (new_error_valid && !new_error_ready) begin
+      $display("WARNING: Tx error report dropped!");
+    end
+  end
+  //synthesis translate_on
+
+
+  //---------------------------------------------------------------------------
+  // Error Reporting State Machine
+  //---------------------------------------------------------------------------
+  //
+  // This state machine reports errors that have been queued up in the error
+  // FIFO.
+  //
+  //---------------------------------------------------------------------------
+
+  localparam ST_ERR_IDLE     = 0;
+  localparam ST_ERR_CODE     = 1;
+
+  reg [0:0] err_state = ST_ERR_IDLE;
+
+  // All ctrlport requests have a time
+  assign m_ctrlport_req_has_time = 1'b1;
+
+  always @(posedge radio_clk) begin
+    if (radio_rst) begin
+      m_ctrlport_req_wr <= 1'b0;
+      err_state         <= ST_ERR_IDLE;
+      next_error_ready  <= 1'b0;
+    end else begin
+      m_ctrlport_req_wr       <= 1'b0;
+      next_error_ready        <= 1'b0;
+
+      case (err_state)
+        ST_ERR_IDLE : begin
+          if (next_error_valid) begin
+            // Setup write of error code
+            m_ctrlport_req_wr       <= 1'b1;
+            m_ctrlport_req_addr     <= reg_error_addr;
+            m_ctrlport_req_data     <= {{(32-ERR_TX_CODE_W){1'b0}}, next_error_code};
+            m_ctrlport_req_time     <= next_error_time;
+            next_error_ready        <= 1'b1;
+            err_state               <= ST_ERR_CODE;
+          end
+        end
+
+        ST_ERR_CODE : begin
+          // Wait for write of error code and timestamp
+          if (m_ctrlport_resp_ack) begin
+            err_state <= ST_ERR_IDLE;
+          end
+        end
+
+        default : err_state <= ST_ERR_IDLE;
+      endcase
+    end
+  end
+
+
+  // Directly connect the port ID, remote port ID, remote EPID since they are 
+  // only used for error reporting.
+  assign m_ctrlport_req_portid     = reg_error_portid;
+  assign m_ctrlport_req_rem_epid   = reg_error_rem_epid;
+  assign m_ctrlport_req_rem_portid = reg_error_rem_portid;
+
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/rfnoc_block_radio.v b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/rfnoc_block_radio.v
new file mode 100644
index 000000000..a97b141c0
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/rfnoc_block_radio.v
@@ -0,0 +1,546 @@
+//
+// Copyright 2019 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: rfnoc_block_radio
+//
+// Description:  This is the top-level file for the RFNoC radio block.
+//
+// Parameters:
+//
+//   THIS_PORTID      : CTRL port ID to which this block is connected
+//   CHDR_W           : CHDR AXI-Stream data bus width
+//   NIPC             : Number of radio samples per radio clock cycle
+//   ITEM_W           : Radio sample width
+//   NUM_PORTS        : Number of radio channels (RX/TX pairs)
+//   MTU              : Maximum transmission unit (i.e., maximum packet size) 
+//                      in CHDR words is 2**MTU.
+//   CTRL_FIFO_SIZE   : Size of the Control Port slave FIFO. This affects the
+//                      number of outstanding commands that can be pending.
+//   PERIPH_BASE_ADDR : CTRL port peripheral window base address
+//   PERIPH_ADDR_W    : CTRL port peripheral address space = 2**PERIPH_ADDR_W
+//
+
+
+module rfnoc_block_radio #(
+  parameter THIS_PORTID      = 0,
+  parameter CHDR_W           = 64,
+  parameter NIPC             = 1,
+  parameter ITEM_W           = 32,
+  parameter NUM_PORTS        = 2,
+  parameter MTU              = 10,
+  parameter CTRL_FIFO_SIZE   = 9,
+  parameter PERIPH_BASE_ADDR = 20'h80000,
+  parameter PERIPH_ADDR_W    = 19
+) (
+  //---------------------------------------------------------------------------
+  // AXIS CHDR Port
+  //---------------------------------------------------------------------------
+
+  input wire rfnoc_chdr_clk,
+
+  // CHDR inputs from framework
+  input  wire [CHDR_W*NUM_PORTS-1:0] s_rfnoc_chdr_tdata,
+  input  wire [       NUM_PORTS-1:0] s_rfnoc_chdr_tlast,
+  input  wire [       NUM_PORTS-1:0] s_rfnoc_chdr_tvalid,
+  output wire [       NUM_PORTS-1:0] s_rfnoc_chdr_tready,
+
+  // CHDR outputs to framework
+  output wire [CHDR_W*NUM_PORTS-1:0] m_rfnoc_chdr_tdata,
+  output wire [       NUM_PORTS-1:0] m_rfnoc_chdr_tlast,
+  output wire [       NUM_PORTS-1:0] m_rfnoc_chdr_tvalid,
+  input  wire [       NUM_PORTS-1:0] m_rfnoc_chdr_tready,
+
+  // Backend interface
+  input  wire [511:0] rfnoc_core_config,
+  output wire [511:0] rfnoc_core_status,
+
+
+  //---------------------------------------------------------------------------
+  // AXIS CTRL Port
+  //---------------------------------------------------------------------------
+
+  input wire rfnoc_ctrl_clk,
+
+  // CTRL port requests from framework
+  input  wire [31:0] s_rfnoc_ctrl_tdata,
+  input  wire        s_rfnoc_ctrl_tlast,
+  input  wire        s_rfnoc_ctrl_tvalid,
+  output wire        s_rfnoc_ctrl_tready,
+
+  // CTRL port requests to framework
+  output wire [31:0] m_rfnoc_ctrl_tdata,
+  output wire        m_rfnoc_ctrl_tlast,
+  output wire        m_rfnoc_ctrl_tvalid,
+  input  wire        m_rfnoc_ctrl_tready,
+
+
+  //---------------------------------------------------------------------------
+  // CTRL Port Peripheral Interface
+  //---------------------------------------------------------------------------
+
+  output wire        m_ctrlport_req_wr,
+  output wire        m_ctrlport_req_rd,
+  output wire [19:0] m_ctrlport_req_addr,
+  output wire [31:0] m_ctrlport_req_data,
+  output wire [ 3:0] m_ctrlport_req_byte_en,
+  output wire        m_ctrlport_req_has_time,
+  output wire [63:0] m_ctrlport_req_time,
+  input  wire        m_ctrlport_resp_ack,
+  input  wire [ 1:0] m_ctrlport_resp_status,
+  input  wire [31:0] m_ctrlport_resp_data,
+
+
+  //---------------------------------------------------------------------------
+  // Radio Interface
+  //---------------------------------------------------------------------------
+
+  input wire radio_clk,
+
+  // Timekeeper interface
+  input wire [63:0] radio_time,
+
+  // Radio Rx interface
+  input  wire [(ITEM_W*NIPC)*NUM_PORTS-1:0] radio_rx_data,
+  input  wire [              NUM_PORTS-1:0] radio_rx_stb,
+  output wire [              NUM_PORTS-1:0] radio_rx_running,
+
+  // Radio Tx interface
+  output wire [(ITEM_W*NIPC)*NUM_PORTS-1:0] radio_tx_data,
+  input  wire [              NUM_PORTS-1:0] radio_tx_stb,
+  output wire [              NUM_PORTS-1:0] radio_tx_running
+);
+
+  `include "rfnoc_block_radio_regs.vh"
+  `include "../../core/rfnoc_axis_ctrl_utils.vh"
+
+  localparam NOC_ID  = 32'h12AD1000;
+  localparam RADIO_W = NIPC*ITEM_W;
+
+
+  // Radio Tx data stream
+  wire [RADIO_W*NUM_PORTS-1:0] axis_tx_tdata;
+  wire [        NUM_PORTS-1:0] axis_tx_tlast;
+  wire [        NUM_PORTS-1:0] axis_tx_tvalid;
+  wire [        NUM_PORTS-1:0] axis_tx_tready;
+  wire [     64*NUM_PORTS-1:0] axis_tx_ttimestamp;
+  wire [        NUM_PORTS-1:0] axis_tx_thas_time;
+  wire [        NUM_PORTS-1:0] axis_tx_teob;
+
+  // Radio Rx data stream
+  wire [RADIO_W*NUM_PORTS-1:0] axis_rx_tdata;
+  wire [        NUM_PORTS-1:0] axis_rx_tlast;
+  wire [        NUM_PORTS-1:0] axis_rx_tvalid;
+  wire [        NUM_PORTS-1:0] axis_rx_tready;
+  wire [     64*NUM_PORTS-1:0] axis_rx_ttimestamp;
+  wire [        NUM_PORTS-1:0] axis_rx_thas_time;
+  wire [        NUM_PORTS-1:0] axis_rx_teob;
+
+  // Control port signals used for register access (NoC shell masters user logic)
+  wire        ctrlport_reg_req_wr;
+  wire        ctrlport_reg_req_rd;
+  wire [19:0] ctrlport_reg_req_addr;
+  wire        ctrlport_reg_has_time;
+  wire [63:0] ctrlport_reg_time;
+  wire [31:0] ctrlport_reg_req_data;
+  wire [31:0] ctrlport_reg_resp_data;
+  wire        ctrlport_reg_resp_ack;
+
+  // Control port signals used for error reporting (user logic masters to NoC shell)
+  wire        ctrlport_err_req_wr;
+  wire [19:0] ctrlport_err_req_addr;
+  wire [ 9:0] ctrlport_err_req_portid;
+  wire [15:0] ctrlport_err_req_rem_epid;
+  wire [ 9:0] ctrlport_err_req_rem_portid;
+  wire [31:0] ctrlport_err_req_data;
+  wire        ctrlport_err_req_has_time;
+  wire [63:0] ctrlport_err_req_time;
+  wire        ctrlport_err_resp_ack;
+
+
+  //---------------------------------------------------------------------------
+  // NoC Shell
+  //---------------------------------------------------------------------------
+
+  wire rfnoc_chdr_rst;
+  wire radio_rst;
+
+  noc_shell_radio #(
+    .NOC_ID          (NOC_ID),
+    .THIS_PORTID     (THIS_PORTID),
+    .CHDR_W          (CHDR_W),
+    .CTRLPORT_SLV_EN (1),
+    .CTRLPORT_MST_EN (1),
+    .CTRL_FIFO_SIZE  (CTRL_FIFO_SIZE),
+    .NUM_DATA_I      (NUM_PORTS),
+    .NUM_DATA_O      (NUM_PORTS),
+    .ITEM_W          (ITEM_W),
+    .NIPC            (NIPC),
+    .PYLD_FIFO_SIZE  (MTU),
+    .MTU             (MTU)
+  ) noc_shell_radio_i (
+    .rfnoc_chdr_clk            (rfnoc_chdr_clk),
+    .rfnoc_chdr_rst            (rfnoc_chdr_rst),
+    .rfnoc_ctrl_clk            (rfnoc_ctrl_clk),
+    .rfnoc_ctrl_rst            (),
+    .rfnoc_core_config         (rfnoc_core_config),
+    .rfnoc_core_status         (rfnoc_core_status),
+    .s_rfnoc_chdr_tdata        (s_rfnoc_chdr_tdata),
+    .s_rfnoc_chdr_tlast        (s_rfnoc_chdr_tlast),
+    .s_rfnoc_chdr_tvalid       (s_rfnoc_chdr_tvalid),
+    .s_rfnoc_chdr_tready       (s_rfnoc_chdr_tready),
+    .m_rfnoc_chdr_tdata        (m_rfnoc_chdr_tdata),
+    .m_rfnoc_chdr_tlast        (m_rfnoc_chdr_tlast),
+    .m_rfnoc_chdr_tvalid       (m_rfnoc_chdr_tvalid),
+    .m_rfnoc_chdr_tready       (m_rfnoc_chdr_tready),
+    .s_rfnoc_ctrl_tdata        (s_rfnoc_ctrl_tdata),
+    .s_rfnoc_ctrl_tlast        (s_rfnoc_ctrl_tlast),
+    .s_rfnoc_ctrl_tvalid       (s_rfnoc_ctrl_tvalid),
+    .s_rfnoc_ctrl_tready       (s_rfnoc_ctrl_tready),
+    .m_rfnoc_ctrl_tdata        (m_rfnoc_ctrl_tdata),
+    .m_rfnoc_ctrl_tlast        (m_rfnoc_ctrl_tlast),
+    .m_rfnoc_ctrl_tvalid       (m_rfnoc_ctrl_tvalid),
+    .m_rfnoc_ctrl_tready       (m_rfnoc_ctrl_tready),
+    .ctrlport_clk              (radio_clk),
+    .ctrlport_rst              (radio_rst),
+    .m_ctrlport_req_wr         (ctrlport_reg_req_wr),
+    .m_ctrlport_req_rd         (ctrlport_reg_req_rd),
+    .m_ctrlport_req_addr       (ctrlport_reg_req_addr),
+    .m_ctrlport_req_data       (ctrlport_reg_req_data),
+    .m_ctrlport_req_byte_en    (),
+    .m_ctrlport_req_has_time   (ctrlport_reg_has_time),
+    .m_ctrlport_req_time       (ctrlport_reg_time),
+    .m_ctrlport_resp_ack       (ctrlport_reg_resp_ack),
+    .m_ctrlport_resp_status    (AXIS_CTRL_STS_OKAY),
+    .m_ctrlport_resp_data      (ctrlport_reg_resp_data),
+    .s_ctrlport_req_wr         (ctrlport_err_req_wr),
+    .s_ctrlport_req_rd         (1'b0),
+    .s_ctrlport_req_addr       (ctrlport_err_req_addr),
+    .s_ctrlport_req_portid     (ctrlport_err_req_portid),
+    .s_ctrlport_req_rem_epid   (ctrlport_err_req_rem_epid),
+    .s_ctrlport_req_rem_portid (ctrlport_err_req_rem_portid),
+    .s_ctrlport_req_data       (ctrlport_err_req_data),
+    .s_ctrlport_req_byte_en    (4'hF),
+    .s_ctrlport_req_has_time   (ctrlport_err_req_has_time),
+    .s_ctrlport_req_time       (ctrlport_err_req_time),
+    .s_ctrlport_resp_ack       (ctrlport_err_resp_ack),
+    .s_ctrlport_resp_status    (),
+    .s_ctrlport_resp_data      (),
+    .axis_data_clk             (radio_clk),
+    .axis_data_rst             (radio_rst),
+    .m_axis_tdata              (axis_tx_tdata),
+    .m_axis_tkeep              (),                          // Radio only transmits full words
+    .m_axis_tlast              (axis_tx_tlast),
+    .m_axis_tvalid             (axis_tx_tvalid),
+    .m_axis_tready             (axis_tx_tready),
+    .m_axis_ttimestamp         (axis_tx_ttimestamp),
+    .m_axis_thas_time          (axis_tx_thas_time),
+    .m_axis_teov               (),
+    .m_axis_teob               (axis_tx_teob),
+    .s_axis_tdata              (axis_rx_tdata),
+    .s_axis_tkeep              ({NUM_PORTS*NIPC{1'b1}}), // Radio only receives full words
+    .s_axis_tlast              (axis_rx_tlast),
+    .s_axis_tvalid             (axis_rx_tvalid),
+    .s_axis_tready             (axis_rx_tready),
+    .s_axis_ttimestamp         (axis_rx_ttimestamp),
+    .s_axis_thas_time          (axis_rx_thas_time),
+    .s_axis_teov               ({NUM_PORTS{1'b0}}),
+    .s_axis_teob               (axis_rx_teob)
+  );
+
+  // Cross the CHDR reset to the radio_clk domain
+  pulse_synchronizer #(
+    .MODE ("POSEDGE")
+  ) ctrl_rst_sync_i (
+    .clk_a   (rfnoc_chdr_clk),
+    .rst_a   (1'b0),
+    .pulse_a (rfnoc_chdr_rst),
+    .busy_a  (),
+    .clk_b   (radio_clk),
+    .pulse_b (radio_rst)
+  );
+
+
+  //---------------------------------------------------------------------------
+  // Decode Control Port Addresses
+  //---------------------------------------------------------------------------
+  //
+  // This block splits the NoC shell's single master control port interface 
+  // into three masters, connected to the shared registers, radio cores, and 
+  // the external CTRL port peripheral interface. The responses from each of 
+  // these are merged into a single response and sent back to the NoC shell.
+  //
+  //---------------------------------------------------------------------------
+
+  wire        ctrlport_shared_req_wr;
+  wire        ctrlport_shared_req_rd;
+  wire [19:0] ctrlport_shared_req_addr;
+  wire [31:0] ctrlport_shared_req_data;
+  wire [ 3:0] ctrlport_shared_req_byte_en;
+  wire        ctrlport_shared_req_has_time;
+  wire [63:0] ctrlport_shared_req_time;
+  reg         ctrlport_shared_resp_ack  = 1'b0;
+  reg  [31:0] ctrlport_shared_resp_data = 0;
+
+  wire        ctrlport_core_req_wr;
+  wire        ctrlport_core_req_rd;
+  wire [19:0] ctrlport_core_req_addr;
+  wire [31:0] ctrlport_core_req_data;
+  wire [ 3:0] ctrlport_core_req_byte_en;
+  wire        ctrlport_core_req_has_time;
+  wire [63:0] ctrlport_core_req_time;
+  wire        ctrlport_core_resp_ack;
+  wire [31:0] ctrlport_core_resp_data;
+
+  ctrlport_decoder_param #(
+    .NUM_SLAVES (3),
+    .PORT_BASE  ({PERIPH_BASE_ADDR, RADIO_BASE_ADDR,                  SHARED_BASE_ADDR}),
+    .PORT_ADDR_W({PERIPH_ADDR_W,    RADIO_ADDR_W + $clog2(NUM_PORTS), SHARED_ADDR_W})
+  ) ctrlport_decoder_param_i (
+    .ctrlport_clk            (radio_clk),
+    .ctrlport_rst            (radio_rst),
+    .s_ctrlport_req_wr       (ctrlport_reg_req_wr),
+    .s_ctrlport_req_rd       (ctrlport_reg_req_rd),
+    .s_ctrlport_req_addr     (ctrlport_reg_req_addr),
+    .s_ctrlport_req_data     (ctrlport_reg_req_data),
+    .s_ctrlport_req_byte_en  (4'b0),
+    .s_ctrlport_req_has_time (ctrlport_reg_has_time),
+    .s_ctrlport_req_time     (ctrlport_reg_time),
+    .s_ctrlport_resp_ack     (ctrlport_reg_resp_ack),
+    .s_ctrlport_resp_status  (),
+    .s_ctrlport_resp_data    (ctrlport_reg_resp_data),
+    .m_ctrlport_req_wr       ({m_ctrlport_req_wr,
+                               ctrlport_core_req_wr,
+                               ctrlport_shared_req_wr}),
+    .m_ctrlport_req_rd       ({m_ctrlport_req_rd,
+                               ctrlport_core_req_rd,
+                               ctrlport_shared_req_rd}),
+    .m_ctrlport_req_addr     ({m_ctrlport_req_addr,
+                               ctrlport_core_req_addr,
+                               ctrlport_shared_req_addr}),
+    .m_ctrlport_req_data     ({m_ctrlport_req_data,
+                               ctrlport_core_req_data,
+                               ctrlport_shared_req_data}),
+    .m_ctrlport_req_byte_en  ({m_ctrlport_req_byte_en,
+                               ctrlport_core_req_byte_en,
+                               ctrlport_shared_req_byte_en}),
+    .m_ctrlport_req_has_time ({m_ctrlport_req_has_time,
+                               ctrlport_core_req_has_time,
+                               ctrlport_shared_req_has_time}),
+    .m_ctrlport_req_time     ({m_ctrlport_req_time,
+                               ctrlport_core_req_time,
+                               ctrlport_shared_req_time}),
+    .m_ctrlport_resp_ack     ({m_ctrlport_resp_ack,
+                               ctrlport_core_resp_ack,
+                               ctrlport_shared_resp_ack}),
+    .m_ctrlport_resp_status  ({m_ctrlport_resp_status,
+                              2'b00,
+                              2'b00}),
+    .m_ctrlport_resp_data    ({m_ctrlport_resp_data,
+                               ctrlport_core_resp_data,
+                               ctrlport_shared_resp_data
+                               })
+  );
+
+
+  //---------------------------------------------------------------------------
+  // Split Radio Control Port Interfaces
+  //---------------------------------------------------------------------------
+
+  wire [   NUM_PORTS-1:0] ctrlport_radios_req_wr;
+  wire [   NUM_PORTS-1:0] ctrlport_radios_req_rd;
+  wire [20*NUM_PORTS-1:0] ctrlport_radios_req_addr;
+  wire [32*NUM_PORTS-1:0] ctrlport_radios_req_data;
+  wire [   NUM_PORTS-1:0] ctrlport_radios_resp_ack;
+  wire [32*NUM_PORTS-1:0] ctrlport_radios_resp_data;
+
+  ctrlport_decoder #(
+    .NUM_SLAVES   (NUM_PORTS),
+    .BASE_ADDR    (0),
+    .SLAVE_ADDR_W (RADIO_ADDR_W)
+  ) ctrlport_decoder_i (
+    .ctrlport_clk            (radio_clk),
+    .ctrlport_rst            (radio_rst),
+    .s_ctrlport_req_wr       (ctrlport_core_req_wr),
+    .s_ctrlport_req_rd       (ctrlport_core_req_rd),
+    .s_ctrlport_req_addr     (ctrlport_core_req_addr),
+    .s_ctrlport_req_data     (ctrlport_core_req_data),
+    .s_ctrlport_req_byte_en  (4'b0),
+    .s_ctrlport_req_has_time (1'b0),
+    .s_ctrlport_req_time     (64'b0),
+    .s_ctrlport_resp_ack     (ctrlport_core_resp_ack),
+    .s_ctrlport_resp_status  (),
+    .s_ctrlport_resp_data    (ctrlport_core_resp_data),
+    .m_ctrlport_req_wr       (ctrlport_radios_req_wr),
+    .m_ctrlport_req_rd       (ctrlport_radios_req_rd),
+    .m_ctrlport_req_addr     (ctrlport_radios_req_addr),
+    .m_ctrlport_req_data     (ctrlport_radios_req_data),
+    .m_ctrlport_req_byte_en  (),
+    .m_ctrlport_req_has_time (),
+    .m_ctrlport_req_time     (),
+    .m_ctrlport_resp_ack     (ctrlport_radios_resp_ack),
+    .m_ctrlport_resp_status  ({NUM_PORTS{2'b00}}),
+    .m_ctrlport_resp_data    (ctrlport_radios_resp_data)
+  );
+
+
+  //---------------------------------------------------------------------------
+  // Merge Control Port Interfaces
+  //---------------------------------------------------------------------------
+  //
+  // This block merges the master control port interfaces of all radio_cores 
+  // into a single master for the NoC shell.
+  //
+  //---------------------------------------------------------------------------
+
+  wire [   NUM_PORTS-1:0] ctrlport_err_radio_req_wr;
+  wire [20*NUM_PORTS-1:0] ctrlport_err_radio_req_addr;
+  wire [10*NUM_PORTS-1:0] ctrlport_err_radio_req_portid;
+  wire [16*NUM_PORTS-1:0] ctrlport_err_radio_req_rem_epid;
+  wire [10*NUM_PORTS-1:0] ctrlport_err_radio_req_rem_portid;
+  wire [32*NUM_PORTS-1:0] ctrlport_err_radio_req_data;
+  wire [   NUM_PORTS-1:0] ctrlport_err_radio_req_has_time;
+  wire [64*NUM_PORTS-1:0] ctrlport_err_radio_req_time;
+  wire [   NUM_PORTS-1:0] ctrlport_err_radio_resp_ack;
+
+  ctrlport_combiner #(
+    .NUM_MASTERS (NUM_PORTS),
+    .PRIORITY    (0)
+  ) ctrlport_combiner_i (
+    .ctrlport_clk              (radio_clk),
+    .ctrlport_rst              (radio_rst),
+    .s_ctrlport_req_wr         (ctrlport_err_radio_req_wr),
+    .s_ctrlport_req_rd         ({NUM_PORTS{1'b0}}),
+    .s_ctrlport_req_addr       (ctrlport_err_radio_req_addr),
+    .s_ctrlport_req_portid     (ctrlport_err_radio_req_portid),
+    .s_ctrlport_req_rem_epid   (ctrlport_err_radio_req_rem_epid),
+    .s_ctrlport_req_rem_portid (ctrlport_err_radio_req_rem_portid),
+    .s_ctrlport_req_data       (ctrlport_err_radio_req_data),
+    .s_ctrlport_req_byte_en    ({4*NUM_PORTS{1'b1}}),
+    .s_ctrlport_req_has_time   (ctrlport_err_radio_req_has_time),
+    .s_ctrlport_req_time       (ctrlport_err_radio_req_time),
+    .s_ctrlport_resp_ack       (ctrlport_err_radio_resp_ack),
+    .s_ctrlport_resp_status    (),
+    .s_ctrlport_resp_data      (),
+    .m_ctrlport_req_wr         (ctrlport_err_req_wr),
+    .m_ctrlport_req_rd         (),
+    .m_ctrlport_req_addr       (ctrlport_err_req_addr),
+    .m_ctrlport_req_portid     (ctrlport_err_req_portid),
+    .m_ctrlport_req_rem_epid   (ctrlport_err_req_rem_epid),
+    .m_ctrlport_req_rem_portid (ctrlport_err_req_rem_portid),
+    .m_ctrlport_req_data       (ctrlport_err_req_data),
+    .m_ctrlport_req_byte_en    (),
+    .m_ctrlport_req_has_time   (ctrlport_err_req_has_time),
+    .m_ctrlport_req_time       (ctrlport_err_req_time),
+    .m_ctrlport_resp_ack       (ctrlport_err_resp_ack),
+    .m_ctrlport_resp_status    (2'b0),
+    .m_ctrlport_resp_data      (32'b0)
+  );
+
+
+  //---------------------------------------------------------------------------
+  // Shared Registers
+  //---------------------------------------------------------------------------
+  //
+  // These registers are shared by all radio channels.
+  //
+  //---------------------------------------------------------------------------
+
+  localparam [15:0] compat_major = 16'd0;
+  localparam [15:0] compat_minor = 16'd0;
+
+  always @(posedge radio_clk) begin
+    if (radio_rst) begin
+      ctrlport_shared_resp_ack  <= 0;
+      ctrlport_shared_resp_data <= 0;
+    end else begin
+      // Default assignments
+      ctrlport_shared_resp_ack  <= 0;
+      ctrlport_shared_resp_data <= 0;
+
+      // Handle register reads
+      if (ctrlport_shared_req_rd) begin
+        case (ctrlport_shared_req_addr)
+          REG_COMPAT_NUM: begin
+            ctrlport_shared_resp_ack  <= 1;
+            ctrlport_shared_resp_data <= { compat_major, compat_minor };
+          end
+        endcase
+      end
+    end
+  end
+
+
+  //---------------------------------------------------------------------------
+  // Radio Cores
+  //---------------------------------------------------------------------------
+  //
+  // This generate block instantiates one radio core for each channel that is
+  // requested by NUM_PORTS.
+  //
+  //---------------------------------------------------------------------------
+
+  genvar i;
+  generate
+    for (i = 0; i < NUM_PORTS; i = i+1) begin : radio_core_gen
+
+      // The radio core contains all the logic related to a single radio channel.
+      radio_core #(
+        .SAMP_W (ITEM_W),
+        .NSPC   (NIPC)
+      ) radio_core_i (
+        .radio_clk                 (radio_clk),
+        .radio_rst                 (radio_rst),
+
+        // Slave Control Port (Register Access)
+        .s_ctrlport_req_wr         (ctrlport_radios_req_wr[i]),
+        .s_ctrlport_req_rd         (ctrlport_radios_req_rd[i]),
+        .s_ctrlport_req_addr       (ctrlport_radios_req_addr[i*20 +: 20]),
+        .s_ctrlport_req_data       (ctrlport_radios_req_data[i*32 +: 32]),
+        .s_ctrlport_resp_ack       (ctrlport_radios_resp_ack[i]),
+        .s_ctrlport_resp_data      (ctrlport_radios_resp_data[i*32 +: 32]),
+
+        // Master Control Port (Error Reporting)
+        .m_ctrlport_req_wr         (ctrlport_err_radio_req_wr[i]),
+        .m_ctrlport_req_addr       (ctrlport_err_radio_req_addr[i*20 +: 20]),
+        .m_ctrlport_req_portid     (ctrlport_err_radio_req_portid[i*10 +: 10]),
+        .m_ctrlport_req_rem_epid   (ctrlport_err_radio_req_rem_epid[i*16 +: 16]),
+        .m_ctrlport_req_rem_portid (ctrlport_err_radio_req_rem_portid[i*10 +: 10]),
+        .m_ctrlport_req_data       (ctrlport_err_radio_req_data[i*32 +: 32]),
+        .m_ctrlport_req_has_time   (ctrlport_err_radio_req_has_time[i]),
+        .m_ctrlport_req_time       (ctrlport_err_radio_req_time[i*64 +: 64]),
+        .m_ctrlport_resp_ack       (ctrlport_err_radio_resp_ack[i]),
+
+        // Tx Data Stream
+        .s_axis_tdata              (axis_tx_tdata[RADIO_W*i +: RADIO_W]),
+        .s_axis_tlast              (axis_tx_tlast[i]),
+        .s_axis_tvalid             (axis_tx_tvalid[i]),
+        .s_axis_tready             (axis_tx_tready[i]),
+        // Sideband Info
+        .s_axis_ttimestamp         (axis_tx_ttimestamp[i*64 +: 64]),
+        .s_axis_thas_time          (axis_tx_thas_time[i]),
+        .s_axis_teob               (axis_tx_teob[i]),
+
+        // Rx Data Stream
+        .m_axis_tdata              (axis_rx_tdata[RADIO_W*i +: RADIO_W]),
+        .m_axis_tlast              (axis_rx_tlast[i]),
+        .m_axis_tvalid             (axis_rx_tvalid[i]),
+        .m_axis_tready             (axis_rx_tready[i]),
+        // Sideband Info
+        .m_axis_ttimestamp         (axis_rx_ttimestamp[i*64 +: 64]),
+        .m_axis_thas_time          (axis_rx_thas_time[i]),
+        .m_axis_teob               (axis_rx_teob[i]),
+
+        // Radio Data
+        .radio_time                (radio_time),
+        .radio_rx_data             (radio_rx_data[(RADIO_W)*i +: (RADIO_W)]),
+        .radio_rx_stb              (radio_rx_stb[i]),
+        .radio_rx_running          (radio_rx_running[i]),
+        .radio_tx_data             (radio_tx_data[(RADIO_W)*i +: (RADIO_W)]),
+        .radio_tx_stb              (radio_tx_stb[i]),
+        .radio_tx_running          (radio_tx_running[i])
+      );
+    end
+  endgenerate
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/rfnoc_block_radio_all_tb.sv b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/rfnoc_block_radio_all_tb.sv
new file mode 100644
index 000000000..ea99692bb
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/rfnoc_block_radio_all_tb.sv
@@ -0,0 +1,68 @@
+//
+// Copyright 2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: rfnoc_block_radio_all_tb
+//
+// Description: This is the testbench for rfnoc_block_radio that instantiates 
+// several variations of rfnoc_block_radio_tb to test different configurations.
+//
+
+
+module rfnoc_block_radio_all_tb;
+
+  timeunit 1ns;
+  timeprecision 1ps;
+
+  import PkgTestExec::*;
+
+
+  //---------------------------------------------------------------------------
+  // Test Definitions
+  //---------------------------------------------------------------------------
+
+  typedef struct {
+    int CHDR_W;
+    int ITEM_W;
+    int NIPC;
+    int NUM_PORTS;
+    int STALL_PROB;
+    int STB_PROB;
+    bit TEST_REGS;
+  } test_config_t;
+
+  localparam NUM_TESTS = 9;
+
+  localparam test_config_t test[NUM_TESTS] = '{
+    '{CHDR_W:  64, ITEM_W: 16, NIPC: 1, NUM_PORTS: 3, STALL_PROB: 10, STB_PROB: 100, TEST_REGS: 1 },
+    '{CHDR_W:  64, ITEM_W: 16, NIPC: 1, NUM_PORTS: 2, STALL_PROB: 25, STB_PROB:  80, TEST_REGS: 1 },
+    '{CHDR_W:  64, ITEM_W: 16, NIPC: 2, NUM_PORTS: 1, STALL_PROB: 25, STB_PROB:  80, TEST_REGS: 0 },
+    '{CHDR_W:  64, ITEM_W: 32, NIPC: 1, NUM_PORTS: 1, STALL_PROB: 25, STB_PROB:  80, TEST_REGS: 0 },
+    '{CHDR_W:  64, ITEM_W: 32, NIPC: 2, NUM_PORTS: 1, STALL_PROB: 10, STB_PROB:  80, TEST_REGS: 0 },
+    '{CHDR_W: 128, ITEM_W: 32, NIPC: 1, NUM_PORTS: 3, STALL_PROB: 10, STB_PROB: 100, TEST_REGS: 1 },
+    '{CHDR_W: 128, ITEM_W: 32, NIPC: 1, NUM_PORTS: 2, STALL_PROB: 25, STB_PROB:  80, TEST_REGS: 0 },
+    '{CHDR_W: 128, ITEM_W: 32, NIPC: 2, NUM_PORTS: 1, STALL_PROB: 25, STB_PROB:  80, TEST_REGS: 0 },
+    '{CHDR_W: 128, ITEM_W: 32, NIPC: 4, NUM_PORTS: 1, STALL_PROB: 10, STB_PROB:  80, TEST_REGS: 0 }
+  };
+
+
+  //---------------------------------------------------------------------------
+  // DUT Instances
+  //---------------------------------------------------------------------------
+
+  genvar i;
+  for (i = 0; i < NUM_TESTS; i++) begin : gen_test_config
+    rfnoc_block_radio_tb #(
+      .CHDR_W     (test[i].CHDR_W    ),
+      .ITEM_W     (test[i].ITEM_W    ),
+      .NIPC       (test[i].NIPC      ),
+      .NUM_PORTS  (test[i].NUM_PORTS ),
+      .STALL_PROB (test[i].STALL_PROB),
+      .STB_PROB   (test[i].STB_PROB  ),
+      .TEST_REGS  (test[i].TEST_REGS )
+    ) rfnoc_block_radio_tb_i ();
+  end : gen_test_config
+
+
+endmodule : rfnoc_block_radio_all_tb
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/rfnoc_block_radio_regs.vh b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/rfnoc_block_radio_regs.vh
new file mode 100644
index 000000000..41f9a144e
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/rfnoc_block_radio_regs.vh
@@ -0,0 +1,125 @@
+//
+// Copyright 2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: rfnoc_block_radio_regs (Header)
+//
+// Description: Header file for RFNoC radio functionality. This includes 
+// register offsets, bitfields and constants for the radio components.
+//
+
+
+//-----------------------------------------------------------------------------
+// Shared Register Offsets (One Set Per Radio NoC Block)
+//-----------------------------------------------------------------------------
+
+localparam SHARED_BASE_ADDR = 20'h00;  // Base address for shared radio registers
+localparam SHARED_ADDR_W    = 4;       // Address space size for shared registers
+
+localparam REG_COMPAT_NUM = 'h00;  // Compatibility number register offset
+
+
+//-----------------------------------------------------------------------------
+// Radio Core Register Offsets (One Set Per Radio Port)
+//-----------------------------------------------------------------------------
+//
+// These registers are replicated depending on the number of radio channels 
+// requested. They start at BASE_ADDR_RADIO and repeat every RADIO_ADDR_SPACE 
+// bytes.
+//
+// WARNING: All registers larger than a single 32-bit word must be read and 
+//          written least significant word first to guarantee coherency.
+//
+//-----------------------------------------------------------------------------
+
+localparam RADIO_BASE_ADDR = 20'h1000; // Base address of first radio. Choose a 
+                                       // nice big power of 2 so we can just pass 
+                                       // the lower bits to the radio cores.
+localparam RADIO_ADDR_W    = 7;        // Address space size per radio
+
+// General Radio Registers
+localparam REG_LOOPBACK_EN   = 'h00;   // Loopback enable (connect Tx output to Rx input)
+localparam REG_RADIO_WIDTH   = 'h04;   // Upper 16 bits is sample width, lower 16 bits is NSPC
+
+// RX Control Registers
+localparam REG_RX_STATUS            = 'h10; // Status of Rx radio
+localparam REG_RX_CMD               = 'h14; // The next radio command to execute
+localparam REG_RX_CMD_NUM_WORDS_LO  = 'h18; // Number of radio words for the next command (low word)
+localparam REG_RX_CMD_NUM_WORDS_HI  = 'h1C; // Number of radio words for the next command (high word)
+localparam REG_RX_CMD_TIME_LO       = 'h20; // Time for the next command (low word)
+localparam REG_RX_CMD_TIME_HI       = 'h24; // Time for the next command (high word)
+localparam REG_RX_MAX_WORDS_PER_PKT = 'h28; // Maximum packet length to build from Rx data
+localparam REG_RX_ERR_PORT          = 'h2C; // Port ID for error reporting
+localparam REG_RX_ERR_REM_PORT      = 'h30; // Remote port ID for error reporting
+localparam REG_RX_ERR_REM_EPID      = 'h34; // Remote EPID (endpoint ID) for error reporting
+localparam REG_RX_ERR_ADDR          = 'h38; // Offset to write error code to
+localparam REG_RX_DATA              = 'h3C; // Read the current Rx output of the radio
+localparam REG_RX_HAS_TIME          = 'h70; // Controls whether or not a channel has timestamps
+
+// TX Control Registers
+localparam REG_TX_IDLE_VALUE   = 'h40; // Value to output when transmitter is idle
+localparam REG_TX_ERROR_POLICY = 'h44; // Tx error policy
+localparam REG_TX_ERR_PORT     = 'h48; // Port ID for error reporting
+localparam REG_TX_ERR_REM_PORT = 'h4C; // Remote port ID for error reporting
+localparam REG_TX_ERR_REM_EPID = 'h50; // Remote EPID (endpoint ID) for error reporting
+localparam REG_TX_ERR_ADDR     = 'h54; // Offset to write error code to
+
+
+//-----------------------------------------------------------------------------
+// Register Bit Fields
+//-----------------------------------------------------------------------------
+
+// REG_RX_CMD bit fields
+localparam RX_CMD_POS       = 0;  // Location of the command bit field
+localparam RX_CMD_LEN       = 2;  // Bit length of the command bit field
+localparam RX_CMD_TIMED_POS = 31; // Location of the bit indicating if this is
+                                  // a timed command or not.
+
+// REG_RX_CMD_NUM_WORDS_HI/LO length field
+localparam RX_CMD_NUM_WORDS_LEN = 48; // Number of bits that are used in the 64-bit
+                                      // NUM_WORDS register (must be in range [33:64]).
+
+// REG_RX_STATUS bit fields
+localparam CMD_FIFO_SPACE_POS = 0;  // Indicates if radio is busy executing a command.
+localparam CMD_FIFO_SPACE_LEN = 6;  // Length of the FIFO_SPACE field
+localparam CMD_FIFO_SPACE_MAX = 32; // Size of command FIFO
+
+// REG_TX_ERROR_POLICY bit fields
+localparam TX_ERR_POLICY_LEN  = 2; // Length of error policy bit field
+
+
+//-----------------------------------------------------------------------------
+// Rx Radio Commands
+//-----------------------------------------------------------------------------
+
+localparam [RX_CMD_LEN-1:0] RX_CMD_STOP       = 0; // Stop acquiring at end of next packet
+localparam [RX_CMD_LEN-1:0] RX_CMD_FINITE     = 1; // Acquire NUM_SAMPS then stop
+localparam [RX_CMD_LEN-1:0] RX_CMD_CONTINUOUS = 2; // Acquire until stopped
+
+
+//-----------------------------------------------------------------------------
+// Tx Error Policies
+//-----------------------------------------------------------------------------
+
+localparam TX_ERR_POLICY_PACKET = 1;  // Wait for end of packet after error
+localparam TX_ERR_POLICY_BURST  = 2;  // Wait for end of burst after error
+
+
+//-----------------------------------------------------------------------------
+// Error Codes
+//-----------------------------------------------------------------------------
+
+// Rx Error Codes
+localparam ERR_RX_CODE_W = 2;  // Bit width of error code values
+//
+localparam ERR_RX_LATE_CMD = 1;  // Late command (arrived after indicated time)
+localparam ERR_RX_OVERRUN  = 2;  // FIFO overflow
+
+
+// Tx Error Codes
+localparam ERR_TX_CODE_W = 2;  // Bit width of error code values
+//
+localparam ERR_TX_UNDERRUN  = 1;  // Data underflow (data not available when needed)
+localparam ERR_TX_LATE_DATA = 2;  // Late data (arrived after indicated time)
+localparam ERR_TX_EOB_ACK   = 3;  // Acknowledge end-of-burst (this is not an error)
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/rfnoc_block_radio_tb.sv b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/rfnoc_block_radio_tb.sv
new file mode 100644
index 000000000..706e0f185
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/rfnoc_block_radio_tb.sv
@@ -0,0 +1,1382 @@
+//
+// Copyright 2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: rfnoc_block_radio_tb
+//
+// Description: This is the testbench for rfnoc_block_radio.
+//
+
+
+module rfnoc_block_radio_tb #(
+  parameter int CHDR_W     = 128, // CHDR bus width
+  parameter int ITEM_W     = 32,  // Sample width
+  parameter int NIPC       = 2,   // Number of samples per radio clock cycle
+  parameter int NUM_PORTS  = 2,   // Number of radio channels
+  parameter int STALL_PROB = 25,  // Probability of AXI BFM stall
+  parameter int STB_PROB   = 80,  // Probability of radio STB asserting
+  parameter bit TEST_REGS  = 1    // Do register tests
+);
+
+  // Include macros and time declarations for use with PkgTestExec
+  `include "test_exec.svh"
+
+  import PkgTestExec::*;
+  import PkgChdrUtils::*;
+  import PkgRfnocBlockCtrlBfm::*;
+  import PkgAxisCtrlBfm::*;
+  import PkgChdrBfm::*;
+  import PkgRfnocItemUtils::*;
+
+  // Pull in radio register offsets and constants
+  `include "rfnoc_block_radio_regs.vh"
+
+
+  // Simulation Parameters
+  localparam logic [ 9:0] THIS_PORTID    = 10'h17;
+  localparam logic [15:0] THIS_EPID      = 16'hDEAD;
+  localparam int          MTU            = 8;
+  localparam int          RADIO_W        = NIPC * ITEM_W;       // Radio word size
+  localparam int          SPP            = 64;                  // Samples per packet
+  localparam int          WPP            = SPP*ITEM_W/RADIO_W;  // Radio words per packet
+  localparam int          CHDR_CLK_PER   = 5;                   // rfnoc_chdr_clk period in ns
+  localparam int          CTRL_CLK_PER   = 25;                  // rfnoc_ctrl_clk period in ns
+  localparam int          RADIO_CLK_PER  = 10;                  // radio_clk_per period in ns
+
+  // Amount of time to wait for a packet to be fully acquired
+  localparam realtime MAX_PKT_WAIT = 4*WPP*(RADIO_CLK_PER+CTRL_CLK_PER)*1ns;
+
+  // Error reporting values to use
+  localparam bit [ 9:0] TX_ERR_DST_PORT     = 10'h2B5;
+  localparam bit [ 9:0] TX_ERR_REM_DST_PORT = 10'h14C;
+  localparam bit [15:0] TX_ERR_REM_DST_EPID = 16'hA18E;
+  localparam bit [19:0] TX_ERR_ADDRESS      = 20'hA31D3;
+
+
+
+  //---------------------------------------------------------------------------
+  // Clocks and Resets
+  //---------------------------------------------------------------------------
+
+  bit rfnoc_chdr_clk;
+  bit rfnoc_ctrl_clk;
+  bit radio_clk;
+
+  // Don't start the clocks automatically (AUTOSTART=0), since we expect
+  // multiple instances of this testbench to run in sequence. They will be
+  // started before the first test.
+  sim_clock_gen #(.PERIOD(CHDR_CLK_PER), .AUTOSTART(0))
+    rfnoc_chdr_clk_gen (.clk(rfnoc_chdr_clk), .rst());
+  sim_clock_gen #(.PERIOD(CTRL_CLK_PER), .AUTOSTART(0))
+    rfnoc_ctrl_clk_gen (.clk(rfnoc_ctrl_clk), .rst());
+  sim_clock_gen #(.PERIOD(RADIO_CLK_PER), .AUTOSTART(0)) 
+    radio_clk_gen (.clk(radio_clk), .rst());
+
+
+
+  //---------------------------------------------------------------------------
+  // Bus Functional Models
+  //---------------------------------------------------------------------------
+
+  // Connections to DUT as interfaces:
+  RfnocBackendIf        backend               (rfnoc_chdr_clk, rfnoc_ctrl_clk);
+  AxiStreamIf #(32)     m_ctrl                (rfnoc_ctrl_clk, 1'b0);
+  AxiStreamIf #(32)     s_ctrl                (rfnoc_ctrl_clk, 1'b0);
+  AxiStreamIf #(CHDR_W) m_chdr [NUM_PORTS] (rfnoc_chdr_clk, 1'b0);
+  AxiStreamIf #(CHDR_W) s_chdr [NUM_PORTS] (rfnoc_chdr_clk, 1'b0);
+
+  // Bus functional model for a software block controller
+  RfnocBlockCtrlBfm #(.CHDR_W(CHDR_W)) blk_ctrl;
+
+
+
+  //---------------------------------------------------------------------------
+  // Radio Data Model
+  //---------------------------------------------------------------------------
+
+  bit [NUM_PORTS*RADIO_W-1:0] radio_rx_data;
+  bit [        NUM_PORTS-1:0] radio_rx_stb;
+
+  bit [63:0] radio_time;
+  bit        radio_pps;
+
+  // Radio data generation
+  sim_radio_gen #(
+    .NSPC         (NIPC),
+    .SAMP_W       (ITEM_W),
+    .NUM_CHANNELS (NUM_PORTS),
+    .STB_PROB     (STB_PROB),
+    .INCREMENT    (NIPC),
+    .PPS_PERIOD   (NIPC * 250)
+  ) radio_gen (
+    .radio_clk     (radio_clk),
+    .radio_rst     (1'b0),
+    .radio_rx_data (radio_rx_data),
+    .radio_rx_stb  (radio_rx_stb),
+    .radio_time    (radio_time),
+    .radio_pps     (radio_pps)
+  );
+
+
+
+  //---------------------------------------------------------------------------
+  // DUT
+  //---------------------------------------------------------------------------
+
+  logic [NUM_PORTS-1:0] radio_rx_running;
+
+  logic [NUM_PORTS*RADIO_W-1:0] radio_tx_data;
+  logic [        NUM_PORTS-1:0] radio_tx_stb;
+  logic [        NUM_PORTS-1:0] radio_tx_running;
+
+  logic [NUM_PORTS*CHDR_W-1:0] s_rfnoc_chdr_tdata_flat;
+  logic [       NUM_PORTS-1:0] s_rfnoc_chdr_tlast_flat;
+  logic [       NUM_PORTS-1:0] s_rfnoc_chdr_tvalid_flat;
+  logic [       NUM_PORTS-1:0] s_rfnoc_chdr_tready_flat;
+
+  logic [NUM_PORTS*CHDR_W-1:0] m_rfnoc_chdr_tdata_flat;
+  logic [       NUM_PORTS-1:0] m_rfnoc_chdr_tlast_flat;
+  logic [       NUM_PORTS-1:0] m_rfnoc_chdr_tvalid_flat;
+  logic [       NUM_PORTS-1:0] m_rfnoc_chdr_tready_flat;
+
+  semaphore port_sem = new(0);
+
+  // Use the same strobe for both Rx and Tx
+  assign radio_tx_stb = radio_rx_stb;
+
+
+  // Flatten the data stream arrays into concatenated vectors
+  genvar i;
+  for (i = 0; i < NUM_PORTS; i++) begin : gen_radio_connections
+    assign s_rfnoc_chdr_tdata_flat[CHDR_W*i+:CHDR_W] = m_chdr[i].tdata;
+    assign s_rfnoc_chdr_tlast_flat[i]                = m_chdr[i].tlast;
+    assign s_rfnoc_chdr_tvalid_flat[i]               = m_chdr[i].tvalid;
+    assign m_chdr[i].tready                          = s_rfnoc_chdr_tready_flat[i];
+
+    assign s_chdr[i].tdata             = m_rfnoc_chdr_tdata_flat[CHDR_W*i+:CHDR_W];
+    assign s_chdr[i].tlast             = m_rfnoc_chdr_tlast_flat[i];
+    assign s_chdr[i].tvalid            = m_rfnoc_chdr_tvalid_flat[i];
+    assign m_rfnoc_chdr_tready_flat[i] = s_chdr[i].tready;
+
+    // Connect each interface to the BFM. This is done in a generate block 
+    // since the interface indices must be constant in SystemVerilog :(
+    initial begin
+      // Get the port number (plus 1) from the semaphore. This will block until 
+      // the semaphore is incremented to this port number (plus 1).
+      port_sem.get(i+1);
+      // Connect the master and slave interfaces to the BFM
+      void'(blk_ctrl.add_master_data_port(m_chdr[i]));
+      void'(blk_ctrl.add_slave_data_port(s_chdr[i]));
+      // Put the port number to communicate that we're done
+      port_sem.put(i+1);
+    end
+  end
+
+
+  rfnoc_block_radio #(
+    .THIS_PORTID (THIS_PORTID),
+    .CHDR_W      (CHDR_W),
+    .NIPC        (NIPC),
+    .ITEM_W      (ITEM_W),
+    .NUM_PORTS   (NUM_PORTS),
+    .MTU         (MTU)
+  ) rfnoc_block_radio_i (
+    .rfnoc_chdr_clk          (backend.chdr_clk),
+    .s_rfnoc_chdr_tdata      (s_rfnoc_chdr_tdata_flat),
+    .s_rfnoc_chdr_tlast      (s_rfnoc_chdr_tlast_flat),
+    .s_rfnoc_chdr_tvalid     (s_rfnoc_chdr_tvalid_flat),
+    .s_rfnoc_chdr_tready     (s_rfnoc_chdr_tready_flat),
+    .m_rfnoc_chdr_tdata      (m_rfnoc_chdr_tdata_flat),
+    .m_rfnoc_chdr_tlast      (m_rfnoc_chdr_tlast_flat),
+    .m_rfnoc_chdr_tvalid     (m_rfnoc_chdr_tvalid_flat),
+    .m_rfnoc_chdr_tready     (m_rfnoc_chdr_tready_flat),
+    .rfnoc_core_config       (backend.cfg),
+    .rfnoc_core_status       (backend.sts),
+    .rfnoc_ctrl_clk          (backend.ctrl_clk),
+    .s_rfnoc_ctrl_tdata      (m_ctrl.tdata),
+    .s_rfnoc_ctrl_tlast      (m_ctrl.tlast),
+    .s_rfnoc_ctrl_tvalid     (m_ctrl.tvalid),
+    .s_rfnoc_ctrl_tready     (m_ctrl.tready),
+    .m_rfnoc_ctrl_tdata      (s_ctrl.tdata),
+    .m_rfnoc_ctrl_tlast      (s_ctrl.tlast),
+    .m_rfnoc_ctrl_tvalid     (s_ctrl.tvalid),
+    .m_rfnoc_ctrl_tready     (s_ctrl.tready),
+    .m_ctrlport_req_wr       (),
+    .m_ctrlport_req_rd       (),
+    .m_ctrlport_req_addr     (),
+    .m_ctrlport_req_data     (),
+    .m_ctrlport_req_byte_en  (),
+    .m_ctrlport_req_has_time (),
+    .m_ctrlport_req_time     (),
+    .m_ctrlport_resp_ack     (1'b0),
+    .m_ctrlport_resp_status  (2'b0),
+    .m_ctrlport_resp_data    (32'b0),
+    .radio_clk               (radio_clk),
+    .radio_time              (radio_time),
+    .radio_rx_data           (radio_rx_data),
+    .radio_rx_stb            (radio_rx_stb),
+    .radio_rx_running        (radio_rx_running),
+    .radio_tx_data           (radio_tx_data),
+    .radio_tx_stb            (radio_tx_stb),
+    .radio_tx_running        (radio_tx_running)
+  );
+
+
+
+  //---------------------------------------------------------------------------
+  // Helper Tasks
+  //---------------------------------------------------------------------------
+
+  // Read a 32-bit register at offset "addr" from shared radio registers
+  task automatic read_shared(logic [19:0] addr, output logic [31:0] data);
+    addr = addr + SHARED_BASE_ADDR;
+    blk_ctrl.reg_read(addr, data);
+  endtask : read_shared
+
+  // Write a 32-bit register at offset "addr" in shared radio registers
+  task automatic write_shared(logic [19:0] addr, logic [31:0] data);
+    addr = addr + SHARED_BASE_ADDR;
+    blk_ctrl.reg_write(addr, data);
+  endtask : write_shared
+
+  // Read a 32-bit register at offset "addr" from radio "radio_num"
+  task automatic read_radio(int radio_num, logic [19:0] addr, output logic [31:0] data);
+    addr = addr + RADIO_BASE_ADDR + (radio_num * 2**RADIO_ADDR_W);
+    blk_ctrl.reg_read(addr, data);
+  endtask : read_radio
+
+  // Read a 64-bit register at offset "addr" from radio "radio_num"
+  task automatic read_radio_64(int radio_num, logic [19:0] addr, output logic [63:0] data);
+    addr = addr + RADIO_BASE_ADDR + (radio_num * 2**RADIO_ADDR_W);
+    blk_ctrl.reg_read(addr,   data[31:0]);
+    blk_ctrl.reg_read(addr+4, data[63:32]);
+  endtask : read_radio_64
+
+  // Write a 32-bit register at offset "addr" in radio "radio_num"
+  task automatic write_radio(int radio_num, logic [19:0] addr, logic [31:0] data);
+    addr = addr + RADIO_BASE_ADDR + (radio_num * 2**RADIO_ADDR_W);
+    blk_ctrl.reg_write(addr, data);
+  endtask : write_radio
+
+  // Write a 64-bit register at offset "addr" in radio "radio_num"
+  task automatic write_radio_64(int radio_num, logic [19:0] addr, logic [63:0] data);
+    addr = addr + RADIO_BASE_ADDR + (radio_num * 2**RADIO_ADDR_W);
+    blk_ctrl.reg_write(addr,   data[31:0]);
+    blk_ctrl.reg_write(addr+4, data[63:32]);
+  endtask : write_radio_64
+
+
+  // Start an Rx acquisition
+  task automatic start_rx (
+    int        radio_num,     // Radio channel to use
+    bit [63:0] num_words = 0  // Number of radio words
+  );
+    logic [31:0] cmd;
+
+    if (num_words == 0) begin
+      // Do a continuous acquisition
+      $display("Radio %0d: Start RX, continuous receive", radio_num);
+      cmd = RX_CMD_CONTINUOUS;
+    end else begin
+      // Do a finite acquisition (num samps and done)
+      $display("Radio %0d: Start RX, receive %0d words", radio_num, num_words);
+      write_radio_64(radio_num, REG_RX_CMD_NUM_WORDS_LO, num_words);
+      cmd = RX_CMD_FINITE;
+    end
+
+    // Write command to radio
+    write_radio(radio_num, REG_RX_CMD, cmd);
+  endtask : start_rx
+
+
+  // Start an Rx acquisition at a specific time
+  task automatic start_rx_timed (
+    int        radio_num,      // Radio channel to use
+    bit [63:0] num_words = 0,  // Number of radio words
+    bit [63:0] start_time
+  );
+    logic [31:0] cmd;
+
+    if (num_words == 0) begin
+      // Do a continuous acquisition
+      $display("Radio %0d: Start RX, continuous receive (timed)", radio_num);
+      cmd = RX_CMD_CONTINUOUS;
+    end else begin
+      // Do a finite acquisition (num samps and done)
+      $display("Radio %0d: Start RX, receive %0d words (timed)", radio_num, num_words);
+      write_radio_64(radio_num, REG_RX_CMD_NUM_WORDS_LO, num_words);
+      cmd = RX_CMD_FINITE;
+    end
+
+    // Mark that this is a timed command
+    cmd[RX_CMD_TIMED_POS] = 1'b1;
+
+    // Set start time for command
+    write_radio_64(radio_num, REG_RX_CMD_TIME_LO, start_time);
+
+    // Write command to radio
+    write_radio(radio_num, REG_RX_CMD, cmd);
+  endtask : start_rx_timed
+
+
+  // Send the Rx stop command to the indicated radio channel
+  task automatic stop_rx(int radio_num);
+    $display("Radio %0d: Stop RX", radio_num);
+    write_radio(radio_num, REG_RX_CMD, RX_CMD_STOP);
+  endtask : stop_rx
+
+
+  // Receive num_words from the indicated radio channel and verify that it's 
+  // sequential and contiguous data aligned on packet boundaries.
+  task automatic check_rx(
+    int radio_num,    // Radio to receive from and check
+    int num_words     // Number of radio words to expect
+  );
+    int              sample_count;    // Counter to track number of samples generated
+    bit [ITEM_W-1:0] sample_val;      // Value of the next sample
+    chdr_word_t      data[$];         // Array of data for the received packet
+    int              num_samples;     // Number of samples to send
+    int              byte_length;     // Number of data bytes in next packet
+    int              expected_length; // Expected byte length of the next packet
+    int              valid_words;     // Number of valid chdr_word_t in next packet
+
+    num_samples = num_words * NIPC;
+
+    sample_count = 0;
+    while (sample_count < num_samples) begin
+      // Fetch the next packet
+      blk_ctrl.recv(radio_num, data, byte_length);
+
+      // Take the first sample as a starting count for the remaining samples
+      if (sample_count == 0) begin
+        sample_val = data[0][ITEM_W-1:0];
+      end
+
+      // Calculate expected length in bytes
+      if (num_samples - sample_count >= SPP) begin
+        // Expecting a full packet
+        expected_length = SPP*ITEM_W/8;
+      end else begin
+        // Expecting partial packet
+        expected_length = (num_samples - sample_count) * ITEM_W/8;
+      end
+
+      // Check that the length matches our expectation
+      `ASSERT_ERROR(
+        byte_length == expected_length,
+        "Received packet didn't have expected length."
+      );
+
+      // Loop over the packet, one chdr_word_t at a time
+      valid_words = int'($ceil(real'(byte_length) / ($bits(chdr_word_t)/8)));
+      for (int i = 0; i < valid_words; i++) begin
+        // Check each sample of the next chdr_word_t value
+        for (int sub_sample = 0; sub_sample < $bits(chdr_word_t)/ITEM_W; sub_sample++) begin
+          chdr_word_t word;
+          word = data[i][ITEM_W*sub_sample +: ITEM_W];  // Work around Vivado 2018.3 issue
+          `ASSERT_ERROR(
+            word == sample_val,
+            $sformatf(
+              "Sample %0d (0x%X) didn't match expected value (0x%X)",
+              sample_count, data[i][ITEM_W*sub_sample +: ITEM_W],  sample_val
+            )
+          );
+          sample_val++;
+          sample_count++;
+
+          // Check if the word is only partially full
+          if (sample_count >= num_samples) break;
+        end
+      end
+    end
+  endtask : check_rx
+
+
+  // Send num_words to the indicated radio for transmission at the given time.
+  task automatic start_tx_timed (
+    int                radio_num,       // Radio channel to transmit on
+    bit   [63:0]       num_words,       // Number of radio words to transmit
+    logic [63:0]       start_time = 'X, // Time at which to begin transmit
+    bit   [ITEM_W-1:0] start_val  = 1,  // Initial sample value
+    bit                eob        = 1   // Set EOB flag at the end
+  );
+    int              sample_count;    // Counter to track number of samples generated
+    bit [ITEM_W-1:0] sample_val;      // Value of the next sample
+    chdr_word_t      data[$];         // Array of data for the packet
+    int              num_samples;     // Number of samples to send
+    int              byte_length;     // Number of bytes for next packet
+    chdr_word_t      chdr_word;       // Next word to send to BFM
+    packet_info_t    pkt_info = 0;    // Flags/timestamp for next packet
+
+    $display("Radio %0d: Start TX, send %0d words", radio_num, num_words);
+
+    num_samples = num_words * NIPC;
+
+    if (!$isunknown(start_time)) pkt_info.has_time = 1;
+
+    sample_val   = start_val;
+    sample_count = 0;
+    while (sample_count < num_samples) begin
+      // Calculate timestamp for this packet
+      if (pkt_info.has_time) begin
+        pkt_info.timestamp = start_time + sample_count;
+      end
+
+      // Clear the payload
+      data = {};
+
+      // Loop until we've built up a packet
+      forever begin
+        // Generate the next word
+        for (int sub_sample = 0; sub_sample < $bits(chdr_word_t)/ITEM_W; sub_sample++) begin
+          chdr_word[ITEM_W*sub_sample +: ITEM_W] = sample_val;
+          sample_val++;
+          sample_count++;
+        end
+
+        // Add next word to the queue
+        data.push_back(chdr_word);
+
+        // Send the packet if we're at a packet boundary
+        if (sample_count % SPP == 0) begin
+          pkt_info.eob = (sample_count == num_samples && eob) ? 1 : 0;
+          byte_length = SPP * ITEM_W/8;
+          blk_ctrl.send(radio_num, data, byte_length, {}, pkt_info);
+          break;
+        end else if (sample_count >= num_samples) begin
+          pkt_info.eob = eob;
+          byte_length = (sample_count % SPP) * ITEM_W/8;
+          blk_ctrl.send(radio_num, data, byte_length, {}, pkt_info);
+          break;
+        end
+      end
+    end
+  endtask : start_tx_timed
+
+
+  // Send num_words to the indicated radio for transmission.
+  task automatic start_tx (
+    int              radio_num,       // Radio channel to transmit on
+    bit [63:0]       num_words,       // Number of radio words to transmit
+    bit [ITEM_W-1:0] start_val = 1,   // Initial sample value
+    bit              eob = 1          // Set EOB flag at the end
+  );
+    // Passing 'X tells the underlying BFM to not insert a timestamp
+    start_tx_timed(radio_num, num_words, 'X, start_val, eob);
+  endtask : start_tx
+
+
+  // Verify the output of a packet, expecting it at a specific time
+  task automatic check_tx_timed (
+    int                radio_num,        // Radio channel to transmit on
+    bit   [63:0]       num_words,        // Number of radio words to expect
+    logic [63:0]       start_time = 'X,  // Expected start time
+    bit   [ITEM_W-1:0] start_val  = 1    // Initial sample value
+  );
+    int sample_val;           // Expected value of next sample
+
+    sample_val = start_val;
+
+    // Wait for the packet to start
+    wait(radio_tx_data[radio_num*RADIO_W +: ITEM_W] == start_val);
+
+    // Check the time
+    if (!$isunknown(start_time)) begin
+      `ASSERT_ERROR(
+        radio_time - start_time <= NIPC*2,
+        $sformatf("Packet transmitted at radio time 0x%0X but expected 0x%0X", radio_time, start_time)
+      );
+    end
+
+    // Verify output one word at a time
+    for (int word_count = 0; word_count < num_words; word_count++) begin
+      // Wait for the next radio word to be output
+      do begin
+        @(posedge radio_clk);
+      end while (radio_tx_stb[radio_num] == 0);
+
+      // Check each sample of the radio word
+      for (int sub_sample = 0; sub_sample < NIPC; sub_sample++) begin
+        `ASSERT_ERROR(
+          radio_tx_data[radio_num*RADIO_W + ITEM_W*sub_sample +: ITEM_W] == sample_val,
+          "Radio output doesn't match expected value"
+        );
+        sample_val++;
+      end
+    end
+  endtask : check_tx_timed
+
+
+  // Verify the output of a packet
+  task automatic check_tx (
+    int              radio_num,        // Radio to transmit on
+    bit [63:0]       num_words,        // Number of radio words to expect
+    bit [ITEM_W-1:0] start_val  = 1    // Initial sample value
+  );
+    check_tx_timed(radio_num, num_words, 'X, start_val);
+  endtask : check_tx
+
+
+  // When we expect and error, this task will check that control packets were
+  // received and that they have the expected values.
+  task check_error (int error);
+    AxisCtrlPacket ctrl_packet;
+    chdr_word_t word;
+
+    // Get error code
+    blk_ctrl.get_ctrl_bfm().get_ctrl(ctrl_packet);
+    word = ctrl_packet.data[0];   // Work around Vivado 2018.3 issue
+    `ASSERT_ERROR(
+      word                            == error &&
+      ctrl_packet.op_word.op_code     == CTRL_OP_WRITE &&
+      ctrl_packet.op_word.address     == TX_ERR_ADDRESS &&
+      ctrl_packet.header.is_ack       == 1'b0 &&
+      ctrl_packet.header.has_time     == 1'b1 &&
+      ctrl_packet.header.num_data     == 1 &&
+      ctrl_packet.header.dst_port     == TX_ERR_DST_PORT &&
+      ctrl_packet.header.rem_dst_port == TX_ERR_REM_DST_PORT &&
+      ctrl_packet.header.rem_dst_epid == TX_ERR_REM_DST_EPID,
+      "Unexpected error code response");
+
+    // Send acknowledgment
+    ctrl_packet.header = 0;
+    ctrl_packet.header.is_ack = 1;
+    blk_ctrl.get_ctrl_bfm().put_ctrl(ctrl_packet);
+  endtask : check_error
+
+
+
+  //---------------------------------------------------------------------------
+  // Test Procedures
+  //---------------------------------------------------------------------------
+
+  task automatic test_block_info();
+    test.start_test("Verify Block Info", 2us);
+
+    // Get static block info and validate it
+    `ASSERT_ERROR(blk_ctrl.get_noc_id() == rfnoc_block_radio_i.NOC_ID, "Incorrect noc_id Value");
+    `ASSERT_ERROR(blk_ctrl.get_num_data_i() == NUM_PORTS, "Incorrect num_data_i Value");
+    `ASSERT_ERROR(blk_ctrl.get_num_data_o() == NUM_PORTS, "Incorrect num_data_o Value");
+    `ASSERT_ERROR(blk_ctrl.get_ctrl_fifosize() == rfnoc_block_radio_i.noc_shell_radio_i.CTRL_FIFO_SIZE,
+      "Incorrect ctrl_fifosize Value");
+    `ASSERT_ERROR(blk_ctrl.get_mtu() == MTU, "Incorrect mtu Value");
+
+    test.end_test();
+  endtask : test_block_info
+
+
+
+  task automatic test_shared_registers();
+    logic [31:0] val;
+    test.start_test("Shared Registers", 10us);
+
+    // Compatibility number
+    read_shared(REG_COMPAT_NUM, val);
+    `ASSERT_ERROR(
+      val == {
+        rfnoc_block_radio_i.compat_major,
+        rfnoc_block_radio_i.compat_minor
+      },
+      "REG_COMPAT_NUM didn't read correctly"
+    );
+    test.end_test();
+  endtask : test_shared_registers
+
+
+
+  task automatic test_general_registers(int radio_num);
+    logic [31:0] val;
+    test.start_test("General Registers", 10us);
+
+    // Test loopback enable register (read/write)
+    read_radio(radio_num, REG_LOOPBACK_EN, val);
+    `ASSERT_ERROR(val == 0, "Initial value of REG_LOOPBACK_EN is incorrect");
+    write_radio(radio_num, REG_LOOPBACK_EN, 32'hFFFFFFFF);
+    read_radio(radio_num, REG_LOOPBACK_EN, val);
+    `ASSERT_ERROR(val == 1, "REG_LOOPBACK_EN didn't update correctly");
+    write_radio(radio_num, REG_LOOPBACK_EN, 0);
+
+    // Read ITEM_W and NIPC (read only)
+    read_radio(radio_num, REG_RADIO_WIDTH, val);
+    `ASSERT_ERROR(val[15:0] == NIPC, "Value of NIPC register is incorrect");
+    `ASSERT_ERROR(val[31:16] == ITEM_W, "Value of ITEM_W register is incorrect");
+
+    test.end_test();
+  endtask : test_general_registers
+
+
+
+  task test_rx_registers(int radio_num);
+    logic [63:0] val, temp, expected;
+    localparam int num_words_len = RX_CMD_NUM_WORDS_LEN;
+
+    test.start_test("Rx Registers", 50us);
+
+    // REG_RX_CMD_STATUS (read only)
+    expected = CMD_FIFO_SPACE_MAX;
+    read_radio(radio_num, REG_RX_STATUS, val);
+    `ASSERT_ERROR(val == expected, "REG_RX_STATUS not initially CMD_FIFO_SPACE_MAX");
+
+    // REG_RX_CMD (read/write). Test a bogus timed stop command just to check 
+    // read/write of the register.
+    expected = 0;
+    expected[RX_CMD_POS +: RX_CMD_LEN] = RX_CMD_STOP;
+    expected[RX_CMD_TIMED_POS] = 1'b1;
+    write_radio(radio_num, REG_RX_CMD, expected);
+    read_radio(radio_num, REG_RX_CMD, val);
+    `ASSERT_ERROR(val == expected, "REG_RX_CMD didn't update correctly");
+
+    // REG_RX_CMD_NUM_WORDS (read/write)
+    read_radio_64(radio_num, REG_RX_CMD_NUM_WORDS_LO, val);
+    `ASSERT_ERROR(val == 0, "REG_RX_CMD_NUM_WORDS not initially 0");
+    expected = 64'hFEDCBA9876543210;
+    write_radio_64(radio_num, REG_RX_CMD_NUM_WORDS_LO, expected);
+    read_radio_64(radio_num, REG_RX_CMD_NUM_WORDS_LO, val);
+    `ASSERT_ERROR(
+      val == expected[num_words_len-1:0],
+     "REG_RX_CMD_NUM_WORDS didn't update correctly"
+    );
+
+    // REG_RX_CMD_TIME (read/write)
+    read_radio_64(radio_num, REG_RX_CMD_TIME_LO, val);
+    `ASSERT_ERROR(val == 0, "REG_RX_CMD_TIME not initially 0");
+    expected = 64'hBEADFEED0123F1FE;
+    write_radio_64(radio_num, REG_RX_CMD_TIME_LO, expected);
+    read_radio_64(radio_num, REG_RX_CMD_TIME_LO, val);
+    `ASSERT_ERROR(val == expected, "REG_RX_CMD_TIME didn't update correctly");
+
+    // REG_RX_MAX_WORDS_PER_PKT (read/write)
+    read_radio(radio_num, REG_RX_MAX_WORDS_PER_PKT, val);
+    `ASSERT_ERROR(val == 64, "REG_RX_MAX_WORDS_PER_PKT not initially 64");
+    expected = 32'hABBEC001;
+    write_radio(radio_num, REG_RX_MAX_WORDS_PER_PKT, expected);
+    read_radio(radio_num, REG_RX_MAX_WORDS_PER_PKT, val);
+    `ASSERT_ERROR(val == expected, "REG_RX_MAX_WORDS_PER_PKT didn't update correctly");
+
+    // REG_RX_ERR_PORT (read/write)
+    read_radio(radio_num, REG_RX_ERR_PORT, val);
+    `ASSERT_ERROR(val == 0, "REG_RX_ERR_PORT not initially 0");
+    expected = $urandom() & 32'h000001FF;
+    write_radio(radio_num, REG_RX_ERR_PORT, expected);
+    read_radio(radio_num, REG_RX_ERR_PORT, val);
+    `ASSERT_ERROR(val == expected, "REG_RX_ERR_PORT didn't update correctly");
+
+    // REG_RX_ERR_REM_PORT (read/write)
+    read_radio(radio_num, REG_RX_ERR_REM_PORT, val);
+    `ASSERT_ERROR(val == 0, "REG_RX_ERR_REM_PORT not initially 0");
+    expected = $urandom() & 32'h000001FF;
+    write_radio(radio_num, REG_RX_ERR_REM_PORT, expected);
+    read_radio(radio_num, REG_RX_ERR_REM_PORT, val);
+    `ASSERT_ERROR(val == expected, "REG_RX_ERR_REM_PORT didn't update correctly");
+
+    // REG_RX_ERR_REM_EPID (read/write)
+    read_radio(radio_num, REG_RX_ERR_REM_EPID, val);
+    `ASSERT_ERROR(val == 0, "REG_RX_ERR_REM_EPID not initially 0");
+    expected = $urandom() & 32'h0000FFFF;
+    write_radio(radio_num, REG_RX_ERR_REM_EPID, expected);
+    read_radio(radio_num, REG_RX_ERR_REM_EPID, val);
+    `ASSERT_ERROR(val == expected, "REG_RX_ERR_REM_EPID didn't update correctly");
+
+    // REG_RX_ERR_ADDR (read/write)
+    read_radio(radio_num, REG_RX_ERR_ADDR, val);
+    `ASSERT_ERROR(val == 0, "REG_RX_ERR_ADDR not initially 0");
+    expected = $urandom() & 32'h000FFFFF;
+    write_radio(radio_num, REG_RX_ERR_ADDR, expected);
+    read_radio(radio_num, REG_RX_ERR_ADDR, val);
+    `ASSERT_ERROR(val == expected, "REG_RX_ERR_ADDR didn't update correctly");
+
+    // REG_RX_DATA (read-only)
+    temp = radio_tx_data[RADIO_W*radio_num +: RADIO_W];
+    read_radio(radio_num, REG_RX_DATA, val);
+    `ASSERT_ERROR(
+      radio_rx_data[RADIO_W*radio_num +: RADIO_W] >= val && val >= temp, 
+      "REG_RX_DATA wasn't in the expected range");
+    read_radio(radio_num, REG_RX_DATA, temp);
+    `ASSERT_ERROR(temp != val, "REG_RX_DATA didn't update");
+
+    test.end_test();
+  endtask : test_rx_registers
+
+
+
+  task automatic test_tx_registers(int radio_num);
+    logic [31:0] val, expected;
+
+    test.start_test("Tx Registers", 50us);
+
+    // REG_TX_IDLE_VALUE (read/write)
+    read_radio(radio_num, REG_TX_IDLE_VALUE, val);
+    `ASSERT_ERROR(val == 0, "REG_TX_IDLE_VALUE not initially 0");
+    expected = $urandom() & {ITEM_W{1'b1}};
+    write_radio(radio_num, REG_TX_IDLE_VALUE, expected);
+    read_radio(radio_num, REG_TX_IDLE_VALUE, val);
+    `ASSERT_ERROR(val == expected, "REG_TX_IDLE_VALUE didn't update correctly");
+
+    // REG_TX_ERROR_POLICY (read/write)
+    read_radio(radio_num, REG_TX_ERROR_POLICY, val);
+    expected = TX_ERR_POLICY_PACKET;
+    `ASSERT_ERROR(val == expected, "REG_TX_ERROR_POLICY not initially 'PACKET'");
+    expected = TX_ERR_POLICY_BURST;
+    write_radio(radio_num, REG_TX_ERROR_POLICY, expected);
+    read_radio(radio_num, REG_TX_ERROR_POLICY, val);
+    `ASSERT_ERROR(val == expected, "REG_TX_ERROR_POLICY didn't update to 'BURST'");
+    expected = TX_ERR_POLICY_PACKET;
+    write_radio(radio_num, REG_TX_ERROR_POLICY, 32'h03); // Try to set both bits!
+    read_radio(radio_num, REG_TX_ERROR_POLICY, val);
+    `ASSERT_ERROR(val == expected, "REG_TX_ERROR_POLICY didn't revert to 'PACKET'");
+
+    // REG_TX_ERR_PORT (read/write)
+    read_radio(radio_num, REG_TX_ERR_PORT, val);
+    `ASSERT_ERROR(val == 0, "REG_TX_ERR_PORT not initially 0");
+    expected = $urandom() & 32'h000001FF;
+    write_radio(radio_num, REG_TX_ERR_PORT, expected);
+    read_radio(radio_num, REG_TX_ERR_PORT, val);
+    `ASSERT_ERROR(val == expected, "REG_TX_ERR_PORT didn't update correctly");
+
+    // REG_TX_ERR_REM_PORT (read/write)
+    read_radio(radio_num, REG_TX_ERR_REM_PORT, val);
+    `ASSERT_ERROR(val == 0, "REG_TX_ERR_REM_PORT not initially 0");
+    expected = $urandom() & 32'h000001FF;
+    write_radio(radio_num, REG_TX_ERR_REM_PORT, expected);
+    read_radio(radio_num, REG_TX_ERR_REM_PORT, val);
+    `ASSERT_ERROR(val == expected, "REG_TX_ERR_REM_PORT didn't update correctly");
+
+    // REG_TX_ERR_REM_EPID (read/write)
+    read_radio(radio_num, REG_TX_ERR_REM_EPID, val);
+    `ASSERT_ERROR(val == 0, "REG_TX_ERR_REM_EPID not initially 0");
+    expected = $urandom() & 32'h0000FFFF;
+    write_radio(radio_num, REG_TX_ERR_REM_EPID, expected);
+    read_radio(radio_num, REG_TX_ERR_REM_EPID, val);
+    `ASSERT_ERROR(val == expected, "REG_TX_ERR_REM_EPID didn't update correctly");
+
+    // REG_TX_ERR_ADDR (read/write)
+    read_radio(radio_num, REG_TX_ERR_ADDR, val);
+    `ASSERT_ERROR(val == 0, "REG_TX_ERR_ADDR not initially 0");
+    expected = $urandom() & 32'h000FFFFF;
+    write_radio(radio_num, REG_TX_ERR_ADDR, expected);
+    read_radio(radio_num, REG_TX_ERR_ADDR, val);
+    `ASSERT_ERROR(val == expected, "REG_TX_ERR_ADDR didn't update correctly");
+
+    test.end_test();
+  endtask : test_tx_registers
+
+
+
+  task automatic test_rx(int radio_num);
+
+    //---------------------
+    // Finite Acquisitions
+    //---------------------
+
+    test.start_test("Rx (finite)", 50us);
+
+    // Set packet length
+    write_radio(radio_num, REG_RX_MAX_WORDS_PER_PKT, WPP);
+
+    // Grab and verify a partial packet
+    start_rx(radio_num, WPP/2);
+    check_rx(radio_num, WPP/2);
+
+    // Grab a minimally-sized packet
+    start_rx(radio_num, 1);
+    check_rx(radio_num, 1);
+
+    // Grab and verify several packets
+    start_rx(radio_num, WPP*15/2);
+    check_rx(radio_num, WPP*15/2);
+
+    // Wait long enough to receive another packet and then make sure we didn't 
+    // receive anything. That is, make sure Rx actually stopped.
+    #MAX_PKT_WAIT;
+    `ASSERT_ERROR(
+      blk_ctrl.num_received(radio_num) == 0,
+      "Received more packets than expected"
+    );
+
+    test.end_test();
+
+
+    //-------------------------
+    // Continuous Acquisitions
+    //-------------------------
+
+    test.start_test("Rx (continuous)", 100us);
+
+    start_rx(radio_num);
+
+    // Grab and verify several packets
+    check_rx(radio_num, WPP*7);
+    stop_rx(radio_num);
+
+    // Grab and discard any remaining packets
+    do begin
+      while (blk_ctrl.num_received(radio_num) != 0) begin
+        ChdrPacket #(CHDR_W) chdr_packet;
+        blk_ctrl.get_chdr(radio_num, chdr_packet);
+      end
+      #MAX_PKT_WAIT;
+    end while (blk_ctrl.num_received(radio_num) != 0);
+
+    test.end_test();
+
+
+    //--------------------------
+    // Finite Timed Acquisition
+    //--------------------------
+
+    begin
+      ChdrPacket #(CHDR_W) chdr_packet;
+      chdr_word_t expected_time;
+
+      test.start_test("Rx (finite, timed)", 100us);
+
+      // Send Rx command with time in the future
+      expected_time = radio_time + 2000;
+      start_rx_timed(radio_num, WPP, expected_time);
+
+      // Take a peak at the timestamp in the received packet to check it
+      blk_ctrl.peek_chdr(radio_num, chdr_packet);
+      `ASSERT_ERROR(
+        chdr_packet.timestamp == expected_time,
+        "Received packet didn't have expected timestamp"
+      );
+
+      // Verify the packet data
+      check_rx(radio_num, WPP);
+      test.end_test();
+    end
+
+
+    //------------------------------
+    // Continuous Timed Acquisition
+    //------------------------------
+
+    begin
+      ChdrPacket #(CHDR_W) chdr_packet;
+      chdr_word_t expected_time;
+
+      test.start_test("Rx (continuous, timed)", 100us);
+
+      // Send Rx command with time in the future
+      expected_time = radio_time + 2000;
+      start_rx_timed(radio_num, 0, expected_time);
+
+      // Take a peak at the timestamp in the received packet to check it
+      blk_ctrl.peek_chdr(radio_num, chdr_packet);
+      `ASSERT_ERROR(
+        chdr_packet.timestamp == expected_time,
+        "Received packet didn't have expected timestamp"
+      );
+
+      // Verify a few packets
+      check_rx(radio_num, WPP*3);
+      stop_rx(radio_num);
+
+      // Grab and discard any remaining packets
+      do begin
+        while (blk_ctrl.num_received(radio_num) != 0) begin
+          ChdrPacket #(CHDR_W) chdr_packet;
+          blk_ctrl.get_chdr(radio_num, chdr_packet);
+        end
+        #(MAX_PKT_WAIT);
+      end while (blk_ctrl.num_received(radio_num) != 0);
+
+      test.end_test();
+    end
+
+
+    //-------------
+    // Rx Overflow
+    //-------------
+    begin
+      logic [31:0] val;
+
+      test.start_test("Rx (now, overflow)", 200us);
+
+      // Configure the error reporting registers
+      write_radio(radio_num, REG_RX_ERR_PORT, TX_ERR_DST_PORT);
+      write_radio(radio_num, REG_RX_ERR_REM_PORT, TX_ERR_REM_DST_PORT);
+      write_radio(radio_num, REG_RX_ERR_REM_EPID, TX_ERR_REM_DST_EPID);
+      write_radio(radio_num, REG_RX_ERR_ADDR, TX_ERR_ADDRESS);
+
+      // Stall the BFM to force a backup of data
+      blk_ctrl.set_slave_stall_prob(radio_num, 100);
+
+      // Acquire continuously until we get an error
+      start_rx(radio_num);
+
+      // Check that we're acquiring
+      read_radio(radio_num, REG_RX_STATUS, val);
+      `ASSERT_ERROR(
+        val[CMD_FIFO_SPACE_POS +: CMD_FIFO_SPACE_LEN] != CMD_FIFO_SPACE_MAX,
+        "Rx radio reports that it is not busy"
+      );
+
+      // Verify that we receive an error
+      check_error(ERR_RX_OVERRUN);
+
+      // Restore the BFM stall probability
+      blk_ctrl.set_slave_stall_prob(radio_num, STALL_PROB);
+
+      // Verify that Rx stopped
+      read_radio(radio_num, REG_RX_STATUS, val);
+      `ASSERT_ERROR(
+        val[CMD_FIFO_SPACE_POS +: CMD_FIFO_SPACE_LEN] == CMD_FIFO_SPACE_MAX,
+        "Rx radio reports that it is still busy after overflow"
+      );
+
+      // Discard any packets we received. Rx should eventually stop 
+      // automatically after an overflow.
+      do begin
+        while (blk_ctrl.num_received(radio_num) != 0) begin
+          ChdrPacket #(CHDR_W) chdr_packet;
+          blk_ctrl.get_chdr(radio_num, chdr_packet);
+        end
+        #(MAX_PKT_WAIT);
+      end while (blk_ctrl.num_received(radio_num) != 0);
+
+     test.end_test();
+    end
+
+
+    //--------------
+    // Late Command
+    //--------------
+
+    test.start_test("Rx (timed, late)", 100us);
+
+    start_rx_timed(radio_num, WPP, radio_time);
+    check_error(ERR_RX_LATE_CMD);
+
+    // Late command should be ignored. Make sure we didn't receive any packets.
+    begin
+      ChdrPacket #(CHDR_W) chdr_packet;
+      #(MAX_PKT_WAIT);
+      `ASSERT_ERROR(
+        blk_ctrl.num_received(radio_num) == 0,
+        "Packets received for late Rx command"
+      );
+
+      // Discard any remaining packets
+      while (blk_ctrl.num_received(radio_num)) blk_ctrl.get_chdr(radio_num, chdr_packet);
+    end
+
+    test.end_test();
+
+
+    //---------------
+    // Command Queue
+    //---------------
+
+    test.start_test("Rx (queue multiple commands)");
+
+    begin
+      logic [31:0] expected, val;
+
+      // Send one continuous command and verify the queue fullness
+      start_rx(radio_num);
+      expected = CMD_FIFO_SPACE_MAX-1;
+      read_radio(radio_num, REG_RX_STATUS, val);
+      `ASSERT_ERROR(
+        val[CMD_FIFO_SPACE_POS+:CMD_FIFO_SPACE_LEN] == expected, 
+        "CMD_FIFO_SPACE did not decrement"
+      );
+
+      // Fill the command FIFO, going one over
+      for (int i = 0; i < CMD_FIFO_SPACE_MAX; i++) begin
+        start_rx(radio_num, WPP);
+      end
+      expected = 0;
+      read_radio(radio_num, REG_RX_STATUS, val);
+      `ASSERT_ERROR(
+        val[CMD_FIFO_SPACE_POS+:CMD_FIFO_SPACE_LEN] == expected, 
+        "CMD_FIFO_SPACE did not reach 0"
+      );
+
+      // Issue stop command and verify that the FIFO empties
+      stop_rx(radio_num);
+      expected = CMD_FIFO_SPACE_MAX;
+      read_radio(radio_num, REG_RX_STATUS, val);
+      `ASSERT_ERROR(
+        val[CMD_FIFO_SPACE_POS+:CMD_FIFO_SPACE_LEN] == expected, 
+        "CMD_FIFO_SPACE did not return to max"
+      );
+
+      // Grab and discard any remaining packets
+      do begin
+        while (blk_ctrl.num_received(radio_num) != 0) begin
+          ChdrPacket #(CHDR_W) chdr_packet;
+          blk_ctrl.get_chdr(radio_num, chdr_packet);
+        end
+        #MAX_PKT_WAIT;
+      end while (blk_ctrl.num_received(radio_num) != 0);
+
+      // Queue several long commands back-to-back and make sure they all 
+      // complete. The lengths are unique to ensure we execute the right 
+      // commands in the expected order.
+      for (int i = 0; i < 3; i++) start_rx(radio_num, WPP*20+i);
+      for (int i = 0; i < 3; i++) check_rx(radio_num, WPP*20+i);
+
+      // Make sure we don't get any more data
+      do begin
+        while (blk_ctrl.num_received(radio_num) != 0) begin
+          `ASSERT_ERROR(0, "Received unexpected packets");
+        end
+        #MAX_PKT_WAIT;
+      end while (blk_ctrl.num_received(radio_num) != 0);
+    end
+
+    test.end_test();
+
+  endtask : test_rx
+
+
+
+  task automatic test_tx(int radio_num);
+    logic [RADIO_W-1:0] radio_data;
+    enum { WAIT_FOR_EOP, WAIT_FOR_EOB } policy;
+
+    //-------
+    // Setup
+    //-------
+
+    test.start_test("Tx Init", 50us);
+
+    // Configure the error reporting registers
+    write_radio(radio_num, REG_TX_ERR_PORT, TX_ERR_DST_PORT);
+    write_radio(radio_num, REG_TX_ERR_REM_PORT, TX_ERR_REM_DST_PORT);
+    write_radio(radio_num, REG_TX_ERR_REM_EPID, TX_ERR_REM_DST_EPID);
+    write_radio(radio_num, REG_TX_ERR_ADDR, TX_ERR_ADDRESS);
+
+    test.end_test();
+
+
+    //---------------
+    // Test Tx (now)
+    //---------------
+
+    test.start_test("Tx (now)", 50us);
+
+    // Grab and verify a partial packet
+    start_tx(radio_num, WPP*3/4);
+    check_tx(radio_num, WPP*3/4);
+    check_error(ERR_TX_EOB_ACK);
+
+    // Grab and verify multiple packets
+    start_tx(radio_num, WPP*3/2);
+    check_tx(radio_num, WPP*3/2);
+    check_error(ERR_TX_EOB_ACK);
+
+    // Test a minimally-sized packet
+    start_tx(radio_num, 1);
+    check_tx(radio_num, 1);
+    check_error(ERR_TX_EOB_ACK);
+
+    test.end_test();
+
+
+    //---------------------
+    // Test Tx (underflow)
+    //---------------------
+
+    test.start_test("Tx (now, underflow)", 50us);
+
+    // Send some bursts without EOB
+    start_tx(radio_num, WPP*3/4, 1, 0);  // Skip EOB
+    check_tx(radio_num, WPP*3/4);
+    check_error(ERR_TX_UNDERRUN);
+
+    start_tx(radio_num, WPP*2, 1, 0);  // Skip EOB
+    check_tx(radio_num, WPP*2);
+    check_error(ERR_TX_UNDERRUN);
+
+    test.end_test();
+
+
+    //-----------------
+    // Test Tx (timed)
+    //-----------------
+
+    test.start_test("Tx (timed)", 50us);
+
+    // Grab and verify a partial packet
+    start_tx_timed(radio_num, WPP*3/4, radio_time + 200);
+    check_tx_timed(radio_num, WPP*3/4, radio_time + 200);
+    check_error(ERR_TX_EOB_ACK);
+
+    // Grab and verify whole packets
+    start_tx_timed(radio_num, WPP*2, radio_time + 200);
+    check_tx_timed(radio_num, WPP*2, radio_time + 200);
+    check_error(ERR_TX_EOB_ACK);
+
+    test.end_test();
+
+
+    //-----------------
+    // Test Tx (timed, underflow)
+    //-----------------
+
+    test.start_test("Tx (timed, underflow)", 50us);
+
+    // Send some bursts without EOB
+    start_tx_timed(radio_num, WPP*3/4, radio_time + 200, 1, 0);
+    check_tx_timed(radio_num, WPP*3/4, radio_time + 200);
+    check_error(ERR_TX_UNDERRUN);
+
+    start_tx_timed(radio_num, WPP*2, radio_time + 200, 1, 0);
+    check_tx_timed(radio_num, WPP*2, radio_time + 200);
+    check_error(ERR_TX_UNDERRUN);
+
+    test.end_test();
+
+
+    //---------------------------
+    // Test Tx (timed, late)
+    //---------------------------
+
+    test.start_test("Tx (timed, late)", 50us);
+
+    // Test each error policy
+    policy = policy.first();
+    do begin
+      // Set the policy
+      if (policy == WAIT_FOR_EOP) begin
+        write_radio(radio_num, REG_TX_ERROR_POLICY, TX_ERR_POLICY_PACKET);
+      end else if (policy == WAIT_FOR_EOB) begin
+        write_radio(radio_num, REG_TX_ERROR_POLICY, TX_ERR_POLICY_BURST);
+      end
+
+// Commenting out the fork code for now due to Vivado 2018.3 bug.
+//      radio_data = radio_tx_data[radio_num];
+//      fork : tx_fork
+        // In this branch of the fork, we send the packets
+        repeat (2) begin
+          // Send late packets with random start value
+          start_tx_timed(radio_num, WPP*3, 0, $urandom());
+
+          if (policy == WAIT_FOR_EOP) begin
+            // We should get three errors, one for each packet
+            repeat (3) check_error(ERR_TX_LATE_DATA);
+          end else if (policy == WAIT_FOR_EOB) begin
+            // We should get one error for the entire burst
+            check_error(ERR_TX_LATE_DATA);
+          end
+        end
+
+//        // The packets sent in the above branch of the fork should be 
+//        // dropped. In this branch of the fork we make sure that the Tx 
+//        // output doesn't change.
+//        begin
+//          forever begin
+//            @(posedge radio_clk)
+//            `ASSERT_ERROR(
+//              radio_data === radio_tx_data[radio_num], 
+//              "Radio Tx output changed when late Tx packet should have been ignored"
+//            );
+//          end
+//        end
+//      join_any
+//
+//      // Stop checking the output
+//      disable tx_fork;
+
+      policy = policy.next();
+    end while (policy != policy.first());
+
+    // Make sure good transmissions can go through now.
+    start_tx_timed(radio_num, WPP, radio_time + 200);
+    check_tx_timed(radio_num, WPP, radio_time + 200);
+    check_error(ERR_TX_EOB_ACK);
+
+    test.end_test();
+
+  endtask : test_tx
+
+
+
+  // Test internal loopback and idle value
+  task automatic test_loopback_and_idle(int radio_num);
+    int              byte_length;
+    chdr_word_t      data[$];
+    bit [ITEM_W-1:0] idle;
+
+    //----------------------------
+    // Use IDLE value to loopback
+    //----------------------------
+
+    test.start_test("Idle Loopback", 50us);
+
+    // Turn on loopback
+    write_radio(radio_num, REG_LOOPBACK_EN, 1);
+
+    // This test ensures we get the Tx output on Rx and not the TB's simulated 
+    // radio data. It also tests updating the idle value. Run the test twice to 
+    // make sure the IDLE value updates.
+    repeat (2) begin
+      // Set idle value
+      idle = $urandom();
+      write_radio(radio_num, REG_TX_IDLE_VALUE, idle);
+
+      // Grab a radio word and check that it equals the IDLE value
+      write_radio_64(radio_num, REG_RX_CMD_NUM_WORDS_LO, 1);
+      write_radio(radio_num, REG_RX_CMD, RX_CMD_FINITE);
+      blk_ctrl.recv(radio_num, data, byte_length);
+
+      // Check the length
+      `ASSERT_ERROR(byte_length == RADIO_W/8, "Didn't receive expected length");
+
+      // Check the payload
+      foreach (data[i]) begin
+        chdr_word_t word;
+        word = data[i];   // Work around Vivado 2018.3 issue
+        `ASSERT_ERROR(
+          word == {$bits(chdr_word_t)/ITEM_W{idle}},
+          "Loopback data didn't match expected"
+        );
+      end
+    end
+
+    test.end_test();
+
+
+    //---------------------
+    // Loopback Tx packets
+    //---------------------
+
+    test.start_test("Tx Loopback", 50us);
+
+    // This test ensures that loopback isn't reordering words or anything else
+    // unexpected.
+
+    // Configure the Tx error reporting registers
+    write_radio(radio_num, REG_TX_ERR_PORT,     TX_ERR_DST_PORT);
+    write_radio(radio_num, REG_TX_ERR_REM_PORT, TX_ERR_REM_DST_PORT);
+    write_radio(radio_num, REG_TX_ERR_REM_EPID, TX_ERR_REM_DST_EPID);
+    write_radio(radio_num, REG_TX_ERR_ADDR,     TX_ERR_ADDRESS);
+
+    // Set packet length
+    write_radio(radio_num, REG_RX_MAX_WORDS_PER_PKT, WPP);
+
+    // Loopback a few packets, back-to-back. This code has a race condition 
+    // since there's a delay between when we start Tx and when Rx starts, due 
+    // to how long it takes to write the Rx registers. Therefore, we transmit a 
+    // lot more packets than we receive to ensure we're still transmitting by 
+    // the time we receive.
+    start_tx(radio_num, WPP*16);
+    start_rx(radio_num, WPP*2);
+
+    // Check the results
+    check_rx(radio_num, WPP*2);
+    check_error(ERR_TX_EOB_ACK);
+
+    // Turn off loopback
+    write_radio(radio_num, REG_LOOPBACK_EN, 0);
+
+    test.end_test();
+  endtask : test_loopback_and_idle;
+
+
+
+  //---------------------------------------------------------------------------
+  // Test Process
+  //---------------------------------------------------------------------------
+
+  timeout_t timeout;
+
+  initial begin : main
+    string tb_name;
+
+    //-------------------------------------------------------------------------
+    // Initialization
+    //-------------------------------------------------------------------------
+
+    // Generate a string for the name of this instance of the testbench
+    tb_name = $sformatf(
+      "rfnoc_block_radio_tb\nCHDR_W = %0D, ITEM_W = %0D, NIPC = %0D, NUM_PORTS = %0D, STALL_PROB = %0D, STB_PROB = %0D, TEST_REGS = %0D",
+      CHDR_W, ITEM_W, NIPC, NUM_PORTS, STALL_PROB, STB_PROB, TEST_REGS
+    );
+
+    test.start_tb(tb_name);
+
+    // Don't start the clocks until after start_tb() returns. This ensures that
+    // the clocks aren't toggling while other instances of this testbench are
+    // running, which speeds up simulation time.
+    rfnoc_chdr_clk_gen.start();
+    rfnoc_ctrl_clk_gen.start();
+    radio_clk_gen.start();
+
+    // Setup and start the stream endpoint BFM
+    blk_ctrl = new(backend, m_ctrl, s_ctrl);
+    for (int i = 0; i < NUM_PORTS; i++) begin
+      // I'd love to do this:
+      //     void'(blk_ctrl.add_master_data_port(m_chdr[i]));
+      //     void'(blk_ctrl.add_slave_data_port(s_chdr[i]));
+      // But interface indices must be constant. So instead, we use a semaphore 
+      // to trigger port initialization and control the order of initialization 
+      // in the generate block gen_radio_connections.
+
+      // Put the port number in the semaphore to cause its initializer to run
+      port_sem.put(i+1);
+      // Delay to allow gen_radio_connections to run
+      #0;
+      // Get the port number again to know when it's done
+      port_sem.get(i+1);
+
+      // Set the CHDR BFM stall probability
+      blk_ctrl.set_master_stall_prob(i, STALL_PROB);
+      blk_ctrl.set_slave_stall_prob(i, STALL_PROB);
+    end
+    blk_ctrl.run();
+
+
+    //-------------------------------------------------------------------------
+    // Reset
+    //-------------------------------------------------------------------------
+
+    test.start_test("Flush block then reset it", 10us);
+    blk_ctrl.flush_and_reset();
+    test.end_test();
+
+
+    //-------------------------------------------------------------------------
+    // Test Sequences
+    //-------------------------------------------------------------------------
+
+    // Run register tests first, since they check that initial values are 
+    // correct.
+
+    test_block_info();
+    if (TEST_REGS) test_shared_registers();
+
+    for (int radio_num = 0; radio_num < NUM_PORTS; radio_num++) begin
+      $display("************************************************************");
+      $display("Testing Radio Channel %0d", radio_num);
+      $display("************************************************************");
+      if (TEST_REGS) begin
+        test_general_registers(radio_num);
+        test_rx_registers(radio_num);
+        test_tx_registers(radio_num);
+      end
+      test_rx(radio_num);
+      test_tx(radio_num);
+      test_loopback_and_idle(radio_num);
+    end
+
+
+    //-------------------------------------------------------------------------
+    // Finish
+    //-------------------------------------------------------------------------
+
+    // End the TB, but don't $finish, since we don't want to kill other 
+    // instances of this testbench that may be running.
+    test.end_tb(0);
+
+    // Kill the clocks to end this instance of the testbench
+    rfnoc_chdr_clk_gen.kill();
+    rfnoc_ctrl_clk_gen.kill();
+    radio_clk_gen.kill();
+
+  end : main
+
+endmodule : rfnoc_block_radio_tb
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/rx_frontend_gen3.v b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/rx_frontend_gen3.v
new file mode 100644
index 000000000..54529136b
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/rx_frontend_gen3.v
@@ -0,0 +1,246 @@
+//
+// Copyright 2015 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module rx_frontend_gen3 #(
+  parameter SR_MAG_CORRECTION = 0,
+  parameter SR_PHASE_CORRECTION = 1,
+  parameter SR_OFFSET_I = 2,
+  parameter SR_OFFSET_Q = 3,
+  parameter SR_IQ_MAPPING = 4,
+  parameter SR_HET_PHASE_INCR = 5,
+  parameter BYPASS_DC_OFFSET_CORR = 0,
+  parameter BYPASS_IQ_COMP = 0,
+  parameter BYPASS_REALMODE_DSP = 0,
+  parameter DEVICE = "7SERIES"
+)(
+  input clk, input reset, input sync_in,
+  input set_stb, input [7:0] set_addr, input [31:0] set_data,
+  input adc_stb, input [15:0] adc_i, input [15:0] adc_q,
+  output rx_stb, output [15:0] rx_i, output [15:0] rx_q
+);
+
+  wire               realmode;
+  wire               swap_iq;
+  wire               invert_i;
+  wire               invert_q;
+  wire               realmode_decim;
+  wire               bypass_all;
+  wire [1:0]         iq_map_reserved;
+  wire [17:0]        mag_corr, phase_corr;
+  wire               phase_dir;
+  wire               phase_sync;
+
+  reg  [23:0]        adc_i_mux, adc_q_mux;
+  reg                adc_mux_stb;
+  wire [23:0]        adc_i_ofs, adc_q_ofs, adc_i_comp, adc_q_comp;
+  reg  [23:0]        adc_i_ofs_dly, adc_q_ofs_dly;
+  wire               adc_ofs_stb, adc_comp_stb;
+  reg  [1:0]         adc_ofs_stb_dly;
+  wire [23:0]        adc_i_dsp, adc_q_dsp;
+  wire               adc_dsp_stb;
+  wire [35:0]        corr_i, corr_q;
+  wire [15:0]        rx_i_out, rx_q_out;
+
+  /********************************************************
+  ** Settings Bus Registers
+  ********************************************************/
+  setting_reg #(.my_addr(SR_MAG_CORRECTION),.width(18)) sr_mag_corr (
+    .clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+    .in(set_data),.out(mag_corr),.changed());
+
+  setting_reg #(.my_addr(SR_PHASE_CORRECTION),.width(18)) sr_phase_corr (
+    .clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+    .in(set_data),.out(phase_corr),.changed());
+
+  setting_reg #(.my_addr(SR_IQ_MAPPING), .width(8)) sr_mux_sel (
+    .clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+    .in(set_data),.out({bypass_all,iq_map_reserved,realmode_decim,invert_i,invert_q,realmode,swap_iq}),.changed());
+
+  // Setting reg: 1 bit to set phase direction: default to 0:
+  //   direction bit == 0: the phase is increased by pi/2 (counter clockwise)
+  //   direction bit == 1: the phase is increased by -pi/2 (clockwise)
+  setting_reg #(.my_addr(SR_HET_PHASE_INCR), .width(1)) sr_phase_dir (
+    .clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+    .in(set_data),.out(phase_dir),.changed(phase_sync));
+
+  /********************************************************
+  ** IQ Mapping (swapping, inversion, real-mode)
+  ********************************************************/
+  // MUX so we can do realmode signals on either input
+  always @(posedge clk) begin
+    if (swap_iq) begin
+      adc_i_mux[23:8] <= invert_q ? ~adc_q   : adc_q;
+      adc_q_mux[23:8] <= realmode ? 16'd0 : invert_i ? ~adc_i : adc_i;
+    end else begin
+      adc_i_mux[23:8] <= invert_i ? ~adc_i   : adc_i;
+      adc_q_mux[23:8] <= realmode ? 16'd0 : invert_q ? ~adc_q : adc_q;
+    end
+    adc_mux_stb <= adc_stb;
+    adc_i_mux[7:0] <= 8'd0;
+    adc_q_mux[7:0] <= 8'd0;
+  end
+
+  /********************************************************
+  ** DC offset Correction
+  ********************************************************/
+  generate
+    if (BYPASS_DC_OFFSET_CORR == 0) begin
+
+      rx_dcoffset #(.WIDTH(24),.ADDR(SR_OFFSET_I)) rx_dcoffset_i (
+        .clk(clk),.rst(reset),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+        .in_stb(adc_mux_stb),.in(adc_i_mux),
+        .out_stb(adc_ofs_stb),.out(adc_i_ofs));
+      rx_dcoffset #(.WIDTH(24),.ADDR(SR_OFFSET_Q)) rx_dcoffset_q (
+        .clk(clk),.rst(reset),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+        .in_stb(adc_mux_stb),.in(adc_q_mux),
+        .out_stb(),.out(adc_q_ofs));
+
+    end else begin
+      assign adc_ofs_stb = adc_mux_stb;
+      assign adc_i_ofs   = adc_i_mux;
+      assign adc_q_ofs   = adc_q_mux;
+    end
+  endgenerate
+
+  /********************************************************
+  ** IQ Imbalance Compensation
+  ********************************************************/
+  generate
+    if (BYPASS_IQ_COMP == 0) begin
+
+      mult_add_clip #(
+        .WIDTH_A(18),
+        .BIN_PT_A(17),
+        .WIDTH_B(18),
+        .BIN_PT_B(17),
+        .WIDTH_C(24),
+        .BIN_PT_C(23),
+        .WIDTH_O(24),
+        .BIN_PT_O(23),
+        .LATENCY(2)
+      ) mult_i (
+        .clk(clk),
+        .reset(reset),
+        .CE(1'b1),
+        .A(adc_i_ofs[23:6]),
+        .B(mag_corr),
+        .C(adc_i_ofs),
+        .O(adc_i_comp)
+      );
+
+      mult_add_clip #(
+        .WIDTH_A(18),
+        .BIN_PT_A(17),
+        .WIDTH_B(18),
+        .BIN_PT_B(17),
+        .WIDTH_C(24),
+        .BIN_PT_C(23),
+        .WIDTH_O(24),
+        .BIN_PT_O(23),
+        .LATENCY(2)
+      ) mult_q (
+        .clk(clk),
+        .reset(reset),
+        .CE(1'b1),
+        .A(adc_i_ofs[23:6]),
+        .B(phase_corr),
+        .C(adc_q_ofs),
+        .O(adc_q_comp)
+      );
+
+      // Delay to match path latencies
+      always @(posedge clk) begin
+        if (reset) begin
+          adc_ofs_stb_dly <= 2'b0;
+        end else begin
+          adc_ofs_stb_dly <= {adc_ofs_stb_dly[0], adc_ofs_stb};
+        end
+      end
+
+      assign adc_comp_stb = adc_ofs_stb_dly[1];
+
+    end else begin
+      assign adc_comp_stb = adc_ofs_stb;
+      assign adc_i_comp   = adc_i_ofs;
+      assign adc_q_comp   = adc_q_ofs;
+    end
+  endgenerate
+
+  /********************************************************
+  ** Realmode DSP:
+  *  - Heterodyne frequency translation
+  *  - Realmode decimation (by 2)
+  ********************************************************/
+  generate
+    if (BYPASS_REALMODE_DSP == 0) begin
+
+      wire [24:0] adc_i_dsp_cout, adc_q_dsp_cout;
+      wire [23:0] adc_i_cclip, adc_q_cclip;
+      wire [23:0] adc_i_hb, adc_q_hb;
+      wire [23:0] adc_i_dec, adc_q_dec;
+      wire        adc_dsp_cout_stb;
+      wire        adc_cclip_stb;
+      wire        adc_hb_stb;
+
+      wire valid_hbf0;
+      wire valid_hbf1;
+      wire valid_dec0;
+      wire valid_dec1;
+
+      // 90 degree mixer
+      quarter_rate_downconverter #(.WIDTH(24)) qr_dc_i(
+        .clk(clk), .reset(reset || sync_in), .phase_sync(phase_sync),
+        .i_tdata({adc_i_comp, adc_q_comp}), .i_tlast(1'b1), .i_tvalid(adc_comp_stb), .i_tready(),
+        .o_tdata({adc_i_dsp_cout, adc_q_dsp_cout}), .o_tlast(), .o_tvalid(adc_dsp_cout_stb), .o_tready(1'b1),
+        .dirctn(phase_dir));
+
+      // Double FIR and decimator block
+      localparam HB_COEFS = {-18'd62, 18'd0, 18'd194, 18'd0, -18'd440, 18'd0, 18'd855, 18'd0, -18'd1505, 18'd0, 18'd2478, 18'd0,
+        -18'd3900, 18'd0, 18'd5990, 18'd0, -18'd9187, 18'd0, 18'd14632, 18'd0, -18'd26536, 18'd0, 18'd83009, 18'd131071, 18'd83009,
+        18'd0, -18'd26536, 18'd0, 18'd14632, 18'd0, -18'd9187, 18'd0, 18'd5990, 18'd0, -18'd3900, 18'd0, 18'd2478, 18'd0, -18'd1505,
+        18'd0, 18'd855, 18'd0, -18'd440, 18'd0, 18'd194, 18'd0, -18'd62};
+
+      axi_fir_filter_dec #(
+          .WIDTH(24),
+          .COEFF_WIDTH(18),
+          .NUM_COEFFS(47),
+          .COEFFS_VEC(HB_COEFS),
+          .BLANK_OUTPUT(0)
+        ) ffd0 (
+        .clk(clk), .reset(reset || sync_in),
+
+        .i_tdata({adc_i_dsp_cout, adc_q_dsp_cout}),
+        .i_tlast(1'b1),
+        .i_tvalid(adc_dsp_cout_stb),
+        .i_tready(),
+
+        .o_tdata({adc_i_dec, adc_q_dec}),
+        .o_tlast(),
+        .o_tvalid(adc_hb_stb),
+        .o_tready(1'b1));
+
+      assign adc_dsp_stb = realmode_decim ? adc_hb_stb : adc_comp_stb;
+      assign adc_i_dsp   = realmode_decim ? adc_i_dec : adc_i_comp;
+      assign adc_q_dsp   = realmode_decim ? adc_q_dec : adc_q_comp;
+
+    end else begin
+      assign adc_dsp_stb = adc_comp_stb;
+      assign adc_i_dsp   = adc_i_comp;
+      assign adc_q_dsp   = adc_q_comp;
+    end
+  endgenerate
+
+  // Round to short complex (sc16)
+  round_sd #(.WIDTH_IN(24),.WIDTH_OUT(16)) round_i (
+    .clk(clk),.reset(reset), .in(adc_i_dsp),.strobe_in(adc_dsp_stb), .out(rx_i_out), .strobe_out(rx_stb));
+  round_sd #(.WIDTH_IN(24),.WIDTH_OUT(16)) round_q (
+    .clk(clk),.reset(reset), .in(adc_q_dsp),.strobe_in(adc_dsp_stb), .out(rx_q_out), .strobe_out());
+
+  assign rx_i = bypass_all ? adc_i : rx_i_out;
+  assign rx_q = bypass_all ? adc_q : rx_q_out;
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/sim_radio_gen.sv b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/sim_radio_gen.sv
new file mode 100644
index 000000000..a6f827f8f
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/sim_radio_gen.sv
@@ -0,0 +1,104 @@
+//
+// Copyright 2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: sim_radio_gen
+//
+// Description: Generate radio data for simulation purposes. The strobe pattern 
+// is random, which is not like a normal radio but covers every possibility. 
+// The data pattern is an incrementing sequence of samples, with each channel 
+// starting at a different value to differentiate them. Strobe and time are 
+// common between channels.
+//
+
+module sim_radio_gen #(
+  parameter int NSPC         = 1,  // Number of samples per clock cycle
+  parameter int SAMP_W       = 32, // Length of each radio sample
+  parameter int NUM_CHANNELS = 1,  // Number of radio RX ports
+  parameter int STB_PROB     = 50, // Probability of STB being asserted on each clock cycle
+  parameter int INCREMENT    = 2,  // Amount by which to increment
+  parameter int PPS_PERIOD   = 50  // Period of the PPS output
+) (
+  input  bit                                radio_clk,
+  input  bit                                radio_rst,
+  output bit [NUM_CHANNELS*SAMP_W*NSPC-1:0] radio_rx_data,
+  output bit [            NUM_CHANNELS-1:0] radio_rx_stb,
+  output bit [                        63:0] radio_time,
+  output bit                                radio_pps
+);
+
+  localparam int RADIO_W = SAMP_W*NSPC;
+  typedef bit [RADIO_W-1:0] radio_t;    // Radio output word
+  typedef bit [SAMP_W-1:0] sample_t;    // Single sample
+
+  initial assert (PPS_PERIOD % INCREMENT == 0) else
+    $fatal(1, "PPS_PERIOD must be a multiple of INCREMENT");
+
+
+  // Generate an initial value all radio channels
+  function radio_t [NUM_CHANNELS-1:0] radio_init();
+    radio_t [NUM_CHANNELS-1:0] ret_val;
+   
+    for (int n = 0; n < NUM_CHANNELS; n++) begin
+      sample_t sample;
+
+      // Calculate the value of first sample in this radio channel
+      sample = sample_t'((2.0 ** SAMP_W) / NUM_CHANNELS * n);
+
+      // Calculate the value of subsequent samples in the channel
+      for (int s = 0; s < NSPC; s++) begin
+        ret_val[n][s*SAMP_W +: SAMP_W] = sample + s;
+      end
+    end
+
+    return ret_val;
+  endfunction : radio_init
+
+
+  //---------------------------------------------------------------------------
+  // Radio Data Generation
+  //---------------------------------------------------------------------------
+
+  radio_t [NUM_CHANNELS-1:0] data = radio_init();
+
+  assign radio_rx_data = data;
+
+  always @(posedge radio_clk) begin : radio_data_count_reg
+    if (radio_rst) begin
+      data         <= radio_init();
+      radio_rx_stb <= '0;
+    end else begin
+      radio_rx_stb <= '0;
+      if ($urandom_range(100) < STB_PROB) begin
+        for (int n = 0; n < NUM_CHANNELS; n++) begin
+          for (int s = 0; s < NSPC; s++) begin
+            data[n][s*SAMP_W +: SAMP_W] <= data[n][s*SAMP_W +: SAMP_W] + NSPC;
+          end
+        end
+        radio_rx_stb <= '1;
+      end
+    end
+  end : radio_data_count_reg
+
+
+  //---------------------------------------------------------------------------
+  // Radio Time
+  //---------------------------------------------------------------------------
+
+  always @(posedge radio_clk) begin
+    if (radio_rst) begin
+      radio_time <= 64'b0;
+      radio_pps  <=  1'b0;
+    end else begin
+      radio_pps  <= 1'b0;
+      if (radio_rx_stb[0]) begin
+        radio_time <= radio_time + INCREMENT;
+        if (radio_time % PPS_PERIOD == 0 && radio_time != 0) begin
+          radio_pps <= 1'b1;
+        end
+      end
+    end
+  end
+
+endmodule : sim_radio_gen
\ No newline at end of file
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/tx_frontend_gen3.v b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/tx_frontend_gen3.v
new file mode 100644
index 000000000..f5435787d
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/tx_frontend_gen3.v
@@ -0,0 +1,173 @@
+//
+// Copyright 2015 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module tx_frontend_gen3 #(
+  parameter SR_OFFSET_I = 0,
+  parameter SR_OFFSET_Q = 1,
+  parameter SR_MAG_CORRECTION = 2,
+  parameter SR_PHASE_CORRECTION = 3,
+  parameter SR_MUX = 4,
+  parameter BYPASS_DC_OFFSET_CORR = 0,
+  parameter BYPASS_IQ_COMP = 0,
+  parameter DEVICE = "7SERIES"
+)(
+  input clk, input reset,
+  input set_stb, input [7:0] set_addr, input [31:0] set_data,
+  input tx_stb, input [15:0] tx_i, input [15:0] tx_q,
+  output reg dac_stb, output reg [15:0] dac_i, output reg [15:0] dac_q
+);
+
+  wire [23:0]        i_dco, q_dco;
+  wire [7:0]         mux_ctrl;
+  wire [17:0]        mag_corr, phase_corr;
+
+  wire [35:0]        corr_i, corr_q;
+  reg  [1:0]         tx_stb_dly;
+  reg  [23:0]        tx_i_dly, tx_q_dly;
+  wire               tx_comp_stb, tx_ofs_stb;
+  wire [23:0]        tx_i_comp, tx_q_comp, tx_i_ofs, tx_q_ofs;
+  wire               tx_round_stb;
+  wire [15:0]        tx_i_round, tx_q_round;
+
+  /********************************************************
+  ** Settings Registers
+  ********************************************************/
+  setting_reg #(.my_addr(SR_OFFSET_I), .width(24)) sr_i_dc_offset (
+    .clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+    .in(set_data),.out(i_dco),.changed());
+
+  setting_reg #(.my_addr(SR_OFFSET_Q), .width(24)) sr_q_dc_offset (
+    .clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+    .in(set_data),.out(q_dco),.changed());
+
+  setting_reg #(.my_addr(SR_MAG_CORRECTION),.width(18)) sr_mag_corr (
+    .clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+    .in(set_data),.out(mag_corr),.changed());
+
+  setting_reg #(.my_addr(SR_PHASE_CORRECTION),.width(18)) sr_phase_corr (
+    .clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+    .in(set_data),.out(phase_corr),.changed());
+
+  setting_reg #(.my_addr(SR_MUX), .width(8), .at_reset(8'h10)) sr_mux_ctrl (
+    .clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+    .in(set_data),.out(mux_ctrl),.changed());
+
+  /********************************************************
+  ** DSP
+  ********************************************************/
+  // I/Q compensation with option to bypass
+  generate
+    if (BYPASS_IQ_COMP == 0) begin
+
+      mult_add_clip #(
+        .WIDTH_A(16),
+        .BIN_PT_A(15),
+        .WIDTH_B(18),
+        .BIN_PT_B(17),
+        .WIDTH_C(16),
+        .BIN_PT_C(15),
+        .WIDTH_O(24),
+        .BIN_PT_O(23),
+        .LATENCY(2)
+      ) mult_i (
+        .clk(clk),
+        .reset(reset),
+        .CE(1'b1),
+        .A(tx_i),
+        .B(mag_corr),
+        .C(tx_i),
+        .O(tx_i_comp)
+      );
+
+      mult_add_clip #(
+        .WIDTH_A(16),
+        .BIN_PT_A(15),
+        .WIDTH_B(18),
+        .BIN_PT_B(17),
+        .WIDTH_C(16),
+        .BIN_PT_C(15),
+        .WIDTH_O(24),
+        .BIN_PT_O(23),
+        .LATENCY(2)
+      ) mult_q (
+        .clk(clk),
+        .reset(reset),
+        .CE(1'b1),
+        .A(tx_i),
+        .B(phase_corr),
+        .C(tx_q),
+        .O(tx_q_comp)
+      );
+
+      // Delay to match path latencies
+      always @(posedge clk) begin
+        if (reset) begin
+          tx_stb_dly <= 2'b0;
+        end else begin
+          tx_stb_dly <= {tx_stb_dly[0], tx_stb};
+        end
+      end
+
+      assign tx_comp_stb = tx_stb_dly[1];
+
+    end else begin
+      assign tx_comp_stb = tx_stb;
+      assign tx_i_comp = {tx_i,8'd0};
+      assign tx_q_comp = {tx_q,8'd0};
+    end
+  endgenerate
+
+  // DC offset correction
+  generate
+    if (BYPASS_DC_OFFSET_CORR == 0) begin
+      add2_and_clip_reg #(.WIDTH(24)) add_dco_i (
+        .clk(clk), .rst(reset), .in1(i_dco), .in2(tx_i_comp), .strobe_in(tx_comp_stb), .sum(tx_i_ofs), .strobe_out(tx_ofs_stb));
+      add2_and_clip_reg #(.WIDTH(24)) add_dco_q (
+        .clk(clk), .rst(reset), .in1(q_dco), .in2(tx_q_comp), .strobe_in(tx_comp_stb), .sum(tx_q_ofs), .strobe_out());
+    end else begin
+      assign tx_ofs_stb = tx_comp_stb;
+      assign tx_i_ofs = tx_i_comp;
+      assign tx_q_ofs = tx_q_comp;
+    end
+  endgenerate
+
+  // Round to short complex (sc16)
+  round_sd #(.WIDTH_IN(24),.WIDTH_OUT(16)) round_i (
+    .clk(clk),.reset(reset), .in(tx_i_ofs),.strobe_in(tx_ofs_stb), .out(tx_i_round), .strobe_out(tx_round_stb));
+  round_sd #(.WIDTH_IN(24),.WIDTH_OUT(16)) round_q (
+    .clk(clk),.reset(reset), .in(tx_q_ofs),.strobe_in(tx_ofs_stb), .out(tx_q_round), .strobe_out());
+
+  // Mux
+  // Muxing logic matches that in tx_frontend.v, and what tx_frontend_core_200.cpp expects.
+  //
+  // mux_ctrl ! 0+0  ! 0+16 ! 1+0  ! 1+16
+  // =========!======!======!======!========
+  // DAC_I    ! tx_i ! tx_i ! tx_q ! tx_q
+  // DAC_Q    ! tx_i ! tx_q ! tx_i ! tx_q
+  //
+  // Most daughterboards will thus use 0x01 or 0x10 as the mux_ctrl value.
+  always @(posedge clk) begin
+    if (reset) begin
+      dac_stb <= 1'b0;
+      dac_i   <= 16'd0;
+      dac_q   <= 16'd0;
+    end else begin
+      dac_stb <= tx_round_stb;
+      case(mux_ctrl[3:0])
+        0 : dac_i <= tx_i_round;
+        1 : dac_i <= tx_q_round;
+        default : dac_i <= 0;
+      endcase
+      case(mux_ctrl[7:4])
+        0 : dac_q <= tx_i_round;
+        1 : dac_q <= tx_q_round;
+        default : dac_q <= 0;
+      endcase
+    end
+  end
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/cadd.v b/fpga/usrp3/lib/rfnoc/cadd.v
new file mode 100644
index 000000000..d571b3440
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/cadd.v
@@ -0,0 +1,32 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Complex adder
+
+module cadd
+  #(parameter WIDTH=16)
+   (input clk, input reset,
+    input [WIDTH*2-1:0] a_tdata, input a_tlast, input a_tvalid, output a_tready,
+    input [WIDTH*2-1:0] b_tdata, input b_tlast, input b_tvalid, output b_tready,
+    output [WIDTH*2-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready);
+
+   wire int_tlast = a_tlast | b_tlast;
+   wire int_tvalid, int_tready;
+   wire [WIDTH*2-1:0] int_tdata;
+
+   assign int_tdata[WIDTH*2-1:WIDTH] = a_tdata[WIDTH*2-1:WIDTH] + b_tdata[WIDTH*2-1:WIDTH];
+   assign int_tdata[WIDTH-1:0] = a_tdata[WIDTH-1:0] + b_tdata[WIDTH-1:0];
+
+   assign int_tvalid = a_tvalid & b_tvalid;
+   assign a_tready = int_tvalid & int_tready;
+   assign b_tready = a_tready;
+   
+   axi_fifo #(.WIDTH(WIDTH*2+1), .SIZE(0)) flop_output
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata({int_tlast, int_tdata}), .i_tvalid(int_tvalid), .i_tready(int_tready),
+      .o_tdata({o_tlast, o_tdata}), .o_tvalid(o_tvalid), .o_tready(o_tready));
+   
+endmodule // cadd
diff --git a/fpga/usrp3/lib/rfnoc/chdr_deframer.v b/fpga/usrp3/lib/rfnoc/chdr_deframer.v
new file mode 100644
index 000000000..408c26e9a
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/chdr_deframer.v
@@ -0,0 +1,108 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// FIXME -- detect seqnum errors?
+
+module chdr_deframer #(
+   parameter WIDTH = 32 // Can be 32 or 64
+)( input clk, input reset, input clear,
+   input [63:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
+   output [WIDTH-1:0] o_tdata, output [127:0] o_tuser, output o_tlast, output o_tvalid, input o_tready);
+   
+   localparam ST_HEAD = 2'd0;
+   localparam ST_TIME = 2'd1;
+   localparam ST_BODY = 2'd2;
+   
+   reg [1:0] 	 chdr_state;
+   reg 		 odd_length;
+
+   wire [127:0]  hdr_i_tuser, hdr_o_tuser;
+   wire 	 hdr_i_tvalid, hdr_i_tready;
+   wire 	 hdr_o_tvalid, hdr_o_tready;
+
+   wire [63:0] 	 body_i_tdata, body_o_tdata;
+   wire 	 body_i_tlast, body_o_tlast;
+   wire 	 body_i_tvalid, body_o_tvalid;
+   wire 	 body_i_tready, body_o_tready;
+
+   wire 	 has_time = i_tdata[61];
+   wire [15:0] 	 len = i_tdata[47:32];
+   reg [63:0] 	 held_i_tdata;
+   
+   assign body_i_tdata = i_tdata;
+   assign body_i_tlast = i_tlast;
+   assign body_i_tvalid = (chdr_state == ST_BODY) ? i_tvalid : 1'b0;
+
+   assign hdr_i_tuser = (chdr_state == ST_HEAD) ? { i_tdata, i_tdata } : { held_i_tdata, i_tdata }; // 2nd half ignored if no time
+   assign hdr_i_tvalid = (chdr_state == ST_TIME) ? i_tvalid :
+			 ((chdr_state == ST_HEAD) & ~has_time) ? i_tvalid :
+			 1'b0;
+   
+   assign i_tready = (chdr_state == ST_BODY) ? body_i_tready : hdr_i_tready;
+
+   // FIXME handle packets with no body
+   always @(posedge clk)
+     if(reset | clear)
+       chdr_state <= ST_HEAD;
+     else
+       case(chdr_state)
+	 ST_HEAD :
+	   if(i_tvalid & hdr_i_tready)
+	     if(has_time)
+	       begin
+		  chdr_state <= ST_TIME;
+		  held_i_tdata <= i_tdata;
+	       end
+	     else
+	       chdr_state <= ST_BODY;
+	 ST_TIME :
+	   if(i_tvalid & hdr_i_tready)
+	     chdr_state <= ST_BODY;
+	 ST_BODY :
+	   if(i_tvalid & body_i_tready & i_tlast)
+	     chdr_state <= ST_HEAD;
+       endcase // case (chdr_state)
+   
+   axi_fifo #(.WIDTH(128), .SIZE(5)) hdr_fifo
+     (.clk(clk), .reset(reset), .clear(clear),
+      .i_tdata(hdr_i_tuser), .i_tvalid(hdr_i_tvalid), .i_tready(hdr_i_tready),
+      .o_tdata(hdr_o_tuser), .o_tvalid(hdr_o_tvalid), .o_tready(hdr_o_tready),
+      .occupied(), .space());
+   
+   axi_fifo #(.WIDTH(65), .SIZE(5)) body_fifo
+     (.clk(clk), .reset(reset), .clear(clear),
+      .i_tdata({body_i_tlast, body_i_tdata}), .i_tvalid(body_i_tvalid), .i_tready(body_i_tready),
+      .o_tdata({body_o_tlast, body_o_tdata}), .o_tvalid(body_o_tvalid), .o_tready(body_o_tready),
+      .occupied(), .space());
+
+   assign o_tuser = hdr_o_tuser;
+   assign o_tvalid = hdr_o_tvalid & body_o_tvalid;
+   assign hdr_o_tready = o_tvalid & o_tready & o_tlast;
+
+   generate if (WIDTH == 32) begin
+     reg second_half;
+     wire odd_len = hdr_o_tuser[98] ^ |hdr_o_tuser[97:96];
+
+     always @(posedge clk)
+       if(reset | clear)
+         second_half <= 1'b0;
+       else
+         if(o_tvalid & o_tready)
+           if(o_tlast)
+             second_half <= 1'b0;
+           else
+             second_half <= ~second_half;
+     
+     assign o_tdata = second_half ? body_o_tdata[31:0] : body_o_tdata[63:32];
+     assign o_tlast = body_o_tlast & (second_half | odd_len);
+     assign body_o_tready = o_tvalid & o_tready & (o_tlast | second_half);
+   end else if (WIDTH == 64) begin
+     assign o_tdata = body_o_tdata;
+     assign o_tlast = body_o_tlast;
+     assign body_o_tready = o_tvalid & o_tready;
+   end endgenerate
+ 
+endmodule // chdr_deframer
diff --git a/fpga/usrp3/lib/rfnoc/chdr_deframer_2clk.v b/fpga/usrp3/lib/rfnoc/chdr_deframer_2clk.v
new file mode 100644
index 000000000..e15263b09
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/chdr_deframer_2clk.v
@@ -0,0 +1,139 @@
+/////////////////////////////////////////////////////////////////////
+//
+// Copyright 2018 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: chdr_deframer_2clk
+// Description:
+//  - Takes a sample stream in and uses the tuser input to frame
+//   a CHDR packet which is output by the module
+//   samples at the output
+//
+/////////////////////////////////////////////////////////////////////
+
+
+module chdr_deframer_2clk #(
+  parameter WIDTH = 32      // 32 and 64 bits supported
+) (
+  input samp_clk, input samp_rst, input pkt_clk, input pkt_rst,
+  input [63:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
+  output [WIDTH-1:0] o_tdata, output [127:0] o_tuser, output o_tlast, output o_tvalid, input o_tready
+);
+
+  localparam [1:0] ST_HEAD = 2'd0;
+  localparam [1:0] ST_TIME = 2'd1;
+  localparam [1:0] ST_BODY = 2'd2;
+
+  reg [1:0]     chdr_state;
+
+  wire [127:0]  hdr_i_tuser, hdr_o_tuser;
+  wire          hdr_i_tvalid, hdr_i_tready;
+  wire          hdr_o_tvalid, hdr_o_tready;
+
+  wire [63:0]   body_i_tdata, body_o_tdata;
+  wire          body_i_tlast, body_o_tlast;
+  wire          body_i_tvalid, body_o_tvalid;
+  wire          body_i_tready, body_o_tready;
+
+  wire          has_time = i_tdata[61];
+  reg [63:0]    held_i_tdata;
+  reg           second_half;
+
+  assign body_i_tdata = i_tdata;
+  assign body_i_tlast = i_tlast;
+  assign body_i_tvalid = (chdr_state == ST_BODY) ? i_tvalid : 1'b0;
+
+  assign hdr_i_tuser = (chdr_state == ST_HEAD) ? { i_tdata, i_tdata } : { held_i_tdata, i_tdata }; // 2nd half ignored if no time
+  assign hdr_i_tvalid = (chdr_state == ST_TIME) ? i_tvalid :
+       ((chdr_state == ST_HEAD) & ~has_time) ? i_tvalid :
+       1'b0;
+
+  assign i_tready = (chdr_state == ST_BODY) ? body_i_tready : hdr_i_tready;
+
+  // FIXME handle packets with no body
+  always @(posedge pkt_clk) begin
+    if (pkt_rst) begin
+      chdr_state <= ST_HEAD;
+    end else begin
+      case(chdr_state)
+        ST_HEAD:
+          if (i_tvalid & hdr_i_tready)
+            if (has_time) begin
+              chdr_state <= ST_TIME;
+              held_i_tdata <= i_tdata;
+            end else begin
+              chdr_state <= ST_BODY;
+            end
+        ST_TIME:
+          if (i_tvalid & hdr_i_tready)
+            chdr_state <= ST_BODY;
+        ST_BODY:
+          if (i_tvalid & body_i_tready & i_tlast)
+            chdr_state <= ST_HEAD;
+      endcase
+    end
+  end
+
+  wire pkt_rst_stretch;
+  pulse_stretch #(.SCALE('d10)) pkt_reset_i (
+    .clk(pkt_clk),
+    .rst(1'b0),
+    .pulse(pkt_rst),
+    .pulse_stretched(pkt_rst_stretch)
+  );
+
+  axi_fifo_2clk #(.WIDTH(128), .SIZE(5)) hdr_fifo_i (
+    .i_aclk(pkt_clk), .o_aclk(samp_clk), .reset(pkt_rst_stretch),
+    .i_tdata(hdr_i_tuser), .i_tvalid(hdr_i_tvalid), .i_tready(hdr_i_tready),
+    .o_tdata(hdr_o_tuser), .o_tvalid(hdr_o_tvalid), .o_tready(hdr_o_tready)
+  );
+
+  axi_fifo_2clk #(.WIDTH(65), .SIZE(9)) body_fifo (
+    .i_aclk(pkt_clk), .o_aclk(samp_clk), .reset(pkt_rst_stretch),
+    .i_tdata({body_i_tlast, body_i_tdata}), .i_tvalid(body_i_tvalid), .i_tready(body_i_tready),
+    .o_tdata({body_o_tlast, body_o_tdata}), .o_tvalid(body_o_tvalid), .o_tready(body_o_tready)
+  );
+
+  wire odd_len = hdr_o_tuser[98] ^ |hdr_o_tuser[97:96];
+
+  generate
+    if (WIDTH == 32) begin : gen_32bit_output
+      // 32-bit Output
+
+      always @(posedge samp_clk) begin
+        if(samp_rst) begin
+          second_half <= 1'b0;
+        end else begin
+          if(o_tvalid & o_tready) begin
+            if(o_tlast)
+              second_half <= 1'b0;
+            else
+              second_half <= ~second_half;
+          end
+        end
+      end
+      
+      assign o_tdata = second_half ? body_o_tdata[WIDTH-1:0] : body_o_tdata[(2*WIDTH)-1:WIDTH];
+      assign o_tlast = body_o_tlast & (second_half | odd_len);
+      assign o_tuser = hdr_o_tuser;
+      assign o_tvalid = hdr_o_tvalid & body_o_tvalid;
+      
+      assign hdr_o_tready = o_tvalid & o_tready & o_tlast;
+      assign body_o_tready = o_tvalid & o_tready & (o_tlast | second_half);
+
+    end else begin : gen_64bit_output
+      // 64-bit Output
+
+      assign o_tdata  = body_o_tdata;
+      assign o_tlast  = body_o_tlast;
+      assign o_tuser  = hdr_o_tuser;
+      assign o_tvalid = hdr_o_tvalid & body_o_tvalid;
+      
+      assign hdr_o_tready  = o_tvalid & o_tready & o_tlast;
+      assign body_o_tready = o_tvalid & o_tready;
+
+    end
+  endgenerate
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/chdr_fifo_large.v b/fpga/usrp3/lib/rfnoc/chdr_fifo_large.v
new file mode 100644
index 000000000..77e1f8a0b
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/chdr_fifo_large.v
@@ -0,0 +1,94 @@
+//
+// Copyright 2016 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module chdr_fifo_large #(
+  parameter SIZE   = 12,
+  parameter DEVICE = "7SERIES"
+) (
+  input         clk, 
+  input         reset, 
+  input         clear,
+
+  input [63:0]  i_tdata,
+  input         i_tlast,
+  input         i_tvalid,
+  output        i_tready,
+
+  output [63:0] o_tdata,
+  output        o_tlast,
+  output        o_tvalid,
+  input         o_tready
+);
+
+  localparam SIZE_THRESHOLD = (
+    (DEVICE == "7SERIES")   ? 14 : (
+    (DEVICE == "VIRTEX6")   ? 14 : (
+    (DEVICE == "SPARTAN6")  ? 12 : (
+    12
+  ))));
+
+  wire [63:0] i_tdata_pre;
+  wire        i_tlast_pre, i_tvalid_pre, i_tready_pre;
+  
+  // SRL based FIFO to break timing paths to BRAM resources
+  axi_fifo_flop2 #(.WIDTH(65)) pre_fifo (
+    .clk(clk), .reset(reset), .clear(clear),
+    .i_tdata({i_tlast, i_tdata}), .i_tvalid(i_tvalid), .i_tready(i_tready),
+    .o_tdata({i_tlast_pre, i_tdata_pre}), .o_tvalid(i_tvalid_pre), .o_tready(i_tready_pre),
+    .space(), .occupied()
+  );
+
+  generate 
+    if (SIZE <= SIZE_THRESHOLD) begin
+      wire [63:0] o_tdata_int;
+      wire        o_tlast_int, o_tvalid_int, o_tready_int;
+      // Instantiate a single axi_fifo if size is not larger than threshold
+      axi_fifo #(.WIDTH(65), .SIZE(SIZE)) main_fifo (
+        .clk(clk), .reset(reset), .clear(clear),
+        .i_tdata({i_tlast_pre, i_tdata_pre}), .i_tvalid(i_tvalid_pre), .i_tready(i_tready_pre),
+        .o_tdata({o_tlast_int, o_tdata_int}), .o_tvalid(o_tvalid_int), .o_tready(o_tready_int),
+        .space(), .occupied()
+      );
+      axi_fifo_flop2 #(.WIDTH(65)) fifo_flop2 (
+        .clk(clk), .reset(reset), .clear(clear),
+        .i_tdata({o_tlast_int, o_tdata_int}), .i_tvalid(o_tvalid_int), .i_tready(o_tready_int),
+        .o_tdata({o_tlast, o_tdata}), .o_tvalid(o_tvalid), .o_tready(o_tready),
+        .space(), .occupied()
+      );
+    end else begin
+      // Instantiate a cascade of axi_fifos if size is larger than threshold
+      localparam CDEPTH = 2**(SIZE - SIZE_THRESHOLD); //Cascade Depth
+      wire [63:0] c_tdata[CDEPTH:0], int_tdata[CDEPTH-1:0];
+      wire        c_tlast[CDEPTH:0], c_tvalid[CDEPTH:0], c_tready[CDEPTH:0];
+      wire        int_tlast[CDEPTH-1:0], int_tvalid[CDEPTH-1:0], int_tready[CDEPTH-1:0];
+      
+      //Connect input to first cascade state
+      assign {c_tdata[0], c_tlast[0], c_tvalid[0]} = {i_tdata_pre, i_tlast_pre, i_tvalid_pre};
+      assign i_tready_pre = c_tready[0];
+      //Connect output to last cascade state
+      assign {o_tdata, o_tlast, o_tvalid} = {c_tdata[CDEPTH], c_tlast[CDEPTH], c_tvalid[CDEPTH]};
+      assign c_tready[CDEPTH] = o_tready;
+
+      genvar i;
+      for (i=0; i<CDEPTH; i=i+1) begin: fifo_stages
+        axi_fifo #(.WIDTH(65), .SIZE(SIZE_THRESHOLD)) main_fifo (
+          .clk(clk), .reset(reset), .clear(clear),
+          .i_tdata({c_tlast[i], c_tdata[i]}), .i_tvalid(c_tvalid[i]), .i_tready(c_tready[i]),
+          .o_tdata({int_tlast[i], int_tdata[i]}), .o_tvalid(int_tvalid[i]), .o_tready(int_tready[i]),
+          .space(), .occupied()
+        );
+        axi_fifo_flop2 #(.WIDTH(65)) fifo_flop2 (
+          .clk(clk), .reset(reset), .clear(clear),
+          .i_tdata({int_tlast[i], int_tdata[i]}), .i_tvalid(int_tvalid[i]), .i_tready(int_tready[i]),
+          .o_tdata({c_tlast[i+1], c_tdata[i+1]}), .o_tvalid(c_tvalid[i+1]), .o_tready(c_tready[i+1]),
+          .space(), .occupied()
+        );
+      end
+    end
+  endgenerate
+
+endmodule // axi_fifo_large
diff --git a/fpga/usrp3/lib/rfnoc/chdr_framer.v b/fpga/usrp3/lib/rfnoc/chdr_framer.v
new file mode 100644
index 000000000..271c8e3d5
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/chdr_framer.v
@@ -0,0 +1,128 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// FIXME handle odd length inputs
+//
+// Warning: Currently only 32 / 64-bit input widths are supported.
+//          If 64-bit is selected, there will be a bubble state.
+//
+
+module chdr_framer
+  #(parameter SIZE=10,
+    parameter WIDTH=32,       // 32 or 64 only! TODO: Extend to other widths.
+    parameter USE_SEQ_NUM=0)  // Use provided seq number in tuser
+   (input clk, input reset, input clear,
+    input [WIDTH-1:0] i_tdata, input [127:0] i_tuser, input i_tlast, input i_tvalid, output i_tready,
+    output [63:0] o_tdata, output o_tlast, output o_tvalid, input o_tready);
+
+   wire 	  header_i_tvalid, header_i_tready;
+   wire [63:0] 	  body_i_tdata;
+   wire 	  body_i_tlast, body_i_tvalid, body_i_tready;
+   
+   wire [127:0]   header_o_tdata;
+   wire 	  header_o_tvalid, header_o_tready;
+   wire [63:0] 	  body_o_tdata;
+   wire 	  body_o_tlast, body_o_tvalid, body_o_tready;
+   reg [15:0] 	  length;
+   reg [11:0] 	  seqnum;
+
+   assign i_tready = header_i_tready & body_i_tready;
+   assign header_i_tvalid = i_tlast & i_tvalid & i_tready;
+   assign body_i_tlast = i_tlast;
+
+   // Handle 32 and 64 widths
+   generate
+     if (WIDTH == 32) begin
+       reg even;
+       always @(posedge clk)
+         if(reset | clear)
+           even <= 0;
+         else
+           if(i_tvalid & i_tready)
+             if(i_tlast)
+               even <= 0;
+             else
+              even <= ~even;
+
+       reg [31:0]     held_i_tdata;
+       always @(posedge clk) begin
+         if (i_tvalid & i_tready) held_i_tdata <= i_tdata;
+       end
+       assign body_i_tvalid = i_tvalid & i_tready & (i_tlast | even);
+       assign body_i_tdata  = even ? { held_i_tdata, i_tdata } : {i_tdata, i_tdata}; // really should be 0 in bottom, but this simplifies mux
+     end else begin
+       assign body_i_tvalid = i_tvalid;
+       assign body_i_tdata  = i_tdata;
+     end
+   endgenerate
+
+   // FIXME handle lengths of partial 32-bit words
+   always @(posedge clk)
+     if(reset | clear)
+       length <= (WIDTH == 32) ? 4 : 8;
+     else if(header_i_tready & header_i_tvalid)
+       length <= (WIDTH == 32) ? 4 : 8;
+     else if(i_tvalid & i_tready)
+       length <= (WIDTH == 32) ? length + 4 : length + 8;
+
+   axi_fifo_flop2 #(.WIDTH(128)) header_fifo_flop2
+     (.clk(clk), .reset(reset), .clear(clear),
+      .i_tdata({i_tuser[127:112],length,i_tuser[95:0]}), .i_tvalid(header_i_tvalid), .i_tready(header_i_tready),
+      .o_tdata(header_o_tdata), .o_tvalid(header_o_tvalid), .o_tready(header_o_tready),
+      .occupied(), .space());
+
+   axi_fifo #(.WIDTH(65), .SIZE(SIZE)) body_fifo
+     (.clk(clk), .reset(reset), .clear(clear),
+      .i_tdata({body_i_tlast,body_i_tdata}), .i_tvalid(body_i_tvalid), .i_tready(body_i_tready),
+      .o_tdata({body_o_tlast,body_o_tdata}), .o_tvalid(body_o_tvalid), .o_tready(body_o_tready),
+      .occupied(), .space());
+     
+   reg [3:0] 	  chdr_state;
+   localparam ST_IDLE = 0;
+   localparam ST_HEAD = 1;
+   localparam ST_TIME = 2;
+   localparam ST_BODY = 3;
+
+   always @(posedge clk)
+     if(reset | clear)
+       chdr_state <= ST_IDLE;
+     else
+       case(chdr_state)
+	 ST_IDLE :
+	   if(header_o_tvalid & body_o_tvalid)
+	     chdr_state <= ST_HEAD;
+	 ST_HEAD :
+	   if(o_tready)
+	     if(header_o_tdata[125])   // time
+	       chdr_state <= ST_TIME;
+	     else
+	       chdr_state <= ST_BODY;
+	 ST_TIME :
+	   if(o_tready)
+	     chdr_state <= ST_BODY;
+	 ST_BODY :
+	   if(o_tready & body_o_tlast)
+	     chdr_state <= ST_IDLE;
+       endcase // case (chdr_state)
+
+   always @(posedge clk)
+     if(reset | clear)
+       seqnum <= 12'd0;
+     else
+       if(o_tvalid & o_tready & o_tlast)
+	 seqnum <= seqnum + 12'd1;
+   
+   wire [15:0] 	  out_length = header_o_tdata[111:96] + (header_o_tdata[125] ? 16'd16 : 16'd8);
+   
+   assign o_tvalid = (chdr_state == ST_HEAD) | (chdr_state == ST_TIME) | (body_o_tvalid & (chdr_state == ST_BODY));
+   assign o_tlast = (chdr_state == ST_BODY) & body_o_tlast;
+   assign o_tdata = (chdr_state == ST_HEAD) ? {header_o_tdata[127:124], (USE_SEQ_NUM ? header_o_tdata[123:112] : seqnum), out_length, header_o_tdata[95:64] } :
+		    (chdr_state == ST_TIME) ? header_o_tdata[63:0] :
+		    body_o_tdata;
+   assign body_o_tready = (chdr_state == ST_BODY) & o_tready;
+   assign header_o_tready = ((chdr_state == ST_TIME) | ((chdr_state == ST_HEAD) & ~header_o_tdata[125])) & o_tready;
+   	 
+endmodule // chdr_framer
diff --git a/fpga/usrp3/lib/rfnoc/chdr_framer_2clk.v b/fpga/usrp3/lib/rfnoc/chdr_framer_2clk.v
new file mode 100644
index 000000000..4c430fbff
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/chdr_framer_2clk.v
@@ -0,0 +1,146 @@
+/////////////////////////////////////////////////////////////////////
+//
+// Copyright 2018 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: chdr_framer_2clk
+// Description:
+//  - Takes a sample stream in and uses the tuser input to frame
+//    a CHDR packet which is output by the module
+//    samples at the output
+//  - FIXME Currently only 32 / 64-bit input widths are supported.
+//
+/////////////////////////////////////////////////////////////////////
+
+module chdr_framer_2clk #(
+  parameter SIZE        = 10,
+  parameter WIDTH       = 32,  // 32 or 64 only! TODO: Extend to other widths.
+  parameter USE_SEQ_NUM = 0   // Use provided seq number in tuser
+) (
+  input samp_clk, input samp_rst, input pkt_clk, input pkt_rst,
+  input [WIDTH-1:0] i_tdata, input [127:0] i_tuser, input i_tlast, input i_tvalid, output i_tready,
+  output [63:0] o_tdata, output o_tlast, output o_tvalid, input o_tready
+);
+
+  wire          header_i_tvalid, header_i_tready;
+  wire [63:0]   body_i_tdata;
+  wire          body_i_tlast, body_i_tvalid, body_i_tready;
+
+  wire [127:0]  header_o_tdata;
+  wire          header_o_tvalid, header_o_tready;
+  wire [63:0]   body_o_tdata;
+  wire          body_o_tlast, body_o_tvalid, body_o_tready;
+  reg  [15:0]   length;
+  reg  [11:0]   seqnum;
+
+  assign i_tready = header_i_tready & body_i_tready;
+  assign header_i_tvalid = i_tlast & i_tvalid & i_tready;
+  assign body_i_tlast = i_tlast;
+
+  // Handle 32 and 64 widths
+  generate
+    if (WIDTH == 32) begin
+     reg even = 1'b0;
+     always @(posedge samp_clk)
+       if(samp_rst)
+         even <= 1'b0;
+       else
+         if(i_tvalid & i_tready)
+           if(i_tlast)
+             even <= 1'b0;
+           else
+             even <= ~even;
+
+     reg [31:0] held_i_tdata;
+     always @(posedge samp_clk) begin
+       if (i_tvalid & i_tready) held_i_tdata <= i_tdata;
+     end
+     assign body_i_tvalid = i_tvalid & i_tready & (i_tlast | even);
+     assign body_i_tdata  = even ? { held_i_tdata, i_tdata } : {i_tdata, i_tdata}; // really should be 0 in bottom, but this simplifies mux
+    end else begin
+     assign body_i_tvalid = i_tvalid & i_tready;
+     assign body_i_tdata  = i_tdata;
+    end
+  endgenerate
+
+  // FIXME handle lengths of partial 32-bit words
+  always @(posedge samp_clk)
+    if (samp_rst)
+      length <= (WIDTH == 32) ? 16'd4 : 16'd8;
+    else if(header_i_tready & header_i_tvalid)
+      length <= (WIDTH == 32) ? 16'd4 : 16'd8;
+    else if(i_tvalid & i_tready)
+      length <= (WIDTH == 32) ? length + 16'd4 : length + 16'd8;
+
+  // Extended reset signal to ensure longer reset on axi_fifo_2clk
+  // as recommended by Xilinx. It clears all partial packets seen
+  // after clearing the fifos.
+  // This pulse stretch ratio works in this case and may not work
+  // for all clocks.
+  wire samp_rst_stretch;
+  pulse_stretch #(.SCALE('d10)) samp_reset_i (
+    .clk(samp_clk),
+    .rst(1'b0),
+    .pulse(samp_rst),
+    .pulse_stretched(samp_rst_stretch)
+  );
+
+  axi_fifo_2clk #(.WIDTH(128), .SIZE(5)) hdr_fifo_i (
+    .i_aclk(samp_clk), .o_aclk(pkt_clk), .reset(samp_rst_stretch),
+    .i_tdata({i_tuser[127:112],length,i_tuser[95:0]}), .i_tvalid(header_i_tvalid), .i_tready(header_i_tready),
+    .o_tdata(header_o_tdata), .o_tvalid(header_o_tvalid), .o_tready(header_o_tready)
+  );
+
+  axi_fifo_2clk #(.WIDTH(65), .SIZE(SIZE)) body_fifo_i (
+    .i_aclk(samp_clk), .o_aclk(pkt_clk), .reset(samp_rst_stretch),
+    .i_tdata({body_i_tlast,body_i_tdata}), .i_tvalid(body_i_tvalid), .i_tready(body_i_tready),
+    .o_tdata({body_o_tlast,body_o_tdata}), .o_tvalid(body_o_tvalid), .o_tready(body_o_tready)
+  );
+
+  reg [1:0] chdr_state;
+  localparam [1:0] ST_IDLE = 0;
+  localparam [1:0] ST_HEAD = 1;
+  localparam [1:0] ST_TIME = 2;
+  localparam [1:0] ST_BODY = 3;
+
+  always @(posedge pkt_clk)
+    if(pkt_rst)
+      chdr_state <= ST_IDLE;
+    else
+      case(chdr_state)
+      ST_IDLE :
+        if(header_o_tvalid & body_o_tvalid)
+          chdr_state <= ST_HEAD;
+      ST_HEAD :
+        if(o_tready)
+          if(header_o_tdata[125])  // time
+            chdr_state <= ST_TIME;
+          else
+            chdr_state <= ST_BODY;
+      ST_TIME :
+        if(o_tready)
+          chdr_state <= ST_BODY;
+      ST_BODY :
+        if(o_tready & body_o_tlast)
+          chdr_state <= ST_IDLE;
+      endcase
+
+  always @(posedge pkt_clk)
+    if(pkt_rst)
+      seqnum <= 12'd0;
+    else
+      if(o_tvalid & o_tready & o_tlast)
+        seqnum <= seqnum + 12'd1;
+
+  wire [15:0] out_length = header_o_tdata[111:96] + (header_o_tdata[125] ? 16'd16 : 16'd8);
+
+  assign o_tvalid = (chdr_state == ST_HEAD) | (chdr_state == ST_TIME) | (body_o_tvalid & (chdr_state == ST_BODY));
+  assign o_tlast = (chdr_state == ST_BODY) & body_o_tlast;
+  assign o_tdata = (chdr_state == ST_HEAD) ? {header_o_tdata[127:124], (USE_SEQ_NUM == 1 ? header_o_tdata[123:112] : seqnum), out_length, header_o_tdata[95:64] } :
+                     (chdr_state == ST_TIME) ? header_o_tdata[63:0] :
+                        body_o_tdata;
+  assign body_o_tready = (chdr_state == ST_BODY) & o_tready;
+  assign header_o_tready = ((chdr_state == ST_TIME) | ((chdr_state == ST_HEAD) & ~header_o_tdata[125])) & o_tready;
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/chdr_pkt_types.vh b/fpga/usrp3/lib/rfnoc/chdr_pkt_types.vh
new file mode 100644
index 000000000..204390cfc
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/chdr_pkt_types.vh
@@ -0,0 +1,11 @@
+// CHDR Packet types
+// [2:1]: Type
+//   [0]: EOB
+localparam [2:0] DATA_PKT     = 3'b000;
+localparam [2:0] DATA_EOB_PKT = 3'b001;
+localparam [2:0] FC_RESP_PKT  = 3'b010;
+localparam [2:0] FC_ACK_PKT   = 3'b011;
+localparam [2:0] CMD_PKT      = 3'b100;
+localparam [2:0] CMD_EOB_PKT  = 3'b101;  // Unused
+localparam [2:0] RESP_PKT     = 3'b110;
+localparam [2:0] RESP_ERR_PKT = 3'b111;
diff --git a/fpga/usrp3/lib/rfnoc/cic_decimate.v b/fpga/usrp3/lib/rfnoc/cic_decimate.v
new file mode 100644
index 000000000..6a723d88e
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/cic_decimate.v
@@ -0,0 +1,148 @@
+//
+// Copyright 2016 Ettus Research
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module cic_decimate #(
+  parameter WIDTH = 16,
+  parameter N = 4,
+  parameter MAX_RATE = 256
+)(
+  input clk,
+  input reset,
+  input rate_stb,
+  input [$clog2(MAX_RATE+1)-1:0] rate, // +1 due to $clog2() rounding
+  input strobe_in,
+  output reg strobe_out,
+  input last_in,
+  output reg last_out,
+  input [WIDTH-1:0] signal_in,
+  output reg [WIDTH-1:0] signal_out
+);
+
+  wire [WIDTH+(N*$clog2(MAX_RATE+1))-1:0] signal_in_ext;
+  reg  [WIDTH+(N*$clog2(MAX_RATE+1))-1:0] integrator [0:N-1];
+  reg  [WIDTH+(N*$clog2(MAX_RATE+1))-1:0] differentiator [0:N-1];
+  reg  [WIDTH+(N*$clog2(MAX_RATE+1))-1:0] pipeline [0:N-1];
+  reg  [WIDTH+(N*$clog2(MAX_RATE+1))-1:0] sampler;
+  reg  [N-1:0] last_integ;
+  reg          last_integ_hold;
+  reg  [N-1:0] last_diff;
+  reg          last_sampler;
+  reg  [N-1:0] strobe_integ;
+  reg          strobe_sampler;
+  reg  [N-1:0] strobe_diff;
+
+  integer i;
+
+  sign_extend #(WIDTH,WIDTH+(N*$clog2(MAX_RATE+1))) ext_input (.in(signal_in),.out(signal_in_ext));
+
+  // Integrate
+  always @(posedge clk) begin
+    if (reset) begin
+      last_integ        <= 0;
+      last_integ_hold   <= 0;
+      for (i = 0; i < N; i = i + 1) begin
+        integrator[i]   <= 0;
+        strobe_integ[i] <= 0;
+      end
+    end else begin
+      strobe_integ      <= {strobe_integ[N-2:0],strobe_in};
+      if (strobe_in) begin
+        last_integ[0]   <= last_in;
+        integrator[0]   <= integrator[0] + signal_in_ext;
+      end
+      for (i = 1; i < N; i = i + 1) begin
+        if (strobe_integ[i-1]) begin
+          last_integ[i] <= last_integ[i-1];
+          integrator[i] <= integrator[i] + integrator[i-1];
+        end
+      end
+      if (last_integ[N-1] & ~strobe_sampler) begin
+        last_integ_hold <= 1'b1;
+      end else if (strobe_sampler) begin
+        last_integ_hold <= 1'b0;
+      end
+    end
+  end
+
+  // Sampler strobe
+  reg [$clog2(MAX_RATE+1)-1:0] counter;
+  always @(posedge clk) begin
+    if (reset) begin
+      counter        <= rate;
+      strobe_sampler <= 1'b0;
+      last_sampler   <= 1'b0;
+      sampler        <= 'd0;
+    end else begin
+      strobe_sampler <= 1'b0;
+      last_sampler   <= 1'b0;
+      if (rate_stb) begin
+        counter          <= rate;
+      end else if (strobe_integ[N-1]) begin
+        if (counter <= 1) begin
+          counter        <= rate;
+          strobe_sampler <= 1'b1;
+          last_sampler   <= last_integ[N-1] | last_integ_hold;
+          sampler        <= integrator[N-1];
+        end else begin
+          counter        <= counter - 1;
+        end
+      end
+    end
+  end
+
+  // Differentiate
+  always @(posedge clk) begin
+    if (reset) begin
+      last_diff          <= 0;
+      for (i = 0; i < N; i = i + 1) begin
+        pipeline[i]       <= 0;
+        differentiator[i] <= 0;
+        strobe_diff       <= 0;
+      end
+    end else begin
+      strobe_diff         <= {strobe_diff[N-2:0], strobe_sampler};
+      if (strobe_sampler) begin
+        last_diff[0]      <= last_sampler;
+        differentiator[0] <= sampler;
+        pipeline[0]       <= sampler - differentiator[0];
+      end
+      for (i = 1; i < N; i = i + 1) begin
+        if (strobe_diff[i-1]) begin
+          last_diff[i]      <= last_diff[i-1];
+          differentiator[i] <= pipeline[i-1];
+          pipeline[i]       <= pipeline[i-1] - differentiator[i];
+        end
+      end
+    end
+  end
+
+  genvar l;
+  wire [WIDTH-1:0] signal_out_shifted[0:MAX_RATE];
+  generate
+    for (l = 1; l <= MAX_RATE; l = l + 1) begin
+      // N*log2(rate), $clog2(rate) = ceil(log2(rate)) which rounds to nearest shift without overflow
+      assign signal_out_shifted[l] = pipeline[N-1][$clog2(l**N)+WIDTH-1:$clog2(l**N)];
+    end
+  endgenerate
+  assign signal_out_shifted[0] = pipeline[N-1][WIDTH-1:0];
+
+  // Output register
+  always @(posedge clk) begin
+    if (reset) begin
+      last_out   <= 1'b0;
+      strobe_out <= 1'b0;
+      signal_out <= 'd0;
+    end else begin
+      strobe_out <= strobe_diff[N-1];
+      if (strobe_diff[N-1]) begin
+        last_out   <= last_diff[N-1];
+        signal_out <= signal_out_shifted[rate];
+      end
+    end
+  end
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/cic_interpolate.v b/fpga/usrp3/lib/rfnoc/cic_interpolate.v
new file mode 100644
index 000000000..d59e973fc
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/cic_interpolate.v
@@ -0,0 +1,132 @@
+//
+// Copyright 2016 Ettus Research
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module cic_interpolate #(
+  parameter WIDTH = 16,
+  parameter N = 4,
+  parameter MAX_RATE = 128
+)(
+  input clk,
+  input reset,
+  input rate_stb,
+  input [$clog2(MAX_RATE+1)-1:0] rate, // +1 due to $clog2() rounding
+  input  strobe_in,
+  output reg strobe_out,
+  input [WIDTH-1:0] signal_in,
+  output reg [WIDTH-1:0] signal_out
+);
+
+  wire [WIDTH+$clog2(MAX_RATE**(N-1))-1:0] signal_in_ext;
+  reg  [WIDTH+$clog2(MAX_RATE**(N-1))-1:0] integrator [0:N-1];
+  reg  [WIDTH+$clog2(MAX_RATE**(N-1))-1:0] differentiator [0:N-1];
+  reg  [WIDTH+$clog2(MAX_RATE**(N-1))-1:0] pipeline [0:N-1];
+  reg  [WIDTH+$clog2(MAX_RATE**(N-1))-1:0] sampler;
+
+  reg  [N-1:0] strobe_diff;
+  reg  [N-1:0] strobe_integ;
+  reg          strobe_sampler;
+
+  integer i;
+
+  sign_extend #(WIDTH,WIDTH+$clog2(MAX_RATE**(N-1))) ext_input (.in(signal_in),.out(signal_in_ext));
+
+  // Differentiate
+  always @(posedge clk) begin
+    if (reset) begin
+      strobe_diff         <= 'd0;
+      for (i = 0; i < N; i = i + 1) begin
+        differentiator[i] <= 0;
+        pipeline[i]       <= 0;
+      end
+    end else begin
+      strobe_diff         <= {strobe_diff[N-2:0], strobe_in};
+      if (strobe_in) begin
+        differentiator[0] <= signal_in_ext;
+        pipeline[0]       <= signal_in_ext - differentiator[0];
+      end
+      for (i = 1; i < N; i = i + 1) begin
+        if (strobe_diff[i-1]) begin
+          differentiator[i] <= pipeline[i-1];
+          pipeline[i]       <= pipeline[i-1] - differentiator[i];
+        end
+      end
+    end
+  end
+
+  // Strober
+  reg [$clog2(MAX_RATE+1)-1:0] counter;
+  wire strobe_out_int;
+
+  always @(posedge clk) begin
+    if (reset | rate_stb) begin
+      counter <= rate;
+    end else if (strobe_diff[N-1]) begin
+      counter <= rate - 1;
+    end else begin
+      if (counter == 0) begin
+        counter <= rate;
+      end else if (counter < rate) begin
+        counter <= counter - 1;
+      end
+    end
+  end
+
+  assign strobe_out_int = (counter < rate) & ~rate_stb;
+
+  // Integrate
+  always @(posedge clk) begin
+    if (reset) begin
+      strobe_sampler    <= 1'b0;
+      strobe_integ      <= 'd0;
+      for (i = 0; i < N; i = i + 1) begin
+        integrator[i]   <= 0;
+      end
+    end else begin
+      strobe_sampler      <= strobe_diff[N-1];
+      if (strobe_diff[N-1]) begin
+        sampler           <= pipeline[N-1];
+      end
+      strobe_integ        <= {strobe_integ[N-2:0],strobe_out_int};
+      if (strobe_sampler) begin
+        integrator[0] <= integrator[0] + sampler;
+      end
+      for (i = 1; i < N; i = i + 1) begin
+        if (strobe_integ[i-1]) begin
+          integrator[i] <= integrator[i] + integrator[i-1];
+        end
+      end
+    end
+  end
+
+  genvar l;
+  wire [WIDTH-1:0] signal_out_shifted[0:MAX_RATE];
+  wire signal_out_shifted_strobe[0:MAX_RATE];
+  generate
+    for (l = 0; l <= MAX_RATE; l = l + 1) begin
+      axi_round #(
+        .WIDTH_IN((l == 0 || l == 1) ? WIDTH : $clog2(l**(N-1))+WIDTH),
+        .WIDTH_OUT(WIDTH))
+      axi_round (
+        .clk(clk), .reset(reset),
+        .i_tdata((l == 0 || l == 1) ? integrator[N-1][WIDTH-1:0] : integrator[N-1][$clog2(l**(N-1))+WIDTH-1:0]),
+        .i_tlast(1'b0), .i_tvalid(strobe_integ[N-1]), .i_tready(),
+        .o_tdata(signal_out_shifted[l]), .o_tlast(), .o_tvalid(signal_out_shifted_strobe[l]), .o_tready(1'b1));
+    end
+  endgenerate
+
+  // Output register
+  always @(posedge clk) begin
+    if (reset) begin
+      strobe_out <= 1'b0;
+      signal_out <= 'd0;
+    end else begin
+      strobe_out <= signal_out_shifted_strobe[0]; // Any of the strobes will work here
+      signal_out <= signal_out_shifted[rate];
+    end
+  end
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/cmul.v b/fpga/usrp3/lib/rfnoc/cmul.v
new file mode 100644
index 000000000..1acb1a8cc
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/cmul.v
@@ -0,0 +1,23 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// This block exists only to wrap the Xilinx IP which has a different interface
+//   Xilinx puts Q in the high bits, I in the low bits, and inverts reset
+
+module cmul
+  (input clk, input reset,
+   input [31:0] a_tdata, input a_tlast, input a_tvalid, output a_tready,
+   input [31:0] b_tdata, input b_tlast, input b_tvalid, output b_tready,
+   output [63:0] o_tdata, output o_tlast, output o_tvalid, input o_tready);
+
+   complex_multiplier complex_multiplier
+     (.aclk(clk), .aresetn(~reset),
+      .s_axis_a_tdata({a_tdata[15:0], a_tdata[31:16]}), .s_axis_a_tlast(a_tlast), .s_axis_a_tvalid(a_tvalid), .s_axis_a_tready(a_tready),
+      .s_axis_b_tdata({b_tdata[15:0], b_tdata[31:16]}), .s_axis_b_tlast(b_tlast), .s_axis_b_tvalid(b_tvalid), .s_axis_b_tready(b_tready),
+      .s_axis_ctrl_tdata(8'd0), .s_axis_ctrl_tvalid(1'b1), .s_axis_ctrl_tready(),
+      .m_axis_dout_tdata({o_tdata[31:0], o_tdata[63:32]}), .m_axis_dout_tlast(o_tlast), .m_axis_dout_tvalid(o_tvalid), .m_axis_dout_tready(o_tready));
+
+endmodule // cmul
diff --git a/fpga/usrp3/lib/rfnoc/complex_invert.v b/fpga/usrp3/lib/rfnoc/complex_invert.v
new file mode 100644
index 000000000..800b5dc97
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/complex_invert.v
@@ -0,0 +1,157 @@
+//
+// Copyright 2015 Ettus Research LLC
+//
+// General complex invert algorithm:
+//   1        1      a - bi     a - bi          a          bi
+// ------ = ------ * ------ = ----------- = --------- - ---------
+// a + bi   a + bi   a - bi   a^2 + b^2     a^2 + b^2   a^2 + b^2
+//
+
+module complex_invert
+(
+  input clk, input reset, input clear,
+  input  [31:0] i_tdata, input  i_tlast, input  i_tvalid, output i_tready,
+  output [31:0] o_tdata, output o_tlast, output o_tvalid, input  o_tready);
+
+  wire [15:0] a_tdata;
+  wire [31:0] a_tdata_int;
+  wire        a_tlast;
+  wire        a_tvalid;
+  wire        a_tready;
+  wire [15:0] b_tdata;
+  wire [31:0] b_tdata_int;
+  wire        b_tlast;
+  wire        b_tvalid;
+  wire        b_tready;
+  wire [31:0] a_b_tdata;
+  wire        a_b_tlast;
+  wire        a_b_tvalid;
+  wire        a_b_tready;
+
+  // Replicate input data into three streams with FIFOing to account for varying latency on the paths
+  split_stream_fifo #(
+    .WIDTH(32),
+    .ACTIVE_MASK(4'b0111),
+    .FIFO_SIZE(5))
+  input_split_stream_fifo0 (
+    .clk(clk), .reset(reset), .clear(clear),
+    .i_tdata(i_tdata), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready),
+    .o0_tdata(a_tdata_int), .o0_tlast(a_tlast), .o0_tvalid(a_tvalid), .o0_tready(a_tready),
+    .o1_tdata(b_tdata_int), .o1_tlast(b_tlast), .o1_tvalid(b_tvalid), .o1_tready(b_tready),
+    .o2_tdata(a_b_tdata), .o2_tlast(a_b_tlast), .o2_tvalid(a_b_tvalid), .o2_tready(a_b_tready),
+    .o3_tdata(), .o3_tlast(), .o3_tvalid(), .o3_tready(1'b0));
+
+  assign a_tdata = a_tdata_int[31:16];
+  assign b_tdata = b_tdata_int[15:0];
+
+  wire [31:0] a2_plus_b2_tdata;
+  wire        a2_plus_b2_tlast;
+  wire        a2_plus_b2_tvalid;
+  wire        a2_plus_b2_tready;
+
+  // a^2 + b^2
+  complex_to_magsq
+  a2_p_b2_complex_to_magsq (
+    .clk(clk), .reset(reset), .clear(clear),
+    .i_tdata(a_b_tdata), .i_tlast(a_b_tlast), .i_tvalid(a_b_tvalid), .i_tready(a_b_tready),
+    .o_tdata(a2_plus_b2_tdata), .o_tlast(a2_plus_b2_tlast), .o_tvalid(a2_plus_b2_tvalid), .o_tready(a2_plus_b2_tready));
+
+  wire [31:0] a2_plus_b2_0_tdata;
+  wire        a2_plus_b2_0_tlast;
+  wire        a2_plus_b2_0_tvalid;
+  wire        a2_plus_b2_0_tready;
+  wire [31:0] a2_plus_b2_1_tdata;
+  wire        a2_plus_b2_1_tlast;
+  wire        a2_plus_b2_1_tvalid;
+  wire        a2_plus_b2_1_tready;
+
+  // Replicate two a^2 + b^2 streams for dividers
+  split_stream_fifo #(
+    .WIDTH(32),
+    .ACTIVE_MASK(4'b0011),
+    .FIFO_SIZE(5))
+  input_split_stream_fifo1 (
+    .clk(clk), .reset(reset), .clear(clear),
+    .i_tdata(a2_plus_b2_tdata), .i_tlast(a2_plus_b2_tlast), .i_tvalid(a2_plus_b2_tvalid), .i_tready(a2_plus_b2_tready),
+    .o0_tdata(a2_plus_b2_0_tdata), .o0_tlast(a2_plus_b2_0_tlast), .o0_tvalid(a2_plus_b2_0_tvalid), .o0_tready(a2_plus_b2_0_tready),
+    .o1_tdata(a2_plus_b2_1_tdata), .o1_tlast(a2_plus_b2_1_tlast), .o1_tvalid(a2_plus_b2_1_tvalid), .o1_tready(a2_plus_b2_1_tready),
+    .o2_tdata(), .o2_tlast(), .o2_tvalid(), .o2_tready(1'b0),
+    .o3_tdata(), .o3_tlast(), .o3_tvalid(), .o3_tready(1'b0));
+
+  wire        div_by_zero_a;
+  wire [47:0] a_div_a2_plus_b2_tdata_int; // signed bit, 15 integer bits, fraction sign bit, 31 fraction
+  wire [47:0] a_div_a2_plus_b2_tdata = div_by_zero_a ? 48'd0 : a_div_a2_plus_b2_tdata_int;
+  wire        a_div_a2_plus_b2_tlast;
+  wire        a_div_a2_plus_b2_tvalid;
+  wire        a_div_a2_plus_b2_tready;
+
+  //     a
+  // ---------
+  // a^2 + b^2
+  // Warning: Divider does not sign extend fractional part into the integer part, although we throw away the integer
+  //          part so this issue does not affect our design.
+  divide_int16_int32
+  a_div_a2_plus_b2_divider (
+    .aclk(clk), .aresetn(~reset),
+    .s_axis_divisor_tdata(a2_plus_b2_0_tdata), .s_axis_divisor_tlast(a2_plus_b2_0_tlast), .s_axis_divisor_tvalid(a2_plus_b2_0_tvalid), .s_axis_divisor_tready(a2_plus_b2_0_tready),
+    .s_axis_dividend_tdata(a_tdata), .s_axis_dividend_tlast(a_tlast), .s_axis_dividend_tvalid(a_tvalid), .s_axis_dividend_tready(a_tready),
+    .m_axis_dout_tdata(a_div_a2_plus_b2_tdata_int), .m_axis_dout_tlast(a_div_a2_plus_b2_tlast), .m_axis_dout_tvalid(a_div_a2_plus_b2_tvalid), .m_axis_dout_tready(a_div_a2_plus_b2_tready),
+    .m_axis_dout_tuser(div_by_zero_a));
+
+  wire [15:0] neg_b_tdata;
+  wire        neg_b_tlast;
+  wire        neg_b_tvalid;
+  wire        neg_b_tready;
+  wire [15:0] neg_b = (b_tdata == -16'sd32768) ? 16'sd32767 : (~b_tdata + 1'b1);
+
+  // Negate b
+  axi_fifo_flop #(.WIDTH(17))
+  neg_b_axi_fifo_flop (
+    .clk(clk), .reset(reset), .clear(clear),
+    .i_tdata({b_tlast,neg_b}), .i_tvalid(b_tvalid), .i_tready(b_tready),
+    .o_tdata({neg_b_tlast,neg_b_tdata}), .o_tvalid(neg_b_tvalid), .o_tready(neg_b_tready),
+    .space(), .occupied());
+
+  wire        div_by_zero_b;
+  wire [47:0] neg_b_div_a2_plus_b2_tdata_int;
+  wire [47:0] neg_b_div_a2_plus_b2_tdata = div_by_zero_b ? 48'd0 : neg_b_div_a2_plus_b2_tdata_int;
+  wire        neg_b_div_a2_plus_b2_tlast;
+  wire        neg_b_div_a2_plus_b2_tvalid;
+  wire        neg_b_div_a2_plus_b2_tready;
+
+  //     bi
+  // ---------
+  // a^2 + b^2
+  divide_int16_int32
+  neg_b_div_a2_plus_b2_divider (
+    .aclk(clk), .aresetn(~reset),
+    .s_axis_divisor_tdata(a2_plus_b2_1_tdata), .s_axis_divisor_tlast(a2_plus_b2_1_tlast), .s_axis_divisor_tvalid(a2_plus_b2_1_tvalid), .s_axis_divisor_tready(a2_plus_b2_1_tready),
+    .s_axis_dividend_tdata(neg_b_tdata), .s_axis_dividend_tlast(neg_b_tlast), .s_axis_dividend_tvalid(neg_b_tvalid), .s_axis_dividend_tready(neg_b_tready),
+    .m_axis_dout_tdata(neg_b_div_a2_plus_b2_tdata_int), .m_axis_dout_tlast(neg_b_div_a2_plus_b2_tlast), .m_axis_dout_tvalid(neg_b_div_a2_plus_b2_tvalid), .m_axis_dout_tready(neg_b_div_a2_plus_b2_tready),
+    .m_axis_dout_tuser(div_by_zero_b));
+
+  // Throw away integer part as the result will always be a fraction due to a^2 + b^2 > a (or b)
+  wire [63:0] one_div_a_plus_bi_tdata = {a_div_a2_plus_b2_tdata[31:0],neg_b_div_a2_plus_b2_tdata[31:0]};
+  wire        one_div_a_plus_bi_tlast;
+  wire        one_div_a_plus_bi_tvalid;
+  wire        one_div_a_plus_bi_tready;
+
+  // Join into one word
+  axi_join #(
+    .INPUTS(2))
+  inst_axi_join (
+   .i_tlast({a_div_a2_plus_b2_tlast,neg_b_div_a2_plus_b2_tlast}), .i_tvalid({a_div_a2_plus_b2_tvalid,neg_b_div_a2_plus_b2_tvalid}), .i_tready({a_div_a2_plus_b2_tready,neg_b_div_a2_plus_b2_tready}),
+   .o_tlast(one_div_a_plus_bi_tlast), .o_tvalid(one_div_a_plus_bi_tvalid), .o_tready(one_div_a_plus_bi_tready));
+
+  // Truncate to a complex int16
+  axi_round_and_clip_complex #(
+    .WIDTH_IN(32),
+    .WIDTH_OUT(16),
+    .CLIP_BITS(11), // Calibrated value
+    .FIFOSIZE())
+  inst_axi_round_and_clip_complex (
+    .clk(clk), .reset(reset),
+    .i_tdata(one_div_a_plus_bi_tdata), .i_tlast(one_div_a_plus_bi_tlast), .i_tvalid(one_div_a_plus_bi_tvalid), .i_tready(one_div_a_plus_bi_tready),
+    .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready));
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/complex_to_mag_approx.v b/fpga/usrp3/lib/rfnoc/complex_to_mag_approx.v
new file mode 100644
index 000000000..7455afcad
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/complex_to_mag_approx.v
@@ -0,0 +1,136 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Fast magnitude approximation.
+// 
+// ALPHA_DENOM & BETA_DENOM should be a power of 2
+// Multiplierless if ALPHA_NUM & BETA_NUM are 1
+//
+// Mag ~= Alpha * max(|I|, |Q|) + Beta * min(|I|, |Q|)
+//
+// (table taken from http://www.dspguru.com/dsp/tricks/magnitude-estimator)
+// =========================================
+// Alpha  Beta       Avg Err   RMS   Peak
+//                   (linear)  (dB)  (dB)
+// -----------------------------------------
+// 1,     1/2        -0.086775 -20.7 -18.6
+// 1,     1/4         0.006456 -27.6 -18.7
+// 1,     11/32      -0.028505 -28.0 -24.8
+// 1,     3/8        -0.040159 -26.4 -23.4
+// 15/16, 15/32      -0.018851 -29.2 -24.1
+// 15/16, 1/2        -0.030505 -26.9 -24.1
+// 31/32, 11/32      -0.000371 -31.6 -22.9
+// 31/32, 3/8        -0.012024 -31.4 -26.1
+// 61/64, 3/8         0.002043 -32.5 -24.3
+// 61/64, 13/32       0.009611 -31.8 -26.6
+// =========================================
+//
+// Input: Complex, Output: Unsigned Int
+
+`ifndef LOG2
+`define LOG2(N) ( \
+   N < 2    ? 0 : \
+   N < 4    ? 1 : \
+   N < 8    ? 2 : \
+   N < 16   ? 3 : \
+   N < 32   ? 4 : \
+   N < 64   ? 5 : \
+   N < 128  ? 6 : \
+   N < 256  ? 7 : \
+   N < 512  ? 8 : \
+   N < 1024 ? 9 : \
+              10)
+`endif
+
+module complex_to_mag_approx #(
+  parameter ALPHA_NUM = 1,
+  parameter ALPHA_DENOM = 1,
+  parameter BETA_NUM = 1,
+  parameter BETA_DENOM = 4,
+  parameter LATENCY = 3, // 0, 1, 2, or 3
+  parameter SAMP_WIDTH = 16)
+(
+  input clk, input reset, input clear,
+  input [2*SAMP_WIDTH-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
+  output [SAMP_WIDTH-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready
+);
+
+  wire [2*SAMP_WIDTH-1:0] pipeline_i_tdata[0:2], pipeline_o_tdata[0:2];
+  wire [2:0] pipeline_i_tvalid, pipeline_i_tlast, pipeline_i_tready;
+  wire [2:0] pipeline_o_tvalid, pipeline_o_tlast, pipeline_o_tready;
+  wire signed [SAMP_WIDTH-1:0] i, q, max, max_int, min, min_int;
+  wire [SAMP_WIDTH-1:0] i_abs, q_abs, i_abs_int, q_abs_int, mag;
+
+
+  // Absolute value
+  assign i = i_tdata[2*SAMP_WIDTH-1:SAMP_WIDTH];
+  assign q = i_tdata[SAMP_WIDTH-1:0];
+  assign i_abs_int = i[SAMP_WIDTH-1] ? (~i + 1'b1) : i;
+  assign q_abs_int = q[SAMP_WIDTH-1] ? (~q + 1'b1) : q;
+
+
+  // First stage pipeline
+  assign pipeline_i_tdata[0]  = {i_abs_int,q_abs_int};
+  assign pipeline_i_tlast[0]  = i_tlast;
+  assign pipeline_i_tvalid[0] = i_tvalid;
+  assign pipeline_o_tready[0] = pipeline_i_tready[1];
+
+  axi_fifo_flop #(.WIDTH(SAMP_WIDTH*2+1))
+  pipeline0_axi_fifo_flop (
+    .clk(clk), .reset(reset), .clear(clear),
+    .i_tdata({pipeline_i_tlast[0],pipeline_i_tdata[0]}), .i_tvalid(pipeline_i_tvalid[0]), .i_tready(pipeline_i_tready[0]),
+    .o_tdata({pipeline_o_tlast[0],pipeline_o_tdata[0]}), .o_tvalid(pipeline_o_tvalid[0]), .o_tready(pipeline_o_tready[0]));
+
+
+  // Max & Min
+  assign i_abs = (LATENCY == 3) ? pipeline_o_tdata[0][2*SAMP_WIDTH-1:SAMP_WIDTH] : i_abs;
+  assign q_abs = (LATENCY == 3) ? pipeline_o_tdata[0][SAMP_WIDTH-1:0]            : q_abs;
+  assign max_int = (i_abs > q_abs) ? i_abs : q_abs;
+  assign min_int = (i_abs > q_abs) ? q_abs : i_abs;
+
+
+  // Second stage pipeline
+  assign pipeline_i_tdata[1]  = {max_int,min_int};
+  assign pipeline_i_tlast[1]  = (LATENCY == 2) ? i_tlast              : pipeline_o_tlast[0];
+  assign pipeline_i_tvalid[1] = (LATENCY == 2) ? i_tvalid             : pipeline_o_tvalid[0];
+  assign pipeline_o_tready[1] = pipeline_i_tready[2];
+
+  axi_fifo_flop #(.WIDTH(SAMP_WIDTH*2+1))
+  pipeline1_axi_fifo_flop (
+    .clk(clk), .reset(reset), .clear(clear),
+    .i_tdata({pipeline_i_tlast[1],pipeline_i_tdata[1]}), .i_tvalid(pipeline_i_tvalid[1]), .i_tready(pipeline_i_tready[1]),
+    .o_tdata({pipeline_o_tlast[1],pipeline_o_tdata[1]}), .o_tvalid(pipeline_o_tvalid[1]), .o_tready(pipeline_o_tready[1]));
+
+
+  // Magnitude Approx
+  assign max = (LATENCY >= 2) ? pipeline_o_tdata[1][2*SAMP_WIDTH-1:SAMP_WIDTH] : max_int;
+  assign min = (LATENCY >= 2) ? pipeline_o_tdata[1][SAMP_WIDTH-1:0]            : min_int;
+  assign mag = ALPHA_NUM * {{`LOG2(ALPHA_DENOM){1'b0}},max[SAMP_WIDTH-1:`LOG2(ALPHA_DENOM)]} +
+                BETA_NUM * {{`LOG2( BETA_DENOM){1'b0}},min[SAMP_WIDTH-1:`LOG2( BETA_DENOM)]};
+
+
+  // Third stage pipeline
+  assign pipeline_i_tdata[2][SAMP_WIDTH-1:0] = mag;
+  assign pipeline_i_tlast[2]  = (LATENCY == 1) ? i_tlast  : pipeline_o_tlast[1];
+  assign pipeline_i_tvalid[2] = (LATENCY == 1) ? i_tvalid : pipeline_o_tvalid[1];
+  assign pipeline_o_tready[2] = o_tready;
+
+  axi_fifo_flop #(.WIDTH(SAMP_WIDTH+1))
+  pipeline2_axi_fifo_flop (
+    .clk(clk), .reset(reset), .clear(clear),
+    .i_tdata({pipeline_i_tlast[2],pipeline_i_tdata[2][SAMP_WIDTH-1:0]}), .i_tvalid(pipeline_i_tvalid[2]), .i_tready(pipeline_i_tready[2]),
+    .o_tdata({pipeline_o_tlast[2],pipeline_o_tdata[2][SAMP_WIDTH-1:0]}), .o_tvalid(pipeline_o_tvalid[2]), .o_tready(pipeline_o_tready[2]));
+
+
+  // Output based on LATENCY mux
+  assign o_tdata  = (LATENCY == 0) ? mag      : pipeline_o_tdata[2][SAMP_WIDTH-1:0];
+  assign o_tlast  = (LATENCY == 0) ? i_tlast  : pipeline_o_tlast[2];
+  assign o_tvalid = (LATENCY == 0) ? i_tvalid : pipeline_o_tvalid[2];
+  assign i_tready = (LATENCY == 0) ? o_tready : 
+                    (LATENCY == 1) ? pipeline_i_tready[2] :
+                    (LATENCY == 2) ? pipeline_i_tready[1] : pipeline_i_tready[0];
+
+endmodule
\ No newline at end of file
diff --git a/fpga/usrp3/lib/rfnoc/complex_to_magsq.v b/fpga/usrp3/lib/rfnoc/complex_to_magsq.v
new file mode 100644
index 000000000..8f0d5ea47
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/complex_to_magsq.v
@@ -0,0 +1,57 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module complex_to_magsq #(
+  parameter WIDTH = 16)
+(
+  input clk, input reset, input clear,
+  input [2*WIDTH-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
+  output [2*WIDTH-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready);
+
+   wire [WIDTH-1:0]    ii_tdata, iq_tdata;
+   wire 	       ii_tlast, ii_tvalid, ii_tready, iq_tlast, iq_tvalid, iq_tready;
+
+   wire [2*WIDTH-1:0]    i_sq_tdata;
+   wire 	       i_sq_tlast, i_sq_tvalid, i_sq_tready;
+
+   split_complex #(.WIDTH(WIDTH)) split_complex
+     (.i_tdata(i_tdata), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready),
+      .oi_tdata(ii_tdata), .oi_tlast(ii_tlast), .oi_tvalid(ii_tvalid), .oi_tready(ii_tready), 
+      .oq_tdata(iq_tdata), .oq_tlast(iq_tlast), .oq_tvalid(iq_tvalid), .oq_tready(iq_tready),
+      .error());
+      
+  // i^2
+  mult #(
+   .WIDTH_A(WIDTH),
+   .WIDTH_B(WIDTH),
+   .WIDTH_P(2*WIDTH),
+   .DROP_TOP_P(5),
+   .LATENCY(2),       // NOTE: If using CASCADE_OUT, set to 3
+   .CASCADE_OUT(0))   // FIXME can use cascade once we get ISE to accept it
+  i_sq_mult (
+    .clk(clk), .reset(reset),
+    .a_tdata(ii_tdata), .a_tlast(ii_tlast), .a_tvalid(ii_tvalid), .a_tready(ii_tready),
+    .b_tdata(ii_tdata), .b_tlast(ii_tlast), .b_tvalid(ii_tvalid), .b_tready(),
+    .p_tdata(i_sq_tdata), .p_tlast(i_sq_tlast), .p_tvalid(i_sq_tvalid), .p_tready(i_sq_tready));
+
+  // q^2 + i^2
+  mult_add #(
+   .WIDTH_A(WIDTH),
+   .WIDTH_B(WIDTH),
+   .WIDTH_P(2*WIDTH),
+   .DROP_TOP_P(5),
+   .LATENCY(4),
+   .CASCADE_IN(0),   // FIXME this can be 1 once we get ISE to accept cascading
+   .CASCADE_OUT(0))
+  q_sq_mult (
+    .clk(clk), .reset(reset),
+    .a_tdata(iq_tdata), .a_tlast(iq_tlast), .a_tvalid(iq_tvalid), .a_tready(iq_tready),
+    .b_tdata(iq_tdata), .b_tlast(iq_tlast), .b_tvalid(iq_tvalid), .b_tready(),
+    .c_tdata(i_sq_tdata), .c_tlast(i_sq_tlast), .c_tvalid(i_sq_tvalid), .c_tready(i_sq_tready),
+    .p_tdata(o_tdata), .p_tlast(o_tlast), .p_tvalid(o_tvalid), .p_tready(o_tready));
+
+endmodule
\ No newline at end of file
diff --git a/fpga/usrp3/lib/rfnoc/conj.v b/fpga/usrp3/lib/rfnoc/conj.v
new file mode 100644
index 000000000..85d78f1d1
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/conj.v
@@ -0,0 +1,20 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// NOTE -- does not flop the output.  could cause timing issues, so follow with axi_fifo_flop if you need it
+
+module conj
+  #(parameter WIDTH=16)
+   (input clk, input reset, input clear,
+    input [2*WIDTH-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
+    output [2*WIDTH-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready);
+
+   assign o_tdata = { i_tdata[2*WIDTH-1:WIDTH] , -i_tdata[WIDTH-1:0] };
+   assign o_tlast = i_tlast;
+   assign o_tvalid = i_tvalid;
+   assign i_tready = o_tready;
+   
+endmodule // conj
diff --git a/fpga/usrp3/lib/rfnoc/const.v b/fpga/usrp3/lib/rfnoc/const.v
new file mode 100644
index 000000000..0345ad406
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/const.v
@@ -0,0 +1,30 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module const
+  #(parameter WIDTH=32)
+   (input clk, input reset,
+    input [WIDTH-1:0] config_tdata, input config_tlast, input config_tvalid, output config_tready,
+    output [WIDTH-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready);
+
+   reg [WIDTH-1:0]     const_val;
+
+   always @(posedge clk)
+     if(reset)
+       const_val <= 0;
+     else
+       if(config_tvalid & config_tready)
+	 const_val <= config_tdata;
+
+   assign config_tready = 1'b1;
+   // FIXME do we want to sync constant change to tlasts?
+   
+   assign o_tdata = const_val;
+   assign o_tlast = 1'b0; // FIXME do we want something else here?
+   assign o_tvalid = 1'b1; // caution -- will fill up a fifo
+   
+endmodule // const
diff --git a/fpga/usrp3/lib/rfnoc/const_sreg.v b/fpga/usrp3/lib/rfnoc/const_sreg.v
new file mode 100644
index 000000000..1bb9d711c
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/const_sreg.v
@@ -0,0 +1,24 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module const_sreg
+  #(parameter BASE=0,
+    parameter WIDTH=32)
+   (input clk, input reset,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    output [WIDTH-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready);
+
+   wire [WIDTH-1:0]     const_val;
+   
+   setting_reg #(.my_addr(BASE), .width(WIDTH)) reg_max
+     (.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data), .out(const_val));
+
+   assign o_tdata = const_val;
+   assign o_tlast = 1'b0; // FIXME do we want something else here?
+   assign o_tvalid = 1'b1; // caution -- will fill up a fifo
+   
+endmodule // const_sreg
diff --git a/fpga/usrp3/lib/rfnoc/core/Makefile.srcs b/fpga/usrp3/lib/rfnoc/core/Makefile.srcs
new file mode 100644
index 000000000..0a646f98b
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/core/Makefile.srcs
@@ -0,0 +1,39 @@
+#
+# Copyright 2018 Ettus Research, A National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+##################################################
+# RFNoC Core Sources
+##################################################
+RFNOC_CORE_HEADERS = $(abspath $(addprefix $(BASE_DIR)/../lib/rfnoc/core/, \
+rfnoc_chdr_utils.vh \
+rfnoc_axis_ctrl_utils.vh \
+rfnoc_chdr_internal_utils.vh \
+ctrlport.vh \
+))
+
+RFNOC_CORE_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/rfnoc/core/, \
+axis_ctrl_endpoint.v \
+axis_ctrl_master.v \
+axis_ctrl_slave.v \
+chdr_compute_tkeep.v \
+chdr_to_chdr_data.v \
+chdr_to_axis_pyld_ctxt.v \
+chdr_to_axis_data_mdata.v \
+chdr_to_axis_data.v \
+axis_pyld_ctxt_to_chdr.v \
+axis_data_mdata_to_chdr.v \
+axis_data_to_chdr.v \
+chdr_ingress_fifo.v \
+chdr_mgmt_pkt_handler.v \
+chdr_data_swapper.v \
+chdr_stream_endpoint.v \
+chdr_stream_input.v \
+chdr_stream_output.v \
+chdr_to_axis_ctrl.v \
+ctrlport_endpoint.v \
+backend_iface.v \
+rfnoc_core_kernel.v \
+))
diff --git a/fpga/usrp3/lib/rfnoc/core/axis_ctrl_endpoint.v b/fpga/usrp3/lib/rfnoc/core/axis_ctrl_endpoint.v
new file mode 100644
index 000000000..e1ded42aa
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/core/axis_ctrl_endpoint.v
@@ -0,0 +1,116 @@
+//
+// Copyright 2018-2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: axis_ctrl_endpoint
+// Description:
+//   A bidirectional AXIS-Control to AXIS-Control converter.
+//   Use this module in noc_shell to interface between the user
+//   logic and the rfnoc infrastructure when both interfaces use
+//   AXIS-Control.
+//
+// Parameters:
+//   - SYNC_CLKS: Is rfnoc_ctrl_clk and axis_ctrl_clk the same clock?
+//   - SLAVE_FIFO_SIZE: The depth of the slave FIFO. Note that the 
+//                      slave FIFO will also buffer master responses.
+//
+// Signals:
+//   - *_rfnoc_ctrl_* : Input/output AXIS-Control from/to the framework
+//   - *_axis_ctrl_*  : Input/output AXIS-Control from/to the user
+
+module axis_ctrl_endpoint #(
+  parameter       SYNC_CLKS       = 0,
+  parameter       SLAVE_FIFO_SIZE = 5
+)(
+  // Clocks, Resets, Misc
+  input  wire         rfnoc_ctrl_clk,
+  input  wire         rfnoc_ctrl_rst,
+  input  wire         axis_ctrl_clk,
+  input  wire         axis_ctrl_rst,
+  // AXIS-Control Bus (RFNoC infrastructure)
+  input  wire [31:0]  s_rfnoc_ctrl_tdata,
+  input  wire         s_rfnoc_ctrl_tlast,
+  input  wire         s_rfnoc_ctrl_tvalid,
+  output wire         s_rfnoc_ctrl_tready,
+  output wire [31:0]  m_rfnoc_ctrl_tdata,
+  output wire         m_rfnoc_ctrl_tlast,
+  output wire         m_rfnoc_ctrl_tvalid,
+  input  wire         m_rfnoc_ctrl_tready,
+  // AXIS-Control Bus (User logic)
+  input  wire [31:0]  s_axis_ctrl_tdata,
+  input  wire         s_axis_ctrl_tlast,
+  input  wire         s_axis_ctrl_tvalid,
+  output wire         s_axis_ctrl_tready,
+  output wire [31:0]  m_axis_ctrl_tdata,
+  output wire         m_axis_ctrl_tlast,
+  output wire         m_axis_ctrl_tvalid,
+  input  wire         m_axis_ctrl_tready
+);
+
+  // ---------------------------------------------------
+  //  RFNoC Includes
+  // ---------------------------------------------------
+  `include "rfnoc_chdr_utils.vh"
+  `include "rfnoc_axis_ctrl_utils.vh"
+
+  // ---------------------------------------------------
+  //  Clock Crossing
+  // ---------------------------------------------------
+
+  wire [31:0] i_ctrl_tdata;
+  wire        i_ctrl_tlast, i_ctrl_tvalid, i_ctrl_tready;
+
+  generate
+    if (SYNC_CLKS) begin
+      axi_fifo #(.WIDTH(32+1), .SIZE(SLAVE_FIFO_SIZE)) in_fifo_i (
+        .clk(axis_ctrl_clk), .reset(axis_ctrl_rst), .clear(1'b0),
+        .i_tdata({s_rfnoc_ctrl_tlast, s_rfnoc_ctrl_tdata}),
+        .i_tvalid(s_rfnoc_ctrl_tvalid), .i_tready(s_rfnoc_ctrl_tready),
+        .o_tdata({i_ctrl_tlast, i_ctrl_tdata}),
+        .o_tvalid(i_ctrl_tvalid), .o_tready(i_ctrl_tready),
+        .space(), .occupied()
+      );
+
+      axi_fifo #(.WIDTH(32+1), .SIZE(1)) out_fifo_i (
+        .clk(axis_ctrl_clk), .reset(axis_ctrl_rst), .clear(1'b0),
+        .i_tdata({s_axis_ctrl_tlast, s_axis_ctrl_tdata}),
+        .i_tvalid(s_axis_ctrl_tvalid), .i_tready(s_axis_ctrl_tready),
+        .o_tdata({m_rfnoc_ctrl_tlast, m_rfnoc_ctrl_tdata}),
+        .o_tvalid(m_rfnoc_ctrl_tvalid), .o_tready(m_rfnoc_ctrl_tready),
+        .space(), .occupied()
+      );
+    end else begin
+      axi_fifo_2clk #(.WIDTH(32+1), .SIZE(SLAVE_FIFO_SIZE), .PIPELINE("NONE")) in_fifo_i (
+        .reset(rfnoc_ctrl_rst),
+        .i_aclk(rfnoc_ctrl_clk),
+        .i_tdata({s_rfnoc_ctrl_tlast, s_rfnoc_ctrl_tdata}),
+        .i_tvalid(s_rfnoc_ctrl_tvalid), .i_tready(s_rfnoc_ctrl_tready),
+        .o_aclk(axis_ctrl_clk),
+        .o_tdata({i_ctrl_tlast, i_ctrl_tdata}),
+        .o_tvalid(i_ctrl_tvalid), .o_tready(i_ctrl_tready)
+      );
+
+      axi_fifo_2clk #(.WIDTH(32+1), .SIZE(1), .PIPELINE("NONE")) out_fifo_i (
+        .reset(axis_ctrl_rst),
+        .i_aclk(axis_ctrl_clk),
+        .i_tdata({s_axis_ctrl_tlast, s_axis_ctrl_tdata}),
+        .i_tvalid(s_axis_ctrl_tvalid), .i_tready(s_axis_ctrl_tready),
+        .o_aclk(rfnoc_ctrl_clk),
+        .o_tdata({m_rfnoc_ctrl_tlast, m_rfnoc_ctrl_tdata}),
+        .o_tvalid(m_rfnoc_ctrl_tvalid), .o_tready(m_rfnoc_ctrl_tready)
+      );
+    end
+  endgenerate
+
+  axi_fifo #(.WIDTH(32+1), .SIZE(1)) slv_pipe_i (
+    .clk(axis_ctrl_clk), .reset(axis_ctrl_rst), .clear(1'b0),
+    .i_tdata({i_ctrl_tlast, i_ctrl_tdata}),
+    .i_tvalid(i_ctrl_tvalid), .i_tready(i_ctrl_tready),
+    .o_tdata({m_axis_ctrl_tlast, m_axis_ctrl_tdata}),
+    .o_tvalid(m_axis_ctrl_tvalid), .o_tready(m_axis_ctrl_tready),
+    .space(), .occupied()
+  );
+
+endmodule // axis_ctrl_endpoint
+
diff --git a/fpga/usrp3/lib/rfnoc/core/axis_ctrl_master.v b/fpga/usrp3/lib/rfnoc/core/axis_ctrl_master.v
new file mode 100644
index 000000000..19ae98f52
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/core/axis_ctrl_master.v
@@ -0,0 +1,316 @@
+//
+// Copyright 2018-2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: axis_ctrl_master
+// Description:
+//  This module implements an AXIS-Control master (and a Control-Port
+//  slave). Requests are accepted on the slave Control-Port, converted
+//  to AXIS-Control requests, then sent over the master AXI-Stream port.
+//  Responses are received on the AXI-Stream slave port, and converted
+//  to Control-Port responses.
+//  NOTE: Transactions are not buffered so there is no need for flow 
+//        control or throttling.
+//
+// Parameters:
+//   - THIS_PORTID     : The local port-ID of this control port
+//
+// Signals:
+//   - s_axis_ctrl_*   : Input control stream (AXI-Stream) for responses
+//   - m_axis_ctrl_*   : Output control stream (AXI-Stream) for requests
+//   - ctrlport_req_*  : Control-port master request port
+//   - ctrlport_resp_* : Control-port master response port
+
+module axis_ctrl_master #(
+  parameter [9:0] THIS_PORTID = 10'd0
+)(
+  // Clock and reset
+  input  wire         clk,
+  input  wire         rst,
+  // AXIS-Control Bus (Response)
+  input  wire [31:0]  s_axis_ctrl_tdata,
+  input  wire         s_axis_ctrl_tlast,
+  input  wire         s_axis_ctrl_tvalid,
+  output wire         s_axis_ctrl_tready,
+  // AXIS-Control Bus (Request)
+  output reg  [31:0]  m_axis_ctrl_tdata,
+  output wire         m_axis_ctrl_tlast,
+  output wire         m_axis_ctrl_tvalid,
+  input  wire         m_axis_ctrl_tready,
+  // Control Port Endpoint (Request)
+  input  wire         ctrlport_req_wr,
+  input  wire         ctrlport_req_rd,
+  input  wire [19:0]  ctrlport_req_addr,
+  input  wire [9:0]   ctrlport_req_portid,
+  input  wire [15:0]  ctrlport_req_rem_epid,
+  input  wire [9:0]   ctrlport_req_rem_portid,
+  input  wire [31:0]  ctrlport_req_data,
+  input  wire [3:0]   ctrlport_req_byte_en,
+  input  wire         ctrlport_req_has_time,
+  input  wire [63:0]  ctrlport_req_time,
+  // Control Port Endpoint (Response)
+  output wire         ctrlport_resp_ack,
+  output wire [1:0]   ctrlport_resp_status,
+  output wire [31:0]  ctrlport_resp_data
+);
+
+  // ---------------------------------------------------
+  //  RFNoC Includes
+  // ---------------------------------------------------
+  `include "rfnoc_chdr_utils.vh"
+  `include "rfnoc_axis_ctrl_utils.vh"
+
+  // ---------------------------------------------------
+  //  State Machine
+  // ---------------------------------------------------
+  localparam [3:0] ST_IDLE          = 4'd0;   // Waiting for a request on slave ctrlport
+  localparam [3:0] ST_REQ_HDR_LO    = 4'd1;   // Sending AXIS-Control request header (low bits)
+  localparam [3:0] ST_REQ_HDR_HI    = 4'd2;   // Sending AXIS-Control request header (high bits)
+  localparam [3:0] ST_REQ_TS_LO     = 4'd3;   // Sending AXIS-Control request timestamp (low bits)
+  localparam [3:0] ST_REQ_TS_HI     = 4'd4;   // Sending AXIS-Control request timestamp (high bits)
+  localparam [3:0] ST_REQ_OP_WORD   = 4'd5;   // Sending AXIS-Control request operation word
+  localparam [3:0] ST_REQ_OP_DATA   = 4'd6;   // Sending AXIS-Control request data word
+  localparam [3:0] ST_RESP_HDR_LO   = 4'd7;   // Receiving AXIS-Control response header (low bits)
+  localparam [3:0] ST_RESP_HDR_HI   = 4'd8;   // Receiving AXIS-Control response header (high bits)
+  localparam [3:0] ST_RESP_TS_LO    = 4'd9;   // Receiving AXIS-Control response timestamp (low bits)
+  localparam [3:0] ST_RESP_TS_HI    = 4'd10;  // Receiving AXIS-Control response timestamp (high bits)
+  localparam [3:0] ST_RESP_OP_WORD  = 4'd11;  // Receiving AXIS-Control response operation word
+  localparam [3:0] ST_RESP_OP_DATA  = 4'd12;  // Receiving AXIS-Control response data word     
+  localparam [3:0] ST_SHORT_PKT_ERR = 4'd13;  // Response was too short. Send a dummy response on ctrlport
+  localparam [3:0] ST_DROP_LONG_PKT = 4'd14;  // Response was too long. Dump the rest of the packet
+
+  // State variables
+  reg [3:0]   state = ST_IDLE;    // Current state for FSM
+  reg [5:0]   seq_num = 6'd0;     // Expected seqnum for response
+  // Request state
+  reg [3:0]   req_opcode;         // Cached opcode for transaction request
+  reg [19:0]  req_addr;           // Cached address for transaction request
+  reg [9:0]   req_portid;         // Cached port ID for transaction request
+  reg [15:0]  req_rem_epid;       // Cached remote endpoint ID for transaction request
+  reg [9:0]   req_rem_portid;     // Cached remote port ID for transaction request
+  reg [31:0]  req_data;           // Cached data word for transaction request
+  reg [3:0]   req_byte_en;        // Cached byte enable for transaction request
+  reg         req_has_time;       // Cached has_time bit for transaction request
+  reg [63:0]  req_time;           // Cached timestamp for transaction request
+  // Response state
+  reg         resp_has_time;      // Does the response have a timestamp?
+  reg [1:0]   resp_status;        // The status in the response
+  reg         resp_seq_err, resp_cmd_err; // Error bits for the response
+
+  always @(posedge clk) begin
+    if (rst) begin
+      state <= ST_IDLE;
+      seq_num <= 6'd0;
+    end else begin
+      case (state)
+
+        // Ready to receive a request on ctrlport
+        // ------------------------------------
+        ST_IDLE: begin
+          if (ctrlport_req_wr | ctrlport_req_rd) begin
+            // A transaction was posted on the slave ctrlport...
+            // Cache the opcode
+            if (ctrlport_req_wr & ctrlport_req_rd)
+              req_opcode   <= AXIS_CTRL_OPCODE_WRITE_READ;
+            else if (ctrlport_req_rd)
+              req_opcode   <= AXIS_CTRL_OPCODE_READ;
+            else
+              req_opcode   <= AXIS_CTRL_OPCODE_WRITE;
+            // Cache transaction info
+            req_addr       <= ctrlport_req_addr;
+            req_portid     <= ctrlport_req_portid;
+            req_rem_epid   <= ctrlport_req_rem_epid;
+            req_rem_portid <= ctrlport_req_rem_portid;
+            req_data       <= ctrlport_req_data;
+            req_byte_en    <= ctrlport_req_byte_en;
+            req_has_time   <= ctrlport_req_has_time;
+            req_time       <= ctrlport_req_time;
+            // Start sending out AXIS-Ctrl packet
+            state <= ST_REQ_HDR_LO;
+          end
+        end
+
+        // Send a request AXIS comand
+        // (a state for each stage in the packet)
+        // ------------------------------------
+        ST_REQ_HDR_LO: begin
+          if (m_axis_ctrl_tready)
+            state <= ST_REQ_HDR_HI;
+        end
+        ST_REQ_HDR_HI: begin
+          if (m_axis_ctrl_tready)
+            state <= req_has_time ? ST_REQ_TS_LO : ST_REQ_OP_WORD;
+        end
+        ST_REQ_TS_LO: begin
+          if (m_axis_ctrl_tready)
+            state <= ST_REQ_TS_HI;
+        end
+        ST_REQ_TS_HI: begin
+          if (m_axis_ctrl_tready)
+            state <= ST_REQ_OP_WORD;
+        end
+        ST_REQ_OP_WORD: begin
+          if (m_axis_ctrl_tready)
+            state <= ST_REQ_OP_DATA;
+        end
+        ST_REQ_OP_DATA: begin
+          if (m_axis_ctrl_tready)
+            state <= ST_RESP_HDR_LO;
+        end
+
+        // Receive a response AXIS comand
+        // (a state for each stage in the packet)
+        // ------------------------------------
+        ST_RESP_HDR_LO: begin
+          if (s_axis_ctrl_tvalid) begin
+            // Remeber if the packet is supposed to have a timestamp
+            resp_has_time <= axis_ctrl_get_has_time(s_axis_ctrl_tdata);
+            // Check for a sequence error
+            resp_seq_err <= (axis_ctrl_get_seq_num(s_axis_ctrl_tdata) != seq_num);
+            // Assert a command error if:
+            // - The port ID does not match
+            // - The response was too short (the next check)
+            resp_cmd_err <= (axis_ctrl_get_dst_port(s_axis_ctrl_tdata) != THIS_PORTID);
+            if (!s_axis_ctrl_tlast) begin
+              state <= ST_RESP_HDR_HI;
+            end else begin
+              // Response was too short
+              resp_cmd_err <= 1'b1;
+              state <= ST_SHORT_PKT_ERR;
+            end
+          end
+        end
+        ST_RESP_HDR_HI: begin
+          if (s_axis_ctrl_tvalid) begin
+            if (!s_axis_ctrl_tlast) begin
+              state <= resp_has_time ? ST_RESP_TS_LO : ST_RESP_OP_WORD;
+            end else begin
+              // Response was too short
+              resp_cmd_err <= 1'b1;
+              state <= ST_SHORT_PKT_ERR;
+            end
+          end
+        end
+        ST_RESP_TS_LO: begin
+          if (s_axis_ctrl_tvalid) begin
+            if (!s_axis_ctrl_tlast) begin
+              state <= ST_RESP_TS_HI;
+            end else begin
+              // Response was too short
+              resp_cmd_err <= 1'b1;
+              state <= ST_SHORT_PKT_ERR;
+            end
+          end
+        end
+        ST_RESP_TS_HI: begin
+          if (s_axis_ctrl_tvalid) begin
+            if (!s_axis_ctrl_tlast) begin
+              state <= ST_RESP_OP_WORD;
+            end else begin
+              // Response was too short
+              resp_cmd_err <= 1'b1;
+              state <= ST_SHORT_PKT_ERR;
+            end
+          end
+        end
+        ST_RESP_OP_WORD: begin
+          if (s_axis_ctrl_tvalid) begin
+            if (!s_axis_ctrl_tlast) begin
+              // Assert a command error if opcode and addr in request does not match response
+              resp_cmd_err <= resp_cmd_err ||
+                              (axis_ctrl_get_opcode(s_axis_ctrl_tdata) != req_opcode) ||
+                              (axis_ctrl_get_address(s_axis_ctrl_tdata) != req_addr);
+              resp_status <= axis_ctrl_get_status(s_axis_ctrl_tdata);
+              state <= ST_RESP_OP_DATA;
+            end else begin
+              // Response was too short
+              resp_cmd_err <= 1'b1;
+              state <= ST_SHORT_PKT_ERR;
+            end
+          end
+        end
+        ST_RESP_OP_DATA: begin
+          if (s_axis_ctrl_tvalid) begin
+            // If the packet was too long then just drop the rest without complaining
+            state <= s_axis_ctrl_tlast ? ST_IDLE : ST_DROP_LONG_PKT;
+            seq_num <= seq_num + 6'd1;
+          end
+        end
+
+        // Error handling states
+        // ------------------------------------
+        ST_SHORT_PKT_ERR: begin
+          state <= ST_IDLE;
+        end
+        ST_DROP_LONG_PKT: begin
+          if (s_axis_ctrl_tvalid && s_axis_ctrl_tlast)
+            state <= ST_IDLE;
+        end
+
+        default: begin
+          // We should never get here
+          state <= ST_IDLE;
+        end
+      endcase
+    end
+  end
+
+  // Logic to drive m_axis_ctrl_*
+  // ------------------------------------
+  always @(*) begin
+    case (state)
+      ST_REQ_HDR_LO: begin
+        m_axis_ctrl_tdata = axis_ctrl_build_hdr_lo(
+          1'b0 /* is_ack*/, req_has_time, seq_num,
+          4'd1 /* num_data */, THIS_PORTID, req_portid);
+      end
+      ST_REQ_HDR_HI: begin
+        m_axis_ctrl_tdata = axis_ctrl_build_hdr_hi(
+          req_rem_portid, req_rem_epid);
+      end
+      ST_REQ_TS_LO: begin
+        m_axis_ctrl_tdata = req_time[31:0];
+      end
+      ST_REQ_TS_HI: begin
+        m_axis_ctrl_tdata = req_time[63:32];
+      end
+      ST_REQ_OP_WORD: begin
+        m_axis_ctrl_tdata = axis_ctrl_build_op_word(
+          AXIS_CTRL_STS_OKAY, req_opcode, req_byte_en, req_addr);
+      end
+      ST_REQ_OP_DATA: begin
+        m_axis_ctrl_tdata = req_data;
+      end
+      default: begin
+        m_axis_ctrl_tdata = 32'h0;
+      end
+    endcase
+  end
+  assign m_axis_ctrl_tvalid = (state == ST_REQ_HDR_LO)  ||
+                              (state == ST_REQ_HDR_HI)  ||
+                              (state == ST_REQ_TS_LO)   ||
+                              (state == ST_REQ_TS_HI)   ||
+                              (state == ST_REQ_OP_WORD) ||
+                              (state == ST_REQ_OP_DATA);
+  assign m_axis_ctrl_tlast  = (state == ST_REQ_OP_DATA);
+
+  // Logic to backpressure responses
+  // ------------------------------------
+  assign s_axis_ctrl_tready = (state == ST_RESP_HDR_LO)  ||
+                              (state == ST_RESP_HDR_HI)  ||
+                              (state == ST_RESP_TS_LO)   ||
+                              (state == ST_RESP_TS_HI)   ||
+                              (state == ST_RESP_OP_WORD) ||
+                              (state == ST_RESP_OP_DATA) ||
+                              (state == ST_DROP_LONG_PKT);
+
+  // Logic to drive Control-port response
+  // ------------------------------------
+  assign ctrlport_resp_ack    = (state == ST_RESP_OP_DATA && s_axis_ctrl_tvalid) || 
+                                (state == ST_SHORT_PKT_ERR); 
+  assign ctrlport_resp_status = resp_cmd_err ? AXIS_CTRL_STS_CMDERR : 
+                                  (resp_seq_err ? AXIS_CTRL_STS_WARNING : resp_status);
+  assign ctrlport_resp_data   = (state == ST_SHORT_PKT_ERR) ? 32'h0 : s_axis_ctrl_tdata;
+
+endmodule // axis_ctrl_master
diff --git a/fpga/usrp3/lib/rfnoc/core/axis_ctrl_slave.v b/fpga/usrp3/lib/rfnoc/core/axis_ctrl_slave.v
new file mode 100644
index 000000000..558d21be2
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/core/axis_ctrl_slave.v
@@ -0,0 +1,333 @@
+//
+// Copyright 2018-2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: axis_ctrl_slave
+// Description:
+//  This module implements an AXIS-Control slave (and a Control-Port
+//  master). Requests are accepted on the slave axis port and responses
+//  are sent out on the master axis port. This module implements the
+//  following operations: {SLEEP, READ, WRITE}. All other operations
+//  will be treated as a nop and the output will throw a CMDERR.
+//
+// Parameters:
+//   None
+//
+// Signals:
+//   - s_axis_ctrl_*   : Input control stream (AXI-Stream) for requests
+//   - m_axis_ctrl_*   : Output control stream (AXI-Stream) for responses
+//   - ctrlport_req_*  : Control-port master request port
+//   - ctrlport_resp_* : Control-port master response port
+
+module axis_ctrl_slave (
+  // CHDR Bus (master and slave)
+  input  wire         clk,
+  input  wire         rst,
+  // AXIS-Control Bus (Request)
+  input  wire [31:0]  s_axis_ctrl_tdata,
+  input  wire         s_axis_ctrl_tlast,
+  input  wire         s_axis_ctrl_tvalid,
+  output wire         s_axis_ctrl_tready,
+  // AXIS-Control Bus (Response)
+  output wire [31:0]  m_axis_ctrl_tdata,
+  output wire         m_axis_ctrl_tlast,
+  output wire         m_axis_ctrl_tvalid,
+  input  wire         m_axis_ctrl_tready,
+  // Control Port Endpoint (Request)
+  output wire         ctrlport_req_wr,
+  output wire         ctrlport_req_rd,
+  output wire [19:0]  ctrlport_req_addr,
+  output wire [31:0]  ctrlport_req_data,
+  output wire [3:0]   ctrlport_req_byte_en,
+  output wire         ctrlport_req_has_time,
+  output wire [63:0]  ctrlport_req_time,
+  // Control Port Endpoint (Response)
+  input  wire         ctrlport_resp_ack,
+  input  wire [1:0]   ctrlport_resp_status,
+  input  wire [31:0]  ctrlport_resp_data
+);
+
+  // ---------------------------------------------------
+  //  RFNoC Includes
+  // ---------------------------------------------------
+  `include "rfnoc_chdr_utils.vh"
+  `include "rfnoc_axis_ctrl_utils.vh"
+
+  // ---------------------------------------------------
+  //  Width converters
+  // ---------------------------------------------------
+  // Convert 32-bit messages to 64 bits for ease of handling
+  // and buffering. Convert back to 32 bits.
+
+  wire [63:0] in64_tdata;
+  wire [1:0]  in64_tkeep;
+  wire        in64_tlast, in64_tvalid;
+  reg         in64_tready;
+
+  axis_width_conv #(
+    .WORD_W(32), .IN_WORDS(1), .OUT_WORDS(2),
+    .SYNC_CLKS(1), .PIPELINE("OUT")
+  ) upsizer_i (
+    .s_axis_aclk(clk), .s_axis_rst(rst),
+    .s_axis_tdata(s_axis_ctrl_tdata), .s_axis_tkeep(1'b1),
+    .s_axis_tlast(s_axis_ctrl_tlast),
+    .s_axis_tvalid(s_axis_ctrl_tvalid), .s_axis_tready(s_axis_ctrl_tready),
+    .m_axis_aclk(clk), .m_axis_rst(rst),
+    .m_axis_tdata(in64_tdata), .m_axis_tkeep(in64_tkeep),
+    .m_axis_tlast(in64_tlast),
+    .m_axis_tvalid(in64_tvalid), .m_axis_tready(in64_tready)
+  );
+
+  reg  [63:0] out64_tdata;
+  wire [1:0]  out64_tkeep;
+  reg         out64_tvalid;
+  wire        out64_tlast, out64_terror, out64_tready;
+
+  wire [63:0] out64_gt_tdata;
+  wire [1:0]  out64_gt_tkeep;
+  wire        out64_gt_tlast, out64_gt_tvalid, out64_gt_tready;
+
+  // The header of the response packet is generated
+  // immediately when a request is received but the data
+  // comes much later. The packet gate will smooth out the
+  // outgoing responses.
+
+  axi_packet_gate #(
+    .WIDTH(66), .SIZE(4)
+  ) gate_i (
+    .clk(clk), .reset(rst), .clear(1'b0),
+    .i_tdata({out64_tkeep, out64_tdata}), .i_tlast(out64_tlast),
+    .i_terror(out64_terror),
+    .i_tvalid(out64_tvalid), .i_tready(out64_tready),
+    .o_tdata({out64_gt_tkeep, out64_gt_tdata}), .o_tlast(out64_gt_tlast),
+    .o_tvalid(out64_gt_tvalid), .o_tready(out64_gt_tready)
+  );
+
+  axis_width_conv #(
+    .WORD_W(32), .IN_WORDS(2), .OUT_WORDS(1),
+    .SYNC_CLKS(1), .PIPELINE("IN")
+  ) downsizer_i (
+    .s_axis_aclk(clk), .s_axis_rst(rst),
+    .s_axis_tdata(out64_gt_tdata), .s_axis_tkeep(out64_gt_tkeep),
+    .s_axis_tlast(out64_gt_tlast),
+    .s_axis_tvalid(out64_gt_tvalid), .s_axis_tready(out64_gt_tready),
+    .m_axis_aclk(clk), .m_axis_rst(rst),
+    .m_axis_tdata(m_axis_ctrl_tdata), .m_axis_tkeep(/*unused*/),
+    .m_axis_tlast(m_axis_ctrl_tlast),
+    .m_axis_tvalid(m_axis_ctrl_tvalid), .m_axis_tready(m_axis_ctrl_tready)
+  );
+
+  // ---------------------------------------------------
+  //  Transaction Processor
+  // ---------------------------------------------------
+
+  localparam [2:0] ST_IN_HDR        = 3'd0;   // Transferring input header to output
+  localparam [2:0] ST_IN_TS         = 3'd1;   // Transferring input timestamp to output
+  localparam [2:0] ST_IN_OP_WORD    = 3'd2;   // Processing input control word 
+  localparam [2:0] ST_WAIT_FOR_ACK  = 3'd3;   // Waiting for a ctrlport response
+  localparam [2:0] ST_SLEEP         = 3'd4;   // Idle state for sleep operation
+  localparam [2:0] ST_OUT_OP_WORD   = 3'd5;   // Outputing control word after respose receipt
+  localparam [2:0] ST_MORE_DATA     = 3'd6;   // Control word is too long. Passing extra data forward
+  localparam [2:0] ST_DROP          = 3'd7;   // Something went wrong. Drop the current packet
+
+  // State variables
+  reg [2:0]   state = ST_IN_HDR;              // Current state of FSM
+  reg [31:0]  sleep_cntr = 32'd0;             // Counter to count sleep cycles
+  reg         cached_has_time = 1'b0;         // Cached "has_time" bit for input transaction request
+  reg [63:0]  cached_time;                    // Cached timestamp for input transaction request
+  reg [1:0]   resp_status;                    // Status for outgoing response
+  reg [31:0]  resp_data;                      // Data for outgoing response
+
+  // Sleep is an internal operation
+  wire ctrlport_req_sleep;
+
+  // Shortcuts (transaction request header)
+  wire        is_ack       = axis_ctrl_get_is_ack      (in64_tdata[31:0] );
+  wire        has_time     = axis_ctrl_get_has_time    (in64_tdata[31:0] );
+  wire [5:0]  seq_num      = axis_ctrl_get_seq_num     (in64_tdata[31:0] );
+  wire [3:0]  num_data     = axis_ctrl_get_num_data    (in64_tdata[31:0] );
+  wire [9:0]  src_port     = axis_ctrl_get_src_port    (in64_tdata[31:0] );
+  wire [9:0]  dst_port     = axis_ctrl_get_dst_port    (in64_tdata[31:0] );
+  wire [9:0]  rem_dst_port = axis_ctrl_get_rem_dst_port(in64_tdata[63:32]);
+  wire [15:0] rem_dst_epid = axis_ctrl_get_rem_dst_epid(in64_tdata[63:32]);
+  wire        malformed    = (is_ack || num_data == 4'd0);
+  // Shortcuts (transaction request op-word)
+  wire [19:0] xact_address = axis_ctrl_get_address(in64_tdata[31:0]);
+  wire [3:0]  xact_byte_en = axis_ctrl_get_byte_en(in64_tdata[31:0]);
+  wire [3:0]  xact_opcode  = axis_ctrl_get_opcode (in64_tdata[31:0]);
+  wire [31:0] xact_data    = in64_tdata[63:32];
+
+  always @(posedge clk) begin
+    if (rst) begin
+      state <= ST_IN_HDR;
+    end else begin
+      case (state)
+
+        // Receive an AXIS-Control request
+        // (a state for each stage in the packet)
+        // Except for the OP_WORD stage, the appropriate response
+        // line is also pushed to the output
+        // ------------------------------------
+        ST_IN_HDR: begin
+          if (in64_tvalid && in64_tready) begin
+            cached_has_time <= has_time;
+            if (!in64_tlast) begin
+              if (malformed)        // Malformed packet. Drop.
+                state <= ST_DROP;
+              else if (has_time)    // Pkt has a timestamp
+                state <= ST_IN_TS;
+              else                  // Pkt has no timestamp
+                state <= ST_IN_OP_WORD;
+            end else begin
+              // Premature termination
+              // out64_terror will be asserted to cancel the outgoing response
+              state <= ST_IN_HDR;
+            end
+          end
+        end
+        ST_IN_TS: begin
+          if (in64_tvalid && in64_tready) begin
+            cached_time <= in64_tdata;
+            if (!in64_tlast) begin
+              state <= ST_IN_OP_WORD;
+            end else begin
+              // Premature termination
+              // out64_terror will be asserted to cancel the outgoing response
+              state <= ST_IN_HDR;
+            end
+          end
+        end
+        ST_IN_OP_WORD: begin
+          if (in64_tvalid) begin
+            if (ctrlport_req_sleep) begin
+              state <= ST_SLEEP;
+              sleep_cntr <= xact_data;
+            end else if (ctrlport_req_rd | ctrlport_req_wr) begin
+              state <= ST_WAIT_FOR_ACK;
+            end else begin
+              // Treat all other operations as a NOP (1 cycle sleep)
+              state <= ST_SLEEP;
+              sleep_cntr <= 32'd0;
+              resp_status <= AXIS_CTRL_STS_CMDERR;
+            end
+          end
+        end
+
+        // Hold the input bus to implement a sleep
+        // ------------------------------------
+        ST_SLEEP: begin
+          if (sleep_cntr == 32'd0) begin
+            state <= ST_OUT_OP_WORD;
+            resp_data <= xact_data;
+            // We could get to this state for an invalid opcode so
+            // only update the status if this is a legit sleep op
+            if (xact_opcode == AXIS_CTRL_OPCODE_SLEEP)
+              resp_status <= AXIS_CTRL_STS_OKAY;
+          end else begin
+            sleep_cntr <= sleep_cntr - 32'd1;
+          end
+        end
+
+        // Wait for a response on the master ctrlport
+        // ------------------------------------
+        ST_WAIT_FOR_ACK: begin
+          if (ctrlport_resp_ack) begin
+            resp_status <= ctrlport_resp_status;
+            if (xact_opcode == AXIS_CTRL_OPCODE_READ ||
+                xact_opcode == AXIS_CTRL_OPCODE_WRITE_READ)
+              resp_data <= ctrlport_resp_data;
+            else
+              resp_data <= xact_data;
+            state <= ST_OUT_OP_WORD;
+          end
+        end
+
+        // Send the AXIS-Control response data
+        // ------------------------------------
+        ST_OUT_OP_WORD: begin
+          if (in64_tvalid && in64_tready) begin
+            state <= in64_tlast ? ST_IN_HDR : ST_MORE_DATA;
+          end
+        end
+
+        // Framing error handlers
+        // ------------------------------------
+        ST_MORE_DATA: begin
+          if (in64_tvalid && in64_tready && in64_tlast)
+            state <= ST_IN_HDR;
+        end
+        ST_DROP: begin
+          if (in64_tvalid && in64_tready && in64_tlast)
+            state <= ST_IN_HDR;
+        end
+
+        default: begin
+          // We should never get here
+          state <= ST_IN_HDR;
+        end
+      endcase
+    end
+  end
+
+  always @(*) begin
+    case (state)
+      ST_IN_HDR: begin      // Swap src/dst and add resp flag when passing header
+        in64_tready  = out64_tready;
+        out64_tdata  = {
+          axis_ctrl_build_hdr_hi(rem_dst_port, rem_dst_epid),
+          axis_ctrl_build_hdr_lo(1'b1, has_time, seq_num, num_data, dst_port, src_port)
+        };
+        out64_tvalid = in64_tvalid && !malformed;
+      end
+      ST_IN_TS: begin       // Pass input to the output without modification
+        in64_tready  = out64_tready;
+        out64_tdata  = in64_tdata;
+        out64_tvalid = in64_tvalid;
+      end
+      ST_OUT_OP_WORD: begin // Update status and data when passing op-word
+        in64_tready  = out64_tready;
+        out64_tdata  = {
+          resp_data, 
+          axis_ctrl_build_op_word(resp_status, xact_opcode, xact_byte_en, xact_address)
+        };
+        out64_tvalid = in64_tvalid;
+      end
+      ST_MORE_DATA: begin   // Pass input to the output without modification
+        in64_tready  = out64_tready;
+        out64_tdata  = in64_tdata;
+        out64_tvalid = in64_tvalid;
+      end
+      ST_DROP: begin        // Consume input but don't produce output
+        in64_tready  = 1'b1;
+        out64_tdata  = 64'h0;
+        out64_tvalid = 1'b0;
+      end
+      default: begin        // State machine is waiting. Don't produce output
+        in64_tready  = 1'b0;
+        out64_tdata  = 64'h0;
+        out64_tvalid = 1'b0;
+      end
+    endcase
+  end
+
+  assign out64_tlast  = in64_tlast;
+  assign out64_tkeep  = in64_tkeep;
+  assign out64_terror = (state == ST_IN_HDR || state == ST_IN_TS) && in64_tlast; //Premature termination
+
+  // Control-port request signals
+  assign ctrlport_req_sleep    = in64_tvalid && (state == ST_IN_OP_WORD) &&
+                                 (xact_opcode == AXIS_CTRL_OPCODE_SLEEP);
+  assign ctrlport_req_wr       = in64_tvalid && (state == ST_IN_OP_WORD) &&
+                                 (xact_opcode == AXIS_CTRL_OPCODE_WRITE ||
+                                  xact_opcode == AXIS_CTRL_OPCODE_WRITE_READ);
+  assign ctrlport_req_rd       = in64_tvalid && (state == ST_IN_OP_WORD) &&
+                                 (xact_opcode == AXIS_CTRL_OPCODE_READ ||
+                                  xact_opcode == AXIS_CTRL_OPCODE_WRITE_READ);
+  assign ctrlport_req_addr     = xact_address;
+  assign ctrlport_req_byte_en  = xact_byte_en;
+  assign ctrlport_req_data     = xact_data;
+  assign ctrlport_req_has_time = cached_has_time;
+  assign ctrlport_req_time     = cached_time;
+
+endmodule // axis_ctrl_slave
diff --git a/fpga/usrp3/lib/rfnoc/core/axis_data_mdata_to_chdr.v b/fpga/usrp3/lib/rfnoc/core/axis_data_mdata_to_chdr.v
new file mode 100644
index 000000000..dbeb35d08
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/core/axis_data_mdata_to_chdr.v
@@ -0,0 +1,603 @@
+//
+// Copyright 2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: axis_data_mdata_to_chdr
+//
+// Description:
+//
+//   A framer module for CHDR data packets. It accepts an input data stream 
+//   (with sideband information for packet flags and timestamp) and a separate 
+//   metadata stream. A data packet and a metadata packet are required to be 
+//   input in order for a single CHDR packet to be generated. If no metadata is 
+//   associated with the payload, then an empty metadata packet must be input 
+//   along with the data packet (i.e., input a metadata packet with 
+//   s_axis_mdata_tkeep set to 0).
+//
+//   The sideband information (e.g., timestamp, flags) must be input coincident 
+//   with the AXI-Stream data input and will be sampled coincident with the 
+//   last word of data in the packet (i.e., when tlast is asserted).
+//
+//   This module also performs an optional clock crossing and data width 
+//   conversion from a user requested width for the payload bus to CHDR_W.
+//
+//   In order to guarantee a gapless CHDR data stream, the metadata packet 
+//   should be input before the end of the data packet, although this is not 
+//   required.
+//
+// Parameters:
+//
+//   CHDR_W         : Width of the input CHDR bus in bits
+//   ITEM_W         : Width of the output item bus in bits
+//   NIPC           : The number of output items delivered per cycle
+//   SYNC_CLKS      : Are the CHDR and data clocks synchronous to each other?
+//   MTU            : Log2 of the maximum packet size in CHDR words
+//   INFO_FIFO_SIZE : Log2 of the info FIFO size. This determines the number of 
+//                    packets that can be simultaneously buffered in the 
+//                    payload FIFO.
+//   PYLD_FIFO_SIZE : Log2 of the payload FIFO size. The actual FIFO size will 
+//                    be the maximum of 2**MTU or 2**PYLD_FIFO_SIZE, since the 
+//                    FIFO must be at least one MTU so that we can calculate 
+//                    the packet length in the header.
+//
+// Signals:
+//
+//   m_axis_chdr_*  : Output CHDR stream
+//   s_axis_*       : Input data stream (AXI-Stream)
+//   s_axis_mdata_* : Input metadata stream (AXI-Stream)
+//   flush_*        : Signals for flush control and status
+//
+
+module axis_data_mdata_to_chdr #(
+  parameter CHDR_W         = 256,
+  parameter ITEM_W         = 32,
+  parameter NIPC           = 2,
+  parameter SYNC_CLKS      = 0,
+  parameter MTU            = 10,
+  parameter INFO_FIFO_SIZE = 4,
+  parameter PYLD_FIFO_SIZE = MTU
+)(
+  // Clock, reset and settings
+  input  wire                     axis_chdr_clk,
+  input  wire                     axis_chdr_rst,
+  input  wire                     axis_data_clk,
+  input  wire                     axis_data_rst,
+  // CHDR out (AXI-Stream)
+  output wire [CHDR_W-1:0]        m_axis_chdr_tdata,
+  output wire                     m_axis_chdr_tlast,
+  output wire                     m_axis_chdr_tvalid,
+  input  wire                     m_axis_chdr_tready,
+  // Payload data stream in (AXI-Stream)
+  input  wire [(ITEM_W*NIPC)-1:0] s_axis_tdata,
+  input  wire [NIPC-1:0]          s_axis_tkeep,
+  input  wire                     s_axis_tlast,
+  input  wire                     s_axis_tvalid,
+  output wire                     s_axis_tready,
+  // Payload sideband info
+  input  wire [63:0]              s_axis_ttimestamp,
+  input  wire                     s_axis_thas_time,
+  input  wire                     s_axis_teov,
+  input  wire                     s_axis_teob,
+  // Metadata stream in (AXI-Stream)
+  input  wire [CHDR_W-1:0]        s_axis_mdata_tdata,
+  input  wire                     s_axis_mdata_tlast,
+  input  wire                     s_axis_mdata_tkeep,
+  input  wire                     s_axis_mdata_tvalid,
+  output wire                     s_axis_mdata_tready,
+  // Flush signals
+  input  wire                     flush_en,
+  input  wire [31:0]              flush_timeout,
+  output wire                     flush_active,
+  output wire                     flush_done
+);
+
+  // Make sure the metadata FIFO is large enough to store an entire packet's 
+  // worth of metadata (32 words).
+  localparam MDATA_FIFO_SIZE = 5;
+
+  // Make sure the payload FIFO is large enough to store an entire packet's 
+  // worth of payload data. This will ensure that we can buffer the entire 
+  // packet to calculate its length.
+  localparam PAYLOAD_FIFO_SIZE = PYLD_FIFO_SIZE > MTU ? 
+                                 PYLD_FIFO_SIZE : MTU;
+
+
+  // ---------------------------------------------------
+  //  RFNoC Includes
+  // ---------------------------------------------------
+
+  `include "rfnoc_chdr_utils.vh"
+  `include "rfnoc_axis_ctrl_utils.vh"
+
+
+  //---------------------------------------------------------------------------
+  // Timestamp and Flags Capture
+  //---------------------------------------------------------------------------
+  //
+  // The timestamp and flags that we use for each packet is that of the last 
+  // data word. Here, we capture this information at the end of the packet. 
+  //
+  //---------------------------------------------------------------------------
+
+  reg [63:0] packet_timestamp;
+  reg        packet_has_time;
+  reg        packet_eov;
+  reg        packet_eob;
+
+  always @(posedge axis_data_clk) begin
+    if (s_axis_tvalid & s_axis_tready & s_axis_tlast) begin
+      packet_timestamp <= s_axis_ttimestamp;
+      packet_has_time  <= s_axis_thas_time;
+      packet_eov       <= s_axis_teov;
+      packet_eob       <= s_axis_teob;
+    end
+  end
+
+
+  //---------------------------------------------------------------------------
+  // Length Counters
+  //---------------------------------------------------------------------------
+  //
+  // Here We track the state of the incoming packet to determine the payload 
+  // and mdata length.
+  //
+  //---------------------------------------------------------------------------
+
+  localparam HDR_LEN = CHDR_W/8;      // Length of CHDR header word in bytes
+
+  reg [15:0] packet_length;
+  reg [15:0] length_count       = HDR_LEN;
+  reg        in_pkt_info_tvalid = 0;
+  wire       in_pkt_info_tready;
+
+  always @(posedge axis_data_clk) begin : pkt_length_counter
+    if (axis_data_rst) begin
+      length_count       <= HDR_LEN;
+      in_pkt_info_tvalid <= 1'b0;
+    end else begin : pkt_length_counter_main
+      // Calculate the length of this word in bytes, taking tkeep into account
+      integer i;
+      integer num_bytes;
+      num_bytes = 0;
+      for (i = 0; i < NIPC; i = i + 1) begin
+        num_bytes = num_bytes + (s_axis_tkeep[i]*(ITEM_W/8));
+      end
+
+      // Update the packet length if the word is accepted
+      in_pkt_info_tvalid <= 1'b0;
+      if (s_axis_tvalid && s_axis_tready) begin
+        if (s_axis_tlast) begin
+          length_count       <= HDR_LEN;
+          packet_length      <= length_count + num_bytes;
+          in_pkt_info_tvalid <= 1'b1;
+        end else begin
+          length_count <= length_count + num_bytes;
+        end
+      end
+    end
+  end
+
+
+  reg [4:0] num_mdata            = 0;
+  reg [4:0] mdata_count          = 0;
+  reg       in_mdata_info_tvalid = 0;
+  wire      in_mdata_info_tready;
+
+  always @(posedge axis_data_clk) begin : num_mdata_counter
+    if (axis_data_rst) begin
+      mdata_count          <= 0;
+      num_mdata            <= 0;
+      in_mdata_info_tvalid <= 1'b0;
+    end else begin : num_mdata_counter_main
+      // Update the mdata length if the word is accepted
+      in_mdata_info_tvalid <= 1'b0;
+      if (s_axis_mdata_tvalid && s_axis_mdata_tready) begin
+        if (s_axis_mdata_tlast) begin
+          mdata_count          <= 0;
+          num_mdata            <= mdata_count + s_axis_mdata_tkeep;
+          in_mdata_info_tvalid <= 1'b1;
+        end else begin
+          mdata_count <= mdata_count + s_axis_mdata_tkeep;
+        end
+      end
+    end
+  end
+
+
+  //---------------------------------------------------------------------------
+  //  Data Width Converter (ITEM_W*NIPC => CHDR_W)
+  //---------------------------------------------------------------------------
+
+  wire [CHDR_W-1:0] in_pyld_tdata;
+  wire              in_pyld_tlast;
+  wire              in_pyld_tvalid;
+  wire              in_pyld_tready;
+  wire              width_conv_tready;
+
+  assign width_conv_tready = in_pyld_tready & in_pkt_info_tready;
+
+  generate
+    if (NIPC != CHDR_W/ITEM_W) begin : gen_axis_width_conv
+      axis_width_conv #(
+        .WORD_W    (ITEM_W),
+        .IN_WORDS  (NIPC),
+        .OUT_WORDS (CHDR_W/ITEM_W),
+        .SYNC_CLKS (1),
+        .PIPELINE  ("IN")
+      ) payload_width_conv_i (
+        .s_axis_aclk   (axis_data_clk),
+        .s_axis_rst    (axis_data_rst),
+        .s_axis_tdata  (s_axis_tdata),
+        .s_axis_tkeep  ({NIPC{1'b1}}),
+        .s_axis_tlast  (s_axis_tlast),
+        .s_axis_tvalid (s_axis_tvalid),
+        .s_axis_tready (s_axis_tready),
+        .m_axis_aclk   (axis_data_clk),
+        .m_axis_rst    (axis_data_rst),
+        .m_axis_tdata  (in_pyld_tdata),
+        .m_axis_tkeep  (),
+        .m_axis_tlast  (in_pyld_tlast),
+        .m_axis_tvalid (in_pyld_tvalid),
+        .m_axis_tready (width_conv_tready)
+      );
+    end else begin : no_gen_axis_width_conv
+      assign in_pyld_tdata  = s_axis_tdata;
+      assign in_pyld_tlast  = s_axis_tlast;
+      assign in_pyld_tvalid = s_axis_tvalid;
+      assign s_axis_tready  = width_conv_tready;
+    end
+  endgenerate
+
+
+  //---------------------------------------------------------------------------
+  // Input FIFOs
+  //---------------------------------------------------------------------------
+  //
+  // Buffer the data, packet info, metadata, and cross it into the CHDR clock 
+  // domain, if needed. The payload FIFO is sized to match the MTU so that an 
+  // entire packet can be buffered while the length is calculated.
+  //
+  //---------------------------------------------------------------------------
+
+  wire [CHDR_W-1:0] out_mdata_tdata,  out_pyld_tdata;
+  wire              out_mdata_tlast,  out_pyld_tlast;
+  wire              out_mdata_tvalid, out_pyld_tvalid;
+  reg               out_mdata_tready, out_pyld_tready;
+
+  wire        out_pkt_info_tvalid;
+  reg         out_pkt_info_tready;
+  wire        out_eob, out_eov, out_has_time;
+  wire [63:0] out_timestamp;
+  wire [15:0] out_length;
+
+  wire [4:0] out_num_mdata;
+  reg        out_mdata_info_tready;
+  wire       out_mdata_info_tvalid;
+
+  wire in_mdata_tready;
+
+
+  assign s_axis_mdata_tready = in_mdata_tready & in_mdata_info_tready;
+
+  generate if (SYNC_CLKS) begin : gen_sync_fifo
+    axi_fifo #(
+      .WIDTH (CHDR_W+1),
+      .SIZE  (PAYLOAD_FIFO_SIZE)
+    ) pyld_fifo (
+      .clk      (axis_chdr_clk),
+      .reset    (axis_chdr_rst),
+      .clear    (1'b0),
+      .i_tdata  ({in_pyld_tlast, in_pyld_tdata}),
+      .i_tvalid (in_pyld_tvalid),
+      .i_tready (in_pyld_tready),
+      .o_tdata  ({out_pyld_tlast, out_pyld_tdata}),
+      .o_tvalid (out_pyld_tvalid),
+      .o_tready (out_pyld_tready),
+      .space    (),
+      .occupied ()
+    );
+    axi_fifo #(
+      .WIDTH (CHDR_W + 1),
+      .SIZE  (MDATA_FIFO_SIZE)
+    ) mdata_fifo (
+      .clk      (axis_chdr_clk),
+      .reset    (axis_chdr_rst),
+      .clear    (1'b0),
+      .i_tdata  ({s_axis_mdata_tlast, s_axis_mdata_tdata}),
+      .i_tvalid (s_axis_mdata_tvalid),
+      .i_tready (in_mdata_tready),
+      .o_tdata  ({out_mdata_tlast, out_mdata_tdata}),
+      .o_tvalid (out_mdata_tvalid),
+      .o_tready (out_mdata_tready),
+      .space    (),
+      .occupied ()
+    );
+    axi_fifo #(
+      .WIDTH (3 + 64 + 16),
+      .SIZE  (INFO_FIFO_SIZE)
+    ) pkt_info_fifo (
+      .clk      (axis_chdr_clk),
+      .reset    (axis_chdr_rst),
+      .clear    (1'b0),
+      .i_tdata  ({packet_eob, packet_eov, packet_has_time,packet_timestamp, packet_length}),
+      .i_tvalid (in_pkt_info_tvalid),
+      .i_tready (in_pkt_info_tready),
+      .o_tdata  ({out_eob, out_eov, out_has_time, out_timestamp, out_length}),
+      .o_tvalid (out_pkt_info_tvalid),
+      .o_tready (out_pkt_info_tready),
+      .space    (),
+      .occupied ()
+    );
+    axi_fifo #(
+      .WIDTH (5),
+      .SIZE  (INFO_FIFO_SIZE)
+    ) mdata_info_fifo (
+      .clk      (axis_chdr_clk),
+      .reset    (axis_chdr_rst),
+      .clear    (1'b0),
+      .i_tdata  (num_mdata),
+      .i_tvalid (in_mdata_info_tvalid),
+      .i_tready (in_mdata_info_tready),
+      .o_tdata  (out_num_mdata),
+      .o_tvalid (out_mdata_info_tvalid),
+      .o_tready (out_mdata_info_tready),
+      .space    (),
+      .occupied ()
+    );
+
+  end else begin : gen_async_fifo
+    axi_fifo_2clk #(
+      .WIDTH (CHDR_W + 1),
+      .SIZE  (PAYLOAD_FIFO_SIZE)
+    ) pyld_fifo (
+      .reset    (axis_data_rst),
+      .i_aclk   (axis_data_clk),
+      .i_tdata  ({in_pyld_tlast, in_pyld_tdata}),
+      .i_tvalid (in_pyld_tvalid),
+      .i_tready (in_pyld_tready),
+      .o_aclk   (axis_chdr_clk),
+      .o_tdata  ({out_pyld_tlast, out_pyld_tdata}),
+      .o_tvalid (out_pyld_tvalid),
+      .o_tready (out_pyld_tready)
+    );
+    axi_fifo_2clk #(
+      .WIDTH (CHDR_W + 1),
+      .SIZE  (MDATA_FIFO_SIZE)
+    ) mdata_fifo (
+      .reset    (axis_data_rst),
+      .i_aclk   (axis_data_clk),
+      .i_tdata  ({s_axis_mdata_tlast, s_axis_mdata_tdata}),
+      .i_tvalid (s_axis_mdata_tvalid),
+      .i_tready (in_mdata_tready),
+      .o_aclk   (axis_chdr_clk),
+      .o_tdata  ({out_mdata_tlast, out_mdata_tdata}),
+      .o_tvalid (out_mdata_tvalid),
+      .o_tready (out_mdata_tready)
+    );
+    axi_fifo_2clk #(
+      .WIDTH (3 + 64 + 16),
+      .SIZE  (INFO_FIFO_SIZE)
+    ) pkt_info_fifo (
+      .reset    (axis_data_rst),
+      .i_aclk   (axis_data_clk),
+      .i_tdata  ({packet_eob, packet_eov, packet_has_time,packet_timestamp, packet_length}),
+      .i_tvalid (in_pkt_info_tvalid),
+      .i_tready (in_pkt_info_tready),
+      .o_aclk   (axis_chdr_clk),
+      .o_tdata  ({out_eob, out_eov, out_has_time, out_timestamp, out_length}),
+      .o_tvalid (out_pkt_info_tvalid),
+      .o_tready (out_pkt_info_tready)
+    );
+    axi_fifo_2clk #(
+      .WIDTH (5),
+      .SIZE  (INFO_FIFO_SIZE)
+    ) mdata_info_fifo (
+      .reset    (axis_data_rst),
+      .i_aclk   (axis_data_clk),
+      .i_tdata  (num_mdata),
+      .i_tvalid (in_mdata_info_tvalid),
+      .i_tready (in_mdata_info_tready),
+      .o_aclk   (axis_chdr_clk),
+      .o_tdata  (out_num_mdata),
+      .o_tvalid (out_mdata_info_tvalid),
+      .o_tready (out_mdata_info_tready)
+    );
+  end endgenerate
+
+
+  //---------------------------------------------------------------------------
+  // Output State Machine
+  //---------------------------------------------------------------------------
+
+  reg  [CHDR_W-1:0] chdr_pf_tdata;
+  reg               chdr_pf_tlast, chdr_pf_tvalid;
+  wire              chdr_pf_tready;
+
+  localparam [1:0] ST_HDR   = 0;   // Processing the output CHDR header       
+  localparam [1:0] ST_TS    = 1;   // Processing the output CHDR timestamp    
+  localparam [1:0] ST_MDATA = 2;   // Processing the output CHDR metadata word
+  localparam [1:0] ST_PYLD  = 3;   // Processing the output CHDR payload word 
+
+  reg [1:0] state = ST_HDR;
+
+  reg [15:0] seq_num = 0;
+
+  wire [63:0] header;
+  reg  [63:0] timestamp;
+  wire [15:0] length;
+  reg         has_mdata;
+
+  // Some the payload, metadata, and timestamp lengths (out_length already 
+  // includes the header).
+  assign length = (CHDR_W > 64) ?
+    out_length + out_num_mdata * (CHDR_W/8) :
+    out_length + out_num_mdata * (CHDR_W/8) + 8*out_has_time;
+
+  // Build the header word
+  assign header = chdr_build_header(
+    6'b0,                                  // vc
+    out_eob,                               // eob
+    out_eov,                               // eov
+    out_has_time ? CHDR_PKT_TYPE_DATA_TS :
+                   CHDR_PKT_TYPE_DATA,     // pkt_type
+    out_num_mdata,                         // num_mdata
+    seq_num,                               // seq_num
+    length,                                // length
+    16'b0                                  // dst_epid
+  );
+
+  always @(posedge axis_chdr_clk) begin
+    if (axis_chdr_rst) begin
+      state   <= ST_HDR;
+      seq_num <= 0;
+    end else begin
+      case (state)
+
+        // ST_HDR: CHDR Header
+        // -------------------
+        ST_HDR: begin
+          timestamp <= out_timestamp;
+          has_mdata <= (out_num_mdata != CHDR_NO_MDATA);
+
+          if (out_pkt_info_tvalid && out_mdata_info_tvalid && chdr_pf_tready) begin
+            if (CHDR_W > 64) begin
+              // When CHDR_W > 64, the timestamp is a part of the header word. 
+              // If this is a data packet (with or without a TS), we skip the 
+              // timestamp state move directly to metadata/body.
+              if (out_num_mdata == CHDR_NO_MDATA) begin
+                state <= ST_PYLD;
+              end else begin
+                state <= ST_MDATA;
+              end
+            end else begin
+              // When CHDR_W == 64, the timestamp comes after the header. Check 
+              // if this is a data packet with a timestamp or metadata to 
+              // figure out the next state.
+              if (out_has_time) begin
+                state <= ST_TS;
+              end else if (out_num_mdata != CHDR_NO_MDATA) begin
+                state <= ST_MDATA;
+              end else begin
+                state <= ST_PYLD;
+              end
+            end
+          end
+        end
+
+        // ST_TS: Timestamp (CHDR_W == 64 only)
+        // ------------------------------------
+        ST_TS: begin
+          if (chdr_pf_tready) begin
+            state <= has_mdata ? ST_MDATA : ST_PYLD;
+          end
+        end
+
+        // ST_MDATA: Metadata word
+        // -----------------------
+        ST_MDATA: begin
+          if (out_mdata_tvalid && out_mdata_tready && out_mdata_tlast) begin
+            state <= ST_PYLD;
+          end
+        end
+
+        // ST_PYLD: Payload word
+        // ---------------------
+        ST_PYLD: begin
+          if (out_pyld_tvalid && out_pyld_tready && out_pyld_tlast) begin
+            state   <= ST_HDR;
+            seq_num <= seq_num + 1;
+          end
+        end
+
+        default: begin
+          // We should never get here
+          state <= ST_HDR;
+        end
+      endcase
+    end
+  end
+
+  always @(*) begin
+    case (state)
+      ST_HDR: begin
+        // Insert header word
+        chdr_pf_tdata         = (CHDR_W > 64) ? { out_timestamp, header } : header;
+        chdr_pf_tvalid        = out_pkt_info_tvalid & out_mdata_info_tvalid;
+        chdr_pf_tlast         = 1'b0;
+        out_mdata_tready      = chdr_pf_tready &  // Remove empty mdata packet from FIFO
+                                (out_num_mdata == CHDR_NO_MDATA);
+        out_mdata_info_tready = chdr_pf_tready;   // Remove mdata info word from FIFO
+        out_pyld_tready       = 1'b0;
+        out_pkt_info_tready   = chdr_pf_tready;   // Remove packet info word from FIFO
+      end
+      ST_TS: begin
+        // Insert timestamp
+        chdr_pf_tdata[63:0]   = timestamp;
+        chdr_pf_tvalid        = 1'b1;  // Timestamp register is always valid in this state
+        chdr_pf_tlast         = 1'b0;
+        out_mdata_tready      = 1'b0;
+        out_mdata_info_tready = 1'b0;
+        out_pyld_tready       = 1'b0;
+        out_pkt_info_tready   = 1'b0;
+      end
+      ST_MDATA: begin
+        // Insert mdata words
+        chdr_pf_tdata         = out_mdata_tdata;
+        chdr_pf_tvalid        = out_mdata_tvalid;
+        chdr_pf_tlast         = 1'b0;
+        out_mdata_tready      = chdr_pf_tready;
+        out_mdata_info_tready = 1'b0;
+        out_pyld_tready       = 1'b0;
+        out_pkt_info_tready   = 1'b0;
+      end
+      ST_PYLD: begin
+        // Insert payload words
+        chdr_pf_tdata         = out_pyld_tdata;
+        chdr_pf_tvalid        = out_pyld_tvalid;
+        chdr_pf_tlast         = out_pyld_tlast;
+        out_mdata_tready      = 1'b0;
+        out_mdata_info_tready = 1'b0;
+        out_pyld_tready       = chdr_pf_tready;
+        out_pkt_info_tready   = 1'b0;
+      end
+      default: begin
+        chdr_pf_tdata         = out_pyld_tdata;
+        chdr_pf_tvalid        = 1'b0;
+        chdr_pf_tlast         = 1'b0;
+        out_mdata_tready      = 1'b0;
+        out_mdata_info_tready = 1'b0;
+        out_pyld_tready       = 1'b0;
+        out_pkt_info_tready   = 1'b0;
+      end
+    endcase
+  end
+
+  
+  //---------------------------------------------------------------------------
+  // Flushing Logic
+  //---------------------------------------------------------------------------
+
+  axis_packet_flush #(
+    .WIDTH              (CHDR_W),
+    .FLUSH_PARTIAL_PKTS (0),
+    .TIMEOUT_W          (32),
+    .PIPELINE           ("IN")
+  ) chdr_flusher_i (
+    .clk           (axis_chdr_clk),
+    .reset         (axis_chdr_rst),
+    .enable        (flush_en),
+    .timeout       (flush_timeout),
+    .flushing      (flush_active),
+    .done          (flush_done),
+    .s_axis_tdata  (chdr_pf_tdata),
+    .s_axis_tlast  (chdr_pf_tlast),
+    .s_axis_tvalid (chdr_pf_tvalid),
+    .s_axis_tready (chdr_pf_tready),
+    .m_axis_tdata  (m_axis_chdr_tdata),
+    .m_axis_tlast  (m_axis_chdr_tlast),
+    .m_axis_tvalid (m_axis_chdr_tvalid),
+    .m_axis_tready (m_axis_chdr_tready)
+  );
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/core/axis_data_to_chdr.v b/fpga/usrp3/lib/rfnoc/core/axis_data_to_chdr.v
new file mode 100644
index 000000000..6a5b3ce05
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/core/axis_data_to_chdr.v
@@ -0,0 +1,452 @@
+//
+// Copyright 2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: axis_data_to_chdr
+//
+// Description:
+//
+//   A framer module for CHDR data packets. It accepts an input data stream 
+//   with sideband information for packet flags and timestamp). A CHDR packet 
+//   will be generated for each data packet that is input.
+//
+//   The sideband information (e.g., timestamp, flags) must be input coincident 
+//   with the AXI-Stream data input and will be sampled coincident with the 
+//   last word of data in the packet (i.e., when tlast is asserted).
+//
+//   This module also performs an optional clock crossing and data width 
+//   conversion from a user requested width for the payload bus to CHDR_W.
+//
+// Parameters:
+//
+//   CHDR_W         : Width of the input CHDR bus in bits
+//   ITEM_W         : Width of the output item bus in bits
+//   NIPC           : The number of output items delivered per cycle
+//   SYNC_CLKS      : Are the CHDR and data clocks synchronous to each other?
+//   MTU            : Log2 of the maximum packet size in CHDR words
+//   INFO_FIFO_SIZE : Log2 of the info FIFO size. This determines the number of 
+//                    packets that can be simultaneously buffered in the 
+//                    payload FIFO.
+//   PYLD_FIFO_SIZE : Log2 of the payload FIFO size. The actual FIFO size will 
+//                    be the maximum of 2**MTU or 2**PYLD_FIFO_SIZE, since the 
+//                    FIFO must be at least one MTU so that we can calculate 
+//                    the packet length in the header.
+//
+// Signals:
+//
+//   m_axis_chdr_* : Output CHDR stream
+//   s_axis_*      : Input data stream (AXI-Stream)
+//   flush_*       : Signals for flush control and status
+//
+
+module axis_data_to_chdr #(
+  parameter CHDR_W         = 256,
+  parameter ITEM_W         = 32,
+  parameter NIPC           = 2,
+  parameter SYNC_CLKS      = 0,
+  parameter MTU            = 10,
+  parameter INFO_FIFO_SIZE = 5,
+  parameter PYLD_FIFO_SIZE = MTU
+)(
+  // Clock, reset and settings
+  input  wire                     axis_chdr_clk,
+  input  wire                     axis_chdr_rst,
+  input  wire                     axis_data_clk,
+  input  wire                     axis_data_rst,
+  // CHDR out (AXI-Stream)
+  output wire [CHDR_W-1:0]        m_axis_chdr_tdata,
+  output wire                     m_axis_chdr_tlast,
+  output wire                     m_axis_chdr_tvalid,
+  input  wire                     m_axis_chdr_tready,
+  // Payload data stream in (AXI-Stream)
+  input  wire [(ITEM_W*NIPC)-1:0] s_axis_tdata,
+  input  wire [NIPC-1:0]          s_axis_tkeep,
+  input  wire                     s_axis_tlast,
+  input  wire                     s_axis_tvalid,
+  output wire                     s_axis_tready,
+  // Payload sideband info
+  input  wire [63:0]              s_axis_ttimestamp,
+  input  wire                     s_axis_thas_time,
+  input  wire                     s_axis_teov,
+  input  wire                     s_axis_teob,
+  // Flush signals
+  input  wire                     flush_en,
+  input  wire [31:0]              flush_timeout,
+  output wire                     flush_active,
+  output wire                     flush_done
+);
+
+  // Make sure the payload FIFO is large enough to store an entire packet's 
+  // worth of payload data. This will ensure that we can buffer the entire 
+  // packet to calculate its length.
+  localparam PAYLOAD_FIFO_SIZE = PYLD_FIFO_SIZE > MTU ? 
+                                 PYLD_FIFO_SIZE : MTU;
+
+
+  // ---------------------------------------------------
+  //  RFNoC Includes
+  // ---------------------------------------------------
+
+  `include "rfnoc_chdr_utils.vh"
+  `include "rfnoc_axis_ctrl_utils.vh"
+
+
+  //---------------------------------------------------------------------------
+  // Timestamp and Flags Capture
+  //---------------------------------------------------------------------------
+  //
+  // The timestamp and flags that we use for each packet is that of the last 
+  // data word. Here, we capture this information at the end of the packet. 
+  //
+  //---------------------------------------------------------------------------
+
+  reg [63:0] packet_timestamp;
+  reg        packet_has_time;
+  reg        packet_eov;
+  reg        packet_eob;
+
+  always @(posedge axis_data_clk) begin
+    if (s_axis_tvalid & s_axis_tready & s_axis_tlast) begin
+      packet_timestamp <= s_axis_ttimestamp;
+      packet_has_time  <= s_axis_thas_time;
+      packet_eov       <= s_axis_teov;
+      packet_eob       <= s_axis_teob;
+    end
+  end
+
+
+  //---------------------------------------------------------------------------
+  // Length Counters
+  //---------------------------------------------------------------------------
+  //
+  // Here We track the state of the incoming packet to determine the payload 
+  // length.
+  //
+  //---------------------------------------------------------------------------
+
+  localparam HDR_LEN = CHDR_W/8;      // Length of CHDR header word in bytes
+
+  reg [15:0] packet_length;
+  reg [15:0] length_count       = HDR_LEN;
+  reg        in_pkt_info_tvalid = 0;
+  wire       in_pkt_info_tready;
+
+  always @(posedge axis_data_clk) begin : pkt_length_counter
+    if (axis_data_rst) begin
+      length_count       <= HDR_LEN;
+      in_pkt_info_tvalid <= 1'b0;
+    end else begin : pkt_length_counter_main
+      // Calculate the length of this word in bytes, taking tkeep into account
+      integer i;
+      integer num_bytes;
+      num_bytes = 0;
+      for (i = 0; i < NIPC; i = i + 1) begin
+        num_bytes = num_bytes + (s_axis_tkeep[i]*(ITEM_W/8));
+      end
+
+      // Update the packet length if the word is accepted
+      in_pkt_info_tvalid <= 1'b0;
+      if (s_axis_tvalid && s_axis_tready) begin
+        if (s_axis_tlast) begin
+          length_count       <= HDR_LEN;
+          packet_length      <= length_count + num_bytes;
+          in_pkt_info_tvalid <= 1'b1;
+        end else begin
+          length_count <= length_count + num_bytes;
+        end
+      end
+    end
+  end
+
+
+  //---------------------------------------------------------------------------
+  //  Data Width Converter (ITEM_W*NIPC => CHDR_W)
+  //---------------------------------------------------------------------------
+
+  wire [CHDR_W-1:0] in_pyld_tdata;
+  wire              in_pyld_tlast;
+  wire              in_pyld_tvalid;
+  wire              in_pyld_tready;
+  wire              width_conv_tready;
+
+  assign width_conv_tready = in_pyld_tready & in_pkt_info_tready;
+
+  generate
+    if (NIPC != CHDR_W/ITEM_W) begin : gen_axis_width_conv
+      axis_width_conv #(
+        .WORD_W    (ITEM_W),
+        .IN_WORDS  (NIPC),
+        .OUT_WORDS (CHDR_W/ITEM_W),
+        .SYNC_CLKS (1),
+        .PIPELINE  ("IN")
+      ) payload_width_conv_i (
+        .s_axis_aclk   (axis_data_clk),
+        .s_axis_rst    (axis_data_rst),
+        .s_axis_tdata  (s_axis_tdata),
+        .s_axis_tkeep  ({NIPC{1'b1}}),
+        .s_axis_tlast  (s_axis_tlast),
+        .s_axis_tvalid (s_axis_tvalid),
+        .s_axis_tready (s_axis_tready),
+        .m_axis_aclk   (axis_data_clk),
+        .m_axis_rst    (axis_data_rst),
+        .m_axis_tdata  (in_pyld_tdata),
+        .m_axis_tkeep  (),
+        .m_axis_tlast  (in_pyld_tlast),
+        .m_axis_tvalid (in_pyld_tvalid),
+        .m_axis_tready (width_conv_tready)
+      );
+    end else begin : no_gen_axis_width_conv
+      assign in_pyld_tdata  = s_axis_tdata;
+      assign in_pyld_tlast  = s_axis_tlast;
+      assign in_pyld_tvalid = s_axis_tvalid;
+      assign s_axis_tready  = width_conv_tready;
+    end
+  endgenerate
+
+
+  //---------------------------------------------------------------------------
+  // Input FIFOs
+  //---------------------------------------------------------------------------
+  //
+  // Buffer the data, packet info, metadata, and cross it into the CHDR clock 
+  // domain, if needed. The payload FIFO is sized to match the MTU so that an 
+  // entire packet can be buffered while the length is calculated.
+  //
+  //---------------------------------------------------------------------------
+
+  wire [CHDR_W-1:0] out_pyld_tdata;
+  wire              out_pyld_tlast;
+  wire              out_pyld_tvalid;
+  reg               out_pyld_tready;
+
+  wire        out_pkt_info_tvalid;
+  reg         out_pkt_info_tready;
+  wire        out_eob, out_eov, out_has_time;
+  wire [63:0] out_timestamp;
+  wire [15:0] out_length;
+
+  generate if (SYNC_CLKS) begin : gen_sync_fifo
+    axi_fifo #(
+      .WIDTH    (CHDR_W+1),
+      .SIZE     (PAYLOAD_FIFO_SIZE)
+    ) pyld_fifo (
+      .clk      (axis_chdr_clk),
+      .reset    (axis_chdr_rst),
+      .clear    (1'b0),
+      .i_tdata  ({in_pyld_tlast, in_pyld_tdata}),
+      .i_tvalid (in_pyld_tvalid),
+      .i_tready (in_pyld_tready),
+      .o_tdata  ({out_pyld_tlast, out_pyld_tdata}),
+      .o_tvalid (out_pyld_tvalid),
+      .o_tready (out_pyld_tready),
+      .space    (),
+      .occupied ()
+    );
+    axi_fifo #(
+      .WIDTH    (3 + 64 + 16),
+      .SIZE     (INFO_FIFO_SIZE)
+    ) pkt_info_fifo (
+      .clk      (axis_chdr_clk),
+      .reset    (axis_chdr_rst),
+      .clear    (1'b0),
+      .i_tdata  ({packet_eob, packet_eov, packet_has_time,packet_timestamp, packet_length}),
+      .i_tvalid (in_pkt_info_tvalid),
+      .i_tready (in_pkt_info_tready),
+      .o_tdata  ({out_eob, out_eov, out_has_time, out_timestamp, out_length}),
+      .o_tvalid (out_pkt_info_tvalid),
+      .o_tready (out_pkt_info_tready),
+      .space    (),
+      .occupied ()
+    );
+
+  end else begin : gen_async_fifo
+    axi_fifo_2clk #(
+      .WIDTH    (CHDR_W + 1),
+      .SIZE     (PAYLOAD_FIFO_SIZE)
+    ) pyld_fifo (
+      .reset    (axis_data_rst),
+      .i_aclk   (axis_data_clk),
+      .i_tdata  ({in_pyld_tlast, in_pyld_tdata}),
+      .i_tvalid (in_pyld_tvalid),
+      .i_tready (in_pyld_tready),
+      .o_aclk   (axis_chdr_clk),
+      .o_tdata  ({out_pyld_tlast, out_pyld_tdata}),
+      .o_tvalid (out_pyld_tvalid),
+      .o_tready (out_pyld_tready)
+    );
+    axi_fifo_2clk #(
+      .WIDTH    (3 + 64 + 16),
+      .SIZE     (INFO_FIFO_SIZE)
+    ) pkt_info_fifo (
+      .reset    (axis_data_rst),
+      .i_aclk   (axis_data_clk),
+      .i_tdata  ({packet_eob, packet_eov, packet_has_time,packet_timestamp, packet_length}),
+      .i_tvalid (in_pkt_info_tvalid),
+      .i_tready (in_pkt_info_tready),
+      .o_aclk   (axis_chdr_clk),
+      .o_tdata  ({out_eob, out_eov, out_has_time, out_timestamp, out_length}),
+      .o_tvalid (out_pkt_info_tvalid),
+      .o_tready (out_pkt_info_tready)
+    );
+  end endgenerate
+
+
+  //---------------------------------------------------------------------------
+  // Output State Machine
+  //---------------------------------------------------------------------------
+
+  reg  [CHDR_W-1:0] chdr_pf_tdata;
+  reg               chdr_pf_tlast, chdr_pf_tvalid;
+  wire              chdr_pf_tready;
+
+  localparam [1:0] ST_HDR   = 0;   // Processing the output CHDR header       
+  localparam [1:0] ST_TS    = 1;   // Processing the output CHDR timestamp    
+  localparam [1:0] ST_PYLD  = 2;   // Processing the output CHDR payload word 
+
+  reg [1:0] state = ST_HDR;
+
+  reg [15:0] seq_num = 0;
+
+  wire [63:0] header;
+  reg  [63:0] timestamp;
+  wire [15:0] length;
+
+  // Some the payload, metadata, and timestamp lengths (out_length already 
+  // includes the header).
+  assign length = (CHDR_W > 64) ? out_length : out_length + 8*out_has_time;
+
+  // Build the header word
+  assign header = chdr_build_header(
+    6'b0,                                  // vc
+    out_eob,                               // eob
+    out_eov,                               // eov
+    out_has_time ? CHDR_PKT_TYPE_DATA_TS :
+                   CHDR_PKT_TYPE_DATA,     // pkt_type
+    0,                                     // num_mdata
+    seq_num,                               // seq_num
+    length,                                // length
+    16'b0                                  // dst_epid
+  );
+
+  always @(posedge axis_chdr_clk) begin
+    if (axis_chdr_rst) begin
+      state   <= ST_HDR;
+      seq_num <= 0;
+    end else begin
+      case (state)
+
+        // ST_HDR: CHDR Header
+        // -------------------
+        ST_HDR: begin
+          timestamp <= out_timestamp;
+
+          if (out_pkt_info_tvalid && chdr_pf_tready) begin
+            seq_num <= seq_num + 1;
+
+            if (CHDR_W > 64) begin
+              // When CHDR_W > 64, the timestamp is a part of the header word. 
+              // If this is a data packet (with or without a TS), we skip the 
+              // timestamp state move directly to the payload.
+              state <= ST_PYLD;
+            end else begin
+              // When CHDR_W == 64, the timestamp comes after the header. Check 
+              // if this is a data packet with a timestamp to figure out the 
+              // next state.
+              if (out_has_time) begin
+                state <= ST_TS;
+              end else begin
+                state <= ST_PYLD;
+              end
+            end
+          end
+        end
+
+        // ST_TS: Timestamp (CHDR_W == 64 only)
+        // ------------------------------------
+        ST_TS: begin
+          if (chdr_pf_tready) begin
+            state <= ST_PYLD;
+          end
+        end
+
+        // ST_PYLD: Payload word
+        // ---------------------
+        ST_PYLD: begin
+          if (out_pyld_tvalid && out_pyld_tready && out_pyld_tlast) begin
+            state   <= ST_HDR;
+          end
+        end
+
+        default: begin
+          // We should never get here
+          state <= ST_HDR;
+        end
+      endcase
+    end
+  end
+
+  always @(*) begin
+    case (state)
+      ST_HDR: begin
+        // Insert header word
+        chdr_pf_tdata         = (CHDR_W > 64) ? { out_timestamp, header } : header;
+        chdr_pf_tvalid        = out_pkt_info_tvalid;
+        chdr_pf_tlast         = 1'b0;
+        out_pyld_tready       = 1'b0;
+        out_pkt_info_tready   = chdr_pf_tready;   // Remove packet info word from FIFO
+      end
+      ST_TS: begin
+        // Insert timestamp
+        chdr_pf_tdata[63:0]   = timestamp;
+        chdr_pf_tvalid        = 1'b1;  // Timestamp register is always valid in this state
+        chdr_pf_tlast         = 1'b0;
+        out_pyld_tready       = 1'b0;
+        out_pkt_info_tready   = 1'b0;
+      end
+      ST_PYLD: begin
+        // Insert payload words
+        chdr_pf_tdata         = out_pyld_tdata;
+        chdr_pf_tvalid        = out_pyld_tvalid;
+        chdr_pf_tlast         = out_pyld_tlast;
+        out_pyld_tready       = chdr_pf_tready;
+        out_pkt_info_tready   = 1'b0;
+      end
+      default: begin
+        chdr_pf_tdata         = out_pyld_tdata;
+        chdr_pf_tvalid        = 1'b0;
+        chdr_pf_tlast         = 1'b0;
+        out_pyld_tready       = 1'b0;
+        out_pkt_info_tready   = 1'b0;
+      end
+    endcase
+  end
+
+  
+  //---------------------------------------------------------------------------
+  // Flushing Logic
+  //---------------------------------------------------------------------------
+
+  axis_packet_flush #(
+    .WIDTH              (CHDR_W),
+    .FLUSH_PARTIAL_PKTS (0),
+    .TIMEOUT_W          (32),
+    .PIPELINE           ("IN")
+  ) chdr_flusher_i (
+    .clk           (axis_chdr_clk),
+    .reset         (axis_chdr_rst),
+    .enable        (flush_en),
+    .timeout       (flush_timeout),
+    .flushing      (flush_active),
+    .done          (flush_done),
+    .s_axis_tdata  (chdr_pf_tdata),
+    .s_axis_tlast  (chdr_pf_tlast),
+    .s_axis_tvalid (chdr_pf_tvalid),
+    .s_axis_tready (chdr_pf_tready),
+    .m_axis_tdata  (m_axis_chdr_tdata),
+    .m_axis_tlast  (m_axis_chdr_tlast),
+    .m_axis_tvalid (m_axis_chdr_tvalid),
+    .m_axis_tready (m_axis_chdr_tready)
+  );
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/core/axis_pyld_ctxt_to_chdr.v b/fpga/usrp3/lib/rfnoc/core/axis_pyld_ctxt_to_chdr.v
new file mode 100644
index 000000000..c73d7f365
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/core/axis_pyld_ctxt_to_chdr.v
@@ -0,0 +1,463 @@
+//
+// Copyright 2018-2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: axis_pyld_ctxt_to_chdr
+// Description:
+//   A header framer module for CHDR data packets.
+//   Accepts an input payload and context stream, and produces an
+//   output CHDR stream.
+//   This module also performs an optional clock crossing and data
+//   width convertion from a user requested width for the
+//   payload bus to CHDR_W.
+//   Context and data packets must be interleaved i.e. a context packet
+//   must arrive before its corresponding data packet. However, if
+//   context prefetching is enabled, the context for the next packet
+//   may arrive before the data for the current packet has been
+//   consumed. In the case of a rate reduction, this allows the module
+//   to sustain a gapless stream of payload items and a bursty
+//   sideband context path.
+//
+// Parameters:
+//   - CHDR_W: Width of the input CHDR bus in bits
+//   - ITEM_W: Width of the output item bus in bits
+//   - NIPC: The number of output items delievered per cycle
+//   - SYNC_CLKS: Are the CHDR and data clocks synchronous to each other?
+//   - CONTEXT_FIFO_SIZE: FIFO size for the context path
+//   - PAYLOAD_FIFO_SIZE: FIFO size for the payload path
+//   - MTU: Log2 of the maximum packet size in words
+//   - CONTEXT_PREFETCH_EN: Is context prefetching enabled?
+//
+// Signals:
+//   - s_axis_payload_* : Input payload stream (AXI-Stream)
+//   - s_axis_context_* : Input context stream (AXI-Stream)
+//   - s_axis_chdr_* : Output CHDR stream (AXI-Stream)
+//   - framer_errors : Number of framer errors (dropped packets)
+//   - flush_* : Signals for flush control and status
+//
+
+module axis_pyld_ctxt_to_chdr #(
+  parameter CHDR_W              = 256,
+  parameter ITEM_W              = 32,
+  parameter NIPC                = 2,
+  parameter SYNC_CLKS           = 0,
+  parameter CONTEXT_FIFO_SIZE   = 1,
+  parameter PAYLOAD_FIFO_SIZE   = 1,
+  parameter MTU                 = 9,
+  parameter CONTEXT_PREFETCH_EN = 1
+)(
+  // Clock, reset and settings
+  input  wire                     axis_chdr_clk,
+  input  wire                     axis_chdr_rst,
+  input  wire                     axis_data_clk,
+  input  wire                     axis_data_rst,
+  // CHDR in (AXI-Stream)
+  output wire [CHDR_W-1:0]        m_axis_chdr_tdata,
+  output wire                     m_axis_chdr_tlast,
+  output wire                     m_axis_chdr_tvalid,
+  input  wire                     m_axis_chdr_tready,
+  // Payload stream out (AXI-Stream)
+  input  wire [(ITEM_W*NIPC)-1:0] s_axis_payload_tdata,
+  input  wire [NIPC-1:0]          s_axis_payload_tkeep,
+  input  wire                     s_axis_payload_tlast,
+  input  wire                     s_axis_payload_tvalid,
+  output wire                     s_axis_payload_tready,
+  // Context stream out (AXI-Stream)
+  input  wire [CHDR_W-1:0]        s_axis_context_tdata,
+  input  wire [3:0]               s_axis_context_tuser,
+  input  wire                     s_axis_context_tlast,
+  input  wire                     s_axis_context_tvalid,
+  output wire                     s_axis_context_tready,
+  // Status
+  output reg  [31:0]              framer_errors,
+  // Flush signals
+  input  wire                     flush_en,
+  input  wire [31:0]              flush_timeout,
+  output wire                     flush_active,
+  output wire                     flush_done
+);
+
+  // ---------------------------------------------------
+  //  RFNoC Includes
+  // ---------------------------------------------------
+  `include "rfnoc_chdr_utils.vh"
+  `include "rfnoc_axis_ctrl_utils.vh"
+
+  // ---------------------------------------------------
+  //  Intput State Machine
+  // ---------------------------------------------------
+  reg [2:0] ctxt_pkt_cnt = 3'd0, pyld_pkt_cnt = 3'd0;
+  // A payload packet can pass only if it is preceeded by a context packet
+  wire pass_pyld = ((ctxt_pkt_cnt - pyld_pkt_cnt) > 3'd0);
+  // A context packet has to be blocked if its corresponding payload packet hasn't passed except
+  // when prefetching is enabled. In that case one additional context packet is allowed to pass
+  wire pass_ctxt = ((ctxt_pkt_cnt - pyld_pkt_cnt) < (CONTEXT_PREFETCH_EN == 1 ? 3'd2 : 3'd1));
+
+  always @(posedge axis_data_clk) begin
+    if (axis_data_rst) begin
+      ctxt_pkt_cnt <= 3'd0;
+      pyld_pkt_cnt <= 3'd0;
+    end else begin
+      if (s_axis_context_tvalid && s_axis_context_tready && s_axis_context_tlast)
+        ctxt_pkt_cnt <= ctxt_pkt_cnt + 3'd1;
+      if (s_axis_payload_tvalid && s_axis_payload_tready && s_axis_payload_tlast)
+        pyld_pkt_cnt <= pyld_pkt_cnt + 3'd1;
+    end
+  end
+
+  wire tmp_ctxt_tvalid, tmp_ctxt_tready;
+  wire tmp_pyld_tvalid, tmp_pyld_tready;
+
+  assign tmp_ctxt_tvalid       = s_axis_context_tvalid && pass_ctxt;
+  assign tmp_pyld_tvalid       = s_axis_payload_tvalid && pass_pyld;
+  assign s_axis_context_tready = tmp_ctxt_tready       && pass_ctxt;
+  assign s_axis_payload_tready = tmp_pyld_tready       && pass_pyld;
+
+  // ---------------------------------------------------
+  //  Data Width Converter: ITEM_W*NIPC => CHDR_W
+  // ---------------------------------------------------
+  wire [CHDR_W-1:0] in_pyld_tdata;
+  wire              in_pyld_tlast;
+  wire              in_pyld_tvalid;
+  wire              in_pyld_tready;
+
+  axis_width_conv #(
+    .WORD_W(ITEM_W), .IN_WORDS(NIPC), .OUT_WORDS(CHDR_W/ITEM_W),
+    .SYNC_CLKS(1), .PIPELINE("IN")
+  ) payload_width_conv_i (
+    .s_axis_aclk(axis_data_clk), .s_axis_rst(axis_data_rst),
+    .s_axis_tdata(s_axis_payload_tdata),
+    .s_axis_tkeep(s_axis_payload_tkeep),
+    .s_axis_tlast(s_axis_payload_tlast),
+    .s_axis_tvalid(tmp_pyld_tvalid),
+    .s_axis_tready(tmp_pyld_tready),
+    .m_axis_aclk(axis_data_clk), .m_axis_rst(axis_data_rst),
+    .m_axis_tdata(in_pyld_tdata),
+    .m_axis_tkeep(/* unused */),
+    .m_axis_tlast(in_pyld_tlast),
+    .m_axis_tvalid(in_pyld_tvalid),
+    .m_axis_tready(in_pyld_tready)
+  );
+
+  // ---------------------------------------------------
+  //  Payload and Context FIFOs
+  // ---------------------------------------------------
+  wire [CHDR_W-1:0] out_ctxt_tdata , out_pyld_tdata ;
+  wire [3:0]        out_ctxt_tuser;
+  wire              out_ctxt_tlast , out_pyld_tlast ;
+  wire              out_ctxt_tvalid, out_pyld_tvalid;
+  reg               out_ctxt_tready, out_pyld_tready;
+
+  generate if (SYNC_CLKS) begin
+    axi_fifo #(.WIDTH(CHDR_W+4+1), .SIZE(CONTEXT_FIFO_SIZE)) ctxt_fifo_i (
+      .clk(axis_chdr_clk), .reset(axis_chdr_rst), .clear(1'b0),
+      .i_tdata({s_axis_context_tlast, s_axis_context_tuser, s_axis_context_tdata}),
+      .i_tvalid(tmp_ctxt_tvalid), .i_tready(tmp_ctxt_tready),
+      .o_tdata({out_ctxt_tlast, out_ctxt_tuser, out_ctxt_tdata}),
+      .o_tvalid(out_ctxt_tvalid), .o_tready(out_ctxt_tready),
+      .space(), .occupied()
+    );
+    axi_fifo #(.WIDTH(CHDR_W+1), .SIZE(PAYLOAD_FIFO_SIZE)) pyld_fifo_i (
+      .clk(axis_chdr_clk), .reset(axis_chdr_rst), .clear(1'b0),
+      .i_tdata({in_pyld_tlast, in_pyld_tdata}),
+      .i_tvalid(in_pyld_tvalid), .i_tready(in_pyld_tready),
+      .o_tdata({out_pyld_tlast, out_pyld_tdata}),
+      .o_tvalid(out_pyld_tvalid), .o_tready(out_pyld_tready),
+      .space(), .occupied()
+    );
+  end else begin
+    axi_fifo_2clk #(.WIDTH(CHDR_W+4+1), .SIZE(CONTEXT_FIFO_SIZE)) ctxt_fifo_i (
+      .reset(axis_data_rst),
+      .i_aclk(axis_data_clk),
+      .i_tdata({s_axis_context_tlast, s_axis_context_tuser, s_axis_context_tdata}),
+      .i_tvalid(tmp_ctxt_tvalid), .i_tready(tmp_ctxt_tready),
+      .o_aclk(axis_chdr_clk),
+      .o_tdata({out_ctxt_tlast, out_ctxt_tuser, out_ctxt_tdata}),
+      .o_tvalid(out_ctxt_tvalid), .o_tready(out_ctxt_tready)
+    );
+    axi_fifo_2clk #(.WIDTH(CHDR_W+1), .SIZE(PAYLOAD_FIFO_SIZE)) pyld_fifo_i (
+      .reset(axis_data_rst),
+      .i_aclk(axis_data_clk),
+      .i_tdata({in_pyld_tlast, in_pyld_tdata}),
+      .i_tvalid(in_pyld_tvalid), .i_tready(in_pyld_tready),
+      .o_aclk(axis_chdr_clk),
+      .o_tdata({out_pyld_tlast, out_pyld_tdata}),
+      .o_tvalid(out_pyld_tvalid), .o_tready(out_pyld_tready)
+    );
+  end endgenerate
+
+  // ---------------------------------------------------
+  //  Output State Machine
+  // ---------------------------------------------------
+  wire [CHDR_W-1:0] chdr_pg_tdata;
+  reg               chdr_pg_tlast, chdr_pg_tvalid;
+  wire              chdr_pg_terror, chdr_pg_tready;
+
+  localparam [2:0] ST_HDR       = 3'd0;   // Processing the output CHDR header       
+  localparam [2:0] ST_TS        = 3'd1;   // Processing the output CHDR timestamp    
+  localparam [2:0] ST_MDATA     = 3'd2;   // Processing the output CHDR metadata word
+  localparam [2:0] ST_BODY      = 3'd3;   // Processing the output CHDR payload word 
+  localparam [2:0] ST_DROP_CTXT = 3'd4;   // Something went wrong... Dropping context packet
+  localparam [2:0] ST_DROP_PYLD = 3'd5;   // Something went wrong... Dropping payload packet
+  localparam [2:0] ST_TERMINATE = 3'd6;   // Something went wrong... Rejecting output packet
+
+  reg [2:0] state = ST_HDR;
+  reg [4:0] mdata_pending = 5'd0;
+
+  // Shortcuts: CHDR header
+  wire [2:0] out_pkt_type = chdr_get_pkt_type(out_ctxt_tdata[63:0]);
+  wire [4:0] out_num_mdata = chdr_get_num_mdata(out_ctxt_tdata[63:0]);
+
+  always @(posedge axis_chdr_clk) begin
+    if (axis_chdr_rst) begin
+      state <= ST_HDR;
+      framer_errors <= 32'd0;
+    end else begin
+      case (state)
+
+        // ST_HDR: CHDR Header
+        // -------------------
+        ST_HDR: begin
+          if (out_ctxt_tvalid && out_ctxt_tready) begin
+            mdata_pending <= out_num_mdata;
+            if (CHDR_W > 64) begin
+              // When CHDR_W > 64, the timestamp is a part of the header word.
+              // If this is a data packet (with/without a TS), we skip the TS state
+              // move directly to metadata/body
+              if (out_num_mdata != CHDR_NO_MDATA) begin
+                if (!out_ctxt_tlast)
+                  if (out_ctxt_tuser == CONTEXT_FIELD_HDR_TS)
+                    state <= ST_MDATA;        // tlast should be low. Move to metadata.
+                  else
+                    state <= ST_DROP_CTXT;    // Malformed packet: Wrong tuser. Drop ctxt+pyld
+                else
+                  state <= ST_DROP_PYLD;      // Premature tlast. Drop pyld
+              end else begin
+                if (out_ctxt_tlast)
+                  if (out_ctxt_tuser == CONTEXT_FIELD_HDR_TS)
+                    state <= ST_BODY;         // tlast should be high. Move to payload.
+                  else
+                    state <= ST_DROP_PYLD;    // Malformed packet: Wrong tuser. Drop pyld
+                else
+                  state <= ST_DROP_CTXT;      // Malformed packet: extra context lines. Drop ctxt+pyld
+              end
+            end else begin
+              // When CHDR_W == 64, the timestamp comes after the header. Check if this is a data
+              // packet with a TS to figure out the next state. If no TS, then check for metadata
+              // to move to the next state. Drop any non-data packets.
+              if (out_pkt_type == CHDR_PKT_TYPE_DATA_TS) begin
+                if (!out_ctxt_tlast)
+                  if (out_ctxt_tuser == CONTEXT_FIELD_HDR)
+                    state <= ST_TS;           // tlast should be low. Move to timestamp.
+                  else
+                    state <= ST_DROP_CTXT;    // Malformed packet: Wrong tuser. Drop ctxt+pyld
+                else
+                  state <= ST_DROP_PYLD;      // Premature tlast. Drop pyld
+              end else begin
+                if (out_num_mdata != CHDR_NO_MDATA) begin
+                  if (!out_ctxt_tlast)
+                    if (out_ctxt_tuser == CONTEXT_FIELD_HDR)
+                      state <= ST_MDATA;      // tlast should be low. Move to metadata.
+                    else
+                      state <= ST_DROP_CTXT;  // Malformed packet: Wrong tuser. Drop ctxt+pyld
+                  else
+                    state <= ST_DROP_PYLD;    // Premature tlast. Drop pyld
+                end else begin
+                  if (out_ctxt_tlast)
+                    if (out_ctxt_tuser == CONTEXT_FIELD_HDR)
+                      state <= ST_BODY;       // tlast should be high. Move to payload.
+                    else
+                      state <= ST_DROP_PYLD;  // Malformed packet: Wrong tuser. Drop pyld
+                  else
+                    state <= ST_DROP_CTXT;    // Malformed packet: extra context lines. Drop ctxt+pyld
+                end
+              end
+            end
+          end
+        end
+
+        // ST_TS: Timestamp (CHDR_W == 64 only)
+        // ------------------------------------
+        ST_TS: begin
+          if (out_ctxt_tvalid && out_ctxt_tready) begin
+            if (mdata_pending != CHDR_NO_MDATA) begin
+              if (!out_ctxt_tlast)
+                if (out_ctxt_tuser == CONTEXT_FIELD_TS)
+                  state <= ST_MDATA;        // tlast should be low. Move to metadata.
+                else
+                  state <= ST_DROP_CTXT;    // Malformed packet: Wrong tuser. Drop ctxt+pyld
+              else
+                state <= ST_DROP_PYLD;      // Premature tlast. Drop pyld
+            end else begin
+              if (out_ctxt_tlast)
+                if (out_ctxt_tuser == CONTEXT_FIELD_TS)
+                  state <= ST_BODY;         // tlast should be high. Move to payload.
+                else
+                  state <= ST_DROP_PYLD;    // Malformed packet: Wrong tuser. Drop pyld
+              else
+                state <= ST_DROP_CTXT;      // Malformed packet: extra context lines. Drop ctxt+pyld
+            end
+          end
+        end
+
+        // ST_MDATA: Metadata word
+        // -----------------------
+        ST_MDATA: begin
+          if (out_ctxt_tvalid && out_ctxt_tready) begin
+            if (mdata_pending != 5'd1) begin
+              mdata_pending <= mdata_pending - 'd1;
+              if (!out_ctxt_tlast)
+                if (out_ctxt_tuser == CONTEXT_FIELD_MDATA)
+                  state <= ST_MDATA;        // tlast should be low. Continue processing metadata.
+                else
+                  state <= ST_DROP_CTXT;    // Malformed packet: Wrong tuser. Drop ctxt+pyld
+              else
+                state <= ST_DROP_PYLD;      // Premature tlast. Drop pyld
+            end else begin
+              if (out_ctxt_tlast)
+                if (out_ctxt_tuser == CONTEXT_FIELD_MDATA)
+                  state <= ST_BODY;         // tlast should be high. Move to payload.
+                else
+                  state <= ST_DROP_PYLD;    // Malformed packet: Wrong tuser. Drop pyld
+              else
+                state <= ST_DROP_CTXT;      // Malformed packet: extra context lines. Drop ctxt+pyld
+            end
+          end
+        end
+
+        // ST_BODY: Payload word
+        // ---------------------
+        ST_BODY: begin
+          if (out_pyld_tvalid && out_pyld_tready) begin
+            state <= out_pyld_tlast ? ST_HDR : ST_BODY;
+          end
+        end
+
+        // ST_DROP_CTXT: Drop current context packet
+        // -----------------------------------------
+        ST_DROP_CTXT: begin
+          if (out_ctxt_tvalid && out_ctxt_tready) begin
+            state <= out_ctxt_tlast ? ST_DROP_PYLD : ST_DROP_CTXT;
+          end
+        end
+
+        // ST_DROP_PYLD: Drop current payload packet
+        // -----------------------------------------
+        ST_DROP_PYLD: begin
+          if (out_pyld_tvalid && out_pyld_tready) begin
+            state <= out_pyld_tlast ? ST_TERMINATE : ST_DROP_PYLD;
+          end
+        end
+
+        // ST_TERMINATE: Drop partial output packet
+        // ----------------------------------------
+        ST_TERMINATE: begin
+          if (chdr_pg_tready) begin
+            state <= ST_HDR;
+            framer_errors <= framer_errors + 32'd1;
+          end
+        end
+
+        default: begin
+          // We should never get here
+          state <= ST_HDR;
+        end
+      endcase
+    end
+  end
+
+
+  always @(*) begin
+    case (state)
+      ST_HDR: begin
+        // A context word passes fwd to the CHDR output
+        chdr_pg_tvalid  = out_ctxt_tvalid;
+        chdr_pg_tlast   = 1'b0;   // tlast is inherited from the data stream
+        out_ctxt_tready = chdr_pg_tready;
+        out_pyld_tready = 1'b0;
+      end
+      ST_TS: begin
+        // A context word passes fwd to the CHDR output
+        chdr_pg_tvalid  = out_ctxt_tvalid;
+        chdr_pg_tlast   = 1'b0;   // tlast is inherited from the data stream
+        out_ctxt_tready = chdr_pg_tready;
+        out_pyld_tready = 1'b0;
+      end
+      ST_MDATA: begin
+        // A context word passes fwd to the CHDR output
+        chdr_pg_tvalid  = out_ctxt_tvalid;
+        chdr_pg_tlast   = 1'b0;   // tlast is inherited from the data stream
+        out_ctxt_tready = chdr_pg_tready;
+        out_pyld_tready = 1'b0;
+      end
+      ST_BODY: begin
+        // A payload word passes fwd to the CHDR output
+        chdr_pg_tvalid  = out_pyld_tvalid;
+        chdr_pg_tlast   = out_pyld_tlast;
+        out_ctxt_tready = 1'b0;
+        out_pyld_tready = chdr_pg_tready;
+      end
+      ST_DROP_CTXT: begin
+        // A context word is consumed without passing fwd
+        chdr_pg_tvalid  = 1'b0;
+        chdr_pg_tlast   = 1'b0;
+        out_ctxt_tready = 1'b1;
+        out_pyld_tready = 1'b0;
+      end
+      ST_DROP_PYLD: begin
+        // A payload word is consumed without passing fwd
+        chdr_pg_tvalid  = 1'b0;
+        chdr_pg_tlast   = 1'b0;
+        out_ctxt_tready = 1'b0;
+        out_pyld_tready = 1'b1;
+      end
+      ST_TERMINATE: begin
+        // A dummy word with a tlast and terror is passed fwd
+        // to evacuate the current packet from the packet_gate
+        chdr_pg_tvalid  = 1'b1;
+        chdr_pg_tlast   = 1'b1;
+        out_ctxt_tready = 1'b0;
+        out_pyld_tready = 1'b0;
+      end
+      default: begin
+        chdr_pg_tvalid  = 1'b0;
+        chdr_pg_tlast   = 1'b0;
+        out_ctxt_tready = 1'b0;
+        out_pyld_tready = 1'b0;
+      end
+    endcase
+  end
+
+  assign chdr_pg_tdata  = (state == ST_BODY) ? out_pyld_tdata : out_ctxt_tdata;
+  assign chdr_pg_terror = (state == ST_TERMINATE);
+
+  // ---------------------------------------------------
+  //  Packet gate
+  // ---------------------------------------------------
+
+  wire [CHDR_W-1:0] chdr_flush_tdata;
+  wire              chdr_flush_tlast, chdr_flush_tvalid;
+  wire              chdr_flush_terror, chdr_flush_tready;
+
+  axis_packet_flush #(
+    .WIDTH(CHDR_W+1), .FLUSH_PARTIAL_PKTS(0), .TIMEOUT_W(32), .PIPELINE("IN")
+  ) chdr_flusher_i (
+    .clk(axis_chdr_clk), .reset(axis_chdr_rst),
+    .enable(flush_en), .timeout(flush_timeout),
+    .flushing(flush_active), .done(flush_done),
+    .s_axis_tdata({chdr_pg_terror, chdr_pg_tdata}), .s_axis_tlast(chdr_pg_tlast),
+    .s_axis_tvalid(chdr_pg_tvalid), .s_axis_tready(chdr_pg_tready),
+    .m_axis_tdata({chdr_flush_terror, chdr_flush_tdata}), .m_axis_tlast(chdr_flush_tlast),
+    .m_axis_tvalid(chdr_flush_tvalid), .m_axis_tready(chdr_flush_tready)
+  );
+
+  axi_packet_gate #( .WIDTH(CHDR_W), .SIZE(MTU), .USE_AS_BUFF(0) ) out_gate_i (
+    .clk(axis_chdr_clk), .reset(axis_chdr_rst), .clear(flush_active),
+    .i_tdata(chdr_flush_tdata), .i_tlast(chdr_flush_tlast), .i_terror(chdr_flush_terror),
+    .i_tvalid(chdr_flush_tvalid), .i_tready(chdr_flush_tready),
+    .o_tdata(m_axis_chdr_tdata), .o_tlast(m_axis_chdr_tlast),
+    .o_tvalid(m_axis_chdr_tvalid), .o_tready(m_axis_chdr_tready)
+  );
+
+endmodule // axis_pyld_ctxt_to_chdr
diff --git a/fpga/usrp3/lib/rfnoc/core/backend_iface.v b/fpga/usrp3/lib/rfnoc/core/backend_iface.v
new file mode 100644
index 000000000..59429ea6b
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/core/backend_iface.v
@@ -0,0 +1,142 @@
+//
+// Copyright 2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: backend_iface
+// Description:
+//   A noc_shell interface to the backend infrastructure
+//
+
+module backend_iface #(
+  parameter [31:0] NOC_ID              = 32'h0,
+  parameter  [5:0] NUM_DATA_I          = 0,
+  parameter  [5:0] NUM_DATA_O          = 0,
+  parameter  [5:0] CTRL_FIFOSIZE       = 0,
+  parameter  [7:0] CTRL_MAX_ASYNC_MSGS = 0,
+  parameter  [5:0] MTU                 = 0
+)(
+  // Input clock
+  input  wire         rfnoc_chdr_clk,
+  input  wire         rfnoc_ctrl_clk,
+  // Backend interface (sync. to rfnoc_ctrl_clk)
+  input  wire [511:0] rfnoc_core_config,
+  output wire [511:0] rfnoc_core_status,
+  // Output reset
+  output wire         rfnoc_chdr_rst,
+  output wire         rfnoc_ctrl_rst,
+  // Flush interface (sync. to rfnoc_chdr_clk)
+  output wire         data_i_flush_en,
+  output wire [31:0]  data_i_flush_timeout,
+  input  wire [63:0]  data_i_flush_active,
+  input  wire [63:0]  data_i_flush_done,
+  output wire         data_o_flush_en,
+  output wire [31:0]  data_o_flush_timeout,
+  input  wire [63:0]  data_o_flush_active,
+  input  wire [63:0]  data_o_flush_done
+);
+  localparam RESET_LENGTH = 32;
+
+  `include "rfnoc_backend_iface.vh"
+
+  // -----------------------------------
+  // CONFIG: Infrastructure => Block
+  // -----------------------------------
+  wire [BEC_TOTAL_WIDTH-1:0] rfnoc_core_config_trim = rfnoc_core_config[BEC_TOTAL_WIDTH-1:0];
+
+  reg  [31:0] flush_timeout_ctclk = 32'd0;
+  reg         flush_en_ctclk      = 1'b0;
+  reg         soft_ctrl_rst_ctclk = 1'b0;
+  reg         soft_chdr_rst_ctclk = 1'b0;
+
+  // Register logic before synchronizer
+  always @(posedge rfnoc_ctrl_clk) begin
+    flush_timeout_ctclk <= rfnoc_core_config_trim[BEC_FLUSH_TIMEOUT_OFFSET +: BEC_FLUSH_TIMEOUT_WIDTH];
+    flush_en_ctclk      <= rfnoc_core_config_trim[BEC_FLUSH_EN_OFFSET      +: BEC_FLUSH_EN_WIDTH     ];
+    soft_ctrl_rst_ctclk <= rfnoc_core_config_trim[BEC_SOFT_CTRL_RST_OFFSET +: BEC_SOFT_CTRL_RST_WIDTH];
+    soft_chdr_rst_ctclk <= rfnoc_core_config_trim[BEC_SOFT_CHDR_RST_OFFSET +: BEC_SOFT_CHDR_RST_WIDTH];
+  end
+
+  // Synchronizer
+  wire [31:0] flush_timeout_chclk;
+  wire        flush_en_chclk;
+
+  // Note: We are using a synchronizer to cross the 32-bit timeout bus
+  // into a different clock domain. Typically we would use a 2clk FIFO
+  // but it's OK to have the bits unsynchronized here because the value
+  // is static and is set from SW long before it is actually used.
+
+  synchronizer #(.WIDTH(33), .INITIAL_VAL(33'd0)) sync_ctrl_i (
+    .clk(rfnoc_chdr_clk), .rst(1'b0),
+    .in({flush_en_ctclk, flush_timeout_ctclk}),
+    .out({flush_en_chclk, flush_timeout_chclk})
+  );
+
+  // Synchronize the reset to the CHDR and CTRL clock domains, and extend the 
+  // reset pulse to make it long enough for most IP to reset correctly.
+
+  wire rfnoc_ctrl_rst_pulse;
+  wire rfnoc_chdr_rst_pulse;
+
+  pulse_synchronizer #(.MODE("POSEDGE")) soft_ctrl_rst_sync_i (
+    .clk_a(rfnoc_ctrl_clk), .rst_a(1'b0), .pulse_a(soft_ctrl_rst_ctclk), .busy_a(),
+    .clk_b(rfnoc_ctrl_clk), .pulse_b(rfnoc_ctrl_rst_pulse)
+  );
+
+  pulse_synchronizer #(.MODE("POSEDGE")) soft_chdr_rst_sync_i (
+    .clk_a(rfnoc_ctrl_clk), .rst_a(1'b0), .pulse_a(soft_chdr_rst_ctclk), .busy_a(),
+    .clk_b(rfnoc_chdr_clk), .pulse_b(rfnoc_chdr_rst_pulse)
+  );
+
+  pulse_stretch_min #(.LENGTH(RESET_LENGTH)) soft_ctrl_rst_stretch_i (
+    .clk(rfnoc_ctrl_clk), .rst(1'b0),
+    .pulse_in(rfnoc_ctrl_rst_pulse), .pulse_out(rfnoc_ctrl_rst)
+  );
+
+  pulse_stretch_min #(.LENGTH(RESET_LENGTH)) soft_chdr_rst_stretch_i (
+    .clk(rfnoc_chdr_clk), .rst(1'b0),
+    .pulse_in(rfnoc_chdr_rst_pulse), .pulse_out(rfnoc_chdr_rst)
+  );
+
+  assign data_i_flush_timeout = flush_timeout_chclk;
+  assign data_o_flush_timeout = flush_timeout_chclk;
+  assign data_i_flush_en      = flush_en_chclk;
+  assign data_o_flush_en      = flush_en_chclk;
+
+  // -----------------------------------
+  // STATUS: Block => Infrastructure
+  // -----------------------------------
+
+  reg  flush_active_chclk  = 1'b0;
+  reg  flush_done_chclk    = 1'b0;
+
+  // Register logic before synchronizer
+  wire flush_active_ctclk;
+  wire flush_done_ctclk;
+
+  always @(posedge rfnoc_chdr_clk) begin
+    flush_active_chclk <= (|data_i_flush_active[NUM_DATA_I-1:0]) | (|data_o_flush_active[NUM_DATA_O-1:0]);
+    flush_done_chclk   <= (&data_i_flush_done  [NUM_DATA_I-1:0]) & (&data_o_flush_done  [NUM_DATA_O-1:0]);
+  end
+
+  // Synchronizer
+  synchronizer #(.WIDTH(2), .INITIAL_VAL(2'd0)) sync_status_i (
+    .clk(rfnoc_ctrl_clk), .rst(1'b0),
+    .in({flush_active_chclk, flush_done_chclk}),
+    .out({flush_active_ctclk, flush_done_ctclk})
+  );
+
+  assign rfnoc_core_status[BES_PROTO_VER_OFFSET          +:BES_PROTO_VER_WIDTH          ] = BACKEND_PROTO_VER;
+  assign rfnoc_core_status[BES_NUM_DATA_I_OFFSET         +:BES_NUM_DATA_I_WIDTH         ] = NUM_DATA_I;
+  assign rfnoc_core_status[BES_NUM_DATA_O_OFFSET         +:BES_NUM_DATA_O_WIDTH         ] = NUM_DATA_O;
+  assign rfnoc_core_status[BES_CTRL_FIFOSIZE_OFFSET      +:BES_CTRL_FIFOSIZE_WIDTH      ] = CTRL_FIFOSIZE;
+  assign rfnoc_core_status[BES_CTRL_MAX_ASYNC_MSGS_OFFSET+:BES_CTRL_MAX_ASYNC_MSGS_WIDTH] = CTRL_MAX_ASYNC_MSGS;
+  assign rfnoc_core_status[BES_NOC_ID_OFFSET             +:BES_NOC_ID_WIDTH             ] = NOC_ID;
+  assign rfnoc_core_status[BES_FLUSH_ACTIVE_OFFSET       +:BES_FLUSH_ACTIVE_WIDTH       ] = flush_active_ctclk;
+  assign rfnoc_core_status[BES_FLUSH_DONE_OFFSET         +:BES_FLUSH_DONE_WIDTH         ] = flush_done_ctclk;
+  assign rfnoc_core_status[BES_DATA_MTU_OFFSET           +:BES_DATA_MTU_WIDTH           ] = MTU;
+  // Assign the rest to 0
+  assign rfnoc_core_status[511:BES_TOTAL_WIDTH] = {(512-BES_TOTAL_WIDTH){1'b0}};
+
+endmodule // backend_iface
+
diff --git a/fpga/usrp3/lib/rfnoc/core/chdr_compute_tkeep.v b/fpga/usrp3/lib/rfnoc/core/chdr_compute_tkeep.v
new file mode 100644
index 000000000..72c5bab13
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/core/chdr_compute_tkeep.v
@@ -0,0 +1,86 @@
+//
+// Copyright 2018 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: chdr_compute_tkeep
+// Description:
+//  This module monitors an AXI-Stream CHDR bus and uses the
+//  packet size field in the CHDR header to compute a tkeep
+//  trailer signal to indicate the the valid bytes when
+//  tlast is asserted.
+//
+// Parameters:
+//   - CHDR_W: Width of the CHDR bus in bits
+//   - ITEM_W: Width of the item bus in bits (must be a multiple of 8)
+//
+// Signals:
+//   - axis_* : AXI-Stream CHDR bus
+
+module chdr_compute_tkeep #(
+  parameter CHDR_W = 256,
+  parameter ITEM_W = 32
+)(
+  input  wire                       clk,
+  input  wire                       rst,
+  input  wire [CHDR_W-1:0]          axis_tdata,
+  input  wire                       axis_tlast,
+  input  wire                       axis_tvalid,
+  input  wire                       axis_tready,
+  output wire [(CHDR_W/ITEM_W)-1:0] axis_tkeep
+);
+
+  `include "rfnoc_chdr_utils.vh"
+
+  generate if (CHDR_W > ITEM_W) begin 
+
+    localparam CHDR_W_BYTES = CHDR_W/8;
+    localparam ITEM_W_BYTES = ITEM_W/8;
+    localparam KEEP_W       = CHDR_W_BYTES/ITEM_W_BYTES;
+
+    // Binary to thermometer decoder
+    // 2'd0 => 4'b1111 (special case)
+    // 2'd1 => 4'b0001
+    // 2'd2 => 4'b0011
+    // 2'd3 => 4'b0111
+    function [KEEP_W-1:0] bin2thermo;
+      input [$clog2(KEEP_W)-1:0] bin;
+      bin2thermo = ~((~1)<<((bin-1)%KEEP_W));
+    endfunction
+  
+    // Read the packet length and figure out the number
+    // of trailing items
+    wire [15:0]       pkt_len    = chdr_get_length(axis_tdata[63:0]);
+    wire [KEEP_W-1:0] len_thermo = bin2thermo(pkt_len[$clog2(CHDR_W_BYTES)-1:$clog2(ITEM_W_BYTES)]);
+    reg  [KEEP_W-1:0] reg_len_thermo = 'h0;
+    reg               is_header = 1'b1;
+
+    always @(posedge clk) begin
+      if (rst) begin
+        is_header <= 1'b1;
+      end else if (axis_tvalid & axis_tready) begin
+        is_header <= axis_tlast;
+        if (is_header) begin
+          reg_len_thermo <= len_thermo;
+        end
+      end
+    end
+
+    // tkeep indicates trailing items, so for lines with tlast == 0,
+    // tkeep is all 1's.
+    assign axis_tkeep = (~axis_tlast) ? {KEEP_W{1'b1}} :
+      (is_header ? len_thermo : reg_len_thermo);
+
+  end else if (CHDR_W == ITEM_W) begin
+
+    // Only one item per CHDR word. So always keep it.
+    assign axis_tkeep = 1'b1;
+
+  end else begin
+
+    // Illegal. A item must be smaller than the CHDR_W
+    illegal_parameter_value item_w_cannot_be_larger_than_chdr_w();
+
+  end endgenerate
+
+endmodule // chdr_compute_tkeep
diff --git a/fpga/usrp3/lib/rfnoc/core/chdr_data_swapper.v b/fpga/usrp3/lib/rfnoc/core/chdr_data_swapper.v
new file mode 100644
index 000000000..9b5e96bca
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/core/chdr_data_swapper.v
@@ -0,0 +1,227 @@
+//
+// Copyright 2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: chdr_data_swapper
+// Description:
+//  A module to adapt a CHDR stream to correctly sequence in
+//  a software buffer of a user-specified type. Here are the 
+//  the swapping assumptions:
+//  - The CHDR header, timestamp and metadata for all packet
+//    types must be interpreted as a uint64_t.
+//  - All Control, Stream Status/Cmd, Management packet payloads
+//    must reside in a uint64_t* buffer.
+//  - The buffer type for the data packet payload and metadata
+//    is user configurable
+//
+// Parameters:
+//   - CHDR_W: Width of the tdata bus in bits
+//
+// Signals:
+//   - payload_sw_buff: SW buffer mode for payload (0=u64, 1=u32, 2=u16, 3=u8)
+//   - mdata_sw_buff  : SW buffer mode for metadata (0=u64, 1=u32, 2=u16, 3=u8)
+//   - s_axis_*       : The input AXI stream
+//   - m_axis_*       : The output AXI stream
+//
+
+module chdr_data_swapper #(
+  parameter CHDR_W = 256
+)(
+  // Clock and Reset
+  input  wire              clk,
+  input  wire              rst,
+  // Software Buffer Mode
+  input  wire [1:0]        payload_sw_buff,
+  input  wire [1:0]        mdata_sw_buff,
+  input  wire              swap_endianness,
+  // Input AXIS
+  input  wire [CHDR_W-1:0] s_axis_tdata,
+  input  wire              s_axis_tlast,
+  input  wire              s_axis_tvalid,
+  output wire              s_axis_tready,
+  // Output AXIS           
+  output wire [CHDR_W-1:0] m_axis_tdata,
+  output wire              m_axis_tlast,
+  output wire              m_axis_tvalid,
+  input  wire              m_axis_tready
+);
+
+  `include "../core/rfnoc_chdr_utils.vh"
+
+  // *_sw_buff values
+  localparam [1:0] SW_BUFF_UINT64 = 2'd0;
+  localparam [1:0] SW_BUFF_UINT32 = 2'd1;
+  localparam [1:0] SW_BUFF_UINT16 = 2'd2;
+  localparam [1:0] SW_BUFF_UINT8  = 2'd3;
+
+  localparam SWAP_W = $clog2(CHDR_W);
+
+  // Packet states
+  localparam [2:0] ST_HDR       = 3'd0;
+  localparam [2:0] ST_TS        = 3'd1;
+  localparam [2:0] ST_MDATA     = 3'd2;
+  localparam [2:0] ST_DATA_BODY = 3'd3;
+  localparam [2:0] ST_OTHER     = 3'd4;
+
+  reg [2:0]         state = ST_HDR;
+  reg [4:0]         mdata_pending = CHDR_NO_MDATA;
+  reg [SWAP_W-2:0]  pyld_tswap = 'h0, mdata_tswap = 'h0;
+
+  // Shortcuts: CHDR header
+  wire [2:0] pkt_type = chdr_get_pkt_type(s_axis_tdata[63:0]);
+  wire [4:0] num_mdata = chdr_get_num_mdata(s_axis_tdata[63:0]);
+
+  // State machine to determine packet state
+  always @(posedge clk) begin
+    if (rst) begin
+      state <= ST_HDR;
+    end else if (s_axis_tvalid & s_axis_tready) begin
+      case (state)
+        ST_HDR: begin
+          mdata_pending <= num_mdata;
+          if (!s_axis_tlast) begin
+            if (CHDR_W > 64) begin
+              if (pkt_type == CHDR_PKT_TYPE_DATA || pkt_type == CHDR_PKT_TYPE_DATA_TS) begin
+                if (num_mdata != CHDR_NO_MDATA) begin
+                  state <= ST_MDATA;
+                end else begin
+                  state <= ST_DATA_BODY;
+                end
+              end else begin
+                state <= ST_OTHER;
+              end
+            end else begin
+              if (pkt_type == CHDR_PKT_TYPE_DATA_TS) begin
+                state <= ST_TS;
+              end else if (pkt_type == CHDR_PKT_TYPE_DATA) begin
+                if (num_mdata != CHDR_NO_MDATA) begin
+                  state <= ST_MDATA;
+                end else begin
+                  state <= ST_DATA_BODY;
+                end
+              end else begin
+                state <= ST_OTHER;
+              end
+            end
+          end else begin
+            state <= ST_HDR;
+          end
+        end
+        ST_TS: begin
+          if (!s_axis_tlast) begin
+            if (mdata_pending != CHDR_NO_MDATA) begin
+              state <= ST_MDATA;
+            end else begin
+              state <= ST_DATA_BODY;
+            end
+          end else begin
+            state <= ST_HDR;
+          end
+        end
+        ST_MDATA: begin
+          if (!s_axis_tlast) begin
+            if (mdata_pending == 5'd1) begin
+              state <= ST_DATA_BODY;
+            end else begin
+              mdata_pending <= mdata_pending - 5'd1;
+            end
+          end else begin
+            state <= ST_HDR;
+          end
+        end
+        ST_DATA_BODY: begin
+          if (s_axis_tlast) begin
+            state <= ST_HDR;
+          end
+        end
+        ST_OTHER: begin
+          if (s_axis_tlast) begin
+            state <= ST_HDR;
+          end
+        end
+        default: begin
+          state <= ST_HDR;
+        end
+      endcase
+    end
+  end
+
+  // Convert SW buff size to swap-lane map
+  always @(posedge clk) begin
+    pyld_tswap <= 'h0;
+    mdata_tswap <= 'h0;
+    case (payload_sw_buff)
+      SW_BUFF_UINT8:
+        pyld_tswap[4:2] <= 3'b111;
+      SW_BUFF_UINT16:
+        pyld_tswap[4:2] <= 3'b110;
+      SW_BUFF_UINT32:
+        pyld_tswap[4:2] <= 3'b100;
+      default:
+        pyld_tswap[4:2] <= 3'b000;
+    endcase
+    case (mdata_sw_buff)
+      SW_BUFF_UINT8:
+        mdata_tswap[4:2] <= 3'b111;
+      SW_BUFF_UINT16:
+        mdata_tswap[4:2] <= 3'b110;
+      SW_BUFF_UINT32:
+        mdata_tswap[4:2] <= 3'b100;
+      default:
+        mdata_tswap[4:2] <= 3'b000;
+    endcase
+  end
+
+  wire [SWAP_W-2:0] s_axis_tswap_dyn = 
+    (state == ST_DATA_BODY) ? pyld_tswap : (
+    (state == ST_MDATA) ? mdata_tswap : {(SWAP_W-1){1'b0}}
+  );
+  wire s_axis_tswap_end = swap_endianness && 
+    (state == ST_DATA_BODY || state == ST_MDATA);
+
+  // Swapper that re-aligns items in a buffer for software
+ wire [CHDR_W-1:0] out_swap_tdata, out_swap_tdata_pre;
+ wire              out_swap_tswap_end, out_swap_tlast, out_swap_tvalid, out_swap_tready;
+
+  axis_data_swap #(
+    .DATA_W(CHDR_W), .USER_W(1'b1),
+    .STAGES_EN({{(SWAP_W-6){1'b0}}, 6'b111100}), .DYNAMIC(1)
+  ) chdr_dyn_swap_i (
+    .clk          (clk               ),
+    .rst          (rst               ),
+    .s_axis_tdata (s_axis_tdata      ),
+    .s_axis_tswap (s_axis_tswap_dyn  ),
+    .s_axis_tuser (s_axis_tswap_end  ),
+    .s_axis_tlast (s_axis_tlast      ),
+    .s_axis_tvalid(s_axis_tvalid     ),
+    .s_axis_tready(s_axis_tready     ),
+    .m_axis_tdata (out_swap_tdata_pre),
+    .m_axis_tuser (out_swap_tswap_end),
+    .m_axis_tlast (out_swap_tlast    ),
+    .m_axis_tvalid(out_swap_tvalid   ),
+    .m_axis_tready(out_swap_tready   )
+  );
+
+  // Swapper that pre-corrects for transport endianness
+  genvar i;
+  generate for (i = 0; i < CHDR_W/8; i=i+1) begin
+    assign out_swap_tdata[i*8 +: 8] = out_swap_tswap_end ? 
+      out_swap_tdata_pre[((CHDR_W/8)-i-1)*8 +: 8] : out_swap_tdata_pre[i*8 +: 8];
+  end endgenerate
+
+  axi_fifo_flop2 #(.WIDTH(CHDR_W+1)) out_reg_i (
+    .clk     (clk                             ),
+    .reset   (rst                             ),
+    .clear   (1'b0                            ),
+    .i_tdata ({out_swap_tlast, out_swap_tdata}),
+    .i_tvalid(out_swap_tvalid                 ),
+    .i_tready(out_swap_tready                 ),
+    .o_tdata ({m_axis_tlast, m_axis_tdata}    ),
+    .o_tvalid(m_axis_tvalid                   ),
+    .o_tready(m_axis_tready                   ),
+    .occupied(                                ),
+    .space   (                                )
+  );
+
+endmodule // chdr_data_swapper
diff --git a/fpga/usrp3/lib/rfnoc/core/chdr_ingress_fifo.v b/fpga/usrp3/lib/rfnoc/core/chdr_ingress_fifo.v
new file mode 100644
index 000000000..e2660426f
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/core/chdr_ingress_fifo.v
@@ -0,0 +1,95 @@
+//
+// Copyright 2016 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module chdr_ingress_fifo #(
+  parameter WIDTH  = 64,
+  parameter SIZE   = 12,
+  parameter DEVICE = "7SERIES"
+) (
+  input              clk,
+  input              reset,
+  input              clear,
+
+  input [WIDTH-1:0]  i_tdata,
+  input              i_tlast,
+  input              i_tvalid,
+  output             i_tready,
+
+  output [WIDTH-1:0] o_tdata,
+  output             o_tlast,
+  output             o_tvalid,
+  input              o_tready
+);
+
+  localparam SIZE_THRESHOLD = (
+    (DEVICE == "7SERIES")   ? 14 : (
+    (DEVICE == "VIRTEX6")   ? 14 : (
+    (DEVICE == "SPARTAN6")  ? 12 : (
+    12
+  ))));
+
+  wire [WIDTH-1:0] i_tdata_pre;
+  wire             i_tlast_pre, i_tvalid_pre, i_tready_pre;
+  
+  // SRL based FIFO to break timing paths to BRAM resources
+  axi_fifo_flop2 #(.WIDTH(WIDTH+1)) pre_fifo (
+    .clk(clk), .reset(reset), .clear(clear),
+    .i_tdata({i_tlast, i_tdata}), .i_tvalid(i_tvalid), .i_tready(i_tready),
+    .o_tdata({i_tlast_pre, i_tdata_pre}), .o_tvalid(i_tvalid_pre), .o_tready(i_tready_pre),
+    .space(), .occupied()
+  );
+
+  generate 
+    if (SIZE <= SIZE_THRESHOLD) begin
+      wire [WIDTH-1:0] o_tdata_int;
+      wire             o_tlast_int, o_tvalid_int, o_tready_int;
+      // Instantiate a single axi_fifo if size is not larger than threshold
+      axi_fifo #(.WIDTH(WIDTH+1), .SIZE(SIZE)) main_fifo (
+        .clk(clk), .reset(reset), .clear(clear),
+        .i_tdata({i_tlast_pre, i_tdata_pre}), .i_tvalid(i_tvalid_pre), .i_tready(i_tready_pre),
+        .o_tdata({o_tlast_int, o_tdata_int}), .o_tvalid(o_tvalid_int), .o_tready(o_tready_int),
+        .space(), .occupied()
+      );
+      axi_fifo_flop2 #(.WIDTH(WIDTH+1)) fifo_flop2 (
+        .clk(clk), .reset(reset), .clear(clear),
+        .i_tdata({o_tlast_int, o_tdata_int}), .i_tvalid(o_tvalid_int), .i_tready(o_tready_int),
+        .o_tdata({o_tlast, o_tdata}), .o_tvalid(o_tvalid), .o_tready(o_tready),
+        .space(), .occupied()
+      );
+    end else begin
+      // Instantiate a cascade of axi_fifos if size is larger than threshold
+      localparam CDEPTH = 2**(SIZE - SIZE_THRESHOLD); //Cascade Depth
+      wire [WIDTH-1:0] c_tdata[CDEPTH:0], int_tdata[CDEPTH-1:0];
+      wire             c_tlast[CDEPTH:0], c_tvalid[CDEPTH:0], c_tready[CDEPTH:0];
+      wire             int_tlast[CDEPTH-1:0], int_tvalid[CDEPTH-1:0], int_tready[CDEPTH-1:0];
+      
+      //Connect input to first cascade state
+      assign {c_tdata[0], c_tlast[0], c_tvalid[0]} = {i_tdata_pre, i_tlast_pre, i_tvalid_pre};
+      assign i_tready_pre = c_tready[0];
+      //Connect output to last cascade state
+      assign {o_tdata, o_tlast, o_tvalid} = {c_tdata[CDEPTH], c_tlast[CDEPTH], c_tvalid[CDEPTH]};
+      assign c_tready[CDEPTH] = o_tready;
+
+      genvar i;
+      for (i=0; i<CDEPTH; i=i+1) begin: fifo_stages
+        axi_fifo #(.WIDTH(WIDTH+1), .SIZE(SIZE_THRESHOLD)) main_fifo (
+          .clk(clk), .reset(reset), .clear(clear),
+          .i_tdata({c_tlast[i], c_tdata[i]}), .i_tvalid(c_tvalid[i]), .i_tready(c_tready[i]),
+          .o_tdata({int_tlast[i], int_tdata[i]}), .o_tvalid(int_tvalid[i]), .o_tready(int_tready[i]),
+          .space(), .occupied()
+        );
+        axi_fifo_flop2 #(.WIDTH(WIDTH+1)) fifo_flop2 (
+          .clk(clk), .reset(reset), .clear(clear),
+          .i_tdata({int_tlast[i], int_tdata[i]}), .i_tvalid(int_tvalid[i]), .i_tready(int_tready[i]),
+          .o_tdata({c_tlast[i+1], c_tdata[i+1]}), .o_tvalid(c_tvalid[i+1]), .o_tready(c_tready[i+1]),
+          .space(), .occupied()
+        );
+      end
+    end
+  endgenerate
+
+endmodule // axi_fifo_large
diff --git a/fpga/usrp3/lib/rfnoc/core/chdr_mgmt_pkt_handler.v b/fpga/usrp3/lib/rfnoc/core/chdr_mgmt_pkt_handler.v
new file mode 100644
index 000000000..f9c56a6e1
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/core/chdr_mgmt_pkt_handler.v
@@ -0,0 +1,617 @@
+//
+// Copyright 2018 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: chdr_mgmt_pkt_handler
+// Description:
+//   This module sits inline on a CHDR stream and adds a management
+//   node that is discoverable and configurable by software. As a 
+//   management node, a control-port master to configure any slave.
+//   The output CHDR stream has an additional tdest and tid which can
+//   be used to make routing decisions for management packets only.
+//   tid will be CHDR_MGMT_ROUTE_TDEST when tdest should be used.
+//
+// Parameters:
+//   - PROTOVER: RFNoC protocol version {8'd<major>, 8'd<minor>}
+//   - CHDR_W: Width of the CHDR bus in bits
+//   - USER_W: Width of the user/data bits that accompany an advertisement op
+//   - RESP_FIFO_SIZE: Log2 of the depth of the response FIFO
+//                     Maximum value = 8
+//
+// Signals:
+//   - s_axis_chdr_* : Input CHDR stream (AXI-Stream)
+//   - m_axis_chdr_* : Output CHDR stream (AXI-Stream)
+//   - node_info: Info about the node that contains this management slave
+//   - ctrlport_* : Control-port master for management peripheral
+//   - op_*: Strobe and info signals for a mgmt advertisement
+
+module chdr_mgmt_pkt_handler #(
+  parameter [15:0] PROTOVER       = {8'd1, 8'd0},
+  parameter        CHDR_W         = 256,
+  parameter        USER_W         = 1,
+  parameter [0:0]  MGMT_ONLY      = 0,
+  parameter        RESP_FIFO_SIZE = 5
+)(
+  // Clock, reset and settings
+  input  wire              clk,
+  input  wire              rst,
+  // Node Info
+  input  wire [47:0]       node_info,
+  // CHDR Data In (AXI-Stream)
+  input  wire [CHDR_W-1:0] s_axis_chdr_tdata,
+  input  wire              s_axis_chdr_tlast,
+  input  wire              s_axis_chdr_tvalid,
+  output wire              s_axis_chdr_tready,
+  input  wire [USER_W-1:0] s_axis_chdr_tuser,
+  // CHDR Data Out (AXI-Stream)             
+  output wire [CHDR_W-1:0] m_axis_chdr_tdata,
+  output wire [1:0]        m_axis_chdr_tid,      // Routing mode. Values defined in rfnoc_chdr_internal_utils.vh
+  output wire [9:0]        m_axis_chdr_tdest,    // Manual routing destination (only valid for tid = CHDR_MGMT_ROUTE_TDEST)
+  output wire              m_axis_chdr_tlast,
+  output wire              m_axis_chdr_tvalid,
+  input  wire              m_axis_chdr_tready,
+  // Control port endpoint
+  output reg               ctrlport_req_wr,
+  output reg               ctrlport_req_rd,
+  output reg  [15:0]       ctrlport_req_addr,
+  output reg  [31:0]       ctrlport_req_data,
+  input  wire              ctrlport_resp_ack,
+  input  wire [31:0]       ctrlport_resp_data,
+  // Mgmt packet advertisement  strobe
+  output wire [USER_W-1:0] op_data,
+  output wire              op_stb,
+  output wire [15:0]       op_dst_epid,
+  output wire [15:0]       op_src_epid
+);
+
+  // ---------------------------------------------------
+  //  RFNoC Includes
+  // ---------------------------------------------------
+  `include "rfnoc_chdr_utils.vh"
+  `include "rfnoc_chdr_internal_utils.vh"
+
+  // ---------------------------------------------------
+  //  Instantiate input demux and output mux to allow
+  //  non-management packets to be bypassed
+  // ---------------------------------------------------
+
+  localparam CHDR_W_BYTES = CHDR_W / 8;
+  localparam LOG2_CHDR_W_BYTES = $clog2(CHDR_W_BYTES);
+
+  wire [CHDR_W-1:0] s_mgmt_tdata, m_mgmt_tdata;
+  wire [USER_W-1:0] s_mgmt_tuser;
+  wire [9:0]        m_mgmt_tdest;
+  wire [1:0]        m_mgmt_tid;
+  wire              s_mgmt_tlast, s_mgmt_tvalid, s_mgmt_tready;
+  wire              m_mgmt_tlast, m_mgmt_tvalid, m_mgmt_tready;
+
+  generate if (!MGMT_ONLY) begin
+    // Instantiate MUX and DEMUX to segregate management and non-management packets.
+    // Management packets go to the main state machine, all others get bypassed to
+    // the output.
+    wire [CHDR_W-1:0] bypass_tdata;
+    wire [9:0]        bypass_tdest;
+    wire [1:0]        bypass_tid;
+    wire              bypass_tlast, bypass_tvalid, bypass_tready;
+    wire [CHDR_W-1:0] s_header;
+
+    // We consume the management packet only if it is actually a management packet and we
+    // don't know where it's going. If the packet has a valid EPID, it is a response that
+    // is capable of being routed.
+    wire consume_mgmt_pkt = (chdr_get_pkt_type(s_header[63:0]) == CHDR_PKT_TYPE_MGMT) && 
+                            (chdr_get_dst_epid(s_header[63:0]) == NULL_EPID);
+
+    axi_demux #(
+      .WIDTH(CHDR_W), .SIZE(2), .PRE_FIFO_SIZE(1), .POST_FIFO_SIZE(0)
+    ) mgmt_demux_i (
+      .clk(clk), .reset(rst), .clear(1'b0),
+      .header(s_header), .dest(consume_mgmt_pkt ? 1'b1 : 1'b0),
+      .i_tdata(s_axis_chdr_tdata), .i_tlast(s_axis_chdr_tlast),
+      .i_tvalid(s_axis_chdr_tvalid), .i_tready(s_axis_chdr_tready),
+      .o_tdata({s_mgmt_tdata, bypass_tdata}), .o_tlast({s_mgmt_tlast, bypass_tlast}),
+      .o_tvalid({s_mgmt_tvalid, bypass_tvalid}), .o_tready({s_mgmt_tready, bypass_tready})
+    );
+
+    // Only one cycle of delay, so can skip past the demux with the tuser bits
+    // Packets are longer than the latency through the axi_demux
+    assign s_mgmt_tuser               = s_axis_chdr_tuser;
+
+    assign {bypass_tid, bypass_tdest} = {CHDR_MGMT_ROUTE_EPID, 10'h0};
+
+    axi_mux #(
+      .WIDTH(CHDR_W+10+2), .SIZE(2), .PRE_FIFO_SIZE(0), .POST_FIFO_SIZE(1)
+    ) mgmt_mux_i (
+      .clk(clk), .reset(rst), .clear(1'b0),
+      .i_tdata({m_mgmt_tid, m_mgmt_tdest, m_mgmt_tdata, bypass_tid, bypass_tdest, bypass_tdata}),
+      .i_tlast({m_mgmt_tlast, bypass_tlast}),
+      .i_tvalid({m_mgmt_tvalid, bypass_tvalid}), .i_tready({m_mgmt_tready, bypass_tready}),
+      .o_tdata({m_axis_chdr_tid, m_axis_chdr_tdest, m_axis_chdr_tdata}),
+      .o_tlast(m_axis_chdr_tlast),
+      .o_tvalid(m_axis_chdr_tvalid), .o_tready(m_axis_chdr_tready)
+    );
+  end else begin
+    // We are assuming that only management packets come into this module so we don't
+    // instantiate a bypass path to save resources.
+    assign s_mgmt_tdata       = s_axis_chdr_tdata;
+    assign s_mgmt_tlast       = s_axis_chdr_tlast;
+    assign s_mgmt_tvalid      = s_axis_chdr_tvalid;
+    assign s_mgmt_tuser       = s_axis_chdr_tuser;
+    assign s_axis_chdr_tready = s_mgmt_tready;
+
+    assign m_axis_chdr_tdata  = m_mgmt_tdata;
+    assign m_axis_chdr_tdest  = m_mgmt_tdest;
+    assign m_axis_chdr_tid    = m_mgmt_tid;
+    assign m_axis_chdr_tlast  = m_mgmt_tlast;
+    assign m_axis_chdr_tvalid = m_mgmt_tvalid;
+    assign m_mgmt_tready      = m_axis_chdr_tready;
+  end endgenerate
+
+  // ---------------------------------------------------
+  //  Convert management packets to 64-bit
+  //  For CHDR_W > 64, only the bottom 64 bits are used
+  // ---------------------------------------------------
+  wire [63:0]       i64_tdata;
+  wire [USER_W-1:0] i64_tuser;
+  wire              i64_tlast, i64_tvalid;
+  reg               i64_tready;
+  reg [63:0]        o64_tdata;
+  reg [9:0]         o64_tdest;
+  reg [1:0]         o64_tid;
+  reg               o64_tlast, o64_tvalid;
+  wire              o64_tready;
+
+  axi_fifo #(.WIDTH(USER_W+65), .SIZE(1)) in_flop_i (
+    .clk(clk), .reset(rst), .clear(1'b0),
+    .i_tdata({s_mgmt_tuser, s_mgmt_tlast, s_mgmt_tdata[63:0]}),
+    .i_tvalid(s_mgmt_tvalid), .i_tready(s_mgmt_tready),
+    .o_tdata({i64_tuser, i64_tlast, i64_tdata}),
+    .o_tvalid(i64_tvalid), .o_tready(i64_tready),
+    .space(), .occupied()
+  );
+
+  axi_fifo #(.WIDTH(64+10+2+1), .SIZE(1)) out_flop_i (
+    .clk(clk), .reset(rst), .clear(1'b0),
+    .i_tdata({o64_tlast, o64_tdest, o64_tid, o64_tdata}),
+    .i_tvalid(o64_tvalid), .i_tready(o64_tready),
+    .o_tdata({m_mgmt_tlast, m_mgmt_tdest, m_mgmt_tid, m_mgmt_tdata[63:0]}),
+    .o_tvalid(m_mgmt_tvalid), .o_tready(m_mgmt_tready),
+    .space(), .occupied()
+  );
+
+  generate 
+    if (CHDR_W > 64)
+      assign m_mgmt_tdata[CHDR_W-1:CHDR_W-64] = 'h0;
+  endgenerate
+
+  // ---------------------------------------------------
+  //  Parse management packet
+  // ---------------------------------------------------
+  localparam [3:0] ST_CHDR_IN_HDR     = 4'd0;   // Consuming input CHDR header
+  localparam [3:0] ST_CHDR_IN_MDATA   = 4'd1;   // Discarding input CHDR metadata
+  localparam [3:0] ST_MGMT_IN_HDR     = 4'd2;   // Consuming input management header
+  localparam [3:0] ST_MGMT_OP_EXEC    = 4'd3;   // Management operation started
+  localparam [3:0] ST_MGMT_OP_WAIT    = 4'd4;   // Waiting for management op to finish
+  localparam [3:0] ST_MGMT_OP_DONE    = 4'd5;   // Consuming management op line
+  localparam [3:0] ST_CHDR_OUT_HDR    = 4'd6;   // Outputing a CHDR header
+  localparam [3:0] ST_MGMT_OUT_HDR    = 4'd7;   // Outputing a managment header
+  localparam [3:0] ST_PASS_PAYLOAD    = 4'd8;   // Passing payload for downstream hops
+  localparam [3:0] ST_MOD_LAST_HOP    = 4'd9;   // Processing last hop
+  localparam [3:0] ST_POP_RESPONSE    = 4'd10;  // Popping response from response FIFO
+  localparam [3:0] ST_APPEND_LAST_HOP = 4'd11;  // Appending response to last hop
+  localparam [3:0] ST_FAILSAFE_DROP   = 4'd12;  // Something went wrong. Flushing input.
+
+  // Pieces of state maintained by this state machine
+  reg [3:0]  pkt_state = ST_CHDR_IN_HDR;        // The state variable
+  reg [4:0]  num_mdata;                         // Number of metadata lines in packet
+  reg [63:0] cached_chdr_hdr, cached_mgmt_hdr;  // Cached copies of the CHDR and mgmt headers
+  reg [15:0] stripped_len;                      // The new CHDR length after ops are stripped
+  reg [9:0]  hops_remaining;                    // Number of hops remaining until pkt is consumed
+  reg [7:0]  resp_op_code;                      // Opcode for the response
+  reg [47:0] resp_op_payload;                   // Payload for the response
+  reg [USER_W-1:0] cached_tuser;                // Cached copy of the tuser bits (for the advertise op)
+
+  // Shortcuts
+  wire [7:0]  op_code = chdr_mgmt_get_op_code(i64_tdata);
+  wire [47:0] op_payload = chdr_mgmt_get_op_payload(i64_tdata);
+
+  // Inputs and outputs for the response FIFO
+  wire [55:0] resp_i_tdata, resp_o_tdata;
+  wire        resp_i_tvalid, resp_o_tvalid;
+  wire [7:0]  num_resp_pending;
+
+  // The massive state machine
+  // -------------------------
+  always @(posedge clk) begin
+    if (rst) begin
+      // We just need to initialize pkt_state here.
+      // All other registers are initialized in states before their usage
+      pkt_state <= ST_CHDR_IN_HDR;
+    end else begin
+      case (pkt_state)
+
+        // ST_CHDR_IN_HDR
+        // ------------------
+        // - Cache and consume the CHDR header. It will be modified
+        //   later before the packet is sent out.
+        // - Initialize CHDR specific state
+        ST_CHDR_IN_HDR: begin
+          if (i64_tvalid && i64_tready) begin
+            cached_chdr_hdr <= i64_tdata;
+            cached_tuser <= i64_tuser;
+            stripped_len <= chdr_get_length(i64_tdata);
+            num_mdata <= chdr_get_num_mdata(i64_tdata) - 5'd1;
+            if (!i64_tlast) begin
+              if (chdr_get_pkt_type(i64_tdata) != CHDR_PKT_TYPE_MGMT)
+                pkt_state <= ST_FAILSAFE_DROP;  // Drop non-mgmt packets
+              else if (chdr_get_num_mdata(i64_tdata) != CHDR_NO_MDATA)
+                pkt_state <= ST_CHDR_IN_MDATA;  // Skip over metadata
+              else
+                pkt_state <= ST_MGMT_IN_HDR;    // Start processing packet
+            end else begin
+              pkt_state <= ST_CHDR_IN_HDR;      // Premature termination
+            end
+          end
+        end
+
+        // ST_CHDR_IN_MDATA
+        // ------------------
+        // - Discard incoming CHDR metadata
+        ST_CHDR_IN_MDATA: begin
+          if (i64_tvalid && i64_tready) begin
+            num_mdata <= num_mdata - 5'd1;
+            if (!i64_tlast)
+              pkt_state <= (num_mdata == CHDR_NO_MDATA) ? ST_MGMT_IN_HDR : ST_CHDR_IN_MDATA;
+            else
+              pkt_state <= ST_CHDR_IN_HDR;  // Premature termination
+          end
+        end
+
+        // ST_MGMT_IN_HDR
+        // ------------------
+        // - Cache and consume the managment header. It will be modified
+        //   later before the packet is sent out.
+        // - Initialize management specific state
+        ST_MGMT_IN_HDR: begin
+          if (i64_tvalid && i64_tready) begin
+            cached_mgmt_hdr <= i64_tdata;
+            hops_remaining <= chdr_mgmt_get_num_hops(i64_tdata);
+            pkt_state <= (!i64_tlast) ? ST_MGMT_OP_EXEC : ST_CHDR_IN_HDR;
+          end
+        end
+
+        // ST_MGMT_OP_EXEC
+        // ------------------
+        // - We are processing a management operation for this hop
+        // - Launch the requested action be looking at the op_code
+        ST_MGMT_OP_EXEC: begin
+          if (i64_tvalid) begin
+            // Assume that the packet is getting routed normally
+            // unless some operation changes that
+            o64_tid   <= CHDR_MGMT_ROUTE_EPID;
+            o64_tdest <= 10'd0;
+            case (op_code)
+              // Operation: Do nothing
+              CHDR_MGMT_OP_NOP: begin
+                // No-op. Jump to the finish state
+                pkt_state <= ST_MGMT_OP_DONE;
+              end
+              // Operation: Advertise this management packet to outside logic
+              CHDR_MGMT_OP_ADVERTISE: begin
+                // Pretty much a no-op. Jump to the finish state
+                pkt_state <= ST_MGMT_OP_DONE;
+              end
+              // Operation: Select a destination (tdest and tid) for the output CHDR stream
+              CHDR_MGMT_OP_SEL_DEST: begin
+                o64_tid   <= CHDR_MGMT_ROUTE_TDEST;
+                o64_tdest <= chdr_mgmt_sel_dest_get_tdest(op_payload);
+                pkt_state <= ST_MGMT_OP_DONE;   // Single cycle op
+              end
+              // Operation: Return the packet to source (turn it around)
+              CHDR_MGMT_OP_RETURN: begin
+                o64_tid   <= CHDR_MGMT_RETURN_TO_SRC;
+                pkt_state <= ST_MGMT_OP_DONE; // Single cycle op
+              end
+              // Operation: Handle a node information request.
+              //            Send the info as a response
+              CHDR_MGMT_OP_INFO_REQ: begin
+                pkt_state <= ST_MGMT_OP_DONE; // Single cycle op
+              end
+              // Operation: Handle a node information response.
+              //            Treat as a no-op because this is a slave
+              CHDR_MGMT_OP_INFO_RESP: begin
+                pkt_state <= ST_MGMT_OP_DONE;
+              end
+              // Operation: Post a write on the outgoing control-port
+              CHDR_MGMT_OP_CFG_WR_REQ: begin
+                // ctrlport_req_* signals are assigned below
+                pkt_state <= ST_MGMT_OP_WAIT; // Wait until ACKed
+              end
+              // Operation: Post a read on the outgoing control-port
+              CHDR_MGMT_OP_CFG_RD_REQ: begin
+                // ctrlport_req_* signals are assigned below
+                pkt_state <= ST_MGMT_OP_WAIT; // Wait until ACKed
+              end
+              // Operation: Handle a read response.
+              //            Treat as a no-op because this is a slave
+              CHDR_MGMT_OP_CFG_RD_RESP: begin
+                pkt_state <= ST_MGMT_OP_DONE;
+              end
+              default: begin
+                // We should never get here
+                pkt_state <= ST_CHDR_IN_HDR;
+              end
+            endcase
+          end
+        end
+
+        // ST_MGMT_OP_WAIT
+        // ------------------
+        // - A management operation has started. We are waiting for it to finish
+        ST_MGMT_OP_WAIT: begin
+          if (i64_tvalid) begin
+            if (op_code == CHDR_MGMT_OP_CFG_WR_REQ ||
+                op_code == CHDR_MGMT_OP_CFG_RD_REQ) begin
+              // Wait for an control-port transaction to finish
+              if (ctrlport_resp_ack) begin
+                pkt_state <= ST_MGMT_OP_DONE;
+              end
+            end else begin
+              // All other operations should not get here
+              pkt_state <= ST_MGMT_OP_DONE;
+            end
+          end
+        end
+
+        // ST_MGMT_OP_DONE
+        // ------------------
+        // - The management operation has finished
+        // - Consume a word on the input CHDR stream and update interal state
+        ST_MGMT_OP_DONE: begin
+          if (i64_tvalid && i64_tready) begin
+            if (!i64_tlast) begin
+              // We just consumed 8-bytes from the incoming packet
+              stripped_len <= stripped_len - CHDR_W_BYTES;
+              // Check if this was the last op for this hop. If so start
+              // to output a packet, otherwise start the next op.
+              if (chdr_mgmt_get_ops_pending(i64_tdata) == 8'd0) begin
+                hops_remaining <= hops_remaining - 10'd1;
+                pkt_state <= ST_CHDR_OUT_HDR;
+              end else begin
+                pkt_state <= ST_MGMT_OP_EXEC;
+              end
+            end else begin
+              // Premature termination or this is the last operation
+              // Either way, move back to the beginning of the next pkt
+              pkt_state <= ST_CHDR_IN_HDR;
+            end
+          end
+        end
+
+        // ST_CHDR_OUT_HDR
+        // ------------------
+        // - We are outputing the CHDR header
+        ST_CHDR_OUT_HDR: begin
+          if (o64_tvalid && o64_tready)
+            pkt_state <= ST_MGMT_OUT_HDR;
+        end
+
+        // ST_CHDR_OUT_HDR
+        // ------------------
+        // - We are outputing the management header
+        ST_MGMT_OUT_HDR: begin
+          if (o64_tvalid && o64_tready)
+            if (resp_o_tvalid && (hops_remaining == 10'd1))
+              pkt_state <= ST_MOD_LAST_HOP;   // Special state to append responses to last hod
+            else
+              pkt_state <= ST_PASS_PAYLOAD;   // Just pass the data as-is
+        end
+
+        // ST_PASS_PAYLOAD
+        // ------------------
+        // - We are passing the payload for the downstream hops as-is
+        ST_PASS_PAYLOAD: begin
+          if (o64_tvalid && o64_tready) begin
+            if (!i64_tlast) begin
+              // Check if this was the last op for this hop. If so update
+              // the hop count. If this is the last hop then enter the next
+              // state to process it. We might need to append responses for our
+              // management operations.
+              if (chdr_mgmt_get_ops_pending(i64_tdata) == 8'd0) begin
+                hops_remaining <= hops_remaining - 10'd1;
+                if (resp_o_tvalid && (hops_remaining == 10'd1))
+                  pkt_state <= ST_MOD_LAST_HOP;   // Special state to append responses to last hod
+                else
+                  pkt_state <= ST_PASS_PAYLOAD;   // Just pass the data as-is
+              end else begin
+                pkt_state <= ST_PASS_PAYLOAD;
+              end
+            end else begin
+              pkt_state <= ST_CHDR_IN_HDR;
+            end
+          end
+        end
+
+        // ST_MOD_LAST_HOP
+        // ------------------
+        // - We are processing the last hop. We need a special state because we
+        //   need to update the "ops_pending" field if we have responses to tack
+        //   on to the end of the hop.
+        // - We continue to pass the input to the output while modifying ops_pending
+        // - For the last op, we move to the APPEND state if we need to add responses
+        ST_MOD_LAST_HOP: begin
+          if (o64_tvalid && o64_tready) begin
+              // Check if this was the last op for this hop.
+            if (chdr_mgmt_get_ops_pending(i64_tdata) == 8'd0) begin
+              if (resp_o_tvalid)
+                pkt_state <= ST_POP_RESPONSE;  // We have pending responses
+              else
+                pkt_state <= i64_tlast ? ST_CHDR_IN_HDR : ST_FAILSAFE_DROP;
+            end
+          end
+        end
+
+        // ST_POP_RESPONSE
+        // ------------------
+        // - Pop a response word from the FIFO
+        ST_POP_RESPONSE: begin
+          if (resp_o_tvalid) begin
+            resp_op_code <= resp_o_tdata[7:0];
+            resp_op_payload <= resp_o_tdata[55:8];
+            pkt_state <= ST_APPEND_LAST_HOP;
+          end
+        end
+
+        // ST_APPEND_LAST_HOP
+        // ------------------
+        // - Append the popped response to the output packet here
+        // - Keep doing so until the response FIFO is empty
+        ST_APPEND_LAST_HOP: begin
+          if (o64_tvalid && o64_tready)
+            pkt_state <= resp_o_tvalid ? ST_POP_RESPONSE : ST_CHDR_IN_HDR;
+        end
+
+        // ST_FAILSAFE_DROP
+        // ------------------
+        // - Something went wrong. Discard the packet and re-arm the state machine
+        ST_FAILSAFE_DROP: begin
+          if (i64_tvalid && i64_tready)
+            pkt_state <= i64_tlast ? ST_CHDR_IN_HDR : ST_FAILSAFE_DROP;
+        end
+
+        default: begin
+          // We should never get here
+          pkt_state <= ST_CHDR_IN_HDR;
+        end
+      endcase
+    end
+  end
+
+  // Logic to determine when to consume a word from the input CHDR stream
+  always @(*) begin
+    case (pkt_state)
+      ST_CHDR_IN_HDR:
+        i64_tready = 1'b1;        // Unconditionally consume header
+      ST_CHDR_IN_MDATA:
+        i64_tready = 1'b1;        // Unconditionally discard header
+      ST_MGMT_IN_HDR:
+        i64_tready = 1'b1;        // Unconditionally consume header
+      ST_MGMT_OP_DONE:
+        i64_tready = 1'b1;        // Operation is done. Consume op-word
+      ST_PASS_PAYLOAD:
+        i64_tready = o64_tready;  // We are passing input -> output
+      ST_MOD_LAST_HOP:
+        i64_tready = o64_tready;  // We are passing input -> output
+      ST_FAILSAFE_DROP:
+        i64_tready = 1'b1;        // Unconditionally consume to drop
+      default:
+        i64_tready = 1'b0;        // Hold the input. We are processing it
+    endcase
+  end
+
+  // Swap src/dst EPIDs if returning packet to source
+  wire [15:0] o64_dst_epid = (o64_tid == CHDR_MGMT_RETURN_TO_SRC) ? 
+    chdr_mgmt_get_src_epid(cached_mgmt_hdr) : chdr_get_dst_epid(cached_chdr_hdr);
+  wire [15:0] o64_src_epid = (o64_tid == CHDR_MGMT_RETURN_TO_SRC) ? 
+    chdr_get_dst_epid(cached_chdr_hdr) : chdr_mgmt_get_src_epid(cached_mgmt_hdr);
+
+  // Logic to drive the output CHDR stream
+  always @(*) begin
+    case (pkt_state)
+      ST_CHDR_OUT_HDR: begin
+        // We are generating new data using cached values.
+        // Output header = Input header with new length
+        o64_tdata  = chdr_set_length(
+          chdr_set_dst_epid(cached_chdr_hdr, o64_dst_epid), 
+          (stripped_len + (num_resp_pending << LOG2_CHDR_W_BYTES)));
+        o64_tvalid = 1'b1;
+        o64_tlast  = 1'b0;
+      end
+      ST_MGMT_OUT_HDR: begin
+        // We are generating new data using cached values.
+        // Output header = Input header with new num_hops and some protocol info
+        o64_tdata  = chdr_mgmt_build_hdr(PROTOVER, chdr_w_to_enum(CHDR_W), 
+          chdr_mgmt_get_num_hops(cached_mgmt_hdr) - 10'd1, o64_src_epid);
+        o64_tvalid = 1'b1;
+        o64_tlast  = 1'b0;
+      end
+      ST_PASS_PAYLOAD: begin
+        // Input -> Output without modification
+        o64_tdata  = i64_tdata;
+        o64_tvalid = i64_tvalid;
+        o64_tlast  = i64_tlast;
+      end
+      ST_MOD_LAST_HOP: begin
+        // Input -> Output but update the ops_pending field
+        o64_tdata  = chdr_mgmt_build_op(chdr_mgmt_get_op_payload(i64_tdata),
+          chdr_mgmt_get_op_code(i64_tdata),
+          chdr_mgmt_get_ops_pending(i64_tdata) + num_resp_pending);
+        o64_tvalid = i64_tvalid;
+        o64_tlast  = i64_tlast && !resp_o_tvalid;
+      end
+      ST_APPEND_LAST_HOP: begin
+        // We are generating new data using cached values.
+        o64_tdata  = chdr_mgmt_build_op(resp_op_payload, resp_op_code, num_resp_pending);
+        o64_tvalid = 1'b1;
+        o64_tlast  = !resp_o_tvalid;
+      end
+      default: begin
+        // We are processing something. Don't output
+        o64_tdata  = 64'h0;
+        o64_tvalid = 1'b0;
+        o64_tlast  = 1'b0;
+      end
+    endcase
+  end
+
+  // CHDR_MGMT_OP_ADVERTISE
+  // ----------------------
+  assign op_stb      = i64_tvalid && (pkt_state == ST_MGMT_OP_DONE) &&
+                       (op_code == CHDR_MGMT_OP_ADVERTISE);
+  assign op_dst_epid = chdr_get_dst_epid(cached_chdr_hdr);
+  assign op_src_epid = chdr_mgmt_get_src_epid(cached_mgmt_hdr);
+  assign op_data     = cached_tuser;
+
+  // CHDR_MGMT_OP_CFG_WR_REQ
+  // CHDR_MGMT_OP_CFG_RD_REQ
+  // -----------------------
+  // The request is sent out in the ST_MGMT_OP_EXEC state and we wait for a response
+  // in the ST_MGMT_OP_WAIT state
+  always @(posedge clk) begin
+    if (rst) begin
+      ctrlport_req_wr   <= 1'b0;
+      ctrlport_req_rd   <= 1'b0;
+    end else begin
+      ctrlport_req_wr   <= i64_tvalid && (pkt_state == ST_MGMT_OP_EXEC) &&
+                          (op_code == CHDR_MGMT_OP_CFG_WR_REQ);
+      ctrlport_req_rd   <= i64_tvalid && (pkt_state == ST_MGMT_OP_EXEC) &&
+                          (op_code == CHDR_MGMT_OP_CFG_RD_REQ);
+      ctrlport_req_addr <= chdr_mgmt_cfg_reg_get_addr(op_payload);
+      ctrlport_req_data <= chdr_mgmt_cfg_reg_get_data(op_payload);
+    end
+  end
+
+  // CHDR_MGMT_OP_CFG_RD_REQ
+  // CHDR_MGMT_OP_INFO_REQ
+  // -----------------------
+  // Collect the response for these operations and push to the response FIFO
+  assign resp_i_tvalid = i64_tvalid && (
+    ((pkt_state == ST_MGMT_OP_WAIT) && (op_code == CHDR_MGMT_OP_CFG_RD_REQ) && ctrlport_resp_ack) ||
+    ((pkt_state == ST_MGMT_OP_DONE) && (op_code == CHDR_MGMT_OP_INFO_REQ)));
+  assign resp_i_tdata = (op_code == CHDR_MGMT_OP_CFG_RD_REQ) ?
+    {ctrlport_resp_data, ctrlport_req_addr, CHDR_MGMT_OP_CFG_RD_RESP} : // Ctrlport response
+    {node_info, CHDR_MGMT_OP_INFO_RESP};                                // NodeInfo
+
+  // The response FIFO should be deep enough to store all the responses
+  wire [15:0] resp_fifo_occ;
+  axi_fifo #(.WIDTH(56), .SIZE(RESP_FIFO_SIZE)) resp_fifo_i (
+    .clk(clk), .reset(rst), .clear(pkt_state == ST_CHDR_IN_HDR),
+    .i_tdata(resp_i_tdata), .i_tvalid(resp_i_tvalid),
+    .i_tready(/* Must be high. Responses will be dropped if FIFO is full */),
+    .o_tdata(resp_o_tdata), .o_tvalid(resp_o_tvalid),
+    .o_tready(resp_o_tvalid && (pkt_state == ST_POP_RESPONSE)),
+    .space(), .occupied(resp_fifo_occ)
+  );
+  assign num_resp_pending = resp_fifo_occ[7:0];
+
+endmodule // chdr_mgmt_pkt_handler
diff --git a/fpga/usrp3/lib/rfnoc/core/chdr_stream_endpoint.v b/fpga/usrp3/lib/rfnoc/core/chdr_stream_endpoint.v
new file mode 100644
index 000000000..9c824a0af
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/core/chdr_stream_endpoint.v
@@ -0,0 +1,621 @@
+//
+// Copyright 2018-2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: chdr_stream_endpoint
+// Description:
+//   The implementation of a stream endpoint. This module serves as
+//   an endpoint for a bidirectional stream. It implement a control
+//   and a data path, both of which can be individually enabled using
+//   parameters. The control path contains a bidirectional CHDR to 
+//   AXIS-Control converter. The data path has a stream input and
+//   output port.
+//
+// Parameters:
+//   - PROTOVER: RFNoC protocol version {8'd<major>, 8'd<minor>}
+//   - CHDR_W: Width of the CHDR bus in bits
+//   - INST_NUM: The instance number of this module
+//   - CTRL_XBAR_PORT: The port index on the control crossbar that
+//                     this module's control path will connect to
+//   - AXIS_CTRL_EN: Enable control traffic (axis_ctrl port)
+//   - AXIS_DATA_EN: Enable data traffic (axis_data port)
+//   - NUM_DATA_I: Number of AXIS data slave ports
+//   - NUM_DATA_O: Number of AXIS data master ports
+//   - INGRESS_BUFF_SIZE: Buffer size in log2 of the number of words
+//                        in the ingress buffer for the stream
+//   - MTU: Log2 of the maximum packet size in words
+//   - REPORT_STRM_ERRS: Report data stream errors upstream
+//   - SIM_SPEEDUP: Set to 1 in simultion, and 0 otherwise
+//
+// Signals:
+//   - device_id     : The ID of the device that has instantiated this module
+//   - *_axis_chdr_* : Input/output CHDR stream (AXI-Stream)
+//   - *_axis_ctrl_* : Input/output AXIS-Control streams (AXI-Stream)
+//   - *_axis_data_* : Input/output CHDR Data streams (AXI-Stream)
+//   - strm_*_err_stb: The stream encountered an error
+//   - signal_*_err  : Notify upstream that we encountered an error
+
+module chdr_stream_endpoint #(
+  parameter [15:0] PROTOVER          = {8'd1, 8'd0},
+  parameter        CHDR_W            = 64,
+  parameter [9:0]  INST_NUM          = 0,
+  parameter [9:0]  CTRL_XBAR_PORT    = 0,
+  parameter [0:0]  AXIS_CTRL_EN      = 1,
+  parameter [0:0]  AXIS_DATA_EN      = 1,
+  parameter [5:0]  NUM_DATA_I        = 1,
+  parameter [5:0]  NUM_DATA_O        = 1,
+  parameter [5:0]  INGRESS_BUFF_SIZE = 12,
+  parameter [5:0]  MTU               = 10,
+  parameter [0:0]  REPORT_STRM_ERRS  = 1,
+  parameter [0:0]  SIM_SPEEDUP       = 0
+)(
+  // Clock, reset and settings
+  input  wire                           rfnoc_chdr_clk,
+  input  wire                           rfnoc_chdr_rst,
+  input  wire                           rfnoc_ctrl_clk,
+  input  wire                           rfnoc_ctrl_rst,
+  // Device info                        
+  input  wire [15:0]                    device_id,
+  // CHDR in (AXI-Stream)               
+  input  wire [CHDR_W-1:0]              s_axis_chdr_tdata,
+  input  wire                           s_axis_chdr_tlast,
+  input  wire                           s_axis_chdr_tvalid,
+  output wire                           s_axis_chdr_tready,
+  // CHDR out (AXI-Stream)
+  output wire [CHDR_W-1:0]              m_axis_chdr_tdata,
+  output wire                           m_axis_chdr_tlast,
+  output wire                           m_axis_chdr_tvalid,
+  input  wire                           m_axis_chdr_tready,
+  // Flow controlled data in (AXI-Stream)
+  input  wire [(CHDR_W*NUM_DATA_I)-1:0] s_axis_data_tdata,
+  input  wire [NUM_DATA_I-1:0]          s_axis_data_tlast,
+  input  wire [NUM_DATA_I-1:0]          s_axis_data_tvalid,
+  output wire [NUM_DATA_I-1:0]          s_axis_data_tready,
+  // Flow controlled data out (AXI-Stream)
+  output wire [(CHDR_W*NUM_DATA_O)-1:0] m_axis_data_tdata,
+  output wire [NUM_DATA_O-1:0]          m_axis_data_tlast,
+  output wire [NUM_DATA_O-1:0]          m_axis_data_tvalid,
+  input  wire [NUM_DATA_O-1:0]          m_axis_data_tready,
+  // Control in (AXI-Stream)
+  input  wire [31:0]                    s_axis_ctrl_tdata,
+  input  wire                           s_axis_ctrl_tlast,
+  input  wire                           s_axis_ctrl_tvalid,
+  output wire                           s_axis_ctrl_tready,
+  // Control out (AXI-Stream)
+  output wire [31:0]                    m_axis_ctrl_tdata,
+  output wire                           m_axis_ctrl_tlast,
+  output wire                           m_axis_ctrl_tvalid,
+  input  wire                           m_axis_ctrl_tready,
+  // Stream status specfic              
+  output wire                           strm_seq_err_stb,
+  output wire                           strm_data_err_stb,
+  output wire                           strm_route_err_stb,
+  input  wire                           signal_data_err
+);
+
+  // ---------------------------------------------------
+  //  RFNoC Includes
+  // ---------------------------------------------------
+  `include "rfnoc_chdr_utils.vh"
+  `include "rfnoc_chdr_internal_utils.vh"
+
+  // ---------------------------------------------------
+  //  Filter packets by type 
+  // ---------------------------------------------------
+  wire [CHDR_W-1:0] ctrl_i_tdata,  ctrl_o_tdata;
+  wire              ctrl_i_tlast,  ctrl_o_tlast;
+  wire              ctrl_i_tvalid, ctrl_o_tvalid;
+  wire              ctrl_i_tready, ctrl_o_tready;
+
+  wire [CHDR_W-1:0] data_i_tdata,  data_o_tdata;
+  wire              data_i_tlast,  data_o_tlast;
+  wire              data_i_tvalid, data_o_tvalid;
+  wire              data_i_tready, data_o_tready;
+
+  wire [CHDR_W-1:0] strs_i_tdata,  strs_o_tdata;
+  wire              strs_i_tlast,  strs_o_tlast;
+  wire              strs_i_tvalid, strs_o_tvalid;
+  wire              strs_i_tready, strs_o_tready;
+
+  wire [CHDR_W-1:0] mgmt_i_tdata,  mgmt_o_tdata;
+  wire              mgmt_i_tlast,  mgmt_o_tlast;
+  wire              mgmt_i_tvalid, mgmt_o_tvalid;
+  wire              mgmt_i_tready, mgmt_o_tready;
+
+  function [1:0] compute_demux_dest;
+    input [63:0] hdr;
+    if (chdr_get_pkt_type(hdr) == CHDR_PKT_TYPE_CTRL)
+      // Control
+      compute_demux_dest = 2'd2;
+    else if (chdr_get_pkt_type(hdr) == CHDR_PKT_TYPE_STRC ||
+             chdr_get_pkt_type(hdr) == CHDR_PKT_TYPE_DATA ||
+             chdr_get_pkt_type(hdr) == CHDR_PKT_TYPE_DATA_TS)
+      // Data and stream command
+      compute_demux_dest = 2'd1;
+    else if (chdr_get_pkt_type(hdr) == CHDR_PKT_TYPE_STRS)
+      // Stream status
+      compute_demux_dest = 2'd0;
+    else
+      // Management (all packets must return to sender)
+      compute_demux_dest = 2'd3;
+  endfunction
+
+  // We give the demux a FIFO large enough to buffer short packets
+  // Flow control will ensure that data does not back up through
+  // this demux but we might have the other packet types block
+  // each other.
+  localparam DEMUX_FIFO_SIZE = 5;
+
+  wire [CHDR_W-1:0] chdr_header;
+  axi_demux #(
+    .WIDTH(CHDR_W), .SIZE(4), .PRE_FIFO_SIZE(DEMUX_FIFO_SIZE), .POST_FIFO_SIZE(1)
+  ) mgmt_demux_i (
+    .clk(rfnoc_chdr_clk), .reset(rfnoc_chdr_rst), .clear(1'b0),
+    .header(chdr_header), .dest(compute_demux_dest(chdr_header[63:0])),
+    .i_tdata (s_axis_chdr_tdata ),
+    .i_tlast (s_axis_chdr_tlast ),
+    .i_tvalid(s_axis_chdr_tvalid),
+    .i_tready(s_axis_chdr_tready),
+    .o_tdata ({mgmt_i_tdata,  ctrl_i_tdata,  data_i_tdata,  strs_i_tdata }),
+    .o_tlast ({mgmt_i_tlast,  ctrl_i_tlast,  data_i_tlast,  strs_i_tlast }),
+    .o_tvalid({mgmt_i_tvalid, ctrl_i_tvalid, data_i_tvalid, strs_i_tvalid}),
+    .o_tready({mgmt_i_tready, ctrl_i_tready, data_i_tready, strs_i_tready})
+  );
+
+  axi_mux #(
+    .WIDTH(CHDR_W), .SIZE(4), .PRIO(1), .PRE_FIFO_SIZE(0), .POST_FIFO_SIZE(1)
+  ) mgmt_mux_i (
+    .clk(rfnoc_chdr_clk), .reset(rfnoc_chdr_rst), .clear(1'b0),
+    .i_tdata ({mgmt_o_tdata,  data_o_tdata,  strs_o_tdata,  ctrl_o_tdata }),
+    .i_tlast ({mgmt_o_tlast,  data_o_tlast,  strs_o_tlast,  ctrl_o_tlast }),
+    .i_tvalid({mgmt_o_tvalid, data_o_tvalid, strs_o_tvalid, ctrl_o_tvalid}),
+    .i_tready({mgmt_o_tready, data_o_tready, strs_o_tready, ctrl_o_tready}),
+    .o_tdata (m_axis_chdr_tdata ),
+    .o_tlast (m_axis_chdr_tlast ),
+    .o_tvalid(m_axis_chdr_tvalid),
+    .o_tready(m_axis_chdr_tready)
+  );
+
+  // ---------------------------------------------------
+  //  Management Path 
+  // ---------------------------------------------------
+  wire              ctrlport_req_wr, ctrlport_req_rd;
+  reg               ctrlport_resp_ack = 1'b0;
+  wire [15:0]       ctrlport_req_addr;
+  wire [31:0]       ctrlport_req_data;
+  reg  [31:0]       ctrlport_resp_data;
+
+  localparam [17:0] EXTENDED_INFO = {
+    3'b0, REPORT_STRM_ERRS, NUM_DATA_O, NUM_DATA_I, AXIS_DATA_EN, AXIS_CTRL_EN};
+
+  // Handle management packets here
+  chdr_mgmt_pkt_handler #(
+    .PROTOVER(PROTOVER), .CHDR_W(CHDR_W), .MGMT_ONLY(1)
+  ) mgmt_ep_i (
+    .clk(rfnoc_chdr_clk), .rst(rfnoc_chdr_rst),
+    .node_info(chdr_mgmt_build_node_info(EXTENDED_INFO, INST_NUM, NODE_TYPE_STREAM_EP, device_id)),
+    .s_axis_chdr_tdata(mgmt_i_tdata), .s_axis_chdr_tlast(mgmt_i_tlast),
+    .s_axis_chdr_tvalid(mgmt_i_tvalid), .s_axis_chdr_tready(mgmt_i_tready),
+    .s_axis_chdr_tuser('d0),
+    .m_axis_chdr_tdata(mgmt_o_tdata), .m_axis_chdr_tlast(mgmt_o_tlast),
+    .m_axis_chdr_tdest(/* unused */), .m_axis_chdr_tid(/* unused */),
+    .m_axis_chdr_tvalid(mgmt_o_tvalid), .m_axis_chdr_tready(mgmt_o_tready),
+    .ctrlport_req_wr(ctrlport_req_wr), .ctrlport_req_rd(ctrlport_req_rd),
+    .ctrlport_req_addr(ctrlport_req_addr), .ctrlport_req_data(ctrlport_req_data),
+    .ctrlport_resp_ack(ctrlport_resp_ack), .ctrlport_resp_data(ctrlport_resp_data),
+    .op_stb(/* unused */), .op_dst_epid(/* unused */), .op_src_epid(/* unused */),
+    .op_data(/* unused */)
+  );
+
+  // ============================== REGISTERS ============================== 
+  // * REG_EPID_SELF (Read-Write):
+  //   The endpoint ID of this stream endpoint
+  //   - [15:0]: Endpoint ID
+  // * REG_RESET_AND_FLUSH (Write-Only):
+  //   Reset and flush register
+  //   - [0]: Flush data path
+  //   - [1]: Flush control path
+  // * REG_OSTRM_CTRL_STATUS (Read-Write):
+  //   Control and status register for the output stream
+  //   - [0]  : Configuration start (strobe)
+  //   - [1]  : Is this transport lossy?
+  //   - [3:2]: Payload SW buff (0=u64, 1=u32, 2=u16, 3=u8)
+  //   - [5:4]: Metadata SW buff (0=u64, 1=u32, 2=u16, 3=u8)
+  //   - [6]  : Swap endianness
+  // * REG_OSTRM_DST_EPID (Write-Only):
+  //   The endpoint ID of a downstream stream endpoint
+  //   - [15:0]: Endpoint ID
+  // * REG_OSTRM_FC_FREQ_BYTES_LO, REG_OSTRM_FC_FREQ_BYTES_HI (Write-Only):
+  //   Number of bytes between flow control status messages
+  // * REG_OSTRM_FC_FREQ_PKTS (Write-Only):
+  //   Number of packets between flow control status messages
+  // * REG_OSTRM_FC_HEADROOM (Write-Only):
+  //   Flow control headroom register
+  //   - [15:0]: Bytes of headroom
+  //   - [23:16]: Packets of headroom
+  // * REG_OSTRM_BUFF_CAP_BYTES_LO, REG_OSTRM_BUFF_CAP_BYTES_HI (Read-Only):
+  //   Number of bytes in the downstream buffer
+  // * REG_OSTRM_BUFF_CAP_PKTS (Read-Only):
+  //   Number of packets in the downstream buffer
+  // * REG_OSTRM_SEQ_ERR_CNT (Read-Only):
+  //   Number of sequence errors since initialization
+  // * REG_OSTRM_DATA_ERR_CNT (Read-Only):
+  //   Number of data integrity errors since initialization
+  // * REG_OSTRM_ROUTE_ERR_CNT (Read-Only):
+  //   Number of routing errors since initialization
+  // * REG_ISTRM_CTRL_STATUS (Read-Write):
+  //   Control and status register for the input stream
+  //   - [0]  : Reserved
+  //   - [1]  : Reserved
+  //   - [3:2]: Payload SW buff (0=u64, 1=u32, 2=u16, 3=u8)
+  //   - [5:4]: Metadata SW buff (0=u64, 1=u32, 2=u16, 3=u8)
+  //   - [6]  : Swap endianness
+  // ======================================================================= 
+
+  localparam [15:0] REG_EPID_SELF               = 16'h00;   //RW
+  localparam [15:0] REG_RESET_AND_FLUSH         = 16'h04;   //W
+  localparam [15:0] REG_OSTRM_CTRL_STATUS       = 16'h08;   //RW
+  localparam [15:0] REG_OSTRM_DST_EPID          = 16'h0C;   //W
+  localparam [15:0] REG_OSTRM_FC_FREQ_BYTES_LO  = 16'h10;   //W
+  localparam [15:0] REG_OSTRM_FC_FREQ_BYTES_HI  = 16'h14;   //W
+  localparam [15:0] REG_OSTRM_FC_FREQ_PKTS      = 16'h18;   //W
+  localparam [15:0] REG_OSTRM_FC_HEADROOM       = 16'h1C;   //W
+  localparam [15:0] REG_OSTRM_BUFF_CAP_BYTES_LO = 16'h20;   //R
+  localparam [15:0] REG_OSTRM_BUFF_CAP_BYTES_HI = 16'h24;   //R
+  localparam [15:0] REG_OSTRM_BUFF_CAP_PKTS     = 16'h28;   //R
+  localparam [15:0] REG_OSTRM_SEQ_ERR_CNT       = 16'h2C;   //R
+  localparam [15:0] REG_OSTRM_DATA_ERR_CNT      = 16'h30;   //R
+  localparam [15:0] REG_OSTRM_ROUTE_ERR_CNT     = 16'h34;   //R
+  localparam [15:0] REG_ISTRM_CTRL_STATUS       = 16'h38;   //RW
+
+  // Configurable registers
+  reg  [15:0] reg_epid_self = 16'h0;
+  reg         reg_ctrl_reset = 1'b0;
+  reg         reg_istrm_reset = 1'b0;
+  reg         reg_ostrm_reset = 1'b0;
+  reg         reg_ostrm_cfg_start = 1'b0;
+  wire        reg_ostrm_cfg_pending;
+  wire        reg_ostrm_cfg_failed;
+  reg         reg_ostrm_cfg_lossy_xport = 1'b0;
+  reg  [1:0]  reg_ostrm_cfg_pyld_sw_buff = 2'd0;
+  reg  [1:0]  reg_ostrm_cfg_mdata_sw_buff = 2'd0;
+  reg         reg_ostrm_cfg_swap_endian = 1'b0;
+  reg  [15:0] reg_ostrm_dst_epid = 16'h0;
+  reg  [39:0] reg_fc_freq_bytes = 40'h0;
+  reg  [23:0] reg_fc_freq_pkts = 24'h0;
+  reg  [15:0] reg_fc_headroom_bytes = 16'd0;
+  reg  [7:0]  reg_fc_headroom_pkts = 8'd0;
+  reg  [1:0]  reg_istrm_cfg_pyld_sw_buff = 2'd0;
+  reg  [1:0]  reg_istrm_cfg_mdata_sw_buff = 2'd0;
+  reg         reg_istrm_cfg_swap_endian = 1'b0;
+  wire        reg_fc_enabled;
+  wire [39:0] reg_buff_cap_bytes;
+  wire [23:0] reg_buff_cap_pkts;
+  wire [31:0] reg_seq_err_cnt;
+  wire [31:0] reg_data_err_cnt;
+  wire [31:0] reg_route_err_cnt;
+
+  always @(posedge rfnoc_chdr_clk) begin
+    if (rfnoc_chdr_rst) begin
+      ctrlport_resp_ack <= 1'b0;
+    end else begin
+      // All transactions finish in 1 cycle
+      ctrlport_resp_ack <= ctrlport_req_wr | ctrlport_req_rd;
+      // Handle register writes
+      if (ctrlport_req_wr) begin
+        case(ctrlport_req_addr)
+          REG_EPID_SELF:
+            reg_epid_self <= ctrlport_req_data[15:0];
+          REG_RESET_AND_FLUSH:
+            {reg_ctrl_reset, reg_istrm_reset, reg_ostrm_reset} <= ctrlport_req_data[2:0];
+          REG_OSTRM_CTRL_STATUS:
+            {reg_ostrm_cfg_swap_endian, reg_ostrm_cfg_mdata_sw_buff, reg_ostrm_cfg_pyld_sw_buff,
+             reg_ostrm_cfg_lossy_xport, reg_ostrm_cfg_start} <= ctrlport_req_data[6:0];
+          REG_OSTRM_DST_EPID:
+            reg_ostrm_dst_epid <= ctrlport_req_data[15:0];
+          REG_OSTRM_FC_FREQ_BYTES_LO:
+            reg_fc_freq_bytes[31:0] <= ctrlport_req_data[31:0];
+          REG_OSTRM_FC_FREQ_BYTES_HI:
+            reg_fc_freq_bytes[39:32] <= ctrlport_req_data[7:0];
+          REG_OSTRM_FC_FREQ_PKTS:
+            reg_fc_freq_pkts <= ctrlport_req_data[23:0];
+          REG_OSTRM_FC_HEADROOM:
+            {reg_fc_headroom_pkts, reg_fc_headroom_bytes} <= ctrlport_req_data[23:0];
+          REG_ISTRM_CTRL_STATUS:
+            {reg_istrm_cfg_swap_endian, reg_istrm_cfg_mdata_sw_buff, reg_istrm_cfg_pyld_sw_buff} 
+              <= ctrlport_req_data[6:2];
+        endcase
+      end else begin
+        // Strobed registers
+        reg_ostrm_cfg_start <= 1'b0;
+        reg_ctrl_reset <= 1'b0;
+        reg_ostrm_reset <= 1'b0;
+        reg_istrm_reset <= 1'b0;
+      end
+      // Handle register reads
+      if (ctrlport_req_rd) begin
+        case(ctrlport_req_addr)
+          REG_EPID_SELF:
+            ctrlport_resp_data <= {16'h0, reg_epid_self};
+          REG_OSTRM_CTRL_STATUS:
+            ctrlport_resp_data <= {
+              reg_fc_enabled, reg_ostrm_cfg_failed, reg_ostrm_cfg_pending, 23'h0,
+              reg_ostrm_cfg_mdata_sw_buff, reg_ostrm_cfg_pyld_sw_buff,
+              reg_ostrm_cfg_lossy_xport, 1'b0};
+          REG_OSTRM_BUFF_CAP_BYTES_LO:
+            ctrlport_resp_data <= reg_buff_cap_bytes[31:0];
+          REG_OSTRM_BUFF_CAP_BYTES_HI:
+            ctrlport_resp_data <= {24'h0, reg_buff_cap_bytes[39:32]};
+          REG_OSTRM_BUFF_CAP_PKTS:
+            ctrlport_resp_data <= {8'h0, reg_buff_cap_pkts};
+          REG_OSTRM_SEQ_ERR_CNT:
+            ctrlport_resp_data <= reg_seq_err_cnt;
+          REG_OSTRM_DATA_ERR_CNT:
+            ctrlport_resp_data <= reg_data_err_cnt;
+          REG_OSTRM_ROUTE_ERR_CNT:
+            ctrlport_resp_data <= reg_route_err_cnt;
+          REG_ISTRM_CTRL_STATUS:
+            ctrlport_resp_data <= {26'h0,
+              reg_istrm_cfg_mdata_sw_buff, reg_istrm_cfg_pyld_sw_buff, 2'b0};
+          default:
+            ctrlport_resp_data <= 32'h0;
+        endcase
+      end
+    end
+  end
+
+  // ---------------------------------------------------
+  //  Data and Flow Control Path 
+  // ---------------------------------------------------
+  genvar i;
+  generate if (AXIS_DATA_EN) begin: datapath
+    localparam INPUT_FLUSH_TIMEOUT_W = SIM_SPEEDUP ? 6 : 14;
+
+    // Data => CHDR
+    //-------------
+    wire [CHDR_W-1:0] axis_di_tdata,  axis_dis_tdata, axis_di_tdata_pre;
+    wire [5:0]        axis_di_tdest;
+    wire              axis_di_tlast,  axis_dis_tlast;
+    wire              axis_di_tvalid, axis_dis_tvalid;
+    wire              axis_di_tready, axis_dis_tready;
+
+    // Optional MUX to combine multiple input data ports into a single one
+    if (NUM_DATA_I == 6'd1) begin
+      axi_fifo #(.WIDTH(CHDR_W+1), .SIZE(1)) axis_s_reg_i (
+        .clk(rfnoc_chdr_clk), .reset(rfnoc_chdr_rst | reg_ostrm_reset), .clear(1'b0),
+        .i_tdata({s_axis_data_tlast, s_axis_data_tdata}),
+        .i_tvalid(s_axis_data_tvalid), .i_tready(s_axis_data_tready),
+        .o_tdata({axis_di_tlast, axis_di_tdata_pre}),
+        .o_tvalid(axis_di_tvalid), .o_tready(axis_di_tready),
+        .space(), .occupied()
+      );
+      assign axis_di_tdest = 6'd0;
+    end else begin
+      wire [((CHDR_W+6)*NUM_DATA_I)-1:0] s_axis_data_tdata_tmp;
+      for (i = 0; i < NUM_DATA_I; i=i+1) begin
+        assign s_axis_data_tdata_tmp[(i*(CHDR_W+6))+:(CHDR_W+6)] = {i[5:0], s_axis_data_tdata[(i*CHDR_W)+:CHDR_W]};
+      end
+
+      axi_mux #(
+        .WIDTH(CHDR_W+6), .SIZE(NUM_DATA_I), .PRIO(0), .PRE_FIFO_SIZE(1), .POST_FIFO_SIZE(1)
+      ) axis_s_mux_i (
+        .clk(rfnoc_chdr_clk), .reset(rfnoc_chdr_rst | reg_ostrm_reset), .clear(1'b0),
+        .i_tdata(s_axis_data_tdata_tmp), .i_tlast(s_axis_data_tlast),
+        .i_tvalid(s_axis_data_tvalid), .i_tready(s_axis_data_tready),
+        .o_tdata({axis_di_tdest, axis_di_tdata_pre}), .o_tlast(axis_di_tlast),
+        .o_tvalid(axis_di_tvalid), .o_tready(axis_di_tready)
+      );
+    end
+
+    // Logic to correctly fill in the VC field in the CHDR header
+    reg axis_di_hdr = 1'b1;
+    always @(posedge rfnoc_chdr_clk) begin
+      if (rfnoc_chdr_rst | reg_ostrm_reset)
+        axis_di_hdr <= 1'b1;
+      else if (axis_di_tvalid && axis_di_tready)
+        axis_di_hdr <= axis_di_tlast;
+    end
+    assign axis_di_tdata[63:0] = axis_di_hdr ? chdr_set_vc(axis_di_tdata_pre[63:0], axis_di_tdest) :
+                                               axis_di_tdata_pre[63:0];
+    if (CHDR_W > 64) begin
+      assign axis_di_tdata[CHDR_W-1:64] = axis_di_tdata_pre[CHDR_W-1:64];
+    end
+
+    // Module to swap words in the payload and metadata depending on SW settings 
+    chdr_data_swapper #( .CHDR_W(CHDR_W)) di_swap_i (
+      .clk            (rfnoc_chdr_clk),
+      .rst            (rfnoc_chdr_rst | reg_ostrm_reset),
+      .payload_sw_buff(reg_ostrm_cfg_pyld_sw_buff),
+      .mdata_sw_buff  (reg_ostrm_cfg_mdata_sw_buff),
+      .swap_endianness(reg_ostrm_cfg_swap_endian),
+      .s_axis_tdata   (axis_di_tdata),
+      .s_axis_tlast   (axis_di_tlast),
+      .s_axis_tvalid  (axis_di_tvalid),
+      .s_axis_tready  (axis_di_tready),
+      .m_axis_tdata   (axis_dis_tdata),
+      .m_axis_tlast   (axis_dis_tlast),
+      .m_axis_tvalid  (axis_dis_tvalid),
+      .m_axis_tready  (axis_dis_tready)
+    );
+
+    // Stream endpoint flow-control output module
+    chdr_stream_output #(
+      .CHDR_W(CHDR_W), .MTU(MTU)
+    ) strm_output_i (
+      .clk                  (rfnoc_chdr_clk),
+      .rst                  (rfnoc_chdr_rst | reg_ostrm_reset),
+      .m_axis_chdr_tdata    (data_o_tdata),
+      .m_axis_chdr_tlast    (data_o_tlast),
+      .m_axis_chdr_tvalid   (data_o_tvalid),
+      .m_axis_chdr_tready   (data_o_tready),
+      .s_axis_data_tdata    (axis_dis_tdata),
+      .s_axis_data_tlast    (axis_dis_tlast),
+      .s_axis_data_tvalid   (axis_dis_tvalid),
+      .s_axis_data_tready   (axis_dis_tready),
+      .s_axis_strs_tdata    (strs_i_tdata),
+      .s_axis_strs_tlast    (strs_i_tlast),
+      .s_axis_strs_tvalid   (strs_i_tvalid),
+      .s_axis_strs_tready   (strs_i_tready),
+      .cfg_start            (reg_ostrm_cfg_start),
+      .cfg_pending          (reg_ostrm_cfg_pending),
+      .cfg_failed           (reg_ostrm_cfg_failed),
+      .cfg_lossy_xport      (reg_ostrm_cfg_lossy_xport),
+      .cfg_dst_epid         (reg_ostrm_dst_epid),
+      .cfg_this_epid        (reg_epid_self),
+      .cfg_fc_freq_bytes    (reg_fc_freq_bytes),
+      .cfg_fc_freq_pkts     (reg_fc_freq_pkts),
+      .cfg_fc_headroom_bytes(reg_fc_headroom_bytes),
+      .cfg_fc_headroom_pkts (reg_fc_headroom_pkts),
+      .fc_enabled           (reg_fc_enabled),
+      .capacity_bytes       (reg_buff_cap_bytes),
+      .capacity_pkts        (reg_buff_cap_pkts),
+      .seq_err_stb          (strm_seq_err_stb),
+      .seq_err_cnt          (reg_seq_err_cnt),
+      .data_err_stb         (strm_data_err_stb),
+      .data_err_cnt         (reg_data_err_cnt),
+      .route_err_stb        (strm_route_err_stb),
+      .route_err_cnt        (reg_route_err_cnt)
+    );
+
+    // CHDR => Data
+    //-------------
+    wire [CHDR_W-1:0] axis_do_tdata,  axis_dos_tdata;
+    wire              axis_do_tlast,  axis_dos_tlast;
+    wire              axis_do_tvalid, axis_dos_tvalid;
+    wire              axis_do_tready, axis_dos_tready;
+
+    // Stream endpoint flow-control input module
+    chdr_stream_input #(
+      .CHDR_W(CHDR_W), .BUFF_SIZE(INGRESS_BUFF_SIZE),
+      .FLUSH_TIMEOUT_W(INPUT_FLUSH_TIMEOUT_W),
+      .MONITOR_EN(0), .SIGNAL_ERRS(REPORT_STRM_ERRS)
+    ) strm_input_i (
+      .clk               (rfnoc_chdr_clk),
+      .rst               (rfnoc_chdr_rst | reg_istrm_reset),
+      .s_axis_chdr_tdata (data_i_tdata),
+      .s_axis_chdr_tlast (data_i_tlast),
+      .s_axis_chdr_tvalid(data_i_tvalid),
+      .s_axis_chdr_tready(data_i_tready),
+      .m_axis_data_tdata (axis_do_tdata),
+      .m_axis_data_tlast (axis_do_tlast),
+      .m_axis_data_tvalid(axis_do_tvalid),
+      .m_axis_data_tready(axis_do_tready),
+      .m_axis_strs_tdata (strs_o_tdata),
+      .m_axis_strs_tlast (strs_o_tlast),
+      .m_axis_strs_tvalid(strs_o_tvalid),
+      .m_axis_strs_tready(strs_o_tready),
+      .data_err_stb      (signal_data_err)
+    );
+
+    // Module to swap words in the payload and metadata depending on SW settings 
+    chdr_data_swapper #( .CHDR_W(CHDR_W)) do_swap_i (
+      .clk            (rfnoc_chdr_clk),
+      .rst            (rfnoc_chdr_rst | reg_istrm_reset),
+      .payload_sw_buff(reg_istrm_cfg_pyld_sw_buff),
+      .mdata_sw_buff  (reg_istrm_cfg_mdata_sw_buff),
+      .swap_endianness(reg_istrm_cfg_swap_endian),
+      .s_axis_tdata   (axis_do_tdata),
+      .s_axis_tlast   (axis_do_tlast),
+      .s_axis_tvalid  (axis_do_tvalid),
+      .s_axis_tready  (axis_do_tready),
+      .m_axis_tdata   (axis_dos_tdata),
+      .m_axis_tlast   (axis_dos_tlast),
+      .m_axis_tvalid  (axis_dos_tvalid),
+      .m_axis_tready  (axis_dos_tready)
+    );
+
+    // Optional DEMUX to split multiple single stream into multiple outputs
+    // Packets with an invalid (out of bounds) VC goes to port 0 
+    if (NUM_DATA_O == 6'd1) begin
+      axi_fifo #(.WIDTH(CHDR_W+1), .SIZE(1)) axis_m_reg_i (
+        .clk(rfnoc_chdr_clk), .reset(rfnoc_chdr_rst | reg_istrm_reset), .clear(1'b0),
+        .i_tdata({axis_dos_tlast, axis_dos_tdata}),
+        .i_tvalid(axis_dos_tvalid), .i_tready(axis_dos_tready),
+        .o_tdata({m_axis_data_tlast, m_axis_data_tdata}),
+        .o_tvalid(m_axis_data_tvalid), .o_tready(m_axis_data_tready),
+        .space(), .occupied()
+      );
+    end else begin
+      wire [CHDR_W-1:0] data_header;
+      wire [5:0]        data_vc = chdr_get_vc(data_header[63:0]);
+      axi_demux #(
+        .WIDTH(CHDR_W), .SIZE(NUM_DATA_O), .PRE_FIFO_SIZE(1), .POST_FIFO_SIZE(1)
+      ) axis_m_demux_i (
+        .clk(rfnoc_chdr_clk), .reset(rfnoc_chdr_rst | reg_istrm_reset), .clear(1'b0),
+        .header(data_header),
+        .dest((data_vc < NUM_DATA_O) ? data_vc[$clog2(NUM_DATA_O)-1:0] : {$clog2(NUM_DATA_O){1'b0}}),
+        .i_tdata(axis_dos_tdata), .i_tlast(axis_dos_tlast),
+        .i_tvalid(axis_dos_tvalid), .i_tready(axis_dos_tready),
+        .o_tdata(m_axis_data_tdata), .o_tlast(m_axis_data_tlast),
+        .o_tvalid(m_axis_data_tvalid), .o_tready(m_axis_data_tready)
+      );
+    end
+
+  end else begin    // if (AXIS_DATA_EN)
+
+    assign data_i_tready = 1'b1;
+    assign data_o_tdata  = {CHDR_W{1'b0}};
+    assign data_o_tlast  = 1'b0;
+    assign data_o_tvalid = 1'b0;
+
+    assign strs_i_tready = 1'b1;
+    assign strs_o_tdata  = {CHDR_W{1'b0}};
+    assign strs_o_tlast  = 1'b0;
+    assign strs_o_tvalid = 1'b0;
+
+    assign s_axis_data_tready = {NUM_DATA_I{1'b0}};
+    assign m_axis_data_tdata  = {(CHDR_W*NUM_DATA_O){1'b0}};
+    assign m_axis_data_tlast  = {NUM_DATA_O{1'b0}};
+    assign m_axis_data_tvalid = {NUM_DATA_O{1'b0}};
+
+  end endgenerate
+
+  // ---------------------------------------------------
+  //  Control Path 
+  // ---------------------------------------------------
+  generate if (AXIS_CTRL_EN) begin: ctrlpath
+
+    // Convert from a CHDR control packet to an AXIS control packet
+    chdr_to_axis_ctrl #(
+      .CHDR_W(CHDR_W), .THIS_PORTID(CTRL_XBAR_PORT)
+    ) chdr_ctrl_adapter_i (
+      .rfnoc_chdr_clk     (rfnoc_chdr_clk),
+      .rfnoc_chdr_rst     (rfnoc_chdr_rst | reg_ctrl_reset),
+      .this_epid          (reg_epid_self),
+      .s_rfnoc_chdr_tdata (ctrl_i_tdata),
+      .s_rfnoc_chdr_tlast (ctrl_i_tlast),
+      .s_rfnoc_chdr_tvalid(ctrl_i_tvalid),
+      .s_rfnoc_chdr_tready(ctrl_i_tready),
+      .m_rfnoc_chdr_tdata (ctrl_o_tdata),
+      .m_rfnoc_chdr_tlast (ctrl_o_tlast),
+      .m_rfnoc_chdr_tvalid(ctrl_o_tvalid),
+      .m_rfnoc_chdr_tready(ctrl_o_tready),
+      .rfnoc_ctrl_clk     (rfnoc_ctrl_clk),
+      .rfnoc_ctrl_rst     (rfnoc_ctrl_rst),
+      .s_rfnoc_ctrl_tdata (s_axis_ctrl_tdata),
+      .s_rfnoc_ctrl_tlast (s_axis_ctrl_tlast),
+      .s_rfnoc_ctrl_tvalid(s_axis_ctrl_tvalid),
+      .s_rfnoc_ctrl_tready(s_axis_ctrl_tready),
+      .m_rfnoc_ctrl_tdata (m_axis_ctrl_tdata),
+      .m_rfnoc_ctrl_tlast (m_axis_ctrl_tlast),
+      .m_rfnoc_ctrl_tvalid(m_axis_ctrl_tvalid),
+      .m_rfnoc_ctrl_tready(m_axis_ctrl_tready)
+    );
+
+  end else begin    // if (AXIS_CTRL_EN)
+
+    assign ctrl_i_tready = 1'b1;
+    assign ctrl_o_tdata  = {CHDR_W{1'b0}};
+    assign ctrl_o_tlast  = 1'b0;
+    assign ctrl_o_tvalid = 1'b0;
+
+    assign s_axis_ctrl_tready = 1'b1;
+    assign m_axis_ctrl_tdata  = 32'h0;
+    assign m_axis_ctrl_tlast  = 1'b0;
+    assign m_axis_ctrl_tvalid = 1'b0;
+
+  end endgenerate
+
+endmodule // chdr_stream_endpoint
+
diff --git a/fpga/usrp3/lib/rfnoc/core/chdr_stream_input.v b/fpga/usrp3/lib/rfnoc/core/chdr_stream_input.v
new file mode 100644
index 000000000..2a8a9c628
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/core/chdr_stream_input.v
@@ -0,0 +1,569 @@
+//
+// Copyright 2018-2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: chdr_stream_input
+// Description:
+//   Implements the CHDR input port for a stream endpoint.
+//   The module accepts stream command and data packets and 
+//   emits stream status packets. Flow control and error state
+//   is communicated using stream status packets. There are no
+//   external config interfaces because all configuration is done
+//   using stream command packets.
+//
+// Parameters:
+//   - CHDR_W: Width of the CHDR bus in bits
+//   - BUFF_SIZE: Buffer size in log2 of the number of words in the
+//                ingress buffer for the stream
+//   - FLUSH_TIMEOUT_W: log2 of the number of cycles to wait in order
+//                      to flush the input stream
+//   - SIGNAL_ERRS: If set to 1 then all stream errors will be notified
+//                  upstream, otherwise ALL errors are ignored
+//
+// Signals:
+//   - s_axis_chdr_* : Input CHDR stream (AXI-Stream)
+//   - m_axis_chdr_* : Output flow-controlled CHDR stream (AXI-Stream)
+//   - m_axis_strs_* : Output stream status (AXI-Stream)
+//   - data_err_stb  : If asserted, a data error notification is sent upstream
+//
+
+module chdr_stream_input #(
+  parameter CHDR_W          = 256,
+  parameter BUFF_SIZE       = 14,
+  parameter FLUSH_TIMEOUT_W = 14,
+  parameter MONITOR_EN      = 1,
+  parameter SIGNAL_ERRS     = 1
+)(
+  // Clock, reset and settings
+  input  wire              clk,
+  input  wire              rst,
+  // CHDR in (AXI-Stream)
+  input  wire [CHDR_W-1:0] s_axis_chdr_tdata,
+  input  wire              s_axis_chdr_tlast,
+  input  wire              s_axis_chdr_tvalid,
+  output wire              s_axis_chdr_tready,
+  // Flow controlled data out (AXI-Stream)
+  output wire [CHDR_W-1:0] m_axis_data_tdata,
+  output wire              m_axis_data_tlast,
+  output wire              m_axis_data_tvalid,
+  input  wire              m_axis_data_tready,
+  // Stream status out (AXI-Stream)
+  output reg  [CHDR_W-1:0] m_axis_strs_tdata,
+  output wire              m_axis_strs_tlast,
+  output wire              m_axis_strs_tvalid,
+  input  wire              m_axis_strs_tready,
+  // External stream error signal
+  input  wire              data_err_stb
+);
+
+  // The buffer size depends on the BUFF_SIZE parameter
+  localparam [40:0] BUFF_SIZE_BYTES = ((41'h1 << BUFF_SIZE) * (CHDR_W / 8)) - 41'h1;
+  // This is a flit-buffer. No packet limits
+  localparam [23:0] BUFF_SIZE_PKTS  = 24'hFFFFFF;
+
+  // ---------------------------------------------------
+  //  RFNoC Includes
+  // ---------------------------------------------------
+  `include "rfnoc_chdr_utils.vh"
+  `include "rfnoc_chdr_internal_utils.vh"
+
+  // ---------------------------------------------------
+  //  Ingress Buffer and Flow Control Logic
+  // ---------------------------------------------------
+  wire [CHDR_W-1:0] buff_tdata;
+  wire              buff_tlast, buff_tvalid;
+  reg               buff_tready;
+  wire [15:0]       buff_info;
+
+  chdr_ingress_fifo #(
+    .WIDTH(CHDR_W), .SIZE(BUFF_SIZE)
+  ) ingress_fifo_i (
+    .clk(clk), .reset(rst), .clear(1'b0),
+    .i_tdata(s_axis_chdr_tdata), .i_tlast(s_axis_chdr_tlast),
+    .i_tvalid(s_axis_chdr_tvalid), .i_tready(s_axis_chdr_tready),
+    .o_tdata(buff_tdata), .o_tlast(buff_tlast),
+    .o_tvalid(buff_tvalid), .o_tready(buff_tready)
+  );
+
+  generate if (MONITOR_EN) begin
+    wire [BUFF_SIZE:0] occ_lines;
+    axis_fifo_monitor #( .COUNT_W(BUFF_SIZE+1) ) fifo_mon_i (
+      .clk(clk), .reset(rst),
+      .i_tlast(s_axis_chdr_tlast), .i_tvalid(s_axis_chdr_tvalid), .i_tready(s_axis_chdr_tready),
+      .o_tlast(buff_tlast), .o_tvalid(buff_tvalid), .o_tready(buff_tready),
+      .i_sop(), .i_eop(), .o_sop(), .o_eop(),
+      .occupied(occ_lines), .occupied_pkts()
+    );
+    // buff_info represents a fraction of the fullness of the buffer
+    // fullness percentage = (buff_info / 32768) * 100
+    if (BUFF_SIZE + 1 >= 16)
+      assign buff_info = occ_lines[BUFF_SIZE:(BUFF_SIZE-15)];
+    else
+      assign buff_info = {occ_lines, {(15-BUFF_SIZE){1'b0}}};
+  end else begin
+    assign buff_info = 16'd0;
+  end endgenerate
+
+  // Flow Control State
+  // xfer_cnt: Total transfer count since fc_enabled = 1
+  // accum: Transfer count since last FC response
+  // fc_freq: The threshold for sending an FC response
+  reg [63:0] xfer_cnt_bytes = 64'd0;
+  reg [39:0] xfer_cnt_pkts  = 40'd0;
+  reg [63:0] accum_bytes    = 64'd0;
+  reg [39:0] accum_pkts     = 40'd0;
+  reg [63:0] fc_freq_bytes  = 64'd0;
+  reg [39:0] fc_freq_pkts   = 40'd0;
+
+  // State machine transition signals info
+  reg        fc_enabled = 1'b0;   // Is flow control enabled?
+  wire       fc_ping;             // A flow control response was requested
+  wire       fc_first_resp;       // Send the first flow control response
+  wire       fc_refresh;          // Refresh accumulated values
+  wire       fc_override;         // Override total xfer counts
+  reg        fc_override_del = 1'b0;
+  reg  [3:0] fc_due_shreg = 4'h0; // Is a response due? (shift register)
+
+  // Endpoint IDs of this endpoint and the stream source
+  reg [15:0] this_epid = 16'd0, return_epid = 16'd0;
+
+  // Cached values from a stream command
+  reg [63:0] strc_num_bytes;
+  reg [39:0] strc_num_pkts;
+  reg [3:0]  strc_op_data;  // Unused for now
+  reg [3:0]  strc_op_code;
+
+  // Total transfer count updater
+  always @(posedge clk) begin
+    if (rst || !fc_enabled) begin
+      // Reset
+      xfer_cnt_bytes <= 64'd0;
+      xfer_cnt_pkts  <= 40'd0;
+    end else if (fc_override) begin
+      // Override
+      xfer_cnt_bytes <= strc_num_bytes;
+      xfer_cnt_pkts  <= strc_num_pkts;
+    end else if (buff_tvalid && buff_tready) begin
+      // Count
+      xfer_cnt_bytes <= xfer_cnt_bytes + (CHDR_W/8);
+      if (buff_tlast)
+        xfer_cnt_pkts <= xfer_cnt_pkts + 40'd1;
+    end
+  end
+
+  // Accumulated transfer count updater
+  always @(posedge clk) begin
+    if (rst || !fc_enabled || fc_refresh) begin
+      // Reset
+      accum_bytes <= 64'd0;
+      accum_pkts  <= 40'd0;
+    end else if (buff_tvalid && buff_tready) begin
+      // Count
+      accum_bytes <= accum_bytes + (CHDR_W/8);
+      if (buff_tlast)
+        accum_pkts <= accum_pkts + 40'd1;
+    end
+  end
+
+  // Flow control trigger
+  // Why a shift-register here?
+  // 1. For edge detection
+  // 2. To allow the tools to re-time the wide comparators.
+  //    We don't care about the latency here because stream
+  //    status messages are asynchronous wrt the input.
+  always @(posedge clk) begin
+    if (rst || !fc_enabled) begin
+      fc_due_shreg <= 4'h0;
+    end else begin
+      fc_due_shreg <= {
+        fc_due_shreg[2:0],
+        (accum_bytes >= fc_freq_bytes) || (accum_pkts >= fc_freq_pkts)
+      };
+    end
+  end
+  wire fc_resp_due = fc_due_shreg[2] && !fc_due_shreg[3];
+
+   // ---------------------------------------------------
+  //  Stream Command Handler
+  // ---------------------------------------------------
+  localparam [2:0] ST_IN_HDR    = 3'd0;   // The CHDR header of an input pkt
+  localparam [2:0] ST_IN_DATA   = 3'd1;   // The CHDR body (incl. mdata) of an input pkt
+  localparam [2:0] ST_STRC_W0   = 3'd2;   // The first word of a stream command
+  localparam [2:0] ST_STRC_W1   = 3'd3;   // The second word of a stream command
+  localparam [2:0] ST_STRC_EXEC = 3'd4;   // A stream command is executing
+  localparam [2:0] ST_FLUSH     = 3'd5;   // Input is flushing
+  localparam [2:0] ST_DROP      = 3'd6;   // Current packet is being dropped
+
+  reg [2:0]   state = ST_IN_HDR;          // State of the input state machine
+  reg         pkt_too_long = 1'b0;        // Error case. Packet is too long
+  reg         is_first_data_pkt = 1'b1;   // Is this the first data pkt after fc_enabled = 1?
+  reg         is_first_strc_pkt = 1'b1;   // Is this the strm cmd data pkt after fc_enabled = 1?
+  reg [15:0]  exp_data_seq_num = 16'd0;   // Expected sequence number for the next data pkt
+  reg [15:0]  exp_strc_seq_num = 16'd0;   // Expected sequence number for the next stream cmd pkt
+  reg [15:0]  strc_dst_epid = 16'd0;      // EPID in CHDR header of STRC packet 
+
+  reg [FLUSH_TIMEOUT_W-1:0] flush_counter = {FLUSH_TIMEOUT_W{1'b0}};
+
+  // Shortcuts
+  wire is_data_pkt = 
+    chdr_get_pkt_type(buff_tdata[63:0]) == CHDR_PKT_TYPE_DATA ||
+    chdr_get_pkt_type(buff_tdata[63:0]) == CHDR_PKT_TYPE_DATA_TS;
+  wire is_strc_pkt =
+    chdr_get_pkt_type(buff_tdata[63:0]) == CHDR_PKT_TYPE_STRC;
+
+  // Error Logic
+  wire data_seq_err_stb = (state == ST_IN_HDR) && is_data_pkt && !is_first_data_pkt &&
+    (chdr_get_seq_num(buff_tdata[63:0]) != exp_data_seq_num);
+  wire strc_seq_err_stb = (state == ST_IN_HDR) && is_strc_pkt && !is_first_strc_pkt &&
+    (chdr_get_seq_num(buff_tdata[63:0]) != exp_strc_seq_num);
+  wire seq_err_stb = (data_seq_err_stb || strc_seq_err_stb) && buff_tvalid && buff_tready;
+
+  wire route_err_stb = buff_tvalid && buff_tready && (state == ST_IN_HDR) && 
+    (chdr_get_dst_epid(buff_tdata[63:0]) != this_epid);
+
+  // Break critical paths to response FIFO
+  reg [47:0] stream_err_info = 48'h0;
+  reg        stream_err_stb = 1'b0;
+  reg [3:0]  stream_err_status = CHDR_STRS_STATUS_OKAY;
+
+  always @(posedge clk) begin
+    if (rst || (SIGNAL_ERRS == 0)) begin
+      stream_err_stb <= 1'b0;
+    end else begin
+      stream_err_stb <= seq_err_stb | route_err_stb | data_err_stb;
+      if (seq_err_stb) begin
+        stream_err_status <= CHDR_STRS_STATUS_SEQERR;
+        // The extended info has the packet type (to detect which stream
+        // had an error), the expected and actual sequence number.
+        stream_err_info <= {13'h0, chdr_get_pkt_type(buff_tdata[63:0]),
+            data_seq_err_stb ? exp_data_seq_num : exp_strc_seq_num, 
+            chdr_get_seq_num(buff_tdata[63:0])};
+      end else if (route_err_stb) begin
+        stream_err_status <= CHDR_STRS_STATUS_RTERR;
+        // The extended info has the expected and actual destination EPID.
+        stream_err_info <= {16'd0, this_epid, chdr_get_dst_epid(buff_tdata[63:0])};
+      end else begin
+        stream_err_status <= CHDR_STRS_STATUS_DATAERR;
+        // The extended info has the expected and actual destination EPID.
+        stream_err_info <= {16'd0, this_epid, chdr_get_dst_epid(buff_tdata[63:0])};
+      end
+    end
+  end
+
+  // Input State Machine
+  // - Pass data packets forward
+  // - Consume stream cmd packets
+  always @(posedge clk) begin
+    if (rst) begin
+      state <= ST_IN_HDR;
+      pkt_too_long <= 1'b0;
+      fc_enabled <= 1'b0;
+    end else begin
+      case (state)
+        ST_IN_HDR: begin
+          if (buff_tvalid && buff_tready) begin
+            if (!buff_tlast) begin
+              // Classify packet and...
+              if (is_strc_pkt) begin
+                // ...consume if it is a stream command or...
+                state <= ST_STRC_W0;
+              end else if (is_data_pkt) begin
+                // ...pass to output if it is a data packet...
+                state <= ST_IN_DATA;
+              end else begin
+                // ... otherwise drop.
+                state <= ST_DROP;
+              end
+            end
+            // Update other state vars
+            pkt_too_long <= 1'b0;
+            if (is_strc_pkt) begin
+              is_first_strc_pkt <= 1'b0;
+              strc_dst_epid <= chdr_get_dst_epid(buff_tdata[63:0]);
+              exp_strc_seq_num <= chdr_get_seq_num(buff_tdata[63:0]) + 16'd1;
+            end else if (is_data_pkt) begin
+              is_first_data_pkt <= 1'b0;
+              exp_data_seq_num <= chdr_get_seq_num(buff_tdata[63:0]) + 16'd1;
+            end
+          end
+        end
+        ST_IN_DATA: begin
+          // Pass the data packet forward
+          if (buff_tvalid && buff_tready && buff_tlast)
+            state <= ST_IN_HDR;
+        end
+        ST_STRC_W0: begin
+          if (buff_tvalid && buff_tready) begin
+            // Consume the first word of a stream command packet
+            if (CHDR_W > 64) begin
+              strc_num_bytes <= chdr128_strc_get_num_bytes(buff_tdata[127:0]);
+              strc_num_pkts  <= chdr128_strc_get_num_pkts (buff_tdata[127:0]);
+              strc_op_data   <= chdr128_strc_get_op_data  (buff_tdata[127:0]);
+              strc_op_code   <= chdr128_strc_get_op_code  (buff_tdata[127:0]);
+              return_epid    <= chdr128_strs_get_src_epid (buff_tdata[127:0]);
+              state <= ST_STRC_EXEC;
+              pkt_too_long <= ~buff_tlast;
+            end else begin
+              strc_num_pkts <= chdr64_strc_get_num_pkts(buff_tdata[63:0]);
+              strc_op_data  <= chdr64_strc_get_op_data (buff_tdata[63:0]);
+              strc_op_code  <= chdr64_strc_get_op_code (buff_tdata[63:0]);
+              return_epid   <= chdr64_strs_get_src_epid(buff_tdata[63:0]);
+              state <= ST_STRC_W1;
+            end
+          end
+        end
+        ST_STRC_W1: begin
+          if (buff_tvalid && buff_tready) begin
+            // Consume the second word of a stream command packet
+            strc_num_bytes <= chdr64_strc_get_num_bytes(buff_tdata[63:0]);
+            state <= ST_STRC_EXEC;
+            pkt_too_long <= ~buff_tlast;
+          end
+        end
+        ST_STRC_EXEC: begin
+          case (strc_op_code)
+            CHDR_STRC_OPCODE_INIT: begin
+              // Configure FC but disable it temporarily
+              fc_freq_bytes <= strc_num_bytes;
+              fc_freq_pkts <= strc_num_pkts;
+              this_epid <= strc_dst_epid;
+              fc_enabled <= 1'b0;
+              // Flush the input
+              state <= ST_FLUSH;
+              flush_counter <= {FLUSH_TIMEOUT_W{1'b1}};
+            end
+            CHDR_STRC_OPCODE_PING: begin
+              // Ping can complete in 1 cycle
+              state <= pkt_too_long ? ST_DROP : ST_IN_HDR;
+            end
+            CHDR_STRC_OPCODE_RESYNC: begin
+              // Resync can complete in 1 cycle
+              state <= pkt_too_long ? ST_DROP : ST_IN_HDR;
+            end
+            default: begin
+              state <= pkt_too_long ? ST_DROP : ST_IN_HDR;
+            end
+          endcase
+        end
+        ST_FLUSH: begin
+          // Drop until the next packet arrives
+          if (buff_tvalid && buff_tready) begin
+            flush_counter <= {FLUSH_TIMEOUT_W{1'b1}};
+          end else begin
+            flush_counter <= flush_counter - 'd1;
+            if (flush_counter == {FLUSH_TIMEOUT_W{1'b0}}) begin
+              // Done flushing. Re-arm flow control and reset packet
+              // sequence check info.
+              fc_enabled <= 1'b1;
+              is_first_data_pkt <= 1'b1;
+              is_first_strc_pkt <= 1'b1;
+              state <= ST_IN_HDR;
+            end
+          end
+        end
+        ST_DROP: begin
+          // Drop until the next packet arrives
+          if (buff_tvalid && buff_tready && buff_tlast)
+            state <= ST_IN_HDR;
+        end
+        default: begin
+          // We should never get here
+          state <= ST_IN_HDR;
+        end
+      endcase
+    end
+  end
+
+  always @(*) begin
+    case (state)
+      ST_IN_HDR:
+        buff_tready = m_axis_data_tready || !is_data_pkt;
+      ST_IN_DATA:
+        buff_tready = m_axis_data_tready;
+      ST_STRC_W0:
+        buff_tready = 1'b1;
+      ST_STRC_W1:
+        buff_tready = 1'b1;
+      ST_FLUSH:
+        buff_tready = 1'b1;
+      ST_DROP:
+        buff_tready = 1'b1;
+      default:
+        buff_tready = 1'b0;
+    endcase
+  end
+
+  // Logic to drive output port
+  assign m_axis_data_tdata  = buff_tdata;
+  assign m_axis_data_tlast  = buff_tlast;
+  assign m_axis_data_tvalid = buff_tvalid && 
+    ((state == ST_IN_HDR && is_data_pkt) || state == ST_IN_DATA);
+
+  // Logic to drive triggers
+  assign fc_ping = (state == ST_STRC_EXEC) && (strc_op_code == CHDR_STRC_OPCODE_PING);
+  assign fc_first_resp = (state == ST_FLUSH) && (flush_counter == {FLUSH_TIMEOUT_W{1'b0}});
+  assign fc_override = (state == ST_STRC_EXEC) && (strc_op_code == CHDR_STRC_OPCODE_RESYNC);
+  always @(posedge clk) fc_override_del <= fc_override;
+
+  wire [51:0] resp_o_tdata;
+  wire        resp_o_tvalid;
+  reg  [51:0] resp_i_tdata;
+  reg         resp_i_tvalid = 1'b0;
+
+  // Send a stream status packet for the following cases:
+  // - Immediately after initialization 
+  // - If a response is explicitly requested (ping)
+  // - If a response is due i.e. we have exceeded the frequency
+  // - If FC is resynchronized via a stream cmd
+  // - If an error is detected in the stream
+  always @(posedge clk) begin
+    if (rst) begin
+      resp_i_tvalid <= 1'b0;
+      resp_i_tdata  <= 52'h0;
+    end else begin
+      resp_i_tvalid <= fc_first_resp || fc_ping || fc_resp_due || fc_override_del || stream_err_stb;
+      resp_i_tdata  <= stream_err_stb ? {stream_err_info, stream_err_status} : {48'h0, CHDR_STRS_STATUS_OKAY};
+    end
+  end
+
+  // ---------------------------------------------------
+  //  Stream Status Responder
+  // ---------------------------------------------------
+  localparam [2:0] ST_STRS_IDLE = 3'd0;   // Waiting for response to post
+  localparam [2:0] ST_STRS_HDR  = 3'd1;   // Sending response CHDR header
+  localparam [2:0] ST_STRS_W0   = 3'd2;   // Sending first response word
+  localparam [2:0] ST_STRS_W1   = 3'd3;   // Sending second response word
+  localparam [2:0] ST_STRS_W2   = 3'd4;   // Sending third response word
+  localparam [2:0] ST_STRS_W3   = 3'd5;   // Sending fourth response word
+  localparam [2:0] ST_STRS_DONE = 3'd6;   // Consuming response
+
+  reg [2:0]  resp_state = ST_STRS_IDLE;   // State of the responder
+  reg [15:0] resp_seq_num = 16'd0;        // Current sequence number of response
+
+  assign fc_refresh = (resp_state == ST_STRS_DONE);
+
+  // A FIFO that holds up to 32 posted responses and status information
+  // NOTE: This is a lossy FIFO. If the downstream response port is clogged
+  // then we will drop responses. That should never happen in a normal operating
+  // scenario.
+  axi_fifo #(.WIDTH(48 + 4), .SIZE(5)) resp_fifo_i (
+    .clk(clk), .reset(rst), .clear(1'b0),
+    .i_tdata(resp_i_tdata), .i_tvalid(resp_i_tvalid), .i_tready(/* Lossy FIFO */),
+    .o_tdata(resp_o_tdata), .o_tvalid(resp_o_tvalid), .o_tready(resp_state == ST_STRS_DONE || !fc_enabled),
+    .space(), .occupied()
+  );
+
+  // Responder State Machine
+  // - Wait for response to appear in FIFO
+  // - Output a full packet (different # of xfers depending on CHDR_W)
+  always @(posedge clk) begin
+    if (rst || !fc_enabled) begin
+      resp_state <= ST_STRS_IDLE;
+      resp_seq_num <= 16'd0;
+    end else begin
+      case (resp_state)
+        ST_STRS_IDLE: begin
+          if (resp_o_tvalid)
+            resp_state <= ST_STRS_HDR;
+        end
+        ST_STRS_HDR: begin
+          if (m_axis_strs_tready)
+            resp_state <= ST_STRS_W0;
+        end
+        ST_STRS_W0: begin
+          if (m_axis_strs_tready)
+            if (CHDR_W < 256)
+              resp_state <= ST_STRS_W1;
+            else
+              resp_state <= ST_STRS_DONE;
+        end
+        ST_STRS_W1: begin
+          if (m_axis_strs_tready)
+            if (CHDR_W < 128)
+              resp_state <= ST_STRS_W2;
+            else
+              resp_state <= ST_STRS_DONE;
+        end
+        ST_STRS_W2: begin
+          if (m_axis_strs_tready)
+            resp_state <= ST_STRS_W3;
+        end
+        ST_STRS_W3: begin
+          if (m_axis_strs_tready)
+            resp_state <= ST_STRS_DONE;
+        end
+        ST_STRS_DONE: begin
+          resp_state <= ST_STRS_IDLE;
+          resp_seq_num <= resp_seq_num + 16'd1;
+        end
+        default: begin
+          // We should never get here
+          resp_state <= ST_STRS_IDLE;
+        end
+      endcase
+    end
+  end
+
+  // Output data. Header and Payload
+  wire [63:0] strs_header = chdr_build_header(
+    /*VC*/ 6'd0, /*eob*/ 1'b0, /*eov*/ 1'b0, CHDR_PKT_TYPE_STRS, CHDR_NO_MDATA,
+    resp_seq_num, 16'd32+(CHDR_W/8), return_epid);
+  wire [255:0] strs_payload = chdr256_strs_build(
+    /*statusinfo*/ resp_o_tdata[51:4], buff_info,
+    xfer_cnt_bytes, xfer_cnt_pkts,
+    BUFF_SIZE_PKTS[23:0], BUFF_SIZE_BYTES[39:0],
+    resp_o_tdata[3:0], this_epid);
+
+  // m_axis_strs_* signal values depend on CHDR_W
+  generate
+    if (CHDR_W == 64) begin
+      // Response spans 5 transfers (header + 4 words)
+      assign m_axis_strs_tlast = (resp_state == ST_STRS_W3);
+      always @(*) begin
+        case (resp_state)
+          ST_STRS_W0:
+            m_axis_strs_tdata = strs_payload[63:0];
+          ST_STRS_W1:
+            m_axis_strs_tdata = strs_payload[127:64];
+          ST_STRS_W2:
+            m_axis_strs_tdata = strs_payload[191:128];
+          ST_STRS_W3:
+            m_axis_strs_tdata = strs_payload[255:192];
+          default:
+            m_axis_strs_tdata = strs_header;
+        endcase
+      end
+    end else if (CHDR_W == 128) begin
+      // Response spans 3 transfers (header + 2 words)
+      assign m_axis_strs_tlast = (resp_state == ST_STRS_W1);
+      always @(*) begin
+        case (resp_state)
+          ST_STRS_W0:
+            m_axis_strs_tdata = strs_payload[127:0];
+          ST_STRS_W1:
+            m_axis_strs_tdata = strs_payload[255:128];
+          default:
+            m_axis_strs_tdata = {64'h0, strs_header};
+        endcase
+      end
+    end else begin
+      // Response spans 2 transfers (header + word)
+      assign m_axis_strs_tlast = (resp_state == ST_STRS_W0);
+      always @(*) begin
+        case (resp_state)
+          ST_STRS_W0:
+            m_axis_strs_tdata[255:0] = strs_payload;
+          default:
+            m_axis_strs_tdata[255:0] = {192'h0, strs_header};
+        endcase
+        if (CHDR_W > 256) begin
+          m_axis_strs_tdata[CHDR_W-1:256] = 'h0;
+        end
+      end
+    end
+  endgenerate
+
+  assign m_axis_strs_tvalid = (resp_state != ST_STRS_IDLE) && (resp_state != ST_STRS_DONE);
+
+endmodule // chdr_stream_input
diff --git a/fpga/usrp3/lib/rfnoc/core/chdr_stream_output.v b/fpga/usrp3/lib/rfnoc/core/chdr_stream_output.v
new file mode 100644
index 000000000..271c7fccc
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/core/chdr_stream_output.v
@@ -0,0 +1,557 @@
+//
+// Copyright 2018-2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: chdr_stream_output
+// Description:
+//   Implements the CHDR output port for a stream endpoint.
+//   The module generates stream command packets to setup
+//   a downstream endpoint module (chdr_stream_input). Once
+//   a stream is setup, the CHDR data on the axis_data port
+//   can be sent downstream with full flow control. Stream
+//   status messages are recieved from the downstream node
+//   to update flow control state. This module has an external
+//   configuration bus to initiate stream creation.
+//
+// Parameters:
+//   - CHDR_W: Width of the CHDR bus in bits
+//   - MTU: Log2 of the maximum number of lines in a packet
+//
+// Signals:
+//   - m_axis_chdr_* : Output CHDR stream (AXI-Stream)
+//   - s_axis_data_* : Input CHDR Data stream (AXI-Stream) before flow control
+//   - s_axis_strs_* : Input stream status (AXI-Stream)
+
+module chdr_stream_output #(
+  parameter CHDR_W = 256,
+  parameter MTU    = 10
+)(
+  // Clock, reset and settings
+  input  wire              clk,
+  input  wire              rst,
+  // CHDR out (AXI-Stream)
+  output wire [CHDR_W-1:0] m_axis_chdr_tdata,
+  output wire              m_axis_chdr_tlast,
+  output wire              m_axis_chdr_tvalid,
+  input  wire              m_axis_chdr_tready,
+  // Data packets in (AXI-Stream)
+  input  wire [CHDR_W-1:0] s_axis_data_tdata,
+  input  wire              s_axis_data_tlast,
+  input  wire              s_axis_data_tvalid,
+  output wire              s_axis_data_tready,
+  // Stream status in (AXI-Stream)
+  input  wire [CHDR_W-1:0] s_axis_strs_tdata,
+  input  wire              s_axis_strs_tlast,
+  input  wire              s_axis_strs_tvalid,
+  output wire              s_axis_strs_tready,
+  // Configuration port
+  input  wire              cfg_start,
+  output reg               cfg_pending = 1'b0,
+  output reg               cfg_failed = 1'b0,
+  input  wire              cfg_lossy_xport,
+  input  wire [15:0]       cfg_dst_epid,
+  input  wire [15:0]       cfg_this_epid,
+  input  wire [39:0]       cfg_fc_freq_bytes,
+  input  wire [23:0]       cfg_fc_freq_pkts,
+  input  wire [15:0]       cfg_fc_headroom_bytes,
+  input  wire [7:0]        cfg_fc_headroom_pkts,
+  // Flow control status
+  output reg               fc_enabled     = 1'b0,
+  output reg  [39:0]       capacity_bytes = 40'd0,
+  output reg  [23:0]       capacity_pkts  = 24'd0,
+  // Stream status
+  output wire              seq_err_stb,
+  output reg  [31:0]       seq_err_cnt = 32'd0,
+  output wire              data_err_stb,
+  output reg  [31:0]       data_err_cnt = 32'd0,
+  output wire              route_err_stb,
+  output reg  [31:0]       route_err_cnt = 32'd0
+);
+
+  // ---------------------------------------------------
+  //  RFNoC Includes
+  // ---------------------------------------------------
+  `include "rfnoc_chdr_utils.vh"
+  `include "rfnoc_chdr_internal_utils.vh"
+
+  localparam CHDR_W_LOG2 = $clog2(CHDR_W);
+
+  // ---------------------------------------------------
+  //  Output packet gate
+  // ---------------------------------------------------
+  reg  [CHDR_W-1:0] chdr_out_tdata;
+  reg               chdr_out_tlast, chdr_out_tvalid;
+  wire              chdr_out_tready;
+
+  axi_packet_gate #(
+    .WIDTH(CHDR_W), .SIZE(MTU), .USE_AS_BUFF(0)
+  ) chdr_pkt_gate_i (
+    .clk(clk), .reset(rst), .clear(1'b0),
+    .i_tdata(chdr_out_tdata), .i_tlast(chdr_out_tlast), .i_terror(1'b0),
+    .i_tvalid(chdr_out_tvalid), .i_tready(chdr_out_tready),
+    .o_tdata(m_axis_chdr_tdata), .o_tlast(m_axis_chdr_tlast),
+    .o_tvalid(m_axis_chdr_tvalid), .o_tready(m_axis_chdr_tready)
+  );
+
+  // ---------------------------------------------------
+  //  Flow Control State
+  // ---------------------------------------------------
+
+  // send_cnt: Total transfer count at the sender (here)
+  // recv_cnt: Total transfer count at the receiver
+  // accum:    Transfer count since last FC resynchronization request
+  // headroom: Total headroom to keep in the downstream buffer
+  // adj_cap:  The adjusted capacity (after headroom) of the downstream buffer
+  // strc_cnt: Saved count for the STRC packet (prevents mid-packet updates)
+  reg [63:0] send_cnt_bytes = 64'd0;
+  reg [39:0] send_cnt_pkts  = 40'd0;
+  reg [63:0] recv_cnt_bytes = 64'd0;
+  reg [39:0] recv_cnt_pkts  = 40'd0;
+  reg [39:0] accum_bytes    = 40'd0;
+  reg [23:0] accum_pkts     = 24'd0;
+  reg [15:0] headroom_bytes = 16'd0;
+  reg [ 7:0] headroom_pkts  =  8'd0;
+  reg [39:0] adj_cap_bytes  = 40'd0;
+  reg [23:0] adj_cap_pkts   = 24'd0;
+  reg [63:0] strc_cnt_bytes = 64'd0;
+
+  // Output transfer count
+  always @(posedge clk) begin
+    if (rst || !fc_enabled) begin
+      send_cnt_bytes <= 64'd0;
+      send_cnt_pkts  <= 40'd0;
+    end else if (chdr_out_tvalid && chdr_out_tready) begin
+      send_cnt_bytes <= send_cnt_bytes + (CHDR_W/8);
+      if (chdr_out_tlast)
+        send_cnt_pkts <= send_cnt_pkts + 40'd1;
+    end
+  end
+
+  // Buffer occupied counts
+  // TODO: Need better overflow handling
+  wire signed [64:0] occupied_bytes = 
+    $signed({1'b0, send_cnt_bytes}) - $signed({1'b0, recv_cnt_bytes});
+  wire signed [40:0] occupied_pkts =
+    $signed({1'b0, send_cnt_pkts}) - $signed({1'b0, recv_cnt_pkts});
+
+  // OK-to-Send shift register
+  // - Why a shift-register here?
+  //   To allow the tools to re-time the wide comparators.
+  // - We don't care about the latency here because stream
+  //   status messages are asynchronous wrt the data
+  reg  [3:0] ok_shreg = 4'b1111; // OK to send? (shift register)
+  always @(posedge clk) begin
+    if (rst || !fc_enabled) begin
+      ok_shreg <= 4'b1111;
+    end else begin
+      ok_shreg <= {ok_shreg[2:0], (
+        (occupied_bytes[40:0] < $signed({1'b0, adj_cap_bytes})) &&
+        (occupied_pkts [24:0] < $signed({1'b0, adj_cap_pkts }))
+      )};
+    end
+  end
+  wire ok_to_send = ok_shreg[3];
+
+  // Accumulated transfer count updater for FC resync
+  reg lossy_xport = 1'b0;
+  reg [3:0] fc_resync_req_shreg = 4'h0;
+  wire fc_resync_req, fc_resync_ack;
+
+  always @(posedge clk) begin
+    if (rst || !fc_enabled || !lossy_xport || fc_resync_ack) begin
+      // Reset
+      accum_bytes <= 40'd0;
+      accum_pkts <= 24'd0;
+      fc_resync_req_shreg <= 4'b0000;
+    end else begin 
+      if (chdr_out_tvalid && chdr_out_tready) begin
+        // Count
+        accum_bytes <= accum_bytes + (CHDR_W/8);
+        if (chdr_out_tlast)
+          accum_pkts <= accum_pkts + 24'd1;
+      end
+      // FC resync request
+      fc_resync_req_shreg <= {fc_resync_req_shreg[2:0],
+        (accum_bytes > capacity_bytes) || (accum_pkts > capacity_pkts)};
+    end
+  end
+  assign fc_resync_req = fc_resync_req_shreg[3];
+
+  // ---------------------------------------------------
+  //  Stream Status Parser
+  // ---------------------------------------------------
+
+  wire [3:0] msg_i_tdata,  msg_o_tdata;
+  wire       msg_i_tvalid, msg_o_tvalid;
+  wire       msg_i_tready, msg_o_tready;
+
+  axi_fifo #(.WIDTH(4), .SIZE(1)) msg_fifo_i (
+    .clk(clk), .reset(rst), .clear(1'b0),
+    .i_tdata(msg_i_tdata), .i_tvalid(msg_i_tvalid), .i_tready(msg_i_tready),
+    .o_tdata(msg_o_tdata), .o_tvalid(msg_o_tvalid), .o_tready(msg_o_tready),
+    .space(), .occupied()
+  );
+
+  localparam [2:0] ST_STRS_HDR   = 3'd0;  // Receiving the CHDR header of a stream status msg
+  localparam [2:0] ST_STRS_W0    = 3'd1;  // Receiving the first word of a stream status msg
+  localparam [2:0] ST_STRS_W1    = 3'd2;  // Receiving the second word of a stream status msg
+  localparam [2:0] ST_STRS_W2    = 3'd3;  // Receiving the third word of a stream status msg
+  localparam [2:0] ST_STRS_W3    = 3'd4;  // Receiving the fourth word of a stream status msg
+  localparam [2:0] ST_STRS_LATCH = 3'd5;  // Atomically updating and posting the status msg
+  localparam [2:0] ST_STRS_DROP  = 3'd6;  // Something went wrong dropping current packet
+
+  reg [2:0]   strs_state = ST_STRS_HDR;
+  reg         strs_too_long = 1'b0;
+  reg [15:0]  cached_dst_epid = 16'd0;
+  reg [255:0] cached_strs_msg;
+
+  always @(posedge clk) begin
+    if (rst) begin
+      strs_state <= ST_STRS_HDR;
+      strs_too_long <= 1'b0;
+    end else begin
+      case (strs_state)
+
+        // ST_STRS_HDR
+        // ------------------
+        ST_STRS_HDR: begin
+          if (s_axis_strs_tvalid) begin
+            // Only accept stream status packets. Drop everything else
+            if (chdr_get_pkt_type(s_axis_strs_tdata[63:0]) == CHDR_PKT_TYPE_STRS)
+              strs_state <= ST_STRS_W0;
+            else
+              strs_state <= ST_STRS_DROP;
+            strs_too_long <= 1'b0;
+          end
+        end
+
+        // ST_STRS_W0
+        // ------------------
+        // - Cache the first word of the stream status
+        // - For CHDR_W == 64, this is one of 4 words.
+        // - For CHDR_W == 128, this is one of 2 words.
+        // - For CHDR_W >= 256, this is the only word.
+        ST_STRS_W0: begin
+          if (s_axis_strs_tvalid) begin
+            if (CHDR_W == 64) begin
+              cached_strs_msg[63:0] <= s_axis_strs_tdata[63:0];
+              strs_state <= !s_axis_strs_tlast ? ST_STRS_W1 : ST_STRS_HDR;
+            end else if (CHDR_W == 128) begin
+              cached_strs_msg[127:0] <= s_axis_strs_tdata[127:0];
+              strs_state <= !s_axis_strs_tlast ? ST_STRS_W1 : ST_STRS_HDR;
+            end else begin  //CHDR_W >= 256
+              cached_strs_msg[255:0] <= s_axis_strs_tdata[255:0];
+              strs_state <= ST_STRS_LATCH;
+              strs_too_long <= !s_axis_strs_tlast;
+            end
+          end
+        end
+
+        // ST_STRS_W1
+        // ------------------
+        // - Cache the second word of the stream status
+        ST_STRS_W1: begin
+          if (s_axis_strs_tvalid) begin
+            if (CHDR_W == 64) begin
+              cached_strs_msg[127:64] <= s_axis_strs_tdata[63:0];
+              strs_state <= !s_axis_strs_tlast ? ST_STRS_W2 : ST_STRS_HDR;
+            end else begin  //CHDR_W >= 128
+              cached_strs_msg[255:128] <= s_axis_strs_tdata[127:0];
+              strs_state <= ST_STRS_LATCH;
+              strs_too_long <= !s_axis_strs_tlast;
+            end
+          end
+        end
+
+        // ST_STRS_W2
+        // ------------------
+        // - Cache the third word of the stream status
+        ST_STRS_W2: begin
+          if (s_axis_strs_tvalid) begin
+            cached_strs_msg[191:128] <= s_axis_strs_tdata[63:0];
+              strs_state <= !s_axis_strs_tlast ? ST_STRS_W3 : ST_STRS_HDR;
+          end
+        end
+
+        // ST_STRS_W3
+        // ------------------
+        // - Cache the fourth word of the stream status
+        ST_STRS_W3: begin
+          if (s_axis_strs_tvalid) begin
+            cached_strs_msg[255:192] <= s_axis_strs_tdata[63:0];
+            strs_state <= ST_STRS_LATCH;
+            strs_too_long <= !s_axis_strs_tlast;
+          end
+        end
+
+        // ST_STRS_LATCH
+        // ------------------
+        // - Act on the received stream status
+        ST_STRS_LATCH: begin
+          capacity_bytes <= chdr256_strs_get_capacity_bytes(cached_strs_msg);
+          capacity_pkts  <= chdr256_strs_get_capacity_pkts(cached_strs_msg);
+          recv_cnt_bytes <= chdr256_strs_get_xfercnt_bytes(cached_strs_msg);
+          recv_cnt_pkts  <= chdr256_strs_get_xfercnt_pkts(cached_strs_msg);
+          adj_cap_bytes  <= chdr256_strs_get_capacity_bytes(cached_strs_msg) - 
+                            {24'd0, headroom_bytes[15:(CHDR_W_LOG2-3)], {(CHDR_W_LOG2-3){1'b0}}};
+          adj_cap_pkts   <= chdr256_strs_get_capacity_pkts(cached_strs_msg) - 
+                            {16'd0, headroom_pkts};
+          if (msg_i_tready) begin
+            strs_state <= strs_too_long ? ST_STRS_DROP : ST_STRS_HDR;
+          end
+        end
+
+        // ST_STRS_DROP
+        // ------------------
+        ST_STRS_DROP: begin
+          if (s_axis_strs_tvalid && s_axis_strs_tlast)
+            strs_state <= ST_STRS_HDR;
+        end
+        default: begin
+          // We should never get here
+          strs_state <= ST_STRS_HDR;
+        end
+      endcase
+    end
+  end
+
+  assign s_axis_strs_tready = (strs_state != ST_STRS_LATCH);
+
+  assign msg_i_tvalid = (strs_state == ST_STRS_LATCH);
+  assign msg_i_tdata = (chdr256_strs_get_src_epid(cached_strs_msg) != cached_dst_epid) ? 
+    CHDR_STRS_STATUS_CMDERR : chdr256_strs_get_status(cached_strs_msg);
+
+
+  // ---------------------------------------------------
+  //  Main State Machine
+  // ---------------------------------------------------
+
+  localparam [2:0] ST_PASS_DATA = 3'd0;   // Passing input axis_data out
+  localparam [2:0] ST_STRC_HDR  = 3'd1;   // Sending CHDR header for stream cmd
+  localparam [2:0] ST_STRC_W0   = 3'd2;   // Sending first word of stream cmd
+  localparam [2:0] ST_STRC_W1   = 3'd3;   // Sending second word of stream cmd
+  localparam [2:0] ST_STRC_WAIT = 3'd4;   // Waiting for response (stream status)
+  localparam [2:0] ST_INIT_DLY  = 3'd5;   // Finishing command execution
+
+  reg [2:0]   state = ST_PASS_DATA;
+  reg         mid_pkt = 1'b0;
+  reg [15:0]  data_seq_num = 16'd0;
+  reg [15:0]  strc_seq_num = 16'd0;
+  reg [2:0]   cfg_delay = 3'd0;
+
+  always @(posedge clk) begin
+    if (rst) begin
+      state <= ST_PASS_DATA;
+      mid_pkt <= 1'b0;
+      data_seq_num <= 16'd0;
+      strc_seq_num <= 16'd0;
+      cfg_pending <= 1'b0;
+      cfg_failed <= 1'b0;
+    end else begin
+      case (state)
+
+        // ST_PASS_DATA
+        // ------------------
+        // This is the default state where input data is passed to the
+        // output port. Flow control is enforced in this state.
+        // This state also serves as the launch state for a configuration
+        // operation (using cfg_start) 
+        ST_PASS_DATA: begin
+          // Update the mid_pkt flag and sequence number
+          if (chdr_out_tvalid && chdr_out_tready) begin
+            mid_pkt <= !chdr_out_tlast;
+            if (chdr_out_tlast)
+              data_seq_num <= data_seq_num + 16'd1;
+          end
+          // Launch a configuration operation
+          if (cfg_start) begin
+            // Latch cfg command
+            cfg_pending <= 1'b1;
+            cfg_failed <= 1'b0;
+            // Disable flow control
+            fc_enabled <= 1'b0;
+            // Cache relevant data from the cfg cmd
+            lossy_xport <= cfg_lossy_xport;
+            cached_dst_epid <= cfg_dst_epid;
+            headroom_bytes <= cfg_fc_headroom_bytes;
+            headroom_pkts <= cfg_fc_headroom_pkts;
+          end
+          // Wait for current packet to transfer then begin the
+          // configuration process or stream command
+          if (cfg_start || cfg_pending || fc_resync_req) begin
+            if (mid_pkt) begin
+              if (chdr_out_tvalid && chdr_out_tready && chdr_out_tlast)
+                state <= ST_STRC_HDR;
+            end else begin
+              if (!(chdr_out_tvalid && chdr_out_tready))
+                state <= ST_STRC_HDR;
+            end
+          end
+        end
+
+        // ST_STRC_HDR
+        // ------------------
+        // Send the CHDR header for a stream command
+        ST_STRC_HDR: begin
+          if (chdr_out_tvalid && chdr_out_tready) begin
+            state <= ST_STRC_W0;
+            // Update seqnum for the next packet
+            strc_seq_num <= strc_seq_num + 16'd1;
+          end
+          // Update byte count for stream command
+          strc_cnt_bytes <= send_cnt_bytes;
+        end
+
+        // ST_STRC_W0
+        // ------------------
+        // Send the first line of a stream command
+        ST_STRC_W0: begin
+          if (chdr_out_tvalid && chdr_out_tready)
+            if (CHDR_W < 128)
+              state <= ST_STRC_W1;
+            else
+              state <= ST_STRC_WAIT;
+        end
+
+        // ST_STRC_W1
+        // ------------------
+        // Send the second line of a stream command
+        ST_STRC_W1: begin
+          if (chdr_out_tvalid && chdr_out_tready)
+            state <= fc_resync_req ? ST_PASS_DATA : ST_STRC_WAIT;
+        end
+
+        // ST_STRC_WAIT
+        // ------------------
+        // Done sending stream command. Wait for a response
+        ST_STRC_WAIT: begin
+          // Wait for a new response to arrive
+          if (msg_o_tvalid) begin
+            if (msg_o_tdata == CHDR_STRS_STATUS_OKAY) begin
+              state <= ST_INIT_DLY;
+              cfg_delay <= 3'd4;
+              fc_enabled <= 1'b1;
+              data_seq_num <= 16'd0;
+              strc_seq_num <= 16'd0;
+            end else begin
+              state <= ST_PASS_DATA;
+              cfg_failed <= 1'b1;
+              cfg_pending <= 1'b0;
+            end
+          end
+        end
+
+        // ST_INIT_DLY
+        // ------------------
+        // Delay matching state for ok_shreg
+        ST_INIT_DLY: begin
+          if (cfg_delay == 3'd0) begin
+            state <= ST_PASS_DATA;
+            cfg_pending <= 1'b0;
+          end else begin
+            cfg_delay <= cfg_delay - 3'd1;
+          end
+        end
+
+        // We should never get here
+        default: begin
+          state <= ST_PASS_DATA;
+        end
+      endcase
+    end
+  end
+
+  // Header for output CHDR data
+  wire [CHDR_W-1:0] data_header;
+  assign data_header[63:0] = chdr_set_seq_num(
+    chdr_set_dst_epid(s_axis_data_tdata[63:0], cached_dst_epid),
+    data_seq_num);
+  generate if (CHDR_W > 64)
+    assign data_header[CHDR_W-1:64] = s_axis_data_tdata[CHDR_W-1:64];
+  endgenerate
+
+  // Header for stream command
+  wire [CHDR_W-1:0] strc_header;
+  assign strc_header[63:0] = chdr_build_header(
+    /*VC*/ 6'd0, /*eob*/ 1'b0, /*eov*/ 1'b0, CHDR_PKT_TYPE_STRC, CHDR_NO_MDATA,
+    strc_seq_num, 16'd16+(CHDR_W/8), cached_dst_epid);
+  generate if (CHDR_W > 64)
+    assign strc_header[CHDR_W-1:64] = {(CHDR_W-64){1'b0}};
+  endgenerate
+
+  // Payload for stream command
+  wire [127:0] strc_init_payload = chdr128_strc_build(
+    {24'h0, cfg_fc_freq_bytes}, {16'h0, cfg_fc_freq_pkts},
+    /*op_data*/ 4'h0, CHDR_STRC_OPCODE_INIT, cfg_this_epid);
+  wire [127:0] strc_resync_payload = chdr128_strc_build(
+    strc_cnt_bytes, send_cnt_pkts,
+    /*op_data*/ 4'h0, CHDR_STRC_OPCODE_RESYNC, cfg_this_epid);
+  wire [127:0] strc_payload = fc_resync_req ? strc_resync_payload : strc_init_payload;
+
+  always @(*) begin
+    case (state)
+      ST_PASS_DATA: begin
+        chdr_out_tdata  = mid_pkt ? s_axis_data_tdata : data_header;
+        chdr_out_tlast  = s_axis_data_tlast;
+        chdr_out_tvalid = s_axis_data_tvalid && ok_to_send;
+      end
+      ST_STRC_HDR: begin
+        chdr_out_tdata  = strc_header;
+        chdr_out_tlast  = 1'b0;
+        chdr_out_tvalid = ok_to_send;
+      end
+      ST_STRC_W0: begin
+        chdr_out_tdata  = strc_payload;
+        chdr_out_tlast  = (CHDR_W < 128) ? 1'b0 : 1'b1;
+        chdr_out_tvalid = ok_to_send;
+      end
+      ST_STRC_W1: begin
+        // We will enter this state only if CHDR_W = 64
+        chdr_out_tdata  = strc_payload[127:64];
+        chdr_out_tlast  = 1'b1;
+        chdr_out_tvalid = ok_to_send;
+      end
+      default: begin
+        chdr_out_tdata  = {CHDR_W{1'b0}};
+        chdr_out_tlast  = 1'b0;
+        chdr_out_tvalid = 1'b0;
+      end
+    endcase
+  end
+  assign s_axis_data_tready = (state == ST_PASS_DATA) && chdr_out_tready && ok_to_send;
+
+  // Consume all messages when passing data forward. The flow control state is automatically
+  // updated outside the message FIFO. When a stream command is issued, we wait for the
+  // "wait" state to consume responses.
+  assign msg_o_tready = msg_o_tvalid && (state == ST_PASS_DATA || state == ST_STRC_WAIT);
+
+  // Acknowledge a flow control resync command
+  assign fc_resync_ack = fc_resync_req && (state == ST_STRC_W1) && 
+                         chdr_out_tvalid && chdr_out_tready && chdr_out_tlast;
+
+  // ---------------------------------------------------
+  //  Stream Status Reporting
+  // ---------------------------------------------------
+
+  wire runtime_err_stb = msg_o_tvalid && msg_o_tready && (state == ST_PASS_DATA);
+  assign seq_err_stb = runtime_err_stb && (msg_o_tdata == CHDR_STRS_STATUS_SEQERR);
+  assign data_err_stb = runtime_err_stb && (msg_o_tdata == CHDR_STRS_STATUS_DATAERR);
+  assign route_err_stb = runtime_err_stb && (msg_o_tdata == CHDR_STRS_STATUS_RTERR);
+
+  always @(posedge clk) begin
+    if (rst || !fc_enabled) begin
+      seq_err_cnt <= 32'd0;
+      data_err_cnt <= 32'd0;
+      route_err_cnt <= 32'd0;
+    end else begin
+      if (seq_err_stb)
+        seq_err_cnt <= seq_err_cnt + 32'd1;
+      if (data_err_stb)
+        data_err_cnt <= data_err_cnt + 32'd1;
+      if (route_err_stb)
+        route_err_cnt <= route_err_cnt + 32'd1;
+    end
+  end
+
+endmodule // chdr_stream_output
diff --git a/fpga/usrp3/lib/rfnoc/core/chdr_to_axis_ctrl.v b/fpga/usrp3/lib/rfnoc/core/chdr_to_axis_ctrl.v
new file mode 100644
index 000000000..1f9dba2eb
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/core/chdr_to_axis_ctrl.v
@@ -0,0 +1,319 @@
+//
+// Copyright 2018 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: chdr_to_axis_ctrl
+// Description:
+//  Converts from CHDR to AXIS-Control and vice versa.
+//  This module has to handle remote control transactions
+//  correctly. The CHDR frame has/needs the DstEPID, DstPort
+//  SrcEPID and SrcPort and the AXIS-Ctrl frame has/needs
+//  the DstPort, SrcPort, RemDstEPID and RemDstPort.
+//
+// Parameters:
+//   - CHDR_W: Width of the CHDR bus in bits
+//   - THIS_PORTID: The port number of the control xbar
+//                  that this module is connected to.
+//
+// Signals:
+//   - s_rfnoc_chdr_* : Input CHDR stream (AXI-Stream)
+//   - m_rfnoc_chdr_* : Output CHDR stream (AXI-Stream)
+//   - s_rfnoc_ctrl_* : Input control stream (AXI-Stream)
+//   - m_rfnoc_ctrl_* : Output control stream (AXI-Stream)
+
+module chdr_to_axis_ctrl #(
+  parameter       CHDR_W      = 256,
+  parameter [9:0] THIS_PORTID = 10'd0
+)(
+  // CHDR Bus (master and slave)
+  input  wire              rfnoc_chdr_clk,
+  input  wire              rfnoc_chdr_rst,
+  input  wire [15:0]       this_epid,
+  input  wire [CHDR_W-1:0] s_rfnoc_chdr_tdata,
+  input  wire              s_rfnoc_chdr_tlast,
+  input  wire              s_rfnoc_chdr_tvalid,
+  output wire              s_rfnoc_chdr_tready,
+  output wire [CHDR_W-1:0] m_rfnoc_chdr_tdata,
+  output wire              m_rfnoc_chdr_tlast,
+  output wire              m_rfnoc_chdr_tvalid,
+  input  wire              m_rfnoc_chdr_tready,
+  // AXIS-Control Bus (master and slave)
+  input  wire              rfnoc_ctrl_clk,
+  input  wire              rfnoc_ctrl_rst,
+  input  wire [31:0]       s_rfnoc_ctrl_tdata,
+  input  wire              s_rfnoc_ctrl_tlast,
+  input  wire              s_rfnoc_ctrl_tvalid,
+  output wire              s_rfnoc_ctrl_tready,
+  output wire [31:0]       m_rfnoc_ctrl_tdata,
+  output wire              m_rfnoc_ctrl_tlast,
+  output wire              m_rfnoc_ctrl_tvalid,
+  input  wire              m_rfnoc_ctrl_tready
+);
+
+  // ---------------------------------------------------
+  //  RFNoC Includes
+  // ---------------------------------------------------
+  `include "rfnoc_chdr_utils.vh"
+  `include "rfnoc_axis_ctrl_utils.vh"
+
+  localparam [1:0] ST_CHDR_HDR   = 2'd0;  // Processing the CHDR header
+  localparam [1:0] ST_CHDR_MDATA = 2'd1;  // Processing the CHDR metadata
+  localparam [1:0] ST_CTRL_HDR   = 2'd2;  // Processing the CHDR control header
+  localparam [1:0] ST_CTRL_BODY  = 2'd3;  // Processing the CHDR control body
+
+  // ---------------------------------------------------
+  //  Input/output register slices
+  // ---------------------------------------------------
+  // - ch2ct: CHDR to Ctrl
+  // - ct2ch: Ctrl to CHDR
+
+  wire [CHDR_W-1:0] ch2ct_tdata,  ct2ch_tdata;
+  wire              ch2ct_tlast,  ct2ch_tlast;
+  wire              ch2ct_tvalid, ct2ch_tvalid;
+  wire              ch2ct_tready, ct2ch_tready;
+
+  axi_fifo #(.WIDTH(CHDR_W+1), .SIZE(1)) ch2ct_reg_i (
+    .clk(rfnoc_chdr_clk), .reset(rfnoc_chdr_rst), .clear(1'b0),
+    .i_tdata({s_rfnoc_chdr_tlast, s_rfnoc_chdr_tdata}),
+    .i_tvalid(s_rfnoc_chdr_tvalid), .i_tready(s_rfnoc_chdr_tready),
+    .o_tdata({ch2ct_tlast, ch2ct_tdata}),
+    .o_tvalid(ch2ct_tvalid), .o_tready(ch2ct_tready),
+    .space(), .occupied()
+  );
+
+  axi_fifo #(.WIDTH(CHDR_W+1), .SIZE(1)) ct2ch_reg_i (
+    .clk(rfnoc_chdr_clk), .reset(rfnoc_chdr_rst), .clear(1'b0),
+    .i_tdata({ct2ch_tlast, ct2ch_tdata}),
+    .i_tvalid(ct2ch_tvalid), .i_tready(ct2ch_tready),
+    .o_tdata({m_rfnoc_chdr_tlast, m_rfnoc_chdr_tdata}),
+    .o_tvalid(m_rfnoc_chdr_tvalid), .o_tready(m_rfnoc_chdr_tready),
+    .space(), .occupied()
+  );
+
+  // ---------------------------------------------------
+  //  CH2CT: CHDR => Ctrl path
+  // ---------------------------------------------------
+  // When converting CHDR => Ctrl we know we are dealing with
+  // a remote control transaction so we need to perform
+  // the following transformations to ensure that the packet
+  // has all the info to route downstream and has enough info
+  // to return to the master (of the transaction).
+  // - Use the CHDR DstPort as the Ctrl DstPort (forward the master's request)
+  // - Use THIS_PORTID as the Ctrl SrcPort (for the return path back here)
+  // - Use the CHDR SrcEPID as the Ctrl RemDstEPID (return path for CHDR packet)
+  // - Use the CHDR SrcPort as the Ctrl RemDstPort (return path in the downstream EP)
+  // - Ignore the CHDR DstEPID because packet is already here
+
+  reg [1:0]   ch2ct_state = ST_CHDR_HDR;
+  reg [4:0]   ch2ct_nmdata = CHDR_NO_MDATA;
+
+  always @(posedge rfnoc_chdr_clk) begin
+    if (rfnoc_chdr_rst) begin
+      ch2ct_state <= ST_CHDR_HDR;
+    end else if (ch2ct_tvalid && ch2ct_tready) begin
+      case (ch2ct_state)
+        ST_CHDR_HDR: begin
+          ch2ct_nmdata <= chdr_get_num_mdata(ch2ct_tdata[63:0]) - 5'd1;
+          if (!ch2ct_tlast)
+            ch2ct_state <= (chdr_get_num_mdata(ch2ct_tdata[63:0]) == 5'd0) ? 
+              ST_CTRL_HDR : ST_CHDR_MDATA;
+          else
+            ch2ct_state <= ST_CHDR_HDR;  // Premature termination
+        end
+        ST_CHDR_MDATA: begin
+          ch2ct_nmdata <= ch2ct_nmdata - 5'd1;
+          if (!ch2ct_tlast)
+            ch2ct_state <= (ch2ct_nmdata == CHDR_NO_MDATA) ? ST_CTRL_HDR : ST_CHDR_MDATA;
+          else
+            ch2ct_state <= ST_CHDR_HDR;  // Premature termination
+        end
+        ST_CTRL_HDR: begin
+          ch2ct_state <= ch2ct_tlast ? ST_CHDR_HDR : ST_CTRL_BODY;
+        end
+        ST_CTRL_BODY: begin
+          if (ch2ct_tlast)
+            ch2ct_state <= ST_CHDR_HDR;
+        end
+        default: begin
+          // We should never get here
+          ch2ct_state <= ST_CHDR_HDR;
+        end
+      endcase
+    end
+  end
+
+  wire [(CHDR_W/32)-1:0] ch2ct_tkeep;
+  chdr_compute_tkeep #(.CHDR_W(CHDR_W), .ITEM_W(32)) chdr_tkeep_gen_i (
+    .clk(rfnoc_chdr_clk), .rst(rfnoc_chdr_rst),
+    .axis_tdata(ch2ct_tdata), .axis_tlast(ch2ct_tlast),
+    .axis_tvalid(ch2ct_tvalid), .axis_tready(ch2ct_tready),
+    .axis_tkeep(ch2ct_tkeep)
+  );
+
+  // Create the first two lines of the Ctrl word (wide)
+  // using data from CHDR packet 
+  wire [CHDR_W-1:0] ch2ct_new_ctrl_hdr;
+  assign ch2ct_new_ctrl_hdr[63:0] = {
+    axis_ctrl_build_hdr_hi(
+      axis_ctrl_get_src_port(ch2ct_tdata[31:0]),
+      axis_ctrl_get_rem_dst_epid(ch2ct_tdata[63:32])
+    ),
+    axis_ctrl_build_hdr_lo(
+      axis_ctrl_get_is_ack  (ch2ct_tdata[31:0]),
+      axis_ctrl_get_has_time(ch2ct_tdata[31:0]),
+      axis_ctrl_get_seq_num (ch2ct_tdata[31:0]),
+      axis_ctrl_get_num_data(ch2ct_tdata[31:0]),
+      THIS_PORTID,
+      axis_ctrl_get_dst_port(ch2ct_tdata[31:0])
+    )
+  };
+  generate if (CHDR_W > 64) begin
+    assign ch2ct_new_ctrl_hdr[CHDR_W-1:64] = ch2ct_tdata[CHDR_W-1:64];
+  end endgenerate
+
+  wire [CHDR_W-1:0] ch2ct_wctrl_tdata = 
+    (ch2ct_state == ST_CTRL_HDR) ? ch2ct_new_ctrl_hdr : ch2ct_tdata;
+
+  axis_width_conv #(
+    .WORD_W(32), .IN_WORDS(CHDR_W/32), .OUT_WORDS(1),
+    .SYNC_CLKS(0), .PIPELINE("OUT")
+  ) ctrl_downsizer_i (
+    .s_axis_aclk(rfnoc_chdr_clk), .s_axis_rst(rfnoc_chdr_rst),
+    .s_axis_tdata(ch2ct_wctrl_tdata),
+    .s_axis_tkeep(ch2ct_tkeep),
+    .s_axis_tlast(ch2ct_tlast),
+    .s_axis_tvalid(ch2ct_tvalid && (ch2ct_state == ST_CTRL_HDR || ch2ct_state == ST_CTRL_BODY)),
+    .s_axis_tready(ch2ct_tready),
+    .m_axis_aclk(rfnoc_ctrl_clk), .m_axis_rst(rfnoc_ctrl_rst),
+    .m_axis_tdata(m_rfnoc_ctrl_tdata),
+    .m_axis_tkeep(/* Unused: OUT_WORDS=1 */),
+    .m_axis_tlast(m_rfnoc_ctrl_tlast),
+    .m_axis_tvalid(m_rfnoc_ctrl_tvalid),
+    .m_axis_tready(m_rfnoc_ctrl_tready)
+  );
+
+  // ---------------------------------------------------
+  //  CT2CH: Ctrl => CHDR path
+  // ---------------------------------------------------
+  // When converting Ctrl => CHDR we know we are dealing with
+  // a remote control transaction so we need to perform
+  // the following transformations to ensure that the packet
+  // has all the info to route downstream and has enough info
+  // to return to the initiator of the transaction.
+  // - Use the Ctrl RemDstEPID as the CHDR DstEPID (forward the master's request)
+  // - Use the Ctrl RemDstPort as the CHDR DstPort (forward the master's request)
+  // - Use the this_epid as CHDR SrcEPID (return path for the CHDR packet)
+  // - Use the Ctrl SrcPort as the CHDR SrcPort (return path to the master)
+  // - Ignore the Ctrl DstPort because the packet has already been routed 
+
+  wire [CHDR_W-1:0] ct2ch_wctrl_tdata;
+  wire              ct2ch_wctrl_tlast, ct2ch_wctrl_tvalid, ct2ch_wctrl_tready;
+
+  axis_width_conv #(
+    .WORD_W(32), .IN_WORDS(1), .OUT_WORDS(CHDR_W/32),
+    .SYNC_CLKS(0), .PIPELINE("IN")
+  ) ctrl_upsizer_i (
+    .s_axis_aclk(rfnoc_ctrl_clk), .s_axis_rst(rfnoc_ctrl_rst),
+    .s_axis_tdata(s_rfnoc_ctrl_tdata),
+    .s_axis_tkeep(/* Unused: IN_WORDS=1 */),
+    .s_axis_tlast(s_rfnoc_ctrl_tlast),
+    .s_axis_tvalid(s_rfnoc_ctrl_tvalid),
+    .s_axis_tready(s_rfnoc_ctrl_tready),
+    .m_axis_aclk(rfnoc_chdr_clk), .m_axis_rst(rfnoc_chdr_rst),
+    .m_axis_tdata(ct2ch_wctrl_tdata),
+    .m_axis_tkeep(/* Unused: We are updating the CHDR length */),
+    .m_axis_tlast(ct2ch_wctrl_tlast),
+    .m_axis_tvalid(ct2ch_wctrl_tvalid),
+    .m_axis_tready(ct2ch_wctrl_tready)
+  );
+
+  reg [1:0] ct2ch_state = ST_CHDR_HDR;
+  reg [15:0] ct2ch_seqnum = 16'd0;
+
+  always @(posedge rfnoc_chdr_clk) begin
+    if (rfnoc_chdr_rst) begin
+      ct2ch_state <= ST_CHDR_HDR;
+      ct2ch_seqnum <= 16'd0;
+    end else if (ct2ch_tvalid && ct2ch_tready) begin
+      case (ct2ch_state)
+        ST_CHDR_HDR: begin
+          if (!ct2ch_tlast)
+            ct2ch_state <= ST_CTRL_HDR;
+        end
+        ST_CTRL_HDR: begin
+          if (ct2ch_tlast)
+            ct2ch_state <= ST_CHDR_HDR;
+          else
+            ct2ch_state <= ST_CTRL_BODY;
+        end
+        ST_CTRL_BODY: begin
+          if (ct2ch_tlast)
+            ct2ch_state <= ST_CHDR_HDR;
+        end
+        default: begin
+          // We should never get here
+          ct2ch_state <= ST_CHDR_HDR;
+        end
+      endcase
+      if (ct2ch_tlast)
+        ct2ch_seqnum <= ct2ch_seqnum + 16'd1;
+    end
+  end
+
+  // Hold the first line to generate info for the outgoing CHDR header
+  assign ct2ch_wctrl_tready = (ct2ch_state == ST_CTRL_HDR || ct2ch_state == ST_CTRL_BODY) ? ct2ch_tready : 1'b0;
+
+  wire [7:0] ct2ch_32bit_lines = 8'd3 +                               // Header + OpWord
+    (axis_ctrl_get_has_time(ct2ch_wctrl_tdata[31:0]) ? 8'd2 : 8'd0) + // Timestamp
+    ({4'h0, axis_ctrl_get_num_data(ct2ch_wctrl_tdata[31:0])});        // Data words
+
+  wire [15:0] ct2ch_chdr_lines = 16'd1 +            // CHDR header
+    ct2ch_32bit_lines[7:$clog2(CHDR_W/32)] +        // Convert 32-bit lines to CHDR_W
+    (|ct2ch_32bit_lines[$clog2(CHDR_W/32)-1:0]);    // Residue
+
+  reg [63:0] ct2ch_chdr_tdata;
+  always @(*) begin
+    case (ct2ch_state)
+      ST_CHDR_HDR: begin
+        ct2ch_chdr_tdata = chdr_build_header(
+          6'd0, /* VC */
+          1'b0, 1'b0, /* eob, eov */
+          CHDR_PKT_TYPE_CTRL,
+          CHDR_NO_MDATA,
+          ct2ch_seqnum,
+          (ct2ch_chdr_lines << $clog2(CHDR_W/8)), /* length in bytes */
+          axis_ctrl_get_rem_dst_epid(ct2ch_wctrl_tdata[63:32])
+        );
+      end
+      ST_CTRL_HDR: begin
+        ct2ch_chdr_tdata = {
+          axis_ctrl_build_hdr_hi(
+            10'd0,        /* Unused in CHDR Control payload */
+            this_epid     /* This is the SrcEPID */
+          ),
+          axis_ctrl_build_hdr_lo(
+            axis_ctrl_get_is_ack  (ct2ch_wctrl_tdata[31:0]),
+            axis_ctrl_get_has_time(ct2ch_wctrl_tdata[31:0]),
+            axis_ctrl_get_seq_num (ct2ch_wctrl_tdata[31:0]),
+            axis_ctrl_get_num_data(ct2ch_wctrl_tdata[31:0]),
+            axis_ctrl_get_src_port(ct2ch_wctrl_tdata[31:0]),
+            axis_ctrl_get_rem_dst_port(ct2ch_wctrl_tdata[63:32])
+          )
+        };
+      end
+      default: begin
+        ct2ch_chdr_tdata = ct2ch_wctrl_tdata[63:0];
+      end
+    endcase
+  end
+
+  // Output signals
+  assign ct2ch_tdata[63:0] = ct2ch_chdr_tdata;
+  assign ct2ch_tlast       = ct2ch_wctrl_tlast;
+  assign ct2ch_tvalid      = ct2ch_wctrl_tvalid;
+  generate if (CHDR_W > 64) begin
+    assign ct2ch_tdata[CHDR_W-1:64] = ct2ch_wctrl_tdata[CHDR_W-1:64];
+  end endgenerate
+
+endmodule // chdr_to_axis_ctrl
diff --git a/fpga/usrp3/lib/rfnoc/core/chdr_to_axis_data.v b/fpga/usrp3/lib/rfnoc/core/chdr_to_axis_data.v
new file mode 100644
index 000000000..a00a9952c
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/core/chdr_to_axis_data.v
@@ -0,0 +1,422 @@
+//
+// Copyright 2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: chdr_to_axis_data
+//
+// Description:
+//
+//   A deframer module for CHDR data packets. It accepts an input CHDR stream 
+//   and produces an output data stream that includes the payload of the 
+//   packet, as well as timestamp and packet flags presented as sideband 
+//   information.
+//
+//   This module also performs an optional clock crossing and data width 
+//   conversion from CHDR_W to a user requested width for the payload data bus.
+//
+// Parameters:
+//   - CHDR_W         : Width of the input CHDR bus in bits
+//   - ITEM_W         : Width of the output item bus in bits
+//   - NIPC           : The number of output items delivered per cycle
+//   - SYNC_CLKS      : Are the CHDR and data clocks synchronous to each other?
+//   - INFO_FIFO_SIZE : Log2 of the FIFO size for the packet info data path
+//   - PYLD_FIFO_SIZE : Log2 of the FIFO size for the payload data path
+//
+// Signals:
+//   - s_axis_chdr_*  : Input CHDR stream (AXI-Stream)
+//   - m_axis_*       : Output payload data stream (AXI-Stream)
+//   - m_axis_mdata_* : Output mdata stream (AXI-Stream)
+//   - flush_*        : Signals for flush control and status
+//
+
+module chdr_to_axis_data #(
+  parameter CHDR_W         = 256,
+  parameter ITEM_W         = 32,
+  parameter NIPC           = 2,
+  parameter SYNC_CLKS      = 0,
+  parameter INFO_FIFO_SIZE = 5,
+  parameter PYLD_FIFO_SIZE = 5
+)(
+  // Clock, reset and settings
+  input  wire                     axis_chdr_clk,
+  input  wire                     axis_chdr_rst,
+  input  wire                     axis_data_clk,
+  input  wire                     axis_data_rst,
+  // CHDR in (AXI-Stream)
+  input  wire [CHDR_W-1:0]        s_axis_chdr_tdata,
+  input  wire                     s_axis_chdr_tlast,
+  input  wire                     s_axis_chdr_tvalid,
+  output wire                     s_axis_chdr_tready,
+  // Payload data stream out (AXI-Stream)
+  output wire [(ITEM_W*NIPC)-1:0] m_axis_tdata,
+  output wire [NIPC-1:0]          m_axis_tkeep,
+  output wire                     m_axis_tlast,
+  output wire                     m_axis_tvalid,
+  input  wire                     m_axis_tready,
+  // Payload sideband information
+  output wire [63:0]              m_axis_ttimestamp,
+  output wire                     m_axis_thas_time,
+  output wire [15:0]              m_axis_tlength,
+  output wire                     m_axis_teob,
+  output wire                     m_axis_teov,
+  // Flush signals
+  input  wire                     flush_en,
+  input  wire [31:0]              flush_timeout,
+  output wire                     flush_active,
+  output wire                     flush_done
+);
+
+  // ---------------------------------------------------
+  //  RFNoC Includes
+  // ---------------------------------------------------
+  `include "rfnoc_chdr_utils.vh"
+  `include "rfnoc_axis_ctrl_utils.vh"
+
+  // ---------------------------------------------------
+  //  Pipeline
+  // ---------------------------------------------------
+  localparam CHDR_KEEP_W = CHDR_W/ITEM_W;
+
+  wire [CHDR_W-1:0]       in_chdr_tdata;
+  wire [CHDR_KEEP_W-1:0]  in_chdr_tkeep;
+  wire                    in_chdr_tlast, in_chdr_tvalid;
+  reg                     in_chdr_tready;
+
+  axi_fifo_flop2 #(.WIDTH(CHDR_W+1)) in_pipe_i (
+    .clk(axis_chdr_clk), .reset(axis_chdr_rst), .clear(1'b0),
+    .i_tdata({s_axis_chdr_tlast, s_axis_chdr_tdata}),
+    .i_tvalid(s_axis_chdr_tvalid), .i_tready(s_axis_chdr_tready),
+    .o_tdata({in_chdr_tlast, in_chdr_tdata}),
+    .o_tvalid(in_chdr_tvalid), .o_tready(in_chdr_tready),
+    .space(), .occupied()
+  );
+
+  chdr_compute_tkeep #(.CHDR_W(CHDR_W), .ITEM_W(ITEM_W)) tkeep_gen_i (
+    .clk(axis_chdr_clk), .rst(axis_chdr_rst),
+    .axis_tdata(in_chdr_tdata), .axis_tlast(in_chdr_tlast),
+    .axis_tvalid(in_chdr_tvalid), .axis_tready(in_chdr_tready),
+    .axis_tkeep(in_chdr_tkeep)
+  );
+
+  // ---------------------------------------------------
+  //  Input State Machine
+  // ---------------------------------------------------
+  localparam INFO_W = 64+1+16+1+1;   // timestamp, has_time, length, eob, eov
+
+  wire [CHDR_W-1:0]       in_pyld_tdata;
+  wire [CHDR_KEEP_W-1:0]  in_pyld_tkeep;
+  wire                    in_pyld_tlast, in_pyld_tvalid, in_pyld_tready;
+
+  reg [INFO_W-1:0] in_info_tdata;
+  reg              in_info_tvalid;
+  wire             in_info_tready;
+
+  localparam [2:0] ST_HDR   = 3'd0;   // Processing the input CHDR header
+  localparam [2:0] ST_TS    = 3'd1;   // Processing the input CHDR timestamp
+  localparam [2:0] ST_MDATA = 3'd2;   // Processing the input CHDR metadata word
+  localparam [2:0] ST_BODY  = 3'd3;   // Processing the input CHDR payload word
+  localparam [2:0] ST_DROP  = 3'd4;   // Something went wrong... Dropping packet
+
+  reg [2:0] state = ST_HDR;
+  reg [4:0] mdata_pending = CHDR_NO_MDATA;
+
+  reg [15:0] chdr_length_reg;
+  reg        chdr_eob_reg, chdr_eov_reg;
+
+  // Shortcuts: CHDR header
+  wire [2:0] in_pkt_type = chdr_get_pkt_type(in_chdr_tdata[63:0]);
+  wire [4:0] in_num_mdata = chdr_get_num_mdata(in_chdr_tdata[63:0]);
+
+  always @(posedge axis_chdr_clk) begin
+    if (axis_chdr_rst) begin
+      state <= ST_HDR;
+    end else if (in_chdr_tvalid & in_chdr_tready) begin
+      case (state)
+
+        // ST_HDR: CHDR Header
+        // -------------------
+        ST_HDR: begin
+          // Always cache the number of metadata words
+          mdata_pending <= in_num_mdata;
+          // Figure out the next state
+          if (!in_chdr_tlast) begin
+            if (CHDR_W > 64) begin
+              // When CHDR_W > 64, the timestamp is a part of the header word.
+              // If this is a data packet (with/without a TS), we move on to the metadata/body
+              // state otherwise we drop it. Non-data packets should never reach here.
+              if (in_pkt_type == CHDR_PKT_TYPE_DATA || in_pkt_type == CHDR_PKT_TYPE_DATA_TS) begin
+                if (in_num_mdata != CHDR_NO_MDATA) begin
+                  state <= ST_MDATA;
+                end else begin
+                  state <= ST_BODY;
+                end
+              end else begin
+                state <= ST_DROP;
+              end
+            end else begin
+              // When CHDR_W == 64, the timestamp comes after the header. Check if this is a data
+              // packet with a TS to figure out the next state. If no TS, then check for metadata
+              // to move to the next state. Drop any non-data packets.
+              chdr_length_reg <= chdr_calc_payload_length(CHDR_W, in_chdr_tdata);
+              chdr_eob_reg    <= chdr_get_eob(in_chdr_tdata);
+              chdr_eov_reg    <= chdr_get_eov(in_chdr_tdata);
+              if (in_pkt_type == CHDR_PKT_TYPE_DATA_TS) begin
+                state <= ST_TS;
+              end else if (in_pkt_type == CHDR_PKT_TYPE_DATA) begin
+                if (in_num_mdata != CHDR_NO_MDATA) begin
+                  state <= ST_MDATA;
+                end else begin
+                  state <= ST_BODY;
+                end
+              end else begin
+                state <= ST_DROP;
+              end
+            end
+          end else begin    // Premature termination
+            // Packets must have at least one payload line
+            state <= ST_HDR;
+          end
+        end
+
+        // ST_TS: Timestamp (CHDR_W == 64 only)
+        // ------------------------------------
+        ST_TS: begin
+          if (!in_chdr_tlast) begin
+            if (mdata_pending != CHDR_NO_MDATA) begin
+              state <= ST_MDATA;
+            end else begin
+              state <= ST_BODY;
+            end
+          end else begin    // Premature termination
+            // Packets must have at least one payload line
+            state <= ST_HDR;
+          end
+        end
+
+        // ST_MDATA: Metadata word
+        // -----------------------
+        ST_MDATA: begin
+          if (!in_chdr_tlast) begin
+            // Count down metadata and stop at 1
+            if (mdata_pending == 5'd1) begin
+              state <= ST_BODY;
+            end else begin
+              mdata_pending <= mdata_pending - 5'd1;
+            end
+          end else begin    // Premature termination
+            // Packets must have at least one payload line
+            state <= ST_HDR;
+          end
+        end
+
+        // ST_BODY: Payload word
+        // ---------------------
+        ST_BODY: begin
+          if (in_chdr_tlast) begin
+            state <= ST_HDR;
+          end
+        end
+
+        // ST_DROP: Drop current packet
+        // ----------------------------
+        ST_DROP: begin
+          if (in_chdr_tlast) begin
+            state <= ST_HDR;
+          end
+        end
+
+        default: begin
+          // We should never get here
+          state <= ST_HDR;
+        end
+      endcase
+    end
+  end
+
+  // CHDR data goes to the payload stream only in the BODY state. Packets are
+  // expected to have at least one payload word so the CHDR tlast can be used
+  // as the payload tlast.
+  assign in_pyld_tdata  = in_chdr_tdata;
+  assign in_pyld_tkeep  = in_chdr_tkeep;
+  assign in_pyld_tlast  = in_chdr_tlast;
+  assign in_pyld_tvalid = in_chdr_tvalid && (state == ST_BODY);
+
+  always @(*) begin
+    // Packet timestamp and flags go into the info FIFO, but only if it's a 
+    // data packet since non-data packets will be discarded.
+    if (CHDR_W > 64) begin
+      // When CHDR_W > 64, all info will be in the first word of the CHDR packet
+      in_info_tdata =  { in_chdr_tdata[127:64], 
+                         chdr_get_has_time(in_chdr_tdata),
+                         chdr_calc_payload_length(CHDR_W, in_chdr_tdata),
+                         chdr_get_eob(in_chdr_tdata),
+                         chdr_get_eov(in_chdr_tdata) };
+      in_info_tvalid = in_chdr_tvalid && (state == ST_HDR && 
+        (in_pkt_type == CHDR_PKT_TYPE_DATA || in_pkt_type == CHDR_PKT_TYPE_DATA_TS));
+    end else begin
+      // When CHDR_W == 64, the flags will be in the first word of the packet, 
+      // but the timestamp will be in the second word, if there is a timestamp.
+      if (state == ST_HDR && in_pkt_type == CHDR_PKT_TYPE_DATA) begin
+        // No timestamp in this case
+        in_info_tdata  = { in_chdr_tdata[63:0], 1'b0, 
+                           chdr_calc_payload_length(CHDR_W, in_chdr_tdata),
+                           chdr_get_eob(in_chdr_tdata), chdr_get_eov(in_chdr_tdata) };
+        in_info_tvalid = in_chdr_tvalid;
+      end else begin
+        // Assuming timestamp is present, so use flags from previous clock cycle
+        in_info_tdata  = { in_chdr_tdata[63:0], 1'b1, chdr_length_reg,
+                           chdr_eob_reg, chdr_eov_reg };
+        in_info_tvalid = in_chdr_tvalid && (state == ST_TS);
+      end
+    end
+
+    case (state)
+      ST_HDR   : in_chdr_tready = in_info_tready;
+      ST_TS    : in_chdr_tready = in_info_tready;
+      ST_MDATA : in_chdr_tready = 1'b1;
+      ST_BODY  : in_chdr_tready = in_pyld_tready;
+      ST_DROP  : in_chdr_tready = 1'b1;
+      default  : in_chdr_tready = 1'b0;
+    endcase
+  end
+
+  // ---------------------------------------------------
+  //  Payload and mdata FIFOs
+  // ---------------------------------------------------
+  wire [CHDR_W-1:0]       out_pyld_tdata;
+  wire [CHDR_KEEP_W-1:0]  out_pyld_tkeep;
+  wire                    out_pyld_tlast, out_pyld_tvalid, out_pyld_tready;
+  
+  wire [INFO_W-1:0]       out_info_tdata;
+  wire                    out_info_tvalid, out_info_tready;
+
+  wire [(ITEM_W*NIPC)-1:0] conv_pyld_tdata;
+  wire [NIPC-1:0]          conv_pyld_tkeep;
+  wire                     conv_pyld_tlast, conv_pyld_tvalid, conv_pyld_tready;
+
+
+  generate if (SYNC_CLKS) begin : gen_sync_fifo
+    axi_fifo #(.WIDTH(INFO_W), .SIZE(INFO_FIFO_SIZE)) info_fifo_i (
+      .clk(axis_data_clk), .reset(axis_data_rst), .clear(1'b0),
+      .i_tdata(in_info_tdata),
+      .i_tvalid(in_info_tvalid), .i_tready(in_info_tready),
+      .o_tdata(out_info_tdata),
+      .o_tvalid(out_info_tvalid), .o_tready(out_info_tready),
+      .space(), .occupied()
+    );
+    axi_fifo #(.WIDTH(CHDR_W+CHDR_KEEP_W+1), .SIZE(PYLD_FIFO_SIZE)) pyld_fifo_i (
+      .clk(axis_data_clk), .reset(axis_data_rst), .clear(1'b0),
+      .i_tdata({in_pyld_tlast, in_pyld_tkeep, in_pyld_tdata}),
+      .i_tvalid(in_pyld_tvalid), .i_tready(in_pyld_tready),
+      .o_tdata({out_pyld_tlast, out_pyld_tkeep, out_pyld_tdata}),
+      .o_tvalid(out_pyld_tvalid), .o_tready(out_pyld_tready),
+      .space(), .occupied()
+    );
+  end else begin : gen_async_fifo
+    axi_fifo_2clk #(.WIDTH(INFO_W), .SIZE(INFO_FIFO_SIZE)) info_fifo_i (
+      .reset(axis_chdr_rst),
+      .i_aclk(axis_chdr_clk),
+      .i_tdata(in_info_tdata),
+      .i_tvalid(in_info_tvalid), .i_tready(in_info_tready),
+      .o_aclk(axis_data_clk),
+      .o_tdata(out_info_tdata),
+      .o_tvalid(out_info_tvalid), .o_tready(out_info_tready)
+    );
+    axi_fifo_2clk #(.WIDTH(CHDR_W+CHDR_KEEP_W+1), .SIZE(PYLD_FIFO_SIZE)) pyld_fifo_i (
+      .reset(axis_chdr_rst),
+      .i_aclk(axis_chdr_clk),
+      .i_tdata({in_pyld_tlast, in_pyld_tkeep, in_pyld_tdata}),
+      .i_tvalid(in_pyld_tvalid), .i_tready(in_pyld_tready),
+      .o_aclk(axis_data_clk),
+      .o_tdata({out_pyld_tlast, out_pyld_tkeep, out_pyld_tdata}),
+      .o_tvalid(out_pyld_tvalid), .o_tready(out_pyld_tready)
+    );
+  end endgenerate
+
+  // ---------------------------------------------------
+  //  Data Width Converter: CHDR_W => ITEM_W*NIPC
+  // ---------------------------------------------------
+  generate
+    if (CHDR_W != ITEM_W*NIPC) begin : gen_axis_width_conv
+      axis_width_conv #(
+        .WORD_W(ITEM_W), .IN_WORDS(CHDR_W/ITEM_W), .OUT_WORDS(NIPC),
+        .SYNC_CLKS(1), .PIPELINE("NONE")
+      ) payload_width_conv_i (
+        .s_axis_aclk(axis_data_clk), .s_axis_rst(axis_data_rst),
+        .s_axis_tdata(out_pyld_tdata), .s_axis_tkeep(out_pyld_tkeep),
+        .s_axis_tlast(out_pyld_tlast), .s_axis_tvalid(out_pyld_tvalid),
+        .s_axis_tready(out_pyld_tready),
+        .m_axis_aclk(axis_data_clk), .m_axis_rst(axis_data_rst),
+        .m_axis_tdata(conv_pyld_tdata), .m_axis_tkeep(conv_pyld_tkeep),
+        .m_axis_tlast(conv_pyld_tlast), .m_axis_tvalid(conv_pyld_tvalid),
+        .m_axis_tready(conv_pyld_tready)
+      );
+    end else begin : no_gen_axis_width_conv
+      assign conv_pyld_tdata  = out_pyld_tdata;
+      assign conv_pyld_tkeep  = out_pyld_tkeep;
+      assign conv_pyld_tlast  = out_pyld_tlast;
+      assign conv_pyld_tvalid = out_pyld_tvalid;
+      assign out_pyld_tready  = conv_pyld_tready;
+    end
+  endgenerate
+
+  // ---------------------------------------------------
+  //  Merge payload and info streams
+  // ---------------------------------------------------
+  // There should be one info word for each payload packet.
+  wire [INFO_W+(ITEM_W+1)*NIPC-1:0] flush_tdata;
+  wire                              flush_tlast;
+  wire                              flush_tvalid;
+  wire                              flush_tready;
+
+  assign flush_tdata      = { out_info_tdata, conv_pyld_tkeep, conv_pyld_tdata };
+  assign flush_tlast      = conv_pyld_tlast;
+  assign flush_tvalid     = conv_pyld_tvalid  && out_info_tvalid;
+  assign conv_pyld_tready = flush_tready      && out_info_tvalid;
+  assign out_info_tready  = conv_pyld_tready  && conv_pyld_tlast && conv_pyld_tvalid;
+
+  // ---------------------------------------------------
+  //  Flushing Logic
+  // ---------------------------------------------------
+  wire [31:0] flush_timeout_dclk;
+  wire        flush_en_dclk;
+  wire        flush_active_pyld_cclk;
+  wire        flush_done_pyld_cclk;
+  wire        flush_active_pyld;
+  wire        flush_done_pyld;
+
+  synchronizer #(.WIDTH(2), .INITIAL_VAL(4'd0)) flush_2clk_rb_i (
+    .clk(axis_chdr_clk), .rst(1'b0),
+    .in({flush_active_pyld, flush_done_pyld}),
+    .out({flush_active_pyld_cclk, flush_done_pyld_cclk})
+  );
+  assign flush_active = flush_active_pyld_cclk;
+  assign flush_done = flush_done_pyld_cclk;
+
+  axi_fifo_2clk #(.WIDTH(33), .SIZE(1)) flush_2clk_ctrl_i (
+    .reset(axis_chdr_rst),
+    .i_aclk(axis_chdr_clk),
+    .i_tdata({flush_en, flush_timeout}), .i_tvalid(1'b1), .i_tready(),
+    .o_aclk(axis_data_clk),
+    .o_tdata({flush_en_dclk, flush_timeout_dclk}), .o_tvalid(), .o_tready(1'b1)
+  );
+
+  axis_packet_flush #(
+    .WIDTH(INFO_W+(ITEM_W+1)*NIPC), .FLUSH_PARTIAL_PKTS(0), .TIMEOUT_W(32), .PIPELINE("OUT")
+  ) pyld_flusher_i (
+    .clk(axis_data_clk), .reset(axis_data_rst),
+    .enable(flush_en_dclk), .timeout(flush_timeout_dclk),
+    .flushing(flush_active_pyld), .done(flush_done_pyld),
+    .s_axis_tdata(flush_tdata),
+    .s_axis_tlast(flush_tlast),
+    .s_axis_tvalid(flush_tvalid),
+    .s_axis_tready(flush_tready),
+    .m_axis_tdata({m_axis_ttimestamp, m_axis_thas_time, m_axis_tlength, 
+                   m_axis_teob, m_axis_teov, m_axis_tkeep, m_axis_tdata}),
+    .m_axis_tlast(m_axis_tlast),
+    .m_axis_tvalid(m_axis_tvalid),
+    .m_axis_tready(m_axis_tready)
+  );
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/core/chdr_to_axis_data_mdata.v b/fpga/usrp3/lib/rfnoc/core/chdr_to_axis_data_mdata.v
new file mode 100644
index 000000000..90eb5c767
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/core/chdr_to_axis_data_mdata.v
@@ -0,0 +1,538 @@
+//
+// Copyright 2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: chdr_to_axis_data_mdata
+//
+// Description:
+//
+//   A deframer module for CHDR data packets. It accepts an input CHDR stream, 
+//   and produces two output streams:
+//
+//     1) Payload data, which includes the payload of the packet, as well as 
+//        timestamp and packet flags presented as sideband information.
+//     2) Metadata (mdata), which contains only the metadata of the packet.
+//
+//   This module also performs an optional clock crossing and data width 
+//   conversion from CHDR_W to a user requested width for the payload data bus.
+//
+//   The metadata and data packets are interleaved, i.e., a mdata packet will 
+//   arrive before its corresponding data packet. However, if mdata prefetching 
+//   is enabled, the mdata for the next packet might arrive before the data for 
+//   the current packet has been consumed. In the case of a rate reduction, 
+//   this allows the module to sustain a gapless stream of payload items and a 
+//   bursty sideband mdata path. If there is no metadata in a packet, then an 
+//   empty packet is output on m_axis_mdata_* (i.e., m_axis_mdata_tkeep will be 
+//   set to 0).
+//
+// Parameters:
+//
+//   - CHDR_W            : Width of the input CHDR bus in bits
+//   - ITEM_W            : Width of the output item bus in bits
+//   - NIPC              : The number of output items delivered per cycle
+//   - SYNC_CLKS         : Are the CHDR and data clocks synchronous to each other?
+//   - MDATA_FIFO_SIZE   : FIFO size for the mdata path
+//   - INFO_FIFO_SIZE    : FIFO size for the packet info path
+//   - PAYLOAD_FIFO_SIZE : FIFO size for the payload path
+//   - MDATA_PREFETCH_EN : Is mdata prefetching enabled?
+//
+// Signals:
+//
+//   - s_axis_chdr_*  : Input CHDR stream (AXI-Stream)
+//   - m_axis_*       : Output payload data stream (AXI-Stream)
+//   - m_axis_mdata_* : Output mdata stream (AXI-Stream)
+//   - flush_*        : Signals for flush control and status
+//
+
+module chdr_to_axis_data_mdata #(
+  parameter CHDR_W            = 256,
+  parameter ITEM_W            = 32,
+  parameter NIPC              = 2,
+  parameter SYNC_CLKS         = 0,
+  parameter MDATA_FIFO_SIZE   = 1,
+  parameter INFO_FIFO_SIZE    = 1,
+  parameter PAYLOAD_FIFO_SIZE = 1,
+  parameter MDATA_PREFETCH_EN = 1
+)(
+  // Clock, reset and settings
+  input  wire                     axis_chdr_clk,
+  input  wire                     axis_chdr_rst,
+  input  wire                     axis_data_clk,
+  input  wire                     axis_data_rst,
+  // CHDR in (AXI-Stream)
+  input  wire [CHDR_W-1:0]        s_axis_chdr_tdata,
+  input  wire                     s_axis_chdr_tlast,
+  input  wire                     s_axis_chdr_tvalid,
+  output wire                     s_axis_chdr_tready,
+  // Payload data stream out (AXI-Stream)
+  output wire [(ITEM_W*NIPC)-1:0] m_axis_tdata,
+  output wire [NIPC-1:0]          m_axis_tkeep,
+  output wire                     m_axis_tlast,
+  output wire                     m_axis_tvalid,
+  input  wire                     m_axis_tready,
+  // Payload sideband information
+  output wire [63:0]              m_axis_ttimestamp,
+  output wire                     m_axis_thas_time,
+  output wire [15:0]              m_axis_tlength,
+  output wire                     m_axis_teob,
+  output wire                     m_axis_teov,
+  // Metadata stream out (AXI-Stream)
+  output wire [CHDR_W-1:0]        m_axis_mdata_tdata,
+  output wire                     m_axis_mdata_tlast,
+  output wire                     m_axis_mdata_tkeep,
+  output wire                     m_axis_mdata_tvalid,
+  input  wire                     m_axis_mdata_tready,
+  // Flush signals
+  input  wire                     flush_en,
+  input  wire [31:0]              flush_timeout,
+  output wire                     flush_active,
+  output wire                     flush_done
+);
+
+  // ---------------------------------------------------
+  //  RFNoC Includes
+  // ---------------------------------------------------
+  `include "rfnoc_chdr_utils.vh"
+  `include "rfnoc_axis_ctrl_utils.vh"
+
+  // ---------------------------------------------------
+  //  Pipeline
+  // ---------------------------------------------------
+  localparam CHDR_KEEP_W = CHDR_W/ITEM_W;
+
+  wire [CHDR_W-1:0]       in_chdr_tdata;
+  wire [CHDR_KEEP_W-1:0]  in_chdr_tkeep;
+  wire                    in_chdr_tlast, in_chdr_tvalid;
+  reg                     in_chdr_tready;
+
+  axi_fifo_flop2 #(.WIDTH(CHDR_W+1)) in_pipe_i (
+    .clk(axis_chdr_clk), .reset(axis_chdr_rst), .clear(1'b0),
+    .i_tdata({s_axis_chdr_tlast, s_axis_chdr_tdata}),
+    .i_tvalid(s_axis_chdr_tvalid), .i_tready(s_axis_chdr_tready),
+    .o_tdata({in_chdr_tlast, in_chdr_tdata}),
+    .o_tvalid(in_chdr_tvalid), .o_tready(in_chdr_tready),
+    .space(), .occupied()
+  );
+
+  chdr_compute_tkeep #(.CHDR_W(CHDR_W), .ITEM_W(ITEM_W)) tkeep_gen_i (
+    .clk(axis_chdr_clk), .rst(axis_chdr_rst),
+    .axis_tdata(in_chdr_tdata), .axis_tlast(in_chdr_tlast),
+    .axis_tvalid(in_chdr_tvalid), .axis_tready(in_chdr_tready),
+    .axis_tkeep(in_chdr_tkeep)
+  );
+
+  // ---------------------------------------------------
+  //  Input State Machine
+  // ---------------------------------------------------
+  localparam INFO_W = 64+1+16+1+1;   // timestamp, has_time, length, eob, eov
+
+  wire [CHDR_W-1:0]       in_pyld_tdata;
+  wire [CHDR_KEEP_W-1:0]  in_pyld_tkeep;
+  wire                    in_pyld_tlast, in_pyld_tvalid, in_pyld_tready;
+
+  reg [INFO_W-1:0] in_info_tdata;
+  reg              in_info_tvalid;
+  wire             in_info_tready;
+
+  wire [CHDR_W-1:0] in_mdata_tdata;
+  wire              in_mdata_tkeep;
+  wire              in_mdata_tlast, in_mdata_tvalid, in_mdata_tready;
+
+
+  localparam [2:0] ST_HDR   = 3'd0;   // Processing the input CHDR header
+  localparam [2:0] ST_TS    = 3'd1;   // Processing the input CHDR timestamp
+  localparam [2:0] ST_MDATA = 3'd2;   // Processing the input CHDR metadata word
+  localparam [2:0] ST_BODY  = 3'd3;   // Processing the input CHDR payload word
+  localparam [2:0] ST_DROP  = 3'd4;   // Something went wrong... Dropping packet
+
+  reg [2:0] state = ST_HDR;
+  reg [4:0] mdata_pending = CHDR_NO_MDATA;
+  reg       last_mdata_line;
+
+  reg [15:0] chdr_length_reg;
+  reg        chdr_eob_reg, chdr_eov_reg;
+
+  // Shortcuts: CHDR header
+  wire [2:0] in_pkt_type = chdr_get_pkt_type(in_chdr_tdata[63:0]);
+  wire [4:0] in_num_mdata = chdr_get_num_mdata(in_chdr_tdata[63:0]);
+
+  always @(posedge axis_chdr_clk) begin
+    if (axis_chdr_rst) begin
+      state <= ST_HDR;
+    end else if (in_chdr_tvalid & in_chdr_tready) begin
+      case (state)
+
+        // ST_HDR: CHDR Header
+        // -------------------
+        ST_HDR: begin
+          // Always cache the number of metadata words
+          mdata_pending <= in_num_mdata;
+          // Figure out the next state
+          if (!in_chdr_tlast) begin
+            if (CHDR_W > 64) begin
+              // When CHDR_W > 64, the timestamp is a part of the header word.
+              // If this is a data packet (with/without a TS), we move on to the metadata/body
+              // state otherwise we drop it. Non-data packets should never reach here.
+              if (in_pkt_type == CHDR_PKT_TYPE_DATA || in_pkt_type == CHDR_PKT_TYPE_DATA_TS) begin
+                if (in_num_mdata != CHDR_NO_MDATA) begin
+                  state <= ST_MDATA;
+                end else begin
+                  state <= ST_BODY;
+                end
+              end else begin
+                state <= ST_DROP;
+              end
+            end else begin
+              // When CHDR_W == 64, the timestamp comes after the header. Check if this is a data
+              // packet with a TS to figure out the next state. If no TS, then check for metadata
+              // to move to the next state. Drop any non-data packets.
+              chdr_length_reg <= chdr_calc_payload_length(CHDR_W, in_chdr_tdata);
+              chdr_eob_reg    <= chdr_get_eob(in_chdr_tdata);
+              chdr_eov_reg    <= chdr_get_eov(in_chdr_tdata);
+              if (in_pkt_type == CHDR_PKT_TYPE_DATA_TS) begin
+                state <= ST_TS;
+              end else if (in_pkt_type == CHDR_PKT_TYPE_DATA) begin
+                if (in_num_mdata != CHDR_NO_MDATA) begin
+                  state <= ST_MDATA;
+                end else begin
+                  state <= ST_BODY;
+                end
+              end else begin
+                state <= ST_DROP;
+              end
+            end
+          end else begin    // Premature termination
+            // Packets must have at least one payload line
+            state <= ST_HDR;
+          end
+        end
+
+        // ST_TS: Timestamp (CHDR_W == 64 only)
+        // ------------------------------------
+        ST_TS: begin
+          if (!in_chdr_tlast) begin
+            if (mdata_pending != CHDR_NO_MDATA) begin
+              state <= ST_MDATA;
+            end else begin
+              state <= ST_BODY;
+            end
+          end else begin    // Premature termination
+            // Packets must have at least one payload line
+            state <= ST_HDR;
+          end
+        end
+
+        // ST_MDATA: Metadata word
+        // -----------------------
+        ST_MDATA: begin
+          if (!in_chdr_tlast) begin
+            // Count down metadata and stop at 1
+            if (mdata_pending == 5'd1) begin
+              state <= ST_BODY;
+            end else begin
+              mdata_pending <= mdata_pending - 5'd1;
+            end
+          end else begin    // Premature termination
+            // Packets must have at least one payload line
+            state <= ST_HDR;
+          end
+        end
+
+        // ST_BODY: Payload word
+        // ---------------------
+        ST_BODY: begin
+          if (in_chdr_tlast) begin
+            state <= ST_HDR;
+          end
+        end
+
+        // ST_DROP: Drop current packet
+        // ----------------------------
+        ST_DROP: begin
+          if (in_chdr_tlast) begin
+            state <= ST_HDR;
+          end
+        end
+
+        default: begin
+          // We should never get here
+          state <= ST_HDR;
+        end
+      endcase
+    end
+  end
+
+  // CHDR data goes to the payload stream only in the BODY state.
+  // Packets are expected to have at least one payload word so the
+  // CHDR tlast can be used as the payload tlast
+  assign in_pyld_tdata  = in_chdr_tdata;
+  assign in_pyld_tkeep  = in_chdr_tkeep;
+  assign in_pyld_tlast  = in_chdr_tlast;
+  assign in_pyld_tvalid = in_chdr_tvalid && (state == ST_BODY);
+
+  // Only metadata goes into the mdata FIFO. However, if there is no metadata,
+  // then we want an empty packet to go into the mdata FIFO. We check the
+  // packet type because non-data packets will be discarded.
+  assign in_mdata_tdata  = in_chdr_tdata;
+  assign in_mdata_tlast  = in_chdr_tlast || last_mdata_line;
+  assign in_mdata_tkeep  = (state == ST_MDATA);
+  assign in_mdata_tvalid = in_chdr_tvalid && (
+    (state == ST_MDATA) ||
+    (state == ST_HDR && in_num_mdata  == CHDR_NO_MDATA && 
+      (in_pkt_type == CHDR_PKT_TYPE_DATA || in_pkt_type == CHDR_PKT_TYPE_DATA_TS)));
+
+  always @(*) begin
+    // Packet timestamp and flags go into the info FIFO, but only if it's a 
+    // data packet since non-data packets will be discarded.
+    if (CHDR_W > 64) begin
+      // When CHDR_W > 64, all info will be in the first word of the CHDR packet
+      in_info_tdata =  { in_chdr_tdata[127:64], 
+                         chdr_get_has_time(in_chdr_tdata),
+                         chdr_calc_payload_length(CHDR_W, in_chdr_tdata),
+                         chdr_get_eob(in_chdr_tdata),
+                         chdr_get_eov(in_chdr_tdata) };
+      in_info_tvalid = in_chdr_tvalid && (state == ST_HDR && 
+        (in_pkt_type == CHDR_PKT_TYPE_DATA || in_pkt_type == CHDR_PKT_TYPE_DATA_TS));
+    end else begin
+      // When CHDR_W == 64, the flags will be in the first word of the packet, 
+      // but the timestamp will be in the second word, if there is a timestamp.
+      if (state == ST_HDR && in_pkt_type == CHDR_PKT_TYPE_DATA) begin
+        // No timestamp in this case
+        in_info_tdata  = { in_chdr_tdata[63:0], 1'b0, 
+                           chdr_calc_payload_length(CHDR_W, in_chdr_tdata),
+                           chdr_get_eob(in_chdr_tdata), chdr_get_eov(in_chdr_tdata) };
+        in_info_tvalid = in_chdr_tvalid;
+      end else begin
+        // Assuming timestamp is present, so use flags from previous clock cycle
+        in_info_tdata  = { in_chdr_tdata[63:0], 1'b1, chdr_length_reg,
+                           chdr_eob_reg, chdr_eov_reg };
+        in_info_tvalid = in_chdr_tvalid && (state == ST_TS);
+      end
+    end
+
+    case (state)
+      ST_HDR: begin
+        in_chdr_tready  = in_info_tready && in_mdata_tready;
+        last_mdata_line = (in_num_mdata == CHDR_NO_MDATA);
+      end
+      ST_TS: begin
+        in_chdr_tready  = in_info_tready && in_mdata_tready;
+        last_mdata_line = 1'b0;
+      end
+      ST_MDATA: begin
+        in_chdr_tready  = in_mdata_tready;
+        last_mdata_line = (mdata_pending == 5'd1);
+      end
+      ST_BODY: begin
+        in_chdr_tready  = in_pyld_tready;
+        last_mdata_line = 1'b0;
+      end
+      ST_DROP: begin
+        in_chdr_tready  = 1'b1;
+        last_mdata_line = 1'b0;
+      end
+      default: begin
+        in_chdr_tready  = 1'b0;
+        last_mdata_line = 1'b0;
+      end
+    endcase
+  end
+
+  // ---------------------------------------------------
+  //  Payload and mdata FIFOs
+  // ---------------------------------------------------
+  wire [CHDR_W-1:0]       out_pyld_tdata;
+  wire [CHDR_KEEP_W-1:0]  out_pyld_tkeep;
+  wire                    out_pyld_tlast, out_pyld_tvalid, out_pyld_tready;
+
+  wire tmp_mdata_tvalid, tmp_mdata_tready;
+  wire tmp_info_tready;
+
+  wire [(ITEM_W*NIPC)-1:0] flush_pyld_tdata;
+  wire [NIPC-1:0]          flush_pyld_tkeep;
+  wire                     flush_pyld_tlast, flush_pyld_tvalid, flush_pyld_tready;
+  wire [INFO_W-1:0]        flush_info_tdata;
+  wire [CHDR_W-1:0]        flush_mdata_tdata;
+  wire                     flush_mdata_tkeep;
+  wire                     flush_mdata_tlast, flush_mdata_tvalid, flush_mdata_tready;
+
+  generate if (SYNC_CLKS) begin : gen_sync_fifo
+    axi_fifo #(.WIDTH(CHDR_W+2), .SIZE(MDATA_FIFO_SIZE)) mdata_fifo_i (
+      .clk(axis_data_clk), .reset(axis_data_rst), .clear(1'b0),
+      .i_tdata({in_mdata_tkeep, in_mdata_tlast, in_mdata_tdata}),
+      .i_tvalid(in_mdata_tvalid), .i_tready(in_mdata_tready),
+      .o_tdata({flush_mdata_tkeep, flush_mdata_tlast, flush_mdata_tdata}),
+      .o_tvalid(tmp_mdata_tvalid), .o_tready(tmp_mdata_tready),
+      .space(), .occupied()
+    );
+    axi_fifo #(.WIDTH(INFO_W), .SIZE(INFO_FIFO_SIZE)) info_fifo_i (
+      .clk(axis_data_clk), .reset(axis_data_rst), .clear(1'b0),
+      .i_tdata(in_info_tdata),
+      .i_tvalid(in_info_tvalid), .i_tready(in_info_tready),
+      .o_tdata(flush_info_tdata),
+      .o_tvalid(), .o_tready(tmp_info_tready),
+      .space(), .occupied()
+    );
+    axi_fifo #(.WIDTH(CHDR_W+CHDR_KEEP_W+1), .SIZE(PAYLOAD_FIFO_SIZE)) pyld_fifo_i (
+      .clk(axis_data_clk), .reset(axis_data_rst), .clear(1'b0),
+      .i_tdata({in_pyld_tlast, in_pyld_tkeep, in_pyld_tdata}),
+      .i_tvalid(in_pyld_tvalid), .i_tready(in_pyld_tready),
+      .o_tdata({out_pyld_tlast, out_pyld_tkeep, out_pyld_tdata}),
+      .o_tvalid(out_pyld_tvalid), .o_tready(out_pyld_tready),
+      .space(), .occupied()
+    );
+  end else begin : gen_async_fifo
+    axi_fifo_2clk #(.WIDTH(CHDR_W+2), .SIZE(MDATA_FIFO_SIZE)) mdata_fifo_i (
+      .reset(axis_chdr_rst),
+      .i_aclk(axis_chdr_clk),
+      .i_tdata({in_mdata_tkeep, in_mdata_tlast, in_mdata_tdata}),
+      .i_tvalid(in_mdata_tvalid), .i_tready(in_mdata_tready),
+      .o_aclk(axis_data_clk),
+      .o_tdata({flush_mdata_tkeep, flush_mdata_tlast, flush_mdata_tdata}),
+      .o_tvalid(tmp_mdata_tvalid), .o_tready(tmp_mdata_tready)
+    );
+    axi_fifo_2clk #(.WIDTH(INFO_W), .SIZE(INFO_FIFO_SIZE)) info_fifo_i (
+      .reset(axis_chdr_rst),
+      .i_aclk(axis_chdr_clk),
+      .i_tdata(in_info_tdata),
+      .i_tvalid(in_info_tvalid), .i_tready(in_info_tready),
+      .o_aclk(axis_data_clk),
+      .o_tdata(flush_info_tdata),
+      .o_tvalid(), .o_tready(tmp_info_tready)
+    );
+    axi_fifo_2clk #(.WIDTH(CHDR_W+CHDR_KEEP_W+1), .SIZE(PAYLOAD_FIFO_SIZE)) pyld_fifo_i (
+      .reset(axis_chdr_rst),
+      .i_aclk(axis_chdr_clk),
+      .i_tdata({in_pyld_tlast, in_pyld_tkeep, in_pyld_tdata}),
+      .i_tvalid(in_pyld_tvalid), .i_tready(in_pyld_tready),
+      .o_aclk(axis_data_clk),
+      .o_tdata({out_pyld_tlast, out_pyld_tkeep, out_pyld_tdata}),
+      .o_tvalid(out_pyld_tvalid), .o_tready(out_pyld_tready)
+    );
+  end endgenerate
+
+  // ---------------------------------------------------
+  //  Data Width Converter: CHDR_W => ITEM_W*NIPC
+  // ---------------------------------------------------
+  wire tmp_pyld_tvalid, tmp_pyld_tready;
+
+  generate
+    if (CHDR_W != ITEM_W*NIPC) begin : gen_axis_width_conv
+      axis_width_conv #(
+        .WORD_W(ITEM_W), .IN_WORDS(CHDR_W/ITEM_W), .OUT_WORDS(NIPC),
+        .SYNC_CLKS(1), .PIPELINE("NONE")
+      ) payload_width_conv_i (
+        .s_axis_aclk(axis_data_clk), .s_axis_rst(axis_data_rst),
+        .s_axis_tdata(out_pyld_tdata), .s_axis_tkeep(out_pyld_tkeep),
+        .s_axis_tlast(out_pyld_tlast), .s_axis_tvalid(out_pyld_tvalid),
+        .s_axis_tready(out_pyld_tready),
+        .m_axis_aclk(axis_data_clk), .m_axis_rst(axis_data_rst),
+        .m_axis_tdata(flush_pyld_tdata), .m_axis_tkeep(flush_pyld_tkeep),
+        .m_axis_tlast(flush_pyld_tlast), .m_axis_tvalid(tmp_pyld_tvalid),
+        .m_axis_tready(tmp_pyld_tready)
+      );
+    end else begin : no_gen_axis_width_conv
+      assign flush_pyld_tdata = out_pyld_tdata;
+      assign flush_pyld_tkeep = out_pyld_tkeep;
+      assign flush_pyld_tlast = out_pyld_tlast;
+      assign tmp_pyld_tvalid  = out_pyld_tvalid;
+      assign out_pyld_tready  = tmp_pyld_tready;
+    end
+  endgenerate
+
+
+  // ---------------------------------------------------
+  //  Output State Machine
+  // ---------------------------------------------------
+  reg [2:0] mdata_pkt_cnt = 3'd0, pyld_pkt_cnt = 3'd0;
+
+  // A payload packet can pass only if it is preceded by a mdata packet
+  wire pass_pyld = ((mdata_pkt_cnt - pyld_pkt_cnt) > 3'd0);
+  // A mdata packet has to be blocked if its corresponding payload packet hasn't passed except
+  // when prefetching is enabled. In that case one additional mdata packet is allowed to pass
+  wire pass_mdata = ((mdata_pkt_cnt - pyld_pkt_cnt) < (MDATA_PREFETCH_EN == 1 ? 3'd2 : 3'd1));
+
+  always @(posedge axis_data_clk) begin
+    if (axis_data_rst) begin
+      mdata_pkt_cnt <= 3'd0;
+      pyld_pkt_cnt <= 3'd0;
+    end else begin
+      if (flush_mdata_tvalid && flush_mdata_tready && flush_mdata_tlast)
+        mdata_pkt_cnt <= mdata_pkt_cnt + 3'd1;
+      if (flush_pyld_tvalid && flush_pyld_tready && flush_pyld_tlast)
+        pyld_pkt_cnt <= pyld_pkt_cnt + 3'd1;
+    end
+  end
+
+  assign flush_pyld_tvalid = tmp_pyld_tvalid && pass_pyld;
+  assign tmp_pyld_tready = flush_pyld_tready && pass_pyld;
+
+  // Only read the info FIFO once per packet
+  assign tmp_info_tready = tmp_pyld_tready && flush_pyld_tlast && tmp_pyld_tvalid;
+
+  assign flush_mdata_tvalid = tmp_mdata_tvalid && pass_mdata;
+  assign tmp_mdata_tready = flush_mdata_tready && pass_mdata;
+
+  // ---------------------------------------------------
+  //  Flushing Logic
+  // ---------------------------------------------------
+  wire [31:0] flush_timeout_dclk;
+  wire        flush_en_dclk;
+  wire        flush_active_pyld_cclk, flush_active_mdata_cclk;
+  wire        flush_done_pyld_cclk, flush_done_mdata_cclk;
+  wire        flush_active_pyld, flush_active_mdata;
+  wire        flush_done_pyld, flush_done_mdata;
+
+  synchronizer #(.WIDTH(4), .INITIAL_VAL(4'd0)) flush_2clk_rb_i (
+    .clk(axis_chdr_clk), .rst(1'b0),
+    .in({flush_active_pyld, flush_done_pyld,
+         flush_active_mdata, flush_done_mdata}),
+    .out({flush_active_pyld_cclk, flush_done_pyld_cclk,
+         flush_active_mdata_cclk, flush_done_mdata_cclk})
+  );
+  assign flush_active = flush_active_pyld_cclk | flush_active_mdata_cclk;
+  assign flush_done = flush_done_pyld_cclk & flush_done_mdata_cclk;
+
+  axi_fifo_2clk #(.WIDTH(33), .SIZE(1)) flush_2clk_ctrl_i (
+    .reset(axis_chdr_rst),
+    .i_aclk(axis_chdr_clk),
+    .i_tdata({flush_en, flush_timeout}), .i_tvalid(1'b1), .i_tready(),
+    .o_aclk(axis_data_clk),
+    .o_tdata({flush_en_dclk, flush_timeout_dclk}), .o_tvalid(), .o_tready(1'b1)
+  );
+
+  axis_packet_flush #(
+    .WIDTH(INFO_W+(ITEM_W+1)*NIPC), .FLUSH_PARTIAL_PKTS(0), .TIMEOUT_W(32), .PIPELINE("OUT")
+  ) pyld_flusher_i (
+    .clk(axis_data_clk), .reset(axis_data_rst),
+    .enable(flush_en_dclk), .timeout(flush_timeout_dclk),
+    .flushing(flush_active_pyld), .done(flush_done_pyld),
+    .s_axis_tdata({flush_info_tdata, flush_pyld_tkeep, flush_pyld_tdata}),
+    .s_axis_tlast(flush_pyld_tlast),
+    .s_axis_tvalid(flush_pyld_tvalid),
+    .s_axis_tready(flush_pyld_tready),
+    .m_axis_tdata({m_axis_ttimestamp, m_axis_thas_time, m_axis_tlength, 
+                   m_axis_teob, m_axis_teov, m_axis_tkeep, m_axis_tdata}),
+    .m_axis_tlast(m_axis_tlast),
+    .m_axis_tvalid(m_axis_tvalid),
+    .m_axis_tready(m_axis_tready)
+  );
+
+  axis_packet_flush #(
+    .WIDTH(CHDR_W+1), .FLUSH_PARTIAL_PKTS(0), .TIMEOUT_W(32), .PIPELINE("OUT")
+  ) mdata_flusher_i (
+    .clk(axis_data_clk), .reset(axis_data_rst),
+    .enable(flush_en_dclk), .timeout(flush_timeout_dclk),
+    .flushing(flush_active_mdata), .done(flush_done_mdata),
+    .s_axis_tdata({flush_mdata_tkeep, flush_mdata_tdata}),
+    .s_axis_tlast(flush_mdata_tlast),
+    .s_axis_tvalid(flush_mdata_tvalid),
+    .s_axis_tready(flush_mdata_tready),
+    .m_axis_tdata({m_axis_mdata_tkeep, m_axis_mdata_tdata}),
+    .m_axis_tlast(m_axis_mdata_tlast),
+    .m_axis_tvalid(m_axis_mdata_tvalid),
+    .m_axis_tready(m_axis_mdata_tready)
+  );
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/core/chdr_to_axis_pyld_ctxt.v b/fpga/usrp3/lib/rfnoc/core/chdr_to_axis_pyld_ctxt.v
new file mode 100644
index 000000000..f604584e8
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/core/chdr_to_axis_pyld_ctxt.v
@@ -0,0 +1,458 @@
+//
+// Copyright 2018-2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: chdr_to_axis_pyld_ctxt
+// Description:
+//   A header deframer module for CHDR data packets.
+//   Accepts an input CHDR stream, and produces two output streams:
+//   1) Payload, which contains the payload of the packet
+//   2) Context, which contains the header info in the packet i.e.
+//      CHDR header, timestamp and metadata (marked with a tuser)
+//   This module also performs an optional clock crossing and data
+//   width convertion from CHDR_W to a user requested width for the
+//   payload bus.
+//   Context and data packets are interleaved i.e. a context packet
+//   will arrive before its corresponding data packet. However, if
+//   context prefetching is enabled, the context for the next packet
+//   might arrive before the data for the current packet has been
+//   consumed. In the case of a rate reduction, this allows the module
+//   to sustain a gapless stream of payload items and a bursty
+//   sideband context path.
+//
+// Parameters:
+//   - CHDR_W: Width of the input CHDR bus in bits
+//   - ITEM_W: Width of the output item bus in bits
+//   - NIPC: The number of output items delievered per cycle
+//   - SYNC_CLKS: Are the CHDR and data clocks synchronous to each other?
+//   - CONTEXT_FIFO_SIZE: FIFO size for the context path
+//   - PAYLOAD_FIFO_SIZE: FIFO size for the payload path
+//   - CONTEXT_PREFETCH_EN: Is context prefetching enabled?
+//
+// Signals:
+//   - s_axis_chdr_* : Input CHDR stream (AXI-Stream)
+//   - m_axis_payload_* : Output payload stream (AXI-Stream)
+//   - m_axis_context_* : Output context stream (AXI-Stream)
+//   - flush_* : Signals for flush control and status
+//
+
+module chdr_to_axis_pyld_ctxt #(
+  parameter CHDR_W              = 256,
+  parameter ITEM_W              = 32,
+  parameter NIPC                = 2,
+  parameter SYNC_CLKS           = 0,
+  parameter CONTEXT_FIFO_SIZE   = 1,
+  parameter PAYLOAD_FIFO_SIZE   = 1,
+  parameter CONTEXT_PREFETCH_EN = 1
+)(
+  // Clock, reset and settings
+  input  wire                     axis_chdr_clk,
+  input  wire                     axis_chdr_rst,
+  input  wire                     axis_data_clk,
+  input  wire                     axis_data_rst,
+  // CHDR in (AXI-Stream)
+  input  wire [CHDR_W-1:0]        s_axis_chdr_tdata,
+  input  wire                     s_axis_chdr_tlast,
+  input  wire                     s_axis_chdr_tvalid,
+  output wire                     s_axis_chdr_tready,
+  // Payload stream out (AXI-Stream)
+  output wire [(ITEM_W*NIPC)-1:0] m_axis_payload_tdata,
+  output wire [NIPC-1:0]          m_axis_payload_tkeep,
+  output wire                     m_axis_payload_tlast,
+  output wire                     m_axis_payload_tvalid,
+  input  wire                     m_axis_payload_tready,
+  // Context stream out (AXI-Stream)
+  output wire [CHDR_W-1:0]        m_axis_context_tdata,
+  output wire [3:0]               m_axis_context_tuser,
+  output wire                     m_axis_context_tlast,
+  output wire                     m_axis_context_tvalid,
+  input  wire                     m_axis_context_tready,
+  // Flush signals
+  input  wire                     flush_en,
+  input  wire [31:0]              flush_timeout,
+  output wire                     flush_active,
+  output wire                     flush_done
+);
+
+  // ---------------------------------------------------
+  //  RFNoC Includes
+  // ---------------------------------------------------
+  `include "rfnoc_chdr_utils.vh"
+  `include "rfnoc_axis_ctrl_utils.vh"
+
+  // ---------------------------------------------------
+  //  Pipeline
+  // ---------------------------------------------------
+  localparam CHDR_KEEP_W = CHDR_W/ITEM_W;
+
+  wire [CHDR_W-1:0]       in_chdr_tdata;
+  wire [CHDR_KEEP_W-1:0]  in_chdr_tkeep;
+  wire                    in_chdr_tlast, in_chdr_tvalid;
+  reg                     in_chdr_tready;
+
+  axi_fifo_flop2 #(.WIDTH(CHDR_W+1)) in_pipe_i (
+    .clk(axis_chdr_clk), .reset(axis_chdr_rst), .clear(1'b0),
+    .i_tdata({s_axis_chdr_tlast, s_axis_chdr_tdata}),
+    .i_tvalid(s_axis_chdr_tvalid), .i_tready(s_axis_chdr_tready),
+    .o_tdata({in_chdr_tlast, in_chdr_tdata}),
+    .o_tvalid(in_chdr_tvalid), .o_tready(in_chdr_tready),
+    .space(), .occupied()
+  );
+
+  chdr_compute_tkeep #(.CHDR_W(CHDR_W), .ITEM_W(ITEM_W)) tkeep_gen_i (
+    .clk(axis_chdr_clk), .rst(axis_chdr_rst),
+    .axis_tdata(in_chdr_tdata), .axis_tlast(in_chdr_tlast),
+    .axis_tvalid(in_chdr_tvalid), .axis_tready(in_chdr_tready),
+    .axis_tkeep(in_chdr_tkeep)
+  );
+
+  // ---------------------------------------------------
+  //  Input State Machine
+  // ---------------------------------------------------
+  wire [CHDR_W-1:0]       in_pyld_tdata;
+  wire [CHDR_KEEP_W-1:0]  in_pyld_tkeep;
+  wire                    in_pyld_tlast, in_pyld_tvalid, in_pyld_tready;
+
+  wire [CHDR_W-1:0] in_ctxt_tdata;
+  reg  [3:0]        in_ctxt_tuser;
+  wire              in_ctxt_tlast, in_ctxt_tvalid, in_ctxt_tready;
+
+
+  localparam [2:0] ST_HDR   = 3'd0;   // Processing the input CHDR header
+  localparam [2:0] ST_TS    = 3'd1;   // Processing the input CHDR timestamp
+  localparam [2:0] ST_MDATA = 3'd2;   // Processing the input CHDR metadata word
+  localparam [2:0] ST_BODY  = 3'd3;   // Processing the input CHDR payload word
+  localparam [2:0] ST_DROP  = 3'd4;   // Something went wrong... Dropping packet
+
+  reg [2:0] state = ST_HDR;
+  reg [4:0] mdata_pending = CHDR_NO_MDATA;
+  reg       last_ctxt_line;
+
+  // Shortcuts: CHDR header
+  wire [2:0] in_pkt_type = chdr_get_pkt_type(in_chdr_tdata[63:0]);
+  wire [4:0] in_num_mdata = chdr_get_num_mdata(in_chdr_tdata[63:0]);
+
+  always @(posedge axis_chdr_clk) begin
+    if (axis_chdr_rst) begin
+      state <= ST_HDR;
+    end else if (in_chdr_tvalid & in_chdr_tready) begin
+      case (state)
+
+        // ST_HDR: CHDR Header
+        // -------------------
+        ST_HDR: begin
+          // Always cache the number of metadata words
+          mdata_pending <= in_num_mdata;
+          // Figure out the next state
+          if (!in_chdr_tlast) begin
+            if (CHDR_W > 64) begin
+              // When CHDR_W > 64, the timestamp is a part of the header word.
+              // If this is a data packet (with/without a TS), we move on to the metadata/body
+              // state otherwise we drop it. Non-data packets should never reach here.
+              if (in_pkt_type == CHDR_PKT_TYPE_DATA || in_pkt_type == CHDR_PKT_TYPE_DATA_TS) begin
+                if (in_num_mdata != CHDR_NO_MDATA) begin
+                  state <= ST_MDATA;
+                end else begin
+                  state <= ST_BODY;
+                end
+              end else begin
+                state <= ST_DROP;
+              end
+            end else begin
+              // When CHDR_W == 64, the timestamp comes after the header. Check if this is a data
+              // packet with a TS to figure out the next state. If no TS, then check for metadata
+              // to move to the next state. Drop any non-data packets.
+              if (in_pkt_type == CHDR_PKT_TYPE_DATA_TS) begin
+                state <= ST_TS;
+              end else if (in_pkt_type == CHDR_PKT_TYPE_DATA) begin
+                if (in_num_mdata != CHDR_NO_MDATA) begin
+                  state <= ST_MDATA;
+                end else begin
+                  state <= ST_BODY;
+                end
+              end else begin
+                state <= ST_DROP;
+              end
+            end
+          end else begin    // Premature termination
+            // Packets must have at least one payload line
+            state <= ST_HDR;
+          end
+        end
+
+        // ST_TS: Timestamp (CHDR_W == 64 only)
+        // ------------------------------------
+        ST_TS: begin
+          if (!in_chdr_tlast) begin
+            if (mdata_pending != CHDR_NO_MDATA) begin
+              state <= ST_MDATA;
+            end else begin
+              state <= ST_BODY;
+            end
+          end else begin    // Premature termination
+            // Packets must have at least one payload line
+            state <= ST_HDR;
+          end
+        end
+
+        // ST_MDATA: Metadata word
+        // -----------------------
+        ST_MDATA: begin
+          if (!in_chdr_tlast) begin
+            // Count down metadata and stop at 1
+            if (mdata_pending == 5'd1) begin
+              state <= ST_BODY;
+            end else begin
+              mdata_pending <= mdata_pending - 5'd1;
+            end
+          end else begin    // Premature termination
+            // Packets must have at least one payload line
+            state <= ST_HDR;
+          end
+        end
+
+        // ST_BODY: Payload word
+        // ---------------------
+        ST_BODY: begin
+          if (in_chdr_tlast) begin
+            state <= ST_HDR;
+          end
+        end
+
+        // ST_DROP: Drop current packet
+        // ----------------------------
+        ST_DROP: begin
+          if (in_chdr_tlast) begin
+            state <= ST_HDR;
+          end
+        end
+
+        default: begin
+          // We should never get here
+          state <= ST_HDR;
+        end
+      endcase
+    end
+  end
+
+  // CHDR data goes to the payload stream only in the BODY state.
+  // Packets are expected to have at least one payload word so the
+  // CHDR tlast can be used as the payload tlast
+  assign in_pyld_tdata  = in_chdr_tdata;
+  assign in_pyld_tkeep  = in_chdr_tkeep;
+  assign in_pyld_tlast  = in_chdr_tlast;
+  assign in_pyld_tvalid = in_chdr_tvalid && (state == ST_BODY);
+
+  // CHDR data goes to the context stream in the HDR,TS,MDATA state.
+  // tlast has to be recomputed for the context stream, however, we 
+  // still need to correctly handle an errant packet without a payload
+  assign in_ctxt_tdata  = in_chdr_tdata;
+  assign in_ctxt_tlast  = in_chdr_tlast || last_ctxt_line;
+  assign in_ctxt_tvalid = in_chdr_tvalid && (state != ST_BODY && state != ST_DROP);
+
+  always @(*) begin
+    case (state)
+      ST_HDR: begin
+        // The header goes to the context stream
+        in_chdr_tready <= in_ctxt_tready;
+        in_ctxt_tuser  <= (CHDR_W > 64) ? CONTEXT_FIELD_HDR_TS : CONTEXT_FIELD_HDR;
+        last_ctxt_line <= (in_num_mdata == 7'd0) && (
+                           in_pkt_type == CHDR_PKT_TYPE_DATA || 
+                          (in_pkt_type == CHDR_PKT_TYPE_DATA_TS && CHDR_W > 64));
+      end
+      ST_TS: begin
+        // The timestamp goes to the context stream
+        in_chdr_tready <= in_ctxt_tready;
+        in_ctxt_tuser  <= CONTEXT_FIELD_TS;
+        last_ctxt_line <= (mdata_pending == CHDR_NO_MDATA);
+      end
+      ST_MDATA: begin
+        // The metadata goes to the context stream
+        in_chdr_tready <= in_ctxt_tready;
+        in_ctxt_tuser  <= CONTEXT_FIELD_MDATA;
+        last_ctxt_line <= (mdata_pending == 5'd1);
+      end
+      ST_BODY: begin
+        // The body goes to the payload stream
+        in_chdr_tready <= in_pyld_tready;
+        in_ctxt_tuser  <= 4'h0;
+        last_ctxt_line <= 1'b0;
+      end
+      ST_DROP: begin
+        // Errant packets get dropped
+        in_chdr_tready <= 1'b1;
+        in_ctxt_tuser  <= 4'h0;
+        last_ctxt_line <= 1'b0;
+      end
+      default: begin
+        in_chdr_tready <= 1'b0;
+        in_ctxt_tuser  <= 4'h0;
+        last_ctxt_line <= 1'b0;
+      end
+    endcase
+  end
+
+  // ---------------------------------------------------
+  //  Payload and Context FIFOs
+  // ---------------------------------------------------
+  wire [CHDR_W-1:0]       out_pyld_tdata;
+  wire [CHDR_KEEP_W-1:0]  out_pyld_tkeep;
+  wire                    out_pyld_tlast, out_pyld_tvalid, out_pyld_tready;
+
+  wire tmp_ctxt_tvalid, tmp_ctxt_tready;
+
+  wire [(ITEM_W*NIPC)-1:0] flush_pyld_tdata;
+  wire [NIPC-1:0]          flush_pyld_tkeep;
+  wire                     flush_pyld_tlast, flush_pyld_tvalid, flush_pyld_tready;
+  wire [CHDR_W-1:0]        flush_ctxt_tdata;
+  wire [3:0]               flush_ctxt_tuser;
+  wire                     flush_ctxt_tlast, flush_ctxt_tvalid, flush_ctxt_tready;
+
+  generate if (SYNC_CLKS) begin : gen_sync_fifo
+    axi_fifo #(.WIDTH(CHDR_W+4+1), .SIZE(CONTEXT_FIFO_SIZE)) ctxt_fifo_i (
+      .clk(axis_data_clk), .reset(axis_data_rst), .clear(1'b0),
+      .i_tdata({in_ctxt_tlast, in_ctxt_tuser, in_ctxt_tdata}),
+      .i_tvalid(in_ctxt_tvalid), .i_tready(in_ctxt_tready),
+      .o_tdata({flush_ctxt_tlast, flush_ctxt_tuser, flush_ctxt_tdata}),
+      .o_tvalid(tmp_ctxt_tvalid), .o_tready(tmp_ctxt_tready),
+      .space(), .occupied()
+    );
+    axi_fifo #(.WIDTH(CHDR_W+CHDR_KEEP_W+1), .SIZE(PAYLOAD_FIFO_SIZE)) pyld_fifo_i (
+      .clk(axis_data_clk), .reset(axis_data_rst), .clear(1'b0),
+      .i_tdata({in_pyld_tlast, in_pyld_tkeep, in_pyld_tdata}),
+      .i_tvalid(in_pyld_tvalid), .i_tready(in_pyld_tready),
+      .o_tdata({out_pyld_tlast, out_pyld_tkeep, out_pyld_tdata}),
+      .o_tvalid(out_pyld_tvalid), .o_tready(out_pyld_tready),
+      .space(), .occupied()
+    );
+  end else begin : gen_async_fifo
+    axi_fifo_2clk #(.WIDTH(CHDR_W+4+1), .SIZE(CONTEXT_FIFO_SIZE)) ctxt_fifo_i (
+      .reset(axis_chdr_rst),
+      .i_aclk(axis_chdr_clk),
+      .i_tdata({in_ctxt_tlast, in_ctxt_tuser, in_ctxt_tdata}),
+      .i_tvalid(in_ctxt_tvalid), .i_tready(in_ctxt_tready),
+      .o_aclk(axis_data_clk),
+      .o_tdata({flush_ctxt_tlast, flush_ctxt_tuser, flush_ctxt_tdata}),
+      .o_tvalid(tmp_ctxt_tvalid), .o_tready(tmp_ctxt_tready)
+    );
+    axi_fifo_2clk #(.WIDTH(CHDR_W+CHDR_KEEP_W+1), .SIZE(PAYLOAD_FIFO_SIZE)) pyld_fifo_i (
+      .reset(axis_chdr_rst),
+      .i_aclk(axis_chdr_clk),
+      .i_tdata({in_pyld_tlast, in_pyld_tkeep, in_pyld_tdata}),
+      .i_tvalid(in_pyld_tvalid), .i_tready(in_pyld_tready),
+      .o_aclk(axis_data_clk),
+      .o_tdata({out_pyld_tlast, out_pyld_tkeep, out_pyld_tdata}),
+      .o_tvalid(out_pyld_tvalid), .o_tready(out_pyld_tready)
+    );
+  end endgenerate
+
+  // ---------------------------------------------------
+  //  Data Width Converter: CHDR_W => ITEM_W*NIPC
+  // ---------------------------------------------------
+  wire tmp_pyld_tvalid, tmp_pyld_tready;
+
+  axis_width_conv #(
+    .WORD_W(ITEM_W), .IN_WORDS(CHDR_W/ITEM_W), .OUT_WORDS(NIPC),
+    .SYNC_CLKS(1), .PIPELINE("NONE")
+  ) payload_width_conv_i (
+    .s_axis_aclk(axis_data_clk), .s_axis_rst(axis_data_rst),
+    .s_axis_tdata(out_pyld_tdata), .s_axis_tkeep(out_pyld_tkeep),
+    .s_axis_tlast(out_pyld_tlast), .s_axis_tvalid(out_pyld_tvalid),
+    .s_axis_tready(out_pyld_tready),
+    .m_axis_aclk(axis_data_clk), .m_axis_rst(axis_data_rst),
+    .m_axis_tdata(flush_pyld_tdata), .m_axis_tkeep(flush_pyld_tkeep),
+    .m_axis_tlast(flush_pyld_tlast), .m_axis_tvalid(tmp_pyld_tvalid),
+    .m_axis_tready(tmp_pyld_tready)
+  );
+
+  // ---------------------------------------------------
+  //  Output State Machine
+  // ---------------------------------------------------
+  reg [2:0] ctxt_pkt_cnt = 3'd0, pyld_pkt_cnt = 3'd0;
+
+  // A payload packet can pass only if it is preceeded by a context packet
+  wire pass_pyld = ((ctxt_pkt_cnt - pyld_pkt_cnt) > 3'd0);
+  // A context packet has to be blocked if its corresponding payload packet hasn't passed except
+  // when prefetching is enabled. In that case one additional context packet is allowed to pass
+  wire pass_ctxt = ((ctxt_pkt_cnt - pyld_pkt_cnt) < (CONTEXT_PREFETCH_EN == 1 ? 3'd2 : 3'd1));
+
+  always @(posedge axis_data_clk) begin
+    if (axis_data_rst) begin
+      ctxt_pkt_cnt <= 3'd0;
+      pyld_pkt_cnt <= 3'd0;
+    end else begin
+      if (flush_ctxt_tvalid && flush_ctxt_tready && flush_ctxt_tlast)
+        ctxt_pkt_cnt <= ctxt_pkt_cnt + 3'd1;
+      if (flush_pyld_tvalid && flush_pyld_tready && flush_pyld_tlast)
+        pyld_pkt_cnt <= pyld_pkt_cnt + 3'd1;
+    end
+  end
+
+  assign flush_pyld_tvalid = tmp_pyld_tvalid && pass_pyld;
+  assign tmp_pyld_tready = flush_pyld_tready && pass_pyld;
+
+  assign flush_ctxt_tvalid = tmp_ctxt_tvalid && pass_ctxt;
+  assign tmp_ctxt_tready = flush_ctxt_tready && pass_ctxt;
+
+  // ---------------------------------------------------
+  //  Flushing Logic
+  // ---------------------------------------------------
+  wire [31:0] flush_timeout_dclk;
+  wire        flush_en_dclk;
+  wire        flush_active_pyld_cclk, flush_active_ctxt_cclk;
+  wire        flush_done_pyld_cclk, flush_done_ctxt_cclk;
+  wire        flush_active_pyld, flush_active_ctxt;
+  wire        flush_done_pyld, flush_done_ctxt;
+
+  synchronizer #(.WIDTH(4), .INITIAL_VAL(4'd0)) flush_2clk_rb_i (
+    .clk(axis_chdr_clk), .rst(1'b0),
+    .in({flush_active_pyld, flush_done_pyld,
+         flush_active_ctxt, flush_done_ctxt}),
+    .out({flush_active_pyld_cclk, flush_done_pyld_cclk,
+         flush_active_ctxt_cclk, flush_done_ctxt_cclk})
+  );
+  assign flush_active = flush_active_pyld_cclk | flush_active_ctxt_cclk;
+  assign flush_done = flush_done_pyld_cclk & flush_done_ctxt_cclk;
+
+  axi_fifo_2clk #(.WIDTH(33), .SIZE(1)) flush_2clk_ctrl_i (
+    .reset(axis_chdr_rst),
+    .i_aclk(axis_chdr_clk),
+    .i_tdata({flush_en, flush_timeout}), .i_tvalid(1'b1), .i_tready(),
+    .o_aclk(axis_data_clk),
+    .o_tdata({flush_en_dclk, flush_timeout_dclk}), .o_tvalid(), .o_tready(1'b1)
+  );
+
+  axis_packet_flush #(
+    .WIDTH((ITEM_W+1)*NIPC), .FLUSH_PARTIAL_PKTS(0), .TIMEOUT_W(32), .PIPELINE("OUT")
+  ) pyld_flusher_i (
+    .clk(axis_data_clk), .reset(axis_data_rst),
+    .enable(flush_en_dclk), .timeout(flush_timeout_dclk),
+    .flushing(flush_active_pyld), .done(flush_done_pyld),
+    .s_axis_tdata({flush_pyld_tkeep, flush_pyld_tdata}),
+    .s_axis_tlast(flush_pyld_tlast),
+    .s_axis_tvalid(flush_pyld_tvalid),
+    .s_axis_tready(flush_pyld_tready),
+    .m_axis_tdata({m_axis_payload_tkeep, m_axis_payload_tdata}),
+    .m_axis_tlast(m_axis_payload_tlast),
+    .m_axis_tvalid(m_axis_payload_tvalid),
+    .m_axis_tready(m_axis_payload_tready)
+  );
+
+  axis_packet_flush #(
+    .WIDTH(CHDR_W+4), .FLUSH_PARTIAL_PKTS(0), .TIMEOUT_W(32), .PIPELINE("OUT")
+  ) ctxt_flusher_i (
+    .clk(axis_data_clk), .reset(axis_data_rst),
+    .enable(flush_en_dclk), .timeout(flush_timeout_dclk),
+    .flushing(flush_active_ctxt), .done(flush_done_ctxt),
+    .s_axis_tdata({flush_ctxt_tuser, flush_ctxt_tdata}),
+    .s_axis_tlast(flush_ctxt_tlast),
+    .s_axis_tvalid(flush_ctxt_tvalid),
+    .s_axis_tready(flush_ctxt_tready),
+    .m_axis_tdata({m_axis_context_tuser, m_axis_context_tdata}),
+    .m_axis_tlast(m_axis_context_tlast),
+    .m_axis_tvalid(m_axis_context_tvalid),
+    .m_axis_tready(m_axis_context_tready)
+  );
+
+endmodule // chdr_to_axis_pyld_ctxt
diff --git a/fpga/usrp3/lib/rfnoc/core/chdr_to_chdr_data.v b/fpga/usrp3/lib/rfnoc/core/chdr_to_chdr_data.v
new file mode 100644
index 000000000..390d77bca
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/core/chdr_to_chdr_data.v
@@ -0,0 +1,55 @@
+//
+// Copyright 2018-2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: axis_raw_data_to_chdr
+// Description:
+//   A simple adapter for when CHDR data is requested as an
+//   interface to user logic.
+//
+// Parameters:
+//   - CHDR_W: Width of the input CHDR bus in bits
+//
+// Signals:
+//   - s_axis_chdr_* : Input CHDR stream (AXI-Stream)
+//   - m_axis_chdr_* : Output CHDR stream (AXI-Stream)
+//   - flush_* : Signals for flush control and status
+//
+
+module chdr_to_chdr_data #(
+  parameter CHDR_W = 256
+)(
+  // Clock, reset and settings
+  input  wire              axis_chdr_clk,
+  input  wire              axis_chdr_rst,
+  // CHDR in (AXI-Stream)
+  input  wire [CHDR_W-1:0] s_axis_chdr_tdata,
+  input  wire              s_axis_chdr_tlast,
+  input  wire              s_axis_chdr_tvalid,
+  output wire              s_axis_chdr_tready,
+  // CHDR in (AXI-Stream)
+  output wire [CHDR_W-1:0] m_axis_chdr_tdata,
+  output wire              m_axis_chdr_tlast,
+  output wire              m_axis_chdr_tvalid,
+  input  wire              m_axis_chdr_tready,
+  // Flush signals
+  input  wire              flush_en,
+  input  wire [31:0]       flush_timeout,
+  output wire              flush_active,
+  output wire              flush_done
+);
+
+  axis_packet_flush #(
+    .WIDTH(CHDR_W), .FLUSH_PARTIAL_PKTS(0), .TIMEOUT_W(32), .PIPELINE("OUT")
+  ) chdr_flusher_i (
+    .clk(axis_chdr_clk), .reset(axis_chdr_rst),
+    .enable(flush_en), .timeout(flush_timeout),
+    .flushing(flush_active), .done(flush_done),
+    .s_axis_tdata(s_axis_chdr_tdata), .s_axis_tlast(s_axis_chdr_tlast),
+    .s_axis_tvalid(s_axis_chdr_tvalid), .s_axis_tready(s_axis_chdr_tready),
+    .m_axis_tdata(m_axis_chdr_tdata), .m_axis_tlast(m_axis_chdr_tlast),
+    .m_axis_tvalid(m_axis_chdr_tvalid), .m_axis_tready(m_axis_chdr_tready)
+  );
+
+endmodule // chdr_to_chdr_data
diff --git a/fpga/usrp3/lib/rfnoc/core/ctrlport.vh b/fpga/usrp3/lib/rfnoc/core/ctrlport.vh
new file mode 100644
index 000000000..7b5f9fcaa
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/core/ctrlport.vh
@@ -0,0 +1,26 @@
+//
+// Copyright 2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: ctrlport.vh
+// Description:
+// Defines constants for the control port interface.
+//
+// Requires rfnoc_axis_ctrl_utils.vh in same directory to be
+// included first.
+
+//---------------------------------------------------------------
+// Signal widths
+//---------------------------------------------------------------
+localparam CTRLPORT_ADDR_W = 20;
+localparam CTRLPORT_DATA_W = 32;
+localparam CTRLPORT_STS_W  =  2;
+
+//---------------------------------------------------------------
+// Status values
+//---------------------------------------------------------------
+localparam [1:0] CTRL_STS_OKAY    = 2'b00;
+localparam [1:0] CTRL_STS_CMDERR  = 2'b01;
+localparam [1:0] CTRL_STS_TSERR   = 2'b10;
+localparam [1:0] CTRL_STS_WARNING = 2'b11;
diff --git a/fpga/usrp3/lib/rfnoc/core/ctrlport_endpoint.v b/fpga/usrp3/lib/rfnoc/core/ctrlport_endpoint.v
new file mode 100644
index 000000000..4a7d7302a
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/core/ctrlport_endpoint.v
@@ -0,0 +1,284 @@
+//
+// Copyright 2018-2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: ctrlport_endpoint
+// Description:
+//   A bidirectional AXIS-Control to Control-Port converter.
+//   Use this module in noc_shell to interface between the user
+//   logic (using ctrlport) and the rfnoc infrastructure (axis_ctrl)
+//
+// Parameters:
+//   - THIS_PORTID: The 10-bit ID of the control XB port that is
+//                  connected to this converter.
+//   - SYNC_CLKS: Is rfnoc_ctrl_clk and ctrlport_clk the same clock?
+//   - AXIS_CTRL_MST_EN: Enable an AXIS-Ctrl master
+//   - AXIS_CTRL_SLV_EN: Enable an AXIS-Ctrl slave
+//   - SLAVE_FIFO_SIZE: FIFO depth for the slave port
+//
+// Signals:
+//   - *_rfnoc_ctrl_* : Input/output AXIS-Control stream (AXI-Stream)
+//   - *_ctrlport_*   : Input/output control-port bus
+
+module ctrlport_endpoint #(
+  parameter [9:0] THIS_PORTID       = 10'd0,
+  parameter       SYNC_CLKS         = 0,
+  parameter [0:0] AXIS_CTRL_MST_EN  = 1,
+  parameter [0:0] AXIS_CTRL_SLV_EN  = 1,
+  parameter       SLAVE_FIFO_SIZE   = 5
+)(
+  // Clocks, Resets, Misc
+  input  wire         rfnoc_ctrl_clk,
+  input  wire         rfnoc_ctrl_rst,
+  input  wire         ctrlport_clk,
+  input  wire         ctrlport_rst,
+  // AXIS-Control Bus
+  input  wire [31:0]  s_rfnoc_ctrl_tdata,
+  input  wire         s_rfnoc_ctrl_tlast,
+  input  wire         s_rfnoc_ctrl_tvalid,
+  output wire         s_rfnoc_ctrl_tready,
+  output wire [31:0]  m_rfnoc_ctrl_tdata,
+  output wire         m_rfnoc_ctrl_tlast,
+  output wire         m_rfnoc_ctrl_tvalid,
+  input  wire         m_rfnoc_ctrl_tready,
+  // Control Port Master (Request)
+  output wire         m_ctrlport_req_wr,
+  output wire         m_ctrlport_req_rd,
+  output wire [19:0]  m_ctrlport_req_addr,
+  output wire [31:0]  m_ctrlport_req_data,
+  output wire [3:0]   m_ctrlport_req_byte_en,
+  output wire         m_ctrlport_req_has_time,
+  output wire [63:0]  m_ctrlport_req_time,
+  // Control Port Master (Response)
+  input  wire         m_ctrlport_resp_ack,
+  input  wire [1:0]   m_ctrlport_resp_status,
+  input  wire [31:0]  m_ctrlport_resp_data,
+  // Control Port Slave (Request)
+  input  wire         s_ctrlport_req_wr,
+  input  wire         s_ctrlport_req_rd,
+  input  wire [19:0]  s_ctrlport_req_addr,
+  input  wire [9:0]   s_ctrlport_req_portid,
+  input  wire [15:0]  s_ctrlport_req_rem_epid,
+  input  wire [9:0]   s_ctrlport_req_rem_portid,
+  input  wire [31:0]  s_ctrlport_req_data,
+  input  wire [3:0]   s_ctrlport_req_byte_en,
+  input  wire         s_ctrlport_req_has_time,
+  input  wire [63:0]  s_ctrlport_req_time,
+  // Control Port Slave (Response)
+  output wire         s_ctrlport_resp_ack,
+  output wire [1:0]   s_ctrlport_resp_status,
+  output wire [31:0]  s_ctrlport_resp_data
+);
+
+  // ---------------------------------------------------
+  //  RFNoC Includes
+  // ---------------------------------------------------
+  `include "rfnoc_chdr_utils.vh"
+  `include "rfnoc_axis_ctrl_utils.vh"
+
+  // ---------------------------------------------------
+  //  Clock Crossing
+  // ---------------------------------------------------
+
+  wire [31:0] i_ctrl_tdata,  o_ctrl_tdata;
+  wire        i_ctrl_tlast,  o_ctrl_tlast;
+  wire        i_ctrl_tvalid, o_ctrl_tvalid;
+  wire        i_ctrl_tready, o_ctrl_tready;
+
+  generate
+    if (SYNC_CLKS) begin : gen_sync_fifos
+      axi_fifo #(.WIDTH(32+1), .SIZE(1)) in_fifo_i (
+        .clk(ctrlport_clk), .reset(ctrlport_rst), .clear(1'b0),
+        .i_tdata({s_rfnoc_ctrl_tlast, s_rfnoc_ctrl_tdata}),
+        .i_tvalid(s_rfnoc_ctrl_tvalid), .i_tready(s_rfnoc_ctrl_tready),
+        .o_tdata({i_ctrl_tlast, i_ctrl_tdata}),
+        .o_tvalid(i_ctrl_tvalid), .o_tready(i_ctrl_tready),
+        .space(), .occupied()
+      );
+
+      axi_fifo #(.WIDTH(32+1), .SIZE(1)) out_fifo_i (
+        .clk(ctrlport_clk), .reset(ctrlport_rst), .clear(1'b0),
+        .i_tdata({o_ctrl_tlast, o_ctrl_tdata}),
+        .i_tvalid(o_ctrl_tvalid), .i_tready(o_ctrl_tready),
+        .o_tdata({m_rfnoc_ctrl_tlast, m_rfnoc_ctrl_tdata}),
+        .o_tvalid(m_rfnoc_ctrl_tvalid), .o_tready(m_rfnoc_ctrl_tready),
+        .space(), .occupied()
+      );
+    end else begin : gen_async_fifos
+      axi_fifo_2clk #(.WIDTH(32+1), .SIZE(1), .PIPELINE("IN")) in_fifo_i (
+        .reset(rfnoc_ctrl_rst),
+        .i_aclk(rfnoc_ctrl_clk),
+        .i_tdata({s_rfnoc_ctrl_tlast, s_rfnoc_ctrl_tdata}),
+        .i_tvalid(s_rfnoc_ctrl_tvalid), .i_tready(s_rfnoc_ctrl_tready),
+        .o_aclk(ctrlport_clk),
+        .o_tdata({i_ctrl_tlast, i_ctrl_tdata}),
+        .o_tvalid(i_ctrl_tvalid), .o_tready(i_ctrl_tready)
+      );
+
+      axi_fifo_2clk #(.WIDTH(32+1), .SIZE(1), .PIPELINE("OUT")) out_fifo_i (
+        .reset(ctrlport_rst),
+        .i_aclk(ctrlport_clk),
+        .i_tdata({o_ctrl_tlast, o_ctrl_tdata}),
+        .i_tvalid(o_ctrl_tvalid), .i_tready(o_ctrl_tready),
+        .o_aclk(rfnoc_ctrl_clk),
+        .o_tdata({m_rfnoc_ctrl_tlast, m_rfnoc_ctrl_tdata}),
+        .o_tvalid(m_rfnoc_ctrl_tvalid), .o_tready(m_rfnoc_ctrl_tready)
+      );
+
+    end
+  endgenerate
+
+  // ---------------------------------------------------
+  //  MUXING
+  // ---------------------------------------------------
+  wire [31:0] mst_req_tdata,  mst_resp_tdata ;
+  wire        mst_req_tlast,  mst_resp_tlast ;
+  wire        mst_req_tvalid, mst_resp_tvalid;
+  wire        mst_req_tready, mst_resp_tready;
+
+  wire [31:0] slv_req_tdata,  slv_req_fifo_tdata,  slv_resp_tdata ;
+  wire        slv_req_tlast,  slv_req_fifo_tlast,  slv_resp_tlast ;
+  wire        slv_req_tvalid, slv_req_fifo_tvalid, slv_resp_tvalid;
+  wire        slv_req_tready, slv_req_fifo_tready, slv_resp_tready;
+
+  generate
+    if (AXIS_CTRL_MST_EN == 1'b1 && AXIS_CTRL_SLV_EN == 1'b1) begin : gen_mst_slv_muxing
+      wire [31:0] in_hdr;
+      axi_demux #(
+        .WIDTH(32), .SIZE(2), .PRE_FIFO_SIZE(0), .POST_FIFO_SIZE(0)
+      ) demux_i (
+        .clk(ctrlport_clk), .reset(ctrlport_rst), .clear(1'b0),
+        .header(in_hdr), .dest(axis_ctrl_get_is_ack(in_hdr)),
+        .i_tdata (i_ctrl_tdata ),
+        .i_tlast (i_ctrl_tlast ),
+        .i_tvalid(i_ctrl_tvalid),
+        .i_tready(i_ctrl_tready),
+        .o_tdata ({mst_resp_tdata,  slv_req_tdata }),
+        .o_tlast ({mst_resp_tlast,  slv_req_tlast }),
+        .o_tvalid({mst_resp_tvalid, slv_req_tvalid}),
+        .o_tready({mst_resp_tready, slv_req_tready})
+      );
+
+      axi_mux #(
+        .WIDTH(32), .SIZE(2), .PRIO(0), .PRE_FIFO_SIZE(0), .POST_FIFO_SIZE(0)
+      ) mux_i (
+        .clk(ctrlport_clk), .reset(ctrlport_rst), .clear(1'b0),
+        .i_tdata ({mst_req_tdata,  slv_resp_tdata }),
+        .i_tlast ({mst_req_tlast,  slv_resp_tlast }),
+        .i_tvalid({mst_req_tvalid, slv_resp_tvalid}),
+        .i_tready({mst_req_tready, slv_resp_tready}),
+        .o_tdata (o_ctrl_tdata ),
+        .o_tlast (o_ctrl_tlast ),
+        .o_tvalid(o_ctrl_tvalid),
+        .o_tready(o_ctrl_tready)
+      );
+
+    end else if (AXIS_CTRL_MST_EN == 1'b1) begin : gen_mst_muxing
+
+      assign mst_resp_tdata  = i_ctrl_tdata;
+      assign mst_resp_tlast  = i_ctrl_tlast;
+      assign mst_resp_tvalid = i_ctrl_tvalid;
+      assign i_ctrl_tready   = mst_resp_tready;
+
+      assign o_ctrl_tdata    = mst_req_tdata;
+      assign o_ctrl_tlast    = mst_req_tlast;
+      assign o_ctrl_tvalid   = mst_req_tvalid;
+      assign mst_req_tready  = o_ctrl_tready;
+
+    end else begin : gen_no_mst_muxing
+
+      assign slv_req_tdata   = i_ctrl_tdata;
+      assign slv_req_tlast   = i_ctrl_tlast;
+      assign slv_req_tvalid  = i_ctrl_tvalid;
+      assign i_ctrl_tready   = slv_req_tready;
+
+      assign o_ctrl_tdata    = slv_resp_tdata;
+      assign o_ctrl_tlast    = slv_resp_tlast;
+      assign o_ctrl_tvalid   = slv_resp_tvalid;
+      assign slv_resp_tready = o_ctrl_tready;
+
+    end
+  endgenerate
+
+  // ---------------------------------------------------
+  //  AXIS Control Master and Slave
+  // ---------------------------------------------------
+
+  generate
+    if (AXIS_CTRL_MST_EN == 1'b1) begin : gen_ctrl_master
+      axis_ctrl_master #( .THIS_PORTID(THIS_PORTID) ) axis_ctrl_mst_i (
+        .clk                    (ctrlport_clk),
+        .rst                    (ctrlport_rst),
+        .s_axis_ctrl_tdata      (mst_resp_tdata),
+        .s_axis_ctrl_tlast      (mst_resp_tlast),
+        .s_axis_ctrl_tvalid     (mst_resp_tvalid),
+        .s_axis_ctrl_tready     (mst_resp_tready),
+        .m_axis_ctrl_tdata      (mst_req_tdata),
+        .m_axis_ctrl_tlast      (mst_req_tlast),
+        .m_axis_ctrl_tvalid     (mst_req_tvalid),
+        .m_axis_ctrl_tready     (mst_req_tready),
+        .ctrlport_req_wr        (s_ctrlport_req_wr),
+        .ctrlport_req_rd        (s_ctrlport_req_rd),
+        .ctrlport_req_addr      (s_ctrlport_req_addr),
+        .ctrlport_req_portid    (s_ctrlport_req_portid),
+        .ctrlport_req_rem_epid  (s_ctrlport_req_rem_epid),
+        .ctrlport_req_rem_portid(s_ctrlport_req_rem_portid),
+        .ctrlport_req_data      (s_ctrlport_req_data),
+        .ctrlport_req_byte_en   (s_ctrlport_req_byte_en),
+        .ctrlport_req_has_time  (s_ctrlport_req_has_time),
+        .ctrlport_req_time      (s_ctrlport_req_time),
+        .ctrlport_resp_ack      (s_ctrlport_resp_ack),
+        .ctrlport_resp_status   (s_ctrlport_resp_status),
+        .ctrlport_resp_data     (s_ctrlport_resp_data)
+      );
+    end else begin : gen_no_ctrl_master
+      assign mst_resp_tready = 1'b1;
+      assign mst_req_tlast = 1'b0;
+      assign mst_req_tvalid = 1'b0;
+      assign s_ctrlport_resp_ack = 1'b0;
+    end
+
+    if (AXIS_CTRL_SLV_EN == 1'b1) begin : gen_ctrl_slave
+      axi_fifo #(.WIDTH(32+1), .SIZE(SLAVE_FIFO_SIZE)) slv_fifo_i (
+        .clk(ctrlport_clk), .reset(ctrlport_rst), .clear(1'b0),
+        .i_tdata({slv_req_tlast, slv_req_tdata}),
+        .i_tvalid(slv_req_tvalid), .i_tready(slv_req_tready),
+        .o_tdata({slv_req_fifo_tlast, slv_req_fifo_tdata}),
+        .o_tvalid(slv_req_fifo_tvalid), .o_tready(slv_req_fifo_tready),
+        .space(), .occupied()
+      );
+
+      axis_ctrl_slave axis_ctrl_slv_i (
+        .clk                  (ctrlport_clk),
+        .rst                  (ctrlport_rst),
+        .s_axis_ctrl_tdata    (slv_req_fifo_tdata),
+        .s_axis_ctrl_tlast    (slv_req_fifo_tlast),
+        .s_axis_ctrl_tvalid   (slv_req_fifo_tvalid),
+        .s_axis_ctrl_tready   (slv_req_fifo_tready),
+        .m_axis_ctrl_tdata    (slv_resp_tdata),
+        .m_axis_ctrl_tlast    (slv_resp_tlast),
+        .m_axis_ctrl_tvalid   (slv_resp_tvalid),
+        .m_axis_ctrl_tready   (slv_resp_tready),
+        .ctrlport_req_wr      (m_ctrlport_req_wr),
+        .ctrlport_req_rd      (m_ctrlport_req_rd),
+        .ctrlport_req_addr    (m_ctrlport_req_addr),
+        .ctrlport_req_data    (m_ctrlport_req_data),
+        .ctrlport_req_byte_en (m_ctrlport_req_byte_en),
+        .ctrlport_req_has_time(m_ctrlport_req_has_time),
+        .ctrlport_req_time    (m_ctrlport_req_time),
+        .ctrlport_resp_ack    (m_ctrlport_resp_ack),
+        .ctrlport_resp_status (m_ctrlport_resp_status),
+        .ctrlport_resp_data   (m_ctrlport_resp_data)
+      );
+    end else begin : gen_no_ctrl_slave
+      assign slv_req_fifo_tready = 1'b1;
+      assign slv_resp_tlast = 1'b0;
+      assign slv_resp_tvalid = 1'b0;
+      assign m_ctrlport_req_wr = 1'b0;
+      assign m_ctrlport_req_rd = 1'b0;
+    end
+  endgenerate
+
+endmodule // ctrlport_endpoint
+
diff --git a/fpga/usrp3/lib/rfnoc/core/rfnoc_axis_ctrl_utils.vh b/fpga/usrp3/lib/rfnoc/core/rfnoc_axis_ctrl_utils.vh
new file mode 100644
index 000000000..5c3dab8ac
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/core/rfnoc_axis_ctrl_utils.vh
@@ -0,0 +1,154 @@
+//
+// Copyright 2018 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+// =============================================================
+//  AXIS-Ctrl Bitfields
+// =============================================================
+
+// -----------------------
+//  Line 0: HDR_0
+// -----------------------
+// Bits     Name          Meaning
+// ----     ----          -------
+// 31       is_ack        Is this an acknowledgment to a transaction?
+// 30       has_time      Does the transaction have a timestamp?
+// 29:24    seq_num       Sequence number
+// 23:20    num_data      Number of data words
+// 19:10    src_port      Ctrl XB port that the source block is on 
+// 9:0      dst_port      Ctrl XB port that the destination block is on 
+
+// -----------------------
+//  Line 1: HDR_1
+// -----------------------
+// Bits     Name          Meaning
+// ----     ----          -------
+// 31:26    <Reserved>
+// 25:16    rem_dst_port  Ctrl XB port that the remote dest block is on
+// 15:0     rem_dst_epid  Endpoint ID of the remote dest of this msg
+
+// -----------------------
+//  Line 2: TS_LO (Optional)
+// -----------------------
+// Bits     Name       Meaning
+// ----     ----       -------
+// 31:0     timestamp  Lower 32 bits of the timestamp
+
+// -----------------------
+//  Line 3: TS_HI (Optional)
+// -----------------------
+// Bits     Name       Meaning
+// ----     ----       -------
+// 31:0     timestamp  Upper 32 bits of the timestamp
+
+// -----------------------
+//  Line 4: OP Word
+// -----------------------
+// Bits     Name       Meaning
+// ----     ----       -------
+// 31:30    status     The status of the ack
+// 29:28    <Reserved>
+// 27:24    opcode     Operation Code
+// 23:20    byte_en    Byte enable strobe
+// 19:0     address    Address for transaction
+
+// AXIS-Ctrl Status
+//
+localparam [1:0] AXIS_CTRL_STS_OKAY    = 2'b00;
+localparam [1:0] AXIS_CTRL_STS_CMDERR  = 2'b01;
+localparam [1:0] AXIS_CTRL_STS_TSERR   = 2'b10;
+localparam [1:0] AXIS_CTRL_STS_WARNING = 2'b11;
+
+// AXIS-Ctrl Opcode Definitions
+//
+localparam [3:0] AXIS_CTRL_OPCODE_SLEEP      = 4'd0;
+localparam [3:0] AXIS_CTRL_OPCODE_WRITE      = 4'd1;
+localparam [3:0] AXIS_CTRL_OPCODE_READ       = 4'd2;
+localparam [3:0] AXIS_CTRL_OPCODE_WRITE_READ = 4'd3;
+
+// AXIS-Ctrl Getter Functions
+//
+function [0:0] axis_ctrl_get_is_ack(input [31:0] header);
+  axis_ctrl_get_is_ack = header[31];
+endfunction
+
+function [0:0] axis_ctrl_get_has_time(input [31:0] header);
+  axis_ctrl_get_has_time = header[30];
+endfunction
+
+function [5:0] axis_ctrl_get_seq_num(input [31:0] header);
+  axis_ctrl_get_seq_num = header[29:24];
+endfunction
+
+function [3:0] axis_ctrl_get_num_data(input [31:0] header);
+  axis_ctrl_get_num_data = header[23:20];
+endfunction
+
+function [9:0] axis_ctrl_get_src_port(input [31:0] header);
+  axis_ctrl_get_src_port = header[19:10];
+endfunction
+
+function [9:0] axis_ctrl_get_dst_port(input [31:0] header);
+  axis_ctrl_get_dst_port = header[9:0];
+endfunction
+
+function [15:0] axis_ctrl_get_rem_dst_epid(input [31:0] header);
+  axis_ctrl_get_rem_dst_epid = header[15:0];
+endfunction
+
+function [9:0] axis_ctrl_get_rem_dst_port(input [31:0] header);
+  axis_ctrl_get_rem_dst_port = header[25:16];
+endfunction
+
+function [1:0] axis_ctrl_get_status(input [31:0] header);
+  axis_ctrl_get_status = header[31:30];
+endfunction
+
+function [3:0] axis_ctrl_get_opcode(input [31:0] header);
+  axis_ctrl_get_opcode = header[27:24];
+endfunction
+
+function [3:0] axis_ctrl_get_byte_en(input [31:0] header);
+  axis_ctrl_get_byte_en = header[23:20];
+endfunction
+
+function [19:0] axis_ctrl_get_address(input [31:0] header);
+  axis_ctrl_get_address = header[19:0];
+endfunction
+
+// AXIS-Ctrl Setter Functions
+//
+function [31:0] axis_ctrl_build_hdr_lo(
+  input [0:0]  is_ack,
+  input [0:0]  has_time,
+  input [5:0]  seq_num,
+  input [3:0]  num_data,
+  input [9:0]  src_port,
+  input [9:0]  dst_port
+);
+  axis_ctrl_build_hdr_lo = {is_ack, has_time, seq_num, num_data, src_port, dst_port};
+endfunction
+
+function [31:0] axis_ctrl_build_hdr_hi(
+  input [9:0]  rem_dst_port,
+  input [15:0] rem_dst_epid
+);
+  axis_ctrl_build_hdr_hi = {6'h0, rem_dst_port, rem_dst_epid};
+endfunction
+
+function [31:0] chdr_ctrl_build_hdr_hi(
+  input [15:0] src_epid
+);
+  chdr_ctrl_build_hdr_hi = {16'h0, src_epid};
+endfunction
+
+function [31:0] axis_ctrl_build_op_word(
+  input [1:0]  status,
+  input [3:0]  opcode,
+  input [3:0]  byte_en,
+  input [19:0] address
+);
+  axis_ctrl_build_op_word = {status, 2'b00, opcode, byte_en, address};
+endfunction
diff --git a/fpga/usrp3/lib/rfnoc/core/rfnoc_backend_iface.vh b/fpga/usrp3/lib/rfnoc/core/rfnoc_backend_iface.vh
new file mode 100644
index 000000000..ec5c152f6
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/core/rfnoc_backend_iface.vh
@@ -0,0 +1,52 @@
+//
+// Copyright 2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+// Each block has a backed interface that is 512 bits wide. This bus
+// is split into 16 32-bit registers to it is preferable to have fields
+// aligned at 32-bit boundaries
+
+// Backend Config
+localparam BEC_FLUSH_TIMEOUT_OFFSET = 0;
+localparam BEC_FLUSH_TIMEOUT_WIDTH  = 32;
+localparam BEC_FLUSH_EN_OFFSET      = BEC_FLUSH_TIMEOUT_OFFSET + BEC_FLUSH_TIMEOUT_WIDTH;
+localparam BEC_FLUSH_EN_WIDTH       = 1;
+localparam BEC_SOFT_CTRL_RST_OFFSET = BEC_FLUSH_EN_OFFSET + BEC_FLUSH_EN_WIDTH;
+localparam BEC_SOFT_CTRL_RST_WIDTH  = 1;
+localparam BEC_SOFT_CHDR_RST_OFFSET = BEC_SOFT_CTRL_RST_OFFSET + BEC_SOFT_CTRL_RST_WIDTH;
+localparam BEC_SOFT_CHDR_RST_WIDTH  = 1;
+localparam BEC_TOTAL_WIDTH          = BEC_SOFT_CHDR_RST_OFFSET + BEC_SOFT_CHDR_RST_WIDTH;
+
+localparam [511:0] BEC_DEFAULT_VAL = {
+  {(512-BEC_TOTAL_WIDTH){1'b0}},
+  1'b1,     // BEC_SOFT_CHDR_RST
+  1'b1,     // BEC_SOFT_CTRL_RST
+  1'b0,     // BEC_FLUSH_EN
+  32'd0     // BEC_FLUSH_TIMEOUT
+};
+
+// Backend Status
+localparam BES_PROTO_VER_OFFSET           = 0;
+localparam BES_PROTO_VER_WIDTH            = 6;
+localparam BES_NUM_DATA_I_OFFSET          = BES_PROTO_VER_OFFSET + BES_PROTO_VER_WIDTH;
+localparam BES_NUM_DATA_I_WIDTH           = 6;
+localparam BES_NUM_DATA_O_OFFSET          = BES_NUM_DATA_I_OFFSET + BES_NUM_DATA_I_WIDTH;
+localparam BES_NUM_DATA_O_WIDTH           = 6;
+localparam BES_CTRL_FIFOSIZE_OFFSET       = BES_NUM_DATA_O_OFFSET + BES_NUM_DATA_O_WIDTH;
+localparam BES_CTRL_FIFOSIZE_WIDTH        = 6;
+localparam BES_CTRL_MAX_ASYNC_MSGS_OFFSET = BES_CTRL_FIFOSIZE_OFFSET + BES_CTRL_FIFOSIZE_WIDTH;
+localparam BES_CTRL_MAX_ASYNC_MSGS_WIDTH  = 8;
+localparam BES_NOC_ID_OFFSET              = BES_CTRL_MAX_ASYNC_MSGS_OFFSET + BES_CTRL_MAX_ASYNC_MSGS_WIDTH;
+localparam BES_NOC_ID_WIDTH               = 32;
+localparam BES_FLUSH_ACTIVE_OFFSET        = BES_NOC_ID_OFFSET + BES_NOC_ID_WIDTH;
+localparam BES_FLUSH_ACTIVE_WIDTH         = 1;
+localparam BES_FLUSH_DONE_OFFSET          = BES_FLUSH_ACTIVE_OFFSET + BES_FLUSH_ACTIVE_WIDTH;
+localparam BES_FLUSH_DONE_WIDTH           = 1;
+localparam BES_DATA_MTU_OFFSET            = BES_FLUSH_DONE_OFFSET + BES_FLUSH_DONE_WIDTH;
+localparam BES_DATA_MTU_WIDTH             = 6;
+localparam BES_TOTAL_WIDTH                = BES_DATA_MTU_OFFSET + BES_DATA_MTU_WIDTH;
+
+// Protocol version for this definition
+localparam [5:0] BACKEND_PROTO_VER  = 6'd1;
\ No newline at end of file
diff --git a/fpga/usrp3/lib/rfnoc/core/rfnoc_chdr_internal_utils.vh b/fpga/usrp3/lib/rfnoc/core/rfnoc_chdr_internal_utils.vh
new file mode 100644
index 000000000..1d70c0f1c
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/core/rfnoc_chdr_internal_utils.vh
@@ -0,0 +1,452 @@
+//
+// Copyright 2018 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+// =============================================================
+//  Stream Status Bitfields
+// =============================================================
+
+// -----------------------
+//  Line 0
+// -----------------------
+// Bits     Name            Meaning
+// ----     ----            -------
+// 63:24    capacity_bytes  Downstream buffer capacity in bytes
+// 23:20    <reserved>
+// 19:16    status          Stream status code (enumeration)
+// 15:0     src_epid        Endpoint ID of the source of this msg
+
+// -----------------------
+//  Line 1
+// -----------------------
+// Bits     Name            Meaning
+// ----     ----            -------
+// 63:24    xfercnt_pkts    Transfer count in packets
+// 23:0     capacity_pkts   Downstream buffer capacity in packets
+
+// -----------------------
+//  Line 2
+// -----------------------
+// Bits     Name            Meaning
+// ----     ----            -------
+// 63:0     xfercnt_bytes   Transfer count in bytes
+
+// -----------------------
+//  Line 3
+// -----------------------
+// Bits     Name            Meaning
+// ----     ----            -------
+// 63:16    status_info     Extended information about status (diagnostic only)
+// 15:0     buff_info       Extended information about buffer state (diagnostic only)
+
+localparam [3:0] CHDR_STRS_STATUS_OKAY    = 4'd0; // No error
+localparam [3:0] CHDR_STRS_STATUS_CMDERR  = 4'd1; // Cmd execution failed
+localparam [3:0] CHDR_STRS_STATUS_SEQERR  = 4'd2; // Sequence number discontinuity
+localparam [3:0] CHDR_STRS_STATUS_DATAERR = 4'd3; // Data integrity check failed
+localparam [3:0] CHDR_STRS_STATUS_RTERR   = 4'd4; // Unexpected destination
+
+// 64-bit fields
+function [39:0] chdr64_strs_get_capacity_bytes(input [63:0] header);
+  chdr64_strs_get_capacity_bytes = header[63:24];
+endfunction
+
+function [3:0] chdr64_strs_get_status(input [63:0] header);
+  chdr64_strs_get_status = header[19:16];
+endfunction
+
+function [15:0] chdr64_strs_get_src_epid(input [63:0] header);
+  chdr64_strs_get_src_epid = header[15:0];
+endfunction
+
+function [39:0] chdr64_strs_get_xfercnt_pkts(input [63:0] header);
+  chdr64_strs_get_xfercnt_pkts = header[63:24];
+endfunction
+
+function [23:0] chdr64_strs_get_capacity_pkts(input [63:0] header);
+  chdr64_strs_get_capacity_pkts = header[23:0];
+endfunction
+
+function [63:0] chdr64_strs_get_xfercnt_bytes(input [63:0] header);
+  chdr64_strs_get_xfercnt_bytes = header[63:0];
+endfunction
+
+function [47:0] chdr64_strs_get_status_info(input [63:0] header);
+  chdr64_strs_get_status_info = header[63:16];
+endfunction
+
+function [15:0] chdr64_strs_get_buff_info(input [63:0] header);
+  chdr64_strs_get_buff_info = header[15:0];
+endfunction
+
+
+// 128-bit fields
+function [39:0] chdr128_strs_get_capacity_bytes(input [127:0] header);
+  chdr128_strs_get_capacity_bytes = chdr64_strs_get_capacity_bytes(header[63:0]);
+endfunction
+
+function [3:0] chdr128_strs_get_status(input [127:0] header);
+  chdr128_strs_get_status = chdr64_strs_get_status(header[63:0]);
+endfunction
+
+function [15:0] chdr128_strs_get_src_epid(input [127:0] header);
+  chdr128_strs_get_src_epid = chdr64_strs_get_src_epid(header[63:0]);
+endfunction
+
+function [23:0] chdr128_strs_get_capacity_pkts(input [127:0] header);
+  chdr128_strs_get_capacity_pkts = chdr64_strs_get_capacity_pkts(header[127:64]);
+endfunction
+
+function [39:0] chdr128_strs_get_xfercnt_pkts(input [127:0] header);
+  chdr128_strs_get_xfercnt_pkts = chdr64_strs_get_xfercnt_pkts(header[127:64]);
+endfunction
+
+function [63:0] chdr128_strs_get_xfercnt_bytes(input [127:0] header);
+  chdr128_strs_get_xfercnt_bytes = chdr64_strs_get_xfercnt_bytes(header[63:0]);
+endfunction
+
+function [47:0] chdr128_strs_get_status_info(input [127:0] header);
+  chdr128_strs_get_status_info = chdr64_strs_get_status_info(header[127:64]);
+endfunction
+
+function [15:0] chdr128_strs_get_buff_info(input [127:0] header);
+  chdr128_strs_get_buff_info = chdr64_strs_get_buff_info(header[127:64]);
+endfunction
+
+
+// 256-bit fields
+function [39:0] chdr256_strs_get_capacity_bytes(input [255:0] header);
+  chdr256_strs_get_capacity_bytes = chdr64_strs_get_capacity_bytes(header[63:0]);
+endfunction
+
+function [3:0] chdr256_strs_get_status(input [255:0] header);
+  chdr256_strs_get_status = chdr64_strs_get_status(header[63:0]);
+endfunction
+
+function [15:0] chdr256_strs_get_src_epid(input [255:0] header);
+  chdr256_strs_get_src_epid = chdr64_strs_get_src_epid(header[63:0]);
+endfunction
+
+function [23:0] chdr256_strs_get_capacity_pkts(input [255:0] header);
+  chdr256_strs_get_capacity_pkts = chdr64_strs_get_capacity_pkts(header[127:64]);
+endfunction
+
+function [39:0] chdr256_strs_get_xfercnt_pkts(input [255:0] header);
+  chdr256_strs_get_xfercnt_pkts = chdr64_strs_get_xfercnt_pkts(header[127:64]);
+endfunction
+
+function [63:0] chdr256_strs_get_xfercnt_bytes(input [255:0] header);
+  chdr256_strs_get_xfercnt_bytes = chdr64_strs_get_xfercnt_bytes(header[191:128]);
+endfunction
+
+function [47:0] chdr256_strs_get_status_info(input [255:0] header);
+  chdr256_strs_get_status_info = chdr64_strs_get_status_info(header[255:192]);
+endfunction
+
+function [15:0] chdr256_strs_get_buff_info(input [255:0] header);
+  chdr256_strs_get_buff_info = chdr64_strs_get_buff_info(header[255:192]);
+endfunction
+
+// Stream Status Setter Functions
+//
+
+// 64-bit fields
+function [63:0] chdr64_strs_build_w0(
+  input [39:0] capacity_bytes,
+  input [3:0]  status,
+  input [15:0] src_epid
+);
+  chdr64_strs_build_w0 = {capacity_bytes, 4'h0, status, src_epid};
+endfunction
+
+function [63:0] chdr64_strs_build_w1(
+  input [39:0] xfercnt_pkts,
+  input [23:0] capacity_pkts
+);
+  chdr64_strs_build_w1 = {xfercnt_pkts, capacity_pkts};
+endfunction
+
+function [63:0] chdr64_strs_build_w2(
+  input [63:0] xfercnt_bytes
+);
+  chdr64_strs_build_w2 = xfercnt_bytes;
+endfunction
+
+function [63:0] chdr64_strs_build_w3(
+  input [47:0] status_info,
+  input [15:0] buff_info
+);
+  chdr64_strs_build_w3 = {status_info, buff_info};
+endfunction
+
+// 128-bit fields
+function [127:0] chdr128_strs_build_w0(
+  input [39:0] xfercnt_pkts,
+  input [23:0] capacity_pkts,
+  input [39:0] capacity_bytes,
+  input [3:0]  status,
+  input [15:0] src_epid
+);
+  chdr128_strs_build_w0 = {
+    chdr64_strs_build_w1(xfercnt_pkts, capacity_pkts),
+    chdr64_strs_build_w0(capacity_bytes, status, src_epid)};
+endfunction
+
+function [127:0] chdr128_strs_build_w1(
+  input [47:0] status_info,
+  input [15:0] buff_info,
+  input [63:0] xfercnt_bytes
+);
+  chdr128_strs_build_w1 = {
+    chdr64_strs_build_w3(status_info, buff_info),
+    chdr64_strs_build_w2(xfercnt_bytes)};
+endfunction
+
+// 256-bit fields
+function [255:0] chdr256_strs_build(
+  input [47:0] status_info,
+  input [15:0] buff_info,
+  input [63:0] xfercnt_bytes,
+  input [39:0] xfercnt_pkts,
+  input [23:0] capacity_pkts,
+  input [39:0] capacity_bytes,
+  input [3:0]  status,
+  input [15:0] src_epid
+);
+  chdr256_strs_build = {
+    chdr64_strs_build_w3(status_info, buff_info),
+    chdr64_strs_build_w2(xfercnt_bytes),
+    chdr64_strs_build_w1(xfercnt_pkts, capacity_pkts),
+    chdr64_strs_build_w0(capacity_bytes, status, src_epid)};
+endfunction
+
+// =============================================================
+//  Stream Command Bitfields
+// =============================================================
+
+// -----------------------
+//  Line 0
+// -----------------------
+// Bits     Name            Meaning
+// ----     ----            -------
+// 63:24    num_pkts        Downstream buffer capacity in bytes
+// 23:20    op_data         Payload for command
+// 19:16    op_code         Command operation code (enumeration)
+// 15:0     src_epid        Endpoint ID of the source of this msg
+
+// -----------------------
+//  Line 1
+// -----------------------
+// Bits     Name            Meaning
+// ----     ----            -------
+// 63:0     num_bytes       Transfer count in packets
+
+localparam [3:0] CHDR_STRC_OPCODE_INIT    = 4'd0;
+localparam [3:0] CHDR_STRC_OPCODE_PING    = 4'd1;
+localparam [3:0] CHDR_STRC_OPCODE_RESYNC  = 4'd2;
+
+// 64-bit fields
+function [39:0] chdr64_strc_get_num_pkts(input [63:0] header);
+  chdr64_strc_get_num_pkts = header[63:24];
+endfunction
+
+function [3:0] chdr64_strc_get_op_data(input [63:0] header);
+  chdr64_strc_get_op_data = header[23:20];
+endfunction
+
+function [3:0] chdr64_strc_get_op_code(input [63:0] header);
+  chdr64_strc_get_op_code = header[19:16];
+endfunction
+
+function [15:0] chdr64_strc_get_src_epid(input [63:0] header);
+  chdr64_strc_get_src_epid = header[15:0];
+endfunction
+
+function [63:0] chdr64_strc_get_num_bytes(input [63:0] header);
+  chdr64_strc_get_num_bytes = header[63:0];
+endfunction
+
+// 128-bit fields
+function [39:0] chdr128_strc_get_num_pkts(input [127:0] header);
+  chdr128_strc_get_num_pkts = chdr64_strc_get_num_pkts(header[63:0]);
+endfunction
+
+function [3:0] chdr128_strc_get_op_data(input [127:0] header);
+  chdr128_strc_get_op_data = chdr64_strc_get_op_data(header[63:0]);
+endfunction
+
+function [3:0] chdr128_strc_get_op_code(input [127:0] header);
+  chdr128_strc_get_op_code = chdr64_strc_get_op_code(header[63:0]);
+endfunction
+
+function [15:0] chdr128_strc_get_src_epid(input [127:0] header);
+  chdr128_strc_get_src_epid = chdr64_strc_get_src_epid(header[63:0]);
+endfunction
+
+function [63:0] chdr128_strc_get_num_bytes(input [127:0] header);
+  chdr128_strc_get_num_bytes = chdr64_strc_get_num_bytes(header[127:64]);
+endfunction
+
+// Stream Command Setter Functions
+//
+
+// 64-bit fields
+
+function [63:0] chdr64_strc_build_w0(
+  input [39:0] num_pkts,
+  input [3:0]  op_data,
+  input [3:0]  op_code,
+  input [15:0] src_epid
+);
+  chdr64_strc_build_w0 = {num_pkts, op_data, op_code, src_epid};
+endfunction
+
+function [63:0] chdr64_strc_build_w1(
+  input [63:0] num_bytes
+);
+  chdr64_strc_build_w1 = num_bytes;
+endfunction
+
+// 128-bit fields
+function [127:0] chdr128_strc_build(
+  input [63:0] num_bytes,
+  input [39:0] num_pkts,
+  input [3:0]  op_data,
+  input [3:0]  op_code,
+  input [15:0] src_epid
+);
+  chdr128_strc_build = {
+    chdr64_strc_build_w1(num_bytes),
+    chdr64_strc_build_w0(num_pkts, op_data, op_code, src_epid)};
+endfunction
+
+// =============================================================
+//  Management Packet Bitfields
+// =============================================================
+
+// -----------------------
+//  HDR
+// -----------------------
+// Bits     Name          Meaning
+// ----     ----          -------
+// 63:48    proto_ver     Protocol Version
+// 47:45    chdr_w        Bitwidth of the CHDR interface
+// 44:26    <Reserved>
+// 25:16    num_hops      Number of hops that this message will take (TTL)
+// 15:0     src_epid      Endpoint ID of the source of this msg
+
+// -----------------------
+//  OP
+// -----------------------
+// Bits     Name          Meaning
+// ----     ----          -------
+// 63:16    op_payload    Operation Payload
+// 15:8     op_code       Operation code
+// 7:0      ops_pending   Number of operations pending in this hop
+
+localparam [2:0] CHDR_MGMT_WIDTH_64  = 3'd0;
+localparam [2:0] CHDR_MGMT_WIDTH_128 = 3'd1;
+localparam [2:0] CHDR_MGMT_WIDTH_256 = 3'd2;
+localparam [2:0] CHDR_MGMT_WIDTH_512 = 3'd3;
+
+function [2:0] chdr_w_to_enum(input integer bits);
+  if (bits == 512)
+    chdr_w_to_enum = CHDR_MGMT_WIDTH_512;
+  else if (bits == 256)
+    chdr_w_to_enum = CHDR_MGMT_WIDTH_256;
+  else if (bits == 128)
+    chdr_w_to_enum = CHDR_MGMT_WIDTH_128;
+  else
+    chdr_w_to_enum = CHDR_MGMT_WIDTH_64;
+endfunction
+
+localparam [7:0] CHDR_MGMT_OP_NOP         = 8'd0;
+localparam [7:0] CHDR_MGMT_OP_ADVERTISE   = 8'd1;
+localparam [7:0] CHDR_MGMT_OP_SEL_DEST    = 8'd2;
+localparam [7:0] CHDR_MGMT_OP_RETURN      = 8'd3;
+localparam [7:0] CHDR_MGMT_OP_INFO_REQ    = 8'd4;
+localparam [7:0] CHDR_MGMT_OP_INFO_RESP   = 8'd5;
+localparam [7:0] CHDR_MGMT_OP_CFG_WR_REQ  = 8'd6;
+localparam [7:0] CHDR_MGMT_OP_CFG_RD_REQ  = 8'd7;
+localparam [7:0] CHDR_MGMT_OP_CFG_RD_RESP = 8'd8;
+
+function [15:0] chdr_mgmt_get_proto_ver(input [63:0] header);
+  chdr_mgmt_get_proto_ver = header[63:48];
+endfunction
+
+function [2:0] chdr_mgmt_get_chdr_w(input [63:0] header);
+  chdr_mgmt_get_chdr_w = header[47:45];
+endfunction
+
+function [9:0] chdr_mgmt_get_num_hops(input [63:0] header);
+  chdr_mgmt_get_num_hops = header[25:16];
+endfunction
+
+function [15:0] chdr_mgmt_get_src_epid(input [63:0] header);
+  chdr_mgmt_get_src_epid = header[15:0];
+endfunction
+
+function [47:0] chdr_mgmt_get_op_payload(input [63:0] header);
+  chdr_mgmt_get_op_payload = header[63:16];
+endfunction
+
+function [7:0] chdr_mgmt_get_op_code(input [63:0] header);
+  chdr_mgmt_get_op_code = header[15:8];
+endfunction
+
+function [7:0] chdr_mgmt_get_ops_pending(input [63:0] header);
+  chdr_mgmt_get_ops_pending = header[7:0];
+endfunction
+
+function [63:0] chdr_mgmt_build_hdr(
+  input [15:0] proto_ver,
+  input [2:0]  chdr_w,
+  input [9:0]  num_hops,
+  input [15:0] src_epid
+);
+  chdr_mgmt_build_hdr = {proto_ver, chdr_w, 19'h0, num_hops, src_epid};
+endfunction
+
+function [63:0] chdr_mgmt_build_op(
+  input [47:0] op_payload,
+  input [7:0]  op_code,
+  input [7:0]  ops_pending
+);
+  chdr_mgmt_build_op = {op_payload, op_code, ops_pending};
+endfunction
+
+// Definition for the TID field for the output of chdr_mgmt_pkt_handler
+localparam [1:0] CHDR_MGMT_ROUTE_EPID    = 2'd0;  // Route based on EPID
+localparam [1:0] CHDR_MGMT_ROUTE_TDEST   = 2'd1;  // Route based on tdest field
+localparam [1:0] CHDR_MGMT_RETURN_TO_SRC = 2'd2;  // Return packet to sender
+
+// -----------------------
+//  OP specific fields
+// -----------------------
+
+localparam [3:0] NODE_TYPE_INVALID   = 4'd0;
+localparam [3:0] NODE_TYPE_XBAR      = 4'd1;
+localparam [3:0] NODE_TYPE_STREAM_EP = 4'd2;
+localparam [3:0] NODE_TYPE_TRANSPORT = 4'd3;
+
+function [47:0] chdr_mgmt_build_node_info(
+  input [17:0] ext_info,
+  input [9:0]  node_inst,
+  input [3:0]  node_type,
+  input [15:0] device_id
+);
+  chdr_mgmt_build_node_info = {ext_info, node_inst, node_type, device_id};
+endfunction
+
+function [9:0] chdr_mgmt_sel_dest_get_tdest(input [47:0] payload);
+  chdr_mgmt_sel_dest_get_tdest = payload[9:0];
+endfunction
+
+function [15:0] chdr_mgmt_cfg_reg_get_addr(input [47:0] payload);
+  chdr_mgmt_cfg_reg_get_addr = payload[15:0];
+endfunction
+
+function [31:0] chdr_mgmt_cfg_reg_get_data(input [47:0] payload);
+  chdr_mgmt_cfg_reg_get_data = payload[47:16];
+endfunction
diff --git a/fpga/usrp3/lib/rfnoc/core/rfnoc_chdr_utils.vh b/fpga/usrp3/lib/rfnoc/core/rfnoc_chdr_utils.vh
new file mode 100644
index 000000000..047d58bc0
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/core/rfnoc_chdr_utils.vh
@@ -0,0 +1,200 @@
+//
+// Copyright 2018 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+// =============================================================
+//  CHDR Bitfields
+// =============================================================
+//
+// The Condensed Hierarchical Datagram for RFNoC (CHDR) is 
+// a protocol that defines the fundamental unit of data transfer
+// in an RFNoC network. 
+// 
+// -----------------------
+//  Header
+// -----------------------
+// Bits     Name       Meaning
+// ----     ----       -------
+// 63:58    vc         Virtual Channel
+// 57       eob        End of Burst Delimiter
+// 56       eov        End of Vector Delimiter
+// 55:53    pkt_type   Packet Type (enumeration)
+// 52:48    num_mdata  Number of lines of metadata
+// 47:32    seq_num    Sequence number for the packet
+// 31:16    length     Length of the datagram in bytes
+// 15:0     dst_epid   Destination Endpoint ID
+// 
+// Field: Packet Type
+// -----------------------
+// 3'd0     Management
+// 3'd1     Stream Status
+// 3'd2     Stream Command
+// 3'd3     <Reserved>
+// 3'd4     Control Transaction
+// 3'd5     <Reserved>
+// 3'd6     Data (without timestamp)
+// 3'd7     Data (with timestamp)
+//
+
+// Special CHDR Values
+//
+
+// Packet Type
+localparam [2:0] CHDR_PKT_TYPE_MGMT    = 3'd0;
+localparam [2:0] CHDR_PKT_TYPE_STRS    = 3'd1;
+localparam [2:0] CHDR_PKT_TYPE_STRC    = 3'd2;
+//localparam [2:0] RESERVED            = 3'd3;
+localparam [2:0] CHDR_PKT_TYPE_CTRL    = 3'd4;
+//localparam [2:0] RESERVED            = 3'd5;
+localparam [2:0] CHDR_PKT_TYPE_DATA    = 3'd6;
+localparam [2:0] CHDR_PKT_TYPE_DATA_TS = 3'd7;
+
+// Metadata
+localparam [4:0] CHDR_NO_MDATA = 5'd0;
+
+// EPID
+localparam [15:0] NULL_EPID = 16'd0;
+
+// CHDR Getter Functions
+//
+function [5:0] chdr_get_vc(input [63:0] header);
+  chdr_get_vc = header[63:58];
+endfunction
+
+function [0:0] chdr_get_eob(input [63:0] header);
+  chdr_get_eob = header[57];
+endfunction
+
+function [0:0] chdr_get_eov(input [63:0] header);
+  chdr_get_eov = header[56];
+endfunction
+
+function [2:0] chdr_get_pkt_type(input [63:0] header);
+  chdr_get_pkt_type = header[55:53];
+endfunction
+
+function [4:0] chdr_get_num_mdata(input [63:0] header);
+  chdr_get_num_mdata = header[52:48];
+endfunction
+
+function [15:0] chdr_get_seq_num(input [63:0] header);
+  chdr_get_seq_num = header[47:32];
+endfunction
+
+function [15:0] chdr_get_length(input [63:0] header);
+  chdr_get_length = header[31:16];
+endfunction
+
+function [15:0] chdr_get_dst_epid(input [63:0] header);
+  chdr_get_dst_epid = header[15:0];
+endfunction
+
+// CHDR Setter Functions
+//
+function [63:0] chdr_build_header(
+  input [5:0]  vc,
+  input [0:0]  eob,
+  input [0:0]  eov,
+  input [2:0]  pkt_type,
+  input [4:0]  num_mdata,
+  input [15:0] seq_num,
+  input [15:0] length,
+  input [15:0] dst_epid
+);
+  chdr_build_header = {vc, eob, eov, pkt_type, num_mdata, seq_num, length, dst_epid};
+endfunction
+
+function [63:0] chdr_set_vc(
+  input [63:0] base_hdr,
+  input [5:0]  vc
+);
+  chdr_set_vc = {vc, base_hdr[57:0]};
+endfunction
+
+function [63:0] chdr_set_eob(
+  input [63:0] base_hdr,
+  input [0:0]  eob
+);
+  chdr_set_eob = {base_hdr[63:58], eob, base_hdr[56:0]};
+endfunction
+
+function [63:0] chdr_set_eov(
+  input [63:0] base_hdr,
+  input [0:0]  eov
+);
+  chdr_set_eov = {base_hdr[63:57], eov, base_hdr[55:0]};
+endfunction
+
+function [63:0] chdr_set_delims(
+  input [63:0] base_hdr,
+  input [0:0]  eob,
+  input [0:0]  eov
+);
+  chdr_set_delims = {base_hdr[63:58], eob, eov, base_hdr[55:0]};
+endfunction
+
+function [63:0] chdr_set_pkt_type(
+  input [63:0] base_hdr,
+  input [2:0]  pkt_type
+);
+  chdr_set_pkt_type = {base_hdr[63:56], pkt_type, base_hdr[52:0]};
+endfunction
+
+function [63:0] chdr_set_num_mdata(
+  input [63:0] base_hdr,
+  input [4:0]  num_mdata
+);
+  chdr_set_num_mdata = {base_hdr[63:53], num_mdata, base_hdr[47:0]};
+endfunction
+
+function [63:0] chdr_set_seq_num(
+  input [63:0] base_hdr,
+  input [15:0] seq_num
+);
+  chdr_set_seq_num = {base_hdr[63:48], seq_num, base_hdr[31:0]};
+endfunction
+
+function [63:0] chdr_set_length(
+  input [63:0] base_hdr,
+  input [15:0] length
+);
+  chdr_set_length = {base_hdr[63:32], length, base_hdr[15:0]};
+endfunction
+
+function [63:0] chdr_set_dst_epid(
+  input [63:0] base_hdr,
+  input [15:0] dst_epid
+);
+  chdr_set_dst_epid = {base_hdr[63:16], dst_epid};
+endfunction
+
+// =============================================================
+//  Data Packet Specific
+// =============================================================
+
+localparam [3:0] CONTEXT_FIELD_HDR    = 4'd0;
+localparam [3:0] CONTEXT_FIELD_HDR_TS = 4'd1;
+localparam [3:0] CONTEXT_FIELD_TS     = 4'd2;
+localparam [3:0] CONTEXT_FIELD_MDATA  = 4'd3;
+
+function [0:0] chdr_get_has_time(input [63:0] header);
+  chdr_get_has_time = (chdr_get_pkt_type(header) == CHDR_PKT_TYPE_DATA_TS);
+endfunction
+
+// Calculate the payload length in bytes based on the CHDR_W and header
+function [15:0] chdr_calc_payload_length(input [31:0] chdr_w, input [63:0] header);
+  reg [15:0] payload_length, mdata_length, header_length;
+  begin
+    if (chdr_w == 64) begin
+      header_length = chdr_get_has_time(header) ? 2*(chdr_w/8) : (chdr_w/8);
+    end else begin
+      header_length = chdr_w/8;
+    end
+    mdata_length   = chdr_get_num_mdata(header) * (chdr_w/8);
+    payload_length = chdr_get_length(header) - mdata_length - header_length;
+
+    chdr_calc_payload_length = payload_length;
+  end
+endfunction
diff --git a/fpga/usrp3/lib/rfnoc/core/rfnoc_core_kernel.v b/fpga/usrp3/lib/rfnoc/core/rfnoc_core_kernel.v
new file mode 100644
index 000000000..15a7940a4
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/core/rfnoc_core_kernel.v
@@ -0,0 +1,385 @@
+//
+// Copyright 2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: rfnoc_core_kernel
+// Description:
+//   The main utility and software interface module for an
+//   assembled rfnoc design
+//
+// Parameters:
+//   - PROTOVER: RFNoC protocol version {8'd<major>, 8'd<minor>}
+//   - DEVICE_TYPE: The device type to use in the Device Info register
+//   - DEVICE_FAMILY: The device family (to pass to Xilinx primitives)
+//   - SAFE_START_CLKS: Instantiate logic to ensure that all output
+//                      clocks are glitch-free and startup safely
+//   - NUM_BLOCKS: Number of blocks instantiated in the design
+//   - NUM_STREAM_ENDPOINTS: Number of stream EPs instantiated in the design
+//   - NUM_ENDPOINTS_CTRL: Number of stream EPs connected to the ctrl crossbar
+//   - NUM_TRANSPORTS: Number of transports instantiated in the design
+//   - NUM_EDGES: Number of edges of static connection in the design
+//   - CHDR_XBAR_PRESENT: 1 if the CHDR crossbar is present. If 0 then
+//                        transports are directly connected to SEPs
+//   - EDGE_TBL_FILE: The memory init file for the static connection
+//                    adjacency list
+//
+// Signals:
+//   - chdr_aclk : The input CHDR clock (may be unbuffered if SAFE_START_CLKS=1)
+//   - chdr_aclk_locked : The PLL locked pin for the input CHDR clock (unused if SAFE_START_CLKS=0)
+//   - ctrl_aclk : The input Control clock (may be unbuffered if SAFE_START_CLKS=1)
+//   - ctrl_aclk_locked : The PLL locked pin for the input Control clock (unused if SAFE_START_CLKS=0)
+//   - core_chdr_clk: Output stable CHDR clock for the rest of the design
+//   - core_chdr_rst: Output sync CHDR reset for all infrastructure modules (not blocks)
+//   - core_ctrl_clk: Output stable Control clock for the rest of the design
+//   - core_ctrl_rst: Output sync Control reset for all infrastructure modules (not blocks)
+//   - s_axis_ctrl_* : Slave AXIS-Ctrl for the primary (zero'th) control endpoint
+//   - m_axis_ctrl_* : Master AXIS-Ctrl for the primary (zero'th) control endpoint
+//   - device_id: The dynamic device_id to read through the Device Info register (domain: core_chdr_clk)
+//   - rfnoc_core_config: The backend config port for all blocks in the design (domain: core_ctrl_clk)
+//   - rfnoc_core_status: The backend status port for all blocks in the design (domain: core_ctrl_clk)
+
+module rfnoc_core_kernel #(
+  parameter [15:0] PROTOVER             = {8'd1, 8'd0},
+  parameter [15:0] DEVICE_TYPE          = 16'd0,
+  parameter        DEVICE_FAMILY        = "7SERIES",
+  parameter        SAFE_START_CLKS      = 0,
+  parameter [9:0]  NUM_BLOCKS           = 0,
+  parameter [9:0]  NUM_STREAM_ENDPOINTS = 0,
+  parameter [9:0]  NUM_ENDPOINTS_CTRL   = 0,
+  parameter [9:0]  NUM_TRANSPORTS       = 0,
+  parameter [11:0] NUM_EDGES            = 0,
+  parameter [0:0]  CHDR_XBAR_PRESENT    = 1,
+  parameter        EDGE_TBL_FILE        = ""
+)(
+  // Input clocks and resets
+  input  wire                        chdr_aclk,
+  input  wire                        chdr_aclk_locked,
+  input  wire                        ctrl_aclk,
+  input  wire                        ctrl_aclk_locked,
+  input  wire                        core_arst,
+  // Output clocks and resets
+  output wire                        core_chdr_clk,
+  output wire                        core_chdr_rst,
+  output wire                        core_ctrl_clk,
+  output wire                        core_ctrl_rst,
+  // AXIS-Control Bus
+  input  wire [31:0]                 s_axis_ctrl_tdata,
+  input  wire                        s_axis_ctrl_tlast,
+  input  wire                        s_axis_ctrl_tvalid,
+  output wire                        s_axis_ctrl_tready,
+  output wire [31:0]                 m_axis_ctrl_tdata,
+  output wire                        m_axis_ctrl_tlast,
+  output wire                        m_axis_ctrl_tvalid,
+  input  wire                        m_axis_ctrl_tready,
+  // Global info (domain: core_chdr_clk)
+  input  wire [15:0]                 device_id,
+  // Backend config/status for each block (domain: core_ctrl_clk)
+  output wire [(512*NUM_BLOCKS)-1:0] rfnoc_core_config,
+  input  wire [(512*NUM_BLOCKS)-1:0] rfnoc_core_status
+);
+
+  `include "rfnoc_axis_ctrl_utils.vh"
+  `include "rfnoc_backend_iface.vh"
+
+  // -----------------------------------
+  // Clocking and Resets
+  // -----------------------------------
+
+  generate if (SAFE_START_CLKS == 1) begin
+    // Safe startup logic for the CHDR and Control clocks:
+    // chdr_aclk and ctrl_aclk can be unbuffered.
+    // Use a BUFGCE to disable the clock until the upstream
+    // PLLs have locked.
+
+    wire chdr_ce_clk, ctrl_ce_clk;
+    (* keep = "true" *) (* async_reg = "true" *) reg [7:0] chdr_clk_ce_shreg = 8'h0;
+    (* keep = "true" *) (* async_reg = "true" *) reg [7:0] ctrl_clk_ce_shreg = 8'h0;
+
+    // A glitch-free clock buffer with an enable
+    BUFGCE chdr_clk_buf_i (
+      .I (chdr_aclk),
+      .CE(chdr_clk_ce_shreg[7]),
+      .O (core_chdr_clk)
+    );
+    // A separate clock buffer for the CE signal
+    // We instantiate this manually to prevent the tools from instantiating
+    // the more scare BUFG here. There are a lot more BUFHs than BUFGs
+    BUFH chdr_ce_buf_i (
+      .I(chdr_aclk),
+      .O(chdr_ce_clk)
+    );
+    always @(posedge chdr_ce_clk) begin
+      chdr_clk_ce_shreg <= {chdr_clk_ce_shreg[6:0], chdr_aclk_locked};
+    end
+
+    // A glitch-free clock buffer with an enable
+    BUFGCE ctrl_clk_buf_i (
+      .I (ctrl_aclk),
+      .CE(ctrl_clk_ce_shreg[7]),
+      .O (core_ctrl_clk)
+    );
+    // A separate clock buffer for the CE signal
+    // We instantiate this manually to prevent the tools from instantiating
+    // the more scare BUFG here. There are a lot more BUFHs than BUFGs
+    BUFH ctrl_ce_buf_i (
+      .I(ctrl_aclk),
+      .O(ctrl_ce_clk)
+    );
+    always @(posedge ctrl_ce_clk) begin
+      ctrl_clk_ce_shreg <= {ctrl_clk_ce_shreg[6:0], ctrl_aclk_locked};
+    end
+  end else begin
+    // We assume that chdr_aclk and ctrl_aclk start safely and are glitch-free
+    assign core_chdr_clk = chdr_aclk;
+    assign core_ctrl_clk = ctrl_aclk;
+  end endgenerate
+
+  reset_sync rst_sync_chdr_i (
+    .clk(core_chdr_clk), .reset_in(core_arst), .reset_out(core_chdr_rst)
+  );
+  reset_sync rst_sync_ctrl_i (
+    .clk(core_ctrl_clk), .reset_in(core_arst), .reset_out(core_ctrl_rst)
+  );
+
+  // -----------------------------------
+  // AXIS-Ctrl Slave
+  // -----------------------------------
+
+  wire         ctrlport_req_wr;
+  wire         ctrlport_req_rd;
+  wire [19:0]  ctrlport_req_addr;
+  wire [31:0]  ctrlport_req_data;
+  reg          ctrlport_resp_ack;
+  reg  [31:0]  ctrlport_resp_data;
+
+  // The port ID of this endpoint must be zero
+  localparam [9:0] RFNOC_CORE_PORT_ID = 10'd0;
+
+  ctrlport_endpoint #(
+    .THIS_PORTID(RFNOC_CORE_PORT_ID), .SYNC_CLKS(1),
+    .AXIS_CTRL_MST_EN(0), .AXIS_CTRL_SLV_EN(1),
+    .SLAVE_FIFO_SIZE(5)
+  ) ctrlport_ep_i (
+    .rfnoc_ctrl_clk           (core_ctrl_clk      ),
+    .rfnoc_ctrl_rst           (core_ctrl_rst      ),
+    .ctrlport_clk             (core_ctrl_clk      ),
+    .ctrlport_rst             (core_ctrl_rst      ),
+    .s_rfnoc_ctrl_tdata       (s_axis_ctrl_tdata  ),
+    .s_rfnoc_ctrl_tlast       (s_axis_ctrl_tlast  ),
+    .s_rfnoc_ctrl_tvalid      (s_axis_ctrl_tvalid ),
+    .s_rfnoc_ctrl_tready      (s_axis_ctrl_tready ),
+    .m_rfnoc_ctrl_tdata       (m_axis_ctrl_tdata  ),
+    .m_rfnoc_ctrl_tlast       (m_axis_ctrl_tlast  ),
+    .m_rfnoc_ctrl_tvalid      (m_axis_ctrl_tvalid ),
+    .m_rfnoc_ctrl_tready      (m_axis_ctrl_tready ),
+    .m_ctrlport_req_wr        (ctrlport_req_wr    ),
+    .m_ctrlport_req_rd        (ctrlport_req_rd    ),
+    .m_ctrlport_req_addr      (ctrlport_req_addr  ),
+    .m_ctrlport_req_data      (ctrlport_req_data  ),
+    .m_ctrlport_req_byte_en   (/* not supported */),
+    .m_ctrlport_req_has_time  (/* not supported */),
+    .m_ctrlport_req_time      (/* not supported */),
+    .m_ctrlport_resp_ack      (ctrlport_resp_ack  ),
+    .m_ctrlport_resp_status   (AXIS_CTRL_STS_OKAY ),
+    .m_ctrlport_resp_data     (ctrlport_resp_data ),
+    .s_ctrlport_req_wr        (1'b0               ),
+    .s_ctrlport_req_rd        (1'b0               ),
+    .s_ctrlport_req_addr      (20'd0              ),
+    .s_ctrlport_req_portid    (10'd0              ),
+    .s_ctrlport_req_rem_epid  (16'd0              ),
+    .s_ctrlport_req_rem_portid(10'd0              ),
+    .s_ctrlport_req_data      (32'h0              ),
+    .s_ctrlport_req_byte_en   (4'h0               ),
+    .s_ctrlport_req_has_time  (1'b0               ),
+    .s_ctrlport_req_time      (1'b0               ),
+    .s_ctrlport_resp_ack      (/* unused */       ),
+    .s_ctrlport_resp_status   (/* unused */       ),
+    .s_ctrlport_resp_data     (/* unused */       )
+  );
+
+  // ------------------------------------------------
+  // Segment Address space into the three functions:
+  // - Block Specific (incl. global regs)
+  // - Connections
+  // ------------------------------------------------
+
+  reg  [15:0] req_addr      = 16'h0;
+  reg  [31:0] req_data      = 32'h0;
+  reg         blk_req_wr    = 1'b0;
+  reg         blk_req_rd    = 1'b0;
+  reg         blk_resp_ack  = 1'b0;
+  reg  [31:0] blk_resp_data = 32'h0;
+  reg         con_req_wr    = 1'b0;
+  reg         con_req_rd    = 1'b0;
+  reg         con_resp_ack  = 1'b0;
+  reg  [31:0] con_resp_data = 32'h0;
+
+  // Shortcuts
+  wire blk_addr_space = (ctrlport_req_addr[19:16] == 4'd0);
+  wire con_addr_space = (ctrlport_req_addr[19:16] == 4'd1);
+
+  // ControlPort MUX
+  always @(posedge core_ctrl_clk) begin
+    // Write strobe
+    blk_req_wr <= ctrlport_req_wr & blk_addr_space;
+    con_req_wr <= ctrlport_req_wr & con_addr_space;
+    // Read strobe
+    blk_req_rd <= ctrlport_req_rd & blk_addr_space;
+    con_req_rd <= ctrlport_req_rd & con_addr_space;
+    // Address and Data (shared)
+    req_addr <= ctrlport_req_addr[15:0];
+    req_data <= ctrlport_req_data;
+    // Response
+    ctrlport_resp_ack <= blk_resp_ack | con_resp_ack;
+    if (blk_resp_ack)
+      ctrlport_resp_data <= blk_resp_data;
+    else
+      ctrlport_resp_data <= con_resp_data;
+  end
+
+  // -----------------------------------
+  // Block Address Space
+  // -----------------------------------
+
+  // Arrange the backend block wires into a 2-d array where the
+  // outer index represents the slot number and the inner index represents
+  // a register index for that slot. We have 512 bits of read/write
+  // data which translates to 16 32-bit registers per slot. The first slot
+  // belongs to this endpoint, the next N slots map to the instantiated
+  // stream endpoints and the remaining slots map to block control and
+  // status endpoint. The slot number has a 1-to-1 mapping to the port
+  // number on the control crossbar.
+  localparam NUM_REGS_PER_SLOT = 512/32;
+  localparam NUM_SLOTS = 1 /*this*/ + NUM_STREAM_ENDPOINTS + NUM_BLOCKS;
+  localparam BLOCK_OFFSET = 1 /*this*/ + NUM_STREAM_ENDPOINTS;
+
+  reg  [31:0] config_arr_2d [0:NUM_SLOTS-1][0:NUM_REGS_PER_SLOT-1];
+  wire [31:0] status_arr_2d [0:NUM_SLOTS-1][0:NUM_REGS_PER_SLOT-1];
+
+  genvar b, i;
+  generate
+    for (b = 0; b < NUM_BLOCKS; b=b+1) begin
+      for (i = 0; i < NUM_REGS_PER_SLOT; i=i+1) begin
+        assign rfnoc_core_config[(b*512)+(i*32) +: 32] = config_arr_2d[b+BLOCK_OFFSET][i];
+        assign status_arr_2d[b+BLOCK_OFFSET][i] = rfnoc_core_status[(b*512)+(i*32) +: 32];
+      end
+    end
+  endgenerate
+
+  integer m, n;
+  always @(posedge core_ctrl_clk) begin
+    if (core_ctrl_rst) begin
+      blk_resp_ack <= 1'b0;
+      for (m = 0; m < NUM_SLOTS; m = m + 1) begin
+        for (n = 0; n < NUM_REGS_PER_SLOT; n = n + 1) begin
+          config_arr_2d[m][n] <= BEC_DEFAULT_VAL[(n*32)+:32];
+        end
+      end
+    end else begin
+      // All transactions finish in 1 cycle
+      blk_resp_ack <= blk_req_wr | blk_req_rd;
+      // Handle register writes
+      if (blk_req_wr) begin
+        config_arr_2d[req_addr[$clog2(NUM_SLOTS)+5:6]][req_addr[5:2]] <= req_data;
+      end
+      // Handle register reads
+      if (blk_req_rd) begin
+        blk_resp_data <= status_arr_2d[req_addr[$clog2(NUM_SLOTS)+5:6]][req_addr[5:2]];
+      end
+    end
+  end
+
+  // Global Registers
+  localparam [3:0] REG_GLOBAL_PROTOVER          = 4'd0;  // Offset = 0x00
+  localparam [3:0] REG_GLOBAL_PORT_CNT          = 4'd1;  // Offset = 0x04
+  localparam [3:0] REG_GLOBAL_EDGE_CNT          = 4'd2;  // Offset = 0x08
+  localparam [3:0] REG_GLOBAL_DEVICE_INFO       = 4'd3;  // Offset = 0x0C
+  localparam [3:0] REG_GLOBAL_ENDPOINT_CTRL_CNT = 4'd4;  // Offset = 0x10
+
+  // Clock-crossing for device_id.
+  // FIFO going from core_chdr_clk domain to core_ctrl_clk.
+  wire        device_id_fifo_ovalid;
+  wire [15:0] device_id_fifo_odata;
+  axi_fifo_2clk # (
+    .WIDTH     (16),
+    .SIZE      (2)
+  ) device_id_fifo_i (
+    .reset     (1'b0),
+    .i_aclk    (core_chdr_clk),
+    .i_tdata   (device_id),
+    .i_tvalid  (1'b1),
+    .i_tready  (),
+    .o_aclk    (core_ctrl_clk),
+    .o_tdata   (device_id_fifo_odata),
+    .o_tvalid  (device_id_fifo_ovalid),
+    .o_tready  (1'b1)
+  );
+  // Register the FIFO's output to always have valid data available.
+  reg  [15:0] device_id_ctrl_clk = 16'h0;
+  always @(posedge core_ctrl_clk) begin
+    if (device_id_fifo_ovalid) begin
+      device_id_ctrl_clk <= device_id_fifo_odata;
+    end
+  end
+
+  // Signature and protocol version
+  assign status_arr_2d[RFNOC_CORE_PORT_ID][REG_GLOBAL_PROTOVER] = {16'h12C6, PROTOVER[15:0]};
+
+  // Global port count register
+  localparam [0:0] STATIC_ROUTER_PRESENT = (NUM_EDGES == 12'd0) ? 1'b0 : 1'b1;
+  assign status_arr_2d[RFNOC_CORE_PORT_ID][REG_GLOBAL_PORT_CNT] =
+    {STATIC_ROUTER_PRESENT, CHDR_XBAR_PRESENT,
+     NUM_TRANSPORTS[9:0], NUM_BLOCKS[9:0], NUM_STREAM_ENDPOINTS[9:0]};
+  // Global edge count register
+  assign status_arr_2d[RFNOC_CORE_PORT_ID][REG_GLOBAL_EDGE_CNT] = {20'd0, NUM_EDGES[11:0]};
+  // Device information
+  assign status_arr_2d[RFNOC_CORE_PORT_ID][REG_GLOBAL_DEVICE_INFO] = {DEVICE_TYPE, device_id_ctrl_clk};
+  // Number of stream endpoint connected to the ctrl crossbar
+  assign status_arr_2d[RFNOC_CORE_PORT_ID][REG_GLOBAL_ENDPOINT_CTRL_CNT] = {22'b0, NUM_ENDPOINTS_CTRL[9:0]};
+
+  // -----------------------------------
+  // Connections Address Space
+  // -----------------------------------
+
+  // All inter-block static connections must be stored in a memory
+  // file which will be used to initialize a ROM that can be read
+  // by software for topology discovery. The format of the memory
+  // must be as follows:
+  // * Word Width: 32 bits
+  // * Maximum Depth: 16384 entries
+  // * Layout:
+  //   - 0x000 : HEADER
+  //   - 0x001 : EDGE_0_DEF
+  //   - 0x002 : EDGE_1_DEF
+  //   ...
+  //   - 0xFFF : EDGE_4094_DEF
+  //
+  // where:
+  // * HEADER       = {18'd0, NumEntries[13:0]}
+  // * EDGE_<N>_DEF = {SrcBlkIndex[9:0], SrcBlkPort[5:0], DstBlkIndex[9:0], DstBlkPort[5:0]}
+  //
+  // The BlkIndex is the port number of the block on the control crossbar amd the BlkPort is
+  // the index of the input or output port of the block.
+
+  generate if (EDGE_TBL_FILE == "" || NUM_EDGES == 0) begin
+    // If no file is specified or if the number of edges is zero
+    // then just return zero for all transactions
+    always @(posedge core_ctrl_clk) begin
+      con_resp_ack  <= (con_req_wr | con_req_rd);
+      con_resp_data <= 32'h0;
+    end
+  end else begin
+    // Initialize ROM from file and read it during a reg transaction
+    reg [31:0] edge_tbl_rom[0:NUM_EDGES];
+    initial begin
+      $readmemh(EDGE_TBL_FILE, edge_tbl_rom, 0, NUM_EDGES);
+    end
+    always @(posedge core_ctrl_clk) begin
+      con_resp_ack  <= (con_req_wr | con_req_rd);
+      con_resp_data <= edge_tbl_rom[req_addr[$clog2(NUM_EDGES+1)+1:2]];
+    end
+  end endgenerate
+
+endmodule // rfnoc_core_kernel
+
diff --git a/fpga/usrp3/lib/rfnoc/counter.v b/fpga/usrp3/lib/rfnoc/counter.v
new file mode 100644
index 000000000..f3480aaf6
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/counter.v
@@ -0,0 +1,37 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Simple counter, reset by i_tlast on input side.  i_tdata not connected
+//  Most useful for indexing a RAM, creating a ramp, etc.
+
+module counter
+  #(parameter WIDTH=16)
+   (input clk, input reset, input clear,
+    input [WIDTH:0] max,
+    input i_tlast, input i_tvalid, output i_tready,
+    output [WIDTH-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready);
+
+   reg [WIDTH-1:0]     count;
+   
+   wire 	       do_it = o_tready & i_tvalid;
+   wire 	       done = (count >= (max-1));
+   
+   always @(posedge clk)
+     if(reset | clear)
+       count <= 0;
+     else
+       if(do_it)
+	 if( done | i_tlast )
+	   count <= 0;
+   	 else
+	   count <= count + 1;
+   
+   assign o_tdata = count;
+   assign o_tlast = done | i_tlast;
+   assign o_tvalid = i_tvalid;
+   assign i_tready = do_it;
+   
+endmodule // counter
diff --git a/fpga/usrp3/lib/rfnoc/crossbar/Makefile.srcs b/fpga/usrp3/lib/rfnoc/crossbar/Makefile.srcs
new file mode 100644
index 000000000..6fa49cd04
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/crossbar/Makefile.srcs
@@ -0,0 +1,25 @@
+#
+# Copyright 2018 Ettus Research, a National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+##################################################
+# Crossbar Sources
+##################################################
+RFNOC_XBAR_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/rfnoc/crossbar/, \
+axis_ctrl_crossbar_2d_mesh.v \
+axis_ctrl_crossbar_nxn.v \
+torus_2d_dor_router_single_sw.v \
+mesh_2d_dor_router_single_sw.v \
+axis_ingress_vc_buff.v \
+axis_switch.v \
+axis_port_terminator.v \
+chdr_crossbar_nxn.v \
+chdr_xb_ingress_buff.v \
+chdr_xb_routing_table.v \
+))
+
+# Unused sources
+# torus_2d_dor_router_multi_sw.v \
+# mesh_2d_dor_router_multi_sw.v \
diff --git a/fpga/usrp3/lib/rfnoc/crossbar/README.pdf b/fpga/usrp3/lib/rfnoc/crossbar/README.pdf
new file mode 100644
index 000000000..838702bd1
Binary files /dev/null and b/fpga/usrp3/lib/rfnoc/crossbar/README.pdf differ
diff --git a/fpga/usrp3/lib/rfnoc/crossbar/axis_ctrl_crossbar_2d_mesh.v b/fpga/usrp3/lib/rfnoc/crossbar/axis_ctrl_crossbar_2d_mesh.v
new file mode 100644
index 000000000..e69bdfe3c
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/crossbar/axis_ctrl_crossbar_2d_mesh.v
@@ -0,0 +1,288 @@
+//
+// Copyright 2018 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: axis_ctrl_crossbar_2d_mesh
+// Description: 
+//   This module implements a 2-dimentional (2d) mesh network (mesh) crossbar
+//   for AXIS-CTRL traffic. Supports mesh and torus topologies.
+//   It uses AXI-Stream for all of its links. 
+//   The torus topology, routing algorithms and the router architecture is 
+//   described in README.md in this directory. 
+// Parameters:
+//   - WIDTH: Width of the AXI-Stream data bus
+//   - DIM_SIZE: Number of routers alone one dimension (# Nodes = DIM_SIZE * DIM_SIZE)
+//   - TOPOLOGY: Is this a mesh (MESH) or a torus (TORUS) topology
+//   - INGRESS_BUFF_SIZE: log2 of the ingress terminal buffer size (in words)
+//   - ROUTER_BUFF_SIZE: log2 of the ingress inter-router buffer size (in words)
+//   - ROUTING_ALLOC: Algorithm to allocate routing paths between routers.
+//     * WORMHOLE: Allocate route as soon as first word in pkt arrives
+//     * CUT-THROUGH: Allocate route only after the full pkt arrives
+//   - SWITCH_ALLOC: Algorithm to allocate the switch
+//     * PRIO: Priority based. Priority: Y-dim > X-dim > Term
+//     * ROUND-ROBIN: Round robin input port allocation
+//   - DEADLOCK_TIMEOUT: Number of cycles to wait until a deadlock is detected
+// Signals:
+//   - s_axis_*: Slave port for router (flattened)
+//   - m_axis_*: Master port for router (flattened)
+//
+
+module axis_ctrl_crossbar_2d_mesh #(
+  parameter DIM_SIZE          = 4,
+  parameter WIDTH             = 64,
+  parameter TOPOLOGY          = "MESH",
+  parameter INGRESS_BUFF_SIZE = 5,
+  parameter ROUTER_BUFF_SIZE  = 5,
+  parameter ROUTING_ALLOC     = "WORMHOLE",
+  parameter SWITCH_ALLOC      = "PRIO",
+  parameter DEADLOCK_TIMEOUT  = 16384
+) (
+  input  wire                                 clk,
+  input  wire                                 reset,
+  // Inputs
+  input  wire [(DIM_SIZE*DIM_SIZE*WIDTH)-1:0] s_axis_tdata,
+  input  wire [DIM_SIZE*DIM_SIZE-1:0]         s_axis_tlast,
+  input  wire [DIM_SIZE*DIM_SIZE-1:0]         s_axis_tvalid,
+  output wire [DIM_SIZE*DIM_SIZE-1:0]         s_axis_tready,
+  // Output
+  output wire [(DIM_SIZE*DIM_SIZE*WIDTH)-1:0] m_axis_tdata,
+  output wire [DIM_SIZE*DIM_SIZE-1:0]         m_axis_tlast,
+  output wire [DIM_SIZE*DIM_SIZE-1:0]         m_axis_tvalid,
+  input  wire [DIM_SIZE*DIM_SIZE-1:0]         m_axis_tready,
+  // Deadlock alert
+  output wire                                 deadlock_detected
+);
+
+  `include "mesh_node_mapping.vh"
+
+  //-------------------------------------------------------
+  // Unflatten input and output ports
+  //-------------------------------------------------------
+
+  wire [WIDTH-1:0] i_tdata_arr [0:DIM_SIZE-1][0:DIM_SIZE-1];
+  wire             i_tlast_arr [0:DIM_SIZE-1][0:DIM_SIZE-1];
+  wire             i_tvalid_arr[0:DIM_SIZE-1][0:DIM_SIZE-1];
+  wire             i_tready_arr[0:DIM_SIZE-1][0:DIM_SIZE-1];
+
+  wire [WIDTH-1:0] o_tdata_arr [0:DIM_SIZE-1][0:DIM_SIZE-1];
+  wire             o_tlast_arr [0:DIM_SIZE-1][0:DIM_SIZE-1];
+  wire             o_tvalid_arr[0:DIM_SIZE-1][0:DIM_SIZE-1];
+  wire             o_tready_arr[0:DIM_SIZE-1][0:DIM_SIZE-1];
+
+  wire             clear_routers = deadlock_detected;
+
+  genvar p,x,y;
+  generate
+    for (p = 0; p < DIM_SIZE*DIM_SIZE; p=p+1) begin
+      assign i_tdata_arr[node_to_ydst(p)][node_to_xdst(p)] = s_axis_tdata[p*WIDTH +: WIDTH];
+      assign i_tlast_arr[node_to_ydst(p)][node_to_xdst(p)] = s_axis_tlast[p];
+      assign i_tvalid_arr[node_to_ydst(p)][node_to_xdst(p)] = s_axis_tvalid[p];
+      assign s_axis_tready[p] = i_tready_arr[node_to_ydst(p)][node_to_xdst(p)] | clear_routers;
+
+      assign m_axis_tdata[p*WIDTH +: WIDTH] = o_tdata_arr[node_to_ydst(p)][node_to_xdst(p)];
+      assign m_axis_tlast[p] = o_tlast_arr [node_to_ydst(p)][node_to_xdst(p)];
+      assign m_axis_tvalid[p] = o_tvalid_arr[node_to_ydst(p)][node_to_xdst(p)] & ~clear_routers;
+      assign o_tready_arr[node_to_ydst(p)][node_to_xdst(p)] = m_axis_tready[p];
+    end
+  endgenerate
+
+  //-------------------------------------------------------
+  // Instantiate routers
+  //-------------------------------------------------------
+
+  wire [WIDTH-1:0] e2w_tdata_arr [0:DIM_SIZE-1][0:DIM_SIZE-1];
+  wire             e2w_tdest_arr [0:DIM_SIZE-1][0:DIM_SIZE-1];
+  wire             e2w_tlast_arr [0:DIM_SIZE-1][0:DIM_SIZE-1];
+  wire             e2w_tvalid_arr[0:DIM_SIZE-1][0:DIM_SIZE-1];
+  wire             e2w_tready_arr[0:DIM_SIZE-1][0:DIM_SIZE-1];
+
+  wire [WIDTH-1:0] w2e_tdata_arr [0:DIM_SIZE-1][0:DIM_SIZE-1];
+  wire             w2e_tdest_arr [0:DIM_SIZE-1][0:DIM_SIZE-1];
+  wire             w2e_tlast_arr [0:DIM_SIZE-1][0:DIM_SIZE-1];
+  wire             w2e_tvalid_arr[0:DIM_SIZE-1][0:DIM_SIZE-1];
+  wire             w2e_tready_arr[0:DIM_SIZE-1][0:DIM_SIZE-1];
+
+  wire [WIDTH-1:0] n2s_tdata_arr [0:DIM_SIZE-1][0:DIM_SIZE-1];
+  wire             n2s_tdest_arr [0:DIM_SIZE-1][0:DIM_SIZE-1];
+  wire             n2s_tlast_arr [0:DIM_SIZE-1][0:DIM_SIZE-1];
+  wire             n2s_tvalid_arr[0:DIM_SIZE-1][0:DIM_SIZE-1];
+  wire             n2s_tready_arr[0:DIM_SIZE-1][0:DIM_SIZE-1];
+
+  wire [WIDTH-1:0] s2n_tdata_arr [0:DIM_SIZE-1][0:DIM_SIZE-1];
+  wire             s2n_tdest_arr [0:DIM_SIZE-1][0:DIM_SIZE-1];
+  wire             s2n_tlast_arr [0:DIM_SIZE-1][0:DIM_SIZE-1];
+  wire             s2n_tvalid_arr[0:DIM_SIZE-1][0:DIM_SIZE-1];
+  wire             s2n_tready_arr[0:DIM_SIZE-1][0:DIM_SIZE-1];
+
+  localparam              N    = DIM_SIZE;
+  localparam              NEND = DIM_SIZE - 1;
+  localparam [WIDTH-1:0]  ZERO = {WIDTH{1'b0}};
+
+  generate
+    for (y = 0; y < DIM_SIZE; y=y+1) begin: ydim
+      for (x = 0; x < DIM_SIZE; x=x+1) begin: xdim
+        if (TOPOLOGY == "MESH") begin
+          mesh_2d_dor_router_single_sw #(
+            .WIDTH              (WIDTH),
+            .DIM_SIZE           (DIM_SIZE),
+            .XB_ADDR_X          (x),
+            .XB_ADDR_Y          (y),
+            .TERM_BUFF_SIZE     (INGRESS_BUFF_SIZE),
+            .XB_BUFF_SIZE       (ROUTER_BUFF_SIZE),
+            .ROUTING_ALLOC      (ROUTING_ALLOC),
+            .SWITCH_ALLOC       (SWITCH_ALLOC)
+          ) rtr_i (
+            // Clock and reset
+            .clk                (clk),
+            .reset              (reset | clear_routers),
+            // Terminals
+            .s_axis_ter_tdata   (i_tdata_arr [y][x]),
+            .s_axis_ter_tlast   (i_tlast_arr [y][x]),
+            .s_axis_ter_tvalid  (i_tvalid_arr[y][x]),
+            .s_axis_ter_tready  (i_tready_arr[y][x]),
+            .m_axis_ter_tdata   (o_tdata_arr [y][x]),
+            .m_axis_ter_tlast   (o_tlast_arr [y][x]),
+            .m_axis_ter_tvalid  (o_tvalid_arr[y][x]),
+            .m_axis_ter_tready  (o_tready_arr[y][x]),
+            // West connections
+            .s_axis_wst_tdata   ((x != 0)    ? e2w_tdata_arr [y][x]         : ZERO),
+            .s_axis_wst_tdest   ((x != 0)    ? e2w_tdest_arr [y][x]         : 1'b0),
+            .s_axis_wst_tlast   ((x != 0)    ? e2w_tlast_arr [y][x]         : 1'b0),
+            .s_axis_wst_tvalid  ((x != 0)    ? e2w_tvalid_arr[y][x]         : 1'b0),
+            .s_axis_wst_tready  (              e2w_tready_arr[y][x]               ),
+            .m_axis_wst_tdata   (              w2e_tdata_arr [y][(x+N-1)%N]       ),
+            .m_axis_wst_tdest   (              w2e_tdest_arr [y][(x+N-1)%N]       ),
+            .m_axis_wst_tlast   (              w2e_tlast_arr [y][(x+N-1)%N]       ),
+            .m_axis_wst_tvalid  (              w2e_tvalid_arr[y][(x+N-1)%N]       ),
+            .m_axis_wst_tready  ((x != 0)    ? w2e_tready_arr[y][(x+N-1)%N] : 1'b1),
+            // East connections
+            .s_axis_est_tdata   ((x != NEND) ? w2e_tdata_arr [y][x]         : ZERO),
+            .s_axis_est_tdest   ((x != NEND) ? w2e_tdest_arr [y][x]         : 1'b0),
+            .s_axis_est_tlast   ((x != NEND) ? w2e_tlast_arr [y][x]         : 1'b0),
+            .s_axis_est_tvalid  ((x != NEND) ? w2e_tvalid_arr[y][x]         : 1'b0),
+            .s_axis_est_tready  (              w2e_tready_arr[y][x]               ),
+            .m_axis_est_tdata   (              e2w_tdata_arr [y][(x+1)%N]         ),
+            .m_axis_est_tdest   (              e2w_tdest_arr [y][(x+1)%N]         ),
+            .m_axis_est_tlast   (              e2w_tlast_arr [y][(x+1)%N]         ),
+            .m_axis_est_tvalid  (              e2w_tvalid_arr[y][(x+1)%N]         ),
+            .m_axis_est_tready  ((x != NEND) ? e2w_tready_arr[y][(x+1)%N]   : 1'b1),
+            // North connections
+            .s_axis_nor_tdata   ((y != 0)    ? s2n_tdata_arr [y][x]         : ZERO),
+            .s_axis_nor_tdest   ((y != 0)    ? s2n_tdest_arr [y][x]         : 1'b0),
+            .s_axis_nor_tlast   ((y != 0)    ? s2n_tlast_arr [y][x]         : 1'b0),
+            .s_axis_nor_tvalid  ((y != 0)    ? s2n_tvalid_arr[y][x]         : 1'b0),
+            .s_axis_nor_tready  (              s2n_tready_arr[y][x]               ),
+            .m_axis_nor_tdata   (              n2s_tdata_arr [(y+N-1)%N][x]       ),
+            .m_axis_nor_tdest   (              n2s_tdest_arr [(y+N-1)%N][x]       ),
+            .m_axis_nor_tlast   (              n2s_tlast_arr [(y+N-1)%N][x]       ),
+            .m_axis_nor_tvalid  (              n2s_tvalid_arr[(y+N-1)%N][x]       ),
+            .m_axis_nor_tready  ((y != 0)    ? n2s_tready_arr[(y+N-1)%N][x] : 1'b1),
+            // South connections
+            .s_axis_sou_tdata   ((y != NEND) ? n2s_tdata_arr [y][x]         : ZERO),
+            .s_axis_sou_tdest   ((y != NEND) ? n2s_tdest_arr [y][x]         : 1'b0),
+            .s_axis_sou_tlast   ((y != NEND) ? n2s_tlast_arr [y][x]         : 1'b0),
+            .s_axis_sou_tvalid  ((y != NEND) ? n2s_tvalid_arr[y][x]         : 1'b0),
+            .s_axis_sou_tready  (              n2s_tready_arr[y][x]               ),
+            .m_axis_sou_tdata   (              s2n_tdata_arr [(y+1)%N][x]         ),
+            .m_axis_sou_tdest   (              s2n_tdest_arr [(y+1)%N][x]         ),
+            .m_axis_sou_tlast   (              s2n_tlast_arr [(y+1)%N][x]         ),
+            .m_axis_sou_tvalid  (              s2n_tvalid_arr[(y+1)%N][x]         ),
+            .m_axis_sou_tready  ((y != NEND) ? s2n_tready_arr[(y+1)%N][x]   : 1'b1)
+          );
+        end else begin
+          torus_2d_dor_router_single_sw #(
+            .WIDTH              (WIDTH),
+            .DIM_SIZE           (DIM_SIZE),
+            .XB_ADDR_X          (x),
+            .XB_ADDR_Y          (y),
+            .TERM_BUFF_SIZE     (INGRESS_BUFF_SIZE),
+            .XB_BUFF_SIZE       (ROUTER_BUFF_SIZE),
+            .ROUTING_ALLOC      (ROUTING_ALLOC),
+            .SWITCH_ALLOC       (SWITCH_ALLOC)
+          ) rtr_i (
+            // Clock and reset
+            .clk                (clk),
+            .reset              (reset | clear_routers),
+            // Terminals
+            .s_axis_term_tdata  (i_tdata_arr [y][x]),
+            .s_axis_term_tlast  (i_tlast_arr [y][x]),
+            .s_axis_term_tvalid (i_tvalid_arr[y][x]),
+            .s_axis_term_tready (i_tready_arr[y][x]),
+            .m_axis_term_tdata  (o_tdata_arr [y][x]),
+            .m_axis_term_tlast  (o_tlast_arr [y][x]),
+            .m_axis_term_tvalid (o_tvalid_arr[y][x]),
+            .m_axis_term_tready (o_tready_arr[y][x]),
+            // X-dim connections
+            .s_axis_xdim_tdata  (e2w_tdata_arr [y][x]      ),
+            .s_axis_xdim_tdest  (e2w_tdest_arr [y][x]      ),
+            .s_axis_xdim_tlast  (e2w_tlast_arr [y][x]      ),
+            .s_axis_xdim_tvalid (e2w_tvalid_arr[y][x]      ),
+            .s_axis_xdim_tready (e2w_tready_arr[y][x]      ),
+            .m_axis_xdim_tdata  (e2w_tdata_arr [y][(x+1)%N]),
+            .m_axis_xdim_tdest  (e2w_tdest_arr [y][(x+1)%N]),
+            .m_axis_xdim_tlast  (e2w_tlast_arr [y][(x+1)%N]),
+            .m_axis_xdim_tvalid (e2w_tvalid_arr[y][(x+1)%N]),
+            .m_axis_xdim_tready (e2w_tready_arr[y][(x+1)%N]),
+            // Y-dim connections
+            .s_axis_ydim_tdata  (s2n_tdata_arr [y][x]      ),
+            .s_axis_ydim_tdest  (s2n_tdest_arr [y][x]      ),
+            .s_axis_ydim_tlast  (s2n_tlast_arr [y][x]      ),
+            .s_axis_ydim_tvalid (s2n_tvalid_arr[y][x]      ),
+            .s_axis_ydim_tready (s2n_tready_arr[y][x]      ),
+            .m_axis_ydim_tdata  (s2n_tdata_arr [(y+1)%N][x]),
+            .m_axis_ydim_tdest  (s2n_tdest_arr [(y+1)%N][x]),
+            .m_axis_ydim_tlast  (s2n_tlast_arr [(y+1)%N][x]),
+            .m_axis_ydim_tvalid (s2n_tvalid_arr[(y+1)%N][x]),
+            .m_axis_ydim_tready (s2n_tready_arr[(y+1)%N][x])
+          );
+        end
+      end
+    end
+  endgenerate
+
+  //-------------------------------------------------------
+  // Deadlock detector
+  //-------------------------------------------------------
+  // A deadlock is defined on an AXIS bus as an extended period
+  // where tvlid=1 but tready=0. If at least one slave port is in
+  // this state and none of the master ports are then this router
+  // will go into a failsafe deadlock recovery mode. The DEADLOCK_TIMEOUT 
+  // parameter defines the duration for which this condition has 
+  // to be true. In deadlock recovery mode, all routers are held in reset
+  // (thus losing all packets in flights) and all input ports are flushed.
+  
+  wire m_locked = |(m_axis_tvalid & ~m_axis_tready);
+  wire s_locked = |(s_axis_tvalid & ~s_axis_tready);
+
+  // A counter that tracks the duration for which the router is livelocked
+  // If the livelock duration is higher than DEADLOCK_TIMEOUT then it is a
+  // deadlock
+  reg [$clog2(DEADLOCK_TIMEOUT)-1:0] deadlock_counter = DEADLOCK_TIMEOUT-1;
+  always @(posedge clk) begin
+    if (reset | ~(s_locked & ~m_locked)) begin
+      deadlock_counter <= DEADLOCK_TIMEOUT-1;
+    end else if (deadlock_counter != 'd0) begin
+      deadlock_counter <= deadlock_counter - 1;
+    end
+  end
+
+  // A counter that tracks the deadlock recovery period. If the slave ports
+  // have no activity for DEADLOCK_TIMEOUT cycles then the router can
+  // successfully come out of the deadlocked state.
+  reg [$clog2(DEADLOCK_TIMEOUT)-1:0] deadlock_recover_counter = 'd0;
+  always @(posedge clk) begin
+    if (reset) begin
+      deadlock_recover_counter <= 'd0;
+    end else if (deadlock_detected) begin
+      if (|s_axis_tvalid)
+        deadlock_recover_counter <= DEADLOCK_TIMEOUT-1;
+      else
+        deadlock_recover_counter <= deadlock_recover_counter - 1;
+    end else if (deadlock_counter == 'd0) begin
+      deadlock_recover_counter <= DEADLOCK_TIMEOUT-1;
+    end
+  end
+  assign deadlock_detected = (deadlock_recover_counter != 0);
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/crossbar/axis_ctrl_crossbar_nxn.v b/fpga/usrp3/lib/rfnoc/crossbar/axis_ctrl_crossbar_nxn.v
new file mode 100644
index 000000000..6de082b4c
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/crossbar/axis_ctrl_crossbar_nxn.v
@@ -0,0 +1,130 @@
+//
+// Copyright 2018 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: axis_ctrl_crossbar_nxn
+// Description: 
+//   This module implements a 2-dimentional (2d) mesh network (mesh) crossbar
+//   for AXIS-CTRL traffic. Supports mesh and torus topologies.
+//   It uses AXI-Stream for all of its links. 
+//   The torus topology, routing algorithms and the router architecture is 
+//   described in README.md in this directory. 
+// Parameters:
+//   - WIDTH: Width of the AXI-Stream data bus
+//   - NPORTS: Number of ports (maximum 1024)
+//   - TOPOLOGY: Is this a mesh (MESH) or a torus (TORUS) topology
+//   - INGRESS_BUFF_SIZE: log2 of the ingress terminal buffer size (in words)
+//   - ROUTER_BUFF_SIZE: log2 of the ingress inter-router buffer size (in words)
+//   - ROUTING_ALLOC: Algorithm to allocate routing paths between routers.
+//     * WORMHOLE: Allocate route as soon as first word in pkt arrives
+//     * CUT-THROUGH: Allocate route only after the full pkt arrives
+//   - SWITCH_ALLOC: Algorithm to allocate the switch
+//     * PRIO: Priority based. Priority: Y-dim > X-dim > Term
+//     * ROUND-ROBIN: Round robin input port allocation
+//   - DEADLOCK_TIMEOUT: Number of cycles to wait until a deadlock is detected
+// Signals:
+//   - s_axis_*: Slave port for router (flattened)
+//   - m_axis_*: Master port for router (flattened)
+//
+
+module axis_ctrl_crossbar_nxn #(
+  parameter WIDTH             = 32,
+  parameter NPORTS            = 10,
+  parameter TOPOLOGY          = "TORUS",
+  parameter INGRESS_BUFF_SIZE = 5,
+  parameter ROUTER_BUFF_SIZE  = 5,
+  parameter ROUTING_ALLOC     = "WORMHOLE",
+  parameter SWITCH_ALLOC      = "PRIO",
+  parameter DEADLOCK_TIMEOUT  = 16384
+) (
+  input  wire                      clk,
+  input  wire                      reset,
+  // Inputs
+  input  wire [(NPORTS*WIDTH)-1:0] s_axis_tdata,
+  input  wire [NPORTS-1:0]         s_axis_tlast,
+  input  wire [NPORTS-1:0]         s_axis_tvalid,
+  output wire [NPORTS-1:0]         s_axis_tready,
+  // Output
+  output wire [(NPORTS*WIDTH)-1:0] m_axis_tdata,
+  output wire [NPORTS-1:0]         m_axis_tlast,
+  output wire [NPORTS-1:0]         m_axis_tvalid,
+  input  wire [NPORTS-1:0]         m_axis_tready,
+  // Deadlock alert
+  output wire                      deadlock_detected
+);
+
+  function integer csqrt_max1024;
+    input integer value;
+    integer i;
+  begin
+    csqrt_max1024 = 1;
+    for (i = 1; i <= 32; i = i + 1)  // sqrt(1024) = 32
+      csqrt_max1024 = csqrt_max1024 + (i*i < value ? 1 : 0);
+  end
+  endfunction
+
+  localparam integer DIM_SIZE = csqrt_max1024(NPORTS);
+
+  wire [(DIM_SIZE*DIM_SIZE*WIDTH)-1:0] i_tdata,  o_tdata ;
+  wire [DIM_SIZE*DIM_SIZE-1:0]         i_tlast,  o_tlast ;
+  wire [DIM_SIZE*DIM_SIZE-1:0]         i_tvalid, o_tvalid;
+  wire [DIM_SIZE*DIM_SIZE-1:0]         i_tready, o_tready;
+
+  // axis_ctrl_crossbar_2d_mesh needs to scale up in squares
+  // i.e. 4, 9, 16, 25, ... but NPORTS can be any number, so
+  // instantiate the next highest square number of ports and
+  // terminate the rest.
+  axis_ctrl_crossbar_2d_mesh #(
+    .WIDTH            (WIDTH),
+    .DIM_SIZE         (DIM_SIZE),
+    .TOPOLOGY         (TOPOLOGY),
+    .INGRESS_BUFF_SIZE(INGRESS_BUFF_SIZE),
+    .ROUTER_BUFF_SIZE (ROUTER_BUFF_SIZE),
+    .ROUTING_ALLOC    (ROUTING_ALLOC),
+    .SWITCH_ALLOC     (SWITCH_ALLOC),
+    .DEADLOCK_TIMEOUT (DEADLOCK_TIMEOUT)
+  ) router_dut_i (
+    .clk              (clk),
+    .reset            (reset),
+    .s_axis_tdata     (i_tdata),
+    .s_axis_tlast     (i_tlast),
+    .s_axis_tvalid    (i_tvalid),
+    .s_axis_tready    (i_tready),
+    .m_axis_tdata     (o_tdata), 
+    .m_axis_tlast     (o_tlast),
+    .m_axis_tvalid    (o_tvalid), 
+    .m_axis_tready    (o_tready),
+    .deadlock_detected(deadlock_detected)
+  );
+
+  // Connect the bottom NPORTS to the IO
+  assign i_tdata[(NPORTS*WIDTH)-1:0] = s_axis_tdata;
+  assign i_tlast[NPORTS-1:0]         = s_axis_tlast;
+  assign i_tvalid[NPORTS-1:0]        = s_axis_tvalid;
+  assign s_axis_tready               = i_tready[NPORTS-1:0];
+
+  assign m_axis_tdata                = o_tdata[(NPORTS*WIDTH)-1:0];
+  assign m_axis_tlast                = o_tlast[NPORTS-1:0];
+  assign m_axis_tvalid               = o_tvalid[NPORTS-1:0];
+  assign o_tready[NPORTS-1:0]        = m_axis_tready;
+
+  // Terminate the rest
+  genvar i;
+  generate for (i = NPORTS; i < (DIM_SIZE*DIM_SIZE); i = i + 1) begin: ports
+    axis_port_terminator #(.DATA_W(WIDTH)) term_i (
+      .clk          (clk),
+      .reset        (reset),
+      .s_axis_tdata (o_tdata[(i*WIDTH)+:WIDTH]),
+      .s_axis_tlast (o_tlast[i]),
+      .s_axis_tvalid(o_tvalid[i]),
+      .s_axis_tready(o_tready[i]),
+      .m_axis_tdata (i_tdata[(i*WIDTH)+:WIDTH]),
+      .m_axis_tlast (i_tlast[i]),
+      .m_axis_tvalid(i_tvalid[i]),
+      .m_axis_tready(i_tready[i]),
+      .pkts_dropped ()
+    );
+  end endgenerate
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/crossbar/axis_ingress_vc_buff.v b/fpga/usrp3/lib/rfnoc/crossbar/axis_ingress_vc_buff.v
new file mode 100644
index 000000000..fd10d6682
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/crossbar/axis_ingress_vc_buff.v
@@ -0,0 +1,178 @@
+//
+// Copyright 2018 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: axis_ingress_vc_buff
+// Description:
+//  A wrapper around a buffer to implement one or more virtual channels
+//  Supports gate a packet for cut-through routing
+
+module axis_ingress_vc_buff #(
+  parameter WIDTH     = 64,         // Width of the datapath
+  parameter NUM_VCS   = 2,          // Number of virtual channels
+  parameter SIZE      = 5,          // Virtual channel buffer size
+  parameter ROUTING   = "WORMHOLE", // Routing (switching) method {WORMHOLE, CUT-THROUGH}
+  parameter DEST_W    = (NUM_VCS > 1) ? $clog2(NUM_VCS) : 1 // PRIVATE
+) (
+  input  wire               clk,
+  input  wire               reset,
+  input  wire [WIDTH-1:0]   s_axis_tdata,
+  input  wire [DEST_W-1:0]  s_axis_tdest,
+  input  wire               s_axis_tlast,
+  input  wire               s_axis_tvalid,
+  output wire               s_axis_tready,
+  output wire [WIDTH-1:0]   m_axis_tdata,
+  output wire               m_axis_tlast,
+  output wire               m_axis_tvalid,
+  input  wire               m_axis_tready
+);
+
+  generate if (NUM_VCS > 1) begin
+    //----------------------------------------------------
+    // Multiple virtual channels
+    //----------------------------------------------------
+
+    wire [(WIDTH*NUM_VCS)-1:0] bufin_tdata , bufout_tdata ;
+    wire [NUM_VCS-1:0]         bufin_tlast , bufout_tlast ;
+    wire [NUM_VCS-1:0]         bufin_tvalid, bufout_tvalid;
+    wire [NUM_VCS-1:0]         bufin_tready, bufout_tready;
+  
+    axi_demux #(
+      .WIDTH(WIDTH), .SIZE(NUM_VCS),
+      .PRE_FIFO_SIZE(0 /* must be 0 */), .POST_FIFO_SIZE(0)
+    ) vc_demux_i (
+      .clk      (clk),
+      .reset    (reset),
+      .clear    (1'b0),
+      .header   (/* unused */),
+      .dest     (s_axis_tdest ),
+      .i_tdata  (s_axis_tdata ),
+      .i_tlast  (s_axis_tlast ),
+      .i_tvalid (s_axis_tvalid),
+      .i_tready (s_axis_tready),
+      .o_tdata  (bufin_tdata),
+      .o_tlast  (bufin_tlast),
+      .o_tvalid (bufin_tvalid),
+      .o_tready (bufin_tready)
+    );
+  
+    genvar vc;
+    for (vc = 0; vc < NUM_VCS; vc = vc + 1) begin
+      if (ROUTING == "WORMHOLE") begin
+        axi_fifo #(
+          .WIDTH(WIDTH+1), .SIZE(SIZE)
+        ) buf_i (
+          .clk      (clk), 
+          .reset    (reset), 
+          .clear    (1'b0),
+          .i_tdata  ({bufin_tlast[vc], bufin_tdata  [(vc*WIDTH)+:WIDTH]}),
+          .i_tvalid (bufin_tvalid [vc]),
+          .i_tready (bufin_tready [vc]),
+          .o_tdata  ({bufout_tlast[vc], bufout_tdata [(vc*WIDTH)+:WIDTH]}),
+          .o_tvalid (bufout_tvalid[vc]),
+          .o_tready (bufout_tready[vc]),
+          .space    (),
+          .occupied ()
+        );
+      end else begin
+        axi_packet_gate #(
+          .WIDTH(WIDTH), .SIZE(SIZE)
+        ) buf_i (
+          .clk      (clk), 
+          .reset    (reset), 
+          .clear    (1'b0),
+          .i_tdata  (bufin_tdata[(vc*WIDTH)+:WIDTH]),
+          .i_tlast  (bufin_tlast[vc]),
+          .i_tvalid (bufin_tvalid[vc]),
+          .i_tready (bufin_tready[vc]),
+          .i_terror (1'b0),
+          .o_tdata  (bufout_tdata[(vc*WIDTH)+:WIDTH]),
+          .o_tlast  (bufout_tlast[vc]),
+          .o_tvalid (bufout_tvalid[vc]),
+          .o_tready (bufout_tready[vc])
+        );
+      end
+    end
+  
+    axi_mux #(
+      .WIDTH(WIDTH), .SIZE(NUM_VCS),
+      .PRE_FIFO_SIZE(0), .POST_FIFO_SIZE(1)
+    ) vc_mux_i (
+      .clk      (clk),
+      .reset    (reset),
+      .clear    (1'b0),
+      .i_tdata  (bufout_tdata ),
+      .i_tlast  (bufout_tlast ),
+      .i_tvalid (bufout_tvalid),
+      .i_tready (bufout_tready),
+      .o_tdata  (m_axis_tdata ),
+      .o_tlast  (m_axis_tlast ),
+      .o_tvalid (m_axis_tvalid),
+      .o_tready (m_axis_tready)
+    );
+
+  end else begin
+    //----------------------------------------------------
+    // Single virtual channel
+    //----------------------------------------------------
+    wire [WIDTH-1:0] pipe_tdata;
+    wire             pipe_tlast;
+    wire             pipe_tvalid;
+    wire             pipe_tready;
+
+    if (ROUTING == "WORMHOLE") begin
+      axi_fifo #(
+        .WIDTH(WIDTH+1), .SIZE(SIZE)
+      ) buf_i (
+        .clk      (clk), 
+        .reset    (reset), 
+        .clear    (1'b0),
+        .i_tdata  ({s_axis_tlast, s_axis_tdata}),
+        .i_tvalid (s_axis_tvalid ),
+        .i_tready (s_axis_tready ),
+        .o_tdata  ({pipe_tlast, pipe_tdata}),
+        .o_tvalid (pipe_tvalid),
+        .o_tready (pipe_tready),
+        .space    (),
+        .occupied ()
+      );
+    end else begin
+      axi_packet_gate #(
+        .WIDTH(WIDTH), .SIZE(SIZE)
+      ) buf_i (
+        .clk      (clk), 
+        .reset    (reset), 
+        .clear    (1'b0),
+        .i_tdata  (s_axis_tdata),
+        .i_tlast  (s_axis_tlast),
+        .i_tvalid (s_axis_tvalid),
+        .i_tready (s_axis_tready),
+        .i_terror (1'b0),
+        .o_tdata  (pipe_tdata),
+        .o_tlast  (pipe_tlast),
+        .o_tvalid (pipe_tvalid),
+        .o_tready (pipe_tready)
+      );
+    end
+
+    axi_fifo #(
+      .WIDTH(WIDTH+1), .SIZE(1)
+    ) buf_i (
+      .clk      (clk), 
+      .reset    (reset), 
+      .clear    (1'b0),
+      .i_tdata  ({pipe_tlast, pipe_tdata}),
+      .i_tvalid (pipe_tvalid ),
+      .i_tready (pipe_tready ),
+      .o_tdata  ({m_axis_tlast, m_axis_tdata}),
+      .o_tvalid (m_axis_tvalid),
+      .o_tready (m_axis_tready),
+      .space    (),
+      .occupied ()
+    );
+
+  end endgenerate
+
+endmodule
+
diff --git a/fpga/usrp3/lib/rfnoc/crossbar/axis_port_terminator.v b/fpga/usrp3/lib/rfnoc/crossbar/axis_port_terminator.v
new file mode 100644
index 000000000..bf9fa24be
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/crossbar/axis_port_terminator.v
@@ -0,0 +1,44 @@
+//
+// Copyright 2018 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: axis_port_terminator
+// Description:
+//   A dummy terminator for unused crossbar ports
+
+module axis_port_terminator #(
+  parameter DATA_W = 64
+) (
+  // Clocks and resets
+  input  wire               clk,
+  input  wire               reset,
+  // Input ports
+  input  wire [DATA_W-1:0]  s_axis_tdata,   // Input data
+  input  wire               s_axis_tlast,   // Input EOP (last)
+  input  wire               s_axis_tvalid,  // Input valid
+  output wire               s_axis_tready,  // Input ready
+  // Output ports
+  output wire [DATA_W-1:0]  m_axis_tdata,   // Output data
+  output wire               m_axis_tlast,   // Output EOP (last) 
+  output wire               m_axis_tvalid,  // Output valid
+  input  wire               m_axis_tready,  // Output ready
+  // Metrics
+  output reg  [15:0]        pkts_dropped
+);
+
+  assign s_axis_tready  = 1'b1;
+  assign m_axis_tdata   = {DATA_W{1'b0}};
+  assign m_axis_tlast   = 1'b0;
+  assign m_axis_tvalid  = 1'b0;
+
+  always @(posedge clk) begin
+    if (reset) begin
+      pkts_dropped <= 'd0;
+    end else if (s_axis_tvalid & s_axis_tlast & s_axis_tready) begin
+      pkts_dropped <= pkts_dropped + 'd1;
+    end
+  end
+
+endmodule
+
diff --git a/fpga/usrp3/lib/rfnoc/crossbar/axis_switch.v b/fpga/usrp3/lib/rfnoc/crossbar/axis_switch.v
new file mode 100644
index 000000000..24b9e4129
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/crossbar/axis_switch.v
@@ -0,0 +1,164 @@
+//
+// Copyright 2018 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: axis_switch
+// Description:
+//   Implementation of a M-input, N-output AXI-Stream switch.
+//   One of the M input ports is allocated based on the s_axis_alloc signal
+//   and the packet on that port is sent to one of the N output ports based
+//   on the tdest signal
+
+module axis_switch #(
+  parameter DATA_W     = 64,    // tdata width
+  parameter DEST_W     = 1,     // Output tdest width
+  parameter IN_PORTS   = 3,     // Number of input ports
+  parameter OUT_PORTS  = 3,     // Number of output ports
+  parameter PIPELINE   = 1,     // Instantiate output pipeline stage?
+  parameter ALLOC_W    = (IN_PORTS == 1) ? 1 : $clog2(IN_PORTS) //PRIVATE
+) (
+  // Clocks and resets
+  input  wire                                             clk,            // Switch clock
+  input  wire                                             reset,          // Reset
+  // Input ports
+  input  wire [(DATA_W*IN_PORTS)-1:0]                     s_axis_tdata,   // Input data
+  input  wire [((DEST_W+$clog2(OUT_PORTS))*IN_PORTS)-1:0] s_axis_tdest,   // Input destination
+  input  wire [IN_PORTS-1:0]                              s_axis_tlast,   // Input EOP (last)
+  input  wire [IN_PORTS-1:0]                              s_axis_tvalid,  // Input valid
+  output wire [IN_PORTS-1:0]                              s_axis_tready,  // Input ready
+  input  wire [ALLOC_W-1:0]                               s_axis_alloc,   // Input port allocation for switch
+  // Output ports
+  output wire [(DATA_W*OUT_PORTS)-1:0]                    m_axis_tdata,   // Output data       
+  output wire [(DEST_W*OUT_PORTS)-1:0]                    m_axis_tdest,   // Output destination
+  output wire [OUT_PORTS-1:0]                             m_axis_tlast,   // Output EOP (last) 
+  output wire [OUT_PORTS-1:0]                             m_axis_tvalid,  // Output valid      
+  input  wire [OUT_PORTS-1:0]                             m_axis_tready   // Output ready      
+);
+  // PRIVATE: Vivado synthesizer workaround (cannot be localparam)
+  localparam CLOG2_IN_PORTS = $clog2(IN_PORTS);
+  localparam CLOG2_OUT_PORTS = $clog2(OUT_PORTS);
+
+  //---------------------------------------------------------
+  // Flatten/unflatten and pipeline
+  //---------------------------------------------------------
+  wire [DATA_W-1:0]                   i_tdata [0:IN_PORTS-1];
+  wire [DEST_W+$clog2(OUT_PORTS)-1:0] i_tdest [0:IN_PORTS-1];
+  wire                                i_tlast [0:IN_PORTS-1];
+  wire [IN_PORTS-1:0]                 i_tvalid;
+  wire [IN_PORTS-1:0]                 i_tready;
+  wire [ALLOC_W-1:0]                  i_alloc;
+  wire [DATA_W-1:0]                   o_tdata [0:OUT_PORTS-1];
+  wire [DEST_W-1:0]                   o_tdest [0:OUT_PORTS-1];
+  wire                                o_tlast [0:OUT_PORTS-1];
+  wire [OUT_PORTS-1:0]                o_tvalid;
+  wire [OUT_PORTS-1:0]                o_tready;
+
+  genvar i, o;
+  generate
+    for (i = 0; i < IN_PORTS; i = i + 1) begin: in_ports
+      assign i_tdata      [i] = s_axis_tdata [(i*DATA_W)+:DATA_W];
+      assign i_tdest      [i] = s_axis_tdest [(i*(DEST_W+CLOG2_OUT_PORTS))+:(DEST_W+CLOG2_OUT_PORTS)];
+      assign i_tlast      [i] = s_axis_tlast [i];
+      assign i_tvalid     [i] = s_axis_tvalid[i];
+      assign s_axis_tready[i] = i_tready     [i];
+    end
+    assign i_alloc = s_axis_alloc;   //i_alloc has to be delay matched to valid
+
+    for (o = 0; o < OUT_PORTS; o = o + 1) begin
+      if (PIPELINE == 1) begin
+        axi_fifo_flop2 #(.WIDTH(DEST_W+1+DATA_W)) out_pipe_i (
+          .clk(clk), .reset(reset), .clear(1'b0),
+          .i_tdata({o_tdest[o], o_tlast[o], o_tdata[o]}),
+          .i_tvalid(o_tvalid[o]), .i_tready(o_tready[o]),
+          .o_tdata({m_axis_tdest[(o*DEST_W)+:DEST_W], m_axis_tlast[o], m_axis_tdata[(o*DATA_W)+:DATA_W]}),
+          .o_tvalid(m_axis_tvalid[o]), .o_tready(m_axis_tready[o]),
+          .space(), .occupied()
+        );
+      end else begin
+        assign m_axis_tdata [(o*DATA_W)+:DATA_W] = o_tdata      [o];
+        assign m_axis_tdest [(o*DEST_W)+:DEST_W] = o_tdest      [o];
+        assign m_axis_tlast [o]                  = o_tlast      [o];
+        assign m_axis_tvalid[o]                  = o_tvalid     [o];
+        assign o_tready     [o]                  = m_axis_tready[o];
+      end
+    end
+  endgenerate
+
+  //---------------------------------------------------------
+  // Allocator
+  //---------------------------------------------------------
+  // The "chosen" input port will drive this bus
+  wire [DATA_W-1:0]                   master_tdata;
+  wire [DEST_W+$clog2(OUT_PORTS)-1:0] master_tdest;
+  wire                                master_tlast;
+  wire                                master_tvalid;
+  wire                                master_tready;
+
+  generate if (IN_PORTS > 1) begin
+    reg [IN_PORTS-1:0] ialloc_oh;
+    reg [$clog2(IN_PORTS)-1:0] alloc_reg;
+    always @(posedge clk) begin
+      if (reset) begin
+        ialloc_oh <= {IN_PORTS{1'b0}};
+      end else begin
+        if (ialloc_oh == {IN_PORTS{1'b0}}) begin
+          if (|i_tvalid) begin
+            ialloc_oh[i_alloc] <= 1'b1;
+            alloc_reg <= i_alloc;
+          end
+        end else begin
+          if(master_tready & master_tvalid & master_tlast)
+            ialloc_oh <= {IN_PORTS{1'b0}};
+        end
+      end
+    end
+
+    assign master_tdata   = i_tdata[alloc_reg];
+    assign master_tdest   = i_tdest[alloc_reg];
+    assign master_tlast   = i_tlast[alloc_reg];
+    assign master_tvalid  = |(i_tvalid & ialloc_oh);
+    assign i_tready       = i_tvalid & ialloc_oh & {IN_PORTS{master_tready}};
+  end else begin
+    // Special case: One input port
+    assign master_tdata   = i_tdata[0];
+    assign master_tdest   = i_tdest[0];
+    assign master_tlast   = i_tlast[0];
+    assign master_tvalid  = i_tvalid[0];
+    assign i_tready[0]    = master_tready;
+  end endgenerate
+
+  //---------------------------------------------------------
+  // Router
+  //---------------------------------------------------------
+  generate if (OUT_PORTS > 1) begin
+    reg [OUT_PORTS-1:0] odst_oh;
+    always @(posedge clk) begin
+      if (reset) begin
+        odst_oh <= {OUT_PORTS{1'b0}};
+      end else begin
+        if (odst_oh == {OUT_PORTS{1'b0}}) begin
+          if (master_tvalid)
+            odst_oh[master_tdest[CLOG2_OUT_PORTS-1:0]] <= 1'b1;
+        end else begin
+          if(master_tready & master_tvalid & master_tlast)
+            odst_oh <= {OUT_PORTS{1'b0}};
+        end
+      end
+    end
+    assign master_tready = |(o_tready & odst_oh);
+    assign o_tvalid = {OUT_PORTS{master_tvalid}} & odst_oh;
+  end else begin
+    // Special case: One output port
+    assign master_tready = o_tready[0];
+    assign o_tvalid[0] = master_tvalid;
+  end endgenerate
+
+  generate for (o = 0; o < OUT_PORTS; o = o + 1) begin
+    assign o_tdata[o] = master_tdata;
+    assign o_tdest[o] = master_tdest[DEST_W+CLOG2_OUT_PORTS-1:CLOG2_OUT_PORTS];
+    assign o_tlast[o] = master_tlast;
+  end endgenerate
+
+endmodule
+
diff --git a/fpga/usrp3/lib/rfnoc/crossbar/chdr_crossbar_nxn.v b/fpga/usrp3/lib/rfnoc/crossbar/chdr_crossbar_nxn.v
new file mode 100644
index 000000000..79f1a6626
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/crossbar/chdr_crossbar_nxn.v
@@ -0,0 +1,381 @@
+//
+// Copyright 2018 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: chdr_crossbar_nxn
+// Description: 
+//   This module implements a full-bandwidth NxN crossbar with N input and output ports
+//   for CHDR traffic. It supports multiple optimization strategies for performance,
+//   area and timing tradeoffs. It uses AXI-Stream for all of its links. The crossbar
+//   has a dynamic routing table based on a Content Addressable Memory (CAM). The SID
+//   is used to determine the destination of a packet and the routing table contains
+//   a re-programmable SID to crossbar port mapping. The table is programmed using
+//   special route config packets on the data input ports or using an optional
+//   management port.
+//   The topology, routing algorithms and the router architecture is 
+//   described in README.md in this directory. 
+// Parameters:
+//   - CHDR_W: Width of the AXI-Stream data bus
+//   - NPORTS: Number of ports to instantiate
+//   - DEFAULT_PORT: The failsafe port to forward a packet to is SID mapping is missing
+//   - MTU: log2 of max packet size (in words)
+//   - ROUTE_TBL_SIZE: log2 of the number of mappings that the routing table can hold 
+//     at any time. Mapping values are maintained in a FIFO fashion.
+//   - MUX_ALLOC: Algorithm to allocate the egress MUX
+//     * PRIO: Priority based. Lower port numbers have a higher priority
+//     * ROUND-ROBIN: Round robin input port allocation
+//   - OPTIMIZE: Optimization strategy for performance vs area vs timing tradeoffs
+//     * AREA: Attempt to minimize area at the cost of performance (throughput) and/or timing
+//     * PERFORMANCE: Attempt to maximize performance at the cost of area and/or timing
+//     * TIMING: Attempt to maximize Fmax at the cost of area and/or performance
+//   - NPORTS_MGMT: Number of ports with management endpoint. The first NPORTS_MGMT ports will
+//     have the management port instantiated
+//   - EXT_RTCFG_PORT: Enable a side-channel AXI-Stream management port to configure the
+//     routing table
+// Signals:
+//   - s_axis_*: Slave port for router (flattened)
+//   - m_axis_*: Master port for router (flattened)
+//   - s_axis_mgmt_*: Management slave port
+//   - device_id: The ID of the device that has instantiated this module
+//
+
+module chdr_crossbar_nxn #(
+  parameter [15:0] PROTOVER       = {8'd1, 8'd0},
+  parameter        CHDR_W         = 64,
+  parameter [7:0]  NPORTS         = 8,
+  parameter [7:0]  DEFAULT_PORT   = 0,
+  parameter        MTU            = 9,
+  parameter        ROUTE_TBL_SIZE = 6,
+  parameter        MUX_ALLOC      = "ROUND-ROBIN",
+  parameter        OPTIMIZE       = "AREA",
+  parameter [7:0]  NPORTS_MGMT    = NPORTS,
+  parameter [0:0]  EXT_RTCFG_PORT = 0
+) (
+  input  wire                       clk,
+  input  wire                       reset,
+  // Device info
+  input  wire [15:0]                device_id,
+  // Inputs
+  input  wire [(CHDR_W*NPORTS)-1:0] s_axis_tdata,
+  input  wire [NPORTS-1:0]          s_axis_tlast,
+  input  wire [NPORTS-1:0]          s_axis_tvalid,
+  output wire [NPORTS-1:0]          s_axis_tready,
+  // Output
+  output wire [(CHDR_W*NPORTS)-1:0] m_axis_tdata,
+  output wire [NPORTS-1:0]          m_axis_tlast,
+  output wire [NPORTS-1:0]          m_axis_tvalid,
+  input  wire [NPORTS-1:0]          m_axis_tready,
+  // Router config management port
+  input  wire                       ext_rtcfg_stb,
+  input  wire [15:0]                ext_rtcfg_addr,
+  input  wire [31:0]                ext_rtcfg_data,
+  output wire                       ext_rtcfg_ack
+);
+  // ---------------------------------------------------
+  //  RFNoC Includes
+  // ---------------------------------------------------
+  `include "../core/rfnoc_chdr_utils.vh"
+  `include "../core/rfnoc_chdr_internal_utils.vh"
+
+  localparam        NPORTS_W = $clog2(NPORTS);
+  localparam        EPID_W   = 16;
+  localparam [17:0] EXT_INFO = {1'b0, EXT_RTCFG_PORT, NPORTS_MGMT, NPORTS};
+
+  localparam [0:0] PKT_ST_HEAD = 1'b0;
+  localparam [0:0] PKT_ST_BODY = 1'b1;
+
+  // The compute_mux_alloc function is the switch allocation function for the MUX 
+  // i.e. it chooses which input port reserves the output MUX for packet transfer.
+  function [NPORTS_W-1:0] compute_mux_alloc;
+    input [NPORTS-1:0] pkt_waiting;
+    input [NPORTS_W-1:0] last_alloc;
+    reg signed [NPORTS_W:0] i;
+  begin
+    compute_mux_alloc = last_alloc;
+    for (i = NPORTS-1; i >= 0; i=i-1) begin
+      if (MUX_ALLOC == "PRIO") begin
+        // Priority. Lower port index gets a higher priority.
+        if (pkt_waiting[i])
+          compute_mux_alloc = i;
+      end else begin
+        // Round-robin
+        if (pkt_waiting[(last_alloc + i + 1) % NPORTS])
+          compute_mux_alloc = (last_alloc + i + 1) % NPORTS;
+      end
+    end
+  end
+  endfunction
+
+  wire [NPORTS-1:0]            rtcfg_req_wr;
+  wire [(16*NPORTS)-1:0]       rtcfg_req_addr;
+  wire [(32*NPORTS)-1:0]       rtcfg_req_data;
+  wire [NPORTS-1:0]            rtcfg_resp_ack;
+  wire [(EPID_W*NPORTS)-1:0]   find_tdata;
+  wire [NPORTS-1:0]            find_tvalid;
+  wire [NPORTS-1:0]            find_tready;
+  wire [(NPORTS_W*NPORTS)-1:0] result_tdata;
+  wire [NPORTS-1:0]            result_tkeep;
+  wire [NPORTS-1:0]            result_tvalid;
+  wire [NPORTS-1:0]            result_tready;
+
+  // Instantiate a single CAM-based routing table that will be shared between all
+  // input ports. Configuration and lookup is performed using an AXI-Stream iface.
+  // If multiple packets arrive simultaneously, only the headers of those packets will
+  // be serialized in order to arbitrate this map. Selection is done round-robin.
+  chdr_xb_routing_table #(
+    .SIZE(ROUTE_TBL_SIZE), .NPORTS(NPORTS),
+    .EXT_INS_PORT_EN(EXT_RTCFG_PORT)
+  ) routing_tbl_i (
+    .clk               (clk           ),
+    .reset             (reset         ),
+    .port_req_wr       (rtcfg_req_wr  ),
+    .port_req_addr     (rtcfg_req_addr),
+    .port_req_data     (rtcfg_req_data),
+    .port_resp_ack     (rtcfg_resp_ack),
+    .ext_req_wr        (ext_rtcfg_stb ),
+    .ext_req_addr      (ext_rtcfg_addr),
+    .ext_req_data      (ext_rtcfg_data),
+    .ext_resp_ack      (ext_rtcfg_ack ),
+    .axis_find_tdata   (find_tdata    ),
+    .axis_find_tvalid  (find_tvalid   ),
+    .axis_find_tready  (find_tready   ),
+    .axis_result_tdata (result_tdata  ),
+    .axis_result_tkeep (result_tkeep  ),
+    .axis_result_tvalid(result_tvalid ),
+    .axis_result_tready(result_tready )
+  );
+
+  wire [CHDR_W-1:0]          i_tdata   [0:NPORTS-1];
+  wire [9:0]                 i_tdest   [0:NPORTS-1];
+  wire [1:0]                 i_tid     [0:NPORTS-1];
+  wire                       i_tlast   [0:NPORTS-1];
+  wire                       i_tvalid  [0:NPORTS-1];
+  wire                       i_tready  [0:NPORTS-1];
+  wire [CHDR_W-1:0]          buf_tdata [0:NPORTS-1];
+  wire [NPORTS_W-1:0]        buf_tdest [0:NPORTS-1], buf_tdest_tmp[0:NPORTS-1];
+  wire                       buf_tkeep [0:NPORTS-1];
+  wire                       buf_tlast [0:NPORTS-1];
+  wire                       buf_tvalid[0:NPORTS-1];
+  wire                       buf_tready[0:NPORTS-1];
+  wire [CHDR_W-1:0]          swi_tdata [0:NPORTS-1];
+  wire [NPORTS_W-1:0]        swi_tdest [0:NPORTS-1];
+  wire                       swi_tlast [0:NPORTS-1];
+  wire                       swi_tvalid[0:NPORTS-1];
+  wire                       swi_tready[0:NPORTS-1];
+  wire [(CHDR_W*NPORTS)-1:0] swo_tdata [0:NPORTS-1], muxi_tdata [0:NPORTS-1];
+  wire [NPORTS-1:0]          swo_tlast [0:NPORTS-1], muxi_tlast [0:NPORTS-1];
+  wire [NPORTS-1:0]          swo_tvalid[0:NPORTS-1], muxi_tvalid[0:NPORTS-1];
+  wire [NPORTS-1:0]          swo_tready[0:NPORTS-1], muxi_tready[0:NPORTS-1];
+
+  genvar n, i, j;
+  generate
+    for (n = 0; n < NPORTS; n = n + 1) begin: i_ports
+      // For each input port, first check if we have a management packet
+      // arriving. If it arrives, the top config commands are extrated, sent to the
+      // routing table for configuration, and the rest of the packet is forwarded
+      // down to the router.
+      // the router.
+      if (n < NPORTS_MGMT) begin
+        chdr_mgmt_pkt_handler #(
+          .PROTOVER(PROTOVER), .CHDR_W(CHDR_W), .MGMT_ONLY(0)
+        ) mgmt_ep_i (
+          .clk                (clk                                                              ),
+          .rst                (reset                                                            ),
+          .node_info          (chdr_mgmt_build_node_info(EXT_INFO, n, NODE_TYPE_XBAR, device_id)),
+          .s_axis_chdr_tdata  (s_axis_tdata [(n*CHDR_W)+:CHDR_W]                                ),
+          .s_axis_chdr_tlast  (s_axis_tlast [n]                                                 ),
+          .s_axis_chdr_tvalid (s_axis_tvalid[n]                                                 ),
+          .s_axis_chdr_tready (s_axis_tready[n]                                                 ),
+          .s_axis_chdr_tuser  ('d0                                                              ),
+          .m_axis_chdr_tdata  (i_tdata      [n]                                                 ),
+          .m_axis_chdr_tdest  (i_tdest      [n]                                                 ), 
+          .m_axis_chdr_tid    (i_tid        [n]                                                 ),
+          .m_axis_chdr_tlast  (i_tlast      [n]                                                 ),
+          .m_axis_chdr_tvalid (i_tvalid     [n]                                                 ),
+          .m_axis_chdr_tready (i_tready     [n]                                                 ),
+          .ctrlport_req_wr    (rtcfg_req_wr [n]                                                 ),
+          .ctrlport_req_rd    (/* unused */                                                     ),
+          .ctrlport_req_addr  (rtcfg_req_addr[(n*16)+:16]                                       ),
+          .ctrlport_req_data  (rtcfg_req_data[(n*32)+:32]                                       ),
+          .ctrlport_resp_ack  (rtcfg_resp_ack[n]                                                ),
+          .ctrlport_resp_data (32'h0 /* unused */                                               ),
+          .op_stb             (/* unused */                                                     ),
+          .op_dst_epid        (/* unused */                                                     ),
+          .op_src_epid        (/* unused */                                                     ),
+          .op_data            (/* unused */                                                     )
+        );
+      end else begin
+        assign i_tdata      [n] = s_axis_tdata [(n*CHDR_W)+:CHDR_W];
+        assign i_tid        [n] = CHDR_MGMT_ROUTE_EPID;
+        assign i_tdest      [n] = 10'd0;  // Unused
+        assign i_tlast      [n] = s_axis_tlast [n];
+        assign i_tvalid     [n] = s_axis_tvalid[n];
+        assign s_axis_tready[n] = i_tready     [n];
+
+        assign rtcfg_req_wr  [n]          =  1'b0;
+        assign rtcfg_req_addr[(n*16)+:16] = 16'h0;
+        assign rtcfg_req_data[(n*32)+:32] = 32'h0;
+      end
+
+      // Ingress buffer module that does the following:
+      // - Stores and gates an incoming packet
+      // - Looks up destination in routing table and attaches a tdest for the packet
+      chdr_xb_ingress_buff #(
+        .WIDTH(CHDR_W), .MTU(MTU), .DEST_W(NPORTS_W), .NODE_ID(n)
+      ) buf_i (
+        .clk                 (clk                                  ),
+        .reset               (reset                                ),
+        .s_axis_chdr_tdata   (i_tdata      [n]                     ),
+        .s_axis_chdr_tdest   (i_tdest      [n][NPORTS_W-1:0]       ),
+        .s_axis_chdr_tid     (i_tid        [n]                     ),
+        .s_axis_chdr_tlast   (i_tlast      [n]                     ),
+        .s_axis_chdr_tvalid  (i_tvalid     [n]                     ),
+        .s_axis_chdr_tready  (i_tready     [n]                     ),
+        .m_axis_chdr_tdata   (buf_tdata    [n]                     ),
+        .m_axis_chdr_tdest   (buf_tdest_tmp[n]                     ),
+        .m_axis_chdr_tkeep   (buf_tkeep    [n]                     ),
+        .m_axis_chdr_tlast   (buf_tlast    [n]                     ),
+        .m_axis_chdr_tvalid  (buf_tvalid   [n]                     ),
+        .m_axis_chdr_tready  (buf_tready   [n]                     ),
+        .m_axis_find_tdata   (find_tdata   [(n*EPID_W)+:EPID_W]    ),
+        .m_axis_find_tvalid  (find_tvalid  [n]                     ),
+        .m_axis_find_tready  (find_tready  [n]                     ),
+        .s_axis_result_tdata (result_tdata [(n*NPORTS_W)+:NPORTS_W]),
+        .s_axis_result_tkeep (result_tkeep [n]                     ),
+        .s_axis_result_tvalid(result_tvalid[n]                     ),
+        .s_axis_result_tready(result_tready[n]                     )
+      );
+      assign buf_tdest[n] = buf_tkeep[n] ? buf_tdest_tmp[n] : DEFAULT_PORT[NPORTS_W-1:0];
+
+      // Pipeline state
+      axi_fifo #(
+        .WIDTH(CHDR_W+1+NPORTS_W), .SIZE(1)
+      ) pipe_i (
+        .clk      (clk                                       ), 
+        .reset    (reset                                     ), 
+        .clear    (1'b0                                      ),
+        .i_tdata  ({buf_tlast[n], buf_tdest[n], buf_tdata[n]}),
+        .i_tvalid (buf_tvalid[n]                             ),
+        .i_tready (buf_tready[n]                             ),
+        .o_tdata  ({swi_tlast[n], swi_tdest[n], swi_tdata[n]}),
+        .o_tvalid (swi_tvalid[n]                             ),
+        .o_tready (swi_tready[n]                             ),
+        .space    (/* Unused */                              ),
+        .occupied (/* Unused */                              )
+      );
+
+      // Ingress demux. Use the tdest field to determine packet destination
+      axis_switch #(
+        .DATA_W(CHDR_W), .DEST_W(1), .IN_PORTS(1), .OUT_PORTS(NPORTS), .PIPELINE(1)
+      ) demux_i (
+        .clk           (clk                  ),
+        .reset         (reset                ),
+        .s_axis_tdata  (swi_tdata [n]        ),
+        .s_axis_tdest  ({1'b0, swi_tdest [n]}), 
+        .s_axis_tlast  (swi_tlast [n]        ),
+        .s_axis_tvalid (swi_tvalid[n]        ),
+        .s_axis_tready (swi_tready[n]        ),
+        .s_axis_alloc  (1'b0                 ),
+        .m_axis_tdata  (swo_tdata [n]        ),
+        .m_axis_tdest  (/* Unused */         ),
+        .m_axis_tlast  (swo_tlast [n]        ),
+        .m_axis_tvalid (swo_tvalid[n]        ),
+        .m_axis_tready (swo_tready[n]        )
+      );
+    end
+
+    for (i = 0; i < NPORTS; i = i + 1) begin
+      for (j = 0; j < NPORTS; j = j + 1) begin
+        assign muxi_tdata [i][j*CHDR_W+:CHDR_W] = swo_tdata  [j][i*CHDR_W+:CHDR_W];
+        assign muxi_tlast [i][j]                = swo_tlast  [j][i];
+        assign muxi_tvalid[i][j]                = swo_tvalid [j][i];
+        assign swo_tready [i][j]                = muxi_tready[j][i];
+      end
+    end
+
+    for (n = 0; n < NPORTS; n = n + 1) begin: o_ports
+      if (OPTIMIZE == "PERFORMANCE") begin
+        // Use the axis_switch module when optimizing for performance
+        // This logic has some extra levels of logic to ensure
+        // that the switch allocation happens in 0 clock cycles which
+        // means that Fmax for this implementation will be lower.
+
+        wire mux_ready = |muxi_tready[n];   // Max 1 bit should be high
+        wire mux_valid = |muxi_tvalid[n];
+        wire mux_last  = |(muxi_tvalid[n] & muxi_tlast[n]);
+  
+        // Track the input packet state
+        reg [0:0] pkt_state = PKT_ST_HEAD;
+        always @(posedge clk) begin
+          if (reset) begin
+            pkt_state <= PKT_ST_HEAD;
+          end else if (mux_valid & mux_ready) begin
+            pkt_state <= mux_last ? PKT_ST_HEAD : PKT_ST_BODY;
+          end
+        end
+  
+        // The switch requires the allocation to stay valid until the
+        // end of the packet. We also might need to keep the previous
+        // packet's allocation to compute the current one
+        reg  [NPORTS_W-1:0] prev_sw_alloc = {NPORTS_W{1'b0}};
+        reg  [NPORTS_W-1:0] pkt_sw_alloc  = {NPORTS_W{1'b0}};
+        wire [NPORTS_W-1:0] muxi_sw_alloc = (mux_valid && pkt_state == PKT_ST_HEAD) ? 
+          compute_mux_alloc(muxi_tvalid[n], prev_sw_alloc) : pkt_sw_alloc;
+  
+        always @(posedge clk) begin
+          if (reset) begin
+            prev_sw_alloc <= {NPORTS_W{1'b0}};
+            pkt_sw_alloc <= {NPORTS_W{1'b0}};
+          end else if (mux_valid & mux_ready) begin
+            if (pkt_state == PKT_ST_HEAD)
+              pkt_sw_alloc <= muxi_sw_alloc;
+            if (mux_last)
+              prev_sw_alloc <= muxi_sw_alloc;
+          end
+        end
+  
+        axis_switch #(
+          .DATA_W(CHDR_W), .DEST_W(1), .IN_PORTS(NPORTS), .OUT_PORTS(1),
+          .PIPELINE(0)
+        ) mux_i (
+          .clk           (clk                              ),
+          .reset         (reset                            ),
+          .s_axis_tdata  (muxi_tdata [n]                   ),
+          .s_axis_tdest  ({NPORTS{1'b0}} /* Unused */      ),
+          .s_axis_tlast  (muxi_tlast [n]                   ),
+          .s_axis_tvalid (muxi_tvalid[n]                   ),
+          .s_axis_tready (muxi_tready[n]                   ),
+          .s_axis_alloc  (muxi_sw_alloc                    ),
+          .m_axis_tdata  (m_axis_tdata [(n*CHDR_W)+:CHDR_W]),
+          .m_axis_tdest  (/* Unused */                     ),
+          .m_axis_tlast  (m_axis_tlast [n]                 ),
+          .m_axis_tvalid (m_axis_tvalid[n]                 ),
+          .m_axis_tready (m_axis_tready[n]                 )
+        );
+      end else begin
+        // axi_mux has an additional bubble cycle but the logic
+        // to allocate an input port has fewer levels and takes
+        // up fewer resources.
+        axi_mux #(
+          .PRIO(MUX_ALLOC == "PRIO"), .WIDTH(CHDR_W), .SIZE(NPORTS),
+          .PRE_FIFO_SIZE(OPTIMIZE == "TIMING" ? 1 : 0), .POST_FIFO_SIZE(1)
+        ) mux_i (
+          .clk      (clk                              ),
+          .reset    (reset                            ),
+          .clear    (1'b0                             ),
+          .i_tdata  (muxi_tdata   [n]                 ),
+          .i_tlast  (muxi_tlast   [n]                 ),
+          .i_tvalid (muxi_tvalid  [n]                 ),
+          .i_tready (muxi_tready  [n]                 ),
+          .o_tdata  (m_axis_tdata [(n*CHDR_W)+:CHDR_W]),
+          .o_tlast  (m_axis_tlast [n]                 ),
+          .o_tvalid (m_axis_tvalid[n]                 ),
+          .o_tready (m_axis_tready[n]                 )
+        );
+      end
+    end
+  endgenerate
+
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/crossbar/chdr_xb_ingress_buff.v b/fpga/usrp3/lib/rfnoc/crossbar/chdr_xb_ingress_buff.v
new file mode 100644
index 000000000..dcb11da8e
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/crossbar/chdr_xb_ingress_buff.v
@@ -0,0 +1,259 @@
+//
+// Copyright 2018 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: chdr_ingress_buff
+//
+// Description:
+//
+//   Ingress buffer module for the CHDR crossbar. This module stores and gates
+//   the incoming packet and simultaneously determines the destination (TDEST)
+//   by inspecting the incoming TID. If the TID is CHDR_MGMT_ROUTE_EPID then we
+//   perform a lookup on the TID to determine the correct output for TDEST.
+//
+// Parameters:
+//
+//   WIDTH   : Data width of the CHDR interfaces (TDATA)
+//   MTU     : Maximum transmission unit, in WIDTH-sized words, is 2**MTU
+//   DEST_W  : Width of the destination routing information (TDEST)
+//   NODE_ID : Numeric identifier for this port
+//
+
+module chdr_xb_ingress_buff #(
+  parameter       WIDTH   = 64,
+  parameter       MTU     = 5,
+  parameter       DEST_W  = 4,
+  parameter [9:0] NODE_ID = 0
+) (
+  input  wire               clk,
+  input  wire               reset,
+  // CHDR input port
+  input  wire [WIDTH-1:0]   s_axis_chdr_tdata,
+  input  wire [DEST_W-1:0]  s_axis_chdr_tdest,
+  input  wire [1:0]         s_axis_chdr_tid,
+  input  wire               s_axis_chdr_tlast,
+  input  wire               s_axis_chdr_tvalid,
+  output wire               s_axis_chdr_tready,
+  // CHDR output port (with a tdest and tkeep)
+  output wire [WIDTH-1:0]   m_axis_chdr_tdata,
+  output wire [DEST_W-1:0]  m_axis_chdr_tdest,
+  output wire               m_axis_chdr_tkeep,
+  output wire               m_axis_chdr_tlast,
+  output wire               m_axis_chdr_tvalid,
+  input  wire               m_axis_chdr_tready,
+  // Find port going to routing table
+  output wire [15:0]        m_axis_find_tdata,
+  output wire               m_axis_find_tvalid,
+  input  wire               m_axis_find_tready,
+  // Result port from routing table
+  input  wire [DEST_W-1:0]  s_axis_result_tdata,
+  input  wire               s_axis_result_tkeep,
+  input  wire               s_axis_result_tvalid,
+  output wire               s_axis_result_tready
+);
+
+  // RFNoC Includes
+  `include "../core/rfnoc_chdr_utils.vh"
+  `include "../core/rfnoc_chdr_internal_utils.vh"
+
+
+  //---------------------------------------------------------------------------
+  // Packet Buffer
+  //---------------------------------------------------------------------------
+
+  wire [WIDTH-1:0]  gate_i_tdata , gate_o_tdata ;
+  wire              gate_i_tlast , gate_o_tlast ;
+  wire              gate_i_tvalid, gate_o_tvalid;
+  wire              gate_i_tready, gate_o_tready;
+
+  // The axi_packet_gate queues up an entire packet before letting it go out.
+  // This reduces congestion in the crossbar for slowly-built packets.
+  axi_packet_gate #(
+    .WIDTH (WIDTH),
+    .SIZE  (MTU)
+  ) axi_packet_gate_i (
+    .clk      (clk),
+    .reset    (reset),
+    .clear    (1'b0),
+    .i_tdata  (gate_i_tdata),
+    .i_tlast  (gate_i_tlast),
+    .i_terror (1'b0),
+    .i_tvalid (gate_i_tvalid),
+    .i_tready (gate_i_tready),
+    .o_tdata  (gate_o_tdata),
+    .o_tlast  (gate_o_tlast),
+    .o_tvalid (gate_o_tvalid),
+    .o_tready (gate_o_tready)
+  );
+
+
+  //---------------------------------------------------------------------------
+  // Destination (TDEST) Muxing
+  //---------------------------------------------------------------------------
+
+  wire [15:0]       find_tdata;
+  wire              find_tvalid, find_tready;
+
+  wire [DEST_W-1:0] dest_i_tdata;
+  wire              dest_i_tkeep, dest_i_tvalid, dest_i_tready;
+  wire [DEST_W-1:0] dest_o_tdata;
+  wire              dest_o_tkeep, dest_o_tvalid, dest_o_tready;
+
+  // The find_fifo holds the lookup requests from the find_* AXI stream and
+  // sends them on to the m_axis_find_* stream port. It is required because the
+  // input logic (see below) doesn't obey the AXI handshake protocol but this
+  // FIFO can tolerate it.
+  axi_fifo #(
+    .WIDTH (16),
+    .SIZE  (1)
+  ) find_fifo_i (
+    .clk      (clk),
+    .reset    (reset),
+    .clear    (1'b0),
+    .i_tdata  (find_tdata),
+    .i_tvalid (find_tvalid),
+    .i_tready (find_tready),
+    .o_tdata  (m_axis_find_tdata),
+    .o_tvalid (m_axis_find_tvalid),
+    .o_tready (m_axis_find_tready),
+    .space    (),
+    .occupied ()
+  );
+
+  // The destination (TDEST) can come from two sources: Directly from the
+  // packet info (in which case TDEST was immediately determined and comes in
+  // on dest_* AXI stream) or via a lookup (in which case the result comes in
+  // on s_axis_result_*). Only one of these data paths is used at a time, so we
+  // mux them together here create a single stream (dest_o_*) that contains the
+  // destination for the next packet.
+  axi_mux #(
+    .WIDTH          (DEST_W+1),
+    .SIZE           (2),
+    .PRIO           (1),
+    .PRE_FIFO_SIZE  (1),
+    .POST_FIFO_SIZE (1)
+  ) dest_mux_i (
+    .clk      (clk),
+    .reset    (reset),
+    .clear    (1'b0),
+    .i_tdata  ({dest_i_tkeep, dest_i_tdata, 
+                s_axis_result_tkeep, s_axis_result_tdata}),
+    .i_tlast  (2'b11),
+    .i_tvalid ({dest_i_tvalid, s_axis_result_tvalid}),
+    .i_tready ({dest_i_tready, s_axis_result_tready}),
+    .o_tdata  ({dest_o_tkeep, dest_o_tdata}),
+    .o_tlast  (),
+    .o_tvalid (dest_o_tvalid),
+    .o_tready (dest_o_tready)
+  );
+
+
+  //---------------------------------------------------------------------------
+  // Input Logic
+  //---------------------------------------------------------------------------
+  //
+  // When a packet comes in, we may have to do one of the following:
+  //   1) Lookup the TDEST using the EPID
+  //   2) Use the specified input TDEST
+  //   3) Use the NODE_ID as the TDEST (to return the packet)
+  //
+  //---------------------------------------------------------------------------
+
+  // The s_axis_chdr_hdr_valid signal indicates when TDATA and TID contain the
+  // header information for the current packet.
+  reg s_axis_chdr_hdr_valid = 1'b1;
+
+  always @(posedge clk) begin
+    if (reset) begin
+      s_axis_chdr_hdr_valid <= 1'b1;
+    end else if (s_axis_chdr_tvalid & s_axis_chdr_tready) begin
+      s_axis_chdr_hdr_valid <= s_axis_chdr_tlast;
+    end
+  end
+
+  // The dest_find_tready signal indicates if the find_fifo is ready or if the
+  // dest port of the dest_muax is ready, depending on which path will be used.
+  reg dest_find_tready;
+
+  always @(*) begin
+    if (s_axis_chdr_hdr_valid) begin
+      case (s_axis_chdr_tid)
+        CHDR_MGMT_ROUTE_EPID:
+          dest_find_tready = find_tready;
+        CHDR_MGMT_ROUTE_TDEST:
+          dest_find_tready = dest_i_tready;
+        CHDR_MGMT_RETURN_TO_SRC:
+          dest_find_tready = dest_i_tready;
+        default:
+          dest_find_tready = dest_i_tready; // We should never get here
+      endcase
+    end else begin
+      dest_find_tready = 1'b1;
+    end
+  end
+
+  // We can accept a transfer from the input CHDR stream only if the the packet
+  // gate and dest/find datapaths are ready.
+  assign s_axis_chdr_tready = s_axis_chdr_tvalid &&
+                              gate_i_tready      &&
+                              dest_find_tready;
+
+  // The chdr_header_stb signal indicates when we write data into the dest/find
+  // data path. This happens when we're accepting the header word of the packet
+  // into the packet gate.
+  wire chdr_header_stb = s_axis_chdr_tvalid &&
+                         s_axis_chdr_tready &&
+                         s_axis_chdr_hdr_valid;
+
+  // **************************************************************************
+  // WARNING: The logic below violates AXI-Stream by having a tready -> tvalid
+  //          dependency To ensure no deadlocks, we must place FIFOs downstream
+  //          of gate_i_*, find_* and dest_i_*
+
+  // Here we decide if we need to do a lookup using the find_* path or if the
+  // destination is known and can be put directly on the dest_* path.
+  //
+  // Start a lookup request if the TID is CHDR_MGMT_ROUTE_EPID.
+  assign find_tdata  = chdr_get_dst_epid(s_axis_chdr_tdata[63:0]);
+  assign find_tvalid = chdr_header_stb && 
+                       (s_axis_chdr_tid == CHDR_MGMT_ROUTE_EPID);
+  // Set TDEST directly if TID is CHDR_MGMT_ROUTE_TDEST or
+  // CHDR_MGMT_RETURN_TO_SRC.
+  assign dest_i_tdata  = (s_axis_chdr_tid == CHDR_MGMT_ROUTE_TDEST) ? 
+                         s_axis_chdr_tdest : NODE_ID[DEST_W-1:0];
+  assign dest_i_tkeep  = 1'b1;
+  assign dest_i_tvalid = chdr_header_stb && 
+                         (s_axis_chdr_tid != CHDR_MGMT_ROUTE_EPID);
+
+  // Input logic for axi_packet_gate
+  assign gate_i_tdata  = s_axis_chdr_tdata;
+  assign gate_i_tlast  = s_axis_chdr_tlast;
+  assign gate_i_tvalid = s_axis_chdr_tready && s_axis_chdr_tvalid;
+
+  //
+  // **************************************************************************
+
+
+  //---------------------------------------------------------------------------
+  // Output Logic
+  //---------------------------------------------------------------------------
+  //
+  // The destination for the packet (TDEST) must be valid before we allow the
+  // header of the packet to pass through. So the packet must be blocked until
+  // the output of the dest_o_* is valid. TDEST and TKEEP must remain valid
+  // until the end of the packet.
+  //
+  //---------------------------------------------------------------------------
+
+  assign m_axis_chdr_tdata  = gate_o_tdata;
+  assign m_axis_chdr_tlast  = gate_o_tlast;
+  assign m_axis_chdr_tdest  = dest_o_tdata;
+  assign m_axis_chdr_tkeep  = dest_o_tkeep;
+  assign m_axis_chdr_tvalid = gate_o_tvalid && dest_o_tvalid;
+
+  assign gate_o_tready = m_axis_chdr_tvalid && m_axis_chdr_tready;
+  assign dest_o_tready = m_axis_chdr_tvalid && m_axis_chdr_tready && m_axis_chdr_tlast;
+
+endmodule
+
diff --git a/fpga/usrp3/lib/rfnoc/crossbar/chdr_xb_routing_table.v b/fpga/usrp3/lib/rfnoc/crossbar/chdr_xb_routing_table.v
new file mode 100644
index 000000000..f445efc68
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/crossbar/chdr_xb_routing_table.v
@@ -0,0 +1,122 @@
+//
+// Copyright 2018 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: chdr_xb_routing_table
+// Description:
+//   A routing table for the CHDR crossbar. This table is designed
+//   to be shared between all ports. It has an AXI-Stream lookup
+//   interface and a ctrlport (reduced) configuration interface.
+
+module chdr_xb_routing_table #(
+  parameter SIZE            = 6,
+  parameter NPORTS          = 4,
+  parameter EXT_INS_PORT_EN = 1
+) (
+  // Clocks and resets
+  input  wire                               clk,
+  input  wire                               reset,
+  // Insertion Interface (for XB ports)
+  input  wire [NPORTS-1:0]                  port_req_wr,
+  input  wire [(16*NPORTS)-1:0]             port_req_addr,
+  input  wire [(32*NPORTS)-1:0]             port_req_data,
+  output wire [NPORTS-1:0]                  port_resp_ack,
+  // Insertion Interface (External)         
+  input  wire                               ext_req_wr,
+  input  wire [15:0]                        ext_req_addr,
+  input  wire [31:0]                        ext_req_data,
+  output wire                               ext_resp_ack,
+  // Find Interface                         
+  input  wire [(16*NPORTS)-1:0]             axis_find_tdata,
+  input  wire [NPORTS-1:0]                  axis_find_tvalid,
+  output wire [NPORTS-1:0]                  axis_find_tready,
+  // Result Interface (for Find)
+  output wire [($clog2(NPORTS)*NPORTS)-1:0] axis_result_tdata,
+  output wire [NPORTS-1:0]                  axis_result_tkeep,
+  output wire [NPORTS-1:0]                  axis_result_tvalid,
+  input  wire [NPORTS-1:0]                  axis_result_tready
+);
+  localparam NPORTS_W   = $clog2(NPORTS);
+  localparam CFG_W      = NPORTS_W + 16;
+  localparam CFG_PORTS  = NPORTS + EXT_INS_PORT_EN;
+
+  // CAM-based lookup table
+
+  wire [15:0]         insert_tdest;
+  wire [NPORTS_W-1:0] insert_tdata;
+  wire                insert_tvalid;
+  wire                insert_tready;
+
+  axis_muxed_kv_map #(
+    .KEY_WIDTH(16), .VAL_WIDTH(NPORTS_W),
+    .SIZE(SIZE), .NUM_PORTS(NPORTS)
+  ) kv_map_i (
+    .clk               (clk               ),
+    .reset             (reset               ),
+    .axis_insert_tdata (insert_tdata      ),
+    .axis_insert_tdest (insert_tdest      ),
+    .axis_insert_tvalid(insert_tvalid     ),
+    .axis_insert_tready(insert_tready     ),
+    .axis_find_tdata   (axis_find_tdata   ),
+    .axis_find_tvalid  (axis_find_tvalid  ),
+    .axis_find_tready  (axis_find_tready  ),
+    .axis_result_tdata (axis_result_tdata ),
+    .axis_result_tkeep (axis_result_tkeep ),
+    .axis_result_tvalid(axis_result_tvalid),
+    .axis_result_tready(axis_result_tready)
+  );
+
+  // Logic to convert from ctrlport to AXI-Stream
+
+  wire                ins_req_wr  [0:CFG_PORTS-1];
+  wire [15:0]         ins_req_addr[0:CFG_PORTS-1];
+  wire [NPORTS_W-1:0] ins_req_data[0:CFG_PORTS-1];
+  wire                ins_resp_ack[0:CFG_PORTS-1];
+
+  reg  [(CFG_PORTS*CFG_W)-1:0] cfg_tdata;
+  reg  [CFG_PORTS-1:0] cfg_tvalid = {CFG_PORTS{1'b0}};
+  wire [CFG_PORTS-1:0] cfg_tready;
+
+  genvar i;
+  generate for (i = 0; i < CFG_PORTS; i=i+1) begin
+    assign ins_req_wr  [i] = (i < NPORTS) ? port_req_wr[i]                  : ext_req_wr;
+    assign ins_req_addr[i] = (i < NPORTS) ? port_req_addr[i*16 +: 16]       : ext_req_addr;
+    assign ins_req_data[i] = (i < NPORTS) ? port_req_data[i*32 +: NPORTS_W] : ext_req_data[NPORTS_W-1:0];
+    if (i < NPORTS)
+      assign port_resp_ack[i] = ins_resp_ack[i];
+    else
+      assign ext_resp_ack     = ins_resp_ack[i];
+
+    always @(posedge clk) begin
+      if (reset) begin
+        cfg_tvalid[i] <= 1'b0;
+      end else begin
+        if (~cfg_tvalid[i]) begin
+          if (ins_req_wr[i]) begin
+            cfg_tvalid[i] <= 1'b1;
+            cfg_tdata[(CFG_W*i) +: CFG_W] <= {ins_req_data[i], ins_req_addr[i]};
+          end
+        end else begin
+          cfg_tvalid[i] <= ~cfg_tready[i];
+        end
+      end
+    end
+    assign ins_resp_ack[i] = cfg_tvalid[i] & cfg_tready[i];
+  end endgenerate
+
+  // Multiplexer between XB ports and external cfg
+
+  axi_mux #(
+    .WIDTH(CFG_W), .SIZE(CFG_PORTS),
+    .PRE_FIFO_SIZE(0), .POST_FIFO_SIZE(1)
+  ) rtcfg_mux_i (
+    .clk(clk), .reset(reset), .clear(1'b0),
+    .i_tdata(cfg_tdata), .i_tlast({(NPORTS_W + 16){1'b1}}),
+    .i_tvalid(cfg_tvalid), .i_tready(cfg_tready),
+    .o_tdata({insert_tdata, insert_tdest}), .o_tlast(),
+    .o_tvalid(insert_tvalid), .o_tready(insert_tready)
+  );
+
+endmodule
+
diff --git a/fpga/usrp3/lib/rfnoc/crossbar/crossbar_tb/Makefile b/fpga/usrp3/lib/rfnoc/crossbar/crossbar_tb/Makefile
new file mode 100644
index 000000000..7fa7ae03b
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/crossbar/crossbar_tb/Makefile
@@ -0,0 +1,52 @@
+#
+# Copyright 2015 Ettus Research LLC
+#
+
+#-------------------------------------------------
+# Top-of-Makefile
+#-------------------------------------------------
+# Define BASE_DIR to point to the "top" dir
+BASE_DIR = $(abspath ../../../../top)
+# Include viv_sim_preamble after defining BASE_DIR
+include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
+
+#-------------------------------------------------
+# Design Specific
+#-------------------------------------------------
+# Define part using PART_ID (<device>/<package>/<speedgrade>)
+ARCH = kintex7
+PART_ID = xc7k410t/ffg900/-2
+
+# Include makefiles and sources for the DUT and its dependencies
+include $(BASE_DIR)/../lib/control/Makefile.srcs
+include $(BASE_DIR)/../lib/fifo/Makefile.srcs
+include $(BASE_DIR)/../lib/rfnoc/crossbar/Makefile.srcs
+include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs
+
+DESIGN_SRCS = $(abspath \
+$(FIFO_SRCS) \
+$(CONTROL_LIB_SRCS) \
+$(RFNOC_XBAR_SRCS) \
+$(RFNOC_CORE_SRCS) \
+)
+
+#-------------------------------------------------
+# Testbench Specific
+#-------------------------------------------------
+# Define only one toplevel module
+TB_TOP_MODULE ?= crossbar_tb
+SIM_TOP = $(TB_TOP_MODULE)
+
+SIM_SRCS = \
+$(abspath chdr_traffic_source_sim.sv) \
+$(abspath chdr_traffic_sink_sim.sv) \
+$(abspath crossbar_tb.sv) \
+$(abspath $(TB_TOP_MODULE).sv)
+
+#-------------------------------------------------
+# Bottom-of-Makefile
+#-------------------------------------------------
+# Include all simulator specific makefiles here
+# Each should define a unique target to simulate
+# e.g. xsim, vsim, etc and a common "clean" target
+include $(BASE_DIR)/../tools/make/viv_simulator.mak
diff --git a/fpga/usrp3/lib/rfnoc/crossbar/crossbar_tb/axis_ctrl_crossbar_nxn_tb/Makefile b/fpga/usrp3/lib/rfnoc/crossbar/crossbar_tb/axis_ctrl_crossbar_nxn_tb/Makefile
new file mode 100644
index 000000000..0f1a10a6e
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/crossbar/crossbar_tb/axis_ctrl_crossbar_nxn_tb/Makefile
@@ -0,0 +1,51 @@
+#
+# Copyright 2015 Ettus Research LLC
+#
+
+#-------------------------------------------------
+# Top-of-Makefile
+#-------------------------------------------------
+# Define BASE_DIR to point to the "top" dir
+BASE_DIR = $(abspath ../../../../../top)
+# Include viv_sim_preamble after defining BASE_DIR
+include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
+
+#-------------------------------------------------
+# Design Specific
+#-------------------------------------------------
+# Define part using PART_ID (<device>/<package>/<speedgrade>)
+ARCH = kintex7
+PART_ID = xc7k410t/ffg900/-2
+
+# Include makefiles and sources for the DUT and its dependencies
+include $(BASE_DIR)/../lib/control/Makefile.srcs
+include $(BASE_DIR)/../lib/fifo/Makefile.srcs
+include $(BASE_DIR)/../lib/rfnoc/crossbar/Makefile.srcs
+include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs
+
+DESIGN_SRCS = $(abspath \
+$(FIFO_SRCS) \
+$(CONTROL_LIB_SRCS) \
+$(RFNOC_XBAR_SRCS) \
+$(RFNOC_CORE_SRCS) \
+)
+
+#-------------------------------------------------
+# Testbench Specific
+#-------------------------------------------------
+# Define only one toplevel module
+SIM_TOP = axis_ctrl_crossbar_nxn_tb
+
+SIM_SRCS = \
+$(abspath axis_ctrl_crossbar_nxn_tb.sv) \
+$(abspath ../crossbar_tb.sv) \
+$(abspath ../chdr_traffic_source_sim.sv) \
+$(abspath ../chdr_traffic_sink_sim.sv)
+
+#-------------------------------------------------
+# Bottom-of-Makefile
+#-------------------------------------------------
+# Include all simulator specific makefiles here
+# Each should define a unique target to simulate
+# e.g. xsim, vsim, etc and a common "clean" target
+include $(BASE_DIR)/../tools/make/viv_simulator.mak
diff --git a/fpga/usrp3/lib/rfnoc/crossbar/crossbar_tb/axis_ctrl_crossbar_nxn_tb/axis_ctrl_crossbar_nxn_tb.sv b/fpga/usrp3/lib/rfnoc/crossbar/crossbar_tb/axis_ctrl_crossbar_nxn_tb/axis_ctrl_crossbar_nxn_tb.sv
new file mode 100644
index 000000000..fa112f5cb
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/crossbar/crossbar_tb/axis_ctrl_crossbar_nxn_tb/axis_ctrl_crossbar_nxn_tb.sv
@@ -0,0 +1,26 @@
+//
+// Copyright 2018 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+
+
+`timescale 1ns/1ps
+
+module axis_ctrl_crossbar_nxn_tb();
+  crossbar_tb #(
+    .TEST_NAME          ("axis_ctrl_crossbar_nxn_tb"),
+    .ROUTER_IMPL        ("axis_ctrl_2d_torus"       ), // Router implementation
+    .ROUTER_PORTS       (20                         ), // Number of ports
+    .ROUTER_DWIDTH      (64                         ), // Router datapath width
+    .MTU_LOG2           (5                          ), // log2 of max packet size for router
+    .NUM_MASTERS        (4                          ), // Number of data generators in test
+    .TEST_MAX_PACKETS   (100                        ), // How many packets to stream per test case?
+    .TEST_LPP           (20                         ), // Lines per packet
+    .TEST_MIN_INJ_RATE  (10                         ), // Minimum injection rate to test
+    .TEST_MAX_INJ_RATE  (40                         ), // Maximum injection rate to test
+    .TEST_INJ_RATE_INCR (10                         ), // Injection rate increment
+    .TEST_GEN_LL_FILES  (0                          )  // Generate files to produce load-latency graphs?
+  ) impl (
+    /* no IO */
+  );
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/crossbar/crossbar_tb/chdr_crossbar_nxn_tb/Makefile b/fpga/usrp3/lib/rfnoc/crossbar/crossbar_tb/chdr_crossbar_nxn_tb/Makefile
new file mode 100644
index 000000000..399515640
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/crossbar/crossbar_tb/chdr_crossbar_nxn_tb/Makefile
@@ -0,0 +1,51 @@
+#
+# Copyright 2015 Ettus Research LLC
+#
+
+#-------------------------------------------------
+# Top-of-Makefile
+#-------------------------------------------------
+# Define BASE_DIR to point to the "top" dir
+BASE_DIR = $(abspath ../../../../../top)
+# Include viv_sim_preamble after defining BASE_DIR
+include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
+
+#-------------------------------------------------
+# Design Specific
+#-------------------------------------------------
+# Define part using PART_ID (<device>/<package>/<speedgrade>)
+ARCH = kintex7
+PART_ID = xc7k410t/ffg900/-2
+
+# Include makefiles and sources for the DUT and its dependencies
+include $(BASE_DIR)/../lib/control/Makefile.srcs
+include $(BASE_DIR)/../lib/fifo/Makefile.srcs
+include $(BASE_DIR)/../lib/rfnoc/crossbar/Makefile.srcs
+include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs
+
+DESIGN_SRCS = $(abspath \
+$(FIFO_SRCS) \
+$(CONTROL_LIB_SRCS) \
+$(RFNOC_XBAR_SRCS) \
+$(RFNOC_CORE_SRCS) \
+)
+
+#-------------------------------------------------
+# Testbench Specific
+#-------------------------------------------------
+# Define only one toplevel module
+SIM_TOP = chdr_crossbar_nxn_tb
+
+SIM_SRCS = \
+$(abspath chdr_crossbar_nxn_tb.sv) \
+$(abspath ../crossbar_tb.sv) \
+$(abspath ../chdr_traffic_source_sim.sv) \
+$(abspath ../chdr_traffic_sink_sim.sv)
+
+#-------------------------------------------------
+# Bottom-of-Makefile
+#-------------------------------------------------
+# Include all simulator specific makefiles here
+# Each should define a unique target to simulate
+# e.g. xsim, vsim, etc and a common "clean" target
+include $(BASE_DIR)/../tools/make/viv_simulator.mak
diff --git a/fpga/usrp3/lib/rfnoc/crossbar/crossbar_tb/chdr_crossbar_nxn_tb/chdr_crossbar_nxn_tb.sv b/fpga/usrp3/lib/rfnoc/crossbar/crossbar_tb/chdr_crossbar_nxn_tb/chdr_crossbar_nxn_tb.sv
new file mode 100644
index 000000000..1c5cace63
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/crossbar/crossbar_tb/chdr_crossbar_nxn_tb/chdr_crossbar_nxn_tb.sv
@@ -0,0 +1,26 @@
+//
+// Copyright 2018 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+
+
+`timescale 1ns/1ps
+
+module chdr_crossbar_nxn_tb();
+  crossbar_tb #(
+    .TEST_NAME          ("chdr_crossbar_nxn_tb"),
+    .ROUTER_IMPL        ("chdr_crossbar_nxn"   ), // Router implementation
+    .ROUTER_PORTS       (10                    ), // Number of ports
+    .ROUTER_DWIDTH      (64                    ), // Router datapath width
+    .MTU_LOG2           (7                     ), // log2 of max packet size for router
+    .NUM_MASTERS        (10                    ), // Number of data generators in test
+    .TEST_MAX_PACKETS   (100                   ), // How many packets to stream per test case?
+    .TEST_LPP           (100                   ), // Lines per packet
+    .TEST_MIN_INJ_RATE  (60                    ), // Minimum injection rate to test
+    .TEST_MAX_INJ_RATE  (100                   ), // Maximum injection rate to test
+    .TEST_INJ_RATE_INCR (10                    ), // Injection rate increment
+    .TEST_GEN_LL_FILES  (0                     )  // Generate files to produce load-latency graphs?
+  ) impl (
+    /* no IO */
+  );
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/crossbar/crossbar_tb/chdr_traffic_sink_sim.sv b/fpga/usrp3/lib/rfnoc/crossbar/crossbar_tb/chdr_traffic_sink_sim.sv
new file mode 100644
index 000000000..a9fe3ba27
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/crossbar/crossbar_tb/chdr_traffic_sink_sim.sv
@@ -0,0 +1,150 @@
+//
+// Copyright 2018 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: chdr_traffic_sink_sim
+// Description:
+//   A sink for CHDR traffic. Simulation only.
+//   Accepts packets and computes the following metrics:
+//   - Data integrity errors
+//   - Packet latency
+//   - Throughput counts
+//   All metrics can optionally be written to a file to
+//   generate load-latency graphs.
+
+`timescale 1ns/1ps
+
+`include "sim_cvita_lib.svh"
+
+module chdr_traffic_sink_sim #(
+  parameter        WIDTH     = 64,
+  parameter        MTU       = 5,
+  parameter [15:0] NODE_ID   = 'd0,
+  parameter [15:0] NUM_NODES = 'd16,
+  parameter        FILE_PATH = ".",
+  parameter        FLUSH_N   = 4
+) (
+  // Clocks and resets
+  input             clk,
+  input             rst,
+  // Settings       
+  input [63:0]      current_time,
+  input             start_stb,
+  input [7:0]       injection_rate,
+  input [15:0]      lines_per_pkt,
+  input [7:0]       traffic_patt,
+  // CHDR master interface
+  input [WIDTH-1:0] s_axis_tdata,
+  input             s_axis_tlast,
+  input             s_axis_tvalid,
+  output            s_axis_tready,
+  // Metrics        
+  output            session_active,
+  output [31:0]     xfer_count,
+  output [31:0]     pkt_count,
+  output [31:0]     data_err_count,
+  output [31:0]     route_err_count
+);
+
+  // Constants
+  localparam integer ERR_BIT_PKT_SIZE_MISMATCH = 1;
+  localparam integer ERR_BIT_PKT_DATA_MISMATCH = 2;
+  localparam integer ERR_BIT_PKT_DEST_MISMATCH = 4;
+  localparam integer ERR_BIT_PKT_SEQUENCE_ERR  = 8;
+
+  cvita_slave  #(.DWIDTH(WIDTH)) s_chdr (.clk(clk));
+  cvita_pkt_t  pkt;
+
+  assign s_chdr.axis.tdata = s_axis_tdata;
+  assign s_chdr.axis.tlast = s_axis_tlast;
+  assign s_chdr.axis.tvalid = s_axis_tvalid;
+  assign s_axis_tready = s_chdr.axis.tready;
+
+  logic         running = 0;
+  integer       num_data_errs = 0;
+  integer       num_route_errs = 0;
+  logic [31:0]  num_pkts_xferd = 0;
+  logic [31:0]  num_samps_xferd = 0;
+
+  assign data_err_count = num_data_errs;
+  assign route_err_count = num_route_errs;
+  assign xfer_count = num_samps_xferd;
+  assign pkt_count = num_pkts_xferd;
+  assign session_active = running;
+
+  integer session = 0;
+  string filename;
+  integer handle = 0;
+  integer err = 0;
+  integer bus_idle_cnt = 0;
+  logic [WIDTH-1:0] i;
+
+  // Egress buff in source is MTU + 4
+  localparam integer IDLE_TIMEOUT = (1 << (MTU + 4 + FLUSH_N));
+
+  initial begin: consume_blk
+    // Consume infinitely
+    s_chdr.reset();
+    while (1) begin
+      // A session begins on the posedge of start_stb
+      while (~start_stb) @(posedge clk);
+      session = session + 1;
+      $sformat(filename, "%s/pkts_node%05d_inj%03d_lpp%05d_traffic%c_sess%04d.csv",
+        FILE_PATH, NODE_ID, injection_rate, lines_per_pkt, traffic_patt, session);
+      if (FILE_PATH != "") begin
+        handle = $fopen(filename, "w");
+        if (handle == 0) begin
+          $error("Could not open file: %s", filename);
+          $finish();
+        end
+      end
+      if (handle != 0) $fdisplay(handle, "Src,Dst,Seqno,Error,Latency");
+      s_chdr.reset();
+      num_data_errs = 0;
+      num_route_errs = 0;
+      num_pkts_xferd = 0;
+      num_samps_xferd = 0;
+      bus_idle_cnt = 0;
+      running = 1;
+      while (1) begin
+        // Pull packet from bus
+        err = 0;
+        if (~s_chdr.axis.tvalid[0]) begin
+          @(posedge clk);
+          bus_idle_cnt = bus_idle_cnt + 1;
+          if (bus_idle_cnt <= IDLE_TIMEOUT)
+            continue;
+          else
+            break;
+        end
+        s_chdr.pull_pkt(pkt, 0);
+        bus_idle_cnt = 0;
+        num_pkts_xferd = num_pkts_xferd + 1;
+        num_samps_xferd = num_samps_xferd + lines_per_pkt;
+        // Validate packet
+        if (pkt.hdr.dst_sid != NODE_ID) begin
+          err = err + ERR_BIT_PKT_DEST_MISMATCH;
+          num_route_errs = num_route_errs + 1;
+        end
+        if (pkt.payload.size() != lines_per_pkt-2) begin
+          err = err + ERR_BIT_PKT_SIZE_MISMATCH;
+          num_data_errs = num_data_errs + 1;
+        end else begin
+          for (i = 'd0; i < (lines_per_pkt-2); i=i+1) begin
+            if (pkt.payload[i] != i) begin
+              err = err + ERR_BIT_PKT_DATA_MISMATCH;
+              num_data_errs = num_data_errs + 1;
+              break;
+            end
+          end
+        end
+        if (handle != 0) $fdisplay(handle, "%00d,%00d,%00d,%00d,%00d",
+          pkt.hdr.src_sid, pkt.hdr.dst_sid, pkt.hdr.seqnum, err, (current_time - pkt.hdr.timestamp));
+      end
+      running = 0;
+      if (handle != 0) $fclose(handle);
+    end
+  end
+
+endmodule
\ No newline at end of file
diff --git a/fpga/usrp3/lib/rfnoc/crossbar/crossbar_tb/chdr_traffic_source_sim.sv b/fpga/usrp3/lib/rfnoc/crossbar/crossbar_tb/chdr_traffic_source_sim.sv
new file mode 100644
index 000000000..8c3d974c9
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/crossbar/crossbar_tb/chdr_traffic_source_sim.sv
@@ -0,0 +1,202 @@
+//
+// Copyright 2018 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: chdr_traffic_source_sim
+// Description:
+//   A traffic generator for CHDR traffic. Simulation only.
+//   Supports multiple traffic pattern and injection rates.
+//
+
+`timescale 1ns/1ps
+
+`include "sim_cvita_lib.svh"
+
+module chdr_traffic_source_sim #(
+  parameter        WIDTH        = 64,   // Width of the AXI-Stream data bus
+  parameter        MTU          = 5,    // log2 of the max number of lines in a packet
+  parameter [15:0] NODE_ID      = 'd0,  // Node ID for this generator
+  parameter [15:0] NUM_NODES    = 'd16  // Total number of generators in the application
+) (
+  // Clocks and resets
+  input               clk,              // AXI-Stream clock
+  input               rst,              // AXI-Stream reset
+  // Settings         
+  input [63:0]        current_time,     // The current value of the global timebase (synch to clk)
+  input               start_stb,        // A strobe that indicates the start of a generation session
+  input [7:0]         injection_rate,   // The inject rate (in percent) to simulate
+  input [15:0]        lines_per_pkt,    // Number of lines per packet to generate
+  input [7:0]         traffic_patt,     // The traffic pattern (see localparams below for values)
+  input [31:0]        num_pkts_to_send, // Number of packets to send
+  // CHDR master interface
+  output [WIDTH-1:0]  m_axis_tdata,     // AXI-Stream master tdata
+  output              m_axis_tlast,     // AXI-Stream master tlast
+  output              m_axis_tvalid,    // AXI-Stream master tvalid
+  input               m_axis_tready,    // AXI-Stream master tready
+  // Metrics          
+  output              session_active,   // Signal indicating if generation session is active
+  output [63:0]       session_duration, // Session duration (only valid after session ends)
+  output [31:0]       xfer_count,       // Number of lines transferred (only valid after session ends)
+  output [31:0]       pkt_count         // Number of packets transferred (only valid after session ends)
+);
+  // **** Supported Traffic Patters ****
+  localparam [7:0] TRAFFIC_PATT_LOOPBACK       = 8'd76;  //L
+  localparam [7:0] TRAFFIC_PATT_NEIGHBOR       = 8'd78;  //N
+  localparam [7:0] TRAFFIC_PATT_BIT_COMPLEMENT = 8'd67;  //C
+  localparam [7:0] TRAFFIC_PATT_SEQUENTIAL     = 8'd83;  //S
+  localparam [7:0] TRAFFIC_PATT_UNIFORM        = 8'd85;  //U
+  localparam [7:0] TRAFFIC_PATT_UNIFORM_OTHERS = 8'd79;  //O
+  localparam [7:0] TRAFFIC_PATT_RANDOM_PERM    = 8'd82;  //R
+
+  cvita_master  #(.DWIDTH(WIDTH)) m_chdr (.clk(clk));
+  axis_t        #(.DWIDTH(WIDTH)) post_fifo (.clk(clk));
+  axis_t        #(.DWIDTH(WIDTH)) pre_gate (.clk(clk));
+  cvita_hdr_t  header;
+  reg throttle = 1'b1;
+
+  logic        running = 0;
+  logic [31:0] curr_pkt_num = 'd0;
+  logic [31:0] num_samps_xferd = 'd0;
+  logic [63:0] start_time = 0;
+  logic [63:0] stop_time = 0;
+  logic [15:0] last_gen_sid = (NODE_ID - 16'd1);
+
+  assign xfer_count = num_samps_xferd;
+  assign pkt_count = curr_pkt_num;
+  assign session_duration = (stop_time - start_time);
+  assign session_active = running;
+
+  // Utility function to assign SIDs based on traffic pattern
+  function [15:0] gen_dst_sid;
+    input [7:0] traffic_patt;
+    input [15:0] last_sid;
+
+    if (traffic_patt == TRAFFIC_PATT_UNIFORM) begin
+      gen_dst_sid = $urandom_range('d0, NUM_NODES-'d1);
+    end else if (traffic_patt == TRAFFIC_PATT_UNIFORM_OTHERS) begin
+      logic [31:0] rnum = $urandom_range('d0, NUM_NODES-'d2);
+      if (rnum < NODE_ID)
+        gen_dst_sid = rnum[15:0];
+      else
+        gen_dst_sid = rnum[15:0] + 16'd1;
+    end else if (traffic_patt == TRAFFIC_PATT_SEQUENTIAL) begin
+      gen_dst_sid = (last_sid + 16'd1) % NUM_NODES;
+    end else if (traffic_patt == TRAFFIC_PATT_NEIGHBOR) begin
+      gen_dst_sid = (NODE_ID + 16'd1) % NUM_NODES;
+    end else if (traffic_patt == TRAFFIC_PATT_LOOPBACK) begin
+      gen_dst_sid = NODE_ID;
+    end else if (traffic_patt == TRAFFIC_PATT_BIT_COMPLEMENT) begin
+      gen_dst_sid = (NUM_NODES - NODE_ID - 1) % NUM_NODES;
+    end else if (traffic_patt == TRAFFIC_PATT_RANDOM_PERM) begin
+      //TODO: Implement me
+      gen_dst_sid = 0;
+    end else begin
+      gen_dst_sid = 'd0;
+    end
+  endfunction
+
+  // Generation loop. Push to m_chdr infinitely fast
+  initial begin: gen_blk
+    // Generate infinitely
+    $srandom(NODE_ID + NUM_NODES);
+    m_chdr.reset();
+    while (1) begin
+      // A generation session begins on the posedge of start_stb
+      while (~start_stb) @(posedge clk);
+      curr_pkt_num = 'd0;
+      m_chdr.reset();
+      num_samps_xferd = 'd0;
+      start_time = current_time;
+      running = 1;
+      while (curr_pkt_num < num_pkts_to_send) begin
+        header = '{
+          pkt_type:DATA, has_time:1, eob:0,
+          seqnum:curr_pkt_num[11:0], length:(lines_per_pkt*8),
+          src_sid:NODE_ID, dst_sid:gen_dst_sid(traffic_patt, last_gen_sid),
+          timestamp:0 //TS attached later
+        };
+        last_gen_sid = header.dst_sid;
+        curr_pkt_num = curr_pkt_num + 'd1;
+        m_chdr.push_ramp_pkt(lines_per_pkt-2, 'h0, 'h1, header);
+        num_samps_xferd = num_samps_xferd + lines_per_pkt;
+      end
+      running = 0;
+      stop_time = current_time;
+    end
+  end
+
+  // Capture packets in a really short FIFO (for backpressure)
+  axi_fifo #(
+    .WIDTH(WIDTH+1), .SIZE(MTU + 1)
+  ) fifo_i (
+    .clk      (clk), 
+    .reset    (rst), 
+    .clear    (1'b0),
+    .i_tdata  ({m_chdr.axis.tlast, m_chdr.axis.tdata}),
+    .i_tvalid (m_chdr.axis.tvalid),
+    .i_tready (m_chdr.axis.tready),
+    .o_tdata  ({post_fifo.tlast, post_fifo.tdata}),
+    .o_tvalid (post_fifo.tvalid),
+    .o_tready (post_fifo.tready),
+    .space    (),
+    .occupied ()
+  );
+
+  // Attach timestamp after the packet leaves the FIFO after
+  // throttling. 
+
+  localparam [1:0] ST_HDR   = 2'd0;
+  localparam [1:0] ST_TS    = 2'd1;
+  localparam [1:0] ST_BODY  = 2'd2;
+
+  reg [1:0] pkt_state = ST_HDR;
+  always_ff @(posedge clk) begin
+    if (rst) begin
+      pkt_state <= ST_HDR;
+    end else if (pre_gate.tvalid & pre_gate.tready) begin
+      case (pkt_state)
+        ST_HDR:
+          if (~pre_gate.tlast)
+            pkt_state <= pre_gate.tdata[61] ? ST_TS : ST_BODY;
+        ST_TS:
+          pkt_state <= pre_gate.tlast ? ST_HDR : ST_BODY;
+        ST_BODY:
+          pkt_state <= pre_gate.tlast ? ST_HDR : ST_BODY;
+        default:
+          pkt_state <= ST_HDR;
+      endcase
+    end
+  end
+
+  // Enforce injection rate by pulling from FIFO with a certain time probability
+  always_ff @(posedge clk) begin
+    throttle <= ($urandom_range(32'd99, 32'd0) > {24'h0, injection_rate});
+  end
+
+  // Insert timestamp + throttle logic
+  assign pre_gate.tdata   = (pkt_state == ST_TS) ? current_time : post_fifo.tdata;
+  assign pre_gate.tlast   = post_fifo.tlast;
+  assign pre_gate.tvalid  = post_fifo.tvalid & ~throttle;
+  assign post_fifo.tready = pre_gate.tready & ~throttle;
+
+  // Gate the packet to smooth out throttle-related noise.
+  // This also serves as a buffer for the packet in case things are backed up
+  axi_packet_gate #(
+    .WIDTH(WIDTH), .SIZE(MTU + 4), .USE_AS_BUFF(1)
+  ) pkt_gate_i (
+    .clk      (clk), 
+    .reset    (rst), 
+    .clear    (1'b0),
+    .i_tdata  (pre_gate.tdata),
+    .i_tlast  (pre_gate.tlast),
+    .i_terror (1'b0),
+    .i_tvalid (pre_gate.tvalid),
+    .i_tready (pre_gate.tready),
+    .o_tdata  (m_axis_tdata),
+    .o_tlast  (m_axis_tlast),
+    .o_tvalid (m_axis_tvalid),
+    .o_tready (m_axis_tready)
+  );
+
+endmodule
\ No newline at end of file
diff --git a/fpga/usrp3/lib/rfnoc/crossbar/crossbar_tb/crossbar_tb.sv b/fpga/usrp3/lib/rfnoc/crossbar/crossbar_tb/crossbar_tb.sv
new file mode 100644
index 000000000..fc9d53fe7
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/crossbar/crossbar_tb/crossbar_tb.sv
@@ -0,0 +1,428 @@
+//
+// Copyright 2018 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+
+
+`timescale 1ns/1ps
+`define NS_PER_TICK 1
+`define NUM_TEST_CASES 7
+
+`include "sim_clks_rsts.vh"
+`include "sim_exec_report.vh"
+`include "sim_set_rb_lib.svh"
+`include "sim_axis_lib.svh"
+
+`define SIM_TIMEOUT_US 1000000 // Default: 1s
+
+module crossbar_tb #(
+  parameter TEST_NAME          = "crossbar_tb",
+  // Router parameters
+  parameter ROUTER_IMPL        = "axi_crossbar", // Router implementation
+  parameter ROUTER_PORTS       = 10,             // # Router ports
+  parameter ROUTER_DWIDTH      = 64,             // Router datapath width
+  parameter MTU_LOG2           = 7,              // log2 of max packet size for router
+  parameter NUM_MASTERS        = ROUTER_PORTS,   // Number of data generators in test
+  // Test parameters
+  parameter TEST_MAX_PACKETS   = 50,             // How many packets to stream per test case?
+  parameter TEST_LPP           = 50,             // Lines per packet
+  parameter TEST_MIN_INJ_RATE  = 60,             // Minimum injection rate to test
+  parameter TEST_MAX_INJ_RATE  = 100,            // Maximum injection rate to test
+  parameter TEST_INJ_RATE_INCR = 10,             // Injection rate increment
+  parameter TEST_GEN_LL_FILES  = 0               // Generate files to produce load-latency graphs?
+
+)(
+  /* no IO */
+);
+  `TEST_BENCH_INIT(TEST_NAME,`NUM_TEST_CASES,`NS_PER_TICK)
+
+  //----------------------------------------------------
+  // General test setup
+  //----------------------------------------------------
+
+  // Clocks and reset
+  `DEFINE_CLK(clk, 5.000, 50)
+  `DEFINE_RESET(rst, 0, 10)
+
+  // Timekeeper (cycle counter)
+  logic [63:0] timestamp;
+  initial begin : timekeeper_blk
+    while (rst) @(posedge clk);
+    timestamp = 'd0;
+    while (~rst) begin
+      @(posedge clk);
+      timestamp = timestamp + 'd1;
+    end
+  end
+
+  //----------------------------------------------------
+  // Instantiate traffic generators, checkers, buses
+  //----------------------------------------------------
+  localparam FILE_PATH = {`WORKING_DIR, "/data/", ROUTER_IMPL};
+
+  // Data buses
+  axis_t #(.DWIDTH(ROUTER_DWIDTH), .NUM_STREAMS(ROUTER_PORTS)) src2rtr_axis (.clk(clk));
+  axis_t #(.DWIDTH(ROUTER_DWIDTH), .NUM_STREAMS(ROUTER_PORTS)) rtr2snk_axis (.clk(clk));
+  
+  // Control buses
+  settings_bus_master #(.SR_AWIDTH(16), .SR_DWIDTH(32)) rtr_sb (.clk(clk));
+  wire rtr_sb_ack;
+
+  // Test vector source and sink instantiation
+  logic [7:0]   set_injection_rate;
+  logic [15:0]  set_lines_per_pkt;
+  logic [7:0]   set_traffic_patt;
+  logic [31:0]  set_num_pkts_to_send;
+  logic         snk_start_stb = 0;
+  logic         src_start_stb = 0;
+
+  wire [63:0]             session_duration   [0:ROUTER_PORTS-1];
+  wire [ROUTER_PORTS-1:0] src_active;
+  wire [31:0]             src_xfer_count     [0:ROUTER_PORTS-1];
+  wire [31:0]             src_pkt_count      [0:ROUTER_PORTS-1];
+  wire [ROUTER_PORTS-1:0] snk_active;
+  wire [31:0]             snk_xfer_count     [0:ROUTER_PORTS-1];
+  wire [31:0]             snk_pkt_count      [0:ROUTER_PORTS-1];
+  wire [31:0]             snk_data_err_count [0:ROUTER_PORTS-1];
+  wire [31:0]             snk_route_err_count[0:ROUTER_PORTS-1];
+
+  wire  deadlock_detected;
+  reg   deadlock_detected_del = 1'b0;
+  always @(posedge clk) deadlock_detected_del <= deadlock_detected;
+  wire  deadlock_re = (deadlock_detected & ~deadlock_detected_del);
+  wire  deadlock_fe = (~deadlock_detected & deadlock_detected_del);
+
+  genvar i;
+  generate for (i = 0; i < ROUTER_PORTS; i=i+1) begin: src_snk_blk
+    chdr_traffic_source_sim #(
+      .WIDTH            (ROUTER_DWIDTH),
+      .MTU              (MTU_LOG2),
+      .NODE_ID          (i),
+      .NUM_NODES        (ROUTER_PORTS)
+    ) traffic_src (     
+      .clk              (clk),
+      .rst              (rst),
+      .current_time     (timestamp),
+      .start_stb        (src_start_stb & (i < NUM_MASTERS)),
+      .injection_rate   (set_injection_rate),
+      .lines_per_pkt    (set_lines_per_pkt),
+      .traffic_patt     (set_traffic_patt),
+      .num_pkts_to_send (set_num_pkts_to_send),
+      .m_axis_tdata     (src2rtr_axis.tdata[((i+1)*ROUTER_DWIDTH)-1:i*ROUTER_DWIDTH]),
+      .m_axis_tlast     (src2rtr_axis.tlast[i]),
+      .m_axis_tvalid    (src2rtr_axis.tvalid[i]),
+      .m_axis_tready    (src2rtr_axis.tready[i]),
+      .session_active   (src_active[i]),
+      .session_duration (session_duration[i]),
+      .xfer_count       (src_xfer_count[i]),
+      .pkt_count        (src_pkt_count[i])
+    );
+  
+    chdr_traffic_sink_sim #(
+      .WIDTH            (ROUTER_DWIDTH),
+      .MTU              (MTU_LOG2),
+      .NODE_ID          (i),
+      .NUM_NODES        (ROUTER_PORTS),
+      .FILE_PATH        (TEST_GEN_LL_FILES==1 ? FILE_PATH : "")
+    ) traffic_sink (    
+      .clk              (clk),
+      .rst              (rst),
+      .current_time     (timestamp),
+      .start_stb        (snk_start_stb),
+      .injection_rate   (set_injection_rate),
+      .lines_per_pkt    (set_lines_per_pkt),
+      .traffic_patt     (set_traffic_patt),
+      .s_axis_tdata     (rtr2snk_axis.tdata[((i+1)*ROUTER_DWIDTH)-1:i*ROUTER_DWIDTH]),
+      .s_axis_tlast     (rtr2snk_axis.tlast[i]),
+      .s_axis_tvalid    (rtr2snk_axis.tvalid[i]),
+      .s_axis_tready    (rtr2snk_axis.tready[i]),
+      .session_active   (snk_active[i]),
+      .xfer_count       (snk_xfer_count[i]),
+      .pkt_count        (snk_pkt_count[i]),
+      .data_err_count   (snk_data_err_count[i]),
+      .route_err_count  (snk_route_err_count[i])
+    );
+  end endgenerate
+
+  //----------------------------------------------------
+  // Instantiate DUT
+  //----------------------------------------------------
+  generate if (ROUTER_IMPL == "FIFO") begin
+    for (i = 0; i < ROUTER_PORTS; i=i+1) begin
+      axi_fifo #(
+        .WIDTH(ROUTER_DWIDTH+1), .SIZE(0)
+      ) fifo_i (
+        .clk      (clk), 
+        .reset    (rst), 
+        .clear    (1'b0),
+        .i_tdata  ({src2rtr_axis.tlast[i], src2rtr_axis.tdata[((i+1)*ROUTER_DWIDTH)-1:i*ROUTER_DWIDTH]}),
+        .i_tvalid (src2rtr_axis.tvalid[i]),
+        .i_tready (src2rtr_axis.tready[i]),
+        .o_tdata  ({rtr2snk_axis.tlast[i], rtr2snk_axis.tdata[((i+1)*ROUTER_DWIDTH)-1:i*ROUTER_DWIDTH]}),
+        .o_tvalid (rtr2snk_axis.tvalid[i]),
+        .o_tready (rtr2snk_axis.tready[i]),
+        .space    (),
+        .occupied ()
+      );
+    end
+  end else if (ROUTER_IMPL == "axi_crossbar") begin
+    axi_crossbar #(
+      .BASE         (0),
+      .FIFO_WIDTH   (ROUTER_DWIDTH),
+      .DST_WIDTH    (16),
+      .NUM_INPUTS   (ROUTER_PORTS),
+      .NUM_OUTPUTS  (ROUTER_PORTS)
+    ) router_dut_i (
+       // General
+      .clk          (clk),
+      .reset        (rst),
+      .clear        (1'b0),
+      .local_addr   (8'd0),
+      // Inputs     
+      .i_tdata      (src2rtr_axis.tdata),
+      .i_tlast      (src2rtr_axis.tlast),
+      .i_tvalid     (src2rtr_axis.tvalid),
+      .i_tready     (src2rtr_axis.tready),
+      .pkt_present  (src2rtr_axis.tvalid),
+      // Output
+      .o_tdata      (rtr2snk_axis.tdata),
+      .o_tlast      (rtr2snk_axis.tlast),
+      .o_tvalid     (rtr2snk_axis.tvalid),
+      .o_tready     (rtr2snk_axis.tready),
+      // Setting Bus
+      .set_stb      (rtr_sb.settings_bus.set_stb),
+      .set_addr     (rtr_sb.settings_bus.set_addr),
+      .set_data     (rtr_sb.settings_bus.set_data),
+      // Readback bus
+      .rb_rd_stb    (1'b0),
+      .rb_addr      ({(2*$clog2(ROUTER_PORTS)){1'b0}}),
+      .rb_data      ()
+    );
+  end else if (ROUTER_IMPL == "chdr_crossbar_nxn") begin
+    chdr_crossbar_nxn #(
+      .CHDR_W         (ROUTER_DWIDTH),
+      .NPORTS         (ROUTER_PORTS),
+      .DEFAULT_PORT   (0),
+      .MTU            (MTU_LOG2),
+      .ROUTE_TBL_SIZE (6),
+      .MUX_ALLOC      ("ROUND-ROBIN"),
+      .OPTIMIZE       ("AREA"),
+      .NPORTS_MGMT    (0),
+      .EXT_RTCFG_PORT (1)
+    ) router_dut_i (
+       // General         
+      .clk            (clk),
+      .reset          (rst),
+      // Inputs
+      .s_axis_tdata   (src2rtr_axis.tdata),
+      .s_axis_tlast   (src2rtr_axis.tlast),
+      .s_axis_tvalid  (src2rtr_axis.tvalid),
+      .s_axis_tready  (src2rtr_axis.tready),
+      // Output
+      .m_axis_tdata   (rtr2snk_axis.tdata),
+      .m_axis_tlast   (rtr2snk_axis.tlast),
+      .m_axis_tvalid  (rtr2snk_axis.tvalid),
+      .m_axis_tready  (rtr2snk_axis.tready),
+      // External router config
+      .ext_rtcfg_stb  (rtr_sb.settings_bus.set_stb),
+      .ext_rtcfg_addr (rtr_sb.settings_bus.set_addr),
+      .ext_rtcfg_data (rtr_sb.settings_bus.set_data),
+      .ext_rtcfg_ack  (rtr_sb_ack)
+    );
+  end else begin
+    axis_ctrl_crossbar_nxn #(
+      .WIDTH            (ROUTER_DWIDTH),
+      .NPORTS           (ROUTER_PORTS),
+      .TOPOLOGY         (ROUTER_IMPL == "axis_ctrl_2d_torus" ? "TORUS" : "MESH"),
+      .INGRESS_BUFF_SIZE(MTU_LOG2),
+      .ROUTER_BUFF_SIZE (MTU_LOG2),
+      .ROUTING_ALLOC    ("WORMHOLE"),
+      .SWITCH_ALLOC     ("PRIO")
+    ) router_dut_i (
+       // General
+      .clk              (clk),
+      .reset            (rst),
+      // Inputs         
+      .s_axis_tdata     (src2rtr_axis.tdata),
+      .s_axis_tlast     (src2rtr_axis.tlast),
+      .s_axis_tvalid    (src2rtr_axis.tvalid),
+      .s_axis_tready    (src2rtr_axis.tready),
+      // Output         
+      .m_axis_tdata     (rtr2snk_axis.tdata),
+      .m_axis_tlast     (rtr2snk_axis.tlast),
+      .m_axis_tvalid    (rtr2snk_axis.tvalid),
+      .m_axis_tready    (rtr2snk_axis.tready),
+      // Deadlock detection
+      .deadlock_detected(deadlock_detected)
+    );
+  end endgenerate
+
+  //----------------------------------------------------
+  // Test routine. Runs tests and writes metrics to file
+  //----------------------------------------------------
+
+  // Constants
+  localparam [7:0] TRAFFIC_PATT_LOOPBACK       = 8'd76;  //L
+  localparam [7:0] TRAFFIC_PATT_NEIGHBOR       = 8'd78;  //N
+  localparam [7:0] TRAFFIC_PATT_BIT_COMPLEMENT = 8'd67;  //C
+  localparam [7:0] TRAFFIC_PATT_SEQUENTIAL     = 8'd83;  //S
+  localparam [7:0] TRAFFIC_PATT_UNIFORM        = 8'd85;  //U
+  localparam [7:0] TRAFFIC_PATT_UNIFORM_OTHERS = 8'd79;  //O
+  localparam [7:0] TRAFFIC_PATT_RANDOM_PERM    = 8'd82;  //R
+
+  string        filename;
+  integer       node;
+  integer       session = 0;
+  integer       handle = 0;
+  logic [63:0]  start_time;
+  integer       total_pkts_recvd = 0, total_pkts_sent = 0;
+
+  task sim_dataflow;
+    input [7:0]  injection_rate;
+    input [7:0]  traffic_patt;
+    input [15:0] lines_per_pkt;
+    input [31:0] num_pkts_to_send;
+  begin
+    session = session + 1;
+    $display("--------------- New Simulation ---------------");
+    $display("- Module = %s", ROUTER_IMPL);
+    $display("- Nodes = %00d", ROUTER_PORTS);
+    $display("- Injection Rate = %00d%%", injection_rate);
+    $display("- Traffic Pattern = %c", traffic_patt);
+    $display("- Packet Size = %00d words (%00d bits)", lines_per_pkt, ROUTER_DWIDTH);
+    $display("- Max Packets = %00d", num_pkts_to_send);
+    // Configure settings
+    @(posedge clk);
+    set_injection_rate = injection_rate;
+    set_lines_per_pkt = lines_per_pkt;
+    set_traffic_patt = traffic_patt;
+    set_num_pkts_to_send = num_pkts_to_send;
+    @(posedge clk);
+    // Start the sink then the source
+    $display("Data flow starting...");
+    snk_start_stb = 1;
+    src_start_stb = 1;
+    @(posedge clk);
+    src_start_stb = 0;
+    snk_start_stb = 0;
+    @(posedge clk);
+    start_time = timestamp;
+    // Wait for source blocks to finish generating
+    $display("Waiting for packets to transmit... (may take a while)");
+    while (|src_active) begin
+      @(posedge clk);
+      if (deadlock_re) $display("WARNING: Deadlock detected");
+      if (deadlock_fe) $display("Recovered from deadlock");
+    end 
+    // Wait for sink blocks to finish consuming
+    $display("All packets transmitted. Waiting to flush...");
+    while (|snk_active) @(posedge clk);
+    // If router deadlocks then wait for it to recover
+    if (deadlock_detected) begin
+      $display("Waiting for deadlock recovery to finish...");
+      while (deadlock_detected) @(posedge clk);
+    end
+    repeat(set_lines_per_pkt) @(posedge clk);
+    // Record summary to file and print to console
+    $sformat(filename, "%s/info_inj%03d_lpp%05d_traffic%c_sess%04d.csv",
+      FILE_PATH, injection_rate, lines_per_pkt, traffic_patt, session);
+    if (TEST_GEN_LL_FILES == 1) begin
+      handle = $fopen(filename, "w");
+      if (handle == 0) begin
+        $error("Could not open file: %s", filename);
+        $finish();
+      end
+    end
+    if (handle != 0) $fdisplay(handle, "Impl,Node,TxPkts,RxPkts,Duration,ErrRoute,ErrData");
+    total_pkts_sent = 0;
+    total_pkts_recvd = 0;
+    for (node = 0; node < ROUTER_PORTS; node=node+1) begin
+      $display("- Node #%03d: TX = %5d pkts, RX = %5d pkts, Inj Rate = %3d%%. Errs = %5d route, %5d data",
+        node,src_pkt_count[node], snk_pkt_count[node], ((src_xfer_count[node]*100)/session_duration[node]),
+        snk_route_err_count[node], snk_data_err_count[node]);
+      if (handle != 0) $fdisplay(handle, "%s,%00d,%00d,%00d,%00d,%00d,%00d", ROUTER_IMPL,
+        node,src_pkt_count[node], snk_pkt_count[node], session_duration[node],
+        snk_route_err_count[node], snk_data_err_count[node]);
+      total_pkts_sent = total_pkts_sent + src_pkt_count[node];
+      total_pkts_recvd = total_pkts_recvd + snk_pkt_count[node];
+      `ASSERT_ERROR(snk_route_err_count[node] == 0, "Routing errors. Received packets destined to other nodes");
+      `ASSERT_ERROR(snk_data_err_count[node] == 0, "Integrity errors. Received corrupted packets");
+    end
+    $display("Finished. Elapsed = %00d cycles, TX = %00d pkts, RX = %00d pkts",
+      (timestamp - start_time), total_pkts_sent, total_pkts_recvd);
+    `ASSERT_ERROR(total_pkts_recvd == total_pkts_sent, "Total # TX packets did not match the total # RX packets");
+    if (handle != 0) $fclose(handle);
+    $display("----------------------------------------------");
+  end
+  endtask
+
+  //----------------------------------------------------
+  // Main test loop
+  //----------------------------------------------------
+
+  logic [31:0] MAX_PACKETS    = TEST_MAX_PACKETS;
+  logic [15:0] LPP            = TEST_LPP;
+  integer      MIN_INJ_RATE   = TEST_MIN_INJ_RATE;
+  integer      MAX_INJ_RATE   = TEST_MAX_INJ_RATE;
+  integer      INJ_RATE_INCR  = TEST_INJ_RATE_INCR;
+
+  integer inj_rate = 0;
+  initial begin : tb_main
+    src_start_stb = 0;
+    snk_start_stb = 0;
+    rtr_sb.reset();
+    while (rst) @(posedge clk);
+
+    repeat (10) @(posedge clk);
+
+    `TEST_CASE_START("Set up crossbar");
+      for (node = 0; node < ROUTER_PORTS; node=node+1) begin
+        if (ROUTER_IMPL == "axi_crossbar") begin
+          rtr_sb.write(16'd256 + node[15:0], {16'h0, node[15:0]});
+        end else if (ROUTER_IMPL == "chdr_crossbar_nxn") begin
+          rtr_sb.write(node[15:0], {16'h0, node[15:0]});
+          while (~rtr_sb_ack) @(posedge clk);
+        end
+      end
+    `TEST_CASE_DONE(1)
+
+     `TEST_CASE_START("Simulate LOOPBACK Traffic Pattern");
+       for (inj_rate = MIN_INJ_RATE; inj_rate <= MAX_INJ_RATE; inj_rate = inj_rate + INJ_RATE_INCR) begin
+         sim_dataflow(inj_rate, TRAFFIC_PATT_LOOPBACK, LPP, MAX_PACKETS);
+       end
+     `TEST_CASE_DONE(1)
+
+     `TEST_CASE_START("Simulate SEQUENTIAL Traffic Pattern");
+       for (inj_rate = MIN_INJ_RATE; inj_rate <= MAX_INJ_RATE; inj_rate = inj_rate + INJ_RATE_INCR) begin
+         sim_dataflow(inj_rate, TRAFFIC_PATT_SEQUENTIAL, LPP, MAX_PACKETS);
+       end
+     `TEST_CASE_DONE(1)
+
+     `TEST_CASE_START("Simulate UNIFORM Traffic Pattern");
+       for (inj_rate = MIN_INJ_RATE; inj_rate <= MAX_INJ_RATE; inj_rate = inj_rate + INJ_RATE_INCR) begin
+         sim_dataflow(inj_rate, TRAFFIC_PATT_UNIFORM, LPP, MAX_PACKETS);
+       end
+     `TEST_CASE_DONE(1)
+
+     `TEST_CASE_START("Simulate UNIFORM_OTHERS Traffic Pattern");
+       for (inj_rate = MIN_INJ_RATE; inj_rate <= MAX_INJ_RATE; inj_rate = inj_rate + INJ_RATE_INCR) begin
+         sim_dataflow(inj_rate, TRAFFIC_PATT_UNIFORM_OTHERS, LPP, MAX_PACKETS);
+       end
+     `TEST_CASE_DONE(1)
+
+     `TEST_CASE_START("Simulate BIT_COMPLEMENT Traffic Pattern");
+       for (inj_rate = MIN_INJ_RATE; inj_rate <= MAX_INJ_RATE; inj_rate = inj_rate + INJ_RATE_INCR) begin
+         sim_dataflow(inj_rate, TRAFFIC_PATT_BIT_COMPLEMENT, LPP, MAX_PACKETS);
+       end
+     `TEST_CASE_DONE(1)
+
+    `TEST_CASE_START("Simulate NEIGHBOR Traffic Pattern");
+      for (inj_rate = MIN_INJ_RATE; inj_rate <= MAX_INJ_RATE; inj_rate = inj_rate + INJ_RATE_INCR) begin
+        sim_dataflow(inj_rate, TRAFFIC_PATT_NEIGHBOR, LPP, MAX_PACKETS);
+      end
+    `TEST_CASE_DONE(1)
+
+    `TEST_BENCH_DONE
+  end // initial begin
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/crossbar/crossbar_tb/gen_load_latency_graph.py b/fpga/usrp3/lib/rfnoc/crossbar/crossbar_tb/gen_load_latency_graph.py
new file mode 100755
index 000000000..35821c2c4
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/crossbar/crossbar_tb/gen_load_latency_graph.py
@@ -0,0 +1,169 @@
+#!/usr/bin/env python3
+#
+# Copyright 2018 Ettus Research, A National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+# Description
+#   Parses the output files generated by crossbar_tb and outputs
+#   a load-latency graph and a expected-actual throughput graph
+
+import os, sys
+import argparse
+import time
+import glob
+import csv
+import re
+import numpy as np
+
+import matplotlib
+#matplotlib.use('Agg')
+import matplotlib.pyplot as plt
+
+def get_options():
+    parser = argparse.ArgumentParser(description='Generate Load Latency Graphs')
+    parser.add_argument('datadir', type=str, default='.', help='Location of packet capture files generated by testbench')
+    return parser.parse_args()
+
+TRAFFIC_PATTERNS = {'U':'UNIFORM', 'O':'UNIFORM_OTHERS', 'N':'NEIGHBOR', 'L':'LOOPBACK', 'S':'SEQUENTIAL', 'C':'BIT_COMPLEMENT', 'R':'RANDOM_PERM'}
+
+class InfoFile():
+    def __init__(self, filename):
+        # Extract test info from filename
+        m = re.search(r".*/info_inj([0-9]+)_lpp([0-9]+)_traffic(.)_sess([0-9]+)\.csv", filename)
+        if m is None:
+            raise ValueError('Incorrect filename format: %s'%(filename))
+        self.inj_rate = int(m.group(1))
+        self.lpp = int(m.group(2))
+        self.traffic_patt = TRAFFIC_PATTERNS[m.group(3)]
+        self.session = int(m.group(4))
+
+        self.tx_pkts = 0
+        self.rx_pkts = 0
+        self.duration = 0
+        self.errs = 0
+        self.nodes = 0
+        with open(filename, 'r') as csvfile:
+            reader = csv.reader(csvfile, delimiter=',')
+            isheader = True
+            for row in reader:
+                if isheader:
+                    isheader = False
+                    if row != ['Impl', 'Node', 'TxPkts', 'RxPkts', 'Duration', 'ErrRoute', 'ErrData']:
+                        raise ValueError('Incorrect header: %s'%(filename))
+                else:
+                    self.impl = row[0]
+                    self.tx_pkts = self.tx_pkts + int(row[2])
+                    self.rx_pkts = self.tx_pkts + int(row[3])
+                    self.duration = self.duration + int(row[4])
+                    self.errs = self.errs + int(row[5]) + int(row[6])
+                    self.nodes = self.nodes + 1
+        self.real_inj_rate = (100.0 * self.tx_pkts * self.lpp) / self.duration
+
+class PktFile():
+    def __init__(self, filename):
+        # Extract test info from filename
+        m = re.search(r".*/pkts_node([0-9]+)_inj([0-9]+)_lpp([0-9]+)_traffic(.)_sess([0-9]+)\.csv", filename)
+        if m is None:
+            raise ValueError('Incorrect filename format: %s'%(filename))
+        self.node = int(m.group(1))
+        self.inj_rate = int(m.group(2))
+        self.lpp = int(m.group(3))
+        self.traffic_patt = TRAFFIC_PATTERNS[m.group(4)]
+        self.session = int(m.group(5))
+
+        self.latencies = []
+        with open(filename, 'r') as csvfile:
+            reader = csv.reader(csvfile, delimiter=',')
+            isheader = True
+            for row in reader:
+                if isheader:
+                    isheader = False
+                    if row != ['Src', 'Dst', 'Seqno', 'Error', 'Latency']:
+                        raise ValueError('Incorrect header: %s'%(filename))
+                else:
+                    self.latencies.append(int(row[4]))
+
+
+########################################################################
+# main
+########################################################################
+if __name__=='__main__':
+    options = get_options()
+
+    if (not os.path.isdir(options.datadir)):
+        print('ERROR: Data director %s does not exist'%(options.datadir))
+        sys.exit(1)
+
+    info_db = dict()
+    info_files = glob.glob(os.path.join(options.datadir, 'info*.csv'))
+    router_impl = ''
+    lines_per_pkt = 0
+    for ifile in info_files:
+        print('INFO: Reading %s...'%(ifile))
+        tmp = InfoFile(ifile)
+        router_impl = tmp.impl  # Assume that all files have the same impl
+        lines_per_pkt = tmp.lpp  # Assume that all files have the same LPP
+        info_db[(tmp.lpp, tmp.traffic_patt, tmp.inj_rate)] = tmp
+
+    pkt_db = dict()
+    pkts_files = glob.glob(os.path.join(options.datadir, 'pkts*.csv'))
+    for pfile in pkts_files:
+        print('INFO: Reading %s...'%(pfile))
+        tmp = PktFile(pfile)
+        config_key = (tmp.lpp, tmp.traffic_patt)
+        if config_key not in pkt_db:
+            pkt_db[config_key] = dict()
+        if tmp.inj_rate not in pkt_db[config_key]:
+            pkt_db[config_key][tmp.inj_rate] = []
+
+
+        pkt_db[config_key][tmp.inj_rate].extend(tmp.latencies)
+
+    # Write load-latency plots to file
+    actual_inj_rate_db = dict()
+    for config in sorted(pkt_db):
+        (lpp, traffic_patt) = config
+        ll_file = 'load-latency_%s_traffic-%s_lpp-%d.png'%(router_impl, traffic_patt, lpp)
+        print('INFO: Writing file ' + ll_file + '...')
+        percentile = [0, 25, 50, 75, 90, 95, 99, 99.9, 100]
+        plt.figure()
+        plt.title('Load Latency Graph for %s\n(Traffic: %s, LPP: %d)'%(router_impl, traffic_patt, lpp))
+        for p in percentile:
+            plot_data = dict()
+            for inj_rate in pkt_db[config]:
+                real_inj_rate = info_db[(lpp, traffic_patt, inj_rate)].real_inj_rate
+                plot_data[real_inj_rate] = np.percentile(pkt_db[config][inj_rate], p)
+            latencies = []
+            rates = []
+            for inj_rate in sorted(plot_data):
+                rates.append(inj_rate)
+                latencies.append(plot_data[inj_rate])
+            plt.plot(rates, latencies, label='$P_{%.1f}$'%(p))
+            plt.xlabel('Load (%)')
+            plt.xticks(range(0, 110, 10))
+            plt.ylabel('Latency (cycles)')
+            plt.grid(True)
+        plt.legend()
+        plt.savefig(os.path.join(options.datadir, ll_file), dpi=120)
+        # Generate actual inj_rate graph
+        real_inj_rates = []
+        for inj_rate in sorted(pkt_db[config]):
+            real_inj_rates.append(info_db[(lpp, traffic_patt, inj_rate)].real_inj_rate)
+        actual_inj_rate_db[config] = (sorted(pkt_db[config]), real_inj_rates)
+
+    # Write offered vs actual injection rate plots to file
+    injrate_file = 'injection-rate_%s_lpp-%d.png'%(router_impl, lines_per_pkt)
+    print('INFO: Writing file ' + injrate_file + '...')
+    plt.figure()
+    plt.title('Max Injection Rate Graph for %s'%(router_impl))
+    for config in actual_inj_rate_db:
+        (x, y) = actual_inj_rate_db[config]
+        plt.plot(x, y, label=str(config))
+        plt.xlabel('Offered Injection Rate (%)')
+        plt.xticks(range(0, 110, 10))
+        plt.ylabel('Accepted Injection Rate (%)')
+        plt.yticks(range(0, 110, 10))
+        plt.grid(True)
+    plt.legend()
+    plt.savefig(os.path.join(options.datadir, injrate_file), dpi=120)
\ No newline at end of file
diff --git a/fpga/usrp3/lib/rfnoc/crossbar/crossbar_tb/run_sim_multi.py b/fpga/usrp3/lib/rfnoc/crossbar/crossbar_tb/run_sim_multi.py
new file mode 100755
index 000000000..8e546fef9
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/crossbar/crossbar_tb/run_sim_multi.py
@@ -0,0 +1,106 @@
+#!/usr/bin/python3
+#
+# Copyright 2018 Ettus Research, a National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+# Description
+#   Run the crossbar testbench (crossbar_tb) for varios parameter
+#   configurations and generates load-latency graphs for each run.
+
+import argparse
+import math
+import os, sys
+import shutil
+import glob
+import subprocess
+
+g_tb_top_template = """
+`timescale 1ns/1ps
+module crossbar_tb_auto();
+  crossbar_tb #(
+    .TEST_NAME          ("crossbar_tb_auto"),
+    .ROUTER_IMPL        ("{rtr_impl}"),
+    .ROUTER_PORTS       ({rtr_ports}),
+    .ROUTER_DWIDTH      ({rtr_width}),
+    .MTU_LOG2           ({rtr_mtu}),
+    .NUM_MASTERS        ({rtr_sources}),
+    .TEST_MAX_PACKETS   ({tst_maxpkts}),
+    .TEST_LPP           ({tst_lpp}),
+    .TEST_MIN_INJ_RATE  ({tst_injrate_min}),
+    .TEST_MAX_INJ_RATE  ({tst_injrate_max}),
+    .TEST_INJ_RATE_INCR (10),
+    .TEST_GEN_LL_FILES  (1)
+  ) impl (
+    /* no IO */
+  );
+endmodule
+"""
+
+g_test_params = {
+    'data': {'rtr_width':64, 'rtr_mtu':7, 'tst_maxpkts':100, 'tst_lpp':100, 'tst_injrate_min':30, 'tst_injrate_max':100},
+    'ctrl': {'rtr_width':64, 'rtr_mtu':5, 'tst_maxpkts':100, 'tst_lpp':20,  'tst_injrate_min':10, 'tst_injrate_max':50},
+}
+
+g_xb_types = {
+    'chdr_crossbar_nxn':'data', 'axi_crossbar':'data',
+    'axis_ctrl_2d_torus':'ctrl', 'axis_ctrl_2d_mesh':'ctrl'
+}
+
+def get_options():
+    parser = argparse.ArgumentParser(description='Run correctness sim and generate load-latency plots')
+    parser.add_argument('--impl', type=str, default='chdr_crossbar_nxn', help='Implementation (CSV) [%s]'%(','.join(g_xb_types.keys())))
+    parser.add_argument('--ports', type=str, default='16', help='Number of ports (CSV)')
+    parser.add_argument('--sources', type=str, default='16', help='Number of active data sources (masters)')
+    return parser.parse_args()
+
+def launch_run(impl, ports, sources):
+    run_name = '%s_ports%d_srcs%d'%(impl, ports, sources)
+    # Prepare a transform map to autogenerate a TB file
+    transform = {'rtr_impl':impl, 'rtr_ports':ports, 'rtr_sources':sources}
+    for k,v in g_test_params[g_xb_types[impl]].items():
+        transform[k] = v
+    # Create crossbar_tb_auto.sv with specified parameters
+    with open('crossbar_tb_auto.sv', 'w') as out_file:
+        out_file.write(g_tb_top_template.format(**transform))
+    # Create data directory for the simulation
+    data_dir = os.path.join('data', impl)
+    export_dir = os.path.join('data', run_name)
+    try:
+        os.makedirs('data')
+    except FileExistsError:
+        pass
+    os.makedirs(data_dir)
+    os.makedirs(export_dir)
+    # Run "make xsim"
+    exitcode = subprocess.Popen('make xsim TB_TOP_MODULE=crossbar_tb_auto', shell=True).wait()
+    if exitcode != 0:
+        raise RuntimeError('Error running "make xsim". Was setupenv.sh run?')
+    # Generate load-latency graphs
+    exitcode = subprocess.Popen('gen_load_latency_graph.py ' + data_dir, shell=True).wait()
+    if exitcode != 0:
+        raise RuntimeError('Error running "gen_load_latency_graph.py"')
+    # Copy files
+    os.rename('xsim.log', os.path.join(export_dir, 'xsim.log'))
+    for file in glob.glob(os.path.join(data_dir, '*.png')):
+        shutil.copy(file, export_dir)
+    # Cleanup outputs
+    subprocess.Popen('make cleanall', shell=True).wait()
+    try:
+        os.remove('crossbar_tb_auto.sv')
+    except FileNotFoundError:
+        pass
+    try:
+        shutil.rmtree(data_dir)
+    except OSError:
+        print('WARNING: Could not delete ' + data_dir)
+
+def main():
+    args = get_options();
+    for impl in args.impl.strip().split(','):
+        for ports in args.ports.strip().split(','):
+            for sources in args.sources.strip().split(','):
+                launch_run(impl, int(ports), min(int(ports), int(sources)))
+
+if __name__ == '__main__':
+    main()
diff --git a/fpga/usrp3/lib/rfnoc/crossbar/gen_node_to_coord_mapping.py b/fpga/usrp3/lib/rfnoc/crossbar/gen_node_to_coord_mapping.py
new file mode 100755
index 000000000..a2eaf71fb
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/crossbar/gen_node_to_coord_mapping.py
@@ -0,0 +1,125 @@
+#!/usr/bin/python3
+#
+# Copyright 2018 Ettus Research, a National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+import argparse
+import math
+import sys
+import datetime
+import random
+
+# Parse command line options
+# ------------------------------------------------
+def get_options():
+    parser = argparse.ArgumentParser(description='Generate a node to coordinate mapping file.')
+    parser.add_argument('--pattern', type=str, default='xy', choices=['xy', 'yx', 'spiral', 'random'], help='Node distribution pattern')
+    parser.add_argument('--dimsize', type=int, default=4, help='Maximum dimension size')
+    parser.add_argument('--seed', type=int, default=None, help='Seed for random permutation generator')
+    return parser.parse_args()
+
+# Pattern Generators
+# ------------------------------------------------
+def gen_xy(N):
+    nodes = dict()
+    for y in range(N):
+        for x in range(N):
+            nodes[(y*N + x)] = (x, y)
+    return nodes
+
+def gen_yx(N):
+    nodes = dict()
+    for y in range(N):
+        for x in range(N):
+            nodes[(x*N + y)] = (x, y)
+    return nodes
+
+def gen_spiral(N):
+    nodes = dict()
+    x = y = 0
+    dx = 0
+    dy = -1
+    for i in range(N**2):
+        if (-N/2 < x <= N/2) and (-N/2 < y <= N/2):
+            nodes[i] = (x + int(math.ceil(N/2)) - 1, y + int(math.ceil(N/2)) - 1)
+        if x == y or (x < 0 and x == -y) or (x > 0 and x == 1-y):
+            dx, dy = -dy, dx
+        x, y = x+dx, y+dy
+    return nodes
+
+def gen_random(N):
+    nodes = dict()
+    rnodes = random.sample(range(N*N), N*N)
+    for y in range(N):
+        for x in range(N):
+            nodes[rnodes[x*N + y]] = (x, y)
+    return nodes
+
+# Source Generators
+# ------------------------------------------------
+def layout_nodes(nodes):
+    N = int(math.sqrt(len(nodes)))
+    #inv_nodes = {v: k for k, v in nodes.iteritems()}
+    coords = {v: k for k, v in nodes.items()}
+    lines = []
+    for y in range(N):
+        line = ''
+        for x in range(N):
+            line += '%5d'%(coords[(x,y)])
+        lines.append(line)
+    return lines
+
+def gen_vparams(nodes, N, pattern):
+    src_lines = [ '\n// DIM_SIZE = %d, PATTERN = %s'%(N,pattern.upper()), '//------------------------------------' ]
+    for l in layout_nodes(nodes):
+        src_lines.append('// ' + l)
+    bitw = math.ceil(math.log2(N))
+    xvals = ','.join(['%d\'d%d'%(bitw,v[0]) for k, v in sorted(nodes.items(), reverse=True)])
+    yvals = ','.join(['%d\'d%d'%(bitw,v[1]) for k, v in sorted(nodes.items(), reverse=True)])
+    xpar = 'localparam [%d:0] XCOORD_DIM_%03d = {%s};'%(bitw*N*N-1, N, xvals)
+    ypar = 'localparam [%d:0] YCOORD_DIM_%03d = {%s};'%(bitw*N*N-1, N, yvals)
+    src_lines.append(xpar)
+    src_lines.append(ypar)
+    src_lines.append('')
+    return src_lines
+
+def gen_lookup_func(dim, N):
+    src_lines = [ 'function [CLOG2_DIM_SIZE-1:0] node_to_%sdst;'%(dim), '  input [WIDTH-1:0] header;', 'begin']
+    dim_sizes = range(2, N+1)
+    for i in dim_sizes:
+        node_bitw = math.ceil(math.log2(i*i))
+        dim_bitw = math.ceil(math.log2(i))
+        prefix = '  ' if (i == dim_sizes[0]) else '  else '
+        src_lines.append(prefix + 'if (DIM_SIZE == %d)'%(i))
+        src_lines.append('    node_to_%sdst = %sCOORD_DIM_%03d[%d*header[%d:0] +: %d];'%(dim,dim.upper(),i,dim_bitw,node_bitw-1,dim_bitw))
+    src_lines.append('  else')
+    src_lines.append('    node_to_%sdst = {CLOG2_DIM_SIZE{1\'d0}};'%(dim))
+    src_lines.append('end endfunction\n\n')
+    return src_lines
+
+def gen_vheader(dimsize, mapgen, pattern, filename):
+    with open(filename, 'w') as vhfile:
+        vhfile.write('// Copyright %s Ettus Research, A National Instruments Company\n'%(datetime.datetime.now().year))
+        vhfile.write('// SPDX-License-Identifier: LGPL-3.0-or-later\n')
+        vhfile.write('//\n')
+        vhfile.write('// Autogenerated file. Do not modify.\n')
+        vhfile.write('// $ %s\n'%(' '.join(sys.argv[:])))
+        vhfile.write('\nparameter CLOG2_DIM_SIZE = $clog2(DIM_SIZE); //Vivado workaround\n\n')
+        for i in range(2, dimsize+1):
+            nodes = mapgen(i)
+            N = math.sqrt(len(nodes))
+            vhfile.write('\n'.join(gen_vparams(nodes, N, pattern)))
+        vhfile.write('\n\n')
+        vhfile.write('\n'.join(gen_lookup_func('x', dimsize)))
+        vhfile.write('\n'.join(gen_lookup_func('y', dimsize)))
+
+def main():
+    args = get_options();
+    random.seed(args.seed)
+    generators = {'xy': gen_xy, 'yx': gen_yx, 'spiral':gen_spiral, 'random': gen_random}
+    gen_vheader(args.dimsize, generators[args.pattern], args.pattern, 'mesh_node_mapping.vh')
+
+if __name__ == '__main__':
+    main()
diff --git a/fpga/usrp3/lib/rfnoc/crossbar/mesh_2d_dor_router_multi_sw.v b/fpga/usrp3/lib/rfnoc/crossbar/mesh_2d_dor_router_multi_sw.v
new file mode 100644
index 000000000..e0338347b
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/crossbar/mesh_2d_dor_router_multi_sw.v
@@ -0,0 +1,481 @@
+//
+// Copyright 2018 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: mesh_2d_dor_router_multi_sw
+// Description:
+//   Alternate implementation for mesh_2d_dor_router_single_sw with
+//   multiple switches for independent paths between inputs and outputs
+//   **NOTE**: This module has not been validated
+
+module mesh_2d_dor_router_multi_sw #(
+  parameter                        WIDTH          = 64,
+  parameter                        DIM_SIZE       = 4,
+  parameter [$clog2(DIM_SIZE)-1:0] XB_ADDR_X      = 0,
+  parameter [$clog2(DIM_SIZE)-1:0] XB_ADDR_Y      = 0,
+  parameter                        TERM_BUFF_SIZE = 5,
+  parameter                        XB_BUFF_SIZE   = 5,
+  parameter                        ROUTING_ALLOC  = "WORMHOLE",  // Routing (switching) method {WORMHOLE, CUT-THROUGH}
+  parameter                        SWITCH_ALLOC   = "PRIO"       // Switch allocation algorithm {ROUND-ROBIN, PRIO}
+) (
+  // Clocks and resets
+  input  wire             clk,
+  input  wire             reset,
+
+  // Terminal connections
+  input  wire [WIDTH-1:0] s_axis_ter_tdata,
+  input  wire             s_axis_ter_tlast,
+  input  wire             s_axis_ter_tvalid,
+  output wire             s_axis_ter_tready,
+  output wire [WIDTH-1:0] m_axis_ter_tdata,
+  output wire             m_axis_ter_tlast,
+  output wire             m_axis_ter_tvalid,
+  input  wire             m_axis_ter_tready,
+
+  // West inter-router connections
+  input  wire [WIDTH-1:0] s_axis_wst_tdata,
+  input  wire [0:0]       s_axis_wst_tdest,
+  input  wire             s_axis_wst_tlast,
+  input  wire             s_axis_wst_tvalid,
+  output wire             s_axis_wst_tready,
+  output wire [WIDTH-1:0] m_axis_wst_tdata,
+  output wire [0:0]       m_axis_wst_tdest,
+  output wire             m_axis_wst_tlast,
+  output wire             m_axis_wst_tvalid,
+  input  wire             m_axis_wst_tready,
+
+  // East inter-router connections
+  input  wire [WIDTH-1:0] s_axis_est_tdata,
+  input  wire [0:0]       s_axis_est_tdest,
+  input  wire             s_axis_est_tlast,
+  input  wire             s_axis_est_tvalid,
+  output wire             s_axis_est_tready,
+  output wire [WIDTH-1:0] m_axis_est_tdata,
+  output wire [0:0]       m_axis_est_tdest,
+  output wire             m_axis_est_tlast,
+  output wire             m_axis_est_tvalid,
+  input  wire             m_axis_est_tready,
+
+  // North inter-router connections
+  input  wire [WIDTH-1:0] s_axis_nor_tdata,
+  input  wire [0:0]       s_axis_nor_tdest,
+  input  wire             s_axis_nor_tlast,
+  input  wire             s_axis_nor_tvalid,
+  output wire             s_axis_nor_tready,
+  output wire [WIDTH-1:0] m_axis_nor_tdata,
+  output wire [0:0]       m_axis_nor_tdest,
+  output wire             m_axis_nor_tlast,
+  output wire             m_axis_nor_tvalid,
+  input  wire             m_axis_nor_tready,
+
+  // South inter-router connections
+  input  wire [WIDTH-1:0] s_axis_sou_tdata,
+  input  wire [0:0]       s_axis_sou_tdest,
+  input  wire             s_axis_sou_tlast,
+  input  wire             s_axis_sou_tvalid,
+  output wire             s_axis_sou_tready,
+  output wire [WIDTH-1:0] m_axis_sou_tdata,
+  output wire [0:0]       m_axis_sou_tdest,
+  output wire             m_axis_sou_tlast,
+  output wire             m_axis_sou_tvalid,
+  input  wire             m_axis_sou_tready
+);
+  // -------------------------------------------------
+  // Routing functions
+  // -------------------------------------------------
+  `include "mesh_node_mapping.vh"
+
+  function [2:0] term_route;
+    input [WIDTH-1:0] header;
+    reg [$clog2(DIM_SIZE)-1:0] xdst, ydst;
+    reg signed [$clog2(DIM_SIZE):0] xdiff, ydiff;
+  begin
+    xdst  = node_to_xdst(header);
+    ydst  = node_to_ydst(header);
+    xdiff = xdst - XB_ADDR_X;
+    ydiff = ydst - XB_ADDR_Y;
+    // Routing logic
+    if (xdst == XB_ADDR_X && ydst == XB_ADDR_Y) begin
+      term_route = 3'd0; //TER
+    end else if (xdst == XB_ADDR_X) begin
+      if (ydiff < 0)
+        term_route = 3'd3; //NOR
+      else
+        term_route = 3'd4; //SOU
+    end else begin
+      if (xdiff < 0)
+        term_route = 3'd1; //WST
+      else
+        term_route = 3'd2; //EST
+    end
+  end
+  endfunction
+
+  function [1:0] xdim_route;
+    input [WIDTH-1:0] header;
+    reg [$clog2(DIM_SIZE)-1:0] xdst, ydst;
+    reg signed [$clog2(DIM_SIZE):0] xdiff, ydiff;
+  begin
+    xdst  = node_to_xdst(header);
+    ydst  = node_to_ydst(header);
+    xdiff = xdst - XB_ADDR_X;
+    ydiff = ydst - XB_ADDR_Y;
+    // Routing logic
+    if (xdst == XB_ADDR_X && ydst == XB_ADDR_Y) begin
+      xdim_route = 2'd0; //TER
+    end else if (xdst == XB_ADDR_X) begin
+      if (ydiff < 0)
+        xdim_route = 2'd2; //NOR
+      else
+        xdim_route = 2'd3; //SOU
+    end else begin
+      xdim_route = 2'd1; //Forward
+    end
+  end
+  endfunction
+
+  function [0:0] ydim_route;
+    input [WIDTH-1:0] header;
+    reg [$clog2(DIM_SIZE)-1:0] xdst, ydst;
+    reg signed [$clog2(DIM_SIZE):0] xdiff, ydiff;
+  begin
+    xdst  = node_to_xdst(header);
+    ydst  = node_to_ydst(header);
+    xdiff = xdst - XB_ADDR_X;
+    ydiff = ydst - XB_ADDR_Y;
+    // Routing logic
+    if (xdst == XB_ADDR_X && ydst == XB_ADDR_Y) begin
+      ydim_route = 1'd0; //TER
+    end else if (xdst == XB_ADDR_X) begin
+      ydim_route = 1'd1; //Forward
+    end
+  end
+  endfunction
+
+
+  // -------------------------------------------------
+  // Input buffers
+  // -------------------------------------------------
+  wire [WIDTH-1:0] ter_i_tdata;
+  wire             ter_i_tlast;
+  wire             ter_i_tvalid;
+  wire             ter_i_tready;
+
+  axi_packet_gate #(
+    .WIDTH(WIDTH), .SIZE(TERM_BUFF_SIZE)
+  ) term_in_pkt_gate_i (
+    .clk      (clk), 
+    .reset    (reset), 
+    .clear    (1'b0),
+    .i_tdata  (s_axis_ter_tdata),
+    .i_tlast  (s_axis_ter_tlast),
+    .i_tvalid (s_axis_ter_tvalid),
+    .i_tready (s_axis_ter_tready),
+    .i_terror (1'b0),
+    .o_tdata  (ter_i_tdata),
+    .o_tlast  (ter_i_tlast),
+    .o_tvalid (ter_i_tvalid),
+    .o_tready (ter_i_tready)
+  );
+
+  wire [WIDTH-1:0] wst_i_tdata,  est_i_tdata,  nor_i_tdata,  sou_i_tdata;
+  wire             wst_i_tlast,  est_i_tlast,  nor_i_tlast,  sou_i_tlast;
+  wire             wst_i_tvalid, est_i_tvalid, nor_i_tvalid, sou_i_tvalid;
+  wire             wst_i_tready, est_i_tready, nor_i_tready, sou_i_tready;
+
+  axis_ingress_vc_buff #(
+    .WIDTH(WIDTH), .NUM_VCS(1),
+    .SIZE(XB_BUFF_SIZE),
+    .ROUTING(ROUTING_ALLOC)
+  ) wst_in_vc_buf_i (
+    .clk           (clk), 
+    .reset         (reset), 
+    .s_axis_tdata  (s_axis_wst_tdata),
+    .s_axis_tdest  (s_axis_wst_tdest),
+    .s_axis_tlast  (s_axis_wst_tlast),
+    .s_axis_tvalid (s_axis_wst_tvalid),
+    .s_axis_tready (s_axis_wst_tready),
+    .m_axis_tdata  (wst_i_tdata),
+    .m_axis_tlast  (wst_i_tlast),
+    .m_axis_tvalid (wst_i_tvalid),
+    .m_axis_tready (wst_i_tready)
+  );
+
+  axis_ingress_vc_buff #(
+    .WIDTH(WIDTH), .NUM_VCS(1),
+    .SIZE(XB_BUFF_SIZE),
+    .ROUTING(ROUTING_ALLOC)
+  ) est_in_vc_buf_i (
+    .clk           (clk), 
+    .reset         (reset), 
+    .s_axis_tdata  (s_axis_est_tdata),
+    .s_axis_tdest  (s_axis_est_tdest),
+    .s_axis_tlast  (s_axis_est_tlast),
+    .s_axis_tvalid (s_axis_est_tvalid),
+    .s_axis_tready (s_axis_est_tready),
+    .m_axis_tdata  (est_i_tdata),
+    .m_axis_tlast  (est_i_tlast),
+    .m_axis_tvalid (est_i_tvalid),
+    .m_axis_tready (est_i_tready)
+  );
+
+  axis_ingress_vc_buff #(
+    .WIDTH(WIDTH), .NUM_VCS(1),
+    .SIZE(XB_BUFF_SIZE),
+    .ROUTING(ROUTING_ALLOC)
+  ) nor_in_vc_buf_i (
+    .clk           (clk), 
+    .reset         (reset), 
+    .s_axis_tdata  (s_axis_nor_tdata),
+    .s_axis_tdest  (s_axis_nor_tdest),
+    .s_axis_tlast  (s_axis_nor_tlast),
+    .s_axis_tvalid (s_axis_nor_tvalid),
+    .s_axis_tready (s_axis_nor_tready),
+    .m_axis_tdata  (nor_i_tdata),
+    .m_axis_tlast  (nor_i_tlast),
+    .m_axis_tvalid (nor_i_tvalid),
+    .m_axis_tready (nor_i_tready)
+  );
+
+  axis_ingress_vc_buff #(
+    .WIDTH(WIDTH), .NUM_VCS(1),
+    .SIZE(XB_BUFF_SIZE),
+    .ROUTING(ROUTING_ALLOC)
+  ) sou_in_vc_buf_i (
+    .clk           (clk), 
+    .reset         (reset), 
+    .s_axis_tdata  (s_axis_sou_tdata),
+    .s_axis_tdest  (s_axis_sou_tdest),
+    .s_axis_tlast  (s_axis_sou_tlast),
+    .s_axis_tvalid (s_axis_sou_tvalid),
+    .s_axis_tready (s_axis_sou_tready),
+    .m_axis_tdata  (sou_i_tdata),
+    .m_axis_tlast  (sou_i_tlast),
+    .m_axis_tvalid (sou_i_tvalid),
+    .m_axis_tready (sou_i_tready)
+  );
+
+  // -------------------------------------------------
+  // Input demuxes
+  // -------------------------------------------------
+
+  wire [WIDTH-1:0] t2t_tdata,  t2w_tdata,  t2e_tdata,  t2n_tdata,  t2s_tdata;
+  wire             t2t_tlast,  t2w_tlast,  t2e_tlast,  t2n_tlast,  t2s_tlast;
+  wire             t2t_tvalid, t2w_tvalid, t2e_tvalid, t2n_tvalid, t2s_tvalid;
+  wire             t2t_tready, t2w_tready, t2e_tready, t2n_tready, t2s_tready;
+
+  wire [WIDTH-1:0] w2t_tdata,  w2e_tdata,  w2n_tdata,  w2s_tdata;
+  wire             w2t_tlast,  w2e_tlast,  w2n_tlast,  w2s_tlast;
+  wire             w2t_tvalid, w2e_tvalid, w2n_tvalid, w2s_tvalid;
+  wire             w2t_tready, w2e_tready, w2n_tready, w2s_tready;
+
+  wire [WIDTH-1:0] e2t_tdata,  e2w_tdata,  e2n_tdata,  e2s_tdata;
+  wire             e2t_tlast,  e2w_tlast,  e2n_tlast,  e2s_tlast;
+  wire             e2t_tvalid, e2w_tvalid, e2n_tvalid, e2s_tvalid;
+  wire             e2t_tready, e2w_tready, e2n_tready, e2s_tready;
+
+  wire [WIDTH-1:0] n2t_tdata,  n2s_tdata;
+  wire             n2t_tlast,  n2s_tlast;
+  wire             n2t_tvalid, n2s_tvalid;
+  wire             n2t_tready, n2s_tready;
+
+  wire [WIDTH-1:0] s2t_tdata,  s2n_tdata;
+  wire             s2t_tlast,  s2n_tlast;
+  wire             s2t_tvalid, s2n_tvalid;
+  wire             s2t_tready, s2n_tready;
+
+  wire [WIDTH-1:0] ter_i_hdr, wst_i_hdr, est_i_hdr, nor_i_hdr, sou_i_hdr;
+
+  axi_demux #(
+    .WIDTH(WIDTH), .SIZE(5),
+    .PRE_FIFO_SIZE(0 /* must be 0 */), .POST_FIFO_SIZE(0)
+  ) ter_i_demux_i (
+    .clk      (clk),
+    .reset    (reset),
+    .clear    (1'b0),
+    .header   (ter_i_hdr),
+    .dest     (term_route(ter_i_hdr)),
+    .i_tdata  (ter_i_tdata),
+    .i_tlast  (ter_i_tlast),
+    .i_tvalid (ter_i_tvalid),
+    .i_tready (ter_i_tready),
+    .o_tdata  ({t2s_tdata,  t2n_tdata,  t2e_tdata,  t2w_tdata,  t2t_tdata}),
+    .o_tlast  ({t2s_tlast,  t2n_tlast,  t2e_tlast,  t2w_tlast,  t2t_tlast}),
+    .o_tvalid ({t2s_tvalid, t2n_tvalid, t2e_tvalid, t2w_tvalid, t2t_tvalid}),
+    .o_tready ({t2s_tready, t2n_tready, t2e_tready, t2w_tready, t2t_tready})
+  );
+
+  axi_demux #(
+    .WIDTH(WIDTH), .SIZE(4),
+    .PRE_FIFO_SIZE(0 /* must be 0 */), .POST_FIFO_SIZE(0)
+  ) wst_i_demux_i (
+    .clk      (clk),
+    .reset    (reset),
+    .clear    (1'b0),
+    .header   (wst_i_hdr),
+    .dest     (xdim_route(wst_i_hdr)),
+    .i_tdata  (wst_i_tdata),
+    .i_tlast  (wst_i_tlast),
+    .i_tvalid (wst_i_tvalid),
+    .i_tready (wst_i_tready),
+    .o_tdata  ({w2s_tdata,  w2n_tdata,  w2e_tdata,  w2t_tdata}),
+    .o_tlast  ({w2s_tlast,  w2n_tlast,  w2e_tlast,  w2t_tlast}),
+    .o_tvalid ({w2s_tvalid, w2n_tvalid, w2e_tvalid, w2t_tvalid}),
+    .o_tready ({w2s_tready, w2n_tready, w2e_tready, w2t_tready})
+  );
+
+  axi_demux #(
+    .WIDTH(WIDTH), .SIZE(4),
+    .PRE_FIFO_SIZE(0 /* must be 0 */), .POST_FIFO_SIZE(0)
+  ) est_i_demux_i (
+    .clk      (clk),
+    .reset    (reset),
+    .clear    (1'b0),
+    .header   (est_i_hdr),
+    .dest     (xdim_route(est_i_hdr)),
+    .i_tdata  (est_i_tdata),
+    .i_tlast  (est_i_tlast),
+    .i_tvalid (est_i_tvalid),
+    .i_tready (est_i_tready),
+    .o_tdata  ({e2s_tdata,  e2n_tdata,  e2w_tdata,  e2t_tdata}),
+    .o_tlast  ({e2s_tlast,  e2n_tlast,  e2w_tlast,  e2t_tlast}),
+    .o_tvalid ({e2s_tvalid, e2n_tvalid, e2w_tvalid, e2t_tvalid}),
+    .o_tready ({e2s_tready, e2n_tready, e2w_tready, e2t_tready})
+  );
+
+  axi_demux #(
+    .WIDTH(WIDTH), .SIZE(2),
+    .PRE_FIFO_SIZE(0 /* must be 0 */), .POST_FIFO_SIZE(0)
+  ) nor_i_demux_i (
+    .clk      (clk),
+    .reset    (reset),
+    .clear    (1'b0),
+    .header   (nor_i_hdr),
+    .dest     (ydim_route(nor_i_hdr)),
+    .i_tdata  (nor_i_tdata),
+    .i_tlast  (nor_i_tlast),
+    .i_tvalid (nor_i_tvalid),
+    .i_tready (nor_i_tready),
+    .o_tdata  ({n2t_tdata,  n2s_tdata}),
+    .o_tlast  ({n2t_tlast,  n2s_tlast}),
+    .o_tvalid ({n2t_tvalid, n2s_tvalid}),
+    .o_tready ({n2t_tready, n2s_tready})
+  );
+
+  axi_demux #(
+    .WIDTH(WIDTH), .SIZE(2),
+    .PRE_FIFO_SIZE(0 /* must be 0 */), .POST_FIFO_SIZE(0)
+  ) sou_i_demux_i (
+    .clk      (clk),
+    .reset    (reset),
+    .clear    (1'b0),
+    .header   (sou_i_hdr),
+    .dest     (ydim_route(sou_i_hdr)),
+    .i_tdata  (sou_i_tdata),
+    .i_tlast  (sou_i_tlast),
+    .i_tvalid (sou_i_tvalid),
+    .i_tready (sou_i_tready),
+    .o_tdata  ({s2t_tdata,  s2n_tdata}),
+    .o_tlast  ({s2t_tlast,  s2n_tlast}),
+    .o_tvalid ({s2t_tvalid, s2n_tvalid}),
+    .o_tready ({s2t_tready, s2n_tready})
+  );
+
+  // -------------------------------------------------
+  // Output muxes
+  // -------------------------------------------------
+
+  axi_mux #(
+    .WIDTH(WIDTH), .SIZE(5),
+    .PRE_FIFO_SIZE(0), .POST_FIFO_SIZE(1)
+  ) ter_o_mux_i (
+    .clk      (clk),
+    .reset    (reset),
+    .clear    (1'b0),
+    .i_tdata  ({t2t_tdata,  w2t_tdata,  e2t_tdata,  n2t_tdata,  s2t_tdata}),
+    .i_tlast  ({t2t_tlast,  w2t_tlast,  e2t_tlast,  n2t_tlast,  s2t_tlast}),
+    .i_tvalid ({t2t_tvalid, w2t_tvalid, e2t_tvalid, n2t_tvalid, s2t_tvalid}),
+    .i_tready ({t2t_tready, w2t_tready, e2t_tready, n2t_tready, s2t_tready}),
+    .o_tdata  (m_axis_ter_tdata),
+    .o_tlast  (m_axis_ter_tlast),
+    .o_tvalid (m_axis_ter_tvalid),
+    .o_tready (m_axis_ter_tready)
+  );
+
+  axi_mux #(
+    .WIDTH(WIDTH), .SIZE(2),
+    .PRE_FIFO_SIZE(0), .POST_FIFO_SIZE(1)
+  ) wst_o_mux_i (
+    .clk      (clk),
+    .reset    (reset),
+    .clear    (1'b0),
+    .i_tdata  ({t2w_tdata,  e2w_tdata}),
+    .i_tlast  ({t2w_tlast,  e2w_tlast}),
+    .i_tvalid ({t2w_tvalid, e2w_tvalid}),
+    .i_tready ({t2w_tready, e2w_tready}),
+    .o_tdata  (m_axis_wst_tdata),
+    .o_tlast  (m_axis_wst_tlast),
+    .o_tvalid (m_axis_wst_tvalid),
+    .o_tready (m_axis_wst_tready)
+  );
+  assign m_axis_wst_tdest = 1'b0;
+
+  axi_mux #(
+    .WIDTH(WIDTH), .SIZE(2),
+    .PRE_FIFO_SIZE(0), .POST_FIFO_SIZE(1)
+  ) est_o_mux_i (
+    .clk      (clk),
+    .reset    (reset),
+    .clear    (1'b0),
+    .i_tdata  ({t2e_tdata,  w2e_tdata}),
+    .i_tlast  ({t2e_tlast,  w2e_tlast}),
+    .i_tvalid ({t2e_tvalid, w2e_tvalid}),
+    .i_tready ({t2e_tready, w2e_tready}),
+    .o_tdata  (m_axis_est_tdata),
+    .o_tlast  (m_axis_est_tlast),
+    .o_tvalid (m_axis_est_tvalid),
+    
+    
+    .o_tready (m_axis_est_tready)
+  );
+  assign m_axis_est_tdest = 1'b0;
+
+  axi_mux #(
+    .WIDTH(WIDTH), .SIZE(4),
+    .PRE_FIFO_SIZE(0), .POST_FIFO_SIZE(1)
+  ) nor_o_mux_i (
+    .clk      (clk),
+    .reset    (reset),
+    .clear    (1'b0),
+    .i_tdata  ({t2n_tdata,  w2n_tdata,  e2n_tdata,  s2n_tdata}),
+    .i_tlast  ({t2n_tlast,  w2n_tlast,  e2n_tlast,  s2n_tlast}),
+    .i_tvalid ({t2n_tvalid, w2n_tvalid, e2n_tvalid, s2n_tvalid}),
+    .i_tready ({t2n_tready, w2n_tready, e2n_tready, s2n_tready}),
+    .o_tdata  (m_axis_nor_tdata),
+    .o_tlast  (m_axis_nor_tlast),
+    .o_tvalid (m_axis_nor_tvalid),
+    .o_tready (m_axis_nor_tready)
+  );
+  assign m_axis_nor_tdest = 1'b0;
+
+  axi_mux #(
+    .WIDTH(WIDTH), .SIZE(4),
+    .PRE_FIFO_SIZE(0), .POST_FIFO_SIZE(1)
+  ) sou_o_mux_i (
+    .clk      (clk),
+    .reset    (reset),
+    .clear    (1'b0),
+    .i_tdata  ({t2s_tdata,  w2s_tdata,  e2s_tdata,  n2s_tdata}),
+    .i_tlast  ({t2s_tlast,  w2s_tlast,  e2s_tlast,  n2s_tlast}),
+    .i_tvalid ({t2s_tvalid, w2s_tvalid, e2s_tvalid, n2s_tvalid}),
+    .i_tready ({t2s_tready, w2s_tready, e2s_tready, n2s_tready}),
+    .o_tdata  (m_axis_sou_tdata),
+    .o_tlast  (m_axis_sou_tlast),
+    .o_tvalid (m_axis_sou_tvalid),
+    .o_tready (m_axis_sou_tready)
+  );
+  assign m_axis_sou_tdest = 1'b0;
+
+endmodule
+
diff --git a/fpga/usrp3/lib/rfnoc/crossbar/mesh_2d_dor_router_single_sw.v b/fpga/usrp3/lib/rfnoc/crossbar/mesh_2d_dor_router_single_sw.v
new file mode 100644
index 000000000..65cded545
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/crossbar/mesh_2d_dor_router_single_sw.v
@@ -0,0 +1,398 @@
+//
+// Copyright 2018 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: mesh_2d_dor_router_single_sw
+// Description: 
+//   This module implements the router for a 2-dimentional (2d) 
+//   mesh network that uses dimension order routing (dor) and has a 
+//   single underlying switch (single_sw). It uses AXI-Stream for all of its
+//   links. 
+//   The mesh topology, routing algorithms and the router architecture is 
+//   described in README.md in this directory. 
+// Parameters:
+//   - WIDTH: Width of the AXI-Stream data bus
+//   - DIM_SIZE: Number of routers alone one dimension
+//   - XB_ADDR_X: The X-coordinate of this router in the topology
+//   - XB_ADDR_Y: The Y-coordinate of this router in the topology
+//   - TERM_BUFF_SIZE: log2 of the ingress terminal buffer size (in words)
+//   - XB_BUFF_SIZE: log2 of the ingress inter-router buffer size (in words)
+//   - ROUTING_ALLOC: Algorithm to allocate routing paths between routers.
+//     * WORMHOLE: Allocate route as soon as first word in pkt arrives
+//     * CUT-THROUGH: Allocate route only after the full pkt arrives
+//   - SWITCH_ALLOC: Algorithm to allocate the switch
+//     * PRIO: Priority based. Priority: Y-dim > X-dim > Term
+//     * ROUND-ROBIN: Round robin input port allocation
+// Signals:
+//   - *_axis_ter_*: Terminal ports (master/slave)
+//   - *_axis_wst_*: Inter-router X-dim west connections (master/slave)
+//   - *_axis_est_*: Inter-router X-dim east connections (master/slave)
+//   - *_axis_nor_*: Inter-router X-dim north connections (master/slave)
+//   - *_axis_sou_*: Inter-router X-dim south connections (master/slave)
+//
+
+module mesh_2d_dor_router_single_sw #(
+  parameter                        WIDTH          = 64,
+  parameter                        DIM_SIZE       = 4,
+  parameter [$clog2(DIM_SIZE)-1:0] XB_ADDR_X      = 0,
+  parameter [$clog2(DIM_SIZE)-1:0] XB_ADDR_Y      = 0,
+  parameter                        TERM_BUFF_SIZE = 5,
+  parameter                        XB_BUFF_SIZE   = 5,
+  parameter                        ROUTING_ALLOC  = "WORMHOLE",  // Routing (switching) method {WORMHOLE, CUT-THROUGH}
+  parameter                        SWITCH_ALLOC   = "PRIO"       // Switch allocation algorithm {ROUND-ROBIN, PRIO}
+) (
+  // Clocks and resets
+  input  wire             clk,
+  input  wire             reset,
+
+  // Terminal connections
+  input  wire [WIDTH-1:0] s_axis_ter_tdata,
+  input  wire             s_axis_ter_tlast,
+  input  wire             s_axis_ter_tvalid,
+  output wire             s_axis_ter_tready,
+  output wire [WIDTH-1:0] m_axis_ter_tdata,
+  output wire             m_axis_ter_tlast,
+  output wire             m_axis_ter_tvalid,
+  input  wire             m_axis_ter_tready,
+
+  // West inter-router connections
+  input  wire [WIDTH-1:0] s_axis_wst_tdata,
+  input  wire [0:0]       s_axis_wst_tdest,
+  input  wire             s_axis_wst_tlast,
+  input  wire             s_axis_wst_tvalid,
+  output wire             s_axis_wst_tready,
+  output wire [WIDTH-1:0] m_axis_wst_tdata,
+  output wire [0:0]       m_axis_wst_tdest,
+  output wire             m_axis_wst_tlast,
+  output wire             m_axis_wst_tvalid,
+  input  wire             m_axis_wst_tready,
+
+  // East inter-router connections
+  input  wire [WIDTH-1:0] s_axis_est_tdata,
+  input  wire [0:0]       s_axis_est_tdest,
+  input  wire             s_axis_est_tlast,
+  input  wire             s_axis_est_tvalid,
+  output wire             s_axis_est_tready,
+  output wire [WIDTH-1:0] m_axis_est_tdata,
+  output wire [0:0]       m_axis_est_tdest,
+  output wire             m_axis_est_tlast,
+  output wire             m_axis_est_tvalid,
+  input  wire             m_axis_est_tready,
+
+  // North inter-router connections
+  input  wire [WIDTH-1:0] s_axis_nor_tdata,
+  input  wire [0:0]       s_axis_nor_tdest,
+  input  wire             s_axis_nor_tlast,
+  input  wire             s_axis_nor_tvalid,
+  output wire             s_axis_nor_tready,
+  output wire [WIDTH-1:0] m_axis_nor_tdata,
+  output wire [0:0]       m_axis_nor_tdest,
+  output wire             m_axis_nor_tlast,
+  output wire             m_axis_nor_tvalid,
+  input  wire             m_axis_nor_tready,
+
+  // South inter-router connections
+  input  wire [WIDTH-1:0] s_axis_sou_tdata,
+  input  wire [0:0]       s_axis_sou_tdest,
+  input  wire             s_axis_sou_tlast,
+  input  wire             s_axis_sou_tvalid,
+  output wire             s_axis_sou_tready,
+  output wire [WIDTH-1:0] m_axis_sou_tdata,
+  output wire [0:0]       m_axis_sou_tdest,
+  output wire             m_axis_sou_tlast,
+  output wire             m_axis_sou_tvalid,
+  input  wire             m_axis_sou_tready
+);
+  // -------------------------------------------------
+  // Routing functions
+  // -------------------------------------------------
+
+  // mesh_node_mapping.vh file contains the mapping between the node number
+  // and its XY coordinates. It is autogenerated and defines the node_to_xdst
+  // and node_to_ydst functions.
+  `include "mesh_node_mapping.vh"
+
+  localparam [2:0] SW_DEST_TER  = 3'd0;
+  localparam [2:0] SW_DEST_WST  = 3'd1;
+  localparam [2:0] SW_DEST_EST  = 3'd2;
+  localparam [2:0] SW_DEST_NOR  = 3'd3;
+  localparam [2:0] SW_DEST_SOU  = 3'd4;
+  localparam [2:0] SW_NUM_DESTS = 3'd5;
+
+  // The compute_switch_tdest function is the destination selector
+  // i.e. it will inspecte the bottom $clog2(DIM_SIZE)*2 bits of the
+  // first word of a packet and determine the destination of the packet. 
+  function [3:0] compute_switch_tdest;
+    input [WIDTH-1:0] header;
+    input [3:0]       src;
+    reg [$clog2(DIM_SIZE)-1:0] xdst, ydst;
+    reg signed [$clog2(DIM_SIZE):0] xdiff, ydiff;
+  begin
+    xdst  = node_to_xdst(header);
+    ydst  = node_to_ydst(header);
+    xdiff = xdst - XB_ADDR_X;
+    ydiff = ydst - XB_ADDR_Y;
+    // Routing logic
+    // - MSB is the VC, 3 LSBs are the router destination
+    // - VC in a mesh is always 0
+    if (xdiff == 'd0 && ydiff == 'd0) begin
+      // VC=0 because terminals don't have VCs
+      compute_switch_tdest = {1'b0, SW_DEST_TER};
+    end else if (xdiff == 'd0) begin
+      // VC=1 for CCW turns and VC=0 for everything else
+      if (ydiff < 0)
+        compute_switch_tdest = {(src == SW_DEST_WST), SW_DEST_NOR};
+      else
+        compute_switch_tdest = {(src == SW_DEST_EST), SW_DEST_SOU};
+    end else begin
+      // VC=0 because east-west paths don't have VCs
+      if (xdiff < 0)
+        compute_switch_tdest = {1'b0, SW_DEST_WST}; 
+      else
+        compute_switch_tdest = {1'b0, SW_DEST_EST};
+    end
+    if (xdst != 'hx && ydst != 'hx) begin
+      if (XB_ADDR_X == 0 && compute_switch_tdest == SW_DEST_WST)
+        $display("Illegal route chosen: WEST. xdst=%d, ydst=%d, xaddr=%d, yaddr=%d", xdst, ydst, XB_ADDR_X, XB_ADDR_Y);
+      if (XB_ADDR_X == DIM_SIZE-1 && compute_switch_tdest == SW_DEST_EST)
+        $display("Illegal route chosen: EAST. xdst=%d, ydst=%d, xaddr=%d, yaddr=%d", xdst, ydst, XB_ADDR_X, XB_ADDR_Y);
+      if (XB_ADDR_Y == 0 && compute_switch_tdest == SW_DEST_NOR)
+        $display("Illegal route chosen: NORTH. xdst=%d, ydst=%d, xaddr=%d, yaddr=%d", xdst, ydst, XB_ADDR_X, XB_ADDR_Y);
+      if (XB_ADDR_Y == DIM_SIZE-1 && compute_switch_tdest == SW_DEST_SOU)
+        $display("Illegal route chosen: SOUTH. xdst=%d, ydst=%d, xaddr=%d, yaddr=%d", xdst, ydst, XB_ADDR_X, XB_ADDR_Y);
+    end
+    //$display("xdst=%d, ydst=%d, xaddr=%d, yaddr=%d, dst=%d", xdst, ydst, XB_ADDR_X, XB_ADDR_Y, compute_switch_tdest);
+  end
+  endfunction
+
+  // The compute_switch_alloc function is the switch allocation function 
+  // i.e. it chooses which input port reserves the switch for packet transfer.
+  // After the switch is allocated, all other ports will be backpressured until
+  // the packet finishes transferring.
+  function [2:0] compute_switch_alloc;
+    input [4:0] pkt_waiting;
+    input [2:0] last_alloc;
+  begin
+    if (pkt_waiting == 5'b00000) begin
+      compute_switch_alloc = SW_DEST_TER;
+    end else if (pkt_waiting == 5'b00001) begin
+      compute_switch_alloc = SW_DEST_TER;
+    end else if (pkt_waiting == 5'b00010) begin
+      compute_switch_alloc = SW_DEST_WST;
+    end else if (pkt_waiting == 5'b00100) begin
+      compute_switch_alloc = SW_DEST_EST;
+    end else if (pkt_waiting == 5'b01000) begin
+      compute_switch_alloc = SW_DEST_NOR;
+    end else if (pkt_waiting == 5'b10000) begin
+      compute_switch_alloc = SW_DEST_SOU;
+    end else begin
+      if (SWITCH_ALLOC == "PRIO") begin
+        // Priority: South > East > North > West > Term
+        if (pkt_waiting[SW_DEST_SOU])
+          compute_switch_alloc = SW_DEST_SOU;
+        else if (pkt_waiting[SW_DEST_EST])
+          compute_switch_alloc = SW_DEST_EST;
+        else if (pkt_waiting[SW_DEST_NOR])
+          compute_switch_alloc = SW_DEST_NOR;
+        else if (pkt_waiting[SW_DEST_WST])
+          compute_switch_alloc = SW_DEST_WST;
+        else
+          compute_switch_alloc = SW_DEST_TER;
+      end else begin
+        // Round-robin
+        if (pkt_waiting[(last_alloc + 3'd1) % SW_NUM_DESTS])
+          compute_switch_alloc = (last_alloc + 3'd1) % SW_NUM_DESTS;
+        else if (pkt_waiting[(last_alloc + 3'd2) % SW_NUM_DESTS])
+          compute_switch_alloc = (last_alloc + 3'd2) % SW_NUM_DESTS;
+        else if (pkt_waiting[(last_alloc + 3'd3) % SW_NUM_DESTS])
+          compute_switch_alloc = (last_alloc + 3'd3) % SW_NUM_DESTS;
+        else if (pkt_waiting[(last_alloc + 3'd4) % SW_NUM_DESTS])
+          compute_switch_alloc = (last_alloc + 3'd4) % SW_NUM_DESTS;
+        else
+          compute_switch_alloc = last_alloc;
+      end
+    end
+    //$display("pkt_waiting=%b, alloc=%d, last_alloc=%d", pkt_waiting, compute_switch_alloc, last_alloc);
+  end
+  endfunction
+
+  // -------------------------------------------------
+  // Input buffers
+  // -------------------------------------------------
+  wire [WIDTH-1:0] ter_i_tdata;
+  wire [3:0]       ter_i_tdest;
+  wire             ter_i_tlast;
+  wire             ter_i_tvalid;
+  wire             ter_i_tready;
+
+  // Data coming in from the terminal is gated until a full packet arrives
+  // in order to minimize the switch allocation time per packet.
+  axi_packet_gate #(
+    .WIDTH(WIDTH), .SIZE(TERM_BUFF_SIZE)
+  ) term_in_pkt_gate_i (
+    .clk      (clk), 
+    .reset    (reset), 
+    .clear    (1'b0),
+    .i_tdata  (s_axis_ter_tdata),
+    .i_tlast  (s_axis_ter_tlast),
+    .i_tvalid (s_axis_ter_tvalid),
+    .i_tready (s_axis_ter_tready),
+    .i_terror (1'b0),
+    .o_tdata  (ter_i_tdata),
+    .o_tlast  (ter_i_tlast),
+    .o_tvalid (ter_i_tvalid),
+    .o_tready (ter_i_tready)
+  );
+  assign ter_i_tdest = compute_switch_tdest(ter_i_tdata, SW_DEST_TER);
+
+  wire [WIDTH-1:0] wst_i_tdata,  est_i_tdata,  nor_i_tdata,  sou_i_tdata;
+  wire [3:0]       wst_i_tdest,  est_i_tdest,  nor_i_tdest,  sou_i_tdest;
+  wire             wst_i_tlast,  est_i_tlast,  nor_i_tlast,  sou_i_tlast;
+  wire             wst_i_tvalid, est_i_tvalid, nor_i_tvalid, sou_i_tvalid;
+  wire             wst_i_tready, est_i_tready, nor_i_tready, sou_i_tready;
+
+  axis_ingress_vc_buff #(
+    .WIDTH(WIDTH), .NUM_VCS(1),
+    .SIZE(XB_BUFF_SIZE),
+    .ROUTING(ROUTING_ALLOC)
+  ) wst_in_vc_buf_i (
+    .clk           (clk), 
+    .reset         (reset), 
+    .s_axis_tdata  (s_axis_wst_tdata),
+    .s_axis_tdest  (s_axis_wst_tdest),
+    .s_axis_tlast  (s_axis_wst_tlast),
+    .s_axis_tvalid (s_axis_wst_tvalid),
+    .s_axis_tready (s_axis_wst_tready),
+    .m_axis_tdata  (wst_i_tdata),
+    .m_axis_tlast  (wst_i_tlast),
+    .m_axis_tvalid (wst_i_tvalid),
+    .m_axis_tready (wst_i_tready)
+  );
+  assign wst_i_tdest = compute_switch_tdest(wst_i_tdata, SW_DEST_WST);
+
+  axis_ingress_vc_buff #(
+    .WIDTH(WIDTH), .NUM_VCS(1),
+    .SIZE(XB_BUFF_SIZE),
+    .ROUTING(ROUTING_ALLOC)
+  ) est_in_vc_buf_i (
+    .clk           (clk), 
+    .reset         (reset), 
+    .s_axis_tdata  (s_axis_est_tdata),
+    .s_axis_tdest  (s_axis_est_tdest),
+    .s_axis_tlast  (s_axis_est_tlast),
+    .s_axis_tvalid (s_axis_est_tvalid),
+    .s_axis_tready (s_axis_est_tready),
+    .m_axis_tdata  (est_i_tdata),
+    .m_axis_tlast  (est_i_tlast),
+    .m_axis_tvalid (est_i_tvalid),
+    .m_axis_tready (est_i_tready)
+  );
+  assign est_i_tdest = compute_switch_tdest(est_i_tdata, SW_DEST_EST);
+
+  axis_ingress_vc_buff #(
+    .WIDTH(WIDTH), .NUM_VCS(2), // Only north-south traffic has VCs
+    .SIZE(XB_BUFF_SIZE),
+    .ROUTING(ROUTING_ALLOC)
+  ) nor_in_vc_buf_i (
+    .clk           (clk), 
+    .reset         (reset), 
+    .s_axis_tdata  (s_axis_nor_tdata),
+    .s_axis_tdest  (s_axis_nor_tdest),
+    .s_axis_tlast  (s_axis_nor_tlast),
+    .s_axis_tvalid (s_axis_nor_tvalid),
+    .s_axis_tready (s_axis_nor_tready),
+    .m_axis_tdata  (nor_i_tdata),
+    .m_axis_tlast  (nor_i_tlast),
+    .m_axis_tvalid (nor_i_tvalid),
+    .m_axis_tready (nor_i_tready)
+  );
+  assign nor_i_tdest = compute_switch_tdest(nor_i_tdata, SW_DEST_NOR);
+
+  axis_ingress_vc_buff #(
+    .WIDTH(WIDTH), .NUM_VCS(2), // Only north-south traffic has VCs
+    .SIZE(XB_BUFF_SIZE),
+    .ROUTING(ROUTING_ALLOC)
+  ) sou_in_vc_buf_i (
+    .clk           (clk), 
+    .reset         (reset), 
+    .s_axis_tdata  (s_axis_sou_tdata),
+    .s_axis_tdest  (s_axis_sou_tdest),
+    .s_axis_tlast  (s_axis_sou_tlast),
+    .s_axis_tvalid (s_axis_sou_tvalid),
+    .s_axis_tready (s_axis_sou_tready),
+    .m_axis_tdata  (sou_i_tdata),
+    .m_axis_tlast  (sou_i_tlast),
+    .m_axis_tvalid (sou_i_tvalid),
+    .m_axis_tready (sou_i_tready)
+  );
+  assign sou_i_tdest = compute_switch_tdest(sou_i_tdata, SW_DEST_SOU);
+
+  //-------------------------------------------------
+  // Switch
+  //-------------------------------------------------
+  // Track the input packet state
+  localparam [0:0] PKT_ST_HEAD = 1'b0;
+  localparam [0:0] PKT_ST_BODY = 1'b1;
+  reg [0:0] pkt_state = PKT_ST_HEAD;
+
+  // The switch only accept packets on a single port at a time.
+  wire sw_in_ready = |({sou_i_tready, nor_i_tready, est_i_tready, wst_i_tready, ter_i_tready});
+  wire sw_in_valid = |({sou_i_tvalid, nor_i_tvalid, est_i_tvalid, wst_i_tvalid, ter_i_tvalid});
+  wire sw_in_last  = |({sou_i_tlast & sou_i_tvalid, nor_i_tlast & nor_i_tvalid,
+                        est_i_tlast & est_i_tvalid, wst_i_tlast & wst_i_tvalid,
+                        ter_i_tlast & ter_i_tvalid});
+
+  always @(posedge clk) begin
+    if (reset) begin
+      pkt_state <= PKT_ST_HEAD;
+    end else if (sw_in_valid & sw_in_ready) begin
+      pkt_state <= sw_in_last ? PKT_ST_HEAD : PKT_ST_BODY;
+    end
+  end
+
+  // The switch requires the allocation to stay valid until the
+  // end of the packet. We also might need to keep the previous
+  // packet's allocation to compute the current one
+  wire [2:0] switch_alloc;
+  reg  [2:0] prev_switch_alloc = SW_DEST_TER;
+  reg  [2:0] pkt_switch_alloc  = SW_DEST_TER;
+
+  always @(posedge clk) begin
+    if (reset) begin
+      prev_switch_alloc <= SW_DEST_TER;
+      pkt_switch_alloc <= SW_DEST_TER;
+    end else if (sw_in_valid & sw_in_ready) begin
+      if (pkt_state == PKT_ST_HEAD)
+        pkt_switch_alloc <= switch_alloc;
+      if (sw_in_last)
+        prev_switch_alloc <= switch_alloc;
+    end
+  end
+
+  assign switch_alloc = (sw_in_valid && pkt_state == PKT_ST_HEAD) ? 
+    compute_switch_alloc({sou_i_tvalid, nor_i_tvalid, est_i_tvalid, wst_i_tvalid, ter_i_tvalid}, prev_switch_alloc) :
+    pkt_switch_alloc;
+
+  wire ter_tdest_discard;
+  axis_switch #(
+    .DATA_W(WIDTH), .DEST_W(1), .IN_PORTS(5), .OUT_PORTS(5)
+  ) switch_i (
+    .clk           (clk),
+    .reset         (reset),
+    .s_axis_tdata  ({sou_i_tdata , nor_i_tdata , est_i_tdata , wst_i_tdata , ter_i_tdata }),
+    .s_axis_tdest  ({sou_i_tdest , nor_i_tdest , est_i_tdest , wst_i_tdest , ter_i_tdest }), 
+    .s_axis_tlast  ({sou_i_tlast , nor_i_tlast , est_i_tlast , wst_i_tlast , ter_i_tlast }),
+    .s_axis_tvalid ({sou_i_tvalid, nor_i_tvalid, est_i_tvalid, wst_i_tvalid, ter_i_tvalid}),
+    .s_axis_tready ({sou_i_tready, nor_i_tready, est_i_tready, wst_i_tready, ter_i_tready}),
+    .s_axis_alloc  (switch_alloc),
+    .m_axis_tdata  ({m_axis_sou_tdata,  m_axis_nor_tdata,  m_axis_est_tdata,  m_axis_wst_tdata,  m_axis_ter_tdata }),
+    .m_axis_tdest  ({m_axis_sou_tdest,  m_axis_nor_tdest,  m_axis_est_tdest,  m_axis_wst_tdest,  ter_tdest_discard}),
+    .m_axis_tlast  ({m_axis_sou_tlast,  m_axis_nor_tlast,  m_axis_est_tlast,  m_axis_wst_tlast,  m_axis_ter_tlast }),
+    .m_axis_tvalid ({m_axis_sou_tvalid, m_axis_nor_tvalid, m_axis_est_tvalid, m_axis_wst_tvalid, m_axis_ter_tvalid}),
+    .m_axis_tready ({m_axis_sou_tready, m_axis_nor_tready, m_axis_est_tready, m_axis_wst_tready, m_axis_ter_tready})
+  );
+
+
+endmodule
+
diff --git a/fpga/usrp3/lib/rfnoc/crossbar/mesh_node_mapping.vh b/fpga/usrp3/lib/rfnoc/crossbar/mesh_node_mapping.vh
new file mode 100644
index 000000000..466b0c615
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/crossbar/mesh_node_mapping.vh
@@ -0,0 +1,294 @@
+// Copyright 2018 Ettus Research, A National Instruments Company
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Autogenerated file. Do not modify.
+// $ ./gen_node_to_coord_mapping.py --dimsize 16 --pattern spiral
+
+parameter CLOG2_DIM_SIZE = $clog2(DIM_SIZE); //Vivado workaround
+
+
+// DIM_SIZE = 2, PATTERN = SPIRAL
+//------------------------------------
+//     0    1
+//     3    2
+localparam [3:0] XCOORD_DIM_002 = {1'd0,1'd1,1'd1,1'd0};
+localparam [3:0] YCOORD_DIM_002 = {1'd1,1'd1,1'd0,1'd0};
+
+// DIM_SIZE = 3, PATTERN = SPIRAL
+//------------------------------------
+//     6    7    8
+//     5    0    1
+//     4    3    2
+localparam [17:0] XCOORD_DIM_003 = {2'd2,2'd1,2'd0,2'd0,2'd0,2'd1,2'd2,2'd2,2'd1};
+localparam [17:0] YCOORD_DIM_003 = {2'd0,2'd0,2'd0,2'd1,2'd2,2'd2,2'd2,2'd1,2'd1};
+
+// DIM_SIZE = 4, PATTERN = SPIRAL
+//------------------------------------
+//     6    7    8    9
+//     5    0    1   10
+//     4    3    2   11
+//    15   14   13   12
+localparam [31:0] XCOORD_DIM_004 = {2'd0,2'd1,2'd2,2'd3,2'd3,2'd3,2'd3,2'd2,2'd1,2'd0,2'd0,2'd0,2'd1,2'd2,2'd2,2'd1};
+localparam [31:0] YCOORD_DIM_004 = {2'd3,2'd3,2'd3,2'd3,2'd2,2'd1,2'd0,2'd0,2'd0,2'd0,2'd1,2'd2,2'd2,2'd2,2'd1,2'd1};
+
+// DIM_SIZE = 5, PATTERN = SPIRAL
+//------------------------------------
+//    20   21   22   23   24
+//    19    6    7    8    9
+//    18    5    0    1   10
+//    17    4    3    2   11
+//    16   15   14   13   12
+localparam [74:0] XCOORD_DIM_005 = {3'd4,3'd3,3'd2,3'd1,3'd0,3'd0,3'd0,3'd0,3'd0,3'd1,3'd2,3'd3,3'd4,3'd4,3'd4,3'd4,3'd3,3'd2,3'd1,3'd1,3'd1,3'd2,3'd3,3'd3,3'd2};
+localparam [74:0] YCOORD_DIM_005 = {3'd0,3'd0,3'd0,3'd0,3'd0,3'd1,3'd2,3'd3,3'd4,3'd4,3'd4,3'd4,3'd4,3'd3,3'd2,3'd1,3'd1,3'd1,3'd1,3'd2,3'd3,3'd3,3'd3,3'd2,3'd2};
+
+// DIM_SIZE = 6, PATTERN = SPIRAL
+//------------------------------------
+//    20   21   22   23   24   25
+//    19    6    7    8    9   26
+//    18    5    0    1   10   27
+//    17    4    3    2   11   28
+//    16   15   14   13   12   29
+//    35   34   33   32   31   30
+localparam [107:0] XCOORD_DIM_006 = {3'd0,3'd1,3'd2,3'd3,3'd4,3'd5,3'd5,3'd5,3'd5,3'd5,3'd5,3'd4,3'd3,3'd2,3'd1,3'd0,3'd0,3'd0,3'd0,3'd0,3'd1,3'd2,3'd3,3'd4,3'd4,3'd4,3'd4,3'd3,3'd2,3'd1,3'd1,3'd1,3'd2,3'd3,3'd3,3'd2};
+localparam [107:0] YCOORD_DIM_006 = {3'd5,3'd5,3'd5,3'd5,3'd5,3'd5,3'd4,3'd3,3'd2,3'd1,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd1,3'd2,3'd3,3'd4,3'd4,3'd4,3'd4,3'd4,3'd3,3'd2,3'd1,3'd1,3'd1,3'd1,3'd2,3'd3,3'd3,3'd3,3'd2,3'd2};
+
+// DIM_SIZE = 7, PATTERN = SPIRAL
+//------------------------------------
+//    42   43   44   45   46   47   48
+//    41   20   21   22   23   24   25
+//    40   19    6    7    8    9   26
+//    39   18    5    0    1   10   27
+//    38   17    4    3    2   11   28
+//    37   16   15   14   13   12   29
+//    36   35   34   33   32   31   30
+localparam [146:0] XCOORD_DIM_007 = {3'd6,3'd5,3'd4,3'd3,3'd2,3'd1,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd1,3'd2,3'd3,3'd4,3'd5,3'd6,3'd6,3'd6,3'd6,3'd6,3'd6,3'd5,3'd4,3'd3,3'd2,3'd1,3'd1,3'd1,3'd1,3'd1,3'd2,3'd3,3'd4,3'd5,3'd5,3'd5,3'd5,3'd4,3'd3,3'd2,3'd2,3'd2,3'd3,3'd4,3'd4,3'd3};
+localparam [146:0] YCOORD_DIM_007 = {3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd1,3'd2,3'd3,3'd4,3'd5,3'd6,3'd6,3'd6,3'd6,3'd6,3'd6,3'd6,3'd5,3'd4,3'd3,3'd2,3'd1,3'd1,3'd1,3'd1,3'd1,3'd1,3'd2,3'd3,3'd4,3'd5,3'd5,3'd5,3'd5,3'd5,3'd4,3'd3,3'd2,3'd2,3'd2,3'd2,3'd3,3'd4,3'd4,3'd4,3'd3,3'd3};
+
+// DIM_SIZE = 8, PATTERN = SPIRAL
+//------------------------------------
+//    42   43   44   45   46   47   48   49
+//    41   20   21   22   23   24   25   50
+//    40   19    6    7    8    9   26   51
+//    39   18    5    0    1   10   27   52
+//    38   17    4    3    2   11   28   53
+//    37   16   15   14   13   12   29   54
+//    36   35   34   33   32   31   30   55
+//    63   62   61   60   59   58   57   56
+localparam [191:0] XCOORD_DIM_008 = {3'd0,3'd1,3'd2,3'd3,3'd4,3'd5,3'd6,3'd7,3'd7,3'd7,3'd7,3'd7,3'd7,3'd7,3'd7,3'd6,3'd5,3'd4,3'd3,3'd2,3'd1,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd1,3'd2,3'd3,3'd4,3'd5,3'd6,3'd6,3'd6,3'd6,3'd6,3'd6,3'd5,3'd4,3'd3,3'd2,3'd1,3'd1,3'd1,3'd1,3'd1,3'd2,3'd3,3'd4,3'd5,3'd5,3'd5,3'd5,3'd4,3'd3,3'd2,3'd2,3'd2,3'd3,3'd4,3'd4,3'd3};
+localparam [191:0] YCOORD_DIM_008 = {3'd7,3'd7,3'd7,3'd7,3'd7,3'd7,3'd7,3'd7,3'd6,3'd5,3'd4,3'd3,3'd2,3'd1,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd1,3'd2,3'd3,3'd4,3'd5,3'd6,3'd6,3'd6,3'd6,3'd6,3'd6,3'd6,3'd5,3'd4,3'd3,3'd2,3'd1,3'd1,3'd1,3'd1,3'd1,3'd1,3'd2,3'd3,3'd4,3'd5,3'd5,3'd5,3'd5,3'd5,3'd4,3'd3,3'd2,3'd2,3'd2,3'd2,3'd3,3'd4,3'd4,3'd4,3'd3,3'd3};
+
+// DIM_SIZE = 9, PATTERN = SPIRAL
+//------------------------------------
+//    72   73   74   75   76   77   78   79   80
+//    71   42   43   44   45   46   47   48   49
+//    70   41   20   21   22   23   24   25   50
+//    69   40   19    6    7    8    9   26   51
+//    68   39   18    5    0    1   10   27   52
+//    67   38   17    4    3    2   11   28   53
+//    66   37   16   15   14   13   12   29   54
+//    65   36   35   34   33   32   31   30   55
+//    64   63   62   61   60   59   58   57   56
+localparam [323:0] XCOORD_DIM_009 = {4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd2,4'd1,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd1,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd8,4'd8,4'd8,4'd8,4'd8,4'd8,4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd2,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd7,4'd7,4'd7,4'd7,4'd7,4'd6,4'd5,4'd4,4'd3,4'd2,4'd2,4'd2,4'd2,4'd2,4'd3,4'd4,4'd5,4'd6,4'd6,4'd6,4'd6,4'd5,4'd4,4'd3,4'd3,4'd3,4'd4,4'd5,4'd5,4'd4};
+localparam [323:0] YCOORD_DIM_009 = {4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd1,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd8,4'd8,4'd8,4'd8,4'd8,4'd8,4'd8,4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd2,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd7,4'd7,4'd7,4'd7,4'd7,4'd7,4'd6,4'd5,4'd4,4'd3,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd3,4'd4,4'd5,4'd6,4'd6,4'd6,4'd6,4'd6,4'd5,4'd4,4'd3,4'd3,4'd3,4'd3,4'd4,4'd5,4'd5,4'd5,4'd4,4'd4};
+
+// DIM_SIZE = 10, PATTERN = SPIRAL
+//------------------------------------
+//    72   73   74   75   76   77   78   79   80   81
+//    71   42   43   44   45   46   47   48   49   82
+//    70   41   20   21   22   23   24   25   50   83
+//    69   40   19    6    7    8    9   26   51   84
+//    68   39   18    5    0    1   10   27   52   85
+//    67   38   17    4    3    2   11   28   53   86
+//    66   37   16   15   14   13   12   29   54   87
+//    65   36   35   34   33   32   31   30   55   88
+//    64   63   62   61   60   59   58   57   56   89
+//    99   98   97   96   95   94   93   92   91   90
+localparam [399:0] XCOORD_DIM_010 = {4'd0,4'd1,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9,4'd9,4'd9,4'd9,4'd9,4'd9,4'd9,4'd9,4'd9,4'd9,4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd2,4'd1,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd1,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd8,4'd8,4'd8,4'd8,4'd8,4'd8,4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd2,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd7,4'd7,4'd7,4'd7,4'd7,4'd6,4'd5,4'd4,4'd3,4'd2,4'd2,4'd2,4'd2,4'd2,4'd3,4'd4,4'd5,4'd6,4'd6,4'd6,4'd6,4'd5,4'd4,4'd3,4'd3,4'd3,4'd4,4'd5,4'd5,4'd4};
+localparam [399:0] YCOORD_DIM_010 = {4'd9,4'd9,4'd9,4'd9,4'd9,4'd9,4'd9,4'd9,4'd9,4'd9,4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd2,4'd1,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd1,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd8,4'd8,4'd8,4'd8,4'd8,4'd8,4'd8,4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd2,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd7,4'd7,4'd7,4'd7,4'd7,4'd7,4'd6,4'd5,4'd4,4'd3,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd3,4'd4,4'd5,4'd6,4'd6,4'd6,4'd6,4'd6,4'd5,4'd4,4'd3,4'd3,4'd3,4'd3,4'd4,4'd5,4'd5,4'd5,4'd4,4'd4};
+
+// DIM_SIZE = 11, PATTERN = SPIRAL
+//------------------------------------
+//   110  111  112  113  114  115  116  117  118  119  120
+//   109   72   73   74   75   76   77   78   79   80   81
+//   108   71   42   43   44   45   46   47   48   49   82
+//   107   70   41   20   21   22   23   24   25   50   83
+//   106   69   40   19    6    7    8    9   26   51   84
+//   105   68   39   18    5    0    1   10   27   52   85
+//   104   67   38   17    4    3    2   11   28   53   86
+//   103   66   37   16   15   14   13   12   29   54   87
+//   102   65   36   35   34   33   32   31   30   55   88
+//   101   64   63   62   61   60   59   58   57   56   89
+//   100   99   98   97   96   95   94   93   92   91   90
+localparam [483:0] XCOORD_DIM_011 = {4'd10,4'd9,4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd2,4'd1,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd1,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9,4'd10,4'd10,4'd10,4'd10,4'd10,4'd10,4'd10,4'd10,4'd10,4'd10,4'd9,4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd2,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9,4'd9,4'd9,4'd9,4'd9,4'd9,4'd9,4'd9,4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd8,4'd8,4'd8,4'd8,4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd3,4'd3,4'd3,4'd3,4'd4,4'd5,4'd6,4'd7,4'd7,4'd7,4'd7,4'd6,4'd5,4'd4,4'd4,4'd4,4'd5,4'd6,4'd6,4'd5};
+localparam [483:0] YCOORD_DIM_011 = {4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd1,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9,4'd10,4'd10,4'd10,4'd10,4'd10,4'd10,4'd10,4'd10,4'd10,4'd10,4'd10,4'd9,4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd2,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9,4'd9,4'd9,4'd9,4'd9,4'd9,4'd9,4'd9,4'd9,4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd8,4'd8,4'd8,4'd8,4'd8,4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd3,4'd3,4'd3,4'd3,4'd3,4'd4,4'd5,4'd6,4'd7,4'd7,4'd7,4'd7,4'd7,4'd6,4'd5,4'd4,4'd4,4'd4,4'd4,4'd5,4'd6,4'd6,4'd6,4'd5,4'd5};
+
+// DIM_SIZE = 12, PATTERN = SPIRAL
+//------------------------------------
+//   110  111  112  113  114  115  116  117  118  119  120  121
+//   109   72   73   74   75   76   77   78   79   80   81  122
+//   108   71   42   43   44   45   46   47   48   49   82  123
+//   107   70   41   20   21   22   23   24   25   50   83  124
+//   106   69   40   19    6    7    8    9   26   51   84  125
+//   105   68   39   18    5    0    1   10   27   52   85  126
+//   104   67   38   17    4    3    2   11   28   53   86  127
+//   103   66   37   16   15   14   13   12   29   54   87  128
+//   102   65   36   35   34   33   32   31   30   55   88  129
+//   101   64   63   62   61   60   59   58   57   56   89  130
+//   100   99   98   97   96   95   94   93   92   91   90  131
+//   143  142  141  140  139  138  137  136  135  134  133  132
+localparam [575:0] XCOORD_DIM_012 = {4'd0,4'd1,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9,4'd10,4'd11,4'd11,4'd11,4'd11,4'd11,4'd11,4'd11,4'd11,4'd11,4'd11,4'd11,4'd11,4'd10,4'd9,4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd2,4'd1,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd1,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9,4'd10,4'd10,4'd10,4'd10,4'd10,4'd10,4'd10,4'd10,4'd10,4'd10,4'd9,4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd2,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9,4'd9,4'd9,4'd9,4'd9,4'd9,4'd9,4'd9,4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd8,4'd8,4'd8,4'd8,4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd3,4'd3,4'd3,4'd3,4'd4,4'd5,4'd6,4'd7,4'd7,4'd7,4'd7,4'd6,4'd5,4'd4,4'd4,4'd4,4'd5,4'd6,4'd6,4'd5};
+localparam [575:0] YCOORD_DIM_012 = {4'd11,4'd11,4'd11,4'd11,4'd11,4'd11,4'd11,4'd11,4'd11,4'd11,4'd11,4'd11,4'd10,4'd9,4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd2,4'd1,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd1,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9,4'd10,4'd10,4'd10,4'd10,4'd10,4'd10,4'd10,4'd10,4'd10,4'd10,4'd10,4'd9,4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd2,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9,4'd9,4'd9,4'd9,4'd9,4'd9,4'd9,4'd9,4'd9,4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd8,4'd8,4'd8,4'd8,4'd8,4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd3,4'd3,4'd3,4'd3,4'd3,4'd4,4'd5,4'd6,4'd7,4'd7,4'd7,4'd7,4'd7,4'd6,4'd5,4'd4,4'd4,4'd4,4'd4,4'd5,4'd6,4'd6,4'd6,4'd5,4'd5};
+
+// DIM_SIZE = 13, PATTERN = SPIRAL
+//------------------------------------
+//   156  157  158  159  160  161  162  163  164  165  166  167  168
+//   155  110  111  112  113  114  115  116  117  118  119  120  121
+//   154  109   72   73   74   75   76   77   78   79   80   81  122
+//   153  108   71   42   43   44   45   46   47   48   49   82  123
+//   152  107   70   41   20   21   22   23   24   25   50   83  124
+//   151  106   69   40   19    6    7    8    9   26   51   84  125
+//   150  105   68   39   18    5    0    1   10   27   52   85  126
+//   149  104   67   38   17    4    3    2   11   28   53   86  127
+//   148  103   66   37   16   15   14   13   12   29   54   87  128
+//   147  102   65   36   35   34   33   32   31   30   55   88  129
+//   146  101   64   63   62   61   60   59   58   57   56   89  130
+//   145  100   99   98   97   96   95   94   93   92   91   90  131
+//   144  143  142  141  140  139  138  137  136  135  134  133  132
+localparam [675:0] XCOORD_DIM_013 = {4'd12,4'd11,4'd10,4'd9,4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd2,4'd1,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd1,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9,4'd10,4'd11,4'd12,4'd12,4'd12,4'd12,4'd12,4'd12,4'd12,4'd12,4'd12,4'd12,4'd12,4'd12,4'd11,4'd10,4'd9,4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd2,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9,4'd10,4'd11,4'd11,4'd11,4'd11,4'd11,4'd11,4'd11,4'd11,4'd11,4'd11,4'd10,4'd9,4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9,4'd10,4'd10,4'd10,4'd10,4'd10,4'd10,4'd10,4'd10,4'd9,4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd3,4'd3,4'd3,4'd3,4'd3,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9,4'd9,4'd9,4'd9,4'd9,4'd9,4'd8,4'd7,4'd6,4'd5,4'd4,4'd4,4'd4,4'd4,4'd4,4'd5,4'd6,4'd7,4'd8,4'd8,4'd8,4'd8,4'd7,4'd6,4'd5,4'd5,4'd5,4'd6,4'd7,4'd7,4'd6};
+localparam [675:0] YCOORD_DIM_013 = {4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd1,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9,4'd10,4'd11,4'd12,4'd12,4'd12,4'd12,4'd12,4'd12,4'd12,4'd12,4'd12,4'd12,4'd12,4'd12,4'd12,4'd11,4'd10,4'd9,4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd2,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9,4'd10,4'd11,4'd11,4'd11,4'd11,4'd11,4'd11,4'd11,4'd11,4'd11,4'd11,4'd11,4'd10,4'd9,4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9,4'd10,4'd10,4'd10,4'd10,4'd10,4'd10,4'd10,4'd10,4'd10,4'd9,4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd3,4'd3,4'd3,4'd3,4'd3,4'd3,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9,4'd9,4'd9,4'd9,4'd9,4'd9,4'd9,4'd8,4'd7,4'd6,4'd5,4'd4,4'd4,4'd4,4'd4,4'd4,4'd4,4'd5,4'd6,4'd7,4'd8,4'd8,4'd8,4'd8,4'd8,4'd7,4'd6,4'd5,4'd5,4'd5,4'd5,4'd6,4'd7,4'd7,4'd7,4'd6,4'd6};
+
+// DIM_SIZE = 14, PATTERN = SPIRAL
+//------------------------------------
+//   156  157  158  159  160  161  162  163  164  165  166  167  168  169
+//   155  110  111  112  113  114  115  116  117  118  119  120  121  170
+//   154  109   72   73   74   75   76   77   78   79   80   81  122  171
+//   153  108   71   42   43   44   45   46   47   48   49   82  123  172
+//   152  107   70   41   20   21   22   23   24   25   50   83  124  173
+//   151  106   69   40   19    6    7    8    9   26   51   84  125  174
+//   150  105   68   39   18    5    0    1   10   27   52   85  126  175
+//   149  104   67   38   17    4    3    2   11   28   53   86  127  176
+//   148  103   66   37   16   15   14   13   12   29   54   87  128  177
+//   147  102   65   36   35   34   33   32   31   30   55   88  129  178
+//   146  101   64   63   62   61   60   59   58   57   56   89  130  179
+//   145  100   99   98   97   96   95   94   93   92   91   90  131  180
+//   144  143  142  141  140  139  138  137  136  135  134  133  132  181
+//   195  194  193  192  191  190  189  188  187  186  185  184  183  182
+localparam [783:0] XCOORD_DIM_014 = {4'd0,4'd1,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9,4'd10,4'd11,4'd12,4'd13,4'd13,4'd13,4'd13,4'd13,4'd13,4'd13,4'd13,4'd13,4'd13,4'd13,4'd13,4'd13,4'd13,4'd12,4'd11,4'd10,4'd9,4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd2,4'd1,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd1,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9,4'd10,4'd11,4'd12,4'd12,4'd12,4'd12,4'd12,4'd12,4'd12,4'd12,4'd12,4'd12,4'd12,4'd12,4'd11,4'd10,4'd9,4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd2,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9,4'd10,4'd11,4'd11,4'd11,4'd11,4'd11,4'd11,4'd11,4'd11,4'd11,4'd11,4'd10,4'd9,4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9,4'd10,4'd10,4'd10,4'd10,4'd10,4'd10,4'd10,4'd10,4'd9,4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd3,4'd3,4'd3,4'd3,4'd3,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9,4'd9,4'd9,4'd9,4'd9,4'd9,4'd8,4'd7,4'd6,4'd5,4'd4,4'd4,4'd4,4'd4,4'd4,4'd5,4'd6,4'd7,4'd8,4'd8,4'd8,4'd8,4'd7,4'd6,4'd5,4'd5,4'd5,4'd6,4'd7,4'd7,4'd6};
+localparam [783:0] YCOORD_DIM_014 = {4'd13,4'd13,4'd13,4'd13,4'd13,4'd13,4'd13,4'd13,4'd13,4'd13,4'd13,4'd13,4'd13,4'd13,4'd12,4'd11,4'd10,4'd9,4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd2,4'd1,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd1,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9,4'd10,4'd11,4'd12,4'd12,4'd12,4'd12,4'd12,4'd12,4'd12,4'd12,4'd12,4'd12,4'd12,4'd12,4'd12,4'd11,4'd10,4'd9,4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd2,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9,4'd10,4'd11,4'd11,4'd11,4'd11,4'd11,4'd11,4'd11,4'd11,4'd11,4'd11,4'd11,4'd10,4'd9,4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9,4'd10,4'd10,4'd10,4'd10,4'd10,4'd10,4'd10,4'd10,4'd10,4'd9,4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd3,4'd3,4'd3,4'd3,4'd3,4'd3,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9,4'd9,4'd9,4'd9,4'd9,4'd9,4'd9,4'd8,4'd7,4'd6,4'd5,4'd4,4'd4,4'd4,4'd4,4'd4,4'd4,4'd5,4'd6,4'd7,4'd8,4'd8,4'd8,4'd8,4'd8,4'd7,4'd6,4'd5,4'd5,4'd5,4'd5,4'd6,4'd7,4'd7,4'd7,4'd6,4'd6};
+
+// DIM_SIZE = 15, PATTERN = SPIRAL
+//------------------------------------
+//   210  211  212  213  214  215  216  217  218  219  220  221  222  223  224
+//   209  156  157  158  159  160  161  162  163  164  165  166  167  168  169
+//   208  155  110  111  112  113  114  115  116  117  118  119  120  121  170
+//   207  154  109   72   73   74   75   76   77   78   79   80   81  122  171
+//   206  153  108   71   42   43   44   45   46   47   48   49   82  123  172
+//   205  152  107   70   41   20   21   22   23   24   25   50   83  124  173
+//   204  151  106   69   40   19    6    7    8    9   26   51   84  125  174
+//   203  150  105   68   39   18    5    0    1   10   27   52   85  126  175
+//   202  149  104   67   38   17    4    3    2   11   28   53   86  127  176
+//   201  148  103   66   37   16   15   14   13   12   29   54   87  128  177
+//   200  147  102   65   36   35   34   33   32   31   30   55   88  129  178
+//   199  146  101   64   63   62   61   60   59   58   57   56   89  130  179
+//   198  145  100   99   98   97   96   95   94   93   92   91   90  131  180
+//   197  144  143  142  141  140  139  138  137  136  135  134  133  132  181
+//   196  195  194  193  192  191  190  189  188  187  186  185  184  183  182
+localparam [899:0] XCOORD_DIM_015 = {4'd14,4'd13,4'd12,4'd11,4'd10,4'd9,4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd2,4'd1,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd1,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9,4'd10,4'd11,4'd12,4'd13,4'd14,4'd14,4'd14,4'd14,4'd14,4'd14,4'd14,4'd14,4'd14,4'd14,4'd14,4'd14,4'd14,4'd14,4'd13,4'd12,4'd11,4'd10,4'd9,4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd2,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9,4'd10,4'd11,4'd12,4'd13,4'd13,4'd13,4'd13,4'd13,4'd13,4'd13,4'd13,4'd13,4'd13,4'd13,4'd13,4'd12,4'd11,4'd10,4'd9,4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9,4'd10,4'd11,4'd12,4'd12,4'd12,4'd12,4'd12,4'd12,4'd12,4'd12,4'd12,4'd12,4'd11,4'd10,4'd9,4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd3,4'd3,4'd3,4'd3,4'd3,4'd3,4'd3,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9,4'd10,4'd11,4'd11,4'd11,4'd11,4'd11,4'd11,4'd11,4'd11,4'd10,4'd9,4'd8,4'd7,4'd6,4'd5,4'd4,4'd4,4'd4,4'd4,4'd4,4'd4,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9,4'd10,4'd10,4'd10,4'd10,4'd10,4'd10,4'd9,4'd8,4'd7,4'd6,4'd5,4'd5,4'd5,4'd5,4'd5,4'd6,4'd7,4'd8,4'd9,4'd9,4'd9,4'd9,4'd8,4'd7,4'd6,4'd6,4'd6,4'd7,4'd8,4'd8,4'd7};
+localparam [899:0] YCOORD_DIM_015 = {4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd1,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9,4'd10,4'd11,4'd12,4'd13,4'd14,4'd14,4'd14,4'd14,4'd14,4'd14,4'd14,4'd14,4'd14,4'd14,4'd14,4'd14,4'd14,4'd14,4'd14,4'd13,4'd12,4'd11,4'd10,4'd9,4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd2,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9,4'd10,4'd11,4'd12,4'd13,4'd13,4'd13,4'd13,4'd13,4'd13,4'd13,4'd13,4'd13,4'd13,4'd13,4'd13,4'd13,4'd12,4'd11,4'd10,4'd9,4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9,4'd10,4'd11,4'd12,4'd12,4'd12,4'd12,4'd12,4'd12,4'd12,4'd12,4'd12,4'd12,4'd12,4'd11,4'd10,4'd9,4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd3,4'd3,4'd3,4'd3,4'd3,4'd3,4'd3,4'd3,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9,4'd10,4'd11,4'd11,4'd11,4'd11,4'd11,4'd11,4'd11,4'd11,4'd11,4'd10,4'd9,4'd8,4'd7,4'd6,4'd5,4'd4,4'd4,4'd4,4'd4,4'd4,4'd4,4'd4,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9,4'd10,4'd10,4'd10,4'd10,4'd10,4'd10,4'd10,4'd9,4'd8,4'd7,4'd6,4'd5,4'd5,4'd5,4'd5,4'd5,4'd5,4'd6,4'd7,4'd8,4'd9,4'd9,4'd9,4'd9,4'd9,4'd8,4'd7,4'd6,4'd6,4'd6,4'd6,4'd7,4'd8,4'd8,4'd8,4'd7,4'd7};
+
+// DIM_SIZE = 16, PATTERN = SPIRAL
+//------------------------------------
+//   210  211  212  213  214  215  216  217  218  219  220  221  222  223  224  225
+//   209  156  157  158  159  160  161  162  163  164  165  166  167  168  169  226
+//   208  155  110  111  112  113  114  115  116  117  118  119  120  121  170  227
+//   207  154  109   72   73   74   75   76   77   78   79   80   81  122  171  228
+//   206  153  108   71   42   43   44   45   46   47   48   49   82  123  172  229
+//   205  152  107   70   41   20   21   22   23   24   25   50   83  124  173  230
+//   204  151  106   69   40   19    6    7    8    9   26   51   84  125  174  231
+//   203  150  105   68   39   18    5    0    1   10   27   52   85  126  175  232
+//   202  149  104   67   38   17    4    3    2   11   28   53   86  127  176  233
+//   201  148  103   66   37   16   15   14   13   12   29   54   87  128  177  234
+//   200  147  102   65   36   35   34   33   32   31   30   55   88  129  178  235
+//   199  146  101   64   63   62   61   60   59   58   57   56   89  130  179  236
+//   198  145  100   99   98   97   96   95   94   93   92   91   90  131  180  237
+//   197  144  143  142  141  140  139  138  137  136  135  134  133  132  181  238
+//   196  195  194  193  192  191  190  189  188  187  186  185  184  183  182  239
+//   255  254  253  252  251  250  249  248  247  246  245  244  243  242  241  240
+localparam [1023:0] XCOORD_DIM_016 = {4'd0,4'd1,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9,4'd10,4'd11,4'd12,4'd13,4'd14,4'd15,4'd15,4'd15,4'd15,4'd15,4'd15,4'd15,4'd15,4'd15,4'd15,4'd15,4'd15,4'd15,4'd15,4'd15,4'd15,4'd14,4'd13,4'd12,4'd11,4'd10,4'd9,4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd2,4'd1,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd1,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9,4'd10,4'd11,4'd12,4'd13,4'd14,4'd14,4'd14,4'd14,4'd14,4'd14,4'd14,4'd14,4'd14,4'd14,4'd14,4'd14,4'd14,4'd14,4'd13,4'd12,4'd11,4'd10,4'd9,4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd2,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9,4'd10,4'd11,4'd12,4'd13,4'd13,4'd13,4'd13,4'd13,4'd13,4'd13,4'd13,4'd13,4'd13,4'd13,4'd13,4'd12,4'd11,4'd10,4'd9,4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9,4'd10,4'd11,4'd12,4'd12,4'd12,4'd12,4'd12,4'd12,4'd12,4'd12,4'd12,4'd12,4'd11,4'd10,4'd9,4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd3,4'd3,4'd3,4'd3,4'd3,4'd3,4'd3,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9,4'd10,4'd11,4'd11,4'd11,4'd11,4'd11,4'd11,4'd11,4'd11,4'd10,4'd9,4'd8,4'd7,4'd6,4'd5,4'd4,4'd4,4'd4,4'd4,4'd4,4'd4,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9,4'd10,4'd10,4'd10,4'd10,4'd10,4'd10,4'd9,4'd8,4'd7,4'd6,4'd5,4'd5,4'd5,4'd5,4'd5,4'd6,4'd7,4'd8,4'd9,4'd9,4'd9,4'd9,4'd8,4'd7,4'd6,4'd6,4'd6,4'd7,4'd8,4'd8,4'd7};
+localparam [1023:0] YCOORD_DIM_016 = {4'd15,4'd15,4'd15,4'd15,4'd15,4'd15,4'd15,4'd15,4'd15,4'd15,4'd15,4'd15,4'd15,4'd15,4'd15,4'd15,4'd14,4'd13,4'd12,4'd11,4'd10,4'd9,4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd2,4'd1,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd0,4'd1,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9,4'd10,4'd11,4'd12,4'd13,4'd14,4'd14,4'd14,4'd14,4'd14,4'd14,4'd14,4'd14,4'd14,4'd14,4'd14,4'd14,4'd14,4'd14,4'd14,4'd13,4'd12,4'd11,4'd10,4'd9,4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd2,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd1,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9,4'd10,4'd11,4'd12,4'd13,4'd13,4'd13,4'd13,4'd13,4'd13,4'd13,4'd13,4'd13,4'd13,4'd13,4'd13,4'd13,4'd12,4'd11,4'd10,4'd9,4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9,4'd10,4'd11,4'd12,4'd12,4'd12,4'd12,4'd12,4'd12,4'd12,4'd12,4'd12,4'd12,4'd12,4'd11,4'd10,4'd9,4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd3,4'd3,4'd3,4'd3,4'd3,4'd3,4'd3,4'd3,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9,4'd10,4'd11,4'd11,4'd11,4'd11,4'd11,4'd11,4'd11,4'd11,4'd11,4'd10,4'd9,4'd8,4'd7,4'd6,4'd5,4'd4,4'd4,4'd4,4'd4,4'd4,4'd4,4'd4,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9,4'd10,4'd10,4'd10,4'd10,4'd10,4'd10,4'd10,4'd9,4'd8,4'd7,4'd6,4'd5,4'd5,4'd5,4'd5,4'd5,4'd5,4'd6,4'd7,4'd8,4'd9,4'd9,4'd9,4'd9,4'd9,4'd8,4'd7,4'd6,4'd6,4'd6,4'd6,4'd7,4'd8,4'd8,4'd8,4'd7,4'd7};
+
+
+function [CLOG2_DIM_SIZE-1:0] node_to_xdst;
+  input [WIDTH-1:0] header;
+begin
+  if (DIM_SIZE == 2)
+    node_to_xdst = XCOORD_DIM_002[1*header[1:0] +: 1];
+  else if (DIM_SIZE == 3)
+    node_to_xdst = XCOORD_DIM_003[2*header[3:0] +: 2];
+  else if (DIM_SIZE == 4)
+    node_to_xdst = XCOORD_DIM_004[2*header[3:0] +: 2];
+  else if (DIM_SIZE == 5)
+    node_to_xdst = XCOORD_DIM_005[3*header[4:0] +: 3];
+  else if (DIM_SIZE == 6)
+    node_to_xdst = XCOORD_DIM_006[3*header[5:0] +: 3];
+  else if (DIM_SIZE == 7)
+    node_to_xdst = XCOORD_DIM_007[3*header[5:0] +: 3];
+  else if (DIM_SIZE == 8)
+    node_to_xdst = XCOORD_DIM_008[3*header[5:0] +: 3];
+  else if (DIM_SIZE == 9)
+    node_to_xdst = XCOORD_DIM_009[4*header[6:0] +: 4];
+  else if (DIM_SIZE == 10)
+    node_to_xdst = XCOORD_DIM_010[4*header[6:0] +: 4];
+  else if (DIM_SIZE == 11)
+    node_to_xdst = XCOORD_DIM_011[4*header[6:0] +: 4];
+  else if (DIM_SIZE == 12)
+    node_to_xdst = XCOORD_DIM_012[4*header[7:0] +: 4];
+  else if (DIM_SIZE == 13)
+    node_to_xdst = XCOORD_DIM_013[4*header[7:0] +: 4];
+  else if (DIM_SIZE == 14)
+    node_to_xdst = XCOORD_DIM_014[4*header[7:0] +: 4];
+  else if (DIM_SIZE == 15)
+    node_to_xdst = XCOORD_DIM_015[4*header[7:0] +: 4];
+  else if (DIM_SIZE == 16)
+    node_to_xdst = XCOORD_DIM_016[4*header[7:0] +: 4];
+  else
+    node_to_xdst = {CLOG2_DIM_SIZE{1'd0}};
+end endfunction
+
+function [CLOG2_DIM_SIZE-1:0] node_to_ydst;
+  input [WIDTH-1:0] header;
+begin
+  if (DIM_SIZE == 2)
+    node_to_ydst = YCOORD_DIM_002[1*header[1:0] +: 1];
+  else if (DIM_SIZE == 3)
+    node_to_ydst = YCOORD_DIM_003[2*header[3:0] +: 2];
+  else if (DIM_SIZE == 4)
+    node_to_ydst = YCOORD_DIM_004[2*header[3:0] +: 2];
+  else if (DIM_SIZE == 5)
+    node_to_ydst = YCOORD_DIM_005[3*header[4:0] +: 3];
+  else if (DIM_SIZE == 6)
+    node_to_ydst = YCOORD_DIM_006[3*header[5:0] +: 3];
+  else if (DIM_SIZE == 7)
+    node_to_ydst = YCOORD_DIM_007[3*header[5:0] +: 3];
+  else if (DIM_SIZE == 8)
+    node_to_ydst = YCOORD_DIM_008[3*header[5:0] +: 3];
+  else if (DIM_SIZE == 9)
+    node_to_ydst = YCOORD_DIM_009[4*header[6:0] +: 4];
+  else if (DIM_SIZE == 10)
+    node_to_ydst = YCOORD_DIM_010[4*header[6:0] +: 4];
+  else if (DIM_SIZE == 11)
+    node_to_ydst = YCOORD_DIM_011[4*header[6:0] +: 4];
+  else if (DIM_SIZE == 12)
+    node_to_ydst = YCOORD_DIM_012[4*header[7:0] +: 4];
+  else if (DIM_SIZE == 13)
+    node_to_ydst = YCOORD_DIM_013[4*header[7:0] +: 4];
+  else if (DIM_SIZE == 14)
+    node_to_ydst = YCOORD_DIM_014[4*header[7:0] +: 4];
+  else if (DIM_SIZE == 15)
+    node_to_ydst = YCOORD_DIM_015[4*header[7:0] +: 4];
+  else if (DIM_SIZE == 16)
+    node_to_ydst = YCOORD_DIM_016[4*header[7:0] +: 4];
+  else
+    node_to_ydst = {CLOG2_DIM_SIZE{1'd0}};
+end endfunction
+
diff --git a/fpga/usrp3/lib/rfnoc/crossbar/synth/axis_ctrl_crossbar_nxn_top.tcl b/fpga/usrp3/lib/rfnoc/crossbar/synth/axis_ctrl_crossbar_nxn_top.tcl
new file mode 100644
index 000000000..39440b512
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/crossbar/synth/axis_ctrl_crossbar_nxn_top.tcl
@@ -0,0 +1,18 @@
+#!/usr/bin/python3
+#
+# Copyright 2018 Ettus Research, a National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+create_project tmp_proj -part xc7k410tffg900-3 -in_memory
+add_files {axis_ctrl_crossbar_nxn_top.v ../axis_ctrl_crossbar_nxn.v ../axis_ctrl_crossbar_2d_mesh.v ../mesh_2d_dor_router_multi_sw.v ../axis_switch.v ../axis_ingress_vc_buff.v ../mesh_node_mapping.vh ../mesh_2d_dor_router_single_sw.v ../torus_2d_dor_router_single_sw.v ../torus_2d_dor_router_multi_sw.v ../axis_port_terminator.v}
+add_files {../../../fifo/axi_fifo_flop.v ../../../fifo/axi_fifo_flop2.v ../../../fifo/axi_fifo.v ../../../fifo/axi_mux_select.v ../../../fifo/axi_fifo_bram.v ../../../fifo/axi_fifo_cascade.v ../../../fifo/axi_mux.v ../../../fifo/axi_fifo_short.v ../../../fifo/axi_demux.v ../../../fifo/axi_packet_gate.v ../../../control/map/cam_priority_encoder.v ../../../control/map/cam_srl.v ../../../control/map/cam_bram.v ../../../control/map/cam.v ../../../control/map/kv_map.v ../../../control/map/axis_muxed_kv_map.v ../../../control/ram_2port.v}
+set_property top axis_ctrl_crossbar_nxn_top [current_fileset]
+synth_design
+create_clock -name clk -period 2.0 [get_ports clk]
+report_utilization -no_primitives -file axis_ctrl_crossbar_nxn.rpt
+report_timing_summary -setup -no_detailed_paths -no_header -datasheet -append -file axis_ctrl_crossbar_nxn.rpt
+write_checkpoint -force axis_ctrl_crossbar_nxn.dcp
+close_project
+exit
\ No newline at end of file
diff --git a/fpga/usrp3/lib/rfnoc/crossbar/synth/axis_ctrl_crossbar_nxn_top.v.in b/fpga/usrp3/lib/rfnoc/crossbar/synth/axis_ctrl_crossbar_nxn_top.v.in
new file mode 100644
index 000000000..6805100b9
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/crossbar/synth/axis_ctrl_crossbar_nxn_top.v.in
@@ -0,0 +1,47 @@
+//
+// Copyright 2018 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module axis_ctrl_crossbar_nxn_top(
+  input clk,
+  input rst
+);
+  // Router global config
+  localparam IMPL        = "{top}";
+  localparam NPORTS      = {ports};
+  localparam DWIDTH      = {dataw};
+  localparam MTU         = {mtu};
+  localparam ROUTING     = "{ralloc}";
+
+  (* dont_touch = "true"*) wire [(DWIDTH*NPORTS)-1:0] s_axis_tdata , m_axis_tdata ;
+  (* dont_touch = "true"*) wire [NPORTS-1:0]          s_axis_tlast , m_axis_tlast ;
+  (* dont_touch = "true"*) wire [NPORTS-1:0]          s_axis_tvalid, m_axis_tvalid;
+  (* dont_touch = "true"*) wire [NPORTS-1:0]          s_axis_tready, m_axis_tready;
+  (* dont_touch = "true"*) wire                       deadlock_detected;
+
+  axis_ctrl_crossbar_nxn #(
+    .WIDTH            (DWIDTH),
+    .NPORTS           (NPORTS),
+    .TOPOLOGY         (IMPL),
+    .INGRESS_BUFF_SIZE(MTU),
+    .ROUTER_BUFF_SIZE (MTU),
+    .ROUTING_ALLOC    (ROUTING),
+    .SWITCH_ALLOC     ("ROUND-ROBIN")
+  ) router_dut_i (
+    .clk              (clk),
+    .reset            (rst),
+    .s_axis_tdata     (s_axis_tdata ),
+    .s_axis_tlast     (s_axis_tlast ),
+    .s_axis_tvalid    (s_axis_tvalid),
+    .s_axis_tready    (s_axis_tready),
+    .m_axis_tdata     (m_axis_tdata ),
+    .m_axis_tlast     (m_axis_tlast ),
+    .m_axis_tvalid    (m_axis_tvalid),
+    .m_axis_tready    (m_axis_tready),
+    .deadlock_detected(deadlock_detected)
+  );
+
+endmodule
+
diff --git a/fpga/usrp3/lib/rfnoc/crossbar/synth/chdr_crossbar_nxn_top.tcl b/fpga/usrp3/lib/rfnoc/crossbar/synth/chdr_crossbar_nxn_top.tcl
new file mode 100644
index 000000000..304384aee
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/crossbar/synth/chdr_crossbar_nxn_top.tcl
@@ -0,0 +1,18 @@
+#!/usr/bin/python3
+#
+# Copyright 2018 Ettus Research, a National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+create_project tmp_proj -part xc7k410tffg900-3 -in_memory
+add_files {chdr_crossbar_nxn_top.v ../chdr_crossbar_nxn.v ../axis_switch.v ../chdr_xb_ingress_buff.v ../chdr_xb_routing_table.v ../../core/chdr_mgmt_pkt_handler.v ../../core/rfnoc_chdr_utils.vh ../../core/rfnoc_chdr_internal_utils.vh}
+add_files {../../../fifo/axi_fifo_flop.v ../../../fifo/axi_fifo_flop2.v ../../../fifo/axi_fifo.v ../../../fifo/axi_mux_select.v ../../../fifo/axi_fifo_bram.v ../../../fifo/axi_fifo_cascade.v ../../../fifo/axi_mux.v ../../../fifo/axi_fifo_short.v ../../../fifo/axi_demux.v ../../../fifo/axi_packet_gate.v ../../../control/map/cam_priority_encoder.v ../../../control/map/cam_srl.v ../../../control/map/cam_bram.v ../../../control/map/cam.v ../../../control/map/kv_map.v ../../../control/map/axis_muxed_kv_map.v ../../../control/ram_2port.v}
+set_property top chdr_crossbar_nxn_top [current_fileset]
+synth_design
+create_clock -name clk -period 2.0 [get_ports clk]
+report_utilization -no_primitives -file chdr_crossbar_nxn.rpt
+report_timing_summary -setup -no_detailed_paths -no_header -datasheet -append -file chdr_crossbar_nxn.rpt
+write_checkpoint -force chdr_crossbar_nxn.dcp
+close_project
+exit
\ No newline at end of file
diff --git a/fpga/usrp3/lib/rfnoc/crossbar/synth/chdr_crossbar_nxn_top.v.in b/fpga/usrp3/lib/rfnoc/crossbar/synth/chdr_crossbar_nxn_top.v.in
new file mode 100644
index 000000000..fbf0852a3
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/crossbar/synth/chdr_crossbar_nxn_top.v.in
@@ -0,0 +1,55 @@
+//
+// Copyright 2018 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module chdr_crossbar_nxn_top(
+  input clk,
+  input rst
+);
+  // Router global config
+  localparam NPORTS      = {ports};
+  localparam DWIDTH      = {dataw};
+  localparam MTU         = {mtu};
+  localparam RLUT_SIZE   = {rlutsize};
+  localparam OPTIMIZE    = "{opt}";
+
+  (* dont_touch = "true"*) wire [(DWIDTH*NPORTS)-1:0] s_axis_tdata , m_axis_tdata ;
+  (* dont_touch = "true"*) wire [NPORTS-1:0]          s_axis_tlast , m_axis_tlast ;
+  (* dont_touch = "true"*) wire [NPORTS-1:0]          s_axis_tvalid, m_axis_tvalid;
+  (* dont_touch = "true"*) wire [NPORTS-1:0]          s_axis_tready, m_axis_tready;
+
+  chdr_crossbar_nxn #(
+    .CHDR_W             (DWIDTH),
+    .NPORTS             (NPORTS),
+    .DEFAULT_PORT       (0),
+    .MTU                (MTU),
+    .ROUTE_TBL_SIZE     (RLUT_SIZE),
+    .MUX_ALLOC          ("ROUND-ROBIN"),
+    .OPTIMIZE           (OPTIMIZE),
+    .NPORTS_MGMT        (NPORTS),
+    .EXT_RTCFG_PORT     (1)
+  ) router_dut_i (
+     // General         
+    .clk                (clk),
+    .reset              (rst),
+    // Inputs           
+    .s_axis_tdata       (s_axis_tdata),
+    .s_axis_tlast       (s_axis_tlast),
+    .s_axis_tvalid      (s_axis_tvalid),
+    .s_axis_tready      (s_axis_tready),
+    // Output           
+    .m_axis_tdata       (m_axis_tdata),
+    .m_axis_tlast       (m_axis_tlast),
+    .m_axis_tvalid      (m_axis_tvalid),
+    .m_axis_tready      (m_axis_tready),
+    // External rtcfg port
+    .ext_rtcfg_stb      (0),
+    .ext_rtcfg_addr     (0),
+    .ext_rtcfg_data     (0),
+    .ext_rtcfg_ack      ()
+  );
+
+endmodule
+
diff --git a/fpga/usrp3/lib/rfnoc/crossbar/synth/synth_axis_ctrl_crossbar_nxn.py b/fpga/usrp3/lib/rfnoc/crossbar/synth/synth_axis_ctrl_crossbar_nxn.py
new file mode 100755
index 000000000..4ca6e07fa
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/crossbar/synth/synth_axis_ctrl_crossbar_nxn.py
@@ -0,0 +1,37 @@
+#! /usr/bin/python3
+#!/usr/bin/python3
+#
+# Copyright 2018 Ettus Research, a National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+import argparse
+import synth_run
+
+modname = 'axis_ctrl_crossbar_nxn'
+
+# Parse command line options
+def get_options():
+    parser = argparse.ArgumentParser(description='Generate synthesis results for ' + modname)
+    parser.add_argument('--top', type=str, default='TORUS', help='Topologies (CSV)')
+    parser.add_argument('--ports', type=str, default='8', help='Number of ports (CSV)')
+    parser.add_argument('--dataw', type=str, default='32', help='Router datapath width (CSV)')
+    parser.add_argument('--mtu', type=str, default='5', help='MTU (CSV)')
+    parser.add_argument('--ralloc', type=str, default='WORMHOLE', help='Router allocation method (CSV)')
+    return parser.parse_args()
+
+def main():
+    args = get_options()
+    keys = ['top', 'ports', 'dataw', 'mtu', 'ralloc']
+    for top in args.top.strip().split(','):
+        for ports in args.ports.strip().split(','):
+            for dataw in args.dataw.strip().split(','):
+                for mtu in args.mtu.strip().split(','):
+                    for ralloc in args.ralloc.strip().split(','):
+                        # Collect parameters
+                        transform = {'ports':ports, 'dataw':dataw, 'mtu':mtu, 'top':top, 'ralloc':ralloc}
+                        synth_run.synth_run(modname, keys, transform)
+
+if __name__ == '__main__':
+    main()
diff --git a/fpga/usrp3/lib/rfnoc/crossbar/synth/synth_chdr_crossbar_nxn.py b/fpga/usrp3/lib/rfnoc/crossbar/synth/synth_chdr_crossbar_nxn.py
new file mode 100755
index 000000000..668e7a247
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/crossbar/synth/synth_chdr_crossbar_nxn.py
@@ -0,0 +1,37 @@
+#! /usr/bin/python3
+#!/usr/bin/python3
+#
+# Copyright 2018 Ettus Research, a National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+import argparse
+import synth_run
+
+modname = 'chdr_crossbar_nxn'
+
+# Parse command line options
+def get_options():
+    parser = argparse.ArgumentParser(description='Generate synthesis results for ' + modname)
+    parser.add_argument('--opt', type=str, default='AREA', help='Optimization strategies (CSV)')
+    parser.add_argument('--ports', type=str, default='8', help='Number of ports (CSV)')
+    parser.add_argument('--dataw', type=str, default='64', help='Router datapath width (CSV)')
+    parser.add_argument('--mtu', type=str, default='10', help='MTU or Ingress buffer size (CSV)')
+    parser.add_argument('--rlutsize', type=str, default='6', help='Router lookup table size (CSV)')
+    return parser.parse_args()
+
+def main():
+    args = get_options()
+    keys = ['opt', 'ports', 'dataw', 'mtu', 'rlutsize']
+    for opt in args.opt.strip().split(','):
+        for ports in args.ports.strip().split(','):
+            for dataw in args.dataw.strip().split(','):
+                for mtu in args.mtu.strip().split(','):
+                    for rlutsize in args.rlutsize.strip().split(','):
+                        # Collect parameters
+                        transform = {'opt':opt, 'ports':ports, 'dataw':dataw, 'mtu':mtu, 'rlutsize':rlutsize}
+                        synth_run.synth_run(modname, keys, transform)
+
+if __name__ == '__main__':
+    main()
diff --git a/fpga/usrp3/lib/rfnoc/crossbar/synth/synth_run.py b/fpga/usrp3/lib/rfnoc/crossbar/synth/synth_run.py
new file mode 100644
index 000000000..a9801ac20
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/crossbar/synth/synth_run.py
@@ -0,0 +1,67 @@
+#! /usr/bin/python3
+#!/usr/bin/python3
+#
+# Copyright 2018 Ettus Research, a National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+import sys, os
+import subprocess
+import re
+
+def synth_run(modname, keys, transform):
+    prefix = modname + '_' + ('_'.join(['%s%s'%(k,transform[k]) for k in keys]))
+    print('='*(len(prefix)+2))
+    print(' %s '%(prefix))
+    print('='*(len(prefix)+2))
+    # Write Verilog top-level file
+    with open(modname + '_top.v.in', 'r') as in_file:
+        with open(modname + '_top.v', 'w') as out_file:
+            out_file.write(in_file.read().format(**transform))
+    # Run Vivado
+    exitcode = subprocess.Popen(
+        'vivado -mode tcl -source %s_top.tcl -nolog -nojou'%(modname), shell=True
+    ).wait()
+    if exitcode != 0:
+        raise RuntimeError('Error running vivado. Was setupenv.sh run?')
+    # Extract info
+    lut = 100.0
+    reg = 100.0
+    bram = 100.0
+    dsp = 100.0
+    fmax = 0.0
+    with open(modname + '.rpt', 'r') as rpt_file:
+        rpt = rpt_file.readlines()
+    for line in rpt:
+        lm = re.match(r'.*Slice LUTs\*.*\|(.*)\|(.*)\|(.*)\|(.*)\|.*', line)
+        if lm is not None:
+            lut = float(lm.group(1).strip())
+        rm = re.match(r'.*Slice Registers.*\|(.*)\|(.*)\|(.*)\|(.*)\|.*', line)
+        if rm is not None:
+            reg = float(rm.group(1).strip())
+        bm = re.match(r'.*Block RAM Tile.*\|(.*)\|(.*)\|(.*)\|(.*)\|.*', line)
+        if bm is not None:
+            bram = float(bm.group(1).strip())
+        dm = re.match(r'.*DSPs.*\|(.*)\|(.*)\|(.*)\|(.*)\|.*', line)
+        if dm is not None:
+            dsp = float(dm.group(1).strip())
+        tm = re.match(r'.*clk.*\| clk\s*\|(.*)\|.*\|.*\|.*\|.*\|.*\|.*\|.*\|', line)
+        if tm is not None:
+            fmax = 1000.0/float(tm.group(1).strip())
+    # Save report
+    os.rename(modname + '.rpt', prefix + '.rpt')
+    os.rename(modname + '.dcp', prefix + '.dcp')
+    try:
+        os.remove(modname + '_top.v')
+        os.remove('fsm_encoding.os')
+    except FileNotFoundError:
+        pass
+    # Write summary report line
+    res_keys = ['lut','reg','bram','dsp','fmax']
+    res = {'lut':lut, 'reg':reg, 'bram':bram, 'dsp':dsp, 'fmax':fmax, 'prefix':prefix}
+    if not os.path.exists(modname + '_summary.csv'):
+        with open(modname + '_summary.csv', 'w') as summaryf:
+            summaryf.write((','.join(keys + res_keys)) + '\n')
+    with open(modname + '_summary.csv', 'a') as summaryf:
+        summaryf.write((','.join(['%s'%(transform[k]) for k in keys])) + ',' + (','.join(['%.1f'%(res[k]) for k in res_keys])) + '\n')
diff --git a/fpga/usrp3/lib/rfnoc/crossbar/torus_2d_dor_router_multi_sw.v b/fpga/usrp3/lib/rfnoc/crossbar/torus_2d_dor_router_multi_sw.v
new file mode 100644
index 000000000..cd70450a0
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/crossbar/torus_2d_dor_router_multi_sw.v
@@ -0,0 +1,338 @@
+//
+// Copyright 2018 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: torus_2d_dor_router_multi_sw
+// Description:
+//   Alternate implementation for torus_2d_dor_router_single_sw with
+//   multiple switches for independent paths between inputs and outputs
+//   **NOTE**: This module has not been validated
+
+module torus_2d_dor_router_multi_sw #(
+  parameter                         WIDTH          = 64,
+  parameter                         DIM_SIZE       = 4,
+  parameter [$clog2(DIM_SIZE)-1:0]  XB_ADDR_X      = 0,
+  parameter [$clog2(DIM_SIZE)-1:0]  XB_ADDR_Y      = 0,
+  parameter                         TERM_BUFF_SIZE = 5,
+  parameter                         XB_BUFF_SIZE   = 5,
+  parameter                         ROUTING_ALLOC  = "WORMHOLE"
+) (
+  // Clocks and resets
+  input  wire             clk,
+  input  wire             reset,
+
+  // Terminal connections
+  input  wire [WIDTH-1:0] s_axis_term_tdata,
+  input  wire             s_axis_term_tlast,
+  input  wire             s_axis_term_tvalid,
+  output wire             s_axis_term_tready,
+  output wire [WIDTH-1:0] m_axis_term_tdata,
+  output wire             m_axis_term_tlast,
+  output wire             m_axis_term_tvalid,
+  input  wire             m_axis_term_tready,
+
+  // X-dimension inter-XB connections
+  input  wire [WIDTH-1:0] s_axis_xdim_tdata,
+  input  wire [0:0]       s_axis_xdim_tdest,
+  input  wire             s_axis_xdim_tlast,
+  input  wire             s_axis_xdim_tvalid,
+  output wire             s_axis_xdim_tready,
+  output wire [WIDTH-1:0] m_axis_xdim_tdata,
+  output wire [0:0]       m_axis_xdim_tdest,
+  output wire             m_axis_xdim_tlast,
+  output wire             m_axis_xdim_tvalid,
+  input  wire             m_axis_xdim_tready,
+
+  // Y-dimension inter-XB connections
+  input  wire [WIDTH-1:0] s_axis_ydim_tdata,
+  input  wire [0:0]       s_axis_ydim_tdest,
+  input  wire             s_axis_ydim_tlast,
+  input  wire             s_axis_ydim_tvalid,
+  output wire             s_axis_ydim_tready,
+  output wire [WIDTH-1:0] m_axis_ydim_tdata,
+  output wire [0:0]       m_axis_ydim_tdest,
+  output wire             m_axis_ydim_tlast,
+  output wire             m_axis_ydim_tvalid,
+  input  wire             m_axis_ydim_tready
+);
+
+  // -------------------------------------------------
+  // Routing functions
+  // -------------------------------------------------
+  `include "mesh_node_mapping.vh"
+
+  function [2:0] term_in_route;
+    input [WIDTH:0] header;
+    reg [$clog2(DIM_SIZE)-1:0] xdst, ydst, xdiff, ydiff;
+  begin
+    xdst  = node_to_xdst(header);
+    ydst  = node_to_ydst(header);
+    xdiff = xdst - XB_ADDR_X;
+    ydiff = ydst - XB_ADDR_Y;
+    // Routing logic
+    // - MSB is the VC, 2 LSBs are the router destination
+    // - Long journeys get VC = 1 to bypass local traffic
+    if (xdst == XB_ADDR_X && ydst == XB_ADDR_Y) begin
+      term_in_route = {1'b0 /* VC don't care */, 2'd2 /* term out */};
+    end else if (xdst == XB_ADDR_X) begin
+      term_in_route = {ydiff[$clog2(DIM_SIZE)-1], 2'd0 /* ydim out */};
+    end else begin
+      term_in_route = {xdiff[$clog2(DIM_SIZE)-1], 2'd1 /* xdim out */};
+    end
+  end
+  endfunction
+
+  function [2:0] xdim_in_route;
+    input [WIDTH:0] header;
+    reg [$clog2(DIM_SIZE)-1:0] xdst, ydst, xdiff, ydiff;
+  begin
+    xdst  = node_to_xdst(header);
+    ydst  = node_to_ydst(header);
+    xdiff = xdst - XB_ADDR_X;
+    ydiff = ydst - XB_ADDR_Y;
+    // Routing logic
+    // - MSB is the VC, 2 LSBs are the router destination
+    // - Long journeys get VC = 1 to bypass local traffic
+    if (xdst == XB_ADDR_X && ydst == XB_ADDR_Y) begin
+      xdim_in_route = {1'b0 /* VC don't care */, 2'd2 /* term out */};
+    end else if (xdst == XB_ADDR_X) begin
+      xdim_in_route = {ydiff[$clog2(DIM_SIZE)-1], 2'd0 /* ydim out */};
+    end else begin
+      xdim_in_route = {xdiff[$clog2(DIM_SIZE)-1], 2'd1 /* xdim out */};
+    end
+  end
+  endfunction
+
+  function [1:0] ydim_in_route;
+    input [WIDTH:0] header;
+    reg [$clog2(DIM_SIZE)-1:0] ydst, ydiff;
+  begin
+    ydst  = node_to_ydst(header);
+    ydiff = ydst - XB_ADDR_Y;
+    // Routing logic
+    // - MSB is the VC, LSB is the router destination
+    // - Long journeys get VC = 1 to bypass local traffic
+    if (ydst == XB_ADDR_Y) begin
+      ydim_in_route = {1'b0 /* VC don't care */, 1'd1 /* term out */};
+    end else begin
+      ydim_in_route = {ydiff[$clog2(DIM_SIZE)-1], 1'd0 /* ydim out */};
+    end
+  end
+  endfunction
+
+  // -------------------------------------------------
+  // Input demuxes
+  // -------------------------------------------------
+  wire [WIDTH-1:0] ti_gt_tdata;
+  wire             ti_gt_tdest; 
+  wire             ti_gt_tlast; 
+  wire             ti_gt_tvalid;
+  wire             ti_gt_tready;
+  wire [WIDTH-1:0] t2t_tdata,  t2x_tdata,  t2y_tdata;
+  wire             t2t_tdest,  t2x_tdest,  t2y_tdest;
+  wire             t2t_tlast,  t2x_tlast,  t2y_tlast;
+  wire             t2t_tvalid, t2x_tvalid, t2y_tvalid;
+  wire             t2t_tready, t2x_tready, t2y_tready;
+  wire [WIDTH-1:0] term_in_hdr;
+  wire [1:0]       term_in_port;
+
+  assign {ti_gt_tdest, term_in_port} = term_in_route(term_in_hdr);
+
+  axi_packet_gate #(
+    .WIDTH(WIDTH), .SIZE(TERM_BUFF_SIZE)
+  ) term_in_pkt_gate_i (
+    .clk      (clk), 
+    .reset    (reset), 
+    .clear    (1'b0),
+    .i_tdata  (s_axis_term_tdata),
+    .i_tlast  (s_axis_term_tlast),
+    .i_tvalid (s_axis_term_tvalid),
+    .i_tready (s_axis_term_tready),
+    .i_terror (1'b0),
+    .o_tdata  (ti_gt_tdata),
+    .o_tlast  (ti_gt_tlast),
+    .o_tvalid (ti_gt_tvalid),
+    .o_tready (ti_gt_tready)
+  );
+
+  axi_demux #(
+    .WIDTH(WIDTH+1), .SIZE(3),
+    .PRE_FIFO_SIZE(0 /* must be 0 */), .POST_FIFO_SIZE(0)
+  ) term_in_demux_i (
+    .clk      (clk),
+    .reset    (reset),
+    .clear    (1'b0),
+    .header   (term_in_hdr),
+    .dest     (term_in_port),
+    .i_tdata  ({ti_gt_tdest, ti_gt_tdata}),
+    .i_tlast  (ti_gt_tlast),
+    .i_tvalid (ti_gt_tvalid),
+    .i_tready (ti_gt_tready),
+    .o_tdata  ({t2t_tdest, t2t_tdata, t2x_tdest, t2x_tdata, t2y_tdest, t2y_tdata}),
+    .o_tlast  ({t2t_tlast,  t2x_tlast,  t2y_tlast}),
+    .o_tvalid ({t2t_tvalid, t2x_tvalid, t2y_tvalid}),
+    .o_tready ({t2t_tready, t2x_tready, t2y_tready})
+  );
+
+  wire [WIDTH-1:0] xi_gt_tdata;
+  wire             xi_gt_tdest; 
+  wire             xi_gt_tlast; 
+  wire             xi_gt_tvalid;
+  wire             xi_gt_tready;
+  wire [WIDTH-1:0] x2t_tdata,  x2x_tdata,  x2y_tdata;
+  wire             x2t_tdest,  x2x_tdest,  x2y_tdest;
+  wire             x2t_tlast,  x2x_tlast,  x2y_tlast;
+  wire             x2t_tvalid, x2x_tvalid, x2y_tvalid;
+  wire             x2t_tready, x2x_tready, x2y_tready;
+  wire [WIDTH-1:0] xdim_in_hdr;
+  wire [1:0]       xdim_in_port;
+
+  assign {xi_gt_tdest, xdim_in_port} = xdim_in_route(xdim_in_hdr);
+
+  axis_ingress_vc_buff #(
+    .WIDTH(WIDTH), .NUM_VCS(2),
+    .SIZE(XB_BUFF_SIZE),
+    .ROUTING(ROUTING_ALLOC)
+  ) xdim_in_vc_buf_i (
+    .clk           (clk), 
+    .reset         (reset), 
+    .s_axis_tdata  (s_axis_xdim_tdata),
+    .s_axis_tdest  (s_axis_xdim_tdest),
+    .s_axis_tlast  (s_axis_xdim_tlast),
+    .s_axis_tvalid (s_axis_xdim_tvalid),
+    .s_axis_tready (s_axis_xdim_tready),
+    .m_axis_tdata  (xi_gt_tdata),
+    .m_axis_tlast  (xi_gt_tlast),
+    .m_axis_tvalid (xi_gt_tvalid),
+    .m_axis_tready (xi_gt_tready)
+  );
+
+  axi_demux #(
+    .WIDTH(WIDTH+1), .SIZE(3),
+    .PRE_FIFO_SIZE(0 /* must be 0 */), .POST_FIFO_SIZE(0)
+  ) xdim_in_demux_i (
+    .clk      (clk),
+    .reset    (reset),
+    .clear    (1'b0),
+    .header   (xdim_in_hdr),
+    .dest     (xdim_in_port),
+    .i_tdata  ({xi_gt_tdest, xi_gt_tdata}),
+    .i_tlast  (xi_gt_tlast),
+    .i_tvalid (xi_gt_tvalid),
+    .i_tready (xi_gt_tready),
+    .o_tdata  ({x2t_tdest, x2t_tdata, x2x_tdest, x2x_tdata, x2y_tdest, x2y_tdata}),
+    .o_tlast  ({x2t_tlast, x2x_tlast, x2y_tlast}),
+    .o_tvalid ({x2t_tvalid, x2x_tvalid, x2y_tvalid}),
+    .o_tready ({x2t_tready, x2x_tready, x2y_tready})
+  );
+
+  wire [WIDTH-1:0] yi_gt_tdata;
+  wire             yi_gt_tdest; 
+  wire             yi_gt_tlast; 
+  wire             yi_gt_tvalid;
+  wire             yi_gt_tready;
+  wire [WIDTH-1:0] y2t_tdata,  y2y_tdata;
+  wire             y2t_tdest,  y2y_tdest;
+  wire             y2t_tlast,  y2y_tlast;
+  wire             y2t_tvalid, y2y_tvalid;
+  wire             y2t_tready, y2y_tready;
+  wire [WIDTH-1:0] ydim_in_hdr;
+  wire [0:0]       ydim_in_port;
+
+  assign {yi_gt_tdest, ydim_in_port} = ydim_in_route(ydim_in_hdr);
+
+  axis_ingress_vc_buff #(
+    .WIDTH(WIDTH), .NUM_VCS(2),
+    .SIZE(XB_BUFF_SIZE),
+    .ROUTING(ROUTING_ALLOC)
+  ) ydim_in_vc_buf_i (
+    .clk           (clk), 
+    .reset         (reset), 
+    .s_axis_tdata  (s_axis_ydim_tdata ),
+    .s_axis_tdest  (s_axis_ydim_tdest ),
+    .s_axis_tlast  (s_axis_ydim_tlast ),
+    .s_axis_tvalid (s_axis_ydim_tvalid),
+    .s_axis_tready (s_axis_ydim_tready),
+    .m_axis_tdata  (yi_gt_tdata ),
+    .m_axis_tlast  (yi_gt_tlast ),
+    .m_axis_tvalid (yi_gt_tvalid),
+    .m_axis_tready (yi_gt_tready)
+  );
+
+  axi_demux #(
+    .WIDTH(WIDTH+1), .SIZE(2),
+    .PRE_FIFO_SIZE(0 /* must be 0 */), .POST_FIFO_SIZE(0)
+  ) ydim_in_demux_i (
+    .clk      (clk),
+    .reset    (reset),
+    .clear    (1'b0),
+    .header   (ydim_in_hdr),
+    .dest     (ydim_in_port),
+    .i_tdata  ({yi_gt_tdest, yi_gt_tdata}),
+    .i_tlast  (yi_gt_tlast),
+    .i_tvalid (yi_gt_tvalid),
+    .i_tready (yi_gt_tready),
+    .o_tdata  ({y2t_tdest, y2t_tdata, y2y_tdest, y2y_tdata}),
+    .o_tlast  ({y2t_tlast,  y2y_tlast}),
+    .o_tvalid ({y2t_tvalid, y2y_tvalid}),
+    .o_tready ({y2t_tready, y2y_tready})
+  );
+
+  // -------------------------------------------------
+  // Output muxes
+  // -------------------------------------------------
+  wire term_tdest_discard;
+  axi_mux #(
+    .WIDTH(WIDTH+1), .SIZE(3),
+    .PRE_FIFO_SIZE(0), .POST_FIFO_SIZE(1)
+  ) term_out_mux_i (
+    .clk      (clk),
+    .reset    (reset),
+    .clear    (1'b0),
+    .i_tdata  ({t2t_tdest, t2t_tdata, x2t_tdest, x2t_tdata, y2t_tdest, y2t_tdata}),
+    .i_tlast  ({t2t_tlast, x2t_tlast, y2t_tlast }),
+    .i_tvalid ({t2t_tvalid, x2t_tvalid, y2t_tvalid}),
+    .i_tready ({t2t_tready, x2t_tready, y2t_tready}),
+    .o_tdata  ({term_tdest_discard, m_axis_term_tdata}),
+    .o_tlast  (m_axis_term_tlast),
+    .o_tvalid (m_axis_term_tvalid),
+    .o_tready (m_axis_term_tready)
+  );
+
+  axi_mux #(
+    .WIDTH(WIDTH+1), .SIZE(2),
+    .PRE_FIFO_SIZE(0), .POST_FIFO_SIZE(1)
+  ) xdim_out_mux_i (
+    .clk      (clk),
+    .reset    (reset),
+    .clear    (1'b0),
+    .i_tdata  ({t2x_tdest, t2x_tdata, x2x_tdest, x2x_tdata}),
+    .i_tlast  ({t2x_tlast,  x2x_tlast}),
+    .i_tvalid ({t2x_tvalid, x2x_tvalid}),
+    .i_tready ({t2x_tready, x2x_tready}),
+    .o_tdata  ({m_axis_xdim_tdest, m_axis_xdim_tdata}),
+    .o_tlast  (m_axis_xdim_tlast ),
+    .o_tvalid (m_axis_xdim_tvalid),
+    .o_tready (m_axis_xdim_tready)
+  );
+
+  axi_mux #(
+    .WIDTH(WIDTH+1), .SIZE(3),
+    .PRE_FIFO_SIZE(0), .POST_FIFO_SIZE(1)
+  ) ydim_out_mux_i (
+    .clk      (clk),
+    .reset    (reset),
+    .clear    (1'b0),
+    .i_tdata  ({t2y_tdest, t2y_tdata, x2y_tdest, x2y_tdata, y2y_tdest, y2y_tdata}),
+    .i_tlast  ({t2y_tlast, x2y_tlast, y2y_tlast }),
+    .i_tvalid ({t2y_tvalid, x2y_tvalid, y2y_tvalid}),
+    .i_tready ({t2y_tready, x2y_tready, y2y_tready}),
+    .o_tdata  ({m_axis_ydim_tdest, m_axis_ydim_tdata}),
+    .o_tlast  (m_axis_ydim_tlast),
+    .o_tvalid (m_axis_ydim_tvalid),
+    .o_tready (m_axis_ydim_tready)
+  );
+
+endmodule
+
diff --git a/fpga/usrp3/lib/rfnoc/crossbar/torus_2d_dor_router_single_sw.v b/fpga/usrp3/lib/rfnoc/crossbar/torus_2d_dor_router_single_sw.v
new file mode 100644
index 000000000..21a66782d
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/crossbar/torus_2d_dor_router_single_sw.v
@@ -0,0 +1,294 @@
+//
+// Copyright 2018 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: torus_2d_dor_router_single_sw
+// Description: 
+//   This module implements the router for a 2-dimentional (2d) 
+//   torus network that uses dimension order routing (dor) and has a 
+//   single underlying switch (single_sw). It uses AXI-Stream for all of its
+//   links. 
+//   The torus topology, routing algorithms and the router architecture is 
+//   described in README.md in this directory. 
+// Parameters:
+//   - WIDTH: Width of the AXI-Stream data bus
+//   - DIM_SIZE: Number of routers alone one dimension
+//   - XB_ADDR_X: The X-coordinate of this router in the topology
+//   - XB_ADDR_Y: The Y-coordinate of this router in the topology
+//   - TERM_BUFF_SIZE: log2 of the ingress terminal buffer size (in words)
+//   - XB_BUFF_SIZE: log2 of the ingress inter-router buffer size (in words)
+//   - ROUTING_ALLOC: Algorithm to allocate routing paths between routers.
+//     * WORMHOLE: Allocate route as soon as first word in pkt arrives
+//     * CUT-THROUGH: Allocate route only after the full pkt arrives
+//   - SWITCH_ALLOC: Algorithm to allocate the switch
+//     * PRIO: Priority based. Priority: Y-dim > X-dim > Term
+//     * ROUND-ROBIN: Round robin input port allocation
+// Signals:
+//   - *_axis_term_*: Terminal ports (master/slave)
+//   - *_axis_xdim_*: Inter-router X-dim connections (master/slave)
+//   - *_axis_ydim_*: Inter-router Y-dim connections (master/slave)
+//
+
+module torus_2d_dor_router_single_sw #(
+  parameter                         WIDTH          = 64,
+  parameter                         DIM_SIZE       = 4,
+  parameter [$clog2(DIM_SIZE)-1:0]  XB_ADDR_X      = 0,
+  parameter [$clog2(DIM_SIZE)-1:0]  XB_ADDR_Y      = 0,
+  parameter                         TERM_BUFF_SIZE = 5,
+  parameter                         XB_BUFF_SIZE   = 5,
+  parameter                         ROUTING_ALLOC  = "WORMHOLE",
+  parameter                         SWITCH_ALLOC   = "PRIO"
+) (
+  // Clocks and resets
+  input  wire             clk,
+  input  wire             reset,
+
+  // Terminal connections
+  input  wire [WIDTH-1:0] s_axis_term_tdata,
+  input  wire             s_axis_term_tlast,
+  input  wire             s_axis_term_tvalid,
+  output wire             s_axis_term_tready,
+  output wire [WIDTH-1:0] m_axis_term_tdata,
+  output wire             m_axis_term_tlast,
+  output wire             m_axis_term_tvalid,
+  input  wire             m_axis_term_tready,
+
+  // X-dimension inter-XB connections
+  input  wire [WIDTH-1:0] s_axis_xdim_tdata,
+  input  wire [0:0]       s_axis_xdim_tdest,
+  input  wire             s_axis_xdim_tlast,
+  input  wire             s_axis_xdim_tvalid,
+  output wire             s_axis_xdim_tready,
+  output wire [WIDTH-1:0] m_axis_xdim_tdata,
+  output wire [0:0]       m_axis_xdim_tdest,
+  output wire             m_axis_xdim_tlast,
+  output wire             m_axis_xdim_tvalid,
+  input  wire             m_axis_xdim_tready,
+
+  // Y-dimension inter-XB connections
+  input  wire [WIDTH-1:0] s_axis_ydim_tdata,
+  input  wire [0:0]       s_axis_ydim_tdest,
+  input  wire             s_axis_ydim_tlast,
+  input  wire             s_axis_ydim_tvalid,
+  output wire             s_axis_ydim_tready,
+  output wire [WIDTH-1:0] m_axis_ydim_tdata,
+  output wire [0:0]       m_axis_ydim_tdest,
+  output wire             m_axis_ydim_tlast,
+  output wire             m_axis_ydim_tvalid,
+  input  wire             m_axis_ydim_tready
+);
+
+  //-------------------------------------------------
+  // Routing and switch allocation functions
+  //-------------------------------------------------
+
+  // mesh_node_mapping.vh file contains the mapping between the node number
+  // and its XY coordinates. It is autogenerated and defines the node_to_xdst
+  // and node_to_ydst functions.
+  `include "mesh_node_mapping.vh"
+
+  localparam [1:0] SW_DEST_TERM = 2'd0;
+  localparam [1:0] SW_DEST_XDIM = 2'd1;
+  localparam [1:0] SW_DEST_YDIM = 2'd2;
+  localparam [1:0] SW_NUM_DESTS = 2'd3;
+
+  // The compute_switch_tdest function is the destination selector
+  // i.e. it will inspecte the bottom $clog2(DIM_SIZE)*2 bits of the
+  // first word of a packet and determine the destination of the packet. 
+  function [2:0] compute_switch_tdest;
+    input [WIDTH-1:0] header;
+    reg [$clog2(DIM_SIZE)-1:0] xdst, ydst;
+    reg signed [$clog2(DIM_SIZE):0] xdiff, ydiff;
+  begin
+    xdst  = node_to_xdst(header);
+    ydst  = node_to_ydst(header);
+    xdiff = xdst - XB_ADDR_X;
+    ydiff = ydst - XB_ADDR_Y;
+    // Routing logic
+    // - MSB is the VC, 2 LSBs are the router destination
+    // - Long journeys get VC = 1 to bypass local traffic
+    if (xdiff == 'd0 && ydiff == 'd0) begin
+      compute_switch_tdest = {1'b0 /* VC don't care */,  SW_DEST_TERM};
+    end else if (xdiff != 'd0) begin
+      compute_switch_tdest = {(xdiff < 0), SW_DEST_XDIM};
+    end else begin
+      compute_switch_tdest = {(ydiff < 0), SW_DEST_YDIM};
+    end
+    //$display("xdst=%d, ydst=%d, xaddr=%d, yaddr=%d, dst=%d", xdst, ydst, XB_ADDR_X, XB_ADDR_Y, compute_switch_tdest);
+  end
+  endfunction
+
+  // The compute_switch_alloc function is the switch allocation function 
+  // i.e. it chooses which input port reserves the switch for packet transfer.
+  // After the switch is allocated, all other ports will be backpressured until
+  // the packet finishes transferring.
+  function [1:0] compute_switch_alloc;
+    input [2:0] pkt_waiting;
+    input [1:0] last_alloc;
+  begin
+    if (pkt_waiting == 3'b000) begin
+      compute_switch_alloc = SW_DEST_TERM;
+    end else if (pkt_waiting == 3'b001) begin
+      compute_switch_alloc = SW_DEST_TERM;
+    end else if (pkt_waiting == 3'b010) begin
+      compute_switch_alloc = SW_DEST_XDIM;
+    end else if (pkt_waiting == 3'b100) begin
+      compute_switch_alloc = SW_DEST_YDIM;
+    end else begin
+      if (SWITCH_ALLOC == "PRIO") begin
+        // Priority: Y-dim > X-dim > Term
+        if (pkt_waiting[SW_DEST_YDIM])
+          compute_switch_alloc = SW_DEST_YDIM;
+        else if (pkt_waiting[SW_DEST_XDIM])
+          compute_switch_alloc = SW_DEST_XDIM;
+        else
+          compute_switch_alloc = SW_DEST_TERM;
+      end else begin
+        // Round-robin
+        if (pkt_waiting[(last_alloc + 3'd1) % SW_NUM_DESTS])
+          compute_switch_alloc = (last_alloc + 3'd1) % SW_NUM_DESTS;
+        else if (pkt_waiting[(last_alloc + 3'd2) % SW_NUM_DESTS])
+          compute_switch_alloc = (last_alloc + 3'd2) % SW_NUM_DESTS;
+        else
+          compute_switch_alloc = last_alloc;
+      end
+    end
+  end
+  endfunction
+
+  //-------------------------------------------------
+  // Ingress buffers
+  //-------------------------------------------------
+  wire [WIDTH-1:0] ydim_in_data , xdim_in_data , term_in_data ;
+  wire [2:0]       ydim_in_dest , xdim_in_dest , term_in_dest ; 
+  wire             ydim_in_last , xdim_in_last , term_in_last ; 
+  wire             ydim_in_valid, xdim_in_valid, term_in_valid;
+  wire             ydim_in_ready, xdim_in_ready, term_in_ready;
+
+  // Data coming in from the terminal is gated until a full packet arrives
+  // in order to minimize the switch allocation time per packet.
+  axi_packet_gate #(
+    .WIDTH(WIDTH), .SIZE(TERM_BUFF_SIZE)
+  ) term_in_pkt_gate_i (
+    .clk      (clk), 
+    .reset    (reset), 
+    .clear    (1'b0),
+    .i_tdata  (s_axis_term_tdata),
+    .i_tlast  (s_axis_term_tlast),
+    .i_tvalid (s_axis_term_tvalid),
+    .i_tready (s_axis_term_tready),
+    .i_terror (1'b0),
+    .o_tdata  (term_in_data),
+    .o_tlast  (term_in_last),
+    .o_tvalid (term_in_valid),
+    .o_tready (term_in_ready)
+  );
+  assign term_in_dest = compute_switch_tdest(term_in_data);
+
+  // The XY directions have buffers with 2 virtual channels to minimize the
+  // possibility of a deadlock.
+  axis_ingress_vc_buff #(
+    .WIDTH(WIDTH), .NUM_VCS(2),
+    .SIZE(XB_BUFF_SIZE),
+    .ROUTING(ROUTING_ALLOC)
+  ) xdim_in_vc_buf_i (
+    .clk           (clk), 
+    .reset         (reset), 
+    .s_axis_tdata  (s_axis_xdim_tdata),
+    .s_axis_tdest  (s_axis_xdim_tdest),
+    .s_axis_tlast  (s_axis_xdim_tlast),
+    .s_axis_tvalid (s_axis_xdim_tvalid),
+    .s_axis_tready (s_axis_xdim_tready),
+    .m_axis_tdata  (xdim_in_data),
+    .m_axis_tlast  (xdim_in_last),
+    .m_axis_tvalid (xdim_in_valid),
+    .m_axis_tready (xdim_in_ready)
+  );
+  assign xdim_in_dest = compute_switch_tdest(xdim_in_data);
+
+  axis_ingress_vc_buff #(
+    .WIDTH(WIDTH), .NUM_VCS(2),
+    .SIZE(XB_BUFF_SIZE),
+    .ROUTING(ROUTING_ALLOC)
+  ) ydim_in_vc_buf_i (
+    .clk           (clk), 
+    .reset         (reset), 
+    .s_axis_tdata  (s_axis_ydim_tdata ),
+    .s_axis_tdest  (s_axis_ydim_tdest ),
+    .s_axis_tlast  (s_axis_ydim_tlast ),
+    .s_axis_tvalid (s_axis_ydim_tvalid),
+    .s_axis_tready (s_axis_ydim_tready),
+    .m_axis_tdata  (ydim_in_data ),
+    .m_axis_tlast  (ydim_in_last ),
+    .m_axis_tvalid (ydim_in_valid),
+    .m_axis_tready (ydim_in_ready)
+  );
+  assign ydim_in_dest = compute_switch_tdest(ydim_in_data);
+
+  //-------------------------------------------------
+  // Switch
+  //-------------------------------------------------
+
+  // Track the input packet state
+  localparam [0:0] PKT_ST_HEAD = 1'b0;
+  localparam [0:0] PKT_ST_BODY = 1'b1;
+  reg [0:0] pkt_state = PKT_ST_HEAD;
+
+  // The switch only accept packets on a single port at a time.
+  wire sw_in_ready = |({ydim_in_ready, xdim_in_ready, term_in_ready});
+  wire sw_in_valid = |({ydim_in_valid, xdim_in_valid, term_in_valid});
+  wire sw_in_last  = |({ydim_in_last&ydim_in_valid, xdim_in_last&xdim_in_valid, term_in_last&term_in_valid});
+
+  always @(posedge clk) begin
+    if (reset) begin
+      pkt_state <= PKT_ST_HEAD;
+    end else if (sw_in_valid & sw_in_ready) begin
+      pkt_state <= sw_in_last ? PKT_ST_HEAD : PKT_ST_BODY;
+    end
+  end
+
+  // The switch requires the allocation to stay valid until the
+  // end of the packet. We also might need to keep the previous
+  // packet's allocation to compute the current one
+  wire [1:0] switch_alloc;
+  reg  [1:0] prev_switch_alloc = SW_DEST_TERM;
+  reg  [1:0] pkt_switch_alloc  = SW_DEST_TERM;
+
+  always @(posedge clk) begin
+    if (reset) begin
+      prev_switch_alloc <= SW_DEST_TERM;
+      pkt_switch_alloc <= SW_DEST_TERM;
+    end else if (sw_in_valid & sw_in_ready) begin
+      if (pkt_state == PKT_ST_HEAD)
+        pkt_switch_alloc <= switch_alloc;
+      if (sw_in_last)
+        prev_switch_alloc <= switch_alloc;
+    end
+  end
+
+  assign switch_alloc = (sw_in_valid && pkt_state == PKT_ST_HEAD) ? 
+    compute_switch_alloc({ydim_in_valid, xdim_in_valid, term_in_valid}, prev_switch_alloc) :
+    pkt_switch_alloc;
+
+  wire term_tdest_discard;
+  axis_switch #(
+    .DATA_W(WIDTH), .DEST_W(1), .IN_PORTS(3), .OUT_PORTS(3)
+  ) switch_i (
+    .clk           (clk),
+    .reset         (reset),
+    .s_axis_tdata  ({ydim_in_data , xdim_in_data , term_in_data }),
+    .s_axis_tdest  ({ydim_in_dest , xdim_in_dest , term_in_dest }), 
+    .s_axis_tlast  ({ydim_in_last , xdim_in_last , term_in_last }),
+    .s_axis_tvalid ({ydim_in_valid, xdim_in_valid, term_in_valid}),
+    .s_axis_tready ({ydim_in_ready, xdim_in_ready, term_in_ready}),
+    .s_axis_alloc  (switch_alloc),
+    .m_axis_tdata  ({m_axis_ydim_tdata,  m_axis_xdim_tdata,  m_axis_term_tdata }),
+    .m_axis_tdest  ({m_axis_ydim_tdest,  m_axis_xdim_tdest,  term_tdest_discard}),
+    .m_axis_tlast  ({m_axis_ydim_tlast,  m_axis_xdim_tlast,  m_axis_term_tlast }),
+    .m_axis_tvalid ({m_axis_ydim_tvalid, m_axis_xdim_tvalid, m_axis_term_tvalid}),
+    .m_axis_tready ({m_axis_ydim_tready, m_axis_xdim_tready, m_axis_term_tready})
+  );
+
+endmodule
+
diff --git a/fpga/usrp3/lib/rfnoc/cvita_hdr_decoder.v b/fpga/usrp3/lib/rfnoc/cvita_hdr_decoder.v
new file mode 100644
index 000000000..289c674e8
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/cvita_hdr_decoder.v
@@ -0,0 +1,32 @@
+//
+// Copyright 2016 Ettus Research
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Decoder header word into CVITA header fields
+
+module cvita_hdr_decoder (
+  input [127:0] header,
+  output [1:0] pkt_type, output eob, output has_time,
+  output [11:0] seqnum, output [15:0] length, output [15:0] payload_length,
+  output [15:0] src_sid, output [15:0] dst_sid,
+  output [63:0] vita_time
+);
+
+  wire [63:0] hdr[0:1];
+  assign hdr[0] = header[127:64];
+  assign hdr[1] = header[63:0];
+
+  assign pkt_type  = hdr[0][63:62];
+  assign has_time  = hdr[0][61];
+  assign eob       = hdr[0][60];
+  assign seqnum    = hdr[0][59:48];
+  assign length    = hdr[0][47:32];
+  assign src_sid   = hdr[0][31:16];
+  assign dst_sid   = hdr[0][15:0];
+  assign vita_time = hdr[1];
+
+  assign payload_length = has_time ? length - 16'd16 : length - 16'd8;
+
+endmodule
\ No newline at end of file
diff --git a/fpga/usrp3/lib/rfnoc/cvita_hdr_encoder.v b/fpga/usrp3/lib/rfnoc/cvita_hdr_encoder.v
new file mode 100644
index 000000000..82bfcb2ae
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/cvita_hdr_encoder.v
@@ -0,0 +1,22 @@
+//
+// Copyright 2016 Ettus Research
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Encodes CVITA packet header fields into a header word
+
+module cvita_hdr_encoder (
+  input [1:0] pkt_type, input eob, input has_time,
+  input [11:0] seqnum,
+  input [15:0] payload_length,
+  input [15:0] src_sid, input [15:0] dst_sid,
+  input [63:0] vita_time,
+  output [127:0] header
+);
+
+  assign header = {pkt_type, has_time, eob, seqnum,
+                   payload_length + (has_time ? 16'd16 : 16'd8),
+                   src_sid, dst_sid, vita_time};
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/cvita_hdr_modify.v b/fpga/usrp3/lib/rfnoc/cvita_hdr_modify.v
new file mode 100644
index 000000000..874e1776c
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/cvita_hdr_modify.v
@@ -0,0 +1,36 @@
+//
+// Copyright 2016 Ettus Research
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Modifies CVITA packet header fields
+
+module cvita_hdr_modify (
+  input  [127:0] header_in,
+  output [127:0] header_out,
+  input use_pkt_type,       input [1:0] pkt_type,
+  input use_has_time,       input has_time,
+  input use_eob,            input eob,
+  input use_seqnum,         input [11:0] seqnum,
+  input use_length,         input [15:0] length,
+  input use_payload_length, input [15:0] payload_length,
+  input use_src_sid,        input [15:0] src_sid,
+  input use_dst_sid,        input [15:0] dst_sid,
+  input use_vita_time,      input [63:0] vita_time
+);
+
+  wire [15:0] length_adj = payload_length + (header_out[125] /* Has time */ ? 16'd16 : 16'd8);
+
+  assign header_out = {
+    (use_pkt_type       == 1'b1) ? pkt_type   : header_in[127:126],
+    (use_has_time       == 1'b1) ? has_time   : header_in[125],
+    (use_eob            == 1'b1) ? eob        : header_in[124],
+    (use_seqnum         == 1'b1) ? seqnum     : header_in[123:112],
+    (use_length         == 1'b1) ? length     :
+    (use_payload_length == 1'b1) ? length_adj : header_in[111:96],
+    (use_src_sid        == 1'b1) ? src_sid    : header_in[95:80],
+    (use_dst_sid        == 1'b1) ? dst_sid    : header_in[79:64],
+    (use_vita_time      == 1'b1) ? vita_time  : header_in[63:0]};
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/cvita_hdr_parser.v b/fpga/usrp3/lib/rfnoc/cvita_hdr_parser.v
new file mode 100644
index 000000000..d64c3b6d9
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/cvita_hdr_parser.v
@@ -0,0 +1,89 @@
+//
+// Copyright 2015 Ettus Research
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Parses CVITA packet header and outputs discrete signals.
+
+module cvita_hdr_parser #(
+  parameter REGISTER = 1    // 0 = No registering, header / vita_time only valid when hdr_stb / vita_time_stb is asserted (lower resource utilization)
+                            // 1 = Header / vita time are registered and valid for the length of entire packet.
+)(
+  input clk, input reset, input clear,
+  output hdr_stb,
+  output [1:0] pkt_type, output eob, output has_time,
+  output [11:0] seqnum, output [15:0] length, output [15:0] payload_length,
+  output [15:0] src_sid, output [15:0] dst_sid,
+  output vita_time_stb,
+  output [63:0] vita_time,
+  input [63:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
+  output [63:0] o_tdata, output o_tlast, output o_tvalid, input o_tready
+);
+
+  generate
+    if (REGISTER) begin
+      axi_fifo_flop2 #(.WIDTH(65)) axi_fifo_flop (
+        .clk(clk), .reset(reset), .clear(clear),
+        .i_tdata({i_tlast,i_tdata}), .i_tvalid(i_tvalid), .i_tready(i_tready),
+        .o_tdata({o_tlast,o_tdata}), .o_tvalid(o_tvalid), .o_tready(o_tready),
+        .space(), .occupied());
+    end else begin
+      assign o_tdata  = i_tdata;
+      assign o_tlast  = i_tlast;
+      assign o_tvalid = i_tvalid;
+      assign i_tready = o_tready;
+    end
+  endgenerate
+
+  reg first_time, first_line, read_time;
+  wire [63:0] hdr, hdr_vita_time;
+  reg [63:0] hdr_reg, vita_time_reg;
+
+  always @(posedge clk) begin
+    if (reset | clear) begin
+      first_time    <= 1'b1;
+      first_line    <= 1'b1;
+      read_time     <= 1'b0;
+      hdr_reg       <= 64'd0;
+      vita_time_reg <= 64'd0;
+    end else begin
+      if (o_tvalid & o_tready) begin
+        first_time      <= 1'b0;
+        if (first_line) begin
+          hdr_reg       <= o_tdata;
+          first_line    <= 1'b0;
+          if (has_time & ~o_tlast) begin
+            read_time   <= 1'b1;
+          end
+        end
+        if (read_time) begin
+          vita_time_reg <= o_tdata;
+          read_time     <= 1'b0;
+        end
+        if (o_tlast) begin
+          first_line    <= 1'b1;
+        end
+      end
+    end
+  end
+
+  // REGISTER = 0: Always use o_tdata, output only valid when hdr_stb = 1
+  // REGISTER = 1: Mux to make sure header output is available immediately and also registered for rest of packet.
+  assign hdr            = (hdr_stb       | (REGISTER == 0)) ? o_tdata : hdr_reg;
+  assign hdr_vita_time  = (vita_time_stb | (REGISTER == 0)) ? o_tdata : vita_time_reg;
+
+  assign hdr_stb        = first_line & o_tvalid & o_tready;
+  assign pkt_type       = hdr[63:62];
+  assign has_time       = hdr[61];
+  assign eob            = hdr[60];
+  assign seqnum         = hdr[59:48];
+  assign length         = hdr[47:32];
+  assign payload_length = length - (has_time ? 16'd16 : 16'd8);
+  assign src_sid        = hdr[31:16];
+  assign dst_sid        = hdr[15:0];
+
+  assign vita_time_stb  = read_time & o_tvalid & o_tready;
+  assign vita_time      = hdr_vita_time;
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/data_types.vh b/fpga/usrp3/lib/rfnoc/data_types.vh
new file mode 100644
index 000000000..006deb9c2
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/data_types.vh
@@ -0,0 +1,23 @@
+// Number of bytes per word
+typedef struct {
+  string name;
+  int bytes_per_word;
+} cvita_data_type_t;
+localparam cvita_data_type_t U16  = '{name:"U16",  bytes_per_word:2};  // uint16
+localparam cvita_data_type_t U32  = '{name:"U32",  bytes_per_word:4};  // uint32
+localparam cvita_data_type_t U64  = '{name:"U64",  bytes_per_word:8};  // uint64
+localparam cvita_data_type_t U128 = '{name:"U128", bytes_per_word:16}; // uint128
+localparam cvita_data_type_t S8   = '{name:"S8",   bytes_per_word:1};  // int8
+localparam cvita_data_type_t S16  = '{name:"S16",  bytes_per_word:2};  // int16
+localparam cvita_data_type_t S32  = '{name:"S32",  bytes_per_word:4};  // int32
+localparam cvita_data_type_t S64  = '{name:"S64",  bytes_per_word:8};  // int64
+localparam cvita_data_type_t S128 = '{name:"S128", bytes_per_word:16}; // int128
+localparam cvita_data_type_t SC8  = '{name:"SC8",  bytes_per_word:2};  // complex int8
+localparam cvita_data_type_t SC12 = '{name:"SC12", bytes_per_word:3};  // complex int12
+localparam cvita_data_type_t SC16 = '{name:"SC16", bytes_per_word:4};  // complex int16
+localparam cvita_data_type_t SC32 = '{name:"SC32", bytes_per_word:8};  // complex int32
+localparam cvita_data_type_t SC64 = '{name:"SC64", bytes_per_word:16}; // complex int64
+localparam cvita_data_type_t F32  = '{name:"F32",  bytes_per_word:4};  // single precision float
+localparam cvita_data_type_t F64  = '{name:"F64",  bytes_per_word:8};  // double precision float
+localparam cvita_data_type_t FC32 = '{name:"FC32", bytes_per_word:8};  // single precision complex float
+localparam cvita_data_type_t FC64 = '{name:"FC64", bytes_per_word:16}; // double precision complex float
\ No newline at end of file
diff --git a/fpga/usrp3/lib/rfnoc/datapath_gatekeeper.v b/fpga/usrp3/lib/rfnoc/datapath_gatekeeper.v
new file mode 100644
index 000000000..0289c6c27
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/datapath_gatekeeper.v
@@ -0,0 +1,62 @@
+//
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Description:
+//   A gatekeeper module for data packets entering and leaving
+//   the user logic in an RFNoC block. This module keeps track
+//   of the packet count for software to detect activity and 
+//   provides a mechanism to flush packets from software. Useful
+//   to prevent slow-moving or misbehaving noc blocks from clogging
+//   up the infrastructure.
+
+module datapath_gatekeeper #(
+  parameter WIDTH   = 64,
+  parameter COUNT_W = 16
+)(
+  // Clocks and resets
+  input  wire               clk,
+  input  wire               reset,
+  // Input data stream      
+  input  wire [WIDTH-1:0]   s_axis_tdata,
+  input  wire               s_axis_tlast,
+  input  wire               s_axis_tvalid,
+  output wire               s_axis_tready,
+  // Output data stream     
+  output wire [WIDTH-1:0]   m_axis_tdata,
+  output wire               m_axis_tlast,
+  output wire               m_axis_tvalid,
+  input  wire               m_axis_tready,
+  // Settings and Status
+  input  wire               flush,          // Drop all packets coming into module
+  output wire               flushing,       // Is the module still dropping packets?
+  output wire [COUNT_W-1:0] pkt_count       // Input packet counter (includes drops)
+);
+
+  axis_strm_monitor #(
+    .WIDTH(1), .COUNT_W(COUNT_W),
+    .PKT_LENGTH_EN(0), .PKT_CHKSUM_EN(0),
+    .PKT_COUNT_EN(1), .XFER_COUNT_EN(0)
+  ) monitor_i (
+    .clk(clk), .reset(reset),
+    .axis_tdata(1'b0), .axis_tlast(s_axis_tlast),
+    .axis_tvalid(s_axis_tvalid), .axis_tready(s_axis_tready),
+    .sop(), .eop(),
+    .pkt_length(), .pkt_chksum(),
+    .pkt_count(pkt_count), .xfer_count()
+  );
+
+  axis_packet_flush #(
+    .WIDTH(WIDTH), .FLUSH_PARTIAL_PKTS(0),
+    .TIMEOUT_W(1), .PIPELINE("NONE")
+  ) flusher_i (
+    .clk(clk), .reset(reset),
+    .enable(flush), .timeout(1'b0), .flushing(flushing), .done(),
+    .s_axis_tdata(s_axis_tdata), .s_axis_tlast(s_axis_tlast),
+    .s_axis_tvalid(s_axis_tvalid), .s_axis_tready(s_axis_tready),
+    .m_axis_tdata(m_axis_tdata), .m_axis_tlast(m_axis_tlast),
+    .m_axis_tvalid(m_axis_tvalid), .m_axis_tready(m_axis_tready)
+  );
+
+endmodule
\ No newline at end of file
diff --git a/fpga/usrp3/lib/rfnoc/ddc.v b/fpga/usrp3/lib/rfnoc/ddc.v
new file mode 100644
index 000000000..a14f001ff
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/ddc.v
@@ -0,0 +1,635 @@
+//
+// Copyright 2016 Ettus Research
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+//! RFNoC specific digital down-conversion chain
+
+module ddc #(
+  parameter SR_FREQ_ADDR     = 0,
+  parameter SR_SCALE_IQ_ADDR = 1,
+  parameter SR_DECIM_ADDR    = 2,
+  parameter SR_MUX_ADDR      = 3,
+  parameter SR_COEFFS_ADDR   = 4,
+  parameter PRELOAD_HBS      = 1, // Preload half band filter state with 0s
+  parameter NUM_HB           = 3,
+  parameter CIC_MAX_DECIM    = 255,
+  parameter SAMPLE_WIDTH     = 16,
+  parameter WIDTH            = 24
+)(
+  input clk, input reset,
+  input clear, // Resets everything except the timed phase inc FIFO and phase inc
+  input set_stb, input [7:0] set_addr, input [31:0] set_data,
+  input timed_set_stb, input [7:0] timed_set_addr, input [31:0] timed_set_data,
+  input [31:0] sample_in_tdata,
+  input sample_in_tvalid,
+  input sample_in_tlast,
+  output sample_in_tready,
+  input sample_in_tuser,
+  input sample_in_eob,
+  output [31:0] sample_out_tdata,
+  output sample_out_tvalid,
+  input sample_out_tready,
+  output sample_out_tlast
+);
+
+  localparam  cwidth = 25;
+  localparam  zwidth = 24;
+
+  wire [31:0] sr_phase_inc, sr_phase_inc_timed_tdata;
+  wire sr_phase_inc_valid, sr_phase_inc_timed_tvalid, sr_phase_inc_timed_tready, sr_phase_inc_timed_tlast;
+  reg [31:0] phase_inc;
+  reg [31:0] phase;
+  reg phase_inc_valid;
+  
+  wire [SAMPLE_WIDTH*2-1:0] dds_in_tdata;
+  wire dds_in_tlast;
+  wire dds_in_tvalid;
+  wire dds_in_tready;
+  wire [SAMPLE_WIDTH*2-1:0] dds_in_fifo_tdata;
+  wire dds_in_fifo_tlast;
+  wire dds_in_fifo_tvalid;
+  wire dds_in_fifo_tready;
+  wire [WIDTH-1:0] dds_in_i_tdata;
+  wire [WIDTH-1:0] dds_in_q_tdata;  
+  wire [WIDTH-1:0] dds_out_i_tdata;
+  wire [WIDTH-1:0] dds_out_q_tdata;
+  
+  wire [SAMPLE_WIDTH*2-1:0] dds_in_sync_tdata;
+  wire dds_in_sync_tvalid, dds_in_sync_tready, dds_in_sync_tlast;
+  wire [WIDTH-1:0] phase_sync_tdata;
+  wire phase_sync_tvalid, phase_sync_tready, phase_sync_tlast;  
+
+  wire [WIDTH-1:0] phase_tdata = phase[31:32-WIDTH];
+  wire phase_tvalid, phase_tready, phase_tlast;
+  wire dds_out_tlast;
+  wire dds_out_tvalid;
+  wire [15:0] dds_input_fifo_space, dds_input_fifo_occupied;  
+
+  wire [17:0] scale_factor;
+  wire last_cic;
+  wire last_cic_decimate_in;
+  wire strobe_dds_clip;
+  wire [WIDTH-1:0] i_dds_clip, q_dds_clip;
+  wire [WIDTH-1:0] i_cic, q_cic;
+  wire [46:0] i_hb1, q_hb1;
+  wire [46:0] i_hb2, q_hb2;
+  wire [47:0] i_hb3, q_hb3;
+  wire sample_out_stb;
+
+  wire strobe_cic, strobe_hb1, strobe_hb2, strobe_hb3;
+  wire ddc_chain_tready;
+
+  reg [7:0] cic_decim_rate;
+  wire [7:0] cic_decim_rate_int;
+  wire rate_changed;
+
+  wire [SAMPLE_WIDTH-1:0] sample_in_i = {sample_in_tdata[31:16]};
+  wire [SAMPLE_WIDTH-1:0] sample_in_q = {sample_in_tdata[15:0]};
+
+  wire sample_mux_tready;
+  wire sample_mux_set_freq;
+  wire [SAMPLE_WIDTH-1:0] sample_mux_i, sample_mux_q;
+  wire realmode;
+  wire swap_iq;
+
+  reg [1:0] hb_rate;
+  wire [1:0] hb_rate_int;
+  wire [2:0] enable_hb = { hb_rate == 2'b11, hb_rate[1] == 1'b1, hb_rate != 2'b00 };
+
+  wire reload_go, reload_we1, reload_we2, reload_we3, reload_ld1, reload_ld2, reload_ld3;
+  wire [17:0] coef_din;
+
+  //phase incr settings regs and mux.
+  setting_reg #(.my_addr(SR_FREQ_ADDR)) set_freq (
+    .clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+    .in(set_data),.out(sr_phase_inc),.changed(sr_phase_inc_valid));
+
+  assign sr_phase_inc_timed_tready = sample_in_tvalid & sample_in_tready & sample_mux_set_freq;
+
+  axi_setting_reg #(
+    .ADDR(SR_FREQ_ADDR),
+    .USE_FIFO(1),
+    .FIFO_SIZE(5))
+  set_freq_timed (
+    .clk(clk), .reset(reset), .error_stb(),
+    .set_stb(timed_set_stb), .set_addr(timed_set_addr), .set_data(timed_set_data),
+    .o_tdata(sr_phase_inc_timed_tdata), .o_tlast(sr_phase_inc_timed_tlast), .o_tvalid(sr_phase_inc_timed_tvalid),
+    .o_tready(sr_phase_inc_timed_tready));
+
+  // Load phase increment depending on whether or not the settings bus write is
+  // a timed command. Non-timed commands get priority.
+  always @(posedge clk) begin
+    if (reset) begin
+      phase_inc <= 'd0;
+      phase_inc_valid <= 'd0;
+    end else begin
+      if (sr_phase_inc_valid) begin
+        phase_inc <= sr_phase_inc;
+        phase_inc_valid <= sr_phase_inc_valid;
+      end else if (sr_phase_inc_timed_tvalid & sr_phase_inc_timed_tready) begin
+        phase_inc <= sr_phase_inc_timed_tdata;
+        phase_inc_valid <= sr_phase_inc_timed_tvalid;
+      end else
+        phase_inc_valid <= 1'b0;
+    end
+  end
+
+  setting_reg #(.my_addr(SR_SCALE_IQ_ADDR), .width(18)) set_scale_iq (
+    .clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+    .in(set_data),.out(scale_factor),.changed());
+
+  setting_reg #(.my_addr(SR_DECIM_ADDR), .width(10), .at_reset(1 /* No decimation */)) set_decim (
+    .clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+    .in(set_data),.out({hb_rate_int, cic_decim_rate_int}),.changed(rate_changed));
+
+  setting_reg #(.my_addr(SR_MUX_ADDR), .width(2)) set_mux (
+    .clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+    .in(set_data),.out({realmode,swap_iq}),.changed());
+
+  setting_reg #(.my_addr(SR_COEFFS_ADDR), .width(24)) set_coeffs (
+    .clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+    .in(set_data),.out({reload_ld3,reload_we3,reload_ld2,reload_we2,reload_ld1,reload_we1,coef_din}),.changed(reload_go));
+
+  // Prevent changing rate while processing samples as this
+  // will corrupt the output
+  reg active, rate_changed_hold, rate_changed_stb;
+  always @(posedge clk) begin
+    if (reset) begin
+      active            <= 1'b0;
+      rate_changed_hold <= 1'b0;
+      rate_changed_stb  <= 1'b0;
+      cic_decim_rate    <= 'd1;
+      hb_rate           <= 'd0;
+    end else begin
+      if (clear) begin
+        active <= 1'b0;
+      end else if (sample_in_tvalid & sample_in_tready) begin
+        active <= 1'b1;
+      end
+      if (rate_changed & active) begin
+        rate_changed_hold <= 1'b1;
+      end
+      if ((clear | ~active) & (rate_changed | rate_changed_hold)) begin
+        rate_changed_hold <= 1'b0;
+        rate_changed_stb  <= 1'b1;
+        cic_decim_rate    <= cic_decim_rate_int;
+        hb_rate           <= hb_rate_int;
+      end else begin
+        rate_changed_stb  <= 1'b0;
+      end
+    end
+  end
+
+
+  //doesn't need to be registered and now can have back pressure from dds
+  assign sample_mux_set_freq = sample_in_tuser;
+  assign sample_mux_i = swap_iq ? sample_in_q : sample_in_i;
+  assign sample_mux_q = realmode ? 'd0 : (swap_iq ? sample_in_i : sample_in_q);
+
+  /** Phase accumulator, Xilinx DDS/Complex Mult **/
+  
+  //connect samples to dds
+  assign dds_in_tdata = {sample_mux_i,sample_mux_q};
+  assign dds_in_tvalid = sample_in_tvalid & ddc_chain_tready; //if the rest of the chain isn't ready, then halt all data flow. this should help with rate changes...
+  assign dds_in_tlast = sample_in_tlast;
+  assign sample_in_tready = dds_in_tready & ddc_chain_tready;
+ 
+  assign phase_tvalid = dds_in_tvalid;
+  assign phase_tlast = dds_in_tlast;
+ 
+   // NCO
+  always @(posedge clk) begin
+    if (reset | clear | (phase_inc_valid & sr_phase_inc_timed_tready) | sample_in_eob) begin
+      phase <= 0;
+    end else if (dds_in_tvalid & dds_in_tready) begin //only increment phase when data is ready
+      phase <= phase + phase_inc;
+    end
+  end
+
+  // Sync the two path's pipeline delay.
+  // This is needed to ensure that applying the phase update happens on the
+  // correct sample regardless of differing downstream path delays.
+  axi_sync #(
+    .SIZE(2),
+    .WIDTH_VEC({WIDTH,2*SAMPLE_WIDTH}), // Vector of widths, each width is defined by a 32-bit value
+    .FIFO_SIZE(0))
+  axi_sync (
+    .clk(clk), .reset(reset), .clear(clear),
+    .i_tdata({phase_tdata,dds_in_tdata}),
+    .i_tlast({phase_tlast,dds_in_tlast}),
+    .i_tvalid({phase_tvalid,dds_in_tvalid}),
+    .i_tready({phase_tready,dds_in_tready}),
+    .o_tdata({phase_sync_tdata,dds_in_sync_tdata}),
+    .o_tlast({phase_sync_tlast,dds_in_sync_tlast}),
+    .o_tvalid({phase_sync_tvalid,dds_in_sync_tvalid}),
+    .o_tready({phase_sync_tready,dds_in_sync_tready}));
+
+  //hold data to align with dds pipelining  
+  axi_fifo #(.WIDTH(2*SAMPLE_WIDTH+1), .SIZE(5)) dds_input_fifo
+    (.clk(clk), .reset(reset), .clear(clear),
+    .i_tdata({dds_in_sync_tlast,dds_in_sync_tdata}), .i_tvalid(dds_in_sync_tvalid), .i_tready(dds_in_sync_tready),
+    .o_tdata({dds_in_fifo_tlast,dds_in_fifo_tdata}), .o_tvalid(dds_in_fifo_tvalid), .o_tready(dds_in_fifo_tready),
+    .space(dds_input_fifo_space), .occupied(dds_input_fifo_occupied)
+    );
+        
+  // after fifo, do q quick sign extend op to get up to 24 bits. to match how the dds deals with the data path.
+  // add extra bits to fit the dds width, 5 bits added here
+  sign_extend #(
+    .bits_in(SAMPLE_WIDTH), .bits_out(WIDTH))
+  sign_extend_dds_i (
+    .in({dds_in_fifo_tdata[2*SAMPLE_WIDTH-1:SAMPLE_WIDTH]}), .out(dds_in_i_tdata));
+
+  sign_extend #(
+    .bits_in(SAMPLE_WIDTH), .bits_out(WIDTH))
+  sign_extend_dds_q (
+    .in({dds_in_fifo_tdata[SAMPLE_WIDTH-1:0]}), .out(dds_in_q_tdata));      
+  
+  
+  dds_freq_tune dds_freq_tune_inst (
+    .clk(clk),
+    .reset(reset | clear),
+    .eob(sample_in_eob),
+    .rate_changed(rate_changed_hold),
+    .dds_input_fifo_occupied(dds_input_fifo_occupied),
+    /* IQ input */
+    .s_axis_din_tlast(dds_in_fifo_tlast),
+    .s_axis_din_tvalid(dds_in_fifo_tvalid),
+    .s_axis_din_tready(dds_in_fifo_tready),
+    .s_axis_din_tdata({dds_in_q_tdata, dds_in_i_tdata}), //48 = WIDTH*2
+    /* Phase input from NCO */
+    .s_axis_phase_tvalid(phase_sync_tvalid),
+    .s_axis_phase_tready(phase_sync_tready), // used in the axi_sync
+    .s_axis_phase_tlast(phase_sync_tlast),
+    .s_axis_phase_tdata(phase_sync_tdata), //24 bit = WIDTH
+    /* IQ output */
+    .m_axis_dout_tlast(dds_out_tlast),
+    .m_axis_dout_tvalid(dds_out_tvalid),
+    .m_axis_dout_tready(ddc_chain_tready), 
+    .m_axis_dout_tdata({dds_out_q_tdata, dds_out_i_tdata})
+        
+  );
+
+   //48 = WIDTH*2
+  //chop off top byte because it's not actually used and we want to match expected gain/bit use found in freq shift
+  assign i_dds_clip = {dds_out_i_tdata[15:0],8'h00};
+  assign q_dds_clip = {dds_out_q_tdata[15:0],8'h00};
+  assign strobe_dds_clip = dds_out_tvalid & sample_out_tready;
+  assign last_cic_decimate_in = dds_out_tlast;
+  
+  /** CIC DECIMATE **/
+  cic_decimate #(.WIDTH(WIDTH), .N(4), .MAX_RATE(CIC_MAX_DECIM)) cic_decimate_i (
+    .clk(clk), .reset(reset | clear),
+    .rate_stb(rate_changed_stb), .rate(cic_decim_rate), .strobe_in(strobe_dds_clip), .strobe_out(strobe_cic),
+    .last_in(last_cic_decimate_in), .last_out(last_cic), .signal_in(i_dds_clip), .signal_out(i_cic));
+
+  cic_decimate #(.WIDTH(WIDTH), .N(4), .MAX_RATE(CIC_MAX_DECIM)) cic_decimate_q (
+    .clk(clk), .reset(reset | clear),
+    .rate_stb(rate_changed_stb), .rate(cic_decim_rate), .strobe_in(strobe_dds_clip), .strobe_out(),
+    .last_in(1'b0), .last_out(), .signal_in(q_dds_clip), .signal_out(q_cic));
+
+  // Halfbands
+  wire nd1, nd2, nd3;
+  wire rfd1, rfd2, rfd3;
+  wire rdy1, rdy2, rdy3;
+  wire data_valid1, data_valid2, data_valid3;
+
+  localparam HB1_SCALE = 18;
+  localparam HB2_SCALE = 18;
+  localparam HB3_SCALE = 18;
+
+  // Track last sample as it propagates through the half band filters
+  // Note: Delays calibrated for specific pipeline delay in each hb filter
+  reg [5:0] hb1_in_cnt, hb2_in_cnt, hb3_in_cnt;
+  reg [4:0] hb1_out_cnt, hb2_out_cnt, hb3_out_cnt;
+  reg [4:0] hb1_last_cnt, hb2_last_cnt, hb3_last_cnt;
+  reg hb1_last_set, hb2_last_set, hb3_last_set;
+  reg last_hb1, last_hb2, last_hb3;
+  always @(posedge clk) begin
+    if (reset | clear) begin
+      hb1_in_cnt   <= 'd0;
+      hb2_in_cnt   <= 'd0;
+      hb3_in_cnt   <= 'd0;
+      hb1_out_cnt  <= 'd0;
+      hb2_out_cnt  <= 'd0;
+      hb3_out_cnt  <= 'd0;
+      hb1_last_cnt <= 'd0;
+      hb2_last_cnt <= 'd0;
+      hb3_last_cnt <= 'd0;
+      hb1_last_set <= 1'b0;
+      hb2_last_set <= 1'b0;
+      hb3_last_set <= 1'b0;
+      last_hb1     <= 1'b0;
+      last_hb2     <= 1'b0;
+      last_hb3     <= 1'b0;
+    end else begin
+      // HB1
+      if (strobe_cic & rfd1) begin
+        hb1_in_cnt     <= hb1_in_cnt + 1'b1;
+        if (last_cic) begin
+          hb1_last_set <= 1'b1;
+          hb1_last_cnt <= hb1_in_cnt[5:1];
+        end
+      end
+      if (strobe_hb1) begin
+        hb1_out_cnt    <= hb1_out_cnt + 1'b1;
+      end
+      // Avoid subtracting 1 from hb1_last_cnt by initializing hb1_out_cnt = 1
+      if (hb1_last_set & (hb1_out_cnt == hb1_last_cnt)) begin
+        last_hb1       <= 1'b1;
+        hb1_last_set   <= 1'b0;
+        hb1_last_cnt   <= 'd0;
+      end else if (last_hb1 & strobe_hb1 & rfd2) begin
+        last_hb1       <= 1'b0;
+      end
+      // HB2
+      if (strobe_hb1 & rfd2) begin
+        hb2_in_cnt   <= hb2_in_cnt + 1'b1;
+        if (last_hb1) begin
+          hb2_last_set <= 1'b1;
+          hb2_last_cnt <= hb2_in_cnt[5:1];
+        end
+      end
+      if (strobe_hb2) begin
+        hb2_out_cnt    <= hb2_out_cnt + 1'b1;
+      end
+      if (hb2_last_set & (hb2_out_cnt == hb2_last_cnt)) begin
+        last_hb2       <= 1'b1;
+        hb2_last_set   <= 1'b0;
+        hb2_last_cnt   <= 'd0;
+      end else if (last_hb2 & strobe_hb2 & rfd3) begin
+        last_hb2       <= 1'b0;
+      end
+      // HB3
+      if (strobe_hb2 & rfd3) begin
+        hb3_in_cnt     <= hb3_in_cnt + 1'b1;
+        if (last_hb2) begin
+          hb3_last_set <= 1'b1;
+          hb3_last_cnt <= hb3_in_cnt[5:1];
+        end
+      end
+      if (strobe_hb3) begin
+        hb3_out_cnt    <= hb3_out_cnt + 1'b1;
+      end
+      if (hb3_last_set & (hb3_out_cnt == hb3_last_cnt)) begin
+        last_hb3       <= 1'b1;
+        hb3_last_set   <= 1'b0;
+        hb3_last_cnt   <= 'd0;
+      end else if (last_hb3 & strobe_hb3) begin
+        last_hb3       <= 1'b0;
+      end
+    end
+  end
+
+  // Each filter will accept N-1 samples before outputting
+  // a sample. This logic "preloads" the pipeline with 0s
+  // so the first sample in pushes out a sample.
+  reg [5:0] hb1_cnt, hb2_cnt, hb3_cnt;
+  reg hb1_en, hb2_en, hb3_en, hb1_rdy, hb2_rdy, hb3_rdy;
+  generate
+    if (PRELOAD_HBS) begin
+      always @(posedge clk) begin
+        if (reset | clear) begin
+          hb1_cnt <= 0;
+          hb2_cnt <= 0;
+          hb3_cnt <= 0;
+          hb1_en  <= 1'b1;
+          hb2_en  <= 1'b1;
+          hb3_en  <= 1'b1;
+          hb1_rdy <= 1'b0;
+          hb2_rdy <= 1'b0;
+          hb3_rdy <= 1'b0;
+        end else begin
+          if (hb1_en & rfd1) begin
+            if (hb1_cnt < 47) begin
+              hb1_cnt <= hb1_cnt + 1;
+            end else begin
+              hb1_en  <= 1'b0;
+            end
+          end
+          if (data_valid1) begin
+            hb1_rdy   <= 1'b1;
+          end
+          if (hb2_en & rfd2) begin
+            if (hb2_cnt < 47) begin
+              hb2_cnt <= hb2_cnt + 1;
+            end else begin
+              hb2_en  <= 1'b0;
+            end
+          end
+          if (data_valid2) begin
+            hb2_rdy   <= 1'b1;
+          end
+          if (hb3_en & rfd3) begin
+            if (hb3_cnt < 63) begin
+              hb3_cnt <= hb3_cnt + 1;
+            end else begin
+              hb3_en  <= 1'b0;
+            end
+          end
+          if (data_valid3) begin
+            hb3_rdy   <= 1'b1;
+          end
+        end
+      end
+    end else begin
+      always @(*) begin
+        hb1_en  <= 1'b0;
+        hb2_en  <= 1'b0;
+        hb3_en  <= 1'b0;
+        hb1_rdy <= 1'b1;
+        hb2_rdy <= 1'b1;
+        hb3_rdy <= 1'b1;
+      end
+    end
+  endgenerate
+
+  assign ddc_chain_tready = sample_out_tready & hb1_rdy & hb2_rdy & hb3_rdy;
+
+  assign strobe_hb1 = data_valid1 & hb1_rdy;
+  assign strobe_hb2 = data_valid2 & hb2_rdy;
+  assign strobe_hb3 = data_valid3 & hb3_rdy;
+  assign nd1 = strobe_cic | hb1_en;
+  assign nd2 = strobe_hb1 | hb2_en;
+  assign nd3 = strobe_hb2 | hb3_en;
+  generate //no point in using a for loop generate because each hb is different.
+  if( NUM_HB > 0) begin
+    hbdec1 hbdec1 (
+      .clk(clk), // input clk
+      .sclr(reset | clear), // input sclr
+      .ce(1'b1), // input ce
+      .coef_ld(reload_go & reload_ld1), // input coef_ld
+      .coef_we(reload_go & reload_we1), // input coef_we
+      .coef_din(coef_din), // input [17 : 0] coef_din
+      .rfd(rfd1), // output rfd
+      .nd(nd1), // input nd
+      .din_1(i_cic), // input [23 : 0] din_1
+      .din_2(q_cic), // input [23 : 0] din_2
+      .rdy(rdy1), // output rdy
+      .data_valid(data_valid1), // output data_valid
+      .dout_1(i_hb1), // output [46 : 0] dout_1
+      .dout_2(q_hb1)); // output [46 : 0] dout_2
+  end else begin //if (NUM_HB <= 2)
+    assign rdy1 = 1'b1;
+    assign rfd1 = 1'b1;
+    assign data_valid1 = 1'b1;
+    assign i_hb1 = 'h0;
+    assign q_hb1 = 'h0;
+  end
+  if( NUM_HB > 1) begin
+    hbdec2 hbdec2 (
+      .clk(clk), // input clk
+      .sclr(reset | clear), // input sclr
+      .ce(1'b1), // input ce
+      .coef_ld(reload_go & reload_ld2), // input coef_ld
+      .coef_we(reload_go & reload_we2), // input coef_we
+      .coef_din(coef_din), // input [17 : 0] coef_din
+      .rfd(rfd2), // output rfd
+      .nd(nd2), // input nd
+      .din_1(i_hb1[23+HB1_SCALE:HB1_SCALE]), // input [23 : 0] din_1
+      .din_2(q_hb1[23+HB1_SCALE:HB1_SCALE]), // input [23 : 0] din_2
+      .rdy(rdy2), // output rdy
+      .data_valid(data_valid2), // output data_valid
+      .dout_1(i_hb2), // output [46 : 0] dout_1
+      .dout_2(q_hb2)); // output [46 : 0] dout_2
+  end else begin //if (NUM_HB <= 2)
+    assign rdy2 = 1'b1;
+    assign rfd2 = 1'b1;
+    assign data_valid2 = 1'b1;
+    assign i_hb2 = 'h0;
+    assign q_hb2 = 'h0;
+  end
+  if( NUM_HB > 2) begin
+    hbdec3 hbdec3 (
+      .clk(clk), // input clk
+      .sclr(reset | clear), // input sclr
+      .ce(1'b1), // input ce
+      .coef_ld(reload_go & reload_ld3), // input coef_ld
+      .coef_we(reload_go & reload_we3), // input coef_we
+      .coef_din(coef_din), // input [17 : 0] coef_din
+      .rfd(rfd3), // output rfd
+      .nd(nd3), // input nd
+      .din_1(i_hb2[23+HB2_SCALE:HB2_SCALE]), // input [23 : 0] din_1
+      .din_2(q_hb2[23+HB2_SCALE:HB2_SCALE]), // input [23 : 0] din_2
+      .rdy(rdy3), // output rdy
+      .data_valid(data_valid3), // output data_valid
+      .dout_1(i_hb3), // output [47 : 0] dout_1
+      .dout_2(q_hb3)); // output [47 : 0] dout_2
+  end else begin //if (NUM_HB <= 2)
+    assign rdy3 = 1'b1;
+    assign rfd3 = 1'b1;
+    assign data_valid3 = 1'b1;
+    assign i_hb3 = 'h0;
+    assign q_hb3 = 'h0;
+  end
+  endgenerate
+  reg [23:0] i_unscaled, q_unscaled;
+  reg strobe_unscaled;
+  reg last_unscaled;
+  //this state machine must be changed if the user wants 4 hbs
+  always @(posedge clk) begin
+    if (reset | clear) begin
+      i_unscaled <= 'd0;
+      q_unscaled <= 'd0;
+      last_unscaled <= 1'b0;
+      strobe_unscaled <= 1'b0;
+    end else begin
+      case(hb_rate)
+        2'd0 : begin
+          last_unscaled <= last_cic;
+          strobe_unscaled <= strobe_cic;
+          i_unscaled <= i_cic[23:0];
+          q_unscaled <= q_cic[23:0];
+        end
+        2'd1 : begin
+          last_unscaled <= last_hb1;
+          strobe_unscaled <= strobe_hb1;
+          i_unscaled <= i_hb1[23+HB1_SCALE:HB1_SCALE];
+          q_unscaled <= q_hb1[23+HB1_SCALE:HB1_SCALE];
+        end
+        2'd2 : begin
+          last_unscaled <= last_hb2;
+          strobe_unscaled <= strobe_hb2;
+          i_unscaled <= i_hb2[23+HB2_SCALE:HB2_SCALE];
+          q_unscaled <= q_hb2[23+HB2_SCALE:HB2_SCALE];
+        end
+        2'd3 : begin
+          last_unscaled <= last_hb3;
+          strobe_unscaled <= strobe_hb3;
+          i_unscaled <= i_hb3[23+HB3_SCALE:HB3_SCALE];
+          q_unscaled <= q_hb3[23+HB3_SCALE:HB3_SCALE];
+        end
+      endcase // case (hb_rate)
+    end
+  end
+
+  wire [42:0] i_scaled, q_scaled;
+  wire [23:0] i_clip, q_clip;
+  reg         strobe_scaled;
+  reg         last_scaled;
+  wire        strobe_clip;
+  reg [1:0]   last_clip;
+
+  MULT_MACRO #(
+    .DEVICE("7SERIES"),     // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6","7SERIES"
+    .LATENCY(1),            // Desired clock cycle latency, 0-4
+    .WIDTH_A(25),           // Multiplier A-input bus width, 1-25
+    .WIDTH_B(18))           // Multiplier B-input bus width, 1-18
+  SCALE_I (.P(i_scaled),    // Multiplier output bus, width determined by WIDTH_P parameter
+    .A({i_unscaled[23],i_unscaled}),     // Multiplier input A bus, width determined by WIDTH_A parameter
+    .B(scale_factor),                    // Multiplier input B bus, width determined by WIDTH_B parameter
+    .CE(strobe_unscaled),   // 1-bit active high input clock enable
+    .CLK(clk),              // 1-bit positive edge clock input
+    .RST(reset | clear));   // 1-bit input active high reset
+
+  MULT_MACRO #(
+    .DEVICE("7SERIES"),     // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6","7SERIES"
+    .LATENCY(1),            // Desired clock cycle latency, 0-4
+    .WIDTH_A(25),           // Multiplier A-input bus width, 1-25
+    .WIDTH_B(18))           // Multiplier B-input bus width, 1-18
+   SCALE_Q (.P(q_scaled),   // Multiplier output bus, width determined by WIDTH_P parameter
+    .A({q_unscaled[23],q_unscaled}),     // Multiplier input A bus, width determined by WIDTH_A parameter
+    .B(scale_factor),                    // Multiplier input B bus, width determined by WIDTH_B parameter
+    .CE(strobe_unscaled),   // 1-bit active high input clock enable
+    .CLK(clk),              // 1-bit positive edge clock input
+    .RST(reset | clear));   // 1-bit input active high reset
+
+  wire [31:0] sample_out;
+  reg sample_out_last;
+
+  always @(posedge clk) begin
+    if (reset | clear) begin
+      strobe_scaled   <= 1'b0;
+      last_scaled     <= 1'b0;
+      last_clip       <= 'd0;
+      sample_out_last <= 1'b0;
+    end else begin
+      strobe_scaled   <= strobe_unscaled;
+      last_scaled     <= last_unscaled;
+      last_clip[1:0]  <= {last_clip[0], last_scaled};
+      sample_out_last <= last_clip[1];
+    end
+  end
+
+  clip_reg #(.bits_in(29), .bits_out(24), .STROBED(1)) clip_i (
+    .clk(clk), .reset(reset | clear), .in(i_scaled[42:14]), .strobe_in(strobe_scaled), .out(i_clip), .strobe_out(strobe_clip));
+  clip_reg #(.bits_in(29), .bits_out(24), .STROBED(1)) clip_q (
+    .clk(clk), .reset(reset | clear), .in(q_scaled[42:14]), .strobe_in(strobe_scaled), .out(q_clip), .strobe_out());
+
+  round_sd #(.WIDTH_IN(24), .WIDTH_OUT(16), .DISABLE_SD(1)) round_i (
+    .clk(clk), .reset(reset | clear), .in(i_clip), .strobe_in(strobe_clip), .out(sample_out[31:16]), .strobe_out(sample_out_stb));
+  round_sd #(.WIDTH_IN(24), .WIDTH_OUT(16), .DISABLE_SD(1)) round_q (
+    .clk(clk), .reset(reset | clear), .in(q_clip), .strobe_in(strobe_clip), .out(sample_out[15:0]), .strobe_out());
+
+  //FIFO_SIZE = 8 infers a bram fifo
+  strobed_to_axi #(
+    .WIDTH(32),
+    .FIFO_SIZE(8))
+  strobed_to_axi (
+    .clk(clk), .reset(reset), .clear(clear),
+    .in_stb(sample_out_stb), .in_data(sample_out), .in_last(sample_out_last),
+    .o_tdata(sample_out_tdata), .o_tlast(sample_out_tlast), .o_tvalid(sample_out_tvalid), .o_tready(sample_out_tready));
+
+endmodule // ddc_chain
diff --git a/fpga/usrp3/lib/rfnoc/dds_freq_tune.v b/fpga/usrp3/lib/rfnoc/dds_freq_tune.v
new file mode 100644
index 000000000..2491c01a1
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/dds_freq_tune.v
@@ -0,0 +1,208 @@
+//
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// DDS frequency shift with complex multiply
+
+module dds_freq_tune  #(
+  parameter WIDTH = 24,
+  parameter PHASE_WIDTH = 24,
+  parameter SIN_COS_WIDTH = 16,
+  parameter OUTPUT_WIDTH = 24
+)(
+  input         clk,
+  input         reset,
+  input         eob,
+  input         rate_changed,
+  input [15:0]  dds_input_fifo_occupied,
+  /* IQ input */
+  input [WIDTH*2-1:0]  s_axis_din_tdata,
+  input         s_axis_din_tlast,
+  input         s_axis_din_tvalid,
+  output        s_axis_din_tready,
+  /* Phase input from NCO */
+  input [PHASE_WIDTH-1:0]  s_axis_phase_tdata,
+  input         s_axis_phase_tlast,
+  input         s_axis_phase_tvalid,
+  output        s_axis_phase_tready,
+  /* IQ output */
+  output [OUTPUT_WIDTH*2-1:0] m_axis_dout_tdata,
+  output        m_axis_dout_tlast,
+  output        m_axis_dout_tvalid,
+  input         m_axis_dout_tready,
+
+  //debug signals
+  output [2:0] state_out,
+  output phase_valid_hold_out,
+  output [7:0] phase_invalid_wait_count_out,
+  output reset_dds_out,
+  output m_axis_dds_tlast_out,
+  output m_axis_dds_tvalid_out,
+  output m_axis_dds_tready_out,
+  output [SIN_COS_WIDTH*2-1:0] m_axis_dds_tdata_out //[31:16] = sin|q [15:0] cos|i
+);
+
+  //wires for dds output
+  wire m_axis_dds_tlast;
+  wire m_axis_dds_tvalid;
+  wire m_axis_dds_tready;
+  wire [SIN_COS_WIDTH*2-1:0] m_axis_dds_tdata; //[31:16] = sin|q [15:0] cos|i
+  reg reset_reg;
+  reg phase_valid_hold;
+  reg [7:0] phase_invalid_wait_count;
+  reg [2:0] state;
+  reg reset_dds     = 1'b1;  // Init DDS resets to 1, since simulation model 
+  reg reset_dds_reg = 1'b1;  // requires reset at time 0 to avoid failure.
+  reg phase_ready_wait;
+  wire s_axis_phase_tready_dds;
+
+  //when we're holding valid, make ready low so no new data comes in.
+  assign s_axis_phase_tready = s_axis_phase_tready_dds & ~phase_valid_hold;
+
+  localparam INIT = 3'b000;
+  localparam VALID = 3'b001;
+  localparam WAIT = 3'b010;
+  localparam HOLD_VALID = 3'b011;
+
+  //reset needs to be 2 clk cycles minimum for Xilinx DDS IP
+  always @(posedge clk) begin
+    reset_reg <= reset;
+    reset_dds_reg <= reset_dds;
+  end
+
+  //some logic to reset the dds when data is goes from valid to not valid
+  //also holds valid high until the pipeline has passed tlast through.
+  always @(posedge clk) begin
+    if(reset) begin
+      state <= INIT;
+      phase_valid_hold <= 1'b0;
+      phase_invalid_wait_count <= 16'h00;
+      reset_dds <= 1'b0;
+    end
+    else begin
+      case(state)
+        INIT: begin//init case
+          phase_valid_hold <= 1'b0;
+          phase_invalid_wait_count <= 16'h0000;
+          reset_dds <= 1'b0;
+          if(s_axis_phase_tvalid) begin
+            state <= VALID;
+          end
+        end
+        VALID: begin //valid data
+          if(~s_axis_phase_tvalid) begin
+            state <= WAIT;
+          end
+        end
+        WAIT: begin //wait until we either get valid data or don't
+          if(m_axis_dds_tready) begin //only increment when the downstream can accept data.
+            phase_invalid_wait_count <= phase_invalid_wait_count + 4'b1;
+          end
+          if(s_axis_phase_tvalid) begin //if we get valid data shortly after, then don't push data through and reset
+            state <= INIT;
+          end else begin
+            if(eob | (phase_invalid_wait_count >= 16'h40) | rate_changed ) begin //if a valid never comes, aka eob
+              state <= HOLD_VALID;
+            end
+          end
+        end
+        HOLD_VALID: begin//hold valid to finish pipeline. Apparently the dds IP won't empty without additional valids.
+          phase_valid_hold <= 1'b1;
+          // Wait for input FIFO to be empty
+          if (~s_axis_din_tvalid) begin
+            state <= INIT;
+            reset_dds <= 1'b1;
+          end
+        end
+      endcase
+    end
+  end
+
+  //dds to generate sin/cos data from phase
+  dds_sin_cos_lut_only dds_inst (
+    .aclk(clk),                                // input wire aclk
+    .aresetn(~(reset | reset_reg | reset_dds | reset_dds_reg)),            // input wire aresetn active low rst
+    .s_axis_phase_tvalid(s_axis_phase_tvalid | phase_valid_hold),  // input wire s_axis_phase_tvalid
+    .s_axis_phase_tready(s_axis_phase_tready_dds),  // output wire s_axis_phase_tready
+    .s_axis_phase_tlast(s_axis_phase_tlast),     //tlast
+    .s_axis_phase_tdata(s_axis_phase_tdata),    // input wire [23 : 0] s_axis_phase_tdata
+    .m_axis_data_tvalid(m_axis_dds_tvalid),    // output wire m_axis_data_tvalid
+    .m_axis_data_tready(m_axis_dds_tready),    // input wire m_axis_data_tready
+    .m_axis_data_tlast(m_axis_dds_tlast),      // input wire m_axis_data_tready
+    .m_axis_data_tdata(m_axis_dds_tdata)      // output wire [31 : 0] m_axis_data_tdata
+  );
+
+  wire [WIDTH*2-1:0] mult_in_a_tdata;
+  wire mult_in_a_tvalid;
+  wire mult_in_a_tready;
+  wire mult_in_a_tlast;
+  wire [SIN_COS_WIDTH*2-1:0] mult_in_b_tdata;
+  wire mult_in_b_tvalid;
+  wire mult_in_b_tready;
+  wire mult_in_b_tlast; //no connect
+  wire [2*32-1:0] mult_out_tdata;
+  wire mult_out_tvalid;
+  wire mult_out_tready;
+  wire mult_out_tlast;
+
+  axi_sync #(
+    .SIZE(2),
+    .WIDTH_VEC({SIN_COS_WIDTH*2, WIDTH*2}),
+    .FIFO_SIZE(0))
+  axi_sync (
+    .clk(clk), .reset(reset), .clear(),
+    .i_tdata({m_axis_dds_tdata,s_axis_din_tdata}),
+    .i_tlast({m_axis_dds_tlast,s_axis_din_tlast}),
+    .i_tvalid({m_axis_dds_tvalid,s_axis_din_tvalid}),
+    .i_tready({m_axis_dds_tready,s_axis_din_tready}),
+    .o_tdata({mult_in_b_tdata,mult_in_a_tdata}),
+    .o_tlast({mult_in_b_tlast,mult_in_a_tlast}),
+    .o_tvalid({mult_in_b_tvalid,mult_in_a_tvalid}),
+    .o_tready({mult_in_b_tready,mult_in_a_tready}));
+
+  //a = input i/q data stream 48 bit i/q lower bits i, upper bits q
+  //b = output of dds 32 bit cos/sin. lower cos, upper sin
+  complex_multiplier_dds complex_mult_inst (
+    .aclk(clk),                              // input wire aclk
+    .aresetn(~(reset | reset_reg)),                        // input wire aresetn
+    .s_axis_a_tvalid(mult_in_a_tvalid),        // input wire s_axis_a_tvalid
+    .s_axis_a_tready(mult_in_a_tready),        // output wire s_axis_a_tready
+    .s_axis_a_tlast(mult_in_a_tlast),          // input wire s_axis_a_tlast
+    .s_axis_a_tdata({mult_in_a_tdata}),          // input wire [47 : 0] s_axis_a_tdata
+    .s_axis_b_tvalid(mult_in_b_tvalid),        // input wire s_axis_b_tvalid
+    .s_axis_b_tready(mult_in_b_tready),        // output wire s_axis_b_tready
+    .s_axis_b_tlast(mult_in_b_tlast),        // output wire s_axis_b_tlast
+    .s_axis_b_tdata(mult_in_b_tdata),          // input wire [31 : 0] s_axis_b_tdata
+    .m_axis_dout_tvalid(mult_out_tvalid),  // output wire m_axis_dout_tvalid
+    .m_axis_dout_tready(mult_out_tready),  // input wire m_axis_dout_tready
+    .m_axis_dout_tlast(mult_out_tlast),    // output wire m_axis_dout_tlast
+    .m_axis_dout_tdata(mult_out_tdata)    // output wire [63 : 0] m_axis_dout_tdata
+  );
+
+  axi_round_complex #(
+    .WIDTH_IN(32),
+    .WIDTH_OUT(OUTPUT_WIDTH))
+  axi_round_complex_inst (
+    .clk(clk),
+    .reset(reset | reset_reg),
+    .i_tdata(mult_out_tdata),
+    .i_tlast(mult_out_tlast),
+    .i_tvalid(mult_out_tvalid),
+    .i_tready(mult_out_tready),
+    .o_tdata(m_axis_dout_tdata),
+    .o_tlast(m_axis_dout_tlast),
+    .o_tvalid(m_axis_dout_tvalid),
+    .o_tready(m_axis_dout_tready));
+
+  //debug
+  assign state_out = state;
+  assign phase_valid_hold_out = phase_valid_hold;
+  assign phase_invalid_wait_count_out = phase_invalid_wait_count;
+  assign reset_dds_out = reset_dds;
+  assign m_axis_dds_tlast_out = m_axis_dds_tlast;
+  assign m_axis_dds_tvalid_out = m_axis_dds_tvalid;
+  assign m_axis_dds_tready_out = m_axis_dds_tready;
+  assign m_axis_dds_tdata_out = m_axis_dds_tdata;
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/dds_timed.v b/fpga/usrp3/lib/rfnoc/dds_timed.v
new file mode 100644
index 000000000..fd03f6a23
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/dds_timed.v
@@ -0,0 +1,290 @@
+//
+// Copyright 2016 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// DDS that supports timed commands via the settings bus
+
+module dds_timed #(
+  parameter SR_FREQ_ADDR      = 0,
+  parameter SR_SCALE_IQ_ADDR  = 1,
+  parameter CMD_FIFO_SIZE     = 5,
+  parameter WIDTH             = 16,
+  parameter DDS_WIDTH         = 24,
+  parameter PHASE_WIDTH       = 24,
+  parameter PHASE_ACCUM_WIDTH = 32,
+  parameter SCALING_WIDTH     = 18,
+  parameter HEADER_WIDTH      = 128,
+  parameter HEADER_FIFO_SIZE  = 5,
+  parameter SR_AWIDTH         = 8,
+  parameter SR_DWIDTH         = 32,
+  parameter SR_TWIDTH         = 64
+)(
+  input clk, input reset, input clear,
+  output timed_cmd_fifo_full,
+  input set_stb, input [SR_AWIDTH-1:0] set_addr, input [SR_DWIDTH-1:0] set_data,
+  input [SR_TWIDTH-1:0] set_time, input set_has_time,
+  input [2*WIDTH-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready, input [HEADER_WIDTH-1:0] i_tuser,
+  output [2*WIDTH-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready, output [HEADER_WIDTH-1:0] o_tuser
+);
+
+  /**************************************************************************
+  * Track VITA time
+  *************************************************************************/
+  wire [2*WIDTH-1:0] int_tdata;
+  wire [HEADER_WIDTH-1:0] int_tuser;
+  wire int_tlast, int_tvalid, int_tready, int_tag;
+  wire [SR_AWIDTH-1:0] out_set_addr, timed_set_addr;
+  wire [SR_DWIDTH-1:0] out_set_data, timed_set_data;
+  wire out_set_stb, timed_set_stb;
+  wire eob;
+
+  axi_tag_time #(
+    .WIDTH(2*WIDTH),
+    .NUM_TAGS(1),
+    .SR_TAG_ADDRS(SR_FREQ_ADDR))
+  axi_tag_time (
+    .clk(clk),
+    .reset(reset),
+    .clear(clear),
+    .tick_rate(16'd1),
+    .timed_cmd_fifo_full(timed_cmd_fifo_full),
+    .s_axis_data_tdata(i_tdata), .s_axis_data_tlast(i_tlast),
+    .s_axis_data_tvalid(i_tvalid), .s_axis_data_tready(i_tready),
+    .s_axis_data_tuser(i_tuser),
+    .m_axis_data_tdata(int_tdata), .m_axis_data_tlast(int_tlast),
+    .m_axis_data_tvalid(int_tvalid), .m_axis_data_tready(int_tready),
+    .m_axis_data_tuser(int_tuser), .m_axis_data_tag(int_tag),
+    .in_set_stb(set_stb), .in_set_addr(set_addr), .in_set_data(set_data),
+    .in_set_time(set_time), .in_set_has_time(set_has_time),
+    .out_set_stb(out_set_stb), .out_set_addr(out_set_addr), .out_set_data(out_set_data),
+    .timed_set_stb(timed_set_stb), .timed_set_addr(timed_set_addr), .timed_set_data(timed_set_data));
+
+  wire [2*WIDTH-1:0] dds_in_tdata, unused_tdata;
+  wire [HEADER_WIDTH-1:0] header_in_tdata, header_out_tdata, unused_tuser;
+  wire dds_in_tlast, dds_in_tvalid, dds_in_tready, dds_in_tag;
+  wire header_in_tvalid, header_in_tready, header_in_tlast, unused_tag;
+  wire header_out_tvalid, header_out_tready;
+
+  split_stream #(
+    .WIDTH(2*WIDTH+HEADER_WIDTH+1), .ACTIVE_MASK(4'b0011))
+  split_head (
+    .clk(clk), .reset(reset), .clear(clear),
+    .i_tdata({int_tdata,int_tuser,int_tag}), .i_tlast(int_tlast),
+    .i_tvalid(int_tvalid), .i_tready(int_tready),
+    .o0_tdata({dds_in_tdata,unused_tuser,dds_in_tag}), .o0_tlast(dds_in_tlast),
+    .o0_tvalid(dds_in_tvalid), .o0_tready(dds_in_tready),
+    .o1_tdata({unused_tdata,header_in_tdata,unused_tag}), .o1_tlast(header_in_tlast),
+    .o1_tvalid(header_in_tvalid), .o1_tready(header_in_tready),
+    .o2_tready(1'b0), .o3_tready(1'b0));
+
+  axi_fifo #(
+    .WIDTH(HEADER_WIDTH), .SIZE(HEADER_FIFO_SIZE))
+  axi_fifo_header (
+    .clk(clk), .reset(reset), .clear(clear),
+    .i_tdata(header_in_tdata), .i_tvalid(header_in_tvalid & header_in_tlast), .i_tready(header_in_tready),
+    .o_tdata(header_out_tdata), .o_tvalid(header_out_tvalid),
+    .o_tready(header_out_tready), // Consume header on last output sample
+    .space(), .occupied());
+
+  assign eob = header_in_tdata[124];
+
+  /**************************************************************************
+  * Settings Regs
+  *************************************************************************/
+  wire [PHASE_ACCUM_WIDTH-1:0] phase_inc_tdata, phase_inc_timed_tdata;
+  wire phase_inc_tlast, phase_inc_tvalid, phase_inc_tready;
+  wire phase_inc_timed_tlast, phase_inc_timed_tready , phase_inc_timed_tvalid;
+
+  axi_setting_reg #(
+    .ADDR(SR_FREQ_ADDR), .AWIDTH(SR_AWIDTH), .WIDTH(PHASE_ACCUM_WIDTH), .STROBE_LAST(1))
+  set_freq (
+    .clk(clk), .reset(reset),
+    .set_stb(out_set_stb), .set_addr(out_set_addr), .set_data(out_set_data),
+    .o_tdata(phase_inc_tdata), .o_tlast(phase_inc_tlast), .o_tvalid(phase_inc_tvalid), .o_tready(phase_inc_tready));
+
+  axi_setting_reg #(
+    .ADDR(SR_FREQ_ADDR), .USE_FIFO(1), .FIFO_SIZE(CMD_FIFO_SIZE), .AWIDTH(SR_AWIDTH), .WIDTH(PHASE_ACCUM_WIDTH), .STROBE_LAST(1))
+  set_freq_timed (
+    .clk(clk), .reset(reset),
+    .set_stb(timed_set_stb), .set_addr(timed_set_addr), .set_data(timed_set_data),
+    .o_tdata(phase_inc_timed_tdata), .o_tlast(phase_inc_timed_tlast), .o_tvalid(phase_inc_timed_tvalid), .o_tready(phase_inc_timed_tready));
+
+  wire [SCALING_WIDTH-1:0] scaling_tdata;
+  wire scaling_tvalid, scaling_tready;
+
+  axi_setting_reg #(
+    .ADDR(SR_SCALE_IQ_ADDR), .AWIDTH(SR_AWIDTH), .WIDTH(SCALING_WIDTH), .REPEATS(1))
+  set_scale (
+    .clk(clk), .reset(reset),
+    .set_stb(out_set_stb), .set_addr(out_set_addr), .set_data(out_set_data),
+    .o_tdata(scaling_tdata), .o_tlast(), .o_tvalid(scaling_tvalid), .o_tready(scaling_tready));
+
+  /**************************************************************************
+  * DDS + Complex Mult + Phase Accumulator
+  *************************************************************************/
+  wire [PHASE_ACCUM_WIDTH-1:0] phase_inc_mux_tdata;
+  reg [PHASE_ACCUM_WIDTH-1:0] phase_inc;
+  wire phase_inc_mux_tlast, phase_inc_mux_tvalid, phase_inc_mux_tready;
+  reg [PHASE_ACCUM_WIDTH-1:0] phase;
+
+  wire [PHASE_WIDTH-1:0] phase_tdata = phase[PHASE_ACCUM_WIDTH-1:PHASE_ACCUM_WIDTH-PHASE_WIDTH];
+  wire phase_tvalid, phase_tready, phase_tlast;
+  
+  wire [WIDTH*2-1:0] dds_in_fifo_tdata;
+  wire dds_in_fifo_tvalid, dds_in_fifo_tready, dds_in_fifo_tlast;    
+  wire dds_out_tlast, dds_out_tvalid, dds_out_tready;
+  
+  wire [DDS_WIDTH-1:0] dds_in_i_tdata, dds_in_q_tdata;
+  wire [DDS_WIDTH-1:0] dds_out_i_tdata, dds_out_q_tdata;
+  wire [15:0] dds_input_fifo_space, dds_input_fifo_occupied;
+  
+  wire [WIDTH*2-1:0] dds_in_sync_tdata;
+  wire dds_in_sync_tvalid, dds_in_sync_tready, dds_in_sync_tlast;
+  wire [PHASE_WIDTH-1:0] phase_sync_tdata;
+  wire phase_sync_tvalid, phase_sync_tready, phase_sync_tlast;    
+  
+  assign phase_inc_mux_tdata    = phase_inc_timed_tready ? phase_inc_timed_tdata : phase_inc_tdata;
+  assign phase_inc_mux_tlast    = phase_inc_timed_tready ? phase_inc_timed_tlast : phase_inc_tlast;
+  assign phase_inc_mux_tvalid   = phase_inc_timed_tready ? phase_inc_timed_tvalid : phase_inc_tvalid;
+  assign phase_inc_tready       = phase_inc_mux_tready;
+  assign phase_inc_timed_tready = phase_inc_mux_tready & dds_in_tag;
+  assign phase_inc_mux_tready = phase_tready;
+
+  // phase is only valid when input i/q data stream is valid
+  assign phase_tvalid = dds_in_tvalid;
+  assign phase_tlast = dds_in_tlast;
+
+  always @(posedge clk) begin
+    if (reset | clear) begin
+      phase_inc <= 0;
+    end else if (phase_inc_mux_tvalid & phase_inc_mux_tready) begin
+      phase_inc <= phase_inc_mux_tdata;
+    end
+  end
+    
+  // NCO, increment phase input to DDS SIN/COS LUT
+  always @(posedge clk) begin
+    if (reset | clear | (phase_inc_mux_tvalid & phase_inc_mux_tready) | eob) begin
+      phase <= 0;
+    end else if (dds_in_tvalid & dds_in_tready) begin //only increment phase when data into dds is valid and data fifo is ready
+      phase <= phase + phase_inc;
+    end
+  end
+
+
+  // Sync the two path's pipeline delay.
+  // This is needed to ensure that applying the phase update happens on the
+  // correct sample regardless of differing downstream path delays.
+  axi_sync #(
+    .SIZE(2),
+    .WIDTH_VEC({PHASE_WIDTH,2*WIDTH}), // Vector of widths, each width is defined by a 32-bit value
+    .FIFO_SIZE(0))
+  axi_sync (
+    .clk(clk), .reset(reset), .clear(clear),
+    .i_tdata({phase_tdata,dds_in_tdata}),
+    .i_tlast({phase_tlast,dds_in_tlast}),
+    .i_tvalid({phase_tvalid,dds_in_tvalid}),
+    .i_tready({phase_tready,dds_in_tready}),
+    .o_tdata({phase_sync_tdata,dds_in_sync_tdata}),
+    .o_tlast({phase_sync_tlast,dds_in_sync_tlast}),
+    .o_tvalid({phase_sync_tvalid,dds_in_sync_tvalid}),
+    .o_tready({phase_sync_tready,dds_in_sync_tready}));
+
+  // fifo to hold input data while pipeline catches up in dds
+  // this is blocked by the axi_sync following the dds 
+  axi_fifo #(.WIDTH(2*WIDTH+1), .SIZE(5)) dds_input_fifo(
+    .clk(clk), .reset(reset), .clear(clear),
+    .i_tdata({dds_in_sync_tlast,dds_in_sync_tdata}), .i_tvalid(dds_in_sync_tvalid), .i_tready(dds_in_sync_tready),
+    .o_tdata({dds_in_fifo_tlast,dds_in_fifo_tdata}), .o_tvalid(dds_in_fifo_tvalid), .o_tready(dds_in_fifo_tready),
+    .space(dds_input_fifo_space), .occupied(dds_input_fifo_occupied)
+  );
+  
+  // after fifo, do q quick sign extend op to get up to 24 bits. to match how the cordic deals with the data path.
+  sign_extend #(
+    .bits_in(WIDTH), .bits_out(DDS_WIDTH))
+  sign_extend_dds_i (
+    .in(dds_in_fifo_tdata[2*WIDTH-1:WIDTH]), .out(dds_in_i_tdata));
+
+  sign_extend #(
+    .bits_in(WIDTH), .bits_out(DDS_WIDTH))
+  sign_extend_dds_q (
+    .in(dds_in_fifo_tdata[WIDTH-1:0]), .out(dds_in_q_tdata));
+  
+
+  // Wrapper for Xilinx IP AXI DDS + Complex Multiply  
+  // NOTE: Seems Xilinx IP expects opposite I/Q combined complex data buses, so they are swapped here.
+  dds_freq_tune dds_freq_tune_inst (
+    .clk(clk),
+    .reset(reset | clear),
+    .eob(eob),
+    .rate_changed(1'b0),
+    .dds_input_fifo_occupied(dds_input_fifo_occupied),
+    /* IQ input */
+    .s_axis_din_tlast(dds_in_fifo_tlast),
+    .s_axis_din_tvalid(dds_in_fifo_tvalid),
+    .s_axis_din_tready(dds_in_fifo_tready),
+    .s_axis_din_tdata({dds_in_q_tdata, dds_in_i_tdata}),
+    /* Phase input from NCO */
+    .s_axis_phase_tlast(phase_sync_tlast),
+    .s_axis_phase_tvalid(phase_sync_tvalid),
+    .s_axis_phase_tready(phase_sync_tready),
+    .s_axis_phase_tdata(phase_sync_tdata), //24 bit
+    /* IQ output */
+    .m_axis_dout_tlast(dds_out_tlast),
+    .m_axis_dout_tvalid(dds_out_tvalid),
+    .m_axis_dout_tready(dds_out_tready),
+    .m_axis_dout_tdata({dds_out_q_tdata, dds_out_i_tdata})
+     //debug signals
+  );
+  /************************************************************************
+  * Perform scaling on the IQ output
+  ************************************************************************/
+  wire [DDS_WIDTH+SCALING_WIDTH-1:0] scaled_i_tdata, scaled_q_tdata;
+  wire scaled_tlast, scaled_tvalid, scaled_tready;
+
+  mult #(
+   .WIDTH_A(DDS_WIDTH),
+   .WIDTH_B(SCALING_WIDTH),
+   .WIDTH_P(DDS_WIDTH+SCALING_WIDTH),
+   .DROP_TOP_P(4),
+   .LATENCY(3),
+   .CASCADE_OUT(0))
+  i_mult (
+    .clk(clk), .reset(reset | clear),
+    .a_tdata(dds_out_i_tdata), .a_tlast(dds_out_tlast), .a_tvalid(dds_out_tvalid), .a_tready(dds_out_tready),
+    .b_tdata(scaling_tdata), .b_tlast(1'b0), .b_tvalid(dds_out_tvalid /* aligning scaling_tdata with dds_tdata */), .b_tready(scaling_tready),
+    .p_tdata(scaled_i_tdata), .p_tlast(scaled_tlast), .p_tvalid(scaled_tvalid), .p_tready(scaled_tready));
+
+  mult #(
+   .WIDTH_A(DDS_WIDTH),
+   .WIDTH_B(SCALING_WIDTH),
+   .WIDTH_P(DDS_WIDTH+SCALING_WIDTH),
+   .DROP_TOP_P(4),
+   .LATENCY(3),
+   .CASCADE_OUT(0))
+  q_mult (
+    .clk(clk), .reset(reset | clear),
+    .a_tdata(dds_out_q_tdata), .a_tlast(), .a_tvalid(dds_out_tvalid), .a_tready(),
+    .b_tdata(scaling_tdata), .b_tlast(1'b0), .b_tvalid(dds_out_tvalid /* aligning scaling_tdata with dds_tdata */), .b_tready(),
+    .p_tdata(scaled_q_tdata), .p_tlast(), .p_tvalid(), .p_tready(scaled_tready));
+
+  wire [2*WIDTH-1:0] sample_tdata;
+  wire sample_tlast, sample_tvalid, sample_tready;
+
+  axi_round_and_clip_complex #(
+    .WIDTH_IN(DDS_WIDTH+SCALING_WIDTH), .WIDTH_OUT(WIDTH), .CLIP_BITS(12))
+  axi_round_and_clip_complex (
+    .clk(clk), .reset(reset | clear),
+    .i_tdata({scaled_i_tdata, scaled_q_tdata}), .i_tlast(scaled_tlast), .i_tvalid(scaled_tvalid), .i_tready(scaled_tready),
+    .o_tdata(sample_tdata), .o_tlast(sample_tlast), .o_tvalid(sample_tvalid), .o_tready(sample_tready));
+
+  // Throttle output on last sample if header is not valid
+  assign header_out_tready = sample_tlast & sample_tvalid & o_tready;
+  assign sample_tready     = (sample_tvalid & sample_tlast) ? (header_out_tvalid & o_tready) : o_tready;
+  assign o_tvalid          = (sample_tvalid & sample_tlast) ? header_out_tvalid : sample_tvalid;
+  assign o_tlast           = sample_tlast;
+  assign o_tdata           = sample_tdata;
+  assign o_tuser           = header_out_tdata;
+  
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/delay_fifo.v b/fpga/usrp3/lib/rfnoc/delay_fifo.v
new file mode 100644
index 000000000..ad13392c8
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/delay_fifo.v
@@ -0,0 +1,41 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module delay_fifo
+  #(parameter MAX_LEN=1023,
+    parameter WIDTH=16)
+   (input clk, input reset, input clear,
+    input [$clog2(MAX_LEN+1)-1:0] len,
+    input [WIDTH-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
+    output [WIDTH-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready);
+
+   reg [$clog2(MAX_LEN+1)-1:0] full_count;
+   wire 		  full = full_count == len;
+   
+   wire 		  do_op = i_tvalid & o_tready;
+
+   assign i_tready = o_tready;
+   assign o_tvalid = i_tvalid;
+
+   wire [WIDTH-1:0] 		    fifo_out;
+   
+   axi_fifo #(.WIDTH(WIDTH), .SIZE($clog2(MAX_LEN+1))) sample_fifo
+     (.clk(clk), .reset(reset), .clear(clear),
+      .i_tdata(i_tdata), .i_tvalid(do_op), .i_tready(),
+      .o_tdata(fifo_out), .o_tvalid(), .o_tready(do_op&full));
+
+   always @(posedge clk)
+     if(reset | clear)
+       full_count <= 0;
+     else
+       if(do_op & ~full)
+	 full_count <= full_count + 1;     // FIXME careful if len changes during operation you must clear
+   
+   assign o_tdata = full ? fifo_out : 0;
+   assign o_tlast = i_tlast;
+
+endmodule // delay_fifo
diff --git a/fpga/usrp3/lib/rfnoc/delay_type2.v b/fpga/usrp3/lib/rfnoc/delay_type2.v
new file mode 100644
index 000000000..6403f23b2
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/delay_type2.v
@@ -0,0 +1,35 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// This delay doesn't use a fifo, and solves pipeline bubble issues.  
+// FIXME -- issues are that it will generate output without input, and you can't reduce delay, only increase
+
+module delay_type2
+  #(parameter MAX_LEN_LOG2=10,
+    parameter WIDTH=16,
+    parameter DELAY_VAL=0)
+   (input clk, input reset, input clear,
+    input [MAX_LEN_LOG2-1:0] len,
+    input [WIDTH-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
+    output [WIDTH-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready);
+
+   reg [MAX_LEN_LOG2-1:0] delay_count;
+
+   wire 		  delay_done = delay_count >= len;
+   
+   always @(posedge clk)
+     if(reset)
+       delay_count <= 0;
+     else
+       if(~delay_done & o_tvalid & o_tready)
+	 delay_count <= delay_count + 1;
+
+   assign o_tdata = delay_done ? i_tdata : DELAY_VAL;
+   assign o_tlast = delay_done ? i_tlast : 1'b0;      // FIXME think about this more, no answer is perfect in all situations
+   assign o_tvalid = delay_done ? i_tvalid : 1'b1;
+   assign i_tready = delay_done ? o_tready : 1'b0;
+   
+endmodule // delay_type2
diff --git a/fpga/usrp3/lib/rfnoc/delay_type3.v b/fpga/usrp3/lib/rfnoc/delay_type3.v
new file mode 100644
index 000000000..6b2dfa1fd
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/delay_type3.v
@@ -0,0 +1,32 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module delay_type3
+  #(parameter FIFOSIZE=5,
+    parameter MAX_LEN_LOG2=10,
+    parameter WIDTH=16,
+    parameter DELAY_VAL=0)
+   (input clk, input reset, input clear,
+    input [MAX_LEN_LOG2-1:0] len,
+    input [WIDTH-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
+    output [WIDTH-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready);
+
+   wire [WIDTH-1:0]    int_tdata;
+   wire 	       int_tlast, int_tvalid, int_tready;
+   
+   axi_fifo #(.WIDTH(WIDTH+1), .SIZE(MAX_LEN_LOG2)) sample_fifo
+     (.clk(clk), .reset(reset), .clear(clear),
+      .i_tdata({i_tlast,i_tdata}), .i_tvalid(i_tvalid), .i_tready(i_tready),
+      .o_tdata({int_tlast,int_tdata}), .o_tvalid(int_tvalid), .o_tready(int_tready));
+
+   delay_type2 #(.MAX_LEN_LOG2(MAX_LEN_LOG2), .WIDTH(WIDTH), .DELAY_VAL(DELAY_VAL)) delay
+     (.clk(clk), .reset(reset), .clear(clear),
+      .len(len),
+      .i_tdata(int_tdata), .i_tlast(int_tlast), .i_tvalid(int_tvalid), .i_tready(int_tready),
+      .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready));
+
+endmodule // delay_type3
\ No newline at end of file
diff --git a/fpga/usrp3/lib/rfnoc/delay_type4.v b/fpga/usrp3/lib/rfnoc/delay_type4.v
new file mode 100644
index 000000000..c1f3360ae
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/delay_type4.v
@@ -0,0 +1,38 @@
+//
+// Copyright 2018 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// This delay doesn't use a fifo, and solves pipeline bubble issues.
+// fixes some issues that seemed to occur with delay_type2:
+// - o_tvalid is set to 0 when delay_done is 0
+// - added the clear signal
+// - i_tvalid is a combinational input to incrementing delay_count
+
+module delay_type4
+  #(parameter MAX_LEN_LOG2=4,
+    parameter WIDTH=16,
+    parameter DELAY_VAL=0)
+  (input clk, input reset, input clear,
+    input [MAX_LEN_LOG2-1:0] len,
+    input [WIDTH-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
+    output [WIDTH-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready);
+
+  reg [MAX_LEN_LOG2-1:0] delay_count;
+
+  wire delay_done = delay_count >= len;
+
+  always @(posedge clk)
+    if(reset | clear)
+      delay_count <= 0;
+    else
+      if(~delay_done & i_tvalid & o_tready)
+        delay_count <= delay_count + 1;
+
+  assign o_tdata = delay_done ? i_tdata : DELAY_VAL;
+  assign o_tlast = delay_done ? i_tlast : 1'b0;      // FIXME (carried over from delay_type2) think about this more, no answer is perfect in all situations
+  assign o_tvalid = delay_done ? i_tvalid : 1'b0;
+  assign i_tready = delay_done ? o_tready : 1'b0;
+
+endmodule // delay_type4
diff --git a/fpga/usrp3/lib/rfnoc/duc.v b/fpga/usrp3/lib/rfnoc/duc.v
new file mode 100644
index 000000000..7a4fcc602
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/duc.v
@@ -0,0 +1,275 @@
+//
+// Copyright 2016 Ettus Research
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+//! RFNoC specific digital up-conversion chain
+// High level block diagram:
+//
+// HB1 -> HB2 -> CIC -> DDS/multiplier -> Scaler
+
+// We don't care about framing here, hence no tlast
+
+module duc #(
+  parameter SR_PHASE_INC_ADDR = 0,
+  parameter SR_SCALE_ADDR     = 1,
+  parameter SR_INTERP_ADDR    = 2,
+  parameter NUM_HB            = 2,
+  parameter CIC_MAX_INTERP    = 128
+
+)(
+  input clk, input reset, input clear,
+  input set_stb, input [7:0] set_addr, input [31:0] set_data,
+  input [31:0] i_tdata, input [127:0] i_tuser, input i_tvalid, output i_tready,
+  output [31:0] o_tdata, output [127:0] o_tuser, output o_tvalid, input o_tready
+);
+
+  localparam RESET_DELAY = 3;
+
+  localparam WIDTH  = 16; // Input/output bitwidth of the module
+  localparam CWIDTH = 24; // Internal bitwidth needed for CORDIC accuracy
+  localparam PWIDTH = 32; // Phase accumulator bitwidth
+
+  reg  [1:0] hb_rate;             // Current Halfband rate
+  reg  [7:0] cic_interp_rate;     // Current CIC rate
+
+  wire [1:0] hb_rate_int;
+  wire [7:0] cic_interp_rate_int;
+
+  wire [2*CWIDTH-1:0] o_tdata_halfbands;  // Halfband output
+  wire o_tvalid_halfbands;
+
+  wire rate_changed;    // Rate changed by the settings registers
+  wire reset_on_change; // Reset the halfbands and the cic everytime there is a rate change
+  wire reset_on_live_change; // Reset when rate changes while streaming
+
+  wire [PWIDTH-1:0] o_tdata_phase;
+  wire o_tvalid_phase;
+  wire o_tlast_phase;
+  wire i_tready_phase;
+
+  wire [17:0] scale_factor;
+
+ /**************************************************************************
+  * Settings registers
+  **************************************************************************/
+  // AXI settings bus for phase values
+  axi_setting_reg #(
+    .ADDR(SR_PHASE_INC_ADDR), .AWIDTH(8), .WIDTH(PWIDTH), .STROBE_LAST(1), .REPEATS(1))
+  axi_sr_phase (
+    .clk(clk), .reset(reset),
+    .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+    .o_tdata(o_tdata_phase), .o_tlast(o_tlast_phase), .o_tvalid(o_tvalid_phase), .o_tready(i_tready_phase));
+
+  // AXI settings bus for scale
+  setting_reg #(.my_addr(SR_SCALE_ADDR), .width(18)) sr_scale (
+    .clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+    .in(set_data),.out(scale_factor),.changed());
+
+  // AXI settings bus for interpolation rate
+  setting_reg #(.my_addr(SR_INTERP_ADDR), .width(10), .at_reset(1)) sr_interp
+    (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+     .in(set_data),.out({hb_rate_int,cic_interp_rate_int}),.changed(rate_changed));
+
+  // Changing interpolation rates while processing only when axi_rate_change sends a clear
+  reg active, rate_changed_hold;
+  reg [RESET_DELAY-1:0] shift_reset;
+  always @(posedge clk) begin
+    if (reset) begin
+      active            <= 1'b0;
+      rate_changed_hold <= 1'b0;
+      cic_interp_rate   <= 'd1;
+      hb_rate           <= 'd0;
+      shift_reset       <= 'd0;
+    end else begin
+      if (clear | reset_on_change) begin
+        active <= 1'b0;
+      end else if (i_tready & i_tvalid) begin
+        active <= 1'b1;
+      end
+      if (rate_changed & active) begin
+        rate_changed_hold <= 1'b1;
+      end
+      if ((clear | ~active) & (rate_changed | rate_changed_hold)) begin
+        rate_changed_hold <= 1'b0;
+        cic_interp_rate   <= cic_interp_rate_int;
+        hb_rate           <= hb_rate_int;
+        shift_reset       <= {shift_reset[RESET_DELAY-1:0], 1'b1};
+      end else begin
+        shift_reset       <= {shift_reset[RESET_DELAY-1:0], 1'b0};
+      end
+    end
+  end
+
+  // Long reset for the halfbands
+  assign reset_on_change = |shift_reset;
+  assign reset_on_live_change =  (clear | reset_on_change | (~active & rate_changed));
+
+ /**************************************************************************
+  * Halfbands
+  *************************************************************************/
+
+  // Sign extend from 16 to 24 bits to increase the accuracy from the frequency shifter
+  wire [2*CWIDTH-1:0] o_tdata_extd;
+
+  sign_extend #(.bits_in(WIDTH), .bits_out(CWIDTH)) sign_extend_in_i (
+    .in(i_tdata[2*WIDTH-1:WIDTH]), .out(o_tdata_extd[2*CWIDTH-1:CWIDTH]));
+
+  sign_extend #(.bits_in(WIDTH), .bits_out(CWIDTH)) sign_extend_in_q (
+    .in(i_tdata[WIDTH-1:0]), .out(o_tdata_extd[CWIDTH-1:0]));
+
+  // Halfband 1 wires
+  wire i_tready_hb1;
+  wire [2*CWIDTH-1:0] o_tdata_hb1;
+  wire o_tvalid_hb1, o_tready_hb1;
+  // Halfband 2 wires
+  wire i_tready_hb2;
+  wire [2*CWIDTH-1:0] o_tdata_hb2;
+  wire o_tvalid_hb2, o_tready_hb2;
+  // Halfband 3 wires
+  wire i_tready_hb3;
+  wire [2*CWIDTH-1:0] o_tdata_hb3;
+  wire o_tvalid_hb3, o_tready_hb3;
+  generate
+  if( NUM_HB > 0 ) begin
+  axi_hb47 halfband1 (
+    .aclk(clk),
+    .aresetn(~(reset | clear | reset_on_change)),
+    .s_axis_data_tvalid(i_tvalid),
+    .s_axis_data_tready(i_tready_hb1),
+    .s_axis_data_tdata(o_tdata_extd),
+    .m_axis_data_tvalid(o_tvalid_hb1),
+    .m_axis_data_tready(o_tready_hb1),
+    .m_axis_data_tdata(o_tdata_hb1)
+  );
+  end else begin
+  assign o_tdata_hb1 = 'h0;
+  assign o_tvalid_hb1 = 1'h0;
+  assign i_tready_hb1 = 1'b0;
+  end
+  if( NUM_HB > 1 ) begin
+  axi_hb47 halfband2 (
+    .aclk(clk),
+    .aresetn(~(reset | clear | reset_on_change)),
+    .s_axis_data_tvalid(o_tvalid_hb1),
+    .s_axis_data_tready(i_tready_hb2),
+    .s_axis_data_tdata({o_tdata_hb1[2*CWIDTH-1:CWIDTH] << 2, o_tdata_hb1[CWIDTH-1:0] << 2}),
+    .m_axis_data_tvalid(o_tvalid_hb2),
+    .m_axis_data_tready(o_tready_hb2),
+    .m_axis_data_tdata(o_tdata_hb2)
+  );
+  end else begin
+  assign o_tdata_hb2 = 'h0;
+  assign o_tvalid_hb2 = 1'h0;
+  assign i_tready_hb2 = 1'b0;
+  end
+  if( NUM_HB > 2 ) begin
+  axi_hb47 halfband3 (
+    .aclk(clk),
+    .aresetn(~(reset | clear | reset_on_change)),
+    .s_axis_data_tvalid(o_tvalid_hb2),
+    .s_axis_data_tready(i_tready_hb3),
+    .s_axis_data_tdata({o_tdata_hb2[2*CWIDTH-1:CWIDTH] << 2, o_tdata_hb2[CWIDTH-1:0] << 2}),
+    .m_axis_data_tvalid(o_tvalid_hb3),
+    .m_axis_data_tready(o_tready_hb3),
+    .m_axis_data_tdata(o_tdata_hb3)
+  );
+  end else begin
+  assign o_tdata_hb3 = 'h0;
+  assign o_tvalid_hb3 = 1'h0;
+  assign i_tready_hb3 = 1'b0;
+  end
+  endgenerate
+ /**************************************************************************
+  * Halfband selection multiplexing
+  *************************************************************************/
+  wire [2*CWIDTH-1:0] o_tdata_cic;
+  wire [2*CWIDTH-1:0] o_cic;
+  wire o_tvalid_cic, i_tready_cic;
+  wire o_tready_cic;
+
+  assign o_tdata_halfbands = (hb_rate == 2'b0) ? o_tdata_extd :
+                             (hb_rate == 2'b1) ?  {o_tdata_hb1[2*CWIDTH-1:CWIDTH] << 2, o_tdata_hb1[CWIDTH-1:0] << 2} :
+                             (hb_rate == 2'b10) ? {o_tdata_hb2[2*CWIDTH-1:CWIDTH] << 2, o_tdata_hb2[CWIDTH-1:0] << 2} :
+                                                  {o_tdata_hb3[2*CWIDTH-1:CWIDTH] << 2, o_tdata_hb3[CWIDTH-1:0] << 2};
+  // Clearing valid on rate change as the halfbands take 2 cycles to clear
+  assign o_tvalid_halfbands = reset_on_live_change ? 1'b0 :
+                              (hb_rate == 2'b0)    ?  i_tvalid :
+                              (hb_rate == 2'b1)    ?  o_tvalid_hb1 :
+                              (hb_rate == 2'b10)    ? o_tvalid_hb2 :
+                                                      o_tvalid_hb3;
+  // Throttle input data while rate change is going on
+  assign i_tready     =  reset_on_live_change ? 1'b0 :
+                         (hb_rate == 2'b0)    ? i_tready_cic :
+                                                i_tready_hb1;
+  assign o_tready_hb1 =  reset_on_live_change ? 1'b0 :
+                         (hb_rate == 2'b1)    ? i_tready_cic :
+                                                i_tready_hb2;
+  assign o_tready_hb2 =  reset_on_live_change ? 1'b0 :
+                         (hb_rate == 2'b10)   ? i_tready_cic :
+                                                i_tready_hb3;
+
+  assign o_tready_hb3 =  reset_on_live_change ? 1'b0 : i_tready_cic;
+
+ /**************************************************************************
+  * Ettus CIC; the Xilinx CIC has a minimum interpolation of 4,
+  * so we use the strobed version and convert to and from AXI.
+  *************************************************************************/
+  wire to_cic_stb, from_cic_stb;
+  wire [2*CWIDTH-1:0] to_cic_data;
+  wire [CWIDTH-1:0] i_cic;
+  wire [CWIDTH-1:0] q_cic;
+
+  // Convert from AXI to strobed and back to AXI again for the CIC interpolation module
+  axi_to_strobed #(.WIDTH(2*CWIDTH), .FIFO_SIZE(1), .MIN_RATE(128)) axi_to_strobed (
+    .clk(clk), .reset(reset | reset_on_change), .clear(clear),
+    .out_rate(cic_interp_rate), .ready(i_tready_cartesian & o_tready), .error(),
+    .i_tdata(o_tdata_halfbands), .i_tvalid(o_tvalid_halfbands), .i_tlast(1'b0), .i_tready(i_tready_cic),
+    .out_stb(to_cic_stb), .out_last(), .out_data(to_cic_data)
+  );
+
+  cic_interpolate #(.WIDTH(CWIDTH), .N(4), .MAX_RATE(CIC_MAX_INTERP)) cic_interpolate_i (
+    .clk(clk), .reset(reset | clear | reset_on_change),
+    .rate_stb(reset_on_change),
+    .rate(cic_interp_rate), .strobe_in(to_cic_stb), .strobe_out(from_cic_stb),
+    .signal_in(to_cic_data[2*CWIDTH-1:CWIDTH]), .signal_out(i_cic)
+  );
+
+  cic_interpolate #(.WIDTH(CWIDTH), .N(4), .MAX_RATE(CIC_MAX_INTERP)) cic_interpolate_q (
+    .clk(clk), .reset(reset | clear | reset_on_change),
+    .rate_stb(reset_on_change),
+    .rate(cic_interp_rate), .strobe_in(to_cic_stb), .strobe_out(),
+    .signal_in(to_cic_data[CWIDTH-1:0]), .signal_out(q_cic)
+  );
+
+  assign o_cic = {i_cic, q_cic};
+
+  //FIFO_SIZE = 8 infers a bram fifo
+  strobed_to_axi #(.WIDTH(2*CWIDTH), .FIFO_SIZE(8)) strobed_to_axi (
+    .clk(clk), .reset(reset | reset_on_change), .clear(clear),
+    .in_stb(from_cic_stb), .in_data(o_cic), .in_last(1'b0),
+    .o_tdata(o_tdata_cic), .o_tvalid(o_tvalid_cic), .o_tlast(), .o_tready(o_tready_cic)
+  );
+
+
+ /**************************************************************************
+  * Clip back to 16 bits
+  *************************************************************************/
+  wire o_tvalid_clip;
+
+  axi_round_and_clip_complex #(
+    .WIDTH_IN(CWIDTH), .WIDTH_OUT(WIDTH), .CLIP_BITS(CWIDTH-WIDTH)) // No rounding, all clip
+  axi_round_and_clip_complex (
+    .clk(clk), .reset(reset | clear | reset_on_change),
+    .i_tdata(o_tdata_cic), .i_tlast(1'b0), .i_tvalid(o_tvalid_cic), .i_tready(o_tready_cic),
+    .o_tdata(o_tdata), .o_tlast(), .o_tvalid(o_tvalid_clip), .o_tready(i_tready_cartesian));
+
+  assign o_tvalid = reset_on_live_change ? 1'b0 : o_tvalid_clip;
+  assign i_tready_cartesian = reset_on_live_change ? 1'b0 : o_tready;
+
+  // Note: To facilitate timed tunes, the code has been moved outside
+  //       the duc module to dds_timed.v.
+
+endmodule // duc
diff --git a/fpga/usrp3/lib/rfnoc/fft_shift.v b/fpga/usrp3/lib/rfnoc/fft_shift.v
new file mode 100644
index 000000000..453da8050
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/fft_shift.v
@@ -0,0 +1,198 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Arranges FFT output AXI stream packets so zero frequency bin is centered. Expects i_tuser to have FFT index.
+// Intended to complement Xilinx Coregen AXI-stream FFT, but should work with any core with similar output.
+// Works with natural and bit/digit reversed order. 
+//
+// When using Xilinx FFT core, use bit/digit reversed order (versus natural order) to save resources
+//
+// Config bits:
+//   0: Reverse output so positive frequencies are sent first
+//   1: Bypass fft shift
+
+module fft_shift #(
+  parameter MAX_FFT_SIZE_LOG2 = 11,
+  parameter WIDTH = 32)
+(
+  input clk, input reset,
+  input [1:0] config_tdata, input config_tvalid, output config_tready,
+  input [$clog2(MAX_FFT_SIZE_LOG2+1)-1:0] fft_size_log2_tdata, input fft_size_log2_tvalid, output fft_size_log2_tready,
+  input [WIDTH-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready, input [MAX_FFT_SIZE_LOG2-1:0] i_tuser,
+  output [WIDTH-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready
+);
+
+  reg ping_pong;
+  reg loading_pkt;
+  reg [2:0] reconfig_stall;
+  reg reverse, bypass;
+  reg [$clog2(MAX_FFT_SIZE_LOG2+1)-1:0] fft_size_log2_reg;
+  reg [MAX_FFT_SIZE_LOG2:0] fft_size;
+  reg [MAX_FFT_SIZE_LOG2-1:0] fft_size_minus_1, fft_shift_mask;
+  wire [WIDTH-1:0] ping_rd_data, pong_rd_data;
+  reg [MAX_FFT_SIZE_LOG2-1:0] ping_rd_addr, pong_rd_addr;
+  // t_user is the FFT index, this XOR is how the natural order FFT output is flipped to
+  // center the zero frequency bin in the middle. This is essentially adding half the FFT length to
+  // the write address without carrying, causing the upper half addresses to wrap around to the lower half
+  // and vice versa.
+  wire [MAX_FFT_SIZE_LOG2-1:0] ping_wr_addr = fft_shift_mask ^ i_tuser;
+  wire [MAX_FFT_SIZE_LOG2-1:0] pong_wr_addr = fft_shift_mask ^ i_tuser;
+  wire ping_wr_en = ping_pong ? i_tvalid & i_tready : 1'b0;
+  wire pong_wr_en = ping_pong ? 1'b0                : i_tvalid & i_tready;
+  // Always reads when loading ping/pong RAM so first word falls through. Avoids a bubble state.
+  wire ping_rd_en = ping_pong ? 1'b1                : o_tvalid & o_tready;
+  wire pong_rd_en = ping_pong ? o_tvalid & o_tready : 1'b1;
+  reg ping_loaded, pong_loaded;
+  // Only fill ping (or pong) RAM if it is empty and fft size has propagated through
+  assign i_tready = (ping_pong ? ~ping_loaded       : ~pong_loaded) & ~reconfig_stall[2];
+  reg ping_tlast, pong_tlast;
+  // Dump data in ping RAM (but only if it has been loaded!) while also loading in pong RAM and vice versa
+  assign o_tvalid = ping_pong ? pong_loaded         : ping_loaded;
+  assign o_tlast = ping_pong ? pong_tlast           : ping_tlast;
+  assign o_tdata = ping_pong ? pong_rd_data         : ping_rd_data;
+
+  // Prevent reconfiguration from occurring except at valid times. If the user violates tvalid rules
+  // (i.e. deasserts tvalid during the middle of a packet), could cause next output packet to have
+  // the wrong size.
+  assign config_tready        = ~ping_loaded & ~pong_loaded & ~loading_pkt;
+  assign fft_size_log2_tready = config_tready;
+
+  ram_2port #(
+    .DWIDTH(WIDTH),
+    .AWIDTH(MAX_FFT_SIZE_LOG2))
+  ping_ram_2port (
+    .clka(clk),.ena(1'b1),.wea(ping_wr_en),.addra(ping_wr_addr),.dia(i_tdata),.doa(),
+    .clkb(clk),.enb(ping_rd_en),.web(1'b0),.addrb(ping_rd_addr),.dib({WIDTH{1'b0}}),.dob(ping_rd_data));
+
+  ram_2port #(
+    .DWIDTH(WIDTH),
+    .AWIDTH(MAX_FFT_SIZE_LOG2))
+  pong_ram_2port (
+    .clka(clk),.ena(1'b1),.wea(pong_wr_en),.addra(pong_wr_addr),.dia(i_tdata),.doa(),
+    .clkb(clk),.enb(pong_rd_en),.web(1'b0),.addrb(pong_rd_addr),.dib({WIDTH{1'b0}}),.dob(pong_rd_data));
+
+  always @(posedge clk) begin
+    if (reset) begin
+      ping_pong             <= 1'b1;
+      ping_loaded           <= 1'b0;
+      pong_loaded           <= 1'b0;
+      ping_rd_addr          <= 0;
+      pong_rd_addr          <= 0;
+      ping_tlast            <= 1'b0;
+      pong_tlast            <= 1'b0;
+      fft_shift_mask        <= 0;
+      fft_size_minus_1      <= 0;
+      fft_size              <= 0;
+      fft_size_log2_reg     <= 0;
+      bypass                <= 1'b0;
+      reverse               <= 1'b0;
+      reconfig_stall        <= 3'd0;
+      loading_pkt           <= 1'b0;
+    end else begin
+      fft_size_minus_1   <= fft_size-1;
+      fft_size           <= 1 << fft_size_log2_reg;
+      // Configure FFT shift mask such that the output order is either
+      // unaffected (bypass), positive frequencies first (reverse), or
+      // negative frequencies first
+      if (bypass) begin
+        fft_shift_mask   <= 'd0;
+      end else if (reverse) begin
+        fft_shift_mask   <= (fft_size-1) >> 1;
+      end else begin
+        fft_shift_mask   <= fft_size >> 1;
+      end
+
+      // Restrict updating 
+      if (config_tready & config_tvalid) begin
+        reverse           <= config_tdata[0];
+        bypass            <= config_tdata[1];
+        reconfig_stall    <= 3'b100;
+      end
+      // Restrict updating FFT size to valid times
+      // Also, deassert i_tready until updated fft size has propagated through
+      if (fft_size_log2_tready & fft_size_log2_tvalid) begin
+        fft_size_log2_reg <= fft_size_log2_tdata[$clog2(MAX_FFT_SIZE_LOG2)-1:0];
+        reconfig_stall    <= 3'b111;
+      end
+      if (~(config_tready & config_tvalid) & ~(fft_size_log2_tready & fft_size_log2_tvalid)) begin
+        reconfig_stall[0] <= 1'b0;
+        reconfig_stall[2:1] <= reconfig_stall[1:0];
+      end
+
+      // Used to disable reconfiguration when we are receiving a packet
+      if (i_tvalid & i_tready & ~i_tlast & ~loading_pkt) begin
+        loading_pkt <= 1'b1;
+      end else if (i_tvalid & i_tready & i_tlast & loading_pkt) begin
+        loading_pkt <= 1'b0;
+      end
+
+      // Logic to simultaneously load ping RAM and unload pong RAM. Note, write address for ping RAM handled with i_tuser, 
+      // so we only look for i_tlast instead of maintaining a write address counter.
+      if (ping_pong) begin
+        // Unload pong RAM
+        if (pong_loaded & o_tready & o_tvalid) begin
+          // i.e. pong_rd_addr == fft_size-1, more efficient to use tlast
+          if (pong_tlast) begin
+            // Special case: ping RAM loaded before pong RAM emptied
+            if (ping_loaded | (i_tvalid & i_tready & i_tlast)) begin
+              ping_pong <= ~ping_pong;
+            end
+            pong_tlast   <= 1'b0;
+            pong_loaded  <= 1'b0;
+            pong_rd_addr <= 0;
+          end else begin
+            pong_rd_addr <= pong_rd_addr + 1;
+          end
+          if (pong_rd_addr == fft_size_minus_1) begin
+            pong_tlast <= 1'b1;
+          end
+        end
+        // Ping RAM done loading
+        if (i_tvalid & i_tready & i_tlast) begin
+          // Value at addr 0 already loaded (see first word fall through and avoiding a bubble state comment above)
+          ping_rd_addr <= 1;
+          ping_loaded  <= 1'b1;
+          // We can switch to the pong RAM only if it is empty (or about to be empty)
+          if (~pong_loaded) begin
+            ping_pong <= ~ping_pong;
+          end
+        end
+        // Special case: Ping and pong RAM loaded, wait until pong RAM unloaded.
+        if (ping_loaded & (pong_loaded & o_tvalid & o_tlast)) begin
+          ping_pong <= ~ping_pong;
+        end
+      // Same as above, just ping / pong switched
+      end else begin
+        if (ping_loaded & o_tready & o_tvalid) begin
+          if (ping_tlast) begin
+            if (pong_loaded | (i_tvalid & i_tready & i_tlast)) begin
+              ping_pong <= ~ping_pong;
+            end
+            ping_tlast   <= 1'b0;
+            ping_loaded  <= 1'b0;
+            ping_rd_addr <= 0;
+          end else begin
+            ping_rd_addr <= ping_rd_addr + 1;
+          end
+          if (ping_rd_addr == fft_size_minus_1) begin
+            ping_tlast <= 1'b1;
+          end
+        end
+        if (i_tvalid & i_tready & i_tlast) begin
+          pong_rd_addr <= 1;
+          pong_loaded  <= 1'b1;
+          if (~ping_loaded | (ping_loaded & o_tvalid & o_tlast)) begin
+            ping_pong <= ~ping_pong;
+          end
+        end
+        if (pong_loaded & (ping_loaded & o_tvalid & o_tlast)) begin
+          ping_pong <= ~ping_pong;
+        end
+      end
+    end
+  end
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/file_sink.v b/fpga/usrp3/lib/rfnoc/file_sink.v
new file mode 100644
index 000000000..3e4caaba1
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/file_sink.v
@@ -0,0 +1,107 @@
+//
+// Copyright 2015 National Instruments
+//
+
+module file_sink #(
+  parameter SR_SWAP_SAMPLES        = 0, // 0: Do nothing, 1: 8-bit swap, 2: 16-bit, 3: 32-bit
+  parameter SR_ENDIANNESS          = 1, // 0: Do nothing, 1: 16-bit boundary, 2: 32-bit
+  // Default (after reset) values for above settings register set to sc16 (reverse endianess on
+  parameter DEFAULT_SWAP_SAMPLES   = 2,
+  parameter DEFAULT_ENDIANNESS     = 2,
+  parameter FILENAME = "")
+(
+  input clk_i,
+  input rst_i,
+
+  input set_stb_i,
+  input [7:0] set_addr_i,
+  input [31:0] set_data_i,
+
+  input  [63:0] i_tdata,
+  input  i_tlast,
+  input  i_tvalid,
+  output i_tready);
+
+  integer file = 0;
+  reg hdr = 1'b1;
+
+  wire [1:0] swap_samples;
+  wire [1:0] endianness;
+
+  wire [63:0] data_int;
+  wire [63:0] data;
+
+  setting_reg #(
+    .my_addr(SR_SWAP_SAMPLES),
+    .width(2),
+    .at_reset(DEFAULT_SWAP_SAMPLES))
+  sr_swap_samples (
+    .clk(clk_i),
+    .rst(rst_i),
+    .strobe(set_stb_i),
+    .addr(set_addr_i),
+    .in(set_data_i),
+    .out(swap_samples),
+    .changed());
+
+  setting_reg #(
+    .my_addr(SR_ENDIANNESS),
+    .width(2),
+    .at_reset(DEFAULT_ENDIANNESS))
+  sr_endianness (
+    .clk(clk_i),
+    .rst(rst_i),
+    .strobe(set_stb_i),
+    .addr(set_addr_i),
+    .in(set_data_i),
+    .out(endianness),
+    .changed());
+
+  // We're ready as soon as the file is open
+  assign i_tready = (file == 0) ? 1'b0 : 1'b1;
+
+  // Swap samples
+  assign data_int = (swap_samples == 2'd0) ?  i_tdata :
+                    (swap_samples == 2'd1) ? {i_tdata[55:48], i_tdata[63:56], i_tdata[39:32], i_tdata[47:40],
+                                              i_tdata[23:16], i_tdata[31:24], i_tdata[ 7: 0], i_tdata[15: 8]} :
+                    (swap_samples == 2'd2) ? {i_tdata[47:32], i_tdata[63:48], i_tdata[15: 0], i_tdata[31:16]} :
+                    (swap_samples == 2'd3) ? {i_tdata[31:0], i_tdata[63:32]} :
+                                              64'd0;
+
+  // Swap endianness
+  assign data = (endianness == 2'd0) ?  data_int :
+                (endianness == 2'd1) ? {data_int[47:32], data_int[63:48], data_int[15: 0], data_int[31:16]} :
+                (endianness == 2'd2) ? {data_int[39:32], data_int[47:40], data_int[55:48], data_int[63:56],
+                                        data_int[ 7: 0], data_int[15: 8], data_int[23:16], data_int[31:24]} :
+                                        64'd0;
+
+  initial begin
+    if (FILENAME != "") begin
+      file = $fopen(FILENAME, "wb");
+      if(!file)
+        $error("Could not open file sink.");
+      $display("File sink ready.");
+    end
+  end
+
+  always @(posedge clk_i) begin
+    if(rst_i) begin
+      hdr <= 1'b1;
+    end
+    else begin
+      if(i_tvalid) begin
+        if(hdr) begin
+          hdr <= 1'b0;
+        end
+        else begin
+          $fwrite(file, "%u", data);
+        end
+      end
+
+      if(i_tlast) begin
+        hdr <= 1'b1;
+      end
+    end
+  end
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/file_source.v b/fpga/usrp3/lib/rfnoc/file_source.v
new file mode 100644
index 000000000..160cd9984
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/file_source.v
@@ -0,0 +1,183 @@
+
+// Copyright 2014, Ettus Research
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+
+// Dummy data source.  Turn it on by setting a packet length in its setting reg, turn it off by setting 0.  
+// Will generate as fast as it can.
+
+module file_source #(
+  parameter SR_ENABLE              = 0,
+  parameter SR_PKT_LENGTH          = 1,
+  parameter SR_RATE                = 2,
+  parameter SR_SEND_TIME           = 3,
+  parameter SR_SWAP_SAMPLES        = 4, // 0: Do nothing, 1: 8-bit swap, 2: 16-bit, 3: 32-bit
+  parameter SR_ENDIANNESS          = 5, // 0: Do nothing, 1: 16-bit boundary, 2: 32-bit
+  // Default (after reset) values for above settings register set to sc16
+  parameter DEFAULT_SWAP_SAMPLES   = 2,
+  parameter DEFAULT_ENDIANNESS     = 2,
+  parameter FILE_LENGTH            = 65536, // Bytes
+  parameter FILENAME="")
+(
+  input clk, input reset, input [31:0] sid,
+  input set_stb, input [7:0] set_addr, input [31:0] set_data,
+  output [63:0] o_tdata, output o_tlast, output o_tvalid, input o_tready);
+
+  reg [63:0] mem[0:FILE_LENGTH/8-1];
+  integer    file, file_length;
+  reg [$clog2(FILE_LENGTH/8)-1:0] index;
+  integer i;
+
+  initial begin
+    if (FILENAME != "") begin
+      $readmemh(FILENAME, mem);
+    end
+  end
+
+  wire [31:0] sid;
+  reg  [11:0] seqnum;
+  wire [15:0] rate;
+  reg  [1:0]  state;
+  reg  [15:0] line_number;
+
+  wire [63:0] int_tdata;
+  wire        int_tlast, int_tvalid, int_tready;
+
+  wire        enable;
+  wire [15:0] len;
+  reg  [15:0] count;
+  wire        send_time;
+  wire [1:0]  swap_samples;
+  wire [1:0]  endianness;
+
+  setting_reg #(.my_addr(SR_ENABLE), .width(1)) sr_sid (
+    .clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
+    .out(enable), .changed());
+
+  setting_reg #(.my_addr(SR_PKT_LENGTH), .width(16)) sr_len (
+    .clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
+    .out(len), .changed());
+
+  setting_reg #(.my_addr(SR_RATE), .width(16)) sr_rate (
+    .clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
+    .out(rate), .changed());
+
+  setting_reg #(.my_addr(SR_SEND_TIME), .width(1)) sr_send_time (
+    .clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
+    .out(send_time), .changed());
+
+  setting_reg #(
+    .my_addr(SR_SWAP_SAMPLES), .width(2), .at_reset(DEFAULT_SWAP_SAMPLES))
+  sr_swap_samples (
+    .clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
+    .out(swap_samples), .changed());
+
+  setting_reg #(
+    .my_addr(SR_ENDIANNESS), .width(2), .at_reset(DEFAULT_ENDIANNESS))
+  sr_endianness (
+    .clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
+    .out(endianness), .changed());
+
+  localparam IDLE = 2'd0;
+  localparam HEAD = 2'd1;
+  localparam TIME = 2'd2;
+  localparam DATA = 2'd3;
+
+  always @(posedge clk) begin
+    if(reset) begin
+      state <= IDLE;
+      count <= 0;
+      index <= 0;
+      seqnum <= 0;
+    end else begin
+      case (state)
+        IDLE : begin
+          if (len != 0) begin
+            state <= HEAD;
+          end
+        end
+        HEAD : begin
+          if (int_tvalid & int_tready) begin
+            count <= 1;
+            seqnum <= seqnum + 1;
+            if (send_time) begin
+              state <= TIME;
+            end else begin
+              state <= DATA;
+            end
+          end
+        end
+        TIME : begin
+          if (int_tvalid & int_tready) begin
+            state <= DATA;
+          end
+        end
+        DATA : begin
+          if (int_tvalid & int_tready) begin
+            index <= index + 1;
+            if (count == len) begin
+              state <= IDLE;
+              count <= 0;
+            end else begin
+              count <= count + 1;
+            end
+          end
+        end
+        default : state <= IDLE;
+      endcase
+    end
+  end
+
+  reg [63:0] time_cnt;
+  always @(posedge clk) begin
+    if (reset) begin
+      time_cnt <= 'd0;
+    end else begin
+      time_cnt <= time_cnt + 1;
+    end
+  end
+
+  wire [15:0] pkt_len = { len[12:0], 3'b000 } + 16'd8 + (send_time ? 16'd8 : 16'd0);
+
+  wire [63:0] data_int = mem[index];
+  // Swap endianness
+  wire [63:0] data = (endianness == 2'd0) ?  data_int :
+                     (endianness == 2'd1) ? {data_int[47:32], data_int[63:48], data_int[15: 0], data_int[31:16]} :
+                     (endianness == 2'd2) ? {data_int[39:32], data_int[47:40], data_int[55:48], data_int[63:56],
+                                             data_int[ 7: 0], data_int[15: 8], data_int[23:16], data_int[31:24]} :
+                                             64'd0;
+  // Swap samples
+  wire [63:0] data_out = (swap_samples == 2'd0) ?  data :
+                         (swap_samples == 2'd1) ? {data[55:48], data[63:56], data[39:32], data[47:40],
+                                                   data[23:16], data[31:24], data[ 7: 0], data[15: 8]} :
+                         (swap_samples == 2'd2) ? {data[47:32], data[63:48], data[15: 0], data[31:16]} :
+                         (swap_samples == 2'd3) ? {data[31: 0], data[63:32]} :
+                                                   64'd0;
+
+  assign int_tdata = (state == HEAD) ? { 2'b00, send_time, 1'b0, seqnum, pkt_len, sid } :
+                     (state == TIME) ? time_cnt : data_out;
+
+  assign int_tlast = (count == len);
+
+  reg [15:0]  line_timer;
+  always @(posedge clk) begin
+    if (reset) begin
+       line_timer <= 0;
+    end else begin
+      if (line_timer == 0 || line_timer == 1) begin
+        line_timer <= rate;
+      end else begin
+        line_timer <= line_timer - 1;
+      end
+    end
+  end
+
+  assign int_tvalid = enable & ((state==HEAD)|(state==DATA)|(state==TIME)) & (line_timer==0 || line_timer==1);
+
+  axi_packet_gate #(.WIDTH(64)) gate (
+    .clk(clk), .reset(reset), .clear(1'b0),
+    .i_tdata(int_tdata), .i_tlast(int_tlast), .i_terror(1'b0), .i_tvalid(int_tvalid), .i_tready(int_tready),
+    .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready));
+
+endmodule // file_source
diff --git a/fpga/usrp3/lib/rfnoc/fir_filter_slice.v b/fpga/usrp3/lib/rfnoc/fir_filter_slice.v
new file mode 100644
index 000000000..3f83f54e3
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/fir_filter_slice.v
@@ -0,0 +1,74 @@
+//
+// Copyright 2017 Ettus Research
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Multiply-accumulate with preadder for use as a computation unit
+// in FIR filters. Designed to infer a DSP48 for all registers
+// and arithmetic.
+//
+// Parameters:
+//   IN_WIDTH                 - Input width
+//   COEFF_WIDTH              - Coefficient width
+//   ACCUM_WIDTH              - Accumulator width
+//   OUT_WIDTH                - Output width
+//
+module fir_filter_slice #(
+  parameter IN_WIDTH     = 16,
+  parameter COEFF_WIDTH  = 16,
+  parameter ACCUM_WIDTH  = 32,
+  parameter OUT_WIDTH    = 32)
+(
+  input clk,
+  input reset,
+  input clear,
+  input sample_in_stb,
+  input signed [IN_WIDTH-1:0] sample_in_a,       // Sample in
+  input signed [IN_WIDTH-1:0] sample_in_b,       // Sample in for symmetric filters
+  output signed [IN_WIDTH-1:0] sample_forward,   // Delayed sample in to forward
+  input signed [COEFF_WIDTH-1:0] coeff_in,       // Filter tap coefficient
+  output signed [COEFF_WIDTH-1:0] coeff_forward, // Filter tap coefficient to forward
+  input coeff_load_stb,                          // Load coefficient
+  input signed [ACCUM_WIDTH-1:0] sample_accum,   // Accumulating path
+  output signed [OUT_WIDTH-1:0] sample_out       // Result
+);
+
+  reg signed [IN_WIDTH-1:0] a_reg[0:1];
+  reg signed [IN_WIDTH-1:0] d_reg;
+  reg signed [IN_WIDTH:0] ad_reg;
+  reg signed [COEFF_WIDTH-1:0] b_reg[0:1];
+  reg signed [IN_WIDTH+COEFF_WIDTH:0] m_reg;
+  reg signed [ACCUM_WIDTH-1:0] p_reg;
+
+  always @(posedge clk) begin
+    if (reset | clear) begin
+      a_reg[0]   <= 0;
+      a_reg[1]   <= 0;
+      d_reg      <= 0;
+      b_reg[0]   <= 0;
+      b_reg[1]   <= 0;
+      ad_reg     <= 0;
+      m_reg      <= 0;
+      p_reg      <= 0;
+    end else begin
+      if (sample_in_stb) begin
+        a_reg[0] <= sample_in_a;
+        a_reg[1] <= a_reg[0];
+        d_reg    <= sample_in_b;
+        ad_reg   <= a_reg[1] + d_reg;
+        m_reg    <= ad_reg * b_reg[1];
+        p_reg    <= sample_accum + m_reg;
+      end
+      if (coeff_load_stb) begin
+        b_reg[0] <= coeff_in;
+      end
+      b_reg[1]   <= b_reg[0];
+    end
+  end
+
+  assign coeff_forward  = b_reg[0];
+  assign sample_forward = a_reg[1];
+  assign sample_out     = p_reg[OUT_WIDTH-1:0];
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/fosphor/axi_logpwr.v b/fpga/usrp3/lib/rfnoc/fosphor/axi_logpwr.v
new file mode 100644
index 000000000..037c33563
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/fosphor/axi_logpwr.v
@@ -0,0 +1,102 @@
+/*
+ * axi_logpwr.v
+ *
+ * Copyright (C) 2014  Ettus Corporation LLC
+ * Copyright 2018 Ettus Research, a National Instruments Company
+ *
+ * SPDX-License-Identifier: LGPL-3.0-or-later
+ *
+ * vim: ts=4 sw=4
+ */
+
+`ifdef SIM
+`default_nettype none
+`endif
+
+module axi_logpwr #(
+	parameter [1:0] RANDOM_MODE = 2'b11
+)(
+	input  clk, input reset,
+	input  [31:0] i_tdata, input  i_tlast, input  i_tvalid, output i_tready,
+	output [15:0] o_tdata, output o_tlast, output o_tvalid, input  o_tready
+);
+
+	// Signals
+	reg ready;
+	reg valid_1;
+	wire valid_12;
+	wire last_12;
+
+	wire [31:0] rng;
+
+	wire [15:0] in_real_0;
+	wire [15:0] in_imag_0;
+	wire [15:0] out_logpwr_12;
+
+	wire [16:0] fifo_di;
+	wire [16:0] fifo_do;
+	wire fifo_wren;
+	wire fifo_afull;
+	wire fifo_rden;
+	wire fifo_empty;
+
+ 	// Input control
+	assign in_real_0 = i_tdata[31:16];
+	assign in_imag_0 = i_tdata[15:0];
+
+	always @(posedge clk)
+	begin
+		ready <= ~fifo_afull | o_tready;
+		valid_1 <= i_tvalid & ready;
+	end
+
+	assign i_tready = ready;
+
+	// Delays
+	delay_bit #(11) dl_valid (valid_1, valid_12, clk);
+	delay_bit #(12) dl_last  (i_tlast, last_12, clk);
+
+	// RNG Instance
+    rng rng_I (
+		.out(rng),
+		.clk(clk),
+		.rst(reset)
+	);
+
+	// logpwr Instance
+	f15_logpwr logpwr_I (
+		.in_real_0(in_real_0),
+		.in_imag_0(in_imag_0),
+		.out_12(out_logpwr_12),
+		.rng(rng),
+		.random_mode(RANDOM_MODE),
+		.clk(clk),
+		.rst(reset)
+	);
+
+	// Output FIFO
+	assign fifo_di   = { last_12, out_logpwr_12 };
+	assign fifo_wren = { valid_12 };
+
+	fifo_srl #(
+		.WIDTH(17),
+		.LOG2_DEPTH(6),
+		.AFULL_LEVEL(49)
+	) fifo_I (
+		.di(fifo_di),
+		.wren(fifo_wren),
+		.afull(fifo_afull),
+		.do(fifo_do),
+		.rden(fifo_rden),
+		.empty(fifo_empty),
+		.clk(clk),
+		.rst(reset)
+	);
+
+	assign o_tdata  = fifo_do[15:0];
+	assign o_tlast  = fifo_do[16];
+	assign o_tvalid = ~fifo_empty;
+
+	assign fifo_rden = ~fifo_empty & o_tready;
+
+endmodule // axi_logpwr
diff --git a/fpga/usrp3/lib/rfnoc/fosphor/delay.v b/fpga/usrp3/lib/rfnoc/fosphor/delay.v
new file mode 100644
index 000000000..44c043642
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/fosphor/delay.v
@@ -0,0 +1,140 @@
+/*
+ * delay.v
+ *
+ * Generates a delay line/bus using a combination of SRL and Register
+ *
+ * Copyright (C) 2014  Ettus Corporation LLC
+ * Copyright 2018 Ettus Research, a National Instruments Company
+ *
+ * SPDX-License-Identifier: LGPL-3.0-or-later
+ *
+ * vim: ts=4 sw=4
+ */
+
+`ifdef SIM
+`default_nettype none
+`endif
+
+// ---------------------------------------------------------------------------
+// Single line delay
+// ---------------------------------------------------------------------------
+
+module delay_bit #(
+	parameter integer DELAY = 1
+)(
+	input  wire d,
+	output wire q,
+	input  wire clk
+);
+
+	// Signals
+	wire [4:0] addr = DELAY - 2;
+	wire ff_in;
+
+	// Generate SRL if needed (or bypass if not)
+	generate
+		if (DELAY > 17) begin
+			SRLC32E srl_I (
+				.Q(ff_in),
+				.A(addr),
+				.CE(1'b1),
+				.CLK(clk),
+				.D(d)
+			);
+		end else if (DELAY > 1) begin
+			SRL16E srl_I (
+				.Q(ff_in),
+				.A0(addr[0]),
+				.A1(addr[1]),
+				.A2(addr[2]),
+				.A3(addr[3]),
+				.CE(1'b1),
+				.CLK(clk),
+				.D(d)
+			);
+		end else begin
+			assign ff_in = d;
+		end
+	endgenerate
+
+	// Generate flip-flop if needed (or bypass if not)
+	generate
+		if (DELAY > 0) begin
+			FDRE ff_I (
+				.Q(q),
+				.C(clk),
+				.CE(1'b1),
+				.D(ff_in),
+				.R(1'b0)
+			);
+		end else begin
+			assign q = ff_in;
+		end
+	endgenerate
+
+endmodule // delay_bit
+
+
+// ---------------------------------------------------------------------------
+// Bus delay
+// ---------------------------------------------------------------------------
+
+module delay_bus #(
+	parameter integer DELAY = 1,
+	parameter integer WIDTH = 1
+)(
+	input  wire [WIDTH-1:0] d,
+	output wire [WIDTH-1:0] q,
+	input  wire clk
+);
+	genvar i;
+
+	// Variables / Signals
+	wire [4:0] addr = DELAY - 2;
+	wire [WIDTH-1:0] ff_in;
+
+	// Generate SRL if needed (or bypass if not)
+	generate
+		if (DELAY > 17) begin
+			for (i=0; i<WIDTH; i=i+1)
+				SRLC32E srl_I (
+					.Q(ff_in[i]),
+					.A(addr),
+					.CE(1'b1),
+					.CLK(clk),
+					.D(d[i])
+				);
+		end else if (DELAY > 1) begin
+			for (i=0; i<WIDTH; i=i+1)
+				SRL16E srl_I (
+					.Q(ff_in[i]),
+					.A0(addr[0]),
+					.A1(addr[1]),
+					.A2(addr[2]),
+					.A3(addr[3]),
+					.CE(1'b1),
+					.CLK(clk),
+					.D(d[i])
+				);
+		end else begin
+			assign ff_in = d;
+		end
+	endgenerate
+
+	// Generate flip-flop if needed (or bypass if not)
+	generate
+		if (DELAY > 0) begin
+			for (i=0; i<WIDTH; i=i+1)
+				FDRE ff_I (
+					.Q(q[i]),
+					.C(clk),
+					.CE(1'b1),
+					.D(ff_in[i]),
+					.R(1'b0)
+				);
+		end else begin
+			assign q = ff_in;
+		end
+	endgenerate
+
+endmodule // delay_bus
diff --git a/fpga/usrp3/lib/rfnoc/fosphor/f15_avg.v b/fpga/usrp3/lib/rfnoc/fosphor/f15_avg.v
new file mode 100644
index 000000000..30123ee20
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/fosphor/f15_avg.v
@@ -0,0 +1,117 @@
+/*
+ * f15_avg.v
+ *
+ * Applies the y(t+1) = alpha * y(t) + (1 - alpha) * x(t)
+ * to compute an IIR average
+ *
+ * Copyright (C) 2015  Ettus Corporation LLC
+ * Copyright 2018 Ettus Research, a National Instruments Company
+ *
+ * SPDX-License-Identifier: LGPL-3.0-or-later
+ *
+ * vim: ts=4 sw=4
+ */
+
+`ifdef SIM
+`default_nettype none
+`endif
+
+module f15_avg #(
+	parameter integer Y_WIDTH = 12,
+	parameter integer X_WIDTH = 16
+)(
+	input  wire [Y_WIDTH-1:0] yin_0,
+	input  wire [X_WIDTH-1:0] x_0,
+	input  wire [15:0] rng_0,
+	input  wire [15:0] alpha_0,
+	input  wire clear_0,
+	output wire [Y_WIDTH-1:0] yout_4,
+	input  wire clk,
+	input  wire rst
+);
+
+	// Signals
+	wire [X_WIDTH-1:0] x_2;
+	wire clear_3;
+	wire [47:0] pout_4;
+
+	// Main DSP Instance
+	DSP48E1 #(
+		.A_INPUT("DIRECT"),
+		.B_INPUT("DIRECT"),
+		.USE_DPORT("TRUE"),
+		.USE_MULT("MULTIPLY"),
+		.AUTORESET_PATDET("NO_RESET"),
+		.MASK(48'h3fffffffffff),
+		.PATTERN(48'h000000000000),
+		.SEL_MASK("MASK"),
+		.SEL_PATTERN("PATTERN"),
+		.USE_PATTERN_DETECT("PATDET"),
+		.ACASCREG(1),
+		.ADREG(1),
+		.ALUMODEREG(1),
+		.AREG(1),
+		.BCASCREG(1),
+		.BREG(2),
+		.CARRYINREG(1),
+		.CARRYINSELREG(1),
+		.CREG(1),
+		.DREG(1),
+		.INMODEREG(1),
+		.MREG(1),
+		.OPMODEREG(1),
+		.PREG(1),
+		.USE_SIMD("ONE48")
+	)
+	dsp_avg_I (
+		.P(pout_4),
+		.ACIN(30'h0),
+		.BCIN(18'h0),
+		.CARRYCASCIN(1'h0),
+		.MULTSIGNIN(1'h0),
+		.PCIN(48'h000000000000),
+		.ALUMODE(4'b0000),		// Z + X + Y + CIN
+		.CARRYINSEL(3'h0),
+		.CEINMODE(1'b1),
+		.CLK(clk),
+		.INMODE(5'b01100),		// B=B2, A=D-A2
+		.OPMODE(7'b0110101),	// X=M1, Y=M2, Z=C
+		.RSTINMODE(rst),
+		.A({{(30-X_WIDTH){1'b0}}, x_0}),
+		.B({2'h0, alpha_0}),
+		.C({{(32-X_WIDTH){1'b0}}, x_2, 16'h8000}),
+		.CARRYIN(1'b0),
+		.D({{(25-X_WIDTH){1'b0}}, yin_0, rng_0[X_WIDTH-Y_WIDTH-1:0]}),
+		.CEA1(1'b0),
+		.CEA2(1'b1),
+		.CEAD(1'b1),
+		.CEALUMODE(1'b1),
+		.CEB1(1'b1),
+		.CEB2(1'b1),
+		.CEC(1'b1),
+		.CECARRYIN(1'b1),
+		.CECTRL(1'b1),
+		.CED(1'b1),
+		.CEM(1'b1),
+		.CEP(1'b1),
+		.RSTA(rst),
+		.RSTALLCARRYIN(rst),
+		.RSTALUMODE(rst),
+		.RSTB(rst),
+		.RSTC(rst),
+		.RSTCTRL(rst),
+		.RSTD(rst),
+		.RSTM(rst),
+		.RSTP(clear_3)
+	);
+
+	// Delay x for the C input
+	delay_bus #(2, X_WIDTH) dl_x (x_0, x_2, clk);
+
+	// Delay clear to use as reset for P
+	delay_bit #(3) dl_clear (clear_0, clear_3, clk);
+
+	// Map the output
+	assign yout_4 = pout_4[X_WIDTH+15:X_WIDTH-Y_WIDTH+16];
+
+endmodule // f15_avg
diff --git a/fpga/usrp3/lib/rfnoc/fosphor/f15_binmap.v b/fpga/usrp3/lib/rfnoc/fosphor/f15_binmap.v
new file mode 100644
index 000000000..36935a0e9
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/fosphor/f15_binmap.v
@@ -0,0 +1,139 @@
+/*
+ * f15_binmap.v
+ *
+ * Maps a log pwr value to an histogram bin
+ *
+ * Copyright (C) 2014  Ettus Corporation LLC
+ * Copyright 2018 Ettus Research, a National Instruments Company
+ *
+ * SPDX-License-Identifier: LGPL-3.0-or-later
+ *
+ * vim: ts=4 sw=4
+ */
+
+`ifdef SIM
+`default_nettype none
+`endif
+
+module f15_binmap #(
+	parameter integer BIN_WIDTH = 6,
+	parameter integer SCALE_FRAC_BITS = 8
+)(
+	input  wire [15:0] in_0,
+	input  wire [15:0] offset_0,		// unsigned
+	input  wire [15:0] scale_0,			// unsigned
+	output reg  [BIN_WIDTH-1:0] bin_5,	// bin number
+	output reg  sat_ind_5,				// saturation indicator
+	input  wire clk,
+	input  wire rst
+);
+	localparam integer TBI = 15 + SCALE_FRAC_BITS;	// Top-Bit-Index
+
+	// Signals
+	wire [47:0] dsp_pout_4;
+	wire dsp_pat_match_4;
+
+
+	// Main DSP
+	// --------
+	// computes (in - cfg_offset) * cfg_scale
+
+	DSP48E1 #(
+		.A_INPUT("DIRECT"),
+		.B_INPUT("DIRECT"),
+		.USE_DPORT("TRUE"),
+		.USE_MULT("MULTIPLY"),
+		.AUTORESET_PATDET("NO_RESET"),
+		.MASK({1'b1, {(46-TBI){1'b0}}, {(TBI+1){1'b1}}}),
+		.PATTERN(48'h000000000000),
+		.SEL_MASK("MASK"),
+		.SEL_PATTERN("PATTERN"),
+		.USE_PATTERN_DETECT("PATDET"),
+		.ACASCREG(1),
+		.ADREG(1),
+		.ALUMODEREG(1),
+		.AREG(1),
+		.BCASCREG(2),
+		.BREG(2),
+		.CARRYINREG(1),
+		.CARRYINSELREG(1),
+		.CREG(1),
+		.DREG(1),
+		.INMODEREG(1),
+		.MREG(1),
+		.OPMODEREG(1),
+		.PREG(1),
+		.USE_SIMD("ONE48")
+	)
+	dsp_binmap_I (
+		.PATTERNDETECT(dsp_pat_match_4),
+		.P(dsp_pout_4),
+		.ACIN(30'h0),
+		.BCIN(18'h0),
+		.CARRYCASCIN(1'h0),
+		.MULTSIGNIN(1'h0),
+		.PCIN(48'h000000000000),
+		.ALUMODE(4'b0000),		// Z + X + Y + CIN
+		.CARRYINSEL(3'h0),
+		.CEINMODE(1'b1),
+		.CLK(clk),
+		.INMODE(5'b01100),		// B=B2, A=D-A2
+		.OPMODE(7'b0000101),	// X=M1, Y=M2, Z=0
+		.RSTINMODE(rst),
+		.A({14'h0, offset_0}),
+		.B({ 2'h0, scale_0}),
+		.C({48'h0}),
+		.CARRYIN(1'b0),
+		.D({ 9'h0, in_0}),
+		.CEA1(1'b0),
+		.CEA2(1'b1),
+		.CEAD(1'b1),
+		.CEALUMODE(1'b1),
+		.CEB1(1'b1),
+		.CEB2(1'b1),
+		.CEC(1'b1),
+		.CECARRYIN(1'b1),
+		.CECTRL(1'b1),
+		.CED(1'b1),
+		.CEM(1'b1),
+		.CEP(1'b1),
+		.RSTA(rst),
+		.RSTALLCARRYIN(rst),
+		.RSTALUMODE(rst),
+		.RSTB(rst),
+		.RSTC(rst),
+		.RSTCTRL(rst),
+		.RSTD(rst),
+		.RSTM(rst),
+		.RSTP(rst)
+	);
+
+
+	// Post-DSP mapping & saturation
+	// -----------------------------
+
+	always @(posedge clk)
+	begin
+		if (rst == 1) begin
+			bin_5 <= 0;
+			sat_ind_5 <= 0;
+		end else begin
+			// Undeflow
+			if (dsp_pout_4[47] == 1) begin
+				bin_5 <= {BIN_WIDTH{1'b0}};
+				sat_ind_5 <= 1;
+
+			// Overflow
+			end else if (dsp_pat_match_4 == 0) begin
+				bin_5 <= {BIN_WIDTH{1'b1}};
+				sat_ind_5 <= 1;
+
+			// In-range
+			end else begin
+				bin_5 <= dsp_pout_4[TBI:TBI-BIN_WIDTH+1];
+				sat_ind_5 <= 0;
+			end
+		end
+	end
+
+endmodule // f15_binmap
diff --git a/fpga/usrp3/lib/rfnoc/fosphor/f15_core.v b/fpga/usrp3/lib/rfnoc/fosphor/f15_core.v
new file mode 100644
index 000000000..003fd1d50
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/fosphor/f15_core.v
@@ -0,0 +1,609 @@
+/*
+ * f15_core.v
+ *
+ * Core of the fosphor IP
+ *
+ * Copyright (C) 2014,2015  Ettus Corporation LLC
+ * Copyright 2018 Ettus Research, a National Instruments Company
+ *
+ * SPDX-License-Identifier: LGPL-3.0-or-later
+ *
+ * vim: ts=4 sw=4
+ */
+
+`ifdef SIM
+`default_nettype none
+`endif
+
+module f15_core (
+	input  clk, input reset,
+	input  clear_req,
+	input  [ 1:0] cfg_random,
+	input  [15:0] cfg_offset, input [15:0] cfg_scale,
+	input  [15:0] cfg_trise,  input [15:0] cfg_tdecay,
+	input  [15:0] cfg_alpha,  input [15:0] cfg_epsilon,
+	input  [11:0] cfg_decim, input cfg_decim_changed,
+	input  [ 1:0] cfg_wf_div, input cfg_wf_mode,
+	input  [ 7:0] cfg_wf_decim, input cfg_wf_decim_changed,
+	input  [31:0] i_tdata, input  i_tlast, input  i_tvalid, output i_tready,
+	output [31:0] o_hist_tdata, output o_hist_tlast, output o_hist_tvalid, input o_hist_tready, output o_hist_teob,
+	output [31:0] o_wf_tdata,   output o_wf_tlast,   output o_wf_tvalid,   input o_wf_tready
+);
+	// Signals
+	reg [31:0] in_data;
+	reg in_last;
+	reg in_valid;
+	reg in_ready;
+
+	wire [15:0] proc_real_0, proc_imag_0;
+	wire [15:0] proc_logpwr_12, proc_logpwr_end;
+	wire proc_last_0, proc_last_12, proc_last_end;
+	wire proc_valid_0, proc_valid_12, proc_valid_end;
+
+	reg [5:0] proc_binscan_addr_end;
+	reg proc_binscan_last_end;
+	reg proc_clear_end;
+	reg clear_pending;
+
+	wire rise_last_0, rise_last_15;
+	wire rise_valid_0, rise_valid_15, rise_valid_24;
+	wire [15:0] rise_logpwr_0;
+	wire [5:0]  rise_pwrbin_5, rise_pwrbin_15;
+	reg  [9:0]  rise_addr_lsb_15;
+	wire [15:0] rise_addr_15, rise_addr_24;
+	wire [8:0]  rise_intensity_18, rise_intensity_23;
+	reg  [8:0]  rise_intensity_24;
+
+	wire decay_last_0, decay_last_9;
+	wire decay_valid_0, decay_valid_9;
+	reg  [ 9:0] decay_addr_lsb_0;
+	wire [15:0] decay_addr_0, decay_addr_9;
+	wire [8:0]  decay_intensity_3, decay_intensity_8;
+	reg  [8:0]  decay_intensity_9;
+	wire decay_clear_0, decay_clear_9;
+
+	reg  [10:0] sls_addr_0;
+	wire [10:0] sls_addr_6;
+	wire [35:0] sls_data_2, sls_data_6;
+	wire sls_last_0;
+	wire sls_valid_0, sls_valid_6;
+
+	wire [15:0] avgmh_logpwr_0, avgmh_logpwr_2;
+	wire avgmh_clear_0, avgmh_clear_2;
+	wire [11:0] avgmh_avg_2, avgmh_avg_6, avgmh_avg_9;
+	wire [11:0] avgmh_max_2, avgmh_max_6, avgmh_max_9;
+
+	wire [5:0] out_binaddr_0, out_binaddr_9;
+	wire out_binlast_0, out_binlast_9;
+	wire [33:0] out_hist_fifo_di;
+	wire out_hist_fifo_wren;
+	wire out_hist_fifo_afull;
+	wire [33:0] out_hist_fifo_do;
+	wire out_hist_fifo_rden;
+	wire out_hist_fifo_empty;
+
+	wire [11:0] wf_data_2, wf_data_5, wf_data_6;
+	wire [15:0] wf_logpwr_0, wf_logpwr_2;
+	wire [ 7:0] wf_out_data_5;
+	wire wf_last_0, wf_last_2, wf_out_last_5;
+	wire wf_valid_0, wf_valid_2, wf_out_valid_5;
+
+	reg  [ 1:0] out_wf_cnt;
+	reg  [32:0] out_wf_fifo_di;
+	reg  out_wf_fifo_wren;
+	wire out_wf_fifo_afull;
+	wire [32:0] out_wf_fifo_do;
+	wire out_wf_fifo_rden;
+	wire out_wf_fifo_empty;
+
+	wire [31:0] rng;
+
+
+	// -----------------------------------------------------------------------
+	// Input
+	// -----------------------------------------------------------------------
+
+	always @(posedge clk)
+	begin
+		// Control
+		if (reset) begin
+			in_valid <= 1'b0;
+			in_ready <= 1'b0;
+		end else begin
+			// Valid flag
+			in_valid <= i_tvalid & i_tready;
+
+			// We know we can get a sample if :
+			//  - Both outputs consumed a sample
+			//  - Both FIFOs have enough space
+			in_ready <= (o_hist_tready & o_wf_tready) |
+			            (~out_hist_fifo_afull & ~out_wf_fifo_afull);
+		end
+
+		// Data pipeline
+		in_data <= i_tdata;
+		in_last <= i_tlast;
+	end
+
+	assign i_tready = in_ready;
+
+
+	// -----------------------------------------------------------------------
+	// Processing chain
+	// -----------------------------------------------------------------------
+
+	// Input to this stage
+	assign proc_real_0  = in_data[31:16];
+	assign proc_imag_0  = in_data[15:0];
+	assign proc_last_0  = in_last;
+	assign proc_valid_0 = in_valid;
+
+	// Log power
+	f15_logpwr logpwr_I (
+		.in_real_0(proc_real_0),
+		.in_imag_0(proc_imag_0),
+		.out_12(proc_logpwr_12),
+		.rng(rng),
+		.random_mode(cfg_random),
+		.clk(clk),
+		.rst(reset)
+	);
+
+	// Aggregation
+		// Not supported ATM but this is where it would be
+
+	// Flag propagation
+	delay_bit #(12) dl_proc_last  (proc_last_0,  proc_last_12,  clk);
+	delay_bit #(12) dl_proc_valid (proc_valid_0, proc_valid_12, clk);
+
+	// Even/Odd resequencing
+	f15_eoseq #(
+		.WIDTH(16)
+	) eoseq_I (
+		.in_data(proc_logpwr_12),
+		.in_valid(proc_valid_12),
+		.in_last(proc_last_12),
+		.out_data(proc_logpwr_end),
+		.out_valid(proc_valid_end),
+		.out_last(proc_last_end),
+		.clk(clk),
+		.rst(reset)
+	);
+
+	// Bin address counter and clear process
+		// We do this here so we can propagate to every other stage with
+		// just delay lines
+	always @(posedge clk)
+	begin
+		if (reset) begin
+			proc_binscan_addr_end <= 6'd0;
+			proc_binscan_last_end <= 1'b0;
+		end else if (proc_valid_end & proc_last_end) begin
+			proc_binscan_addr_end <= proc_binscan_addr_end + 1;
+			proc_binscan_last_end <= (proc_binscan_addr_end == 6'h3e);
+		end
+	end
+
+	always @(posedge clk)
+	begin
+		if (reset) begin
+			clear_pending  <= 1'b0;
+			proc_clear_end <= 1'b0;
+		end else begin
+			if (proc_valid_end & proc_last_end & proc_binscan_last_end) begin
+				clear_pending  <= 1'b0;
+				proc_clear_end <= clear_pending;
+			end else begin
+				clear_pending  <= clear_pending | clear_req;
+			end
+		end
+	end
+
+
+	// -----------------------------------------------------------------------
+	// Rise
+	// -----------------------------------------------------------------------
+
+	// Input of this stage
+	assign rise_last_0   = proc_last_end;
+	assign rise_valid_0  = proc_valid_end;
+	assign rise_logpwr_0 = proc_logpwr_end;
+
+	// Power Bin mapping
+	f15_binmap #(
+		.BIN_WIDTH(6),
+		.SCALE_FRAC_BITS(8)
+	) binmap_I (
+		.in_0(rise_logpwr_0),
+		.offset_0(cfg_offset),
+		.scale_0(cfg_scale),
+		.bin_5(rise_pwrbin_5),
+		.sat_ind_5(),				// FIXME: Could be use to disable write ena (configurable)
+		.clk(clk),
+		.rst(reset)
+	);
+
+	// Delay
+	// (We need to make sure rise doesn't conflict with decay)
+	delay_bus #(10, 6) dl_pwrbin (rise_pwrbin_5, rise_pwrbin_15, clk);
+	delay_bit #(15)    dl_valid  (rise_valid_0,  rise_valid_15,  clk);
+	delay_bit #(15)    dl_last   (rise_last_0,   rise_last_15,   clk);
+
+	// Address
+	always @(posedge clk)
+	begin
+		if (reset)
+			rise_addr_lsb_15[9:0] <= 9'd0;
+		else if (rise_valid_15)
+			if (rise_last_15)
+				rise_addr_lsb_15 <= 9'd0;
+			else
+				rise_addr_lsb_15 <= rise_addr_lsb_15[9:0] + 1;
+	end
+
+	assign rise_addr_15 = { rise_pwrbin_15, rise_addr_lsb_15 };
+
+	// Exponential rise
+	f15_rise_decay #(
+		.WIDTH(9)
+	) rise_I (
+		.in_0(rise_intensity_18),
+		.out_5(rise_intensity_23),
+		.k_0(cfg_trise),
+		.ena_0(1'b1),
+		.mode_0(1'b0),
+		.rng(rng[15:0]),
+		.clk(clk),
+		.rst(reset)
+	);
+
+	// Need one more stage just for proper even/odd interlacing
+	always @(posedge clk)
+		rise_intensity_24 <= rise_intensity_23;
+
+	// Propagate control
+	delay_bit #(9)     dl_rise_valid2 (rise_valid_15, rise_valid_24, clk);
+	delay_bus #(9, 16) dl_rise_addr2  (rise_addr_15,  rise_addr_24,  clk);
+
+
+	// -----------------------------------------------------------------------
+	// State storage
+	// -----------------------------------------------------------------------
+
+	f15_histo_mem #(
+		.ADDR_WIDTH(16)
+	) mem_I (
+		// Rise readout
+		.addr_AR(rise_addr_15),
+		.data_AR(rise_intensity_18),
+		.ena_AR(rise_valid_15),
+
+		// Rise writeback
+		.addr_AW(rise_addr_24),
+		.data_AW(rise_intensity_24),
+		.ena_AW(rise_valid_24),
+
+		// Decay readout
+		.addr_BR(decay_addr_0),
+		.data_BR(decay_intensity_3),
+		.ena_BR(decay_valid_0),
+
+		// Decay writeback
+		.addr_BW(decay_addr_9),
+		.data_BW(decay_intensity_9),
+		.ena_BW(decay_valid_9),
+
+		// Common
+		.clk(clk),
+		.rst(reset)
+	);
+
+
+	// -----------------------------------------------------------------------
+	// Decay & Clear
+	// -----------------------------------------------------------------------
+
+	// Input of this stage
+	assign decay_last_0  = proc_last_end;
+	assign decay_valid_0 = proc_valid_end;
+	assign decay_clear_0 = proc_clear_end;
+
+	// Address generation
+	always @(posedge clk)
+	begin
+		if (reset)
+			decay_addr_lsb_0 <= 10'd0;
+		else if (decay_valid_0)
+			if (decay_last_0)
+				decay_addr_lsb_0 <= 10'd0;
+			else
+				decay_addr_lsb_0 <= decay_addr_lsb_0 + 1;
+	end
+
+	assign decay_addr_0 = { proc_binscan_addr_end, decay_addr_lsb_0 };
+
+	// Exponential decay
+	f15_rise_decay #(
+		.WIDTH(9)
+	) decay_I (
+		.in_0(decay_intensity_3),
+		.out_5(decay_intensity_8),
+		.k_0(cfg_tdecay),
+		.ena_0(1'b1),
+		.mode_0(1'b1),
+		.rng(rng[15:0]),
+		.clk(clk),
+		.rst(reset)
+	);
+
+	// Need one more stage just for proper even/odd interlacing
+	// Also do the clear in there
+	always @(posedge clk)
+		if (decay_clear_9)
+			decay_intensity_9 <= 9'd0;
+		else
+			decay_intensity_9 <= decay_intensity_8;
+
+	// Propagate control
+	delay_bit #(9)     dl_decay_valid (decay_valid_0, decay_valid_9, clk);
+	delay_bit #(9)     dl_decay_last  (decay_last_0,  decay_last_9,  clk);
+	delay_bit #(9)     dl_decay_clear (decay_clear_0, decay_clear_9, clk);
+	delay_bus #(9, 16) dl_decay_addr  (decay_addr_0,  decay_addr_9,  clk);
+
+
+	// -----------------------------------------------------------------------
+	// Shared line-storage
+	// -----------------------------------------------------------------------
+		// This is shared between the average/max-hold spectrum lines and the
+		// waterfall aggregation
+
+	// Input of this stage
+	assign sls_last_0   = proc_last_end;
+	assign sls_valid_0  = proc_valid_end;
+
+	// Address
+	always @(posedge clk)
+	begin
+		if (reset)
+			sls_addr_0 <= 11'd0;
+		else if (sls_valid_0)
+			if (sls_last_0)
+				sls_addr_0 <= 11'd0;
+			else
+				sls_addr_0 <= sls_addr_0 + 1;
+	end
+
+	delay_bus #(6, 11) dl_sls_addr  (sls_addr_0,  sls_addr_6,  clk);
+	delay_bit #(6)     dl_sls_valid (sls_valid_0, sls_valid_6, clk);
+
+	// Storage
+	f15_line_mem #(
+		.AWIDTH(11),
+		.DWIDTH(36)
+	) line_mem_I (
+		.rd_addr(sls_addr_0),
+		.rd_data(sls_data_2),
+		.rd_ena(sls_valid_0),
+		.wr_addr(sls_addr_6),
+		.wr_data(sls_data_6),
+		.wr_ena(sls_valid_6),
+		.clk(clk),
+		.rst(reset)
+	);
+
+	// Data mapping
+	assign avgmh_avg_2 = sls_data_2[11: 0];
+	assign avgmh_max_2 = sls_data_2[23:12];
+	assign wf_data_2   = sls_data_2[35:24];
+
+	assign sls_data_6[11: 0] = avgmh_avg_6;
+	assign sls_data_6[23:12] = avgmh_max_6;
+	assign sls_data_6[35:24] = wf_data_6;
+
+
+	// -----------------------------------------------------------------------
+	// Average and Max-Hold
+	// -----------------------------------------------------------------------
+
+	// Input of this stage
+	assign avgmh_logpwr_0 = proc_logpwr_end;
+	assign avgmh_clear_0  = proc_clear_end;
+
+	// Modify stage: Average
+	f15_avg #(
+		.Y_WIDTH(12),
+		.X_WIDTH(16)
+	) avg_I (
+		.yin_0(avgmh_avg_2),
+		.x_0(avgmh_logpwr_2),
+		.rng_0(rng[15:0]),
+		.alpha_0(cfg_alpha),
+		.clear_0(avgmh_clear_2),
+		.yout_4(avgmh_avg_6),
+		.clk(clk),
+		.rst(reset)
+	);
+
+	// Modify stage: Max Hold
+	f15_maxhold #(
+		.Y_WIDTH(12),
+		.X_WIDTH(16),
+		.FRAC_WIDTH(8)
+	) maxhold_I (
+		.yin_0(avgmh_max_2),
+		.x_0(avgmh_logpwr_2),
+		.rng_0(rng[15:0]),
+		.epsilon_0(cfg_epsilon),
+		.clear_0(avgmh_clear_2),
+		.yout_4(avgmh_max_6),
+		.clk(clk),
+		.rst(reset)
+	);
+
+	// Delays
+	delay_bus #(2, 16) dl_avgmh_logpwr (avgmh_logpwr_0, avgmh_logpwr_2, clk);
+	delay_bit #(2)     dl_avgmh_clear  (avgmh_clear_0,  avgmh_clear_2,  clk);
+	delay_bus #(3, 12) dl_avgmh_max    (avgmh_max_6,    avgmh_max_9,    clk);
+	delay_bus #(3, 12) dl_avgmh_avg    (avgmh_avg_6,    avgmh_avg_9,    clk);
+
+
+	// -----------------------------------------------------------------------
+	// Histogram Output
+	// -----------------------------------------------------------------------
+
+		// For the 'tap' to work, we need avmh and decay blocks to have the
+		// same number of pipeline stage and be right after proc.
+
+	// Input of this stage
+	assign out_binaddr_0 = proc_binscan_addr_end;
+	assign out_binlast_0 = proc_binscan_last_end;
+
+	// Delays
+	delay_bus #(9, 6) dl_out_binaddr (out_binaddr_0, out_binaddr_9, clk);
+	delay_bit #(9)    dl_out_binlast (out_binlast_0, out_binlast_9, clk);
+
+	// Packetizer
+	f15_packetizer #(
+		.BIN_WIDTH(6),
+		.DECIM_WIDTH(12)
+	) packetizer_I (
+		.in_bin_addr(out_binaddr_9),
+		.in_bin_last(out_binlast_9),
+		.in_histo(decay_intensity_9[8:1]),
+		.in_spectra_max(avgmh_max_9[11:4]),
+		.in_spectra_avg(avgmh_avg_9[11:4]),
+		.in_last(decay_last_9),
+		.in_valid(decay_valid_9),
+		.out_data(out_hist_fifo_di[31:0]),
+		.out_last(out_hist_fifo_di[32]),
+		.out_eob(out_hist_fifo_di[33]),
+		.out_valid(out_hist_fifo_wren),
+		.cfg_decim(cfg_decim),
+		.cfg_decim_changed(cfg_decim_changed),
+		.clk(clk),
+		.rst(reset)
+	);
+
+	// FIFO
+	fifo_srl #(
+		.WIDTH(34),
+		.LOG2_DEPTH(6),
+		.AFULL_LEVEL(20)
+	) out_hist_fifo_I (
+		.di(out_hist_fifo_di),
+		.wren(out_hist_fifo_wren),
+		.afull(out_hist_fifo_afull),
+		.do(out_hist_fifo_do),
+		.rden(out_hist_fifo_rden),
+		.empty(out_hist_fifo_empty),
+		.clk(clk),
+		.rst(reset)
+	);
+
+	// AXI mapping
+	assign o_hist_tdata = out_hist_fifo_do[31:0];
+	assign o_hist_tlast = out_hist_fifo_do[32];
+	assign o_hist_teob  = out_hist_fifo_do[33];
+	assign o_hist_tvalid = ~out_hist_fifo_empty;
+	assign out_hist_fifo_rden = ~out_hist_fifo_empty && o_hist_tready;
+
+
+	// -----------------------------------------------------------------------
+	// Waterfall Output
+	// -----------------------------------------------------------------------
+
+	// Input to this stage (synced to SLS)
+	assign wf_logpwr_0 = proc_logpwr_end;
+	assign wf_last_0   = proc_last_end;
+	assign wf_valid_0  = proc_valid_end;
+
+	// Delay some input signals
+	delay_bus #(2, 16) dl_wf_logpwr (wf_logpwr_0, wf_logpwr_2, clk);
+	delay_bit #(2)     dl_wf_last   (wf_last_0,   wf_last_2,   clk);
+	delay_bit #(2)     dl_wf_valid  (wf_valid_0,  wf_valid_2,  clk);
+
+	// Decimation / Aggregation
+	f15_wf_agg #(
+		.Y_WIDTH(12),
+		.X_WIDTH(16),
+		.DECIM_WIDTH(8)
+	) dut_wf (
+		.yin_0(wf_data_2),
+		.x_0(wf_logpwr_2),
+		.valid_0(wf_valid_2),
+		.last_0(wf_last_2),
+		.rng_0(rng[15:0]),
+		.yout_3(wf_data_5),
+		.zout_3(wf_out_data_5),
+		.zvalid_3(wf_out_valid_5),
+		.cfg_div(cfg_wf_div),
+		.cfg_mode(cfg_wf_mode),
+		.cfg_decim(cfg_wf_decim),
+		.cfg_decim_changed(cfg_wf_decim_changed),
+		.clk(clk),
+		.rst(reset)
+	);
+
+	// Delay some output signals
+	delay_bus #(1, 12) dl_wf_data     (wf_data_5, wf_data_6, clk);
+	delay_bit #(3)     dl_wf_out_last (wf_last_2, wf_out_last_5, clk);
+
+	// Pack into 32 bits words
+	always @(posedge clk)
+	begin
+		if (reset) begin
+			out_wf_fifo_di   <= 0;
+			out_wf_fifo_wren <= 1'b0;
+			out_wf_cnt       <= 2'b00;
+		end else begin
+			if (wf_out_valid_5) begin
+				if (wf_out_last_5) begin
+					out_wf_fifo_di   <= { 1'b1, out_wf_fifo_di[23:0], wf_out_data_5 };
+					out_wf_fifo_wren <= 1'b1;
+					out_wf_cnt       <= 2'b00;
+				end else begin
+					out_wf_fifo_di   <= { 1'b0, out_wf_fifo_di[23:0], wf_out_data_5 };
+					out_wf_fifo_wren <= (out_wf_cnt == 2'b11);
+					out_wf_cnt       <= out_wf_cnt + 1;
+				end
+			end else begin
+				out_wf_fifo_wren <= 1'b0;
+			end
+		end
+	end
+
+	// FIFO
+	fifo_srl #(
+		.WIDTH(33),
+		.LOG2_DEPTH(6),
+		.AFULL_LEVEL(20)
+	) out_wf_fifo_I (
+		.di(out_wf_fifo_di),
+		.wren(out_wf_fifo_wren),
+		.afull(out_wf_fifo_afull),
+		.do(out_wf_fifo_do),
+		.rden(out_wf_fifo_rden),
+		.empty(out_wf_fifo_empty),
+		.clk(clk),
+		.rst(reset)
+	);
+
+	// AXI mapping
+	assign o_wf_tdata = out_wf_fifo_do[31:0];
+	assign o_wf_tlast = out_wf_fifo_do[32];
+	assign o_wf_tvalid = ~out_wf_fifo_empty;
+	assign out_wf_fifo_rden = ~out_wf_fifo_empty && o_wf_tready;
+
+
+	// -----------------------------------------------------------------------
+	// Misc
+	// -----------------------------------------------------------------------
+
+	// RNG
+`ifdef SIM
+	assign rng = 0;
+`else
+	rng rng_I (rng, clk, reset);
+`endif
+
+endmodule // f15_core
diff --git a/fpga/usrp3/lib/rfnoc/fosphor/f15_eoseq.v b/fpga/usrp3/lib/rfnoc/fosphor/f15_eoseq.v
new file mode 100644
index 000000000..6d209cd16
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/fosphor/f15_eoseq.v
@@ -0,0 +1,78 @@
+/*
+ * f15_eoseq.v
+ *
+ * Resequence a data flow with data/valid/last ensuring EVEN/ODD
+ * sequencing (even data on even cycles, odd data on odd cycles)
+ *
+ * Copyright (C) 2014  Ettus Corporation LLC
+ * Copyright 2018 Ettus Research, a National Instruments Company
+ *
+ * SPDX-License-Identifier: LGPL-3.0-or-later
+ *
+ * vim: ts=4 sw=4
+ */
+
+`ifdef SIM
+`default_nettype none
+`endif
+
+module f15_eoseq #(
+	parameter integer WIDTH = 16
+)(
+	input  wire [WIDTH-1:0] in_data,
+	input  wire in_valid,
+	input  wire in_last,
+	output reg  [WIDTH-1:0] out_data,
+	output reg  out_valid,
+	output reg  out_last,
+	input  wire clk,
+	input  wire rst
+);
+
+	// Signals
+	reg [WIDTH-1:0] buf_data;
+	reg buf_valid;
+	reg buf_last;
+
+	wire flip;
+	reg odd;
+	reg sel;
+
+	// Control
+	always @(posedge clk)
+		if (rst)
+			odd <= 1'b0;
+		else
+			odd <= ~(in_last & in_valid) & (odd ^ in_valid);
+
+	always @(posedge clk)
+		if (rst)
+			sel <= 1'b0;
+		else if (flip)
+			sel <= ~sel;
+
+	assign flip = ~in_valid | (in_last & ~odd);
+
+	// Buffer
+	always @(posedge clk)
+	begin
+		buf_data  <= in_data;
+		buf_valid <= in_valid;
+		buf_last  <= in_last;
+	end
+
+	// Output
+	always @(posedge clk)
+	begin
+		if (sel) begin
+			out_data  <= buf_data;
+			out_valid <= buf_valid;
+			out_last  <= buf_last;
+		end else begin
+			out_data  <= in_data;
+			out_valid <= in_valid;
+			out_last  <= in_last;
+		end
+	end
+
+endmodule // f15_eoseq
diff --git a/fpga/usrp3/lib/rfnoc/fosphor/f15_histo_mem.v b/fpga/usrp3/lib/rfnoc/fosphor/f15_histo_mem.v
new file mode 100644
index 000000000..7a7f7e279
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/fosphor/f15_histo_mem.v
@@ -0,0 +1,287 @@
+/*
+ * f15_histo_mem.v
+ *
+ * Histogram State storage. Basically a memory with 2 R/W ports where
+ * each port can do read & write at different address at the same time
+ * if those address are inteleaved (like read at odd address when writing
+ * to even address).
+ *
+ * This allows two independent process to do READ/MODIFY/WRITE.
+ *
+ * Copyright (C) 2014  Ettus Corporation LLC
+ * Copyright 2018 Ettus Research, a National Instruments Company
+ *
+ * SPDX-License-Identifier: LGPL-3.0-or-later
+ *
+ * vim: ts=4 sw=4
+ */
+
+`ifdef SIM
+`default_nettype none
+`endif
+
+module f15_histo_mem #(
+	parameter integer ADDR_WIDTH = 16
+)(
+	// Port A Read
+	input  wire [ADDR_WIDTH-1:0] addr_AR,
+	output reg  [8:0] data_AR,
+	input  wire ena_AR,
+
+	// Port A Write
+	input  wire [ADDR_WIDTH-1:0] addr_AW,
+	input  wire [8:0] data_AW,
+	input  wire ena_AW,
+
+	// Port B Read
+	input  wire [ADDR_WIDTH-1:0] addr_BR,
+	output reg  [8:0] data_BR,
+	input  wire ena_BR,
+
+	// Port B Write
+	input  wire [ADDR_WIDTH-1:0] addr_BW,
+	input  wire [8:0] data_BW,
+	input  wire ena_BW,
+
+	// Error detection
+	output reg  conflict_A,
+	output reg  conflict_B,
+
+	// Common
+	input  wire clk,
+	input  wire rst
+);
+
+	// Signals
+		// Memory banks IF
+	wire [ADDR_WIDTH-2:0] even_addra, odd_addra;
+	wire [ADDR_WIDTH-2:0] even_addrb, odd_addrb;
+	wire [8:0] even_dia, odd_dia;
+	wire [8:0] even_dib, odd_dib;
+	wire [8:0] even_doa, odd_doa;
+	wire [8:0] even_dob, odd_dob;
+	wire even_wea, odd_wea;
+	wire even_web, odd_web;
+	wire even_rea, odd_rea;
+	wire even_reb, odd_reb;
+
+		// Control
+	wire sel_A, sel_B;
+
+
+	// Mux selection
+	assign sel_A = ena_AR ? addr_AR[0] : ~addr_AW[0];
+	assign sel_B = ena_BR ? addr_BR[0] : ~addr_BW[0];
+
+	// Conflict detection
+	always @(posedge clk)
+	begin
+		conflict_A <= !(addr_AR[0] ^ addr_AW[0]) & ena_AR & ena_AW;
+		conflict_B <= !(addr_BR[0] ^ addr_BW[0]) & ena_BR & ena_BW;
+	end
+
+	// Control signals
+	assign even_wea =  sel_A & ena_AW;
+	assign odd_wea  = !sel_A & ena_AW;
+	assign even_web =  sel_B & ena_BW;
+	assign odd_web  = !sel_B & ena_BW;
+	assign even_rea = !sel_A & ena_AR;
+	assign odd_rea  =  sel_A & ena_AR;
+	assign even_reb = !sel_B & ena_BR;
+	assign odd_reb  =  sel_B & ena_BR;
+
+	// Address path mapping
+	assign even_addra = sel_A ? addr_AW[ADDR_WIDTH-1:1] : addr_AR[ADDR_WIDTH-1:1];
+	assign even_addrb = sel_B ? addr_BW[ADDR_WIDTH-1:1] : addr_BR[ADDR_WIDTH-1:1];
+	assign odd_addra  = sel_A ? addr_AR[ADDR_WIDTH-1:1] : addr_AW[ADDR_WIDTH-1:1];
+	assign odd_addrb  = sel_B ? addr_BR[ADDR_WIDTH-1:1] : addr_BW[ADDR_WIDTH-1:1];
+
+	// Data path mapping
+	assign even_dia = data_AW;
+	assign odd_dia  = data_AW;
+	assign even_dib = data_BW;
+	assign odd_dib  = data_BW;
+
+	always @(posedge clk)
+	begin
+		data_AR <= even_doa | odd_doa;
+		data_BR <= even_dob | odd_dob;
+	end
+
+	// Instanciate memory banks
+	f15_histo_mem_bank #(
+		.ADDR_WIDTH(ADDR_WIDTH-1)
+	) mem_even (
+		.addra(even_addra),
+		.addrb(even_addrb),
+		.dia(even_dia),
+		.dib(even_dib),
+		.doa(even_doa),
+		.dob(even_dob),
+		.wea(even_wea),
+		.web(even_web),
+		.rea(even_rea),
+		.reb(even_reb),
+		.clk(clk),
+		.rst(rst)
+	);
+
+	f15_histo_mem_bank #(
+		.ADDR_WIDTH(ADDR_WIDTH-1)
+	) mem_odd (
+		.addra(odd_addra),
+		.addrb(odd_addrb),
+		.dia(odd_dia),
+		.dib(odd_dib),
+		.doa(odd_doa),
+		.dob(odd_dob),
+		.wea(odd_wea),
+		.web(odd_web),
+		.rea(odd_rea),
+		.reb(odd_reb),
+		.clk(clk),
+		.rst(rst)
+	);
+
+endmodule // f15_histo_mem
+
+
+module f15_histo_mem_bank #(
+	parameter integer ADDR_WIDTH = 15
+)(
+	input  wire [ADDR_WIDTH-1:0] addra,
+	input  wire [ADDR_WIDTH-1:0] addrb,
+	input  wire [8:0] dia,
+	input  wire [8:0] dib,
+	output reg  [8:0] doa,
+	output reg  [8:0] dob,
+	input  wire wea,
+	input  wire web,
+	input  wire rea,
+	input  wire reb,
+	input  wire clk,
+	input  wire rst
+);
+	localparam integer N_BRAMS = 1 << (ADDR_WIDTH - 12);
+	genvar i;
+	integer j;
+
+	// Signals
+		// Direct RAM connections
+	wire [15:0] ramb_addra;
+	wire [15:0] ramb_addrb;
+	wire [31:0] ramb_dia;
+	wire [31:0] ramb_dib;
+	wire [ 3:0] ramb_dipa;
+	wire [ 3:0] ramb_dipb;
+	wire [31:0] ramb_doa[0:N_BRAMS-1];
+	wire [31:0] ramb_dob[0:N_BRAMS-1];
+	wire [ 3:0] ramb_dopa[0:N_BRAMS-1];
+	wire [ 3:0] ramb_dopb[0:N_BRAMS-1];
+	wire        ramb_wea[0:N_BRAMS-1];
+	wire        ramb_web[0:N_BRAMS-1];
+	reg         ramb_rstdoa[0:N_BRAMS-1];
+	reg         ramb_rstdob[0:N_BRAMS-1];
+
+		// Control
+	reg onehota[0:N_BRAMS-1];
+	reg onehotb[0:N_BRAMS-1];
+
+	// Map address LSB and data inputs
+	assign ramb_addra = { 1'b0, addra[11:0], 3'b000 };
+	assign ramb_addrb = { 1'b0, addrb[11:0], 3'b000 };
+
+	assign ramb_dia   = { 16'h0000, dia[8:1] };
+	assign ramb_dib   = { 16'h0000, dib[8:1] };
+	assign ramb_dipa  = {  3'b000,  dia[0] };
+	assign ramb_dipb  = {  3'b000,  dib[0] };
+
+	// OR all the RAMB outputs
+	always @*
+	begin
+		doa = 9'h0;
+		dob = 9'h0;
+		for (j=0; j<N_BRAMS; j=j+1) begin
+			doa = doa | { ramb_doa[j][7:0], ramb_dopa[j][0] };
+			dob = dob | { ramb_dob[j][7:0], ramb_dopb[j][0] };
+		end
+	end
+
+	// Generate array
+	generate
+		for (i=0; i<N_BRAMS; i=i+1) begin
+
+			// Decode address MSB to one-hot signal
+			always @(addra,addrb)
+			begin
+				onehota[i] <= (addra[ADDR_WIDTH-1:12] == i) ? 1'b1 : 1'b0;
+				onehotb[i] <= (addrb[ADDR_WIDTH-1:12] == i) ? 1'b1 : 1'b0;
+			end
+
+			// If no read, then reset the output reg to zero
+			always @(posedge clk)
+			begin
+				ramb_rstdoa[i] <= !(onehota[i] & rea);
+				ramb_rstdob[i] <= !(onehotb[i] & reb);
+			end
+
+			// Mask the write enable with decoded address
+			assign ramb_wea[i] = onehota[i] & wea;
+			assign ramb_web[i] = onehotb[i] & web;
+
+			// Instantiate RAM Block
+			RAMB36E1 #(
+				.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
+				.SIM_COLLISION_CHECK("NONE"),
+				.DOA_REG(1),
+				.DOB_REG(1),
+				.EN_ECC_READ("FALSE"),
+				.EN_ECC_WRITE("FALSE"),
+				.RAM_EXTENSION_A("NONE"),
+				.RAM_EXTENSION_B("NONE"),
+				.RAM_MODE("TDP"),
+				.READ_WIDTH_A(9),
+				.READ_WIDTH_B(9),
+				.WRITE_WIDTH_A(9),
+				.WRITE_WIDTH_B(9),
+				.RSTREG_PRIORITY_A("RSTREG"),
+				.RSTREG_PRIORITY_B("RSTREG"),
+				.SIM_DEVICE("7SERIES"),
+				.SRVAL_A(36'h000000000),
+				.SRVAL_B(36'h000000000),
+				.WRITE_MODE_A("READ_FIRST"),
+				.WRITE_MODE_B("READ_FIRST")
+			)
+			mem_elem_I (
+				.DOADO(ramb_doa[i]),
+				.DOPADOP(ramb_dopa[i]),
+				.DOBDO(ramb_dob[i]),
+				.DOPBDOP(ramb_dopb[i]),
+				.CASCADEINA(1'b0),
+				.CASCADEINB(1'b0),
+				.INJECTDBITERR(1'b0),
+				.INJECTSBITERR(1'b0),
+				.ADDRARDADDR(ramb_addra),
+				.CLKARDCLK(clk),
+				.ENARDEN(1'b1),
+				.REGCEAREGCE(1'b1),
+				.RSTRAMARSTRAM(rst),
+				.RSTREGARSTREG(ramb_rstdoa[i]),
+				.WEA({3'b0, ramb_wea[i]}),
+				.DIADI(ramb_dia),
+				.DIPADIP(ramb_dipa),
+				.ADDRBWRADDR(ramb_addrb),
+				.CLKBWRCLK(clk),
+				.ENBWREN(1'b1),
+				.REGCEB(1'b1),
+				.RSTRAMB(rst),
+				.RSTREGB(ramb_rstdob[i]),
+				.WEBWE({7'b0, ramb_web[i]}),
+				.DIBDI(ramb_dib),
+				.DIPBDIP(ramb_dipb)
+			);
+
+		end
+	endgenerate
+
+endmodule // f15_histo_mem_bank
diff --git a/fpga/usrp3/lib/rfnoc/fosphor/f15_line_mem.v b/fpga/usrp3/lib/rfnoc/fosphor/f15_line_mem.v
new file mode 100644
index 000000000..7a98d5c6e
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/fosphor/f15_line_mem.v
@@ -0,0 +1,67 @@
+/*
+ * f15_line_mem.v
+ *
+ * Memory for a single line to compute max-hold / average
+ * Read latency is 2 and if read is not enabled, output data is forced
+ * to zero.
+ *
+ * Copyright (C) 2015  Ettus Corporation LLC
+ * Copyright 2018 Ettus Research, a National Instruments Company
+ *
+ * SPDX-License-Identifier: LGPL-3.0-or-later
+ *
+ * vim: ts=4 sw=4
+ */
+
+`ifdef SIM
+`default_nettype none
+`endif
+
+module f15_line_mem #(
+	parameter integer AWIDTH = 12,
+    parameter integer DWIDTH = 18
+)(
+	input  wire [AWIDTH-1:0] rd_addr,
+	output reg  [DWIDTH-1:0] rd_data,
+	input  wire rd_ena,
+
+	input  wire [AWIDTH-1:0] wr_addr,
+	input  wire [DWIDTH-1:0] wr_data,
+	input  wire wr_ena,
+
+	input  wire clk,
+	input  wire rst
+);
+
+	// Signals
+	reg [DWIDTH-1:0] ram [(1<<AWIDTH)-1:0];
+	reg [DWIDTH-1:0] rd_data_r;
+	reg rd_ena_r;
+
+`ifdef SIM
+	integer i;
+	initial
+		for (i=0; i<(1<<AWIDTH); i=i+1)
+			ram[i] = 0;
+`endif
+
+	always @(posedge clk)
+	begin
+		// Read
+		rd_data_r <= ram[rd_addr];
+
+		// Write
+		if (wr_ena)
+			ram[wr_addr] <= wr_data;
+
+		// Register the enable flag
+		rd_ena_r <= rd_ena;
+
+		// Final read register
+		if (rd_ena_r)
+			rd_data <= rd_data_r;
+		else
+			rd_data <= 0;
+	end
+
+endmodule // f15_line_mem
diff --git a/fpga/usrp3/lib/rfnoc/fosphor/f15_logpwr.v b/fpga/usrp3/lib/rfnoc/fosphor/f15_logpwr.v
new file mode 100644
index 000000000..cd10bc56a
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/fosphor/f15_logpwr.v
@@ -0,0 +1,504 @@
+/*
+ * f15_logpwr.v
+ *
+ * Log Power computation
+ * Take a complex 16 bits input and outputs a 16 bits estimate
+ * of 2048 * log2(i^2+q^2).
+ *
+ * Fully-pipelined, 12 levels
+ *
+ * Copyright (C) 2014  Ettus Corporation LLC
+ * Copyright 2018 Ettus Research, a National Instruments Company
+ *
+ * SPDX-License-Identifier: LGPL-3.0-or-later
+ *
+ * vim: ts=4 sw=4
+ */
+
+`ifdef SIM
+`default_nettype none
+`endif
+
+module f15_logpwr(
+	input  wire [15:0] in_real_0,
+	input  wire [15:0] in_imag_0,
+	output wire [15:0] out_12,
+	input  wire [31:0] rng,
+	input  wire [ 1:0] random_mode, /* [0] = lsb random ena, [1] = random add */
+	input  wire clk,
+	input  wire rst
+);
+
+	// Signals
+		// Randomness control
+	reg   [7:0] rng_lsb;
+	wire  [6:0] opmode;
+
+		// Power squared
+	wire [47:0] dsp_pchain_3;
+	wire [47:0] dsp_pout_4;
+
+	wire  [4:0] msb_check;
+	wire [31:0] pwr_4;
+	reg  [31:0] pwr_5,  pwr_6,  pwr_7,  pwr_8,  pwr_9;
+	reg   [4:0] log2_5, log2_6, log2_7, log2_8, log2_9;
+
+		// LUT
+	wire [15:0] lut_addr_9;
+	wire [31:0] lut_do_11;
+
+	wire        msb_9, msb_11;
+	wire  [4:0] lsbs_9, lsbs_11;
+	wire  [4:0] log2_11;
+
+		// Final value
+	reg  [20:0] final_12;
+
+
+	// -------------
+	// Power squared
+	// -------------
+		// Output is (in_real * in_real) + (in_imag * in_imag)
+		// with possibly some random lsb filled in for in_{real,imag} and some
+		// noise added to the result.
+
+	// Randomness control
+	always @(posedge clk)
+		if (random_mode[0])
+			rng_lsb <= rng[31:24];
+		else
+			rng_lsb <= 8'h00;
+
+	assign opmode = random_mode[1] ? 7'b0110101 : 7'b0000101;
+
+	// Square of in_real + noise
+	DSP48E1 #(
+		.A_INPUT("DIRECT"),
+		.B_INPUT("DIRECT"),
+		.USE_DPORT("FALSE"),
+		.USE_MULT("MULTIPLY"),
+		.AUTORESET_PATDET("NO_RESET"),
+		.MASK(48'h3fffffffffff),
+		.PATTERN(48'h000000000000),
+		.SEL_MASK("MASK"),
+		.SEL_PATTERN("PATTERN"),
+		.USE_PATTERN_DETECT("NO_PATDET"),
+		.ACASCREG(1),
+		.ADREG(0),
+		.ALUMODEREG(1),
+		.AREG(1),
+		.BCASCREG(1),
+		.BREG(1),
+		.CARRYINREG(1),
+		.CARRYINSELREG(1),
+		.CREG(1),
+		.DREG(0),
+		.INMODEREG(1),
+		.MREG(1),
+		.OPMODEREG(1),
+		.PREG(1),
+		.USE_SIMD("ONE48")
+	)
+	dsp_real_sq_I (
+		.PCOUT(dsp_pchain_3),
+		.ACIN(30'h0000),
+		.BCIN(18'h000),
+		.CARRYCASCIN(1'h0),
+		.MULTSIGNIN(1'h0),
+		.PCIN(48'h000000000000),
+		.ALUMODE(4'b0000),		// Z + X + Y + CIN
+		.CARRYINSEL(3'h0),
+		.CEINMODE(1'b1),
+		.CLK(clk),
+		.INMODE(5'b00000),		// B=B2, A=A2
+		.OPMODE(opmode),		// X=M1, Y=M2, Z=(random_mode[1] ? C : 0)
+		.RSTINMODE(rst),
+		.A({{12{in_real_0[15]}}, in_real_0, rng_lsb[7:6]}),
+		.B({                     in_real_0, rng_lsb[5:4]}),
+		.C({{41{1'b0}},rng[6:0]}),
+		.CARRYIN(1'b0),
+		.D(25'h0000),
+		.CEA1(1'b0),
+		.CEA2(1'b1),
+		.CEAD(1'b0),
+		.CEALUMODE(1'b1),
+		.CEB1(1'b0),
+		.CEB2(1'b1),
+		.CEC(1'b1),
+		.CECARRYIN(1'b1),
+		.CECTRL(1'b1),
+		.CED(1'b0),
+		.CEM(1'b1),
+		.CEP(1'b1),
+		.RSTA(rst),
+		.RSTALLCARRYIN(rst),
+		.RSTALUMODE(rst),
+		.RSTB(rst),
+		.RSTC(rst),
+		.RSTCTRL(rst),
+		.RSTD(rst),
+		.RSTM(rst),
+		.RSTP(rst)
+	);
+
+	// Square of in_imag and final sum
+	DSP48E1 #(
+		.A_INPUT("DIRECT"),
+		.B_INPUT("DIRECT"),
+		.USE_DPORT("FALSE"),
+		.USE_MULT("MULTIPLY"),
+		.AUTORESET_PATDET("NO_RESET"),
+		.MASK(48'h3fffffffffff),
+		.PATTERN(48'h000000000000),
+		.SEL_MASK("MASK"),
+		.SEL_PATTERN("PATTERN"),
+		.USE_PATTERN_DETECT("NO_PATDET"),
+		.ACASCREG(1),
+		.ADREG(0),
+		.ALUMODEREG(1),
+		.AREG(2),
+		.BCASCREG(1),
+		.BREG(2),
+		.CARRYINREG(1),
+		.CARRYINSELREG(1),
+		.CREG(1),
+		.DREG(0),
+		.INMODEREG(1),
+		.MREG(1),
+		.OPMODEREG(1),
+		.PREG(1),
+		.USE_SIMD("ONE48")
+	)
+	dsp_imag_sq_I (
+		.P(dsp_pout_4),
+		.ACIN(30'h0000),
+		.BCIN(18'h000),
+		.CARRYCASCIN(1'h0),
+		.MULTSIGNIN(1'h0),
+		.PCIN(dsp_pchain_3),
+		.ALUMODE(4'b0000),		// Z + X + Y + CIN
+		.CARRYINSEL(3'h0),
+		.CEINMODE(1'b1),
+		.CLK(clk),
+		.INMODE(5'b00000),		// B=B2, A=A2
+		.OPMODE(7'b0010101),	// X=M1, Y=M2, Z=PCIN
+		.RSTINMODE(rst),
+		.A({{12{in_imag_0[15]}}, in_imag_0, rng_lsb[3:2]}),
+		.B({                     in_imag_0, rng_lsb[1:0]}),
+		.C(48'h0000),
+		.CARRYIN(1'b0),
+		.D(25'h0000),
+		.CEA1(1'b1),
+		.CEA2(1'b1),
+		.CEAD(1'b0),
+		.CEALUMODE(1'b1),
+		.CEB1(1'b1),
+		.CEB2(1'b1),
+		.CEC(1'b1),
+		.CECARRYIN(1'b1),
+		.CECTRL(1'b1),
+		.CED(1'b0),
+		.CEM(1'b1),
+		.CEP(1'b1),
+		.RSTA(rst),
+		.RSTALLCARRYIN(rst),
+		.RSTALUMODE(rst),
+		.RSTB(rst),
+		.RSTC(rst),
+		.RSTCTRL(rst),
+		.RSTD(rst),
+		.RSTM(rst),
+		.RSTP(rst)
+	);
+
+	assign pwr_4 = dsp_pout_4[35:4];
+
+
+	// ----------------------------------
+	// Log2 computation and normalization
+	// ----------------------------------
+		// When shifting, instead of zero filling, we fill with RNG data
+		// Again, this helps reduce the visible quantization effects
+		// for very low power values.
+
+	// First stage
+	assign msb_check[4] = |(pwr_4[31:16]);
+
+	always @(posedge clk)
+	begin
+		if (msb_check[4])
+			pwr_5 <= pwr_4;
+		else
+			pwr_5 <= { pwr_4[15:0], rng[31:16] };
+
+		log2_5 <= { msb_check[4], 4'b0000 };
+	end
+
+	// Second stage
+	assign msb_check[3] = |(pwr_5[31:24]);
+
+	always @(posedge clk)
+	begin
+		if (msb_check[3])
+			pwr_6 <= pwr_5;
+		else
+			pwr_6 <= { pwr_5[23:0], rng[15:8] };
+
+		log2_6 <= { log2_5[4], msb_check[3], 3'b000 };
+	end
+
+	// Third stage
+	assign msb_check[2] = |(pwr_6[31:28]);
+
+	always @(posedge clk)
+	begin
+		if (msb_check[2])
+			pwr_7 <= pwr_6;
+		else
+			pwr_7 <= { pwr_6[27:0], rng[7:4] };
+
+		log2_7 <= { log2_6[4:3], msb_check[2], 2'b00 };
+	end
+
+	// Fourth stage
+	assign msb_check[1] = |(pwr_7[31:30]);
+
+	always @(posedge clk)
+	begin
+		if (msb_check[1])
+			pwr_8 <= pwr_7;
+		else
+			pwr_8 <= { pwr_7[29:0], rng[3:2] };
+
+		log2_8 <= { log2_7[4:2], msb_check[1], 1'b0 };
+	end
+
+	// Final stage
+	assign msb_check[0] =   pwr_8[31];
+
+	always @(posedge clk)
+	begin
+		if (msb_check[0])
+			pwr_9 <= pwr_8;
+		else
+			pwr_9 <= { pwr_8[30:0], rng[1] };
+
+		log2_9 <= { log2_8[4:1], msb_check[0] };
+		log2_9 <= { log2_8[4:1], msb_check[0] };
+	end
+
+
+	// ----------
+	// LUT lookup
+	// ----------
+
+	// Address mapping
+	assign lut_addr_9 = { 1'b0, pwr_9[30:20], 4'h0 };
+
+	// Actual LUT
+	RAMB36E1 #(
+		.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
+		.SIM_COLLISION_CHECK("NONE"),
+		.DOA_REG(1),
+		.DOB_REG(1),
+		.EN_ECC_READ("FALSE"),
+		.EN_ECC_WRITE("FALSE"),
+		.INIT_00(256'h02b202840256022801fa01cd019f01710143011500e700b8008a005c002e0000),
+		.INIT_01(256'h058c055f0531050404d604a9047b044e042003f203c503970369033b030e02e0),
+		.INIT_02(256'h08610834080707da07ad077f0752072506f806ca069d06700642061505e705ba),
+		.INIT_03(256'h0b310b040ad70aaa0a7d0a500a2409f709ca099d09700943091608e908bc088e),
+		.INIT_04(256'h0dfb0dce0da20d750d490d1c0cef0cc30c960c6a0c3d0c100be40bb70b8a0b5d),
+		.INIT_05(256'h10bf10931067103b100e0fe20fb60f8a0f5d0f310f050ed90eac0e800e530e27),
+		.INIT_06(256'h137e1353132712fb12cf12a31277124b121f11f311c7119b116f1143111710eb),
+		.INIT_07(256'h1639160d15e215b6158a155f1533150814dc14b014851459142d140213d613aa),
+		.INIT_08(256'h18ed18c21897186c1841181517ea17bf17941768173d171216e616bb168f1664),
+		.INIT_09(256'h1b9d1b731b481b1d1af21ac71a9c1a711a461a1b19f019c5199a196f19441919),
+		.INIT_0A(256'h1e481e1e1df31dc91d9e1d741d491d1e1cf41cc91c9e1c731c491c1e1bf31bc8),
+		.INIT_0B(256'h20ee20c4209a20702045201b1ff11fc61f9c1f721f471f1d1ef21ec81e9d1e73),
+		.INIT_0C(256'h23902366233c231222e822be2294226a2240221621ec21c12197216d21432119),
+		.INIT_0D(256'h262c260325d925af2586255c2532250824df24b5248b24612437240d23e423ba),
+		.INIT_0E(256'h28c4289b28712848281e27f527cc27a22779274f272626fc26d326a9267f2656),
+		.INIT_0F(256'h2b572b2e2b052adc2ab32a8a2a612a372a0e29e529bc299229692940291728ed),
+		.INIT_10(256'h2de62dbd2d942d6b2d432d1a2cf12cc82c9f2c762c4d2c242bfb2bd22ba92b80),
+		.INIT_11(256'h30703047301f2ff62fce2fa52f7d2f542f2b2f032eda2eb12e892e602e372e0f),
+		.INIT_12(256'h32f632cd32a5327d3255322c320431dc31b3318b3162313a311230e930c13098),
+		.INIT_13(256'h3577354f352734ff34d734af3487345f3437340f33e733be3396336e3346331e),
+		.INIT_14(256'h37f437cc37a4377d3755372d370536de36b6368e3666363e361635ef35c7359f),
+		.INIT_15(256'h3a6c3a453a1e39f639cf39a7398039583931390938e238ba3892386b3843381b),
+		.INIT_16(256'h3ce13cba3c933c6b3c443c1d3bf63bcf3ba73b803b593b313b0a3ae33abb3a94),
+		.INIT_17(256'h3f513f2a3f033edd3eb63e8f3e683e413e1a3df33dcc3da53d7d3d563d2f3d08),
+		.INIT_18(256'h41be41974170414a412340fc40d540af40884061403a40143fed3fc63f9f3f78),
+		.INIT_19(256'h442643ff43d943b3438c4366433f431942f242cc42a5427f42584231420b41e4),
+		.INIT_1A(256'h468a4664463e461745f145cb45a5457f45584532450c44e544bf44994472444c),
+		.INIT_1B(256'h48ea48c4489e48784853482d480747e147bb4795476f4748472246fc46d646b0),
+		.INIT_1C(256'h4b474b214afb4ad64ab04a8a4a644a3f4a1949f349cd49a84982495c49364910),
+		.INIT_1D(256'h4d9f4d7a4d544d2f4d094ce44cbe4c994c734c4e4c284c034bdd4bb84b924b6c),
+		.INIT_1E(256'h4ff44fcf4faa4f844f5f4f3a4f154eef4eca4ea54e7f4e5a4e354e0f4dea4dc5),
+		.INIT_1F(256'h5245522051fb51d651b1518c51675142511d50f850d350ae50895063503e5019),
+		.INIT_20(256'h5492546e5449542453ff53da53b65391536c5347532252fd52d952b4528f526a),
+		.INIT_21(256'h56dc56b75693566e564a5625560155dc55b85593556e554a5525550054dc54b7),
+		.INIT_22(256'h592258fe58d958b55891586c5848582457ff57db57b75792576e574957255700),
+		.INIT_23(256'h5b645b405b1c5af85ad45ab05a8c5a685a445a2059fb59d759b3598f596a5946),
+		.INIT_24(256'h5da35d805d5c5d385d145cf05ccc5ca85c845c605c3d5c195bf55bd15bad5b89),
+		.INIT_25(256'h5fdf5fbb5f985f745f505f2d5f095ee55ec25e9e5e7a5e565e335e0f5deb5dc7),
+		.INIT_26(256'h621761f461d061ad618961666142611f60fb60d860b46091606d604a60266003),
+		.INIT_27(256'h644c6429640563e263bf639c637863556332630f62eb62c862a56281625e623a),
+		.INIT_28(256'h667d665a6637661465f165ce65ab658865656542651f64fc64d864b56492646f),
+		.INIT_29(256'h68ab688868666843682067fd67da67b767946772674f672c670966e666c366a0),
+		.INIT_2A(256'h6ad66ab36a916a6e6a4b6a296a0669e469c1699e697b69596936691368f168ce),
+		.INIT_2B(256'h6cfd6cdb6cb96c966c746c516c2f6c0c6bea6bc76ba56b836b606b3d6b1b6af8),
+		.INIT_2C(256'h6f226eff6edd6ebb6e996e776e546e326e106dee6dcb6da96d876d646d426d20),
+		.INIT_2D(256'h7143712170ff70dd70bb709970777055703370116fee6fcc6faa6f886f666f44),
+		.INIT_2E(256'h7361733f731d72fb72da72b87296727472527230720e71ec71cb71a971877165),
+		.INIT_2F(256'h757c755a7539751774f574d474b27490746f744d742b740a73e873c673a47383),
+		.INIT_30(256'h779477727751772f770e76ec76cb76aa7688766776457624760275e075bf759d),
+		.INIT_31(256'h79a87987796679457924790278e178c0789e787d785c783a781977f877d677b5),
+		.INIT_32(256'h7bba7b997b787b577b367b157af47ad37ab27a917a707a4e7a2d7a0c79eb79ca),
+		.INIT_33(256'h7dc97da87d887d677d467d257d047ce37cc27ca17c807c5f7c3e7c1d7bfc7bdb),
+		.INIT_34(256'h7fd57fb57f947f737f537f327f117ef07ed07eaf7e8e7e6d7e4d7e2c7e0b7dea),
+		.INIT_35(256'h81de81be819d817d815c813c811b80fb80da80ba809980788058803780177ff6),
+		.INIT_36(256'h83e583c483a48384836383438323830282e282c182a1828182608240821f81ff),
+		.INIT_37(256'h85e885c885a88588856785478527850784e784c684a684868466844584258405),
+		.INIT_38(256'h87e987c987a98789876987498729870986e986c986a986898668864886288608),
+		.INIT_39(256'h89e789c789a78987896789488928890888e888c888a888888868884888298809),
+		.INIT_3A(256'h8be28bc28ba28b838b638b438b248b048ae48ac58aa58a858a668a468a268a06),
+		.INIT_3B(256'h8dda8dbb8d9b8d7c8d5c8d3d8d1d8cfe8cde8cbf8c9f8c808c608c408c218c01),
+		.INIT_3C(256'h8fd08fb18f918f728f538f338f148ef58ed58eb68e978e778e588e388e198dfa),
+		.INIT_3D(256'h91c391a49185916691469127910890e990ca90ab908b906c904d902e900e8fef),
+		.INIT_3E(256'h93b39394937693579338931992fa92db92bc929c927d925e923f9220920191e2),
+		.INIT_3F(256'h95a19583956495459526950794e894ca94ab948c946d944e942f941093f193d2),
+		.INIT_40(256'h978d976e974f9731971296f396d596b696979679965a963b961c95fe95df95c0),
+		.INIT_41(256'h997599579938991a98fb98dd98be98a09881986398449826980797e897ca97ab),
+		.INIT_42(256'h9b5c9b3d9b1f9b019ae29ac49aa69a879a699a4a9a2c9a0e99ef99d199b29994),
+		.INIT_43(256'h9d3f9d219d039ce59cc79ca99c8a9c6c9c4e9c309c119bf39bd59bb79b989b7a),
+		.INIT_44(256'h9f219f039ee59ec79ea99e8b9e6d9e4f9e309e129df49dd69db89d9a9d7c9d5e),
+		.INIT_45(256'ha100a0e2a0c4a0a6a088a06aa04ca02ea0119ff39fd59fb79f999f7b9f5d9f3f),
+		.INIT_46(256'ha2dca2bea2a1a283a265a247a22aa20ca1eea1d0a1b3a195a177a159a13ba11e),
+		.INIT_47(256'ha4b6a499a47ba45ea440a422a405a3e7a3c9a3aca38ea371a353a335a318a2fa),
+		.INIT_48(256'ha68ea671a653a636a618a5fba5dda5c0a5a2a585a567a54aa52ca50fa4f1a4d4),
+		.INIT_49(256'ha863a846a829a80ba7eea7d1a7b4a796a779a75ca73ea721a703a6e6a6c9a6ab),
+		.INIT_4A(256'haa36aa19a9fca9dfa9c2a9a5a987a96aa94da930a913a8f5a8d8a8bba89ea881),
+		.INIT_4B(256'hac07abeaabcdabb0ab93ab76ab59ab3cab1fab02aae5aac8aaabaa8eaa71aa53),
+		.INIT_4C(256'hadd6adb9ad9cad7fad62ad45ad28ad0cacefacd2acb5ac98ac7bac5eac41ac24),
+		.INIT_4D(256'hafa2af85af68af4caf2faf12aef5aed9aebcae9fae82ae66ae49ae2cae0fadf2),
+		.INIT_4E(256'hb16cb14fb133b116b0fab0ddb0c0b0a4b087b06ab04eb031b015aff8afdbafbf),
+		.INIT_4F(256'hb334b317b2fbb2deb2c2b2a5b289b26cb250b233b217b1fab1deb1c1b1a5b188),
+		.INIT_50(256'hb4f9b4ddb4c1b4a4b488b46cb44fb433b417b3fab3deb3c2b3a5b389b36cb350),
+		.INIT_51(256'hb6bdb6a1b684b668b64cb630b614b5f7b5dbb5bfb5a3b587b56ab54eb532b515),
+		.INIT_52(256'hb87eb862b846b82ab80eb7f2b7d6b7bab79eb781b765b749b72db711b6f5b6d9),
+		.INIT_53(256'hba3dba21ba05b9e9b9ceb9b2b996b97ab95eb942b926b90ab8eeb8d2b8b6b89a),
+		.INIT_54(256'hbbfabbdebbc3bba7bb8bbb6fbb54bb38bb1cbb00bae4bac8baadba91ba75ba59),
+		.INIT_55(256'hbdb5bd9abd7ebd62bd47bd2bbd0fbcf4bcd8bcbcbca1bc85bc69bc4dbc32bc16),
+		.INIT_56(256'hbf6ebf53bf37bf1cbf00bee5bec9beadbe92be76be5bbe3fbe24be08bdecbdd1),
+		.INIT_57(256'hc125c10ac0eec0d3c0b7c09cc081c065c04ac02ec013bff7bfdcbfc1bfa5bf8a),
+		.INIT_58(256'hc2dac2bfc2a3c288c26dc251c236c21bc200c1e4c1c9c1aec192c177c15cc140),
+		.INIT_59(256'hc48dc472c456c43bc420c405c3eac3cfc3b3c398c37dc362c347c32bc310c2f5),
+		.INIT_5A(256'hc63dc622c607c5ecc5d1c5b6c59bc580c565c54ac52fc514c4f9c4dec4c3c4a8),
+		.INIT_5B(256'hc7ecc7d1c7b7c79cc781c766c74bc730c715c6fac6dfc6c4c6a9c68ec673c658),
+		.INIT_5C(256'hc999c97ec964c949c92ec913c8f9c8dec8c3c8a8c88dc873c858c83dc822c807),
+		.INIT_5D(256'hcb44cb2acb0fcaf4cadacabfcaa4ca8aca6fca54ca3aca1fca04c9e9c9cfc9b4),
+		.INIT_5E(256'hccedccd3ccb8cc9ecc83cc69cc4ecc34cc19cbfecbe4cbc9cbafcb94cb79cb5f),
+		.INIT_5F(256'hce94ce7ace60ce45ce2bce10cdf6cddccdc1cda7cd8ccd72cd57cd3dcd22cd08),
+		.INIT_60(256'hd03ad01fd005cfebcfd1cfb6cf9ccf82cf67cf4dcf33cf18cefecee4cec9ceaf),
+		.INIT_61(256'hd1ddd1c3d1a9d18fd174d15ad140d126d10cd0f1d0d7d0bdd0a3d088d06ed054),
+		.INIT_62(256'hd37fd365d34bd330d316d2fcd2e2d2c8d2aed294d27ad260d246d22cd211d1f7),
+		.INIT_63(256'hd51ed504d4ead4d1d4b7d49dd483d469d44fd435d41bd401d3e7d3cdd3b3d399),
+		.INIT_64(256'hd6bcd6a2d689d66fd655d63bd621d607d5eed5d4d5bad5a0d586d56cd552d538),
+		.INIT_65(256'hd858d83fd825d80bd7f1d7d8d7bed7a4d78bd771d757d73dd723d70ad6f0d6d6),
+		.INIT_66(256'hd9f3d9d9d9bfd9a6d98cd973d959d93fd926d90cd8f2d8d9d8bfd8a5d88cd872),
+		.INIT_67(256'hdb8bdb72db58db3fdb25db0cdaf2dad9dabfdaa6da8cda72da59da3fda26da0c),
+		.INIT_68(256'hdd22dd09dcefdcd6dcbcdca3dc8adc70dc57dc3ddc24dc0adbf1dbd8dbbedba5),
+		.INIT_69(256'hdeb7de9ede84de6bde52de39de1fde06ddedddd3ddbadda1dd87dd6edd55dd3b),
+		.INIT_6A(256'he04ae031e018dfffdfe6dfccdfb3df9adf81df68df4edf35df1cdf03dee9ded0),
+		.INIT_6B(256'he1dce1c3e1aae191e178e15fe145e12ce113e0fae0e1e0c8e0afe096e07de063),
+		.INIT_6C(256'he36ce353e33ae321e308e2efe2d6e2bde2a4e28be272e259e240e227e20ee1f5),
+		.INIT_6D(256'he4fae4e1e4c8e4afe497e47ee465e44ce433e41ae401e3e8e3cfe3b7e39ee385),
+		.INIT_6E(256'he686e66ee655e63ce624e60be5f2e5d9e5c0e5a8e58fe576e55de544e52ce513),
+		.INIT_6F(256'he811e7f9e7e0e7c7e7afe796e77de765e74ce733e71be702e6e9e6d1e6b8e69f),
+		.INIT_70(256'he99be982e96ae951e938e920e907e8efe8d6e8bee8a5e88ce874e85be843e82a),
+		.INIT_71(256'heb22eb0aeaf1ead9eac0eaa8ea90ea77ea5fea46ea2eea15e9fde9e4e9cce9b3),
+		.INIT_72(256'heca8ec90ec78ec5fec47ec2eec16ebfeebe5ebcdebb5eb9ceb84eb6beb53eb3b),
+		.INIT_73(256'hee2dee14edfcede4edccedb3ed9bed83ed6bed52ed3aed22ed09ecf1ecd9ecc1),
+		.INIT_74(256'hefafef97ef7fef67ef4fef37ef1fef06eeeeeed6eebeeea6ee8dee75ee5dee45),
+		.INIT_75(256'hf131f119f101f0e8f0d0f0b8f0a0f088f070f058f040f028f010eff8efe0efc8),
+		.INIT_76(256'hf2b0f298f280f268f251f239f221f209f1f1f1d9f1c1f1a9f191f179f161f149),
+		.INIT_77(256'hf42ef417f3fff3e7f3cff3b7f39ff387f370f358f340f328f310f2f8f2e0f2c8),
+		.INIT_78(256'hf5abf593f57bf564f54cf534f51cf505f4edf4d5f4bdf4a5f48ef476f45ef446),
+		.INIT_79(256'hf726f70ef6f7f6dff6c7f6b0f698f680f669f651f639f622f60af5f2f5daf5c3),
+		.INIT_7A(256'hf8a0f888f870f859f841f82af812f7fbf7e3f7cbf7b4f79cf785f76df755f73e),
+		.INIT_7B(256'hfa18fa00f9e9f9d1f9baf9a2f98bf973f95cf944f92df915f8fef8e6f8cff8b7),
+		.INIT_7C(256'hfb8efb77fb5ffb48fb31fb19fb02faeafad3fabcfaa4fa8dfa75fa5efa46fa2f),
+		.INIT_7D(256'hfd03fcecfcd5fcbdfca6fc8ffc77fc60fc49fc32fc1afc03fbecfbd4fbbdfba5),
+		.INIT_7E(256'hfe77fe60fe48fe31fe1afe03fdecfdd4fdbdfda6fd8ffd77fd60fd49fd32fd1a),
+		.INIT_7F(256'hffe9ffd2ffbbffa4ff8dff75ff5eff47ff30ff19ff02feebfed3febcfea5fe8e),
+		.INIT_A(36'h000000000),
+		.INIT_B(36'h000000000),
+		.INIT_FILE("NONE"),
+		.RAM_MODE("TDP"),
+		.RAM_EXTENSION_A("NONE"),
+		.RAM_EXTENSION_B("NONE"),
+		.READ_WIDTH_A(18),
+		.READ_WIDTH_B(0),
+		.WRITE_WIDTH_A(0),
+		.WRITE_WIDTH_B(36),				// the RAMB36E1 model fails without this
+		.RSTREG_PRIORITY_A("RSTREG"),
+		.RSTREG_PRIORITY_B("RSTREG"),
+		.SRVAL_A(36'h000000000),
+		.SRVAL_B(36'h000000000),
+		.SIM_DEVICE("7SERIES"),
+		.WRITE_MODE_A("READ_FIRST"),
+		.WRITE_MODE_B("READ_FIRST")
+	)
+	log_lut_I (
+		.DOADO(lut_do_11),
+		.CASCADEINA(1'b0),
+		.CASCADEINB(1'b0),
+		.INJECTDBITERR(1'b0),
+		.INJECTSBITERR(1'b0),
+		.ADDRARDADDR(lut_addr_9),
+		.CLKARDCLK(clk),
+		.ENARDEN(1'b1),
+		.REGCEAREGCE(1'b1),
+		.RSTRAMARSTRAM(rst),
+		.RSTREGARSTREG(rst),
+		.WEA(4'h0),
+		.DIADI(32'h00000000),
+		.DIPADIP(4'h0),
+		.ADDRBWRADDR(16'h0000),
+		.CLKBWRCLK(1'b0),
+		.ENBWREN(1'b0),
+		.REGCEB(1'b0),
+		.RSTRAMB(1'b0),
+		.RSTREGB(1'b0),
+		.WEBWE(8'h0),
+		.DIBDI(32'h00000000),
+		.DIPBDIP(4'h0)
+	);
+
+	// LSBs mapping
+	assign msb_9  = pwr_9[31];
+	assign lsbs_9 = pwr_9[19:15];
+
+	// Delay lines to compensate for LUT delay
+	delay_bit #(2)    dl_msb  (msb_9,  msb_11,  clk);
+	delay_bus #(2, 5) dl_lsbs (lsbs_9, lsbs_11, clk);
+	delay_bus #(2, 5) dl_log2 (log2_9, log2_11, clk);
+
+
+	// -----------
+	// Final value
+	// -----------
+
+	// Final add & saturation
+	always @(posedge clk)
+	begin
+		if (!msb_11)
+			final_12 <= 16'h0000;
+		else
+			final_12 <= { log2_11, lut_do_11[15:0] } + lsbs_11;
+	end
+
+	// Mapping
+	assign out_12 = final_12[20:5];
+
+endmodule // f15_logpwr
diff --git a/fpga/usrp3/lib/rfnoc/fosphor/f15_maxhold.v b/fpga/usrp3/lib/rfnoc/fosphor/f15_maxhold.v
new file mode 100644
index 000000000..ecd92adfb
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/fosphor/f15_maxhold.v
@@ -0,0 +1,71 @@
+/*
+ * f15_maxhold.v
+ *
+ * Computes the max hold (with epsilon decay)
+ *
+ * Copyright (C) 2015  Ettus Corporation LLC
+ * Copyright 2018 Ettus Research, a National Instruments Company
+ *
+ * SPDX-License-Identifier: LGPL-3.0-or-later
+ *
+ * vim: ts=4 sw=4
+ */
+
+`ifdef SIM
+`default_nettype none
+`endif
+
+module f15_maxhold #(
+	parameter integer Y_WIDTH = 12,
+	parameter integer X_WIDTH = 16,
+	parameter integer FRAC_WIDTH = 8
+)(
+	input  wire [Y_WIDTH-1:0] yin_0,
+	input  wire [X_WIDTH-1:0] x_0,
+	input  wire [15:0] rng_0,
+	input  wire [15:0] epsilon_0,
+	input  wire clear_0,
+	output wire [Y_WIDTH-1:0] yout_4,
+	input  wire clk,
+	input  wire rst
+);
+
+	 localparam integer I_WIDTH = X_WIDTH + FRAC_WIDTH;
+
+	// Signals
+	reg [X_WIDTH-1:0] x_1;
+	reg [I_WIDTH  :0] y_1;
+	reg [Y_WIDTH  :0] d_1;
+	reg clear_1;
+
+	reg [Y_WIDTH-1:0] y_2;
+
+	// Stage 1
+	always @(posedge clk)
+	begin
+		x_1 <= x_0;
+		y_1 <= { 1'b0, yin_0, rng_0[I_WIDTH-Y_WIDTH-1:0] } - epsilon_0;
+		d_1 <= { 1'b0, yin_0 } - { 1'b0, x_0[X_WIDTH-1:X_WIDTH-Y_WIDTH] };
+		clear_1 <= clear_0;
+	end
+
+	// Stage 2
+	always @(posedge clk)
+	begin
+		if (clear_1)
+			y_2 <= 0;
+		else if (d_1[Y_WIDTH])
+			// x is larger, use this
+			y_2 <= x_1[X_WIDTH-1:X_WIDTH-Y_WIDTH];
+		else
+			// y is larger, take old y with small decay
+			if (y_1[I_WIDTH])
+				y_2 <= 0;
+			else
+				y_2 <= y_1[I_WIDTH-1:I_WIDTH-Y_WIDTH];
+	end
+
+	// Apply two more delay to match the avg block
+	delay_bus #(2, Y_WIDTH) dl_y (y_2, yout_4, clk);
+
+endmodule // f15_maxhold
diff --git a/fpga/usrp3/lib/rfnoc/fosphor/f15_packetizer.v b/fpga/usrp3/lib/rfnoc/fosphor/f15_packetizer.v
new file mode 100644
index 000000000..d8ff2ae34
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/fosphor/f15_packetizer.v
@@ -0,0 +1,136 @@
+/*
+ * f15_packetizer.v
+ *
+ * Copyright (C) 2015  Ettus Corporation LLC
+ * Copyright 2018 Ettus Research, a National Instruments Company
+ *
+ * SPDX-License-Identifier: LGPL-3.0-or-later
+ *
+ * vim: ts=4 sw=4
+ */
+
+`ifdef SIM
+`default_nettype none
+`endif
+
+module f15_packetizer #(
+	parameter integer BIN_WIDTH = 6,
+	parameter integer DECIM_WIDTH = 10
+)(
+	input  wire [BIN_WIDTH-1:0] in_bin_addr,
+	input  wire in_bin_last,
+	input  wire [7:0] in_histo,
+	input  wire [7:0] in_spectra_max,
+	input  wire [7:0] in_spectra_avg,
+	input  wire in_last,
+	input  wire in_valid,
+
+	output reg [31:0] out_data,
+	output reg out_last,
+	output reg out_eob,
+	output reg out_valid,
+
+	input  wire [DECIM_WIDTH-1:0] cfg_decim,
+	input  wire cfg_decim_changed,
+
+	input  wire clk,
+	input  wire rst
+);
+
+	// FSM
+	localparam
+		ST_WAIT = 0,
+		ST_SEND_HISTO = 1,
+		ST_SEND_MAX = 2,
+		ST_SEND_AVG = 3;
+
+	reg [1:0] state;
+
+	// Signals
+	reg [DECIM_WIDTH:0] decim_cnt;
+	reg [1:0] bcnt;
+
+	// 1-in-N decimation counter
+	always @(posedge clk)
+	begin
+		if (rst)
+			decim_cnt <= 0;
+		else if (cfg_decim_changed)
+			// Force Reload
+			decim_cnt <= { 1'b0, cfg_decim };
+		else if (in_valid & in_bin_last & in_last)
+			if (decim_cnt[DECIM_WIDTH])
+				// Reload
+				decim_cnt <= { 1'b0, cfg_decim };
+			else
+				// Just decrement
+				decim_cnt <= decim_cnt - 1;
+	end
+
+	// FSM
+	always @(posedge clk)
+	begin
+		if (rst)
+			state <= ST_WAIT;
+		else if (in_valid & in_last)
+			case (state)
+				ST_WAIT:
+					if (in_bin_last & decim_cnt[DECIM_WIDTH])
+						state <= ST_SEND_HISTO;
+
+				ST_SEND_HISTO:
+					if (in_bin_last)
+						state <= ST_SEND_MAX;
+
+				ST_SEND_MAX:
+					state <= ST_SEND_AVG;
+
+				ST_SEND_AVG:
+					state <= ST_WAIT;
+			endcase
+	end
+
+	// Byte counter
+	always @(posedge clk)
+	begin
+		if (rst)
+			bcnt <= 2'b00;
+		else if (in_valid)
+			if (in_last | (bcnt == 2'b11))
+				bcnt <= 2'b00;
+			else
+				bcnt <= bcnt + 1;
+	end
+
+	// Input mux & shift register
+	always @(posedge clk)
+	begin
+		if (in_valid)
+		begin
+			// Shift
+			out_data[31:8] <= out_data[23:0];
+
+			// New LSBs
+			case (state)
+				ST_SEND_HISTO: out_data[7:0] <= in_histo;
+				ST_SEND_MAX:   out_data[7:0] <= in_spectra_max;
+				ST_SEND_AVG:   out_data[7:0] <= in_spectra_avg;
+			endcase
+		end
+	end
+
+	// Output last, eob, valid
+	always @(posedge clk)
+	begin
+		if (rst) begin
+			out_last  <= 1'b0;
+			out_eob   <= 1'b0;
+			out_valid <= 1'b0;
+		end else begin
+			out_last  <= in_last;
+			out_eob   <= (state == ST_SEND_AVG);
+			out_valid <= in_valid & (in_last | bcnt == 2'b11) & (state != ST_WAIT);
+		end
+	end
+
+endmodule // f15_packetizer
diff --git a/fpga/usrp3/lib/rfnoc/fosphor/f15_rise_decay.v b/fpga/usrp3/lib/rfnoc/fosphor/f15_rise_decay.v
new file mode 100644
index 000000000..aeba14c7f
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/fosphor/f15_rise_decay.v
@@ -0,0 +1,160 @@
+/*
+ * f15_rise_decay.v
+ *
+ * Applies the rise or decay to a given value.
+ *
+ * Copyright (C) 2014  Ettus Corporation LLC
+ * Copyright 2018 Ettus Research, a National Instruments Company
+ *
+ * SPDX-License-Identifier: LGPL-3.0-or-later
+ *
+ * vim: ts=4 sw=4
+ */
+
+`ifdef SIM
+`default_nettype none
+`endif
+
+module f15_rise_decay #(
+	parameter integer WIDTH = 9
+)(
+	input  wire [WIDTH-1:0] in_0,	// input
+	output reg  [WIDTH-1:0] out_5,	// output
+	input  wire [15:0] k_0,			// time constant
+	input  wire ena_0,				// If ena=0, then output original value
+	input  wire mode_0,				// 0=rise, 1=decay
+	input  wire [15:0] rng,
+	input  wire clk,
+	input  wire rst
+);
+
+	// Signals
+	reg mode_1;
+	reg [4:0] inmode_1;
+
+	wire [WIDTH-1:0] in_2;
+	wire ena_2;
+	wire [6:0] opmode_2;
+	reg  [3:0] alumode_2;
+
+	wire [47:0] pout_4;
+	wire pmatch_4;
+
+
+	// Main DSP
+	// --------
+
+	// Mode control
+		// For rise  we have INMODE=00000 (A=A2,   B=B2), ALUMODE=0000 (C+M)
+		// For decay we have INMODE=01100 (A=D-A2, B=B2), ALUMODE=0011 (C-M)
+	always @(posedge clk)
+	begin
+		mode_1 <= mode_0;
+
+		if (mode_0)
+			inmode_1 <= 5'b00000;
+		else
+			inmode_1 <= 5'b01100;
+
+		if (mode_1)
+			alumode_2 <= 4'b0011;
+		else
+			alumode_2 <= 4'b0000;
+	end
+
+		// When not enabled, we use OPMODE to do pass-through
+	delay_bit #(2) dl_ena (ena_0, ena_2, clk);
+	assign opmode_2  = ena_2 ? 7'b0110101 : 7'b0110000;
+
+	// Delay for input to C
+	delay_bus #(2, WIDTH) dl_in (in_0, in_2, clk);
+
+	// Instance
+	DSP48E1 #(
+		.A_INPUT("DIRECT"),
+		.B_INPUT("DIRECT"),
+		.USE_DPORT("TRUE"),
+		.USE_MULT("MULTIPLY"),
+		.AUTORESET_PATDET("NO_RESET"),
+		.MASK({1'b1, {(31-WIDTH){1'b0}}, {(WIDTH+16){1'b1}}}),
+		.PATTERN(48'h000000000000),
+		.SEL_MASK("MASK"),
+		.SEL_PATTERN("PATTERN"),
+		.USE_PATTERN_DETECT("PATDET"),
+		.ACASCREG(1),
+		.ADREG(1),
+		.ALUMODEREG(1),
+		.AREG(1),
+		.BCASCREG(2),
+		.BREG(2),
+		.CARRYINREG(1),
+		.CARRYINSELREG(1),
+		.CREG(1),
+		.DREG(1),
+		.INMODEREG(1),
+		.MREG(1),
+		.OPMODEREG(1),
+		.PREG(1),
+		.USE_SIMD("ONE48")
+	)
+	dsp_exp_I (
+		.PATTERNDETECT(pmatch_4),
+		.P(pout_4),
+		.ACIN(30'h0),
+		.BCIN(18'h0),
+		.CARRYCASCIN(1'h0),
+		.MULTSIGNIN(1'h0),
+		.PCIN(48'h000000000000),
+		.ALUMODE(alumode_2),
+		.CARRYINSEL(3'h0),
+		.CEINMODE(1'b1),
+		.CLK(clk),
+		.INMODE(inmode_1),
+		.OPMODE(opmode_2),
+		.RSTINMODE(rst),
+		.A({{(30-WIDTH){1'b0}}, in_0}),
+		.B({ 2'h0, k_0}),
+		.C({{(32-WIDTH){1'b0}}, in_2, rng}),
+		.CARRYIN(1'b0),
+		.D({{(24-WIDTH){1'b0}}, 1'b1, {WIDTH{1'b0}}}),
+		.CEA1(1'b0),
+		.CEA2(1'b1),
+		.CEAD(1'b1),
+		.CEALUMODE(1'b1),
+		.CEB1(1'b1),
+		.CEB2(1'b1),
+		.CEC(1'b1),
+		.CECARRYIN(1'b1),
+		.CECTRL(1'b1),
+		.CED(1'b1),
+		.CEM(1'b1),
+		.CEP(1'b1),
+		.RSTA(rst),
+		.RSTALLCARRYIN(rst),
+		.RSTALUMODE(rst),
+		.RSTB(rst),
+		.RSTC(rst),
+		.RSTCTRL(rst),
+		.RSTD(rst),
+		.RSTM(rst),
+		.RSTP(rst)
+	);
+
+
+	// Saturation
+	// ----------
+
+	always @(posedge clk)
+	begin
+		if (rst == 1)
+			out_5 <= 0;
+		else
+			if (pout_4[47] == 1)
+				out_5 <= {WIDTH{1'b0}};
+			else if (pmatch_4 == 0)
+				out_5 <= {WIDTH{1'b1}};
+			else
+				out_5 <= pout_4[WIDTH+15:16];
+	end
+
+endmodule // f15_rise_decay
diff --git a/fpga/usrp3/lib/rfnoc/fosphor/f15_wf_agg.v b/fpga/usrp3/lib/rfnoc/fosphor/f15_wf_agg.v
new file mode 100644
index 000000000..7b12bc4d5
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/fosphor/f15_wf_agg.v
@@ -0,0 +1,189 @@
+/*
+ * f15_wf_agg.v
+ *
+ * Watefall Aggregation
+ *
+ * Copyright (C) 2016  Ettus Corporation LLC
+ *
+ * vim: ts=4 sw=4
+ */
+
+`ifdef SIM
+`default_nettype none
+`endif
+
+module f15_wf_agg #(
+	parameter integer Y_WIDTH = 12,
+	parameter integer X_WIDTH = 16,
+	parameter integer DECIM_WIDTH = 8
+)(
+	input wire [Y_WIDTH-1:0] yin_0,
+	input wire [X_WIDTH-1:0] x_0,
+	input wire valid_0,
+	input wire last_0,
+	input wire [15:0] rng_0,
+
+	output wire [Y_WIDTH-1:0] yout_3,
+	output wire [7:0] zout_3,
+	output wire zvalid_3,
+
+	input wire [1:0] cfg_div,
+	input wire cfg_mode,		// 0=MaxHold, 1=Average
+	input wire [DECIM_WIDTH-1:0] cfg_decim,
+	input wire cfg_decim_changed,
+
+	input wire clk,
+	input wire rst
+);
+
+	localparam integer R_WIDTH = X_WIDTH + 9;
+
+	// Signals
+		// Data pah
+	reg [R_WIDTH-1:0] xe_1;
+	reg [R_WIDTH-1:0] ye_1;
+
+	wire over_2;
+	reg [R_WIDTH-1:0] r_2;
+	reg [Y_WIDTH-1:0] x_2;
+	reg [Y_WIDTH-1:0] y_2;
+
+	reg [Y_WIDTH-1:0] y_3;
+
+		// Control
+	reg [DECIM_WIDTH:0] decim_cnt;
+	reg init_0;
+	wire init_2;
+	reg init_force_0;
+	reg flush_0;
+	reg zvalid_1;
+
+
+	// Datapath
+	// --------
+
+	// X predivision mux
+	always @(posedge clk)
+	begin
+		case (cfg_div)
+			2'b00:
+				xe_1 <= { 1'd0, x_0, 8'd0 };	// 1:1
+
+			2'b01:
+				xe_1 <= { 4'd0, x_0, 5'd0 };	// 1:8
+
+			2'b10:
+				xe_1 <= { 7'd0, x_0, 2'd0 };	// 1:64
+
+			2'b11:
+				xe_1 <= { 9'd0, x_0 };			// 1:256
+		endcase
+	end
+
+	// Y register
+	always @(posedge clk)
+	begin
+		if (cfg_mode)
+			// Average
+			ye_1 <= { 1'b0, yin_0, rng_0[R_WIDTH-Y_WIDTH-2:0] };
+		else
+			// Max Hold
+			ye_1 <= { 1'b0, yin_0, {(R_WIDTH-Y_WIDTH-1){1'b0}} };
+	end
+
+	// Adder / Substractor
+	always @(posedge clk)
+	begin
+		if (cfg_mode)
+			// Average
+			r_2 <= ye_1 + xe_1;
+		else
+			// Max-Hold
+			r_2 <= ye_1 - xe_1;
+	end
+
+	assign over_2 = r_2[R_WIDTH-1];
+
+	// Registers for the two branches.
+	always @(posedge clk)
+	begin
+		x_2 <= xe_1[R_WIDTH-2:R_WIDTH-Y_WIDTH-1];
+		y_2 <= ye_1[R_WIDTH-2:R_WIDTH-Y_WIDTH-1];
+	end
+
+	// Output mux
+	always @(posedge clk)
+	begin
+		// If first : take x_2
+		// If average :
+		//  - If overflow = 0 -> take r_2
+		//  - If overflow = 1 -> sature to all 1's
+		// If max-hold
+		//  - If overflow = 0 -> take y_2
+		//  - If overflow = 1 -> take x_2
+		if (init_2)
+			y_3 <= x_2;
+		else if (cfg_mode)
+			y_3 <= over_2 ? { (Y_WIDTH){1'b1} } : r_2[R_WIDTH-2:R_WIDTH-Y_WIDTH-1];
+		else
+			y_3 <= over_2 ? x_2 : y_2;
+	end
+
+	assign yout_3 = y_3;
+	assign zout_3 = y_3[Y_WIDTH-1:Y_WIDTH-8];
+
+
+	// Control
+	// -------
+
+	// 1-in-N decimation counter
+	always @(posedge clk)
+	begin
+		if (rst)
+			decim_cnt <= 0;
+		else if (cfg_decim_changed)
+			// Force Reload
+			decim_cnt <= { 1'b0, cfg_decim };
+		else if (valid_0 & last_0)
+			if (decim_cnt[DECIM_WIDTH])
+				// Reload
+				decim_cnt <= { 1'b0, cfg_decim };
+			else
+				// Just decrement
+				decim_cnt <= decim_cnt - 1;
+	end
+
+	// Decimation flush & init states
+	always @(posedge clk)
+	begin
+		if (rst) begin
+			// Initial state
+			flush_0 <= 1'b0;
+			init_0  <= 1'b1;
+			init_force_0 <= 1'b0;
+		end else begin
+			if (valid_0 & last_0) begin
+				// Flushing
+				flush_0 <= decim_cnt[DECIM_WIDTH];
+
+				// Init after flush or if forced
+				init_0 <= flush_0 | init_force_0;
+			end
+
+			// Init forcing after a decim change
+			if (cfg_decim_changed)
+				init_force_0 <= 1'b1;
+			else if (valid_0 & last_0)
+				init_force_0 <= 1'b0;
+		end
+	end
+
+	delay_bit #(2) dl_init(init_0, init_2, clk);
+
+	// Z-output valid
+	always @(posedge clk)
+		zvalid_1 <= valid_0 & flush_0;
+
+	delay_bit #(2) dl_zvalid(zvalid_1, zvalid_3, clk);
+
+endmodule // f15_wf_agg
diff --git a/fpga/usrp3/lib/rfnoc/fosphor/fifo_srl.v b/fpga/usrp3/lib/rfnoc/fosphor/fifo_srl.v
new file mode 100644
index 000000000..700da18d3
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/fosphor/fifo_srl.v
@@ -0,0 +1,169 @@
+/*
+ * fifo_srl.v
+ *
+ * Very small/light-weight FIFO using SRL.
+ * Only for synchronous design. Has a fixed depth of 15 or 31 entries and
+ * always work in the so-called first-word-fall-thru mode.
+ *
+ * Copyright (C) 2014  Ettus Corporation LLC
+ * Copyright 2018 Ettus Research, a National Instruments Company
+ *
+ * SPDX-License-Identifier: LGPL-3.0-or-later
+ *
+ * vim: ts=4 sw=4
+ */
+
+`ifdef SIM
+`default_nettype none
+`endif
+
+module fifo_srl #(
+	parameter integer WIDTH = 4,
+	parameter integer LOG2_DEPTH = 5,	// 4 or 5
+	parameter integer AFULL_LEVEL = -1	// -1 -> No AFULL
+
+)(
+	input  wire [WIDTH-1:0] di,
+	input  wire wren,
+	output wire full,
+	output wire afull,
+
+	output reg  [WIDTH-1:0] do,
+	input  wire rden,
+	output reg  empty,
+
+	input  wire clk,
+	input  wire rst
+);
+
+	genvar i;
+
+	// Signals
+	wire [WIDTH-1:0] srl_q;
+	reg  [LOG2_DEPTH-1:0] srl_addr;
+	wire srl_addr_ce;
+
+	wire srl_write;
+	wire srl_read;
+
+	wire srl_full;
+	wire srl_afull;
+	reg  srl_empty;
+	wire srl_aempty;
+
+	// Instanciate the SRLs
+	generate
+		if (LOG2_DEPTH == 6) begin
+			wire [WIDTH-1:0] srl0_q31, srl0_q, srl1_q;
+
+			for (i=0; i<WIDTH; i=i+1)
+			begin : srl_64
+				SRLC32E srl_I0 (
+					.Q(srl0_q[i]),
+					.Q31(srl0_q31[i]),
+					.A(srl_addr[4:0]),
+					.CE(srl_write),
+					.CLK(clk),
+					.D(di[i])
+				);
+
+				SRLC32E srl_I1 (
+					.Q(srl1_q[i]),
+					.A(srl_addr[4:0]),
+					.CE(srl_write),
+					.CLK(clk),
+					.D(srl0_q31[i])
+				);
+
+				MUXF7 mux_I (
+					.O(srl_q[i]),
+					.I0(srl0_q[i]),
+					.I1(srl1_q[i]),
+					.S(srl_addr[5])
+				);
+			end
+		end else if (LOG2_DEPTH == 5) begin
+			for (i=0; i<WIDTH; i=i+1)
+				SRLC32E srl_I (
+					.Q(srl_q[i]),
+					.A(srl_addr),
+					.CE(srl_write),
+					.CLK(clk),
+					.D(di[i])
+				);
+		end else if (LOG2_DEPTH == 4) begin
+			for (i=0; i<WIDTH; i=i+1)
+				SRL16E srl_I (
+					.Q(srl_q[i]),
+					.A0(srl_addr[0]),
+					.A1(srl_addr[1]),
+					.A2(srl_addr[2]),
+					.A3(srl_addr[3]),
+					.CE(srl_write),
+					.CLK(clk),
+					.D(di[i])
+				);
+		end
+	endgenerate
+
+	// Address counter
+	assign srl_addr_ce = srl_write ^ srl_read;
+
+	always @(posedge clk)
+	begin
+		if (rst)
+			srl_addr <= {LOG2_DEPTH{1'b1}};
+		else if (srl_addr_ce) begin
+			if (srl_write)
+				srl_addr <= srl_addr + 1;
+			else
+				srl_addr <= srl_addr - 1;
+		end
+	end
+
+	// SRL status
+	assign srl_full = srl_addr == {{(LOG2_DEPTH-1){1'b1}}, 1'b0};
+
+	generate
+		if (AFULL_LEVEL != -1) begin
+			assign srl_afull = (srl_addr >= AFULL_LEVEL) && ~&(srl_addr);
+		end else begin
+			assign srl_afull = 1'b0;
+		end
+	endgenerate
+
+	assign srl_aempty = &(~srl_addr);
+
+	always @(posedge clk)
+	begin
+		if (rst)
+			srl_empty <= 1'b1;
+		else if (srl_addr_ce)
+			srl_empty <= srl_aempty & srl_read;
+	end
+
+	// Output register (to capture whatever comes out from SRL)
+	always @(posedge clk)
+	begin
+		if (srl_read)
+			do <= srl_q;
+	end
+
+	// Control and flag generation
+		// Write/Full is easy
+	assign srl_write = wren;
+	assign full = srl_full;
+	assign afull = srl_afull;
+
+		// Read/Empty is tricky
+	always @(posedge clk)
+	begin
+		if (rst)
+			empty <= 1'b1;
+		else if (rden | srl_read)
+			empty <= srl_empty;
+	end
+
+	assign srl_read = (rden | empty) & ~srl_empty;
+
+endmodule // fifo_srl
diff --git a/fpga/usrp3/lib/rfnoc/fosphor/rng.v b/fpga/usrp3/lib/rfnoc/fosphor/rng.v
new file mode 100644
index 000000000..6d6715fd0
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/fosphor/rng.v
@@ -0,0 +1,87 @@
+/*
+ * rng.v
+ *
+ * Very simple 32-bits PRNG using a few underlying LFSR.
+ *
+ * Copyright (C) 2014  Ettus Corporation LLC
+ * Copyright 2018 Ettus Research, a National Instruments Company
+ *
+ * SPDX-License-Identifier: LGPL-3.0-or-later
+ *
+ * vim: ts=4 sw=4
+ */
+
+`ifdef SIM
+`default_nettype none
+`endif
+
+// ---------------------------------------------------------------------------
+// Main RNG
+// ---------------------------------------------------------------------------
+
+module rng(
+	output reg  [31:0] out,
+	input  wire clk,
+	input  wire rst
+);
+
+	// Signals
+	wire [4:0] out5, out5rev;
+	wire [7:0] out8;
+	wire [11:0] out12;
+	wire [15:0] out16;
+
+	// Instanciate 4 LFSRs of different lengths
+	lfsr #(.WIDTH( 5), .POLY( 5'b01001)) lfsr5  (.out(out5),  .clk(clk), .rst(rst));
+	lfsr #(.WIDTH( 8), .POLY( 8'h71   )) lfsr8  (.out(out8),  .clk(clk), .rst(rst));
+	lfsr #(.WIDTH(12), .POLY(12'hc11  )) lfsr12 (.out(out12), .clk(clk), .rst(rst));
+	lfsr #(.WIDTH(16), .POLY(16'h6701 )) lfsr16 (.out(out16), .clk(clk), .rst(rst));
+
+	// Reverse the 5 bit LFSR output
+	genvar i;
+	generate
+		for (i=0; i<5; i=i+1)
+			assign out5rev[i] = out5[4-i];
+	endgenerate
+
+	// Combine the outputs 'somehow'
+	always @(posedge clk)
+		out <= {
+			out16[15:11] ^ out5rev,		// 5 bits
+			out16[10:2],				// 9 bits
+			out16[1:0] ^ out12[11:10],	// 2 bits
+			out12[9:2],					// 8 bits
+			out12[1:0] ^ out8[7:6],		// 2 bits
+			out8[5:0]					// 6 bits
+		};
+
+endmodule // rng
+
+
+// ---------------------------------------------------------------------------
+// LFSR sub module
+// ---------------------------------------------------------------------------
+
+module lfsr #(
+	parameter integer WIDTH = 8,
+	parameter POLY = 8'h71
+)(
+	output reg  [WIDTH-1:0] out,
+	input  wire clk,
+	input  wire rst
+);
+
+	// Signals
+	wire fb;
+
+	// Linear Feedback
+	assign fb = ^(out & POLY);
+
+	// Register
+	always @(posedge clk)
+		if (rst)
+			out <= { {(WIDTH-1){1'b0}}, 1'b1 };
+		else
+			out <= { fb, out[WIDTH-1:1] };
+
+endmodule // lfsr
diff --git a/fpga/usrp3/lib/rfnoc/join_complex.v b/fpga/usrp3/lib/rfnoc/join_complex.v
new file mode 100644
index 000000000..ac4ff48d1
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/join_complex.v
@@ -0,0 +1,27 @@
+
+// Copyright 2014, Ettus Research
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+
+// Module to join a complex stream to I and Q outputs.  NOTE -- ONLY works when you can guarantee upstream paths match!
+
+module join_complex
+  #(parameter WIDTH=16)
+   (input [WIDTH-1:0] ii_tdata, input ii_tlast, input ii_tvalid, output ii_tready,
+    input [WIDTH-1:0] iq_tdata, input iq_tlast, input iq_tvalid, output iq_tready,
+    output [WIDTH*2-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready,
+    output error);
+
+   assign o_tdata = {ii_tdata,iq_tdata};
+
+   assign o_tlast = ii_tlast;
+
+   assign o_tvalid = ii_tvalid;
+
+   assign ii_tready = o_tready;
+   assign iq_tready = o_tready;
+
+   assign  error = (ii_tlast ^ iq_tlast) | (ii_tvalid ^ iq_tvalid);
+      
+endmodule // join_complex
diff --git a/fpga/usrp3/lib/rfnoc/keep_one_in_n.v b/fpga/usrp3/lib/rfnoc/keep_one_in_n.v
new file mode 100644
index 000000000..d83dcd7cb
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/keep_one_in_n.v
@@ -0,0 +1,73 @@
+//
+// Copyright 2016 Ettus Research
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Note: n == 0 lets everything through.
+// Warning: Sample / packet counts reset when n is changed, caution if changing during operation!
+
+module keep_one_in_n #(
+  parameter KEEP_FIRST=0,  // 0: Drop n-1 words then keep last word, 1: Keep 1st word then drop n-1
+  parameter WIDTH=16,
+  parameter MAX_N=65535
+)(
+  input clk, input reset,
+  input vector_mode,
+  input [$clog2(MAX_N+1)-1:0] n,
+  input [WIDTH-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
+  output [WIDTH-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready
+);
+
+  reg [$clog2(MAX_N+1)-1:0] sample_cnt, pkt_cnt, n_reg;
+  reg n_changed;
+
+  always @(posedge clk) begin
+    if (reset) begin
+       n_reg      <= 1;
+       n_changed  <= 1'b0;
+    end else begin
+      n_reg       <= n;
+      if (n_reg != n) begin
+        n_changed <= 1'b1;
+      end else begin
+        n_changed <= 1'b0;
+      end
+    end
+  end
+
+  wire on_last_sample  = ( (sample_cnt >= n_reg) | (n_reg == 0) );
+  wire on_first_sample = ( (sample_cnt == 1)     | (n_reg == 0) );
+  wire on_last_pkt     = ( (pkt_cnt >= n_reg)    | (n_reg == 0) );
+  wire on_first_pkt    = ( (pkt_cnt == 1)        | (n_reg == 0) );
+
+  always @(posedge clk) begin
+    if (reset | n_changed) begin
+       sample_cnt <= 1;
+       pkt_cnt    <= 1;
+    end else begin
+      if (i_tvalid & i_tready) begin
+        if (on_last_sample) begin
+          sample_cnt <= 1;
+        end else begin
+          sample_cnt <= sample_cnt + 1'd1;
+        end
+      end
+      if (i_tvalid & i_tready & i_tlast) begin
+        if (on_last_pkt) begin
+          pkt_cnt <= 1;
+        end else begin
+          pkt_cnt <= pkt_cnt + 1'd1;
+        end
+      end
+    end
+  end
+
+  assign i_tready = o_tready | (vector_mode ? (KEEP_FIRST ? ~on_first_pkt    : ~on_last_pkt) :
+                                              (KEEP_FIRST ? ~on_first_sample : ~on_last_sample));
+  assign o_tvalid = i_tvalid & (vector_mode ? (KEEP_FIRST ?  on_first_pkt    :  on_last_pkt) :
+                                              (KEEP_FIRST ?  on_first_sample :  on_last_sample));
+  assign o_tdata  = i_tdata;
+  assign o_tlast  = i_tlast  & (vector_mode ? 1'b1 : on_last_pkt);
+
+endmodule // keep_one_in_n_vec
diff --git a/fpga/usrp3/lib/rfnoc/moving_sum.v b/fpga/usrp3/lib/rfnoc/moving_sum.v
new file mode 100644
index 000000000..e3d8e2889
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/moving_sum.v
@@ -0,0 +1,80 @@
+//
+// Copyright 2016 Ettus Research
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module moving_sum #(
+  parameter MAX_LEN = 1023,
+  parameter WIDTH   = 16
+)(
+  input clk, input reset, input clear,
+  input [$clog2(MAX_LEN+1)-1:0] len,
+  input [WIDTH-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
+  output [WIDTH+$clog2(MAX_LEN+1)-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready
+);
+
+  wire signed [WIDTH+$clog2(MAX_LEN+1)-1:0] sum;
+  reg signed [WIDTH+$clog2(MAX_LEN+1)-1:0] sum_reg;
+  reg [$clog2(MAX_LEN+1)-1:0] full_count, len_reg;
+  reg len_changed;
+
+  wire full  = (full_count == len_reg);
+  wire do_op = (i_tvalid & i_tready);
+
+  wire i_tready_int, i_tvalid_int;
+  wire fifo_tvalid, fifo_tready;
+  wire [WIDTH-1:0] fifo_tdata;
+
+  axi_fifo #(.WIDTH(WIDTH), .SIZE($clog2(MAX_LEN))) axi_fifo (
+    .clk(clk), .reset(reset | len_changed), .clear(clear),
+    .i_tdata(i_tdata), .i_tvalid(do_op), .i_tready(),
+    .o_tdata(fifo_tdata), .o_tvalid(fifo_tvalid), .o_tready(fifo_tready),
+    .occupied(), .space());
+
+  assign fifo_tready = i_tvalid & i_tready_int & full;
+
+  always @(posedge clk) begin
+    if (reset | clear | len_changed) begin
+       full_count <= 'd0;
+    end else begin
+      if (do_op & ~full) begin
+        full_count <= full_count + 1;
+      end
+    end
+  end
+
+  assign sum = sum_reg + $signed(i_tdata) - (full ? $signed(fifo_tdata) : 0);
+
+  always @(posedge clk) begin
+    if (reset | clear) begin
+      sum_reg     <= 'd0;
+      len_reg     <= 1;
+      len_changed <= 1'b0;
+    end else begin
+      len_reg <= (len == 0) ? 1 : len;
+      if (len_reg != len) begin
+        len_changed <= 1'b1;
+      end else begin
+        len_changed <= 1'b0;
+      end
+      if (len_changed) begin
+        sum_reg <= 'd0;
+      end else if (do_op) begin
+        sum_reg <= sum;
+      end
+    end
+  end
+
+  // Output register
+  axi_fifo_flop #(.WIDTH(WIDTH+$clog2(MAX_LEN+1)+1)) axi_fifo_flop (
+    .clk(clk), .reset(reset), .clear(clear),
+    .i_tdata({i_tlast,sum}), .i_tvalid(i_tvalid_int), .i_tready(i_tready_int),
+    .o_tdata({o_tlast,o_tdata}), .o_tvalid(o_tvalid), .o_tready(o_tready),
+    .occupied(), .space());
+
+  assign i_tready     = (~full | (fifo_tvalid & full)) & i_tready_int & ~len_changed;
+  assign i_tvalid_int = (~full | (fifo_tvalid & full)) & i_tvalid     & ~len_changed;
+
+endmodule // moving_sum
diff --git a/fpga/usrp3/lib/rfnoc/mult.v b/fpga/usrp3/lib/rfnoc/mult.v
new file mode 100644
index 000000000..c32025236
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/mult.v
@@ -0,0 +1,115 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Write xilinx DSP48E1 primitive for multiplication with AXI interfaces
+// Latency must be 2 to 4
+
+// FIXME handle tlast
+// FIXME handle CASCADE_OUT
+
+module mult
+  #(parameter WIDTH_A=25,
+    parameter WIDTH_B=18,
+    parameter WIDTH_P=48,     // must be 48 if you are cascading
+    parameter DROP_TOP_P=0,   // must be 0 if you are cascading
+    parameter LATENCY=3,
+    parameter CASCADE_OUT=0)
+   (input clk, input reset,
+    input [WIDTH_A-1:0] a_tdata, input a_tlast, input a_tvalid, output a_tready,
+    input [WIDTH_B-1:0] b_tdata, input b_tlast, input b_tvalid, output b_tready,
+    output [WIDTH_P-1:0] p_tdata, output p_tlast, output p_tvalid, input p_tready);
+   
+   wire [24:0] 		   A_IN = { a_tdata, {(25-(WIDTH_A)){1'b0}}};
+   wire [17:0] 		   B_IN = { b_tdata, {(18-(WIDTH_B)){1'b0}}};
+   wire [47:0] 		   P1_OUT, P1_OUT_CASC;
+   wire [47:0] 		   p_tdata_int = CASCADE_OUT ? P1_OUT_CASC : P1_OUT;
+   assign p_tdata = p_tdata_int[47-DROP_TOP_P:48-WIDTH_P-DROP_TOP_P];
+      
+   localparam MREG_IN = 1;    // Always have this reg
+   localparam PREG_IN = (LATENCY >= 3) ? 1 : 0;
+   localparam A2REG_IN = (LATENCY >= 2) ? 1 : 0;
+   localparam A1REG_IN = (LATENCY == 4) ? 1 : 0;
+   localparam AREG_IN = A1REG_IN + A2REG_IN;
+
+   wire [A1REG_IN:0] 		   en0, en1;
+   wire [PREG_IN:0] 		   en_post;
+   reg 				   CEP, CEM, CEA2, CEA1, CEB2, CEB1;
+   wire 			   CE = 1'b0;   // FIXME
+   
+   always @*
+     case(LATENCY)
+       2 : {CEP, CEM, CEA2, CEA1, CEB2, CEB1} <= { 1'b0      , en_post[0], en0[0], 1'b0  , en1[0], 1'b0   };
+       3 : {CEP, CEM, CEA2, CEA1, CEB2, CEB1} <= { en_post[1], en_post[0], en0[0], 1'b0  , en1[0], 1'b0   };
+       4 : {CEP, CEM, CEA2, CEA1, CEB2, CEB1} <= { en_post[1], en_post[0], en0[1], en0[0], en1[1], en1[0] };
+     endcase
+	 
+   axi_pipe_join #(.PRE_JOIN_STAGES0(AREG_IN), .PRE_JOIN_STAGES1(AREG_IN),
+		   .POST_JOIN_STAGES(MREG_IN+PREG_IN)) axi_pipe_join
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i0_tlast(a_tlast), .i0_tvalid(a_tvalid), .i0_tready(a_tready),
+      .i1_tlast(b_tlast), .i1_tvalid(b_tvalid), .i1_tready(b_tready),
+      .o_tlast(p_tlast), .o_tvalid(p_tvalid), .o_tready(p_tready),
+      .enables0(en0), .enables1(en1), .enables_post(en_post));
+   
+   DSP48E1 #(.ACASCREG(AREG_IN),       
+             .AREG(AREG_IN),           
+             .ADREG(0),
+             .DREG(0),
+             .BCASCREG(AREG_IN),       
+             .BREG(AREG_IN),           
+             .MREG(MREG_IN),           
+             .PREG(PREG_IN)) 
+   DSP48_inst (.ACOUT(),   
+               .BCOUT(),  
+               .CARRYCASCOUT(), 
+               .CARRYOUT(), 
+               .MULTSIGNOUT(), 
+               .OVERFLOW(), 
+               .P(P1_OUT),          
+               .PATTERNBDETECT(), 
+               .PATTERNDETECT(), 
+               .PCOUT(P1_OUT_CASC),  
+               .UNDERFLOW(), 
+               .A({5'b0,A_IN}),          
+               .ACIN(30'b0),    
+               .ALUMODE(4'b0000), 
+               .B(B_IN),          
+               .BCIN(18'b0),    
+               .C(48'b0),          
+               .CARRYCASCIN(1'b0), 
+               .CARRYIN(1'b0), 
+               .CARRYINSEL(3'b0), 
+               .CEA1(CEA1),      
+               .CEA2(CEA2),      
+               .CEAD(1'b0),
+               .CEALUMODE(1'b1), 
+               .CEB1(CEB1),      
+               .CEB2(CEB2),      
+               .CEC(CE),       //
+               .CECARRYIN(CE), 
+               .CECTRL(1'b1), 
+               .CED(CE),
+               .CEINMODE(CE),
+               .CEM(CEM),       
+               .CEP(CEP),       
+               .CLK(clk),       
+               .D(25'b0),
+               .INMODE(5'b0),
+               .MULTSIGNIN(1'b0), 
+               .OPMODE(7'b0000101), 
+               .PCIN(48'b0),      
+               .RSTA(reset),     
+               .RSTALLCARRYIN(reset), 
+               .RSTALUMODE(reset), 
+               .RSTB(reset),     
+               .RSTC(reset),   
+               .RSTD(reset),  
+               .RSTCTRL(reset),
+               .RSTINMODE(reset), 
+               .RSTM(reset), 
+               .RSTP(reset));
+   
+endmodule // mult
diff --git a/fpga/usrp3/lib/rfnoc/mult_add.v b/fpga/usrp3/lib/rfnoc/mult_add.v
new file mode 100644
index 000000000..e853d7d74
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/mult_add.v
@@ -0,0 +1,124 @@
+
+// Copyright 2014 Ettus Research
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// Write xilinx DSP48E1 primitive for mult-add with AXI interfaces
+
+module mult_add
+  #(parameter WIDTH_A=25,
+    parameter WIDTH_B=18,
+    parameter WIDTH_P=48,       // Must be 48 if you are cascading
+    parameter DROP_TOP_P=0,     // Must be 0 if you are cascading
+    parameter LATENCY=3,
+    parameter CASCADE_IN=0,
+    parameter CASCADE_OUT=0)
+   (input clk, input reset,
+    input [WIDTH_A-1:0] a_tdata, input a_tlast, input a_tvalid, output a_tready,
+    input [WIDTH_B-1:0] b_tdata, input b_tlast, input b_tvalid, output b_tready,
+    input [WIDTH_P-1:0] c_tdata, input c_tlast, input c_tvalid, output c_tready,
+    output [WIDTH_P-1:0] p_tdata, output p_tlast, output p_tvalid, input p_tready);
+   
+   wire [24:0] 		 A_IN = { a_tdata, {(25-(WIDTH_A)){1'b0}}};
+   wire [17:0] 		 B_IN = { b_tdata, {(18-(WIDTH_B)){1'b0}}};
+   wire [47:0] 		 P1_OUT, P1_OUT_CASC;
+   wire [47:0] 		 p_tdata_int = CASCADE_OUT ? P1_OUT_CASC : P1_OUT;
+   assign p_tdata = p_tdata_int[47-DROP_TOP_P:48-WIDTH_P-DROP_TOP_P];
+
+   wire [47:0] 		 c_tdata_int = { {DROP_TOP_P{c_tdata[WIDTH_P-1]}}, c_tdata, {(48-WIDTH_P-DROP_TOP_P){1'b0}} };
+   
+   wire [47:0] 		 CIN  = CASCADE_IN ? 48'h0000_0000_0000 : c_tdata_int;
+   wire [47:0] 		 PCIN = CASCADE_IN ? c_tdata_int : 48'h0000_0000_0000;
+
+   localparam MREG_IN = 1;    // Always have this reg
+   localparam PREG_IN = (LATENCY >= 3) ? 1 : 0;
+   localparam A2REG_IN = (LATENCY >= 2) ? 1 : 0;
+   localparam A1REG_IN = (LATENCY == 4) ? 1 : 0;
+   localparam AREG_IN = A1REG_IN + A2REG_IN;
+   // See OPMODE Control Bits Settings, Table 2-7,2-8,2-9
+   localparam ZMUX_PCIN = 3'b001;
+   localparam ZMUX_C = 3'b011;
+   localparam XMUX_M = 2'b01;
+   localparam YMUX_M = 2'b01;
+   
+   wire [A1REG_IN:0] 	 enables_a, enables_b;
+   wire 		 enable_c, enable_m;
+   wire [PREG_IN:0] 	 en_post;
+   wire 		 CE = 1'b1;   // FIXME
+   wire 		 LOAD = 1'b1;
+   wire 		 CEC, CEM, CEP;
+   reg 			 CEA2, CEA1, CEB2, CEB1;
+   
+   always @*
+     case(LATENCY)
+       3 : {CEA2, CEA1, CEB2, CEB1} <= { enables_a[0], 1'b0  , enables_b[0], 1'b0   };
+       4 : {CEA2, CEA1, CEB2, CEB1} <= { enables_a[1], enables_a[0], enables_b[1], enables_b[0] };
+     endcase
+   
+   axi_pipe_mac #(.LATENCY(LATENCY), .CASCADE_IN(CASCADE_IN)) axi_pipe_mac
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .a_tlast(a_tlast), .a_tvalid(a_tvalid), .a_tready(a_tready),
+      .b_tlast(b_tlast), .b_tvalid(b_tvalid), .b_tready(b_tready),
+      .c_tlast(c_tlast), .c_tvalid(c_tvalid), .c_tready(c_tready),
+      .p_tlast(p_tlast), .p_tvalid(p_tvalid), .p_tready(p_tready),
+      .enables_a(enables_a), .enables_b(enables_b), .enable_c(CEC), .enable_m(CEM), .enable_p(CEP));
+   
+   DSP48E1 #(.ACASCREG(AREG_IN),       
+             .AREG(AREG_IN),           
+             .ADREG(0),
+             .DREG(0),
+             .BCASCREG(AREG_IN),       
+             .BREG(AREG_IN),           
+             .MREG(MREG_IN),           
+             .PREG(PREG_IN)) 
+   DSP48_inst (.ACOUT(),          // Outputs start here
+               .BCOUT(),  
+               .CARRYCASCOUT(), 
+               .CARRYOUT(), 
+               .MULTSIGNOUT(), 
+               .OVERFLOW(), 
+               .P(P1_OUT),          
+               .PATTERNBDETECT(), 
+               .PATTERNDETECT(), 
+               .PCOUT(P1_OUT_CASC),  
+               .UNDERFLOW(), 
+               .A({5'b0,A_IN}),   // Inputs start here
+               .ACIN(30'b0),    
+               .ALUMODE(4'b0000),   //////////////////////
+               .B(B_IN),       
+               .BCIN(18'b0),    
+               .C(CIN),          ///////////////////////
+               .CARRYCASCIN(1'b0), 
+               .CARRYIN(1'b0), 
+               .CARRYINSEL(3'b0), 
+               .CEA1(CEA1),      
+               .CEA2(CEA2),      
+               .CEAD(1'b0),
+               .CEALUMODE(1'b1),   ////////////////////////
+               .CEB1(CEB1),      
+               .CEB2(CEB2),      
+               .CEC(CEC),       ///////////////////////////
+               .CECARRYIN(CE), 
+               .CECTRL(CE), 
+               .CED(CE),
+               .CEINMODE(CE),
+               .CEM(CEM),       
+               .CEP(CEP),       
+               .CLK(clk),       
+               .D(25'b0),
+               .INMODE(5'b0),    ///////////////////////
+               .MULTSIGNIN(1'b0), 
+               .OPMODE({(CASCADE_IN ? ZMUX_PCIN : ZMUX_C), YMUX_M, XMUX_M}), // ////////////////////
+               .PCIN(PCIN),      //////////////////////
+               .RSTA(reset),     
+               .RSTALLCARRYIN(reset), 
+               .RSTALUMODE(reset), 
+               .RSTB(reset),     
+               .RSTC(reset),   
+               .RSTD(reset),  
+               .RSTCTRL(reset),
+               .RSTINMODE(reset), 
+               .RSTM(reset), 
+               .RSTP(reset));
+   
+endmodule // mult
diff --git a/fpga/usrp3/lib/rfnoc/mult_add_rc.v b/fpga/usrp3/lib/rfnoc/mult_add_rc.v
new file mode 100644
index 000000000..91d548ee0
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/mult_add_rc.v
@@ -0,0 +1,64 @@
+
+// Copyright 2014 Ettus Research
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// Complex times real.  Complex number is on port B (18I, 18Q), real is on A (25 bits)
+
+module mult_add_rc
+  #(parameter WIDTH_REAL=25,
+    parameter WIDTH_CPLX=18,
+    parameter WIDTH_P=48,
+    parameter DROP_TOP_P=0,
+    parameter LATENCY=3,
+    parameter CASCADE_IN=0,
+    parameter CASCADE_OUT=0)
+   (input clk, input reset,
+    input [WIDTH_REAL-1:0] real_tdata, input real_tlast, input real_tvalid, output real_tready,
+    input [2*WIDTH_CPLX-1:0] cplx_tdata, input cplx_tlast, input cplx_tvalid, output cplx_tready,
+    input [2*WIDTH_P-1:0] c_tdata, input c_tlast, input c_tvalid, output c_tready,
+    output [2*WIDTH_P-1:0] p_tdata, output p_tlast, output p_tvalid, input p_tready);
+
+   // NOTE -- we cheat here and share ready/valid.  This works because we can guarantee both
+   //           paths will match
+
+   generate
+      if(WIDTH_REAL > WIDTH_CPLX)
+	begin
+	   mult_add #(.WIDTH_A(WIDTH_REAL), .WIDTH_B(WIDTH_CPLX), .WIDTH_P(WIDTH_P), .DROP_TOP_P(DROP_TOP_P),
+		      .LATENCY(LATENCY), .CASCADE_IN(CASCADE_IN), .CASCADE_OUT(CASCADE_OUT)) mult_add_i
+	     (.clk(clk), .reset(reset),
+	      .a_tdata(real_tdata), .a_tlast(real_tlast), .a_tvalid(real_tvalid), .a_tready(real_tready),
+	      .b_tdata(cplx_tdata[2*WIDTH_CPLX-1:WIDTH_CPLX]), .b_tlast(cplx_tlast), .b_tvalid(cplx_tvalid), .b_tready(cplx_tready),
+	      .c_tdata(c_tdata[2*WIDTH_P-1:WIDTH_P]), .c_tlast(c_tlast), .c_tvalid(c_tvalid), .c_tready(c_tready),
+	      .p_tdata(p_tdata[2*WIDTH_P-1:WIDTH_P]), .p_tlast(p_tlast), .p_tvalid(p_tvalid), .p_tready(p_tready));
+           
+	   mult_add #(.WIDTH_A(WIDTH_REAL), .WIDTH_B(WIDTH_CPLX), .WIDTH_P(WIDTH_P), .DROP_TOP_P(DROP_TOP_P),
+		      .LATENCY(LATENCY), .CASCADE_IN(CASCADE_IN), .CASCADE_OUT(CASCADE_OUT)) mult_add_q
+	     (.clk(clk), .reset(reset),
+	      .a_tdata(real_tdata), .a_tlast(real_tlast), .a_tvalid(real_tvalid), .a_tready(),
+	      .b_tdata(cplx_tdata[WIDTH_CPLX-1:0]), .b_tlast(cplx_tlast), .b_tvalid(cplx_tvalid), .b_tready(),
+	      .c_tdata(c_tdata[WIDTH_P-1:0]), .c_tlast(c_tlast), .c_tvalid(c_tvalid), .c_tready(),
+	      .p_tdata(p_tdata[WIDTH_P-1:0]), .p_tlast(), .p_tvalid(), .p_tready(p_tready));
+        end // if (WIDTH_REAL > WIDTH_CPLX)
+      else
+	begin
+	   mult_add #(.WIDTH_A(WIDTH_CPLX), .WIDTH_B(WIDTH_REAL), .WIDTH_P(WIDTH_P), .DROP_TOP_P(DROP_TOP_P),
+		      .LATENCY(LATENCY), .CASCADE_IN(CASCADE_IN), .CASCADE_OUT(CASCADE_OUT)) mult_add_i
+	     (.clk(clk), .reset(reset),
+	      .a_tdata(cplx_tdata[2*WIDTH_CPLX-1:WIDTH_CPLX]), .a_tlast(cplx_tlast), .a_tvalid(cplx_tvalid), .a_tready(cplx_tready),
+	      .b_tdata(real_tdata), .b_tlast(real_tlast), .b_tvalid(real_tvalid), .b_tready(real_tready),
+	      .c_tdata(c_tdata[2*WIDTH_P-1:WIDTH_P]), .c_tlast(c_tlast), .c_tvalid(c_tvalid), .c_tready(c_tready),
+	      .p_tdata(p_tdata[2*WIDTH_P-1:WIDTH_P]), .p_tlast(p_tlast), .p_tvalid(p_tvalid), .p_tready(p_tready));
+           
+	   mult_add #(.WIDTH_A(WIDTH_CPLX), .WIDTH_B(WIDTH_REAL), .WIDTH_P(WIDTH_P), .DROP_TOP_P(DROP_TOP_P),
+		      .LATENCY(LATENCY), .CASCADE_IN(CASCADE_IN), .CASCADE_OUT(CASCADE_OUT)) mult_add_q
+	     (.clk(clk), .reset(reset),
+	      .a_tdata(cplx_tdata[WIDTH_CPLX-1:0]), .a_tlast(cplx_tlast), .a_tvalid(cplx_tvalid), .a_tready(),
+	      .b_tdata(real_tdata), .b_tlast(real_tlast), .b_tvalid(real_tvalid), .b_tready(),
+	      .c_tdata(c_tdata[WIDTH_P-1:0]), .c_tlast(c_tlast), .c_tvalid(c_tvalid), .c_tready(),
+	      .p_tdata(p_tdata[WIDTH_P-1:0]), .p_tlast(), .p_tvalid(), .p_tready(p_tready));
+        end // else: !if(WIDTH_REAL > WIDTH_CPLX)
+   endgenerate
+	
+endmodule // mult
diff --git a/fpga/usrp3/lib/rfnoc/mult_rc.v b/fpga/usrp3/lib/rfnoc/mult_rc.v
new file mode 100644
index 000000000..f8643f33e
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/mult_rc.v
@@ -0,0 +1,57 @@
+
+// Copyright 2014 Ettus Research
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// Complex times real.  One width must be less than 26 and the other less than 19.
+
+module mult_rc
+  #(parameter WIDTH_REAL=25,
+    parameter WIDTH_CPLX=18,
+    parameter WIDTH_P=48,
+    parameter DROP_TOP_P=0,
+    parameter LATENCY=3,
+    parameter CASCADE_OUT=0)
+   (input clk, input reset,
+    input [WIDTH_REAL-1:0] real_tdata, input real_tlast, input real_tvalid, output real_tready,
+    input [2*WIDTH_CPLX-1:0] cplx_tdata, input cplx_tlast, input cplx_tvalid, output cplx_tready,
+    output [2*WIDTH_P-1:0] p_tdata, output p_tlast, output p_tvalid, input p_tready);
+
+   // NOTE -- we cheat here and share ready/valid.  This works because we can guarantee both
+   //           paths will match
+   generate
+      if(WIDTH_REAL > WIDTH_CPLX)
+	begin
+	   mult #(.WIDTH_A(WIDTH_REAL), .WIDTH_B(WIDTH_CPLX), .WIDTH_P(WIDTH_P), .DROP_TOP_P(DROP_TOP_P),
+		  .LATENCY(LATENCY), .CASCADE_OUT(CASCADE_OUT)) mult_i
+	     (.clk(clk), .reset(reset),
+	      .a_tdata(real_tdata), .a_tlast(real_tlast), .a_tvalid(real_tvalid), .a_tready(real_tready),
+	      .b_tdata(cplx_tdata[2*WIDTH_CPLX-1:WIDTH_CPLX]), .b_tlast(cplx_tlast), .b_tvalid(cplx_tvalid), .b_tready(cplx_tready),
+	      .p_tdata(p_tdata[2*WIDTH_P-1:WIDTH_P]), .p_tlast(p_tlast), .p_tvalid(p_tvalid), .p_tready(p_tready));
+           
+	   mult #(.WIDTH_A(WIDTH_REAL), .WIDTH_B(WIDTH_CPLX), .WIDTH_P(WIDTH_P), .DROP_TOP_P(DROP_TOP_P),
+		  .LATENCY(LATENCY), .CASCADE_OUT(CASCADE_OUT)) mult_q
+	     (.clk(clk), .reset(reset),
+	      .a_tdata(real_tdata), .a_tlast(real_tlast), .a_tvalid(real_tvalid), .a_tready(),
+	      .b_tdata(cplx_tdata[WIDTH_CPLX-1:0]), .b_tlast(cplx_tlast), .b_tvalid(cplx_tvalid), .b_tready(),
+	      .p_tdata(p_tdata[WIDTH_P-1:0]), .p_tlast(), .p_tvalid(), .p_tready(p_tready));
+        end // if (WIDTH_REAL > WIDTH_CPLX)
+      else
+	begin
+	   mult #(.WIDTH_A(WIDTH_CPLX), .WIDTH_B(WIDTH_REAL), .WIDTH_P(WIDTH_P), .DROP_TOP_P(DROP_TOP_P),
+		  .LATENCY(LATENCY), .CASCADE_OUT(CASCADE_OUT)) mult_i
+	     (.clk(clk), .reset(reset),
+	      .a_tdata(cplx_tdata[2*WIDTH_CPLX-1:WIDTH_CPLX]), .a_tlast(cplx_tlast), .a_tvalid(cplx_tvalid), .a_tready(cplx_tready),
+	      .b_tdata(real_tdata), .b_tlast(real_tlast), .b_tvalid(real_tvalid), .b_tready(real_tready),
+	      .p_tdata(p_tdata[2*WIDTH_P-1:WIDTH_P]), .p_tlast(p_tlast), .p_tvalid(p_tvalid), .p_tready(p_tready));
+           
+	   mult #(.WIDTH_A(WIDTH_CPLX), .WIDTH_B(WIDTH_REAL), .WIDTH_P(WIDTH_P), .DROP_TOP_P(DROP_TOP_P),
+		  .LATENCY(LATENCY), .CASCADE_OUT(CASCADE_OUT)) mult_q
+	     (.clk(clk), .reset(reset),
+	      .a_tdata(cplx_tdata[WIDTH_CPLX-1:0]), .a_tlast(cplx_tlast), .a_tvalid(cplx_tvalid), .a_tready(),
+	      .b_tdata(real_tdata), .b_tlast(real_tlast), .b_tvalid(real_tvalid), .b_tready(),
+	      .p_tdata(p_tdata[WIDTH_P-1:0]), .p_tlast(), .p_tvalid(), .p_tready(p_tready));
+	end // else: !if(WIDTH_REAL > WIDTH_CPLX)
+   endgenerate
+   
+endmodule // mult_rc
diff --git a/fpga/usrp3/lib/rfnoc/multiply.v b/fpga/usrp3/lib/rfnoc/multiply.v
new file mode 100644
index 000000000..ad0353c66
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/multiply.v
@@ -0,0 +1,138 @@
+//
+// Copyright 2015 Ettus Research
+//
+// AXI Stream multiplier. Relies on synthesis engine for proper DSP inference.
+
+module multiply #(
+  parameter WIDTH_A     = 16,
+  parameter WIDTH_B     = 16,
+  parameter WIDTH_P     = 32,
+  parameter DROP_TOP_P  = 1,  // Default drops extra bit (16-bit signed x 16-bit signed => 31-bits signed)
+  parameter LATENCY     = 3,  // multiplier pipeline latency, 0 - 4
+  parameter EN_SATURATE = 0,  // Enable saturating output to avoid overflow (adds +1 to latency)
+  parameter EN_ROUND    = 0,  // Enable rounding dropped LSBs (adds +1 to latency, total of +2 if used with EN_SATURATE)
+  parameter SIGNED      = 1)  // Signed multiply
+(
+  input clk, input reset,
+  input [WIDTH_A-1:0] a_tdata, input a_tlast, input a_tvalid, output a_tready,
+  input [WIDTH_B-1:0] b_tdata, input b_tlast, input b_tvalid, output b_tready,
+  output [WIDTH_P-1:0] p_tdata, output p_tlast, output p_tvalid, input p_tready
+);
+
+  localparam A_LATENCY = (LATENCY == 1) ? 1 :
+                         (LATENCY == 2) ? 1 :
+                         (LATENCY == 3) ? 2 :
+                         (LATENCY == 4) ? 2 : 2;
+  localparam B_LATENCY = A_LATENCY;
+  localparam P_LATENCY = (LATENCY == 2) ? 1 :
+                         (LATENCY == 3) ? 1 :
+                         (LATENCY == 4) ? 2 : 2;
+
+  reg [WIDTH_A-1:0]         a_reg[A_LATENCY-1:0];
+  reg [WIDTH_B-1:0]         b_reg[B_LATENCY-1:0];
+  reg [WIDTH_A+WIDTH_B-1:0] p_reg[P_LATENCY-1:0];
+
+  wire [A_LATENCY-1:0] en_a_reg;
+  wire [B_LATENCY-1:0] en_b_reg;
+  wire [P_LATENCY-1:0] en_p_reg;
+  wire p_int_tlast, p_int_tvalid, p_int_tready;
+  axi_pipe_join #(
+    .PRE_JOIN_STAGES0(A_LATENCY),
+    .PRE_JOIN_STAGES1(B_LATENCY),
+    .POST_JOIN_STAGES(P_LATENCY))
+  axi_pipe_join (
+    .clk(clk), .reset(reset), .clear(1'b0),
+    .i0_tlast(a_tlast), .i0_tvalid(a_tvalid), .i0_tready(a_tready),
+    .i1_tlast(b_tlast), .i1_tvalid(b_tvalid), .i1_tready(b_tready),
+    .o_tlast(p_int_tlast), .o_tvalid(p_int_tvalid), .o_tready(p_int_tready),
+    .enables0(en_a_reg), .enables1(en_b_reg), .enables_post(en_p_reg));
+
+  // Multiply
+  wire [WIDTH_A+WIDTH_B-1:0] p_mult_signed   = (LATENCY == 0) ? $signed(a_tdata) * $signed(b_tdata) : $signed(a_reg[A_LATENCY-1]) * $signed(b_reg[B_LATENCY-1]);
+  wire [WIDTH_A+WIDTH_B-1:0] p_mult_unsigned = (LATENCY == 0) ? a_tdata * b_tdata : a_reg[A_LATENCY-1] * b_reg[B_LATENCY-1];
+  wire [WIDTH_A+WIDTH_B-1:0] p_int_tdata     = (LATENCY == 0) ? (SIGNED ? p_mult_signed : p_mult_unsigned) : p_reg[P_LATENCY-1];
+
+  // Register pipeline
+  integer i;
+  always @(posedge clk) begin
+    if (reset) begin
+      for (i = 0; i < A_LATENCY; i = i + 1) begin
+        a_reg[i] <= 'd0;
+      end
+      for (i = 0; i < B_LATENCY; i = i + 1) begin
+        b_reg[i] <= 'd0;
+      end
+      for (i = 0; i < P_LATENCY; i = i + 1) begin
+        p_reg[i] <= 'd0;
+      end
+    end else begin
+      for (i = 0; i < A_LATENCY; i = i + 1) begin
+        if (en_a_reg[i]) begin
+          if (i == 0) begin
+            a_reg[i] <= $signed(a_tdata);
+          end else begin
+            a_reg[i] <= a_reg[i-1];
+          end
+        end
+      end
+      for (i = 0; i < B_LATENCY; i = i + 1) begin
+        if (en_b_reg[i]) begin
+          if (i == 0) begin
+            b_reg[i] <= $signed(b_tdata);
+          end else begin
+            b_reg[i] <= b_reg[i-1];
+          end
+        end
+      end
+      for (i = 0; i < P_LATENCY; i = i + 1) begin
+        if (en_p_reg[i]) begin
+          if (i == 0) begin
+            p_reg[i] <= SIGNED ? p_mult_signed : p_mult_unsigned;
+          end else begin
+            p_reg[i] <= p_reg[i-1];
+          end
+        end
+      end
+    end
+  end
+
+  // Saturate & Round
+  // TODO: Might be able to replace axi_round with DSP's built in rounding
+  generate
+    if ((EN_SATURATE == 1) && (EN_ROUND == 1)) begin
+      axi_round_and_clip #(
+        .WIDTH_IN(WIDTH_A+WIDTH_B),
+        .WIDTH_OUT(WIDTH_P),
+        .CLIP_BITS(DROP_TOP_P))
+      axi_round_and_clip (
+        .clk(clk), .reset(reset),
+        .i_tdata(p_int_tdata), .i_tlast(p_int_tlast), .i_tvalid(p_int_tvalid), .i_tready(p_int_tready),
+        .o_tdata(p_tdata), .o_tlast(p_tlast), .o_tvalid(p_tvalid), .o_tready(p_tready));
+    end else if ((EN_SATURATE == 0) && (EN_ROUND == 1)) begin
+      axi_round #(
+        .WIDTH_IN(WIDTH_A+WIDTH_B-DROP_TOP_P),
+        .WIDTH_OUT(WIDTH_P))
+      axi_round (
+        .clk(clk), .reset(reset),
+        .i_tdata(p_int_tdata[WIDTH_A+WIDTH_B-DROP_TOP_P-1:0]), .i_tlast(p_int_tlast), .i_tvalid(p_int_tvalid), .i_tready(p_int_tready),
+        .o_tdata(p_tdata), .o_tlast(p_tlast), .o_tvalid(p_tvalid), .o_tready(p_tready));
+    end else if ((EN_SATURATE == 1) && (EN_ROUND == 0)) begin
+      wire [WIDTH_A+WIDTH_B-DROP_TOP_P-1:0] p_clip_tdata;
+      axi_clip #(
+        .WIDTH_IN(WIDTH_A+WIDTH_B),
+        .WIDTH_OUT(WIDTH_A+WIDTH_B-DROP_TOP_P),
+        .CLIP_BITS(DROP_TOP_P))
+      axi_clip (
+        .clk(clk), .reset(reset),
+        .i_tdata(p_int_tdata), .i_tlast(p_int_tlast), .i_tvalid(p_int_tvalid), .i_tready(p_int_tready),
+        .o_tdata(p_clip_tdata), .o_tlast(p_tlast), .o_tvalid(p_tvalid), .o_tready(p_tready));
+      assign p_tdata = p_clip_tdata[WIDTH_A+WIDTH_B-DROP_TOP_P-1:WIDTH_A+WIDTH_B-DROP_TOP_P-WIDTH_P];
+    end else begin
+      assign p_tdata      = p_int_tdata[WIDTH_A+WIDTH_B-DROP_TOP_P-1:WIDTH_A+WIDTH_B-DROP_TOP_P-WIDTH_P];
+      assign p_tlast      = p_int_tlast;
+      assign p_tvalid     = p_int_tvalid;
+      assign p_int_tready = p_tready;
+    end
+  endgenerate
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/noc_shell_regs.vh b/fpga/usrp3/lib/rfnoc/noc_shell_regs.vh
new file mode 100644
index 000000000..a81bd4119
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/noc_shell_regs.vh
@@ -0,0 +1,25 @@
+  // Registers 0 - 127 for NoC Shell
+  localparam [7:0] SR_FLOW_CTRL_BYTES_PER_ACK     = 1;
+  localparam [7:0] SR_FLOW_CTRL_WINDOW_SIZE       = 2;
+  localparam [7:0] SR_FLOW_CTRL_EN                = 3;
+  localparam [7:0] SR_ERROR_POLICY                = 4;
+  localparam [7:0] SR_SRC_SID                     = 5;
+  localparam [7:0] SR_NEXT_DST_SID                = 6;
+  localparam [7:0] SR_RESP_IN_DST_SID             = 7;
+  localparam [7:0] SR_RESP_OUT_DST_SID            = 8;
+  localparam [7:0] SR_FLOW_CTRL_PKT_LIMIT         = 9;
+  localparam [7:0] SR_RB_ADDR_USER                = 124;
+  localparam [7:0] SR_CLEAR_RX_FC                 = 125;
+  localparam [7:0] SR_CLEAR_TX_FC                 = 126;
+  localparam [7:0] SR_RB_ADDR                     = 127;
+  // Registers 128-255 for users
+  localparam [7:0] SR_USER_REG_BASE               = 128;
+
+  // NoC Shell readback registers
+  localparam [7:0] RB_NOC_ID                      = 0;
+  localparam [7:0] RB_GLOBAL_PARAMS               = 1;
+  localparam [7:0] RB_FIFOSIZE                    = 2;
+  localparam [7:0] RB_MTU                         = 3;
+  localparam [7:0] RB_BLOCK_PORT_SIDS             = 4;
+  localparam [7:0] RB_USER_RB_DATA                = 5;
+  localparam [7:0] RB_NOC_SHELL_COMPAT_NUM        = 6;
diff --git a/fpga/usrp3/lib/rfnoc/noc_traffic_counter.v b/fpga/usrp3/lib/rfnoc/noc_traffic_counter.v
new file mode 100644
index 000000000..5ac2ff44e
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/noc_traffic_counter.v
@@ -0,0 +1,128 @@
+//
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module noc_traffic_counter #(
+  parameter SR_REG_BASE = 128,
+  parameter RB_REG_BASE = 0)
+(
+  input bus_clk, input bus_rst,
+  input ce_clk, input ce_rst,
+
+  // Control sink
+  input [31:0] set_data, input [7:0] set_addr, input set_stb,
+  output rb_stb, input [7:0] rb_addr, output [63:0] rb_data,
+
+  // Traffic signals to count
+  input i_tlast, input i_tvalid, input i_tready,
+  input o_tlast, input o_tvalid, input  o_tready,
+  input str_sink_tlast, input str_sink_tvalid, input str_sink_tready,
+  input str_src_tlast, input str_src_tvalid, input str_src_tready
+);
+  wire        en, counter_enable_changed;
+
+  wire [31:0] set_data_bclk;
+  wire [7:0]  set_addr_bclk;
+  wire        set_stb_bclk;
+
+  reg  [63:0] rb_data_bclk;
+  wire [7:0]  rb_addr_bclk;
+  reg         rb_stb_bclk;
+
+  reg  [63:0] tick_cnt_noc_shell;
+
+  wire [63:0] xbar_to_shell_xfer_cnt;
+  wire [63:0] xbar_to_shell_pkt_cnt;
+
+  wire [63:0] shell_to_xbar_xfer_cnt;
+  wire [63:0] shell_to_xbar_pkt_cnt;
+
+  wire [63:0] shell_to_ce_xfer_cnt;
+  wire [63:0] shell_to_ce_pkt_cnt;
+
+  wire [63:0] ce_to_shell_xfer_cnt;
+  wire [63:0] ce_to_shell_pkt_cnt;
+
+  localparam SR_COUNTER_ENABLE      = SR_REG_BASE + 0;
+
+  localparam RB_SIGNATURE              = RB_REG_BASE + 0;
+  localparam RB_BUS_CLK_TICKS          = RB_REG_BASE + 1;
+  localparam RB_XBAR_TO_SHELL_XFER_CNT = RB_REG_BASE + 2;
+  localparam RB_XBAR_TO_SHELL_PKT_CNT  = RB_REG_BASE + 3;
+  localparam RB_SHELL_TO_XBAR_XFER_CNT = RB_REG_BASE + 4;
+  localparam RB_SHELL_TO_XBAR_PKT_CNT  = RB_REG_BASE + 5;
+  localparam RB_SHELL_TO_CE_XFER_CNT   = RB_REG_BASE + 6;
+  localparam RB_SHELL_TO_CE_PKT_CNT    = RB_REG_BASE + 7;
+  localparam RB_CE_TO_SHELL_XFER_CNT   = RB_REG_BASE + 8;
+  localparam RB_CE_TO_SHELL_PKT_CNT    = RB_REG_BASE + 9;
+
+  // Registers are implemented on bus clock
+  axi_fifo_2clk #(.WIDTH(8+8+32), .SIZE(2)) reg_write_to_bclk (
+     .reset(ce_rst), .i_aclk(ce_clk),
+     .i_tdata({set_addr, rb_addr, set_data}), .i_tvalid(set_stb), .i_tready(),
+     .o_aclk(bus_clk),
+     .o_tdata({set_addr_bclk, rb_addr_bclk, set_data_bclk}), .o_tvalid(set_stb_bclk), .o_tready(1'b1));
+
+  axi_fifo_2clk #(.WIDTH(64), .SIZE(2)) reg_rb_from_bclk (
+     .reset(bus_rst), .i_aclk(bus_clk),
+     .i_tdata(rb_data_bclk), .i_tvalid(rb_stb_bclk), .i_tready(),
+     .o_aclk(ce_clk),
+     .o_tdata(rb_data), .o_tvalid(rb_stb), .o_tready(1'b1));
+
+  setting_reg #(.my_addr(SR_COUNTER_ENABLE), .width(1)) enable_measurement_reg (
+    .clk(bus_clk), .rst(bus_rst), .strobe(set_stb_bclk), .addr(set_addr_bclk),
+    .in(set_data_bclk), .out(en), .changed(counter_enable_changed));
+
+  always @(posedge bus_clk)
+    if (set_stb_bclk) begin
+      case(rb_addr_bclk)
+        RB_SIGNATURE             : rb_data_bclk <= 64'h712AFF1C00000000;
+        RB_BUS_CLK_TICKS         : rb_data_bclk <= tick_cnt_noc_shell;
+        RB_XBAR_TO_SHELL_XFER_CNT : rb_data_bclk <= xbar_to_shell_xfer_cnt;
+        RB_XBAR_TO_SHELL_PKT_CNT  : rb_data_bclk <= xbar_to_shell_pkt_cnt;
+        RB_SHELL_TO_XBAR_XFER_CNT : rb_data_bclk <= shell_to_xbar_xfer_cnt;
+        RB_SHELL_TO_XBAR_PKT_CNT  : rb_data_bclk <= shell_to_xbar_pkt_cnt;
+        RB_SHELL_TO_CE_XFER_CNT   : rb_data_bclk <= shell_to_ce_xfer_cnt;
+        RB_SHELL_TO_CE_PKT_CNT    : rb_data_bclk <= shell_to_ce_pkt_cnt;
+        RB_CE_TO_SHELL_XFER_CNT   : rb_data_bclk <= ce_to_shell_xfer_cnt;
+        RB_CE_TO_SHELL_PKT_CNT    : rb_data_bclk <= ce_to_shell_pkt_cnt;
+        default                   : rb_data_bclk <= 64'h0BADC0DE0BADC0DE;
+      endcase
+    end
+
+  always @(posedge bus_clk)
+    rb_stb_bclk <= set_stb_bclk;
+
+  assign counter_rst = en & counter_enable_changed;
+
+  axis_strm_monitor #(.COUNT_W(64), .PKT_COUNT_EN(1), .XFER_COUNT_EN(1)) xbar_to_shell (
+    .clk(bus_clk), .reset(counter_rst),
+    .axis_tdata(), .axis_tlast(i_tlast & en), .axis_tvalid(i_tvalid & en), .axis_tready(i_tready & en),
+    .xfer_count(xbar_to_shell_xfer_cnt), .pkt_count(xbar_to_shell_pkt_cnt));
+
+  axis_strm_monitor #(.COUNT_W(64), .PKT_COUNT_EN(1), .XFER_COUNT_EN(1)) shell_to_xbar (
+    .clk(bus_clk), .reset(counter_rst),
+    .axis_tdata(), .axis_tlast(o_tlast & en), .axis_tvalid(o_tvalid & en), .axis_tready(o_tready & en),
+    .xfer_count(shell_to_xbar_xfer_cnt), .pkt_count(shell_to_xbar_pkt_cnt));
+
+  axis_strm_monitor #(.COUNT_W(64), .PKT_COUNT_EN(1), .XFER_COUNT_EN(1)) shell_to_ce (
+    .clk(bus_clk), .reset(counter_rst),
+    .axis_tdata(), .axis_tlast(str_sink_tlast & en), .axis_tvalid(str_sink_tvalid & en), .axis_tready(str_sink_tready & en),
+    .xfer_count(shell_to_ce_xfer_cnt), .pkt_count(shell_to_ce_pkt_cnt));
+
+  axis_strm_monitor #(.COUNT_W(64), .PKT_COUNT_EN(1), .XFER_COUNT_EN(1)) ce_to_shell (
+    .clk(bus_clk), .reset(counter_rst),
+    .axis_tdata(), .axis_tlast(str_src_tlast & en), .axis_tvalid(str_src_tvalid & en), .axis_tready(str_src_tready & en),
+    .xfer_count(ce_to_shell_xfer_cnt), .pkt_count(ce_to_shell_pkt_cnt));
+
+  // Count clock ticks
+  always @(posedge bus_clk)
+    if (counter_rst)
+      tick_cnt_noc_shell <= 0;
+    else
+      if (en)
+        tick_cnt_noc_shell <= tick_cnt_noc_shell + 1;
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/null_source.v b/fpga/usrp3/lib/rfnoc/null_source.v
new file mode 100644
index 000000000..f31188dee
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/null_source.v
@@ -0,0 +1,99 @@
+
+// Copyright 2014, Ettus Research
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+
+// Dummy data source.  Turn it on by setting a packet length in its setting reg, turn it off by setting 0.  
+// Will generate as fast as it can.
+
+module null_source
+  #(parameter SR_LINES_PER_PACKET    = 129,
+    parameter SR_LINE_RATE           = 130,
+    parameter SR_ENABLE_STREAM       = 131)
+   (input clk, input reset, input clear,
+    input [31:0] sid,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    output [63:0] o_tdata, output o_tlast, output o_tvalid, input o_tready);
+
+   reg [11:0]      seqnum;
+   wire [15:0]      rate;
+   reg [1:0]      state;
+   reg [15:0]      line_number;
+   
+   wire [63:0]      int_tdata;
+   wire      int_tlast, int_tvalid, int_tready;
+
+   wire [15:0]      len;
+   reg [15:0]      count;
+   reg [15:0]      packet_count;
+   wire      enable;
+   
+   setting_reg #(.my_addr(SR_LINES_PER_PACKET), .width(16)) len_reg
+     (.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
+      .out(len), .changed());
+
+   setting_reg #(.my_addr(SR_LINE_RATE), .width(16)) rate_reg
+     (.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
+      .out(rate), .changed());
+
+   setting_reg #(.my_addr(SR_ENABLE_STREAM), .width(1)) enable_reg
+     (.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
+      .out(enable), .changed());
+
+   localparam IDLE = 2'd0;
+   localparam HEAD = 2'd1;
+   localparam DATA = 2'd2;
+
+   always @(posedge clk)
+      if(reset | clear) begin
+         state <= IDLE;
+         count <= 0;
+         seqnum <= 0;
+      end else begin
+         case(state)
+         IDLE :
+            if(enable)
+               state <= HEAD;
+         HEAD :
+            if(int_tvalid & int_tready) begin
+               count <= 1;
+               state <= DATA;
+               seqnum <= seqnum + 1;
+            end
+         DATA :
+            if(int_tvalid & int_tready)
+               if(count >= len) begin
+                  state <= IDLE;
+                  count <= 0;
+               end
+            else
+               count <= count + 1;
+         default :
+            state <= IDLE;
+         endcase // case (state)
+      end // else: !if(reset)
+
+   wire [15:0] pkt_len = { len[12:0], 3'b000 } + 16'd8;
+   
+   assign int_tdata = (state == HEAD) ? { 4'b0000, seqnum, pkt_len, sid } : {~count,count,count,count} ;
+   assign int_tlast = (count >= len);
+
+   reg [15:0]  line_timer;
+   always @(posedge clk)
+      if(reset | clear)
+         line_timer <= 0;
+      else
+         if(line_timer == 0)
+            line_timer <= rate;
+         else
+            line_timer <= line_timer - 1;
+
+   assign int_tvalid = ((state==HEAD)|(state==DATA)) & (line_timer==0);
+
+   axi_packet_gate #(.WIDTH(64), .SIZE(10)) gate
+     (.clk(clk), .reset(reset), .clear(clear),
+      .i_tdata(int_tdata), .i_tlast(int_tlast), .i_terror(1'b0), .i_tvalid(int_tvalid), .i_tready(int_tready),
+      .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready));
+   
+endmodule // null_source
diff --git a/fpga/usrp3/lib/rfnoc/packet_resizer.v b/fpga/usrp3/lib/rfnoc/packet_resizer.v
new file mode 100644
index 000000000..5d2675df5
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/packet_resizer.v
@@ -0,0 +1,70 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Not necessarily that useful in general, but a good test block
+
+module packet_resizer
+  #(parameter SR_PKT_SIZE=1)
+   (input clk, input reset,
+    input [15:0] next_dst_sid,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    input [31:0] i_tdata, input [127:0] i_tuser, input i_tlast, input i_tvalid, output i_tready,
+    output [31:0] o_tdata, output [127:0] o_tuser, output o_tlast, output o_tvalid, input o_tready);
+
+   wire [15:0] 	  pkt_size;
+   reg [15:0] 	  count;
+   reg 		  first_packet_in_burst = 1'b1;
+   
+   setting_reg #(.my_addr(SR_PKT_SIZE), .width(16)) reg_pkt_size
+     (.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
+      .out(pkt_size));
+
+   // Parse i_tuser
+   wire [1:0] 	  TYPE_in = i_tuser[127:126];
+   wire 	  TSI_in = i_tuser[125];
+   wire 	  EOB_in = i_tuser[124];
+   wire [11:0] 	  SEQ_in = i_tuser[123:112];
+   wire [15:0] 	  LEN_in = i_tuser[111:96];
+   wire [15:0] 	  SRC_in = i_tuser[95:80];
+   wire [15:0] 	  DST_in = i_tuser[79:64];
+   wire [63:0] 	  TIME_in = i_tuser[63:0];
+   
+   // Generate o_tuser
+   wire [1:0] 	  TYPE_out = TYPE_in;
+   wire 	  TSI_out = TSI_in & first_packet_in_burst;
+   wire 	  EOB_out = EOB_in & i_tlast;
+   wire [11:0] 	  SEQ_out = SEQ_in;     // Doesn't actually matter, it gets overwritten by chdr_framer
+   wire [15:0] 	  LEN_out = LEN_in;     // Only the bottom 2 bits actually matter, rest gets overwritten
+   wire [15:0] 	  SRC_out = DST_in;
+   wire [15:0] 	  DST_out = next_dst_sid;
+   wire [63:0] 	  TIME_out = TIME_in;
+
+   // Pass nearly everything through unchanged
+   assign o_tdata = i_tdata;
+   assign o_tlast = (count == pkt_size) | EOB_out;   
+   assign o_tuser = { TYPE_out, TSI_out, EOB_out, SEQ_out, LEN_out, SRC_out, DST_out, TIME_out };
+
+   assign o_tvalid = i_tvalid;
+   assign i_tready = o_tready;
+
+   always @(posedge clk)
+     if(reset)
+       count <= 16'd4;
+     else
+       if(o_tvalid & o_tready)
+	 if(o_tlast)
+	   count <= 16'd4;
+	 else
+	   count <= count + 16'd4;
+
+   always @(posedge clk)
+     if(reset)
+       first_packet_in_burst <= 1'b1;
+     else
+       if(o_tvalid & o_tready & o_tlast)
+	 first_packet_in_burst <= EOB_out;
+   
+endmodule // packet_resizer
diff --git a/fpga/usrp3/lib/rfnoc/periodic_framer.v b/fpga/usrp3/lib/rfnoc/periodic_framer.v
new file mode 100644
index 000000000..3e83bcf8d
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/periodic_framer.v
@@ -0,0 +1,151 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module periodic_framer #(
+  parameter SR_FRAME_LEN            = 0,
+  parameter SR_GAP_LEN              = 1,
+  parameter SR_OFFSET               = 2,
+  parameter SR_NUMBER_SYMBOLS_MAX   = 3,
+  parameter SR_NUMBER_SYMBOLS_SHORT = 4,
+  // Skip a set number of gaps at the beginning. Use 1 to properly frame 802.11 long preamble.
+  parameter SKIP_GAPS               = 1,
+  parameter WIDTH                   = 32)
+(
+  input clk, input reset, input clear,
+  input set_stb, input [7:0] set_addr, input [31:0] set_data,
+  input [WIDTH-1:0] stream_i_tdata, input stream_i_tlast, input stream_i_tvalid, output stream_i_tready,
+  output [WIDTH-1:0] stream_o_tdata, output stream_o_tlast, output stream_o_tvalid, input stream_o_tready,
+  output reg sof, output reg eof);
+
+  wire [15:0] frame_len;
+  wire [15:0] gap_len;
+  wire [15:0] offset;
+
+  wire [15:0] numsymbols_max, numsymbols_thisburst, numsymbols_short;
+  wire [15:0] burst_len;
+  wire        set_numsymbols;
+  wire        consume;
+  reg  [15:0] counter;
+  reg  [$clog2(SKIP_GAPS):0] skip_cnt;
+  reg  [15:0] numsymbols;
+
+  setting_reg #(.my_addr(SR_FRAME_LEN), .width(16)) reg_frame_len (
+    .clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
+    .out(frame_len), .changed());
+
+  setting_reg #(.my_addr(SR_GAP_LEN), .width(16)) reg_gap_len (
+    .clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
+    .out(gap_len), .changed());
+
+  setting_reg #(.my_addr(SR_OFFSET), .width(16)) reg_offset (
+    .clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
+    .out(offset), .changed());
+
+  setting_reg #(.my_addr(SR_NUMBER_SYMBOLS_MAX), .width(16)) reg_max_symbols (
+    .clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
+    .out(numsymbols_max), .changed());
+
+  setting_reg #(.my_addr(SR_NUMBER_SYMBOLS_SHORT), .width(16)) reg_symbols_short (
+    .clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
+    .out(numsymbols_short), .changed(set_numsymbols));
+
+  reg [1:0]  state;
+  localparam ST_WAIT_FOR_TRIG = 2'd0;
+  localparam ST_DO_OFFSET     = 2'd1;
+  localparam ST_FRAME         = 2'd2;
+  localparam ST_GAP           = 2'd3;
+
+  reg shorten_burst;
+  always @(posedge clk) begin
+    if (reset | clear) begin
+      shorten_burst <= 1'b0;
+    end else if (set_numsymbols) begin
+      shorten_burst <= 1'b1;
+    end else if(state == ST_WAIT_FOR_TRIG) begin
+      shorten_burst <= 1'b0;
+    end
+  end
+
+  assign numsymbols_thisburst = shorten_burst ? numsymbols_short : numsymbols_max;
+
+  always @(posedge clk) begin
+    if (reset | clear) begin
+      eof        <= 1'b0;
+      sof        <= 1'b0;
+      counter    <= 1;
+      skip_cnt   <= 0;
+      numsymbols <= 16'd1;
+      state      <= ST_WAIT_FOR_TRIG;
+    end else begin
+      if (consume) begin
+        case(state)
+          ST_WAIT_FOR_TRIG : begin
+            eof       <= 1'b0;
+            skip_cnt  <= 0;
+            if (stream_i_tlast) begin
+              counter <= 16'b1;
+              if (offset == 0) begin
+                state   <= ST_FRAME;
+              end else begin
+                state   <= ST_DO_OFFSET;
+              end
+            end
+          end
+
+          ST_DO_OFFSET : begin
+            if (counter >= offset) begin
+              sof        <= 1'b1;
+              counter    <= 16'b1;
+              numsymbols <= 16'd1;
+              state      <= ST_FRAME;
+            end else begin
+              counter <= counter + 16'd1;
+            end
+          end
+
+          ST_FRAME : begin
+            if (counter >= frame_len) begin
+              sof        <= 1'b0;
+              counter    <= 1;
+              numsymbols <= numsymbols + 1;
+              if (numsymbols >= numsymbols_thisburst) begin
+                eof      <= 1'b1;
+                state    <= ST_WAIT_FOR_TRIG;
+              end else begin
+                if (skip_cnt < SKIP_GAPS) begin
+                  skip_cnt <= skip_cnt + 1;
+                  state    <= ST_FRAME;
+                end else begin
+                  state  <= ST_GAP;
+                end
+              end
+            end else begin
+              counter <= counter + 16'd1;
+            end
+          end
+
+          ST_GAP : begin
+            if (counter >= gap_len) begin
+              state   <= ST_FRAME;
+              counter <= 1;
+            end else begin
+              counter <= counter + 16'd1;
+            end
+          end
+        endcase
+      end
+    end
+  end
+
+  assign stream_o_tdata = stream_i_tdata;
+  assign stream_o_tlast = (state == ST_FRAME) & (counter >= frame_len);
+  assign stream_o_tvalid = stream_i_tvalid & (state == ST_FRAME);
+
+  assign stream_i_tready = consume;
+  assign consume = stream_i_tvalid & ((state != ST_FRAME) | stream_o_tready);
+
+endmodule // periodic_framer
diff --git a/fpga/usrp3/lib/rfnoc/phase_accum.v b/fpga/usrp3/lib/rfnoc/phase_accum.v
new file mode 100644
index 000000000..a1c50b28a
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/phase_accum.v
@@ -0,0 +1,72 @@
+//
+// Copyright 2015 Ettus Research
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Expects scaled radians fixed point input format of the form Q2.#,
+// Example: WIDTH_IN=8 then input format: Q2.5 (sign bit, 2 integer bits, 5 fraction bits)
+module phase_accum #(
+  parameter REVERSE_ROTATION = 0, // Negate phase increment value
+  parameter WIDTH_ACCUM = 16,
+  parameter WIDTH_IN = 16,
+  parameter WIDTH_OUT = 16)
+(
+  input clk, input reset, input clear,
+  input [WIDTH_IN-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
+  output [WIDTH_OUT-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready
+);
+
+  reg signed [WIDTH_ACCUM-1:0] accum, accum_next, phase_inc;
+  // Scaled radians. Restrict range from +1 to -1.
+  wire signed [WIDTH_ACCUM-1:0] POS_ROLLOVER = 2**(WIDTH_ACCUM-3);
+  wire signed [WIDTH_ACCUM-1:0] NEG_ROLLOVER = -(2**(WIDTH_ACCUM-3));
+
+  wire [WIDTH_OUT-1:0] output_round_tdata;
+  wire output_round_tvalid, output_round_tready, output_round_tlast;
+
+  // Phase accumulator, can rotate in either direction
+  always @(posedge clk) begin
+    if (reset | clear) begin
+      accum      <= 'd0;
+      accum_next <= 'd0;
+      phase_inc  <= 'd0;
+    end else if (i_tready & i_tvalid) begin
+      if (i_tlast) begin
+        accum       <= {WIDTH_ACCUM{1'b0}};
+        accum_next  <= REVERSE_ROTATION ? -$signed(i_tdata) : $signed(i_tdata);
+        phase_inc   <= REVERSE_ROTATION ? -$signed(i_tdata) : $signed(i_tdata);
+      end else begin
+        if (accum_next >= POS_ROLLOVER) begin
+          accum_next <= accum_next + phase_inc - 2*POS_ROLLOVER;
+          accum      <= accum + phase_inc - 2*POS_ROLLOVER;
+        end else if (accum_next <= NEG_ROLLOVER) begin
+          accum_next <= accum_next + phase_inc - 2*NEG_ROLLOVER;
+          accum      <= accum + phase_inc - 2*NEG_ROLLOVER;
+        end else begin
+          accum_next <= accum_next + phase_inc;
+          accum      <= accum + phase_inc;
+        end
+      end
+    end
+  end
+
+  generate
+    // Bypass rounding if accumulator width is same as output width
+    if (WIDTH_ACCUM == WIDTH_OUT) begin
+      assign o_tdata  = accum;
+      assign o_tvalid = i_tvalid;
+      assign o_tlast  = i_tlast;
+      assign i_tready = o_tready;
+    end else begin
+      axi_round #(
+        .WIDTH_IN(WIDTH_ACCUM),
+        .WIDTH_OUT(WIDTH_OUT))
+      axi_round (
+        .clk(clk), .reset(reset),
+        .i_tdata(accum), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready),
+        .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready));
+    end
+  endgenerate
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/ram_to_fifo.v b/fpga/usrp3/lib/rfnoc/ram_to_fifo.v
new file mode 100644
index 000000000..2f4a4c169
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/ram_to_fifo.v
@@ -0,0 +1,57 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+// Dual ported ram attached to a FIFO for readout
+//   Most useful for storing coefficients for windows, filters, etc.
+//   Config port is used for writing in order
+//   i_* (address in) and o_* (data out) ports are for streams, and can read out in arbitrary order
+
+module ram_to_fifo
+  #(parameter DWIDTH=32,
+    parameter AWIDTH=10)
+   (input clk, input reset, input clear,
+    // FIXME add writing port
+    input [DWIDTH-1:0] config_tdata, input config_tlast, input config_tvalid, output config_tready,
+    input [AWIDTH-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
+    output [DWIDTH-1:0] o_tdata, output reg o_tlast, output reg o_tvalid, input o_tready);
+
+   // Write side
+   reg [AWIDTH-1:0] 	write_addr;
+   
+   assign config_tready = 1'b1;
+
+   always @(posedge clk)
+     if(reset | clear)
+       write_addr <= 0;
+     else
+       if(config_tvalid & config_tready)
+	 if(config_tlast)
+	   write_addr <= 0;
+	 else
+	   write_addr <= write_addr + 1;
+      
+   ram_2port #(.DWIDTH(DWIDTH), .AWIDTH(AWIDTH)) ram_2port
+     (.clka(clk), .ena(1'b1), .wea(config_tvalid), .addra(write_addr), .dia(config_tdata), .doa(), // Write port
+      .clkb(clk), .enb(i_tready & i_tvalid), .web(1'b0), .addrb(i_tdata), .dib({DWIDTH{1'b1}}), .dob(o_tdata)); // Read port
+
+   // Read side
+   assign i_tready = ~o_tvalid | o_tready;
+
+   always @(posedge clk)
+     if(reset | clear)
+       begin
+	  o_tvalid <= 1'b0;
+	  o_tlast <= 1'b0;
+       end
+     else
+       begin
+	  o_tvalid <= (i_tready & i_tvalid) | (o_tvalid & ~o_tready);
+	  if(i_tready & i_tvalid)
+	    o_tlast <= i_tlast;
+       end
+   
+endmodule // ram_to_fifo
diff --git a/fpga/usrp3/lib/rfnoc/sim/axis_pyld_ctxt_converter_tb/Makefile b/fpga/usrp3/lib/rfnoc/sim/axis_pyld_ctxt_converter_tb/Makefile
new file mode 100644
index 000000000..71d2841f9
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/sim/axis_pyld_ctxt_converter_tb/Makefile
@@ -0,0 +1,45 @@
+#
+# Copyright 2019 Ettus Research, A National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+#-------------------------------------------------
+# Top-of-Makefile
+#-------------------------------------------------
+# Define BASE_DIR to point to the "top" dir
+BASE_DIR = $(abspath ../../../../top)
+# Include viv_sim_preamble after defining BASE_DIR
+include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
+
+#-------------------------------------------------
+# Design Specific
+#-------------------------------------------------
+# Include makefiles and sources for the DUT and its dependencies
+include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs
+
+include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs
+include $(BASE_DIR)/../lib/rfnoc/crossbar/Makefile.srcs
+
+DESIGN_SRCS += $(abspath \
+$(RFNOC_CORE_SRCS) \
+$(RFNOC_XBAR_SRCS) \
+)
+
+#-------------------------------------------------
+# Testbench Specific
+#-------------------------------------------------
+SIM_TOP = axis_pyld_ctxt_converter_tb
+
+SIM_SRCS = \
+$(abspath axis_pyld_ctxt_converter_tb.sv) \
+
+# MODELSIM_USER_DO = $(abspath wave.do)
+
+#-------------------------------------------------
+# Bottom-of-Makefile
+#-------------------------------------------------
+# Include all simulator specific makefiles here
+# Each should define a unique target to simulate
+# e.g. xsim, vsim, etc and a common "clean" target
+include $(BASE_DIR)/../tools/make/viv_simulator.mak
diff --git a/fpga/usrp3/lib/rfnoc/sim/axis_pyld_ctxt_converter_tb/axis_pyld_ctxt_converter_tb.sv b/fpga/usrp3/lib/rfnoc/sim/axis_pyld_ctxt_converter_tb/axis_pyld_ctxt_converter_tb.sv
new file mode 100644
index 000000000..c8b50c15a
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/sim/axis_pyld_ctxt_converter_tb/axis_pyld_ctxt_converter_tb.sv
@@ -0,0 +1,465 @@
+//
+// Copyright 2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: axis_pyld_ctxt_converter_tb
+//
+
+`default_nettype none
+
+
+module axis_pyld_ctxt_converter_tb;
+
+  // ----------------------------------------
+  // Global settings
+  // ----------------------------------------
+  
+  // Include macros and time declarations for use with PkgTestExec
+  `include "test_exec.svh"
+
+  import PkgTestExec::*;
+  import PkgAxiStreamBfm::*;
+  import PkgChdrUtils::*;
+  import PkgChdrBfm::*;
+
+  // Parameters
+  localparam bit      VERBOSE           = 0;
+  localparam int      CHDR_W            = 64;
+  localparam int      MTU               = 7;
+  localparam int      MTU_BITS          = (1 << MTU) * CHDR_W;
+  localparam int      NINST             = 6;
+  localparam int      START_INST        = 0;
+  localparam int      STOP_INST         = NINST-1;
+  localparam int      NUM_PKTS_PER_TEST = 100;
+  localparam int      FAST_STALL_PROB   = 0;
+  localparam int      SLOW_STALL_PROB   = 35;
+  localparam realtime CHDR_CLK_PERIOD   = 3.0;
+  localparam int      MAX_PYLD_W        = 256;
+
+  typedef struct {
+    realtime clk_period;
+    int      item_w;
+    int      nipc;
+    int      ctxt_fifo;
+    int      pyld_fifo;
+    bit      prefetch;
+  } inst_params_t;
+
+  // Module instances to test
+  localparam inst_params_t INST_PARAMS[0:NINST-1] = {
+    '{clk_period: 6.0, item_w:64, nipc: 1, ctxt_fifo:5, pyld_fifo:7, prefetch:1},
+    '{clk_period:20.0, item_w:32, nipc: 6, ctxt_fifo:5, pyld_fifo:1, prefetch:1},
+    '{clk_period: 3.0, item_w:32, nipc: 4, ctxt_fifo:1, pyld_fifo:2, prefetch:0},
+    '{clk_period:10.0, item_w:16, nipc: 4, ctxt_fifo:8, pyld_fifo:5, prefetch:1},
+    '{clk_period: 3.0, item_w:32, nipc: 2, ctxt_fifo:1, pyld_fifo:7, prefetch:0},
+    '{clk_period: 3.0, item_w:8,  nipc:13, ctxt_fifo:1, pyld_fifo:7, prefetch:0}
+  };
+
+  // ----------------------------------------
+  // Interfaces and clocks
+  // ----------------------------------------
+
+  // Clocks and resets
+  bit             rfnoc_chdr_clk, rfnoc_chdr_rst;
+  bit [NINST-1:0] rfnoc_data_clk, rfnoc_data_rst;
+  // Common CHDR Clock
+  sim_clock_gen #(CHDR_CLK_PERIOD) chdr_clk_gen_i (rfnoc_chdr_clk, rfnoc_chdr_rst);
+
+  // Flush interface
+  logic [31:0] r2c_framer_errors[0:NINST-1];
+  logic [31:0] r2c_flush_timeout[0:NINST-1], c2r_flush_timeout[0:NINST-1];
+  logic [0:0]  r2c_flush_en     [0:NINST-1], c2r_flush_en     [0:NINST-1];
+  wire  [0:0]  r2c_flush_active [0:NINST-1], c2r_flush_active [0:NINST-1];
+  wire  [0:0]  r2c_flush_done   [0:NINST-1], c2r_flush_done   [0:NINST-1];
+
+  // CHDR interface
+  wire [CHDR_W-1:0]  chdr_tdata [0:NINST-1];
+  wire               chdr_tlast [0:NINST-1];
+  wire               chdr_tvalid[0:NINST-1];
+  wire               chdr_tready[0:NINST-1];
+
+  // AXIS interfaces and BFMs
+  AxiStreamIf  #(CHDR_W, 4)  r2c_ctxt [0:NINST-1] ();
+  AxiStreamIf  #(CHDR_W, 4)  c2r_ctxt [0:NINST-1] ();
+  AxiStreamIf  #(MAX_PYLD_W) r2c_pyld [0:NINST-1] ();
+  AxiStreamIf  #(MAX_PYLD_W) c2r_pyld [0:NINST-1] ();
+  AxiStreamBfm #(CHDR_W, 4)  ctxt_bfm [0:NINST-1]   ;
+  AxiStreamBfm #(MAX_PYLD_W) pyld_bfm [0:NINST-1]   ;
+
+  // Instantiate DUTs
+  genvar inst_i;
+  generate for (inst_i = 0; inst_i < NINST; inst_i++) begin: inst
+
+    // Assign clocks and resets to ctxt and pyld streams
+    assign r2c_ctxt[inst_i].clk = rfnoc_data_clk[inst_i];
+    assign r2c_ctxt[inst_i].rst = rfnoc_data_rst[inst_i];
+    assign c2r_ctxt[inst_i].clk = rfnoc_data_clk[inst_i];
+    assign c2r_ctxt[inst_i].rst = rfnoc_data_rst[inst_i];
+
+    assign r2c_pyld[inst_i].clk = rfnoc_data_clk[inst_i];
+    assign r2c_pyld[inst_i].rst = rfnoc_data_rst[inst_i];
+    assign c2r_pyld[inst_i].clk = rfnoc_data_clk[inst_i];
+    assign c2r_pyld[inst_i].rst = rfnoc_data_rst[inst_i];
+
+    // Instantiate clock generator
+    sim_clock_gen #(INST_PARAMS[inst_i].clk_period) dclk_gen (
+      rfnoc_data_clk[inst_i], rfnoc_data_rst[inst_i]
+    );
+
+    // Instantiate PyldCtxt to Chdr DUT
+    axis_pyld_ctxt_to_chdr #(
+      .CHDR_W               (CHDR_W),
+      .ITEM_W               (INST_PARAMS[inst_i].item_w),
+      .NIPC                 (INST_PARAMS[inst_i].nipc),
+      .SYNC_CLKS            (INST_PARAMS[inst_i].clk_period == CHDR_CLK_PERIOD),
+      .CONTEXT_FIFO_SIZE    (INST_PARAMS[inst_i].ctxt_fifo),
+      .PAYLOAD_FIFO_SIZE    (INST_PARAMS[inst_i].pyld_fifo),
+      .MTU                  (MTU),
+      .CONTEXT_PREFETCH_EN  (INST_PARAMS[inst_i].prefetch)
+    ) r2c_dut (
+      .axis_chdr_clk        (rfnoc_chdr_clk),
+      .axis_chdr_rst        (rfnoc_chdr_rst),
+      .axis_data_clk        (rfnoc_data_clk[inst_i]),
+      .axis_data_rst        (rfnoc_data_rst[inst_i]),
+      .m_axis_chdr_tdata    (chdr_tdata[inst_i]),
+      .m_axis_chdr_tlast    (chdr_tlast[inst_i]),
+      .m_axis_chdr_tvalid   (chdr_tvalid[inst_i]),
+      .m_axis_chdr_tready   (chdr_tready[inst_i]),
+      .s_axis_payload_tdata (r2c_pyld[inst_i].slave.tdata[(INST_PARAMS[inst_i].item_w*INST_PARAMS[inst_i].nipc)-1:0]),
+      .s_axis_payload_tkeep (r2c_pyld[inst_i].slave.tkeep[INST_PARAMS[inst_i].nipc-1:0]),
+      .s_axis_payload_tlast (r2c_pyld[inst_i].slave.tlast),
+      .s_axis_payload_tvalid(r2c_pyld[inst_i].slave.tvalid),
+      .s_axis_payload_tready(r2c_pyld[inst_i].slave.tready),
+      .s_axis_context_tdata (r2c_ctxt[inst_i].slave.tdata),
+      .s_axis_context_tuser (r2c_ctxt[inst_i].slave.tuser),
+      .s_axis_context_tlast (r2c_ctxt[inst_i].slave.tlast),
+      .s_axis_context_tvalid(r2c_ctxt[inst_i].slave.tvalid),
+      .s_axis_context_tready(r2c_ctxt[inst_i].slave.tready),
+      .framer_errors        (r2c_framer_errors[inst_i]),
+      .flush_en             (r2c_flush_en[inst_i]),
+      .flush_timeout        (r2c_flush_timeout[inst_i]),
+      .flush_active         (r2c_flush_active[inst_i]),
+      .flush_done           (r2c_flush_done[inst_i])
+    );
+
+    // Instantiate Chdr to PyldCtxt DUT
+    chdr_to_axis_pyld_ctxt #(
+      .CHDR_W               (CHDR_W),
+      .ITEM_W               (INST_PARAMS[inst_i].item_w),
+      .NIPC                 (INST_PARAMS[inst_i].nipc),
+      .SYNC_CLKS            (INST_PARAMS[inst_i].clk_period == CHDR_CLK_PERIOD),
+      .CONTEXT_FIFO_SIZE    (INST_PARAMS[inst_i].ctxt_fifo),
+      .PAYLOAD_FIFO_SIZE    (INST_PARAMS[inst_i].pyld_fifo),
+      .CONTEXT_PREFETCH_EN  (INST_PARAMS[inst_i].prefetch)
+    ) c2r_dut (
+      .axis_chdr_clk        (rfnoc_chdr_clk),
+      .axis_chdr_rst        (rfnoc_chdr_rst),
+      .axis_data_clk        (rfnoc_data_clk[inst_i]),
+      .axis_data_rst        (rfnoc_data_rst[inst_i]),
+      .s_axis_chdr_tdata    (chdr_tdata[inst_i]),
+      .s_axis_chdr_tlast    (chdr_tlast[inst_i]),
+      .s_axis_chdr_tvalid   (chdr_tvalid[inst_i]),
+      .s_axis_chdr_tready   (chdr_tready[inst_i]),
+      .m_axis_payload_tdata (c2r_pyld[inst_i].master.tdata[(INST_PARAMS[inst_i].item_w*INST_PARAMS[inst_i].nipc)-1:0]),
+      .m_axis_payload_tkeep (c2r_pyld[inst_i].master.tkeep[INST_PARAMS[inst_i].nipc-1:0]),
+      .m_axis_payload_tlast (c2r_pyld[inst_i].master.tlast),
+      .m_axis_payload_tvalid(c2r_pyld[inst_i].master.tvalid),
+      .m_axis_payload_tready(c2r_pyld[inst_i].master.tready),
+      .m_axis_context_tdata (c2r_ctxt[inst_i].master.tdata),
+      .m_axis_context_tuser (c2r_ctxt[inst_i].master.tuser),
+      .m_axis_context_tlast (c2r_ctxt[inst_i].master.tlast),
+      .m_axis_context_tvalid(c2r_ctxt[inst_i].master.tvalid),
+      .m_axis_context_tready(c2r_ctxt[inst_i].master.tready),
+      .flush_en             (c2r_flush_en[inst_i]),
+      .flush_timeout        (c2r_flush_timeout[inst_i]),
+      .flush_active         (c2r_flush_active[inst_i]),
+      .flush_done           (c2r_flush_done[inst_i])
+    );
+
+    // Assert Reset and start BFMs
+    initial begin
+      dclk_gen.reset();
+      r2c_flush_en[inst_i] = 0;
+      c2r_flush_en[inst_i] = 0;
+      pyld_bfm[inst_i] = new(r2c_pyld[inst_i], c2r_pyld[inst_i]);
+      pyld_bfm[inst_i].run();
+      ctxt_bfm[inst_i] = new(r2c_ctxt[inst_i], c2r_ctxt[inst_i]);
+      ctxt_bfm[inst_i].run();
+    end
+  end endgenerate
+
+  function automatic bit pyld_pkts_equal(
+    ref AxiStreamPacket #(MAX_PYLD_W) exp,
+    ref AxiStreamPacket #(MAX_PYLD_W) act,
+    input int item_w,
+    input int nipc
+  );
+    if (exp.data.size() != act.data.size()) return 0;
+    if (exp.keep.size() != act.keep.size()) return 0;
+    for (int i = 0; i < exp.data.size(); i++) begin
+      // Convert to bit
+      automatic bit [MAX_PYLD_W-1:0] mask     = '0;
+      automatic bit [MAX_PYLD_W-1:0] data_exp = exp.data[i];
+      automatic bit [MAX_PYLD_W-1:0] data_act = act.data[i];
+      for (int r = 0; r < nipc; r++) begin
+        if (exp.keep[i][r] === 1'b1) begin
+          automatic bit [MAX_PYLD_W-1:0] samp_mask = ((1<<item_w)-1);
+          mask |= (samp_mask << (r*item_w));
+        end
+      end
+      if (exp.keep[i] !== act.keep[i]) return 0;
+      if ((data_exp&mask) !== (data_act&mask)) return 0;
+    end
+    return 1;
+  endfunction
+
+  task automatic send_recv_data_packets(
+    input int inst,
+    input inst_params_t params, //We pass this separately to work around Vivado bug
+    input int num_pkts,
+    input int mst_stall_prob,
+    input int slv_stall_prob,
+    input bit flushing = 0
+  );
+    int nipc     = params.nipc;
+    int item_w   = params.item_w;
+    bit prefetch = params.prefetch;
+
+    AxiStreamPacket #(MAX_PYLD_W) pyld_pkt_arr[$] = {};
+    AxiStreamPacket #(CHDR_W, 4)  ctxt_pkt_arr[$] = {};
+
+    // Set stall probabilities
+    ctxt_bfm[inst].set_master_stall_prob(mst_stall_prob);
+    ctxt_bfm[inst].set_slave_stall_prob(slv_stall_prob);
+    pyld_bfm[inst].set_master_stall_prob(mst_stall_prob);
+    pyld_bfm[inst].set_slave_stall_prob(slv_stall_prob);
+
+    // Generate a stream of data packets
+    for (int p = 0; p < num_pkts; p++) begin
+      int len_lines = $urandom_range((MTU_BITS/(item_w*nipc))-10, 1);
+      int keep_int = $urandom_range(nipc, 1);
+      pyld_pkt_arr[p] = new();
+      for (int i = 0; i < len_lines; i++) begin
+        logic [MAX_PYLD_W-1:0] rand_samp;
+        logic [(MAX_PYLD_W/8)-1:0] keep_val = 'x;
+        for (int r = 0; r < (((nipc*item_w)+31)/32); r++)
+          rand_samp[r*32 +: 32] = $urandom();
+        pyld_pkt_arr[p].data.push_back(rand_samp);
+        pyld_pkt_arr[p].user.push_back('x);
+        for (int r = 0; r < nipc; r++) begin
+          if (i == len_lines-1)
+            keep_val[r] = (r < keep_int) ? 1'b1 : 1'b0;
+          else
+            keep_val[r] = 1'b1;
+        end
+        pyld_pkt_arr[p].keep.push_back(keep_val);
+      end
+    end
+
+    // Generate context packet for each data packet
+    foreach (pyld_pkt_arr[p]) begin
+      automatic chdr_header_t chdr_hdr;
+      automatic bit has_time = $urandom_range(1);
+      automatic int num_mdata = $urandom_range(5);
+      automatic int num_pyld_lines = pyld_pkt_arr[p].data.size();
+      automatic int invalid_samps = 0;
+      automatic int length;
+      for (int r = 0; r < nipc; r++)
+        if (pyld_pkt_arr[p].keep[num_pyld_lines-1][r] === 1'b0)
+          invalid_samps++;
+      length = 
+        (CHDR_W/8) +                                        // header
+        ((has_time && (CHDR_W == 64)) ? (CHDR_W/8) : 0) +   // timestamp
+        (num_mdata * (CHDR_W/8)) +                          // metadata
+        (num_pyld_lines * nipc * (item_w/8)) +              // payload
+        (-invalid_samps * (item_w/8));                      // payload (back out empty slots)
+
+      chdr_hdr = '{
+        vc        : $urandom_range(63),
+        eob       : $urandom_range(1),
+        eov       : $urandom_range(1),
+        pkt_type  : has_time ? CHDR_DATA_WITH_TS : CHDR_DATA_NO_TS,
+        num_mdata : num_mdata,
+        seq_num   : p,
+        length    : length,
+        dst_epid  : $urandom()
+      };
+
+      ctxt_pkt_arr[p] = new();
+      ctxt_pkt_arr[p].data.push_back(chdr_hdr);
+      ctxt_pkt_arr[p].user.push_back((has_time && (CHDR_W > 64)) ? CONTEXT_FIELD_HDR_TS : CONTEXT_FIELD_HDR);
+      ctxt_pkt_arr[p].keep.push_back('x);
+      if (has_time && (CHDR_W == 64)) begin
+        ctxt_pkt_arr[p].data.push_back(~p);
+        ctxt_pkt_arr[p].user.push_back(CONTEXT_FIELD_TS);
+        ctxt_pkt_arr[p].keep.push_back('x);
+      end
+      for (int i = 0; i < num_mdata; i++) begin
+        ctxt_pkt_arr[p].data.push_back(i);
+        ctxt_pkt_arr[p].user.push_back(CONTEXT_FIELD_MDATA);
+        ctxt_pkt_arr[p].keep.push_back('x);
+      end
+    end
+
+    // Spin up 4 threads: {RX, TX} x {Context, Payload}
+    fork
+      begin: tx_context
+        timeout_t timeout;
+        for (int p = 0; p < num_pkts; p++) begin
+          test.start_timeout(timeout, 50us, "Waiting to send TX context pkt");
+          ctxt_bfm[inst].put(ctxt_pkt_arr[p].copy());
+          test.end_timeout(timeout);
+          if (VERBOSE) $display("[INST%0d:TxContext:%0d]\n%s", inst, p, ctxt_pkt_arr[p].sprint());
+        end
+      end
+      begin: tx_payload
+        timeout_t timeout;
+        for (int p = 0; p < num_pkts; p++) begin
+          test.start_timeout(timeout, 50us, "Waiting to send TX payload pkt");
+          pyld_bfm[inst].put(pyld_pkt_arr[p].copy());
+          test.end_timeout(timeout);
+          if (VERBOSE) $display("[INST%0d:TxPayload:%0d]\n%s", inst, p, pyld_pkt_arr[p].sprint());
+        end
+      end
+      begin: rx_context
+        if (!flushing) begin
+          timeout_t timeout;
+          automatic AxiStreamPacket #(CHDR_W, 4) rx_ctxt_pkt;
+          for (int p = 0; p < num_pkts; p++) begin
+            test.start_timeout(timeout, 50us, "Waiting to recv RX context pkt");
+            ctxt_bfm[inst].get(rx_ctxt_pkt);
+            test.end_timeout(timeout);
+            if (VERBOSE) $display("[INST%0d:RxContext:%0d]\n%s", inst, p, rx_ctxt_pkt.sprint());
+            if (VERBOSE) $display("[INST%0d:ExpContext:%0d]\n%s", inst, p, ctxt_pkt_arr[p].sprint());
+            `ASSERT_ERROR(ctxt_pkt_arr[p].equal(rx_ctxt_pkt), "RX context packet did not match TX");
+          end
+        end
+      end
+      begin: rx_payload
+        if (!flushing) begin
+          timeout_t timeout;
+          automatic AxiStreamPacket #(MAX_PYLD_W) rx_pyld_pkt;
+          for (int p = 0; p < num_pkts; p++) begin
+            test.start_timeout(timeout, 50us, "Waiting to recv RX payload pkt");
+            pyld_bfm[inst].get(rx_pyld_pkt);
+            test.end_timeout(timeout);
+            if (VERBOSE) $display("[INST%0d:RxPayload:%0d]\n%s", inst, p, rx_pyld_pkt.sprint());
+            if (VERBOSE) $display("[INST%0d:ExpPayload:%0d]\n%s", inst, p, pyld_pkt_arr[p].sprint());
+            `ASSERT_ERROR(pyld_pkts_equal(pyld_pkt_arr[p], rx_pyld_pkt, item_w, nipc), "RX payload packet did not match TX");
+          end
+        end
+      end
+    join
+  endtask
+
+
+  // ----------------------------------------
+  // Test Process
+  // ----------------------------------------
+  initial begin
+
+    // Shared Variables
+    // ----------------------------------------
+    timeout_t    timeout;
+    string       tc_label;
+
+    // Initialize
+    // ----------------------------------------
+    test.start_tb("axis_pyld_ctxt_converter_tb");
+
+    // Reset
+    // ----------------------------------------
+    chdr_clk_gen_i.reset();
+
+    test.start_test("Wait for reset");
+    test.start_timeout(timeout, 1us, "Waiting for reset");
+    while (rfnoc_chdr_rst)  @(posedge rfnoc_chdr_clk);
+    while (|rfnoc_data_rst) @(posedge rfnoc_chdr_clk);
+    repeat (100) @(posedge rfnoc_chdr_clk);
+    test.end_timeout(timeout);
+    `ASSERT_ERROR(!rfnoc_chdr_rst && !(|rfnoc_data_rst), "Reset did not deassert");
+    test.end_test();
+
+    for (int inst_num = START_INST; inst_num <= STOP_INST; inst_num++) begin
+      $display("-----------------------------------------------------------------------------------------------");
+      $display("Testing INST%0d:%p", inst_num, INST_PARAMS[inst_num]);
+      $display("-----------------------------------------------------------------------------------------------");
+
+      // Stream Random Data
+      // ----------------------------------------
+      for (int cfg = 0; cfg < 4; cfg++) begin
+        automatic integer mst_cfg = cfg[0];
+        automatic integer slv_cfg = cfg[1];
+        $sformat(tc_label, "INST%0d: Stream Random Data (%s Mst, %s Slv)", 
+          inst_num,(mst_cfg?"Slow":"Fast"), (slv_cfg?"Slow":"Fast"));
+        test.start_test(tc_label);
+        send_recv_data_packets(inst_num, INST_PARAMS[inst_num], NUM_PKTS_PER_TEST,
+          mst_cfg ? SLOW_STALL_PROB : FAST_STALL_PROB,
+          slv_cfg ? SLOW_STALL_PROB : FAST_STALL_PROB
+        );
+        `ASSERT_ERROR(r2c_framer_errors[inst_num] === '0, "Encountered framer errors");
+        test.end_test();
+      end
+
+      // Flush
+      // ----------------------------------------
+      $sformat(tc_label, "INST%0d: Flush PyldCtxt => CHDR (Idle)", inst_num);
+      test.start_test(tc_label);
+      r2c_flush_timeout[inst_num] = $urandom_range(400, 200);
+      r2c_flush_en[inst_num] = 1'b1;
+      repeat (100) @(posedge rfnoc_chdr_clk);
+      `ASSERT_ERROR(r2c_flush_active[inst_num] === 1, "Flushing did not begin on time");
+      `ASSERT_ERROR(r2c_flush_done[inst_num] === 0, "Flushing ended prematurely");
+      repeat (r2c_flush_timeout[inst_num] + 1) @(posedge rfnoc_chdr_clk);
+      `ASSERT_ERROR(r2c_flush_done[inst_num] === 1, "Flushing did not end on time");
+      r2c_flush_en[inst_num] = 1'b0;
+      @(posedge rfnoc_chdr_clk);
+      test.end_test();
+
+      $sformat(tc_label, "INST%0d: Flush CHDR => PyldCtxt (Idle)", inst_num);
+      test.start_test(tc_label);
+      c2r_flush_timeout[inst_num] = $urandom_range(400, 200);
+      c2r_flush_en[inst_num] = 1'b1;
+      repeat (100) @(posedge rfnoc_data_clk[inst_num]);
+      `ASSERT_ERROR(c2r_flush_active[inst_num] === 1, "Flushing did not begin on time");
+      `ASSERT_ERROR(c2r_flush_done[inst_num] === 0, "Flushing ended prematurely");
+      repeat (c2r_flush_timeout[inst_num] + 1) @(posedge rfnoc_data_clk[inst_num]);
+      `ASSERT_ERROR(c2r_flush_done[inst_num] === 1, "Flushing did not end on time");
+      c2r_flush_en[inst_num] = 1'b0;
+      @(posedge rfnoc_data_clk[inst_num]);
+      test.end_test();
+
+      $sformat(tc_label, "INST%0d: Flush PyldCtxt => CHDR (Streaming)", inst_num);
+      test.start_test(tc_label);
+      r2c_flush_timeout[inst_num] = $urandom_range(400, 200);
+      r2c_flush_en[inst_num] = 1'b1;
+      repeat (100) @(posedge rfnoc_chdr_clk);
+      `ASSERT_ERROR(r2c_flush_active[inst_num] === 1, "Flushing did not begin on time");
+      `ASSERT_ERROR(r2c_flush_done[inst_num] === 0, "Flushing ended prematurely");
+      send_recv_data_packets(inst_num, INST_PARAMS[inst_num], NUM_PKTS_PER_TEST/10,
+        FAST_STALL_PROB, FAST_STALL_PROB, 1 /*flushing*/
+      );
+      repeat (NUM_PKTS_PER_TEST/10 * (1<<MTU) * 4) @(posedge rfnoc_chdr_clk);
+      repeat (r2c_flush_timeout[inst_num] + 1) @(posedge rfnoc_chdr_clk);
+      `ASSERT_ERROR(r2c_flush_done[inst_num] === 1, "Flushing did not end on time");
+      r2c_flush_en[inst_num] = 1'b0;
+      @(posedge rfnoc_chdr_clk);
+      test.end_test();
+
+      $sformat(tc_label, "INST%0d: Stream Data After Flush", inst_num);
+      test.start_test(tc_label);
+      send_recv_data_packets(inst_num, INST_PARAMS[inst_num], NUM_PKTS_PER_TEST/10,
+        FAST_STALL_PROB, FAST_STALL_PROB
+      );
+      `ASSERT_ERROR(r2c_framer_errors[inst_num] === '0, "Encountered framer errors");
+      test.end_test();
+    end
+
+    // Finish Up
+    // ----------------------------------------
+    // Display final statistics and results
+    test.end_tb();
+  end
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/sim/chdr_stream_endpoint_tb/Makefile b/fpga/usrp3/lib/rfnoc/sim/chdr_stream_endpoint_tb/Makefile
new file mode 100644
index 000000000..b2773db02
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/sim/chdr_stream_endpoint_tb/Makefile
@@ -0,0 +1,44 @@
+#
+# Copyright 2019 Ettus Research, A National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+#-------------------------------------------------
+# Top-of-Makefile
+#-------------------------------------------------
+# Define BASE_DIR to point to the "top" dir
+BASE_DIR = $(abspath ../../../../top)
+# Include viv_sim_preamble after defining BASE_DIR
+include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
+
+#-------------------------------------------------
+# Design Specific
+#-------------------------------------------------
+# Include makefiles and sources for the DUT and its dependencies
+include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs
+
+include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs
+include $(BASE_DIR)/../lib/rfnoc/crossbar/Makefile.srcs
+
+DESIGN_SRCS += $(abspath \
+$(RFNOC_CORE_SRCS) \
+$(RFNOC_XBAR_SRCS) \
+)
+
+#-------------------------------------------------
+# Testbench Specific
+#-------------------------------------------------
+SIM_TOP = chdr_stream_endpoint_tb
+
+SIM_SRCS = \
+$(abspath lossy_xport_model.v) \
+$(abspath chdr_stream_endpoint_tb.sv) \
+
+#-------------------------------------------------
+# Bottom-of-Makefile
+#-------------------------------------------------
+# Include all simulator specific makefiles here
+# Each should define a unique target to simulate
+# e.g. xsim, vsim, etc and a common "clean" target
+include $(BASE_DIR)/../tools/make/viv_simulator.mak
diff --git a/fpga/usrp3/lib/rfnoc/sim/chdr_stream_endpoint_tb/chdr_stream_endpoint_tb.sv b/fpga/usrp3/lib/rfnoc/sim/chdr_stream_endpoint_tb/chdr_stream_endpoint_tb.sv
new file mode 100644
index 000000000..0626ee447
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/sim/chdr_stream_endpoint_tb/chdr_stream_endpoint_tb.sv
@@ -0,0 +1,1149 @@
+//
+// Copyright 2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: chdr_stream_endpoint_tb
+//
+
+`default_nettype none
+
+
+module chdr_stream_endpoint_tb;
+
+  // ----------------------------------------
+  // Global settings
+  // ----------------------------------------
+  
+  // Include macros and time declarations for use with PkgTestExec
+  `include "test_exec.svh"
+
+  import PkgTestExec::*;
+  import PkgChdrUtils::*;
+  import PkgChdrBfm::*;
+
+  // Clocks and resets
+  bit rfnoc_chdr_clk, rfnoc_chdr_rst;
+  bit rfnoc_ctrl_clk, rfnoc_ctrl_rst;
+  sim_clock_gen #(6.0)  rfnoc_chdr_clk_gen (rfnoc_chdr_clk, rfnoc_chdr_rst); // 166.6 MHz
+  sim_clock_gen #(20.0) rfnoc_ctrl_clk_gen (rfnoc_ctrl_clk, rfnoc_ctrl_rst); // 50 MHz
+
+  // Parameters
+  localparam bit    VERBOSE           = 0;
+  localparam int    NUM_PKTS_PER_TEST = 200;
+  localparam int    FAST_STALL_PROB   = 0;
+  localparam int    SLOW_STALL_PROB   = 35;
+
+  localparam int    CHDR_W   = 64;
+  localparam int    MTU      = 7;
+  localparam [15:0] PROTOVER = {8'd1, 8'd0};
+  localparam [15:0] DEV_ID   = 16'hBEEF;
+  localparam [15:0] EPID_TB  = 16'h1001;
+  localparam [15:0] EPID_A   = 16'h1002;
+  localparam [15:0] EPID_B   = 16'h1003;
+  localparam [9:0]  PORT_TB  = 10'd0;
+  localparam [9:0]  PORT_A   = 10'd1;
+  localparam [9:0]  PORT_B   = 10'd2;
+
+  // ----------------------------------------
+  // DUT (and Crossbar) Instantiations
+  // ----------------------------------------
+  wire [CHDR_W-1:0] c2ae_chdr_tdata , c2ax_chdr_tdata , a2c_chdr_tdata ;
+  wire              c2ae_chdr_tlast , c2ax_chdr_tlast , a2c_chdr_tlast ;
+  wire              c2ae_chdr_tvalid, c2ax_chdr_tvalid, a2c_chdr_tvalid;
+  wire              c2ae_chdr_tready, c2ax_chdr_tready, a2c_chdr_tready;
+  wire [CHDR_W-1:0] c2be_chdr_tdata , c2bx_chdr_tdata , b2c_chdr_tdata ;
+  wire              c2be_chdr_tlast , c2bx_chdr_tlast , b2c_chdr_tlast ;
+  wire              c2be_chdr_tvalid, c2bx_chdr_tvalid, b2c_chdr_tvalid;
+  wire              c2be_chdr_tready, c2bx_chdr_tready, b2c_chdr_tready;
+
+  wire [31:0] a_ctrl_in_tdata, a_ctrl_out_tdata, b_ctrl_in_tdata, b_ctrl_out_tdata;
+  wire        a_ctrl_loop_tlast , b_ctrl_loop_tlast ;
+  wire        a_ctrl_loop_tvalid, b_ctrl_loop_tvalid;
+  wire        a_ctrl_loop_tready, b_ctrl_loop_tready;
+
+  logic       a_signal_data_err, b_signal_data_err;
+  logic       a_lossy_input, b_lossy_input;
+  logic [7:0] a_seqerr_prob, b_seqerr_prob;
+  logic [7:0] a_rterr_prob, b_rterr_prob;
+
+  AxiStreamIf #(CHDR_W) m_tb_chdr (rfnoc_chdr_clk, rfnoc_chdr_rst);
+  AxiStreamIf #(CHDR_W) s_tb_chdr (rfnoc_chdr_clk, rfnoc_chdr_rst);
+
+  AxiStreamIf #(CHDR_W) m_a0_data (rfnoc_chdr_clk, rfnoc_chdr_rst);
+  AxiStreamIf #(CHDR_W) s_a0_data (rfnoc_chdr_clk, rfnoc_chdr_rst);
+  AxiStreamIf #(CHDR_W) m_a1_data (rfnoc_chdr_clk, rfnoc_chdr_rst);
+  AxiStreamIf #(CHDR_W) s_a1_data (rfnoc_chdr_clk, rfnoc_chdr_rst);
+  AxiStreamIf #(CHDR_W) m_b0_data (rfnoc_chdr_clk, rfnoc_chdr_rst);
+  AxiStreamIf #(CHDR_W) s_b0_data (rfnoc_chdr_clk, rfnoc_chdr_rst);
+  AxiStreamIf #(CHDR_W) m_b1_data (rfnoc_chdr_clk, rfnoc_chdr_rst);
+  AxiStreamIf #(CHDR_W) s_b1_data (rfnoc_chdr_clk, rfnoc_chdr_rst);
+
+  chdr_stream_endpoint #(
+    .PROTOVER           (PROTOVER),
+    .CHDR_W             (CHDR_W),
+    .AXIS_CTRL_EN       (1),
+    .AXIS_DATA_EN       (1),
+    .INST_NUM           (0),
+    .NUM_DATA_I         (2),
+    .NUM_DATA_O         (2),
+    .CTRL_XBAR_PORT     (PORT_A),
+    .INGRESS_BUFF_SIZE  (MTU+1),
+    .MTU                (MTU),
+    .REPORT_STRM_ERRS   (1),
+    .SIM_SPEEDUP        (1)
+  ) sep_a (
+    .rfnoc_chdr_clk     (rfnoc_chdr_clk                                    ),
+    .rfnoc_chdr_rst     (rfnoc_chdr_rst                                    ),
+    .rfnoc_ctrl_clk     (rfnoc_ctrl_clk                                    ),
+    .rfnoc_ctrl_rst     (rfnoc_ctrl_rst                                    ),
+    .device_id          (DEV_ID                                            ),
+    .s_axis_chdr_tdata  (c2ae_chdr_tdata                                   ),
+    .s_axis_chdr_tlast  (c2ae_chdr_tlast                                   ),
+    .s_axis_chdr_tvalid (c2ae_chdr_tvalid                                  ),
+    .s_axis_chdr_tready (c2ae_chdr_tready                                  ),
+    .m_axis_chdr_tdata  (a2c_chdr_tdata                                    ),
+    .m_axis_chdr_tlast  (a2c_chdr_tlast                                    ),
+    .m_axis_chdr_tvalid (a2c_chdr_tvalid                                   ),
+    .m_axis_chdr_tready (a2c_chdr_tready                                   ),
+    .s_axis_data_tdata  ({m_a1_data.slave.tdata  , m_a0_data.slave.tdata  }),
+    .s_axis_data_tlast  ({m_a1_data.slave.tlast  , m_a0_data.slave.tlast  }),
+    .s_axis_data_tvalid ({m_a1_data.slave.tvalid , m_a0_data.slave.tvalid }),
+    .s_axis_data_tready ({m_a1_data.slave.tready , m_a0_data.slave.tready }),
+    .m_axis_data_tdata  ({s_a1_data.master.tdata , s_a0_data.master.tdata }),
+    .m_axis_data_tlast  ({s_a1_data.master.tlast , s_a0_data.master.tlast }),
+    .m_axis_data_tvalid ({s_a1_data.master.tvalid, s_a0_data.master.tvalid}),
+    .m_axis_data_tready ({s_a1_data.master.tready, s_a0_data.master.tready}),
+    .s_axis_ctrl_tdata  (a_ctrl_out_tdata                                  ),
+    .s_axis_ctrl_tlast  (a_ctrl_loop_tlast                                 ),
+    .s_axis_ctrl_tvalid (a_ctrl_loop_tvalid                                ),
+    .s_axis_ctrl_tready (a_ctrl_loop_tready                                ),
+    .m_axis_ctrl_tdata  (a_ctrl_in_tdata                                   ),
+    .m_axis_ctrl_tlast  (a_ctrl_loop_tlast                                 ),
+    .m_axis_ctrl_tvalid (a_ctrl_loop_tvalid                                ),
+    .m_axis_ctrl_tready (a_ctrl_loop_tready                                ),
+    .strm_seq_err_stb   (                                                  ),
+    .strm_data_err_stb  (                                                  ),
+    .strm_route_err_stb (                                                  ),
+    .signal_data_err    (a_signal_data_err                                 )
+  );
+
+  chdr_stream_endpoint #(
+    .PROTOVER           (PROTOVER),
+    .CHDR_W             (CHDR_W),
+    .AXIS_CTRL_EN       (1),
+    .AXIS_DATA_EN       (1),
+    .INST_NUM           (1),
+    .NUM_DATA_I         (2),
+    .NUM_DATA_O         (2),
+    .CTRL_XBAR_PORT     (PORT_B),
+    .INGRESS_BUFF_SIZE  (MTU+1),
+    .MTU                (MTU),
+    .REPORT_STRM_ERRS   (1),
+    .SIM_SPEEDUP        (1)
+  ) sep_b (
+    .rfnoc_chdr_clk     (rfnoc_chdr_clk                                    ),
+    .rfnoc_chdr_rst     (rfnoc_chdr_rst                                    ),
+    .rfnoc_ctrl_clk     (rfnoc_ctrl_clk                                    ),
+    .rfnoc_ctrl_rst     (rfnoc_ctrl_rst                                    ),
+    .device_id          (DEV_ID                                            ),
+    .s_axis_chdr_tdata  (c2be_chdr_tdata                                   ),
+    .s_axis_chdr_tlast  (c2be_chdr_tlast                                   ),
+    .s_axis_chdr_tvalid (c2be_chdr_tvalid                                  ),
+    .s_axis_chdr_tready (c2be_chdr_tready                                  ),
+    .m_axis_chdr_tdata  (b2c_chdr_tdata                                    ),
+    .m_axis_chdr_tlast  (b2c_chdr_tlast                                    ),
+    .m_axis_chdr_tvalid (b2c_chdr_tvalid                                   ),
+    .m_axis_chdr_tready (b2c_chdr_tready                                   ),
+    .s_axis_data_tdata  ({m_b1_data.slave.tdata  , m_b0_data.slave.tdata  }),
+    .s_axis_data_tlast  ({m_b1_data.slave.tlast  , m_b0_data.slave.tlast  }),
+    .s_axis_data_tvalid ({m_b1_data.slave.tvalid , m_b0_data.slave.tvalid }),
+    .s_axis_data_tready ({m_b1_data.slave.tready , m_b0_data.slave.tready }),
+    .m_axis_data_tdata  ({s_b1_data.master.tdata , s_b0_data.master.tdata }),
+    .m_axis_data_tlast  ({s_b1_data.master.tlast , s_b0_data.master.tlast }),
+    .m_axis_data_tvalid ({s_b1_data.master.tvalid, s_b0_data.master.tvalid}),
+    .m_axis_data_tready ({s_b1_data.master.tready, s_b0_data.master.tready}),
+    .s_axis_ctrl_tdata  (b_ctrl_out_tdata                                  ),
+    .s_axis_ctrl_tlast  (b_ctrl_loop_tlast                                 ),
+    .s_axis_ctrl_tvalid (b_ctrl_loop_tvalid                                ),
+    .s_axis_ctrl_tready (b_ctrl_loop_tready                                ),
+    .m_axis_ctrl_tdata  (b_ctrl_in_tdata                                   ),
+    .m_axis_ctrl_tlast  (b_ctrl_loop_tlast                                 ),
+    .m_axis_ctrl_tvalid (b_ctrl_loop_tvalid                                ),
+    .m_axis_ctrl_tready (b_ctrl_loop_tready                                ),
+    .strm_seq_err_stb   (                                                  ),
+    .strm_data_err_stb  (                                                  ),
+    .strm_route_err_stb (                                                  ),
+    .signal_data_err    (b_signal_data_err                                 )
+  );
+
+  chdr_crossbar_nxn #(
+    .CHDR_W         (CHDR_W),
+    .NPORTS         (3),
+    .DEFAULT_PORT   (0),
+    .MTU            (MTU),
+    .ROUTE_TBL_SIZE (6),
+    .MUX_ALLOC      ("ROUND-ROBIN"),
+    .OPTIMIZE       ("AREA"),
+    .NPORTS_MGMT    (1),
+    .EXT_RTCFG_PORT (0),
+    .PROTOVER       (PROTOVER)
+  ) xbar_c (
+    .clk            (rfnoc_chdr_clk),
+    .reset          (rfnoc_chdr_rst),
+    .device_id      (DEV_ID),
+    .s_axis_tdata   ({b2c_chdr_tdata,   a2c_chdr_tdata,   m_tb_chdr.slave.tdata  }),
+    .s_axis_tlast   ({b2c_chdr_tlast,   a2c_chdr_tlast,   m_tb_chdr.slave.tlast  }),
+    .s_axis_tvalid  ({b2c_chdr_tvalid,  a2c_chdr_tvalid,  m_tb_chdr.slave.tvalid }),
+    .s_axis_tready  ({b2c_chdr_tready,  a2c_chdr_tready,  m_tb_chdr.slave.tready }),
+    .m_axis_tdata   ({c2bx_chdr_tdata,  c2ax_chdr_tdata,  s_tb_chdr.master.tdata }),
+    .m_axis_tlast   ({c2bx_chdr_tlast,  c2ax_chdr_tlast,  s_tb_chdr.master.tlast }),
+    .m_axis_tvalid  ({c2bx_chdr_tvalid, c2ax_chdr_tvalid, s_tb_chdr.master.tvalid}),
+    .m_axis_tready  ({c2bx_chdr_tready, c2ax_chdr_tready, s_tb_chdr.master.tready}),
+    .ext_rtcfg_stb  ('0),
+    .ext_rtcfg_addr ('0),
+    .ext_rtcfg_data ('0),
+    .ext_rtcfg_ack  ()
+  );
+
+  lossy_xport_model #( .CHDR_W(CHDR_W) ) xport_a (
+    .clk           (rfnoc_chdr_clk  ),
+    .rst           (rfnoc_chdr_rst  ),
+    .s_axis_tdata  (c2ax_chdr_tdata ),
+    .s_axis_tlast  (c2ax_chdr_tlast ),
+    .s_axis_tvalid (c2ax_chdr_tvalid),
+    .s_axis_tready (c2ax_chdr_tready),
+    .m_axis_tdata  (c2ae_chdr_tdata ),
+    .m_axis_tlast  (c2ae_chdr_tlast ),
+    .m_axis_tvalid (c2ae_chdr_tvalid),
+    .m_axis_tready (c2ae_chdr_tready),
+    .seqerr_prob   (a_seqerr_prob   ),
+    .rterr_prob    (a_rterr_prob    ),
+    .lossy         (a_lossy_input   )
+  );
+
+  lossy_xport_model #( .CHDR_W(CHDR_W) ) xport_b (
+    .clk           (rfnoc_chdr_clk  ),
+    .rst           (rfnoc_chdr_rst  ),
+    .s_axis_tdata  (c2bx_chdr_tdata ),
+    .s_axis_tlast  (c2bx_chdr_tlast ),
+    .s_axis_tvalid (c2bx_chdr_tvalid),
+    .s_axis_tready (c2bx_chdr_tready),
+    .m_axis_tdata  (c2be_chdr_tdata ),
+    .m_axis_tlast  (c2be_chdr_tlast ),
+    .m_axis_tvalid (c2be_chdr_tvalid),
+    .m_axis_tready (c2be_chdr_tready),
+    .seqerr_prob   (b_seqerr_prob   ),
+    .rterr_prob    (b_rterr_prob    ),
+    .lossy         (b_lossy_input   )
+  );
+
+  // ----------------------------------------
+  // BFMs and Test Models
+  // ----------------------------------------
+
+  ChdrBfm #(CHDR_W) a0_data_bfm = new(m_a0_data, s_a0_data);
+  ChdrBfm #(CHDR_W) b0_data_bfm = new(m_b0_data, s_b0_data);
+  ChdrBfm #(CHDR_W) a1_data_bfm = new(m_a1_data, s_a1_data);
+  ChdrBfm #(CHDR_W) b1_data_bfm = new(m_b1_data, s_b1_data);
+  ChdrBfm #(CHDR_W) tb_chdr_bfm = new(m_tb_chdr, s_tb_chdr);
+
+  // Simple responders for AXIS-Ctrl transactions
+  reg a_first = 1'b1, b_first = 1'b1;
+  always @(posedge rfnoc_ctrl_clk) begin
+    if (rfnoc_ctrl_rst) begin
+      a_first <= 1'd1;
+      b_first <= 1'd1;
+    end else begin
+      if (a_ctrl_loop_tvalid & a_ctrl_loop_tready)
+        a_first <= a_ctrl_loop_tlast;
+      if (b_ctrl_loop_tvalid & b_ctrl_loop_tready)
+        b_first <= b_ctrl_loop_tlast;
+    end
+  end
+  // Respond with an ACK and the source and destination ports swapped
+  assign a_ctrl_out_tdata = 
+    a_first ? {1'b1, a_ctrl_in_tdata[30:20], a_ctrl_in_tdata[9:0], a_ctrl_in_tdata[19:10]} : a_ctrl_in_tdata;
+  assign b_ctrl_out_tdata = 
+    b_first ? {1'b1, b_ctrl_in_tdata[30:20], b_ctrl_in_tdata[9:0], b_ctrl_in_tdata[19:10]} : b_ctrl_in_tdata;
+
+  // ----------------------------------------
+  // Test Utilities
+  // ----------------------------------------
+  integer cached_mgmt_seqnum = 0;
+  integer cached_ctrl_seqnum = 0;
+  integer cached_data_seqnum = 0;
+
+  task automatic send_recv_mgmt_packet(
+    input  chdr_header_t tx_mgmt_hdr,
+    input  chdr_mgmt_t   tx_mgmt_pl,
+    output chdr_header_t rx_mgmt_hdr,
+    output chdr_mgmt_t   rx_mgmt_pl
+  );
+    automatic timeout_t mgmt_timeout;
+    automatic ChdrPacket #(CHDR_W) tx_chdr = new(), rx_chdr;
+    tx_chdr.write_mgmt(tx_mgmt_hdr, tx_mgmt_pl);
+    test.start_timeout(mgmt_timeout, 2us, "Waiting for management transaction");
+    if (VERBOSE) begin $write("Tx"); tx_chdr.print(); end
+    tb_chdr_bfm.put_chdr(tx_chdr.copy());
+    tb_chdr_bfm.get_chdr(rx_chdr);
+    test.end_timeout(mgmt_timeout);
+    rx_chdr.read_mgmt(rx_mgmt_hdr, rx_mgmt_pl);
+    if (VERBOSE) begin $write("Rx"); rx_chdr.print(); end
+  endtask
+
+  task automatic mgmt_read_err_counts(
+    input [15:0] dst_epid,
+    output [31:0] seq_err_count,
+    output [31:0] route_err_count,
+    output [31:0] data_err_count
+  );
+    automatic chdr_header_t tx_mgmt_hdr, rx_mgmt_hdr;
+    automatic chdr_mgmt_t tx_mgmt_pl, rx_mgmt_pl;
+    automatic chdr_mgmt_op_t exp_mgmt_op;
+
+    // Generic management header
+    tx_mgmt_pl.header = '{
+      default:'0, prot_ver:PROTOVER, chdr_width:translate_chdr_w(CHDR_W), src_epid:EPID_TB
+    };
+    // Read error counts
+    tx_mgmt_pl.header.num_hops = 3;
+    tx_mgmt_pl.ops.delete();
+
+    tx_mgmt_pl.ops[0] = '{  // Hop 1: Crossbar: Nop
+      op_payload:48'h0, op_code:MGMT_OP_NOP, ops_pending:8'd0};
+    tx_mgmt_pl.ops[1] = '{  // Hop 2: Read status
+      op_payload:{32'h0, sep_a.REG_OSTRM_SEQ_ERR_CNT}, op_code:MGMT_OP_CFG_RD_REQ, ops_pending:8'd3};
+    tx_mgmt_pl.ops[2] = '{  // Hop 2: Read status
+      op_payload:{32'h0, sep_a.REG_OSTRM_DATA_ERR_CNT}, op_code:MGMT_OP_CFG_RD_REQ, ops_pending:8'd2};
+    tx_mgmt_pl.ops[3] = '{  // Hop 2: Read status
+      op_payload:{32'h0, sep_a.REG_OSTRM_ROUTE_ERR_CNT}, op_code:MGMT_OP_CFG_RD_REQ, ops_pending:8'd1};
+    tx_mgmt_pl.ops[4] = '{  // Hop 2: Stream Endpoint: Return 
+      op_payload:48'h0, op_code:MGMT_OP_RETURN, ops_pending:8'd0};
+    tx_mgmt_pl.ops[5] = '{  // Hop 3: Nop for return
+      op_payload:48'h0, op_code:MGMT_OP_NOP, ops_pending:8'd0};
+    tx_mgmt_hdr = '{
+      pkt_type:CHDR_MANAGEMENT, seq_num:cached_mgmt_seqnum++, dst_epid:dst_epid, default:'0};
+
+    // Send the packet and ensure that error counts are zero
+    send_recv_mgmt_packet(tx_mgmt_hdr, tx_mgmt_pl, rx_mgmt_hdr, rx_mgmt_pl);
+    `ASSERT_ERROR(rx_mgmt_pl.header.num_hops == 1,
+      "Check Errs: Mgmt header was incorrect");
+    seq_err_count = 32'hx;
+    route_err_count = 32'hx;
+    data_err_count = 32'hx;
+    for (int i = 1; i <= 3; i++) begin
+      if (rx_mgmt_pl.ops[i].op_payload[15:0] == sep_a.REG_OSTRM_SEQ_ERR_CNT)
+        seq_err_count = rx_mgmt_pl.ops[i].op_payload[47:16];
+      else if (rx_mgmt_pl.ops[i].op_payload[15:0] == sep_a.REG_OSTRM_DATA_ERR_CNT)
+        data_err_count = rx_mgmt_pl.ops[i].op_payload[47:16];
+      else if (rx_mgmt_pl.ops[i].op_payload[15:0] == sep_a.REG_OSTRM_ROUTE_ERR_CNT)
+        route_err_count = rx_mgmt_pl.ops[i].op_payload[47:16];
+    end
+  endtask
+
+  task automatic send_recv_ctrl_packets(
+    input [15:0] dst_epid,
+    input [15:0] num_pkts,
+    input [15:0] seq_num_start
+  );
+    for (int n = 0; n < num_pkts; n=n+1) begin
+      automatic timeout_t ctrl_timeout;
+      automatic ChdrPacket #(CHDR_W) tx_chdr = new(), rx_chdr, exp_chdr = new();
+      automatic chdr_header_t chdr_hdr;
+      automatic chdr_ctrl_header_t ctrl_hdr, exp_ctrl_hdr;
+      automatic ctrl_op_word_t ctrl_op;
+      automatic ctrl_word_t ctrl_data[$];
+      automatic chdr_word_t ctrl_ts;
+  
+      ctrl_data.delete();
+      for (int i = 0; i < $urandom_range(15,1); i++)
+        ctrl_data[i] = $urandom();
+      ctrl_hdr = '{
+        default  : '0,
+        src_epid : EPID_TB,
+        is_ack   : 1'b0,
+        has_time : $urandom_range(1),
+        seq_num  : seq_num_start[5:0],
+        num_data : ctrl_data.size(),
+        src_port : $urandom(),
+        dst_port : $urandom()
+      };
+      ctrl_ts = $urandom();
+      ctrl_op = '{
+        default      : '0,
+        op_code      : ctrl_opcode_t'($urandom_range(9)),
+        byte_enable  : $urandom_range(15),
+        address      : $urandom()
+      };
+      chdr_hdr = '{
+        dst_epid  : dst_epid,
+        seq_num   : seq_num_start + n[15:0],
+        pkt_type  : CHDR_CONTROL,
+        default   : 0
+      };
+      tx_chdr.write_ctrl(chdr_hdr, ctrl_hdr, ctrl_op, ctrl_data, ctrl_ts);
+
+      test.start_timeout(ctrl_timeout, 2us, "Waiting for management transaction");
+      if (VERBOSE) begin $write("Tx"); tx_chdr.print(); end
+      tb_chdr_bfm.put_chdr(tx_chdr.copy());
+      tb_chdr_bfm.get_chdr(rx_chdr);
+      test.end_timeout(ctrl_timeout);
+      if (VERBOSE) begin $write("Rx"); rx_chdr.print(); end
+
+      exp_ctrl_hdr = ctrl_hdr;
+      exp_ctrl_hdr.dst_port = ctrl_hdr.src_port;
+      exp_ctrl_hdr.src_port = ctrl_hdr.dst_port;
+      exp_ctrl_hdr.src_epid = dst_epid;
+      exp_ctrl_hdr.is_ack = 1'b1;
+
+      exp_chdr.write_ctrl(chdr_hdr, exp_ctrl_hdr, ctrl_op, ctrl_data, ctrl_ts);
+      exp_chdr.header.dst_epid = EPID_TB;
+
+
+      if (VERBOSE) begin $write("ExpRx"); exp_chdr.print(); end
+
+      // Validate contents
+      `ASSERT_ERROR(exp_chdr.equal(rx_chdr),
+        "Received CHDR control packet was incorrect");
+    end
+  endtask
+
+  task automatic send_recv_data_packets(
+    input [15:0] src_epid,
+    input [15:0] dst_epid,
+    input [15:0] num_pkts,
+    input [15:0] seq_num_start,
+    input bit    ignore_seq_route_errs = 0
+  );
+    // Pick a VC for this run randomly
+    logic [5:0] vc = $urandom_range(1);
+    fork
+      begin: tx_loop
+        for (int txi = 0; txi < num_pkts; txi=txi+1) begin
+          automatic timeout_t tx_timeout;
+          automatic ChdrPacket #(CHDR_W) tx_chdr = new();
+          automatic chdr_header_t tx_hdr;
+          automatic chdr_word_t tx_ts;
+          automatic chdr_word_t tx_mdata[$];
+          automatic chdr_word_t tx_data[$];
+          // Fill data in the packet
+          tx_hdr = '{
+            vc        : vc,
+            dst_epid  : dst_epid,
+            seq_num   : seq_num_start + txi[15:0],
+            pkt_type  : (txi%4==0) ? CHDR_DATA_WITH_TS : CHDR_DATA_NO_TS,
+            num_mdata : $urandom_range(5),
+            default   : 0
+          };
+          tx_ts = txi;
+          tx_mdata.delete();
+          for (int i = 0; i < tx_hdr.num_mdata; i++)
+            tx_mdata[i] = $urandom();
+          tx_data.delete();
+          for (int i = 0; i < $urandom_range((1<<MTU)-10); i++)
+            tx_data[i] = {txi << 16, i[15:0]};
+          tx_chdr.write_raw(tx_hdr, tx_data, tx_mdata, tx_ts);
+          if (VERBOSE) $display("%s%0d:Tx:%0d:",(src_epid == EPID_A)?"A":"B", vc, txi, tx_chdr.sprint());
+          // Send the packet
+          test.start_timeout(tx_timeout, 2us, "Waiting to send data packet");
+          if (src_epid == EPID_A)
+            if (vc == 0)
+              a0_data_bfm.put_chdr(tx_chdr.copy());
+            else
+              a1_data_bfm.put_chdr(tx_chdr.copy());
+          else
+            if (vc == 0)
+              b0_data_bfm.put_chdr(tx_chdr.copy());
+            else
+              b1_data_bfm.put_chdr(tx_chdr.copy());
+          test.end_timeout(tx_timeout);
+        end
+      end
+      begin: rx_loop
+        for (int rxi = 0; rxi < num_pkts; rxi=rxi+1) begin
+          automatic timeout_t rx_timeout;
+          automatic ChdrPacket #(CHDR_W) rx_chdr;
+          // Receive a packet
+          test.start_timeout(rx_timeout, 2us, "Waiting to recv data packet");
+          if (dst_epid == EPID_A)
+            if (vc == 0)
+              a0_data_bfm.get_chdr(rx_chdr);
+            else
+              a1_data_bfm.get_chdr(rx_chdr);
+          else
+            if (vc == 0)
+              b0_data_bfm.get_chdr(rx_chdr);
+            else
+              b1_data_bfm.get_chdr(rx_chdr);
+          test.end_timeout(rx_timeout);
+          // Validate the packet
+          if (VERBOSE) $display("%s:Rx%0d:%0d:",(src_epid == EPID_A)?"A":"B", vc, rxi, rx_chdr.sprint());
+          `ASSERT_ERROR(ignore_seq_route_errs || rx_chdr.header.dst_epid == dst_epid, "Data Pkt: dst_epid was incorrect");
+          `ASSERT_ERROR(ignore_seq_route_errs || (rx_chdr.header.seq_num  == rxi + seq_num_start), "Data Pkt: seq_num was incorrect");
+          if (rx_chdr.header.pkt_type == CHDR_DATA_WITH_TS)
+            `ASSERT_ERROR(rx_chdr.timestamp  == rxi, "Data Pkt: timestamp was incorrect");
+          foreach (rx_chdr.data[i]) begin
+            `ASSERT_ERROR(rx_chdr.data[i] == {rxi << 16, i[15:0]}, "Data Pkt: payload was incorrect");
+          end
+        end
+      end
+    join
+  endtask
+
+  task automatic set_unidir_stall_prob(
+    input [15:0] src_epid,
+    input [15:0] dst_epid,
+    int          src_stall_prob,
+    int          dst_stall_prob
+  );
+    if (src_epid == EPID_A) begin
+      a0_data_bfm.set_master_stall_prob(src_stall_prob);
+      a1_data_bfm.set_master_stall_prob(src_stall_prob);
+      b0_data_bfm.set_slave_stall_prob (dst_stall_prob);
+      b1_data_bfm.set_slave_stall_prob (dst_stall_prob);
+    end else begin
+      b0_data_bfm.set_master_stall_prob(src_stall_prob);
+      b1_data_bfm.set_master_stall_prob(src_stall_prob);
+      a0_data_bfm.set_slave_stall_prob (dst_stall_prob);
+      a1_data_bfm.set_slave_stall_prob (dst_stall_prob);
+    end
+  endtask
+
+  task automatic set_bidir_stall_prob(
+    int src_stall_prob,
+    int dst_stall_prob
+  );
+    set_unidir_stall_prob(EPID_A, EPID_B, src_stall_prob, dst_stall_prob);
+    set_unidir_stall_prob(EPID_B, EPID_A, src_stall_prob, dst_stall_prob);
+  endtask
+
+  // ----------------------------------------
+  // Test Process
+  // ----------------------------------------
+  initial begin
+
+    // Shared Variables
+    // ----------------------------------------
+    timeout_t    timeout;
+    string       tc_label;
+    bit          stop_responder = 0;
+    logic [31:0] seq_err_count;
+    logic [31:0] route_err_count;
+    logic [31:0] data_err_count;
+
+    a_signal_data_err = 0;
+    b_signal_data_err = 0;
+    a_seqerr_prob     = 0;
+    a_rterr_prob      = 0;
+    a_lossy_input     = 0;
+    b_seqerr_prob     = 0;
+    b_rterr_prob      = 0;
+    b_lossy_input     = 0;
+
+    // Initialize
+    // ----------------------------------------
+    test.start_tb("chdr_stream_endpoint_tb");
+
+    // Start the BFMs
+    a0_data_bfm.run();
+    b0_data_bfm.run();
+    a1_data_bfm.run();
+    b1_data_bfm.run();
+    tb_chdr_bfm.run();
+
+    tb_chdr_bfm.set_master_stall_prob(0);
+    tb_chdr_bfm.set_slave_stall_prob(0);
+
+    // Reset
+    // ----------------------------------------
+    rfnoc_ctrl_clk_gen.reset();
+    rfnoc_chdr_clk_gen.reset();
+
+    test.start_test("Wait for reset");
+    test.start_timeout(timeout, 1us, "Waiting for reset");
+    while (rfnoc_ctrl_rst) @(posedge rfnoc_ctrl_clk);
+    while (rfnoc_chdr_rst) @(posedge rfnoc_chdr_clk);
+    test.end_timeout(timeout);
+    `ASSERT_ERROR(!rfnoc_chdr_rst && !rfnoc_ctrl_rst, "Reset did not deassert");
+    test.end_test();
+
+    // Discover Topology
+    // ----------------------------------------
+    test.start_test("Discover Topology");
+    begin
+      automatic chdr_header_t tx_mgmt_hdr, rx_mgmt_hdr;
+      automatic chdr_mgmt_t tx_mgmt_pl, rx_mgmt_pl;
+      automatic chdr_mgmt_op_t exp_mgmt_op;
+
+      // *Status* We know nothing about the network. Need to discover stuff.
+
+      // Generic management header
+      tx_mgmt_pl.header = '{
+        default:'0, prot_ver:PROTOVER, chdr_width:translate_chdr_w(CHDR_W), src_epid:EPID_TB
+      };
+      // Send a node info request to the crossbar
+      tx_mgmt_pl.header.num_hops = 2;
+      tx_mgmt_pl.ops.delete();
+      tx_mgmt_pl.ops[0] = '{  // Hop 1: Send node info 
+        op_payload:48'h0, op_code:MGMT_OP_INFO_REQ, ops_pending:8'd1};
+      tx_mgmt_pl.ops[1] = '{  // Hop 1: Return 
+        op_payload:48'h0, op_code:MGMT_OP_RETURN, ops_pending:8'd0};
+      tx_mgmt_pl.ops[2] = '{  // Hop 2: Nop for return
+        op_payload:48'h0, op_code:MGMT_OP_NOP, ops_pending:8'd0};
+      tx_mgmt_hdr = '{
+        pkt_type:CHDR_MANAGEMENT, seq_num:cached_mgmt_seqnum++, dst_epid:16'h0, default:'0};
+
+      // Send the packet and check the response
+      send_recv_mgmt_packet(tx_mgmt_hdr, tx_mgmt_pl, rx_mgmt_hdr, rx_mgmt_pl);
+      `ASSERT_ERROR(rx_mgmt_pl.header.num_hops == 1,
+        "Discover XB: Mgmt header was incorrect");
+      exp_mgmt_op = '{op_payload:{2'h0, 8'd1/*ports_mgmt*/, 8'd3 /*ports*/, 10'd0 /*inst*/, 4'd1 /*type*/, DEV_ID},
+        op_code:MGMT_OP_INFO_RESP, ops_pending:8'd0};
+      `ASSERT_ERROR(rx_mgmt_pl.ops[1] == exp_mgmt_op,
+        "Discover XB: Mgmt response ops were incorrect");
+
+      // *Status* We just discovered a crossbar with 3 ports! 
+
+      // Configure the crossbar routing table with our (TB) address
+      //  then send node info request on the other two ports
+      tx_mgmt_pl.header.num_hops = 3;
+      tx_mgmt_pl.ops.delete();
+      tx_mgmt_pl.ops[0] = '{  // Hop 1: Crossbar: Config router to return packet to dest
+        op_payload:{22'h0, PORT_TB, EPID_TB}, op_code:MGMT_OP_CFG_WR_REQ, ops_pending:8'd1};
+      tx_mgmt_pl.ops[1] = '{  // Hop 1: Crossbar: Config router 
+        op_payload:{38'h0, PORT_A}, op_code:MGMT_OP_SEL_DEST, ops_pending:8'd0};
+      tx_mgmt_pl.ops[2] = '{  // Hop 2: Stream Endpoint: Send node info 
+        op_payload:48'h0, op_code:MGMT_OP_INFO_REQ, ops_pending:8'd1};
+      tx_mgmt_pl.ops[3] = '{  // Hop 2: Return 
+        op_payload:48'h0, op_code:MGMT_OP_RETURN, ops_pending:8'd0};
+      tx_mgmt_pl.ops[4] = '{  // Hop 3: TB: Nop for return
+        op_payload:48'h0, op_code:MGMT_OP_NOP, ops_pending:8'd0};
+      tx_mgmt_hdr = '{
+        pkt_type:CHDR_MANAGEMENT, seq_num:cached_mgmt_seqnum++, dst_epid:16'h0, default:'0};
+
+      // Send the packet and check the response
+      send_recv_mgmt_packet(tx_mgmt_hdr, tx_mgmt_pl, rx_mgmt_hdr, rx_mgmt_pl);
+      `ASSERT_ERROR(rx_mgmt_pl.header.num_hops == 1,
+        "Discover SEP A: Mgmt header was incorrect");
+      exp_mgmt_op = '{op_payload:{{4'd1, 6'd2, 6'd2, 2'b11} /*ext_info*/, 10'd0 /*inst*/, 4'd2 /*type*/, DEV_ID},
+        op_code:MGMT_OP_INFO_RESP, ops_pending:8'd0};
+      `ASSERT_ERROR(rx_mgmt_pl.ops[1] == exp_mgmt_op,
+        "Discover SEP A: Mgmt response ops were incorrect");
+
+      // *Status* We just discovered a stream endpoint on crossbar port 1
+
+      // Send node info request on the last port
+      tx_mgmt_pl.header.num_hops = 3;
+      tx_mgmt_pl.ops.delete();
+      tx_mgmt_pl.ops[0] = '{  // Hop 1: Crossbar: Config router 
+        op_payload:{38'h0, PORT_B}, op_code:MGMT_OP_SEL_DEST, ops_pending:8'd0};
+      tx_mgmt_pl.ops[1] = '{  // Hop 2: Stream Endpoint: Send node info 
+        op_payload:48'h0, op_code:MGMT_OP_INFO_REQ, ops_pending:8'd1};
+      tx_mgmt_pl.ops[2] = '{  // Hop 2: Return 
+        op_payload:48'h0, op_code:MGMT_OP_RETURN, ops_pending:8'd0};
+      tx_mgmt_pl.ops[3] = '{  // Hop 3: TB: Nop for return
+        op_payload:48'h0, op_code:MGMT_OP_NOP, ops_pending:8'd0};
+      tx_mgmt_hdr = '{
+        pkt_type:CHDR_MANAGEMENT, seq_num:cached_mgmt_seqnum++, dst_epid:16'h0, default:'0};
+
+      // Send the packet and check the response
+      send_recv_mgmt_packet(tx_mgmt_hdr, tx_mgmt_pl, rx_mgmt_hdr, rx_mgmt_pl);
+      `ASSERT_ERROR(rx_mgmt_pl.header.num_hops == 1,
+        "Discover SEP B: Mgmt header was incorrect");
+      exp_mgmt_op = '{op_payload:{{4'd1, 6'd2, 6'd2, 2'b11} /*ext_info*/, 10'd1 /*inst*/, 4'd2 /*type*/, DEV_ID},
+        op_code:MGMT_OP_INFO_RESP, ops_pending:8'd0};
+      `ASSERT_ERROR(rx_mgmt_pl.ops[1] == exp_mgmt_op,
+        "Discover SEP B: Mgmt response ops were incorrect");
+
+      // *Status* We just discovered a stream endpoint on crossbar port 2
+    end
+    test.end_test();
+
+    // Configure Routes to Stream Endpoints A and B
+    // ----------------------------------------
+    test.start_test("Configure Routes");
+    begin
+      automatic chdr_header_t tx_mgmt_hdr, rx_mgmt_hdr;
+      automatic chdr_mgmt_t tx_mgmt_pl, rx_mgmt_pl;
+      automatic chdr_mgmt_op_t exp_mgmt_op;
+
+      // Generic management header
+      tx_mgmt_pl.header = '{
+        default:'0, prot_ver:PROTOVER, chdr_width:translate_chdr_w(CHDR_W), src_epid:EPID_TB
+      };
+      // Send a node info request to the crossbar
+      tx_mgmt_pl.header.num_hops = 2;
+      tx_mgmt_pl.ops.delete();
+
+      tx_mgmt_pl.ops[0] = '{  // Hop 1: Crossbar: Config path to EP A
+        op_payload:{22'h0, PORT_A, EPID_A}, op_code:MGMT_OP_CFG_WR_REQ, ops_pending:8'd2};
+      tx_mgmt_pl.ops[1] = '{  // Hop 1: Crossbar: Config path to EP B 
+        op_payload:{22'h0, PORT_B, EPID_B}, op_code:MGMT_OP_CFG_WR_REQ, ops_pending:8'd1};
+      tx_mgmt_pl.ops[2] = '{  // Hop 1: Request node info to make the packet come back 
+        op_payload:48'h0, op_code:MGMT_OP_RETURN, ops_pending:8'd0};
+      tx_mgmt_pl.ops[3] = '{  // Hop 2: Nop for return
+        op_payload:48'h0, op_code:MGMT_OP_NOP, ops_pending:8'd0};
+      tx_mgmt_hdr = '{
+        pkt_type:CHDR_MANAGEMENT, seq_num:cached_mgmt_seqnum++, dst_epid:16'h0, default:'0};
+
+      // Send the packet and check the response
+      send_recv_mgmt_packet(tx_mgmt_hdr, tx_mgmt_pl, rx_mgmt_hdr, rx_mgmt_pl);
+      `ASSERT_ERROR(rx_mgmt_pl.header.num_hops == 1,
+        "Config Routes: Mgmt header was incorrect");
+      exp_mgmt_op = '{op_payload:48'h0, op_code:MGMT_OP_NOP, ops_pending:8'd0};
+      `ASSERT_ERROR(rx_mgmt_pl.ops[0] == exp_mgmt_op,
+        "Config Routes: Mgmt response ops were incorrect");
+    end
+    test.end_test();
+
+    // Configure Stream Endpoints
+    // ----------------------------------------
+    test.start_test("Configure Stream Endpoints");
+    begin
+      automatic chdr_header_t tx_mgmt_hdr, rx_mgmt_hdr;
+      automatic chdr_mgmt_t tx_mgmt_pl, rx_mgmt_pl;
+      automatic chdr_mgmt_op_t exp_mgmt_op;
+
+      logic [15:0] epids[2] = {EPID_A, EPID_B};
+      foreach (epids[i]) begin
+        // Generic management header
+        tx_mgmt_pl.header = '{
+          default:'0, prot_ver:PROTOVER, chdr_width:translate_chdr_w(CHDR_W), src_epid:EPID_TB
+        };
+        // Send a node info request to the crossbar
+        tx_mgmt_pl.header.num_hops = 3;
+        tx_mgmt_pl.ops.delete();
+
+        tx_mgmt_pl.ops[0] = '{  // Hop 1: Crossbar: Nop
+          op_payload:48'h0, op_code:MGMT_OP_NOP, ops_pending:8'd0};
+        tx_mgmt_pl.ops[1] = '{  // Hop 2: Reset
+          op_payload:{32'b111, sep_a.REG_RESET_AND_FLUSH}, op_code:MGMT_OP_CFG_WR_REQ, ops_pending:8'd4};
+        tx_mgmt_pl.ops[2] = '{  // Hop 2: Write EPID
+          op_payload:{16'h0, epids[i], sep_a.REG_EPID_SELF}, op_code:MGMT_OP_CFG_WR_REQ, ops_pending:8'd3};
+        tx_mgmt_pl.ops[3] = '{  // Hop 2: Read EPID
+          op_payload:{32'h0, sep_a.REG_EPID_SELF}, op_code:MGMT_OP_CFG_RD_REQ, ops_pending:8'd2};
+        tx_mgmt_pl.ops[4] = '{  // Hop 2: Read EPID
+          op_payload:{32'h0, sep_a.REG_OSTRM_CTRL_STATUS}, op_code:MGMT_OP_CFG_RD_REQ, ops_pending:8'd1};
+        tx_mgmt_pl.ops[5] = '{  // Hop 2: Stream Endpoint: Return 
+          op_payload:48'h0, op_code:MGMT_OP_RETURN, ops_pending:8'd0};
+        tx_mgmt_pl.ops[6] = '{  // Hop 3: Nop for return
+          op_payload:48'h0, op_code:MGMT_OP_NOP, ops_pending:8'd0};
+        tx_mgmt_hdr = '{
+          pkt_type:CHDR_MANAGEMENT, seq_num:cached_mgmt_seqnum++, dst_epid:epids[i], default:'0};
+  
+        // Send the packet and check the response
+        send_recv_mgmt_packet(tx_mgmt_hdr, tx_mgmt_pl, rx_mgmt_hdr, rx_mgmt_pl);
+        `ASSERT_ERROR(rx_mgmt_pl.header.num_hops == 1,
+          "Config SEP: Mgmt header was incorrect");
+        exp_mgmt_op = '{op_payload:{16'h0, epids[i], sep_a.REG_EPID_SELF},
+          op_code:MGMT_OP_CFG_RD_RESP, ops_pending:8'd1};
+        `ASSERT_ERROR(rx_mgmt_pl.ops[1] == exp_mgmt_op,
+          "Config SEP: Mgmt response ops were incorrect");
+        exp_mgmt_op = '{op_payload:{32'h0, sep_a.REG_OSTRM_CTRL_STATUS},
+          op_code:MGMT_OP_CFG_RD_RESP, ops_pending:8'd0};
+        `ASSERT_ERROR(rx_mgmt_pl.ops[2] == exp_mgmt_op,
+          "Config SEP: Mgmt response ops were incorrect");
+      end
+    end
+    test.end_test();
+
+    // Setup a stream between Endpoint A and B
+    // ----------------------------------------
+    test.start_test("Setup bidirectional stream between endpoints A and B");
+    begin
+      automatic chdr_header_t tx_mgmt_hdr, rx_mgmt_hdr;
+      automatic chdr_mgmt_t tx_mgmt_pl, rx_mgmt_pl;
+      automatic chdr_mgmt_op_t exp_mgmt_op;
+
+      logic [15:0] epids[2] = {EPID_A, EPID_B};
+      foreach (epids[i]) begin
+        // Generic management header
+        tx_mgmt_pl.header = '{
+          default:'0, prot_ver:PROTOVER, chdr_width:translate_chdr_w(CHDR_W), src_epid:EPID_TB
+        };
+        // Configure FC on streams
+        tx_mgmt_pl.header.num_hops = 3;
+        tx_mgmt_pl.ops.delete();
+
+        tx_mgmt_pl.ops[0] = '{  // Hop 1: Crossbar: Nop
+          op_payload:48'h0, op_code:MGMT_OP_NOP, ops_pending:8'd0};
+        tx_mgmt_pl.ops[1] = '{  // Hop 2: Write destination EPID
+          op_payload:{16'h0, epids[1-i], sep_a.REG_OSTRM_DST_EPID}, op_code:MGMT_OP_CFG_WR_REQ, ops_pending:8'd7};
+        tx_mgmt_pl.ops[2] = '{  // Hop 2: Configure flow ack control freq
+          op_payload:{32'd50, sep_a.REG_OSTRM_FC_FREQ_BYTES_LO}, op_code:MGMT_OP_CFG_WR_REQ, ops_pending:8'd6};
+        tx_mgmt_pl.ops[3] = '{  // Hop 2: Configure flow ack control freq
+          op_payload:{32'd0, sep_a.REG_OSTRM_FC_FREQ_BYTES_HI}, op_code:MGMT_OP_CFG_WR_REQ, ops_pending:8'd5};
+        tx_mgmt_pl.ops[4] = '{  // Hop 2: Configure flow ack control freq
+          op_payload:{32'd1000, sep_a.REG_OSTRM_FC_FREQ_PKTS}, op_code:MGMT_OP_CFG_WR_REQ, ops_pending:8'd4};
+        tx_mgmt_pl.ops[5] = '{  // Hop 2: Configure flow headroom
+          op_payload:{32'd0, sep_a.REG_OSTRM_FC_HEADROOM}, op_code:MGMT_OP_CFG_WR_REQ, ops_pending:8'd3};
+        tx_mgmt_pl.ops[6] = '{  // Hop 2: Configure word swapping
+          op_payload:{32'h44, sep_a.REG_ISTRM_CTRL_STATUS}, op_code:MGMT_OP_CFG_WR_REQ, ops_pending:8'd2}; // Swap 32-bit words, endianness
+        tx_mgmt_pl.ops[7] = '{  // Hop 2: Configure lossy and start config
+          op_payload:{32'h47, sep_a.REG_OSTRM_CTRL_STATUS}, op_code:MGMT_OP_CFG_WR_REQ, ops_pending:8'd1}; // Swap 32-bit words, endianness, lossy and reset
+        tx_mgmt_pl.ops[8] = '{  // Hop 2: Stream Endpoint: Return 
+          op_payload:48'h0, op_code:MGMT_OP_RETURN, ops_pending:8'd0};
+        tx_mgmt_pl.ops[9] = '{  // Hop 3: Nop for return
+          op_payload:48'h0, op_code:MGMT_OP_NOP, ops_pending:8'd0};
+        tx_mgmt_hdr = '{
+          pkt_type:CHDR_MANAGEMENT, seq_num:cached_mgmt_seqnum++, dst_epid:epids[i], default:'0};
+
+        // Send the packet and check the response
+        send_recv_mgmt_packet(tx_mgmt_hdr, tx_mgmt_pl, rx_mgmt_hdr, rx_mgmt_pl);
+
+        // Wait for some time for node to flush and reset
+        // Typically we would poll in SW but we just wait to keep the code simple
+        repeat (256) @(posedge rfnoc_chdr_clk);
+
+        // Read back FC status
+        tx_mgmt_pl.header.num_hops = 3;
+        tx_mgmt_pl.ops.delete();
+
+        tx_mgmt_pl.ops[0] = '{  // Hop 1: Crossbar: Nop
+          op_payload:48'h0, op_code:MGMT_OP_NOP, ops_pending:8'd0};
+        tx_mgmt_pl.ops[1] = '{  // Hop 2: Read status
+          op_payload:{32'h0, sep_a.REG_OSTRM_CTRL_STATUS}, op_code:MGMT_OP_CFG_RD_REQ, ops_pending:8'd7};
+        tx_mgmt_pl.ops[2] = '{  // Hop 2: Read status
+          op_payload:{32'h0, sep_a.REG_OSTRM_BUFF_CAP_BYTES_LO}, op_code:MGMT_OP_CFG_RD_REQ, ops_pending:8'd6};
+        tx_mgmt_pl.ops[3] = '{  // Hop 2: Read status
+          op_payload:{32'h0, sep_a.REG_OSTRM_BUFF_CAP_BYTES_HI}, op_code:MGMT_OP_CFG_RD_REQ, ops_pending:8'd5};
+        tx_mgmt_pl.ops[4] = '{  // Hop 2: Read status
+          op_payload:{32'h0, sep_a.REG_OSTRM_BUFF_CAP_PKTS}, op_code:MGMT_OP_CFG_RD_REQ, ops_pending:8'd4};
+        tx_mgmt_pl.ops[5] = '{  // Hop 2: Read status
+          op_payload:{32'h0, sep_a.REG_OSTRM_SEQ_ERR_CNT}, op_code:MGMT_OP_CFG_RD_REQ, ops_pending:8'd3};
+        tx_mgmt_pl.ops[6] = '{  // Hop 2: Read status
+          op_payload:{32'h0, sep_a.REG_OSTRM_DATA_ERR_CNT}, op_code:MGMT_OP_CFG_RD_REQ, ops_pending:8'd2};
+        tx_mgmt_pl.ops[7] = '{  // Hop 2: Read status
+          op_payload:{32'h0, sep_a.REG_OSTRM_ROUTE_ERR_CNT}, op_code:MGMT_OP_CFG_RD_REQ, ops_pending:8'd1};
+        tx_mgmt_pl.ops[8] = '{  // Hop 2: Stream Endpoint: Return 
+          op_payload:48'h0, op_code:MGMT_OP_RETURN, ops_pending:8'd0};
+        tx_mgmt_pl.ops[9] = '{  // Hop 3: Nop for return
+          op_payload:48'h0, op_code:MGMT_OP_NOP, ops_pending:8'd0};
+        tx_mgmt_hdr = '{
+          pkt_type:CHDR_MANAGEMENT, seq_num:cached_mgmt_seqnum++, dst_epid:epids[i], default:'0};
+
+        // Send the packet and check the response
+        send_recv_mgmt_packet(tx_mgmt_hdr, tx_mgmt_pl, rx_mgmt_hdr, rx_mgmt_pl);
+        `ASSERT_ERROR(rx_mgmt_pl.header.num_hops == 1,
+          "Config SEP: Mgmt header was incorrect");
+        exp_mgmt_op = '{op_payload:{32'h80000006, sep_a.REG_OSTRM_CTRL_STATUS},   // FC on, no errors and lossy
+          op_code:MGMT_OP_CFG_RD_RESP, ops_pending:8'd6};
+        `ASSERT_ERROR(rx_mgmt_pl.ops[1] == exp_mgmt_op, "Config SEP: Mgmt response was incorrect");
+        exp_mgmt_op = '{op_payload:{((1<<(MTU+1))*(CHDR_W/8)-1), sep_a.REG_OSTRM_BUFF_CAP_BYTES_LO},
+          op_code:MGMT_OP_CFG_RD_RESP, ops_pending:8'd5};
+        `ASSERT_ERROR(rx_mgmt_pl.ops[2] == exp_mgmt_op, "Config SEP: Mgmt response was incorrect");
+        exp_mgmt_op = '{op_payload:{32'h0, sep_a.REG_OSTRM_BUFF_CAP_BYTES_HI},
+          op_code:MGMT_OP_CFG_RD_RESP, ops_pending:8'd4};
+        `ASSERT_ERROR(rx_mgmt_pl.ops[3] == exp_mgmt_op, "Config SEP: Mgmt response was incorrect");
+        exp_mgmt_op = '{op_payload:{32'h00ffffff, sep_a.REG_OSTRM_BUFF_CAP_PKTS},
+          op_code:MGMT_OP_CFG_RD_RESP, ops_pending:8'd3};
+        `ASSERT_ERROR(rx_mgmt_pl.ops[4] == exp_mgmt_op, "Config SEP: Mgmt response was incorrect");
+        exp_mgmt_op = '{op_payload:{32'h0, sep_a.REG_OSTRM_SEQ_ERR_CNT},
+          op_code:MGMT_OP_CFG_RD_RESP, ops_pending:8'd2};
+        `ASSERT_ERROR(rx_mgmt_pl.ops[5] == exp_mgmt_op, "Config SEP: Mgmt response was incorrect");
+        exp_mgmt_op = '{op_payload:{32'h0, sep_a.REG_OSTRM_DATA_ERR_CNT},
+          op_code:MGMT_OP_CFG_RD_RESP, ops_pending:8'd1};
+        `ASSERT_ERROR(rx_mgmt_pl.ops[6] == exp_mgmt_op, "Config SEP: Mgmt response was incorrect");
+        exp_mgmt_op = '{op_payload:{32'h0, sep_a.REG_OSTRM_ROUTE_ERR_CNT},
+          op_code:MGMT_OP_CFG_RD_RESP, ops_pending:8'd0};
+        `ASSERT_ERROR(rx_mgmt_pl.ops[7] == exp_mgmt_op, "Config SEP: Mgmt response was incorrect");
+      end
+    end
+    test.end_test();
+
+    // Control transactions to Endpoint A
+    // ----------------------------------------
+    cached_ctrl_seqnum = 0;
+    for (int cfg = 0; cfg < 2; cfg++) begin
+      $sformat(tc_label, "Control Xact to A (%s)", (cfg?"Slow":"Fast"));
+      test.start_test(tc_label);
+      begin
+        tb_chdr_bfm.set_master_stall_prob(cfg?SLOW_STALL_PROB:FAST_STALL_PROB);
+        tb_chdr_bfm.set_slave_stall_prob(cfg?SLOW_STALL_PROB:FAST_STALL_PROB);
+        send_recv_ctrl_packets(EPID_A, NUM_PKTS_PER_TEST, cached_ctrl_seqnum);
+      end
+      test.end_test();
+      cached_ctrl_seqnum += NUM_PKTS_PER_TEST;
+    end
+
+    // Control transactions to Endpoint B
+    // ----------------------------------------
+    cached_ctrl_seqnum = 0;
+    for (int cfg = 0; cfg < 2; cfg++) begin
+      $sformat(tc_label, "Control Xact to B (%s)", (cfg?"Slow":"Fast"));
+      test.start_test(tc_label);
+      begin
+        tb_chdr_bfm.set_master_stall_prob(cfg?SLOW_STALL_PROB:FAST_STALL_PROB);
+        tb_chdr_bfm.set_slave_stall_prob(cfg?SLOW_STALL_PROB:FAST_STALL_PROB);
+        send_recv_ctrl_packets(EPID_B, NUM_PKTS_PER_TEST, cached_ctrl_seqnum);
+      end
+      test.end_test();
+      cached_ctrl_seqnum += NUM_PKTS_PER_TEST;
+    end
+
+    // Stream data from A to B
+    // ----------------------------------------
+    cached_data_seqnum = 0;
+    for (int cfg = 0; cfg < 4; cfg++) begin
+      automatic logic mst_cfg = cfg[0];
+      automatic logic slv_cfg = cfg[1];
+      $sformat(tc_label, "Stream Data from A to B (%s Mst, %s Slv)",
+        (mst_cfg?"Slow":"Fast"), (slv_cfg?"Slow":"Fast"));
+      test.start_test(tc_label);
+      begin
+        set_unidir_stall_prob(EPID_A, EPID_B,
+          mst_cfg?SLOW_STALL_PROB:FAST_STALL_PROB,
+          slv_cfg?SLOW_STALL_PROB:FAST_STALL_PROB);
+        send_recv_data_packets(EPID_A, EPID_B, NUM_PKTS_PER_TEST, cached_data_seqnum);
+      end
+      test.end_test();
+      cached_data_seqnum += NUM_PKTS_PER_TEST;
+    end
+
+    // Stream data from B to A
+    // ----------------------------------------
+    cached_data_seqnum = 0;
+    for (int cfg = 0; cfg < 4; cfg++) begin
+      automatic logic mst_cfg = cfg[0];
+      automatic logic slv_cfg = cfg[1];
+      $sformat(tc_label, "Stream Data from B to A (%s Mst, %s Slv)",
+        (mst_cfg?"Slow":"Fast"), (slv_cfg?"Slow":"Fast"));
+      test.start_test(tc_label);
+      begin
+        set_unidir_stall_prob(EPID_B, EPID_A,
+          mst_cfg?SLOW_STALL_PROB:FAST_STALL_PROB,
+          slv_cfg?SLOW_STALL_PROB:FAST_STALL_PROB);
+        send_recv_data_packets(EPID_B, EPID_A, NUM_PKTS_PER_TEST, cached_data_seqnum);
+      end
+      test.end_test();
+      cached_data_seqnum += NUM_PKTS_PER_TEST;
+    end
+
+    // Stream data between A <=> B simultaneously
+    // ----------------------------------------
+    for (int cfg = 0; cfg < 4; cfg++) begin
+      automatic logic mst_cfg = cfg[0];
+      automatic logic slv_cfg = cfg[1];
+      $sformat(tc_label, "Stream Data between A <=> B simultaneously (%s Mst, %s Slv)",
+        (mst_cfg?"Slow":"Fast"), (slv_cfg?"Slow":"Fast"));
+      test.start_test(tc_label);
+      begin
+        set_bidir_stall_prob(
+          mst_cfg?SLOW_STALL_PROB:FAST_STALL_PROB,
+          slv_cfg?SLOW_STALL_PROB:FAST_STALL_PROB);
+        fork
+          send_recv_data_packets(EPID_B, EPID_A, NUM_PKTS_PER_TEST, cached_data_seqnum);
+          send_recv_data_packets(EPID_A, EPID_B, NUM_PKTS_PER_TEST, cached_data_seqnum);
+        join
+      end
+      test.end_test();
+      cached_data_seqnum += NUM_PKTS_PER_TEST;
+    end
+
+    // Stream data and control between A <=> B simultaneously
+    // ----------------------------------------
+    for (int cfg = 0; cfg < 4; cfg++) begin
+      automatic logic mst_cfg = cfg[0];
+      automatic logic slv_cfg = cfg[1];
+      $sformat(tc_label, "Stream Data and Control between A <=> B (%s Mst, %s Slv)",
+        (mst_cfg?"Slow":"Fast"), (slv_cfg?"Slow":"Fast"));
+      test.start_test(tc_label);
+      begin
+        tb_chdr_bfm.set_master_stall_prob(mst_cfg?SLOW_STALL_PROB:FAST_STALL_PROB);
+        tb_chdr_bfm.set_slave_stall_prob(slv_cfg?SLOW_STALL_PROB:FAST_STALL_PROB);
+        set_bidir_stall_prob(
+          mst_cfg?SLOW_STALL_PROB:FAST_STALL_PROB,
+          slv_cfg?SLOW_STALL_PROB:FAST_STALL_PROB);
+        fork
+          send_recv_data_packets(EPID_B, EPID_A, NUM_PKTS_PER_TEST/2, cached_data_seqnum);
+          send_recv_data_packets(EPID_A, EPID_B, NUM_PKTS_PER_TEST/2, cached_data_seqnum);
+          send_recv_ctrl_packets(EPID_A, NUM_PKTS_PER_TEST, cached_ctrl_seqnum);
+        join
+        cached_data_seqnum += NUM_PKTS_PER_TEST/2;
+        fork
+          send_recv_data_packets(EPID_B, EPID_A, NUM_PKTS_PER_TEST/2, cached_data_seqnum);
+          send_recv_data_packets(EPID_A, EPID_B, NUM_PKTS_PER_TEST/2, cached_data_seqnum);
+          send_recv_ctrl_packets(EPID_B, NUM_PKTS_PER_TEST, cached_ctrl_seqnum);
+        join
+        cached_data_seqnum += NUM_PKTS_PER_TEST/2;
+        cached_ctrl_seqnum += NUM_PKTS_PER_TEST;
+      end
+      test.end_test();
+    end
+
+    // Check zero sequence errors after streaming
+    // ----------------------------------------
+    test.start_test("Check zero sequence errors after streaming");
+    begin
+      logic [15:0] epids[2] = {EPID_A, EPID_B};
+      foreach (epids[i]) begin
+        mgmt_read_err_counts(epids[i], seq_err_count, route_err_count, data_err_count);
+        `ASSERT_ERROR(seq_err_count == 32'd0, "Check NoErrs: Incorrect seq error count");
+        `ASSERT_ERROR(route_err_count == 32'd0, "Check NoErrs: Incorrect route error count");
+        `ASSERT_ERROR(data_err_count == 32'd0, "Check NoErrs: Incorrect data error count");
+      end
+    end
+    test.end_test();
+
+    // Force sequence error
+    // ----------------------------------------
+    test.start_test("Force sequence error");
+    begin
+      // First sequence error
+      send_recv_data_packets(EPID_A, EPID_B, 1, cached_data_seqnum++, 1);
+      b_seqerr_prob = 100;  // Simulate a dropped packet
+      send_recv_data_packets(EPID_A, EPID_B, 1, cached_data_seqnum++, 1);
+      b_seqerr_prob = 0;
+      repeat (100) @(posedge rfnoc_chdr_clk);  // Wait for sequence error to reach the upstream port
+      mgmt_read_err_counts(EPID_A, seq_err_count, route_err_count, data_err_count);
+      `ASSERT_ERROR(seq_err_count == 32'd1, "Force SeqErr: Incorrect seq error count");
+      `ASSERT_ERROR(route_err_count == 32'd0, "Force SeqErr: Incorrect route error count");
+      `ASSERT_ERROR(data_err_count == 32'd0, "Force SeqErr: Incorrect data error count");
+
+      // Second and third sequence error
+      send_recv_data_packets(EPID_A, EPID_B, 1, cached_data_seqnum++, 1);
+      b_seqerr_prob = 100;  // Simulate another dropped packet
+      send_recv_data_packets(EPID_A, EPID_B, 1, cached_data_seqnum++, 1);
+      b_seqerr_prob = 0;
+      repeat (100) @(posedge rfnoc_chdr_clk);  // Wait for sequence error to reach the upstream port
+      mgmt_read_err_counts(EPID_A, seq_err_count, route_err_count, data_err_count);
+      `ASSERT_ERROR(seq_err_count > 32'd1, "Force SeqErr: Incorrect seq error count");
+      `ASSERT_ERROR(route_err_count == 32'd0, "Force SeqErr: Incorrect route error count");
+      `ASSERT_ERROR(data_err_count == 32'd0, "Force SeqErr: Incorrect data error count");
+    end
+    test.end_test();
+
+    // Force routing error
+    // ----------------------------------------
+    test.start_test("Force routing error");
+    begin
+      logic [31:0] old_route_err_count;
+      // First sequence error
+      send_recv_data_packets(EPID_B, EPID_A, 1, cached_data_seqnum++, 1);
+      a_rterr_prob = 100;  // Simulate a routing error
+      send_recv_data_packets(EPID_B, EPID_A, 1, cached_data_seqnum++, 1);
+      a_rterr_prob = 0;
+      repeat (100) @(posedge rfnoc_chdr_clk);  // Wait for sequence error to reach the upstream port
+      mgmt_read_err_counts(EPID_B, seq_err_count, route_err_count, data_err_count);
+      `ASSERT_ERROR(seq_err_count == 32'd0, "Force RouteErr 1: Incorrect seq error count");
+      `ASSERT_ERROR(route_err_count > 32'd0, "Force RouteErr 1: Incorrect route error count");
+      `ASSERT_ERROR(data_err_count == 32'd0, "Force RouteErr 1: Incorrect data error count");
+      old_route_err_count = route_err_count;
+
+      // Second routing error
+      send_recv_data_packets(EPID_B, EPID_A, 1, cached_data_seqnum++, 1);
+      a_rterr_prob = 100;  // Simulate a routing error
+      send_recv_data_packets(EPID_B, EPID_A, 1, cached_data_seqnum++, 1);
+      a_rterr_prob = 0;
+      repeat (100) @(posedge rfnoc_chdr_clk);  // Wait for sequence error to reach the upstream port
+      mgmt_read_err_counts(EPID_B, seq_err_count, route_err_count, data_err_count);
+      `ASSERT_ERROR(seq_err_count == 32'd0, "Force RouteErr 2: Incorrect seq error count");
+      `ASSERT_ERROR(route_err_count > old_route_err_count, "Force RouteErr 2: Incorrect route error count");
+      `ASSERT_ERROR(data_err_count == 32'd0, "Force RouteErr 2: Incorrect data error count");
+    end
+    test.end_test();
+
+    // Setup a stream between Endpoint A and B
+    // ----------------------------------------
+    test.start_test("Reconfigure flow control (reset state)");
+    begin
+      automatic chdr_header_t tx_mgmt_hdr, rx_mgmt_hdr;
+      automatic chdr_mgmt_t tx_mgmt_pl, rx_mgmt_pl;
+      automatic chdr_mgmt_op_t exp_mgmt_op;
+
+      logic [15:0] epids[2] = {EPID_A, EPID_B};
+      foreach (epids[i]) begin
+        // Generic management header
+        tx_mgmt_pl.header = '{
+          default:'0, prot_ver:PROTOVER, chdr_width:translate_chdr_w(CHDR_W), src_epid:EPID_TB
+        };
+        // Configure FC on streams
+        tx_mgmt_pl.header.num_hops = 3;
+        tx_mgmt_pl.ops.delete();
+
+        tx_mgmt_pl.ops[0] = '{  // Hop 1: Crossbar: Nop
+          op_payload:48'h0, op_code:MGMT_OP_NOP, ops_pending:8'd0};
+        tx_mgmt_pl.ops[1] = '{  // Hop 2: Disable swapping
+          op_payload:{32'd0, sep_a.REG_ISTRM_CTRL_STATUS}, op_code:MGMT_OP_CFG_WR_REQ, ops_pending:8'd2};
+        tx_mgmt_pl.ops[2] = '{  // Hop 2: Configure lossy and start config
+          op_payload:{32'd3, sep_a.REG_OSTRM_CTRL_STATUS}, op_code:MGMT_OP_CFG_WR_REQ, ops_pending:8'd1};
+        tx_mgmt_pl.ops[3] = '{  // Hop 2: Stream Endpoint: Return 
+          op_payload:48'h0, op_code:MGMT_OP_RETURN, ops_pending:8'd0};
+        tx_mgmt_pl.ops[4] = '{  // Hop 3: Nop for return
+          op_payload:48'h0, op_code:MGMT_OP_NOP, ops_pending:8'd0};
+        tx_mgmt_hdr = '{
+          pkt_type:CHDR_MANAGEMENT, seq_num:cached_mgmt_seqnum++, dst_epid:epids[i], default:'0};
+
+        // Send the packet and check the response
+        send_recv_mgmt_packet(tx_mgmt_hdr, tx_mgmt_pl, rx_mgmt_hdr, rx_mgmt_pl);
+
+        // Wait for some time for node to flush and reset
+        // Typically we would poll in SW but we just wait to keep the code simple
+        repeat (256) @(posedge rfnoc_chdr_clk);
+
+        // Read back FC status
+        tx_mgmt_pl.header.num_hops = 3;
+        tx_mgmt_pl.ops.delete();
+
+        tx_mgmt_pl.ops[0] = '{  // Hop 1: Crossbar: Nop
+          op_payload:48'h0, op_code:MGMT_OP_NOP, ops_pending:8'd0};
+        tx_mgmt_pl.ops[1] = '{  // Hop 2: Read status
+          op_payload:{32'h0, sep_a.REG_OSTRM_CTRL_STATUS}, op_code:MGMT_OP_CFG_RD_REQ, ops_pending:8'd1};
+        tx_mgmt_pl.ops[2] = '{  // Hop 2: Stream Endpoint: Return 
+          op_payload:48'h0, op_code:MGMT_OP_RETURN, ops_pending:8'd0};
+        tx_mgmt_pl.ops[3] = '{  // Hop 3: Nop for return
+          op_payload:48'h0, op_code:MGMT_OP_NOP, ops_pending:8'd0};
+        tx_mgmt_hdr = '{
+          pkt_type:CHDR_MANAGEMENT, seq_num:cached_mgmt_seqnum++, dst_epid:epids[i], default:'0};
+
+        // Send the packet and check the response
+        send_recv_mgmt_packet(tx_mgmt_hdr, tx_mgmt_pl, rx_mgmt_hdr, rx_mgmt_pl);
+        `ASSERT_ERROR(rx_mgmt_pl.header.num_hops == 1,
+          "Config SEP: Mgmt header was incorrect");
+        exp_mgmt_op = '{op_payload:{32'h80000002, sep_a.REG_OSTRM_CTRL_STATUS},   // FC on, no errors and lossy
+          op_code:MGMT_OP_CFG_RD_RESP, ops_pending:8'd0};
+        `ASSERT_ERROR(rx_mgmt_pl.ops[1] == exp_mgmt_op, "Config SEP: Mgmt response was incorrect");
+      end
+    end
+    test.end_test();
+
+    // Check zero errors after reinit
+    // ----------------------------------------
+    test.start_test("Check zero errors after reinit");
+    begin
+      logic [15:0] epids[2] = {EPID_A, EPID_B};
+      foreach (epids[i]) begin
+        mgmt_read_err_counts(epids[i], seq_err_count, route_err_count, data_err_count);
+        `ASSERT_ERROR(seq_err_count == 32'd0, "Check NoErrs: Incorrect seq error count");
+        `ASSERT_ERROR(route_err_count == 32'd0, "Check NoErrs: Incorrect route error count");
+        `ASSERT_ERROR(data_err_count == 32'd0, "Check NoErrs: Incorrect data error count");
+      end
+    end
+    test.end_test();
+
+    // Stream data between A <=> B simultaneously
+    // ----------------------------------------
+    test.start_test("Stream Data between A <=> B with a lossy link");
+    begin
+      cached_data_seqnum = 0;
+      set_bidir_stall_prob(FAST_STALL_PROB, SLOW_STALL_PROB);
+      a_lossy_input = 1;
+      b_lossy_input = 1;
+      fork
+        send_recv_data_packets(EPID_B, EPID_A, NUM_PKTS_PER_TEST * 10, cached_data_seqnum);
+        send_recv_data_packets(EPID_A, EPID_B, NUM_PKTS_PER_TEST * 10, cached_data_seqnum);
+      join
+      a_lossy_input = 0;
+      b_lossy_input = 0;
+    end
+    test.end_test();
+    cached_data_seqnum += NUM_PKTS_PER_TEST*10;
+
+    // Finish Up
+    // ----------------------------------------
+    // Display final statistics and results
+    test.end_tb();
+  end
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/sim/chdr_stream_endpoint_tb/lossy_xport_model.v b/fpga/usrp3/lib/rfnoc/sim/chdr_stream_endpoint_tb/lossy_xport_model.v
new file mode 100644
index 000000000..a93b4b305
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/sim/chdr_stream_endpoint_tb/lossy_xport_model.v
@@ -0,0 +1,66 @@
+//
+// Copyright 2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: lossy_xport_model
+//
+
+module lossy_xport_model #(
+  parameter CHDR_W = 256
+)(
+  input  wire              clk,
+  input  wire              rst,
+  input  wire [CHDR_W-1:0] s_axis_tdata,
+  input  wire              s_axis_tlast,
+  input  wire              s_axis_tvalid,
+  output wire              s_axis_tready,
+  output wire [CHDR_W-1:0] m_axis_tdata,
+  output wire              m_axis_tlast,
+  output wire              m_axis_tvalid,
+  input  wire              m_axis_tready,
+  input  wire [7:0]        seqerr_prob,
+  input  wire [7:0]        rterr_prob,
+  input  wire              lossy
+);
+  wire [CHDR_W-1:0] tmp_tdata;
+  wire              tmp_tlast;
+  wire              tmp_tvalid;
+  wire              tmp_tready;
+
+  reg pkt_header = 1'b1;
+  always @(posedge clk) begin
+    if (rst) begin
+      pkt_header <= 1'b1;
+    end else if (s_axis_tvalid && s_axis_tready) begin
+      pkt_header <= s_axis_tlast;
+    end
+  end
+  wire pkt_stb = (s_axis_tvalid && s_axis_tready && s_axis_tlast);
+
+  reg force_seq_err, force_route_err;
+  always @(pkt_stb or seqerr_prob) begin
+    force_seq_err = ($urandom_range(99) < seqerr_prob);
+  end
+  always @(pkt_stb or rterr_prob) begin
+    force_route_err = ($urandom_range(99) < rterr_prob);
+  end
+
+  wire [15:0] new_seq_num  = s_axis_tdata[47:32] + 16'd1;   //Increment SeqNum
+  wire [15:0] new_dst_epid = ~s_axis_tdata[15:0];           //Invert DstEPID
+
+  assign tmp_tdata = !pkt_header ? s_axis_tdata : (
+    force_seq_err ? {s_axis_tdata[CHDR_W-1:48], new_seq_num, s_axis_tdata[31:0]} : (
+      force_route_err ? {s_axis_tdata[CHDR_W-1:16], new_dst_epid} : s_axis_tdata));
+  assign tmp_tlast  = s_axis_tlast;
+  assign tmp_tvalid = s_axis_tvalid;
+  assign s_axis_tready = lossy || tmp_tready;
+
+  axi_fifo #(.WIDTH(CHDR_W+1), .SIZE(1)) out_fifo (
+    .clk(clk), .reset(rst), .clear(1'b0),
+    .i_tdata({tmp_tlast, tmp_tdata}), .i_tvalid(tmp_tvalid), .i_tready(tmp_tready),
+    .o_tdata({m_axis_tlast, m_axis_tdata}), .o_tvalid(m_axis_tvalid), .o_tready(m_axis_tready),
+    .space(), .occupied()
+  );
+
+endmodule
\ No newline at end of file
diff --git a/fpga/usrp3/lib/rfnoc/sim/ctrlport_endpoint_tb/Makefile b/fpga/usrp3/lib/rfnoc/sim/ctrlport_endpoint_tb/Makefile
new file mode 100644
index 000000000..f1f064547
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/sim/ctrlport_endpoint_tb/Makefile
@@ -0,0 +1,39 @@
+#
+# Copyright 2019 Ettus Research, A National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+#-------------------------------------------------
+# Top-of-Makefile
+#-------------------------------------------------
+# Define BASE_DIR to point to the "top" dir
+BASE_DIR = $(abspath ../../../../top)
+# Include viv_sim_preamble after defining BASE_DIR
+include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
+
+#-------------------------------------------------
+# Design Specific
+#-------------------------------------------------
+# Include makefiles and sources for the DUT and its dependencies
+include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs
+
+DESIGN_SRCS += $(abspath \
+$(RFNOC_CORE_SRCS) \
+)
+
+#-------------------------------------------------
+# Testbench Specific
+#-------------------------------------------------
+SIM_TOP = ctrlport_endpoint_tb
+
+SIM_SRCS = \
+$(abspath ctrlport_endpoint_tb.sv) \
+
+#-------------------------------------------------
+# Bottom-of-Makefile
+#-------------------------------------------------
+# Include all simulator specific makefiles here
+# Each should define a unique target to simulate
+# e.g. xsim, vsim, etc and a common "clean" target
+include $(BASE_DIR)/../tools/make/viv_simulator.mak
diff --git a/fpga/usrp3/lib/rfnoc/sim/ctrlport_endpoint_tb/ctrlport_endpoint_tb.sv b/fpga/usrp3/lib/rfnoc/sim/ctrlport_endpoint_tb/ctrlport_endpoint_tb.sv
new file mode 100644
index 000000000..492e48829
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/sim/ctrlport_endpoint_tb/ctrlport_endpoint_tb.sv
@@ -0,0 +1,502 @@
+//
+// Copyright 2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: ctrlport_endpoint_tb
+//
+
+`default_nettype none
+
+
+module ctrlport_endpoint_tb;
+
+  // Include macros and time declarations for use with PkgTestExec
+  `include "test_exec.svh"
+
+  import PkgTestExec::*;
+  import PkgChdrUtils::*;
+  import PkgAxisCtrlBfm::*;
+
+  // Parameters
+  localparam [9:0]  THIS_PORTID = 10'h17;
+  localparam [15:0] THIS_EPID   = 16'hDEAD;
+
+  localparam integer NUM_XACT_PER_TEST = 300;
+  localparam integer FAST_STALL_PROB   = 0;
+  localparam integer SLOW_STALL_PROB   = 50;
+  localparam bit     VERBOSE           = 0;
+
+  // Clock and Reset Definition
+  bit rfnoc_ctrl_clk, rfnoc_ctrl_rst;
+  bit ctrlport_clk, ctrlport_rst;
+
+  sim_clock_gen #(6.0) rfnoc_ctrl_clk_gen (rfnoc_ctrl_clk, rfnoc_ctrl_rst); // 166.6 MHz
+  sim_clock_gen #(20.0) ctrlport_clk_gen (ctrlport_clk, ctrlport_rst); // 50 MHz
+
+  // ----------------------------------------
+  // Instantiate DUT
+  // ----------------------------------------
+  AxiStreamIf #(32) m_ctrl (rfnoc_ctrl_clk, rfnoc_ctrl_rst);
+  AxiStreamIf #(32) s_ctrl (rfnoc_ctrl_clk, rfnoc_ctrl_rst);
+  AxisCtrlBfm axis_ctrl_bfm;
+
+  wire  [31:0]  axis_mst_tdata,  axis_slv_tdata , axis_req_tdata , axis_resp_tdata ;
+  wire          axis_mst_tlast,  axis_slv_tlast , axis_req_tlast , axis_resp_tlast ;
+  wire          axis_mst_tvalid, axis_slv_tvalid, axis_req_tvalid, axis_resp_tvalid;
+  wire          axis_mst_tready, axis_slv_tready, axis_req_tready, axis_resp_tready;
+
+  wire          cp_slv_req_wr;
+  wire          cp_slv_req_rd;
+  wire  [19:0]  cp_slv_req_addr;
+  wire  [31:0]  cp_slv_req_data;
+  wire  [3:0]   cp_slv_req_byte_en;
+  wire          cp_slv_req_has_time;
+  wire  [63:0]  cp_slv_req_time;
+  reg           cp_slv_resp_ack;
+  reg   [1:0]   cp_slv_resp_status;
+  reg   [31:0]  cp_slv_resp_data;
+
+  logic         cp_mst_req_wr;
+  logic         cp_mst_req_rd;
+  logic [19:0]  cp_mst_req_addr;
+  logic [9:0]   cp_mst_req_portid;
+  logic [15:0]  cp_mst_req_rem_epid;
+  logic [9:0]   cp_mst_req_rem_portid;
+  logic [31:0]  cp_mst_req_data;
+  logic [3:0]   cp_mst_req_byte_en;
+  logic         cp_mst_req_has_time;
+  logic [63:0]  cp_mst_req_time;
+  wire          cp_mst_resp_ack;
+  wire  [1:0]   cp_mst_resp_status;
+  wire  [31:0]  cp_mst_resp_data;
+
+  ctrlport_endpoint #(
+    .THIS_PORTID              (THIS_PORTID),
+    .SYNC_CLKS                (0),
+    .AXIS_CTRL_MST_EN         (1),
+    .AXIS_CTRL_SLV_EN         (1),
+    .SLAVE_FIFO_SIZE          (5)
+  ) dut (
+    .rfnoc_ctrl_clk           (rfnoc_ctrl_clk      ),
+    .rfnoc_ctrl_rst           (rfnoc_ctrl_rst      ),
+    .ctrlport_clk             (ctrlport_clk        ),
+    .ctrlport_rst             (ctrlport_rst        ),
+    .s_rfnoc_ctrl_tdata       (axis_mst_tdata      ),
+    .s_rfnoc_ctrl_tlast       (axis_mst_tlast      ),
+    .s_rfnoc_ctrl_tvalid      (axis_mst_tvalid     ),
+    .s_rfnoc_ctrl_tready      (axis_mst_tready     ),
+    .m_rfnoc_ctrl_tdata       (axis_slv_tdata      ),
+    .m_rfnoc_ctrl_tlast       (axis_slv_tlast      ),
+    .m_rfnoc_ctrl_tvalid      (axis_slv_tvalid     ),
+    .m_rfnoc_ctrl_tready      (axis_slv_tready     ),
+    .m_ctrlport_req_wr        (cp_slv_req_wr       ),
+    .m_ctrlport_req_rd        (cp_slv_req_rd       ),
+    .m_ctrlport_req_addr      (cp_slv_req_addr     ),
+    .m_ctrlport_req_data      (cp_slv_req_data     ),
+    .m_ctrlport_req_byte_en   (cp_slv_req_byte_en  ),
+    .m_ctrlport_req_has_time  (cp_slv_req_has_time ),
+    .m_ctrlport_req_time      (cp_slv_req_time     ),
+    .m_ctrlport_resp_ack      (cp_slv_resp_ack     ),
+    .m_ctrlport_resp_status   (cp_slv_resp_status  ),
+    .m_ctrlport_resp_data     (cp_slv_resp_data    ),
+    .s_ctrlport_req_wr        (cp_mst_req_wr       ),
+    .s_ctrlport_req_rd        (cp_mst_req_rd       ),
+    .s_ctrlport_req_addr      (cp_mst_req_addr     ),
+    .s_ctrlport_req_portid    (cp_mst_req_portid   ),
+    .s_ctrlport_req_rem_epid  (cp_mst_req_rem_epid ),
+    .s_ctrlport_req_rem_portid(cp_mst_req_rem_portid),
+    .s_ctrlport_req_data      (cp_mst_req_data     ),
+    .s_ctrlport_req_byte_en   (cp_mst_req_byte_en  ),
+    .s_ctrlport_req_has_time  (cp_mst_req_has_time ),
+    .s_ctrlport_req_time      (cp_mst_req_time     ),
+    .s_ctrlport_resp_ack      (cp_mst_resp_ack     ),
+    .s_ctrlport_resp_status   (cp_mst_resp_status  ),
+    .s_ctrlport_resp_data     (cp_mst_resp_data    )
+  );
+
+  // ----------------------------------------
+  // Test Helpers
+  // ----------------------------------------
+
+  // Add a MUX and DEMUX on the ctrlport logic to loop responses
+  // back into the endpoint and to allow external access from the
+  // master and slave BFM.
+  axi_mux #(
+    .WIDTH(32), .SIZE(2), .PRIO(0), .PRE_FIFO_SIZE(0), .POST_FIFO_SIZE(0)
+  ) mux_i (
+    .clk(rfnoc_ctrl_clk), .reset(rfnoc_ctrl_rst), .clear(1'b0),
+    .i_tdata ({m_ctrl.slave.tdata , axis_resp_tdata }),
+    .i_tlast ({m_ctrl.slave.tlast , axis_resp_tlast }),
+    .i_tvalid({m_ctrl.slave.tvalid, axis_resp_tvalid}),
+    .i_tready({m_ctrl.slave.tready, axis_resp_tready}),
+    .o_tdata (axis_mst_tdata ),
+    .o_tlast (axis_mst_tlast ),
+    .o_tvalid(axis_mst_tvalid),
+    .o_tready(axis_mst_tready)
+  );
+
+  wire [31:0] in_hdr;
+  axi_demux #(
+    .WIDTH(32), .SIZE(2), .PRE_FIFO_SIZE(0), .POST_FIFO_SIZE(0)
+  ) demux_i (
+    .clk(rfnoc_ctrl_clk), .reset(rfnoc_ctrl_rst), .clear(1'b0),
+    .header(in_hdr), .dest(in_hdr[31]),
+    .i_tdata (axis_slv_tdata ),
+    .i_tlast (axis_slv_tlast ),
+    .i_tvalid(axis_slv_tvalid),
+    .i_tready(axis_slv_tready),
+    .o_tdata ({s_ctrl.master.tdata , axis_req_tdata }),
+    .o_tlast ({s_ctrl.master.tlast , axis_req_tlast }),
+    .o_tvalid({s_ctrl.master.tvalid, axis_req_tvalid}),
+    .o_tready({s_ctrl.master.tready, axis_req_tready})
+  );
+
+  // --------------------------
+  // [Dummy Control Port Slave]
+  // Slave Model:
+  // - Respond in 1 clock cycle
+  // - Status = Upper 2 bits of the address
+  // - Response Data = 0xFEED and Negated bottom 16 bits of addr
+  always @(posedge ctrlport_clk) begin
+    if (ctrlport_rst) begin
+      cp_slv_resp_ack <= 1'b0;
+    end else begin
+      cp_slv_resp_ack <= cp_slv_req_wr | cp_slv_req_rd;
+      cp_slv_resp_status <= cp_slv_req_addr[19:18];
+      cp_slv_resp_data <= {16'hFEED, ~cp_slv_req_addr[15:0]};
+    end
+  end
+  // --------------------------
+
+  // ----------------------------
+  // [Dummy AXIS-Ctrl Port Slave]
+  // Slave Model:
+  // - Response = Request but with the ACK bit set
+  // - Status = Upper 2 bits of the address
+  // - Response Data = Request Data
+  reg [4:0] line_num = 5'd0;
+  reg       pkt_has_time = 1'b0;
+  wire pkt_hdr_line = (line_num == 5'd0);
+  wire pkt_op_line = pkt_has_time ? (line_num == 5'd4) : (line_num == 5'd2);
+  always @(posedge rfnoc_ctrl_clk) begin
+    if (rfnoc_ctrl_rst) begin
+      line_num <= 5'd0;
+      pkt_has_time <= 1'b0;
+    end else if (axis_req_tvalid & axis_resp_tready) begin
+      if (pkt_hdr_line)
+        pkt_has_time <= axis_req_tdata[30];
+      line_num <= axis_req_tlast ? 5'd0 : (line_num + 1);
+    end
+  end
+  assign axis_resp_tdata = 
+    pkt_hdr_line ? {1'b1, axis_req_tdata[30:0]} : (
+    pkt_op_line ? {axis_req_tdata[19:18], axis_req_tdata[29:0]} : 
+    axis_req_tdata);
+  assign axis_resp_tlast = axis_req_tlast;
+  assign axis_resp_tvalid = axis_req_tvalid;
+  assign axis_req_tready = axis_resp_tready;
+  // ----------------------------
+
+  // Task to send a ctrlport request and receive a response
+  task ctrlport_transact(
+    input         wr,
+    input         rd,
+    input  [19:0] addr,
+    input  [9:0]  portid,
+    input  [15:0] rem_epid,
+    input  [9:0]  rem_portid,
+    input  [31:0] data,
+    input  [3:0]  byte_en,
+    input         has_time,
+    input  [63:0] timestamp,
+    output [1:0]  resp_status,
+    output [31:0] resp_data
+  );
+    if (rd | wr) begin
+      cp_mst_req_wr         <= wr;
+      cp_mst_req_rd         <= rd;
+      cp_mst_req_addr       <= addr;
+      cp_mst_req_portid     <= portid;
+      cp_mst_req_rem_epid   <= rem_epid;
+      cp_mst_req_rem_portid <= rem_portid;
+      cp_mst_req_data       <= data;
+      cp_mst_req_byte_en    <= byte_en;
+      cp_mst_req_has_time   <= has_time;
+      cp_mst_req_time       <= timestamp;
+      @(posedge ctrlport_clk);
+      cp_mst_req_wr         <= 0;
+      cp_mst_req_rd         <= 0;
+      while (~cp_mst_resp_ack) @(posedge ctrlport_clk);
+      resp_status           = cp_mst_resp_status;
+      resp_data             = cp_mst_resp_data;
+
+      // Validate contents
+      if (VERBOSE) begin
+        $display("%s(addr=%0x, data=%0x, portid=%0x, has_time=%0b) = %0x (Status = %0d)",
+          (rd&wr)?"WRRD":(rd?"RD":"WR"), addr, data, portid, has_time, resp_data, resp_status);
+      end
+      `ASSERT_ERROR(cp_mst_resp_status == addr[19:18],
+        "Received Ctrlport response had the wrong status");
+      `ASSERT_ERROR(cp_mst_resp_data == data,
+        "Received Ctrlport response had the wrong data");
+    end
+  endtask
+
+  // Task to send a AxisCtrl request and receive a response
+  logic [5:0] cached_seq_num = 0;
+  task axis_ctrl_transact(
+    input  [3:0]  opcode,
+    input  [19:0] addr,
+    input  [9:0]  portid,
+    input  [15:0] rem_epid,
+    input  [9:0]  rem_portid,
+    input  [31:0] data[$],
+    input  [3:0]  byte_en,
+    input         has_time,
+    input  [63:0] timestamp,
+    output [1:0]  resp_status,
+    output [31:0] resp_data
+  );
+    automatic AxisCtrlPacket tx_pkt, rx_pkt = null, exp_pkt = null;
+    automatic axis_ctrl_header_t header;
+    automatic ctrl_op_word_t op_word;
+    automatic ctrl_status_t  exp_status;
+    automatic ctrl_word_t    exp_data0;
+
+    // Opcode specific logic
+    case (ctrl_opcode_t'(opcode))
+      CTRL_OP_SLEEP: begin
+        // data[0] = cycles of sleep so limit its value
+        if (data.size() > 0) data[0][31:5] = 0;
+        exp_status = CTRL_STS_OKAY;
+        exp_data0 = data[0];
+      end
+      CTRL_OP_WRITE_READ: begin
+        exp_status = ctrl_status_t'(addr[19:18]);
+        exp_data0 = {16'hFEED, ~addr[15:0]};
+      end
+      CTRL_OP_WRITE: begin
+        exp_status = ctrl_status_t'(addr[19:18]);
+        exp_data0 = data[0];
+      end
+      CTRL_OP_READ: begin
+        exp_status = ctrl_status_t'(addr[19:18]);
+        exp_data0 = {16'hFEED, ~addr[15:0]};
+      end
+      default: begin
+        exp_status = CTRL_STS_CMDERR;
+        exp_data0 = data[0];
+      end
+    endcase
+
+    // Build TX packet
+    tx_pkt = new();
+    header = '{
+      default      : '0,
+      rem_dst_port : rem_portid,
+      rem_dst_epid : rem_epid,
+      is_ack       : 1'b0,
+      has_time     : has_time,
+      seq_num      : cached_seq_num,
+      num_data     : data.size(),
+      src_port     : THIS_PORTID,
+      dst_port     : portid
+    };
+    op_word = '{
+      default      : '0,
+      op_code      : ctrl_opcode_t'(opcode),
+      byte_enable  : byte_en,
+      address      : addr
+    };
+    tx_pkt.write_ctrl(header, op_word, data, timestamp);
+
+    // Build expected packet (NULL if data vector is empty)
+    if (data.size() > 0) begin
+      exp_pkt = tx_pkt.copy();
+      exp_pkt.header.is_ack = 1'b1;
+      exp_pkt.op_word.status = exp_status;
+      exp_pkt.data[0] = exp_data0;
+    end
+
+    if (VERBOSE) $display("*******************");
+    fork
+      // Send the packet
+      begin
+        axis_ctrl_bfm.put_ctrl(tx_pkt.copy());
+        if (VERBOSE) begin $display("[TRANSMITTED]"); tx_pkt.print(); end
+      end
+      // Wait for response only if we are expecting one
+      if (exp_pkt != null) begin
+        axis_ctrl_bfm.get_ctrl(rx_pkt);
+        if (VERBOSE) begin $display("[RECEIVED]"); rx_pkt.print(); end
+      end
+    join
+    cached_seq_num = cached_seq_num + 1;
+
+    // Validate contents
+    if (exp_pkt != null) begin
+      if (VERBOSE) begin $display("[EXPECTED]"); exp_pkt.print(); end
+      `ASSERT_ERROR(exp_pkt.equal(rx_pkt),
+        "Received AXIS-Ctrl packet was incorrect");
+    end
+  endtask
+
+  // ----------------------------------------
+  // Test Process
+  // ----------------------------------------
+  initial begin
+    // Shared Variables
+    // ----------------------------------------
+    timeout_t    timeout;
+    string       tc_label;
+    logic [31:0] data_vtr[$];
+    logic [1:0]  resp_status;
+    logic [31:0] resp_data;
+
+    // Initialize
+    // ----------------------------------------
+    test.start_tb("ctrlport_endpoint_tb");
+
+    // Start the BFMs
+    axis_ctrl_bfm = new(m_ctrl, s_ctrl);
+    axis_ctrl_bfm.run();
+
+    // Reset
+    // ----------------------------------------
+    rfnoc_ctrl_clk_gen.reset();
+    ctrlport_clk_gen.reset();
+
+    test.start_test("Wait for reset");
+    test.start_timeout(timeout, 1us, "Waiting for reset");
+    while (rfnoc_ctrl_rst) @(posedge rfnoc_ctrl_clk);
+    while (ctrlport_rst) @(posedge ctrlport_clk);
+    test.end_timeout(timeout);
+    `ASSERT_ERROR(!ctrlport_rst && !rfnoc_ctrl_rst, "Reset did not deassert");
+    test.end_test();
+
+    // AXIS-Ctrl Slave Test
+    // ----------------------------------------
+    // Send AXIS-Ctrl packets to the DUT and expect AXIS-Ctrl
+    // responses. There is a ctrlport slave implemented above
+    for (int cfg = 0; cfg < 4; cfg++) begin
+      automatic logic mst_cfg = cfg[0];
+      automatic logic slv_cfg = cfg[1];
+      $sformat(tc_label,
+        "AXIS-Ctrl Slave (%s Master, %s Slave)",
+        (mst_cfg?"Slow":"Fast"), (slv_cfg?"Slow":"Fast"));
+      test.start_test(tc_label);
+      begin
+        // Set bus stall probabilities based on configuration
+        axis_ctrl_bfm.set_master_stall_prob(mst_cfg?SLOW_STALL_PROB:FAST_STALL_PROB);
+        axis_ctrl_bfm.set_slave_stall_prob(slv_cfg?SLOW_STALL_PROB:FAST_STALL_PROB);
+        // Test multiple transactions
+        for (int n = 0; n < NUM_XACT_PER_TEST; n++) begin
+          // Generate random data for the payload
+          // It is illegal in the protocol to have a zero
+          // data length but we test it here to ensure no lockups
+          data_vtr.delete();
+          for (int i = 0; i < $urandom_range(15); i++)
+            data_vtr[i] = $urandom();
+          // Perform transaction
+          test.start_timeout(timeout, 10us, "Waiting for AXIS-Ctrl transaction");
+          axis_ctrl_transact(
+            $urandom_range(5), // opcode
+            $urandom(), // addr
+            THIS_PORTID, // portid
+            $urandom(), $urandom(), // rem_epid, rem_portid
+            data_vtr,
+            $urandom_range(15), // byte_en
+            $urandom_range(1), // has_time
+            {$urandom(), $urandom()}, // timestamp
+            resp_status,
+            resp_data
+          );
+          test.end_timeout(timeout);
+        end
+      end
+      test.end_test();
+    end
+
+    // AXIS-Ctrl Master Test
+    // ----------------------------------------
+    // Send Ctrlport packets to the DUT and expect Ctrlport
+    // responses. There is a AXIS-Ctrl slave implemented above
+    test.start_test("AXIS-Ctrl Master");
+    begin
+      // Test multiple transactions
+      for (int n = 0; n < NUM_XACT_PER_TEST * 4; n++) begin
+        test.start_timeout(timeout, 10us, "Waiting for Ctrlport transaction");
+        ctrlport_transact(
+          $urandom_range(1), $urandom_range(1), // wr and rd
+          $urandom(), // addr
+          THIS_PORTID, // portid
+          $urandom(), $urandom(), // rem_epid, rem_portid
+          $urandom(), // data
+          $urandom_range(15), // byte_en
+          $urandom_range(1), // has_time
+          {$urandom(), $urandom()}, // timestamp
+          resp_status,
+          resp_data
+        );
+
+        test.end_timeout(timeout);
+      end
+    end
+    test.end_test();
+
+    // AXIS-Ctrl Master+Slave Test
+    // ----------------------------------------
+    test.start_test("AXIS-Ctrl Master + Slave Simultaneously");
+    begin
+      axis_ctrl_bfm.set_master_stall_prob(FAST_STALL_PROB);
+      axis_ctrl_bfm.set_slave_stall_prob(FAST_STALL_PROB);
+      test.start_timeout(timeout, 10us * NUM_XACT_PER_TEST, "Waiting for test case");
+      fork
+        for (int n = 0; n < NUM_XACT_PER_TEST; n++) begin
+          // Generate random data for the payload
+          // It is illegal in the protocol to have a zero
+          // data length but we test it here to ensure no lockups
+          data_vtr.delete();
+          for (int i = 0; i < $urandom_range(15); i++)
+            data_vtr[i] = $urandom();
+          // Perform transaction
+          axis_ctrl_transact(
+            $urandom_range(5), // opcode
+            $urandom(), // addr
+            THIS_PORTID, // portid
+            $urandom(), $urandom(), // rem_epid, rem_portid
+            data_vtr,
+            $urandom_range(15), // byte_en
+            $urandom_range(1), // has_time
+            {$urandom(), $urandom()}, // timestamp
+            resp_status,
+            resp_data
+          );
+        end
+        for (int n = 0; n < NUM_XACT_PER_TEST; n++) begin
+          ctrlport_transact(
+            $urandom_range(1), $urandom_range(1), // wr and rd
+            $urandom(), // addr
+            THIS_PORTID, // portid
+            $urandom(), $urandom(), // rem_epid, rem_portid
+            $urandom(), // data
+            $urandom_range(15), // byte_en
+            $urandom_range(1), // has_time
+            {$urandom(), $urandom()}, // timestamp
+            resp_status,
+            resp_data
+          );
+        end
+      join
+      test.end_timeout(timeout);
+    end
+    test.end_test();
+
+    // Finish Up
+    // ----------------------------------------
+    // Display final statistics and results
+    test.end_tb();
+  end
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/split_complex.v b/fpga/usrp3/lib/rfnoc/split_complex.v
new file mode 100644
index 000000000..b8b755c10
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/split_complex.v
@@ -0,0 +1,30 @@
+
+// Copyright 2014, Ettus Research
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+
+// Module to split a complex stream to I and Q outputs.  NOTE -- ONLY works when you can guarantee downstream paths match!
+
+module split_complex
+  #(parameter WIDTH=16)
+   (input [WIDTH*2-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
+    output [WIDTH-1:0] oi_tdata, output oi_tlast, output oi_tvalid, input oi_tready,
+    output [WIDTH-1:0] oq_tdata, output oq_tlast, output oq_tvalid, input oq_tready,
+    output error);
+
+   assign oi_tdata = i_tdata[WIDTH*2-1:WIDTH];
+   assign oq_tdata = i_tdata[WIDTH-1:0];
+
+   assign oi_tlast = i_tlast;
+   assign oq_tlast = i_tlast;
+
+   assign oi_tvalid = i_tvalid;
+   assign oq_tvalid = i_tvalid;
+
+   assign i_tready = oi_tready;
+
+   assign  error = oi_tready ^ oq_tready;
+   
+endmodule // split_complex
+
diff --git a/fpga/usrp3/lib/rfnoc/split_stream.v b/fpga/usrp3/lib/rfnoc/split_stream.v
new file mode 100644
index 000000000..ae24ca1f8
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/split_stream.v
@@ -0,0 +1,30 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module split_stream
+  #(parameter WIDTH=16,
+    parameter ACTIVE_MASK=4'b1111)
+   (input clk, input reset, input clear,  // These are not used in plain split_stream
+    input [WIDTH-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
+    output [WIDTH-1:0] o0_tdata, output o0_tlast, output o0_tvalid, input o0_tready,
+    output [WIDTH-1:0] o1_tdata, output o1_tlast, output o1_tvalid, input o1_tready,
+    output [WIDTH-1:0] o2_tdata, output o2_tlast, output o2_tvalid, input o2_tready,
+    output [WIDTH-1:0] o3_tdata, output o3_tlast, output o3_tvalid, input o3_tready);
+
+   assign { o0_tlast, o0_tdata } = { i_tlast, i_tdata };
+   assign { o1_tlast, o1_tdata } = { i_tlast, i_tdata };
+   assign { o2_tlast, o2_tdata } = { i_tlast, i_tdata };
+   assign { o3_tlast, o3_tdata } = { i_tlast, i_tdata };
+
+   // NOTE -- this violates the AXI spec because tvalids are dependent on treadys.
+   //   It will be ok most of the time, but muxes and demuxes will need a fifo in 
+   //   the middle to avoid deadlock
+   
+   assign i_tready = ~|(~{o3_tready,o2_tready,o1_tready,o0_tready} & ACTIVE_MASK);
+   assign { o3_tvalid, o2_tvalid, o1_tvalid, o0_tvalid } = {4{i_tready & i_tvalid}};
+   
+endmodule // split_stream
diff --git a/fpga/usrp3/lib/rfnoc/split_stream_fifo.v b/fpga/usrp3/lib/rfnoc/split_stream_fifo.v
new file mode 100644
index 000000000..d99ec115a
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/split_stream_fifo.v
@@ -0,0 +1,59 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module split_stream_fifo
+  #(parameter WIDTH=16,
+    parameter FIFO_SIZE=5,
+    parameter ACTIVE_MASK=4'b1111)
+   (input clk, input reset, input clear,
+    input [WIDTH-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
+    output [WIDTH-1:0] o0_tdata, output o0_tlast, output o0_tvalid, input o0_tready,
+    output [WIDTH-1:0] o1_tdata, output o1_tlast, output o1_tvalid, input o1_tready,
+    output [WIDTH-1:0] o2_tdata, output o2_tlast, output o2_tvalid, input o2_tready,
+    output [WIDTH-1:0] o3_tdata, output o3_tlast, output o3_tvalid, input o3_tready);
+
+   wire [WIDTH-1:0]    o0_tdata_int, o1_tdata_int, o2_tdata_int, o3_tdata_int;
+   wire 	       o0_tlast_int, o1_tlast_int, o2_tlast_int, o3_tlast_int;
+   wire 	       o0_tvalid_int, o1_tvalid_int, o2_tvalid_int, o3_tvalid_int;
+   wire 	       o0_tready_int, o1_tready_int, o2_tready_int, o3_tready_int;
+   
+   split_stream #(.WIDTH(WIDTH), .ACTIVE_MASK(ACTIVE_MASK)) split_stream
+     (.clk(clk), .reset(reset), .clear(clear),
+      .i_tdata(i_tdata), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready),
+      .o0_tdata(o0_tdata_int), .o0_tlast(o0_tlast_int), .o0_tvalid(o0_tvalid_int), .o0_tready(o0_tready_int),
+      .o1_tdata(o1_tdata_int), .o1_tlast(o1_tlast_int), .o1_tvalid(o1_tvalid_int), .o1_tready(o1_tready_int),
+      .o2_tdata(o2_tdata_int), .o2_tlast(o2_tlast_int), .o2_tvalid(o2_tvalid_int), .o2_tready(o2_tready_int),
+      .o3_tdata(o3_tdata_int), .o3_tlast(o3_tlast_int), .o3_tvalid(o3_tvalid_int), .o3_tready(o3_tready_int));
+
+   generate
+      if(ACTIVE_MASK[0])
+	axi_fifo #(.WIDTH(WIDTH+1), .SIZE(FIFO_SIZE)) axi_fifo0
+	  (.clk(clk), .reset(reset), .clear(clear),
+	   .i_tdata({o0_tlast_int, o0_tdata_int}), .i_tvalid(o0_tvalid_int), .i_tready(o0_tready_int),
+	   .o_tdata({o0_tlast, o0_tdata}), .o_tvalid(o0_tvalid), .o_tready(o0_tready),
+	   .occupied(), .space());
+      if(ACTIVE_MASK[1])
+	axi_fifo #(.WIDTH(WIDTH+1), .SIZE(FIFO_SIZE)) axi_fifo1
+	  (.clk(clk), .reset(reset), .clear(clear),
+	   .i_tdata({o1_tlast_int, o1_tdata_int}), .i_tvalid(o1_tvalid_int), .i_tready(o1_tready_int),
+	   .o_tdata({o1_tlast, o1_tdata}), .o_tvalid(o1_tvalid), .o_tready(o1_tready),
+	   .occupied(), .space());
+      if(ACTIVE_MASK[2])
+	axi_fifo #(.WIDTH(WIDTH+1), .SIZE(FIFO_SIZE)) axi_fifo2
+	  (.clk(clk), .reset(reset), .clear(clear),
+	   .i_tdata({o2_tlast_int, o2_tdata_int}), .i_tvalid(o2_tvalid_int), .i_tready(o2_tready_int),
+	   .o_tdata({o2_tlast, o2_tdata}), .o_tvalid(o2_tvalid), .o_tready(o2_tready),
+	   .occupied(), .space());
+      if(ACTIVE_MASK[3])
+	axi_fifo #(.WIDTH(WIDTH+1), .SIZE(FIFO_SIZE)) axi_fifo3
+	  (.clk(clk), .reset(reset), .clear(clear),
+	   .i_tdata({o3_tlast_int, o3_tdata_int}), .i_tvalid(o3_tvalid_int), .i_tready(o3_tready_int),
+	   .o_tdata({o3_tlast, o3_tdata}), .o_tvalid(o3_tvalid), .o_tready(o3_tready),
+	   .occupied(), .space());
+   endgenerate
+      
+endmodule // split_stream_fifo
diff --git a/fpga/usrp3/lib/rfnoc/utils/Makefile.srcs b/fpga/usrp3/lib/rfnoc/utils/Makefile.srcs
new file mode 100644
index 000000000..c8fb9648f
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/utils/Makefile.srcs
@@ -0,0 +1,29 @@
+#
+# Copyright 2018 Ettus Research, A National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+##################################################
+# RFNoC Utility Sources
+##################################################
+RFNOC_UTIL_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/rfnoc/utils/, \
+chdr_trim_payload.v \
+chdr_pad_packet.v \
+context_handler_sync.v \
+context_builder.v \
+context_parser.v \
+ctrlport_timer.v \
+ctrlport_combiner.v \
+ctrlport_decoder.v \
+ctrlport_decoder_param.v \
+ctrlport_splitter.v \
+ctrlport_resp_combine.v \
+ctrlport_clk_cross.v \
+ctrlport_reg_rw.v \
+ctrlport_reg_ro.v \
+ctrlport_to_settings_bus.v \
+noc_shell_generic_ctrlport_pyld_chdr.v \
+timekeeper.v \
+ctrlport_terminator.v \
+))
diff --git a/fpga/usrp3/lib/rfnoc/utils/axis_ctrlport_reg.v b/fpga/usrp3/lib/rfnoc/utils/axis_ctrlport_reg.v
new file mode 100644
index 000000000..52a372a62
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/utils/axis_ctrlport_reg.v
@@ -0,0 +1,143 @@
+//
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module:  axis_ctrlport_reg
+//
+// Description:
+//
+//   Converts control port writes to an AXI-stream data stream. Flow control is 
+//   handled by pushing back on the ctrlport interface (i.e., by not 
+//   acknowledging ctrlport writes until the AXI-stream data is accepted).
+//
+// Parameters:
+//
+//   ADDR           : Writes to this address will makeup the payload of the 
+//                    packet.
+//
+//   USE_ADDR_LAST  : Indicate if we the ADDR_LAST register generated. Set to 1 
+//                    if TLAST is needed.
+//
+//   ADDR_LAST      : A write to this address will complete the packet (output 
+//                    the last word with TLAST asserted).
+//
+//   DWIDTH         : Width of the AXI-stream data bus
+//
+//   USE_FIFO       : Indicate if you want a FIFO to be inserted before the output.
+//
+//   FIFm_SIZE      : The FIFO depth will be 2^FIFm_SIZE
+//
+//   DATA_AT_RESET  : Value of TDATA at reset.
+//
+//   VALID_AT_RESET : State of TVALID at reset.
+//
+//   LAST_AT_RESET  : State of TLAST at reset.
+//
+
+module axis_ctrlport_reg #(
+  parameter ADDR           = 0,
+  parameter USE_ADDR_LAST  = 0,
+  parameter ADDR_LAST      = ADDR+1,
+  parameter DWIDTH         = 32,
+  parameter USE_FIFO       = 0,
+  parameter FIFm_SIZE      = 5,
+  parameter DATA_AT_RESET  = 0,
+  parameter VALID_AT_RESET = 0,
+  parameter LAST_AT_RESET  = 0
+) (
+  input clk,
+  input reset,
+
+  //---------------------------------------------------------------------------
+  // Control Port
+  //---------------------------------------------------------------------------
+
+  // Control Port Slave (Request)
+  input  wire        s_ctrlport_req_wr,
+  input  wire [19:0] s_ctrlport_req_addr,
+  input  wire [31:0] s_ctrlport_req_data,
+
+  // Control Port Slave (Response)
+  output reg         s_ctrlport_resp_ack,
+
+  //---------------------------------------------------------------------------
+  // AXI-Stream Master
+  //---------------------------------------------------------------------------
+
+  // AXI-Stream Output
+  output [DWIDTH-1:0] m_tdata,
+  output              m_tlast,
+  output              m_tvalid,
+  input               m_tready
+);
+
+  reg  [DWIDTH-1:0] m_tdata_int  = DATA_AT_RESET;
+  reg               m_tlast_int  = VALID_AT_RESET;
+  reg               m_tvalid_int = LAST_AT_RESET;
+  wire              m_tready_int;
+
+
+  //---------------------------------------------------------------------------
+  // CtrlPort to AXI-Stream Logic
+  //---------------------------------------------------------------------------
+
+  always @(posedge clk) begin
+    if (reset) begin
+      m_tdata_int         <= DATA_AT_RESET;
+      m_tvalid_int        <= VALID_AT_RESET;
+      m_tlast_int         <= LAST_AT_RESET;
+      s_ctrlport_resp_ack <= 1'b0;
+    end else begin
+      if (m_tvalid_int & m_tready_int) begin
+        s_ctrlport_resp_ack <= 1'b1;
+        m_tvalid_int        <= 1'b0;
+        m_tlast_int         <= 1'b0;
+      end else begin
+        s_ctrlport_resp_ack <= 1'b0;
+      end
+
+      if (s_ctrlport_req_wr) begin
+        if (s_ctrlport_req_addr == ADDR) begin
+          m_tdata_int  <= s_ctrlport_req_data;
+          m_tvalid_int <= 1'b1;
+          m_tlast_int  <= 1'b0;
+        end else if (USE_ADDR_LAST && ADDR_LAST == s_ctrlport_req_addr) begin
+          m_tdata_int  <= s_ctrlport_req_data;
+          m_tvalid_int <= 1'b1;
+          m_tlast_int  <= 1'b1;
+        end
+      end
+    end
+  end
+
+
+  //---------------------------------------------------------------------------
+  // Output FIFO
+  //---------------------------------------------------------------------------
+
+  if (USE_FIFO) begin : gen_fifo
+    axi_fifo #(
+      .DWIDTH (DWIDTH+1),
+      .SIZE   (FIFm_SIZE)
+    ) axi_fifo (
+      .clk      (clk),
+      .reset    (reset),
+      .clear    (1'b0),
+      .i_tdata  ({m_tlast_int, m_tdata_int}),
+      .i_tvalid (m_tvalid_int),
+      .i_tready (m_tready_int),
+      .o_tdata  ({m_tlast, m_tdata}),
+      .o_tvalid (m_tvalid),
+      .o_tready (m_tready),
+      .space    (),
+      .occupied ()
+    );
+  end else begin : nm_gen_fifo
+    assign m_tdata      = m_tdata_int;
+    assign m_tlast      = m_tlast_int;
+    assign m_tvalid     = m_tvalid_int;
+    assign m_tready_int = m_tready;
+  end
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/utils/chdr_pad_packet.v b/fpga/usrp3/lib/rfnoc/utils/chdr_pad_packet.v
new file mode 100644
index 000000000..14d63fe74
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/utils/chdr_pad_packet.v
@@ -0,0 +1,132 @@
+//
+// Copyright 2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: chdr_pad_packet
+// Description:
+//  This module pads extra data on the AXI-Stream bus
+//  to the requested packet size. This module is for
+//  creating len-sized packets, for DMA engines that
+//  do not support partial transfers.
+//
+// Parameters:
+//  - CHDR_W: Width of the CHDR tdata bus in bits
+//
+// Signals:
+//  - s_axis_* : Input AXI-Stream CHDR bus
+//  - m_axis_* : Output AXI-Stream CHDR bus
+//  - len      : Requested number of CHDR_W lines in the packet (must be > 1)
+
+`default_nettype none
+module chdr_pad_packet #(
+  parameter CHDR_W = 256
+)(
+  input  wire              clk,
+  input  wire              rst,
+  input  wire [15:0]       len,
+  input  wire [CHDR_W-1:0] s_axis_tdata,
+  input  wire              s_axis_tlast,
+  input  wire              s_axis_tvalid,
+  output reg               s_axis_tready,
+  output wire [CHDR_W-1:0] m_axis_tdata,
+  output reg               m_axis_tlast,
+  output reg               m_axis_tvalid,
+  input  wire              m_axis_tready
+);
+
+  localparam [1:0] ST_HEADER = 2'd0;
+  localparam [1:0] ST_BODY   = 2'd1;
+  localparam [1:0] ST_PAD    = 2'd2;
+  localparam [1:0] ST_DROP   = 2'd3;
+
+  reg [1:0]   state;
+  reg [15:0]  lines_left;
+
+  always @(posedge clk) begin
+    if (rst || (len <= 16'd1)) begin
+      state <= ST_HEADER;
+    end else begin
+      case(state)
+        ST_HEADER: begin
+          lines_left <= len - 16'd1;
+          if (s_axis_tvalid && m_axis_tready) begin
+              if (!s_axis_tlast) begin
+                // Packet is more than one line and length not reached
+                state <= ST_BODY;
+              end else begin
+                // Packet is only one line and length not reached
+                state <= ST_PAD;
+              end
+          end
+        end
+        ST_BODY: begin
+          if (s_axis_tvalid && m_axis_tready) begin
+            lines_left <= lines_left - 16'd1;
+            if (s_axis_tlast && (lines_left == 16'd1)) begin
+              // End of input and reached length
+              state <= ST_HEADER;
+            end else if (s_axis_tlast && (lines_left != 16'd1)) begin
+              // End of input, but length not reached
+              state <= ST_PAD;
+            end else if (!s_axis_tlast && (lines_left == 16'd1)) begin
+              // Reached length, but input continues...
+              state <= ST_DROP;
+            end
+          end
+        end
+        ST_PAD: begin
+          if (m_axis_tready) begin
+            lines_left <= lines_left - 16'd1;
+            if (lines_left == 16'd1) begin
+              state <= ST_HEADER;
+            end
+          end
+        end
+        ST_DROP: begin
+          if (s_axis_tvalid && s_axis_tlast) begin
+            state <= ST_HEADER;
+          end
+        end
+        default: begin
+          // We should never get here
+          state <= ST_HEADER;
+        end
+      endcase
+    end
+  end
+
+  assign m_axis_tdata  = s_axis_tdata;
+
+  always @(*) begin
+    case(state)
+      ST_HEADER: begin
+        if (len <= 16'd1) begin
+          s_axis_tready <= 1'b0;
+          m_axis_tvalid <= 1'b0;
+        end else begin
+          s_axis_tready <= m_axis_tready;
+          m_axis_tvalid <= s_axis_tvalid;
+        end
+        m_axis_tlast <= 1'b0;
+      end
+      ST_BODY: begin
+        s_axis_tready <= m_axis_tready;
+        m_axis_tvalid <= s_axis_tvalid;
+        m_axis_tlast  <= (lines_left == 16'd1);
+      end
+      ST_PAD: begin
+        s_axis_tready <= 1'b0;
+        m_axis_tvalid <= 1'b1;
+        m_axis_tlast  <= (lines_left == 16'd1);
+      end
+      ST_DROP: begin
+        s_axis_tready <= 1'b1;
+        m_axis_tvalid <= 1'b0;
+        m_axis_tlast  <= 1'b0;
+      end
+    endcase
+  end
+
+endmodule // chdr_pad_packet
+`default_nettype wire
diff --git a/fpga/usrp3/lib/rfnoc/utils/chdr_trim_payload.v b/fpga/usrp3/lib/rfnoc/utils/chdr_trim_payload.v
new file mode 100644
index 000000000..ffeec1437
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/utils/chdr_trim_payload.v
@@ -0,0 +1,97 @@
+//
+// Copyright 2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: chdr_trim_payload
+// Description:
+//  This module trims any extra data on the AXI-Stream
+//  bus to the CHDR payload size. This ensures that the
+//  line with tlast is the actual last line of the packet
+//
+// Parameters:
+//  - CHDR_W: Width of the CHDR tdata bus in bits
+//  - USER_W: Width of the tuser bus in bits
+//
+// Signals:
+//  - s_axis_* : Input AXI-Stream CHDR bus
+//  - m_axis_* : Output AXI-Stream CHDR bus
+
+module chdr_trim_payload #(
+  parameter CHDR_W = 256,
+  parameter USER_W = 16
+)(
+  input  wire              clk,
+  input  wire              rst,
+  input  wire [CHDR_W-1:0] s_axis_tdata,
+  input  wire [USER_W-1:0] s_axis_tuser,
+  input  wire              s_axis_tlast,
+  input  wire              s_axis_tvalid,
+  output wire              s_axis_tready,
+  output wire [CHDR_W-1:0] m_axis_tdata,
+  output wire [USER_W-1:0] m_axis_tuser,
+  output wire              m_axis_tlast,
+  output wire              m_axis_tvalid,
+  input  wire              m_axis_tready
+);
+
+  `include "../core/rfnoc_chdr_utils.vh"
+
+  localparam LOG2_CHDR_W_BYTES = $clog2(CHDR_W/8);
+
+  localparam [1:0] ST_HEADER = 2'd0;
+  localparam [1:0] ST_BODY   = 2'd1;
+  localparam [1:0] ST_DUMP   = 2'd2;
+
+  reg [1:0]   state;
+  reg [15:0]  lines_left;
+
+  wire [15:0] pkt_length = chdr_get_length(s_axis_tdata[63:0]);
+  wire [15:0] lines_in_pkt = pkt_length[15:LOG2_CHDR_W_BYTES] + (|pkt_length[LOG2_CHDR_W_BYTES-1:0]);
+  wire        last_line = (lines_left == 16'd0);
+
+  always @(posedge clk) begin
+    if (rst) begin
+      state <= ST_HEADER;
+      lines_left <= 16'd0;
+    end else if(s_axis_tvalid & s_axis_tready) begin
+      case(state)
+        ST_HEADER: begin
+          if ((lines_in_pkt == 16'd1) && !s_axis_tlast) begin
+            // First line is valid, dump rest
+            state <= ST_DUMP;
+          end else begin
+            lines_left <= lines_in_pkt - 16'd2;
+            state <= ST_BODY;
+          end
+        end
+        ST_BODY: begin
+          if (last_line && !s_axis_tlast) begin
+            state <= ST_DUMP;
+          end else if (s_axis_tlast) begin
+            state <= ST_HEADER;
+          end else begin
+            lines_left <= lines_left - 16'd1;
+          end
+        end
+        ST_DUMP: begin
+          if (s_axis_tlast)
+            state <= ST_HEADER;
+        end
+        default: begin
+          // We should never get here
+          state <= ST_HEADER;
+        end
+      endcase
+    end
+  end
+
+  assign m_axis_tdata  = s_axis_tdata;
+  assign m_axis_tuser  = s_axis_tuser;
+  assign m_axis_tlast  = s_axis_tlast ||
+                         ((state == ST_HEADER) && (lines_in_pkt == 16'd1)) ||
+                         ((state == ST_BODY) && last_line);
+  assign m_axis_tvalid = s_axis_tvalid && (state != ST_DUMP);
+  assign s_axis_tready = m_axis_tready || (state == ST_DUMP);
+
+endmodule // chdr_trim_payload
diff --git a/fpga/usrp3/lib/rfnoc/utils/context_builder.v b/fpga/usrp3/lib/rfnoc/utils/context_builder.v
new file mode 100644
index 000000000..83171e831
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/utils/context_builder.v
@@ -0,0 +1,392 @@
+//
+// Copyright 2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: context_builder
+//
+// Description:
+//
+// This module builds the payload and context data streams necessary for RFnoC 
+// communication through an AXI-Stream Raw Data (Simple Interface). It takes as 
+// input an AXI-Stream data bus and sideband buses containing the timestamp and 
+// packet flags.
+//
+// For each AXI-Stream raw data packet that is input, the same data packet will 
+// be output in the payload stream along with the context stream that's 
+// necessary to create a CHDR packet for this data packet.
+//
+// The timestamp and flags must be input coincident with the AXI-Stream data 
+// input. The timestamp and flag inputs will be sampled coincident with the 
+// last word of data in the packet (i.e., when tlast is asserted).
+//
+// In order to determine the length of the packet, the entire packet is 
+// buffered before the header in the context stream is generated. Therefore, 
+// the internal FIFO size (configured by MTU) must be large enough to buffer 
+// the maximum packet size.
+//
+// The maximum number of packets that can be simultaneously buffered in this 
+// block is limited by INFO_FIFO_SIZE, where the maximum number of packets is 
+// 2**INFO_FIFO_SIZE. This must be large enough to handle the expected worse 
+// case, or data flow will stall.
+//
+// Parameters:
+//
+//   CHDR_W         : Width of the CHDR interface (width of context words)
+//   ITEM_W         : Number of samples/items per data word
+//   NIPC           : Number of samples/items per clock cycle
+//   MTU            : Log2 of maximum transfer unit (maximum packet size) in CHDR_W sized words.
+//   INFO_FIFO_SIZE : Size of the internal packet info FIFO is 2**INFO_FIFO_SIZE
+//
+
+module context_builder #(
+  parameter CHDR_W         = 64,
+  parameter ITEM_W         = 32,
+  parameter NIPC           = 2,
+  parameter MTU            = 10,
+  parameter INFO_FIFO_SIZE = 5
+) (
+  input axis_data_clk,
+  input axis_data_rst,
+
+  // Data stream in (AXI-Stream)
+  input  wire [(ITEM_W*NIPC)-1:0] s_axis_tdata,
+  input  wire [         NIPC-1:0] s_axis_tkeep,
+  input  wire                     s_axis_tlast,
+  input  wire                     s_axis_tvalid,
+  output wire                     s_axis_tready,
+  // Sideband info (sampled on the first cycle of the packet)
+  input  wire [             63:0] s_axis_ttimestamp,
+  input  wire                     s_axis_thas_time,
+  input  wire                     s_axis_teov,
+  input  wire                     s_axis_teob,
+
+  // Data stream out (AXI-Stream Payload)
+  output wire [(ITEM_W*NIPC)-1:0] m_axis_payload_tdata,
+  output wire [         NIPC-1:0] m_axis_payload_tkeep,
+  output wire                     m_axis_payload_tlast,
+  output wire                     m_axis_payload_tvalid,
+  input  wire                     m_axis_payload_tready,
+
+  // Data stream out (AXI-Stream Context)
+  output reg  [CHDR_W-1:0] m_axis_context_tdata,
+  output reg  [       3:0] m_axis_context_tuser,
+  output reg               m_axis_context_tlast,
+  output reg               m_axis_context_tvalid = 1'b0,
+  input  wire              m_axis_context_tready
+);
+  `include "../core/rfnoc_chdr_utils.vh"
+
+
+  reg packet_info_fifo_full;
+
+
+  //---------------------------------------------------------------------------
+  // Data FIFO
+  //---------------------------------------------------------------------------
+  //
+  // This FIFO buffers packet data while we calculate each packet's length.
+  //
+  //---------------------------------------------------------------------------
+
+  wire s_axis_tvalid_df;
+  wire s_axis_tready_df;
+
+  // Compute MTU (maximum packet) size in data words from the CHDR word MTU.
+  localparam DATA_FIFO_SIZE = MTU + $clog2(CHDR_W) - $clog2(ITEM_W*NIPC);
+
+  axi_fifo #(
+    .WIDTH (NIPC + 1 + ITEM_W*NIPC),
+    .SIZE  (DATA_FIFO_SIZE)
+  ) data_fifo (
+    .clk      (axis_data_clk),
+    .reset    (axis_data_rst),
+    .clear    (1'b0),
+    .i_tdata  ({s_axis_tkeep, s_axis_tlast, s_axis_tdata}),
+    .i_tvalid (s_axis_tvalid_df),
+    .i_tready (s_axis_tready_df),
+    .o_tdata  ({m_axis_payload_tkeep, m_axis_payload_tlast, m_axis_payload_tdata}),
+    .o_tvalid (m_axis_payload_tvalid),
+    .o_tready (m_axis_payload_tready),
+    .space    (),
+    .occupied ()
+  );
+
+  // To prevent the packet info FIFO from overflowing, we block the input of
+  // new packets to the data FIFO whenever the packet info FIFO fills up.
+  assign s_axis_tready    = s_axis_tready_df & ~packet_info_fifo_full;
+  assign s_axis_tvalid_df = s_axis_tvalid    & ~packet_info_fifo_full;
+
+
+  //---------------------------------------------------------------------------
+  // Timestamp and Flags Capture
+  //---------------------------------------------------------------------------
+  //
+  // The timestamp and flags that we use for each packet is that of the last 
+  // data word. This maintains compatibility with how tuser was used on old 
+  // RFnoC. Here, we capture this information at the start of the packet. At 
+  // the end of the packet, when the length is known, this value will be 
+  // inserted into the packet info FIFO.
+  //
+  //---------------------------------------------------------------------------
+
+  reg [63:0] packet_timestamp;
+  reg        packet_has_time;
+  reg        packet_eov;
+  reg        packet_eob;
+
+  always @(posedge axis_data_clk) begin
+    if (s_axis_tvalid & s_axis_tready & s_axis_tlast) begin
+      packet_timestamp <= s_axis_ttimestamp;
+      packet_has_time  <= s_axis_thas_time;
+      packet_eov       <= s_axis_teov;
+      packet_eob       <= s_axis_teob;
+    end
+  end
+
+
+  //---------------------------------------------------------------------------
+  // Length Counter
+  //---------------------------------------------------------------------------
+  //
+  // Here We track the state of the incoming packet to determine its length.
+  //
+  //---------------------------------------------------------------------------
+
+  reg [15:0] packet_length, length_count;
+  reg        packet_length_valid;
+
+  always @(posedge axis_data_clk) begin : length_counter
+    if (axis_data_rst) begin
+      length_count        <= 0;
+      packet_length       <= 0;
+      packet_length_valid <= 1'b0;
+    end else begin : length_counter_main
+      // Calculate the length of this word in bytes, taking tkeep into account
+      integer i;
+      integer num_bytes;
+      num_bytes = 0;
+      for (i = 0; i < NIPC; i = i + 1) begin
+        num_bytes = num_bytes + (s_axis_tkeep[i]*(ITEM_W/8));
+      end
+
+      // Update the packet length if the word is accepted
+      packet_length_valid <= 1'b0;
+      if (s_axis_tvalid & s_axis_tready) begin
+        length_count  <= length_count + num_bytes;
+
+        if (s_axis_tlast) begin
+          length_count        <= 0;
+          packet_length       <= length_count + num_bytes;
+          packet_length_valid <= 1'b1;
+        end
+      end
+    end
+  end
+
+
+  //---------------------------------------------------------------------------
+  // Packet Info FIFO
+  //---------------------------------------------------------------------------
+  //
+  // This FIFO stores the packet info (length, timestamp, flags) for each fully 
+  // received packet. Due to AXI-Stream flow control, we may end up with 
+  // multiple packets being buffered in the data_fifo. The packet_info_fifo 
+  // here stores each packet's info until the packet is ready to go out.
+  //
+  //---------------------------------------------------------------------------
+
+  wire [63:0] next_packet_timestamp;
+  wire        next_packet_has_time;
+  wire        next_packet_eob;
+  wire        next_packet_eov;
+  wire [15:0] next_packet_length;
+  wire [15:0] packet_info_space;
+  wire        packet_info_valid;
+  reg         packet_info_ready = 1'b0;
+
+  axi_fifo #(
+    .WIDTH (3 + 64 + 16),
+    .SIZE  (INFO_FIFO_SIZE)
+  ) packet_info_fifo (
+    .clk      (axis_data_clk),
+    .reset    (axis_data_rst),
+    .clear    (1'b0),
+    .i_tdata  ({packet_eov,
+                packet_eob,
+                packet_has_time,
+                packet_timestamp,
+                packet_length}),
+    .i_tvalid (packet_length_valid),
+    .i_tready (),
+    .o_tdata  ({next_packet_eov,
+                next_packet_eob,
+                next_packet_has_time,
+                next_packet_timestamp,
+                next_packet_length}),
+    .o_tvalid (packet_info_valid),
+    .o_tready (packet_info_ready),
+    .space    (packet_info_space),
+    .occupied ()
+  );
+
+
+  // Create a register to indicate when the FIFO is (almost) full. We leave 
+  // some space so that we can accept a new packet during the delay before data 
+  // transfer gets blocked.
+  always @(posedge axis_data_clk) begin
+    if (axis_data_rst) begin
+      packet_info_fifo_full <= 1'b0;
+    end else begin
+      if (packet_info_space < 4) begin
+        packet_info_fifo_full <= 1'b1;
+      end else begin
+        packet_info_fifo_full <= 1'b0;
+      end
+    end
+  end
+
+
+  //---------------------------------------------------------------------------
+  // Context State Machine
+  //---------------------------------------------------------------------------
+  //
+  // This state machine controls generation of the context packets (containing 
+  // the header and timestamp) that are output on m_axis_context, which will be 
+  // needed to create the CHDR packet.
+  //
+  //---------------------------------------------------------------------------
+
+  localparam ST_IDLE         = 0;
+  localparam ST_HEADER       = 1;
+  localparam ST_TIMESTAMP    = 2;
+
+  reg [ 1:0] state   = ST_IDLE; // Current context FSM state
+  reg [15:0] seq_num = 0;       // CHDR sequence number
+
+  reg [15:0] chdr_length;
+  reg [ 2:0] chdr_pkt_type;
+  reg [63:0] chdr_header;
+
+
+  always @(*) begin : calc_chdr_header
+    // Calculate byte length of the CHDR packet by adding the header and 
+    // timestamp length to the length of the payload.
+    if (CHDR_W == 64) begin
+      // If CHDR_W is 64-bit, timestamp is in a separate word
+      if (next_packet_has_time) begin
+        chdr_length = next_packet_length + 16;      // Add two 64-bit CHDR words
+      end else begin
+        chdr_length = next_packet_length + 8;       // Add one 64-bit CHDR word
+      end
+    end else begin
+      // If CHDR_W is 128-bit or larger, timestamp is in the same word as the header
+      chdr_length = next_packet_length + CHDR_W/8;  // Add one CHDR word
+    end
+
+    // Determine the packet type
+    if (next_packet_has_time) begin
+      chdr_pkt_type = CHDR_PKT_TYPE_DATA_TS;
+    end else begin
+      chdr_pkt_type = CHDR_PKT_TYPE_DATA;
+    end
+
+    // Build up header
+    chdr_header = chdr_build_header(
+      6'b0,                // vc
+      next_packet_eob,     // eob
+      next_packet_eov,     // eov
+      chdr_pkt_type,       // pkt_type
+      0,                   // num_mdata
+      seq_num,             // seq_num
+      chdr_length,         // length of CHDR packet in bytes
+      0                    // dst_epid
+    );
+  end
+
+
+  always @(posedge axis_data_clk) begin
+    if (axis_data_rst) begin
+      state                 <= ST_IDLE;
+      seq_num               <= 'd0;
+      packet_info_ready     <= 1'b0;
+      m_axis_context_tvalid <= 1'b0;
+    end else begin
+      packet_info_ready <= 1'b0;
+
+      if (CHDR_W == 64) begin : gen_ctx_fsm_64
+        // For 64-bit CHDR_W, we require two words, one for the header and one 
+        // for the timestamp.
+        case (state)
+          ST_IDLE: begin
+            m_axis_context_tdata <= chdr_header;
+            m_axis_context_tuser <= CONTEXT_FIELD_HDR;
+            m_axis_context_tlast <= !next_packet_has_time;
+            if (packet_info_valid && !packet_info_ready) begin
+              m_axis_context_tvalid <= 1'b1;
+              seq_num               <= seq_num + 1;
+              state                 <= ST_HEADER;
+            end
+          end
+
+          ST_HEADER : begin
+            // Wait for header to be accepted
+            if (m_axis_context_tready) begin
+              packet_info_ready    <= 1'b1;
+              m_axis_context_tdata <= next_packet_timestamp;
+              if (next_packet_has_time) begin
+                m_axis_context_tlast <= 1'b1;
+                m_axis_context_tuser <= CONTEXT_FIELD_TS;
+                state                <= ST_TIMESTAMP;
+              end else begin
+                m_axis_context_tlast  <= 1'b0;
+                m_axis_context_tvalid <= 1'b0;
+                state                 <= ST_IDLE;
+              end
+            end
+          end
+
+          ST_TIMESTAMP : begin
+            // Wait for timestamp to be accepted
+            if (m_axis_context_tready) begin
+              m_axis_context_tvalid <= 1'b0;
+              state                 <= ST_IDLE;
+            end
+          end
+
+          default: state <= ST_IDLE;
+        endcase
+
+      end else begin : gen_ctx_fsm_128
+        // For 128-bit and larger CHDR_W, we need the header and timestamp in
+        // the same word.
+        case (state)
+          ST_IDLE: begin
+            m_axis_context_tdata <= { next_packet_timestamp, chdr_header };
+            m_axis_context_tuser <= next_packet_has_time ? CONTEXT_FIELD_HDR_TS :
+                                                           CONTEXT_FIELD_HDR;
+            m_axis_context_tlast <= 1'b1;
+            if (packet_info_valid) begin
+              m_axis_context_tvalid <= 1'b1;
+              seq_num               <= seq_num + 1;
+              packet_info_ready     <= 1'b1;
+              state                 <= ST_HEADER;
+            end
+          end
+
+          ST_HEADER : begin
+            // Wait for header to be accepted
+            if (m_axis_context_tready) begin
+              m_axis_context_tvalid <= 1'b0;
+              state                 <= ST_IDLE;
+            end
+          end
+
+          default : state <= ST_IDLE;
+        endcase
+
+      end
+    end
+  end
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/utils/context_handler_sync.v b/fpga/usrp3/lib/rfnoc/utils/context_handler_sync.v
new file mode 100644
index 000000000..c7f899ee9
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/utils/context_handler_sync.v
@@ -0,0 +1,110 @@
+//
+// Copyright 2018-2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: context_handler_sync
+// Description:
+//
+// Parameters:
+//   - CHDR_W: Width of the input CHDR bus in bits
+//
+// Signals:
+//
+
+module context_handler_sync #(
+  parameter CHDR_W = 256,
+  parameter ITEM_W = 32,
+  parameter NIPC   = 2
+)(
+  // Clock and reset
+  input  wire              clk,
+  input  wire              rst,
+  // Context stream in (AXI-Stream)
+  input  wire [CHDR_W-1:0] s_axis_context_tdata,
+  input  wire [3:0]        s_axis_context_tuser,
+  input  wire              s_axis_context_tlast,
+  input  wire              s_axis_context_tvalid,
+  output wire              s_axis_context_tready,
+  // Context stream out (AXI-Stream)
+  output wire [CHDR_W-1:0] m_axis_context_tdata,
+  output wire [3:0]        m_axis_context_tuser,
+  output wire              m_axis_context_tlast,
+  output wire              m_axis_context_tvalid,
+  input  wire              m_axis_context_tready,
+  // Input payload stream monitor
+  input  wire [NIPC-1:0]   in_payload_tkeep,
+  input  wire              in_payload_tlast,
+  input  wire              in_payload_tvalid,
+  input  wire              in_payload_tready,
+  // Output payload stream monitor
+  input  wire [NIPC-1:0]   out_payload_tkeep,
+  input  wire              out_payload_tlast,
+  input  wire              out_payload_tvalid,
+  input  wire              out_payload_tready,
+  // Status
+  output reg               length_err_stb,
+  output reg               seq_err_stb
+);
+
+  `include "../core/rfnoc_chdr_utils.vh"
+
+  // Thermometer to binary decoder
+  // 4'b0000 => 3'd0
+  // 4'b0001 => 3'd1
+  // 4'b0011 => 3'd2
+  // 4'b0111 => 3'd3
+  // 4'b1111 => 3'd4
+  function [$clog2(NIPC):0] thermo2bin(input [NIPC-1:0] thermo);
+    reg [NIPC:0] onehot;
+    integer i;
+  begin
+    onehot = thermo + 1;
+    thermo2bin = 0;
+    for (i = 0; i <= NIPC; i=i+1)
+      if (onehot[i])
+        thermo2bin = thermo2bin | i;
+  end
+  endfunction
+
+  axi_fifo #(.WIDTH(CHDR_W+4+1), .SIZE(1)) ctxt_pipe_i (
+    .clk(clk), .reset(rst), .clear(1'b0),
+    .i_tdata({s_axis_context_tlast, s_axis_context_tuser, s_axis_context_tdata}),
+    .i_tvalid(s_axis_context_tvalid), .i_tready(s_axis_context_tready),
+    .o_tdata({m_axis_context_tlast, m_axis_context_tuser, m_axis_context_tdata}),
+    .o_tvalid(m_axis_context_tvalid), .o_tready(m_axis_context_tready),
+    .space(), .occupied()
+  );
+
+  wire is_ctxt_hdr = s_axis_context_tvalid && s_axis_context_tready &&
+                     (s_axis_context_tuser == CONTEXT_FIELD_HDR || 
+                      s_axis_context_tuser == CONTEXT_FIELD_HDR_TS);
+
+  reg [15:0] exp_pkt_len = 16'd0;
+  reg [15:0] exp_seq_num = 16'd0;
+  reg        check_seq_num = 1'b0;
+  always @(posedge clk) begin
+    if (rst) begin
+      exp_pkt_len <= 16'd0;
+      check_seq_num <= 1'b0;
+    end else if (is_ctxt_hdr) begin
+      check_seq_num <= 1'b1;
+      exp_pkt_len <= chdr_get_length(s_axis_context_tdata[63:0]);
+      exp_seq_num <= chdr_get_seq_num(s_axis_context_tdata[63:0]) + 16'd1;
+    end
+    seq_err_stb <= is_ctxt_hdr && check_seq_num && 
+                   (exp_seq_num != chdr_get_seq_num(s_axis_context_tdata[63:0]));
+  end
+
+  reg [15:0] pyld_pkt_len = 16'd0;
+  always @(posedge clk) begin
+    if (rst) begin
+      pyld_pkt_len <= 16'd0;
+    end else if (in_payload_tvalid && in_payload_tready) begin
+      pyld_pkt_len <= in_payload_tlast ? 16'd0 : (pyld_pkt_len + ((ITEM_W*NIPC)/8));
+    end
+    length_err_stb <= in_payload_tvalid && in_payload_tready && in_payload_tlast &&
+                      (pyld_pkt_len + (thermo2bin(in_payload_tkeep)*(ITEM_W/8)) != exp_pkt_len);
+  end
+
+endmodule // context_handler_sync
diff --git a/fpga/usrp3/lib/rfnoc/utils/context_parser.v b/fpga/usrp3/lib/rfnoc/utils/context_parser.v
new file mode 100644
index 000000000..2d0759af7
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/utils/context_parser.v
@@ -0,0 +1,230 @@
+//
+// Copyright 2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: context_parser
+//
+// Description:
+//
+// This module extracts the context information from the AXI-Stream Raw Data 
+// (Simple Interface) in RFNoC and outputs it as sideband information for an 
+// AXI-Stream data bus. This includes the timestamp, if present, and packet 
+// flags (EOB, EOV).
+//
+// For each payload and context packet that is input, one data packet will be
+// output along with the sideband data.
+//
+// Parameters:
+//
+//   CHDR_W : Width of the CHDR interface (width of context words)
+//   ITEM_W : Width of each item/sample
+//   NIPC   : Number of items/samples per clock cycle
+//
+
+module context_parser #(
+  parameter CHDR_W = 64,
+  parameter ITEM_W = 32,
+  parameter NIPC   = 2
+) (
+  input axis_data_clk,
+  input axis_data_rst,
+
+  // AXI-Stream Raw Data (Simple Interface) input
+  input  wire [(ITEM_W*NIPC)-1:0] s_axis_payload_tdata,
+  input  wire [         NIPC-1:0] s_axis_payload_tkeep,
+  input  wire                     s_axis_payload_tlast,
+  input  wire                     s_axis_payload_tvalid,
+  output wire                     s_axis_payload_tready,
+  //
+  input  wire [       CHDR_W-1:0] s_axis_context_tdata,
+  input  wire                     s_axis_context_tlast,
+  input  wire                     s_axis_context_tvalid,
+  output wire                     s_axis_context_tready,
+
+  // Data stream out (AXI-Stream)
+  output wire [(ITEM_W*NIPC)-1:0] m_axis_tdata,
+  output wire [         NIPC-1:0] m_axis_tkeep,
+  output wire                     m_axis_tlast,
+  output wire                     m_axis_tvalid,
+  input  wire                     m_axis_tready,
+  // Sideband information
+  output wire [             63:0] m_axis_ttimestamp,
+  output wire                     m_axis_thas_time,
+  output wire [             15:0] m_axis_tlength,      // Payload length, in bytes
+  output wire                     m_axis_teov,
+  output wire                     m_axis_teob
+);
+
+  `include "../core/rfnoc_chdr_utils.vh"
+
+
+  // Sideband-FIFO signals
+  reg  sideband_i_tvalid = 1'b0;
+  wire sideband_i_tready;
+  wire sideband_o_tvalid;
+  wire sideband_o_tready;
+
+  // Sideband data for next packet
+  reg [63:0] timestamp;
+  reg        has_time;
+  reg [15:0] length;
+  reg        eov;
+  reg        eob;
+
+
+  //---------------------------------------------------------------------------
+  // Context State Machine
+  //---------------------------------------------------------------------------
+  //
+  // This state machine parses the context data so that it can be output as
+  // sideband information on the AXI-Stream output.
+  //
+  // This state machine assumes that the context packet is always properly 
+  // formed (i.e., it doesn't explicitly check for and drop malformed packets).
+  //
+  //---------------------------------------------------------------------------
+
+  localparam ST_HEADER    = 0;
+  localparam ST_TIMESTAMP = 1;
+  localparam ST_METADATA  = 2;
+
+  reg [1:0] state = ST_HEADER;
+
+  always @(posedge axis_data_clk) begin
+    if (axis_data_rst) begin
+      state             <= ST_HEADER;
+      sideband_i_tvalid <= 1'b0;
+    end else begin
+      sideband_i_tvalid <= 1'b0;
+
+      case(state)
+        ST_HEADER: begin
+          // Grab header information
+          eov      <= chdr_get_eov(s_axis_context_tdata[63:0]);
+          eob      <= chdr_get_eob(s_axis_context_tdata[63:0]);
+          has_time <= chdr_get_has_time(s_axis_context_tdata[63:0]);
+          length   <= chdr_calc_payload_length(CHDR_W, s_axis_context_tdata[63:0]);
+
+          if (s_axis_context_tvalid && s_axis_context_tready) begin
+            if (CHDR_W > 64) begin
+              // When CHDR_W > 64, the timestamp is a part of the header word
+              if (chdr_get_has_time(s_axis_context_tdata[63:0])) begin
+                timestamp <= s_axis_context_tdata[127:64];
+              end
+
+              // Load the sideband data into the FIFO
+              sideband_i_tvalid <= 1'b1;
+
+              // Check if there's more context packet to wait for
+              if (!s_axis_context_tlast) begin
+                state <= ST_METADATA;
+              end
+
+            end else begin
+              // When CHDR_W == 64, the timestamp comes after the header word
+              if (s_axis_context_tlast) begin
+                // Context packet is ending. Load the sideband data into FIFO.
+                sideband_i_tvalid <= 1'b1;
+              end else begin
+                // More context packet to come
+                if (chdr_get_has_time(s_axis_context_tdata[63:0])) begin
+                  state <= ST_TIMESTAMP;
+                end else begin
+                  // Load the sideband data into the FIFO
+                  sideband_i_tvalid <= 1'b1;
+                  state             <= ST_METADATA;
+                end
+              end
+            end
+          end
+        end
+
+        ST_TIMESTAMP: begin
+          // This state only applies when CHDR_W == 64
+          if (s_axis_context_tvalid && s_axis_context_tready) begin
+            timestamp <= s_axis_context_tdata;
+
+            // Load the sideband data into the FIFO
+            sideband_i_tvalid <= 1'b1;
+
+            // Check if there's more context packet to wait for
+            if (s_axis_context_tlast) begin
+              state <= ST_HEADER;
+            end else begin
+              state <= ST_METADATA;
+            end
+          end
+        end
+
+        ST_METADATA: begin
+          // This module doesn't handle metadata currently, so just ignore it
+          if (s_axis_context_tvalid && s_axis_context_tready) begin
+            if (s_axis_context_tlast) begin
+              state <= ST_HEADER;
+            end
+          end
+        end
+
+        default: state <= ST_HEADER;
+      endcase
+    end
+  end
+
+
+  //---------------------------------------------------------------------------
+  // Sideband Data FIFO
+  //---------------------------------------------------------------------------
+  //
+  // Here we buffer the sideband information into a FIFO. The information will 
+  // be output coincident with the corresponding data packet.
+  //
+  //---------------------------------------------------------------------------
+
+  axi_fifo_short #(
+    .WIDTH (83)
+  ) sideband_fifo (
+    .clk      (axis_data_clk),
+    .reset    (axis_data_rst),
+    .clear    (1'b0),
+    .i_tdata  ({length, eob, eov, has_time, timestamp}),
+    .i_tvalid (sideband_i_tvalid),
+    .i_tready (sideband_i_tready),
+    .o_tdata  ({m_axis_tlength, m_axis_teob, m_axis_teov, 
+                m_axis_thas_time, m_axis_ttimestamp}),
+    .o_tvalid (sideband_o_tvalid),
+    .o_tready (sideband_o_tready),
+    .space    (),
+    .occupied ()
+  );
+
+
+  //---------------------------------------------------------------------------
+  // Payload Transfer Logic
+  //---------------------------------------------------------------------------
+  //
+  // Here we handle the logic for AXI-Stream flow control. The data and 
+  // sideband information are treated as a single AXI-Stream bus. The sideband 
+  // information is output for the duration of the packet and is popped off of 
+  // the sideband FIFO at the end of each packet.
+  //
+  //---------------------------------------------------------------------------
+
+  // We can only accept context info when there's room in the sideband FIFO.
+  assign s_axis_context_tready = sideband_i_tready;
+
+  // Allow payload transfer whenever the sideband info is valid
+  assign s_axis_payload_tready = (m_axis_tready         & sideband_o_tvalid);
+  assign m_axis_tvalid         = (s_axis_payload_tvalid & sideband_o_tvalid);
+
+  // Pop off the sideband info at the end of each packet
+  assign sideband_o_tready = (s_axis_payload_tready &
+                              s_axis_payload_tvalid &
+                              s_axis_payload_tlast);
+
+  // Other AXI-Stream signals pass through untouched
+  assign m_axis_tdata = s_axis_payload_tdata;
+  assign m_axis_tkeep = s_axis_payload_tkeep;
+  assign m_axis_tlast = s_axis_payload_tlast;
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/utils/ctrlport_clk_cross.v b/fpga/usrp3/lib/rfnoc/utils/ctrlport_clk_cross.v
new file mode 100644
index 000000000..6aa74c74f
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/utils/ctrlport_clk_cross.v
@@ -0,0 +1,167 @@
+//
+// Copyright 2019 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module:  ctrlport_clk_cross
+//
+// Description:
+//
+//   Crosses a CTRL Port request and response between two clock domains.
+//
+
+
+module ctrlport_clk_cross (
+
+  input wire rst, // Can be either clock domain, but must be glitch-free
+
+  //---------------------------------------------------------------------------
+  // Input Clock Domain (Slave Interface)
+  //---------------------------------------------------------------------------
+
+  input  wire        s_ctrlport_clk,
+  input  wire        s_ctrlport_req_wr,
+  input  wire        s_ctrlport_req_rd,
+  input  wire [19:0] s_ctrlport_req_addr,
+  input  wire [ 9:0] s_ctrlport_req_portid,
+  input  wire [15:0] s_ctrlport_req_rem_epid,
+  input  wire [ 9:0] s_ctrlport_req_rem_portid,
+  input  wire [31:0] s_ctrlport_req_data,
+  input  wire [ 3:0] s_ctrlport_req_byte_en,
+  input  wire        s_ctrlport_req_has_time,
+  input  wire [63:0] s_ctrlport_req_time,
+  output wire        s_ctrlport_resp_ack,
+  output wire [ 1:0] s_ctrlport_resp_status,
+  output wire [31:0] s_ctrlport_resp_data,
+
+  //---------------------------------------------------------------------------
+  // Output Clock Domain (Master Interface)
+  //---------------------------------------------------------------------------
+
+  input  wire        m_ctrlport_clk,
+  output wire        m_ctrlport_req_wr,
+  output wire        m_ctrlport_req_rd,
+  output wire [19:0] m_ctrlport_req_addr,
+  output wire [ 9:0] m_ctrlport_req_portid,
+  output wire [15:0] m_ctrlport_req_rem_epid,
+  output wire [ 9:0] m_ctrlport_req_rem_portid,
+  output wire [31:0] m_ctrlport_req_data,
+  output wire [ 3:0] m_ctrlport_req_byte_en,
+  output wire        m_ctrlport_req_has_time,
+  output wire [63:0] m_ctrlport_req_time,
+  input  wire        m_ctrlport_resp_ack,
+  input  wire [ 1:0] m_ctrlport_resp_status,
+  input  wire [31:0] m_ctrlport_resp_data
+);
+
+  //---------------------------------------------------------------------------
+  // Slave to Master Clock Crossing (Request)
+  //---------------------------------------------------------------------------
+
+  localparam REQ_W = 
+    1  + // ctrlport_req_wr
+    1  + // ctrlport_req_rd
+    20 + // ctrlport_req_addr
+    10 + // ctrlport_req_portid
+    16 + // ctrlport_req_rem_epid
+    10 + // ctrlport_req_rem_portid
+    32 + // ctrlport_req_data
+    4  + // ctrlport_req_byte_en
+    1  + // ctrlport_req_has_time
+    64;  // ctrlport_req_time
+
+  wire [ REQ_W-1:0] s_req_flat;
+  wire [ REQ_W-1:0] m_req_flat;
+  wire              m_req_flat_valid;
+  wire              m_ctrlport_req_wr_tmp;
+  wire              m_ctrlport_req_rd_tmp;
+
+  assign s_req_flat = {
+    s_ctrlport_req_wr,
+    s_ctrlport_req_rd,
+    s_ctrlport_req_addr,
+    s_ctrlport_req_portid,
+    s_ctrlport_req_rem_epid,
+    s_ctrlport_req_rem_portid,
+    s_ctrlport_req_data,
+    s_ctrlport_req_byte_en,
+    s_ctrlport_req_has_time,
+    s_ctrlport_req_time
+  };
+
+  axi_fifo_2clk #(
+    .WIDTH (REQ_W),
+    .SIZE  (3)
+  ) req_fifo (
+    .reset    (rst),
+    .i_aclk   (s_ctrlport_clk),
+    .i_tdata  (s_req_flat),
+    .i_tvalid (s_ctrlport_req_wr | s_ctrlport_req_rd),
+    .i_tready (),
+    .o_aclk   (m_ctrlport_clk),
+    .o_tdata  (m_req_flat),
+    .o_tready (1'b1),
+    .o_tvalid (m_req_flat_valid)
+  );
+
+  assign {
+    m_ctrlport_req_wr_tmp,
+    m_ctrlport_req_rd_tmp,
+    m_ctrlport_req_addr,
+    m_ctrlport_req_portid,
+    m_ctrlport_req_rem_epid,
+    m_ctrlport_req_rem_portid,
+    m_ctrlport_req_data,
+    m_ctrlport_req_byte_en,
+    m_ctrlport_req_has_time,
+    m_ctrlport_req_time
+  } = m_req_flat;
+
+  assign m_ctrlport_req_wr = m_ctrlport_req_wr_tmp & m_req_flat_valid;
+  assign m_ctrlport_req_rd = m_ctrlport_req_rd_tmp & m_req_flat_valid;
+
+
+  //---------------------------------------------------------------------------
+  // Master to Slave Clock Crossing (Response)
+  //---------------------------------------------------------------------------
+
+  localparam RESP_W = 
+    1  + // ctrlport_resp_ack,
+    2  + // ctrlport_resp_status,
+    32;  // ctrlport_resp_data
+
+  wire [RESP_W-1:0] m_resp_flat;
+  wire [RESP_W-1:0] s_resp_flat;
+  wire              s_resp_flat_valid;
+  wire              s_ctrlport_resp_ack_tmp;
+
+  assign m_resp_flat = {
+    m_ctrlport_resp_ack,
+    m_ctrlport_resp_status,
+    m_ctrlport_resp_data
+  };
+
+  axi_fifo_2clk #(
+    .WIDTH (RESP_W),
+    .SIZE  (3)
+  ) resp_fifo (
+    .reset    (rst),
+    .i_aclk   (m_ctrlport_clk),
+    .i_tdata  (m_resp_flat),
+    .i_tvalid (m_ctrlport_resp_ack),
+    .i_tready (),
+    .o_aclk   (s_ctrlport_clk),
+    .o_tdata  (s_resp_flat),
+    .o_tready (1'b1),
+    .o_tvalid (s_resp_flat_valid)
+  );
+
+  assign {
+    s_ctrlport_resp_ack_tmp,
+    s_ctrlport_resp_status,
+    s_ctrlport_resp_data
+  } = s_resp_flat;
+
+  assign s_ctrlport_resp_ack = s_ctrlport_resp_ack_tmp & s_resp_flat_valid;
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/utils/ctrlport_combiner.v b/fpga/usrp3/lib/rfnoc/utils/ctrlport_combiner.v
new file mode 100644
index 000000000..591fadc27
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/utils/ctrlport_combiner.v
@@ -0,0 +1,222 @@
+//
+// Copyright 2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: ctrlport_combiner
+//
+// Description:
+//
+// This block is an arbiter that merges control-port interfaces. This block is 
+// used when you have multiple control-port masters that need to access a 
+// single slave. For example, a NoC block with multiple submodules that each 
+// need to read and/or write registers outside of themselves.
+//
+// This module combines the control-port requests from multiple masters into a 
+// single request for one slave. Simultaneous requests are handled in the order 
+// specified by PRIORITY. The responding ACK is routed back to the requester.
+//
+// Parameters:
+//
+//   NUM_MASTERS : The number of control-port masters to connect to a single 
+//                 control-port slave.
+//   PRIORITY    : Use PRIORITY = 0 for round robin arbitration, PRIORITY = 1 
+//                 for priority arbitration (lowest number port serviced first).
+//
+
+
+module ctrlport_combiner #(
+  parameter NUM_MASTERS = 2,
+  parameter PRIORITY    = 0
+) (
+  input wire ctrlport_clk,
+  input wire ctrlport_rst,
+
+  // Requests from multiple masters
+  input  wire [   NUM_MASTERS-1:0] s_ctrlport_req_wr,
+  input  wire [   NUM_MASTERS-1:0] s_ctrlport_req_rd,
+  input  wire [20*NUM_MASTERS-1:0] s_ctrlport_req_addr,
+  input  wire [10*NUM_MASTERS-1:0] s_ctrlport_req_portid,
+  input  wire [16*NUM_MASTERS-1:0] s_ctrlport_req_rem_epid,
+  input  wire [10*NUM_MASTERS-1:0] s_ctrlport_req_rem_portid,
+  input  wire [32*NUM_MASTERS-1:0] s_ctrlport_req_data,
+  input  wire [ 4*NUM_MASTERS-1:0] s_ctrlport_req_byte_en,
+  input  wire [   NUM_MASTERS-1:0] s_ctrlport_req_has_time,
+  input  wire [64*NUM_MASTERS-1:0] s_ctrlport_req_time,
+  // Responses to multiple masters
+  output reg  [   NUM_MASTERS-1:0] s_ctrlport_resp_ack,
+  output reg  [ 2*NUM_MASTERS-1:0] s_ctrlport_resp_status,
+  output reg  [32*NUM_MASTERS-1:0] s_ctrlport_resp_data,
+
+  // Request to a single slave
+  output reg         m_ctrlport_req_wr,
+  output reg         m_ctrlport_req_rd,
+  output reg  [19:0] m_ctrlport_req_addr,
+  output reg  [ 9:0] m_ctrlport_req_portid,
+  output reg  [15:0] m_ctrlport_req_rem_epid,
+  output reg  [ 9:0] m_ctrlport_req_rem_portid,
+  output reg  [31:0] m_ctrlport_req_data,
+  output reg  [ 3:0] m_ctrlport_req_byte_en,
+  output reg         m_ctrlport_req_has_time,
+  output reg  [63:0] m_ctrlport_req_time,
+  // Response from a single slave
+  input  wire        m_ctrlport_resp_ack,
+  input  wire [ 1:0] m_ctrlport_resp_status,
+  input  wire [31:0] m_ctrlport_resp_data
+);
+
+  reg [$clog2(NUM_MASTERS)-1:0] slave_sel = 0;  // Tracks which slave port is
+                                                // currently being serviced.
+  reg req_load_output = 1'b0;
+
+
+  //---------------------------------------------------------------------------
+  // Input Registers
+  //---------------------------------------------------------------------------
+  //
+  // Latch each request until it can be serviced. Only one request per slave
+  // can be in progress at a time.
+  //
+  //---------------------------------------------------------------------------
+
+  reg [   NUM_MASTERS-1:0] req_valid = 0;
+  reg [   NUM_MASTERS-1:0] req_wr;
+  reg [   NUM_MASTERS-1:0] req_rd;
+  reg [20*NUM_MASTERS-1:0] req_addr;
+  reg [10*NUM_MASTERS-1:0] req_portid;
+  reg [16*NUM_MASTERS-1:0] req_rem_epid;
+  reg [10*NUM_MASTERS-1:0] req_rem_portid;
+  reg [32*NUM_MASTERS-1:0] req_data;
+  reg [ 4*NUM_MASTERS-1:0] req_byte_en;
+  reg [   NUM_MASTERS-1:0] req_has_time;
+  reg [64*NUM_MASTERS-1:0] req_time;
+
+  always @(posedge ctrlport_clk) begin
+    if (ctrlport_rst) begin
+      req_valid <= 0;
+    end else begin : input_reg_gen
+      integer i;
+      for (i = 0; i < NUM_MASTERS; i = i + 1) begin
+        if (s_ctrlport_req_wr[i] | s_ctrlport_req_rd[i]) begin
+          // Mark this slave's request valid and save the request information
+          req_valid[i]             <= 1'b1;
+          req_wr[i]                <= s_ctrlport_req_wr[i];
+          req_rd[i]                <= s_ctrlport_req_rd[i];
+          req_addr[20*i+:20]       <= s_ctrlport_req_addr[20*i+:20];
+          req_portid[10*i+:10]     <= s_ctrlport_req_portid[10*i+:10];
+          req_rem_epid[16*i+:16]   <= s_ctrlport_req_rem_epid[16*i+:16];
+          req_rem_portid[10*i+:10] <= s_ctrlport_req_rem_portid[10*i+:10];
+          req_data[32*i+:32]       <= s_ctrlport_req_data[32*i+:32];
+          req_byte_en[4*i+:4]      <= s_ctrlport_req_byte_en[4*i+:4];
+          req_has_time[i]          <= s_ctrlport_req_has_time[i];
+          req_time[64*i+:64]       <= s_ctrlport_req_time[64*i+:64];
+        end
+      end
+
+      // Clear the active request when it gets output
+      if (req_load_output) begin
+        req_valid[slave_sel] <= 1'b0;
+      end
+    end
+  end
+
+
+  //---------------------------------------------------------------------------
+  // Arbitration State Machine
+  //---------------------------------------------------------------------------
+  //
+  // This state machine tracks which slave port is being serviced and which to
+  // service next. This is done using a counter that simply checks each port in
+  // sequential order and then stops when it finds one that has a valid request.
+  //
+  //---------------------------------------------------------------------------
+
+  reg req_active = 0;  // Indicates if there's a request being serviced
+
+  always @(posedge ctrlport_clk) begin
+    if (ctrlport_rst) begin
+      slave_sel       <= 0;
+      req_active      <= 1'b0;
+      req_load_output <= 1'b0;
+    end else begin
+      req_load_output <= 1'b0;
+
+      if (req_active) begin
+        // Wait until we get the response before we allow another request
+        if (m_ctrlport_resp_ack) begin
+          req_active <= 1'b0;
+
+          // Go to the next slave so we don't service the same slave again
+          if(PRIORITY == 1 || slave_sel == NUM_MASTERS-1)
+            slave_sel <= 0;
+          else
+            slave_sel <= slave_sel + 1;
+        end
+      end else begin
+        // No active request in progress, so check if there's a new request on
+        // the selected slave.
+        if (req_valid[slave_sel]) begin
+          req_active      <= 1'b1;
+          req_load_output <= 1'b1;
+        end else begin
+          // Nothing from this slave, so move to the next slave.
+          if (slave_sel == NUM_MASTERS-1)
+            slave_sel <= 0;
+          else
+            slave_sel <= slave_sel + 1;
+        end
+      end
+    end
+  end
+
+
+  //---------------------------------------------------------------------------
+  // Output Register
+  //---------------------------------------------------------------------------
+  //
+  // Here we load the active request for a single clock cycle and demultiplex 
+  // the response back to the requesting master.
+  //
+  //---------------------------------------------------------------------------
+
+  always @(posedge ctrlport_clk) begin
+    if (ctrlport_rst) begin
+      m_ctrlport_req_wr <= 1'b0;
+      m_ctrlport_req_rd <= 1'b0;
+    end else begin : output_reg_gen
+      integer i;
+
+      // Load the active request
+      if (req_load_output) begin
+        m_ctrlport_req_wr         <= req_wr        [slave_sel];
+        m_ctrlport_req_rd         <= req_rd        [slave_sel];
+        m_ctrlport_req_addr       <= req_addr      [20*slave_sel +: 20];
+        m_ctrlport_req_portid     <= req_portid    [10*slave_sel +: 10];
+        m_ctrlport_req_rem_epid   <= req_rem_epid  [16*slave_sel +: 16];
+        m_ctrlport_req_rem_portid <= req_rem_portid[10*slave_sel +: 10];
+        m_ctrlport_req_data       <= req_data      [32*slave_sel +: 32];
+        m_ctrlport_req_byte_en    <= req_byte_en   [ 4*slave_sel +: 4];
+        m_ctrlport_req_has_time   <= req_has_time  [slave_sel];
+        m_ctrlport_req_time       <= req_time      [64*slave_sel +: 64];
+      end else begin
+        m_ctrlport_req_wr <= 1'b0;
+        m_ctrlport_req_rd <= 1'b0;
+      end
+
+      // Output any response to the master that made the request
+      for (i = 0; i < NUM_MASTERS; i = i + 1) begin
+        // Give the response data to all the slaves (no demux, to save logic)
+        s_ctrlport_resp_status[2*i +: 2] <= m_ctrlport_resp_status;
+        s_ctrlport_resp_data[32*i +: 32] <= m_ctrlport_resp_data;
+
+        // Give the ack only to the master that made the request (use a demux)
+        if (i == slave_sel && m_ctrlport_resp_ack) begin
+          s_ctrlport_resp_ack[i] <= 1'b1;
+        end else begin
+          s_ctrlport_resp_ack[i] <= 1'b0;
+        end
+      end
+    end
+  end
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/utils/ctrlport_decoder.v b/fpga/usrp3/lib/rfnoc/utils/ctrlport_decoder.v
new file mode 100644
index 000000000..74cdb307a
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/utils/ctrlport_decoder.v
@@ -0,0 +1,151 @@
+//
+// Copyright 2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: ctrlport_decoder
+//
+// Description:
+//
+// This block splits a single control port interface into multiple. It is used
+// when you have a single master that needs to access multiple slaves.  For
+// example, a NoC block where the registers are implemented in multiple
+// submodules that must be read/written by a single NoC shell.
+//
+// This version also implements address decoding. The request is passed to a 
+// slave only if the address falls within that slave's address space. Each 
+// slave is given an address space of 2**ADDR_W and the first slave starts at 
+// address BASE_ADDR. In other words, the request address is partitioned as 
+// shown below. 
+//
+//   |---------------- 32-bit -----------------|
+//   |    Base     | Port Num |  Slave Addr    |
+//   |-----------------------------------------|
+//
+// When passed to the slave, the base address and port number bits are stripped 
+// from the request address and only the SLAVE_ADDR_W-bit address is passed 
+// through.
+//
+// Parameters:
+//
+//   NUM_SLAVES   : Number of slave devices that you want to connect to master.
+//   BASE_ADDR    : Base address for slave 0. This should be a power-of-2 
+//                  multiple of the combined slave address spaces.
+//   SLAVE_ADDR_W : Number of address bits to allocate to each slave.
+//
+
+module ctrlport_decoder #(
+  parameter NUM_SLAVES   = 2,
+  parameter BASE_ADDR    = 0,
+  parameter SLAVE_ADDR_W = 8
+) (
+  input wire ctrlport_clk,
+  input wire ctrlport_rst,
+
+  // Slave Interface
+  input  wire        s_ctrlport_req_wr,
+  input  wire        s_ctrlport_req_rd,
+  input  wire [19:0] s_ctrlport_req_addr,
+  input  wire [31:0] s_ctrlport_req_data,
+  input  wire [ 3:0] s_ctrlport_req_byte_en,
+  input  wire        s_ctrlport_req_has_time,
+  input  wire [63:0] s_ctrlport_req_time,
+  output reg         s_ctrlport_resp_ack = 1'b0,
+  output reg  [ 1:0] s_ctrlport_resp_status,
+  output reg  [31:0] s_ctrlport_resp_data,
+
+  // Master Interfaces
+  output reg  [   NUM_SLAVES-1:0] m_ctrlport_req_wr = 0,
+  output reg  [   NUM_SLAVES-1:0] m_ctrlport_req_rd = 0,
+  output reg  [20*NUM_SLAVES-1:0] m_ctrlport_req_addr = 0,
+  output reg  [32*NUM_SLAVES-1:0] m_ctrlport_req_data,
+  output reg  [ 4*NUM_SLAVES-1:0] m_ctrlport_req_byte_en,
+  output reg  [   NUM_SLAVES-1:0] m_ctrlport_req_has_time,
+  output reg  [64*NUM_SLAVES-1:0] m_ctrlport_req_time,
+  input  wire [   NUM_SLAVES-1:0] m_ctrlport_resp_ack,
+  input  wire [ 2*NUM_SLAVES-1:0] m_ctrlport_resp_status,
+  input  wire [32*NUM_SLAVES-1:0] m_ctrlport_resp_data
+);
+
+  localparam        PORT_NUM_W      = $clog2(NUM_SLAVES);
+  localparam        PORT_NUM_POS    = SLAVE_ADDR_W;
+  localparam        BASE_ADDR_W     = 20 - (SLAVE_ADDR_W + PORT_NUM_W);
+  localparam        BASE_ADDR_POS   = SLAVE_ADDR_W + PORT_NUM_W;
+  localparam [19:0] BASE_ADDR_MASK  = { BASE_ADDR_W {1'b1}} << BASE_ADDR_POS;
+
+
+  //---------------------------------------------------------------------------
+  // Split the requests among the slaves
+  //---------------------------------------------------------------------------
+
+  wire [NUM_SLAVES-1:0] decoder;
+
+  genvar i;
+  for (i = 0; i < NUM_SLAVES; i = i+1) begin : gen_split
+    // Check if the upper bits of the request address match each slave. If the 
+    // address matches, set the corresponding decoder[] bit.
+    if (PORT_NUM_W == 0) begin
+      // Only one port in this case, so there are no port number bits to check
+      assign decoder[i] = ((s_ctrlport_req_addr & BASE_ADDR_MASK) == BASE_ADDR);
+    end else begin
+      assign decoder[i] = ((s_ctrlport_req_addr & BASE_ADDR_MASK) == BASE_ADDR) && 
+                           (s_ctrlport_req_addr[PORT_NUM_POS +: PORT_NUM_W] == i);
+    end
+
+    always @(posedge ctrlport_clk) begin
+      if (ctrlport_rst) begin
+        m_ctrlport_req_wr[i] <= 1'b0;
+        m_ctrlport_req_rd[i] <= 1'b0;
+      end else begin
+        // Mask WR and RD based on address decoding
+        m_ctrlport_req_wr[i] <= s_ctrlport_req_wr & decoder[i];
+        m_ctrlport_req_rd[i] <= s_ctrlport_req_rd & decoder[i];
+
+        // Other values pass through to all slaves, but should be ignored
+        // unless the corresponding WR or RD is not asserted.
+        m_ctrlport_req_data    [32*i +: 32] <= s_ctrlport_req_data;
+        m_ctrlport_req_byte_en [4*i +: 4]   <= s_ctrlport_req_byte_en;
+        m_ctrlport_req_has_time[i]          <= s_ctrlport_req_has_time;
+        m_ctrlport_req_time    [64*i +: 64] <= s_ctrlport_req_time;
+
+        // Pass through only the relevant slave bits
+        m_ctrlport_req_addr[20*i+:20]           <= 20'b0;
+        m_ctrlport_req_addr[20*i+:SLAVE_ADDR_W] <= s_ctrlport_req_addr[SLAVE_ADDR_W-1:0];
+      end
+    end
+  end
+
+
+  //---------------------------------------------------------------------------
+  // Decode the responses
+  //---------------------------------------------------------------------------
+
+  reg [31:0] data;
+  reg [ 1:0] status;
+  reg        ack = 0;
+
+  // Take the responses and mask them with ack, then OR them together
+  always @(*) begin : comb_decode
+    integer s;
+    data   = 0;
+    status = 0;
+    ack    = 0;
+    for (s = 0; s < NUM_SLAVES; s = s+1) begin
+      data   = data   | (m_ctrlport_resp_data  [s*32 +: 32] & {32{m_ctrlport_resp_ack[s]}});
+      status = status | (m_ctrlport_resp_status[s* 2 +:  2] & { 2{m_ctrlport_resp_ack[s]}});
+      ack    = ack    | m_ctrlport_resp_ack[s];
+    end
+  end
+
+  // Register the output to break combinatorial path
+  always @(posedge ctrlport_clk) begin
+    if (ctrlport_rst) begin
+      s_ctrlport_resp_ack  <= 0;
+    end else begin
+      s_ctrlport_resp_data   <= data;
+      s_ctrlport_resp_status <= status;
+      s_ctrlport_resp_ack    <= ack;
+    end
+  end
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/utils/ctrlport_decoder_param.v b/fpga/usrp3/lib/rfnoc/utils/ctrlport_decoder_param.v
new file mode 100644
index 000000000..f2f4a438c
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/utils/ctrlport_decoder_param.v
@@ -0,0 +1,169 @@
+//
+// Copyright 2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: ctrlport_decoder_param
+//
+// Description:
+//
+//   This block splits a single control port interface into multiple. It is 
+//   used when you have a single master that needs to access multiple slaves. 
+//   For example, a NoC block where the registers are implemented in multiple 
+//   submodules that must be read/written by a single NoC shell.
+//
+//   This version also implements address decoding. The request is passed to a 
+//   slave only if the address falls within that slave's address space. Each 
+//   slave can have a unique base address and address space size. The address 
+//   space is broken up as follows.
+//
+//     PORT_BASE[0*20 +: 20] = Port 0 base address
+//       │           ┐ 
+//       │           ├── 2**PORT_ADDR_W[0*32 +: 32] bytes for slave 0
+//       │           ┘
+//       .
+//       .
+//     PORT_BASE[1*20 +: 20] = Port 1 base address
+//       │           ┐
+//       │           ├── 2**PORT_ADDR_W[1*32 +: 32] bytes for slave 1
+//       │           ┘
+//       .
+//       .
+//
+//   When passed to the slave, the base address is stripped from the request 
+//   address so that only the PORT_ADDR_W-bit address is passed through.
+//
+// Parameters:
+//
+//   NUM_SLAVES  : The number of slaves to connect to a master.
+//
+//   PORT_BASE   : Base addresses to use fore each slave. This is a 
+//                 concatenation of 20-bit addresses, where the right-most 
+//                 (least-significant) 20 bits corresponds to slave 0. Each 
+//                 address must be a multiple of 2**PORT_ADDR_W, where 
+//                 PORT_ADDR_W is the number of address bits allocated to that 
+//                 slave.
+//
+//   PORT_ADDR_W : Number of address bits to allocate to each slave. This is a 
+//                 concatenation of 32-bit integers, where the right-most 
+//                 (least-significant) 32 bits corresponds to the address space 
+//                 for slave 0.
+//
+
+module ctrlport_decoder_param #(
+  parameter NUM_SLAVES  = 4,
+  parameter PORT_BASE   = { 20'h300, 20'h200, 20'h100, 20'h000 },
+  parameter PORT_ADDR_W = {   32'd8,   32'd8,   32'd8,   32'd8 }
+) (
+  input wire ctrlport_clk,
+  input wire ctrlport_rst,
+
+  // Slave Interface
+  input  wire        s_ctrlport_req_wr,
+  input  wire        s_ctrlport_req_rd,
+  input  wire [19:0] s_ctrlport_req_addr,
+  input  wire [31:0] s_ctrlport_req_data,
+  input  wire [ 3:0] s_ctrlport_req_byte_en,
+  input  wire        s_ctrlport_req_has_time,
+  input  wire [63:0] s_ctrlport_req_time,
+  output reg         s_ctrlport_resp_ack = 1'b0,
+  output reg  [ 1:0] s_ctrlport_resp_status,
+  output reg  [31:0] s_ctrlport_resp_data,
+
+  // Master Interfaces
+  output reg  [   NUM_SLAVES-1:0] m_ctrlport_req_wr = 0,
+  output reg  [   NUM_SLAVES-1:0] m_ctrlport_req_rd = 0,
+  output reg  [20*NUM_SLAVES-1:0] m_ctrlport_req_addr = 0,
+  output reg  [32*NUM_SLAVES-1:0] m_ctrlport_req_data,
+  output reg  [ 4*NUM_SLAVES-1:0] m_ctrlport_req_byte_en,
+  output reg  [   NUM_SLAVES-1:0] m_ctrlport_req_has_time,
+  output reg  [64*NUM_SLAVES-1:0] m_ctrlport_req_time,
+  input  wire [   NUM_SLAVES-1:0] m_ctrlport_resp_ack,
+  input  wire [ 2*NUM_SLAVES-1:0] m_ctrlport_resp_status,
+  input  wire [32*NUM_SLAVES-1:0] m_ctrlport_resp_data
+);
+
+  //---------------------------------------------------------------------------
+  // Address Decode Logic
+  //---------------------------------------------------------------------------
+  //
+  // Check if the upper bits of the request address match each slave. If the
+  // address matches, set the corresponding dec_mask[] bit.
+  //
+  //---------------------------------------------------------------------------
+
+  wire [NUM_SLAVES-1:0] dec_mask;  // Address decoder mask
+
+  genvar i;
+
+  for (i = 0; i < NUM_SLAVES; i = i+1) begin : gen_dec_mask
+    localparam [19:0] BASE_ADDR = PORT_BASE  [i*20 +: 20];
+    localparam [31:0] ADDR_W    = PORT_ADDR_W[i*32 +: 32];
+    assign dec_mask[i] = ~|((s_ctrlport_req_addr ^ BASE_ADDR) & ((~0) << ADDR_W));
+  end
+
+
+  //---------------------------------------------------------------------------
+  // Split the requests among the slaves
+  //---------------------------------------------------------------------------
+
+  for (i = 0; i < NUM_SLAVES; i = i+1) begin : gen_split
+    localparam [31:0] ADDR_W = PORT_ADDR_W[i*32 +: 32];
+
+    always @(posedge ctrlport_clk) begin
+      if (ctrlport_rst) begin
+        m_ctrlport_req_wr[i] <= 1'b0;
+        m_ctrlport_req_rd[i] <= 1'b0;
+      end else begin
+        // Mask WR and RD based on address decoding
+        m_ctrlport_req_wr[i] <= s_ctrlport_req_wr & dec_mask[i];
+        m_ctrlport_req_rd[i] <= s_ctrlport_req_rd & dec_mask[i];
+
+        // Other values pass through to all slaves, but should be ignored
+        // unless WR or RD is asserted.
+        m_ctrlport_req_data    [32*i +: 32] <= s_ctrlport_req_data;
+        m_ctrlport_req_byte_en [4*i +: 4]   <= s_ctrlport_req_byte_en;
+        m_ctrlport_req_has_time[i]          <= s_ctrlport_req_has_time;
+        m_ctrlport_req_time    [64*i +: 64] <= s_ctrlport_req_time;
+
+        // Mask the address bits to that of the slaves address space.
+        m_ctrlport_req_addr[20*i +: 20]     <= 20'b0;
+        m_ctrlport_req_addr[20*i +: ADDR_W] <= s_ctrlport_req_addr[ADDR_W-1 : 0];
+      end
+    end
+  end
+
+
+  //---------------------------------------------------------------------------
+  // Decode the responses
+  //---------------------------------------------------------------------------
+
+  reg [31:0] data;
+  reg [ 1:0] status;
+  reg        ack = 0;
+
+  // Take the responses and mask them with ack, then OR them together
+  always @(*) begin : comb_decode
+    integer s;
+    data   = 0;
+    status = 0;
+    ack    = 0;
+    for (s = 0; s < NUM_SLAVES; s = s+1) begin
+      data   = data   | (m_ctrlport_resp_data  [s*32 +: 32] & {32{m_ctrlport_resp_ack[s]}});
+      status = status | (m_ctrlport_resp_status[s* 2 +:  2] & { 2{m_ctrlport_resp_ack[s]}});
+      ack    = ack    | m_ctrlport_resp_ack[s];
+    end
+  end
+
+  // Register the output to break combinatorial path
+  always @(posedge ctrlport_clk) begin
+    if (ctrlport_rst) begin
+      s_ctrlport_resp_ack  <= 0;
+    end else begin
+      s_ctrlport_resp_data   <= data;
+      s_ctrlport_resp_status <= status;
+      s_ctrlport_resp_ack    <= ack;
+    end
+  end
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/utils/ctrlport_reg_ro.v b/fpga/usrp3/lib/rfnoc/utils/ctrlport_reg_ro.v
new file mode 100644
index 000000000..c21667358
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/utils/ctrlport_reg_ro.v
@@ -0,0 +1,181 @@
+//
+// Copyright 2019 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module:  ctrlport_reg_ro
+//
+// Description:
+//
+//   Implements a read-only register on a CTRL Port bus. The actual register 
+//   bits are driven from outside of this module and passed in through the 
+//   "value_in" input port. All input addresses are assumed to be 32-bit word 
+//   aligned.
+//
+//   The width of the register is configurable. The register will take up the 
+//   full power-of-2 address region, with a minimum of a 4-byte region. For 
+//   example:
+//
+//      WIDTH (Bits) │ Address Space (Bytes)
+//     ──────────────┼───────────────────────
+//        1  to 32   │   4
+//        33 to 64   │   8
+//        64 to 128  │   16
+//        etc.       │   etc.
+//
+//   When COHERENT is true and the WIDTH is larger than a single CTRL Port word 
+//   (32 bits), reading the least-significant word of the register causes the 
+//   other words of the register to be read and saved in a cache register on 
+//   the same clock cycle. Reading the upper words of the register will always  
+//   read from the cached copy. This allows reads of large, multi-word 
+//   registers to be coherent. This is very important for registers in which 
+//   there is a relationship between the upper and lower bits, such as in a 
+//   counter which could change or roll over between 32-bit reads. The 
+//   least-significant word MUST always be read first when COHERENT is true.
+//
+// Parameters:
+//
+//   ADDR     : Byte address to use for this register. This address must be 
+//              aligned to the size of the register.
+//   WIDTH    : Width of register to implement in bits. This determines the 
+//              width of the "value_in" input and the amount of address space 
+//              used by the register, which is always a power of 2.
+//   COHERENT : Setting to 1 implements additional logic so that register reads 
+//              maintain coherency. Setting to 0 removes this logic, so that 
+//              each 32-bit word of the register is treated independently.
+//
+// Ports:
+//
+//   *ctrlport* : CTRL Port interface.
+//   value_in   : The current value of the register.
+//
+
+
+module ctrlport_reg_ro #(
+  parameter [   19:0] ADDR     = 0,
+  parameter           WIDTH    = 32,
+  parameter           COHERENT = 0
+) (
+  input wire ctrlport_clk,
+
+  input  wire        s_ctrlport_req_rd,
+  input  wire [19:0] s_ctrlport_req_addr,
+  output reg         s_ctrlport_resp_ack,
+  output wire [ 1:0] s_ctrlport_resp_status,
+  output reg  [31:0] s_ctrlport_resp_data,
+
+  input wire [WIDTH-1:0] value_in
+);
+
+  //---------------------------------------------------------------------------
+  // Functions
+  //---------------------------------------------------------------------------
+
+  function automatic integer max(input integer a, b);
+    max = a > b ? a : b;
+  endfunction
+
+
+  //---------------------------------------------------------------------------
+  // Local Parameters
+  //---------------------------------------------------------------------------
+
+  // Calculate the number of bytes of address space this register will take up. 
+  // The minimum size is a 32-bit register (4 bytes).
+  localparam NUM_BYTES = max(4, 2**$clog2(WIDTH) / 8);
+
+  // Calculate the number of bits needed to index each byte of this register.
+  localparam BYTE_ADDR_W = $clog2(NUM_BYTES);
+
+  // Calculate the number of bits needed to index each 32-bit word of this  
+  // register.
+  localparam WORD_ADDR_W = BYTE_ADDR_W-2;
+
+
+  //---------------------------------------------------------------------------
+  // Parameter Checking
+  //---------------------------------------------------------------------------
+
+  // Make sure WIDTH is valid
+  if (WIDTH < 1) begin
+    WIDTH_must_be_at_least_1();
+  end
+
+  // Make sure the address is word-aligned to the size of the register
+  if (ADDR[BYTE_ADDR_W-1:0] != 0) begin
+    ADDR_must_be_aligned_to_the_size_of_the_register();
+  end
+
+
+  //---------------------------------------------------------------------------
+  // Resize Input Value
+  //---------------------------------------------------------------------------
+
+  // Use full size to simplify indexing. Unused bits will be optimized away.
+  reg [NUM_BYTES*8-1:0] reg_val = 0;
+
+  always @(*) begin
+    reg_val            <= 0;
+    reg_val[WIDTH-1:0] <= value_in;
+  end
+
+
+  //---------------------------------------------------------------------------
+  // Read Logic
+  //---------------------------------------------------------------------------
+
+  reg [WIDTH-1:0] cache_reg;
+
+  assign s_ctrlport_resp_status = 0;  // Status is always "OK" (0)
+
+  //
+  // Coherent implementation
+  //
+  if (WIDTH > 32 && COHERENT) begin : gen_coherent
+    // In this case we want the upper bits, when read separately, to be 
+    // coherent with the lower bits. So we register the upper bits when the 
+    // least-significant word is read.
+
+    always @(posedge ctrlport_clk) begin
+      // Check if any part of this register is being addressed
+      if (s_ctrlport_req_addr[19 : BYTE_ADDR_W] == ADDR[19 : BYTE_ADDR_W] && s_ctrlport_req_rd) begin
+        s_ctrlport_resp_ack  <= 1'b1;
+
+        // Check if we're reading the least-significant word
+        if (s_ctrlport_req_addr[BYTE_ADDR_W-1 : 2] == 0) begin
+          s_ctrlport_resp_data <= reg_val[31:0];
+          cache_reg            <= reg_val;   // Unused bits will be optimized away
+
+        // Otherwise, grab the word that's being addressed from the cached value
+        end else begin
+          s_ctrlport_resp_data <= cache_reg[s_ctrlport_req_addr[2 +: WORD_ADDR_W]*32 +: 32];
+        end
+      end else begin
+        s_ctrlport_resp_ack <= 1'b0;
+      end
+    end
+
+  //
+  // Non-coherent implementation
+  //
+  end else begin : gen_no_coherent
+    // In this case, coherency is not required, so we just return the word 
+    // that's being addressed.
+
+    always @(posedge ctrlport_clk) begin
+      // Check if any part of this register is being addressed
+      if (s_ctrlport_req_addr[19 : BYTE_ADDR_W] == ADDR[19 : BYTE_ADDR_W] && s_ctrlport_req_rd) begin
+        s_ctrlport_resp_ack  <= 1'b1;
+        if (WORD_ADDR_W > 0) begin
+          // Read back only the word of the register being addressed
+          s_ctrlport_resp_data <= reg_val[s_ctrlport_req_addr[2 +: WORD_ADDR_W]*32 +: 32];
+        end else begin
+          s_ctrlport_resp_data <= reg_val;
+        end
+      end else begin
+        s_ctrlport_resp_ack <= 1'b0;
+      end
+    end
+  end
+   
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/utils/ctrlport_reg_rw.v b/fpga/usrp3/lib/rfnoc/utils/ctrlport_reg_rw.v
new file mode 100644
index 000000000..7e74b1422
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/utils/ctrlport_reg_rw.v
@@ -0,0 +1,247 @@
+//
+// Copyright 2019 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module:  ctrlport_reg_rw
+//
+// Description:
+//
+//   Implements a read/write register on a CTRL Port bus. CTRL Port byte 
+//   enables are supported on writes. All input addresses are assumed to be 
+//   32-bit word aligned.
+//
+//   The width of the register is configurable. The register will take up the 
+//   full power-of-2 address region, with a minimum of a 4-byte region. For 
+//   example:
+//
+//      WIDTH (Bits) │ Address Space (Bytes)
+//     ──────────────┼───────────────────────
+//        1  to 32   │   4
+//        33 to 64   │   8
+//        64 to 128  │   16
+//        etc.       │   etc.
+//
+//   When COHERENCY is true and the WIDTH is larger than a single CTRL Port 
+//   word (32 bits), writing the least-significant words of the register causes 
+//   them to be saved in a cache register and does not immediately update those 
+//   words in the register. Writing the most-significant word of the register 
+//   causes all the words to be simultaneously written to the register. This 
+//   allows writes of large, multi-word registers to be coherent. This is very 
+//   important for registers in which there is a relationship between the upper 
+//   and lower bits, such as in a counter value in which changing only part of 
+//   the word at a time could be seen as a large change when in fact the final 
+//   change is small. The most-significant word MUST always be written last 
+//   when COHERENCY is true.
+//
+// Parameters:
+//
+//   ADDR      : Byte address to use for this register. This address must be 
+//               aligned to the size of the register.
+//   WIDTH     : Width of register to implement in bits. This determines the 
+//               width of the "value_out" input and the amount of address space 
+//               used by the register, which is always a power of 2.
+//   COHERENT  : Setting to 1 implements additional logic so that register 
+//               writes maintain coherency. Setting to 0 removes this logic, so 
+//               that each 32-bit word of the register is treated independently.
+//   RESET_VAL : Value to give the register at power-on and at reset.
+//
+// Ports:
+//
+//   *ctrlport* : CTRL Port interface.
+//   value_out  : The current value of the register.
+//   written    : A strobe (single-cycle pulse) that indicates when the 
+//                register was written. The new value may or may not be the 
+//                same as the old value.
+//
+
+
+module ctrlport_reg_rw #(
+  parameter [     19:0] ADDR      = 0,
+  parameter             WIDTH     = 32,
+  parameter             COHERENT  = 0,
+  parameter [WIDTH-1:0] RESET_VAL = 'h0
+) (
+  input wire ctrlport_clk,
+  input wire ctrlport_rst,
+
+  input  wire        s_ctrlport_req_wr,
+  input  wire        s_ctrlport_req_rd,
+  input  wire [19:0] s_ctrlport_req_addr,
+  input  wire [31:0] s_ctrlport_req_data,
+  input  wire [ 3:0] s_ctrlport_req_byte_en,
+  output wire        s_ctrlport_resp_ack,
+  output wire [ 1:0] s_ctrlport_resp_status,
+  output reg  [31:0] s_ctrlport_resp_data,
+
+  output wire [WIDTH-1:0] value_out,
+  output reg              written
+);
+
+  //---------------------------------------------------------------------------
+  // Functions
+  //---------------------------------------------------------------------------
+
+  function automatic integer max(input integer a, b);
+    max = a > b ? a : b;
+  endfunction
+
+
+  //---------------------------------------------------------------------------
+  // Local Parameters
+  //---------------------------------------------------------------------------
+
+  // Calculate the number of bytes of address space this register will take up. 
+  // The minimum size is a 32-bit register (4 bytes).
+  localparam NUM_BYTES = max(4, 2**$clog2(WIDTH)/8);
+
+  // Calculate the number of bits needed to index each byte of this register.
+  localparam BYTE_ADDR_W = $clog2(NUM_BYTES);
+
+  // Calculate the number of bits needed to index each 32-bit word of this  
+  // register.
+  localparam WORD_ADDR_W = BYTE_ADDR_W-2;
+
+
+  //---------------------------------------------------------------------------
+  // Parameter Checking
+  //---------------------------------------------------------------------------
+
+  // Make sure WIDTH is valid
+  if (WIDTH < 1) begin
+    WIDTH_must_be_at_least_1();
+  end
+
+  // Make sure the address is word-aligned to the size of the register
+  if (ADDR[BYTE_ADDR_W-1:0] != 0) begin
+    ADDR_must_be_aligned_to_the_size_of_the_register();
+  end
+
+
+  //---------------------------------------------------------------------------
+  // Write Logic
+  //---------------------------------------------------------------------------
+
+  // Use full size to simplify indexing. Unused bits will be optimized away.
+  reg [8*NUM_BYTES-1:0] reg_val = 0;
+
+  reg [8*NUM_BYTES-1:0] write_cache_reg;
+  reg [  NUM_BYTES-1:0] write_en_cache_reg;
+
+  reg s_ctrlport_resp_ack_wr;
+
+  integer b, w;
+
+  //
+  // Coherent implementation
+  //
+  if (WIDTH > 32 && COHERENT) begin : gen_coherent
+    always @(posedge ctrlport_clk) begin
+      if (ctrlport_rst) begin
+        reg_val <= RESET_VAL;
+        written <= 1'b0;
+      end else begin
+        // Check if any part of this register is being written to
+        if (s_ctrlport_req_addr[19 : BYTE_ADDR_W] == ADDR[19 : BYTE_ADDR_W] && s_ctrlport_req_wr) begin
+          s_ctrlport_resp_ack_wr <= 1'b1;
+
+          // Check if we're writing the most-significant word
+          if (s_ctrlport_req_addr[BYTE_ADDR_W-1 : 2] == {BYTE_ADDR_W-2{1'b1}}) begin
+            written <= 1'b1;
+
+            // Iterate over the 4 bytes, updating each based on byte_en
+            for (b = 0; b < 4; b = b+1) begin
+              // Update the most-significant word from the input
+              if(s_ctrlport_req_byte_en[b]) begin
+                reg_val[32*(NUM_BYTES/4-1)+b*8 +: 8] <= s_ctrlport_req_data[8*b +: 8];
+              end
+
+              // Update the least-significant words from the cache
+              for (w = 0; w < NUM_BYTES/4; w = w+1) begin
+                if (write_en_cache_reg[b]) begin
+                  reg_val[32*w+b*8 +: 8] <= write_cache_reg[32*w+b*8 +: 8];
+                end
+              end
+            end
+
+          // We're writing one of the least-significant words, so just cache 
+          // the values written.
+          end else begin
+            w = s_ctrlport_req_addr[2 +: WORD_ADDR_W];
+            write_cache_reg[w*32 +: 32]  <= s_ctrlport_req_data;
+            write_en_cache_reg[w*4 +: 4] <= s_ctrlport_req_byte_en;
+          end
+
+        end else begin
+          s_ctrlport_resp_ack_wr <= 1'b0;
+          written                <= 1'b0;
+        end
+      end
+    end
+
+  //
+  // Non-coherent implementation
+  //
+  end else begin : gen_no_coherent
+    always @(posedge ctrlport_clk) begin
+      if (ctrlport_rst) begin
+        reg_val <= RESET_VAL;
+        written <= 1'b0;
+      end else begin
+        // Check if any part of the word is begin written to
+        if (s_ctrlport_req_addr[19 : BYTE_ADDR_W] == ADDR[19 : BYTE_ADDR_W] && s_ctrlport_req_wr) begin
+          for (b = 0; b < 4; b = b + 1) begin
+            if (s_ctrlport_req_byte_en[b]) begin
+              if (WORD_ADDR_W > 0) begin
+                // Update only the word of the register being addressed. "max" 
+                // is needed by Vivado here to elaborate when WORD_ADDR_W is 0.
+                w = s_ctrlport_req_addr[2 +: max(1, WORD_ADDR_W)];
+                reg_val[w*32+b*8 +: 8] <= s_ctrlport_req_data[8*b +: 8];
+              end else begin
+                reg_val[b*8 +: 8] <= s_ctrlport_req_data[8*b +: 8];
+              end
+            end
+          end
+          s_ctrlport_resp_ack_wr <= 1'b1;
+          written                <= 1'b1;
+        end else begin
+          s_ctrlport_resp_ack_wr <= 1'b0;
+          written                <= 1'b0;
+        end
+      end
+    end
+
+  end
+
+
+  //---------------------------------------------------------------------------
+  // Read Logic
+  //---------------------------------------------------------------------------
+
+  reg s_ctrlport_resp_ack_rd;
+
+  assign s_ctrlport_resp_status = 0;  // Status is always "OK" (0)
+
+  assign value_out = reg_val[WIDTH-1:0];
+
+  // Because the register is only changed by software, read coherency is not 
+  // required, so we just return the word that's being addressed.
+  always @(posedge ctrlport_clk) begin
+    // Check if any part of this register is being addressed
+    if (s_ctrlport_req_addr[19 : BYTE_ADDR_W] == ADDR[19 : BYTE_ADDR_W] && s_ctrlport_req_rd) begin
+      s_ctrlport_resp_ack_rd <= 1'b1;
+      if (WORD_ADDR_W > 0) begin
+        // Read back only the word of the register being addressed
+        s_ctrlport_resp_data <= reg_val[s_ctrlport_req_addr[2 +: WORD_ADDR_W]*32 +: 32];
+      end else begin
+        s_ctrlport_resp_data <= reg_val[31:0];
+      end
+    end else begin
+      s_ctrlport_resp_ack_rd <= 1'b0;
+    end
+  end
+
+  // Combine read/write ack
+  assign s_ctrlport_resp_ack = s_ctrlport_resp_ack_wr | s_ctrlport_resp_ack_rd;
+   
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/utils/ctrlport_resp_combine.v b/fpga/usrp3/lib/rfnoc/utils/ctrlport_resp_combine.v
new file mode 100644
index 000000000..e3461cb2c
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/utils/ctrlport_resp_combine.v
@@ -0,0 +1,70 @@
+//
+// Copyright 2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: ctrlport_resp_combine
+//
+// Description:
+//
+//   This module combines the control-port responses from multiple slave blocks 
+//   into a single response for the master. This is done by using ack bit to 
+//   mask all bits of the responses then ORing all the results together onto a 
+//   single response bus. This is valid because only one block is allowed to 
+//   respond to a single request.
+//
+//   Note that no special logic is required to split the requests from the 
+//   master among multiple slaves. A single master request interface can be 
+//   directly connected to all the slaves without issue.
+//
+// Parameters:
+//
+//   NUM_SLAVES : The number of slaves you want to connect to a master.
+//
+
+
+module ctrlport_resp_combine #(
+  parameter NUM_SLAVES = 2
+) (
+  input wire ctrlport_clk,
+  input wire ctrlport_rst,
+
+  // Responses from multiple slaves
+  input wire [   NUM_SLAVES-1:0] m_ctrlport_resp_ack,
+  input wire [ 2*NUM_SLAVES-1:0] m_ctrlport_resp_status,
+  input wire [32*NUM_SLAVES-1:0] m_ctrlport_resp_data,
+
+  // Response to a single master
+  output reg        s_ctrlport_resp_ack,
+  output reg [ 1:0] s_ctrlport_resp_status,
+  output reg [31:0] s_ctrlport_resp_data
+);
+
+  always @(posedge ctrlport_clk) begin
+    if (ctrlport_rst) begin
+      s_ctrlport_resp_data <= 0;
+      s_ctrlport_resp_ack  <= 0;
+    end else begin : or_reg_resp
+      reg [31:0] data;
+      reg [ 1:0] status;
+      reg        ack;
+      integer    s;
+
+      // Take the responses and mask them with ack then OR them together
+      data   = 0;
+      status = 0;
+      ack    = 0;
+      for (s = 0; s < NUM_SLAVES; s = s+1) begin
+        data   = data   | (m_ctrlport_resp_data  [s*32 +: 32] & {32{m_ctrlport_resp_ack[s]}});
+        status = status | (m_ctrlport_resp_status[s* 2 +:  2] & { 2{m_ctrlport_resp_ack[s]}});
+        ack    = ack    |  m_ctrlport_resp_ack[s];
+      end
+
+      // Register the output to break combinatorial path
+      s_ctrlport_resp_data   <= data;
+      s_ctrlport_resp_status <= status;
+      s_ctrlport_resp_ack    <= ack;
+    end
+  end
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/utils/ctrlport_splitter.v b/fpga/usrp3/lib/rfnoc/utils/ctrlport_splitter.v
new file mode 100644
index 000000000..23ef13585
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/utils/ctrlport_splitter.v
@@ -0,0 +1,114 @@
+//
+// Copyright 2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: ctrlport_splitter
+//
+// Description:
+//
+// This block splits a single control port interface into multiple. It is used
+// when you have a single master that needs to access multiple slaves. For
+// example, a NoC block where the registers are implemented in multiple
+// submodules that must be read/written by a single NoC shell.
+//
+// Note that this block does not do any address decoding, so the connected
+// slaves must use non-overlapping address spaces.
+//
+// This module takes the request received by its single slave interface and
+// outputs it on all its master interfaces. In the opposite direction, it takes
+// the responses received by its multiple master interfaces and combines them
+// into a single response on its slave interface. This is done by using the ack
+// bit of each response to mask the other bits of the response, then OR'ing all
+// of the masked responses together onto a single response bus. This is valid
+// because only one block is allowed to respond to a single request.
+//
+// Parameters:
+//
+//   NUM_SLAVES : The number of slaves you want to connect to a master.
+//
+
+
+module ctrlport_splitter #(
+  parameter NUM_SLAVES = 2
+) (
+  input wire ctrlport_clk,
+  input wire ctrlport_rst,
+
+  // Slave Interface
+  input  wire        s_ctrlport_req_wr,
+  input  wire        s_ctrlport_req_rd,
+  input  wire [19:0] s_ctrlport_req_addr,
+  input  wire [31:0] s_ctrlport_req_data,
+  input  wire [ 3:0] s_ctrlport_req_byte_en,
+  input  wire        s_ctrlport_req_has_time,
+  input  wire [63:0] s_ctrlport_req_time,
+  output reg         s_ctrlport_resp_ack = 1'b0,
+  output reg  [ 1:0] s_ctrlport_resp_status,
+  output reg  [31:0] s_ctrlport_resp_data,
+
+  // Master Interfaces
+  output wire [   NUM_SLAVES-1:0] m_ctrlport_req_wr,
+  output wire [   NUM_SLAVES-1:0] m_ctrlport_req_rd,
+  output wire [20*NUM_SLAVES-1:0] m_ctrlport_req_addr,
+  output wire [32*NUM_SLAVES-1:0] m_ctrlport_req_data,
+  output wire [ 4*NUM_SLAVES-1:0] m_ctrlport_req_byte_en,
+  output wire [   NUM_SLAVES-1:0] m_ctrlport_req_has_time,
+  output wire [64*NUM_SLAVES-1:0] m_ctrlport_req_time,
+  input  wire [   NUM_SLAVES-1:0] m_ctrlport_resp_ack,
+  input  wire [ 2*NUM_SLAVES-1:0] m_ctrlport_resp_status,
+  input  wire [32*NUM_SLAVES-1:0] m_ctrlport_resp_data
+);
+
+  //---------------------------------------------------------------------------
+  // Split the requests among the slaves
+  //---------------------------------------------------------------------------
+
+  generate
+    genvar i;
+    for (i = 0; i < NUM_SLAVES; i = i+1) begin : gen_split
+      // No special logic is required to split the requests from the master among
+      // multiple slaves.
+      assign m_ctrlport_req_wr[i]           = s_ctrlport_req_wr;
+      assign m_ctrlport_req_rd[i]           = s_ctrlport_req_rd;
+      assign m_ctrlport_req_addr[20*i+:20]  = s_ctrlport_req_addr;
+      assign m_ctrlport_req_data[32*i+:32]  = s_ctrlport_req_data;
+      assign m_ctrlport_req_byte_en[4*i+:4] = s_ctrlport_req_byte_en;
+      assign m_ctrlport_req_has_time[i]     = s_ctrlport_req_has_time;
+      assign m_ctrlport_req_time[64*i+:64]  = s_ctrlport_req_time;
+    end
+  endgenerate
+
+  //---------------------------------------------------------------------------
+  // Decode the responses
+  //---------------------------------------------------------------------------
+
+  reg [31:0] data;
+  reg [ 1:0] status;
+  reg        ack = 0;
+
+  // Take the responses and mask them with ack, then OR them together
+  always @(*) begin : comb_decode
+    integer s;
+    data   = 0;
+    status = 0;
+    ack    = 0;
+    for (s = 0; s < NUM_SLAVES; s = s+1) begin
+      data   = data   | (m_ctrlport_resp_data  [s*32 +: 32] & {32{m_ctrlport_resp_ack[s]}});
+      status = status | (m_ctrlport_resp_status[s* 2 +:  2] & { 2{m_ctrlport_resp_ack[s]}});
+      ack    = ack    | m_ctrlport_resp_ack[s];
+    end
+  end
+
+  // Register the output to break combinatorial path
+  always @(posedge ctrlport_clk) begin
+    if (ctrlport_rst) begin
+      s_ctrlport_resp_ack  <= 0;
+    end else begin
+      s_ctrlport_resp_data   <= data;
+      s_ctrlport_resp_status <= status;
+      s_ctrlport_resp_ack    <= ack;
+    end
+  end
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/utils/ctrlport_terminator.v b/fpga/usrp3/lib/rfnoc/utils/ctrlport_terminator.v
new file mode 100644
index 000000000..2d087e53e
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/utils/ctrlport_terminator.v
@@ -0,0 +1,50 @@
+//
+// Copyright 2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: ctrlport_terminator.v
+// Description:
+// Returns an error for all ctrlport requests in given address range.
+
+module ctrlport_terminator #(
+  parameter START_ADDRESS = 0, // first address to generate response for
+  parameter LAST_ADDRESS = 32  // last address (including) to generate response for
+)(
+  //---------------------------------------------------------------
+  // ControlPort slave
+  //---------------------------------------------------------------
+  input  wire        ctrlport_clk,
+  input  wire        ctrlport_rst,
+  input  wire        s_ctrlport_req_wr,
+  input  wire        s_ctrlport_req_rd,
+  input  wire [19:0] s_ctrlport_req_addr,
+  input  wire [31:0] s_ctrlport_req_data,
+
+  output  reg        s_ctrlport_resp_ack,
+  output wire [ 1:0] s_ctrlport_resp_status,
+  output wire [31:0] s_ctrlport_resp_data
+);
+
+`include "../core/ctrlport.vh"
+//vhook_nowarn s_ctrlport_req_addr
+//vhook_nowarn s_ctrlport_req_data
+
+// drive acknowledgement on requests but not on reset
+always @(posedge ctrlport_clk) begin
+  if (ctrlport_clk) begin
+    if (ctrlport_rst) begin
+      s_ctrlport_resp_ack <= 1'b0;
+    end else if ((s_ctrlport_req_addr >= START_ADDRESS) && (s_ctrlport_req_addr <= LAST_ADDRESS)) begin
+      s_ctrlport_resp_ack <= s_ctrlport_req_wr | s_ctrlport_req_rd;
+    end else begin
+      s_ctrlport_resp_ack <= 1'b0;
+    end
+  end
+end
+
+// other outputs are fixed
+assign s_ctrlport_resp_status = CTRL_STS_CMDERR;
+assign s_ctrlport_resp_data = { CTRLPORT_DATA_W {1'b0}};
+
+endmodule
\ No newline at end of file
diff --git a/fpga/usrp3/lib/rfnoc/utils/ctrlport_timer.v b/fpga/usrp3/lib/rfnoc/utils/ctrlport_timer.v
new file mode 100644
index 000000000..293ee6559
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/utils/ctrlport_timer.v
@@ -0,0 +1,122 @@
+//
+// Copyright 2018 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: ctrlport_timer
+// Description:
+//   The Control-Port timer module converts an asynchronous timed
+//   transaction into a synchronous blocking transaction. This
+//   module will use the input req_has_time and req_time fields and
+//   produce an output transaction that will execute when the requested
+//   time is current. The module does not pass the has_time and time
+//   signals out because they are no longer relevant. The current time
+//   is an input to this module, and must be a monotonic counter that
+//   updates every time the time strobe is asserted.
+//
+// Parameters:
+//   - PRECISION_BITS : The number of bits to ignore when performing a 
+//                      time comparison to determine execution time.
+//   - EXEC_LATE_CMDS : If a command is late, a TSERR response is sent.
+//                      If EXEC_LATE_CMDS = 1, then the late command will
+//                      be passed to the output regardless of the TSERR.
+//
+// Signals:
+//   - time_now*      : The time_now signal is the current time and the stb
+//                      signal indicates that the time_now is valid.
+//   - s_ctrlport_*   : The slave Control-Port bus.
+//                      This must have the has_time and time signals.
+//   - m_ctrlport_*   : The master Control-Port bus.
+//                      This will not have the has_time and time signals.
+
+module ctrlport_timer #(
+  parameter       PRECISION_BITS = 0,
+  parameter [0:0] EXEC_LATE_CMDS = 0
+)(
+  // Clocks and Resets
+  input  wire         clk,
+  input  wire         rst,
+  // Timestamp (synchronous to clk)
+  input  wire [63:0]  time_now,
+  input  wire         time_now_stb,
+  // Control Port Master (Request)
+  input  wire         s_ctrlport_req_wr,
+  input  wire         s_ctrlport_req_rd,
+  input  wire [19:0]  s_ctrlport_req_addr,
+  input  wire [31:0]  s_ctrlport_req_data,
+  input  wire [3:0]   s_ctrlport_req_byte_en,
+  input  wire         s_ctrlport_req_has_time,
+  input  wire [63:0]  s_ctrlport_req_time,
+  // Control Port Slave (Response)
+  output wire         s_ctrlport_resp_ack,
+  output wire [1:0]   s_ctrlport_resp_status,
+  output wire [31:0]  s_ctrlport_resp_data,
+  // Control Port Master (Request)
+  output wire         m_ctrlport_req_wr,
+  output wire         m_ctrlport_req_rd,
+  output wire [19:0]  m_ctrlport_req_addr,
+  output wire [31:0]  m_ctrlport_req_data,
+  output wire [3:0]   m_ctrlport_req_byte_en,
+  // Control Port Master (Response)
+  input  wire         m_ctrlport_resp_ack,
+  input  wire [1:0]   m_ctrlport_resp_status,
+  input  wire [31:0]  m_ctrlport_resp_data
+);
+
+  `include "../core/rfnoc_chdr_utils.vh"
+  `include "../core/rfnoc_axis_ctrl_utils.vh"
+
+  // Control triggers:
+  // - pending: A command is waiting on the input port
+  // - ontime: The timed command is due for execution (on time)
+  // - late: The timed command is late
+  // - exec: Execute the command (pass it to the output)
+  // - consume: Consume the input command
+  wire         pending, ontime, late, exec, consume;
+  // Cached values for input command
+  wire         cached_req_wr, cached_req_rd;
+  wire [19:0]  cached_req_addr;
+  wire [31:0]  cached_req_data;
+  wire [3:0]   cached_req_byte_en;
+  wire         cached_req_has_time;
+  wire [63:0]  cached_req_time;
+
+  axi_fifo_flop #(.WIDTH(1+1+20+32+4+1+64)) req_cache_i (
+    .clk(clk), .reset(rst), .clear(1'b0),
+    .i_tdata({s_ctrlport_req_wr, s_ctrlport_req_rd, s_ctrlport_req_addr, s_ctrlport_req_data,
+              s_ctrlport_req_byte_en, s_ctrlport_req_has_time, s_ctrlport_req_time}),
+    .i_tvalid(s_ctrlport_req_wr | s_ctrlport_req_rd), .i_tready(),
+    .o_tdata({cached_req_wr, cached_req_rd, cached_req_addr, cached_req_data,
+              cached_req_byte_en, cached_req_has_time, cached_req_time}),
+    .o_tvalid(pending), .o_tready(consume),
+    .occupied(), .space()
+  );
+
+  // Command is on time
+  assign ontime = cached_req_has_time && pending && time_now_stb && 
+    (cached_req_time[63:PRECISION_BITS] == time_now[63:PRECISION_BITS]);
+  // Command is late
+  assign late = cached_req_has_time && pending && time_now_stb && 
+    (cached_req_time[63:PRECISION_BITS] < time_now[63:PRECISION_BITS]);
+  // Logic to pass cmd forward
+  assign exec = pending && (!cached_req_has_time || ontime || (EXEC_LATE_CMDS && late));
+  assign consume = exec || late;
+
+  assign m_ctrlport_req_wr      = cached_req_wr & exec;
+  assign m_ctrlport_req_rd      = cached_req_rd & exec;
+  assign m_ctrlport_req_addr    = cached_req_addr;
+  assign m_ctrlport_req_data    = cached_req_data;
+  assign m_ctrlport_req_byte_en = cached_req_byte_en;
+
+  wire [1:0] resp_status = (late && !exec) ? AXIS_CTRL_STS_TSERR : m_ctrlport_resp_status;
+  axi_fifo_flop #(.WIDTH(2+32)) resp_cache_i (
+    .clk(clk), .reset(rst), .clear(1'b0),
+    .i_tdata({resp_status, m_ctrlport_resp_data}),
+    .i_tvalid(m_ctrlport_resp_ack || (late && !exec)), .i_tready(),
+    .o_tdata({s_ctrlport_resp_status, s_ctrlport_resp_data}),
+    .o_tvalid(s_ctrlport_resp_ack), .o_tready(s_ctrlport_resp_ack),
+    .occupied(), .space()
+  );
+
+endmodule // ctrlport_timer
+
diff --git a/fpga/usrp3/lib/rfnoc/utils/ctrlport_to_settings_bus.v b/fpga/usrp3/lib/rfnoc/utils/ctrlport_to_settings_bus.v
new file mode 100644
index 000000000..121b0ea40
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/utils/ctrlport_to_settings_bus.v
@@ -0,0 +1,241 @@
+//
+// Copyright 2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: ctrlport_to_settings_bus
+//
+// Description: 
+//
+//   Converts CTRL port interface requests to a user register settings bus 
+//   access. This can be used to connect RFNoC block IP settings registers and 
+//   user read-back registers to a control port.
+//
+//   There are a few key differences between control port and the settings bus 
+//   that need to be accounted for. 
+//
+//    * Control port uses byte address whereas the settings bus uses a 
+//      word address. 
+//    * Control port is 32-bit whereas the settings bus supports 
+//      32-bit writes and 64-bit reads.
+//    * The settings bus always does both a write and a read for each
+//      transaction. If the intent is to read a register, then it writes the
+//      address for the read to SR_RB_ADDR. If the intent is to write a
+//      register, then the read result is ignored.
+//
+//   This block handles these differences by allocating a 2048-byte address 
+//   space to each settings bus. Each word of the settings bus is treated like 
+//   a 64-bit word on an eight-byte boundary. To write to a settings register 
+//   N, simply write a 32-bit value to address N*8. To read read-back register 
+//   N, simply perform a 32-bit read from address N*8 followed by a 32-bit read 
+//   from address N*8+4 to get the full 64-bits. If only the lower 32-bits are 
+//   needed then it is not necessary to read the upper 32 bits. Note however, 
+//   that software must always read the lower 32-bits before trying to read the 
+//   upper 32-bits and that these reads should be atomic (no intervening reads 
+//   should occur).
+//
+// Parameters:
+//
+//   NUM_PORTS  : The number of settings buses you wish to connect 
+//
+//   SR_RB_ADDR : Address to use for the settings register that holds the
+//                read-back address. Set to 124 to model register access to
+//                user logic registers. Set to 127 to model access to internal
+//                NoC shell registers.
+//
+//   USE_TIME   : When 0, timestamps are simply passed from ctrlport to
+//                settings bus and the timestamp input is not used. When 1,
+//                this block will wait until the indicated time to arrive on
+//                the timestamp input before issuing the transaction on the
+//                settings bus. In this case, the time must be provided on the
+//                timestamp input.
+//
+
+module ctrlport_to_settings_bus #(
+  parameter NUM_PORTS  = 1,
+  parameter SR_RB_ADDR = 124,
+  parameter USE_TIME   = 0
+) (
+  input wire ctrlport_clk,
+  input wire ctrlport_rst,
+
+  //---------------------------------------------------------------------------
+  // CTRL Port Interface
+  //---------------------------------------------------------------------------
+
+  input  wire        s_ctrlport_req_wr,
+  input  wire        s_ctrlport_req_rd,
+  input  wire [19:0] s_ctrlport_req_addr,
+  input  wire [31:0] s_ctrlport_req_data,
+  input  wire        s_ctrlport_req_has_time,
+  input  wire [63:0] s_ctrlport_req_time,
+  output reg         s_ctrlport_resp_ack = 0,
+  output reg  [31:0] s_ctrlport_resp_data,
+
+  //---------------------------------------------------------------------------
+  // Settings Bus Interface
+  //---------------------------------------------------------------------------
+
+  output wire [NUM_PORTS*32-1:0] set_data,
+  output wire [ NUM_PORTS*8-1:0] set_addr,
+  output reg  [   NUM_PORTS-1:0] set_stb = 0,
+  output wire [NUM_PORTS*64-1:0] set_time,
+  output wire [   NUM_PORTS-1:0] set_has_time,
+
+  input  [NUM_PORTS-1:0]    rb_stb,
+  output [NUM_PORTS*8-1:0]  rb_addr,
+  input  [NUM_PORTS*64-1:0] rb_data,
+
+  //---------------------------------------------------------------------------
+  // Timestamp
+  //---------------------------------------------------------------------------
+
+  // Current timestamp, synchronous to ctrlport_clk
+  input wire [63:0] timestamp
+);
+
+  localparam PORT_W = (NUM_PORTS > 1) ? $clog2(NUM_PORTS) : 1;
+
+  wire [PORT_W-1:0] port_num;
+  reg  [PORT_W-1:0] port_num_reg;
+
+  wire msw_access;
+
+  reg [31:0] set_data_reg;
+  reg [ 7:0] set_addr_reg;
+  reg [63:0] set_time_reg;
+  reg        set_has_time_reg;
+  reg [ 7:0] rb_addr_reg;
+
+  reg [31:0] upper_word;
+
+  // Extract the port index from the address (the bits above the lower 11 bits)
+  assign port_num = (NUM_PORTS > 1) ? s_ctrlport_req_addr[(PORT_W+11)-1:11] : 0;
+
+  // Determine if the upper word is being accessed
+  assign msw_access = s_ctrlport_req_addr[2];
+
+  localparam ST_IDLE        = 0;
+  localparam ST_TIME_CHECK  = 1;
+  localparam ST_STROBE_WAIT = 2;
+  localparam ST_WAIT_RESP   = 3;
+
+  reg [2:0] state = ST_IDLE;
+
+
+  always @(posedge ctrlport_clk) begin
+    if (ctrlport_rst) begin
+      s_ctrlport_resp_ack  <= 0;
+      set_stb              <= 0;
+      state                <= ST_IDLE;
+      s_ctrlport_resp_data <= 32'hX;
+      set_addr_reg         <= 8'hX;
+      rb_addr_reg          <= 8'hX;
+      port_num_reg         <= 8'hX;
+      upper_word           <= 32'hX;
+    end else begin
+      // Default assignments
+      s_ctrlport_resp_ack <= 0;
+      set_stb             <= 0;
+
+      case (state)
+        ST_IDLE : begin
+          if (s_ctrlport_req_rd && port_num < NUM_PORTS) begin
+            // Handle register reads (read-back registers)
+            if (msw_access) begin
+              // Reading the upper word always returns the cached upper-word value 
+              // from the previous lower-word read.
+              s_ctrlport_resp_ack  <= 1;
+              s_ctrlport_resp_data <= upper_word;
+            end else begin
+              // Handle register reads (read-back registers)
+              rb_addr_reg <= s_ctrlport_req_addr[10:3];
+
+              // Read-back of a user register on settings bus is always
+              // combined with a write to the SR_RB_ADDR address.
+              set_addr_reg     <= SR_RB_ADDR;
+              set_data_reg     <= 32'bX;    // CtrlPort has no data in this case
+              set_time_reg     <= s_ctrlport_req_time;
+              set_has_time_reg <= s_ctrlport_req_has_time;
+
+              // Save which port the read is for so that we only watch for 
+              // acknowledgments from that port.
+              port_num_reg <= port_num;
+
+              if (USE_TIME) begin
+                state <= ST_TIME_CHECK;
+              end else begin
+                set_stb[port_num] <= 1;
+                state             <= ST_STROBE_WAIT;
+              end
+            end
+
+          end else if (s_ctrlport_req_wr && port_num < NUM_PORTS) begin
+            // Handle register writes (settings registers)
+            set_addr_reg     <= s_ctrlport_req_addr[10:3];
+            set_data_reg     <= s_ctrlport_req_data;
+            set_time_reg     <= s_ctrlport_req_time;
+            set_has_time_reg <= s_ctrlport_req_has_time;
+
+            // Save which port the write is for so that we only watch for 
+            // acknowledgments from that port.
+            port_num_reg <= port_num;
+
+            if (USE_TIME) begin
+              state <= ST_TIME_CHECK;
+            end else begin
+              set_stb[port_num] <= 1;
+              state             <= ST_STROBE_WAIT;
+            end
+          end
+        end
+
+        ST_TIME_CHECK : begin
+          // If the transaction is timed, wait until the time arrives before
+          // starting. This state is only reachable if USE_TIME is true.
+          if (set_has_time_reg) begin
+            if (timestamp >= set_time_reg) begin
+              set_stb[port_num_reg] <= 1;
+              state                 <= ST_STROBE_WAIT;
+            end
+          end else begin
+            set_stb[port_num_reg] <= 1;
+            state                 <= ST_STROBE_WAIT;
+          end
+        end
+
+        ST_STROBE_WAIT : begin
+          // Wait a cycle before checking for a response
+          state <= ST_WAIT_RESP;
+        end
+
+        ST_WAIT_RESP : begin
+          // Wait for read completion on settings bus, acknowledged by rb_stb.
+          // The read-back data will be ignored by ctrlport if this is a write.
+          upper_word           <= rb_data[(64*port_num_reg + 32) +: 32];
+          s_ctrlport_resp_data <= rb_data[(64*port_num_reg +  0) +: 32];
+          if (rb_stb[port_num_reg] == 1) begin
+            s_ctrlport_resp_ack <= 1;
+            state               <= ST_IDLE;
+          end
+        end
+      
+      endcase
+    end
+  end
+
+
+  genvar i;
+  generate
+    for (i = 0; i < NUM_PORTS; i = i+1) begin : gen_settings_bus
+      // Drive all settings buses with the same values, except the strobe
+      assign rb_addr      [ 8*i +:  8] = rb_addr_reg;
+      assign set_data     [32*i +: 32] = set_data_reg;
+      assign set_addr     [ 8*i +:  8] = set_addr_reg;
+      assign set_time     [64*i +: 64] = set_time_reg;
+      assign set_has_time [         i] = set_has_time_reg;
+    end
+  endgenerate
+
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/utils/noc_shell_generic_ctrlport_pyld_chdr.v b/fpga/usrp3/lib/rfnoc/utils/noc_shell_generic_ctrlport_pyld_chdr.v
new file mode 100644
index 000000000..3a0e7fea7
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/utils/noc_shell_generic_ctrlport_pyld_chdr.v
@@ -0,0 +1,273 @@
+//
+// Copyright 2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: noc_shell_generic_ctrlport_pyld_chdr
+// Description:
+//
+// Parameters:
+//
+// Signals:
+
+module noc_shell_generic_ctrlport_pyld_chdr #(
+  parameter [31:0] NOC_ID          = 32'h0,
+  parameter  [9:0] THIS_PORTID     = 10'd0,
+  parameter        CHDR_W          = 64,
+  parameter  [5:0] CTRL_FIFOSIZE   = 0,
+  parameter  [0:0] CTRLPORT_SLV_EN = 1,
+  parameter  [5:0] NUM_DATA_I      = 0,
+  parameter  [5:0] NUM_DATA_O      = 0,
+  parameter        ITEM_W          = 32,
+  parameter        NIPC            = 2,
+  parameter  [5:0] MTU             = 0,
+  parameter        CTXT_FIFOSIZE   = 1,
+  parameter        PYLD_FIFOSIZE   = 1
+)(
+  // Framework Interface
+  //------------------------------------------------------------
+  // RFNoC Framework Clocks and Resets
+  input  wire                                 rfnoc_chdr_clk,
+  output wire                                 rfnoc_chdr_rst,
+  input  wire                                 rfnoc_ctrl_clk,
+  output wire                                 rfnoc_ctrl_rst,
+  // RFNoC Backend Interface                  
+  input  wire [511:0]                         rfnoc_core_config,
+  output wire [511:0]                         rfnoc_core_status,
+  // CHDR Input Ports (from framework)        
+  input  wire [(CHDR_W*NUM_DATA_I)-1:0]       s_rfnoc_chdr_tdata,
+  input  wire [NUM_DATA_I-1:0]                s_rfnoc_chdr_tlast,
+  input  wire [NUM_DATA_I-1:0]                s_rfnoc_chdr_tvalid,
+  output wire [NUM_DATA_I-1:0]                s_rfnoc_chdr_tready,
+  // CHDR Output Ports (to framework)         
+  output wire [(CHDR_W*NUM_DATA_O)-1:0]       m_rfnoc_chdr_tdata,
+  output wire [NUM_DATA_O-1:0]                m_rfnoc_chdr_tlast,
+  output wire [NUM_DATA_O-1:0]                m_rfnoc_chdr_tvalid,
+  input  wire [NUM_DATA_O-1:0]                m_rfnoc_chdr_tready,
+  // AXIS-Ctrl Input Port (from framework)
+  input  wire [31:0]                          s_rfnoc_ctrl_tdata,
+  input  wire                                 s_rfnoc_ctrl_tlast,
+  input  wire                                 s_rfnoc_ctrl_tvalid,
+  output wire                                 s_rfnoc_ctrl_tready,
+  // AXIS-Ctrl Output Port (to framework)
+  output wire [31:0]                          m_rfnoc_ctrl_tdata,
+  output wire                                 m_rfnoc_ctrl_tlast,
+  output wire                                 m_rfnoc_ctrl_tvalid,
+  input  wire                                 m_rfnoc_ctrl_tready,
+
+  // Client Interface
+  //------------------------------------------------------------
+  // Control Port Master (Request)            
+  output wire                                 m_ctrlport_req_wr,
+  output wire                                 m_ctrlport_req_rd,
+  output wire [19:0]                          m_ctrlport_req_addr,
+  output wire [31:0]                          m_ctrlport_req_data,
+  output wire [3:0]                           m_ctrlport_req_byte_en,
+  output wire                                 m_ctrlport_req_has_time,
+  output wire [63:0]                          m_ctrlport_req_time,
+  input  wire                                 m_ctrlport_resp_ack,
+  input  wire [1:0]                           m_ctrlport_resp_status,
+  input  wire [31:0]                          m_ctrlport_resp_data,
+  // Control Port Slave (Request)             
+  input  wire                                 s_ctrlport_req_wr,
+  input  wire                                 s_ctrlport_req_rd,
+  input  wire [19:0]                          s_ctrlport_req_addr,
+  input  wire [9:0]                           s_ctrlport_req_portid,
+  input  wire [15:0]                          s_ctrlport_req_rem_epid,
+  input  wire [9:0]                           s_ctrlport_req_rem_portid,
+  input  wire [31:0]                          s_ctrlport_req_data,
+  input  wire [3:0]                           s_ctrlport_req_byte_en,
+  input  wire                                 s_ctrlport_req_has_time,
+  input  wire [63:0]                          s_ctrlport_req_time,
+  output wire                                 s_ctrlport_resp_ack,
+  output wire [1:0]                           s_ctrlport_resp_status,
+  output wire [31:0]                          s_ctrlport_resp_data,
+  // Payload stream out (to user logic)
+  output wire [(ITEM_W*NIPC*NUM_DATA_I)-1:0]  m_axis_payload_tdata,
+  output wire [(NIPC*NUM_DATA_I)-1:0]         m_axis_payload_tkeep,
+  output wire [NUM_DATA_I-1:0]                m_axis_payload_tlast,
+  output wire [NUM_DATA_I-1:0]                m_axis_payload_tvalid,
+  input  wire [NUM_DATA_I-1:0]                m_axis_payload_tready,
+  // Context stream out (to user logic)
+  output wire [(CHDR_W*NUM_DATA_I)-1:0]       m_axis_context_tdata,
+  output wire [(4*NUM_DATA_I)-1:0]            m_axis_context_tuser,
+  output wire [NUM_DATA_I-1:0]                m_axis_context_tlast,
+  output wire [NUM_DATA_I-1:0]                m_axis_context_tvalid,
+  input  wire [NUM_DATA_I-1:0]                m_axis_context_tready,
+  // Payload stream in (from user logic)
+  input  wire [(ITEM_W*NIPC*NUM_DATA_O)-1:0]  s_axis_payload_tdata,
+  input  wire [(NIPC*NUM_DATA_O)-1:0]         s_axis_payload_tkeep,
+  input  wire [NUM_DATA_O-1:0]                s_axis_payload_tlast,
+  input  wire [NUM_DATA_O-1:0]                s_axis_payload_tvalid,
+  output wire [NUM_DATA_O-1:0]                s_axis_payload_tready,
+  // Context stream in (from user logic)
+  input  wire [(CHDR_W*NUM_DATA_O)-1:0]       s_axis_context_tdata,
+  input  wire [(4*NUM_DATA_O)-1:0]            s_axis_context_tuser,
+  input  wire [NUM_DATA_O-1:0]                s_axis_context_tlast,
+  input  wire [NUM_DATA_O-1:0]                s_axis_context_tvalid,
+  output wire [NUM_DATA_O-1:0]                s_axis_context_tready
+);
+
+  // ---------------------------------------------------
+  //  Backend Interface
+  // ---------------------------------------------------
+  wire         data_i_flush_en;
+  wire [31:0]  data_i_flush_timeout;
+  wire [63:0]  data_i_flush_active;
+  wire [63:0]  data_i_flush_done;
+  wire         data_o_flush_en;
+  wire [31:0]  data_o_flush_timeout;
+  wire [63:0]  data_o_flush_active;
+  wire [63:0]  data_o_flush_done;
+
+  backend_iface #(
+    .NOC_ID               (NOC_ID       ),
+    .NUM_DATA_I           (NUM_DATA_I   ),
+    .NUM_DATA_O           (NUM_DATA_O   ),
+    .CTRL_FIFOSIZE        (CTRL_FIFOSIZE),
+    .MTU                  (MTU          )
+  ) backend_iface_i (
+    .rfnoc_chdr_clk       (rfnoc_chdr_clk      ),
+    .rfnoc_ctrl_clk       (rfnoc_ctrl_clk      ),
+    .rfnoc_core_config    (rfnoc_core_config   ),
+    .rfnoc_core_status    (rfnoc_core_status   ),
+    .rfnoc_chdr_rst       (rfnoc_chdr_rst      ),
+    .rfnoc_ctrl_rst       (rfnoc_ctrl_rst      ),
+    .data_i_flush_en      (data_i_flush_en     ),
+    .data_i_flush_timeout (data_i_flush_timeout),
+    .data_i_flush_active  (data_i_flush_active ),
+    .data_i_flush_done    (data_i_flush_done   ),
+    .data_o_flush_en      (data_o_flush_en     ),
+    .data_o_flush_timeout (data_o_flush_timeout),
+    .data_o_flush_active  (data_o_flush_active ),
+    .data_o_flush_done    (data_o_flush_done   )
+  );
+
+  // ---------------------------------------------------
+  //  Control Path
+  // ---------------------------------------------------
+
+  ctrlport_endpoint #(
+    .THIS_PORTID              (THIS_PORTID    ),
+    .SYNC_CLKS                (0              ),
+    .AXIS_CTRL_MST_EN         (CTRLPORT_SLV_EN),
+    .AXIS_CTRL_SLV_EN         (1              ),
+    .SLAVE_FIFO_SIZE          (CTRL_FIFOSIZE  )
+  ) ctrlport_ep_i (
+    .rfnoc_ctrl_clk           (rfnoc_ctrl_clk           ),
+    .rfnoc_ctrl_rst           (rfnoc_ctrl_rst           ),
+    .ctrlport_clk             (rfnoc_chdr_clk           ),
+    .ctrlport_rst             (rfnoc_chdr_rst           ),
+    .s_rfnoc_ctrl_tdata       (s_rfnoc_ctrl_tdata       ),
+    .s_rfnoc_ctrl_tlast       (s_rfnoc_ctrl_tlast       ),
+    .s_rfnoc_ctrl_tvalid      (s_rfnoc_ctrl_tvalid      ),
+    .s_rfnoc_ctrl_tready      (s_rfnoc_ctrl_tready      ),
+    .m_rfnoc_ctrl_tdata       (m_rfnoc_ctrl_tdata       ),
+    .m_rfnoc_ctrl_tlast       (m_rfnoc_ctrl_tlast       ),
+    .m_rfnoc_ctrl_tvalid      (m_rfnoc_ctrl_tvalid      ),
+    .m_rfnoc_ctrl_tready      (m_rfnoc_ctrl_tready      ),
+    .m_ctrlport_req_wr        (m_ctrlport_req_wr        ),
+    .m_ctrlport_req_rd        (m_ctrlport_req_rd        ),
+    .m_ctrlport_req_addr      (m_ctrlport_req_addr      ),
+    .m_ctrlport_req_data      (m_ctrlport_req_data      ),
+    .m_ctrlport_req_byte_en   (m_ctrlport_req_byte_en   ),
+    .m_ctrlport_req_has_time  (m_ctrlport_req_has_time  ),
+    .m_ctrlport_req_time      (m_ctrlport_req_time      ),
+    .m_ctrlport_resp_ack      (m_ctrlport_resp_ack      ),
+    .m_ctrlport_resp_status   (m_ctrlport_resp_status   ),
+    .m_ctrlport_resp_data     (m_ctrlport_resp_data     ),
+    .s_ctrlport_req_wr        (s_ctrlport_req_wr        ),
+    .s_ctrlport_req_rd        (s_ctrlport_req_rd        ),
+    .s_ctrlport_req_addr      (s_ctrlport_req_addr      ),
+    .s_ctrlport_req_portid    (s_ctrlport_req_portid    ),
+    .s_ctrlport_req_rem_epid  (s_ctrlport_req_rem_epid  ),
+    .s_ctrlport_req_rem_portid(s_ctrlport_req_rem_portid),
+    .s_ctrlport_req_data      (s_ctrlport_req_data      ),
+    .s_ctrlport_req_byte_en   (s_ctrlport_req_byte_en   ),
+    .s_ctrlport_req_has_time  (s_ctrlport_req_has_time  ),
+    .s_ctrlport_req_time      (s_ctrlport_req_time      ),
+    .s_ctrlport_resp_ack      (s_ctrlport_resp_ack      ),
+    .s_ctrlport_resp_status   (s_ctrlport_resp_status   ),
+    .s_ctrlport_resp_data     (s_ctrlport_resp_data     )
+  );
+
+  // ---------------------------------------------------
+  //  Data Path
+  // ---------------------------------------------------
+
+  genvar i;
+  generate 
+    for (i = 0; i < NUM_DATA_I; i = i + 1) begin: in
+      chdr_to_axis_pyld_ctxt #(
+        .CHDR_W               (CHDR_W        ),
+        .ITEM_W               (ITEM_W        ),
+        .NIPC                 (NIPC          ),
+        .SYNC_CLKS            (0             ),
+        .CONTEXT_FIFO_SIZE    (CTXT_FIFOSIZE),
+        .PAYLOAD_FIFO_SIZE    (PYLD_FIFOSIZE),
+        .CONTEXT_PREFETCH_EN  (1             )
+      ) chdr2raw_i (
+        .axis_chdr_clk        (rfnoc_chdr_clk                                       ),
+        .axis_chdr_rst        (rfnoc_chdr_rst                                       ),
+        .axis_data_clk        (rfnoc_chdr_clk                                       ),
+        .axis_data_rst        (rfnoc_chdr_rst                                       ),
+        .s_axis_chdr_tdata    (s_rfnoc_chdr_tdata   [(i*CHDR_W)+:CHDR_W]            ),
+        .s_axis_chdr_tlast    (s_rfnoc_chdr_tlast   [i]                             ),
+        .s_axis_chdr_tvalid   (s_rfnoc_chdr_tvalid  [i]                             ),
+        .s_axis_chdr_tready   (s_rfnoc_chdr_tready  [i]                             ),
+        .m_axis_payload_tdata (m_axis_payload_tdata [(i*ITEM_W*NIPC)+:(ITEM_W*NIPC)]),
+        .m_axis_payload_tkeep (m_axis_payload_tkeep [(i*NIPC)+:NIPC]                ),
+        .m_axis_payload_tlast (m_axis_payload_tlast [i]                             ),
+        .m_axis_payload_tvalid(m_axis_payload_tvalid[i]                             ),
+        .m_axis_payload_tready(m_axis_payload_tready[i]                             ),
+        .m_axis_context_tdata (m_axis_context_tdata [(i*CHDR_W)+:(CHDR_W)]          ),
+        .m_axis_context_tuser (m_axis_context_tuser [(i*4)+:4]                      ),
+        .m_axis_context_tlast (m_axis_context_tlast [i]                             ),
+        .m_axis_context_tvalid(m_axis_context_tvalid[i]                             ),
+        .m_axis_context_tready(m_axis_context_tready[i]                             ),
+        .flush_en             (data_i_flush_en                                      ),
+        .flush_timeout        (data_i_flush_timeout                                 ),
+        .flush_active         (data_i_flush_active  [i]                             ),
+        .flush_done           (data_i_flush_done    [i]                             )
+      );
+    end
+
+    for (i = 0; i < NUM_DATA_O; i = i + 1) begin: out
+      axis_pyld_ctxt_to_chdr #(
+        .CHDR_W               (CHDR_W        ),
+        .ITEM_W               (ITEM_W        ),
+        .NIPC                 (NIPC          ),
+        .SYNC_CLKS            (0             ),
+        .CONTEXT_FIFO_SIZE    (CTXT_FIFOSIZE ),
+        .PAYLOAD_FIFO_SIZE    (PYLD_FIFOSIZE ),
+        .CONTEXT_PREFETCH_EN  (1             ),
+        .MTU                  (MTU           )
+      ) raw2chdr_i (
+        .axis_chdr_clk        (rfnoc_chdr_clk                                       ),
+        .axis_chdr_rst        (rfnoc_chdr_rst                                       ),
+        .axis_data_clk        (rfnoc_chdr_clk                                       ),
+        .axis_data_rst        (rfnoc_chdr_rst                                       ),
+        .m_axis_chdr_tdata    (m_rfnoc_chdr_tdata   [(i*CHDR_W)+:CHDR_W]            ),
+        .m_axis_chdr_tlast    (m_rfnoc_chdr_tlast   [i]                             ),
+        .m_axis_chdr_tvalid   (m_rfnoc_chdr_tvalid  [i]                             ),
+        .m_axis_chdr_tready   (m_rfnoc_chdr_tready  [i]                             ),
+        .s_axis_payload_tdata (s_axis_payload_tdata [(i*ITEM_W*NIPC)+:(ITEM_W*NIPC)]),
+        .s_axis_payload_tkeep (s_axis_payload_tkeep [(i*NIPC)+:NIPC]                ),
+        .s_axis_payload_tlast (s_axis_payload_tlast [i]                             ),
+        .s_axis_payload_tvalid(s_axis_payload_tvalid[i]                             ),
+        .s_axis_payload_tready(s_axis_payload_tready[i]                             ),
+        .s_axis_context_tdata (s_axis_context_tdata [(i*CHDR_W)+:(CHDR_W)]          ),
+        .s_axis_context_tuser (s_axis_context_tuser [(i*4)+:4]                      ),
+        .s_axis_context_tlast (s_axis_context_tlast [i]                             ),
+        .s_axis_context_tvalid(s_axis_context_tvalid[i]                             ),
+        .s_axis_context_tready(s_axis_context_tready[i]                             ),
+        .framer_errors        (                                                     ),
+        .flush_en             (data_o_flush_en                                      ),
+        .flush_timeout        (data_o_flush_timeout                                 ),
+        .flush_active         (data_o_flush_active  [i]                             ),
+        .flush_done           (data_o_flush_done    [i]                             )
+      );
+    end
+  endgenerate
+
+endmodule // noc_shell_generic_ctrlport_raw
diff --git a/fpga/usrp3/lib/rfnoc/utils/timekeeper.v b/fpga/usrp3/lib/rfnoc/utils/timekeeper.v
new file mode 100644
index 000000000..404f45758
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/utils/timekeeper.v
@@ -0,0 +1,279 @@
+//
+// Copyright 2019 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: timekeeper
+//
+// Description: Timekeeper for RFNoC blocks. This block contains a 64-bit
+// counter to represent the current time in terms of sample clock cycles. The
+// counter can be updated and synchronized using the pps input.
+//
+// WARNING: All register larger than a single 32-bit word should be read and
+//          written least significant word first to guarantee coherency.
+//
+
+module timekeeper #(
+  parameter BASE_ADDR      = 'h00,
+  parameter TIME_INCREMENT = 1  // Amount by which to increment time on each sample clock cycle
+) (
+  input wire         tb_clk,        // Time-base clock
+  input wire         tb_rst,        // Time-base reset in tb_clk domain
+
+  //---------------------------------------------------------------------------
+  // Control Interface
+  //---------------------------------------------------------------------------
+
+  input  wire        s_ctrlport_clk,
+  input  wire        s_ctrlport_req_wr,
+  input  wire        s_ctrlport_req_rd,
+  input  wire [19:0] s_ctrlport_req_addr,
+  input  wire [31:0] s_ctrlport_req_data,
+  output wire        s_ctrlport_resp_ack,
+  output wire [31:0] s_ctrlport_resp_data,
+
+  //---------------------------------------------------------------------------
+  // Time
+  //---------------------------------------------------------------------------
+
+  input wire         sample_rx_stb,          // Sample Rx strobe (data valid indicator)
+  input wire         pps,                    // Pulse per second input
+  output reg [63:0]  tb_timestamp,           // 64-bit  global timestamp synchronous to tb_clk
+  output reg [63:0]  tb_timestamp_last_pps,  // 64-bit  global timestamp synchronous to tb_clk
+  output reg [63:0]  tb_period_ns_q32        // Time Period of time-base in nanoseconds
+);
+
+  //---------------------------------------------------------------------------
+  // Register Logic
+  //---------------------------------------------------------------------------
+
+  reg        set_time_pps;
+  reg        set_time_now;
+  reg        new_time_ctrl;
+  reg [63:0] time_at_next_event;       // Time to load at next timed event
+
+  reg [31:0] tb_timestamp_hi;          // Holding register for reading tb_timestamp
+  reg [31:0] time_at_next_event_lo;    // Holding register for writing time_at_next_event
+  reg [31:0] time_at_next_event_hi;    // Holding register for reading time_at_next_event
+  reg [31:0] tb_timestamp_last_pps_hi; // Holding register for reading tb_timestamp_last_pps
+
+  wire        s_ctrlport_req_wr_tb;
+  wire        s_ctrlport_req_rd_tb;
+  wire [19:0] s_ctrlport_req_addr_tb;
+  wire [31:0] s_ctrlport_req_data_tb;
+  reg         s_ctrlport_resp_ack_tb;
+  reg  [31:0] s_ctrlport_resp_data_tb;
+
+  // Clock crossing from ctrlport_clk to tb_clk domain
+
+  ctrlport_clk_cross ctrlport_clk_cross_tb_i (
+    .rst                       (tb_rst),
+    .s_ctrlport_clk            (s_ctrlport_clk),
+    .s_ctrlport_req_wr         (s_ctrlport_req_wr),
+    .s_ctrlport_req_rd         (s_ctrlport_req_rd),
+    .s_ctrlport_req_addr       (s_ctrlport_req_addr),
+    .s_ctrlport_req_portid     (),
+    .s_ctrlport_req_rem_epid   (),
+    .s_ctrlport_req_rem_portid (),
+    .s_ctrlport_req_data       (s_ctrlport_req_data),
+    .s_ctrlport_req_byte_en    (),
+    .s_ctrlport_req_has_time   (),
+    .s_ctrlport_req_time       (),
+    .s_ctrlport_resp_ack       (s_ctrlport_resp_ack),
+    .s_ctrlport_resp_status    (),
+    .s_ctrlport_resp_data      (s_ctrlport_resp_data),
+    .m_ctrlport_clk            (tb_clk),
+    .m_ctrlport_req_wr         (s_ctrlport_req_wr_tb),
+    .m_ctrlport_req_rd         (s_ctrlport_req_rd_tb),
+    .m_ctrlport_req_addr       (s_ctrlport_req_addr_tb),
+    .m_ctrlport_req_portid     (),
+    .m_ctrlport_req_rem_epid   (),
+    .m_ctrlport_req_rem_portid (),
+    .m_ctrlport_req_data       (s_ctrlport_req_data_tb),
+    .m_ctrlport_req_byte_en    (),
+    .m_ctrlport_req_has_time   (),
+    .m_ctrlport_req_time       (),
+    .m_ctrlport_resp_ack       (s_ctrlport_resp_ack_tb),
+    .m_ctrlport_resp_status    (),
+    .m_ctrlport_resp_data      (s_ctrlport_resp_data_tb)
+  );
+
+  //---------------------------------------------------------------------------
+  // Timekeeper Register Offsets
+  //---------------------------------------------------------------------------
+
+  localparam REG_TIME_NOW_LO         = 'h00;  // Current time count (low word)
+  localparam REG_TIME_NOW_HI         = 'h04;  // Current time count (high word)
+  localparam REG_TIME_EVENT_LO       = 'h08;  // Time for next event (low word)
+  localparam REG_TIME_EVENT_HI       = 'h0C;  // Time for next event (high word)
+  localparam REG_TIME_CTRL           = 'h10;  // Time control word
+  localparam REG_TIME_LAST_PPS_LO    = 'h14;  // Time of last PPS pulse edge (low word)
+  localparam REG_TIME_LAST_PPS_HI    = 'h18;  // Time of last PPS pulse edge (high word)
+  localparam REG_TIME_BASE_PERIOD_LO = 'h1C;  // Time Period in nanoseconds (low word)
+  localparam REG_TIME_BASE_PERIOD_HI = 'h20;  // Time Period in nanoseconds (high word)
+
+  // REG_TIME_CTRL bit fields
+  localparam TIME_NOW_POS  = 0;
+  localparam TIME_PPS_POS  = 1;
+
+  always @(posedge tb_clk) begin
+    if (tb_rst) begin
+      s_ctrlport_resp_ack_tb  <= 0;
+      s_ctrlport_resp_data_tb <= 0;
+      new_time_ctrl           <= 0;
+      set_time_pps            <= 0;
+      set_time_now            <= 0;
+    end else begin
+      // Default assignments
+      s_ctrlport_resp_ack_tb  <= 0;
+      s_ctrlport_resp_data_tb <= 0;
+      new_time_ctrl           <= 0;
+
+      // Handle register writes
+      if (s_ctrlport_req_wr_tb) begin
+        case (s_ctrlport_req_addr_tb)
+          BASE_ADDR + REG_TIME_EVENT_LO: begin
+            time_at_next_event_lo    <= s_ctrlport_req_data_tb;
+            s_ctrlport_resp_ack_tb   <= 1;
+          end
+          BASE_ADDR + REG_TIME_EVENT_HI: begin
+            time_at_next_event[31: 0] <= time_at_next_event_lo;
+            time_at_next_event[63:32] <= s_ctrlport_req_data_tb;
+            s_ctrlport_resp_ack_tb    <= 1;
+          end
+          BASE_ADDR + REG_TIME_CTRL: begin
+            set_time_pps            <= s_ctrlport_req_data_tb[TIME_PPS_POS];
+            set_time_now            <= s_ctrlport_req_data_tb[TIME_NOW_POS];
+            new_time_ctrl           <= 1;
+            s_ctrlport_resp_ack_tb  <= 1;
+          end
+          BASE_ADDR + REG_TIME_BASE_PERIOD_LO: begin
+            tb_period_ns_q32[31:0] <= s_ctrlport_req_data_tb;
+            s_ctrlport_resp_ack_tb <= 1;
+          end
+          BASE_ADDR + REG_TIME_BASE_PERIOD_HI: begin
+            tb_period_ns_q32[63:32] <= s_ctrlport_req_data_tb;
+            s_ctrlport_resp_ack_tb  <= 1;
+          end
+        endcase
+      end
+
+      // Handle register reads
+      if (s_ctrlport_req_rd_tb) begin
+        case (s_ctrlport_req_addr_tb)
+          BASE_ADDR + REG_TIME_NOW_LO: begin
+            s_ctrlport_resp_data_tb <= tb_timestamp[31:0];
+            tb_timestamp_hi         <= tb_timestamp[63:32];
+            s_ctrlport_resp_ack_tb  <= 1;
+          end
+          BASE_ADDR + REG_TIME_NOW_HI: begin
+            s_ctrlport_resp_data_tb <= tb_timestamp_hi;
+            s_ctrlport_resp_ack_tb  <= 1;
+          end
+          BASE_ADDR + REG_TIME_EVENT_LO: begin
+            s_ctrlport_resp_data_tb  <= time_at_next_event[31:0];
+            time_at_next_event_hi    <= time_at_next_event[63:32];
+            s_ctrlport_resp_ack_tb   <= 1;
+          end
+          BASE_ADDR + REG_TIME_EVENT_HI: begin
+            s_ctrlport_resp_data_tb <= time_at_next_event_hi;
+            s_ctrlport_resp_ack_tb  <= 1;
+          end
+          BASE_ADDR + REG_TIME_CTRL: begin
+            s_ctrlport_resp_data_tb                <= 0;
+            s_ctrlport_resp_data_tb[TIME_PPS_POS]  <= set_time_pps;
+            s_ctrlport_resp_data_tb[TIME_NOW_POS]  <= set_time_now;
+            s_ctrlport_resp_ack_tb                 <= 1;
+          end
+          BASE_ADDR + REG_TIME_LAST_PPS_LO: begin
+            s_ctrlport_resp_data_tb     <= tb_timestamp_last_pps[31:0];
+            tb_timestamp_last_pps_hi    <= tb_timestamp_last_pps[63:32];
+            s_ctrlport_resp_ack_tb      <= 1;
+          end
+          BASE_ADDR + REG_TIME_LAST_PPS_HI: begin
+            s_ctrlport_resp_data_tb <= tb_timestamp_last_pps_hi;
+            s_ctrlport_resp_ack_tb  <= 1;
+          end
+          BASE_ADDR + REG_TIME_BASE_PERIOD_LO: begin
+            s_ctrlport_resp_data_tb <= tb_period_ns_q32[31:0];
+            s_ctrlport_resp_ack_tb  <= 1;
+          end
+          BASE_ADDR + REG_TIME_BASE_PERIOD_HI: begin
+            s_ctrlport_resp_data_tb <= tb_period_ns_q32[63:32];
+            s_ctrlport_resp_ack_tb  <= 1;
+          end
+        endcase
+      end
+    end
+  end
+
+
+  //---------------------------------------------------------------------------
+  // Pulse Per Second
+  //---------------------------------------------------------------------------
+
+  reg pps_del;
+  reg pps_edge;
+
+  always @(posedge tb_clk) begin
+    if (tb_rst) begin
+      pps_del  <= 0;
+      pps_edge <= 0;
+    end else begin
+      pps_del <= pps;
+      pps_edge<= pps_del & ~pps;
+    end
+  end
+
+
+  //---------------------------------------------------------------------------
+  // Time Tracker
+  //---------------------------------------------------------------------------
+
+  reg time_event_armed; // Boolean to indicate if we're expecting a timed event
+
+  wire time_event =
+    time_event_armed && (
+      set_time_now || (set_time_pps && pps_edge)
+    );
+
+  always @(posedge tb_clk) begin
+    if (tb_rst) begin
+      tb_timestamp     <= 0;
+      time_event_armed <= 0;
+    end else begin
+      if (time_event) begin
+        // Load the timing info configured prior to the event
+        time_event_armed <= 0;
+        tb_timestamp     <= time_at_next_event;
+      end else if (sample_rx_stb) begin
+        // Update time for each sample word received
+        tb_timestamp <= tb_timestamp + TIME_INCREMENT;
+      end
+
+      if (new_time_ctrl) begin
+        // Indicate that we're expecting a timed event because the time control
+        // register was updated.
+        time_event_armed <= 1;
+      end
+    end
+  end
+
+
+  //---------------------------------------------------------------------------
+  // PPS Tracker
+  //---------------------------------------------------------------------------
+
+  always @(posedge tb_clk) begin
+    if (tb_rst) begin
+      tb_timestamp_last_pps <= 64'h0;
+    end else if (pps_edge) begin
+      if (time_event) begin
+        tb_timestamp_last_pps <= time_at_next_event;
+      end else begin
+        tb_timestamp_last_pps <= tb_timestamp + TIME_INCREMENT;
+      end
+    end
+  end
+
+endmodule
diff --git a/fpga/usrp3/lib/rfnoc/vector_iir.v b/fpga/usrp3/lib/rfnoc/vector_iir.v
new file mode 100644
index 000000000..a875f34fe
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/vector_iir.v
@@ -0,0 +1,187 @@
+//
+// Copyright 2018 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: vector_iir
+// Description: 
+//   This module implements an IIR filter with a variable length delay line.
+//   Transfer Function:                 beta
+//                        H(z) = ------------------
+//                               1 - alpha*z^-delay
+//   where:
+//   - beta is the feedforward tap
+//   - alpha is the feedback tap
+//   - delay (aka vector_len) is the feedback tap delay
+//
+// Parameters:
+//   - MAX_VECTOR_LEN: Maximum value for delay (vector_len)
+//   - IN_W: Input sample width for a real sample which includes the sign bit.
+//           The actual input of the module will be 2*IN_W because it handles
+//           complex data.
+//   - OUT_W: Output sample width for a real sample which includes the sign bit.
+//           The actual output of the module will be 2*OUT_W because it handles
+//           complex data.
+//   - ALPHA_W: Width of the alpha parameter (signed)
+//   - BETA_W: Width of the beta parameter (signed)
+//   - FEEDBACK_W: Number of bits in the feedback delay line (optimal = 25)
+//   - ACCUM_HEADROOM: Number of bits of headroom in the feedback accumulator
+// Signals:
+//   - i_*  : Input sample stream (AXI-Stream)
+//   - o_*  : Output sample stream (AXI-Stream)
+//   - set_*: Static settings
+//
+
+module vector_iir #(
+  parameter MAX_VECTOR_LEN  = 1024,
+  parameter IN_W            = 16,
+  parameter OUT_W           = 16,
+  parameter ALPHA_W         = 16,
+  parameter BETA_W          = 16,
+  parameter FEEDBACK_W      = 25,
+  parameter ACCUM_HEADROOM  = 4
+)(
+  input  wire                               clk,
+  input  wire                               reset,
+  input  wire [$clog2(MAX_VECTOR_LEN)-1:0]  set_vector_len,
+  input  wire [BETA_W-1:0]                  set_beta,
+  input  wire [ALPHA_W-1:0]                 set_alpha,
+  input  wire [IN_W*2-1:0]                  i_tdata,
+  input  wire                               i_tlast,
+  input  wire                               i_tvalid,
+  output wire                               i_tready,
+  output wire [OUT_W*2-1:0]                 o_tdata,
+  output wire                               o_tlast,
+  output wire                               o_tvalid,
+  input  wire                               o_tready
+);
+
+  // There are four registers between the input and output
+  // - Input pipeline (in_X_reg)
+  // - Feedforward product (ff_prod_X_reg)
+  // - Feedback sum (fb_sum_X_reg)
+  // - Output pipeline (dsp_data_out)
+  localparam IN_TO_OUT_LATENCY = 4;
+
+  // The feedback path has 3 cycles of delay
+  // - Feedback sum (fb_sum_X_reg)
+  // - variable_delay_line (2 cyc)
+  // - Scaled feedback (fb_sum_scaled_X_reg)
+  localparam MIN_FB_DELAY = 4;
+
+  // Pipeline settings for timing
+  reg [$clog2(MAX_VECTOR_LEN)-1:0]  reg_fb_delay;
+  reg signed [BETA_W-1:0]           reg_beta;
+  reg signed [ALPHA_W-1:0]          reg_alpha;
+
+  always @(posedge clk) begin
+    reg_fb_delay <= set_vector_len - MIN_FB_DELAY - 1;  //Adjust for pipeline delay
+    reg_beta     <= set_beta;
+    reg_alpha    <= set_alpha;
+  end
+
+  //-----------------------------------------------------------
+  // AXI-Stream wrapper
+  //-----------------------------------------------------------
+  wire [(IN_W*2)-1:0]           dsp_data_in;
+  reg  [(OUT_W*2)-1:0]          dsp_data_out = 0;
+  wire [IN_TO_OUT_LATENCY-1:0]  chain_en;
+
+  // We are implementing an N-cycle DSP operation without AXI-Stream handshaking.
+  // Use an axis_shift_register and the associated strobes to drive clock enables
+  // on the DSP regs to ensure that data/valid/last sync up.
+  axis_shift_register #(
+    .WIDTH(IN_W*2), .NSPC(1), .LATENCY(IN_TO_OUT_LATENCY),
+    .SIDEBAND_DATAPATH(1), .PIPELINE("NONE")
+  ) axis_shreg_i (
+    .clk(clk), .reset(reset),
+    .s_axis_tdata(i_tdata), .s_axis_tkeep(1'b1), .s_axis_tlast(i_tlast),
+    .s_axis_tvalid(i_tvalid), .s_axis_tready(i_tready),
+    .m_axis_tdata(o_tdata), .m_axis_tkeep(), .m_axis_tlast(o_tlast),
+    .m_axis_tvalid(o_tvalid), .m_axis_tready(o_tready),
+    .stage_stb(chain_en), .stage_eop(),
+    .m_sideband_data(dsp_data_in), .m_sideband_keep(),
+    .s_sideband_data(dsp_data_out)
+  );
+
+  //-----------------------------------------------------------
+  // DSP datapath
+  //-----------------------------------------------------------
+  localparam FF_PROD_W = IN_W + BETA_W - 1;
+  localparam FB_PROD_W = FEEDBACK_W + ALPHA_W - 1;
+
+  reg  signed [IN_W-1:0]        in_i_reg = 0, in_q_reg = 0;
+  reg  signed [FF_PROD_W-1:0]   ff_prod_i_reg = 0, ff_prod_q_reg = 0;
+  reg  signed [FB_PROD_W-1:0]   fb_sum_i_reg = 0, fb_sum_q_reg = 0;
+  wire signed [FB_PROD_W-1:0]   fb_trunc_i, fb_trunc_q;
+  wire signed [FEEDBACK_W-1:0]  fb_sum_del_i, fb_sum_del_q;
+  reg  signed [FB_PROD_W-1:0]   fb_sum_scaled_i_reg = 0, fb_sum_scaled_q_reg = 0;
+  wire signed [OUT_W-1:0]       out_i_rnd, out_q_rnd;
+
+  always @(posedge clk) begin
+    if (reset) begin
+      {in_i_reg, in_q_reg} <= 0;
+      ff_prod_i_reg <= 0;
+      ff_prod_q_reg <= 0;
+      fb_sum_i_reg <= 0;
+      fb_sum_q_reg <= 0;
+      fb_sum_scaled_i_reg <= 0;
+      fb_sum_scaled_q_reg <= 0;
+      dsp_data_out <= 0;
+    end else begin
+      if (chain_en[0]) begin
+        // Input pipeline register
+        {in_i_reg, in_q_reg} <= dsp_data_in;
+      end
+      if (chain_en[1]) begin
+        // Feedforward product (x[n] * beta)
+        ff_prod_i_reg <= in_i_reg * reg_beta;
+        ff_prod_q_reg <= in_q_reg * reg_beta;
+        // Compute scaled, delayed feedback (y[n-D] * alpha)
+        fb_sum_scaled_i_reg <= fb_sum_del_i * reg_alpha;
+        fb_sum_scaled_q_reg <= fb_sum_del_q * reg_alpha;
+      end
+      if (chain_en[2]) begin
+        // Sum of feedforward product and scaled, delayed feedback
+        // y[n] = (alpha * y[n-D]) + (x[n] * beta)
+        fb_sum_i_reg <= fb_sum_scaled_i_reg + (ff_prod_i_reg <<< (FB_PROD_W - FF_PROD_W - ACCUM_HEADROOM));
+        fb_sum_q_reg <= fb_sum_scaled_q_reg + (ff_prod_q_reg <<< (FB_PROD_W - FF_PROD_W - ACCUM_HEADROOM));
+      end
+      if (chain_en[3]) begin
+        // Output pipeline register
+        dsp_data_out <= {out_i_rnd, out_q_rnd};
+      end
+    end
+  end
+
+  // Truncate feedback to the requested FEEDBACK_W
+  assign fb_trunc_i = (fb_sum_i_reg >>> (FB_PROD_W - FEEDBACK_W));
+  assign fb_trunc_q = (fb_sum_q_reg >>> (FB_PROD_W - FEEDBACK_W));
+
+  // A variable delay line will be used to store the feedback
+  // This delay line stores "reg_fb_delay" worth of samples which
+  // allows each element in the vector to have it's own independent state
+  variable_delay_line #(
+    .WIDTH(FEEDBACK_W * 2), .DEPTH(MAX_VECTOR_LEN - MIN_FB_DELAY),
+    .DYNAMIC_DELAY(1), .DEFAULT_DATA(0), .OUT_REG(1)
+  ) delay_line_inst (
+    .clk(clk), .clk_en(chain_en[1]), .reset(reset),
+    .stb_in(1'b1),
+    .data_in({fb_trunc_i[FEEDBACK_W-1:0], fb_trunc_q[FEEDBACK_W-1:0]}),
+    .delay(reg_fb_delay),
+    .data_out({fb_sum_del_i, fb_sum_del_q})
+  );
+
+  // Round the accumulator output to produce the final output
+  round #(
+    .bits_in(FB_PROD_W-ACCUM_HEADROOM), .bits_out(OUT_W)
+  ) out_round_i_inst (
+    .in(fb_sum_i_reg[FB_PROD_W-ACCUM_HEADROOM-1:0]), .out(out_i_rnd), .err()
+  );
+  round #(
+    .bits_in(FB_PROD_W-ACCUM_HEADROOM), .bits_out(OUT_W)
+  ) out_round_q_inst (
+    .in(fb_sum_q_reg[FB_PROD_W-ACCUM_HEADROOM-1:0]), .out(out_q_rnd), .err()
+  );
+
+endmodule // vector_iir
diff --git a/fpga/usrp3/lib/rfnoc/xport/Makefile.srcs b/fpga/usrp3/lib/rfnoc/xport/Makefile.srcs
new file mode 100644
index 000000000..12582750b
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/xport/Makefile.srcs
@@ -0,0 +1,17 @@
+#
+# Copyright 2018 Ettus Research, A National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+##################################################
+# RFNoC Utility Sources
+##################################################
+RFNOC_XPORT_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/rfnoc/xport/, \
+chdr_xport_adapter_generic.v \
+eth_ipv4_chdr64_adapter.v \
+eth_ipv4_chdr64_dispatch.v \
+eth_interface.v \
+eth_internal.v \
+liberio_chdr64_adapter.v \
+))
diff --git a/fpga/usrp3/lib/rfnoc/xport/chdr_xport_adapter_generic.v b/fpga/usrp3/lib/rfnoc/xport/chdr_xport_adapter_generic.v
new file mode 100644
index 000000000..6de298530
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/xport/chdr_xport_adapter_generic.v
@@ -0,0 +1,397 @@
+//
+// Copyright 2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: chdr_xport_adapter_generic
+// Description: A generic transport adapter module that can be used in
+//   a veriety of transports. It does the following:
+//   - Exposes a configuration port for mgmt packets to configure the node
+//   - Implements a return-address map for packets with metadata other than
+//     the CHDR. Additional metadata can be passed as a tuser to this module
+//     which will store it in a map indexed by the SrcEPID in a management
+//     packet. For all returning packets, the metadata will be looked up in
+//     the map and attached as the outgoing tuser.
+//   - Implements a loopback path for node-info discovery
+//   - Converts data stream to/from "RFNoC Network Order" (64-bit-Big-Endian)
+//
+// Parameters:
+//   - PROTOVER: RFNoC protocol version {8'd<major>, 8'd<minor>}
+//   - CHDR_W: Width of the CHDR bus in bits
+//   - USER_W: Width of the tuser bus in bits
+//   - TBL_SIZE: Log2 of the depth of the routing table
+//   - NODE_TYPE: The node type to return for a node-info discovery
+//   - NODE_INST: The node type to return for a node-info discovery
+//
+// Signals:
+//   - device_id     : The ID of the device that has instantiated this module
+//   - s_axis_xport_*: The input CHDR stream from the transport (plus tuser metadata)
+//   - m_axis_xport_*: The output CHDR stream to transport (plus tuser metadata)
+//   - s_axis_rfnoc_*: The input CHDR stream from the rfnoc infrastructure
+//   - m_axis_rfnoc_*: The output CHDR stream to the rfnoc infrastructure
+//   - ctrlport_*    : The ctrlport interface for the configuration port
+//
+
+module chdr_xport_adapter_generic #(
+  parameter [15:0] PROTOVER     = {8'd1, 8'd0},
+  parameter        CHDR_W       = 256,
+  parameter        USER_W       = 16,
+  parameter        TBL_SIZE     = 6,
+  parameter [7:0]  NODE_SUBTYPE = 8'd0,
+  parameter        NODE_INST    = 0
+)(
+  // Clock and reset
+  input  wire               clk,
+  input  wire               rst,
+  // Device info
+  input  wire [15:0]        device_id,
+  // Transport stream in (AXI-Stream)
+  input  wire [CHDR_W-1:0]  s_axis_xport_tdata,
+  input  wire [USER_W-1:0]  s_axis_xport_tuser,
+  input  wire               s_axis_xport_tlast,
+  input  wire               s_axis_xport_tvalid,
+  output wire               s_axis_xport_tready,
+  // Transport stream out (AXI-Stream)
+  output wire [CHDR_W-1:0]  m_axis_xport_tdata,
+  output wire [USER_W-1:0]  m_axis_xport_tuser,
+  output wire               m_axis_xport_tlast,
+  output wire               m_axis_xport_tvalid,
+  input  wire               m_axis_xport_tready,
+  // RFNoC stream in (AXI-Stream)
+  input  wire [CHDR_W-1:0]  s_axis_rfnoc_tdata,
+  input  wire               s_axis_rfnoc_tlast,
+  input  wire               s_axis_rfnoc_tvalid,
+  output wire               s_axis_rfnoc_tready,
+  // RFNoC stream out (AXI-Stream)
+  output wire [CHDR_W-1:0]  m_axis_rfnoc_tdata,
+  output wire               m_axis_rfnoc_tlast,
+  output wire               m_axis_rfnoc_tvalid,
+  input  wire               m_axis_rfnoc_tready,
+  // Control port endpoint
+  output wire               ctrlport_req_wr,
+  output wire               ctrlport_req_rd,
+  output wire [15:0]        ctrlport_req_addr,
+  output wire [31:0]        ctrlport_req_data,
+  input  wire               ctrlport_resp_ack,
+  input  wire [31:0]        ctrlport_resp_data
+);
+
+  // ---------------------------------------------------
+  // RFNoC Includes
+  // ---------------------------------------------------
+  `include "../core/rfnoc_chdr_utils.vh"
+  `include "../core/rfnoc_chdr_internal_utils.vh"
+
+  // ---------------------------------------------------
+  // Reverse groups of 64-bit words to translate
+  // stream to "RFNoC Network Order" i.e. Big-Endian
+  // in groups of 8 bytes
+  // ---------------------------------------------------
+  wire [CHDR_W-1:0]  i_xport_tdata;
+  wire [USER_W-1:0]  i_xport_tuser;
+  wire               i_xport_tlast, i_xport_tvalid, i_xport_tready;
+  wire [CHDR_W-1:0]  o_xport_tdata;
+  wire [USER_W-1:0]  o_xport_tuser;
+  wire               o_xport_tlast, o_xport_tvalid, o_xport_tready;
+
+  localparam [$clog2(CHDR_W)-1:0] SWAP_LANES = ((CHDR_W / 64) - 1) << 6;
+
+  axis_data_swap #(
+    .DATA_W(CHDR_W), .USER_W(USER_W), .STAGES_EN(SWAP_LANES), .DYNAMIC(0)
+  ) xport_in_swap_i (
+    .clk(clk), .rst(rst),
+    .s_axis_tdata(s_axis_xport_tdata), .s_axis_tswap('h0),
+    .s_axis_tuser(s_axis_xport_tuser), .s_axis_tlast(s_axis_xport_tlast),
+    .s_axis_tvalid(s_axis_xport_tvalid), .s_axis_tready(s_axis_xport_tready),
+    .m_axis_tdata (i_xport_tdata), .m_axis_tuser(i_xport_tuser),
+    .m_axis_tlast (i_xport_tlast),
+    .m_axis_tvalid(i_xport_tvalid), .m_axis_tready(i_xport_tready)
+  );
+
+  axis_data_swap #(
+    .DATA_W(CHDR_W), .USER_W(USER_W), .STAGES_EN(SWAP_LANES), .DYNAMIC(0)
+  ) xport_out_swap_i (
+    .clk(clk), .rst(rst),
+    .s_axis_tdata(o_xport_tdata), .s_axis_tswap('h0),
+    .s_axis_tuser(o_xport_tuser), .s_axis_tlast(o_xport_tlast),
+    .s_axis_tvalid(o_xport_tvalid), .s_axis_tready(o_xport_tready),
+    .m_axis_tdata (m_axis_xport_tdata), .m_axis_tuser (m_axis_xport_tuser),
+    .m_axis_tlast (m_axis_xport_tlast),
+    .m_axis_tvalid(m_axis_xport_tvalid), .m_axis_tready(m_axis_xport_tready)
+  );
+
+
+  wire [CHDR_W-1:0] x2d_tdata;  // Xport => Demux
+  reg  [USER_W-1:0] x2d_tuser;
+  wire [1:0]        x2d_tid;
+  wire              x2d_tlast, x2d_tvalid, x2d_tready;
+  wire [CHDR_W-1:0] x2x_tdata;  // Xport => Xport (loopback)
+  wire [USER_W-1:0] x2x_tuser;
+  wire              x2x_tlast, x2x_tvalid, x2x_tready;
+  wire [CHDR_W-1:0] m2x_tdata;  // Mux => Xport
+  wire              m2x_tdest;  // 1: Return to src, 0: CHDR input
+  wire [USER_W-1:0] m2x_tuser;
+  wire              m2x_tlast, m2x_tvalid, m2x_tready;
+
+  // ---------------------------------------------------
+  // Transport => DEMUX
+  // ---------------------------------------------------
+  wire              op_stb;
+  wire [15:0]       op_src_epid;
+  wire [USER_W-1:0] op_data;
+  wire              lookup_stb, lookup_done_stb, lookup_result_match;
+  wire [15:0]       lookup_epid;
+  wire [USER_W-1:0] lookup_result_value;
+
+  chdr_mgmt_pkt_handler #(
+    .PROTOVER(PROTOVER), .CHDR_W(CHDR_W), .USER_W(USER_W), .MGMT_ONLY(0)
+  ) mgmt_ep_i (
+    .clk(clk), .rst(rst),
+    .node_info(chdr_mgmt_build_node_info({10'h0, NODE_SUBTYPE}, NODE_INST, NODE_TYPE_TRANSPORT, device_id)),
+    .s_axis_chdr_tdata(i_xport_tdata), .s_axis_chdr_tlast(i_xport_tlast),
+    .s_axis_chdr_tvalid(i_xport_tvalid), .s_axis_chdr_tready(i_xport_tready),
+    .s_axis_chdr_tuser(i_xport_tuser),
+    .m_axis_chdr_tdata(x2d_tdata), .m_axis_chdr_tlast(x2d_tlast),
+    .m_axis_chdr_tdest(/* unused */), .m_axis_chdr_tid(x2d_tid),
+    .m_axis_chdr_tvalid(x2d_tvalid), .m_axis_chdr_tready(x2d_tready),
+    .ctrlport_req_wr(ctrlport_req_wr), .ctrlport_req_rd(ctrlport_req_rd),
+    .ctrlport_req_addr(ctrlport_req_addr), .ctrlport_req_data(ctrlport_req_data),
+    .ctrlport_resp_ack(ctrlport_resp_ack), .ctrlport_resp_data(ctrlport_resp_data),
+    .op_stb(op_stb), .op_dst_epid(/* unused */), .op_src_epid(op_src_epid), .op_data(op_data)
+  );
+
+  kv_map #(
+    .KEY_WIDTH(16), .VAL_WIDTH(USER_W), .SIZE(TBL_SIZE)
+  ) kv_map_i (
+    .clk(clk), .reset(rst),
+    .insert_stb(op_stb), .insert_key(op_src_epid), .insert_val(op_data),
+    .insert_busy(/* Time between op_stb > Insertion time */),
+    .find_key_stb(lookup_stb), .find_key(lookup_epid),
+    .find_res_stb(lookup_done_stb),
+    .find_res_match(lookup_result_match), .find_res_val(lookup_result_value),
+    .count(/* unused */)
+  );
+
+  reg i_xport_hdr = 1'b1;
+  always @(posedge clk) begin
+    if (rst)
+      i_xport_hdr <= 1'b1;
+    else if (i_xport_tvalid && i_xport_tready)
+      i_xport_hdr <= i_xport_tlast;
+  end
+
+  // chdr_mgmt_pkt_handler does not buffer packets and has at least one cycle of delay
+  // TODO: The tuser caching logic could be more robust
+  always @(posedge clk) begin
+    if (i_xport_tvalid && i_xport_tready && i_xport_hdr)
+      x2d_tuser <= i_xport_tuser;
+  end
+
+  // ---------------------------------------------------
+  // MUX and DEMUX for return path
+  // ---------------------------------------------------
+
+  wire [USER_W-1:0] dummy_tuser;
+  axis_switch #(
+    .DATA_W(CHDR_W+USER_W), .DEST_W(1), .IN_PORTS(1), .OUT_PORTS(2), .PIPELINE(0)
+  ) rtn_demux_i (
+    .clk(clk), .reset(rst),
+    .s_axis_tdata({x2d_tuser, x2d_tdata}), .s_axis_alloc(1'b0),
+    .s_axis_tdest(x2d_tid == CHDR_MGMT_RETURN_TO_SRC ? 2'b01 : 2'b00), 
+    .s_axis_tlast(x2d_tlast), .s_axis_tvalid(x2d_tvalid), .s_axis_tready(x2d_tready),
+    .m_axis_tdata({x2x_tuser, x2x_tdata, dummy_tuser, m_axis_rfnoc_tdata}),
+    .m_axis_tdest(/* unused */),
+    .m_axis_tlast({x2x_tlast, m_axis_rfnoc_tlast}),
+    .m_axis_tvalid({x2x_tvalid, m_axis_rfnoc_tvalid}),
+    .m_axis_tready({x2x_tready, m_axis_rfnoc_tready})
+  );
+
+  axi_mux #(
+    .WIDTH(CHDR_W+USER_W+1), .SIZE(2), .PRE_FIFO_SIZE(0), .POST_FIFO_SIZE(0)
+  ) rtn_mux_i (
+    .clk(clk), .reset(rst), .clear(1'b0),
+    .i_tdata({1'b1, x2x_tuser, x2x_tdata, 1'b0, {USER_W{1'b0}}, s_axis_rfnoc_tdata}),
+    .i_tlast({x2x_tlast, s_axis_rfnoc_tlast}),
+    .i_tvalid({x2x_tvalid, s_axis_rfnoc_tvalid}), .i_tready({x2x_tready, s_axis_rfnoc_tready}),
+    .o_tdata({m2x_tdest, m2x_tuser, m2x_tdata}), .o_tlast(m2x_tlast),
+    .o_tvalid(m2x_tvalid), .o_tready(m2x_tready)
+  );
+
+  // ---------------------------------------------------
+  // MUX => Transport
+  // ---------------------------------------------------
+
+  // In this section we must determine what value to put in tuser. If tdest is
+  // 1 then tuser is passed through unchanged. If tdest is 0 then the tuser
+  // value is looked up in the KV map using the EPID in the packet header.
+  //
+  // To do this we split the data (tdata, tlast) and the routing information
+  // (tdest, tuser, and the EPID) into two FIFOs. This allows us to perform a
+  // routing lookup and decide what to do while we continue to buffer data.
+  //
+  // With small packets, multiple routing lookups might be enqueued in the
+  // lookup_fifo, but we can only do one lookup at a time. Output logic
+  // controls release of packets from the data FIFO to ensure we only output
+  // one packet per lookup after the lookup is complete.
+
+  wire              data_fifo_i_tready;
+  wire [CHDR_W-1:0] data_fifo_o_tdata;
+  wire              data_fifo_o_tlast;
+  wire              data_fifo_o_tvalid;
+  wire              data_fifo_o_tready;
+  wire              lookup_fifo_i_tready;
+  wire              lookup_fifo_tdest;
+  wire [USER_W-1:0] lookup_fifo_tuser;
+  wire [      15:0] lookup_fifo_tepid;
+  wire              lookup_fifo_o_tvalid;
+  wire              lookup_fifo_o_tready;
+
+  wire             non_lookup_done_stb;
+  reg              data_fifo_o_hdr = 1'b1;
+  reg              pass_packet;
+  reg [USER_W-1:0] result_tuser;
+  reg              result_tuser_valid;
+  reg [USER_W-1:0] reg_o_tuser;
+
+
+  // Track when the next m2x word contains is the start of a new packet
+  reg m2x_hdr = 1'b1;
+  always @(posedge clk) begin
+    if (rst)
+      m2x_hdr <= 1'b1;
+    else if (m2x_tvalid && m2x_tready)
+      m2x_hdr <= m2x_tlast;
+  end
+
+  // We can only accept data from the mux when when both the data_fifo and
+  // lookup_fifo are ready.
+  assign m2x_tready = data_fifo_i_tready && lookup_fifo_i_tready;
+
+  // The data_fifo only takes the packet data (tdata, tlast). We use an
+  // axi_fifo_short module for the data_fifo because it can tolerate tvalid
+  // going low before a transfer completes.
+  axi_fifo_short #(
+    .WIDTH (1+CHDR_W)
+  ) data_fifo (
+    .clk      (clk),
+    .reset    (rst),
+    .clear    (1'b0),
+    .i_tdata  ({m2x_tlast, m2x_tdata}),
+    .i_tvalid (m2x_tvalid && m2x_tready),
+    .i_tready (data_fifo_i_tready),
+    .o_tdata  ({data_fifo_o_tlast, data_fifo_o_tdata}),
+    .o_tvalid (data_fifo_o_tvalid),
+    .o_tready (data_fifo_o_tready),
+    .space    (),
+    .occupied ()
+  );
+
+  // The lookup FIFO only takes the header routing info (tdest, tuser, epid).
+  // We use axi_fifo_short since it can tolerate tvalid going low before a
+  // transfer completes.
+  axi_fifo_short #(
+    .WIDTH (1+USER_W+16)
+  ) lookup_fifo (
+    .clk      (clk),
+    .reset    (rst),
+    .clear    (1'b0),
+    .i_tdata  ({m2x_tdest, m2x_tuser, chdr_get_dst_epid(m2x_tdata[63:0])}),
+    .i_tvalid (m2x_tvalid && m2x_tready && m2x_hdr),
+    .i_tready (lookup_fifo_i_tready),
+    .o_tdata  ({lookup_fifo_tdest, lookup_fifo_tuser, lookup_fifo_tepid}),
+    .o_tvalid (lookup_fifo_o_tvalid),
+    .o_tready (lookup_fifo_o_tready),
+    .space    (),
+    .occupied ()
+  );
+
+  // Keep track of when we are busy doing a lookup in the KV map.
+  reg lookup_busy = 1'b0;
+  always @(posedge clk) begin
+    if (rst)
+      lookup_busy <= 1'b0;
+    else begin
+      if (lookup_stb)
+        lookup_busy <= 1'b1;
+      else if (lookup_done_stb)
+        lookup_busy <= 1'b0;
+    end
+  end
+
+  // Determine if we can use the output of the lookup_fifo to do a KV map
+  // lookup. We only perform a KV map lookup if tdest is 0 and we can only do
+  // so if the KV map is free and the holding register for the tuser value is
+  // available.
+  assign lookup_epid = lookup_fifo_tepid;
+  assign lookup_stb  = lookup_fifo_o_tvalid && !lookup_busy &&
+                       !lookup_fifo_tdest   && !result_tuser_valid;
+
+  // Determine if we can use the output of the lookup FIFO directly (no lookup
+  // is needed). We can only use it if we're not already doing a KV lookup and
+  // if the holding register for the tuser value is available.
+  assign non_lookup_done_stb = lookup_fifo_o_tvalid && !lookup_busy &&
+                               lookup_fifo_tdest    && !result_tuser_valid;
+
+  // Pop the routing info off of the lookup_fifo if we've started its lookup
+  assign lookup_fifo_o_tready = lookup_stb || non_lookup_done_stb;
+
+  // Track when the next data_fifo_o word is the start of a new packet
+  always @(posedge clk) begin
+    if (rst)
+      data_fifo_o_hdr <= 1'b1;
+    else if (data_fifo_o_tvalid && data_fifo_o_tready && pass_packet)
+      data_fifo_o_hdr <= data_fifo_o_tlast;
+  end
+
+  // Store the lookup result in a holding register. This can come from the KV
+  // map or the incoming tuser.
+  always @(posedge clk) begin
+    if (rst) begin
+      result_tuser       <= {USER_W{1'bX}};    // Don't care
+      result_tuser_valid <= 1'b0;
+    end else begin
+      // The tuser holding register becomes available as soon as we start
+      // transmitting the corresponding packet.
+      if (data_fifo_o_tvalid && data_fifo_o_tready && data_fifo_o_hdr && pass_packet) begin
+        result_tuser_valid <= 1'b0;
+      end
+
+      // Load the result of the lookup
+      if (lookup_done_stb) begin
+        result_tuser       <= lookup_result_match ? lookup_result_value : {USER_W{1'b0}};
+        result_tuser_valid <= 1'b1;
+      end else if (non_lookup_done_stb) begin
+        result_tuser       <= lookup_fifo_tuser;
+        result_tuser_valid <= 1'b1;
+      end
+    end
+  end
+
+  // Control when the packet from the data_fifo can be passed through. Put the
+  // tuser value into a register for the duration of the packet.
+  always @(posedge clk) begin
+    if (rst) begin
+      pass_packet <= 1'b0;
+      reg_o_tuser <= {USER_W{1'bX}};    // Don't care
+    end else begin
+      // We're done passing through a packet when tlast goes out
+      if (data_fifo_o_tvalid && data_fifo_o_tready && data_fifo_o_tlast && pass_packet) begin
+        pass_packet <= 1'b0;
+      end
+
+      // We can pass the next packet through when we're at the start of a
+      // packet and we have the tuser value waiting in the holding register.
+      if (data_fifo_o_hdr && result_tuser_valid && !pass_packet) begin
+        reg_o_tuser <= result_tuser;
+        pass_packet <= 1'b1;
+      end
+    end
+  end
+
+  assign o_xport_tdata      = data_fifo_o_tdata;
+  assign o_xport_tuser      = reg_o_tuser;
+  assign o_xport_tlast      = data_fifo_o_tlast;
+  assign o_xport_tvalid     = data_fifo_o_tvalid & pass_packet;
+  assign data_fifo_o_tready = o_xport_tready & pass_packet;
+
+endmodule // chdr_xport_adapter_generic
\ No newline at end of file
diff --git a/fpga/usrp3/lib/rfnoc/xport/eth_interface.v b/fpga/usrp3/lib/rfnoc/xport/eth_interface.v
new file mode 100644
index 000000000..21e8b809d
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/xport/eth_interface.v
@@ -0,0 +1,252 @@
+//
+// Copyright 2019 Ettus Research, a National Instruments Brand
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Adapts from internal VITA to ethernet packets.  Also handles CPU and ethernet crossover interfaces.
+
+module eth_interface #(
+  parameter [15:0] PROTOVER    = {8'd1, 8'd0},
+  parameter        MTU         = 10,
+  parameter        NODE_INST   = 0,
+  parameter        RT_TBL_SIZE = 6,
+  parameter        REG_AWIDTH  = 14,
+  parameter        BASE        = 0
+) (
+  input         clk,
+  input         reset,
+  input [15:0]  device_id,
+
+  // Register port: Write port (domain: clk)
+  input        reg_wr_req,
+  input [REG_AWIDTH-1:0] reg_wr_addr,
+  input [31:0] reg_wr_data,
+
+  // Register port: Read port (domain: clk)
+  input         reg_rd_req,
+  input  [REG_AWIDTH-1:0] reg_rd_addr,
+  output reg       reg_rd_resp,
+  output reg [31:0] reg_rd_data,
+
+  // Status ports (domain: clk)
+  output [47:0] my_mac,
+  output [31:0] my_ip,
+  output [15:0] my_udp_port,
+
+  // Ethernet ports
+  output [63:0] eth_tx_tdata,
+  output [3:0]  eth_tx_tuser,
+  output        eth_tx_tlast,
+  output        eth_tx_tvalid,
+  input         eth_tx_tready,
+  input [63:0]  eth_rx_tdata,
+  input [3:0]   eth_rx_tuser,
+  input         eth_rx_tlast,
+  input         eth_rx_tvalid,
+  output        eth_rx_tready,
+
+  // Vita router interface
+  output [63:0] e2v_tdata,
+  output        e2v_tlast,
+  output        e2v_tvalid,
+  input         e2v_tready,
+  input [63:0]  v2e_tdata,
+  input         v2e_tlast,
+  input         v2e_tvalid,
+  output        v2e_tready,
+
+  // CPU
+  output [63:0] e2c_tdata,
+  output [3:0]  e2c_tuser,
+  output        e2c_tlast,
+  output        e2c_tvalid,
+  input         e2c_tready,
+  input [63:0]  c2e_tdata,
+  input [3:0]   c2e_tuser,
+  input         c2e_tlast,
+  input         c2e_tvalid,
+  output        c2e_tready
+);
+
+  localparam [47:0] DEFAULT_MAC_ADDR  = {8'h00, 8'h80, 8'h2f, 8'h16, 8'hc5, 8'h2f};
+  localparam [31:0] DEFAULT_IP_ADDR   = {8'd192, 8'd168, 8'd10, 8'd2};
+  localparam [31:0] DEFAULT_UDP_PORT  = 16'd49153;
+
+  //---------------------------------------------------------
+  // Registers
+  //---------------------------------------------------------
+
+  // Allocate one full page for MAC
+  localparam [REG_AWIDTH-1:0] REG_MAC_LSB        = BASE + 'h0000;
+  localparam [REG_AWIDTH-1:0] REG_MAC_MSB        = BASE + 'h0004;
+
+  // Source IP address
+  localparam [REG_AWIDTH-1:0] REG_IP             = BASE + 'h1000;
+  // Source UDP Port
+  localparam [REG_AWIDTH-1:0] REG_UDP            = BASE + 'h1004;
+
+  // Registers for Internal/Bridge Network Mode in CPU
+  localparam [REG_AWIDTH-1:0] REG_BRIDGE_MAC_LSB = BASE + 'h1010;
+  localparam [REG_AWIDTH-1:0] REG_BRIDGE_MAC_MSB = BASE + 'h1014;
+  localparam [REG_AWIDTH-1:0] REG_BRIDGE_IP      = BASE + 'h1018;
+  localparam [REG_AWIDTH-1:0] REG_BRIDGE_UDP     = BASE + 'h101c;
+  localparam [REG_AWIDTH-1:0] REG_BRIDGE_ENABLE  = BASE + 'h1020;
+
+  // MAC address for the dispatcher module.
+  // This value is used to determine if the packet is meant
+  // for this device should be consumed
+  // IP address for the dispatcher module.
+  // This value is used to determine if the packet is addressed
+  // to this device
+  // This module supports two destination ports
+  reg [47:0]      mac_reg;
+  reg [31:0]      ip_reg;
+  reg [15:0]      udp_port;
+  reg [47:0]      bridge_mac_reg;
+  reg [31:0]      bridge_ip_reg;
+  reg [15:0]      bridge_udp_port;
+  reg             bridge_en;
+
+  assign my_mac       = bridge_en ? bridge_mac_reg : mac_reg;
+  assign my_ip        = bridge_en ? bridge_ip_reg : ip_reg;
+  assign my_udp_port  = bridge_en ? bridge_udp_port : udp_port;
+
+  always @(posedge clk) begin
+    if (reset) begin
+      mac_reg         <= DEFAULT_MAC_ADDR;
+      ip_reg          <= DEFAULT_IP_ADDR;
+      udp_port        <= DEFAULT_UDP_PORT;
+      bridge_en       <= 1'b0;
+      bridge_mac_reg  <= DEFAULT_MAC_ADDR;
+      bridge_ip_reg   <= DEFAULT_IP_ADDR;
+      bridge_udp_port <= DEFAULT_UDP_PORT;
+    end
+    else begin
+      if (reg_wr_req)
+        case (reg_wr_addr)
+
+        REG_MAC_LSB:
+          mac_reg[31:0]         <= reg_wr_data;
+
+        REG_MAC_MSB:
+          mac_reg[47:32]        <= reg_wr_data[15:0];
+
+        REG_IP:
+          ip_reg                <= reg_wr_data;
+
+        REG_UDP:
+          udp_port              <= reg_wr_data[15:0];
+
+        REG_BRIDGE_MAC_LSB:
+          bridge_mac_reg[31:0]  <= reg_wr_data;
+
+        REG_BRIDGE_MAC_MSB:
+          bridge_mac_reg[47:32] <= reg_wr_data[15:0];
+
+        REG_BRIDGE_IP:
+          bridge_ip_reg         <= reg_wr_data;
+
+        REG_BRIDGE_UDP:
+          bridge_udp_port       <= reg_wr_data[15:0];
+
+        REG_BRIDGE_ENABLE:
+          bridge_en             <= reg_wr_data[0];
+        endcase
+    end
+  end
+
+  always @ (posedge clk) begin
+    // No reset handling required for readback
+    if (reg_rd_req) begin
+      // Assert read response one cycle after read request
+      reg_rd_resp <= 1'b1;
+      case (reg_rd_addr)
+        REG_MAC_LSB:
+          reg_rd_data <= mac_reg[31:0];
+
+        REG_MAC_MSB:
+          reg_rd_data <= {16'b0,mac_reg[47:32]};
+
+        REG_IP:
+          reg_rd_data <= ip_reg;
+
+        REG_UDP:
+          reg_rd_data <= {16'b0, udp_port};
+
+        REG_BRIDGE_MAC_LSB:
+          reg_rd_data <= bridge_mac_reg[31:0];
+
+        REG_BRIDGE_MAC_MSB:
+          reg_rd_data <= {16'b0,bridge_mac_reg[47:32]};
+
+        REG_BRIDGE_IP:
+          reg_rd_data <= bridge_ip_reg;
+
+        REG_BRIDGE_UDP:
+          reg_rd_data <= {16'b0, bridge_udp_port};
+
+        REG_BRIDGE_ENABLE:
+          reg_rd_data <= {31'b0,bridge_en};
+
+        default:
+          reg_rd_resp <= 1'b0;
+      endcase
+    end
+    // Deassert read response after one clock cycle
+    if (reg_rd_resp) begin
+      reg_rd_resp <= 1'b0;
+    end
+  end
+
+  // In AXI Stream, tkeep is the byte qualifier that indicates
+  // whether the content of the associated byte
+  // of TDATA is processed as part of the data stream.
+  // tuser as used in eth_switch is the numbier of valid bytes
+
+  eth_ipv4_chdr64_adapter #(
+    .PROTOVER        (PROTOVER),
+    .MTU             (MTU),
+    .CPU_FIFO_SIZE   (MTU),
+    .RT_TBL_SIZE     (RT_TBL_SIZE),
+    .NODE_INST       (NODE_INST),
+    .DROP_UNKNOWN_MAC(0),
+    .IS_CPU_ARM      (1)
+  ) eth_adapter_i (
+    .clk             (clk          ),
+    .rst             (reset        ),
+    .device_id       (device_id    ),
+    .s_mac_tdata     (eth_rx_tdata ),
+    .s_mac_tuser     (eth_rx_tuser ),
+    .s_mac_tlast     (eth_rx_tlast ),
+    .s_mac_tvalid    (eth_rx_tvalid),
+    .s_mac_tready    (eth_rx_tready),
+    .m_mac_tdata     (eth_tx_tdata ),
+    .m_mac_tuser     (eth_tx_tuser ),
+    .m_mac_tlast     (eth_tx_tlast ),
+    .m_mac_tvalid    (eth_tx_tvalid),
+    .m_mac_tready    (eth_tx_tready),
+    .s_chdr_tdata    (v2e_tdata    ),
+    .s_chdr_tlast    (v2e_tlast    ),
+    .s_chdr_tvalid   (v2e_tvalid   ),
+    .s_chdr_tready   (v2e_tready   ),
+    .m_chdr_tdata    (e2v_tdata    ),
+    .m_chdr_tlast    (e2v_tlast    ),
+    .m_chdr_tvalid   (e2v_tvalid   ),
+    .m_chdr_tready   (e2v_tready   ),
+    .s_cpu_tdata     (c2e_tdata    ),
+    .s_cpu_tuser     (c2e_tuser    ),
+    .s_cpu_tlast     (c2e_tlast    ),
+    .s_cpu_tvalid    (c2e_tvalid   ),
+    .s_cpu_tready    (c2e_tready   ),
+    .m_cpu_tdata     (e2c_tdata    ),
+    .m_cpu_tuser     (e2c_tuser    ),
+    .m_cpu_tlast     (e2c_tlast    ),
+    .m_cpu_tvalid    (e2c_tvalid   ),
+    .m_cpu_tready    (e2c_tready   ),
+    .my_eth_addr     (my_mac       ),
+    .my_ipv4_addr    (my_ip        ),
+    .my_udp_chdr_port(my_udp_port  )
+  );
+
+
+endmodule // eth_interface
diff --git a/fpga/usrp3/lib/rfnoc/xport/eth_internal.v b/fpga/usrp3/lib/rfnoc/xport/eth_internal.v
new file mode 100644
index 000000000..49cf838a5
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/xport/eth_internal.v
@@ -0,0 +1,433 @@
+///////////////////////////////////////////////////////////////////
+//
+// Copyright 2019 Ettus Research, a National Instruments brand
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: eth_internal
+// Description:
+//   Reduces clutter at top level.
+//   - FPGA-internal Ethernet port
+//   - ARP responder instead of other CPU connection
+//
+//////////////////////////////////////////////////////////////////////
+
+`default_nettype none
+module eth_internal #(
+  parameter        DWIDTH       = 32,
+  parameter        AWIDTH       = 14,
+  parameter [7:0]  PORTNUM      = 0,
+  parameter [15:0] RFNOC_PROTOVER  = {8'd1, 8'd0}
+)(
+  // Resets
+  input wire        bus_rst,
+
+  // Clocks
+  input wire        bus_clk,
+
+  //Axi-lite
+  input  wire                s_axi_aclk,
+  input  wire                s_axi_aresetn,
+  input  wire [AWIDTH-1:0]   s_axi_awaddr,
+  input  wire                s_axi_awvalid,
+  output wire                s_axi_awready,
+
+  input  wire [DWIDTH-1:0]   s_axi_wdata,
+  input  wire [DWIDTH/8-1:0] s_axi_wstrb,
+  input  wire                s_axi_wvalid,
+  output wire                s_axi_wready,
+
+  output wire [1:0]          s_axi_bresp,
+  output wire                s_axi_bvalid,
+  input  wire                s_axi_bready,
+
+  input  wire [AWIDTH-1:0]   s_axi_araddr,
+  input  wire                s_axi_arvalid,
+  output wire                s_axi_arready,
+
+  output wire [DWIDTH-1:0]   s_axi_rdata,
+  output wire [1:0]          s_axi_rresp,
+  output wire                s_axi_rvalid,
+  input  wire                s_axi_rready,
+
+  // Host-Ethernet DMA interface
+  output wire [63:0]  e2h_tdata,
+  output wire [7:0]   e2h_tkeep,
+  output wire         e2h_tlast,
+  output wire         e2h_tvalid,
+  input  wire         e2h_tready,
+
+  input  wire [63:0]  h2e_tdata,
+  input  wire [7:0]   h2e_tkeep,
+  input  wire         h2e_tlast,
+  input  wire         h2e_tvalid,
+  output wire         h2e_tready,
+
+  // RFNoC interface
+  output wire [63:0]  e2v_tdata,
+  output wire         e2v_tlast,
+  output wire         e2v_tvalid,
+  input  wire         e2v_tready,
+
+  input  wire [63:0]  v2e_tdata,
+  input  wire         v2e_tlast,
+  input  wire         v2e_tvalid,
+  output wire         v2e_tready,
+
+  // MISC
+  output wire  [31:0] port_info,
+  input  wire  [15:0] device_id,
+
+  output wire         link_up,
+  output reg          activity
+
+);
+
+  localparam REG_BASE_ETH_IO      = 14'h0;
+  localparam REG_BASE_ETH_SWITCH  = 14'h1000;
+
+  // AXI4-Lite to RegPort (PS to PL Register Access)
+  wire                reg_wr_req;
+  wire  [AWIDTH-1:0]  reg_wr_addr;
+  wire  [DWIDTH-1:0]  reg_wr_data;
+  wire                reg_rd_req;
+  wire  [AWIDTH-1:0]  reg_rd_addr;
+  wire                reg_rd_resp, reg_rd_resp_eth_if;
+  reg                 reg_rd_resp_io = 1'b0;
+  wire  [DWIDTH-1:0]  reg_rd_data, reg_rd_data_eth_if;
+  reg   [DWIDTH-1:0]  reg_rd_data_io = 'd0;
+
+  axil_regport_master #(
+    .DWIDTH         (DWIDTH),   // Width of the AXI4-Lite data bus (must be 32 or 64)
+    .AWIDTH         (AWIDTH),   // Width of the address bus
+    .WRBASE         (0),        // Write address base
+    .RDBASE         (0),        // Read address base
+    .TIMEOUT        (10)        // log2(timeout). Read will timeout after (2^TIMEOUT - 1) cycles
+  ) eth_dma_reg_mst_i (
+    // Clock and reset
+    .s_axi_aclk     (s_axi_aclk),
+    .s_axi_aresetn  (s_axi_aresetn),
+    // AXI4-Lite: Write address port (domain: s_axi_aclk)
+    .s_axi_awaddr   (s_axi_awaddr),
+    .s_axi_awvalid  (s_axi_awvalid),
+    .s_axi_awready  (s_axi_awready),
+    // AXI4-Lite: Write data port (domain: s_axi_aclk)
+    .s_axi_wdata    (s_axi_wdata),
+    .s_axi_wstrb    (s_axi_wstrb),
+    .s_axi_wvalid   (s_axi_wvalid),
+    .s_axi_wready   (s_axi_wready),
+    // AXI4-Lite: Write response port (domain: s_axi_aclk)
+    .s_axi_bresp    (s_axi_bresp),
+    .s_axi_bvalid   (s_axi_bvalid),
+    .s_axi_bready   (s_axi_bready),
+    // AXI4-Lite: Read address port (domain: s_axi_aclk)
+    .s_axi_araddr   (s_axi_araddr),
+    .s_axi_arvalid  (s_axi_arvalid),
+    .s_axi_arready  (s_axi_arready),
+    // AXI4-Lite: Read data port (domain: s_axi_aclk)
+    .s_axi_rdata    (s_axi_rdata),
+    .s_axi_rresp    (s_axi_rresp),
+    .s_axi_rvalid   (s_axi_rvalid),
+    .s_axi_rready   (s_axi_rready),
+    // Register port: Write port (domain: reg_clk)
+    .reg_clk        (bus_clk),
+    .reg_wr_req     (reg_wr_req),
+    .reg_wr_addr    (reg_wr_addr),
+    .reg_wr_data    (reg_wr_data),
+    // Register port: Read port (domain: reg_clk)
+    .reg_rd_req     (reg_rd_req),
+    .reg_rd_addr    (reg_rd_addr),
+    .reg_rd_resp    (reg_rd_resp),
+    .reg_rd_data    (reg_rd_data)
+  );
+
+  // Regport Mux for response
+  regport_resp_mux #(
+    .WIDTH      (DWIDTH),
+    .NUM_SLAVES (2)
+  ) reg_resp_mux_i (
+    .clk(bus_clk), .reset(bus_rst),
+    .sla_rd_resp({reg_rd_resp_eth_if, reg_rd_resp_io}),
+    .sla_rd_data({reg_rd_data_eth_if, reg_rd_data_io}),
+    .mst_rd_resp(reg_rd_resp), .mst_rd_data(reg_rd_data)
+  );
+
+  // ARP responder
+  wire [63:0] e2c_tdata;
+  wire [7:0]  e2c_tkeep;
+  wire        e2c_tlast;
+  wire        e2c_tvalid;
+  wire        e2c_tready;
+
+  wire [63:0] c2e_tdata;
+  wire [7:0]  c2e_tkeep;
+  wire        c2e_tlast;
+  wire        c2e_tvalid;
+  wire        c2e_tready;
+
+  wire [3:0] e2c_tuser;
+  wire [3:0] c2e_tuser;
+
+  // ARM Host-to-Ethernet
+  wire [3:0] e2h_tuser;
+  wire [3:0] h2e_tuser;
+
+  // Host Ethernet-to-CHDR
+  wire [63:0] h2e_chdr_tdata;
+  wire [3:0]  h2e_chdr_tuser;
+  wire        h2e_chdr_tlast;
+  wire        h2e_chdr_tvalid;
+  wire        h2e_chdr_tready;
+  wire [63:0] e2h_chdr_tdata;
+  wire [3:0]  e2h_chdr_tuser;
+  wire        e2h_chdr_tlast;
+  wire        e2h_chdr_tvalid;
+  wire        e2h_chdr_tready;
+
+
+  // In AXI Stream, tkeep is the byte qualifier that indicates
+  // whether the content of the associated byte
+  // of TDATA is processed as part of the data stream.
+  // tuser as used in eth_interface is the number of valid bytes
+
+  // Converting tuser to tkeep for ingress packets
+  assign e2c_tkeep = ~e2c_tlast ? 8'b1111_1111
+                   : (e2c_tuser == 4'd0) ? 8'b1111_1111
+                   : (e2c_tuser == 4'd1) ? 8'b0000_0001
+                   : (e2c_tuser == 4'd2) ? 8'b0000_0011
+                   : (e2c_tuser == 4'd3) ? 8'b0000_0111
+                   : (e2c_tuser == 4'd4) ? 8'b0000_1111
+                   : (e2c_tuser == 4'd5) ? 8'b0001_1111
+                   : (e2c_tuser == 4'd6) ? 8'b0011_1111
+                   : 8'b0111_1111;
+
+  // Converting tkeep to tuser for egress packets
+  assign c2e_tuser = ~c2e_tlast ? 4'd0
+                   : (c2e_tkeep == 8'b1111_1111) ? 4'd0
+                   : (c2e_tkeep == 8'b0111_1111) ? 4'd7
+                   : (c2e_tkeep == 8'b0011_1111) ? 4'd6
+                   : (c2e_tkeep == 8'b0001_1111) ? 4'd5
+                   : (c2e_tkeep == 8'b0000_1111) ? 4'd4
+                   : (c2e_tkeep == 8'b0000_0111) ? 4'd3
+                   : (c2e_tkeep == 8'b0000_0011) ? 4'd2
+                   : (c2e_tkeep == 8'b0000_0001) ? 4'd1
+                   : 4'd0;
+
+  // Converting tuser to tkeep for ingress packets
+  assign e2h_tkeep = ~e2h_tlast ? 8'b1111_1111
+                   : (e2h_tuser == 4'd0) ? 8'b1111_1111
+                   : (e2h_tuser == 4'd1) ? 8'b0000_0001
+                   : (e2h_tuser == 4'd2) ? 8'b0000_0011
+                   : (e2h_tuser == 4'd3) ? 8'b0000_0111
+                   : (e2h_tuser == 4'd4) ? 8'b0000_1111
+                   : (e2h_tuser == 4'd5) ? 8'b0001_1111
+                   : (e2h_tuser == 4'd6) ? 8'b0011_1111
+                   : 8'b0111_1111;
+
+  // Converting tkeep to tuser for egress packets
+  assign h2e_tuser = ~h2e_tlast ? 4'd0
+                   : (h2e_tkeep == 8'b1111_1111) ? 4'd0
+                   : (h2e_tkeep == 8'b0111_1111) ? 4'd7
+                   : (h2e_tkeep == 8'b0011_1111) ? 4'd6
+                   : (h2e_tkeep == 8'b0001_1111) ? 4'd5
+                   : (h2e_tkeep == 8'b0000_1111) ? 4'd4
+                   : (h2e_tkeep == 8'b0000_0111) ? 4'd3
+                   : (h2e_tkeep == 8'b0000_0011) ? 4'd2
+                   : (h2e_tkeep == 8'b0000_0001) ? 4'd1
+                   : 4'd0;
+
+  // FPGA-side addresses for the ARP responder
+  wire [47:0] my_mac;
+  wire [31:0] my_ip;
+  wire [15:0] my_udp_port;
+
+  arm_deframer arm_deframer_i (
+    .clk(bus_clk),
+    .reset(bus_rst),
+    .clear(1'b0),
+    .s_axis_tdata(h2e_tdata),
+    .s_axis_tuser(h2e_tuser),
+    .s_axis_tlast(h2e_tlast),
+    .s_axis_tvalid(h2e_tvalid),
+    .s_axis_tready(h2e_tready),
+    .m_axis_tdata(h2e_chdr_tdata),
+    .m_axis_tuser(h2e_chdr_tuser),
+    .m_axis_tlast(h2e_chdr_tlast),
+    .m_axis_tvalid(h2e_chdr_tvalid),
+    .m_axis_tready(h2e_chdr_tready)
+  );
+
+  axi64_to_xge64 arm_framer (
+    .clk(bus_clk),
+    .reset(bus_rst),
+    .clear(1'b0),
+    .s_axis_tdata(e2h_chdr_tdata),
+    .s_axis_tuser(e2h_chdr_tuser),
+    .s_axis_tlast(e2h_chdr_tlast),
+    .s_axis_tvalid(e2h_chdr_tvalid),
+    .s_axis_tready(e2h_chdr_tready),
+    .m_axis_tdata(e2h_tdata),
+    .m_axis_tuser(e2h_tuser),
+    .m_axis_tlast(e2h_tlast),
+    .m_axis_tvalid(e2h_tvalid),
+    .m_axis_tready(e2h_tready)
+  );
+
+  eth_interface #(
+     .PROTOVER(RFNOC_PROTOVER),
+     .MTU(10),
+     .NODE_INST(0),
+     .REG_AWIDTH (AWIDTH),
+     .BASE(REG_BASE_ETH_SWITCH)
+  ) eth_interface (
+    .clk           (bus_clk),
+    .reset         (bus_rst),
+    .device_id     (device_id),
+    .reg_wr_req    (reg_wr_req),
+    .reg_wr_addr   (reg_wr_addr),
+    .reg_wr_data   (reg_wr_data),
+    .reg_rd_req    (reg_rd_req),
+    .reg_rd_addr   (reg_rd_addr),
+    .reg_rd_resp   (reg_rd_resp_eth_if),
+    .reg_rd_data   (reg_rd_data_eth_if),
+    .my_mac        (my_mac),
+    .my_ip         (my_ip),
+    .my_udp_port   (my_udp_port),
+    .eth_tx_tdata  (e2h_chdr_tdata),
+    .eth_tx_tuser  (e2h_chdr_tuser),
+    .eth_tx_tlast  (e2h_chdr_tlast),
+    .eth_tx_tvalid (e2h_chdr_tvalid),
+    .eth_tx_tready (e2h_chdr_tready),
+    .eth_rx_tdata  (h2e_chdr_tdata),
+    .eth_rx_tuser  (h2e_chdr_tuser),
+    .eth_rx_tlast  (h2e_chdr_tlast),
+    .eth_rx_tvalid (h2e_chdr_tvalid),
+    .eth_rx_tready (h2e_chdr_tready),
+    .e2v_tdata     (e2v_tdata),
+    .e2v_tlast     (e2v_tlast),
+    .e2v_tvalid    (e2v_tvalid),
+    .e2v_tready    (e2v_tready),
+    .v2e_tdata     (v2e_tdata),
+    .v2e_tlast     (v2e_tlast),
+    .v2e_tvalid    (v2e_tvalid),
+    .v2e_tready    (v2e_tready),
+    .e2c_tdata     (e2c_tdata),
+    .e2c_tuser     (e2c_tuser),
+    .e2c_tlast     (e2c_tlast),
+    .e2c_tvalid    (e2c_tvalid),
+    .e2c_tready    (e2c_tready),
+    .c2e_tdata     (c2e_tdata),
+    .c2e_tuser     (c2e_tuser),
+    .c2e_tlast     (c2e_tlast),
+    .c2e_tvalid    (c2e_tvalid),
+    .c2e_tready    (c2e_tready)
+  );
+
+  arp_responder arp_responder_i (
+    .aclk          (bus_clk),
+    .aresetn       (~bus_rst),
+    .mac_addr      (my_mac),
+    .ip_addr       (my_ip),
+    .s_axis_tdata  (e2c_tdata),
+    .s_axis_tvalid (e2c_tvalid),
+    .s_axis_tready (e2c_tready),
+    .s_axis_tkeep  (e2c_tkeep),
+    .s_axis_tlast  (e2c_tlast),
+    .s_axis_tuser  (1'b0),
+    .m_axis_tdata  (c2e_tdata),
+    .m_axis_tvalid (c2e_tvalid),
+    .m_axis_tready (c2e_tready),
+    .m_axis_tkeep  (c2e_tkeep),
+    .m_axis_tlast  (c2e_tlast),
+    .m_axis_tuser  ()
+  );
+
+  //-----------------------------------------------------------------
+  // "I/O" Registers
+  //-----------------------------------------------------------------
+  localparam [7:0] COMPAT_NUM         = 8'd2;
+  localparam [7:0] MGT_PROTOCOL       = 8'd4; // 10 GbE Internal (8'd2 is 10 GbE External)
+
+  // Common registers
+  localparam REG_PORT_INFO            = REG_BASE_ETH_IO + 'h0;
+  localparam REG_MAC_CTRL_STATUS      = REG_BASE_ETH_IO + 'h4;
+  localparam REG_PHY_CTRL_STATUS      = REG_BASE_ETH_IO + 'h8;
+  localparam REG_MAC_LED_CTL          = REG_BASE_ETH_IO + 'hC;
+
+  // Protocol specific constants
+  localparam [1:0]  MAC_LED_CTL_RST_VAL = 2'h0;
+
+  localparam [31:0] MAC_CTRL_RST_VAL = {31'h0, 1'b1}; // tx_enable on reset
+  localparam [31:0] PHY_CTRL_RST_VAL = 32'h0;
+
+  // Writable registers
+  reg [31:0] mac_ctrl_reg = MAC_CTRL_RST_VAL;
+  reg [31:0] phy_ctrl_reg = PHY_CTRL_RST_VAL;
+  reg [1:0]  mac_led_ctl  = MAC_LED_CTL_RST_VAL;
+
+  always @(posedge bus_clk) begin
+    if (bus_rst) begin
+      mac_ctrl_reg <= MAC_CTRL_RST_VAL;
+      phy_ctrl_reg <= PHY_CTRL_RST_VAL;
+      mac_led_ctl  <= MAC_LED_CTL_RST_VAL;
+    end else if (reg_wr_req) begin
+      case(reg_wr_addr)
+        REG_MAC_CTRL_STATUS:
+          mac_ctrl_reg <= reg_wr_data;
+        REG_PHY_CTRL_STATUS:
+          phy_ctrl_reg <= reg_wr_data;
+        REG_MAC_LED_CTL:
+          mac_led_ctl <= reg_wr_data[1:0];
+      endcase
+    end
+  end
+
+  // Readable registers
+  wire [31:0] mac_status, phy_status;
+
+  assign port_info = {COMPAT_NUM, 6'h0, activity, link_up, MGT_PROTOCOL, PORTNUM};
+
+  always @(posedge bus_clk) begin
+    // No reset handling needed for readback
+    if (reg_rd_req) begin
+      reg_rd_resp_io <= 1'b1;
+      case(reg_rd_addr)
+        REG_PORT_INFO:
+          reg_rd_data_io <= port_info;
+        REG_MAC_CTRL_STATUS:
+          reg_rd_data_io <= mac_status;
+        REG_PHY_CTRL_STATUS:
+          reg_rd_data_io <= phy_status;
+        REG_MAC_LED_CTL:
+          reg_rd_data_io <= {30'd0, mac_led_ctl};
+        default:
+          reg_rd_resp_io <= 1'b0;
+      endcase
+    end if (reg_rd_resp_io) begin
+      reg_rd_resp_io <= 1'b0;
+    end
+  end
+
+  assign mac_status = 'd0;
+  assign phy_status[31:8] = 24'h0;
+  assign link_up = 1'b1;
+
+  wire identify_enable = mac_led_ctl[0];
+  wire identify_value  = mac_led_ctl[1];
+
+  //-----------------------------------------------------------------
+  // Activity detector
+  //-----------------------------------------------------------------
+  wire activity_int;
+
+  pulse_stretch act_pulse_str_i (
+    .clk(bus_clk),
+    .rst(bus_rst | ~link_up),
+    .pulse((h2e_tvalid & h2e_tready) | (e2h_tvalid & e2h_tready)),
+    .pulse_stretched(activity_int)
+  );
+
+  always @ (posedge bus_clk) activity <= identify_enable ? identify_value : activity_int;
+
+endmodule
+`default_nettype wire
diff --git a/fpga/usrp3/lib/rfnoc/xport/eth_ipv4_chdr64_adapter.v b/fpga/usrp3/lib/rfnoc/xport/eth_ipv4_chdr64_adapter.v
new file mode 100644
index 000000000..66c1b521e
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/xport/eth_ipv4_chdr64_adapter.v
@@ -0,0 +1,397 @@
+//
+// Copyright 2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: eth_ipv4_chdr64_adapter
+// Description: A generic transport adapter module that can be used in
+//   a veriety of transports. It does the following:
+//   - Exposes a configuration port for mgmt packets to configure the node
+//   - Implements a return-address map for packets with metadata other than
+//     the CHDR. Additional metadata can be passed as a tuser to this module
+//     which will store it in a map indexed by the SrcEPID in a management
+//     packet. For all returning packets, the metadata will be looked up in
+//     the map and attached as the outgoing tuser.
+//   - Implements a loopback path for node-info discovery
+//
+// Parameters:
+//   - PROTOVER: RFNoC protocol version {8'd<major>, 8'd<minor>}
+//   - MTU: Log2 of the MTU of the packet in 64-bit words
+//   - CPU_FIFO_SIZE: Log2 of the FIFO depth (in 64-bit words) for the CPU egress path
+//   - RT_TBL_SIZE: Log2 of the depth of the return-address routing table
+//   - NODE_INST: The node type to return for a node-info discovery
+//   - DROP_UNKNOWN_MAC: Drop packets not addressed to us?
+//
+// Signals:
+//   - device_id : The ID of the device that has instantiated this module
+//   - s_mac_*: The input Ethernet stream from the MAC (plus tuser for trailing bytes + err)
+//   - m_mac_*: The output Ethernet stream to the MAC (plus tuser for trailing bytes + err)
+//   - s_chdr_*: The input CHDR stream from the rfnoc infrastructure
+//   - m_chdr_*: The output CHDR stream to the rfnoc infrastructure
+//   - s_cpu_*: The input Ethernet stream from the CPU (plus tuser for trailing bytes + err)
+//   - m_cpu_*: The output Ethernet stream to the CPU (plus tuser for trailing bytes + err)
+//   - my_eth_addr: The Ethernet (MAC) address of this endpoint
+//   - my_ipv4_addr: The IPv4 address of this endpoint
+//   - my_udp_chdr_port: The UDP port allocated for CHDR traffic on this endpoint
+//
+
+`default_nettype none
+module eth_ipv4_chdr64_adapter #(
+  parameter [15:0] PROTOVER         = {8'd1, 8'd0},
+  parameter        MTU              = 10,
+  parameter        CPU_FIFO_SIZE    = MTU,
+  parameter        RT_TBL_SIZE      = 6,
+  parameter        NODE_INST        = 0,
+  parameter [0:0]  DROP_UNKNOWN_MAC = 1,
+  parameter [0:0]  IS_CPU_ARM       = 0
+)(
+  // Clocking and reset interface
+  input  wire        clk,
+  input  wire        rst,
+  // Device info
+  input  wire [15:0] device_id,
+  // AXI-Stream interface to/from MAC
+  input  wire [63:0] s_mac_tdata,
+  input  wire [3:0]  s_mac_tuser,
+  input  wire        s_mac_tlast,
+  input  wire        s_mac_tvalid,
+  output wire        s_mac_tready,
+  output wire [63:0] m_mac_tdata,
+  output wire [3:0]  m_mac_tuser,
+  output wire        m_mac_tlast,
+  output wire        m_mac_tvalid,
+  input  wire        m_mac_tready,
+  // AXI-Stream interface to/from CHDR infrastructure
+  input  wire [63:0] s_chdr_tdata,
+  input  wire        s_chdr_tlast,
+  input  wire        s_chdr_tvalid,
+  output wire        s_chdr_tready,
+  output wire [63:0] m_chdr_tdata,
+  output wire        m_chdr_tlast,
+  output wire        m_chdr_tvalid,
+  input  wire        m_chdr_tready,
+  // AXI-Stream interface to/from CPU
+  input  wire [63:0] s_cpu_tdata,
+  input  wire [3:0]  s_cpu_tuser,
+  input  wire        s_cpu_tlast,
+  input  wire        s_cpu_tvalid,
+  output wire        s_cpu_tready,
+  output wire [63:0] m_cpu_tdata,
+  output wire [3:0]  m_cpu_tuser,
+  output wire        m_cpu_tlast,
+  output wire        m_cpu_tvalid,
+  input  wire        m_cpu_tready,
+  // Device addresses
+  input  wire [47:0] my_eth_addr,
+  input  wire [31:0] my_ipv4_addr,
+  input  wire [15:0] my_udp_chdr_port
+);
+
+  `include "../core/rfnoc_chdr_utils.vh"
+  `include "../core/rfnoc_chdr_internal_utils.vh"
+  `include "rfnoc_xport_types.vh"
+
+  //-----------------------------------------------------------------------
+  // Byte-swapping function
+  // Ethernet fields we wrote out left-to-right, but AXI-Stream time-orders
+  // its data right-to-left.
+  //-----------------------------------------------------------------------
+  function [63:0] bswap64(
+    input  [63:0] din
+  );
+    begin
+      bswap64 = {din[0 +: 8], din[8 +: 8], din[16 +: 8], din[24 +: 8],
+                 din[32+: 8], din[40+: 8], din[48 +: 8], din[56 +: 8]};
+    end
+  endfunction
+
+  //---------------------------------------
+  // E2X and E2C DEMUX
+  //---------------------------------------
+  wire [63:0] e2x_chdr_tdata;
+  wire [95:0] e2x_chdr_tuser;
+  wire        e2x_chdr_tlast, e2x_chdr_tvalid, e2x_chdr_tready;
+  wire [63:0] e2c_chdr_tdata;
+  wire [3:0]  e2c_chdr_tuser;
+  wire        e2c_chdr_tlast, e2c_chdr_tvalid, e2c_chdr_tready;
+
+  // Ethernet sink. Inspects packet and dispatches
+  // to the correct port.
+  eth_ipv4_chdr64_dispatch #(
+    .DROP_UNKNOWN_MAC(DROP_UNKNOWN_MAC)
+  ) eth_dispatch_i (
+    .clk              (clk),
+    .rst              (rst),
+    .s_mac_tdata      (s_mac_tdata),
+    .s_mac_tuser      (s_mac_tuser),
+    .s_mac_tlast      (s_mac_tlast),
+    .s_mac_tvalid     (s_mac_tvalid),
+    .s_mac_tready     (s_mac_tready),
+    .m_chdr_tdata     (e2x_chdr_tdata),
+    .m_chdr_tuser     (e2x_chdr_tuser),
+    .m_chdr_tlast     (e2x_chdr_tlast),
+    .m_chdr_tvalid    (e2x_chdr_tvalid),
+    .m_chdr_tready    (e2x_chdr_tready),
+    .m_cpu_tdata      (e2c_chdr_tdata),
+    .m_cpu_tuser      (e2c_chdr_tuser),
+    .m_cpu_tlast      (e2c_chdr_tlast),
+    .m_cpu_tvalid     (e2c_chdr_tvalid),
+    .m_cpu_tready     (e2c_chdr_tready),
+    .my_eth_addr      (my_eth_addr),
+    .my_ipv4_addr     (my_ipv4_addr),
+    .my_udp_chdr_port (my_udp_chdr_port)
+  );
+
+  //---------------------------------------
+  // CHDR Transport Adapter
+  //---------------------------------------
+
+  wire [63:0] x2e_chdr_tdata;
+  wire [95:0] x2e_chdr_tuser;
+  wire        x2e_chdr_tlast, x2e_chdr_tvalid, x2e_chdr_tready;
+  wire [63:0] e2x_fifo_tdata;
+  wire        e2x_fifo_tlast, e2x_fifo_tvalid, e2x_fifo_tready;
+  wire [63:0] e2c_fifo_tdata;
+  wire [3:0]  e2c_fifo_tuser;
+  wire        e2c_fifo_tlast, e2c_fifo_tvalid, e2c_fifo_tready;
+
+  chdr_xport_adapter_generic #(
+    .PROTOVER(PROTOVER), .CHDR_W(64),
+    .USER_W(96), .TBL_SIZE(RT_TBL_SIZE),
+    .NODE_SUBTYPE(NODE_SUBTYPE_XPORT_IPV4_CHDR64), .NODE_INST(NODE_INST)
+  ) xport_adapter_gen_i (
+    .clk                (clk),
+    .rst                (rst),
+    .device_id          (device_id),
+    .s_axis_xport_tdata (e2x_chdr_tdata),
+    .s_axis_xport_tuser (e2x_chdr_tuser),
+    .s_axis_xport_tlast (e2x_chdr_tlast),
+    .s_axis_xport_tvalid(e2x_chdr_tvalid),
+    .s_axis_xport_tready(e2x_chdr_tready),
+    .m_axis_xport_tdata (x2e_chdr_tdata),
+    .m_axis_xport_tuser (x2e_chdr_tuser),
+    .m_axis_xport_tlast (x2e_chdr_tlast),
+    .m_axis_xport_tvalid(x2e_chdr_tvalid),
+    .m_axis_xport_tready(x2e_chdr_tready),
+    .s_axis_rfnoc_tdata (s_chdr_tdata),
+    .s_axis_rfnoc_tlast (s_chdr_tlast),
+    .s_axis_rfnoc_tvalid(s_chdr_tvalid),
+    .s_axis_rfnoc_tready(s_chdr_tready),
+    .m_axis_rfnoc_tdata (e2x_fifo_tdata),
+    .m_axis_rfnoc_tlast (e2x_fifo_tlast),
+    .m_axis_rfnoc_tvalid(e2x_fifo_tvalid),
+    .m_axis_rfnoc_tready(e2x_fifo_tready),
+    .ctrlport_req_wr    (/* unused */),
+    .ctrlport_req_rd    (/* unused */),
+    .ctrlport_req_addr  (/* unused */),
+    .ctrlport_req_data  (/* unused */),
+    .ctrlport_resp_ack  (/* unused */),
+    .ctrlport_resp_data (/* unused */)
+  );
+
+  generate
+    if (IS_CPU_ARM == 1'b1) begin
+      //---------------------------------------
+      // Ethernet framer for ARM
+      //---------------------------------------
+
+      // Strip the 6 octet ethernet padding we used internally
+      // before sending to ARM.
+      // Put SOF into bit[3] of tuser.
+      axi64_to_xge64 arm_framer (
+        .clk(clk),
+        .reset(rst),
+        .clear(1'b0),
+        .s_axis_tdata(e2c_chdr_tdata),
+        .s_axis_tuser(e2c_chdr_tuser),
+        .s_axis_tlast(e2c_chdr_tlast),
+        .s_axis_tvalid(e2c_chdr_tvalid),
+        .s_axis_tready(e2c_chdr_tready),
+        .m_axis_tdata(e2c_fifo_tdata),
+        .m_axis_tuser(e2c_fifo_tuser),
+        .m_axis_tlast(e2c_fifo_tlast),
+        .m_axis_tvalid(e2c_fifo_tvalid),
+        .m_axis_tready(e2c_fifo_tready)
+      );
+    end else begin
+      assign e2c_fifo_tdata  = e2c_chdr_tdata;
+      assign e2c_fifo_tuser  = e2c_chdr_tuser;
+      assign e2c_fifo_tlast  = e2c_chdr_tlast;
+      assign e2c_fifo_tvalid = e2c_chdr_tvalid;
+      assign e2c_chdr_tready = e2c_fifo_tready;
+    end
+  endgenerate
+
+  //---------------------------------------
+  // E2X and E2C Output Buffering
+  //---------------------------------------
+
+  // The CPU can be slow to respond (relative to packet wirespeed) so
+  // extra buffer for packets destined there so it doesn't back up.
+  axi_fifo #(
+    .WIDTH(64+4+1),.SIZE(CPU_FIFO_SIZE)
+  ) cpu_fifo_i (
+    .clk(clk), .reset(rst), .clear(1'b0),
+    .i_tdata({e2c_fifo_tlast, e2c_fifo_tuser, e2c_fifo_tdata}),
+    .i_tvalid(e2c_fifo_tvalid), .i_tready(e2c_fifo_tready),
+    .o_tdata({m_cpu_tlast, m_cpu_tuser, m_cpu_tdata}),
+    .o_tvalid(m_cpu_tvalid), .o_tready(m_cpu_tready),
+    .occupied(), .space()
+  );
+
+  // The transport should hook up to a crossbar downstream, which
+  // may backpressure this module because it is in the middle of
+  // transferring a packet. To ensure that upstream logic is not
+  // blocked, we instantiate one packet worth of buffering here.
+  axi_fifo #(
+    .WIDTH(64+1),.SIZE(MTU)
+  ) chdr_fifo_i (
+    .clk(clk), .reset(rst), .clear(1'b0),
+    .i_tdata({e2x_fifo_tlast, e2x_fifo_tdata}),
+    .i_tvalid(e2x_fifo_tvalid), .i_tready(e2x_fifo_tready),
+    .o_tdata({m_chdr_tlast, m_chdr_tdata}),
+    .o_tvalid(m_chdr_tvalid), .o_tready(m_chdr_tready),
+    .occupied(), .space()
+  );
+
+  //---------------------------------------
+  // Ethernet Framer for X2E
+  //---------------------------------------
+  wire [63:0] x2e_framed_tdata;
+  wire [3:0]  x2e_framed_tuser;
+  wire        x2e_framed_tlast, x2e_framed_tvalid, x2e_framed_tready;
+
+  localparam [2:0] ST_IDLE           = 3'd0;
+  localparam [2:0] ST_ETH_L0         = 3'd1;
+  localparam [2:0] ST_ETH_L1         = 3'd2;
+  localparam [2:0] ST_ETH_L2_IPV4_L0 = 3'd3;
+  localparam [2:0] ST_IPV4_L1        = 3'd4;
+  localparam [2:0] ST_IPV4_L2        = 3'd5;
+  localparam [2:0] ST_IPV4_UDP_HDR   = 3'd6;
+  localparam [2:0] ST_CHDR_PAYLOAD   = 3'd7;
+
+  reg [2:0]  frame_state = ST_IDLE;
+  reg [15:0] chdr_len = 16'd0;
+  reg [63:0] frame_tdata;
+
+  always @(posedge clk) begin
+    if(rst) begin
+      frame_state <= ST_IDLE;
+      chdr_len <= 16'd0;
+    end else begin
+      case(frame_state)
+        ST_IDLE: begin
+          if (x2e_chdr_tvalid) begin
+            frame_state <= ST_ETH_L0;
+            chdr_len <= chdr_get_length(x2e_chdr_tdata);
+          end
+        end
+        ST_CHDR_PAYLOAD: begin
+          if (x2e_chdr_tvalid & x2e_framed_tready)
+            if (x2e_chdr_tlast)
+              frame_state <= ST_IDLE;
+        end
+        default: begin
+          if(x2e_framed_tready)
+            frame_state <= frame_state + 3'd1;
+        end
+      endcase
+    end
+  end
+
+  assign x2e_chdr_tready = (frame_state == ST_CHDR_PAYLOAD) ? x2e_framed_tready : 1'b0;
+  assign x2e_framed_tvalid = (frame_state == ST_CHDR_PAYLOAD) ? x2e_chdr_tvalid : (frame_state == ST_IDLE) ? 1'b0 : 1'b1;
+  assign x2e_framed_tlast = (frame_state == ST_CHDR_PAYLOAD) ? x2e_chdr_tlast : 1'b0;
+  assign x2e_framed_tuser = ((frame_state == ST_CHDR_PAYLOAD) & x2e_chdr_tlast) ? {1'b0, chdr_len[2:0]} : 4'b0000;
+  assign x2e_framed_tdata = frame_tdata;
+
+  wire [47:0] pad = 48'h0;
+  wire [47:0] mac_dst = x2e_chdr_tuser[47:0];   // Extract from router lookup results
+  wire [15:0] eth_type = 16'h0800;  // IPv4
+  wire [15:0] misc_ip = { 4'd4 /* IPv4 */, 4'd5 /* IP HDR Len */, 8'h00 /* DSCP and ECN */};
+  wire [15:0] ip_len = (16'd28 + chdr_len);  // 20 for IP, 8 for UDP
+  wire [15:0] ident = 16'h0;
+  wire [15:0] flag_frag = { 3'b010 /* don't fragment */, 13'h0 };
+  wire [15:0] ttl_prot = { 8'h10 /* TTL */, 8'h11 /* UDP */ };
+  wire [15:0] iphdr_checksum;
+  wire [31:0] ip_dst = x2e_chdr_tuser[79:48];   // Extract from router lookup results
+  wire [15:0] udp_dst = x2e_chdr_tuser[95:80];  // Extract from router lookup results
+  wire [15:0] udp_len = (16'd8 + chdr_len);
+  wire [15:0] udp_checksum = 16'h0;
+
+  ip_hdr_checksum ip_hdr_checksum (
+    .clk(clk), .in({misc_ip, ip_len, ident, flag_frag, ttl_prot, 16'd0, my_ipv4_addr, ip_dst}),
+    .out(iphdr_checksum)
+  );
+
+  always @(*) begin
+    case(frame_state)
+      ST_ETH_L0         : frame_tdata <= bswap64({pad[47:0], mac_dst[47:32]});
+      ST_ETH_L1         : frame_tdata <= bswap64({mac_dst[31:0], my_eth_addr[47:16]});
+      ST_ETH_L2_IPV4_L0 : frame_tdata <= bswap64({my_eth_addr[15:0], eth_type[15:0], misc_ip[15:0], ip_len[15:0]});
+      ST_IPV4_L1        : frame_tdata <= bswap64({ident[15:0], flag_frag[15:0], ttl_prot[15:0], iphdr_checksum[15:0]});
+      ST_IPV4_L2        : frame_tdata <= bswap64({my_ipv4_addr[31:0], ip_dst[31:0]});
+      ST_IPV4_UDP_HDR   : frame_tdata <= bswap64({my_udp_chdr_port[15:0], udp_dst[15:0], udp_len[15:0], udp_checksum[15:0]});
+      default           : frame_tdata <= x2e_chdr_tdata;
+    endcase
+  end
+
+  wire [63:0] c2e_tdata;
+  wire [3:0]  c2e_tuser;
+  wire        c2e_tlast;
+  wire        c2e_tvalid;
+  wire        c2e_tready;
+
+  generate
+    if (IS_CPU_ARM == 1'b1) begin
+      //---------------------------------------
+      // Ethernet deframer for ARM
+      //---------------------------------------
+
+      // Add pad of 6 empty bytes to the ethernet packet going from the CPU to the
+      // SFP. This padding added before MAC addresses aligns the source and
+      // destination IP addresses, UDP headers etc.
+      // Note that the xge_mac_wrapper strips this padding to recreate the ethernet
+      // packet
+      arm_deframer inst_arm_deframer
+      (
+        .clk(clk),
+        .reset(rst),
+        .clear(1'b0),
+
+        .s_axis_tdata(s_cpu_tdata),
+        .s_axis_tuser(s_cpu_tuser),
+        .s_axis_tlast(s_cpu_tlast),
+        .s_axis_tvalid(s_cpu_tvalid),
+        .s_axis_tready(s_cpu_tready),
+
+        .m_axis_tdata(c2e_tdata),
+        .m_axis_tuser(c2e_tuser),
+        .m_axis_tlast(c2e_tlast),
+        .m_axis_tvalid(c2e_tvalid),
+        .m_axis_tready(c2e_tready)
+      );
+    end else begin
+      assign c2e_tdata    = s_cpu_tdata;
+      assign c2e_tuser    = s_cpu_tuser;
+      assign c2e_tlast    = s_cpu_tlast;
+      assign c2e_tvalid   = s_cpu_tvalid;
+      assign s_cpu_tready = c2e_tready;
+    end
+  endgenerate
+
+  //---------------------------------------
+  // X2E and C2E MUX
+  //---------------------------------------
+  axi_mux #(
+    .SIZE(2), .PRIO(0), .WIDTH(64+4), .PRE_FIFO_SIZE(0), .POST_FIFO_SIZE(1)
+  ) eth_mux_i (
+    .clk(clk), .reset(rst), .clear(1'b0),
+    .i_tdata({c2e_tuser, c2e_tdata, x2e_framed_tuser, x2e_framed_tdata}), .i_tlast({c2e_tlast, x2e_framed_tlast}),
+    .i_tvalid({c2e_tvalid, x2e_framed_tvalid}), .i_tready({c2e_tready, x2e_framed_tready}),
+    .o_tdata({m_mac_tuser, m_mac_tdata}), .o_tlast(m_mac_tlast),
+    .o_tvalid(m_mac_tvalid), .o_tready(m_mac_tready)
+  );
+
+endmodule // eth_ipv4_chdr64_adapter
+`default_nettype wire
diff --git a/fpga/usrp3/lib/rfnoc/xport/eth_ipv4_chdr64_dispatch.v b/fpga/usrp3/lib/rfnoc/xport/eth_ipv4_chdr64_dispatch.v
new file mode 100644
index 000000000..b954a8100
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/xport/eth_ipv4_chdr64_dispatch.v
@@ -0,0 +1,472 @@
+//
+// Copyright 2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: eth_ipv4_chdr64_dispatch
+// Description:
+//  This module serves as an Ethernet endpoint for CHDR traffic.
+//  Ethernet frames arrive on the s_mac port where they are
+//  inspected and classified as CHDR or !CHDR. A frame contains
+//  CHDR payload if it is addressed to us (Eth and IP), is a UDP
+//  packet and the destination port is one of the CHDR ports.
+//  The UDP payload for CHDR frame is sent out of the m_chdr port
+//  in addition to source information for Eth, IP and UDP. All
+//  other traffic address to us (Eth) is sent to the m_cpu port.
+//  Traffic not addressed (Eth) to us is dropped.
+//
+// Parameters:
+//  - DROP_UNKNOWN_MAC: Drop packets not addressed to us?
+//
+// Signals:
+//   - s_mac_*: The input Ethernet stream from the MAC (plus tuser for trailing bytes + err)
+//              The tuser bits are the values defined in xge_mac_wrapper. Most
+//              relevant is tuser[3], which signals a bad packet that must be
+//              dropped.
+//   - m_chdr_*: The output CHDR stream to the rfnoc infrastructure
+//   - m_cpu_*: The output Ethernet stream to the CPU (plus tuser for trailing bytes + err)
+//   - my_eth_addr: The Ethernet (MAC) address of this endpoint
+//   - my_ipv4_addr: The IPv4 address of this endpoint
+//   - my_udp_chdr_port: The UDP port allocated for CHDR traffic on this endpoint
+//
+
+`default_nettype none
+module eth_ipv4_chdr64_dispatch #(
+  parameter [0:0] DROP_UNKNOWN_MAC = 1
+)(
+  // Clocking and reset interface
+  input  wire        clk,
+  input  wire        rst,
+  // Input 68bit AXI-Stream interface (from MAC)
+  input  wire [63:0] s_mac_tdata,
+  input  wire [3:0]  s_mac_tuser,
+  input  wire        s_mac_tlast,
+  input  wire        s_mac_tvalid,
+  output wire        s_mac_tready,
+  // Output AXI-Stream interface to CHDR infrastructure
+  output wire [63:0] m_chdr_tdata,
+  output wire [95:0] m_chdr_tuser,
+  output wire        m_chdr_tlast,
+  output wire        m_chdr_tvalid,
+  input  wire        m_chdr_tready,
+  // Output AXI-Stream interface to CPU
+  output wire [63:0] m_cpu_tdata,
+  output wire [3:0]  m_cpu_tuser,
+  output wire        m_cpu_tlast,
+  output wire        m_cpu_tvalid,
+  input  wire        m_cpu_tready,
+  // Device addresses
+  input  wire [47:0] my_eth_addr,
+  input  wire [31:0] my_ipv4_addr,
+  input  wire [15:0] my_udp_chdr_port
+);
+
+  //---------------------------------------
+  // Ethernet/IP/UDP Magic Numbers
+  //---------------------------------------
+
+  localparam [47:0] ETH_ADDR_BCAST = {48{1'b1}};
+  localparam [15:0] ETH_TYPE_IPV4 = 16'h0800;
+  localparam [7:0]  IPV4_PROTO_UDP = 8'h11;
+
+  //---------------------------------------
+  // Byte-swapping function
+  //---------------------------------------
+  function [15:0] bswap16(
+    input  [15:0] din
+  );
+    begin
+      bswap16 = {din[0 +: 8], din[8 +: 8]};
+    end
+  endfunction
+
+  function [31:0] bswap32(
+    input  [31:0] din
+  );
+    begin
+      bswap32 = {din[0 +: 8], din[8 +: 8],
+                 din[16+: 8], din[24+: 8]};
+    end
+  endfunction
+
+  //---------------------------------------
+  // Input pipeline stage
+  //---------------------------------------
+
+  wire [63:0] in_tdata;
+  wire [3:0]  in_tuser;
+  wire        in_tlast, in_tvalid;
+  reg         in_tready;
+
+  wire [63:0] cpu_tdata;
+  wire [3:0]  cpu_tuser;
+  reg         cpu_tlast, cpu_terror, cpu_tvalid;
+  wire        cpu_tready;
+
+  wire [63:0] chdr_tdata;
+  wire [95:0] chdr_tuser;
+  wire        chdr_tlast, chdr_tvalid, chdr_tready;
+  wire        chdr_terror;
+
+  axi_fifo #(
+    .WIDTH(64+4+1),.SIZE(1)
+  ) in_reg_i (
+    .clk(clk), .reset(rst), .clear(1'b0),
+    .i_tdata({s_mac_tlast, s_mac_tuser, s_mac_tdata}),
+    .i_tvalid(s_mac_tvalid), .i_tready(s_mac_tready),
+    .o_tdata({in_tlast, in_tuser, in_tdata}),
+    .o_tvalid(in_tvalid), .o_tready(in_tready),
+    .space(), .occupied()
+  );
+
+  //---------------------------------------
+  // Classification state machine
+  //---------------------------------------
+
+  localparam [3:0] ST_IDLE_ETH_L0    = 4'd0;
+  localparam [3:0] ST_ETH_L1         = 4'd1;
+  localparam [3:0] ST_ETH_L2_IPV4_L0 = 4'd2;
+  localparam [3:0] ST_IPV4_L1        = 4'd3;
+  localparam [3:0] ST_IPV4_L2        = 4'd4;
+  localparam [3:0] ST_IPV4_UDP_HDR   = 4'd5;
+  localparam [3:0] ST_FWD_CHDR       = 4'd6;
+  localparam [3:0] ST_FWD_CPU        = 4'd7;
+  localparam [3:0] ST_DROP_PKT       = 4'd8;
+
+  // State info
+  reg [3:0] state = ST_IDLE_ETH_L0;
+  reg       discard_cpu_pkt = 1'b0;
+
+  // Cached fields
+  reg [47:0] eth_dst_addr_cached, eth_src_addr_cached;
+  reg [31:0] ipv4_src_addr_cached;
+  reg [15:0] udp_src_port_cached;
+
+  always @(posedge clk) begin
+    if (rst) begin
+      state <= ST_IDLE_ETH_L0;
+      discard_cpu_pkt <= 1'b0;
+    end else if (in_tvalid && in_tready) begin
+      case (state)
+        // Idle or First line of Eth frame
+        // ----------------------------------
+        // | DstMAC_HI (16) | Preamble (48) |
+        // ----------------------------------
+        ST_IDLE_ETH_L0: begin
+          discard_cpu_pkt <= 1'b0;
+          if (!in_tlast) begin
+            // Just cache addresses. No decisions to be made.
+            eth_dst_addr_cached[47:32] <= bswap16(in_tdata[48 +: 16]);
+            if (in_tuser[3]) begin
+              state <= ST_DROP_PKT;
+              discard_cpu_pkt <= 1'b1;
+            end else begin
+              state <= ST_ETH_L1;
+            end
+          end else begin
+            // Short packet: Violates min eth size of 64 bytes
+            state <= ST_IDLE_ETH_L0;
+          end
+        end
+
+        // Second line of Eth frame
+        // -----------------------------------
+        // | SrcMAC_HI (32) | DstMAC_LO (32) |
+        // -----------------------------------
+        ST_ETH_L1: begin
+          if (!in_tlast) begin
+            // Just cache addresses. No decisions to be made.
+            eth_dst_addr_cached[31:0] <= bswap32(in_tdata[0 +: 32]);
+            eth_src_addr_cached[47:16] <= bswap32(in_tdata[32 +: 32]);
+            if (in_tuser[3]) begin
+              state <= ST_DROP_PKT;
+              discard_cpu_pkt <= 1'b1;
+            end else begin
+              state <= ST_ETH_L2_IPV4_L0;
+            end
+          end else begin
+            // Short packet: Violates min eth size of 64 bytes
+            state <= ST_IDLE_ETH_L0;
+          end
+        end
+
+        // End Eth frame and start of IP
+        // --------------------------------------------------
+        // | IPv4_Line0 (32)| EthType (16) | SrcMAC_LO (16) |
+        // --------------------------------------------------
+        ST_ETH_L2_IPV4_L0: begin
+          if (!in_tlast) begin
+            eth_src_addr_cached[15:0] <= bswap16(in_tdata[0 +: 16]);
+            if (in_tuser[3]) begin
+              state <= ST_DROP_PKT;
+              discard_cpu_pkt <= 1'b1;
+            end else if (eth_dst_addr_cached == ETH_ADDR_BCAST) begin
+              // If Eth destination is bcast then fwd to CPU
+              state <= ST_FWD_CPU;
+            end else if (eth_dst_addr_cached != my_eth_addr && DROP_UNKNOWN_MAC) begin
+              // If Eth destination is not us then drop the packet
+              state <= ST_DROP_PKT;
+              discard_cpu_pkt <= 1'b1;
+            end else if (bswap16(in_tdata[16 +: 16]) != ETH_TYPE_IPV4) begin
+              // If this is not an IPv4 frame then fwd to CPU
+              state <= ST_FWD_CPU;
+            end else begin
+              // Otherwise continue classification
+              // We know this is an IPv4 frame
+              state <= ST_IPV4_L1;
+            end
+          end else begin
+            // Short packet: Violates min eth size of 64 bytes
+            state <= ST_IDLE_ETH_L0;
+          end
+        end
+
+        // Continue IPv4 header
+        // -------------------------------------
+        // | IPv4_Line2 (32) | IPv4_Line1 (32) |
+        // -------------------------------------
+        ST_IPV4_L1: begin
+          if (!in_tlast) begin
+            if (in_tuser[3]) begin
+              state <= ST_DROP_PKT;
+              discard_cpu_pkt <= 1'b1;
+            end else if (in_tdata[40 +: 8] != IPV4_PROTO_UDP) begin
+              // If this is not a UDP frame then fwd to CPU
+              state <= ST_FWD_CPU;
+            end else begin
+              // Otherwise continue classification
+              // We know this is a UDP frame
+              state <= ST_IPV4_L2;
+            end
+          end else begin
+            // Short packet: Violates min eth size of 64 bytes
+            state <= ST_IDLE_ETH_L0;
+          end
+        end
+
+        // Continue IPv4 header
+        // -----------------------------------
+        // | IPDstAddr (32) | IPSrcAddr (32) |
+        // -----------------------------------
+        ST_IPV4_L2: begin
+          if (!in_tlast) begin
+            ipv4_src_addr_cached <= bswap32(in_tdata[0 +: 32]);
+            if (in_tuser[3]) begin
+              state <= ST_DROP_PKT;
+              discard_cpu_pkt <= 1'b1;
+            end else if (bswap32(in_tdata[32 +: 32]) != my_ipv4_addr) begin
+              // If IPv4 destination is not us then fwd to CPU
+              state <= ST_FWD_CPU;
+            end else begin
+              // Otherwise continue classification
+              // We know this is a UDP frame for us
+              state <= ST_IPV4_UDP_HDR;
+            end
+          end else begin
+            // Short packet: Violates min eth size of 64 bytes
+            state <= ST_IDLE_ETH_L0;
+          end
+        end
+
+        // UDP header
+        // -----------------------------------------------------------
+        // | Chksum (16) | Length (16) | DstPort (16) | SrcPort (16) |
+        // -----------------------------------------------------------
+        ST_IPV4_UDP_HDR: begin
+          if (!in_tlast) begin
+            udp_src_port_cached <= bswap16(in_tdata[0 +: 16]);
+            if (in_tuser[3]) begin
+              state <= ST_DROP_PKT;
+              discard_cpu_pkt <= 1'b1;
+            end else if (bswap16(in_tdata[16 +: 16]) == my_udp_chdr_port) begin
+              // The UDP port matches CHDR port
+              state <= ST_FWD_CHDR;
+              discard_cpu_pkt <= 1'b1;
+            end else begin
+              // Not the CHDR port. Forward to CPU
+              state <= ST_FWD_CPU;
+            end
+          end else begin
+            // Short packet: Violates min eth size of 64 bytes
+            state <= ST_IDLE_ETH_L0;
+          end
+        end
+
+        // CHDR Payload
+        ST_FWD_CHDR: begin
+          discard_cpu_pkt <= 1'b0;
+          if (in_tlast)
+            state <= ST_IDLE_ETH_L0;
+        end
+
+        // NotCHDR Payload: Send to CPU
+        ST_FWD_CPU: begin
+          if (in_tlast)
+            state <= ST_IDLE_ETH_L0;
+        end
+
+        // Unwanted Payload: Drop
+        ST_DROP_PKT: begin
+          discard_cpu_pkt <= 1'b0;
+          if (in_tlast)
+            state <= ST_IDLE_ETH_L0;
+        end
+
+        // We should never get here
+        default: begin
+          state <= ST_IDLE_ETH_L0;
+        end
+      endcase
+    end
+  end
+
+  always @(*) begin
+    case (state)
+      ST_IDLE_ETH_L0: begin
+        in_tready   = cpu_tready;
+        cpu_tvalid  = in_tvalid;
+        cpu_tlast   = in_tlast;
+        cpu_terror  = in_tlast;   // Illegal short packet: Drop it
+      end
+      ST_ETH_L1: begin 
+        in_tready   = cpu_tready;
+        cpu_tvalid  = in_tvalid;
+        cpu_tlast   = in_tlast;
+        cpu_terror  = in_tlast;   // Illegal short packet: Drop it
+      end
+      ST_ETH_L2_IPV4_L0: begin 
+        in_tready   = cpu_tready;
+        cpu_tvalid  = in_tvalid;
+        cpu_tlast   = in_tlast;
+        cpu_terror  = in_tlast;   // Illegal short packet: Drop it
+      end
+      ST_IPV4_L1: begin 
+        in_tready   = cpu_tready;
+        cpu_tvalid  = in_tvalid;
+        cpu_tlast   = in_tlast;
+        cpu_terror  = in_tlast;   // Illegal short packet: Drop it
+      end
+      ST_IPV4_L2: begin 
+        in_tready   = cpu_tready;
+        cpu_tvalid  = in_tvalid;
+        cpu_tlast   = in_tlast;
+        cpu_terror  = in_tlast;   // Illegal short packet: Drop it
+      end
+      ST_IPV4_UDP_HDR: begin 
+        in_tready   = cpu_tready;
+        cpu_tvalid  = in_tvalid;
+        cpu_tlast   = in_tlast;
+        cpu_terror  = in_tlast;   // Illegal short packet: Drop it
+      end
+      ST_FWD_CHDR: begin 
+        in_tready   = chdr_tready & (discard_cpu_pkt ? cpu_tready : 1'b1);
+        cpu_tvalid  = discard_cpu_pkt;
+        cpu_tlast   = discard_cpu_pkt;
+        cpu_terror  = discard_cpu_pkt;
+      end
+      ST_FWD_CPU: begin 
+        in_tready   = cpu_tready;
+        cpu_tvalid  = in_tvalid;
+        cpu_tlast   = in_tlast;
+        cpu_terror  = 1'b0;
+      end
+      ST_DROP_PKT: begin 
+        in_tready   = discard_cpu_pkt ? cpu_tready : 1'b1;
+        cpu_tvalid  = discard_cpu_pkt;
+        cpu_tlast   = discard_cpu_pkt;
+        cpu_terror  = discard_cpu_pkt;
+      end
+      default: begin
+        in_tready   = 1'b0;
+        cpu_tvalid  = 1'b0;
+        cpu_tlast   = 1'b0;
+        cpu_terror  = 1'b0;
+      end
+    endcase
+  end
+
+  assign cpu_tdata  = in_tdata;
+  assign cpu_tuser  = in_tuser;
+
+  assign chdr_tdata  = in_tdata;
+  assign chdr_tuser  = {udp_src_port_cached, ipv4_src_addr_cached, eth_src_addr_cached};
+  assign chdr_tlast  = in_tlast;
+  assign chdr_tvalid = in_tvalid && (state == ST_FWD_CHDR);
+  assign chdr_terror = in_tuser[3];
+
+  //---------------------------------------
+  // Output processing
+  //---------------------------------------
+
+  wire [63:0] o_cpu_tdata;
+  wire [3:0]  o_cpu_tuser;
+  wire        o_cpu_terror, o_cpu_tlast, o_cpu_tvalid, o_cpu_tready;
+
+  axi_fifo #(
+    .WIDTH(64+4+1+1),.SIZE(1)
+  ) out_reg_cpu_i (
+    .clk(clk), .reset(rst), .clear(1'b0),
+    .i_tdata({cpu_tlast, cpu_terror, cpu_tuser, cpu_tdata}),
+    .i_tvalid(cpu_tvalid), .i_tready(cpu_tready),
+    .o_tdata({o_cpu_tlast, o_cpu_terror, o_cpu_tuser, o_cpu_tdata}),
+    .o_tvalid(o_cpu_tvalid), .o_tready(o_cpu_tready),
+    .space(), .occupied()
+  );
+
+  // We cannot make a CHDR/noCHDR routing decision until we are in the middle
+  // of a packet so we use a packet gate for the CPU path because we can rewind 
+  // the write pointer and drop the packet in case it's destined for the CHDR
+  // path.
+  // NOTE: The SIZE of this FIFO must be 11 to accomodate a 9000 byte jumbo frame
+  //       regardless of the CHDR MTU
+  axi_packet_gate #( .WIDTH(64+4), .SIZE(11), .USE_AS_BUFF(0) ) cpu_out_gate_i (
+    .clk(clk), .reset(rst), .clear(1'b0),
+    .i_tdata({o_cpu_tuser, o_cpu_tdata}), .i_tlast(o_cpu_tlast), .i_terror(o_cpu_terror | o_cpu_tuser[3]),
+    .i_tvalid(o_cpu_tvalid), .i_tready(o_cpu_tready),
+    .o_tdata({m_cpu_tuser, m_cpu_tdata}), .o_tlast(m_cpu_tlast),
+    .o_tvalid(m_cpu_tvalid), .o_tready(m_cpu_tready)
+  );
+
+  wire [63:0] o_chdr_tdata;
+  wire [95:0] o_chdr_tuser;
+  wire        o_chdr_tlast, o_chdr_tvalid, o_chdr_tready;
+  wire        o_chdr_data_tvalid, o_chdr_user_tvalid;
+  wire        o_chdr_data_tready, o_chdr_user_tready;
+
+  axi_fifo #(
+    .WIDTH(96),.SIZE(8)
+  ) chdr_user_fifo_i (
+    .clk(clk), .reset(rst), .clear(1'b0),
+    .i_tdata(chdr_tuser),
+    .i_tvalid(chdr_tvalid & chdr_tready & chdr_tlast & ~chdr_terror), .i_tready(/* Always ready */),
+    .o_tdata(o_chdr_tuser),
+    .o_tvalid(o_chdr_user_tvalid), .o_tready(o_chdr_user_tready),
+    .space(), .occupied()
+  );
+
+  axi_packet_gate #(
+    .WIDTH(64), .SIZE(11), .USE_AS_BUFF(1), .MIN_PKT_SIZE(1)
+  ) chdr_out_gate_i (
+    .clk(clk), .reset(rst), .clear(1'b0),
+    .i_tdata(chdr_tdata), .i_tlast(chdr_tlast), .i_terror(chdr_terror),
+    .i_tvalid(chdr_tvalid), .i_tready(chdr_tready),
+    .o_tdata(o_chdr_tdata), .o_tlast(o_chdr_tlast),
+    .o_tvalid(o_chdr_data_tvalid), .o_tready(o_chdr_data_tready)
+  );
+
+  assign o_chdr_tvalid = o_chdr_data_tvalid & o_chdr_user_tvalid;
+  assign o_chdr_user_tready = o_chdr_tready & o_chdr_data_tvalid & o_chdr_tlast;
+  assign o_chdr_data_tready = o_chdr_tready & o_chdr_user_tvalid;
+
+  chdr_trim_payload #(
+    .CHDR_W(64), .USER_W(96)
+  ) chdr_trim_i (
+    .clk(clk), .rst(rst),
+    .s_axis_tdata(o_chdr_tdata), .s_axis_tuser(o_chdr_tuser),
+    .s_axis_tlast(o_chdr_tlast), .s_axis_tvalid(o_chdr_tvalid), .s_axis_tready(o_chdr_tready),
+    .m_axis_tdata(m_chdr_tdata), .m_axis_tuser(m_chdr_tuser),
+    .m_axis_tlast(m_chdr_tlast), .m_axis_tvalid(m_chdr_tvalid), .m_axis_tready(m_chdr_tready)
+  );
+
+endmodule // eth_ipv4_chdr64_dispatch
+`default_nettype wire
diff --git a/fpga/usrp3/lib/rfnoc/xport/liberio_chdr64_adapter.v b/fpga/usrp3/lib/rfnoc/xport/liberio_chdr64_adapter.v
new file mode 100644
index 000000000..2800c46bb
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/xport/liberio_chdr64_adapter.v
@@ -0,0 +1,120 @@
+//
+// Copyright 2019 Ettus Research, A National Instruments brand
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: liberio_chdr64_adapter
+// Description: The transport adapter for a liberio transport with CHDR_W of
+//   64. A tuser field is used to identify the DMA engine for return routes.
+//   The stream for a given SrcEPID with ID s_dma_tuser will return packets to
+//   that EPID with same ID on m_dma_tuser (after an Advertise management
+//   operation).
+//
+// Parameters:
+//   - PROTOVER: RFNoC protocol version {8'd<major>, 8'd<minor>}
+//   - RT_TBL_SIZE: Log2 of the depth of the return-address routing table
+//   - NODE_INST: The node type to return for a node-info discovery
+//   - DMA_ID_WIDTH: The width of the tuser signal that identifies the DMA engine)
+//
+// Signals:
+//   - device_id : The ID of the device that has instantiated this module
+//   - s_dma_*: The input DMA stream from the CPU (plus tuser for source DMA engine ID)
+//   - m_dma_*: The output DMA stream to the CPU (plus tuser for dest DMA engine ID)
+//   - s_chdr_*: The input CHDR stream from the rfnoc infrastructure
+//   - m_chdr_*: The output CHDR stream to the rfnoc infrastructure
+//
+
+module liberio_chdr64_adapter #(
+  parameter [15:0] PROTOVER         = {8'd1, 8'd0},
+  parameter        RT_TBL_SIZE      = 6,
+  parameter        NODE_INST        = 0,
+  parameter        DMA_ID_WIDTH     = 8
+)(
+  // Clocking and reset interface
+  input  wire        clk,
+  input  wire        rst,
+  // Device info
+  input  wire [15:0] device_id,
+  // AXI-Stream interface to/from DMA engines
+  input  wire [63:0]              s_dma_tdata,
+  input  wire [DMA_ID_WIDTH-1:0]  s_dma_tuser,
+  input  wire                     s_dma_tlast,
+  input  wire                     s_dma_tvalid,
+  output wire                     s_dma_tready,
+  output wire [63:0]              m_dma_tdata,
+  output wire [DMA_ID_WIDTH-1:0]  m_dma_tuser,
+  output wire                     m_dma_tlast,
+  output wire                     m_dma_tvalid,
+  input  wire                     m_dma_tready,
+  // AXI-Stream interface to/from CHDR infrastructure
+  input  wire [63:0] s_chdr_tdata,
+  input  wire        s_chdr_tlast,
+  input  wire        s_chdr_tvalid,
+  output wire        s_chdr_tready,
+  output wire [63:0] m_chdr_tdata,
+  output wire        m_chdr_tlast,
+  output wire        m_chdr_tvalid,
+  input  wire        m_chdr_tready
+);
+
+  `include "../core/rfnoc_chdr_utils.vh"
+  `include "../core/rfnoc_chdr_internal_utils.vh"
+  `include "rfnoc_xport_types.vh"
+
+  //---------------------------------------
+  // CHDR Transport Adapter
+  //---------------------------------------
+  wire [DMA_ID_WIDTH-1:0] m_axis_xport_tuser;
+
+  chdr_xport_adapter_generic #(
+    .PROTOVER(PROTOVER), .CHDR_W(64),
+    .USER_W(DMA_ID_WIDTH), .TBL_SIZE(RT_TBL_SIZE),
+    .NODE_SUBTYPE(NODE_SUBTYPE_XPORT_LIBERIO_CHDR64), .NODE_INST(NODE_INST)
+  ) xport_adapter_gen_i (
+    .clk                (clk),
+    .rst                (rst),
+    .device_id          (device_id),
+    .s_axis_xport_tdata (s_dma_tdata),
+    .s_axis_xport_tuser (s_dma_tuser),
+    .s_axis_xport_tlast (s_dma_tlast),
+    .s_axis_xport_tvalid(s_dma_tvalid),
+    .s_axis_xport_tready(s_dma_tready),
+    .m_axis_xport_tdata (m_dma_tdata),
+    .m_axis_xport_tuser (m_axis_xport_tuser),
+    .m_axis_xport_tlast (m_dma_tlast),
+    .m_axis_xport_tvalid(m_dma_tvalid),
+    .m_axis_xport_tready(m_dma_tready),
+    .s_axis_rfnoc_tdata (s_chdr_tdata),
+    .s_axis_rfnoc_tlast (s_chdr_tlast),
+    .s_axis_rfnoc_tvalid(s_chdr_tvalid),
+    .s_axis_rfnoc_tready(s_chdr_tready),
+    .m_axis_rfnoc_tdata (m_chdr_tdata),
+    .m_axis_rfnoc_tlast (m_chdr_tlast),
+    .m_axis_rfnoc_tvalid(m_chdr_tvalid),
+    .m_axis_rfnoc_tready(m_chdr_tready),
+    .ctrlport_req_wr    (/* unused */),
+    .ctrlport_req_rd    (/* unused */),
+    .ctrlport_req_addr  (/* unused */),
+    .ctrlport_req_data  (/* unused */),
+    .ctrlport_resp_ack  (/* unused */ 1'b0),
+    .ctrlport_resp_data (/* unused */ 32'd0)
+  );
+
+  // Ensure tdest does not change for entire packet
+  reg m_hdr = 1'b1;
+  always @(posedge clk) begin
+    if (rst)
+      m_hdr <= 1'b1;
+    else if (m_dma_tvalid && m_dma_tready)
+      m_hdr <= m_dma_tlast;
+  end
+
+  reg [DMA_ID_WIDTH-1:0] cached_dest = {DMA_ID_WIDTH{1'b0}};
+  always @(posedge clk) begin
+    if (m_hdr)
+      cached_dest <= m_axis_xport_tuser;
+  end
+
+  assign m_dma_tuser = m_hdr ? m_axis_xport_tuser : cached_dest;
+
+endmodule // liberio_chdr64_adapter
diff --git a/fpga/usrp3/lib/rfnoc/xport/rfnoc_xport_types.vh b/fpga/usrp3/lib/rfnoc/xport/rfnoc_xport_types.vh
new file mode 100644
index 000000000..5b273a4b4
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/xport/rfnoc_xport_types.vh
@@ -0,0 +1,11 @@
+//
+// Copyright 2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+// Add all new transport types here
+localparam [7:0] NODE_SUBTYPE_XPORT_GENERIC        = 8'd0;
+localparam [7:0] NODE_SUBTYPE_XPORT_IPV4_CHDR64    = 8'd1;
+localparam [7:0] NODE_SUBTYPE_XPORT_LIBERIO_CHDR64 = 8'd2;
+localparam [7:0] NODE_SUBTYPE_XPORT_NIRIO_CHDR64   = 8'd3;
diff --git a/fpga/usrp3/lib/sim/Makefile.srcs b/fpga/usrp3/lib/sim/Makefile.srcs
new file mode 100644
index 000000000..b76175cd9
--- /dev/null
+++ b/fpga/usrp3/lib/sim/Makefile.srcs
@@ -0,0 +1,26 @@
+#
+# Copyright 2016 Ettus Research
+#
+
+# Minimal set of sources in lib directory needed for simulation
+include $(BASE_DIR)/../lib/fifo/Makefile.srcs
+include $(BASE_DIR)/../lib/axi/Makefile.srcs
+include $(BASE_DIR)/../lib/control/Makefile.srcs
+include $(BASE_DIR)/../lib/timing/Makefile.srcs
+include $(BASE_DIR)/../lib/packet_proc/Makefile.srcs
+include $(BASE_DIR)/../lib/dsp/Makefile.srcs
+include $(BASE_DIR)/../lib/rfnoc/Makefile.srcs
+
+# Use sim version of axi_fifo_2clk
+FIFO_SRCS := $(filter-out %/axi_fifo_2clk.v,$(FIFO_SRCS))
+FIFO_SRCS += $(abspath $(BASE_DIR)/../lib/sim/fifo/axi_fifo_2clk_sim.v)
+
+SIM_DESIGN_SRCS = $(abspath \
+$(FIFO_SRCS) \
+$(AXI_SRCS) \
+$(CONTROL_LIB_SRCS) \
+$(TIMING_SRCS) \
+$(PACKET_PROC_SRCS) \
+$(DSP_SRCS) \
+$(RFNOC_SRCS) \
+)
diff --git a/fpga/usrp3/lib/sim/arm_deframer/Makefile b/fpga/usrp3/lib/sim/arm_deframer/Makefile
new file mode 100644
index 000000000..eb7231d5e
--- /dev/null
+++ b/fpga/usrp3/lib/sim/arm_deframer/Makefile
@@ -0,0 +1,47 @@
+#
+# Copyright 2015 Ettus Research LLC
+#
+
+#-------------------------------------------------
+# Top-of-Makefile
+#-------------------------------------------------
+# Define BASE_DIR to point to the "top" dir
+BASE_DIR = $(abspath ../../../top)
+# Include viv_sim_preamble after defining BASE_DIR
+include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
+
+#-------------------------------------------------
+# IP Specific
+#-------------------------------------------------
+# If simulation contains IP, define the IP_DIR and point
+# it to the base level IP directory
+LIB_IP_DIR = $(BASE_DIR)/../lib/ip
+
+# Include makefiles and sources for all IP components
+# *after* defining the IP_DIR
+
+DESIGN_SRCS += $(abspath \
+../../packet_proc/arm_deframer.v \
+../../fifo/axi_mux4.v \
+)
+
+#-------------------------------------------------
+# Testbench Specific
+#-------------------------------------------------
+# Define only one toplevel module
+SIM_TOP = arm_deframer_tb
+
+SIM_SRCS = $(abspath \
+$(SIM_PROTORFNOC_SRCS) \
+arm_deframer_tb.sv \
+)
+
+MODELSIM_USER_DO = $(abspath wave.do)
+
+#-------------------------------------------------
+# Bottom-of-Makefile
+#-------------------------------------------------
+# Include all simulator specific makefiles here
+# Each should define a unique target to simulate
+# e.g. xsim, vsim, etc and a common "clean" target
+include $(BASE_DIR)/../tools/make/viv_simulator.mak
diff --git a/fpga/usrp3/lib/sim/arm_deframer/arm_deframer_tb.sv b/fpga/usrp3/lib/sim/arm_deframer/arm_deframer_tb.sv
new file mode 100644
index 000000000..4e252b5b4
--- /dev/null
+++ b/fpga/usrp3/lib/sim/arm_deframer/arm_deframer_tb.sv
@@ -0,0 +1,112 @@
+/////////////////////////////////////////////////////////////////////
+//
+// Copyright 2016-2017 Ettus Research
+//
+// Arm Deframer Testbench
+//
+// Arm Deframer adds a 6 bit padding to the ethernet frame
+//
+//////////////////////////////////////////////////////////////////////
+
+`timescale 1ns/1ps
+`define SIM_RUNTIME_US 0.0001
+`define NS_PER_TICK 1
+`define NUM_TEST_CASES 3
+`include "sim_axis_lib.svh"
+`include "sim_exec_report.vh"
+`include "sim_rfnoc_lib.svh"
+`include "sim_set_rb_lib.svh"
+
+// NOTE: The tesbench is not self-checking
+module arm_deframer_tb();
+  `TEST_BENCH_INIT("arm_deframer_tb",`NUM_TEST_CASES,`NS_PER_TICK);
+  localparam CLK_PERIOD = $ceil(1e6/166.67e6);
+  `DEFINE_CLK(clk, CLK_PERIOD, 50);
+  `DEFINE_RESET(rst, 0, 100);
+
+  axis_master #(.DWIDTH(68)) m_axis (.clk(clk));
+  axis_slave #(.DWIDTH(68)) s_axis (.clk(clk));
+
+  reg clear;
+  wire  [63:0]  c2e_tdata_int;
+  wire  [3:0]   c2e_tuser_int;
+  wire          c2e_tlast_int;
+  wire          c2e_tvalid_int;
+  wire          c2e_tready_int;
+
+  arm_deframer inst_arm_deframer (
+   .clk               (clk),
+   .reset             (rst),
+   .clear             (clear),
+   .s_axis_tdata      (m_axis.axis.tdata[63:0]),
+   .s_axis_tuser      (m_axis.axis.tdata[67:64]),
+   .s_axis_tlast      (m_axis.axis.tlast),
+   .s_axis_tvalid     (m_axis.axis.tvalid),
+   .s_axis_tready     (m_axis.axis.tready),
+   .m_axis_tdata      (c2e_tdata_int),
+   .m_axis_tuser      (c2e_tuser_int),
+   .m_axis_tlast      (c2e_tlast_int),
+   .m_axis_tvalid     (c2e_tvalid_int),
+   .m_axis_tready     (c2e_tready_int)
+  );
+
+  axi_mux4 #(.PRIO(0), .WIDTH(68)) eth_mux
+    (.clk(clk), .reset(reset), .clear(clear),
+     .i0_tdata({c2e_tuser_int,c2e_tdata_int}), .i0_tlast(c2e_tlast_int), .i0_tvalid(c2e_tvalid_int), .i0_tready(c2e_tready_int),
+     .i1_tdata(), .i1_tlast(), .i1_tvalid(), .i1_tready(),
+     .i2_tdata(), .i2_tlast(), .i2_tvalid(), .i2_tready(),
+     .i3_tdata(), .i3_tlast(), .i3_tvalid(1'b0), .i3_tready(),
+     .o_tdata(s_axis.axis.tdata), .o_tlast(s_axis.axis.tlast), .o_tvalid(s_axis.axis.tvalid), .o_tready(1'b1/*s_axis.axis.tready*/));
+
+ reg [63:0] out_tdata;
+ reg [3:0] tuser;
+ reg tlast;
+
+ initial begin
+  forever begin
+    s_axis.pull_word({tuser,out_tdata}, tlast);
+    $display("tuser = %d, out_tdata = %x, last = %d", tuser, out_tdata, tlast);
+  end
+ end
+
+ initial begin : tb_main
+    `TEST_CASE_START("Wait for reset");
+    m_axis.reset;
+    while (rst) @(posedge clk);
+    `TEST_CASE_DONE(~rst);
+
+    `TEST_CASE_START("Send frame");
+    repeat (10) @(posedge clk);
+      for (int j = 0; j < 2; j ++) begin
+      @(posedge clk);
+        $display("----------New Frame---------------");
+        for (int i = 0; i < 9; i ++) begin
+          m_axis.push_word({4'h0,64'h1111111111111111 * i}, 1'b0);
+          //m_axis.push_bubble();
+        end
+        m_axis.push_word({4'h1,64'h9999999999999999}, 1'b1);
+        //m_axis.push_bubble();
+      end
+      @(posedge clk);
+      @(posedge clk);
+    `TEST_CASE_DONE(1);
+     repeat (10) @(posedge clk);
+
+    `TEST_CASE_START("Send frame with bubble");
+    repeat (10) @(posedge clk);
+      for (int j = 0; j < 2; j ++) begin
+      @(posedge clk);
+        $display("----------New Frame---------------");
+        for (int i = 0; i < 9; i ++) begin
+          m_axis.push_word({4'h0,64'h1111111111111111 * i}, 1'b0);
+          m_axis.push_bubble();
+        end
+        m_axis.push_word({4'h1,64'h9999999999999999}, 1'b1);
+        m_axis.push_bubble();
+      end
+      @(posedge clk);
+      @(posedge clk);
+    `TEST_CASE_DONE(1);
+    `TEST_BENCH_DONE;
+ end
+endmodule
diff --git a/fpga/usrp3/lib/sim/axi/axis_shift_register/Makefile b/fpga/usrp3/lib/sim/axi/axis_shift_register/Makefile
new file mode 100644
index 000000000..8a65a6024
--- /dev/null
+++ b/fpga/usrp3/lib/sim/axi/axis_shift_register/Makefile
@@ -0,0 +1,49 @@
+#
+# Copyright 2018 Ettus Research, A National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+#-------------------------------------------------
+# Top-of-Makefile
+#-------------------------------------------------
+# Define BASE_DIR to point to the "top" dir
+BASE_DIR = $(abspath ../../../../top)
+# Include viv_sim_preamble after defining BASE_DIR
+include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
+
+#-------------------------------------------------
+# Design Specific
+#-------------------------------------------------
+# Include makefiles and sources for the DUT and its dependencies
+include $(BASE_DIR)/../lib/axi/Makefile.srcs
+include $(BASE_DIR)/../lib/fifo/Makefile.srcs
+include $(BASE_DIR)/../lib/control/Makefile.srcs
+
+DESIGN_SRCS = $(abspath \
+$(AXI_SRCS) \
+$(FIFO_SRCS) \
+$(CONTROL_LIB_SRCS) \
+)
+
+#-------------------------------------------------
+# Testbench Specific
+#-------------------------------------------------
+# Define only one toplevel module
+SIM_TOP = axis_shift_register_tb
+
+# Add test bench, user design under test, and
+# additional user created files
+SIM_SRCS = $(abspath \
+axis_shift_register_tb.sv \
+)
+
+# MODELSIM_USER_DO = $(abspath wave.do)
+
+#-------------------------------------------------
+# Bottom-of-Makefile
+#-------------------------------------------------
+# Include all simulator specific makefiles here
+# Each should define a unique target to simulate
+# e.g. xsim, vsim, etc and a common "clean" target
+include $(BASE_DIR)/../tools/make/viv_simulator.mak
diff --git a/fpga/usrp3/lib/sim/axi/axis_shift_register/axis_shift_register_tb.sv b/fpga/usrp3/lib/sim/axi/axis_shift_register/axis_shift_register_tb.sv
new file mode 100644
index 000000000..1ce868069
--- /dev/null
+++ b/fpga/usrp3/lib/sim/axi/axis_shift_register/axis_shift_register_tb.sv
@@ -0,0 +1,325 @@
+//
+// Copyright 2018 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+`timescale 1ns/1ps
+`define NS_PER_TICK 1
+`define NUM_TEST_CASES 8
+
+`include "sim_exec_report.vh"
+`include "sim_clks_rsts.vh"
+`include "sim_axis_lib.svh"
+
+module axis_shift_register_tb();
+  `TEST_BENCH_INIT("axis_shift_register_tb", `NUM_TEST_CASES, `NS_PER_TICK);
+  localparam CLK_PERIOD = $ceil(1e9/100.0e6);
+  `DEFINE_CLK(clk, CLK_PERIOD, 50);
+  `DEFINE_RESET(reset, 0, 100);
+
+  localparam             WIDTH                = 32;
+  localparam integer     NUM_INST             = 4;
+
+  logic [WIDTH:0]   i_tdata[0:NUM_INST-1];
+  logic             i_tlast[0:NUM_INST-1], i_tvalid[0:NUM_INST-1];
+  wire              i_tready[0:NUM_INST-1];
+  wire [WIDTH:0]    o_tdata[0:NUM_INST-1];
+  wire              o_tlast[0:NUM_INST-1], o_tvalid[0:NUM_INST-1];
+  logic             o_tready[0:NUM_INST-1];
+  wire [15:0]       stage_stb[0:NUM_INST-1], stage_eop[0:NUM_INST-1];
+  wire [WIDTH-1:0]  sb_dout, sb_din;
+  wire              sb_keep;
+  reg  [WIDTH-1:0]  sb_shreg[0:2];
+  always @(posedge clk) begin
+    if (stage_stb[2][0])
+      sb_shreg[0] <= sb_dout;
+    if (stage_stb[2][1])
+      sb_shreg[1] <= sb_shreg[0];
+    if (stage_stb[2][2])
+      sb_shreg[2] <= sb_shreg[1];
+  end
+  assign sb_din = sb_shreg[2];
+
+  axis_shift_register #(
+    .WIDTH(WIDTH), .NSPC(1), .LATENCY(2),
+    .SIDEBAND_DATAPATH(0), .GAPLESS(0), 
+    .PIPELINE("NONE")
+  ) inst_0 (
+    .clk(clk), .reset(reset),
+    .s_axis_tdata(i_tdata[0]), .s_axis_tkeep(i_tdata[0][WIDTH]), .s_axis_tlast(i_tlast[0]),
+    .s_axis_tvalid(i_tvalid[0]), .s_axis_tready(i_tready[0]),
+    .m_axis_tdata(o_tdata[0]), .m_axis_tkeep(o_tdata[0][WIDTH]), .m_axis_tlast(o_tlast[0]),
+    .m_axis_tvalid(o_tvalid[0]), .m_axis_tready(o_tready[0]),
+    .stage_stb(stage_stb[0]), .stage_eop(stage_eop[0]),
+    .m_sideband_data(), .m_sideband_keep(), .s_sideband_data()
+  );
+
+  axis_shift_register #(
+    .WIDTH(WIDTH), .NSPC(1), .LATENCY(9),
+    .SIDEBAND_DATAPATH(0), .GAPLESS(0), 
+    .PIPELINE("BOTH")
+  ) inst_1 (
+    .clk(clk), .reset(reset),
+    .s_axis_tdata(i_tdata[1]), .s_axis_tkeep(i_tdata[1][WIDTH]), .s_axis_tlast(i_tlast[1]),
+    .s_axis_tvalid(i_tvalid[1]), .s_axis_tready(i_tready[1]),
+    .m_axis_tdata(o_tdata[1]), .m_axis_tkeep(o_tdata[1][WIDTH]), .m_axis_tlast(o_tlast[1]),
+    .m_axis_tvalid(o_tvalid[1]), .m_axis_tready(o_tready[1]),
+    .stage_stb(stage_stb[1]), .stage_eop(stage_eop[1]),
+    .m_sideband_data(), .m_sideband_keep(), .s_sideband_data()
+  );
+
+  axis_shift_register #(
+    .WIDTH(WIDTH/2), .NSPC(2), .LATENCY(3),
+    .SIDEBAND_DATAPATH(1), .GAPLESS(0), 
+    .PIPELINE("NONE")
+  ) inst_2 (
+    .clk(clk), .reset(reset),
+    .s_axis_tdata(i_tdata[2]), .s_axis_tkeep(i_tdata[2][WIDTH]), .s_axis_tlast(i_tlast[2]),
+    .s_axis_tvalid(i_tvalid[2]), .s_axis_tready(i_tready[2]),
+    .m_axis_tdata(o_tdata[2]), .m_axis_tkeep(o_tdata[2][WIDTH]), .m_axis_tlast(o_tlast[2]),
+    .m_axis_tvalid(o_tvalid[2]), .m_axis_tready(o_tready[2]),
+    .stage_stb(stage_stb[2]), .stage_eop(stage_eop[2]),
+    .m_sideband_data(sb_dout), .m_sideband_keep(sb_keep), .s_sideband_data(sb_din)
+  );
+
+  axis_shift_register #(
+    .WIDTH(WIDTH/8), .NSPC(8), .LATENCY(14),
+    .SIDEBAND_DATAPATH(0), .GAPLESS(1), 
+    .PIPELINE("NONE")
+  ) inst_3 (
+    .clk(clk), .reset(reset),
+    .s_axis_tdata(i_tdata[3]), .s_axis_tkeep(i_tdata[3][WIDTH]), .s_axis_tlast(i_tlast[3]),
+    .s_axis_tvalid(i_tvalid[3]), .s_axis_tready(i_tready[3]),
+    .m_axis_tdata(o_tdata[3]), .m_axis_tkeep(o_tdata[3][WIDTH]), .m_axis_tlast(o_tlast[3]),
+    .m_axis_tvalid(o_tvalid[3]), .m_axis_tready(o_tready[3]),
+    .stage_stb(stage_stb[3]), .stage_eop(stage_eop[3]),
+    .m_sideband_data(), .m_sideband_keep(), .s_sideband_data()
+  );
+
+  logic [15:0] prev_stage_stb[0:NUM_INST-1];
+  initial begin : tb_main
+    string s;
+
+    `TEST_CASE_START("Wait for Reset");
+      for (int k = 0; k < NUM_INST; k=k+1) begin
+        o_tready[k] = 1'b1;
+        i_tvalid[k] = 1'b0;
+        prev_stage_stb[k] = 0;
+      end
+      while (reset) @(posedge clk);
+    `TEST_CASE_DONE(~reset);
+
+    `TEST_CASE_START("Check module with LATENCY=2, PIPELINE=NONE");
+      `ASSERT_ERROR(o_tvalid[0] == 1'b0, "Output incorrectly active when idle");
+      `ASSERT_ERROR(i_tready[0] == 1'b1, "Input was not ready when idle");
+      `ASSERT_ERROR(stage_stb[0][1:0] === 0, "Incorrect stage_stb when idle");
+      for (int j = 0; j < 2; j=j+1) begin
+        i_tdata[0] = j;
+        i_tlast[0] = j % 2;
+        i_tvalid[0] = 1'b1;
+        @(posedge clk);
+        i_tvalid[0] = 1'b0;
+        prev_stage_stb[0][1:0] = {prev_stage_stb[0][0], 1'b1};
+        `ASSERT_ERROR(stage_stb[0][1:0] == prev_stage_stb[0][1:0], "Incorrect stage_stb");
+        `ASSERT_ERROR(i_tready[0] == 1'b1, "Input was not ready during fill-up");
+        `ASSERT_ERROR(o_tvalid[0] == 1'b0, "Output incorrectly active during fill-up");
+      end
+      for (int j = 0; j < 2; j=j+1) begin
+        @(posedge clk);
+        `ASSERT_ERROR(o_tvalid[0] == 1'b1, "Output was not active");
+        `ASSERT_ERROR(o_tlast[0] == j % 2, "Incorrect tlast");
+        `ASSERT_ERROR(o_tdata[0] == j, "Incorrect tdata");
+      end
+    `TEST_CASE_DONE(1);
+
+    `TEST_CASE_START("Check module with LATENCY=9, PIPELINE=BOTH");
+      prev_stage_stb[1] = 0;
+      `ASSERT_ERROR(o_tvalid[1] == 1'b0, "Output incorrectly active when idle");
+      `ASSERT_ERROR(i_tready[1] == 1'b1, "Input was not ready when idle");
+      `ASSERT_ERROR(stage_stb[1][1:0] === 0, "Incorrect stage_stb when idle");
+      for (int j = 0; j < 9; j=j+1) begin
+        i_tdata[1] = -j;
+        i_tlast[1] = 1'b1;
+        i_tvalid[1] = 1'b1;
+        @(posedge clk);
+        i_tvalid[1] = 1'b0;
+        prev_stage_stb[1][8:0] = {prev_stage_stb[1][7:0], 1'b1};
+        `ASSERT_ERROR(stage_eop[1][8:0] == prev_stage_stb[1][8:0], "Incorrect stage_eop");
+        `ASSERT_ERROR(stage_stb[1][8:0] == prev_stage_stb[1][8:0], "Incorrect stage_stb");
+        `ASSERT_ERROR(i_tready[1] == 1'b1, "Input was not ready during fill-up");
+        `ASSERT_ERROR(o_tvalid[1] == 1'b0, "Output incorrectly active during fill-up");
+      end
+      for (int j = 0; j < 9; j=j+1) begin
+        @(posedge clk);
+        `ASSERT_ERROR(o_tvalid[1] == 1'b1, "Output was not active");
+        `ASSERT_ERROR(o_tlast[1] == 1'b1, "Incorrect tlast");
+        `ASSERT_ERROR(o_tdata[1] == -j, "Incorrect tdata");
+      end
+      @(posedge clk);
+    `TEST_CASE_DONE(1);
+
+    `TEST_CASE_START("Check module with LATENCY=9, PIPELINE=BOTH (backpressure)");
+      prev_stage_stb[1] = 0;
+      o_tready[1] = 1'b0;
+      `ASSERT_ERROR(o_tvalid[1] == 1'b0, "Output incorrectly active when idle");
+      `ASSERT_ERROR(i_tready[1] == 1'b1, "Input was not ready when idle");
+      `ASSERT_ERROR(stage_stb[1][1:0] === 0, "Incorrect stage_stb when idle");
+      for (int j = 0; j < 9; j=j+1) begin
+        i_tdata[1] = -j;
+        i_tlast[1] = 1'b1;
+        i_tvalid[1] = 1'b1;
+        @(posedge clk);
+        i_tvalid[1] = 1'b0;
+        prev_stage_stb[1][8:0] = {prev_stage_stb[1][7:0], 1'b1};
+        `ASSERT_ERROR(stage_stb[1][8:0] == prev_stage_stb[1][8:0], "Incorrect stage_stb");
+        `ASSERT_ERROR(stage_eop[1][8:0] == prev_stage_stb[1][8:0], "Incorrect stage_eop");
+        `ASSERT_ERROR(i_tready[1] == 1'b1, "Input was not ready during fill-up");
+        `ASSERT_ERROR(o_tvalid[1] == 1'b0, "Output incorrectly active during fill-up");
+      end
+      o_tready[1] = 1'b1;
+      for (int j = 0; j < 9; j=j+1) begin
+        @(posedge clk);
+        `ASSERT_ERROR(o_tvalid[1] == 1'b1, "Output was not active");
+        `ASSERT_ERROR(o_tlast[1] == 1'b1, "Incorrect tlast");
+        `ASSERT_ERROR(o_tdata[1] == -j, "Incorrect tdata");
+      end
+      @(posedge clk);
+    `TEST_CASE_DONE(1);
+
+    `TEST_CASE_START("Check module with LATENCY=9, PIPELINE=BOTH (steady-state)");
+      prev_stage_stb[1] = 0;
+      fork
+        begin
+          for (int j = 0; j < 50; j=j+1) begin
+            i_tdata[1] = j;
+            i_tlast[1] = j % 2;
+            i_tvalid[1] = 1'b1;
+            @(posedge clk);
+            i_tvalid[1] = 1'b0;
+            prev_stage_stb[1][8:0] = {prev_stage_stb[1][7:0], 1'b1};
+            `ASSERT_ERROR(stage_stb[1][8:0] == prev_stage_stb[1][8:0], "Incorrect stage_stb");
+          end
+        end
+        begin
+          o_tready[1] = 1'b1;
+          repeat(9) @(posedge clk);
+          for (int j = 0; j < 50; j=j+1) begin
+            @(posedge clk);
+            `ASSERT_ERROR(o_tvalid[1] == 1'b1, "Output was not active");
+            `ASSERT_ERROR(o_tlast[1] == j % 2, "Incorrect tlast");
+            `ASSERT_ERROR(o_tdata[1] == j, "Incorrect tdata");
+          end
+          @(posedge clk);
+        end
+      join
+    `TEST_CASE_DONE(1);
+
+    `TEST_CASE_START("Check module with LATENCY=9, PIPELINE=BOTH (gaps)");
+      prev_stage_stb[1] = 0;
+      fork
+        begin
+          for (int j = 0; j < 50; j=j+1) begin
+            i_tdata[1] = j;
+            i_tlast[1] = j % 2;
+            i_tvalid[1] = 1'b1;
+            @(posedge clk);
+            while (~i_tready[1]) @(posedge clk);
+            i_tvalid[1] = 1'b0;
+          end
+        end
+        begin
+          o_tready[1] = 1'b1;
+          repeat(9) @(posedge clk);
+          for (int j = 0; j < 20; j=j+1) begin
+            @(posedge clk);
+            `ASSERT_ERROR(o_tvalid[1] == 1'b1, "Output was not active");
+            `ASSERT_ERROR(o_tlast[1] == j % 2, "Incorrect tlast");
+            `ASSERT_ERROR(o_tdata[1] == j, "Incorrect tdata");
+          end
+          o_tready[1] = 1'b0;
+          repeat(4) @(posedge clk);
+          o_tready[1] = 1'b1;
+          for (int j = 20; j < 50; j=j+1) begin
+            @(posedge clk);
+            `ASSERT_ERROR(o_tvalid[1] == 1'b1, "Output was not active");
+            `ASSERT_ERROR(o_tlast[1] == j % 2, "Incorrect tlast");
+            `ASSERT_ERROR(o_tdata[1] == j, "Incorrect tdata");
+          end
+          @(posedge clk);
+        end
+      join
+    `TEST_CASE_DONE(1);
+
+    `TEST_CASE_START("Check module with LATENCY=3, SIDEBAND=1 (gaps)");
+      prev_stage_stb[2] = 0;
+      fork
+        begin
+          for (int j = 0; j < 50; j=j+1) begin
+            i_tdata[2] = j;
+            i_tlast[2] = j % 4 == 0;
+            i_tvalid[2] = 1'b1;
+            @(posedge clk);
+            while (~i_tready[2]) @(posedge clk);
+            i_tvalid[2] = 1'b0;
+          end
+        end
+        begin
+          o_tready[2] = 1'b1;
+          repeat(3) @(posedge clk);
+          for (int j = 0; j < 20; j=j+1) begin
+            @(posedge clk);
+            `ASSERT_ERROR(o_tvalid[2] == 1'b1, "Output was not active");
+            `ASSERT_ERROR(o_tlast[2] == j % 4 == 0, "Incorrect tlast");
+            `ASSERT_ERROR(o_tdata[2] == j, "Incorrect tdata");
+          end
+          o_tready[2] = 1'b0;
+          repeat(4) @(posedge clk);
+          o_tready[2] = 1'b1;
+          for (int j = 20; j < 50; j=j+1) begin
+            @(posedge clk);
+            `ASSERT_ERROR(o_tvalid[2] == 1'b1, "Output was not active");
+            `ASSERT_ERROR(o_tlast[2] == j % 4 == 0, "Incorrect tlast");
+            `ASSERT_ERROR(o_tdata[2] == j, "Incorrect tdata");
+          end
+          @(posedge clk);
+        end
+      join
+    `TEST_CASE_DONE(1);
+
+    `TEST_CASE_START("Check module with LATENCY=14, GAPLESS=1");
+      prev_stage_stb[3] = 0;
+      o_tready[3] = 1'b0;
+      fork
+        begin
+          for (int j = 0; j < 50; j=j+1) begin
+            i_tdata[3] = j;
+            i_tlast[3] = j % 4 == 0;
+            i_tvalid[3] = 1'b1;
+            @(posedge clk);
+            prev_stage_stb[3][13:0] = {prev_stage_stb[3][12:0], 1'b1};
+            `ASSERT_ERROR(stage_stb[3][13:0] == prev_stage_stb[3][13:0], "Incorrect stage_stb");
+            while (~i_tready[3]) @(posedge clk);
+            i_tvalid[3] = 1'b0;
+            if (j > 16) repeat($urandom_range(0, 15)) @(posedge clk);
+            `ASSERT_ERROR(stage_stb[3][13:0] == prev_stage_stb[3][13:0] || stage_stb[3][13:0] == 14'd0, "Incorrect stage_stb");
+          end
+        end
+        begin
+          for (int j = 0; j < 50 - 14; j=j+1) begin
+            while (~o_tvalid[3]) @(posedge clk);
+            @(negedge clk);
+            `ASSERT_ERROR(o_tvalid[3] == 1'b1, "Output was not active");
+            `ASSERT_ERROR(o_tlast[3] == j % 4 == 0, "Incorrect tlast");
+            `ASSERT_ERROR(o_tdata[3] == j, "Incorrect tdata");
+            o_tready[3] = 1'b1;
+            @(negedge clk);
+            o_tready[3] = 1'b0;
+            @(posedge clk);
+          end
+        end
+      join
+    `TEST_CASE_DONE(1);
+    `TEST_BENCH_DONE;
+  end
+endmodule
diff --git a/fpga/usrp3/lib/sim/axi/axis_width_conv/Makefile b/fpga/usrp3/lib/sim/axi/axis_width_conv/Makefile
new file mode 100644
index 000000000..2e7d0ba0c
--- /dev/null
+++ b/fpga/usrp3/lib/sim/axi/axis_width_conv/Makefile
@@ -0,0 +1,35 @@
+#
+# Copyright 2018 Ettus Research, A National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+#-------------------------------------------------
+# Top-of-Makefile
+#-------------------------------------------------
+# Define BASE_DIR to point to the "top" dir
+BASE_DIR = $(abspath ../../../../top)
+# Include viv_sim_preamble after defining BASE_DIR
+include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
+
+#-------------------------------------------------
+# Testbench Specific
+#-------------------------------------------------
+# Define only one toplevel module
+SIM_TOP = axis_width_conv_tb
+
+# Add test bench, user design under test, and
+# additional user created files
+SIM_SRCS = $(abspath \
+axis_width_conv_tb.sv \
+)
+
+# MODELSIM_USER_DO = $(abspath wave.do)
+
+#-------------------------------------------------
+# Bottom-of-Makefile
+#-------------------------------------------------
+# Include all simulator specific makefiles here
+# Each should define a unique target to simulate
+# e.g. xsim, vsim, etc and a common "clean" target
+include $(BASE_DIR)/../tools/make/viv_simulator.mak
diff --git a/fpga/usrp3/lib/sim/axi/axis_width_conv/axis_width_conv_tb.sv b/fpga/usrp3/lib/sim/axi/axis_width_conv/axis_width_conv_tb.sv
new file mode 100644
index 000000000..0b1f4414c
--- /dev/null
+++ b/fpga/usrp3/lib/sim/axi/axis_width_conv/axis_width_conv_tb.sv
@@ -0,0 +1,322 @@
+//
+// Copyright 2018 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+`timescale 1ns/1ps
+`define NS_PER_TICK 1
+`define NUM_TEST_CASES 13
+
+`include "sim_exec_report.vh"
+`include "sim_clks_rsts.vh"
+`include "sim_axis_lib.svh"
+
+module axis_width_conv_tb();
+  `TEST_BENCH_INIT("axis_width_conv_tb", `NUM_TEST_CASES, `NS_PER_TICK);
+
+  `DEFINE_CLK(clk50,  20.000, 50);
+  `DEFINE_CLK(clk200,  5.000, 50);
+  `DEFINE_LATE_START_CLK(clk166, 6.000, 50, 0.37, 0.01)
+  `DEFINE_RESET(areset, 0, 100);
+
+  localparam         WORD_W               = 8;
+  localparam integer NINST                = 6;
+  localparam integer IN_WORDS[0:NINST-1]  = {1, 4, 4, 8, 8, 17};
+  localparam integer OUT_WORDS[0:NINST-1] = {4, 1, 3, 2, 8, 19};
+  localparam integer MAX_IN_WORDS         = 20;
+  localparam integer MAX_OUT_WORDS        = 20;
+  localparam integer MAX_SPP              = 100;
+
+  axis_master #(.DWIDTH((WORD_W+1)*IN_WORDS[0]))  m0 (.clk(clk50));
+  axis_master #(.DWIDTH((WORD_W+1)*IN_WORDS[1]))  m1 (.clk(clk50));
+  axis_master #(.DWIDTH((WORD_W+1)*IN_WORDS[2]))  m2 (.clk(clk50));
+  axis_master #(.DWIDTH((WORD_W+1)*IN_WORDS[3]))  m3 (.clk(clk50));
+  axis_master #(.DWIDTH((WORD_W+1)*IN_WORDS[4]))  m4 (.clk(clk50));
+  axis_master #(.DWIDTH((WORD_W+1)*IN_WORDS[5]))  m5 (.clk(clk50));
+
+  axis_slave  #(.DWIDTH((WORD_W+1)*OUT_WORDS[0])) s0 (.clk(clk50));
+  axis_slave  #(.DWIDTH((WORD_W+1)*OUT_WORDS[1])) s1 (.clk(clk50));
+  axis_slave  #(.DWIDTH((WORD_W+1)*OUT_WORDS[2])) s2 (.clk(clk200));
+  axis_slave  #(.DWIDTH((WORD_W+1)*OUT_WORDS[3])) s3 (.clk(clk166));
+  axis_slave  #(.DWIDTH((WORD_W+1)*OUT_WORDS[4])) s4 (.clk(clk166));
+  axis_slave  #(.DWIDTH((WORD_W+1)*OUT_WORDS[5])) s5 (.clk(clk50));
+
+  // An integer 1-to-4 upsizer
+  axis_width_conv #(
+    .WORD_W(WORD_W), .IN_WORDS(IN_WORDS[0]), .OUT_WORDS(OUT_WORDS[0]),
+    .SYNC_CLKS(1), .PIPELINE("INOUT")
+  ) dut0 (
+    .s_axis_aclk  (clk50),
+    .s_axis_rst   (areset),
+    .s_axis_tdata (m0.axis.tdata[(IN_WORDS[0]*WORD_W)-1:0]), 
+    .s_axis_tkeep (m0.axis.tdata[IN_WORDS[0]*WORD_W+:IN_WORDS[0]]),
+    .s_axis_tlast (m0.axis.tlast),
+    .s_axis_tvalid(m0.axis.tvalid),
+    .s_axis_tready(m0.axis.tready),
+    .m_axis_aclk  (clk50),
+    .m_axis_rst   (areset),
+    .m_axis_tdata (s0.axis.tdata[(OUT_WORDS[0]*WORD_W)-1:0]),
+    .m_axis_tkeep (s0.axis.tdata[OUT_WORDS[0]*WORD_W+:OUT_WORDS[0]]),
+    .m_axis_tlast (s0.axis.tlast),
+    .m_axis_tvalid(s0.axis.tvalid),
+    .m_axis_tready(s0.axis.tready)
+  );
+
+  // An integer 4-to-1 downsizer
+  axis_width_conv #(
+    .WORD_W(WORD_W), .IN_WORDS(IN_WORDS[1]), .OUT_WORDS(OUT_WORDS[1]),
+    .SYNC_CLKS(1), .PIPELINE("IN")
+  ) dut1 (
+    .s_axis_aclk  (clk50),
+    .s_axis_rst   (areset),
+    .s_axis_tdata (m1.axis.tdata[(IN_WORDS[1]*WORD_W)-1:0]), 
+    .s_axis_tkeep (m1.axis.tdata[IN_WORDS[1]*WORD_W+:IN_WORDS[1]]),
+    .s_axis_tlast (m1.axis.tlast),
+    .s_axis_tvalid(m1.axis.tvalid),
+    .s_axis_tready(m1.axis.tready),
+    .m_axis_aclk  (clk50),
+    .m_axis_rst   (areset),
+    .m_axis_tdata (s1.axis.tdata[(OUT_WORDS[1]*WORD_W)-1:0]),
+    .m_axis_tkeep (s1.axis.tdata[OUT_WORDS[1]*WORD_W+:OUT_WORDS[1]]),
+    .m_axis_tlast (s1.axis.tlast),
+    .m_axis_tvalid(s1.axis.tvalid),
+    .m_axis_tready(s1.axis.tready)
+  );
+
+  // A rational integer 4-to-3 downsizer
+  axis_width_conv #(
+    .WORD_W(WORD_W), .IN_WORDS(IN_WORDS[2]), .OUT_WORDS(OUT_WORDS[2]),
+    .SYNC_CLKS(0), .PIPELINE("OUT")
+  ) dut2 (
+    .s_axis_aclk  (clk50),
+    .s_axis_rst   (areset),
+    .s_axis_tdata (m2.axis.tdata[(IN_WORDS[2]*WORD_W)-1:0]), 
+    .s_axis_tkeep (m2.axis.tdata[IN_WORDS[2]*WORD_W+:IN_WORDS[2]]),
+    .s_axis_tlast (m2.axis.tlast),
+    .s_axis_tvalid(m2.axis.tvalid),
+    .s_axis_tready(m2.axis.tready),
+    .m_axis_aclk  (clk200),
+    .m_axis_rst   (areset),
+    .m_axis_tdata (s2.axis.tdata[(OUT_WORDS[2]*WORD_W)-1:0]),
+    .m_axis_tkeep (s2.axis.tdata[OUT_WORDS[2]*WORD_W+:OUT_WORDS[2]]),
+    .m_axis_tlast (s2.axis.tlast),
+    .m_axis_tvalid(s2.axis.tvalid),
+    .m_axis_tready(s2.axis.tready)
+  );
+
+  // An integer 4-to-1 downsizer but with 2 words per cycle
+  axis_width_conv #(
+    .WORD_W(WORD_W), .IN_WORDS(IN_WORDS[3]), .OUT_WORDS(OUT_WORDS[3]),
+    .SYNC_CLKS(0), .PIPELINE("NONE")
+  ) dut3 (
+    .s_axis_aclk  (clk50),
+    .s_axis_rst   (areset),
+    .s_axis_tdata (m3.axis.tdata[(IN_WORDS[3]*WORD_W)-1:0]), 
+    .s_axis_tkeep (m3.axis.tdata[IN_WORDS[3]*WORD_W+:IN_WORDS[3]]),
+    .s_axis_tlast (m3.axis.tlast),
+    .s_axis_tvalid(m3.axis.tvalid),
+    .s_axis_tready(m3.axis.tready),
+    .m_axis_aclk  (clk166),
+    .m_axis_rst   (areset),
+    .m_axis_tdata (s3.axis.tdata[(OUT_WORDS[3]*WORD_W)-1:0]),
+    .m_axis_tkeep (s3.axis.tdata[OUT_WORDS[3]*WORD_W+:OUT_WORDS[3]]),
+    .m_axis_tlast (s3.axis.tlast),
+    .m_axis_tvalid(s3.axis.tvalid),
+    .m_axis_tready(s3.axis.tready)
+  );
+
+  // A passthrough module (no up/down sizing) but with 8 words per cycle
+  axis_width_conv #(
+    .WORD_W(WORD_W), .IN_WORDS(IN_WORDS[4]), .OUT_WORDS(OUT_WORDS[4]),
+    .SYNC_CLKS(0), .PIPELINE("INOUT")
+  ) dut4 (
+    .s_axis_aclk  (clk50),
+    .s_axis_rst   (areset),
+    .s_axis_tdata (m4.axis.tdata[(IN_WORDS[4]*WORD_W)-1:0]), 
+    .s_axis_tkeep (m4.axis.tdata[IN_WORDS[4]*WORD_W+:IN_WORDS[4]]),
+    .s_axis_tlast (m4.axis.tlast),
+    .s_axis_tvalid(m4.axis.tvalid),
+    .s_axis_tready(m4.axis.tready),
+    .m_axis_aclk  (clk166),
+    .m_axis_rst   (areset),
+    .m_axis_tdata (s4.axis.tdata[(OUT_WORDS[4]*WORD_W)-1:0]),
+    .m_axis_tkeep (s4.axis.tdata[OUT_WORDS[4]*WORD_W+:OUT_WORDS[4]]),
+    .m_axis_tlast (s4.axis.tlast),
+    .m_axis_tvalid(s4.axis.tvalid),
+    .m_axis_tready(s4.axis.tready)
+  );
+
+  // A rational integer 17-to-19 upsizer
+  axis_width_conv #(
+    .WORD_W(WORD_W), .IN_WORDS(IN_WORDS[5]), .OUT_WORDS(OUT_WORDS[5]),
+    .SYNC_CLKS(1), .PIPELINE("INOUT")
+  ) dut5 (
+    .s_axis_aclk  (clk50),
+    .s_axis_rst   (areset),
+    .s_axis_tdata (m5.axis.tdata[(IN_WORDS[5]*WORD_W)-1:0]), 
+    .s_axis_tkeep (m5.axis.tdata[IN_WORDS[5]*WORD_W+:IN_WORDS[5]]),
+    .s_axis_tlast (m5.axis.tlast),
+    .s_axis_tvalid(m5.axis.tvalid),
+    .s_axis_tready(m5.axis.tready),
+    .m_axis_aclk  (clk50),
+    .m_axis_rst   (areset),
+    .m_axis_tdata (s5.axis.tdata[(OUT_WORDS[5]*WORD_W)-1:0]),
+    .m_axis_tkeep (s5.axis.tdata[OUT_WORDS[5]*WORD_W+:OUT_WORDS[5]]),
+    .m_axis_tlast (s5.axis.tlast),
+    .m_axis_tvalid(s5.axis.tvalid),
+    .m_axis_tready(s5.axis.tready)
+  );
+
+  // Push a test ramp packet into the specific instance of the module
+  // - words: The size of the packet in words
+  // - inst: The instance number of the module to send to
+  // - gaps: If 1 then insert bubble cycles randomly in the stream
+  task push_test_pkt(input integer words, input integer inst, input logic gaps);
+    begin
+      logic [(MAX_IN_WORDS*WORD_W)-1:0] data = 0;
+      logic [MAX_IN_WORDS-1:0]          keep = 0;
+      logic                             last = 0;
+      integer nspc = IN_WORDS[inst];
+      integer lines = words/nspc;
+      integer residue = words % nspc;
+      if (residue != 0) begin
+        lines = lines + 1;
+      end
+      for (int l = 0; l < lines; l=l+1) begin
+        last = (l == lines-1);
+        for (int p = 0; p < nspc; p=p+1) begin
+          data[p*WORD_W+:WORD_W] = (l*nspc)+p;
+        end
+        keep = (last && (residue != 0)) ? (1<<residue)-1 : (1<<nspc)-1;
+        if (inst == 0)
+          m0.push_word({keep[IN_WORDS[0]-1:0], data[(IN_WORDS[0]*WORD_W)-1:0]}, last);
+        else if (inst == 1)
+          m1.push_word({keep[IN_WORDS[1]-1:0], data[(IN_WORDS[1]*WORD_W)-1:0]}, last);
+        else if (inst == 2)
+          m2.push_word({keep[IN_WORDS[2]-1:0], data[(IN_WORDS[2]*WORD_W)-1:0]}, last);
+        else if (inst == 3)
+          m3.push_word({keep[IN_WORDS[3]-1:0], data[(IN_WORDS[3]*WORD_W)-1:0]}, last);
+        else if (inst == 4)
+          m4.push_word({keep[IN_WORDS[4]-1:0], data[(IN_WORDS[4]*WORD_W)-1:0]}, last);
+        else
+          m5.push_word({keep[IN_WORDS[5]-1:0], data[(IN_WORDS[5]*WORD_W)-1:0]}, last);
+
+        // Keep tvalid deasserted randomly introduce gaps
+        if (gaps) begin
+          integer r = $urandom_range(0, 100);
+          if (r < 20) repeat(r) @(posedge clk50);
+        end
+//        $display("PUSH(%02d)[%03d]: D{%0x}, K{%0b}, L{%0b}", inst, l, data, keep, last);
+      end
+    end
+  endtask
+
+  // Pull a test ramp packet from the specific instance of the module
+  // - words: The size of the packet in words
+  // - inst: The instance number of the module to send to
+  // - gaps: If 1 then insert bubble cycles randomly in the stream
+  // - ok: If 1 then all sanity checks have passed
+  task pull_test_pkt(input integer words, input integer inst, input logic gaps, output logic ok);
+    begin
+      logic [(MAX_OUT_WORDS*WORD_W)-1:0] pull_data = 0;
+      logic [MAX_OUT_WORDS-1:0]          pull_keep = 0;
+      logic                              pull_last = 0;
+
+      logic [(MAX_OUT_WORDS*WORD_W)-1:0] data = 0;
+      logic [MAX_OUT_WORDS-1:0]          keep = 0;
+      logic                              last = 0;
+      logic [(MAX_OUT_WORDS*WORD_W)-1:0] mask = 0;
+      integer nspc = OUT_WORDS[inst];
+      integer lines = words/nspc;
+      integer residue = words % nspc;
+      if (residue != 0) begin
+        lines = lines + 1;
+      end
+      for (int l = 0; l < lines; l=l+1) begin
+        last = (l == lines-1);
+        for (int p = 0; p < nspc; p=p+1) begin
+          data[p*WORD_W+:WORD_W] = (l*nspc)+p;
+        end
+        keep = (last && (residue != 0)) ? (1<<residue)-1 : (1<<nspc)-1;
+        mask = (last && (residue != 0)) ? (1<<(residue*WORD_W))-1 : (1<<(nspc*WORD_W))-1;
+        if (inst == 0)
+          s0.pull_word({pull_keep[OUT_WORDS[0]-1:0], pull_data[(OUT_WORDS[0]*WORD_W)-1:0]}, pull_last);
+        else if (inst == 1)
+          s1.pull_word({pull_keep[OUT_WORDS[1]-1:0], pull_data[(OUT_WORDS[1]*WORD_W)-1:0]}, pull_last);
+        else if (inst == 2)
+          s2.pull_word({pull_keep[OUT_WORDS[2]-1:0], pull_data[(OUT_WORDS[2]*WORD_W)-1:0]}, pull_last);
+        else if (inst == 3)
+          s3.pull_word({pull_keep[OUT_WORDS[3]-1:0], pull_data[(OUT_WORDS[3]*WORD_W)-1:0]}, pull_last);
+        else if (inst == 4)
+          s4.pull_word({pull_keep[OUT_WORDS[4]-1:0], pull_data[(OUT_WORDS[4]*WORD_W)-1:0]}, pull_last);
+        else
+          s5.pull_word({pull_keep[OUT_WORDS[5]-1:0], pull_data[(OUT_WORDS[5]*WORD_W)-1:0]}, pull_last);
+
+        // Keep tready deasserted randomly introduce gaps
+        if (gaps) begin
+          integer r = $urandom_range(0, 100);
+          if (r < 20) repeat(r) @(posedge clk50);
+        end
+        // Check data, keep and last
+        ok = ((data&mask) == (pull_data&mask)) && (keep == (pull_keep&((1<<nspc)-1))) && (last == pull_last);
+//        $display("PULL(%02d)[%03d]: D{%0x =? %0x}, K{%0b =? %0b}, L{%0b =? %0b} ... %s",
+//          inst, l, (data&mask), (pull_data&mask), keep, (pull_keep&((1<<nspc)-1)), last, pull_last, (ok?"OK":"FAIL"));
+      end
+    end
+  endtask
+
+  initial begin : tb_main
+    string s;
+
+    `TEST_CASE_START("Wait for Reset");
+      m0.reset();
+      m1.reset();
+      m2.reset();
+      m3.reset();
+      m4.reset();
+      m5.reset();
+      s0.reset();
+      s1.reset();
+      s2.reset();
+      s3.reset();
+      s4.reset();
+      s5.reset();
+      while (areset) @(posedge clk50);
+    `TEST_CASE_DONE(~areset);
+
+    // Iterate through two modes:
+    // - g == 0: Gapless send and receive. Transfer as fast as possible
+    // - g == 1: Sender and receiver AXI streams will have random bubbles
+    for (int g = 0; g < 2; g=g+1) begin
+      // Iterate through the various instances of the module
+      for (int i = 0; i < NINST; i=i+1) begin
+        $sformat(s, "Testing Instance %0d (%0s gaps)", i, (g==0?"without":"with"));
+        `TEST_CASE_START(s);
+          fork
+            begin
+              // Send packets of increasing size (up to MAX_SPP) to test all
+              // configurations of tkeep and tlast.
+              for (int n = 1; n <= MAX_SPP; n=n+1) begin
+                push_test_pkt(n, i, g);
+              end
+            end
+            begin
+              logic ok;
+              // Receive packets of increasing size and validate tlast, tkeep and tdata
+              for (int n = 1; n <= MAX_SPP; n=n+1) begin
+                pull_test_pkt(n, i, g, ok);
+                $sformat(s, "Packet Validation Failed! (Size=%0d)", n);
+                `ASSERT_ERROR(ok, s);
+              end
+            end
+          join
+          // Gaps to separate the tests in the wfm viewer
+          repeat (100) @(posedge clk50);
+        `TEST_CASE_DONE(1'b1);
+      end
+    end
+
+    `TEST_BENCH_DONE;
+  end
+endmodule
diff --git a/fpga/usrp3/lib/sim/axi_packet_gate/Makefile b/fpga/usrp3/lib/sim/axi_packet_gate/Makefile
new file mode 100644
index 000000000..625a02877
--- /dev/null
+++ b/fpga/usrp3/lib/sim/axi_packet_gate/Makefile
@@ -0,0 +1,46 @@
+#
+# Copyright 2016 Ettus Research
+#
+
+#-------------------------------------------------
+# Top-of-Makefile
+#-------------------------------------------------
+# Define BASE_DIR to point to the "top" dir
+BASE_DIR = $(abspath ../../../top)
+# Include viv_sim_preamble after defining BASE_DIR
+include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
+
+#-------------------------------------------------
+# Design Specific
+#-------------------------------------------------
+# Include makefiles and sources for the DUT and its dependencies
+include $(BASE_DIR)/../lib/control/Makefile.srcs
+include $(BASE_DIR)/../lib/fifo/Makefile.srcs
+
+DESIGN_SRCS = $(abspath \
+$(CONTROL_LIB_SRCS) \
+$(FIFO_SRCS) \
+$(LIB_DIR)/fifo/axi_packet_gate.v \
+)
+
+#-------------------------------------------------
+# Testbench Specific
+#-------------------------------------------------
+# Define only one toplevel module
+SIM_TOP = axi_packet_gate_tb
+
+# Add test bench, user design under test, and
+# additional user created files
+SIM_SRCS = $(abspath \
+axi_packet_gate_tb.sv \
+)
+
+# MODELSIM_USER_DO = $(abspath wave.do)
+
+#-------------------------------------------------
+# Bottom-of-Makefile
+#-------------------------------------------------
+# Include all simulator specific makefiles here
+# Each should define a unique target to simulate
+# e.g. xsim, vsim, etc and a common "clean" target
+include $(BASE_DIR)/../tools/make/viv_simulator.mak
diff --git a/fpga/usrp3/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv b/fpga/usrp3/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv
new file mode 100644
index 000000000..0463a1e28
--- /dev/null
+++ b/fpga/usrp3/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv
@@ -0,0 +1,347 @@
+`timescale 1ns/1ps
+`define NS_PER_TICK 1
+`define NUM_TEST_CASES 7
+
+`include "sim_exec_report.vh"
+`include "sim_clks_rsts.vh"
+`include "sim_axis_lib.svh"
+
+module axi_packet_gate_tb();
+  `TEST_BENCH_INIT("axi_packet_gate_tb", `NUM_TEST_CASES, `NS_PER_TICK);
+  localparam CLK_PERIOD = $ceil(1e9/166.67e6);
+  `DEFINE_CLK(clk, CLK_PERIOD, 50);
+  `DEFINE_RESET(reset, 0, 100);
+
+  localparam MAX_PKT_SIZE = 64;
+
+  // +1 for terror
+  axis_master #(.DWIDTH(32+1)) m_axis (.clk(clk));
+  axis_slave #(.DWIDTH(32)) s_axis (.clk(clk));
+
+  axi_packet_gate #(
+    .WIDTH(32),
+    .SIZE($clog2(MAX_PKT_SIZE)),
+    .USE_AS_BUFF(1)
+  ) dut (
+    .clk(clk), .reset(reset), .clear(1'b0),
+    .i_tdata(m_axis.axis.tdata[31:0]),
+    .i_tvalid(m_axis.axis.tvalid),
+    .i_tlast(m_axis.axis.tlast),
+    .i_terror(m_axis.axis.tdata[32]), // Use MSB as terror
+    .i_tready(m_axis.axis.tready),
+    .o_tdata(s_axis.axis.tdata),
+    .o_tvalid(s_axis.axis.tvalid),
+    .o_tlast(s_axis.axis.tlast),
+    .o_tready(s_axis.axis.tready)
+  );
+
+  /********************************************************
+  ** Verification
+  ********************************************************/
+  task random_wait(int unsigned min_cycles, int unsigned max_cycles);
+    begin
+      int unsigned num_cycles;
+      do begin
+        num_cycles = $random() & (2**($clog2(max_cycles))-1);
+      end while ((num_cycles < min_cycles) || (num_cycles > max_cycles));
+
+      if (num_cycles != 0) begin
+        for (int unsigned i = 0; i < num_cycles; i++) begin
+          @(posedge clk);
+        end
+        @(negedge clk); // Realign with negedge
+      end
+    end
+  endtask
+
+  initial begin : tb_main
+    string s;
+    logic error, last;
+    int cnt, check;
+
+    /********************************************************
+    ** Test 1 -- Reset
+    ********************************************************/
+    `TEST_CASE_START("Wait for Reset");
+    m_axis.reset();
+    s_axis.reset();
+    while (reset) @(posedge clk);
+    `TEST_CASE_DONE(~reset);
+
+    /********************************************************
+    ** Test 2 -- Fill / Empty FIFO
+    ********************************************************/
+    `TEST_CASE_START("Fill and empty FIFO");
+    error = 0;
+    last = 0;
+    cnt = 0;
+    $display("Write %0d words to FIFO", MAX_PKT_SIZE);
+    for (int i = 0; i < MAX_PKT_SIZE; i++) begin
+      $sformat(s, "FIFO prematurely full at %0d (tready not asserted!)", i);
+      `ASSERT_FATAL(m_axis.axis.tready, s);
+      m_axis.push_word({error,cnt}, i == MAX_PKT_SIZE-1);
+      cnt++;
+    end
+    $display("Done writing to FIFO");
+    if (m_axis.axis.tready) begin
+      $display("FIFO not full, fill remaining space");
+      // Continue filling until FIFO is full
+      while (m_axis.axis.tready) begin
+        m_axis.push_word({error,cnt}, 0);
+        cnt++;
+      end
+      $display("Done filling remaining space");
+      $display("Expected FIFO size: %0d, Actual: %0d",MAX_PKT_SIZE,cnt);
+    end
+    // On the first packet, output is held off until a full packet is received
+    repeat(MAX_PKT_SIZE) @(posedge clk);
+    $display("Empty FIFO and check output");
+    for (int i = 0; i < cnt; i++) begin
+      $sformat(s, "FIFO prematurely empty at %0d (tvalid not asserted!)", i);
+      `ASSERT_FATAL(s_axis.axis.tvalid, s);
+      s_axis.pull_word(check, last);
+      $sformat(s, "FIFO output incorrect! Expected: %0d, Actual: %0d", i, check);
+      `ASSERT_FATAL(check == i, s);
+      if (i == cnt-1) begin
+        `ASSERT_FATAL(last, "tlast not asserted on final word!");
+      end else begin
+        `ASSERT_FATAL(~last, "tlast asserted prematurely!");
+      end
+    end
+    `TEST_CASE_DONE(1);
+
+    /********************************************************
+    ** Test 3 -- Check gating
+    ********************************************************/
+    `TEST_CASE_START("Check gating");
+    error = 0;
+    last = 0;
+    cnt = 0;
+
+    $display("Write %0d words to FIFO and check out valid", MAX_PKT_SIZE);
+    for (int i = 0; i < MAX_PKT_SIZE/2; i++) begin
+      m_axis.push_word({error,cnt}, 0);
+      cnt++;
+    end
+    // On the first packet, output is held off until a full packet is received
+    repeat(10) @(posedge clk);
+    `ASSERT_FATAL(~s_axis.axis.tvalid, "Saw output before a full packet input");
+    for (int i = MAX_PKT_SIZE/2; i < MAX_PKT_SIZE; i++) begin
+      m_axis.push_word({error,cnt}, i == MAX_PKT_SIZE-1);
+      cnt++;
+    end
+    repeat(10) @(posedge clk);
+    `ASSERT_FATAL(s_axis.axis.tvalid, "Did not see output even after full packet input");
+    $display("Empty FIFO and check output");
+    for (int i = 0; i < cnt; i++) begin
+      $sformat(s, "FIFO prematurely empty at %0d (tvalid not asserted!)", i);
+      `ASSERT_FATAL(s_axis.axis.tvalid, s);
+      s_axis.pull_word(check, last);
+      $sformat(s, "FIFO output incorrect! Expected: %0d, Actual: %0d", i, check);
+      `ASSERT_FATAL(check == i, s);
+      if (i == cnt-1) begin
+        `ASSERT_FATAL(last, "tlast not asserted on final word!");
+      end else begin
+        `ASSERT_FATAL(~last, "tlast asserted prematurely!");
+      end
+    end
+    `TEST_CASE_DONE(1);
+
+    /********************************************************
+    ** Test 4 -- Ensure no bleed
+    ********************************************************/
+    `TEST_CASE_START("Ensure no bleed");
+    error = 0;
+    last = 0;
+    cnt = 0;
+
+    $display("Write %0d words to FIFO (full packet)", MAX_PKT_SIZE/2);
+    for (int i = 0; i < MAX_PKT_SIZE/2; i++) begin
+      m_axis.push_word({error,cnt}, i == (MAX_PKT_SIZE/2)-1);
+      cnt++;
+    end
+    $display("Write %0d words to FIFO (partial packet)", MAX_PKT_SIZE/4);
+    for (int i = 0; i < MAX_PKT_SIZE/4; i++) begin
+      m_axis.push_word({error,cnt}, 0);
+      cnt++;
+    end
+    // On the first packet, output is held off until a full packet is received
+    repeat(10) @(posedge clk);
+    for (int i = 0; i < MAX_PKT_SIZE/2; i++) begin
+      $sformat(s, "FIFO prematurely empty at %0d (tvalid not asserted!)", i);
+      `ASSERT_FATAL(s_axis.axis.tvalid, s);
+      s_axis.pull_word(check, last);
+      $sformat(s, "FIFO output incorrect! Expected: %0d, Actual: %0d", i, check);
+      `ASSERT_FATAL(check == i, s);
+      if (i == (MAX_PKT_SIZE/2)-1) begin
+        `ASSERT_FATAL(last, "tlast not asserted on final word!");
+      end else begin
+        `ASSERT_FATAL(~last, "tlast asserted prematurely!");
+      end
+    end
+    repeat(10) @(posedge clk);
+    `ASSERT_FATAL(~s_axis.axis.tvalid, "Partial packet bled through with full packet");
+    for (int i = MAX_PKT_SIZE/4; i < MAX_PKT_SIZE/2; i++) begin
+      m_axis.push_word({error,cnt}, i == (MAX_PKT_SIZE/2)-1);
+      cnt++;
+    end
+    repeat(10) @(posedge clk);
+    `ASSERT_FATAL(s_axis.axis.tvalid, "Did not see output even after full packet input");
+    $display("Empty FIFO and check output");
+    for (int i = MAX_PKT_SIZE/2; i < cnt; i++) begin
+      $sformat(s, "FIFO prematurely empty at %0d (tvalid not asserted!)", i);
+      `ASSERT_FATAL(s_axis.axis.tvalid, s);
+      s_axis.pull_word(check, last);
+      $sformat(s, "FIFO output incorrect! Expected: %0d, Actual: %0d", i, check);
+      `ASSERT_FATAL(check == i, s);
+      if (i == cnt-1) begin
+        `ASSERT_FATAL(last, "tlast not asserted on final word!");
+      end else begin
+        `ASSERT_FATAL(~last, "tlast asserted prematurely!");
+      end
+    end
+    `TEST_CASE_DONE(1);
+
+    /********************************************************
+    ** Test 5 -- Back to back small packets
+    ********************************************************/
+    `TEST_CASE_START("Back to back small packets");
+    error = 0;
+    last = 0;
+    cnt = 0;
+    for (int i = 0; i < MAX_PKT_SIZE/2; i++) begin
+      $sformat(s, "FIFO prematurely full at %0d (tready not asserted!)", i);
+      `ASSERT_FATAL(m_axis.axis.tready, s);
+      m_axis.push_word({error,cnt}, i == MAX_PKT_SIZE/2-1);
+      cnt++;
+    end
+    for (int i = 0; i < MAX_PKT_SIZE/2; i++) begin
+      $sformat(s, "FIFO prematurely full at %0d (tready not asserted!)", i);
+      `ASSERT_FATAL(m_axis.axis.tready, s);
+      m_axis.push_word({error,cnt}, i == MAX_PKT_SIZE/2-1);
+      cnt++;
+    end
+    fork
+    begin
+      for (int k = 0; k < 8; k++) begin
+        for (int i = 0; i < MAX_PKT_SIZE/2; i++) begin
+          m_axis.push_word({error,cnt}, i == MAX_PKT_SIZE/2-1);
+          cnt++;
+        end
+      end
+    end
+    begin
+      @(posedge clk);
+      @(posedge clk);
+      @(posedge clk);
+      for (int k = 0; k < 10; k++) begin
+        for (int i = 0; i < MAX_PKT_SIZE/2; i++) begin
+          `ASSERT_FATAL(s_axis.axis.tvalid, "tvalid not asserted!");
+          s_axis.pull_word(check, last);
+          $sformat(s, "FIFO output incorrect! Expected: %0d, Actual: %0d", i, check);
+          `ASSERT_FATAL(check == (i+k*MAX_PKT_SIZE/2), s);
+          if (i == MAX_PKT_SIZE/2-1) begin
+            `ASSERT_FATAL(last, "tlast not asserted on final word!");
+          end else begin
+            `ASSERT_FATAL(~last, "tlast asserted prematurely!");
+          end
+        end
+      end
+    end
+    join
+    `TEST_CASE_DONE(1);
+
+    #2000; // Delay to make the tests visually distinct in waveform viewer
+
+    /********************************************************
+    ** Test 6 -- Drop error packet
+    ** - Send packet, drop a packet, send another packet
+    ********************************************************/
+    `TEST_CASE_START("Drop error packet");
+    cnt = 0;
+    $display("Write packet with %0d words to FIFO", MAX_PKT_SIZE/4);
+    error = 0;
+    for (int i = 0; i < MAX_PKT_SIZE/4; i++) begin
+      $sformat(s, "FIFO prematurely full at %0d (tready not asserted!)", i);
+      `ASSERT_FATAL(m_axis.axis.tready, s);
+      m_axis.push_word({error,cnt}, i == MAX_PKT_SIZE/4-1);
+      cnt++;
+    end
+    $display("Write error packet with %0d words to FIFO", MAX_PKT_SIZE/4);
+    error = 1;
+    for (int i = 0; i < MAX_PKT_SIZE/4; i++) begin
+      $sformat(s, "FIFO prematurely full at %0d (tready not asserted!)", i);
+      `ASSERT_FATAL(m_axis.axis.tready, s);
+      m_axis.push_word({error,cnt}, i == MAX_PKT_SIZE/4-1);
+      cnt++;
+    end
+    $display("Write packet with %0d words to FIFO", MAX_PKT_SIZE/4);
+    error = 0;
+    for (int i = 0; i < MAX_PKT_SIZE/4; i++) begin
+      $sformat(s, "FIFO prematurely full at %0d (tready not asserted!)", i);
+      `ASSERT_FATAL(m_axis.axis.tready, s);
+      m_axis.push_word({error,cnt}, i == MAX_PKT_SIZE/4-1);
+      cnt++;
+    end
+    for (int i = 0; i < MAX_PKT_SIZE/4; i++) begin
+      $sformat(s, "FIFO prematurely empty at %0d (tvalid not asserted!)", i);
+      `ASSERT_FATAL(s_axis.axis.tvalid, s);
+      s_axis.pull_word(check, last);
+      $sformat(s, "FIFO output incorrect! Expected: %0d, Actual: %0d", i, check);
+      `ASSERT_FATAL(check == i, s);
+      if (i == MAX_PKT_SIZE/4-1) begin
+        `ASSERT_FATAL(last, "tlast not asserted on final word!");
+      end else begin
+        `ASSERT_FATAL(~last, "tlast asserted prematurely!");
+      end
+    end
+    for (int i = 0; i < MAX_PKT_SIZE/4; i++) begin
+      $sformat(s, "FIFO prematurely empty at %0d (tvalid not asserted!)", i);
+      `ASSERT_FATAL(s_axis.axis.tvalid, s);
+      s_axis.pull_word(check, last);
+      $sformat(s, "FIFO output incorrect! Expected: %0d, Actual: %0d", i, check);
+      `ASSERT_FATAL(check == (i+MAX_PKT_SIZE/2), s);
+      if (i == MAX_PKT_SIZE/4-1) begin
+        `ASSERT_FATAL(last, "tlast not asserted on final word!");
+      end else begin
+        `ASSERT_FATAL(~last, "tlast asserted prematurely!");
+      end
+    end
+    `TEST_CASE_DONE(1);
+
+    #2000;
+
+    /********************************************************
+    ** Test 7 -- Random read / writes
+    ********************************************************/
+    `TEST_CASE_START("Random read / writes");
+    error = 0;
+    last = 0;
+    cnt = 0;
+    fork
+    begin
+      for (int k = 1; k <= 5000*MAX_PKT_SIZE; k++) begin
+        m_axis.push_word({error,k}, (k % 16) == 0);
+        random_wait(0,16);
+      end
+    end
+    begin
+      for (int k = 1; k <= 5000*MAX_PKT_SIZE; k++) begin
+        random_wait(0,16);
+        s_axis.pull_word(check, last);
+        $sformat(s, "FIFO output incorrect! Expected: %0d, Actual: %0d", k, check);
+        `ASSERT_FATAL(check == k, s);
+        if ((k % 16) == 0) begin
+          `ASSERT_FATAL(last, "tlast not asserted!");
+        end else begin
+          `ASSERT_FATAL(~last, "tlast asserted prematurely!");
+        end
+      end
+    end
+    join
+    `TEST_CASE_DONE(1);
+
+    `TEST_BENCH_DONE;
+
+  end
+endmodule
diff --git a/fpga/usrp3/lib/sim/dsp/ddc_chain/dc_in_cordic_decim_2/gtk.conf.gtkw b/fpga/usrp3/lib/sim/dsp/ddc_chain/dc_in_cordic_decim_2/gtk.conf.gtkw
new file mode 100644
index 000000000..27c2c836e
--- /dev/null
+++ b/fpga/usrp3/lib/sim/dsp/ddc_chain/dc_in_cordic_decim_2/gtk.conf.gtkw
@@ -0,0 +1,64 @@
+[*]
+[*] GTKWave Analyzer v3.3.40 (w)1999-2012 BSI
+[*] Wed Jul 15 02:18:40 2015
+[*]
+[dumpfile] "/disk2/ianb/ettus/fpgadev-b200/fpgadev/usrp3/lib/dsp/sim/sim_ddc_chain/dc_in_cordic_run/waves.vcd"
+[dumpfile_mtime] "Wed Jul 15 02:13:19 2015"
+[dumpfile_size] 238141440
+[savefile] "/disk2/ianb/ettus/fpgadev-b200/fpgadev/usrp3/lib/dsp/sim/sim_ddc_chain/dc_in_cordic_run/gtk.conf.gtkw"
+[timestart] 0
+[size] 2488 1221
+[pos] -1 -1
+*-24.083374 129800000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] ddc_chain_tb.
+[treeopen] ddc_chain_tb.dut_i0.
+[sst_width] 331
+[signals_width] 280
+[sst_expanded] 1
+[sst_vpaned_height] 370
+@28
+ddc_chain_tb.dut_i0.clk
+ddc_chain_tb.dut_i0.rst
+ddc_chain_tb.dut_i0.set_stb
+@22
+#{ddc_chain_tb.dut_i0.set_addr[7:0]} ddc_chain_tb.dut_i0.set_addr[7] ddc_chain_tb.dut_i0.set_addr[6] ddc_chain_tb.dut_i0.set_addr[5] ddc_chain_tb.dut_i0.set_addr[4] ddc_chain_tb.dut_i0.set_addr[3] ddc_chain_tb.dut_i0.set_addr[2] ddc_chain_tb.dut_i0.set_addr[1] ddc_chain_tb.dut_i0.set_addr[0]
+#{ddc_chain_tb.dut_i0.set_data[31:0]} ddc_chain_tb.dut_i0.set_data[31] ddc_chain_tb.dut_i0.set_data[30] ddc_chain_tb.dut_i0.set_data[29] ddc_chain_tb.dut_i0.set_data[28] ddc_chain_tb.dut_i0.set_data[27] ddc_chain_tb.dut_i0.set_data[26] ddc_chain_tb.dut_i0.set_data[25] ddc_chain_tb.dut_i0.set_data[24] ddc_chain_tb.dut_i0.set_data[23] ddc_chain_tb.dut_i0.set_data[22] ddc_chain_tb.dut_i0.set_data[21] ddc_chain_tb.dut_i0.set_data[20] ddc_chain_tb.dut_i0.set_data[19] ddc_chain_tb.dut_i0.set_data[18] ddc_chain_tb.dut_i0.set_data[17] ddc_chain_tb.dut_i0.set_data[16] ddc_chain_tb.dut_i0.set_data[15] ddc_chain_tb.dut_i0.set_data[14] ddc_chain_tb.dut_i0.set_data[13] ddc_chain_tb.dut_i0.set_data[12] ddc_chain_tb.dut_i0.set_data[11] ddc_chain_tb.dut_i0.set_data[10] ddc_chain_tb.dut_i0.set_data[9] ddc_chain_tb.dut_i0.set_data[8] ddc_chain_tb.dut_i0.set_data[7] ddc_chain_tb.dut_i0.set_data[6] ddc_chain_tb.dut_i0.set_data[5] ddc_chain_tb.dut_i0.set_data[4] ddc_chain_tb.dut_i0.set_data[3] ddc_chain_tb.dut_i0.set_data[2] ddc_chain_tb.dut_i0.set_data[1] ddc_chain_tb.dut_i0.set_data[0]
+@10420
+#{ddc_chain_tb.dut_i0.rx_fe_i[23:0]} ddc_chain_tb.dut_i0.rx_fe_i[23] ddc_chain_tb.dut_i0.rx_fe_i[22] ddc_chain_tb.dut_i0.rx_fe_i[21] ddc_chain_tb.dut_i0.rx_fe_i[20] ddc_chain_tb.dut_i0.rx_fe_i[19] ddc_chain_tb.dut_i0.rx_fe_i[18] ddc_chain_tb.dut_i0.rx_fe_i[17] ddc_chain_tb.dut_i0.rx_fe_i[16] ddc_chain_tb.dut_i0.rx_fe_i[15] ddc_chain_tb.dut_i0.rx_fe_i[14] ddc_chain_tb.dut_i0.rx_fe_i[13] ddc_chain_tb.dut_i0.rx_fe_i[12] ddc_chain_tb.dut_i0.rx_fe_i[11] ddc_chain_tb.dut_i0.rx_fe_i[10] ddc_chain_tb.dut_i0.rx_fe_i[9] ddc_chain_tb.dut_i0.rx_fe_i[8] ddc_chain_tb.dut_i0.rx_fe_i[7] ddc_chain_tb.dut_i0.rx_fe_i[6] ddc_chain_tb.dut_i0.rx_fe_i[5] ddc_chain_tb.dut_i0.rx_fe_i[4] ddc_chain_tb.dut_i0.rx_fe_i[3] ddc_chain_tb.dut_i0.rx_fe_i[2] ddc_chain_tb.dut_i0.rx_fe_i[1] ddc_chain_tb.dut_i0.rx_fe_i[0]
+@20000
+-
+@10420
+#{ddc_chain_tb.dut_i0.rx_fe_q[23:0]} ddc_chain_tb.dut_i0.rx_fe_q[23] ddc_chain_tb.dut_i0.rx_fe_q[22] ddc_chain_tb.dut_i0.rx_fe_q[21] ddc_chain_tb.dut_i0.rx_fe_q[20] ddc_chain_tb.dut_i0.rx_fe_q[19] ddc_chain_tb.dut_i0.rx_fe_q[18] ddc_chain_tb.dut_i0.rx_fe_q[17] ddc_chain_tb.dut_i0.rx_fe_q[16] ddc_chain_tb.dut_i0.rx_fe_q[15] ddc_chain_tb.dut_i0.rx_fe_q[14] ddc_chain_tb.dut_i0.rx_fe_q[13] ddc_chain_tb.dut_i0.rx_fe_q[12] ddc_chain_tb.dut_i0.rx_fe_q[11] ddc_chain_tb.dut_i0.rx_fe_q[10] ddc_chain_tb.dut_i0.rx_fe_q[9] ddc_chain_tb.dut_i0.rx_fe_q[8] ddc_chain_tb.dut_i0.rx_fe_q[7] ddc_chain_tb.dut_i0.rx_fe_q[6] ddc_chain_tb.dut_i0.rx_fe_q[5] ddc_chain_tb.dut_i0.rx_fe_q[4] ddc_chain_tb.dut_i0.rx_fe_q[3] ddc_chain_tb.dut_i0.rx_fe_q[2] ddc_chain_tb.dut_i0.rx_fe_q[1] ddc_chain_tb.dut_i0.rx_fe_q[0]
+@20000
+-
+@10420
+#{ddc_chain_tb.dut_i0.i_cordic_clip[23:0]} ddc_chain_tb.dut_i0.i_cordic_clip[23] ddc_chain_tb.dut_i0.i_cordic_clip[22] ddc_chain_tb.dut_i0.i_cordic_clip[21] ddc_chain_tb.dut_i0.i_cordic_clip[20] ddc_chain_tb.dut_i0.i_cordic_clip[19] ddc_chain_tb.dut_i0.i_cordic_clip[18] ddc_chain_tb.dut_i0.i_cordic_clip[17] ddc_chain_tb.dut_i0.i_cordic_clip[16] ddc_chain_tb.dut_i0.i_cordic_clip[15] ddc_chain_tb.dut_i0.i_cordic_clip[14] ddc_chain_tb.dut_i0.i_cordic_clip[13] ddc_chain_tb.dut_i0.i_cordic_clip[12] ddc_chain_tb.dut_i0.i_cordic_clip[11] ddc_chain_tb.dut_i0.i_cordic_clip[10] ddc_chain_tb.dut_i0.i_cordic_clip[9] ddc_chain_tb.dut_i0.i_cordic_clip[8] ddc_chain_tb.dut_i0.i_cordic_clip[7] ddc_chain_tb.dut_i0.i_cordic_clip[6] ddc_chain_tb.dut_i0.i_cordic_clip[5] ddc_chain_tb.dut_i0.i_cordic_clip[4] ddc_chain_tb.dut_i0.i_cordic_clip[3] ddc_chain_tb.dut_i0.i_cordic_clip[2] ddc_chain_tb.dut_i0.i_cordic_clip[1] ddc_chain_tb.dut_i0.i_cordic_clip[0]
+@20000
+-
+@10420
+#{ddc_chain_tb.dut_i0.q_cordic_clip[23:0]} ddc_chain_tb.dut_i0.q_cordic_clip[23] ddc_chain_tb.dut_i0.q_cordic_clip[22] ddc_chain_tb.dut_i0.q_cordic_clip[21] ddc_chain_tb.dut_i0.q_cordic_clip[20] ddc_chain_tb.dut_i0.q_cordic_clip[19] ddc_chain_tb.dut_i0.q_cordic_clip[18] ddc_chain_tb.dut_i0.q_cordic_clip[17] ddc_chain_tb.dut_i0.q_cordic_clip[16] ddc_chain_tb.dut_i0.q_cordic_clip[15] ddc_chain_tb.dut_i0.q_cordic_clip[14] ddc_chain_tb.dut_i0.q_cordic_clip[13] ddc_chain_tb.dut_i0.q_cordic_clip[12] ddc_chain_tb.dut_i0.q_cordic_clip[11] ddc_chain_tb.dut_i0.q_cordic_clip[10] ddc_chain_tb.dut_i0.q_cordic_clip[9] ddc_chain_tb.dut_i0.q_cordic_clip[8] ddc_chain_tb.dut_i0.q_cordic_clip[7] ddc_chain_tb.dut_i0.q_cordic_clip[6] ddc_chain_tb.dut_i0.q_cordic_clip[5] ddc_chain_tb.dut_i0.q_cordic_clip[4] ddc_chain_tb.dut_i0.q_cordic_clip[3] ddc_chain_tb.dut_i0.q_cordic_clip[2] ddc_chain_tb.dut_i0.q_cordic_clip[1] ddc_chain_tb.dut_i0.q_cordic_clip[0]
+@20000
+-
+@10420
+#{ddc_chain_tb.dut_i0.i_cic[23:0]} ddc_chain_tb.dut_i0.i_cic[23] ddc_chain_tb.dut_i0.i_cic[22] ddc_chain_tb.dut_i0.i_cic[21] ddc_chain_tb.dut_i0.i_cic[20] ddc_chain_tb.dut_i0.i_cic[19] ddc_chain_tb.dut_i0.i_cic[18] ddc_chain_tb.dut_i0.i_cic[17] ddc_chain_tb.dut_i0.i_cic[16] ddc_chain_tb.dut_i0.i_cic[15] ddc_chain_tb.dut_i0.i_cic[14] ddc_chain_tb.dut_i0.i_cic[13] ddc_chain_tb.dut_i0.i_cic[12] ddc_chain_tb.dut_i0.i_cic[11] ddc_chain_tb.dut_i0.i_cic[10] ddc_chain_tb.dut_i0.i_cic[9] ddc_chain_tb.dut_i0.i_cic[8] ddc_chain_tb.dut_i0.i_cic[7] ddc_chain_tb.dut_i0.i_cic[6] ddc_chain_tb.dut_i0.i_cic[5] ddc_chain_tb.dut_i0.i_cic[4] ddc_chain_tb.dut_i0.i_cic[3] ddc_chain_tb.dut_i0.i_cic[2] ddc_chain_tb.dut_i0.i_cic[1] ddc_chain_tb.dut_i0.i_cic[0]
+@20000
+-
+@10420
+#{ddc_chain_tb.dut_i0.q_cic[23:0]} ddc_chain_tb.dut_i0.q_cic[23] ddc_chain_tb.dut_i0.q_cic[22] ddc_chain_tb.dut_i0.q_cic[21] ddc_chain_tb.dut_i0.q_cic[20] ddc_chain_tb.dut_i0.q_cic[19] ddc_chain_tb.dut_i0.q_cic[18] ddc_chain_tb.dut_i0.q_cic[17] ddc_chain_tb.dut_i0.q_cic[16] ddc_chain_tb.dut_i0.q_cic[15] ddc_chain_tb.dut_i0.q_cic[14] ddc_chain_tb.dut_i0.q_cic[13] ddc_chain_tb.dut_i0.q_cic[12] ddc_chain_tb.dut_i0.q_cic[11] ddc_chain_tb.dut_i0.q_cic[10] ddc_chain_tb.dut_i0.q_cic[9] ddc_chain_tb.dut_i0.q_cic[8] ddc_chain_tb.dut_i0.q_cic[7] ddc_chain_tb.dut_i0.q_cic[6] ddc_chain_tb.dut_i0.q_cic[5] ddc_chain_tb.dut_i0.q_cic[4] ddc_chain_tb.dut_i0.q_cic[3] ddc_chain_tb.dut_i0.q_cic[2] ddc_chain_tb.dut_i0.q_cic[1] ddc_chain_tb.dut_i0.q_cic[0]
+@20000
+-
+@10420
+#{ddc_chain_tb.dut_i0.\new_hb.i_hb1[46:0]} ddc_chain_tb.dut_i0.\new_hb.i_hb1[46] ddc_chain_tb.dut_i0.\new_hb.i_hb1[45] ddc_chain_tb.dut_i0.\new_hb.i_hb1[44] ddc_chain_tb.dut_i0.\new_hb.i_hb1[43] ddc_chain_tb.dut_i0.\new_hb.i_hb1[42] ddc_chain_tb.dut_i0.\new_hb.i_hb1[41] ddc_chain_tb.dut_i0.\new_hb.i_hb1[40] ddc_chain_tb.dut_i0.\new_hb.i_hb1[39] ddc_chain_tb.dut_i0.\new_hb.i_hb1[38] ddc_chain_tb.dut_i0.\new_hb.i_hb1[37] ddc_chain_tb.dut_i0.\new_hb.i_hb1[36] ddc_chain_tb.dut_i0.\new_hb.i_hb1[35] ddc_chain_tb.dut_i0.\new_hb.i_hb1[34] ddc_chain_tb.dut_i0.\new_hb.i_hb1[33] ddc_chain_tb.dut_i0.\new_hb.i_hb1[32] ddc_chain_tb.dut_i0.\new_hb.i_hb1[31] ddc_chain_tb.dut_i0.\new_hb.i_hb1[30] ddc_chain_tb.dut_i0.\new_hb.i_hb1[29] ddc_chain_tb.dut_i0.\new_hb.i_hb1[28] ddc_chain_tb.dut_i0.\new_hb.i_hb1[27] ddc_chain_tb.dut_i0.\new_hb.i_hb1[26] ddc_chain_tb.dut_i0.\new_hb.i_hb1[25] ddc_chain_tb.dut_i0.\new_hb.i_hb1[24] ddc_chain_tb.dut_i0.\new_hb.i_hb1[23] ddc_chain_tb.dut_i0.\new_hb.i_hb1[22] ddc_chain_tb.dut_i0.\new_hb.i_hb1[21] ddc_chain_tb.dut_i0.\new_hb.i_hb1[20] ddc_chain_tb.dut_i0.\new_hb.i_hb1[19] ddc_chain_tb.dut_i0.\new_hb.i_hb1[18] ddc_chain_tb.dut_i0.\new_hb.i_hb1[17] ddc_chain_tb.dut_i0.\new_hb.i_hb1[16] ddc_chain_tb.dut_i0.\new_hb.i_hb1[15] ddc_chain_tb.dut_i0.\new_hb.i_hb1[14] ddc_chain_tb.dut_i0.\new_hb.i_hb1[13] ddc_chain_tb.dut_i0.\new_hb.i_hb1[12] ddc_chain_tb.dut_i0.\new_hb.i_hb1[11] ddc_chain_tb.dut_i0.\new_hb.i_hb1[10] ddc_chain_tb.dut_i0.\new_hb.i_hb1[9] ddc_chain_tb.dut_i0.\new_hb.i_hb1[8] ddc_chain_tb.dut_i0.\new_hb.i_hb1[7] ddc_chain_tb.dut_i0.\new_hb.i_hb1[6] ddc_chain_tb.dut_i0.\new_hb.i_hb1[5] ddc_chain_tb.dut_i0.\new_hb.i_hb1[4] ddc_chain_tb.dut_i0.\new_hb.i_hb1[3] ddc_chain_tb.dut_i0.\new_hb.i_hb1[2] ddc_chain_tb.dut_i0.\new_hb.i_hb1[1] ddc_chain_tb.dut_i0.\new_hb.i_hb1[0]
+@20000
+-
+@10420
+#{ddc_chain_tb.dut_i0.\new_hb.q_hb1[46:0]} ddc_chain_tb.dut_i0.\new_hb.q_hb1[46] ddc_chain_tb.dut_i0.\new_hb.q_hb1[45] ddc_chain_tb.dut_i0.\new_hb.q_hb1[44] ddc_chain_tb.dut_i0.\new_hb.q_hb1[43] ddc_chain_tb.dut_i0.\new_hb.q_hb1[42] ddc_chain_tb.dut_i0.\new_hb.q_hb1[41] ddc_chain_tb.dut_i0.\new_hb.q_hb1[40] ddc_chain_tb.dut_i0.\new_hb.q_hb1[39] ddc_chain_tb.dut_i0.\new_hb.q_hb1[38] ddc_chain_tb.dut_i0.\new_hb.q_hb1[37] ddc_chain_tb.dut_i0.\new_hb.q_hb1[36] ddc_chain_tb.dut_i0.\new_hb.q_hb1[35] ddc_chain_tb.dut_i0.\new_hb.q_hb1[34] ddc_chain_tb.dut_i0.\new_hb.q_hb1[33] ddc_chain_tb.dut_i0.\new_hb.q_hb1[32] ddc_chain_tb.dut_i0.\new_hb.q_hb1[31] ddc_chain_tb.dut_i0.\new_hb.q_hb1[30] ddc_chain_tb.dut_i0.\new_hb.q_hb1[29] ddc_chain_tb.dut_i0.\new_hb.q_hb1[28] ddc_chain_tb.dut_i0.\new_hb.q_hb1[27] ddc_chain_tb.dut_i0.\new_hb.q_hb1[26] ddc_chain_tb.dut_i0.\new_hb.q_hb1[25] ddc_chain_tb.dut_i0.\new_hb.q_hb1[24] ddc_chain_tb.dut_i0.\new_hb.q_hb1[23] ddc_chain_tb.dut_i0.\new_hb.q_hb1[22] ddc_chain_tb.dut_i0.\new_hb.q_hb1[21] ddc_chain_tb.dut_i0.\new_hb.q_hb1[20] ddc_chain_tb.dut_i0.\new_hb.q_hb1[19] ddc_chain_tb.dut_i0.\new_hb.q_hb1[18] ddc_chain_tb.dut_i0.\new_hb.q_hb1[17] ddc_chain_tb.dut_i0.\new_hb.q_hb1[16] ddc_chain_tb.dut_i0.\new_hb.q_hb1[15] ddc_chain_tb.dut_i0.\new_hb.q_hb1[14] ddc_chain_tb.dut_i0.\new_hb.q_hb1[13] ddc_chain_tb.dut_i0.\new_hb.q_hb1[12] ddc_chain_tb.dut_i0.\new_hb.q_hb1[11] ddc_chain_tb.dut_i0.\new_hb.q_hb1[10] ddc_chain_tb.dut_i0.\new_hb.q_hb1[9] ddc_chain_tb.dut_i0.\new_hb.q_hb1[8] ddc_chain_tb.dut_i0.\new_hb.q_hb1[7] ddc_chain_tb.dut_i0.\new_hb.q_hb1[6] ddc_chain_tb.dut_i0.\new_hb.q_hb1[5] ddc_chain_tb.dut_i0.\new_hb.q_hb1[4] ddc_chain_tb.dut_i0.\new_hb.q_hb1[3] ddc_chain_tb.dut_i0.\new_hb.q_hb1[2] ddc_chain_tb.dut_i0.\new_hb.q_hb1[1] ddc_chain_tb.dut_i0.\new_hb.q_hb1[0]
+@20000
+-
+@10420
+#{ddc_chain_tb.dut_i0.\new_hb.i_hb2[46:0]} ddc_chain_tb.dut_i0.\new_hb.i_hb2[46] ddc_chain_tb.dut_i0.\new_hb.i_hb2[45] ddc_chain_tb.dut_i0.\new_hb.i_hb2[44] ddc_chain_tb.dut_i0.\new_hb.i_hb2[43] ddc_chain_tb.dut_i0.\new_hb.i_hb2[42] ddc_chain_tb.dut_i0.\new_hb.i_hb2[41] ddc_chain_tb.dut_i0.\new_hb.i_hb2[40] ddc_chain_tb.dut_i0.\new_hb.i_hb2[39] ddc_chain_tb.dut_i0.\new_hb.i_hb2[38] ddc_chain_tb.dut_i0.\new_hb.i_hb2[37] ddc_chain_tb.dut_i0.\new_hb.i_hb2[36] ddc_chain_tb.dut_i0.\new_hb.i_hb2[35] ddc_chain_tb.dut_i0.\new_hb.i_hb2[34] ddc_chain_tb.dut_i0.\new_hb.i_hb2[33] ddc_chain_tb.dut_i0.\new_hb.i_hb2[32] ddc_chain_tb.dut_i0.\new_hb.i_hb2[31] ddc_chain_tb.dut_i0.\new_hb.i_hb2[30] ddc_chain_tb.dut_i0.\new_hb.i_hb2[29] ddc_chain_tb.dut_i0.\new_hb.i_hb2[28] ddc_chain_tb.dut_i0.\new_hb.i_hb2[27] ddc_chain_tb.dut_i0.\new_hb.i_hb2[26] ddc_chain_tb.dut_i0.\new_hb.i_hb2[25] ddc_chain_tb.dut_i0.\new_hb.i_hb2[24] ddc_chain_tb.dut_i0.\new_hb.i_hb2[23] ddc_chain_tb.dut_i0.\new_hb.i_hb2[22] ddc_chain_tb.dut_i0.\new_hb.i_hb2[21] ddc_chain_tb.dut_i0.\new_hb.i_hb2[20] ddc_chain_tb.dut_i0.\new_hb.i_hb2[19] ddc_chain_tb.dut_i0.\new_hb.i_hb2[18] ddc_chain_tb.dut_i0.\new_hb.i_hb2[17] ddc_chain_tb.dut_i0.\new_hb.i_hb2[16] ddc_chain_tb.dut_i0.\new_hb.i_hb2[15] ddc_chain_tb.dut_i0.\new_hb.i_hb2[14] ddc_chain_tb.dut_i0.\new_hb.i_hb2[13] ddc_chain_tb.dut_i0.\new_hb.i_hb2[12] ddc_chain_tb.dut_i0.\new_hb.i_hb2[11] ddc_chain_tb.dut_i0.\new_hb.i_hb2[10] ddc_chain_tb.dut_i0.\new_hb.i_hb2[9] ddc_chain_tb.dut_i0.\new_hb.i_hb2[8] ddc_chain_tb.dut_i0.\new_hb.i_hb2[7] ddc_chain_tb.dut_i0.\new_hb.i_hb2[6] ddc_chain_tb.dut_i0.\new_hb.i_hb2[5] ddc_chain_tb.dut_i0.\new_hb.i_hb2[4] ddc_chain_tb.dut_i0.\new_hb.i_hb2[3] ddc_chain_tb.dut_i0.\new_hb.i_hb2[2] ddc_chain_tb.dut_i0.\new_hb.i_hb2[1] ddc_chain_tb.dut_i0.\new_hb.i_hb2[0]
+#{ddc_chain_tb.dut_i0.\new_hb.q_hb2[46:0]} ddc_chain_tb.dut_i0.\new_hb.q_hb2[46] ddc_chain_tb.dut_i0.\new_hb.q_hb2[45] ddc_chain_tb.dut_i0.\new_hb.q_hb2[44] ddc_chain_tb.dut_i0.\new_hb.q_hb2[43] ddc_chain_tb.dut_i0.\new_hb.q_hb2[42] ddc_chain_tb.dut_i0.\new_hb.q_hb2[41] ddc_chain_tb.dut_i0.\new_hb.q_hb2[40] ddc_chain_tb.dut_i0.\new_hb.q_hb2[39] ddc_chain_tb.dut_i0.\new_hb.q_hb2[38] ddc_chain_tb.dut_i0.\new_hb.q_hb2[37] ddc_chain_tb.dut_i0.\new_hb.q_hb2[36] ddc_chain_tb.dut_i0.\new_hb.q_hb2[35] ddc_chain_tb.dut_i0.\new_hb.q_hb2[34] ddc_chain_tb.dut_i0.\new_hb.q_hb2[33] ddc_chain_tb.dut_i0.\new_hb.q_hb2[32] ddc_chain_tb.dut_i0.\new_hb.q_hb2[31] ddc_chain_tb.dut_i0.\new_hb.q_hb2[30] ddc_chain_tb.dut_i0.\new_hb.q_hb2[29] ddc_chain_tb.dut_i0.\new_hb.q_hb2[28] ddc_chain_tb.dut_i0.\new_hb.q_hb2[27] ddc_chain_tb.dut_i0.\new_hb.q_hb2[26] ddc_chain_tb.dut_i0.\new_hb.q_hb2[25] ddc_chain_tb.dut_i0.\new_hb.q_hb2[24] ddc_chain_tb.dut_i0.\new_hb.q_hb2[23] ddc_chain_tb.dut_i0.\new_hb.q_hb2[22] ddc_chain_tb.dut_i0.\new_hb.q_hb2[21] ddc_chain_tb.dut_i0.\new_hb.q_hb2[20] ddc_chain_tb.dut_i0.\new_hb.q_hb2[19] ddc_chain_tb.dut_i0.\new_hb.q_hb2[18] ddc_chain_tb.dut_i0.\new_hb.q_hb2[17] ddc_chain_tb.dut_i0.\new_hb.q_hb2[16] ddc_chain_tb.dut_i0.\new_hb.q_hb2[15] ddc_chain_tb.dut_i0.\new_hb.q_hb2[14] ddc_chain_tb.dut_i0.\new_hb.q_hb2[13] ddc_chain_tb.dut_i0.\new_hb.q_hb2[12] ddc_chain_tb.dut_i0.\new_hb.q_hb2[11] ddc_chain_tb.dut_i0.\new_hb.q_hb2[10] ddc_chain_tb.dut_i0.\new_hb.q_hb2[9] ddc_chain_tb.dut_i0.\new_hb.q_hb2[8] ddc_chain_tb.dut_i0.\new_hb.q_hb2[7] ddc_chain_tb.dut_i0.\new_hb.q_hb2[6] ddc_chain_tb.dut_i0.\new_hb.q_hb2[5] ddc_chain_tb.dut_i0.\new_hb.q_hb2[4] ddc_chain_tb.dut_i0.\new_hb.q_hb2[3] ddc_chain_tb.dut_i0.\new_hb.q_hb2[2] ddc_chain_tb.dut_i0.\new_hb.q_hb2[1] ddc_chain_tb.dut_i0.\new_hb.q_hb2[0]
+@20000
+-
+[pattern_trace] 1
+[pattern_trace] 0
diff --git a/fpga/usrp3/lib/sim/dsp/ddc_chain/dc_in_cordic_decim_2/simulation_script.v b/fpga/usrp3/lib/sim/dsp/ddc_chain/dc_in_cordic_decim_2/simulation_script.v
new file mode 100644
index 000000000..bc11b8b01
--- /dev/null
+++ b/fpga/usrp3/lib/sim/dsp/ddc_chain/dc_in_cordic_decim_2/simulation_script.v
@@ -0,0 +1,82 @@
+//
+// Copyright 2016 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// 10MHz master_clock_rate
+always #50 clk <= ~clk;
+
+   initial
+     begin
+	reset <= 1'b0;
+	i_in <= 0;
+	q_in <= 0;
+	run <= 0;
+	set_stb <= 0;
+	set_addr <= 0;
+	set_data <= 0;
+
+
+	@(posedge clk);
+	// Into Reset...
+	reset <= 1'b1;
+	repeat(10) @(posedge clk);
+	// .. and back out of reset.
+	reset <= 1'b0;
+	repeat(10) @(posedge clk);
+	// Now program DSP configuration via settings regs.
+	write_setting_bus(SR_DSP_RX_FREQ,42949672); // 100kHz @ 10MHz MCR
+	//  (1 << 15) * std::pow(2, ceil_log2(rate_pow))*2./(1.648*rate_pow)
+	write_setting_bus(SR_DSP_RX_SCALE_IQ, 39767); // Should include CORDIC and CIC gain compensation.
+	write_setting_bus(SR_DSP_RX_DECIM, 1<<9|1); // Decim = 2
+	write_setting_bus(SR_DSP_RX_MUX, 0);
+	write_setting_bus(SR_DSP_RX_COEFFS,0);
+	repeat(10) @(posedge clk);
+
+	// Set complex data inputs to DC unit circle position.
+	i_in <= 12'h7ff;
+	q_in <= 12'h0;
+	run <= 1'b1;
+	repeat(100) @(posedge clk);
+	// Set complex data inputs to simulate ADC saturation of front end
+	i_in <= 12'h7ff;
+	q_in <= 12'h100;
+	repeat(1000) @(posedge clk);
+	i_in <= 12'h7ff;
+	q_in <= 12'h200;
+	repeat(1000) @(posedge clk);
+	i_in <= 12'h7ff;
+	q_in <= 12'h300;
+	repeat(1000) @(posedge clk);
+	i_in <= 12'h7ff;
+	q_in <= 12'h400;
+	repeat(1000) @(posedge clk);
+	i_in <= 12'h7ff;
+	q_in <= 12'h500;
+	repeat(1000) @(posedge clk);
+	i_in <= 12'h7ff;
+	q_in <= 12'h600;
+	repeat(1000) @(posedge clk);
+	i_in <= 12'h7ff;
+	q_in <= 12'h700;
+	repeat(1000) @(posedge clk);
+ 	i_in <= 12'h7ff;
+	q_in <= 12'h7FF;
+	// Now test small signal performance
+	repeat(1000) @(posedge clk);
+	i_in <= 12'h001;
+	q_in <= 12'h000;
+	repeat(1000) @(posedge clk);
+ 	i_in <= 12'h000;
+	q_in <= 12'h001;
+	repeat(1000) @(posedge clk);
+	i_in <= 12'hfff;
+	q_in <= 12'h000;
+	repeat(1000) @(posedge clk);
+ 	i_in <= 12'h000;
+	q_in <= 12'hfff;
+
+	repeat(100000) @(posedge clk);
+	$finish();
+
+     end // initial begin
diff --git a/fpga/usrp3/lib/sim/dsp/ddc_chain/dc_in_cordic_decim_6/gtk.conf.gtkw b/fpga/usrp3/lib/sim/dsp/ddc_chain/dc_in_cordic_decim_6/gtk.conf.gtkw
new file mode 100644
index 000000000..27c2c836e
--- /dev/null
+++ b/fpga/usrp3/lib/sim/dsp/ddc_chain/dc_in_cordic_decim_6/gtk.conf.gtkw
@@ -0,0 +1,64 @@
+[*]
+[*] GTKWave Analyzer v3.3.40 (w)1999-2012 BSI
+[*] Wed Jul 15 02:18:40 2015
+[*]
+[dumpfile] "/disk2/ianb/ettus/fpgadev-b200/fpgadev/usrp3/lib/dsp/sim/sim_ddc_chain/dc_in_cordic_run/waves.vcd"
+[dumpfile_mtime] "Wed Jul 15 02:13:19 2015"
+[dumpfile_size] 238141440
+[savefile] "/disk2/ianb/ettus/fpgadev-b200/fpgadev/usrp3/lib/dsp/sim/sim_ddc_chain/dc_in_cordic_run/gtk.conf.gtkw"
+[timestart] 0
+[size] 2488 1221
+[pos] -1 -1
+*-24.083374 129800000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] ddc_chain_tb.
+[treeopen] ddc_chain_tb.dut_i0.
+[sst_width] 331
+[signals_width] 280
+[sst_expanded] 1
+[sst_vpaned_height] 370
+@28
+ddc_chain_tb.dut_i0.clk
+ddc_chain_tb.dut_i0.rst
+ddc_chain_tb.dut_i0.set_stb
+@22
+#{ddc_chain_tb.dut_i0.set_addr[7:0]} ddc_chain_tb.dut_i0.set_addr[7] ddc_chain_tb.dut_i0.set_addr[6] ddc_chain_tb.dut_i0.set_addr[5] ddc_chain_tb.dut_i0.set_addr[4] ddc_chain_tb.dut_i0.set_addr[3] ddc_chain_tb.dut_i0.set_addr[2] ddc_chain_tb.dut_i0.set_addr[1] ddc_chain_tb.dut_i0.set_addr[0]
+#{ddc_chain_tb.dut_i0.set_data[31:0]} ddc_chain_tb.dut_i0.set_data[31] ddc_chain_tb.dut_i0.set_data[30] ddc_chain_tb.dut_i0.set_data[29] ddc_chain_tb.dut_i0.set_data[28] ddc_chain_tb.dut_i0.set_data[27] ddc_chain_tb.dut_i0.set_data[26] ddc_chain_tb.dut_i0.set_data[25] ddc_chain_tb.dut_i0.set_data[24] ddc_chain_tb.dut_i0.set_data[23] ddc_chain_tb.dut_i0.set_data[22] ddc_chain_tb.dut_i0.set_data[21] ddc_chain_tb.dut_i0.set_data[20] ddc_chain_tb.dut_i0.set_data[19] ddc_chain_tb.dut_i0.set_data[18] ddc_chain_tb.dut_i0.set_data[17] ddc_chain_tb.dut_i0.set_data[16] ddc_chain_tb.dut_i0.set_data[15] ddc_chain_tb.dut_i0.set_data[14] ddc_chain_tb.dut_i0.set_data[13] ddc_chain_tb.dut_i0.set_data[12] ddc_chain_tb.dut_i0.set_data[11] ddc_chain_tb.dut_i0.set_data[10] ddc_chain_tb.dut_i0.set_data[9] ddc_chain_tb.dut_i0.set_data[8] ddc_chain_tb.dut_i0.set_data[7] ddc_chain_tb.dut_i0.set_data[6] ddc_chain_tb.dut_i0.set_data[5] ddc_chain_tb.dut_i0.set_data[4] ddc_chain_tb.dut_i0.set_data[3] ddc_chain_tb.dut_i0.set_data[2] ddc_chain_tb.dut_i0.set_data[1] ddc_chain_tb.dut_i0.set_data[0]
+@10420
+#{ddc_chain_tb.dut_i0.rx_fe_i[23:0]} ddc_chain_tb.dut_i0.rx_fe_i[23] ddc_chain_tb.dut_i0.rx_fe_i[22] ddc_chain_tb.dut_i0.rx_fe_i[21] ddc_chain_tb.dut_i0.rx_fe_i[20] ddc_chain_tb.dut_i0.rx_fe_i[19] ddc_chain_tb.dut_i0.rx_fe_i[18] ddc_chain_tb.dut_i0.rx_fe_i[17] ddc_chain_tb.dut_i0.rx_fe_i[16] ddc_chain_tb.dut_i0.rx_fe_i[15] ddc_chain_tb.dut_i0.rx_fe_i[14] ddc_chain_tb.dut_i0.rx_fe_i[13] ddc_chain_tb.dut_i0.rx_fe_i[12] ddc_chain_tb.dut_i0.rx_fe_i[11] ddc_chain_tb.dut_i0.rx_fe_i[10] ddc_chain_tb.dut_i0.rx_fe_i[9] ddc_chain_tb.dut_i0.rx_fe_i[8] ddc_chain_tb.dut_i0.rx_fe_i[7] ddc_chain_tb.dut_i0.rx_fe_i[6] ddc_chain_tb.dut_i0.rx_fe_i[5] ddc_chain_tb.dut_i0.rx_fe_i[4] ddc_chain_tb.dut_i0.rx_fe_i[3] ddc_chain_tb.dut_i0.rx_fe_i[2] ddc_chain_tb.dut_i0.rx_fe_i[1] ddc_chain_tb.dut_i0.rx_fe_i[0]
+@20000
+-
+@10420
+#{ddc_chain_tb.dut_i0.rx_fe_q[23:0]} ddc_chain_tb.dut_i0.rx_fe_q[23] ddc_chain_tb.dut_i0.rx_fe_q[22] ddc_chain_tb.dut_i0.rx_fe_q[21] ddc_chain_tb.dut_i0.rx_fe_q[20] ddc_chain_tb.dut_i0.rx_fe_q[19] ddc_chain_tb.dut_i0.rx_fe_q[18] ddc_chain_tb.dut_i0.rx_fe_q[17] ddc_chain_tb.dut_i0.rx_fe_q[16] ddc_chain_tb.dut_i0.rx_fe_q[15] ddc_chain_tb.dut_i0.rx_fe_q[14] ddc_chain_tb.dut_i0.rx_fe_q[13] ddc_chain_tb.dut_i0.rx_fe_q[12] ddc_chain_tb.dut_i0.rx_fe_q[11] ddc_chain_tb.dut_i0.rx_fe_q[10] ddc_chain_tb.dut_i0.rx_fe_q[9] ddc_chain_tb.dut_i0.rx_fe_q[8] ddc_chain_tb.dut_i0.rx_fe_q[7] ddc_chain_tb.dut_i0.rx_fe_q[6] ddc_chain_tb.dut_i0.rx_fe_q[5] ddc_chain_tb.dut_i0.rx_fe_q[4] ddc_chain_tb.dut_i0.rx_fe_q[3] ddc_chain_tb.dut_i0.rx_fe_q[2] ddc_chain_tb.dut_i0.rx_fe_q[1] ddc_chain_tb.dut_i0.rx_fe_q[0]
+@20000
+-
+@10420
+#{ddc_chain_tb.dut_i0.i_cordic_clip[23:0]} ddc_chain_tb.dut_i0.i_cordic_clip[23] ddc_chain_tb.dut_i0.i_cordic_clip[22] ddc_chain_tb.dut_i0.i_cordic_clip[21] ddc_chain_tb.dut_i0.i_cordic_clip[20] ddc_chain_tb.dut_i0.i_cordic_clip[19] ddc_chain_tb.dut_i0.i_cordic_clip[18] ddc_chain_tb.dut_i0.i_cordic_clip[17] ddc_chain_tb.dut_i0.i_cordic_clip[16] ddc_chain_tb.dut_i0.i_cordic_clip[15] ddc_chain_tb.dut_i0.i_cordic_clip[14] ddc_chain_tb.dut_i0.i_cordic_clip[13] ddc_chain_tb.dut_i0.i_cordic_clip[12] ddc_chain_tb.dut_i0.i_cordic_clip[11] ddc_chain_tb.dut_i0.i_cordic_clip[10] ddc_chain_tb.dut_i0.i_cordic_clip[9] ddc_chain_tb.dut_i0.i_cordic_clip[8] ddc_chain_tb.dut_i0.i_cordic_clip[7] ddc_chain_tb.dut_i0.i_cordic_clip[6] ddc_chain_tb.dut_i0.i_cordic_clip[5] ddc_chain_tb.dut_i0.i_cordic_clip[4] ddc_chain_tb.dut_i0.i_cordic_clip[3] ddc_chain_tb.dut_i0.i_cordic_clip[2] ddc_chain_tb.dut_i0.i_cordic_clip[1] ddc_chain_tb.dut_i0.i_cordic_clip[0]
+@20000
+-
+@10420
+#{ddc_chain_tb.dut_i0.q_cordic_clip[23:0]} ddc_chain_tb.dut_i0.q_cordic_clip[23] ddc_chain_tb.dut_i0.q_cordic_clip[22] ddc_chain_tb.dut_i0.q_cordic_clip[21] ddc_chain_tb.dut_i0.q_cordic_clip[20] ddc_chain_tb.dut_i0.q_cordic_clip[19] ddc_chain_tb.dut_i0.q_cordic_clip[18] ddc_chain_tb.dut_i0.q_cordic_clip[17] ddc_chain_tb.dut_i0.q_cordic_clip[16] ddc_chain_tb.dut_i0.q_cordic_clip[15] ddc_chain_tb.dut_i0.q_cordic_clip[14] ddc_chain_tb.dut_i0.q_cordic_clip[13] ddc_chain_tb.dut_i0.q_cordic_clip[12] ddc_chain_tb.dut_i0.q_cordic_clip[11] ddc_chain_tb.dut_i0.q_cordic_clip[10] ddc_chain_tb.dut_i0.q_cordic_clip[9] ddc_chain_tb.dut_i0.q_cordic_clip[8] ddc_chain_tb.dut_i0.q_cordic_clip[7] ddc_chain_tb.dut_i0.q_cordic_clip[6] ddc_chain_tb.dut_i0.q_cordic_clip[5] ddc_chain_tb.dut_i0.q_cordic_clip[4] ddc_chain_tb.dut_i0.q_cordic_clip[3] ddc_chain_tb.dut_i0.q_cordic_clip[2] ddc_chain_tb.dut_i0.q_cordic_clip[1] ddc_chain_tb.dut_i0.q_cordic_clip[0]
+@20000
+-
+@10420
+#{ddc_chain_tb.dut_i0.i_cic[23:0]} ddc_chain_tb.dut_i0.i_cic[23] ddc_chain_tb.dut_i0.i_cic[22] ddc_chain_tb.dut_i0.i_cic[21] ddc_chain_tb.dut_i0.i_cic[20] ddc_chain_tb.dut_i0.i_cic[19] ddc_chain_tb.dut_i0.i_cic[18] ddc_chain_tb.dut_i0.i_cic[17] ddc_chain_tb.dut_i0.i_cic[16] ddc_chain_tb.dut_i0.i_cic[15] ddc_chain_tb.dut_i0.i_cic[14] ddc_chain_tb.dut_i0.i_cic[13] ddc_chain_tb.dut_i0.i_cic[12] ddc_chain_tb.dut_i0.i_cic[11] ddc_chain_tb.dut_i0.i_cic[10] ddc_chain_tb.dut_i0.i_cic[9] ddc_chain_tb.dut_i0.i_cic[8] ddc_chain_tb.dut_i0.i_cic[7] ddc_chain_tb.dut_i0.i_cic[6] ddc_chain_tb.dut_i0.i_cic[5] ddc_chain_tb.dut_i0.i_cic[4] ddc_chain_tb.dut_i0.i_cic[3] ddc_chain_tb.dut_i0.i_cic[2] ddc_chain_tb.dut_i0.i_cic[1] ddc_chain_tb.dut_i0.i_cic[0]
+@20000
+-
+@10420
+#{ddc_chain_tb.dut_i0.q_cic[23:0]} ddc_chain_tb.dut_i0.q_cic[23] ddc_chain_tb.dut_i0.q_cic[22] ddc_chain_tb.dut_i0.q_cic[21] ddc_chain_tb.dut_i0.q_cic[20] ddc_chain_tb.dut_i0.q_cic[19] ddc_chain_tb.dut_i0.q_cic[18] ddc_chain_tb.dut_i0.q_cic[17] ddc_chain_tb.dut_i0.q_cic[16] ddc_chain_tb.dut_i0.q_cic[15] ddc_chain_tb.dut_i0.q_cic[14] ddc_chain_tb.dut_i0.q_cic[13] ddc_chain_tb.dut_i0.q_cic[12] ddc_chain_tb.dut_i0.q_cic[11] ddc_chain_tb.dut_i0.q_cic[10] ddc_chain_tb.dut_i0.q_cic[9] ddc_chain_tb.dut_i0.q_cic[8] ddc_chain_tb.dut_i0.q_cic[7] ddc_chain_tb.dut_i0.q_cic[6] ddc_chain_tb.dut_i0.q_cic[5] ddc_chain_tb.dut_i0.q_cic[4] ddc_chain_tb.dut_i0.q_cic[3] ddc_chain_tb.dut_i0.q_cic[2] ddc_chain_tb.dut_i0.q_cic[1] ddc_chain_tb.dut_i0.q_cic[0]
+@20000
+-
+@10420
+#{ddc_chain_tb.dut_i0.\new_hb.i_hb1[46:0]} ddc_chain_tb.dut_i0.\new_hb.i_hb1[46] ddc_chain_tb.dut_i0.\new_hb.i_hb1[45] ddc_chain_tb.dut_i0.\new_hb.i_hb1[44] ddc_chain_tb.dut_i0.\new_hb.i_hb1[43] ddc_chain_tb.dut_i0.\new_hb.i_hb1[42] ddc_chain_tb.dut_i0.\new_hb.i_hb1[41] ddc_chain_tb.dut_i0.\new_hb.i_hb1[40] ddc_chain_tb.dut_i0.\new_hb.i_hb1[39] ddc_chain_tb.dut_i0.\new_hb.i_hb1[38] ddc_chain_tb.dut_i0.\new_hb.i_hb1[37] ddc_chain_tb.dut_i0.\new_hb.i_hb1[36] ddc_chain_tb.dut_i0.\new_hb.i_hb1[35] ddc_chain_tb.dut_i0.\new_hb.i_hb1[34] ddc_chain_tb.dut_i0.\new_hb.i_hb1[33] ddc_chain_tb.dut_i0.\new_hb.i_hb1[32] ddc_chain_tb.dut_i0.\new_hb.i_hb1[31] ddc_chain_tb.dut_i0.\new_hb.i_hb1[30] ddc_chain_tb.dut_i0.\new_hb.i_hb1[29] ddc_chain_tb.dut_i0.\new_hb.i_hb1[28] ddc_chain_tb.dut_i0.\new_hb.i_hb1[27] ddc_chain_tb.dut_i0.\new_hb.i_hb1[26] ddc_chain_tb.dut_i0.\new_hb.i_hb1[25] ddc_chain_tb.dut_i0.\new_hb.i_hb1[24] ddc_chain_tb.dut_i0.\new_hb.i_hb1[23] ddc_chain_tb.dut_i0.\new_hb.i_hb1[22] ddc_chain_tb.dut_i0.\new_hb.i_hb1[21] ddc_chain_tb.dut_i0.\new_hb.i_hb1[20] ddc_chain_tb.dut_i0.\new_hb.i_hb1[19] ddc_chain_tb.dut_i0.\new_hb.i_hb1[18] ddc_chain_tb.dut_i0.\new_hb.i_hb1[17] ddc_chain_tb.dut_i0.\new_hb.i_hb1[16] ddc_chain_tb.dut_i0.\new_hb.i_hb1[15] ddc_chain_tb.dut_i0.\new_hb.i_hb1[14] ddc_chain_tb.dut_i0.\new_hb.i_hb1[13] ddc_chain_tb.dut_i0.\new_hb.i_hb1[12] ddc_chain_tb.dut_i0.\new_hb.i_hb1[11] ddc_chain_tb.dut_i0.\new_hb.i_hb1[10] ddc_chain_tb.dut_i0.\new_hb.i_hb1[9] ddc_chain_tb.dut_i0.\new_hb.i_hb1[8] ddc_chain_tb.dut_i0.\new_hb.i_hb1[7] ddc_chain_tb.dut_i0.\new_hb.i_hb1[6] ddc_chain_tb.dut_i0.\new_hb.i_hb1[5] ddc_chain_tb.dut_i0.\new_hb.i_hb1[4] ddc_chain_tb.dut_i0.\new_hb.i_hb1[3] ddc_chain_tb.dut_i0.\new_hb.i_hb1[2] ddc_chain_tb.dut_i0.\new_hb.i_hb1[1] ddc_chain_tb.dut_i0.\new_hb.i_hb1[0]
+@20000
+-
+@10420
+#{ddc_chain_tb.dut_i0.\new_hb.q_hb1[46:0]} ddc_chain_tb.dut_i0.\new_hb.q_hb1[46] ddc_chain_tb.dut_i0.\new_hb.q_hb1[45] ddc_chain_tb.dut_i0.\new_hb.q_hb1[44] ddc_chain_tb.dut_i0.\new_hb.q_hb1[43] ddc_chain_tb.dut_i0.\new_hb.q_hb1[42] ddc_chain_tb.dut_i0.\new_hb.q_hb1[41] ddc_chain_tb.dut_i0.\new_hb.q_hb1[40] ddc_chain_tb.dut_i0.\new_hb.q_hb1[39] ddc_chain_tb.dut_i0.\new_hb.q_hb1[38] ddc_chain_tb.dut_i0.\new_hb.q_hb1[37] ddc_chain_tb.dut_i0.\new_hb.q_hb1[36] ddc_chain_tb.dut_i0.\new_hb.q_hb1[35] ddc_chain_tb.dut_i0.\new_hb.q_hb1[34] ddc_chain_tb.dut_i0.\new_hb.q_hb1[33] ddc_chain_tb.dut_i0.\new_hb.q_hb1[32] ddc_chain_tb.dut_i0.\new_hb.q_hb1[31] ddc_chain_tb.dut_i0.\new_hb.q_hb1[30] ddc_chain_tb.dut_i0.\new_hb.q_hb1[29] ddc_chain_tb.dut_i0.\new_hb.q_hb1[28] ddc_chain_tb.dut_i0.\new_hb.q_hb1[27] ddc_chain_tb.dut_i0.\new_hb.q_hb1[26] ddc_chain_tb.dut_i0.\new_hb.q_hb1[25] ddc_chain_tb.dut_i0.\new_hb.q_hb1[24] ddc_chain_tb.dut_i0.\new_hb.q_hb1[23] ddc_chain_tb.dut_i0.\new_hb.q_hb1[22] ddc_chain_tb.dut_i0.\new_hb.q_hb1[21] ddc_chain_tb.dut_i0.\new_hb.q_hb1[20] ddc_chain_tb.dut_i0.\new_hb.q_hb1[19] ddc_chain_tb.dut_i0.\new_hb.q_hb1[18] ddc_chain_tb.dut_i0.\new_hb.q_hb1[17] ddc_chain_tb.dut_i0.\new_hb.q_hb1[16] ddc_chain_tb.dut_i0.\new_hb.q_hb1[15] ddc_chain_tb.dut_i0.\new_hb.q_hb1[14] ddc_chain_tb.dut_i0.\new_hb.q_hb1[13] ddc_chain_tb.dut_i0.\new_hb.q_hb1[12] ddc_chain_tb.dut_i0.\new_hb.q_hb1[11] ddc_chain_tb.dut_i0.\new_hb.q_hb1[10] ddc_chain_tb.dut_i0.\new_hb.q_hb1[9] ddc_chain_tb.dut_i0.\new_hb.q_hb1[8] ddc_chain_tb.dut_i0.\new_hb.q_hb1[7] ddc_chain_tb.dut_i0.\new_hb.q_hb1[6] ddc_chain_tb.dut_i0.\new_hb.q_hb1[5] ddc_chain_tb.dut_i0.\new_hb.q_hb1[4] ddc_chain_tb.dut_i0.\new_hb.q_hb1[3] ddc_chain_tb.dut_i0.\new_hb.q_hb1[2] ddc_chain_tb.dut_i0.\new_hb.q_hb1[1] ddc_chain_tb.dut_i0.\new_hb.q_hb1[0]
+@20000
+-
+@10420
+#{ddc_chain_tb.dut_i0.\new_hb.i_hb2[46:0]} ddc_chain_tb.dut_i0.\new_hb.i_hb2[46] ddc_chain_tb.dut_i0.\new_hb.i_hb2[45] ddc_chain_tb.dut_i0.\new_hb.i_hb2[44] ddc_chain_tb.dut_i0.\new_hb.i_hb2[43] ddc_chain_tb.dut_i0.\new_hb.i_hb2[42] ddc_chain_tb.dut_i0.\new_hb.i_hb2[41] ddc_chain_tb.dut_i0.\new_hb.i_hb2[40] ddc_chain_tb.dut_i0.\new_hb.i_hb2[39] ddc_chain_tb.dut_i0.\new_hb.i_hb2[38] ddc_chain_tb.dut_i0.\new_hb.i_hb2[37] ddc_chain_tb.dut_i0.\new_hb.i_hb2[36] ddc_chain_tb.dut_i0.\new_hb.i_hb2[35] ddc_chain_tb.dut_i0.\new_hb.i_hb2[34] ddc_chain_tb.dut_i0.\new_hb.i_hb2[33] ddc_chain_tb.dut_i0.\new_hb.i_hb2[32] ddc_chain_tb.dut_i0.\new_hb.i_hb2[31] ddc_chain_tb.dut_i0.\new_hb.i_hb2[30] ddc_chain_tb.dut_i0.\new_hb.i_hb2[29] ddc_chain_tb.dut_i0.\new_hb.i_hb2[28] ddc_chain_tb.dut_i0.\new_hb.i_hb2[27] ddc_chain_tb.dut_i0.\new_hb.i_hb2[26] ddc_chain_tb.dut_i0.\new_hb.i_hb2[25] ddc_chain_tb.dut_i0.\new_hb.i_hb2[24] ddc_chain_tb.dut_i0.\new_hb.i_hb2[23] ddc_chain_tb.dut_i0.\new_hb.i_hb2[22] ddc_chain_tb.dut_i0.\new_hb.i_hb2[21] ddc_chain_tb.dut_i0.\new_hb.i_hb2[20] ddc_chain_tb.dut_i0.\new_hb.i_hb2[19] ddc_chain_tb.dut_i0.\new_hb.i_hb2[18] ddc_chain_tb.dut_i0.\new_hb.i_hb2[17] ddc_chain_tb.dut_i0.\new_hb.i_hb2[16] ddc_chain_tb.dut_i0.\new_hb.i_hb2[15] ddc_chain_tb.dut_i0.\new_hb.i_hb2[14] ddc_chain_tb.dut_i0.\new_hb.i_hb2[13] ddc_chain_tb.dut_i0.\new_hb.i_hb2[12] ddc_chain_tb.dut_i0.\new_hb.i_hb2[11] ddc_chain_tb.dut_i0.\new_hb.i_hb2[10] ddc_chain_tb.dut_i0.\new_hb.i_hb2[9] ddc_chain_tb.dut_i0.\new_hb.i_hb2[8] ddc_chain_tb.dut_i0.\new_hb.i_hb2[7] ddc_chain_tb.dut_i0.\new_hb.i_hb2[6] ddc_chain_tb.dut_i0.\new_hb.i_hb2[5] ddc_chain_tb.dut_i0.\new_hb.i_hb2[4] ddc_chain_tb.dut_i0.\new_hb.i_hb2[3] ddc_chain_tb.dut_i0.\new_hb.i_hb2[2] ddc_chain_tb.dut_i0.\new_hb.i_hb2[1] ddc_chain_tb.dut_i0.\new_hb.i_hb2[0]
+#{ddc_chain_tb.dut_i0.\new_hb.q_hb2[46:0]} ddc_chain_tb.dut_i0.\new_hb.q_hb2[46] ddc_chain_tb.dut_i0.\new_hb.q_hb2[45] ddc_chain_tb.dut_i0.\new_hb.q_hb2[44] ddc_chain_tb.dut_i0.\new_hb.q_hb2[43] ddc_chain_tb.dut_i0.\new_hb.q_hb2[42] ddc_chain_tb.dut_i0.\new_hb.q_hb2[41] ddc_chain_tb.dut_i0.\new_hb.q_hb2[40] ddc_chain_tb.dut_i0.\new_hb.q_hb2[39] ddc_chain_tb.dut_i0.\new_hb.q_hb2[38] ddc_chain_tb.dut_i0.\new_hb.q_hb2[37] ddc_chain_tb.dut_i0.\new_hb.q_hb2[36] ddc_chain_tb.dut_i0.\new_hb.q_hb2[35] ddc_chain_tb.dut_i0.\new_hb.q_hb2[34] ddc_chain_tb.dut_i0.\new_hb.q_hb2[33] ddc_chain_tb.dut_i0.\new_hb.q_hb2[32] ddc_chain_tb.dut_i0.\new_hb.q_hb2[31] ddc_chain_tb.dut_i0.\new_hb.q_hb2[30] ddc_chain_tb.dut_i0.\new_hb.q_hb2[29] ddc_chain_tb.dut_i0.\new_hb.q_hb2[28] ddc_chain_tb.dut_i0.\new_hb.q_hb2[27] ddc_chain_tb.dut_i0.\new_hb.q_hb2[26] ddc_chain_tb.dut_i0.\new_hb.q_hb2[25] ddc_chain_tb.dut_i0.\new_hb.q_hb2[24] ddc_chain_tb.dut_i0.\new_hb.q_hb2[23] ddc_chain_tb.dut_i0.\new_hb.q_hb2[22] ddc_chain_tb.dut_i0.\new_hb.q_hb2[21] ddc_chain_tb.dut_i0.\new_hb.q_hb2[20] ddc_chain_tb.dut_i0.\new_hb.q_hb2[19] ddc_chain_tb.dut_i0.\new_hb.q_hb2[18] ddc_chain_tb.dut_i0.\new_hb.q_hb2[17] ddc_chain_tb.dut_i0.\new_hb.q_hb2[16] ddc_chain_tb.dut_i0.\new_hb.q_hb2[15] ddc_chain_tb.dut_i0.\new_hb.q_hb2[14] ddc_chain_tb.dut_i0.\new_hb.q_hb2[13] ddc_chain_tb.dut_i0.\new_hb.q_hb2[12] ddc_chain_tb.dut_i0.\new_hb.q_hb2[11] ddc_chain_tb.dut_i0.\new_hb.q_hb2[10] ddc_chain_tb.dut_i0.\new_hb.q_hb2[9] ddc_chain_tb.dut_i0.\new_hb.q_hb2[8] ddc_chain_tb.dut_i0.\new_hb.q_hb2[7] ddc_chain_tb.dut_i0.\new_hb.q_hb2[6] ddc_chain_tb.dut_i0.\new_hb.q_hb2[5] ddc_chain_tb.dut_i0.\new_hb.q_hb2[4] ddc_chain_tb.dut_i0.\new_hb.q_hb2[3] ddc_chain_tb.dut_i0.\new_hb.q_hb2[2] ddc_chain_tb.dut_i0.\new_hb.q_hb2[1] ddc_chain_tb.dut_i0.\new_hb.q_hb2[0]
+@20000
+-
+[pattern_trace] 1
+[pattern_trace] 0
diff --git a/fpga/usrp3/lib/sim/dsp/ddc_chain/dc_in_cordic_decim_6/simulation_script.v b/fpga/usrp3/lib/sim/dsp/ddc_chain/dc_in_cordic_decim_6/simulation_script.v
new file mode 100644
index 000000000..19836cc98
--- /dev/null
+++ b/fpga/usrp3/lib/sim/dsp/ddc_chain/dc_in_cordic_decim_6/simulation_script.v
@@ -0,0 +1,83 @@
+//
+// Copyright 2016 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// 10MHz master_clock_rate
+always #50 clk <= ~clk;
+
+   initial
+     begin
+	reset <= 1'b0;
+	i_in <= 0;
+	q_in <= 0;
+	run <= 0;
+	set_stb <= 0;
+	set_addr <= 0;
+	set_data <= 0;
+
+
+	@(posedge clk);
+	// Into Reset...
+	reset <= 1'b1;
+	repeat(10) @(posedge clk);
+	// .. and back out of reset.
+	reset <= 1'b0;
+	repeat(10) @(posedge clk);
+	// Now program DSP configuration via settings regs.
+	write_setting_bus(SR_DSP_RX_FREQ,42949672); // 100kHz @ 10MHz MCR
+	write_setting_bus(SR_DSP_RX_SCALE_IQ, 62842); // Should include CORDIC and CIC gain compensation.
+       // write_setting_bus(SR_DSP_RX_SCALE_IQ, ((1<<16) * 1.647 * 0.5 * 1.22)); // Should include CORDIC and CIC gain compensation.
+	write_setting_bus(SR_DSP_RX_DECIM, 1<<9|3); // Decim = 6
+	write_setting_bus(SR_DSP_RX_MUX, 0);
+	write_setting_bus(SR_DSP_RX_COEFFS,0);
+	repeat(10) @(posedge clk);
+
+	// Set complex data inputs to DC unit circle position.
+	i_in <= 12'h7ff;
+	q_in <= 12'h0;
+	run <= 1'b1;
+	repeat(100) @(posedge clk);
+	// Set complex data inputs to simulate ADC saturation of front end
+	i_in <= 12'h7ff;
+	q_in <= 12'h100;
+	repeat(1000) @(posedge clk);
+	i_in <= 12'h7ff;
+	q_in <= 12'h200;
+	repeat(1000) @(posedge clk);
+	i_in <= 12'h7ff;
+	q_in <= 12'h300;
+	repeat(1000) @(posedge clk);
+	i_in <= 12'h7ff;
+	q_in <= 12'h400;
+	repeat(1000) @(posedge clk);
+	i_in <= 12'h7ff;
+	q_in <= 12'h500;
+	repeat(1000) @(posedge clk);
+	i_in <= 12'h7ff;
+	q_in <= 12'h600;
+	repeat(1000) @(posedge clk);
+	i_in <= 12'h7ff;
+	q_in <= 12'h700;
+	repeat(1000) @(posedge clk);
+ 	i_in <= 12'h7ff;
+	q_in <= 12'h7FF;
+	// Now test small signal performance
+	repeat(1000) @(posedge clk);
+	i_in <= 12'h001;
+	q_in <= 12'h000;
+	repeat(1000) @(posedge clk);
+ 	i_in <= 12'h000;
+	q_in <= 12'h001;
+	repeat(1000) @(posedge clk);
+	i_in <= 12'hfff;
+	q_in <= 12'h000;
+	repeat(1000) @(posedge clk);
+ 	i_in <= 12'h000;
+	q_in <= 12'hfff;
+
+
+	repeat(100000) @(posedge clk);
+	$finish();
+
+     end // initial begin
diff --git a/fpga/usrp3/lib/sim/dsp/ddc_chain/ddc_chain_tb.v b/fpga/usrp3/lib/sim/dsp/ddc_chain/ddc_chain_tb.v
new file mode 100644
index 000000000..fe8bbb000
--- /dev/null
+++ b/fpga/usrp3/lib/sim/dsp/ddc_chain/ddc_chain_tb.v
@@ -0,0 +1,94 @@
+//
+// Copyright 2016 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+`timescale 1ns/1ps
+
+module ddc_chain_tb();
+
+   initial $dumpfile("waves.vcd");
+   initial $dumpvars(2,ddc_chain_tb.dut_i0);
+
+
+   // Need these declarations to use the task libarary.
+`ifndef CHDR_IN_NUMBER
+ `define CHDR_IN_NUMBER 1
+`endif
+`ifndef CHDR_OUT_NUMBER
+ `define CHDR_OUT_NUMBER 1
+`endif
+
+   reg [63:0] data_in[`CHDR_IN_NUMBER-1:0];
+   reg 	      last_in[`CHDR_IN_NUMBER-1:0];
+   reg 	      valid_in[`CHDR_IN_NUMBER-1:0];
+   wire       ready_in[`CHDR_IN_NUMBER-1:0];
+   wire [63:0] data_out[`CHDR_OUT_NUMBER-1:0];
+   wire 	      last_out[`CHDR_OUT_NUMBER-1:0];
+   wire 	      valid_out[`CHDR_OUT_NUMBER-1:0];
+   reg        ready_out[`CHDR_OUT_NUMBER-1:0];
+   //
+
+`include "../../../../../sim/radio_setting_regs.v"
+`include "../../../../../sim/task_library.v"
+
+   localparam DSPNO = 0;
+   localparam WIDTH = 24;
+   localparam NEW_HB_DECIM = 1;
+   localparam DEVICE = "SPARTAN6";
+
+   reg clk = 0;
+   reg reset;
+
+   reg set_stb;
+   reg [7:0] set_addr;
+   reg [31:0] set_data;
+
+   wire [WIDTH-1:0] rx_fe_i, rx_fe_q;
+   wire [31:0] 	    sample;
+   reg 		    run;
+   wire 	    strobe;
+
+   reg [11:0] 	    i_in, q_in;
+
+   assign rx_fe_i = {i_in,12'h0};
+   assign rx_fe_q = {q_in,12'h0};
+
+   //
+   // DUT
+   //
+   ddc_chain
+     #(
+     .BASE(SR_RX_DSP),
+     .DSPNO(DSPNO),
+     .WIDTH(WIDTH),
+     .NEW_HB_DECIM(NEW_HB_DECIM),
+     .DEVICE("SPARTAN6")
+       )
+   dut_i0 (
+     .clk(clk),
+     .rst(reset),
+     .clr(1'b0),
+     .set_stb(set_stb),
+     .set_addr(set_addr),
+     .set_data(set_data),
+
+     // From RX frontend
+     .rx_fe_i(rx_fe_i),
+     .rx_fe_q(rx_fe_q),
+
+     // To RX control
+     .sample(sample),
+     .run(run),
+     .strobe(strobe),
+     .debug()
+     );
+
+
+
+   //
+   // Include testbench
+   //
+`include "simulation_script.v"
+
+endmodule //
diff --git a/fpga/usrp3/lib/sim/dsp/ddc_chain/run_isim b/fpga/usrp3/lib/sim/dsp/ddc_chain/run_isim
new file mode 100755
index 000000000..d43ccf230
--- /dev/null
+++ b/fpga/usrp3/lib/sim/dsp/ddc_chain/run_isim
@@ -0,0 +1,18 @@
+rm -rf fuse* *.exe isim
+vlogcomp -work work ${XILINX}/verilog/src/glbl.v
+vlogcomp -work work --sourcelibext .v \
+	 --sourcelibdir ../../.. \
+	  --sourcelibdir ../../../../control \
+	 --sourcelibdir ../../../../../top/b200/coregen_dsp \
+	 --sourcelibdir ../../../../../top/b200/coregen \
+	 --sourcelibdir ${XILINX}/verilog/src/unimacro \
+	 ddc_chain_tb.v
+
+
+
+fuse work.ddc_chain_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o testbench.exe
+
+# run the simulation script
+./testbench.exe #-gui   #-tclbatch simcmds.tcl 
+
+
diff --git a/fpga/usrp3/lib/sim/dsp/ddc_chain_x300/dctest/.gitignore b/fpga/usrp3/lib/sim/dsp/ddc_chain_x300/dctest/.gitignore
new file mode 100644
index 000000000..7826d75e2
--- /dev/null
+++ b/fpga/usrp3/lib/sim/dsp/ddc_chain_x300/dctest/.gitignore
@@ -0,0 +1,4 @@
+fuse*
+isim*
+*.exe
+*.wcfg
diff --git a/fpga/usrp3/lib/sim/dsp/ddc_chain_x300/dctest/DDC.sav b/fpga/usrp3/lib/sim/dsp/ddc_chain_x300/dctest/DDC.sav
new file mode 100644
index 000000000..96ec87c67
--- /dev/null
+++ b/fpga/usrp3/lib/sim/dsp/ddc_chain_x300/dctest/DDC.sav
@@ -0,0 +1,101 @@
+[*]
+[*] GTKWave Analyzer v3.3.35 (w)1999-2012 BSI
+[*] Thu Dec  5 01:04:45 2013
+[*]
+[dumpfile] "/home/matt/fpgadev/usrp3/sim/ddc_chain_x300/dctest/ddc_chain_x300_tb.vcd"
+[dumpfile_mtime] "Wed Dec  4 23:01:47 2013"
+[dumpfile_size] 12968759
+[savefile] "/home/matt/fpgadev/usrp3/sim/ddc_chain_x300/dctest/DDC.sav"
+[timestart] 0
+[size] 1600 843
+[pos] -1 -1
+*-22.573410 5990000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] ddc_chain_x300_tb.
+[treeopen] ddc_chain_x300_tb.ddc_chain.
+[treeopen] ddc_chain_x300_tb.ddc_chain.clip_i.
+[sst_width] 231
+[signals_width] 313
+[sst_expanded] 1
+[sst_vpaned_height] 229
+@420
+#{ddc_chain_x300_tb.ddc_chain.i_cic[23:0]} ddc_chain_x300_tb.ddc_chain.i_cic[23] ddc_chain_x300_tb.ddc_chain.i_cic[22] ddc_chain_x300_tb.ddc_chain.i_cic[21] ddc_chain_x300_tb.ddc_chain.i_cic[20] ddc_chain_x300_tb.ddc_chain.i_cic[19] ddc_chain_x300_tb.ddc_chain.i_cic[18] ddc_chain_x300_tb.ddc_chain.i_cic[17] ddc_chain_x300_tb.ddc_chain.i_cic[16] ddc_chain_x300_tb.ddc_chain.i_cic[15] ddc_chain_x300_tb.ddc_chain.i_cic[14] ddc_chain_x300_tb.ddc_chain.i_cic[13] ddc_chain_x300_tb.ddc_chain.i_cic[12] ddc_chain_x300_tb.ddc_chain.i_cic[11] ddc_chain_x300_tb.ddc_chain.i_cic[10] ddc_chain_x300_tb.ddc_chain.i_cic[9] ddc_chain_x300_tb.ddc_chain.i_cic[8] ddc_chain_x300_tb.ddc_chain.i_cic[7] ddc_chain_x300_tb.ddc_chain.i_cic[6] ddc_chain_x300_tb.ddc_chain.i_cic[5] ddc_chain_x300_tb.ddc_chain.i_cic[4] ddc_chain_x300_tb.ddc_chain.i_cic[3] ddc_chain_x300_tb.ddc_chain.i_cic[2] ddc_chain_x300_tb.ddc_chain.i_cic[1] ddc_chain_x300_tb.ddc_chain.i_cic[0]
+@28
+ddc_chain_x300_tb.ddc_chain.strobe_cic
+@420
+#{ddc_chain_x300_tb.ddc_chain.i_hb1[46:0]} ddc_chain_x300_tb.ddc_chain.i_hb1[46] ddc_chain_x300_tb.ddc_chain.i_hb1[45] ddc_chain_x300_tb.ddc_chain.i_hb1[44] ddc_chain_x300_tb.ddc_chain.i_hb1[43] ddc_chain_x300_tb.ddc_chain.i_hb1[42] ddc_chain_x300_tb.ddc_chain.i_hb1[41] ddc_chain_x300_tb.ddc_chain.i_hb1[40] ddc_chain_x300_tb.ddc_chain.i_hb1[39] ddc_chain_x300_tb.ddc_chain.i_hb1[38] ddc_chain_x300_tb.ddc_chain.i_hb1[37] ddc_chain_x300_tb.ddc_chain.i_hb1[36] ddc_chain_x300_tb.ddc_chain.i_hb1[35] ddc_chain_x300_tb.ddc_chain.i_hb1[34] ddc_chain_x300_tb.ddc_chain.i_hb1[33] ddc_chain_x300_tb.ddc_chain.i_hb1[32] ddc_chain_x300_tb.ddc_chain.i_hb1[31] ddc_chain_x300_tb.ddc_chain.i_hb1[30] ddc_chain_x300_tb.ddc_chain.i_hb1[29] ddc_chain_x300_tb.ddc_chain.i_hb1[28] ddc_chain_x300_tb.ddc_chain.i_hb1[27] ddc_chain_x300_tb.ddc_chain.i_hb1[26] ddc_chain_x300_tb.ddc_chain.i_hb1[25] ddc_chain_x300_tb.ddc_chain.i_hb1[24] ddc_chain_x300_tb.ddc_chain.i_hb1[23] ddc_chain_x300_tb.ddc_chain.i_hb1[22] ddc_chain_x300_tb.ddc_chain.i_hb1[21] ddc_chain_x300_tb.ddc_chain.i_hb1[20] ddc_chain_x300_tb.ddc_chain.i_hb1[19] ddc_chain_x300_tb.ddc_chain.i_hb1[18] ddc_chain_x300_tb.ddc_chain.i_hb1[17] ddc_chain_x300_tb.ddc_chain.i_hb1[16] ddc_chain_x300_tb.ddc_chain.i_hb1[15] ddc_chain_x300_tb.ddc_chain.i_hb1[14] ddc_chain_x300_tb.ddc_chain.i_hb1[13] ddc_chain_x300_tb.ddc_chain.i_hb1[12] ddc_chain_x300_tb.ddc_chain.i_hb1[11] ddc_chain_x300_tb.ddc_chain.i_hb1[10] ddc_chain_x300_tb.ddc_chain.i_hb1[9] ddc_chain_x300_tb.ddc_chain.i_hb1[8] ddc_chain_x300_tb.ddc_chain.i_hb1[7] ddc_chain_x300_tb.ddc_chain.i_hb1[6] ddc_chain_x300_tb.ddc_chain.i_hb1[5] ddc_chain_x300_tb.ddc_chain.i_hb1[4] ddc_chain_x300_tb.ddc_chain.i_hb1[3] ddc_chain_x300_tb.ddc_chain.i_hb1[2] ddc_chain_x300_tb.ddc_chain.i_hb1[1] ddc_chain_x300_tb.ddc_chain.i_hb1[0]
+@28
+ddc_chain_x300_tb.ddc_chain.strobe_hb1
+@420
+#{ddc_chain_x300_tb.ddc_chain.i_hb2[46:0]} ddc_chain_x300_tb.ddc_chain.i_hb2[46] ddc_chain_x300_tb.ddc_chain.i_hb2[45] ddc_chain_x300_tb.ddc_chain.i_hb2[44] ddc_chain_x300_tb.ddc_chain.i_hb2[43] ddc_chain_x300_tb.ddc_chain.i_hb2[42] ddc_chain_x300_tb.ddc_chain.i_hb2[41] ddc_chain_x300_tb.ddc_chain.i_hb2[40] ddc_chain_x300_tb.ddc_chain.i_hb2[39] ddc_chain_x300_tb.ddc_chain.i_hb2[38] ddc_chain_x300_tb.ddc_chain.i_hb2[37] ddc_chain_x300_tb.ddc_chain.i_hb2[36] ddc_chain_x300_tb.ddc_chain.i_hb2[35] ddc_chain_x300_tb.ddc_chain.i_hb2[34] ddc_chain_x300_tb.ddc_chain.i_hb2[33] ddc_chain_x300_tb.ddc_chain.i_hb2[32] ddc_chain_x300_tb.ddc_chain.i_hb2[31] ddc_chain_x300_tb.ddc_chain.i_hb2[30] ddc_chain_x300_tb.ddc_chain.i_hb2[29] ddc_chain_x300_tb.ddc_chain.i_hb2[28] ddc_chain_x300_tb.ddc_chain.i_hb2[27] ddc_chain_x300_tb.ddc_chain.i_hb2[26] ddc_chain_x300_tb.ddc_chain.i_hb2[25] ddc_chain_x300_tb.ddc_chain.i_hb2[24] ddc_chain_x300_tb.ddc_chain.i_hb2[23] ddc_chain_x300_tb.ddc_chain.i_hb2[22] ddc_chain_x300_tb.ddc_chain.i_hb2[21] ddc_chain_x300_tb.ddc_chain.i_hb2[20] ddc_chain_x300_tb.ddc_chain.i_hb2[19] ddc_chain_x300_tb.ddc_chain.i_hb2[18] ddc_chain_x300_tb.ddc_chain.i_hb2[17] ddc_chain_x300_tb.ddc_chain.i_hb2[16] ddc_chain_x300_tb.ddc_chain.i_hb2[15] ddc_chain_x300_tb.ddc_chain.i_hb2[14] ddc_chain_x300_tb.ddc_chain.i_hb2[13] ddc_chain_x300_tb.ddc_chain.i_hb2[12] ddc_chain_x300_tb.ddc_chain.i_hb2[11] ddc_chain_x300_tb.ddc_chain.i_hb2[10] ddc_chain_x300_tb.ddc_chain.i_hb2[9] ddc_chain_x300_tb.ddc_chain.i_hb2[8] ddc_chain_x300_tb.ddc_chain.i_hb2[7] ddc_chain_x300_tb.ddc_chain.i_hb2[6] ddc_chain_x300_tb.ddc_chain.i_hb2[5] ddc_chain_x300_tb.ddc_chain.i_hb2[4] ddc_chain_x300_tb.ddc_chain.i_hb2[3] ddc_chain_x300_tb.ddc_chain.i_hb2[2] ddc_chain_x300_tb.ddc_chain.i_hb2[1] ddc_chain_x300_tb.ddc_chain.i_hb2[0]
+@28
+ddc_chain_x300_tb.ddc_chain.strobe_hb2
+@420
+#{ddc_chain_x300_tb.ddc_chain.i_hb3[47:0]} ddc_chain_x300_tb.ddc_chain.i_hb3[47] ddc_chain_x300_tb.ddc_chain.i_hb3[46] ddc_chain_x300_tb.ddc_chain.i_hb3[45] ddc_chain_x300_tb.ddc_chain.i_hb3[44] ddc_chain_x300_tb.ddc_chain.i_hb3[43] ddc_chain_x300_tb.ddc_chain.i_hb3[42] ddc_chain_x300_tb.ddc_chain.i_hb3[41] ddc_chain_x300_tb.ddc_chain.i_hb3[40] ddc_chain_x300_tb.ddc_chain.i_hb3[39] ddc_chain_x300_tb.ddc_chain.i_hb3[38] ddc_chain_x300_tb.ddc_chain.i_hb3[37] ddc_chain_x300_tb.ddc_chain.i_hb3[36] ddc_chain_x300_tb.ddc_chain.i_hb3[35] ddc_chain_x300_tb.ddc_chain.i_hb3[34] ddc_chain_x300_tb.ddc_chain.i_hb3[33] ddc_chain_x300_tb.ddc_chain.i_hb3[32] ddc_chain_x300_tb.ddc_chain.i_hb3[31] ddc_chain_x300_tb.ddc_chain.i_hb3[30] ddc_chain_x300_tb.ddc_chain.i_hb3[29] ddc_chain_x300_tb.ddc_chain.i_hb3[28] ddc_chain_x300_tb.ddc_chain.i_hb3[27] ddc_chain_x300_tb.ddc_chain.i_hb3[26] ddc_chain_x300_tb.ddc_chain.i_hb3[25] ddc_chain_x300_tb.ddc_chain.i_hb3[24] ddc_chain_x300_tb.ddc_chain.i_hb3[23] ddc_chain_x300_tb.ddc_chain.i_hb3[22] ddc_chain_x300_tb.ddc_chain.i_hb3[21] ddc_chain_x300_tb.ddc_chain.i_hb3[20] ddc_chain_x300_tb.ddc_chain.i_hb3[19] ddc_chain_x300_tb.ddc_chain.i_hb3[18] ddc_chain_x300_tb.ddc_chain.i_hb3[17] ddc_chain_x300_tb.ddc_chain.i_hb3[16] ddc_chain_x300_tb.ddc_chain.i_hb3[15] ddc_chain_x300_tb.ddc_chain.i_hb3[14] ddc_chain_x300_tb.ddc_chain.i_hb3[13] ddc_chain_x300_tb.ddc_chain.i_hb3[12] ddc_chain_x300_tb.ddc_chain.i_hb3[11] ddc_chain_x300_tb.ddc_chain.i_hb3[10] ddc_chain_x300_tb.ddc_chain.i_hb3[9] ddc_chain_x300_tb.ddc_chain.i_hb3[8] ddc_chain_x300_tb.ddc_chain.i_hb3[7] ddc_chain_x300_tb.ddc_chain.i_hb3[6] ddc_chain_x300_tb.ddc_chain.i_hb3[5] ddc_chain_x300_tb.ddc_chain.i_hb3[4] ddc_chain_x300_tb.ddc_chain.i_hb3[3] ddc_chain_x300_tb.ddc_chain.i_hb3[2] ddc_chain_x300_tb.ddc_chain.i_hb3[1] ddc_chain_x300_tb.ddc_chain.i_hb3[0]
+@28
+ddc_chain_x300_tb.ddc_chain.strobe_hb3
+@420
+ddc_chain_x300_tb.ddc_chain.i_unscaled[23:0]
+#{ddc_chain_x300_tb.ddc_chain.i_scaled[42:0]} ddc_chain_x300_tb.ddc_chain.i_scaled[42] ddc_chain_x300_tb.ddc_chain.i_scaled[41] ddc_chain_x300_tb.ddc_chain.i_scaled[40] ddc_chain_x300_tb.ddc_chain.i_scaled[39] ddc_chain_x300_tb.ddc_chain.i_scaled[38] ddc_chain_x300_tb.ddc_chain.i_scaled[37] ddc_chain_x300_tb.ddc_chain.i_scaled[36] ddc_chain_x300_tb.ddc_chain.i_scaled[35] ddc_chain_x300_tb.ddc_chain.i_scaled[34] ddc_chain_x300_tb.ddc_chain.i_scaled[33] ddc_chain_x300_tb.ddc_chain.i_scaled[32] ddc_chain_x300_tb.ddc_chain.i_scaled[31] ddc_chain_x300_tb.ddc_chain.i_scaled[30] ddc_chain_x300_tb.ddc_chain.i_scaled[29] ddc_chain_x300_tb.ddc_chain.i_scaled[28] ddc_chain_x300_tb.ddc_chain.i_scaled[27] ddc_chain_x300_tb.ddc_chain.i_scaled[26] ddc_chain_x300_tb.ddc_chain.i_scaled[25] ddc_chain_x300_tb.ddc_chain.i_scaled[24] ddc_chain_x300_tb.ddc_chain.i_scaled[23] ddc_chain_x300_tb.ddc_chain.i_scaled[22] ddc_chain_x300_tb.ddc_chain.i_scaled[21] ddc_chain_x300_tb.ddc_chain.i_scaled[20] ddc_chain_x300_tb.ddc_chain.i_scaled[19] ddc_chain_x300_tb.ddc_chain.i_scaled[18] ddc_chain_x300_tb.ddc_chain.i_scaled[17] ddc_chain_x300_tb.ddc_chain.i_scaled[16] ddc_chain_x300_tb.ddc_chain.i_scaled[15] ddc_chain_x300_tb.ddc_chain.i_scaled[14] ddc_chain_x300_tb.ddc_chain.i_scaled[13] ddc_chain_x300_tb.ddc_chain.i_scaled[12] ddc_chain_x300_tb.ddc_chain.i_scaled[11] ddc_chain_x300_tb.ddc_chain.i_scaled[10] ddc_chain_x300_tb.ddc_chain.i_scaled[9] ddc_chain_x300_tb.ddc_chain.i_scaled[8] ddc_chain_x300_tb.ddc_chain.i_scaled[7] ddc_chain_x300_tb.ddc_chain.i_scaled[6] ddc_chain_x300_tb.ddc_chain.i_scaled[5] ddc_chain_x300_tb.ddc_chain.i_scaled[4] ddc_chain_x300_tb.ddc_chain.i_scaled[3] ddc_chain_x300_tb.ddc_chain.i_scaled[2] ddc_chain_x300_tb.ddc_chain.i_scaled[1] ddc_chain_x300_tb.ddc_chain.i_scaled[0]
+@200
+-
+@8420
+#{ddc_chain_x300_tb.ddc_chain.i_cic[23:0]} ddc_chain_x300_tb.ddc_chain.i_cic[23] ddc_chain_x300_tb.ddc_chain.i_cic[22] ddc_chain_x300_tb.ddc_chain.i_cic[21] ddc_chain_x300_tb.ddc_chain.i_cic[20] ddc_chain_x300_tb.ddc_chain.i_cic[19] ddc_chain_x300_tb.ddc_chain.i_cic[18] ddc_chain_x300_tb.ddc_chain.i_cic[17] ddc_chain_x300_tb.ddc_chain.i_cic[16] ddc_chain_x300_tb.ddc_chain.i_cic[15] ddc_chain_x300_tb.ddc_chain.i_cic[14] ddc_chain_x300_tb.ddc_chain.i_cic[13] ddc_chain_x300_tb.ddc_chain.i_cic[12] ddc_chain_x300_tb.ddc_chain.i_cic[11] ddc_chain_x300_tb.ddc_chain.i_cic[10] ddc_chain_x300_tb.ddc_chain.i_cic[9] ddc_chain_x300_tb.ddc_chain.i_cic[8] ddc_chain_x300_tb.ddc_chain.i_cic[7] ddc_chain_x300_tb.ddc_chain.i_cic[6] ddc_chain_x300_tb.ddc_chain.i_cic[5] ddc_chain_x300_tb.ddc_chain.i_cic[4] ddc_chain_x300_tb.ddc_chain.i_cic[3] ddc_chain_x300_tb.ddc_chain.i_cic[2] ddc_chain_x300_tb.ddc_chain.i_cic[1] ddc_chain_x300_tb.ddc_chain.i_cic[0]
+@20000
+-
+@8420
+#{ddc_chain_x300_tb.ddc_chain.i_hb1[46:0]} ddc_chain_x300_tb.ddc_chain.i_hb1[46] ddc_chain_x300_tb.ddc_chain.i_hb1[45] ddc_chain_x300_tb.ddc_chain.i_hb1[44] ddc_chain_x300_tb.ddc_chain.i_hb1[43] ddc_chain_x300_tb.ddc_chain.i_hb1[42] ddc_chain_x300_tb.ddc_chain.i_hb1[41] ddc_chain_x300_tb.ddc_chain.i_hb1[40] ddc_chain_x300_tb.ddc_chain.i_hb1[39] ddc_chain_x300_tb.ddc_chain.i_hb1[38] ddc_chain_x300_tb.ddc_chain.i_hb1[37] ddc_chain_x300_tb.ddc_chain.i_hb1[36] ddc_chain_x300_tb.ddc_chain.i_hb1[35] ddc_chain_x300_tb.ddc_chain.i_hb1[34] ddc_chain_x300_tb.ddc_chain.i_hb1[33] ddc_chain_x300_tb.ddc_chain.i_hb1[32] ddc_chain_x300_tb.ddc_chain.i_hb1[31] ddc_chain_x300_tb.ddc_chain.i_hb1[30] ddc_chain_x300_tb.ddc_chain.i_hb1[29] ddc_chain_x300_tb.ddc_chain.i_hb1[28] ddc_chain_x300_tb.ddc_chain.i_hb1[27] ddc_chain_x300_tb.ddc_chain.i_hb1[26] ddc_chain_x300_tb.ddc_chain.i_hb1[25] ddc_chain_x300_tb.ddc_chain.i_hb1[24] ddc_chain_x300_tb.ddc_chain.i_hb1[23] ddc_chain_x300_tb.ddc_chain.i_hb1[22] ddc_chain_x300_tb.ddc_chain.i_hb1[21] ddc_chain_x300_tb.ddc_chain.i_hb1[20] ddc_chain_x300_tb.ddc_chain.i_hb1[19] ddc_chain_x300_tb.ddc_chain.i_hb1[18] ddc_chain_x300_tb.ddc_chain.i_hb1[17] ddc_chain_x300_tb.ddc_chain.i_hb1[16] ddc_chain_x300_tb.ddc_chain.i_hb1[15] ddc_chain_x300_tb.ddc_chain.i_hb1[14] ddc_chain_x300_tb.ddc_chain.i_hb1[13] ddc_chain_x300_tb.ddc_chain.i_hb1[12] ddc_chain_x300_tb.ddc_chain.i_hb1[11] ddc_chain_x300_tb.ddc_chain.i_hb1[10] ddc_chain_x300_tb.ddc_chain.i_hb1[9] ddc_chain_x300_tb.ddc_chain.i_hb1[8] ddc_chain_x300_tb.ddc_chain.i_hb1[7] ddc_chain_x300_tb.ddc_chain.i_hb1[6] ddc_chain_x300_tb.ddc_chain.i_hb1[5] ddc_chain_x300_tb.ddc_chain.i_hb1[4] ddc_chain_x300_tb.ddc_chain.i_hb1[3] ddc_chain_x300_tb.ddc_chain.i_hb1[2] ddc_chain_x300_tb.ddc_chain.i_hb1[1] ddc_chain_x300_tb.ddc_chain.i_hb1[0]
+@20000
+-
+@8420
+#{ddc_chain_x300_tb.ddc_chain.i_hb2[46:0]} ddc_chain_x300_tb.ddc_chain.i_hb2[46] ddc_chain_x300_tb.ddc_chain.i_hb2[45] ddc_chain_x300_tb.ddc_chain.i_hb2[44] ddc_chain_x300_tb.ddc_chain.i_hb2[43] ddc_chain_x300_tb.ddc_chain.i_hb2[42] ddc_chain_x300_tb.ddc_chain.i_hb2[41] ddc_chain_x300_tb.ddc_chain.i_hb2[40] ddc_chain_x300_tb.ddc_chain.i_hb2[39] ddc_chain_x300_tb.ddc_chain.i_hb2[38] ddc_chain_x300_tb.ddc_chain.i_hb2[37] ddc_chain_x300_tb.ddc_chain.i_hb2[36] ddc_chain_x300_tb.ddc_chain.i_hb2[35] ddc_chain_x300_tb.ddc_chain.i_hb2[34] ddc_chain_x300_tb.ddc_chain.i_hb2[33] ddc_chain_x300_tb.ddc_chain.i_hb2[32] ddc_chain_x300_tb.ddc_chain.i_hb2[31] ddc_chain_x300_tb.ddc_chain.i_hb2[30] ddc_chain_x300_tb.ddc_chain.i_hb2[29] ddc_chain_x300_tb.ddc_chain.i_hb2[28] ddc_chain_x300_tb.ddc_chain.i_hb2[27] ddc_chain_x300_tb.ddc_chain.i_hb2[26] ddc_chain_x300_tb.ddc_chain.i_hb2[25] ddc_chain_x300_tb.ddc_chain.i_hb2[24] ddc_chain_x300_tb.ddc_chain.i_hb2[23] ddc_chain_x300_tb.ddc_chain.i_hb2[22] ddc_chain_x300_tb.ddc_chain.i_hb2[21] ddc_chain_x300_tb.ddc_chain.i_hb2[20] ddc_chain_x300_tb.ddc_chain.i_hb2[19] ddc_chain_x300_tb.ddc_chain.i_hb2[18] ddc_chain_x300_tb.ddc_chain.i_hb2[17] ddc_chain_x300_tb.ddc_chain.i_hb2[16] ddc_chain_x300_tb.ddc_chain.i_hb2[15] ddc_chain_x300_tb.ddc_chain.i_hb2[14] ddc_chain_x300_tb.ddc_chain.i_hb2[13] ddc_chain_x300_tb.ddc_chain.i_hb2[12] ddc_chain_x300_tb.ddc_chain.i_hb2[11] ddc_chain_x300_tb.ddc_chain.i_hb2[10] ddc_chain_x300_tb.ddc_chain.i_hb2[9] ddc_chain_x300_tb.ddc_chain.i_hb2[8] ddc_chain_x300_tb.ddc_chain.i_hb2[7] ddc_chain_x300_tb.ddc_chain.i_hb2[6] ddc_chain_x300_tb.ddc_chain.i_hb2[5] ddc_chain_x300_tb.ddc_chain.i_hb2[4] ddc_chain_x300_tb.ddc_chain.i_hb2[3] ddc_chain_x300_tb.ddc_chain.i_hb2[2] ddc_chain_x300_tb.ddc_chain.i_hb2[1] ddc_chain_x300_tb.ddc_chain.i_hb2[0]
+@20000
+-
+@8420
+#{ddc_chain_x300_tb.ddc_chain.i_hb3[47:0]} ddc_chain_x300_tb.ddc_chain.i_hb3[47] ddc_chain_x300_tb.ddc_chain.i_hb3[46] ddc_chain_x300_tb.ddc_chain.i_hb3[45] ddc_chain_x300_tb.ddc_chain.i_hb3[44] ddc_chain_x300_tb.ddc_chain.i_hb3[43] ddc_chain_x300_tb.ddc_chain.i_hb3[42] ddc_chain_x300_tb.ddc_chain.i_hb3[41] ddc_chain_x300_tb.ddc_chain.i_hb3[40] ddc_chain_x300_tb.ddc_chain.i_hb3[39] ddc_chain_x300_tb.ddc_chain.i_hb3[38] ddc_chain_x300_tb.ddc_chain.i_hb3[37] ddc_chain_x300_tb.ddc_chain.i_hb3[36] ddc_chain_x300_tb.ddc_chain.i_hb3[35] ddc_chain_x300_tb.ddc_chain.i_hb3[34] ddc_chain_x300_tb.ddc_chain.i_hb3[33] ddc_chain_x300_tb.ddc_chain.i_hb3[32] ddc_chain_x300_tb.ddc_chain.i_hb3[31] ddc_chain_x300_tb.ddc_chain.i_hb3[30] ddc_chain_x300_tb.ddc_chain.i_hb3[29] ddc_chain_x300_tb.ddc_chain.i_hb3[28] ddc_chain_x300_tb.ddc_chain.i_hb3[27] ddc_chain_x300_tb.ddc_chain.i_hb3[26] ddc_chain_x300_tb.ddc_chain.i_hb3[25] ddc_chain_x300_tb.ddc_chain.i_hb3[24] ddc_chain_x300_tb.ddc_chain.i_hb3[23] ddc_chain_x300_tb.ddc_chain.i_hb3[22] ddc_chain_x300_tb.ddc_chain.i_hb3[21] ddc_chain_x300_tb.ddc_chain.i_hb3[20] ddc_chain_x300_tb.ddc_chain.i_hb3[19] ddc_chain_x300_tb.ddc_chain.i_hb3[18] ddc_chain_x300_tb.ddc_chain.i_hb3[17] ddc_chain_x300_tb.ddc_chain.i_hb3[16] ddc_chain_x300_tb.ddc_chain.i_hb3[15] ddc_chain_x300_tb.ddc_chain.i_hb3[14] ddc_chain_x300_tb.ddc_chain.i_hb3[13] ddc_chain_x300_tb.ddc_chain.i_hb3[12] ddc_chain_x300_tb.ddc_chain.i_hb3[11] ddc_chain_x300_tb.ddc_chain.i_hb3[10] ddc_chain_x300_tb.ddc_chain.i_hb3[9] ddc_chain_x300_tb.ddc_chain.i_hb3[8] ddc_chain_x300_tb.ddc_chain.i_hb3[7] ddc_chain_x300_tb.ddc_chain.i_hb3[6] ddc_chain_x300_tb.ddc_chain.i_hb3[5] ddc_chain_x300_tb.ddc_chain.i_hb3[4] ddc_chain_x300_tb.ddc_chain.i_hb3[3] ddc_chain_x300_tb.ddc_chain.i_hb3[2] ddc_chain_x300_tb.ddc_chain.i_hb3[1] ddc_chain_x300_tb.ddc_chain.i_hb3[0]
+@20000
+-
+@8420
+ddc_chain_x300_tb.ddc_chain.i_unscaled[23:0]
+@20000
+-
+@8420
+#{ddc_chain_x300_tb.ddc_chain.i_scaled[42:0]} ddc_chain_x300_tb.ddc_chain.i_scaled[42] ddc_chain_x300_tb.ddc_chain.i_scaled[41] ddc_chain_x300_tb.ddc_chain.i_scaled[40] ddc_chain_x300_tb.ddc_chain.i_scaled[39] ddc_chain_x300_tb.ddc_chain.i_scaled[38] ddc_chain_x300_tb.ddc_chain.i_scaled[37] ddc_chain_x300_tb.ddc_chain.i_scaled[36] ddc_chain_x300_tb.ddc_chain.i_scaled[35] ddc_chain_x300_tb.ddc_chain.i_scaled[34] ddc_chain_x300_tb.ddc_chain.i_scaled[33] ddc_chain_x300_tb.ddc_chain.i_scaled[32] ddc_chain_x300_tb.ddc_chain.i_scaled[31] ddc_chain_x300_tb.ddc_chain.i_scaled[30] ddc_chain_x300_tb.ddc_chain.i_scaled[29] ddc_chain_x300_tb.ddc_chain.i_scaled[28] ddc_chain_x300_tb.ddc_chain.i_scaled[27] ddc_chain_x300_tb.ddc_chain.i_scaled[26] ddc_chain_x300_tb.ddc_chain.i_scaled[25] ddc_chain_x300_tb.ddc_chain.i_scaled[24] ddc_chain_x300_tb.ddc_chain.i_scaled[23] ddc_chain_x300_tb.ddc_chain.i_scaled[22] ddc_chain_x300_tb.ddc_chain.i_scaled[21] ddc_chain_x300_tb.ddc_chain.i_scaled[20] ddc_chain_x300_tb.ddc_chain.i_scaled[19] ddc_chain_x300_tb.ddc_chain.i_scaled[18] ddc_chain_x300_tb.ddc_chain.i_scaled[17] ddc_chain_x300_tb.ddc_chain.i_scaled[16] ddc_chain_x300_tb.ddc_chain.i_scaled[15] ddc_chain_x300_tb.ddc_chain.i_scaled[14] ddc_chain_x300_tb.ddc_chain.i_scaled[13] ddc_chain_x300_tb.ddc_chain.i_scaled[12] ddc_chain_x300_tb.ddc_chain.i_scaled[11] ddc_chain_x300_tb.ddc_chain.i_scaled[10] ddc_chain_x300_tb.ddc_chain.i_scaled[9] ddc_chain_x300_tb.ddc_chain.i_scaled[8] ddc_chain_x300_tb.ddc_chain.i_scaled[7] ddc_chain_x300_tb.ddc_chain.i_scaled[6] ddc_chain_x300_tb.ddc_chain.i_scaled[5] ddc_chain_x300_tb.ddc_chain.i_scaled[4] ddc_chain_x300_tb.ddc_chain.i_scaled[3] ddc_chain_x300_tb.ddc_chain.i_scaled[2] ddc_chain_x300_tb.ddc_chain.i_scaled[1] ddc_chain_x300_tb.ddc_chain.i_scaled[0]
+@20000
+-
+@8420
+#{ddc_chain_x300_tb.ddc_chain.i_clip[23:0]} ddc_chain_x300_tb.ddc_chain.i_clip[23] ddc_chain_x300_tb.ddc_chain.i_clip[22] ddc_chain_x300_tb.ddc_chain.i_clip[21] ddc_chain_x300_tb.ddc_chain.i_clip[20] ddc_chain_x300_tb.ddc_chain.i_clip[19] ddc_chain_x300_tb.ddc_chain.i_clip[18] ddc_chain_x300_tb.ddc_chain.i_clip[17] ddc_chain_x300_tb.ddc_chain.i_clip[16] ddc_chain_x300_tb.ddc_chain.i_clip[15] ddc_chain_x300_tb.ddc_chain.i_clip[14] ddc_chain_x300_tb.ddc_chain.i_clip[13] ddc_chain_x300_tb.ddc_chain.i_clip[12] ddc_chain_x300_tb.ddc_chain.i_clip[11] ddc_chain_x300_tb.ddc_chain.i_clip[10] ddc_chain_x300_tb.ddc_chain.i_clip[9] ddc_chain_x300_tb.ddc_chain.i_clip[8] ddc_chain_x300_tb.ddc_chain.i_clip[7] ddc_chain_x300_tb.ddc_chain.i_clip[6] ddc_chain_x300_tb.ddc_chain.i_clip[5] ddc_chain_x300_tb.ddc_chain.i_clip[4] ddc_chain_x300_tb.ddc_chain.i_clip[3] ddc_chain_x300_tb.ddc_chain.i_clip[2] ddc_chain_x300_tb.ddc_chain.i_clip[1] ddc_chain_x300_tb.ddc_chain.i_clip[0]
+@20000
+-
+@28
+ddc_chain_x300_tb.ddc_chain.strobe_unscaled
+ddc_chain_x300_tb.ddc_chain.strobe_scaled
+ddc_chain_x300_tb.ddc_chain.strobe_clip
+ddc_chain_x300_tb.ddc_chain.strobe
+ddc_chain_x300_tb.ddc_chain.clip_i.clip.overflow
+@8420
+#{ddc_chain_x300_tb.ddc_chain.round_i.out[15:0]} ddc_chain_x300_tb.ddc_chain.round_i.out[15] ddc_chain_x300_tb.ddc_chain.round_i.out[14] ddc_chain_x300_tb.ddc_chain.round_i.out[13] ddc_chain_x300_tb.ddc_chain.round_i.out[12] ddc_chain_x300_tb.ddc_chain.round_i.out[11] ddc_chain_x300_tb.ddc_chain.round_i.out[10] ddc_chain_x300_tb.ddc_chain.round_i.out[9] ddc_chain_x300_tb.ddc_chain.round_i.out[8] ddc_chain_x300_tb.ddc_chain.round_i.out[7] ddc_chain_x300_tb.ddc_chain.round_i.out[6] ddc_chain_x300_tb.ddc_chain.round_i.out[5] ddc_chain_x300_tb.ddc_chain.round_i.out[4] ddc_chain_x300_tb.ddc_chain.round_i.out[3] ddc_chain_x300_tb.ddc_chain.round_i.out[2] ddc_chain_x300_tb.ddc_chain.round_i.out[1] ddc_chain_x300_tb.ddc_chain.round_i.out[0]
+@20000
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+@8420
+#{ddc_chain_x300_tb.ddc_chain.i_cordic[24:0]} ddc_chain_x300_tb.ddc_chain.i_cordic[24] ddc_chain_x300_tb.ddc_chain.i_cordic[23] ddc_chain_x300_tb.ddc_chain.i_cordic[22] ddc_chain_x300_tb.ddc_chain.i_cordic[21] ddc_chain_x300_tb.ddc_chain.i_cordic[20] ddc_chain_x300_tb.ddc_chain.i_cordic[19] ddc_chain_x300_tb.ddc_chain.i_cordic[18] ddc_chain_x300_tb.ddc_chain.i_cordic[17] ddc_chain_x300_tb.ddc_chain.i_cordic[16] ddc_chain_x300_tb.ddc_chain.i_cordic[15] ddc_chain_x300_tb.ddc_chain.i_cordic[14] ddc_chain_x300_tb.ddc_chain.i_cordic[13] ddc_chain_x300_tb.ddc_chain.i_cordic[12] ddc_chain_x300_tb.ddc_chain.i_cordic[11] ddc_chain_x300_tb.ddc_chain.i_cordic[10] ddc_chain_x300_tb.ddc_chain.i_cordic[9] ddc_chain_x300_tb.ddc_chain.i_cordic[8] ddc_chain_x300_tb.ddc_chain.i_cordic[7] ddc_chain_x300_tb.ddc_chain.i_cordic[6] ddc_chain_x300_tb.ddc_chain.i_cordic[5] ddc_chain_x300_tb.ddc_chain.i_cordic[4] ddc_chain_x300_tb.ddc_chain.i_cordic[3] ddc_chain_x300_tb.ddc_chain.i_cordic[2] ddc_chain_x300_tb.ddc_chain.i_cordic[1] ddc_chain_x300_tb.ddc_chain.i_cordic[0]
+@20000
+-
+-
+@8420
+#{ddc_chain_x300_tb.ddc_chain.i_cordic_clip[23:0]} ddc_chain_x300_tb.ddc_chain.i_cordic_clip[23] ddc_chain_x300_tb.ddc_chain.i_cordic_clip[22] ddc_chain_x300_tb.ddc_chain.i_cordic_clip[21] ddc_chain_x300_tb.ddc_chain.i_cordic_clip[20] ddc_chain_x300_tb.ddc_chain.i_cordic_clip[19] ddc_chain_x300_tb.ddc_chain.i_cordic_clip[18] ddc_chain_x300_tb.ddc_chain.i_cordic_clip[17] ddc_chain_x300_tb.ddc_chain.i_cordic_clip[16] ddc_chain_x300_tb.ddc_chain.i_cordic_clip[15] ddc_chain_x300_tb.ddc_chain.i_cordic_clip[14] ddc_chain_x300_tb.ddc_chain.i_cordic_clip[13] ddc_chain_x300_tb.ddc_chain.i_cordic_clip[12] ddc_chain_x300_tb.ddc_chain.i_cordic_clip[11] ddc_chain_x300_tb.ddc_chain.i_cordic_clip[10] ddc_chain_x300_tb.ddc_chain.i_cordic_clip[9] ddc_chain_x300_tb.ddc_chain.i_cordic_clip[8] ddc_chain_x300_tb.ddc_chain.i_cordic_clip[7] ddc_chain_x300_tb.ddc_chain.i_cordic_clip[6] ddc_chain_x300_tb.ddc_chain.i_cordic_clip[5] ddc_chain_x300_tb.ddc_chain.i_cordic_clip[4] ddc_chain_x300_tb.ddc_chain.i_cordic_clip[3] ddc_chain_x300_tb.ddc_chain.i_cordic_clip[2] ddc_chain_x300_tb.ddc_chain.i_cordic_clip[1] ddc_chain_x300_tb.ddc_chain.i_cordic_clip[0]
+@20000
+-
+@20001
+-
+[pattern_trace] 1
+[pattern_trace] 0
diff --git a/fpga/usrp3/lib/sim/dsp/ddc_chain_x300/dctest/run_isim b/fpga/usrp3/lib/sim/dsp/ddc_chain_x300/dctest/run_isim
new file mode 100755
index 000000000..6a3e532c6
--- /dev/null
+++ b/fpga/usrp3/lib/sim/dsp/ddc_chain_x300/dctest/run_isim
@@ -0,0 +1,17 @@
+rm -rf fuse* *.exe isim
+vlogcomp -work work ${XILINX}/verilog/src/glbl.v
+vlogcomp -work work --sourcelibext .v \
+	 --sourcelibdir ../../../lib/dsp \
+         --sourcelibdir ../../../lib/control \
+	 --sourcelibdir ../../../top/x300/coregen_dsp \
+	 --sourcelibdir ${XILINX}/verilog/src/unimacro \
+	 ../../../lib/dsp/ddc_chain_x300_tb.v
+
+
+
+fuse work.ddc_chain_x300_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o ddc_chain_x300_tb.exe
+
+# run the simulation scrip
+./ddc_chain_x300_tb.exe  -tclbatch simcmds.tcl  # -gui 
+
+
diff --git a/fpga/usrp3/lib/sim/dsp/ddc_chain_x300/dctest/simcmds.tcl b/fpga/usrp3/lib/sim/dsp/ddc_chain_x300/dctest/simcmds.tcl
new file mode 100755
index 000000000..3dcfd3eaf
--- /dev/null
+++ b/fpga/usrp3/lib/sim/dsp/ddc_chain_x300/dctest/simcmds.tcl
@@ -0,0 +1,9 @@
+# file: simcmds.tcl
+
+# create the simulation script
+#vcd dumpfile isim.vcd
+#vcd dumpvars -m /bus_clk_gen_tb -l 0
+#wave add /
+run 1 s
+quit
+
diff --git a/fpga/usrp3/lib/sim/dsp/ddc_chain_x300/ddc_chain_x300_tb.v b/fpga/usrp3/lib/sim/dsp/ddc_chain_x300/ddc_chain_x300_tb.v
new file mode 100644
index 000000000..901844d66
--- /dev/null
+++ b/fpga/usrp3/lib/sim/dsp/ddc_chain_x300/ddc_chain_x300_tb.v
@@ -0,0 +1,64 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+`timescale 1ns/1ps
+
+module ddc_chain_x300_tb();
+   
+`ifdef ISIM
+`else //iverilog implied.
+//   xlnx_glbl glbl (.GSR(),.GTS());
+`endif
+   
+   localparam SR_TX_DSP        = 8;
+
+   reg clk    = 0;
+   reg reset  = 1;
+   
+   always #10 clk = ~clk;
+   
+   initial $dumpfile("ddc_chain_x300_tb.vcd");
+   initial $dumpvars(0,ddc_chain_x300_tb);
+   reg run = 0;
+   wire strobe;
+   
+   initial
+     begin
+	#1000 reset = 0;
+	@(posedge clk);
+	set_addr <= 0; set_data <= 32'd8434349; set_stb <= 1; @(posedge clk); // CORDIC
+	set_addr <= 1; set_data <= 18'd19800; set_stb <= 1; @(posedge clk); // Scale factor
+	set_addr <= 2; set_data <= 10'h003; set_stb <= 1; @(posedge clk); // Decim control
+	set_addr <= 3; set_data <= 0; set_stb <= 1; @(posedge clk); // Swap iq
+	set_addr <= 4; set_data <= 0; set_stb <= 1; @(posedge clk); // filter taps
+	set_stb <= 0;
+		
+	repeat(10)
+	  @(posedge clk);
+	run <= 1'b1;
+	#30000;
+	$finish;
+     end
+   
+   reg [7:0]   set_addr;
+   reg [31:0]  set_data;
+   reg 	       set_stb = 1'b0;
+
+   wire [15:0] i_out, q_out;
+   wire [23:0] rx_fe_i, rx_fe_q;
+
+   assign rx_fe_i = 24'd8388607;
+   assign rx_fe_q = 24'd8388607;
+   //assign rx_fe_q = 0;
+   
+   ddc_chain_x300 #(.BASE(0), .DSPNO(0), .WIDTH(24)) ddc_chain
+     (.clk(clk), .rst(reset), .clr(1'b0),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q),
+      .sample({i_out,q_out}), .run(run), .strobe(strobe),
+      .debug() );
+   
+endmodule // new_tx_tb
diff --git a/fpga/usrp3/lib/sim/dsp/duc_chain_x300/dctest/.gitignore b/fpga/usrp3/lib/sim/dsp/duc_chain_x300/dctest/.gitignore
new file mode 100644
index 000000000..7826d75e2
--- /dev/null
+++ b/fpga/usrp3/lib/sim/dsp/duc_chain_x300/dctest/.gitignore
@@ -0,0 +1,4 @@
+fuse*
+isim*
+*.exe
+*.wcfg
diff --git a/fpga/usrp3/lib/sim/dsp/duc_chain_x300/dctest/run_isim b/fpga/usrp3/lib/sim/dsp/duc_chain_x300/dctest/run_isim
new file mode 100755
index 000000000..0672e32a6
--- /dev/null
+++ b/fpga/usrp3/lib/sim/dsp/duc_chain_x300/dctest/run_isim
@@ -0,0 +1,17 @@
+rm -rf fuse* *.exe isim
+vlogcomp -work work ${XILINX}/verilog/src/glbl.v
+vlogcomp -work work --sourcelibext .v \
+	 --sourcelibdir ../../../lib/dsp \
+         --sourcelibdir ../../../lib/control \
+	 --sourcelibdir ../../../top/x300/coregen_dsp \
+	 --sourcelibdir ${XILINX}/verilog/src/unimacro \
+	 ../../../lib/dsp/duc_chain_x300_tb.v
+
+
+
+fuse work.duc_chain_x300_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o duc_chain_x300_tb.exe
+
+# run the simulation scrip
+./duc_chain_x300_tb.exe  -tclbatch simcmds.tcl  # -gui 
+
+
diff --git a/fpga/usrp3/lib/sim/dsp/duc_chain_x300/dctest/simcmds.tcl b/fpga/usrp3/lib/sim/dsp/duc_chain_x300/dctest/simcmds.tcl
new file mode 100755
index 000000000..3dcfd3eaf
--- /dev/null
+++ b/fpga/usrp3/lib/sim/dsp/duc_chain_x300/dctest/simcmds.tcl
@@ -0,0 +1,9 @@
+# file: simcmds.tcl
+
+# create the simulation script
+#vcd dumpfile isim.vcd
+#vcd dumpvars -m /bus_clk_gen_tb -l 0
+#wave add /
+run 1 s
+quit
+
diff --git a/fpga/usrp3/lib/sim/dsp/hb47_int/hb47_int_tb.v b/fpga/usrp3/lib/sim/dsp/hb47_int/hb47_int_tb.v
new file mode 100644
index 000000000..b64b5b7dc
--- /dev/null
+++ b/fpga/usrp3/lib/sim/dsp/hb47_int/hb47_int_tb.v
@@ -0,0 +1,136 @@
+//
+// Copyright 2016 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+`timescale 1ns/1ps
+
+module hb47_int_tb();
+
+   wire GSR, GTS;
+   glbl glbl( );
+
+   reg 	clk = 0;
+   reg 	rst;
+   reg 	bypass;
+   reg 	run;
+
+   wire stb_in;
+   reg 	stb_out;
+   reg [7:0] cpo;
+
+   reg [17:0] data_in;
+
+   wire [17:0] data_out_dsp48a; 
+   wire [17:0] data_out_dsp48e;
+   
+   reg [15:0]  freq = 500;
+
+   integer     x = 0, y =0;
+
+
+
+   always #100 clk = ~clk;
+
+   // SPARTAN6 / DSP48A
+    hb47_int
+      #(.WIDTH(18),
+	.DEVICE("SPARTAN6"))
+	hb47_int_i0
+	(
+	 .clk(clk),
+	 .rst(rst),
+	 .bypass(bypass),
+	 .stb_in(stb_in),
+	 .data_in(data_in),
+	 .output_rate(cpo),
+	 .stb_out(stb_out),
+	 .data_out(data_out_dsp48a)
+	 );
+
+   // SERIES7 / DSP48E
+    hb47_int
+      #(.WIDTH(18),
+	.DEVICE("7SERIES"))
+	hb47_int_i1
+	(
+	 .clk(clk),
+	 .rst(rst),
+	 .bypass(bypass),
+	 .stb_in(stb_in),
+	 .data_in(data_in),
+	 .output_rate(cpo),
+	 .stb_out(stb_out),
+	 .data_out(data_out_dsp48e)
+	 );
+
+   always @(negedge clk)
+     if (data_out_dsp48a !== data_out_dsp48e)
+       $display("Output missmatch at %t",$time);
+   
+
+   
+  cic_strober #(.WIDTH(2))
+     hb1_strober(.clock(clk),.reset(rst),.enable(run),.rate(2'd2),
+		 .strobe_fast(stb_out),.strobe_slow(stb_in) );
+
+   initial
+     begin
+	rst <= 1;
+	bypass <= 0;
+	run <= 0;
+	data_in <= 0;
+	stb_out <= 1;
+	cpo <= 1;
+
+	repeat(10) @(posedge clk);
+	rst <= 0;
+	run <= 1;
+
+	for (x=0; x<100000; x=x+1) begin
+	   for (y=0; y<10000; y=y+1)
+	     begin
+		while (stb_in == 1'b0) @(posedge clk);
+		triangle_wave(freq,data_in);
+		@(posedge clk);
+
+	     end
+	   freq = freq * 2;
+	end
+
+	$finish;
+     end // initial begin
+
+
+
+
+   reg signed [18:0] phase_acc = 0;
+   reg 	      direction = 0;
+
+
+   task triangle_wave;
+      input [15:0] inc;
+      output [17:0] data_out;
+
+      begin
+	 if (direction) begin
+	    phase_acc = phase_acc - inc;
+	    if (phase_acc < -19'sh20000) begin
+	       direction = 0;
+	       phase_acc = phase_acc + inc;
+	    end
+	 end else begin
+	    phase_acc = phase_acc + inc;
+	    if (phase_acc > 19'sh1ffff) begin
+	       direction = 1;
+	       phase_acc = phase_acc - inc;
+	    end
+	 end
+	 data_out = phase_acc[17:0];
+      end
+
+   endtask // triangle_wave
+
+
+
+endmodule // hb47_int_tb
diff --git a/fpga/usrp3/lib/sim/dsp/mult_add_clip/Makefile b/fpga/usrp3/lib/sim/dsp/mult_add_clip/Makefile
new file mode 100644
index 000000000..f0cdb3704
--- /dev/null
+++ b/fpga/usrp3/lib/sim/dsp/mult_add_clip/Makefile
@@ -0,0 +1,45 @@
+#
+# Copyright 2018 Ettus Research, A National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+#-------------------------------------------------
+# Top-of-Makefile
+#-------------------------------------------------
+# Define BASE_DIR to point to the "top" dir
+BASE_DIR = $(abspath ../../../../top)
+# Include viv_sim_preamble after defining BASE_DIR
+include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
+
+#-------------------------------------------------
+# Design Specific
+#-------------------------------------------------
+# Include makefiles and sources for the DUT and its dependencies
+include $(BASE_DIR)/../lib/dsp/Makefile.srcs
+
+DESIGN_SRCS = $(abspath \
+$(DSP_SRCS) \
+)
+
+#-------------------------------------------------
+# Testbench Specific
+#-------------------------------------------------
+# Define only one toplevel module
+SIM_TOP = mult_add_clip_tb
+
+# Add test bench, user design under test, and
+# additional user created files
+SIM_SRCS = $(abspath \
+mult_add_clip_tb.sv \
+)
+
+# MODELSIM_USER_DO = $(abspath wave.do)
+
+#-------------------------------------------------
+# Bottom-of-Makefile
+#-------------------------------------------------
+# Include all simulator specific makefiles here
+# Each should define a unique target to simulate
+# e.g. xsim, vsim, etc and a common "clean" target
+include $(BASE_DIR)/../tools/make/viv_simulator.mak
diff --git a/fpga/usrp3/lib/sim/dsp/mult_add_clip/mult_add_clip_tb.sv b/fpga/usrp3/lib/sim/dsp/mult_add_clip/mult_add_clip_tb.sv
new file mode 100644
index 000000000..47cd1a369
--- /dev/null
+++ b/fpga/usrp3/lib/sim/dsp/mult_add_clip/mult_add_clip_tb.sv
@@ -0,0 +1,137 @@
+//
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Checks a few cases of A*B+C against precomputed values
+// Configurations checked include widths and binary points for
+// rx_frontend_gen3 and tx_frontend_gen3. All latencies for those
+// configurations are checked.
+
+
+`timescale 1ns/1ps
+`define NS_PER_TICK 1
+`define NUM_TEST_CASES 2
+
+`include "sim_exec_report.vh"
+`include "sim_clks_rsts.vh"
+
+module mult_add_clip_tb();
+  `TEST_BENCH_INIT("mult_add_clip_tb", `NUM_TEST_CASES, `NS_PER_TICK);
+  localparam CLK_PERIOD = $ceil(1e9/200e6);
+  `DEFINE_CLK(clk, CLK_PERIOD, 50);
+  `DEFINE_RESET(reset, 0, 100);
+
+  // {RX config, TX config}
+  localparam integer AW[0:1]   = {18,16};
+  localparam integer A_PT[0:1] = {17,15};
+  localparam integer BW[0:1]   = {18,18};
+  localparam integer B_PT[0:1] = {17,17};
+  localparam integer CW[0:1]   = {24,16};
+  localparam integer C_PT[0:1] = {23,15};
+  localparam integer OW        = 24;
+  localparam integer O_PT      = 23;
+  localparam integer NUM_LATENCY = 4;
+  localparam integer NUM_CASES   = 2;
+
+  localparam [23:0] A_VECTOR[0:7] = {24'h000000,
+                                     24'h800000,
+                                     24'h7fffff,
+                                     24'h111111,
+                                     24'h333333,
+                                     24'h111111,
+                                     24'h333333,
+                                     24'h333333};
+  localparam [17:0] B_VECTOR[0:7] = {18'h00000,
+                                     18'h1ffff,
+                                     18'h1ffff,
+                                     18'h10000,
+                                     18'h3ffff,
+                                     18'h3ffff,
+                                     18'h10000,
+                                     18'h10000};
+  localparam [23:0] C_VECTOR[0:7] = {24'h000000,
+                                     24'h880000,
+                                     24'h70ffff,
+                                     24'h000000,
+                                     24'h000000,
+                                     24'h101010,
+                                     24'h101010,
+                                     24'hfffff1};
+  localparam [OW-1:0] O_VECTOR_RX[0:7] = {24'h000000,
+                                          24'h800000,
+                                          24'h7fffff,
+                                          24'h088880,
+                                          24'hffffe6,
+                                          24'h101007,
+                                          24'h29a990,
+                                          24'h199971};
+  localparam [OW-1:0] O_VECTOR_TX[0:7] = {24'h000000,
+                                          24'h800000,
+                                          24'h7fffff,
+                                          24'h088880,
+                                          24'hffffe6,
+                                          24'h100ff7,
+                                          24'h29a980,
+                                          24'h199880};
+
+  logic [23:0] a;
+  logic [17:0] b;
+  logic [23:0] c;
+  wire  [OW-1:0] o[0:NUM_LATENCY*NUM_CASES-1];
+
+  task check_result(integer samp, integer inst);
+    begin
+      string s;
+      if ((samp >= inst) && (samp-inst < 8)) begin
+        $sformat(s, "Incorrect data for RX. Samp = %0d, Latency = %0d, Data = %06x, Expected = %06x", samp, inst, o[inst], O_VECTOR_RX[samp-inst]);
+        `ASSERT_ERROR(o[inst] == O_VECTOR_RX[samp-inst], s);
+        $sformat(s, "Incorrect data for TX. Samp = %0d, Latency = %0d, Data = %06x, Expected = %06x", samp, inst, o[inst+NUM_LATENCY], O_VECTOR_TX[samp-inst]);
+        `ASSERT_ERROR(o[inst+NUM_LATENCY] == O_VECTOR_TX[samp-inst], s);
+      end
+    end
+  endtask
+
+  genvar k, l;
+  generate for (k = 0; k < NUM_CASES; k = k + 1) begin: inst
+    for (l = 0; l < NUM_LATENCY; l = l + 1) begin: latency
+      mult_add_clip #(
+        .WIDTH_A(AW[k]),
+        .BIN_PT_A(A_PT[k]),
+        .WIDTH_B(BW[k]),
+        .BIN_PT_B(B_PT[k]),
+        .WIDTH_C(CW[k]),
+        .BIN_PT_C(C_PT[k]),
+        .WIDTH_O(OW),
+        .BIN_PT_O(O_PT),
+        .LATENCY(l+1)
+      ) dut (
+        .clk(clk), .reset(reset), .CE(1'b1),
+        .A(a[23 -: AW[k]]),
+        .B(b[17 -: BW[k]]),
+        .C(c[23 -: CW[k]]),
+        .O(o[k*NUM_LATENCY+l])
+      );
+    end
+  end endgenerate
+
+  initial begin : tb_main
+    `TEST_CASE_START("Wait for Reset");
+      while (reset) @ (posedge clk);
+    `TEST_CASE_DONE(~reset);
+
+    `TEST_CASE_START("Check products");
+    for (int i = 0; i < (8 + NUM_LATENCY); i = i + 1) begin
+      @(negedge clk);
+      for (int j = 0; j < NUM_LATENCY; j = j + 1) begin
+        check_result(i-1, j); // i-1 because inst = latency - 1
+      end
+      a = A_VECTOR[i % 8];
+      b = B_VECTOR[i % 8];
+      c = C_VECTOR[i % 8];
+    end
+    `TEST_CASE_DONE(1);
+    `TEST_BENCH_DONE;
+  end
+
+endmodule // mult_add_clip_tb
diff --git a/fpga/usrp3/lib/sim/dsp/rx_frontend/rx_frontend_tb.v b/fpga/usrp3/lib/sim/dsp/rx_frontend/rx_frontend_tb.v
new file mode 100644
index 000000000..60a866033
--- /dev/null
+++ b/fpga/usrp3/lib/sim/dsp/rx_frontend/rx_frontend_tb.v
@@ -0,0 +1,50 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+`timescale 1ns/1ns
+module rx_frontend_tb();
+   
+   reg clk, rst;
+
+   initial rst = 1;
+   initial #1000 rst = 0;
+   initial clk = 0;
+   always #5 clk = ~clk;
+   
+   initial $dumpfile("rx_frontend_tb.vcd");
+   initial $dumpvars(0,rx_frontend_tb);
+
+   reg [15:0] adc_in;
+   wire [23:0] adc_out;
+
+   always @(posedge clk)
+     begin
+	if(adc_in[15])
+	  $write("-%d,",-adc_in);
+	else
+	  $write("%d,",adc_in);
+	if(adc_out[23])
+	  $write("-%d\n",-adc_out);
+	else
+	  $write("%d\n",adc_out);
+     end	
+   
+   rx_frontend #(.BASE(0), .IQCOMP_EN(1)) rx_frontend
+     (.clk(clk),.rst(rst),
+      .set_stb(0),.set_addr(0),.set_data(0),
+      .adc_a(adc_in), .adc_ovf_a(0),
+      .adc_b(0), .adc_ovf_b(0),
+      .i_out(adc_out),.q_out(),
+      .run(), .debug());
+
+   always @(posedge clk)
+     if(rst)
+       adc_in <= 0;
+     else
+       adc_in <= adc_in + 4;
+   //adc_in <= (($random % 473) + 23)/4;
+   
+endmodule // rx_frontend_tb
diff --git a/fpga/usrp3/lib/sim/dsp/variable_delay_line/Makefile b/fpga/usrp3/lib/sim/dsp/variable_delay_line/Makefile
new file mode 100644
index 000000000..90733cb5d
--- /dev/null
+++ b/fpga/usrp3/lib/sim/dsp/variable_delay_line/Makefile
@@ -0,0 +1,47 @@
+#
+# Copyright 2018 Ettus Research, A National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+#-------------------------------------------------
+# Top-of-Makefile
+#-------------------------------------------------
+# Define BASE_DIR to point to the "top" dir
+BASE_DIR = $(abspath ../../../../top)
+# Include viv_sim_preamble after defining BASE_DIR
+include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
+
+#-------------------------------------------------
+# Design Specific
+#-------------------------------------------------
+# Include makefiles and sources for the DUT and its dependencies
+include $(BASE_DIR)/../lib/dsp/Makefile.srcs
+include $(BASE_DIR)/../lib/control/Makefile.srcs
+
+DESIGN_SRCS = $(abspath \
+$(DSP_SRCS) \
+$(CONTROL_LIB_SRCS) \
+)
+
+#-------------------------------------------------
+# Testbench Specific
+#-------------------------------------------------
+# Define only one toplevel module
+SIM_TOP = variable_delay_line_tb
+
+# Add test bench, user design under test, and
+# additional user created files
+SIM_SRCS = $(abspath \
+variable_delay_line_tb.sv \
+)
+
+# MODELSIM_USER_DO = $(abspath wave.do)
+
+#-------------------------------------------------
+# Bottom-of-Makefile
+#-------------------------------------------------
+# Include all simulator specific makefiles here
+# Each should define a unique target to simulate
+# e.g. xsim, vsim, etc and a common "clean" target
+include $(BASE_DIR)/../tools/make/viv_simulator.mak
diff --git a/fpga/usrp3/lib/sim/dsp/variable_delay_line/variable_delay_line_tb.sv b/fpga/usrp3/lib/sim/dsp/variable_delay_line/variable_delay_line_tb.sv
new file mode 100644
index 000000000..1691f5b8c
--- /dev/null
+++ b/fpga/usrp3/lib/sim/dsp/variable_delay_line/variable_delay_line_tb.sv
@@ -0,0 +1,117 @@
+//
+// Copyright 2018 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+`timescale 1ns/1ps
+`define NS_PER_TICK 1
+`define NUM_TEST_CASES 4
+
+`include "sim_exec_report.vh"
+`include "sim_clks_rsts.vh"
+`include "sim_axis_lib.svh"
+
+module variable_delay_line_tb();
+  `TEST_BENCH_INIT("variable_delay_line_tb", `NUM_TEST_CASES, `NS_PER_TICK);
+  localparam CLK_PERIOD = $ceil(1e9/166.67e6);
+  `DEFINE_CLK(clk, CLK_PERIOD, 50);
+  `DEFINE_RESET(reset, 0, 100);
+
+  localparam             WIDTH                = 32;
+  localparam [WIDTH-1:0] DEFAULT              = 32'hDEADBEEF;
+  localparam integer     NUM_INST             = 24;
+  localparam integer     DELAYS[0:NUM_INST-1] = {3, 14, 15, 16, 17, 30, 31, 32, 33, 127, 256, 511,
+                                                 3, 14, 15, 16, 17, 30, 31, 32, 33, 127, 256, 511};
+
+  logic             in_stb   [0:NUM_INST-1];
+  logic [WIDTH-1:0] in_samp  [0:NUM_INST-1];
+  wire  [WIDTH-1:0] out_samp [0:NUM_INST-1];
+  logic [31:0]      out_delay[0:NUM_INST-1];
+
+  task push_samp(logic [WIDTH-1:0] word, integer inst);
+    begin
+      //$display("D[%0d]: push(0x%08x)", inst, word);
+      in_samp[inst] = word;
+      in_stb[inst] = 1'b1;
+      @(posedge clk);
+      in_stb[inst] = 1'b0;
+    end
+  endtask
+
+  task change_delay(logic [31:0] delay, integer inst);
+    begin
+      out_delay[inst] = delay;
+      @(posedge clk);               // First stage
+      if (inst/(NUM_INST/2) == 1) @(posedge clk); // Pipeline stage
+      @(negedge clk);
+      //$display("D[%0d]: cd(%0d) = 0x%08x", inst, delay, out_samp[inst]);
+    end
+  endtask
+
+  genvar d;
+  generate for (d = 0; d < NUM_INST; d=d+1) begin: inst
+    variable_delay_line #(
+      .WIDTH(WIDTH), .DEPTH(DELAYS[d]),
+      .DYNAMIC_DELAY(1), .DEFAULT_DATA(DEFAULT), .OUT_REG(d / (NUM_INST/2))
+    ) dut (
+      .clk(clk), .clk_en(1'b1), .reset(reset),
+      .data_in(in_samp[d]), .stb_in(in_stb[d]),
+      .delay(out_delay[d]), .data_out(out_samp[d])
+    );
+  end endgenerate
+
+  initial begin : tb_main
+    string s;
+
+    `TEST_CASE_START("Wait for Reset");
+      for (int k = 0; k < NUM_INST; k=k+1) begin
+        in_stb[k]    = 1'b0;
+        out_delay[k] = 0;
+      end
+      while (reset) @(posedge clk);
+    `TEST_CASE_DONE(~reset);
+
+    `TEST_CASE_START("Check startup state of delay line");
+      for (int k = 0; k < NUM_INST; k=k+1) begin
+        $display("Validating delay line with DEPTH=%0d, OUT_REG=%0d...", DELAYS[k], k/(NUM_INST/2));
+        for (int j = 0; j < DELAYS[k]; j=j+1) begin
+          change_delay(j, k);
+          `ASSERT_ERROR(out_samp[k] == DEFAULT, "Transient delay value incorrect");
+        end
+      end
+    `TEST_CASE_DONE(1);
+
+    `TEST_CASE_START("Check partially filled delay line");
+      for (int k = 0; k < NUM_INST; k=k+1) begin
+        $display("Validating delay line with DEPTH=%0d, OUT_REG=%0d...", DELAYS[k], k/(NUM_INST/2));
+        for (int i = 0; i < DELAYS[k]; i=i+1) begin
+          push_samp(i, k);
+          for (int j = 0; j < DELAYS[k]; j=j+1) begin
+            change_delay(j, k);
+            $sformat(s, "Incorrect data. Samp = %0d, Delay = %0d, Data = %08x", i, j, out_samp[k]);
+            `ASSERT_ERROR(out_samp[k] == (j>i ? DEFAULT : i - j), s);
+          end
+        end
+      end
+    `TEST_CASE_DONE(1);
+
+    `TEST_CASE_START("Check steady state delay line");
+      for (int k = 0; k < NUM_INST; k=k+1) begin
+        $display("Validating delay line with DEPTH=%0d, OUT_REG=%0d...", DELAYS[k], k/(NUM_INST/2));
+        for (int i = 0; i < DELAYS[k]; i=i+1) begin
+          push_samp(i + DELAYS[k], k);
+          for (int j = 0; j < DELAYS[k]; j=j+1) begin
+            change_delay(j, k);
+            $sformat(s, "Incorrect data. Samp = %0d, Delay = %0d, Data = %08x", i, j, out_samp[k]);
+            `ASSERT_ERROR(out_samp[k] == DELAYS[k] + i - j, s);
+          end
+        end
+      end
+    `TEST_CASE_DONE(1);
+
+
+    `TEST_BENCH_DONE;
+
+  end
+endmodule
diff --git a/fpga/usrp3/lib/sim/fifo/axi_dram_fifo/default.wcfg b/fpga/usrp3/lib/sim/fifo/axi_dram_fifo/default.wcfg
new file mode 100644
index 000000000..796071597
--- /dev/null
+++ b/fpga/usrp3/lib/sim/fifo/axi_dram_fifo/default.wcfg
@@ -0,0 +1,412 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="./isim.wdb" id="1" type="auto">
+         <top_modules>
+            <top_module name="axi_dram_fifo_tb" />
+            <top_module name="glbl" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <WVObjectSize size="38" />
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/clk" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk</obj_property>
+      <obj_property name="ObjectShortName">clk</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/reset" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">reset</obj_property>
+      <obj_property name="ObjectShortName">reset</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/clear" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clear</obj_property>
+      <obj_property name="ObjectShortName">clear</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/count_rx" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">count_rx[31:0]</obj_property>
+      <obj_property name="ObjectShortName">count_rx[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/count_tx" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">count_tx[31:0]</obj_property>
+      <obj_property name="ObjectShortName">count_tx[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/i_tdata" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">i_tdata[63:0]</obj_property>
+      <obj_property name="ObjectShortName">i_tdata[63:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/i_tlast" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">i_tlast</obj_property>
+      <obj_property name="ObjectShortName">i_tlast</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/i_tvalid" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">i_tvalid</obj_property>
+      <obj_property name="ObjectShortName">i_tvalid</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/i_tready" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">i_tready</obj_property>
+      <obj_property name="ObjectShortName">i_tready</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/input_state" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">input_state[2:0]</obj_property>
+      <obj_property name="ObjectShortName">input_state[2:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/write_ctrl_ready" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">write_ctrl_ready</obj_property>
+      <obj_property name="ObjectShortName">write_ctrl_ready</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/write_ctrl_valid" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">write_ctrl_valid</obj_property>
+      <obj_property name="ObjectShortName">write_ctrl_valid</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/occupied_input" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">occupied_input[5:0]</obj_property>
+      <obj_property name="ObjectShortName">occupied_input[5:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="group92" type="group">
+      <obj_property name="label">INPUT TIMEOUT</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/input_timeout_count" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">input_timeout_count[7:0]</obj_property>
+         <obj_property name="ObjectShortName">input_timeout_count[7:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/input_timeout_reset" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">input_timeout_reset</obj_property>
+         <obj_property name="ObjectShortName">input_timeout_reset</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/input_timeout_triggered" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">input_timeout_triggered</obj_property>
+         <obj_property name="ObjectShortName">input_timeout_triggered</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group60" type="group">
+      <obj_property name="label">AXI_WADDR</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_dma_master_i/write_addr_state" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">write_addr_state[1:0]</obj_property>
+         <obj_property name="ObjectShortName">write_addr_state[1:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="UseCustomSignalColor">true</obj_property>
+         <obj_property name="CustomSignalColor">#ffff00</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_awid" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_awid[0:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_awid[0:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_awaddr" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_awaddr[31:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_awaddr[31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_awlen" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_awlen[7:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_awlen[7:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_awsize" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_awsize[2:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_awsize[2:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_awburst" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_awburst[1:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_awburst[1:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_awvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_awvalid</obj_property>
+         <obj_property name="ObjectShortName">m_axi_awvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_awready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_awready</obj_property>
+         <obj_property name="ObjectShortName">m_axi_awready</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_dma_master_i/write_data_count" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">write_data_count[3:0]</obj_property>
+      <obj_property name="ObjectShortName">write_data_count[3:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="group61" type="group">
+      <obj_property name="label">AXI_WDATA</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_wdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_wdata[63:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_wdata[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_wstrb" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_wstrb[7:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_wstrb[7:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_wlast" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_wlast</obj_property>
+         <obj_property name="ObjectShortName">m_axi_wlast</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_wvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_wvalid</obj_property>
+         <obj_property name="ObjectShortName">m_axi_wvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_wready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_wready</obj_property>
+         <obj_property name="ObjectShortName">m_axi_wready</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group62" type="group">
+      <obj_property name="label">AXI_WRESP</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_bid" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_bid[0:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_bid[0:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_bresp" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_bresp[1:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_bresp[1:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_bvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_bvalid</obj_property>
+         <obj_property name="ObjectShortName">m_axi_bvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_bready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_bready</obj_property>
+         <obj_property name="ObjectShortName">m_axi_bready</obj_property>
+         <obj_property name="UseCustomSignalColor">true</obj_property>
+         <obj_property name="CustomSignalColor">#00ff00</obj_property>
+         <obj_property name="label">/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_bready</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/space" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">space[10:0]</obj_property>
+      <obj_property name="ObjectShortName">space[10:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/occupied" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">occupied[10:0]</obj_property>
+      <obj_property name="ObjectShortName">occupied[10:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+      <obj_property name="CustomSignalColor">#00ffff</obj_property>
+   </wvobject>
+   <wvobject fp_name="group63" type="group">
+      <obj_property name="label">AXI_RADDR</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_dma_master_i/read_addr_state" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">read_addr_state[1:0]</obj_property>
+         <obj_property name="ObjectShortName">read_addr_state[1:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="UseCustomSignalColor">true</obj_property>
+         <obj_property name="CustomSignalColor">#ffff00</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_arid" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_arid[0:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_arid[0:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_araddr" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_araddr[31:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_araddr[31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_arlen" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_arlen[7:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_arlen[7:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_arsize" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_arsize[2:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_arsize[2:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_arburst" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_arburst[1:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_arburst[1:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_arvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_arvalid</obj_property>
+         <obj_property name="ObjectShortName">m_axi_arvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_arready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_arready</obj_property>
+         <obj_property name="ObjectShortName">m_axi_arready</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group64" type="group">
+      <obj_property name="label">AXI_RDATA</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_dma_master_i/read_data_state" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">read_data_state[1:0]</obj_property>
+         <obj_property name="ObjectShortName">read_data_state[1:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="UseCustomSignalColor">true</obj_property>
+         <obj_property name="CustomSignalColor">#ffff00</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_rid" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_rid[0:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_rid[0:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_rdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_rdata[63:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_rdata[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_rresp" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_rresp[1:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_rresp[1:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_rlast" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_rlast</obj_property>
+         <obj_property name="ObjectShortName">m_axi_rlast</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_rvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_rvalid</obj_property>
+         <obj_property name="ObjectShortName">m_axi_rvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_rready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_rready</obj_property>
+         <obj_property name="ObjectShortName">m_axi_rready</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/read_ctrl_valid" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">read_ctrl_valid</obj_property>
+      <obj_property name="ObjectShortName">read_ctrl_valid</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+      <obj_property name="CustomSignalColor">#ffff00</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/read_ctrl_ready" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">read_ctrl_ready</obj_property>
+      <obj_property name="ObjectShortName">read_ctrl_ready</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_dma_master_i/read_data_count" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">read_data_count[3:0]</obj_property>
+      <obj_property name="ObjectShortName">read_data_count[3:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/output_state" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">output_state[2:0]</obj_property>
+      <obj_property name="ObjectShortName">output_state[2:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/space_output" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">space_output[5:0]</obj_property>
+      <obj_property name="ObjectShortName">space_output[5:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="group80" type="group">
+      <obj_property name="label">DRAM FIFO OUT</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tdata_output" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tdata_output[63:0]</obj_property>
+         <obj_property name="ObjectShortName">o_tdata_output[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tvalid_output" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tvalid_output</obj_property>
+         <obj_property name="ObjectShortName">o_tvalid_output</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tready_output" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tready_output</obj_property>
+         <obj_property name="ObjectShortName">o_tready_output</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/update_write" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">update_write</obj_property>
+      <obj_property name="ObjectShortName">update_write</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+      <obj_property name="CustomSignalColor">#ff00ff</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/write_count" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">write_count[3:0]</obj_property>
+      <obj_property name="ObjectShortName">write_count[3:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/update_read" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">update_read</obj_property>
+      <obj_property name="ObjectShortName">update_read</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+      <obj_property name="CustomSignalColor">#ff00ff</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/read_count" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">read_count[3:0]</obj_property>
+      <obj_property name="ObjectShortName">read_count[3:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="group68" type="group">
+      <obj_property name="label">Output TImeout</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/output_timeout_count" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">output_timeout_count[7:0]</obj_property>
+         <obj_property name="ObjectShortName">output_timeout_count[7:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/output_timeout_reset" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">output_timeout_reset</obj_property>
+         <obj_property name="ObjectShortName">output_timeout_reset</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/output_timeout_triggered" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">output_timeout_triggered</obj_property>
+         <obj_property name="ObjectShortName">output_timeout_triggered</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group76" type="group">
+      <obj_property name="label">Extract TLAST</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tdata_i0" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tdata_i0[63:0]</obj_property>
+         <obj_property name="ObjectShortName">o_tdata_i0[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tvalid_i0" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tvalid_i0</obj_property>
+         <obj_property name="ObjectShortName">o_tvalid_i0</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tready_i0" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tready_i0</obj_property>
+         <obj_property name="ObjectShortName">o_tready_i0</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tdata_i1" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tdata_i1[63:0]</obj_property>
+         <obj_property name="ObjectShortName">o_tdata_i1[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tvalid_i1" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tvalid_i1</obj_property>
+         <obj_property name="ObjectShortName">o_tvalid_i1</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tready_i1" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tready_i1</obj_property>
+         <obj_property name="ObjectShortName">o_tready_i1</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tlast_i1" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tlast_i1</obj_property>
+         <obj_property name="ObjectShortName">o_tlast_i1</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tdata" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">o_tdata[63:0]</obj_property>
+      <obj_property name="ObjectShortName">o_tdata[63:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tlast" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_tlast</obj_property>
+      <obj_property name="ObjectShortName">o_tlast</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tvalid" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_tvalid</obj_property>
+      <obj_property name="ObjectShortName">o_tvalid</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tready" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_tready</obj_property>
+      <obj_property name="ObjectShortName">o_tready</obj_property>
+   </wvobject>
+</wave_config>
diff --git a/fpga/usrp3/lib/sim/fifo/axi_dram_fifo/run_isim b/fpga/usrp3/lib/sim/fifo/axi_dram_fifo/run_isim
new file mode 100755
index 000000000..5d32efcdd
--- /dev/null
+++ b/fpga/usrp3/lib/sim/fifo/axi_dram_fifo/run_isim
@@ -0,0 +1,16 @@
+vlogcomp -work work ${XILINX}/verilog/src/glbl.v
+#vlogcomp --define SIM_SCRIPT=true --define ISIM=true -work work ../../../packet_proc/source_flow_control_tb.v
+vlogcomp -work work --sourcelibext .v \
+	 --sourcelibdir ../../axi \
+	 --sourcelibdir ../../fifo \
+	 --sourcelibdir ../../../top/b250/coregen \
+	 ../../axi/axi_dram_fifo_tb.v
+
+
+
+fuse work.axi_dram_fifo_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o axi_dram_fifo_tb.exe
+
+# run the simulation scrip
+./axi_dram_fifo_tb.exe -gui #-tclbatch simcmds.tcl
+#./source_flow_control_tb.exe
+
diff --git a/fpga/usrp3/lib/sim/fifo/axi_dram_fifo/sim_sram_1/default.wcfg b/fpga/usrp3/lib/sim/fifo/axi_dram_fifo/sim_sram_1/default.wcfg
new file mode 100644
index 000000000..796071597
--- /dev/null
+++ b/fpga/usrp3/lib/sim/fifo/axi_dram_fifo/sim_sram_1/default.wcfg
@@ -0,0 +1,412 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="./isim.wdb" id="1" type="auto">
+         <top_modules>
+            <top_module name="axi_dram_fifo_tb" />
+            <top_module name="glbl" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <WVObjectSize size="38" />
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/clk" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk</obj_property>
+      <obj_property name="ObjectShortName">clk</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/reset" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">reset</obj_property>
+      <obj_property name="ObjectShortName">reset</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/clear" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clear</obj_property>
+      <obj_property name="ObjectShortName">clear</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/count_rx" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">count_rx[31:0]</obj_property>
+      <obj_property name="ObjectShortName">count_rx[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/count_tx" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">count_tx[31:0]</obj_property>
+      <obj_property name="ObjectShortName">count_tx[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/i_tdata" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">i_tdata[63:0]</obj_property>
+      <obj_property name="ObjectShortName">i_tdata[63:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/i_tlast" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">i_tlast</obj_property>
+      <obj_property name="ObjectShortName">i_tlast</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/i_tvalid" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">i_tvalid</obj_property>
+      <obj_property name="ObjectShortName">i_tvalid</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/i_tready" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">i_tready</obj_property>
+      <obj_property name="ObjectShortName">i_tready</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/input_state" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">input_state[2:0]</obj_property>
+      <obj_property name="ObjectShortName">input_state[2:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/write_ctrl_ready" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">write_ctrl_ready</obj_property>
+      <obj_property name="ObjectShortName">write_ctrl_ready</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/write_ctrl_valid" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">write_ctrl_valid</obj_property>
+      <obj_property name="ObjectShortName">write_ctrl_valid</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/occupied_input" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">occupied_input[5:0]</obj_property>
+      <obj_property name="ObjectShortName">occupied_input[5:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="group92" type="group">
+      <obj_property name="label">INPUT TIMEOUT</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/input_timeout_count" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">input_timeout_count[7:0]</obj_property>
+         <obj_property name="ObjectShortName">input_timeout_count[7:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/input_timeout_reset" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">input_timeout_reset</obj_property>
+         <obj_property name="ObjectShortName">input_timeout_reset</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/input_timeout_triggered" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">input_timeout_triggered</obj_property>
+         <obj_property name="ObjectShortName">input_timeout_triggered</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group60" type="group">
+      <obj_property name="label">AXI_WADDR</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_dma_master_i/write_addr_state" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">write_addr_state[1:0]</obj_property>
+         <obj_property name="ObjectShortName">write_addr_state[1:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="UseCustomSignalColor">true</obj_property>
+         <obj_property name="CustomSignalColor">#ffff00</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_awid" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_awid[0:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_awid[0:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_awaddr" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_awaddr[31:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_awaddr[31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_awlen" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_awlen[7:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_awlen[7:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_awsize" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_awsize[2:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_awsize[2:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_awburst" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_awburst[1:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_awburst[1:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_awvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_awvalid</obj_property>
+         <obj_property name="ObjectShortName">m_axi_awvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_awready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_awready</obj_property>
+         <obj_property name="ObjectShortName">m_axi_awready</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_dma_master_i/write_data_count" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">write_data_count[3:0]</obj_property>
+      <obj_property name="ObjectShortName">write_data_count[3:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="group61" type="group">
+      <obj_property name="label">AXI_WDATA</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_wdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_wdata[63:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_wdata[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_wstrb" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_wstrb[7:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_wstrb[7:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_wlast" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_wlast</obj_property>
+         <obj_property name="ObjectShortName">m_axi_wlast</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_wvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_wvalid</obj_property>
+         <obj_property name="ObjectShortName">m_axi_wvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_wready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_wready</obj_property>
+         <obj_property name="ObjectShortName">m_axi_wready</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group62" type="group">
+      <obj_property name="label">AXI_WRESP</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_bid" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_bid[0:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_bid[0:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_bresp" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_bresp[1:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_bresp[1:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_bvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_bvalid</obj_property>
+         <obj_property name="ObjectShortName">m_axi_bvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_bready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_bready</obj_property>
+         <obj_property name="ObjectShortName">m_axi_bready</obj_property>
+         <obj_property name="UseCustomSignalColor">true</obj_property>
+         <obj_property name="CustomSignalColor">#00ff00</obj_property>
+         <obj_property name="label">/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_bready</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/space" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">space[10:0]</obj_property>
+      <obj_property name="ObjectShortName">space[10:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/occupied" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">occupied[10:0]</obj_property>
+      <obj_property name="ObjectShortName">occupied[10:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+      <obj_property name="CustomSignalColor">#00ffff</obj_property>
+   </wvobject>
+   <wvobject fp_name="group63" type="group">
+      <obj_property name="label">AXI_RADDR</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_dma_master_i/read_addr_state" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">read_addr_state[1:0]</obj_property>
+         <obj_property name="ObjectShortName">read_addr_state[1:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="UseCustomSignalColor">true</obj_property>
+         <obj_property name="CustomSignalColor">#ffff00</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_arid" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_arid[0:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_arid[0:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_araddr" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_araddr[31:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_araddr[31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_arlen" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_arlen[7:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_arlen[7:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_arsize" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_arsize[2:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_arsize[2:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_arburst" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_arburst[1:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_arburst[1:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_arvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_arvalid</obj_property>
+         <obj_property name="ObjectShortName">m_axi_arvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_arready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_arready</obj_property>
+         <obj_property name="ObjectShortName">m_axi_arready</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group64" type="group">
+      <obj_property name="label">AXI_RDATA</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_dma_master_i/read_data_state" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">read_data_state[1:0]</obj_property>
+         <obj_property name="ObjectShortName">read_data_state[1:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="UseCustomSignalColor">true</obj_property>
+         <obj_property name="CustomSignalColor">#ffff00</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_rid" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_rid[0:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_rid[0:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_rdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_rdata[63:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_rdata[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_rresp" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_rresp[1:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_rresp[1:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_rlast" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_rlast</obj_property>
+         <obj_property name="ObjectShortName">m_axi_rlast</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_rvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_rvalid</obj_property>
+         <obj_property name="ObjectShortName">m_axi_rvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_rready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_rready</obj_property>
+         <obj_property name="ObjectShortName">m_axi_rready</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/read_ctrl_valid" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">read_ctrl_valid</obj_property>
+      <obj_property name="ObjectShortName">read_ctrl_valid</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+      <obj_property name="CustomSignalColor">#ffff00</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/read_ctrl_ready" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">read_ctrl_ready</obj_property>
+      <obj_property name="ObjectShortName">read_ctrl_ready</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_dma_master_i/read_data_count" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">read_data_count[3:0]</obj_property>
+      <obj_property name="ObjectShortName">read_data_count[3:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/output_state" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">output_state[2:0]</obj_property>
+      <obj_property name="ObjectShortName">output_state[2:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/space_output" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">space_output[5:0]</obj_property>
+      <obj_property name="ObjectShortName">space_output[5:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="group80" type="group">
+      <obj_property name="label">DRAM FIFO OUT</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tdata_output" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tdata_output[63:0]</obj_property>
+         <obj_property name="ObjectShortName">o_tdata_output[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tvalid_output" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tvalid_output</obj_property>
+         <obj_property name="ObjectShortName">o_tvalid_output</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tready_output" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tready_output</obj_property>
+         <obj_property name="ObjectShortName">o_tready_output</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/update_write" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">update_write</obj_property>
+      <obj_property name="ObjectShortName">update_write</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+      <obj_property name="CustomSignalColor">#ff00ff</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/write_count" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">write_count[3:0]</obj_property>
+      <obj_property name="ObjectShortName">write_count[3:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/update_read" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">update_read</obj_property>
+      <obj_property name="ObjectShortName">update_read</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+      <obj_property name="CustomSignalColor">#ff00ff</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/read_count" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">read_count[3:0]</obj_property>
+      <obj_property name="ObjectShortName">read_count[3:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="group68" type="group">
+      <obj_property name="label">Output TImeout</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/output_timeout_count" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">output_timeout_count[7:0]</obj_property>
+         <obj_property name="ObjectShortName">output_timeout_count[7:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/output_timeout_reset" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">output_timeout_reset</obj_property>
+         <obj_property name="ObjectShortName">output_timeout_reset</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/output_timeout_triggered" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">output_timeout_triggered</obj_property>
+         <obj_property name="ObjectShortName">output_timeout_triggered</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group76" type="group">
+      <obj_property name="label">Extract TLAST</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tdata_i0" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tdata_i0[63:0]</obj_property>
+         <obj_property name="ObjectShortName">o_tdata_i0[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tvalid_i0" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tvalid_i0</obj_property>
+         <obj_property name="ObjectShortName">o_tvalid_i0</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tready_i0" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tready_i0</obj_property>
+         <obj_property name="ObjectShortName">o_tready_i0</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tdata_i1" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tdata_i1[63:0]</obj_property>
+         <obj_property name="ObjectShortName">o_tdata_i1[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tvalid_i1" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tvalid_i1</obj_property>
+         <obj_property name="ObjectShortName">o_tvalid_i1</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tready_i1" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tready_i1</obj_property>
+         <obj_property name="ObjectShortName">o_tready_i1</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tlast_i1" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tlast_i1</obj_property>
+         <obj_property name="ObjectShortName">o_tlast_i1</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tdata" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">o_tdata[63:0]</obj_property>
+      <obj_property name="ObjectShortName">o_tdata[63:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tlast" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_tlast</obj_property>
+      <obj_property name="ObjectShortName">o_tlast</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tvalid" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_tvalid</obj_property>
+      <obj_property name="ObjectShortName">o_tvalid</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tready" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_tready</obj_property>
+      <obj_property name="ObjectShortName">o_tready</obj_property>
+   </wvobject>
+</wave_config>
diff --git a/fpga/usrp3/lib/sim/fifo/axi_dram_fifo/sim_sram_1/run_isim b/fpga/usrp3/lib/sim/fifo/axi_dram_fifo/sim_sram_1/run_isim
new file mode 100755
index 000000000..03eead1f7
--- /dev/null
+++ b/fpga/usrp3/lib/sim/fifo/axi_dram_fifo/sim_sram_1/run_isim
@@ -0,0 +1,17 @@
+vlogcomp -work work ${XILINX}/verilog/src/glbl.v
+#vlogcomp --define SIM_SCRIPT=true --define ISIM=true -work work ../../../packet_proc/source_flow_control_tb.v
+vlogcomp -work work --sourcelibext .v \
+	 --sourcelibdir ../../../lib/axi \
+	 --sourcelibdir ../../../lib/fifo \
+         --sourcelibdir ../../../lib/control \
+	 --sourcelibdir ../../../top/x300/coregen \
+	 ../../../lib/axi/axi_dram_fifo_tb.v
+
+
+
+fuse work.axi_dram_fifo_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o axi_dram_fifo_tb.exe
+
+# run the simulation scrip
+./axi_dram_fifo_tb.exe  # -gui #-tclbatch simcmds.tcl
+
+
diff --git a/fpga/usrp3/lib/sim/fifo/axi_dram_fifo/sim_sram_1/simulation_script.v b/fpga/usrp3/lib/sim/fifo/axi_dram_fifo/sim_sram_1/simulation_script.v
new file mode 100644
index 000000000..974b4e096
--- /dev/null
+++ b/fpga/usrp3/lib/sim/fifo/axi_dram_fifo/sim_sram_1/simulation_script.v
@@ -0,0 +1,118 @@
+//
+// Copyright 2016 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+reg [31:0] count_rx, count_tx;
+reg status;
+reg fail;
+
+
+//
+// Use task library
+//
+`define USE_TASKS
+
+   initial 
+     begin
+	clk <= 1'b0;
+	reset <= 1'b0;
+	clear <= 1'b0;
+	i_tdata_r <= 0;
+	i_tlast_r <= 0;
+	i_tvalid_r <= 0;
+	o_tready_r <= 0;
+     end
+   
+   always
+     #5 clk <= ~clk;
+   
+   initial
+     begin
+	count_tx = 2;
+	count_rx = 2;
+	status = 0;
+	
+	
+	@(negedge clk);
+	reset <= 1'b1;
+	repeat(10) @(negedge clk);
+	reset <= 1'b0;
+	repeat(10) @(negedge clk);
+
+	// Send 40 packets.
+	repeat(40) begin
+	   send_raw_packet(count_tx);
+	   repeat(2) @(posedge clk);
+	   count_tx = count_tx + 1;
+	   @(posedge clk);
+	end
+	repeat(100) @(posedge clk);
+	
+
+	// Recieve 40 packets
+	repeat(40) begin
+	   receive_raw_packet(count_rx,fail);
+	   status = status || fail;
+	   repeat(2) @(posedge clk);
+	   count_rx = count_rx + 1;
+	   @(posedge clk);
+	end
+	repeat(100) @(posedge clk);
+
+	count_tx = 2;
+	count_rx = 2;
+	
+	// Send 40 packets.
+	repeat(40) begin
+	   send_raw_packet(count_tx);
+	   repeat(2) @(posedge clk);
+	   count_tx = count_tx + 1;
+	   @(posedge clk);
+	end
+	repeat(100) @(posedge clk);
+	// Now fork so send and receive run concurrently
+	fork
+	   begin
+	      // Send 40 packets.
+	      repeat(40) begin
+		 send_raw_packet(count_tx);
+		 repeat(2) @(posedge clk);
+		 count_tx = count_tx + 1;
+		 @(posedge clk);
+	      end
+	   end
+	   begin
+	      // Recieve 80 packets
+	      repeat(80) begin
+		 receive_raw_packet(count_rx,status);
+		 status = status || fail;
+		 repeat(2) @(posedge clk);
+		 count_rx = count_rx + 1;
+		 @(posedge clk);
+		 if (status !== 0) begin
+		    repeat(100) @(posedge clk);
+		    $display("FAILED.");
+		    $finish;	
+		 end
+	      end
+	   end
+	join
+	// Now single threaded agian.
+	repeat(100) @(posedge clk);
+
+	$display;
+	// Should not be able to get to here with FAIL status but check anyhow
+	if (status != 0)
+	  $display("FAILED.");
+	else
+	  $display("PASSED.");
+	
+	@(posedge clk);
+	$finish;
+	
+     end
+   
+   //initial
+   //  o_tready = 1;
+   
diff --git a/fpga/usrp3/lib/sim/fifo/axi_dram_fifo/sim_sram_2/Default.wcfg b/fpga/usrp3/lib/sim/fifo/axi_dram_fifo/sim_sram_2/Default.wcfg
new file mode 100644
index 000000000..3e6d96fb4
--- /dev/null
+++ b/fpga/usrp3/lib/sim/fifo/axi_dram_fifo/sim_sram_2/Default.wcfg
@@ -0,0 +1,388 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="./isim.wdb" id="1" type="auto">
+         <top_modules>
+            <top_module name="axi_dram_fifo_tb" />
+            <top_module name="glbl" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <WVObjectSize size="14" />
+   <wave_markers>
+      <marker time="31415100000" label="" />
+      <marker time="30385518000" label="" />
+      <marker time="23065100000" label="" />
+      <marker time="18355382000" label="" />
+   </wave_markers>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_embed_tlast_i/clk" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk</obj_property>
+      <obj_property name="ObjectShortName">clk</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_embed_tlast_i/reset" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">reset</obj_property>
+      <obj_property name="ObjectShortName">reset</obj_property>
+   </wvobject>
+   <wvobject fp_name="group31" type="group">
+      <obj_property name="label">chdr_test_pattern</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_chdr_test_pattern_i/start" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">start</obj_property>
+         <obj_property name="ObjectShortName">start</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_chdr_test_pattern_i/i_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tdata[63:0]</obj_property>
+         <obj_property name="ObjectShortName">i_tdata[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_chdr_test_pattern_i/i_tlast" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tlast</obj_property>
+         <obj_property name="ObjectShortName">i_tlast</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_chdr_test_pattern_i/i_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tvalid</obj_property>
+         <obj_property name="ObjectShortName">i_tvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_chdr_test_pattern_i/i_tready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tready</obj_property>
+         <obj_property name="ObjectShortName">i_tready</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_chdr_test_pattern_i/o_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tdata[63:0]</obj_property>
+         <obj_property name="ObjectShortName">o_tdata[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_chdr_test_pattern_i/o_tlast" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tlast</obj_property>
+         <obj_property name="ObjectShortName">o_tlast</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_chdr_test_pattern_i/o_tready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tready</obj_property>
+         <obj_property name="ObjectShortName">o_tready</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_chdr_test_pattern_i/o_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tvalid</obj_property>
+         <obj_property name="ObjectShortName">o_tvalid</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group11" type="group">
+      <obj_property name="label">embed_tlast</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_embed_tlast_i/i_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tdata[63:0]</obj_property>
+         <obj_property name="ObjectShortName">i_tdata[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_embed_tlast_i/i_tlast" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tlast</obj_property>
+         <obj_property name="ObjectShortName">i_tlast</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_embed_tlast_i/i_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tvalid</obj_property>
+         <obj_property name="ObjectShortName">i_tvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_embed_tlast_i/i_tready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tready</obj_property>
+         <obj_property name="ObjectShortName">i_tready</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_embed_tlast_i/o_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tdata[63:0]</obj_property>
+         <obj_property name="ObjectShortName">o_tdata[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_embed_tlast_i/o_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tvalid</obj_property>
+         <obj_property name="ObjectShortName">o_tvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_embed_tlast_i/o_tready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tready</obj_property>
+         <obj_property name="ObjectShortName">o_tready</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_embed_tlast_i/state" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">state[1:0]</obj_property>
+         <obj_property name="ObjectShortName">state[1:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group18" type="group">
+      <obj_property name="label">fast_fifo_i0</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fast_fifo_i0/state" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">state[1:0]</obj_property>
+         <obj_property name="ObjectShortName">state[1:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fast_fifo_i0/i_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tdata[63:0]</obj_property>
+         <obj_property name="ObjectShortName">i_tdata[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fast_fifo_i0/i_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">i_tvalid</obj_property>
+         <obj_property name="ObjectShortName">i_tvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fast_fifo_i0/i_tready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tready</obj_property>
+         <obj_property name="ObjectShortName">i_tready</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fast_fifo_i0/o_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tdata[63:0]</obj_property>
+         <obj_property name="ObjectShortName">o_tdata[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fast_fifo_i0/o_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tvalid</obj_property>
+         <obj_property name="ObjectShortName">o_tvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fast_fifo_i0/o_tready" type="logic" db_ref_id="1">
+         <obj_property name="DisplayName">label</obj_property>
+         <obj_property name="ElementShortName">o_tready</obj_property>
+         <obj_property name="ObjectShortName">o_tready</obj_property>
+         <obj_property name="label">o_tready</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group25" type="group">
+      <obj_property name="label">fifo_i1</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fifo_i1/i_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tdata[63:0]</obj_property>
+         <obj_property name="ObjectShortName">i_tdata[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fifo_i1/i_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tvalid</obj_property>
+         <obj_property name="ObjectShortName">i_tvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fifo_i1/i_tready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tready</obj_property>
+         <obj_property name="ObjectShortName">i_tready</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fifo_i1/o_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tdata[63:0]</obj_property>
+         <obj_property name="ObjectShortName">o_tdata[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fifo_i1/o_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tvalid</obj_property>
+         <obj_property name="ObjectShortName">o_tvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fifo_i1/o_tready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tready</obj_property>
+         <obj_property name="ObjectShortName">o_tready</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group79" type="group">
+      <obj_property name="label">AXI write bus</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_awaddr" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">axi_awaddr[31:0]</obj_property>
+         <obj_property name="ObjectShortName">axi_awaddr[31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_awlen" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">axi_awlen[7:0]</obj_property>
+         <obj_property name="ObjectShortName">axi_awlen[7:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_awvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">axi_awvalid</obj_property>
+         <obj_property name="ObjectShortName">axi_awvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_awready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">axi_awready</obj_property>
+         <obj_property name="ObjectShortName">axi_awready</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_wdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">axi_wdata[63:0]</obj_property>
+         <obj_property name="ObjectShortName">axi_wdata[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_wvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">axi_wvalid</obj_property>
+         <obj_property name="ObjectShortName">axi_wvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_wready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">axi_wready</obj_property>
+         <obj_property name="ObjectShortName">axi_wready</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_bvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">axi_bvalid</obj_property>
+         <obj_property name="ObjectShortName">axi_bvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_bready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">axi_bready</obj_property>
+         <obj_property name="ObjectShortName">axi_bready</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/space" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">space[10:0]</obj_property>
+      <obj_property name="ObjectShortName">space[10:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/occupied" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">occupied[10:0]</obj_property>
+      <obj_property name="ObjectShortName">occupied[10:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="group71" type="group">
+      <obj_property name="label">AXI read bus</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_araddr" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_araddr[31:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_araddr[31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_arlen" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_arlen[7:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_arlen[7:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_arvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_arvalid</obj_property>
+         <obj_property name="ObjectShortName">m_axi_arvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_arready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_arready</obj_property>
+         <obj_property name="ObjectShortName">m_axi_arready</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_rdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_rdata[63:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_rdata[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_rvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_rvalid</obj_property>
+         <obj_property name="ObjectShortName">m_axi_rvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_rready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_rready</obj_property>
+         <obj_property name="ObjectShortName">m_axi_rready</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group43" type="group">
+      <obj_property name="label">fifo_i2</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fifo_i2/i_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tdata[63:0]</obj_property>
+         <obj_property name="ObjectShortName">i_tdata[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fifo_i2/i_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tvalid</obj_property>
+         <obj_property name="ObjectShortName">i_tvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fifo_i2/i_tready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tready</obj_property>
+         <obj_property name="ObjectShortName">i_tready</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fifo_i2/o_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tdata[63:0]</obj_property>
+         <obj_property name="ObjectShortName">o_tdata[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fifo_i2/o_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tvalid</obj_property>
+         <obj_property name="ObjectShortName">o_tvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fifo_i2/o_tready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tready</obj_property>
+         <obj_property name="ObjectShortName">o_tready</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group50" type="group">
+      <obj_property name="label">fast_fifo_i1</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fast_fifo_i1/i_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tdata[63:0]</obj_property>
+         <obj_property name="ObjectShortName">i_tdata[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fast_fifo_i1/i_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tvalid</obj_property>
+         <obj_property name="ObjectShortName">i_tvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fast_fifo_i1/i_tready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tready</obj_property>
+         <obj_property name="ObjectShortName">i_tready</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fast_fifo_i1/o_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tdata[63:0]</obj_property>
+         <obj_property name="ObjectShortName">o_tdata[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fast_fifo_i1/o_tready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tready</obj_property>
+         <obj_property name="ObjectShortName">o_tready</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fast_fifo_i1/o_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tvalid</obj_property>
+         <obj_property name="ObjectShortName">o_tvalid</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group58" type="group">
+      <obj_property name="label">axi_fast_extract</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_fast_extract_tlast_i0/i_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tdata[63:0]</obj_property>
+         <obj_property name="ObjectShortName">i_tdata[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_fast_extract_tlast_i0/i_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tvalid</obj_property>
+         <obj_property name="ObjectShortName">i_tvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_fast_extract_tlast_i0/i_tready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tready</obj_property>
+         <obj_property name="ObjectShortName">i_tready</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_fast_extract_tlast_i0/o_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tdata[63:0]</obj_property>
+         <obj_property name="ObjectShortName">o_tdata[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_fast_extract_tlast_i0/o_tlast" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tlast</obj_property>
+         <obj_property name="ObjectShortName">o_tlast</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_fast_extract_tlast_i0/o_tready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tready</obj_property>
+         <obj_property name="ObjectShortName">o_tready</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_fast_extract_tlast_i0/o_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tvalid</obj_property>
+         <obj_property name="ObjectShortName">o_tvalid</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group63" type="group">
+      <obj_property name="label">dram_fifo_output</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tdata[63:0]</obj_property>
+         <obj_property name="ObjectShortName">o_tdata[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tlast" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tlast</obj_property>
+         <obj_property name="ObjectShortName">o_tlast</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tvalid</obj_property>
+         <obj_property name="ObjectShortName">o_tvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tready</obj_property>
+         <obj_property name="ObjectShortName">o_tready</obj_property>
+      </wvobject>
+   </wvobject>
+</wave_config>
diff --git a/fpga/usrp3/lib/sim/fifo/axi_dram_fifo/sim_sram_2/run_isim b/fpga/usrp3/lib/sim/fifo/axi_dram_fifo/sim_sram_2/run_isim
new file mode 100755
index 000000000..46141fcae
--- /dev/null
+++ b/fpga/usrp3/lib/sim/fifo/axi_dram_fifo/sim_sram_2/run_isim
@@ -0,0 +1,19 @@
+/bin/rm -r isim
+
+vlogcomp -work work ${XILINX}/verilog/src/glbl.v
+
+vlogcomp -work work --sourcelibext .v \
+	 --sourcelibdir ../../../lib/axi \
+	 --sourcelibdir ../../../lib/fifo \
+	 --sourcelibdir ../../../lib/control \
+	 --sourcelibdir ../../../top/x300/coregen \
+	 ../../../lib/axi/axi_dram_fifo_tb.v
+
+
+
+fuse work.axi_dram_fifo_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o axi_dram_fifo_tb.exe
+
+# run the simulation scrip
+./axi_dram_fifo_tb.exe  -gui #-tclbatch simcmds.tcl
+
+
diff --git a/fpga/usrp3/lib/sim/fifo/axi_dram_fifo/sim_sram_2/simulation_script.v b/fpga/usrp3/lib/sim/fifo/axi_dram_fifo/sim_sram_2/simulation_script.v
new file mode 100644
index 000000000..66de106d7
--- /dev/null
+++ b/fpga/usrp3/lib/sim/fifo/axi_dram_fifo/sim_sram_2/simulation_script.v
@@ -0,0 +1,96 @@
+//
+// Copyright 2016 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+wire fail;
+wire done;
+reg start;
+reg [15:0] control;
+
+
+
+axi_chdr_test_pattern axi_chdr_test_pattern_i
+  (
+   .clk(clk),
+   .reset(reset),
+  
+   //
+   // CHDR friendly AXI stream input
+   //
+   .i_tdata(i_tdata),
+   .i_tlast(i_tlast),
+   .i_tvalid(i_tvalid),
+   .i_tready(i_tready),
+   //
+   // CHDR friendly AXI Stream output
+   //
+   .o_tdata(o_tdata),
+   .o_tlast(o_tlast),
+   .o_tvalid(o_tvalid),
+   .o_tready(o_tready),
+   //
+   // Test flags
+   //
+   .start(start),
+   .fail(fail),
+   .done(done),
+   .control(control)
+   );
+
+   
+   always
+     #5 clk <= ~clk;
+   
+   initial
+     begin
+	clk <= 1'b0;
+	reset <= 1'b0;
+	clear <= 1'b0;
+	start <= 1'b0;
+	control <= 16'h0101;
+	
+	
+	@(negedge clk);
+	reset <= 1'b1;
+	repeat(10) @(negedge clk);
+	reset <= 1'b0;
+	repeat(10) @(negedge clk);
+	// Now activate BIST
+	start <= 1'b1;
+	
+	// Wait until simulation is done.
+	while(!done)
+	  @(negedge clk);
+	
+	$display;
+	
+	if (fail)
+	  $display("FAILED.");
+	else
+	  $display("Done 1st pass.");
+	
+	@(posedge clk);
+	start <= 1'b0;
+	repeat(10) @(negedge clk);
+	// Now activate BIST
+	start <= 1'b1;
+	
+	// Wait until simulation is done.
+	while(!done)
+	  @(negedge clk);
+	
+	$display;
+	
+	if (fail)
+	  $display("FAILED.");
+	else
+	  $display("PASSED.");
+	
+	$finish;
+	
+     end
+   
+   //initial
+   //  o_tready = 1;
+   
diff --git a/fpga/usrp3/lib/sim/fifo/axi_fifo/Makefile b/fpga/usrp3/lib/sim/fifo/axi_fifo/Makefile
new file mode 100644
index 000000000..3cd861176
--- /dev/null
+++ b/fpga/usrp3/lib/sim/fifo/axi_fifo/Makefile
@@ -0,0 +1,34 @@
+#
+# Copyright 2016 Ettus Research
+#
+
+#-------------------------------------------------
+# Top-of-Makefile
+#-------------------------------------------------
+# Define BASE_DIR to point to the "top" dir
+BASE_DIR = $(abspath ../../../../top)
+# Include viv_sim_preamble after defining BASE_DIR
+include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
+
+#-------------------------------------------------
+# Testbench Specific
+#-------------------------------------------------
+# Define only one toplevel module
+SIM_TOP = axi_fifo_tb
+
+SIM_SRCS = $(abspath \
+axi_fifo_tb.sv \
+$(LIB_DIR)/fifo/axi_fifo.v \
+$(LIB_DIR)/fifo/axi_fifo_flop.v \
+$(LIB_DIR)/fifo/axi_fifo_flop2.v \
+$(LIB_DIR)/fifo/axi_fifo_short.v \
+$(LIB_DIR)/fifo/axi_fifo_bram.v \
+)
+
+#-------------------------------------------------
+# Bottom-of-Makefile
+#-------------------------------------------------
+# Include all simulator specific makefiles here
+# Each should define a unique target to simulate
+# e.g. xsim, vsim, etc and a common "clean" target
+include $(BASE_DIR)/../tools/make/viv_simulator.mak
diff --git a/fpga/usrp3/lib/sim/fifo/axi_fifo/axi_fifo_tb.sv b/fpga/usrp3/lib/sim/fifo/axi_fifo/axi_fifo_tb.sv
new file mode 100644
index 000000000..c2832cade
--- /dev/null
+++ b/fpga/usrp3/lib/sim/fifo/axi_fifo/axi_fifo_tb.sv
@@ -0,0 +1,134 @@
+//
+// Copyright 2016 Ettus Research
+//
+
+`timescale 1ns/1ps
+`define SIM_TIMEOUT_US 1000
+`define NS_PER_TICK 1
+`define NUM_TEST_CASES 4
+
+`include "sim_exec_report.vh"
+`include "sim_clks_rsts.vh"
+`include "sim_cvita_lib.svh"
+`include "sim_axis_lib.svh"
+`include "sim_set_rb_lib.svh"
+
+module axi_fifo_tb();
+  /*********************************************
+  ** Setup Testbench
+  *********************************************/
+  `TEST_BENCH_INIT("axi_fifo_tb",`NUM_TEST_CASES,`NS_PER_TICK);
+  localparam CLK_PERIOD = $ceil(1e9/166.67e6);
+  `DEFINE_CLK(clk, CLK_PERIOD, 50);
+  `DEFINE_RESET(reset, 0, 100);
+
+  // 4 variants: axi_fifo_flop, axi_fifo_flop2, axi_fifo_short, axi_fifo_bram
+  localparam NUM_FIFOS = 4;
+  localparam integer FIFO_SIZES[NUM_FIFOS-1:0] = '{0,1,5,8};
+  localparam NUM_ITERATIONS = 10000;
+
+  /*********************************************
+  ** DUTs
+  ** - Instances of all variations of AXI FIFO
+  *********************************************/
+  reg  [NUM_FIFOS-1:0] clear;
+  axis_master #(.DWIDTH(32), .NUM_STREAMS(NUM_FIFOS)) m_axis(.clk(clk));
+  axis_slave #(.DWIDTH(32), .NUM_STREAMS(NUM_FIFOS)) s_axis(.clk(clk));
+
+  genvar n;
+  generate
+    for (n = 0; n < NUM_FIFOS; n = n + 1) begin
+      axi_fifo #(
+        .SIZE(FIFO_SIZES[n]),
+        .WIDTH(32))
+      axi_fifo (
+        .clk(clk), .reset(reset), .clear(clear[n]),
+        .i_tdata(m_axis.axis.tdata[32*n +: 32]), .i_tvalid(m_axis.axis.tvalid[n]), .i_tready(m_axis.axis.tready[n]),
+        .o_tdata(s_axis.axis.tdata[32*n +: 32]), .o_tvalid(s_axis.axis.tvalid[n]), .o_tready(s_axis.axis.tready[n]),
+        .space(), .occupied());
+    end
+  endgenerate
+
+  /*********************************************
+  ** Testbench
+  *********************************************/
+  int write_word = 0;
+  int read_word = 0;
+  logic last;
+  string s;
+
+  initial begin
+    clear = 'd0;
+
+    /********************************************************
+    ** Test 1 -- Reset
+    ********************************************************/
+    `TEST_CASE_START("Wait for Reset");
+    m_axis.reset();
+    s_axis.reset();
+    while (reset) @(posedge clk);
+    `TEST_CASE_DONE(~reset);
+
+    /********************************************************
+    ** Test 2 -- Check filling FIFOs
+    ********************************************************/
+    `TEST_CASE_START("Check filling FIFOs");
+    for (int i = 0; i < NUM_FIFOS; i++) begin
+      $display("Testing FIFO %0d, SIZE %0d",i,2**FIFO_SIZES[i]);
+      for (int k = 0; k < 2**FIFO_SIZES[i]; k++) begin
+        $sformat(s,"FIFO size should be %0d entries, but detected %0d!",2**FIFO_SIZES[i],k);
+        `ASSERT_FATAL(m_axis.axis.tready[i],s);
+        m_axis.push_word(k,0,i);
+      end
+      $sformat(s,"FIFO depth appears to be greater than %0d entries! Might be due to output registering.",2**FIFO_SIZES[i]);
+      `ASSERT_WARN(~m_axis.axis.tready[i],s);
+    end
+    `TEST_CASE_DONE(1);
+
+    /********************************************************
+    ** Test 3 -- Check emptying FIFOs
+    ********************************************************/
+    `TEST_CASE_START("Check emptying FIFOs");
+    for (int i = 0; i < NUM_FIFOS; i++) begin
+      $display("Testing FIFO %0d, SIZE %0d",i,2**FIFO_SIZES[i]);
+      for (int k = 0; k < 2**FIFO_SIZES[i]; k = k + 1) begin
+        $sformat(s,"FIFO prematurely empty! Occured after %0d reads!",k);
+        `ASSERT_FATAL(s_axis.axis.tvalid[i],s);
+        s_axis.pull_word(read_word,last,i);
+        $sformat(s,"Read invalid FIFO word! Expected: %0d, Actual: %0d",k,read_word);
+        `ASSERT_FATAL(read_word == k,s);
+      end
+      `ASSERT_FATAL(~s_axis.axis.tvalid[i],"FIFO not empty after reading all entries!");
+    end
+    `TEST_CASE_DONE(1);
+
+    /********************************************************
+    ** Test 4 -- Randomized Write / Read Timing
+    ********************************************************/
+    `TEST_CASE_START("Randomized Write / Read");
+    for (int i = 0; i < NUM_FIFOS; i++) begin
+      $display("Testing FIFO %0d, SIZE %0d",i,2**FIFO_SIZES[i]);
+      fork
+      begin
+        write_word = 0;
+        for (int k = 0; k < NUM_ITERATIONS; k++) begin
+          while ($signed($random()) > 0) @(posedge clk);
+          m_axis.push_word(write_word,0,i);
+          write_word++;
+        end
+      end
+      begin
+        for (int k = 0; k < NUM_ITERATIONS; k++) begin
+          while ($signed($random()) > 0) @(posedge clk);
+          s_axis.pull_word(read_word,last,i);
+          $sformat(s,"Read invalid FIFO word! Expected: %0d, Actual: %0d",read_word,k);
+          `ASSERT_FATAL(read_word == k,s);
+        end
+      end
+      join
+    end
+    `TEST_CASE_DONE(1);
+    `TEST_BENCH_DONE;
+  end
+
+endmodule
diff --git a/fpga/usrp3/lib/sim/fifo/axi_fifo_2clk/axi_fifo_2clk_tb.sv b/fpga/usrp3/lib/sim/fifo/axi_fifo_2clk/axi_fifo_2clk_tb.sv
new file mode 100644
index 000000000..c2c69b963
--- /dev/null
+++ b/fpga/usrp3/lib/sim/fifo/axi_fifo_2clk/axi_fifo_2clk_tb.sv
@@ -0,0 +1,121 @@
+//
+// Copyright 2016 Ettus Research
+//
+
+module axi_fifo_2clk_tb();
+
+    localparam WIDTH    = 32;
+    localparam SIZE     = 5;
+
+    reg                 s_axis_clk;
+    reg                 s_axis_rst;
+    reg [WIDTH-1:0]     s_axis_tdata;
+    reg                 s_axis_tvalid;
+    reg                 s_axis_tlast;
+    wire                s_axis_tready;
+    reg                 m_axis_clk;
+    reg                 m_axis_rst;
+    wire [WIDTH-1:0]    m_axis_tdata;
+    wire                m_axis_tvalid;
+    wire                m_axis_tlast;
+    reg                 m_axis_tready;
+    wire [SIZE:0]       s_axis_occupied;
+    wire                s_axis_full;
+    wire                s_axis_empty;
+    wire [SIZE:0]       m_axis_occupied;
+    wire                m_axis_full;
+    wire                m_axis_empty;
+
+    axi_fifo_2clk #(.SIZE(SIZE),.WIDTH(WIDTH)) axi_fifo_2clk (
+        .s_axis_clk(s_axis_clk),
+        .s_axis_rst(s_axis_rst),
+        .s_axis_tdata(s_axis_tdata),
+        .s_axis_tvalid(s_axis_tvalid),
+        .s_axis_tlast(s_axis_tlast),
+        .s_axis_tready(s_axis_tready),
+        .m_axis_clk(m_axis_clk),
+        .m_axis_rst(m_axis_rst),
+        .m_axis_tdata(m_axis_tdata),
+        .m_axis_tvalid(m_axis_tvalid),
+        .m_axis_tlast(m_axis_tlast),
+        .m_axis_tready(m_axis_tready),
+        .s_axis_occupied(s_axis_occupied),
+        .s_axis_full(s_axis_full),
+        .s_axis_empty(s_axis_empty),
+        .m_axis_occupied(m_axis_occupied),
+        .m_axis_full(m_axis_full),
+        .m_axis_empty(m_axis_empty));
+
+    `define S_AXIS_CLK_PERIOD 7
+    initial begin
+        s_axis_clk = 1'b0;
+        forever begin
+            #(`S_AXIS_CLK_PERIOD/2) s_axis_clk = ~s_axis_clk;
+        end
+    end
+
+    `define S_AXIS_RESET_PERIOD 70
+    initial begin
+        s_axis_rst = 1'b1;
+        #(`S_AXIS_RESET_PERIOD) s_axis_rst = 1'b0;
+    end
+
+    `define M_AXIS_CLK_PERIOD 10
+    initial begin
+        m_axis_clk = 1'b0;
+        forever begin
+            #(`M_AXIS_CLK_PERIOD/2) m_axis_clk = ~m_axis_clk;
+        end
+    end
+
+    `define M_AXIS_RESET_PERIOD 100
+    initial begin
+        m_axis_rst = 1'b1;
+        #(`M_AXIS_RESET_PERIOD) m_axis_rst = 1'b0;
+    end
+
+    initial begin
+        @(posedge m_axis_clk);
+        @(posedge s_axis_clk);
+        s_axis_tdata  = 'd0;
+        s_axis_tlast  = 1'b0;
+        s_axis_tvalid = 1'b0;
+        m_axis_tready = 1'b0;
+        assert(~s_axis_full && ~m_axis_full)                 else $error("FIFO is full during reset!");
+        assert(s_axis_empty == 1'b1 && m_axis_empty == 1'b1) else $error("FIFO is not empty during reset!");
+        assert(s_axis_occupied == 0 && m_axis_occupied == 0) else $error("FIFO is occupied during reset!");
+        while (s_axis_rst) @(negedge s_axis_rst);
+        while (m_axis_rst) @(negedge m_axis_rst);
+        @(posedge m_axis_clk);
+        @(posedge s_axis_clk);
+        assert(~s_axis_full && ~m_axis_full)                 else $error("FIFO is full after reset!");
+        assert(s_axis_empty == 1'b1 && m_axis_empty == 1'b1) else $error("FIFO is not empty after reset!");
+        assert(s_axis_occupied == 0 && m_axis_occupied == 0) else $error("FIFO is occupied after reset!");
+        // Fill FIFO
+        while (~s_axis_tready) @(posedge s_axis_clk);
+        for (int i = 0; i < 1 << DEPTH_LOG2; i++) begin
+            s_axis_tdata  = i+1'b1;
+            s_axis_tvalid = 1'b1;
+            @(posedge s_axis_clk);
+        end
+        repeat (6) @(posedge s_axis_clk);
+        assert(s_axis_full && m_axis_full) else $error("Incorrect FIFO full flag!");
+        assert(~s_axis_empty && ~m_axis_empty) else $error("Incorrect FIFO empty flag!");
+        assert(s_axis_occupied == (1 << DEPTH_LOG2) && m_axis_occupied == (1 << DEPTH_LOG2)) else $error("Incorrect FIFO occupied count!");
+        // Empty FIFO
+        s_axis_tdata  = 'd0;
+        s_axis_tvalid = 1'b0;
+        @(posedge m_axis_clk);
+        while (~m_axis_tvalid) @(posedge m_axis_clk);
+        for (int i = 0; i < 1 << DEPTH_LOG2; i++) begin
+            m_axis_tready = 1'b1;
+            @(posedge m_axis_clk);
+            assert(m_axis_tdata == i+1'b1) else $error("Incorrect FIFO data! (read)");
+        end
+        repeat (6) @(posedge m_axis_clk);
+        assert(~s_axis_full && ~m_axis_full) else $error("Incorrect FIFO full flag!");
+        assert(s_axis_empty && m_axis_empty) else $error("Incorrect FIFO empty flag!");
+        assert(s_axis_occupied == 0 && m_axis_occupied == 0) else $error("Incorrect FIFO occupied count!");
+    end
+
+endmodule
\ No newline at end of file
diff --git a/fpga/usrp3/lib/sim/fifo/axi_fifo_2clk_sim.v b/fpga/usrp3/lib/sim/fifo/axi_fifo_2clk_sim.v
new file mode 100644
index 000000000..cf31ae2d9
--- /dev/null
+++ b/fpga/usrp3/lib/sim/fifo/axi_fifo_2clk_sim.v
@@ -0,0 +1,230 @@
+//
+// Copyright 2016 Ettus Research
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module axi_fifo_2clk #(
+    parameter SYNC_STAGES = 2,
+    parameter SIZE        = 10,
+    parameter WIDTH       = 32,
+    parameter PIPELINE    = "<UNUSED>")
+(
+    input reset,
+    input i_aclk,
+    input [WIDTH-1:0] i_tdata,
+    input i_tvalid,
+    output reg i_tready = 1'b0,
+    input o_aclk,
+    output [WIDTH-1:0] o_tdata,
+    output reg o_tvalid = 1'b0,
+    input o_tready
+);
+
+    localparam FIFOSIZE = (SIZE < 5) ? 5 : SIZE;
+
+    // Synchronizers
+    wire o_rst_sync, i_rst_sync;
+    synchronizer #(
+        .INITIAL_VAL(1'b1),
+        .WIDTH(1),
+        .STAGES(SYNC_STAGES))
+    synchronizer_i_rst (
+        .clk(i_aclk), .rst(1'b0),
+        .in(reset), .out(i_rst_sync));
+    synchronizer #(
+        .INITIAL_VAL(1'b1),
+        .WIDTH(1),
+        .STAGES(SYNC_STAGES))
+    synchronizer_o_rst (
+        .clk(o_aclk), .rst(1'b0),
+        .in(reset), .out(o_rst_sync));
+
+    // Gray counter encode / decode + synchronizers
+    reg [FIFOSIZE-1:0] wr_addr, rd_addr;
+    wire [FIFOSIZE-1:0] wr_addr_sync, rd_addr_sync;
+    wire [FIFOSIZE-1:0] wr_addr_gray_sync, wr_addr_gray, rd_addr_gray_sync, rd_addr_gray;
+    synchronizer #(
+        .INITIAL_VAL(0),
+        .WIDTH(FIFOSIZE),
+        .STAGES(SYNC_STAGES))
+    synchronizer_rd_addr_gray (
+        .clk(i_aclk), .rst(o_rst_sync),
+        .in(rd_addr_gray), .out(rd_addr_gray_sync));
+    synchronizer #(
+        .INITIAL_VAL(0),
+        .WIDTH(FIFOSIZE),
+        .STAGES(SYNC_STAGES))
+    synchronizer_wr_addr_gray (
+        .clk(o_aclk), .rst(i_rst_sync),
+        .in(wr_addr_gray), .out(wr_addr_gray_sync));
+    bin2gray #(.WIDTH(FIFOSIZE))
+    bin2gray_wr_addr (.bin(wr_addr), .gray(wr_addr_gray));
+    bin2gray #(.WIDTH(FIFOSIZE))
+    bin2gray_rd_addr (.bin(rd_addr), .gray(rd_addr_gray));
+    gray2bin #(.WIDTH(FIFOSIZE))
+    gray2bin_wr_addr (.gray(wr_addr_gray_sync), .bin(wr_addr_sync));
+    gray2bin #(.WIDTH(FIFOSIZE))
+    gray2bin_rd_addr (.gray(rd_addr_gray_sync), .bin(rd_addr_sync));
+
+    reg [FIFOSIZE:0] i_occupied;
+    reg [FIFOSIZE:0] i_space;
+    reg i_full;
+    reg i_empty;
+    reg [FIFOSIZE:0] o_occupied;
+    reg [FIFOSIZE:0] o_space;
+    reg o_full;
+    reg o_empty;
+
+    reg [WIDTH:0] mem[0:2**(FIFOSIZE)-1];
+    integer i;
+    initial begin
+        for (i = 0; i < 1 << FIFOSIZE; i = i + 1) begin
+            mem[i] = 'd0;
+        end
+    end
+
+    // Write
+    always @(posedge i_aclk) begin
+        if (i_rst_sync) begin
+            wr_addr <= 'd0;
+        end else begin
+            if (i_tvalid & i_tready) begin
+                mem[wr_addr] <= i_tdata;
+                wr_addr      <= wr_addr + 1'b1;
+            end
+        end
+    end
+
+    // Write ready, full, empty, occupied signals
+    always @(posedge i_aclk) begin
+        if (i_rst_sync) begin
+            i_tready   <= 1'b0;
+            i_full     <= 1'b0;
+            i_empty    <= 1'b1;
+            i_occupied <= 'd0;
+            i_space    <= (1'b1 << FIFOSIZE);
+        end else begin
+            if ((rd_addr_sync-1'b1 == wr_addr) & i_tvalid & i_tready) begin
+                i_tready <= 1'b0;
+                i_full   <= 1'b1;
+            end else if ((rd_addr_sync != wr_addr) & i_full) begin
+                i_tready <= 1'b1;
+                i_full   <= 1'b0;
+            end
+            if ((rd_addr_sync == wr_addr) & ~i_full) begin
+                i_tready <= 1'b1;
+                if (~i_tvalid) begin
+                    i_empty  <= 1'b1;
+                end
+            end else begin
+                i_empty  <= 1'b0;
+            end
+            if (i_tvalid) begin
+                if (wr_addr == rd_addr_sync) begin
+                    if (i_full) begin
+                        i_occupied <= 1'b1 << FIFOSIZE;
+                        i_space    <= 'd0;
+                    end else begin
+                        i_occupied <= 'd1;
+                        i_space    <= (1'b1 << FIFOSIZE)-1'b1;
+                    end
+                end else if (wr_addr > rd_addr_sync) begin
+                    i_occupied <= wr_addr - rd_addr_sync + 1'b1;
+                    i_space    <= (1'b1 << FIFOSIZE) - (wr_addr - rd_addr_sync + 1'b1);
+                end else begin
+                    i_occupied <= wr_addr+1'b1 + (1'b1 << FIFOSIZE)-1'b1 - rd_addr_sync + 1'b1;
+                    i_space    <= rd_addr_sync - wr_addr - 1'b1;
+                end
+            end else begin
+                if (wr_addr == rd_addr_sync) begin
+                    if (i_full) begin
+                        i_occupied <= 1'b1 << FIFOSIZE;
+                        i_space    <= 'd0;
+                    end else begin
+                        i_occupied <= 'd0;
+                        i_space    <= 1'b1 << FIFOSIZE;
+                    end
+                end else if (wr_addr > rd_addr_sync) begin
+                    i_occupied <= wr_addr - rd_addr_sync;
+                    i_space    <= (1'b1 << FIFOSIZE) - (wr_addr - rd_addr_sync);
+                end else begin
+                    i_occupied <= wr_addr+1'b1 + (1'b1 << FIFOSIZE)-1'b1 - rd_addr_sync;
+                    i_space    <= rd_addr_sync - wr_addr;
+                end
+            end
+        end
+    end
+
+    // Read
+    always @(posedge o_aclk) begin
+        if (o_rst_sync) begin
+            rd_addr <= 'd0;
+        end else begin
+            if (o_tvalid & o_tready) begin
+                rd_addr <= rd_addr + 1'b1;
+            end
+        end
+    end
+
+    assign o_tdata = mem[rd_addr];
+
+    // Read valid, full, empty, occupied signals
+    always @(posedge o_aclk) begin
+        if (o_rst_sync) begin
+            o_tvalid   <= 1'b0;
+            o_full     <= 1'b0;
+            o_empty    <= 1'b1;
+            o_occupied <= 'd0;
+            o_space    <= 'd0;
+        end else begin
+            if ((rd_addr+1'b1 == wr_addr_sync) & o_tready & o_tvalid) begin
+                o_tvalid <= 1'b0;
+                o_empty  <= 1'b1;
+            end else if ((rd_addr != wr_addr_sync) & o_empty) begin
+                o_tvalid <= 1'b1;
+                o_empty  <= 1'b0;
+            end
+            if ((rd_addr == wr_addr_sync) & ~o_empty & ~o_tready) begin
+                o_full   <= 1'b1;
+            end else begin
+                o_full   <= 1'b0;
+            end
+            if (o_tready) begin
+                if (wr_addr_sync == rd_addr) begin
+                    if (~o_empty) begin
+                        o_occupied <= (1'b1 << FIFOSIZE) - 1'b1;
+                        o_space    <= 'd1;
+                    end else begin
+                        o_occupied <= 'd0;
+                        o_space    <= (1'b1 << FIFOSIZE);
+                    end
+                end else if (wr_addr_sync > rd_addr) begin
+                    o_occupied <= wr_addr_sync - rd_addr - 1'b1;
+                    o_space    <= (1'b1 << FIFOSIZE) - (wr_addr_sync - rd_addr - 1'b1);
+                end else begin
+                    o_occupied <= wr_addr_sync+1'b1 + (1'b1 << FIFOSIZE)-1'b1 - rd_addr - 1'b1;
+                    o_space    <= rd_addr - wr_addr_sync + 1'b1;
+                end
+            end else begin
+                if (wr_addr_sync == rd_addr) begin
+                    if (~o_empty) begin
+                        o_occupied <= 1'b1 << FIFOSIZE;
+                        o_space    <= 'd0;
+                    end else begin
+                        o_occupied <= 'd0;
+                        o_space    <= 1'b1 << FIFOSIZE;
+                    end
+                end else if (wr_addr_sync > rd_addr) begin
+                    o_occupied <= wr_addr_sync - rd_addr;
+                    o_space    <= (1'b1 << FIFOSIZE) - (wr_addr_sync - rd_addr);
+                end else begin
+                    o_occupied <= wr_addr_sync+1'b1 + (1'b1 << FIFOSIZE)-1'b1 - rd_addr;
+                    o_space    <= rd_addr - wr_addr_sync;
+                end
+            end
+        end
+    end
+
+endmodule
diff --git a/fpga/usrp3/lib/sim/fifo/axi_fifo_32_64/axi_fifo_32_64_tb.v b/fpga/usrp3/lib/sim/fifo/axi_fifo_32_64/axi_fifo_32_64_tb.v
new file mode 100644
index 000000000..b3acab3ca
--- /dev/null
+++ b/fpga/usrp3/lib/sim/fifo/axi_fifo_32_64/axi_fifo_32_64_tb.v
@@ -0,0 +1,121 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+`timescale 1ns/1ps
+
+module axi_fifo_32_64_tb();
+
+   reg clk    = 0;
+   reg reset  = 1;
+   
+   always #10 clk = ~clk;
+   
+   initial $dumpfile("axi_fifo_32_64_tb.vcd");
+   initial $dumpvars(0,axi_fifo_32_64_tb);
+
+   task send_packet;
+      input [63:0] data_start;
+      input [2:0]  user;
+      input [31:0] len;
+      
+      begin
+	 @(posedge clk);
+	 {i_tuser, i_tlast, i_tdata} <= { 3'd0, 1'b0, data_start };
+	 repeat(len-1)
+	   begin
+	      i_tvalid <= 1;
+	      @(posedge clk);
+	      i_tdata <= i_tdata + 64'h0000_0002_0000_0002;
+	   end
+	 i_tuser <= user;
+	 i_tlast <= 1;
+	 @(posedge clk);
+	 i_tvalid <= 1'b0;
+	 @(posedge clk);
+      end
+   endtask // send_packet
+   
+   initial
+     begin
+	#1000 reset = 0;
+	#200000;
+	$finish;
+     end
+   
+   reg [63:0] i_tdata;
+   reg [2:0]  i_tuser;
+   reg 	      i_tlast;
+   reg 	      i_tvalid;
+   wire       i_tready;
+
+   wire [63:0] i_tdata_int;
+   wire [2:0]  i_tuser_int;
+   wire        i_tlast_int, i_tvalid_int, i_tready_int;
+
+   wire [63:0] o_tdata;
+   wire [31:0] o_tdata_int, o_tdata_int2;
+   wire [2:0]  o_tuser;
+   wire [1:0]  o_tuser_int, o_tuser_int2;
+   wire        o_tlast, o_tlast_int, o_tvalid, o_tvalid_int, o_tready, o_tready_int;
+   wire        o_tlast_int2, o_tvalid_int2, o_tready_int2;
+   
+   localparam RPT_COUNT = 16;
+   
+   initial
+     begin
+	i_tvalid <= 0;
+	
+	while(reset)
+	  @(posedge clk);
+	@(posedge clk);
+
+	send_packet(64'hA0000000_A0000001, 3'd7, 4);
+	@(posedge clk);
+     end // initial begin
+
+   axi_fifo #(.WIDTH(68), .SIZE(10)) fifo
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata({i_tlast,i_tuser,i_tdata}), .i_tvalid(i_tvalid), .i_tready(i_tready),
+      .o_tdata({i_tlast_int,i_tuser_int,i_tdata_int}), .o_tvalid(i_tvalid_int), .o_tready(i_tready_int));
+
+   axi_fifo64_to_fifo32 dut
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata(i_tdata_int), .i_tuser(i_tuser_int), .i_tlast(i_tlast_int), .i_tvalid(i_tvalid_int), .i_tready(i_tready_int),
+      .o_tdata(o_tdata_int), .o_tuser(o_tuser_int), .o_tlast(o_tlast_int), .o_tvalid(o_tvalid_int), .o_tready(o_tready_int));
+
+   /*
+   axi_fifo #(.WIDTH(35), .SIZE(10)) fifo_middle
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata({o_tlast_int,o_tuser_int,o_tdata_int}), .i_tvalid(o_tvalid_int), .i_tready(o_tready_int),
+      .o_tdata({o_tlast_int2,o_tuser_int2,o_tdata_int2}), .o_tvalid(o_tvalid_int2), .o_tready(o_tready_int2));
+*/
+   assign o_tdata_int2 = o_tdata_int;
+   assign o_tlast_int2 = o_tlast_int;
+   assign o_tuser_int2 = o_tuser_int;
+   assign o_tvalid_int2 = o_tvalid_int;
+   assign o_tready_int = o_tready_int2;
+   
+   axi_fifo32_to_fifo64 dut2
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata(o_tdata_int2), .i_tuser(o_tuser_int2), .i_tlast(o_tlast_int2), .i_tvalid(o_tvalid_int2), .i_tready(o_tready_int2),
+      .o_tdata(o_tdata), .o_tuser(o_tuser), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready));
+
+   assign o_tready = 1'b1;
+   
+   always @(posedge clk)
+     if(i_tvalid & i_tready)
+       $display("IN: TUSER %x\tTLAST %x\tTDATA %x", i_tuser, i_tlast, i_tdata);
+
+   always @(posedge clk)
+     if(o_tvalid_int & o_tready_int)
+       $display("\t\t\t\t\t\tMIDDLE: TUSER %x\tTLAST %x\tTDATA %x", o_tuser_int, o_tlast_int, o_tdata_int);
+
+   always @(posedge clk)
+     if(o_tvalid & o_tready)
+       $display("\t\t\t\t\t\t\t\t\t\t\tOUT: TUSER %x\tTLAST %x\tTDATA %x", o_tuser, o_tlast, o_tdata);
+
+endmodule // axi_fifo_32_64_tb
diff --git a/fpga/usrp3/lib/sim/fifo/axi_packet_gate/axi_packet_gate_tb.v b/fpga/usrp3/lib/sim/fifo/axi_packet_gate/axi_packet_gate_tb.v
new file mode 100644
index 000000000..9df01baf0
--- /dev/null
+++ b/fpga/usrp3/lib/sim/fifo/axi_packet_gate/axi_packet_gate_tb.v
@@ -0,0 +1,112 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+`timescale 1ns/1ps
+
+module axi_packet_gate_tb();
+
+   reg clk    = 0;
+   reg reset  = 1;
+   
+   always #10 clk = ~clk;
+   
+   initial $dumpfile("axi_packet_gate_tb.vcd");
+   initial $dumpvars(0,axi_packet_gate_tb);
+
+   task send_packet;
+      input [63:0] data_start;
+      input [2:0]  user;
+      input [31:0] len;
+      input 	   error;
+      
+      begin
+	 // Send a packet
+	 @(posedge clk);
+	 {i_terror, i_tuser, i_tlast, i_tdata} <= { 1'b0, user, 1'b0, data_start };
+	 repeat(len-1)
+	   begin
+	      i_tvalid <= 1;
+	      @(posedge clk);
+	      i_tdata <= i_tdata + 1;
+	   end
+	 i_tlast <= 1;
+	 i_terror <= error;
+	 i_tdata <= i_tdata + 1;
+	 @(posedge clk);
+	 i_tvalid <= 1'b0;
+	 
+	 @(posedge clk);
+      end
+   endtask // send_packet
+   
+   
+   initial
+     begin
+	#1000 reset = 0;
+	#200000;
+	$finish;
+     end
+   
+   wire [63:0]  o_tdata;
+   reg [63:0] 	i_tdata;
+   wire [2:0] 	o_tuser;
+   reg [2:0] 	i_tuser;
+   reg 		i_tlast;
+   wire 	o_tlast;
+   wire		o_tvalid, i_tready;
+   reg 		i_tvalid, o_tready;
+   reg 		i_terror;
+   
+   localparam RPT_COUNT = 16;
+   
+   initial
+     begin
+	i_tvalid <= 0;
+	o_tready <= 0;
+	
+	while(reset)
+	  @(posedge clk);
+	@(posedge clk);
+
+	send_packet(64'hA0,3'd0, 16, 0);
+	send_packet(64'hB0,3'd0, 16, 0);
+	o_tready <= 1;
+	send_packet(64'hC0,3'd0, 16, 1);
+	send_packet(64'hD0,3'd0, 16, 0);
+	send_packet(64'hE0,3'd0, 16, 0);
+	send_packet(64'hF0,3'd0, 16, 0);
+
+	@(posedge clk);
+
+     end // initial begin
+
+   wire i_terror_int, i_tlast_int, i_tready_int, i_tvalid_int;
+   wire [2:0] i_tuser_int;
+   wire [63:0] i_tdata_int;
+   wire o_tlast_int, o_tready_int, o_tvalid_int;
+   wire [2:0] o_tuser_int;
+   wire [63:0] o_tdata_int;
+   
+   axi_fifo #(.WIDTH(69), .SIZE(10)) fifo
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata({i_terror,i_tlast,i_tuser,i_tdata}), .i_tvalid(i_tvalid), .i_tready(i_tready),
+      .o_tdata({i_terror_int,i_tlast_int,i_tuser_int,i_tdata_int}), .o_tvalid(i_tvalid_int), .o_tready(i_tready_int));
+
+   axi_packet_gate #(.WIDTH(67), .SIZE(10)) dut
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata({i_tuser_int,i_tdata_int}), .i_terror(i_terror_int), .i_tlast(i_tlast_int), .i_tvalid(i_tvalid_int), .i_tready(i_tready_int),
+      .o_tdata({o_tuser_int,o_tdata_int}), .o_tlast(o_tlast_int), .o_tvalid(o_tvalid_int), .o_tready(o_tready_int));
+
+   axi_fifo #(.WIDTH(68), .SIZE(10)) fifo_out
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata({o_tlast_int,o_tuser_int,o_tdata_int}), .i_tvalid(o_tvalid_int), .i_tready(o_tready_int),
+      .o_tdata({o_tlast,o_tuser,o_tdata}), .o_tvalid(o_tvalid), .o_tready(o_tready));
+
+   always @(posedge clk)
+     if(o_tvalid & o_tready)
+       $display("TUSER %x\tTLAST %x\tTDATA %x",o_tuser,o_tlast, o_tdata);
+
+endmodule // axi_packet_gate_tb
diff --git a/fpga/usrp3/lib/sim/io_cap_gen/cap_pattern_verifier/Makefile b/fpga/usrp3/lib/sim/io_cap_gen/cap_pattern_verifier/Makefile
new file mode 100644
index 000000000..d80b63901
--- /dev/null
+++ b/fpga/usrp3/lib/sim/io_cap_gen/cap_pattern_verifier/Makefile
@@ -0,0 +1,53 @@
+#
+# Copyright 2015 Ettus Research LLC
+# Copyright 2016 Ettus Research, a National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+#-------------------------------------------------
+# Top-of-Makefile
+#-------------------------------------------------
+# Define BASE_DIR to point to the "top" dir
+BASE_DIR = $(abspath ../../../../top)
+# Include viv_sim_preamble after defining BASE_DIR
+include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
+
+#-------------------------------------------------
+# Design Specific
+#-------------------------------------------------
+# Define part using PART_ID (<device>/<package>/<speedgrade>)
+ARCH = kintex7
+PART_ID = xc7k410t/ffg900/-2
+
+include $(BASE_DIR)/../lib/control/Makefile.srcs
+
+DESIGN_SRCS = $(abspath \
+$(CONTROL_LIB_SRCS) \
+)
+
+DESIGN_SRCS += $(abspath \
+../../../io_cap_gen/cap_pattern_verifier.v \
+)
+
+#-------------------------------------------------
+# Testbench Specific
+#-------------------------------------------------
+include $(BASE_DIR)/../sim/general/Makefile.srcs
+include $(BASE_DIR)/../sim/axi/Makefile.srcs
+
+# Define only one toplevel module
+SIM_TOP = cap_pattern_verifier_tb
+
+SIM_SRCS = \
+$(abspath cap_pattern_verifier_tb.sv) \
+$(SIM_GENERAL_SRCS) \
+$(SIM_AXI_SRCS)
+
+#-------------------------------------------------
+# Bottom-of-Makefile
+#-------------------------------------------------
+# Include all simulator specific makefiles here
+# Each should define a unique target to simulate
+# e.g. xsim, vsim, etc and a common "clean" target
+include $(BASE_DIR)/../tools/make/viv_simulator.mak
diff --git a/fpga/usrp3/lib/sim/io_cap_gen/cap_pattern_verifier/cap_pattern_verifier_tb.sv b/fpga/usrp3/lib/sim/io_cap_gen/cap_pattern_verifier/cap_pattern_verifier_tb.sv
new file mode 100644
index 000000000..53aae3719
--- /dev/null
+++ b/fpga/usrp3/lib/sim/io_cap_gen/cap_pattern_verifier/cap_pattern_verifier_tb.sv
@@ -0,0 +1,199 @@
+//
+// Copyright 2015 Ettus Research LLC
+// Copyright 2015 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+//
+
+
+`timescale 1ns/1ps
+`define NS_PER_TICK 1
+`define NUM_TEST_CASES 10
+
+`include "sim_clks_rsts.vh"
+`include "sim_exec_report.vh"
+`include "sim_axis_lib.svh"
+
+
+module cap_pattern_verifier_tb();
+  `TEST_BENCH_INIT("cap_pattern_verifier_tb",`NUM_TEST_CASES,`NS_PER_TICK)
+
+  // Define all clocks and resets
+  `DEFINE_CLK(clk, 5, 50)            //100MHz sys_clk to generate DDR3 clocking
+  `DEFINE_RESET(rst, 0, 100)          //100ns for GSR to deassert
+
+  axis_master data0 (.clk(clk));
+  axis_master data1 (.clk(clk));
+  assign data0.axis.tready = 1;
+  assign data1.axis.tready = 1;
+
+  wire [31:0] count0, errors0, count1, errors1;
+  wire        locked0, failed0, locked1, failed1;
+
+  cap_pattern_verifier #(
+    .WIDTH(14),
+    .PATTERN("RAMP"),
+    .RAMP_START(14'h0000),
+    .RAMP_STOP(14'h3FFF),
+    .RAMP_INCR(14'h0001),
+    .NTH_CYCLE(1)
+  ) dut0 (
+    .clk(clk),
+    .rst(rst),
+    .valid(data0.axis.tvalid),
+    .data(data0.axis.tdata[13:0]),
+    .count(count0),
+    .errors(errors0),
+    .locked(locked0),
+    .failed(failed0)
+  );
+  
+  cap_pattern_verifier #(
+    .WIDTH(14),
+    .PATTERN("RAMP"),
+    .RAMP_START(14'h0100),
+    .RAMP_STOP(14'h0FFF),
+    .RAMP_INCR(14'h0001),
+    .NTH_CYCLE(1)
+  ) dut1 (
+    .clk(clk),
+    .rst(rst),
+    .valid(data1.axis.tvalid),
+    .data(data1.axis.tdata[13:0]),
+    .count(count1),
+    .errors(errors1),
+    .locked(locked1),
+    .failed(failed1)
+  );
+
+  //------------------------------------------
+  //Main thread for testbench execution
+  //------------------------------------------
+  initial begin : tb_main
+    localparam ASYNC_RST_LEN  = 10;
+    localparam OUTPUT_LATENCY = 2;
+
+    `TEST_CASE_START("Wait for reset");
+    while (rst) @(posedge clk);
+    @(posedge clk);
+    `TEST_CASE_DONE((rst==0));
+    
+    repeat (10) @(posedge clk);
+
+    `TEST_CASE_START("Check reset state");
+    `ASSERT_ERROR(count0==0,"Invalid state: count");
+    `ASSERT_ERROR(errors0==0,"Invalid state: errors");
+    `ASSERT_ERROR(~locked0,"Invalid state: locked");
+    `ASSERT_ERROR(~failed0,"Invalid state: failed");
+    `TEST_CASE_DONE(1);
+
+    `TEST_CASE_START("Simple ramp");
+    data0.push_ramp_pkt(100, 64'd0, 64'h1);
+    repeat (OUTPUT_LATENCY) @(posedge clk);
+    `ASSERT_ERROR(count0==100,"Invalid state: count");
+    `ASSERT_ERROR(errors0==0,"Invalid state: errors");
+    `ASSERT_ERROR(locked0,"Invalid state: locked");
+    `ASSERT_ERROR(~failed0,"Invalid state: failed");
+    `TEST_CASE_DONE(1);
+
+    rst <= 1;
+    @(posedge clk);
+    rst <= 0;
+    repeat (ASYNC_RST_LEN) @(posedge clk);
+
+    `TEST_CASE_START("Multiple ramp iterations");
+    data0.push_ramp_pkt(65536, 64'd0, 64'h1);
+    repeat (OUTPUT_LATENCY) @(posedge clk);
+    `ASSERT_ERROR(count0==65536,"Invalid state: count");
+    `ASSERT_ERROR(errors0==0,"Invalid state: errors");
+    `ASSERT_ERROR(locked0,"Invalid state: locked");
+    `ASSERT_ERROR(~failed0,"Invalid state: failed");
+    `TEST_CASE_DONE(1);
+
+    #(`NS_PER_TICK*0.3333)
+    rst <= 1;
+    #(`NS_PER_TICK*3.25)
+    rst <= 0;
+    repeat (ASYNC_RST_LEN+1) @(posedge clk);
+
+    `TEST_CASE_START("Simple ramp after async reset");
+    data0.push_ramp_pkt(100, 64'd0, 64'h1);
+    repeat (OUTPUT_LATENCY) @(posedge clk);
+    `ASSERT_ERROR(count0==100,"Invalid state: count");
+    `ASSERT_ERROR(errors0==0,"Invalid state: errors");
+    `ASSERT_ERROR(locked0,"Invalid state: locked");
+    `ASSERT_ERROR(~failed0,"Invalid state: failed");
+    `TEST_CASE_DONE(1);
+
+    rst <= 1;
+    @(posedge clk);
+    rst <= 0;
+    repeat (ASYNC_RST_LEN) @(posedge clk);
+
+    `TEST_CASE_START("Simple failure");
+    data0.push_ramp_pkt(9, 64'd0, 64'h1);
+    data0.push_ramp_pkt(100, 64'd10, 64'h1);
+    repeat (OUTPUT_LATENCY) @(posedge clk);
+    `ASSERT_ERROR(count0==109,"Invalid state: count");
+    `ASSERT_ERROR(errors0==1,"Invalid state: errors");
+    `ASSERT_ERROR(locked0,"Invalid state: locked");
+    `ASSERT_ERROR(failed0,"Invalid state: failed");
+    `TEST_CASE_DONE(1);
+
+    `TEST_CASE_START("Late start success");
+    data1.push_ramp_pkt(4096, 64'd0, 64'h1);
+    repeat (OUTPUT_LATENCY) @(posedge clk);
+    `ASSERT_ERROR(count1==4096-256,"Invalid state: count");
+    `ASSERT_ERROR(errors1==0,"Invalid state: errors");
+    `ASSERT_ERROR(locked1,"Invalid state: locked");
+    `ASSERT_ERROR(~failed1,"Invalid state: failed");
+    `TEST_CASE_DONE(1);
+
+    rst <= 1;
+    @(posedge clk);
+    rst <= 0;
+    repeat (ASYNC_RST_LEN) @(posedge clk);
+
+    `TEST_CASE_START("Late failure overshoot");
+    data1.push_ramp_pkt(4097, 64'd0, 64'h1);
+    repeat (OUTPUT_LATENCY) @(posedge clk);
+    `ASSERT_ERROR(count1==4097-256,"Invalid state: count");
+    `ASSERT_ERROR(errors1==1,"Invalid state: errors");
+    `ASSERT_ERROR(locked1,"Invalid state: locked");
+    `ASSERT_ERROR(failed1,"Invalid state: failed");
+    `TEST_CASE_DONE(1);
+
+    `TEST_CASE_START("Metastable data in reset");
+    @(posedge clk);
+    rst <= 1;
+    data0.push_word(14'hXXXX, 1'b0);
+    data0.push_word(14'hXXXX, 1'b1);
+    repeat (OUTPUT_LATENCY) @(posedge clk);
+    `ASSERT_ERROR(count0==0,"Invalid state: count");
+    `ASSERT_ERROR(errors0==0,"Invalid state: errors");
+    `ASSERT_ERROR(~locked0,"Invalid state: locked");
+    `ASSERT_ERROR(~failed0,"Invalid state: failed");
+    `TEST_CASE_DONE(1);
+
+    `TEST_CASE_START("Metastable data out of reset");
+    rst <= 0;
+    repeat (ASYNC_RST_LEN) @(posedge clk);
+    data0.push_word(14'h0000, 1'b0);
+    data0.push_word(14'h0001, 1'b0);
+    data0.push_word(14'h0002, 1'b0);
+    data0.push_word(14'hXXXX, 1'b0);
+    data0.push_word(14'hXXXX, 1'b0);
+    data0.push_word(14'h0005, 1'b0);
+    repeat (OUTPUT_LATENCY) @(posedge clk);
+    `ASSERT_ERROR(count0==6,"Invalid state: count");
+    `ASSERT_ERROR(errors0==2,"Invalid state: errors");
+    `ASSERT_ERROR(locked0,"Invalid state: locked");
+    `ASSERT_ERROR(failed0,"Invalid state: failed");
+    `TEST_CASE_DONE(1);
+
+    `TEST_BENCH_DONE;
+
+  end
+
+endmodule
diff --git a/fpga/usrp3/lib/sim/io_cap_gen/cat_io_lvds/cat_io_lvds_dual_mode_tb.v b/fpga/usrp3/lib/sim/io_cap_gen/cat_io_lvds/cat_io_lvds_dual_mode_tb.v
new file mode 100644
index 000000000..ecb744086
--- /dev/null
+++ b/fpga/usrp3/lib/sim/io_cap_gen/cat_io_lvds/cat_io_lvds_dual_mode_tb.v
@@ -0,0 +1,780 @@
+//
+// Copyright 2016 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: cat_io_lvds_dual_mode_tb
+//
+// Description: Testbench for cat_io_lvds_dual_mode. 
+//
+
+`timescale 1ns/1ps
+
+module cat_io_lvds_dual_mode_tb();
+
+  localparam CLK_PERIOD    = 10;
+  localparam CLK200_PERIOD = 2.5;
+
+  localparam USE_CLOCK_IDELAY   = 1;
+  localparam USE_DATA_IDELAY    = 1;
+  localparam DATA_IDELAY_MODE   = "FIXED";
+  localparam CLOCK_IDELAY_MODE  = "FIXED";
+  localparam INPUT_CLOCK_DELAY  = 16;
+  localparam INPUT_DATA_DELAY   = 0;
+  localparam USE_CLOCK_ODELAY   = 1;
+  localparam USE_DATA_ODELAY    = 1;
+  localparam DATA_ODELAY_MODE   = "FIXED";
+  localparam CLOCK_ODELAY_MODE  = "FIXED";
+  localparam OUTPUT_CLOCK_DELAY = 31;
+  localparam OUTPUT_DATA_DELAY  = 0;
+
+  reg [8*19:0] test_status;
+  reg          check_enabled;   // Controls when output checking is performed
+
+  reg       clk    = 0;
+  reg       rx_clk = 0;
+  reg       clk200 = 0;
+
+  reg       reset;
+  reg       mimo;
+  reg       tx_ch;
+  reg [5:0] rx_d;
+  reg       rx_frame;
+  reg [7:0] rx_count = 0;
+
+  // Each channel's data begins with a unique identifier (A../B.. or C../D..) 
+  // followed by a count, which should always be sequential.
+  wire [11:0] i0 = { 4'hA, rx_count };
+  wire [11:0] q0 = { 4'hB, rx_count };
+  wire [11:0] i1 = { 4'hC, rx_count };
+  wire [11:0] q1 = { 4'hD, rx_count };
+
+  wire radio_clk;
+
+  reg [11:0] tx_i0;
+  reg [11:0] tx_q0;
+  reg [11:0] tx_i1;
+  reg [11:0] tx_q1;
+
+  wire [11:0] rx_i0;
+  wire [11:0] rx_q0;
+  wire [11:0] rx_i1;
+  wire [11:0] rx_q1;
+
+  wire rx_aligned;
+
+  wire        tx_clk_p, tx_clk_n;
+  wire        tx_frame_p, tx_frame_n;
+  wire [5:0]  tx_d_p, tx_d_n;
+
+  reg [4:0]  ctrl_in_data_delay;
+  reg [4:0]  ctrl_in_clk_delay;
+  reg        ctrl_ld_in_data_delay;
+  reg        ctrl_ld_in_clk_delay;
+
+  reg [4:0]  ctrl_out_data_delay;
+  reg [4:0]  ctrl_out_clk_delay;
+  reg        ctrl_ld_out_data_delay;
+  reg        ctrl_ld_out_clk_delay;
+
+
+  //---------------------------------------------------------------------------
+  // Clock Generation
+  //---------------------------------------------------------------------------
+
+  // IODELAYCTRL reference clock
+  always #(CLK200_PERIOD) clk200 = ~clk200;
+
+  // Create an internal clock we'll use to drive the data
+  always #(CLK_PERIOD) clk = ~clk;
+
+  // RF interface clock. Half the rate of clk and out of phase
+  always @(negedge clk) rx_clk <= ~rx_clk;
+
+
+  //---------------------------------------------------------------------------
+  // Tasks
+  //---------------------------------------------------------------------------
+
+  // Output a single burst of 2*len samples. In MIMO mode, this consists of len 
+  // samples on each channel. In SISO mode, this consists of 2*len samples on  
+  // the same channel.
+  task Burst;
+    input [31:0] len;
+    input        do_mimo;
+    begin
+      repeat(len)
+        begin
+          mimo <= do_mimo;
+
+          // Channel 0 sample
+          @(posedge clk);
+          rx_d <= i0[11:6];
+          rx_frame <= 1;
+          @(posedge clk);
+          rx_d <= q0[11:6];
+          rx_frame <= 1;
+          @(posedge clk);
+          rx_d <= i0[5:0];
+          rx_frame <= do_mimo;
+          @(posedge clk);
+          rx_d <= q0[5:0];
+          rx_frame <= do_mimo;
+
+          // Channel 1 sample / Second channel 0 sample
+          @(posedge clk);
+          rx_d <= i1[11:6];
+          rx_frame <= ~do_mimo;
+          @(posedge clk);
+          rx_d <= q1[11:6];
+          rx_frame <= ~do_mimo;
+          @(posedge clk);
+          rx_d <= i1[5:0];
+          rx_frame <= 0;
+          @(posedge clk);
+          rx_d <= q1[5:0];
+          rx_frame <= 0;
+
+          rx_count <= rx_count + 1;
+        end
+    end
+  endtask // Burst
+
+
+  // Test receiving/transmitting 2*len samples, checking len-2 for correctness. 
+  // The output is checked by the Tx and Rx Output Checkers below. We have to 
+  // be a little bit careful when we enable output checking, because it takes a 
+  // few clock cycles for data to propagate through, and we don't want to check 
+  // the outputs when the outputs are not valid.
+  task TestBurst;
+    input [31:0] len;
+    input        do_mimo;
+    begin
+      if (len <= 2) begin
+        $display("ERROR @%0t in %m: In TestBurst, len must be > 2", $time);
+        $finish;
+      end
+
+      // Input several bursts, to fill the pipeline and cause results on the 
+      // outputs before we start checking.
+      Burst(1, do_mimo);
+
+      // Enable output checking
+      check_enabled <= 1'b1;
+
+      // Do the requested length, minus 1
+      Burst(len-2, do_mimo);
+
+      // Disable output checking
+      check_enabled <= 1'b0;
+
+      // Give an extra output to allow data to propagate to the output
+      Burst(1, do_mimo);
+    end
+  endtask // TestBurst
+
+
+  //---------------------------------------------------------------------------
+  // Test Procedure
+  //---------------------------------------------------------------------------
+
+  initial
+    begin
+      // Initial values
+      check_enabled <= 1'b0;
+      test_status <= "Reset";
+      reset = 1;
+      mimo  = 1;
+      ctrl_in_clk_delay      = INPUT_CLOCK_DELAY;
+      ctrl_in_data_delay     = INPUT_DATA_DELAY;
+      ctrl_ld_in_data_delay  = 1'b0;
+      ctrl_ld_in_clk_delay   = 1'b0;
+      ctrl_out_clk_delay     = OUTPUT_CLOCK_DELAY;
+      ctrl_out_data_delay    = OUTPUT_DATA_DELAY;
+      ctrl_ld_out_data_delay = 1'b0;
+      ctrl_ld_out_clk_delay  = 1'b0;
+      repeat(10) @(negedge rx_clk);
+      reset = 0;
+      @(negedge rx_clk);
+
+      //-----------------------------------------------------------------------
+      // Test Changing Delays
+
+      test_status <= "Load IO delays";
+
+      if (CLOCK_IDELAY_MODE == "VAR_LOAD") begin
+        ctrl_ld_in_clk_delay  = 1'b1;
+        @(negedge rx_clk);
+        ctrl_ld_in_clk_delay  = 1'b0;
+        @(negedge rx_clk);
+      end
+
+      if (DATA_IDELAY_MODE == "VAR_LOAD") begin
+        ctrl_ld_in_data_delay = 1'b1;
+        @(negedge rx_clk);
+        ctrl_ld_in_data_delay = 1'b0;
+        @(negedge rx_clk);
+      end
+
+      if (CLOCK_ODELAY_MODE == "VAR_LOAD") begin
+        ctrl_ld_out_clk_delay  = 1'b1;
+        @(negedge rx_clk);
+        ctrl_ld_out_clk_delay  = 1'b0;
+        @(negedge rx_clk);
+      end
+
+      if (DATA_ODELAY_MODE == "VAR_LOAD") begin
+        ctrl_ld_out_data_delay = 1'b1;
+        @(negedge rx_clk);
+        ctrl_ld_out_data_delay = 1'b0;
+        @(negedge rx_clk);
+      end
+
+      //-----------------------------------------------------------------------
+      // Startup
+
+      test_status <= "Startup";
+
+      // Pump a few clock cycles to get things started (flush out X values)
+      Burst(2,1);
+
+      //-----------------------------------------------------------------------
+      // Test MIMO
+
+      // Input data until the Rx circuit aligns
+      test_status <= "Wait align 1";
+      while (!rx_aligned) begin
+        Burst(1,1);
+      end
+
+      // Input some new samples
+      test_status <= "Burst 1 (MIMO)";
+      TestBurst(30, 1);
+
+      // Reset and do another burst
+      test_status <= "Reset 2";
+      reset = 1;
+      repeat(20) @(negedge rx_clk);
+      reset = 0;
+      repeat(2) @(negedge rx_clk);      
+
+      // Input data until the Rx circuit aligns
+      test_status <= "Wait align 2";
+      while (!rx_aligned) begin
+        Burst(1,1);
+      end
+
+      // Input some new samples
+      test_status <= "Burst 2 (MIMO)";
+      TestBurst(23, 1);
+
+      //-----------------------------------------------------------------------
+      // Test SISO (transmit channel 0)
+
+      tx_ch <= 1'b0;
+
+      // Reset and do another burst
+      test_status <= "Reset 3";
+      reset = 1;
+      repeat(20) @(negedge rx_clk);
+      reset = 0;
+      repeat(2) @(negedge rx_clk);      
+
+      // Input data until the Rx circuit aligns in SISO mode
+      test_status <= "Wait align 3";
+      while (!rx_aligned) begin
+        Burst(1,0);
+      end
+
+      // Test SISO mode
+      test_status <= "Burst 3 (SISO, Ch 0)";
+      TestBurst(25, 0);
+
+      // Reset and do another burst
+      test_status <= "Reset 4";
+      reset = 1;
+      repeat(20) @(negedge rx_clk);
+      reset = 0;
+      repeat(2) @(negedge rx_clk);      
+
+      // Input data until the Rx circuit aligns in SISO mode
+      test_status <= "Wait align 4";
+      while (!rx_aligned) begin
+        Burst(1,0);
+      end
+
+      // Test SISO mode
+      test_status <= "Burst 4 (SISO, Ch 0)";
+      TestBurst(27, 0);
+
+      //-----------------------------------------------------------------------
+      // Test SISO (transmit channel 1)
+
+      tx_ch <= 1'b1;
+
+      // Reset and do another burst
+      test_status <= "Reset 5";
+      reset = 1;
+      repeat(20) @(negedge rx_clk);
+      reset = 0;
+      repeat(2) @(negedge rx_clk);      
+
+      // Input data until the Rx circuit aligns in SISO mode
+      test_status <= "Wait align 5";
+      while (!rx_aligned) begin
+        Burst(1,0);
+      end
+
+      // Test SISO mode
+      test_status <= "Burst 5 (SISO, Ch 1)";
+      TestBurst(25, 0);
+
+      // Reset and do another burst
+      test_status <= "Reset 6";
+      reset = 1;
+      repeat(20) @(negedge rx_clk);
+      reset = 0;
+      repeat(2) @(negedge rx_clk);      
+
+      // Input data until the Rx circuit aligns in SISO mode
+      test_status <= "Wait align 6";
+      while (!rx_aligned) begin
+        Burst(1,0);
+      end
+
+      // Test SISO mode
+      test_status <= "Burst 6 (SISO, Ch 1)";
+      TestBurst(27, 0);
+
+      //-----------------------------------------------------------------------
+      // Done
+
+      test_status <= "Finished";
+      repeat(50) @(negedge rx_clk);
+
+      $finish;
+    end
+
+
+  //---------------------------------------------------------------------------
+  // Rx Output Checker
+  //---------------------------------------------------------------------------
+  //
+  // In MIMO mode, we expect to see:
+  //
+  //   rx_i0:  A00, A01, A02, A03, ...
+  //   rx_q0:  B00, B01, B02, B03, ...
+  //   rx_i1:  C00, C01, C02, C03, ...
+  //   rx_q1:  D00, D01, D02, D03, ...
+  //
+  // In SISO mode, we expect to see (with twice the clock rate):
+  //
+  //   rx_i0:  A00, C00, A01, C01, ...
+  //   rx_q0:  B00, D00, B01, D01, ...
+  //   rx_i1:  A00, C00, A01, C01, ...
+  //   rx_q1:  B00, D00, B01, D01, ...
+  //
+  //---------------------------------------------------------------------------
+
+  reg first_rx_check = 1'b1;
+  reg [11:0] rx_i0_del1, rx_i0_del2;
+  reg [11:0] rx_q0_del1, rx_q0_del2;
+  reg [11:0] rx_i1_del1, rx_i1_del2;
+  reg [11:0] rx_q1_del1, rx_q1_del2;
+
+  always @(posedge radio_clk)
+  begin
+    if (check_enabled) begin
+      if (!first_rx_check) begin
+
+        if (mimo) begin
+
+          // Check prefix for channel 0
+          if (rx_i0[11:8] != 4'hA || rx_q0[11:8] != 4'hB) begin
+            $display("ERROR @%0t in %m: Rx channel 0 didn't have expected A/B prefix in MIMO mode", $time);
+            $finish;
+          end
+
+          // Check prefix for channel 1
+          if (rx_i1[11:8] != 4'hC || rx_q1[11:8] != 4'hD) begin
+            $display("ERROR @%0t in %m: Rx channel 1 didn't have expected C/D in MIMO mode", $time);
+            $finish;
+          end
+
+          // All outputs should have the same count in MIMO mode
+          if (! (rx_i0[7:0] == rx_q0[7:0] &&
+                 rx_i0[7:0] == rx_i1[7:0] && 
+                 rx_i0[7:0] == rx_q1[7:0]) ) begin
+            $display("ERROR @%0t in %m: Rx data counts didn't match on all outputs in MIMO mode", $time);
+            $finish;
+          end
+
+          // Make sure the count increments
+          if (rx_i0[7:0] != rx_i0_del1[7:0] + 8'd1 || rx_q0[7:0] != rx_q0_del1[7:0] + 8'd1 ||
+              rx_i1[7:0] != rx_i1_del1[7:0] + 8'd1 || rx_q1[7:0] != rx_q1_del1[7:0] + 8'd1) begin
+            $display("ERROR @%0t in %m: Rx data count didn't increment as expected", $time);
+            $finish;
+          end
+
+        end else begin  // if (mimo)
+
+          // In SISO mode, both outputs should be the same
+          if (rx_i0 != rx_i1 || rx_q0 != rx_q1) begin
+            $display("ERROR @%0t in %m: Rx channel 0 and 1 don't match in SISO mode", $time);
+            $finish;
+          end
+
+          // Check channel 0 prefix. No need to check channel 1, since we 
+          // already checked that the channels match.
+          if (!((rx_i0[11:8] == 4'hA && rx_q0[11:8] == 4'hB) || 
+                (rx_i0[11:8] == 4'hC && rx_q0[11:8] == 4'hD))) begin
+            $display("ERROR @%0t in %m: Rx data didn't have expected A/B or C/D prefix in SISO mode", $time);
+            $finish;
+          end
+
+          // Make sure we're alternating between channel data. No need to check 
+          // channel 1, since we already checked that the channels match.
+          if (!((rx_i0[11:8] == 4'hA && rx_i0_del1[11:8] == 4'hC) ||
+                (rx_i0[11:8] == 4'hC && rx_i0_del1[11:8] == 4'hA) ||
+                (rx_q0[11:8] == 4'hB && rx_q0_del1[11:8] == 4'hD) ||
+                (rx_q0[11:8] == 4'hD && rx_q0_del1[11:8] == 4'hB))) begin
+            $display("ERROR @%0t in %m: Rx data not toggling between channel data in SISO mode", $time);
+            $finish;
+          end
+
+          // Make sure the counts are the same for both I and Q. No need to 
+          // check channel 1, since we already checked that the channels match.
+          if (rx_i0[7:0] != rx_q0[7:0]) begin
+            $display("ERROR @%0t in %m: Rx data counts didn't match on all outputs in SISO mode", $time);
+            $finish;
+          end
+
+          // Make sure the count increments every other clock cycle. No need to 
+          // check channel 1, since we already checked that the channels match.
+          if (!(
+              rx_i0[7:0] != rx_i0_del2[7:0] + 8'd1 && (rx_i0[7:0] == rx_i0_del1[7:0] || rx_i0[7:0] == rx_i0_del1[7:0] + 8'd1) &&
+              rx_q0[7:0] != rx_q0_del2[7:0] + 8'd1 && (rx_q0[7:0] == rx_q0_del1[7:0] || rx_q0[7:0] == rx_q0_del1[7:0] + 8'd1)
+            )) begin
+            $display("ERROR @%0t in %m: Rx data count didn't increment as expected", $time);
+            $finish;
+          end
+
+        end  // if (mimo)
+      end  // if (!first_rx_check)
+
+      // Make sure we've captured at least one set of values, so we have a 
+      // previous set to look back to.
+      first_rx_check <= 1'b0;
+
+    end else begin  // if (check_enabled)
+      first_rx_check <= 1'b1;
+    end  // if (check_enabled)
+
+    // Save values seen this cycle
+    rx_i0_del1 <= rx_i0;
+    rx_q0_del1 <= rx_q0;
+    rx_i1_del1 <= rx_i1;
+    rx_q1_del1 <= rx_q1;
+    rx_i0_del2 <= rx_i0_del2;
+    rx_q0_del2 <= rx_q0_del2;
+    rx_i1_del2 <= rx_i1_del2;
+    rx_q1_del2 <= rx_q1_del2;
+  end
+
+
+  //---------------------------------------------------------------------------
+  // Tx Output Checker
+  //---------------------------------------------------------------------------
+  //
+  // The code implements a loopback, so the output should match the input. In 
+  // SISO mode, however, the frame signal may not be aligned.
+  //
+  //---------------------------------------------------------------------------
+
+  reg first_tx_check;
+  reg [11:0] tx_i0_del1;
+  reg [11:0] tx_q0_del1;
+  reg [11:0] tx_i1_del1;
+  reg [11:0] tx_q1_del1;
+  reg        tx_frame_del1;
+
+  reg [11:0] tx_i0_check;
+  reg [11:0] tx_q0_check;
+  reg [11:0] tx_i1_check;
+  reg [11:0] tx_q1_check;
+  reg [7:0]  tx_frame_check;
+
+
+  always @(posedge tx_clk_p)
+  begin
+    tx_frame_del1 <= tx_frame_p;
+  end
+
+
+  always @(posedge tx_clk_p)
+  begin
+    if (tx_frame_p && !tx_frame_del1) begin
+      //-----------------------------------------------------------------------
+      // Grab two samples from the output, starting at frame boundary
+      //-----------------------------------------------------------------------
+
+      // Channel 0 sample
+      tx_i0_check[11:6] <= tx_d_p;
+      tx_frame_check[7] <= tx_frame_p;
+      @(posedge tx_clk_n);
+      tx_q0_check[11:6] <= tx_d_p;
+      tx_frame_check[6] <= tx_frame_p;
+      @(posedge tx_clk_p);
+      tx_i0_check[5:0] <= tx_d_p;
+      tx_frame_check[5] <= tx_frame_p;
+      @(posedge tx_clk_n);
+      tx_q0_check[5:0] <= tx_d_p;
+      tx_frame_check[4] <= tx_frame_p;
+
+      // Channel 1 sample / Second channel 0 sample
+      @(posedge tx_clk_p);
+      tx_i1_check[11:6] <= tx_d_p;
+      tx_frame_check[3] <= tx_frame_p;
+      @(posedge tx_clk_n);
+      tx_q1_check[11:6] <= tx_d_p;
+      tx_frame_check[2] <= tx_frame_p;
+      @(posedge tx_clk_p);
+      tx_i1_check[5:0] <= tx_d_p;
+      tx_frame_check[1] <= tx_frame_p;
+      @(posedge tx_clk_n);
+      tx_q1_check[5:0] <= tx_d_p;
+      tx_frame_check[0] <= tx_frame_p;
+
+      #1   // Minimum delay for *_check registers to update in simulation
+
+      if (check_enabled) begin
+        if (!first_tx_check) begin
+   
+          if (mimo) begin
+            //-----------------------------------------------------------------
+            // Check MIMO output
+            //-----------------------------------------------------------------
+
+            // Check that the frame signal is correct
+            if (tx_frame_check != 8'b11110000) begin
+              $display("ERROR @%0t in %m: Tx frame was not correct in MIMO mode", $time);
+              $finish;
+            end
+  
+            // Check prefix for channel 0
+            if (tx_i0_check[11:8] != 4'hA || tx_q0_check[11:8] != 4'hB) begin
+              $display("ERROR @%0t in %m: Tx channel 0 didn't have expected A/B prefix in MIMO mode", $time);
+              $finish;
+            end
+  
+            // Check prefix for channel 1
+            if (tx_i1_check[11:8] != 4'hC || tx_q1_check[11:8] != 4'hD) begin
+              $display("ERROR @%0t in %m: Tx channel 1 didn't have expected C/D in MIMO mode", $time);
+              $finish;
+            end
+  
+            // All outputs should have the same count in MIMO mode
+            if (! (tx_i0_check[7:0] == tx_q0_check[7:0] && 
+                   tx_i0_check[7:0] == tx_i1_check[7:0] &&
+                   tx_i0_check[7:0] == tx_q1_check[7:0]) ) begin
+              $display("ERROR @%0t in %m: Rx data counts didn't match on all outputs in MIMO mode", $time);
+              $finish;
+            end
+  
+            // Make sure the count increments
+            if (tx_i0_check[7:0] != tx_i0_del1[7:0] + 8'd1 || tx_q0_check[7:0] != tx_q0_del1[7:0] + 8'd1 ||
+                tx_i1_check[7:0] != tx_i1_del1[7:0] + 8'd1 || tx_q1_check[7:0] != tx_q1_del1[7:0] + 8'd1) begin
+              $display("ERROR @%0t in %m: Rx data count didn't increment as expected", $time);
+              $finish;
+            end
+          
+          end else begin  
+            //-----------------------------------------------------------------
+            // Check SISO Output
+            //-----------------------------------------------------------------
+
+            // Check that the frame signal is correct
+            if (tx_frame_check != 8'b11001100) begin
+              $display("ERROR @%0t in %m: Tx frame was not correct in SISO mode", $time);
+              $finish;
+            end
+
+
+            // In SISO mode, the data we get depends on which channel is 
+            // selected.
+            //
+            //        Channel 0:                   Channel 1:
+            //  ...,A01,B01,A02,B02,...  OR  ...,C01,D01,C02,D02,...
+            // 
+            // So we should receive
+            //
+            //       A01 A03 A05
+            //   ... B01 B03 B05 ...
+            //       A02 B04 A06
+            //       B02 B04 A07
+            //
+            // or
+            //       C01 C03 C05
+            //   ... D01 D03 D05 ...
+            //       C02 C04 C06
+            //       D02 D04 D07
+            //
+
+            // Check prefixes
+            if (!(
+              // Either A,B on channel 0 or C,D on channel 1
+              ((tx_ch == 0 &&
+                tx_i0_check[11:8] == 4'hA &&
+                tx_q0_check[11:8] == 4'hB) ||
+               (tx_ch == 1 && 
+                tx_i0_check[11:8] == 4'hC &&
+                tx_q0_check[11:8] == 4'hD)) && 
+              // Samples 0 and 1 prefixes equal samples 2 and 3 prefixes
+              (tx_i0_check[11:8] == tx_i1_check[11:8]  && 
+               tx_q0_check[11:8] == tx_q1_check[11:8])
+              )) begin
+              $display("ERROR @%0t in %m: Tx channel didn't have expected prefixes in SISO mode", $time);
+              $finish;
+            end
+  
+            // Check that the data count matches between samples
+            if (!(
+              tx_i0_check[7:0] == tx_q0_check[7:0] &&
+              tx_i1_check[7:0] == tx_q1_check[7:0] &&
+              tx_i0_check[7:0] == tx_i1_check[7:0] - 8'd1
+              )) begin
+              $display("ERROR @%0t in %m: Tx channel data counts didn't correlate in SISO mode", $time);
+              $finish;
+            end
+
+            // Make sure the count increments form one burst to the next
+            if (tx_i0_check[7:0] != tx_i0_del1[7:0] + 8'd2 || 
+                tx_q0_check[7:0] != tx_q0_del1[7:0] + 8'd2 ||
+                tx_i1_check[7:0] != tx_i1_del1[7:0] + 8'd2 ||
+                tx_q1_check[7:0] != tx_q1_del1[7:0] + 8'd2) begin
+              $display("ERROR @%0t in %m: Tx data count didn't increment as expected", $time);
+              $finish;
+            end
+          
+          end
+
+        end else begin  // if (!first_tx_check)
+          // Make sure we've captured at least one set of values, so we have a 
+          // previous set to look back to.
+          first_tx_check <= 1'b0;
+        end  // if (!first_tx_check)
+
+        // Save values seen this cycle
+        tx_i0_del1 <= tx_i0_check;
+        tx_q0_del1 <= tx_q0_check;
+        tx_i1_del1 <= tx_i1_check;
+        tx_q1_del1 <= tx_q1_check;
+
+      end else begin  // if (check_enabled)        
+        first_tx_check <= 1'b1;
+
+      end  // if (check_enabled)
+
+    end  // if (tx_frame_p && !tx_frame_del1)
+
+  end
+
+
+  //---------------------------------------------------------------------------
+  // Tx Input Data Generation
+  //---------------------------------------------------------------------------
+  //
+  // Input a known data pattern similar to the Rx patten.
+  //
+  //   I0:     A01 A02 A03
+  //   Q0: ... B01 B02 B03 ...
+  //   I1:     C01 C02 C03
+  //   Q1:     D01 D02 D03
+  //
+  //---------------------------------------------------------------------------
+
+  reg [7:0] tx_count = 0;
+
+  // Loop the Rx interface of DUT back to its Tx interface
+  always @(posedge radio_clk) begin
+    tx_i0 <= { 4'hA, tx_count };
+    tx_q0 <= { 4'hB, tx_count };
+    tx_i1 <= { 4'hC, tx_count };
+    tx_q1 <= { 4'hD, tx_count };
+    tx_count <= tx_count + 7'd1;
+  end
+
+
+  //---------------------------------------------------------------------------
+  // DUT
+  //---------------------------------------------------------------------------
+
+  cat_io_lvds_dual_mode #(
+    .INVERT_FRAME_RX    (0),
+    .INVERT_DATA_RX     (6'b00_0000),
+    .INVERT_FRAME_TX    (0),
+    .INVERT_DATA_TX     (6'b00_0000),
+    .USE_CLOCK_IDELAY   (USE_CLOCK_IDELAY),
+    .USE_DATA_IDELAY    (USE_DATA_IDELAY),
+    .DATA_IDELAY_MODE   (DATA_IDELAY_MODE),
+    .CLOCK_IDELAY_MODE  (CLOCK_IDELAY_MODE),
+    .INPUT_CLOCK_DELAY  (INPUT_CLOCK_DELAY),
+    .INPUT_DATA_DELAY   (INPUT_DATA_DELAY),
+    .USE_CLOCK_ODELAY   (USE_CLOCK_ODELAY),
+    .USE_DATA_ODELAY    (USE_DATA_ODELAY),
+    .DATA_ODELAY_MODE   (DATA_ODELAY_MODE),
+    .CLOCK_ODELAY_MODE  (CLOCK_ODELAY_MODE),
+    .OUTPUT_CLOCK_DELAY (OUTPUT_CLOCK_DELAY),
+    .OUTPUT_DATA_DELAY  (OUTPUT_DATA_DELAY)
+  ) cat_io_lvds_dual_mode_dut (
+    .rst    (reset),
+    .clk200 (clk200),
+    
+    // Data and frame timing
+    .a_mimo  (mimo),
+    .a_tx_ch (tx_ch),
+    
+    // Delay control interface
+    .ctrl_clk               (rx_clk),
+    //
+    .ctrl_in_data_delay     (ctrl_in_data_delay),
+    .ctrl_in_clk_delay      (ctrl_in_clk_delay),
+    .ctrl_ld_in_data_delay  (ctrl_ld_in_data_delay),
+    .ctrl_ld_in_clk_delay   (ctrl_ld_in_clk_delay),
+    //
+    .ctrl_out_data_delay    (ctrl_out_data_delay),
+    .ctrl_out_clk_delay     (ctrl_out_clk_delay),
+    .ctrl_ld_out_data_delay (ctrl_ld_out_data_delay),
+    .ctrl_ld_out_clk_delay  (ctrl_ld_out_clk_delay),
+    
+    // Baseband sample interface
+    .radio_clk  (radio_clk),
+    .rx_aligned (rx_aligned),
+    //
+    .rx_i0      (rx_i0),
+    .rx_q0      (rx_q0),
+    .rx_i1      (rx_i1),
+    .rx_q1      (rx_q1),
+    //
+    .tx_i0      (tx_i0),
+    .tx_q0      (tx_q0),
+    .tx_i1      (tx_i1),
+    .tx_q1      (tx_q1),
+    
+    // Catalina interface
+    .rx_clk_p   (rx_clk),
+    .rx_clk_n   (~rx_clk),
+    .rx_frame_p (rx_frame),
+    .rx_frame_n (~rx_frame),
+    .rx_d_p     (rx_d),
+    .rx_d_n     (~rx_d),
+    //
+    .tx_clk_p   (tx_clk_p),
+    .tx_clk_n   (tx_clk_n),
+    .tx_frame_p (tx_frame_p),
+    .tx_frame_n (tx_frame_n),
+    .tx_d_p     (tx_d_p),
+    .tx_d_n     (tx_d_n)
+  );
+
+endmodule // cat_io_lvds_dual_mode_tb
diff --git a/fpga/usrp3/lib/sim/io_cap_gen/cat_io_lvds/cat_io_lvds_tb.v b/fpga/usrp3/lib/sim/io_cap_gen/cat_io_lvds/cat_io_lvds_tb.v
new file mode 100644
index 000000000..91cd6f938
--- /dev/null
+++ b/fpga/usrp3/lib/sim/io_cap_gen/cat_io_lvds/cat_io_lvds_tb.v
@@ -0,0 +1,350 @@
+//
+// Copyright 2016 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: cat_io_lvds_tb
+//
+// Description: Testbench for cat_io_lvds.
+//
+
+`timescale 1ns/1ps
+
+module cat_io_lvds_tb();
+
+  localparam CLK_PERIOD    = 10;
+  localparam CLK200_PERIOD = 2.5;
+
+  localparam FRAME_SAMPLE = 0;
+
+  localparam USE_CLOCK_IDELAY   = 1;
+  localparam USE_DATA_IDELAY    = 1;
+  localparam DATA_IDELAY_MODE   = "VAR_LOAD";
+  localparam CLOCK_IDELAY_MODE  = "VAR_LOAD";
+  localparam INPUT_CLOCK_DELAY  = 0;
+  localparam INPUT_DATA_DELAY   = 0;
+  localparam USE_CLOCK_ODELAY   = 1;
+  localparam USE_DATA_ODELAY    = 1;
+  localparam DATA_ODELAY_MODE   = "VAR_LOAD";
+  localparam CLOCK_ODELAY_MODE  = "VAR_LOAD";
+  localparam OUTPUT_CLOCK_DELAY = 0;
+  localparam OUTPUT_DATA_DELAY  = 0;
+
+  reg [8*19:0] test_status;
+
+  reg       clk      = 0;
+  reg       rx_clk   = 0;
+  reg       clk200   = 0;
+
+  reg       reset;
+  reg       mimo;
+  reg [5:0] rx_d;
+  reg       rx_frame;
+  reg [7:0] count;
+
+//  initial $dumpfile("catcap_ddr_lvds_tb.vcd");
+//  initial $dumpvars(0,catcap_ddr_lvds_tb);
+
+  wire [11:0] i0 = {4'hA,count};
+  wire [11:0] q0 = {4'hB,count};
+  wire [11:0] i1 = {4'hC,count};
+  wire [11:0] q1 = {4'hD,count};
+
+  wire radio_clk;
+
+  reg [11:0] tx_i0;
+  reg [11:0] tx_q0;
+  reg [11:0] tx_i1;
+  reg [11:0] tx_q1;
+
+  wire [11:0] rx_i0;
+  wire [11:0] rx_q0;
+  wire [11:0] rx_i1;
+  wire [11:0] rx_q1;
+
+  wire rx_aligned;
+
+  wire        tx_clk_p, tx_clk_n;
+  wire        tx_frame_p, tx_frame_n;
+  wire [5:0]  tx_d_p, tx_d_n;
+
+  reg [4:0]  ctrl_in_data_delay;
+  reg [4:0]  ctrl_in_clk_delay;
+  reg        ctrl_ld_in_data_delay;
+  reg        ctrl_ld_in_clk_delay;
+
+  reg [4:0]  ctrl_out_data_delay;
+  reg [4:0]  ctrl_out_clk_delay;
+  reg        ctrl_ld_out_data_delay;
+  reg        ctrl_ld_out_clk_delay;
+
+
+  //---------------------------------------------------------------------------
+  // Clock Generation
+  //---------------------------------------------------------------------------
+
+  // IODELAYCTRL reference clock
+  always #(CLK200_PERIOD) clk200 = ~clk200;
+
+  // Create an internal clock we'll use to drive the data
+  always #(CLK_PERIOD) clk = ~clk;
+
+  // RF interface clock. Half the rate of clk and out of phase
+  always @(negedge clk) rx_clk <= ~rx_clk;
+
+
+  //---------------------------------------------------------------------------
+  // Tasks
+  //---------------------------------------------------------------------------
+
+  task BURST;
+    input [31:0] len;
+    input        do_mimo;
+    begin
+      count <= 0;
+      repeat(len)
+        begin
+          mimo <= do_mimo;
+
+          // Channel 0 sample
+          @(posedge clk);
+          rx_d <= i0[11:6];
+          rx_frame <= 1;
+          @(posedge clk);
+          rx_d <= q0[11:6];
+          rx_frame <= 1;
+          @(posedge clk);
+          rx_d <= i0[5:0];
+          rx_frame <= ~FRAME_SAMPLE;
+          @(posedge clk);
+          rx_d <= q0[5:0];
+          rx_frame <= ~FRAME_SAMPLE;
+
+          if (do_mimo) begin
+            // Channel 1 sample
+            @(posedge clk);
+            rx_d <= i1[11:6];
+            rx_frame <= FRAME_SAMPLE;
+            @(posedge clk);
+            rx_d <= q1[11:6];
+            rx_frame <= FRAME_SAMPLE;
+            @(posedge clk);
+            rx_d <= i1[5:0];
+            rx_frame <= 0;
+            @(posedge clk);
+            rx_d <= q1[5:0];
+            rx_frame <= 0;
+          end else begin
+            if (!FRAME_SAMPLE) begin
+              // When we frame every two samples (one from each channel), in
+              // MIMO mode, we should only grab channel 0. So input garbage on
+              // channel 1 to make sure the data doesn't get used.
+              @(posedge clk);
+              rx_d <= 6'bXXXXXX;
+              rx_frame <= FRAME_SAMPLE;
+              @(posedge clk);
+              rx_d <= 6'bXXXXXX;
+              rx_frame <= FRAME_SAMPLE;
+              @(posedge clk);
+              rx_d <= 6'bXXXXXX;
+              rx_frame <= 0;
+              @(posedge clk);
+              rx_d <= 6'bXXXXXX;
+              rx_frame <= 0;
+            end else begin
+              // When every sample is framed, we might sync align to either
+              // channel (no way to tell them apart), so input the channel 1
+              // data, but we should only see one channel's data duplicated on
+              // both outputs.
+              @(posedge clk);
+              rx_d <= i1[11:6];
+              rx_frame <= FRAME_SAMPLE;
+              @(posedge clk);
+              rx_d <= q1[11:6];
+              rx_frame <= FRAME_SAMPLE;
+              @(posedge clk);
+              rx_d <= i1[5:0];
+              rx_frame <= 0;
+              @(posedge clk);
+              rx_d <= q1[5:0];
+              rx_frame <= 0;
+            end
+          end
+
+          count <= count + 1;
+        end
+    end
+  endtask // BURST
+
+
+  //---------------------------------------------------------------------------
+  // Test Procedure
+  //---------------------------------------------------------------------------
+
+  initial
+    begin
+      // Initial values
+      test_status <= "Reset";
+      reset = 1;
+      mimo = 1;
+      ctrl_in_data_delay = 5'd0;
+      ctrl_in_clk_delay = 5'd8;
+      ctrl_ld_in_data_delay = 1'b0;
+      ctrl_ld_in_clk_delay = 1'b0;
+      ctrl_out_data_delay = 5'd0;
+      ctrl_out_clk_delay = 5'd16;
+      ctrl_ld_out_data_delay = 1'b0;
+      ctrl_ld_out_clk_delay = 1'b0;
+      repeat(10) @(negedge rx_clk);
+      reset = 0;
+      @(negedge rx_clk);
+
+      // Load new input delay values
+      test_status <= "Load input delays";
+      ctrl_ld_in_data_delay = 1'b1;
+      ctrl_ld_in_clk_delay = 1'b1;
+      @(negedge rx_clk);
+      ctrl_ld_in_data_delay = 1'b0;
+      ctrl_ld_in_clk_delay = 1'b0;
+
+      // Load new output delay values
+      test_status <= "Load output delays";
+      ctrl_ld_out_data_delay = 1'b1;
+      ctrl_ld_out_clk_delay = 1'b1;
+      @(negedge rx_clk);
+      ctrl_ld_out_data_delay = 1'b0;
+      ctrl_ld_out_clk_delay = 1'b0;
+
+      // Input data until the Rx circuit aligns
+      test_status <= "Wait align";
+      while (!rx_aligned) begin
+        BURST(1,1);
+      end
+
+      // Input some new samples
+      test_status <= "Burst 1 (MIMO)";
+      BURST(30, 1);
+
+      // Reset and do another burst
+      test_status <= "Reset 2";
+      reset = 1;
+      repeat(20) @(negedge rx_clk);
+      reset = 0;
+      repeat(2) @(negedge rx_clk);
+
+      // Input data until the Rx circuit aligns
+      test_status <= "Wait align 2";
+      while (!rx_aligned) begin
+        BURST(1,1);
+      end
+
+      // Input some new samples
+      test_status <= "Burst 2 (MIMO)";
+      BURST(30, 1);
+
+      // Reset and do another burst
+      test_status <= "Reset 3";
+      reset = 1;
+      repeat(20) @(negedge rx_clk);
+      reset = 0;
+      repeat(2) @(negedge rx_clk);
+
+      // Input data until the Rx circuit aligns in SISO mode
+      test_status <= "Wait align 3";
+      while (!rx_aligned) begin
+        BURST(1,0);
+      end
+
+      // Switch to SISO mode
+      test_status <= "Burst 3 (SISO)";
+      BURST(25,0);
+
+      repeat(50) @(negedge rx_clk);
+
+
+      $finish;
+    end
+
+
+  //---------------------------------------------------------------------------
+  // DUT
+  //---------------------------------------------------------------------------
+
+  // Loop the Rx interface of cat_io_lvds back to its Tx interface
+  always @(posedge radio_clk) begin
+    tx_i0 = rx_i0;
+    tx_q0 = rx_q0;
+    tx_i1 = rx_i1;
+    tx_q1 = rx_q1;
+  end
+
+  cat_io_lvds #(
+    .INVERT_FRAME_RX    (0),
+    .INVERT_DATA_RX     (6'b00_0000),
+    .INVERT_FRAME_TX    (0),
+    .INVERT_DATA_TX     (6'b00_0000),
+    .USE_CLOCK_IDELAY   (USE_CLOCK_IDELAY  ),
+    .USE_DATA_IDELAY    (USE_DATA_IDELAY   ),
+    .DATA_IDELAY_MODE   (DATA_IDELAY_MODE  ),
+    .CLOCK_IDELAY_MODE  (CLOCK_IDELAY_MODE ),
+    .INPUT_CLOCK_DELAY  (INPUT_CLOCK_DELAY ),
+    .INPUT_DATA_DELAY   (INPUT_DATA_DELAY  ),
+    .USE_CLOCK_ODELAY   (USE_CLOCK_ODELAY  ),
+    .USE_DATA_ODELAY    (USE_DATA_ODELAY   ),
+    .DATA_ODELAY_MODE   (DATA_ODELAY_MODE  ),
+    .CLOCK_ODELAY_MODE  (CLOCK_ODELAY_MODE ),
+    .OUTPUT_CLOCK_DELAY (OUTPUT_CLOCK_DELAY),
+    .OUTPUT_DATA_DELAY  (OUTPUT_DATA_DELAY )
+  ) cat_io_lvds_i0 (
+    .rst    (reset),
+    .clk200 (clk200),
+
+    // Data and frame timing
+    .mimo         (mimo),
+    .frame_sample (FRAME_SAMPLE[0]),
+
+    // Delay control interface
+    .ctrl_clk               (rx_clk),
+    //
+    .ctrl_in_data_delay     (ctrl_in_data_delay),
+    .ctrl_in_clk_delay      (ctrl_in_clk_delay),
+    .ctrl_ld_in_data_delay  (ctrl_ld_in_data_delay),
+    .ctrl_ld_in_clk_delay   (ctrl_ld_in_clk_delay),
+    //
+    .ctrl_out_data_delay    (ctrl_out_data_delay),
+    .ctrl_out_clk_delay     (ctrl_out_clk_delay),
+    .ctrl_ld_out_data_delay (ctrl_ld_out_data_delay),
+    .ctrl_ld_out_clk_delay  (ctrl_ld_out_clk_delay),
+
+    // Baseband sample interface
+    .radio_clk    (radio_clk),
+    .radio_clk_2x (),
+    .rx_aligned   (rx_aligned),
+    //
+    .rx_i0        (rx_i0),
+    .rx_q0        (rx_q0),
+    .rx_i1        (rx_i1),
+    .rx_q1        (rx_q1),
+    //
+    .tx_i0        (tx_i0),
+    .tx_q0        (tx_q0),
+    .tx_i1        (tx_i1),
+    .tx_q1        (tx_q1),
+
+    // Catalina interface
+    .rx_clk_p   (rx_clk),
+    .rx_clk_n   (~rx_clk),
+    .rx_frame_p (rx_frame),
+    .rx_frame_n (~rx_frame),
+    .rx_d_p     (rx_d),
+    .rx_d_n     (~rx_d),
+    //
+    .tx_clk_p   (tx_clk_p),
+    .tx_clk_n   (tx_clk_n),
+    .tx_frame_p (tx_frame_p),
+    .tx_frame_n (tx_frame_n),
+    .tx_d_p     (tx_d_p),
+    .tx_d_n     (tx_d_n)
+  );
+
+endmodule // cat_io_lvds_tb
diff --git a/fpga/usrp3/lib/sim/io_cap_gen/catcap/catcap_tb.build b/fpga/usrp3/lib/sim/io_cap_gen/catcap/catcap_tb.build
new file mode 100755
index 000000000..827ab0628
--- /dev/null
+++ b/fpga/usrp3/lib/sim/io_cap_gen/catcap/catcap_tb.build
@@ -0,0 +1,21 @@
+
+#!/bin/sh
+
+rm -rf isim* 
+rm -rf catcap_tb
+rm -rf fuse*
+\
+#     --sourcelibdir ../../models \
+
+vlogcomp \
+    --sourcelibext .v \
+    --sourcelibdir ../../coregen \
+    --sourcelibdir ../../control_lib \
+    --sourcelibdir . \
+    --sourcelibdir $XILINX/verilog/src \
+    --sourcelibdir $XILINX/verilog/src/unisims \
+    --work work \
+    catcap_tb.v
+
+ 
+fuse -o catcap_tb catcap_tb
\ No newline at end of file
diff --git a/fpga/usrp3/lib/sim/io_cap_gen/catcap/catcap_tb.v b/fpga/usrp3/lib/sim/io_cap_gen/catcap/catcap_tb.v
new file mode 100644
index 000000000..f300cc32f
--- /dev/null
+++ b/fpga/usrp3/lib/sim/io_cap_gen/catcap/catcap_tb.v
@@ -0,0 +1,115 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+`timescale 1ns/1ps
+
+module catcap_tb();
+
+   wire GSR, GTS;
+   glbl glbl( );
+
+   reg 	clk    = 0;
+   reg 	ddrclk = 0;
+   reg 	reset  = 1;
+
+   always #100 clk = ~clk;
+   always @(negedge clk) ddrclk <= ~ddrclk;
+
+   initial $dumpfile("catcap_tb.vcd");
+   initial $dumpvars(0,catcap_tb);
+
+   wire [11:0] i0 = {4'hA,count};
+   wire [11:0] q0 = {4'hB,count};
+   wire [11:0] i1 = {4'hC,count};
+   wire [11:0] q1 = {4'hD,count};
+
+   reg 	       mimo;
+   reg [11:0]  pins;
+   reg 	       frame;
+   reg [7:0]   count;
+   
+   initial
+     begin
+	#1000 reset = 0;
+	MIMO_BURST(4);
+	MIMO_BURST(5);
+	BURST(4);
+	BURST(5);
+	#2000;
+	$finish;
+     end
+   
+   task BURST;
+      input [7:0] len;
+      begin
+	 frame <= 0;
+	 @(posedge clk);
+	 @(posedge clk);
+	 mimo <= 0;
+	 @(posedge clk);
+	 @(posedge clk);
+	 @(posedge clk);
+	 @(posedge ddrclk);
+	 count <= 0;
+	 repeat(len)
+	   begin
+	      @(posedge clk);
+	      pins <= i0;
+	      frame <= 1;
+	      @(posedge clk);
+	      pins <= q0;
+	      frame <= 0;
+	      count <= count + 1;
+	   end
+      end
+   endtask // BURST
+   
+   task MIMO_BURST;
+      input [7:0] len;
+      begin
+	 frame <= 0;
+	 @(posedge clk);
+	 @(posedge clk);
+	 mimo <= 1;
+	 @(posedge clk);
+	 @(posedge clk);
+	 @(posedge clk);
+	 @(posedge ddrclk);
+	 count <= 0;
+	 repeat(len)
+	   begin
+	      @(posedge clk);
+	      pins <= i0;
+	      frame <= 1;
+	      @(posedge clk);
+	      pins <= q0;
+	      @(posedge clk);
+	      pins <= i1;
+	      frame <= 0;
+	      @(posedge clk);
+	      pins <= q1;
+	      count <= count + 1;
+	   end
+	 @(posedge clk);
+	 @(posedge clk);
+      end
+   endtask // MIMO_BURST
+      
+   wire        rx_clk, rx_strobe;
+   wire [11:0] i0o,i1o,q0o,q1o;
+   
+   catcap_ddr_cmos catcap
+     (.data_clk(ddrclk),
+      .reset(reset),
+      .mimo(mimo),
+      .rx_frame(frame),
+      .rx_d(pins),
+      .rx_clk(rx_clk),
+      .rx_strobe(rx_strobe),
+      .i0(i0o),.q0(q0o),
+      .i1(i1o),.q1(q1o));
+   
+endmodule // hb_chain_tb
diff --git a/fpga/usrp3/lib/sim/io_cap_gen/catgen/catgen_tb.build b/fpga/usrp3/lib/sim/io_cap_gen/catgen/catgen_tb.build
new file mode 100755
index 000000000..072495479
--- /dev/null
+++ b/fpga/usrp3/lib/sim/io_cap_gen/catgen/catgen_tb.build
@@ -0,0 +1,21 @@
+
+#!/bin/sh
+
+rm -rf isim* 
+rm -rf catgen_tb
+rm -rf fuse*
+\
+#     --sourcelibdir ../../models \
+
+vlogcomp \
+    --sourcelibext .v \
+    --sourcelibdir ../../coregen \
+    --sourcelibdir ../../control_lib \
+    --sourcelibdir . \
+    --sourcelibdir $XILINX/verilog/src \
+    --sourcelibdir $XILINX/verilog/src/unisims \
+    --work work \
+    catgen_tb.v
+
+ 
+fuse -o catgen_tb catgen_tb
\ No newline at end of file
diff --git a/fpga/usrp3/lib/sim/io_cap_gen/catgen/catgen_tb.v b/fpga/usrp3/lib/sim/io_cap_gen/catgen/catgen_tb.v
new file mode 100644
index 000000000..e55f2de32
--- /dev/null
+++ b/fpga/usrp3/lib/sim/io_cap_gen/catgen/catgen_tb.v
@@ -0,0 +1,103 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+`timescale 1ns/1ps
+
+module catgen_tb();
+
+   wire GSR, GTS;
+   glbl glbl( );
+
+   reg 	clk    = 0;
+   reg 	reset  = 1;
+   wire ddrclk;
+   
+   always #100 clk = ~clk;
+
+   initial $dumpfile("catgen_tb.vcd");
+   initial $dumpvars(0,catgen_tb);
+
+   wire [11:0] pins;
+   wire        frame;
+   
+   reg 	       mimo;
+   reg [7:0]   count;
+   reg 	       tx_strobe;
+   
+   wire [11:0] i0 = {4'hA,count};
+   wire [11:0] q0 = {4'hB,count};
+   wire [11:0] i1 = {4'hC,count};
+   wire [11:0] q1 = {4'hD,count};
+
+   initial
+     begin
+	#1000 reset = 0;
+	BURST(4);
+	BURST(5);
+	MIMO_BURST(4);
+	MIMO_BURST(5);
+	#2000;
+	$finish;
+     end
+   
+   task BURST;
+      input [7:0] len;
+
+      begin
+	 tx_strobe <= 0;
+	 mimo <= 0;
+	 count <= 0;
+	 @(posedge clk);
+	 @(posedge clk);
+	 repeat(len)
+	   begin
+	      tx_strobe <= 1;
+	      @(posedge clk);
+	      count <= count + 1;
+	   end
+	 tx_strobe <= 0;
+	 @(posedge clk);
+	 @(posedge clk);
+	 @(posedge clk);
+      end
+   endtask // BURST
+   
+   task MIMO_BURST;
+      input [7:0] len;
+
+      begin
+	 tx_strobe <= 0;
+	 mimo <= 1;
+	 count <= 0;
+	 @(posedge clk);
+	 @(posedge clk);
+	 repeat(len)
+	   begin
+	      tx_strobe <= 1;
+	      @(posedge clk);
+	      tx_strobe <= 0;
+	      @(posedge clk);
+	      count <= count + 1;
+	   end
+	 tx_strobe <= 0;
+	 @(posedge clk);
+	 @(posedge clk);
+	 @(posedge clk);
+      end
+   endtask // BURST
+   
+   catgen_ddr_cmos catgen
+     (.data_clk(ddrclk),
+      .reset(reset),
+      .mimo(mimo),
+      .tx_frame(frame),
+      .tx_d(pins),
+      .tx_clk(clk),
+      .tx_strobe(tx_strobe),
+      .i0(i0),.q0(q0),
+      .i1(i1),.q1(q1));
+   
+endmodule // hb_chain_tb
diff --git a/fpga/usrp3/lib/sim/io_port2/pcie_dma_ctrl/pcie_dma_ctrl_tb.v b/fpga/usrp3/lib/sim/io_port2/pcie_dma_ctrl/pcie_dma_ctrl_tb.v
new file mode 100644
index 000000000..2b6c40bdd
--- /dev/null
+++ b/fpga/usrp3/lib/sim/io_port2/pcie_dma_ctrl/pcie_dma_ctrl_tb.v
@@ -0,0 +1,92 @@
+//
+// Copyright 2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+`timescale 500ps/1ps
+
+module pcie_dma_ctrl_tb();
+    reg clk    = 0;
+    reg reset  = 1;
+
+    always #10 clk = ~clk;
+
+    initial begin
+        #100 reset = 0;
+        #200000;
+        $finish;
+    end
+   
+    function [63:0] iop2_msg_write;
+        input [19:0]    address;
+        input [31:0]    data;
+        input           half_wd;
+    begin
+        //            {rd_response, wr_request, rd_request, half_word, 8'h00, address, data};
+        iop2_msg_write = {1'b0,        1'b1,       1'b0,       half_wd,   8'h00, address, data};
+    end
+    endfunction // iop2_msg_write
+
+    function [63:0] iop2_msg_read;
+        input [19:0]    address;
+        input           half_wd;
+    begin
+        //            {rd_response, wr_request, rd_request, half_word, 8'h00, address, data};
+        iop2_msg_read = {1'b0,        1'b0,       1'b1,       half_wd,   8'h00, address, 32'h0};
+    end
+    endfunction // iop2_msg_read
+
+    wire [3:0]      clear;
+    wire [63:0]     frame_size;
+    reg [3:0]       pkt_stb = 0;
+    reg [3:0]       samp_stb = 0;
+    reg [3:0]       error = 0;
+    reg [7:0]       rtr_sid = 4;
+    wire [3:0]      rtr_dst;
+
+    reg [63:0]  regi_tdata;
+    reg         regi_tvalid;
+    wire        regi_tready;
+    wire [63:0] rego_tdata;
+    wire        rego_tvalid;
+    reg         rego_tready;
+    reg [31:0]  rego_payload;
+    
+    always @(posedge clk)
+        if (rego_tdata[63] & rego_tvalid & rego_tready)
+            rego_payload <= rego_tdata[31:0];
+
+    initial begin
+        regi_tvalid <= 0;
+        rego_tready <= 0;
+        while (reset) @(posedge clk);
+    
+        rego_tready <= 1;
+        @(posedge clk);
+        
+        regi_tdata <= iop2_msg_write(20'h304, 32'hA, 0);
+        regi_tvalid <= 1;
+        @(posedge clk);
+        while (~regi_tready) @(posedge clk);
+        regi_tvalid <= 0;
+        @(posedge clk);
+    
+    end // initial begin
+    
+    pcie_dma_ctrl #(
+        .NUM_STREAMS(4), .FRAME_SIZE_W(16),
+        .REG_BASE_ADDR(20'h00200), .ENABLE_ROUTER(1),
+        .ROUTER_SID_W(8), .ROUTER_DST_W(4)
+    ) dut (
+        .clk(clk), .reset(reset),
+        .regi_tdata(regi_tdata), .regi_tvalid(regi_tvalid), .regi_tready(regi_tready),
+        .rego_tdata(rego_tdata), .rego_tvalid(rego_tvalid), .rego_tready(rego_tready),
+        .set_clear(clear), .set_frame_size(frame_size), .sample_stb(samp_stb), .packet_stb(pkt_stb), 
+        .stream_err(error), .rtr_sid(rtr_sid), .rtr_dst(rtr_dst)
+    );
+    
+
+endmodule
diff --git a/fpga/usrp3/lib/sim/io_port2/pcie_iop2_msg_arbiter/pcie_iop2_msg_arbiter_tb.v b/fpga/usrp3/lib/sim/io_port2/pcie_iop2_msg_arbiter/pcie_iop2_msg_arbiter_tb.v
new file mode 100644
index 000000000..fe566b1aa
--- /dev/null
+++ b/fpga/usrp3/lib/sim/io_port2/pcie_iop2_msg_arbiter/pcie_iop2_msg_arbiter_tb.v
@@ -0,0 +1,110 @@
+//
+// Copyright 2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+`timescale 500ps/1ps
+
+module pcie_iop2_msg_arbiter_tb();
+    reg clk    = 0;
+    reg reset  = 1;
+
+    always #10 clk = ~clk;
+
+    initial begin
+        #100 reset = 0;
+        #200000;
+        $finish;
+    end
+   
+    function [63:0] iop2_msg_write;
+        input [19:0]    address;
+        input [31:0]    data;
+        input           half_wd;
+    begin
+        //            {rd_response, wr_request, rd_request, half_word, 8'h00, address, data};
+        iop2_msg_write = {1'b0,        1'b1,       1'b0,       half_wd,   8'h00, address, data};
+    end
+    endfunction // iop2_msg_write
+
+    function [63:0] iop2_msg_read;
+        input [19:0]    address;
+        input           half_wd;
+    begin
+        //            {rd_response, wr_request, rd_request, half_word, 8'h00, address, data};
+        iop2_msg_read = {1'b0,        1'b0,       1'b1,       half_wd,   8'h00, address, 32'h0};
+    end
+    endfunction // iop2_msg_read
+
+    reg [63:0]  msgi_tdata;
+    wire [63:0] msgo_tdata;
+    wire        msgo_tvalid, msgi_tready;
+    reg         msgo_tready, msgi_tvalid;
+
+    wire [63:0] basic_regi_tdata, zpu_regi_tdata;
+    wire        basic_regi_tvalid, zpu_regi_tvalid;
+    reg         basic_regi_tready, zpu_regi_tready;
+    reg [63:0]  basic_rego_tdata, zpu_rego_tdata;
+    reg         basic_rego_tvalid, zpu_rego_tvalid;
+    wire        basic_rego_tready, zpu_rego_tready;
+
+    initial begin
+        //@TODO: Make this a self-checking TB
+        while (reset) @(posedge clk);
+    
+        msgo_tready <= 1;
+        basic_regi_tready <= 1;
+        @(posedge clk);
+        
+        
+        msgi_tdata <= iop2_msg_write(20'h0, 32'hDEAD, 0);
+        msgi_tvalid <= 1;
+        while (~msgi_tready) @(posedge clk);
+        msgi_tvalid <= 0;
+        @(posedge clk);
+        
+        
+        msgi_tdata <= iop2_msg_read(20'h00000, 0);
+        msgi_tvalid <= 1;
+        while (~msgi_tready) @(posedge clk);
+        msgi_tvalid <= 0;
+        @(posedge clk);
+
+        zpu_rego_tdata <= {1, 31'h0, 32'h12345678};
+        zpu_rego_tvalid <= 1;
+        while (~zpu_rego_tready) @(posedge clk);
+        zpu_rego_tvalid <= 0;
+        
+
+
+    end // initial begin
+    
+    pcie_iop2_msg_arbiter #(
+        .E0_ADDR(20'h00000), .E0_MASK(20'hFFF00),     //0x00000 - 0x000FF: Basic PCIe registers
+        .E1_ADDR(20'h00100), .E1_MASK(20'hFFF00),     //0x00100 - 0x001FF: PCIe router registers
+        .E2_ADDR(20'h00200), .E2_MASK(20'hFFE00),     //0x00200 - 0x003FF: DMA stream registers
+        .E3_ADDR(20'h40000), .E3_MASK(20'hC0000)      //0x40000 - 0x7FFFF: Client address space 
+    ) iop2_msg_arbiter (
+        .clk(clk), .reset(reset),
+        //Master
+        .regi_tdata(msgi_tdata), .regi_tvalid(msgi_tvalid), .regi_tready(msgi_tready),
+        .rego_tdata(msgo_tdata), .rego_tvalid(msgo_tvalid), .rego_tready(msgo_tready),
+        //Endpoint 0
+        .e0_regi_tdata(basic_regi_tdata), .e0_regi_tvalid(basic_regi_tvalid), .e0_regi_tready(basic_regi_tready),
+        .e0_rego_tdata(basic_rego_tdata), .e0_rego_tvalid(basic_rego_tvalid), .e0_rego_tready(basic_rego_tready),
+        //Endpoint 1
+        .e1_regi_tdata(), .e1_regi_tvalid(), .e1_regi_tready(1'b1),
+        .e1_rego_tdata(64'h0), .e1_rego_tvalid(1'b0), .e1_rego_tready(),
+        //Endpoint 2
+        .e2_regi_tdata(), .e2_regi_tvalid(), .e2_regi_tready(1'b1),
+        .e2_rego_tdata(64'h0), .e2_rego_tvalid(1'b0), .e2_rego_tready(),
+        //Endpoint 3
+        .e3_regi_tdata(zpu_regi_tdata), .e3_regi_tvalid(zpu_regi_tvalid), .e3_regi_tready(zpu_regi_tready),
+        .e3_rego_tdata(zpu_rego_tdata), .e3_rego_tvalid(zpu_rego_tvalid), .e3_rego_tready(zpu_rego_tready)
+    );
+    
+
+endmodule
diff --git a/fpga/usrp3/lib/sim/io_port2/pcie_wb_reg_core/pcie_wb_reg_core_tb.v b/fpga/usrp3/lib/sim/io_port2/pcie_wb_reg_core/pcie_wb_reg_core_tb.v
new file mode 100644
index 000000000..62bec9eb4
--- /dev/null
+++ b/fpga/usrp3/lib/sim/io_port2/pcie_wb_reg_core/pcie_wb_reg_core_tb.v
@@ -0,0 +1,243 @@
+//
+// Copyright 2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+`timescale 500ps/1ps
+`define CHECK_VALUE(val, expected, report) \
+        if (val == expected) \
+            $display("%s...Passed",report); \
+        else \
+            $display("%s...FAILED!!! (Val=0x%x, Exp=0x%x)",report,val,expected); \
+
+module pcie_wb_reg_core_tb();
+    reg         clk = 0, reset = 1; 
+    reg         wb_stb_i = 0;
+    reg         wb_we_i = 0;
+    reg  [15:0] wb_adr_i = 0;
+    reg  [31:0] wb_dat_i = 0;
+    wire        wb_ack_o;
+    wire [31:0] wb_dat_o;
+
+    wire [63:0] msgo_data;
+    wire        msgo_valid;
+    reg         msgo_ready = 0;
+    reg  [63:0] msgi_data = 0;
+    reg         msgi_valid = 0;
+    wire        msgi_ready;
+    
+    reg  [31:0] msgo_payload = 32'h0;
+    reg  [31:0] msgo_ctrl = 32'h0;
+    
+    reg  [31:0] it;
+
+    always #10 clk = ~clk;
+
+    initial begin
+        #100 reset = 0;
+        #200000;
+        $finish;
+    end
+   
+    localparam READ     = 3'b001;
+    localparam WRITE    = 3'b010;
+    localparam RESPONSE = 3'b100;
+   
+    task pcie_send;
+        input [2:0]     op;
+        input [19:0]    address;
+        input [31:0]    data;
+    begin
+        //{rd_resp, wr_request, rd_request, half_word, 8'h00, address, data};
+        msgi_data  <= {op, 1'b0, 8'h00, address, data};
+        msgi_valid <= 1'b1;
+
+        @(posedge clk);
+        while (~msgi_ready) @(posedge clk);
+        
+        msgi_valid <= 1'b0;
+        @(posedge clk);
+    end
+    endtask // pcie_send
+
+    task pcie_recv;
+        input [2:0]     op;
+        input [19:0]    address;
+        input [31:0]    data;
+    begin
+        while (~msgo_valid) @(posedge clk);
+
+        msgo_ready <= 1'b1;
+        @(posedge clk);
+        
+        if (msgo_data[63] == op[2] || (msgo_data[62:61] == op[1:0] && msgo_data[51:32] == address))
+            msgo_payload <= msgo_data[31:0];
+            msgo_ctrl <= msgo_data[63:32];
+
+        msgo_ready <= 1'b0;
+        @(posedge clk);
+    end
+    endtask // pcie_recv
+
+    task wb_send;
+        input [2:0]     op;
+        input [15:0]    address;
+        input [31:0]    data;
+    begin
+        wb_adr_i <= address;
+        wb_dat_i <= data;
+        wb_we_i <= op[1];
+        wb_stb_i <= 1'b1;
+        
+        @(posedge clk);
+        while (~wb_ack_o) @(posedge clk);
+        
+        wb_stb_i <= 1'b0;
+    end
+    endtask // pcie_send
+
+
+    initial begin
+        msgo_ready <= 1'b0;
+        msgi_valid <= 1'b0;
+        while (reset) @(posedge clk);    
+        @(posedge clk);
+        
+        $display("\n[TEST] ZPU Read from PCIe");
+        pcie_send(WRITE, 20'h6a000, 32'h0);
+        `CHECK_VALUE(msgo_payload, 32'h0, "Verify PCIe readback before initiating read request");
+        pcie_send(READ, 20'h6a000, 32'h0);
+        pcie_recv(RESPONSE, 20'h0, 20'h0);
+        `CHECK_VALUE(msgo_payload, 32'h1, "Verify PCIe status after initiating read");
+        pcie_send(READ, 20'h6a000, 32'h0);
+        pcie_recv(RESPONSE, 20'h0, 20'h0);
+        `CHECK_VALUE(msgo_payload, 32'h1, "Verify PCIe status after initiating second read");
+        wb_send(READ, 16'hC, 32'h0);
+        `CHECK_VALUE(wb_dat_o, 32'h6, "Verify WB status after PCIe read request");
+        wb_send(READ, 16'h4, 32'h0);
+        `CHECK_VALUE(wb_dat_o, 32'h2000a000, "Verify WB control value after PCIe read request");
+        wb_send(READ, 16'hC, 32'h0);
+        `CHECK_VALUE(wb_dat_o, 32'h4, "Verify WB status value after consuming PCIe read request");
+        pcie_send(READ, 20'h6a000, 32'h0);
+        pcie_recv(RESPONSE, 20'h0, 20'h0);
+        `CHECK_VALUE(msgo_payload, 32'h1, "Verify PCIe status after WB consumes request only");
+        wb_send(WRITE, 16'h0, 32'hDEADBEEF);
+        wb_send(WRITE, 16'h4, 32'h80000000);
+        wb_send(READ, 16'hC, 32'h0);
+        `CHECK_VALUE(wb_dat_o, 32'h0, "Verify WB status value after responding to PCIe read request");
+        pcie_send(READ, 20'h6a000, 32'h0);
+        pcie_recv(RESPONSE, 20'h0, 20'h0);
+        `CHECK_VALUE(msgo_payload, 32'h0, "Verify PCIe status after WB responds to read request");
+        pcie_send(READ, 20'h7a000, 32'h0);
+        pcie_recv(RESPONSE, 20'h0, 20'h0);
+        `CHECK_VALUE(msgo_payload, 32'hdeadbeef, "Verify PCIe read data");
+    
+        $display("\n[TEST] ZPU Write from PCIe");
+        pcie_send(WRITE, 20'h7b000, 32'h12345678);
+        pcie_send(READ, 20'h7a000, 32'h0);
+        pcie_recv(RESPONSE, 20'h0, 20'h0);
+        `CHECK_VALUE(msgo_payload, 32'hdeadbeef, "Verify that PCIe read data is still intact after write");
+        wb_send(READ, 16'hC, 32'h0);
+        `CHECK_VALUE(wb_dat_o, 32'h2, "Verify WB status value after PCIe write request");
+        wb_send(READ, 16'h0, 32'h0);
+        `CHECK_VALUE(wb_dat_o, 32'h12345678, "Verify WB data value after PCIe read request");
+        wb_send(READ, 16'h4, 32'h0);
+        `CHECK_VALUE(wb_dat_o, 32'h4000b000, "Verify WB control value after PCIe read request");
+        wb_send(READ, 16'hC, 32'h0);
+        `CHECK_VALUE(wb_dat_o, 32'h0, "Verify WB status value after consuming PCIe write request");
+        pcie_send(READ, 20'h6a000, 32'h0);
+        pcie_recv(RESPONSE, 20'h0, 20'h0);
+        `CHECK_VALUE(msgo_payload, 32'h0, "Verify PCIe status after WB consumes request");
+
+        $display("\n[TEST] Chinch Write from ZPU");
+        wb_send(READ, 16'hC, 32'h0);
+        `CHECK_VALUE(wb_dat_o, 32'h0, "Verify WB status value before initiating write request");
+        wb_send(WRITE, 16'h0, 32'h00beef00);
+        wb_send(READ, 16'hC, 32'h0);
+        `CHECK_VALUE(wb_dat_o, 32'h0, "Verify WB status value after writing just the data reg");
+        wb_send(WRITE, 16'h4, 32'h40000200);
+        wb_send(READ, 16'hC, 32'h0);
+        `CHECK_VALUE(wb_dat_o, 32'h0, "Verify WB status value after initiating write");
+        pcie_recv(WRITE, 20'h200, 20'h0);
+        `CHECK_VALUE(msgo_payload, 32'h00beef00, "Verify received PCIe data");
+        `CHECK_VALUE(msgo_ctrl, 32'h40000200, "Verify received PCIe control");
+        wb_send(WRITE, 16'h0, 32'h00feeb00);
+        wb_send(WRITE, 16'h4, 32'h400002fc);
+        pcie_recv(WRITE, 20'h200, 20'h0);
+        `CHECK_VALUE(msgo_payload, 32'h00feeb00, "Verify second received PCIe data");
+        `CHECK_VALUE(msgo_ctrl, 32'h400002fc, "Verify second received PCIe control");
+
+        $display("\n[TEST] Chinch Read from ZPU");
+        wb_send(READ, 16'hC, 32'h0);
+        `CHECK_VALUE(wb_dat_o, 32'h0, "Verify WB status value before initiating read request");
+        wb_send(WRITE, 16'h0, 32'hffffffff);
+        wb_send(READ, 16'hC, 32'h0);
+        `CHECK_VALUE(wb_dat_o, 32'h0, "Verify WB status value after writing just the data reg");
+        wb_send(WRITE, 16'h4, 32'h20000400);
+        wb_send(READ, 16'hC, 32'h0);
+        `CHECK_VALUE(wb_dat_o, 32'h1, "Verify WB status value after initiating read request");
+        pcie_recv(READ, 20'h400, 20'h0);
+        `CHECK_VALUE(msgo_payload, 32'hffffffff, "Verify received PCIe data");
+        `CHECK_VALUE(msgo_ctrl, 32'h20000400, "Verify received PCIe control");
+        wb_send(READ, 16'hC, 32'h0);
+        wb_send(READ, 16'hC, 32'h0);
+        `CHECK_VALUE(wb_dat_o, 32'h1, "Verify WB status value before PCIe responds");
+        pcie_send(RESPONSE, 20'h000, 32'hace06666);
+        wb_send(READ, 16'hC, 32'h0);
+        `CHECK_VALUE(wb_dat_o, 32'h0, "Verify WB status value after PCIe responds");
+        wb_send(READ, 16'h8, 32'h0);
+        `CHECK_VALUE(wb_dat_o, 32'hace06666, "Verify WB read value after PCIe responds");
+
+        $display("\n[TEST] WB Outbound flood");
+        wb_send(READ, 16'hC, 32'h0);
+        `CHECK_VALUE(wb_dat_o, 32'h0, "Verify WB status before request flood");
+        for (it = 0; it < 64; it = it + 1) begin
+            wb_send(WRITE, 16'h4, 32'h20000400);
+        end
+        wb_send(READ, 16'hC, 32'h0);
+        `CHECK_VALUE(wb_dat_o, 32'h11, "Verify WB status after request flood");
+        for (it = 0; it < 64; it = it + 1) begin
+            pcie_recv(READ, 20'h400, 20'h0);
+        end
+        wb_send(READ, 16'hC, 32'h0);
+        `CHECK_VALUE(wb_dat_o, 32'h1, "Verify WB status after consuming requests");
+
+        $display("\n[TEST] PCIe Transaction Status");
+        pcie_send(READ, 20'h6a000, 32'h0);
+        pcie_recv(RESPONSE, 20'h0, 20'h0);
+        `CHECK_VALUE(msgo_payload, 32'h0, "Verify PCIe status before multiple reads");
+        pcie_send(WRITE, 20'h6a000, 32'h0);
+        pcie_send(WRITE, 20'h6a000, 32'h0);
+        pcie_send(WRITE, 20'h6a000, 32'h0);
+        pcie_send(READ, 20'h6a000, 32'h0);
+        pcie_recv(RESPONSE, 20'h0, 20'h0);
+        pcie_send(READ, 20'h6a000, 32'h0);
+        pcie_recv(RESPONSE, 20'h0, 20'h0);
+        pcie_send(READ, 20'h6a000, 32'h0);
+        pcie_recv(RESPONSE, 20'h0, 20'h0);
+        `CHECK_VALUE(msgo_payload, 32'h1, "Verify PCIe status before multiple read requests and status queries");
+        wb_send(READ, 16'h4, 32'h0);
+        wb_send(WRITE, 16'h0, 32'hDEADBEEF);
+        wb_send(WRITE, 16'h4, 32'h80000000);
+        pcie_send(READ, 20'h6a000, 32'h0);
+        pcie_recv(RESPONSE, 20'h0, 20'h0);
+        `CHECK_VALUE(msgo_payload, 32'h0, "Verify PCIe status after response");
+        
+        $display("\n[DONE]");
+
+
+    end // initial begin
+    
+    pcie_wb_reg_core #(.WB_ADDRW(16), .WB_DATAW(32)) dut (
+        .clk(clk), .rst(reset),
+        .wb_stb_i(wb_stb_i), .wb_we_i(wb_we_i), .wb_adr_i(wb_adr_i),
+        .wb_dat_i(wb_dat_i), .wb_ack_o(wb_ack_o), .wb_dat_o(wb_dat_o),
+        .msgi_tdata(msgi_data), .msgi_tvalid(msgi_valid), .msgi_tready(msgi_ready),
+        .msgo_tdata(msgo_data), .msgo_tvalid(msgo_valid), .msgo_tready(msgo_ready),
+        .debug());
+    
+
+endmodule
diff --git a/fpga/usrp3/lib/sim/packet_proc/chdr_chunker/chdr_chunker_tb.v b/fpga/usrp3/lib/sim/packet_proc/chdr_chunker/chdr_chunker_tb.v
new file mode 100644
index 000000000..9e80f9c15
--- /dev/null
+++ b/fpga/usrp3/lib/sim/packet_proc/chdr_chunker/chdr_chunker_tb.v
@@ -0,0 +1,190 @@
+//
+// Copyright 2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+`timescale 1ns/10ps
+
+module chdr_chunker_tb();
+
+   // TB stimulus
+   reg clk    = 0;
+   reg reset  = 1;
+   reg clear  = 0;
+   reg [15:0] quantum;
+
+   // Check vars
+   reg [31:0] o_xfer_count = 0, i_xfer_count = 0;
+   reg [63:0] o_last_tdata = 0;
+
+   
+   always #10 clk = ~clk;
+   
+   initial $dumpfile("chdr_chunker_tb.vcd");
+   initial $dumpvars(0,chdr_chunker_tb);
+
+   function check_result;
+      input [31:0]   o_xfer_count_arg;
+      input [31:0]   i_xfer_count_arg;
+      input [63:0]   o_last_tdata_arg;
+      input          error_arg;
+      begin
+         //Check vars
+         check_result = 1;
+         check_result = check_result & ((o_xfer_count_arg == o_xfer_count) !== 0);
+         check_result = check_result & ((i_xfer_count_arg == i_xfer_count) !== 0);
+         check_result = check_result & ((o_last_tdata_arg == o_last_tdata) !== 0);
+         check_result = check_result & ((error_arg == error) != 0);
+         
+         if (check_result) begin
+            $display ("... Passed");
+         end else begin
+            $display ("... FAILED!!!");
+            $display ("o_xfer_count = %d (Expected %d)",o_xfer_count,o_xfer_count_arg);
+            $display ("i_xfer_count = %d (Expected %d)",i_xfer_count,i_xfer_count_arg);
+            $display ("o_last_tdata = %h (Expected %h)",o_last_tdata,o_last_tdata_arg);
+            $display ("error = %d  (Expected %d)",error,error_arg);
+         end
+
+         //Reset vars
+         o_xfer_count = 0;
+         i_xfer_count = 0;
+         o_last_tdata = 64'h0;
+      end
+   endfunction
+
+   task send_packet;
+      input [63:0] data_start;
+      input [31:0] len;
+      
+      begin
+         if(len < 9) begin
+            {i_tlast, i_tdata} <= { 1'b1, data_start[63:32], len[15:0], data_start[15:0] };
+            i_tvalid <= 1;
+            @(posedge clk);
+            i_tvalid <= 0;
+         end else begin
+            {i_tlast, i_tdata} <= { 1'b0, data_start[63:32], len[15:0], data_start[15:0] };
+            i_tvalid <= 1;
+            @(posedge clk);
+            repeat(((len-1)/8)-1) begin
+               i_tdata <= i_tdata + 64'h0000_0002_0000_0002;
+               @(posedge clk);
+            end
+            i_tdata <= i_tdata + 64'h0000_0002_0000_0002;
+            i_tlast <= 1;
+            @(posedge clk);
+            i_tvalid <= 0;
+        end // else: !if(len < 9)
+      end
+   endtask // send_packet
+
+   task reset_quantum_atomic;
+      input [15:0] quant;
+      begin
+         quantum <= quant;
+         clear <= 1;
+         @(posedge clk);
+         clear <= 0;
+         @(posedge clk);
+      end
+   endtask // reset_quantum_atomic
+
+
+   initial begin
+      #100 reset = 0;
+      #200000;
+      $finish;
+   end
+   
+   reg [63:0]  i_tdata;
+   reg         i_tlast;
+   reg         i_tvalid;
+   wire        i_tready;
+
+   wire [63:0] o_tdata;
+   wire        o_tlast, o_tvalid, o_tready;
+   wire        error;
+   
+   initial begin
+      quantum <= 256;
+      i_tvalid <= 0;
+      while(reset) @(posedge clk);
+
+      $write ("Running test case: First packet after reset");
+      send_packet(64'h00000001_00000000, 128);
+      while(o_tvalid) @(posedge clk);
+      check_result(256,16,64'hFFFFFFFF_FFFFFFFF,0);
+
+      reset_quantum_atomic(8);
+
+      $write ("Running test case: sizeof(packet) < quantum");
+      send_packet(64'h00000001_00000000, 40);
+      while(o_tvalid) @(posedge clk);
+      check_result(8,5,64'hFFFFFFFF_FFFFFFFF,0);
+
+      reset_quantum_atomic(5);
+
+      $write ("Running test case: sizeof(packet) == quantum");
+      send_packet(64'h00000001_00000000, 40);
+      while(o_tvalid) @(posedge clk);
+      check_result(5,5,64'h00000030_00000008,0);
+      
+      $write ("Running test case: sizeof(packet) == quantum - 64bits");
+      send_packet(64'h00000001_00000000, 32);
+      while(o_tvalid) @(posedge clk);
+      check_result(5,4,64'hFFFFFFFF_FFFFFFFF,0);
+
+      $write ("Running test case: sizeof(packet) == quantum + 64bits");
+      send_packet(64'h00000001_00000000, 48);
+      while(o_tvalid) @(posedge clk);
+      check_result(32'hxxxxxxxx,32'hxxxxxxxx,64'hxxxxxxxx_xxxxxxxx,1);
+
+      $write ("Running test case: Error reset");
+      reset_quantum_atomic(8);
+      check_result(32'hxxxxxxxx,32'hxxxxxxxx,64'hxxxxxxxx_xxxxxxxx,0);
+      
+      $write ("Running test case: sizeof(packet) > quantum");
+      send_packet(64'h00000001_00000000, 80);
+      while(o_tvalid) @(posedge clk);
+      check_result(32'hxxxxxxxx,32'hxxxxxxxx,64'hxxxxxxxx_xxxxxxxx,1);
+
+      reset_quantum_atomic(8);
+
+      $write ("Running test case: sizeof(packet) == 2");
+      send_packet(64'h00000001_00000000, 8);
+      while(o_tvalid) @(posedge clk);
+      check_result(8,1,64'hFFFFFFFF_FFFFFFFF,0);
+
+      $write ("Running test case: Multiple packets back-to-back");
+      send_packet(64'h00000001_00000000, 40);
+      while(o_tvalid) @(posedge clk);
+      send_packet(64'h00000001_00000000, 16);
+      while(o_tvalid) @(posedge clk);
+      send_packet(64'h00000001_00000000, 64);
+      while(o_tvalid) @(posedge clk);
+      check_result(24,15,64'h0000004e0000000e,0);
+
+   end // initial begin
+
+
+   chdr_chunker dut (
+      .clk(clk), .reset(reset), .clear(clear), .frame_size(quantum),
+      .i_tdata(i_tdata), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready),
+      .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready),
+      .error(error));
+      
+   assign o_tready = 1;
+  
+   always @(posedge clk) begin
+      if (o_tvalid & o_tready) begin
+         o_xfer_count <= o_xfer_count + 1;
+         o_last_tdata <= o_tdata;
+      end
+      if (i_tvalid & i_tready) i_xfer_count <= i_xfer_count + 1;
+   end
+
+endmodule // chdr_chunker_tb
diff --git a/fpga/usrp3/lib/sim/packet_proc/chdr_dechunker/Makefile b/fpga/usrp3/lib/sim/packet_proc/chdr_dechunker/Makefile
new file mode 100644
index 000000000..f73cbdae9
--- /dev/null
+++ b/fpga/usrp3/lib/sim/packet_proc/chdr_dechunker/Makefile
@@ -0,0 +1,33 @@
+#
+# Copyright 2016 Ettus Research
+#
+
+#-------------------------------------------------
+# Top-of-Makefile
+#-------------------------------------------------
+# Define BASE_DIR to point to the "top" dir
+BASE_DIR = $(abspath ../../../../top)
+# Include viv_sim_preample after defining BASE_DIR
+include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
+
+#-------------------------------------------------
+# Testbench Specific
+#-------------------------------------------------
+# Define only one toplevel module
+SIM_TOP = chdr_dechunker_tb
+
+# Add test bench, user design under test, and
+# additional user created files
+SIM_SRCS = $(abspath \
+chdr_dechunker_tb.sv \
+)
+
+MODELSIM_USER_DO = $(abspath wave.do)
+
+#-------------------------------------------------
+# Bottom-of-Makefile
+#-------------------------------------------------
+# Include all simulator specific makefiles here
+# Each should define a unique target to simulate
+# e.g. xsim, vsim, etc and a common "clean" target
+include $(BASE_DIR)/../tools/make/viv_simulator.mak
diff --git a/fpga/usrp3/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv b/fpga/usrp3/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv
new file mode 100644
index 000000000..38664c20f
--- /dev/null
+++ b/fpga/usrp3/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv
@@ -0,0 +1,200 @@
+//
+// Copyright 2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+// Copyright 2019 Ettus Research, a National Instruments Brand
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+`timescale 1ns/10ps
+
+`define NS_PER_TICK 1
+`define NUM_TEST_CASES 8
+
+`include "sim_exec_report.vh"
+
+
+module chdr_dechunker_tb();
+   `TEST_BENCH_INIT("chdr_dechunker_tb", `NUM_TEST_CASES, `NS_PER_TICK)
+
+   // TB stimulus
+   reg clk    = 0;
+   reg reset  = 1;
+   reg clear  = 0;
+   reg [15:0] quantum;
+   wire error;
+
+   // Check vars
+   reg [31:0] o_xfer_count = 0, i_xfer_count = 0;
+   reg [63:0] o_last_tdata = 0;
+
+   
+   always #10 clk = ~clk;
+   
+   initial $dumpfile("chdr_dechunker_tb.vcd");
+   initial $dumpvars(0,chdr_dechunker_tb);
+
+   function check_result;
+      input [31:0]   o_xfer_count_arg;
+      input [31:0]   i_xfer_count_arg;
+      input [63:0]   o_last_tdata_arg;
+      input          error_arg;
+      begin
+         //Check vars
+         check_result = 1;
+         check_result = check_result & ((o_xfer_count_arg == o_xfer_count) !== 0);
+         check_result = check_result & ((i_xfer_count_arg == i_xfer_count) !== 0);
+         check_result = check_result & ((o_last_tdata_arg == o_last_tdata) !== 0);
+         check_result = check_result & ((error_arg == error) != 0);
+         
+         if (!check_result) begin
+            $display ("o_xfer_count = %d (Expected %d)",o_xfer_count,o_xfer_count_arg);
+            $display ("i_xfer_count = %d (Expected %d)",i_xfer_count,i_xfer_count_arg);
+            $display ("o_last_tdata = %h (Expected %h)",o_last_tdata,o_last_tdata_arg);
+            $display ("error = %d  (Expected %d)",error,error_arg);
+            `ASSERT_ERROR(0, "Result did not match expected value");
+         end
+
+         //Reset vars
+         o_xfer_count = 0;
+         i_xfer_count = 0;
+         o_last_tdata = 64'h0;
+      end
+   endfunction
+
+   task send_packet;
+      input [63:0] data_start;
+      input [31:0] len;
+      input [31:0] quant;
+      
+      begin
+         if(quant < 2) begin
+            {i_tlast, i_tdata} <= { 1'b1, data_start[63:32], len[15:0], data_start[15:0] };
+            i_tvalid <= 1;
+            @(posedge clk);
+            i_tvalid <= 0;
+         end else begin
+            {i_tlast, i_tdata} <= { 1'b0, data_start[63:32], len[15:0], data_start[15:0] };
+            i_tvalid <= 1;
+            @(posedge clk);
+            repeat(quant - 2) begin
+               i_tdata <= i_tdata + 64'h0000_0002_0000_0002;
+               @(posedge clk);
+            end
+            i_tdata <= i_tdata + 64'h0000_0002_0000_0002;
+            i_tlast <= 1;
+            @(posedge clk);
+            i_tvalid <= 1'b0;
+         end // else: !if(quant < 2)
+      end
+   endtask // send_packet
+
+   task reset_quantum_atomic;
+      input [15:0] quant;
+      begin
+         quantum <= quant;
+         clear <= 1;
+         @(posedge clk);
+         clear <= 0;
+         @(posedge clk);
+      end
+   endtask // reset_quantum_atomic
+
+
+   initial begin
+      #100 reset = 0;
+   end
+   
+   reg [63:0]  i_tdata;
+   reg         i_tlast;
+   reg         i_tvalid;
+   wire        i_tready;
+
+   wire [63:0] o_tdata;
+   wire        o_tlast, o_tvalid, o_tready;
+   
+   reg result;
+   initial begin
+      quantum <= 8;
+      i_tvalid <= 0;
+      while(reset) @(posedge clk);
+
+      `TEST_CASE_START("Running test case: First packet after reset");
+      send_packet(64'h00000001_00000000, 32, 8);
+      @(posedge clk);
+      result = check_result(4,8,64'hxxxxxxxx_xxxxxx06, 0);
+      `TEST_CASE_DONE(result);
+
+      reset_quantum_atomic(10);
+
+      `TEST_CASE_START("Running test case: sizeof(packet) < quantum");
+      send_packet(64'h00000001_00000000, 64, 10);
+      @(posedge clk);
+      result = check_result(8,10,64'hxxxxxxxx_xxxxxx0e, 0);
+      `TEST_CASE_DONE(result);
+
+      `TEST_CASE_START("Running test case: sizeof(packet) == quantum");
+      send_packet(64'h00000001_00000000, 80, 10);
+      @(posedge clk);
+      result = check_result(10,10,64'hxxxxxxxx_xxxxxx12, 0);
+      `TEST_CASE_DONE(result);
+      
+      `TEST_CASE_START("Running test case: sizeof(packet) == quantum - 64bits");
+      send_packet(64'h00000001_00000000, 72, 10);
+      @(posedge clk);
+      result = check_result(9,10,64'hxxxxxxxx_xxxxxx10, 0);
+      `TEST_CASE_DONE(result);
+
+      `TEST_CASE_START("Running test case: sizeof(packet) == quantum + 64bits");
+      send_packet(64'h00000001_00000000, 88, 10);
+      @(posedge clk);
+      result = check_result(32'hxxxxxxxx,10,64'hxxxxxxxx_xxxxxxxx, 1);
+      `TEST_CASE_DONE(result);
+
+      reset_quantum_atomic(10);
+
+      `TEST_CASE_START("Running test case: sizeof(packet) > quantum");
+      send_packet(64'h00000001_00000000, 88, 10);
+      @(posedge clk);
+      result = check_result(32'hxxxxxxxx,10,64'hxxxxxxxx_xxxxxxxx, 1);
+      `TEST_CASE_DONE(result);
+
+      reset_quantum_atomic(8);
+
+      `TEST_CASE_START("Running test case: sizeof(packet) == 2");
+      send_packet(64'h00000001_00000000, 8, 8);
+      @(posedge clk);
+      result = check_result(1,8,64'hxxxxxxxx_xxxxxx00, 0);
+      `TEST_CASE_DONE(result);
+
+      `TEST_CASE_START("Running test case: Multiple packets");
+      send_packet(64'h00000001_00000000, 8, 8);
+      send_packet(64'h00000001_00000000, 16, 8);
+      send_packet(64'h00000001_00000000, 24, 8);
+      send_packet(64'h00000001_00000000, 32, 8);
+      @(posedge clk);
+      result = check_result(10,32,64'hxxxxxxxx_xxxxxx06, 0);
+      `TEST_CASE_DONE(result);
+
+      `TEST_BENCH_DONE;
+   end // initial begin
+
+
+   chdr_dechunker dut (
+      .clk(clk), .reset(reset), .clear(clear), .frame_size(quantum),
+      .i_tdata(i_tdata), .i_tvalid(i_tvalid), .i_tready(i_tready),
+      .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready),
+      .error(error));
+      
+   assign o_tready = 1;
+  
+   always @(posedge clk) begin
+      if (o_tvalid & o_tready) begin
+         o_xfer_count <= o_xfer_count + 1;
+         o_last_tdata <= o_tdata;
+      end
+      if (i_tvalid & i_tready) i_xfer_count <= i_xfer_count + 1;
+   end
+
+endmodule // chdr_dechunker_tb
diff --git a/fpga/usrp3/lib/sim/packet_proc/ip_hdr_checksum/ip_hdr_checksum_tb.v b/fpga/usrp3/lib/sim/packet_proc/ip_hdr_checksum/ip_hdr_checksum_tb.v
new file mode 100644
index 000000000..82deca656
--- /dev/null
+++ b/fpga/usrp3/lib/sim/packet_proc/ip_hdr_checksum/ip_hdr_checksum_tb.v
@@ -0,0 +1,43 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+module ip_hdr_checksum_tb();
+   
+   initial $dumpfile("ip_hdr_checksum_tb.vcd");
+   initial $dumpvars(0,ip_hdr_checksum_tb);
+
+   reg clk;
+   
+   wire [159:0] in = {
+		      16'h4500,
+		      16'h0030,
+		      16'h4422,
+		      16'h4000,
+		      16'h8006,
+		      16'h0000,
+		      16'h8c7c,
+		      16'h19ac,
+		      16'hae24,
+		      16'h1e2b
+		      };
+   
+   wire [15:0] 	out;
+   ip_hdr_checksum ip_hdr_checksum
+     (.clk(clk), 
+      .in(in),
+      .out(out));
+
+   initial
+     begin
+	clk <= 0;
+	#100 clk <= 1;
+	#100 clk <= 0;
+	#100 clk <= 1;
+	#100 $display("Computed 0x%x, should be 0x442e", out);
+	#100 $finish;
+     end
+   
+endmodule // ip_hdr_checksum_tb
diff --git a/fpga/usrp3/lib/sim/rfnoc/axi_pipe/axi_pipe_tb.v b/fpga/usrp3/lib/sim/rfnoc/axi_pipe/axi_pipe_tb.v
new file mode 100644
index 000000000..b84657b07
--- /dev/null
+++ b/fpga/usrp3/lib/sim/rfnoc/axi_pipe/axi_pipe_tb.v
@@ -0,0 +1,74 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module axi_pipe_tb;
+
+   initial $dumpfile("axi_pipe_tb.vcd");
+   initial $dumpvars(0,axi_pipe_tb);
+
+   reg clk = 0;
+   always #100 clk <= ~clk;
+   reg reset = 1;
+   initial #1000 @(posedge clk) reset <= 1'b0;
+   initial #30000 $finish;
+   
+   localparam LEN=10;
+   wire [LEN-1:0] enables, valids;
+
+   wire 	  o_tlast, i_tready, o_tvalid;
+   reg 		  i_tvalid = 0;
+   reg 		  o_tready = 0;
+   reg 		  i_tlast = 0;
+   
+   axi_pipe #(.STAGES(LEN)) axi_pipe
+     (.clk(clk), .reset(reset), .clear(0),
+      .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready),
+      .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready),
+      .enables(enables), .valids(valids));
+
+   initial
+     begin
+	@(negedge reset);
+	repeat (3)
+	  @(posedge clk);
+	i_tvalid <= 1;
+	@(posedge clk);
+	i_tvalid <= 0;
+	repeat (15) @(posedge clk);
+	@(posedge clk);
+	o_tready <= 1;
+	repeat (15) @(posedge clk);
+	o_tready <= 0;
+	i_tvalid <= 1;
+	repeat (15) @(posedge clk);
+	o_tready <= 1;
+	i_tvalid <= 0;
+	repeat (15) @(posedge clk);
+	o_tready <= 0;
+	i_tvalid <= 1;
+	@(posedge clk);
+	i_tvalid <= 0;
+	@(posedge clk);
+	i_tvalid <= 1;
+	@(posedge clk);
+	@(posedge clk);
+	i_tlast <= 1;
+	@(posedge clk);
+	i_tvalid <= 0;
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	o_tready <= 1;
+
+     end
+   
+endmodule // axi_pipe
diff --git a/fpga/usrp3/lib/sim/rfnoc/axi_rate_change/Makefile b/fpga/usrp3/lib/sim/rfnoc/axi_rate_change/Makefile
new file mode 100644
index 000000000..fcf21b755
--- /dev/null
+++ b/fpga/usrp3/lib/sim/rfnoc/axi_rate_change/Makefile
@@ -0,0 +1,37 @@
+#
+# Copyright 2016 Ettus Research
+#
+
+#-------------------------------------------------
+# Top-of-Makefile
+#-------------------------------------------------
+# Define BASE_DIR to point to the "top" dir
+BASE_DIR = $(abspath ../../../../top)
+# Include viv_sim_preamble after defining BASE_DIR
+include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
+
+#-------------------------------------------------
+# Testbench Specific
+#-------------------------------------------------
+# Define only one toplevel module
+SIM_TOP = axi_rate_change_tb
+
+# Add test bench, user design under test, and
+# additional user created files
+SIM_SRCS = $(abspath \
+axi_rate_change_tb.sv \
+$(LIB_DIR)/control/ram_2port.v \
+$(LIB_DIR)/fifo/axi_packet_gate.v \
+$(LIB_DIR)/rfnoc/axi_rate_change.v \
+$(LIB_DIR)/rfnoc/axi_drop_partial_packet.v \
+)
+
+MODELSIM_USER_DO = $(abspath wave.do)
+
+#-------------------------------------------------
+# Bottom-of-Makefile
+#-------------------------------------------------
+# Include all simulator specific makefiles here
+# Each should define a unique target to simulate
+# e.g. xsim, vsim, etc and a common "clean" target
+include $(BASE_DIR)/../tools/make/viv_simulator.mak
diff --git a/fpga/usrp3/lib/sim/rfnoc/axi_rate_change/axi_rate_change_tb.sv b/fpga/usrp3/lib/sim/rfnoc/axi_rate_change/axi_rate_change_tb.sv
new file mode 100644
index 000000000..b16c2d26d
--- /dev/null
+++ b/fpga/usrp3/lib/sim/rfnoc/axi_rate_change/axi_rate_change_tb.sv
@@ -0,0 +1,323 @@
+`timescale 1ns/1ps
+`define NS_PER_TICK 1
+`define NUM_TEST_CASES 4
+
+`include "sim_exec_report.vh"
+`include "sim_clks_rsts.vh"
+`include "sim_cvita_lib.svh"
+`include "sim_axis_lib.svh"
+`include "sim_set_rb_lib.svh"
+
+module axi_rate_change_tb();
+  `TEST_BENCH_INIT("axi_rate_change_tb",`NUM_TEST_CASES,`NS_PER_TICK);
+  localparam CLK_PERIOD = $ceil(1e9/166.67e6);
+  `DEFINE_CLK(clk, CLK_PERIOD, 50);
+  `DEFINE_RESET(reset, 0, 100);
+
+  localparam SR_N_ADDR      = 0;
+  localparam SR_M_ADDR      = 1;
+  localparam SR_CONFIG_ADDR = 2;
+  localparam MAX_N = 16;
+  localparam MAX_M = 16;
+
+  logic [15:0] src_sid = 16'h0000;
+  logic [15:0] dst_sid = 16'h0010;
+  settings_bus_master sb (.clk(clk));
+  axis_master #(.DWIDTH(32+128)) m_axis (.clk(clk));
+  axis_slave #(.DWIDTH(32+128)) s_axis (.clk(clk));
+  logic clear, clear_user;
+  logic [31:0] m_axis_data_tdata, s_axis_data_tdata;
+  logic m_axis_data_tlast, m_axis_data_tvalid, m_axis_data_tready;
+  logic s_axis_data_tlast, s_axis_data_tvalid, s_axis_data_tready;
+  logic warning_long_throttle, error_extra_outputs, error_drop_pkt_lockup;
+  axi_rate_change #(
+    .WIDTH(32),
+    .MAX_N(MAX_N),
+    .MAX_M(MAX_M),
+    .SR_N_ADDR(SR_N_ADDR),
+    .SR_M_ADDR(SR_M_ADDR),
+    .SR_CONFIG_ADDR(SR_CONFIG_ADDR))
+  axi_rate_change (
+    .clk(clk), .reset(reset), .clear(clear), .clear_user(clear_user),
+    .src_sid(src_sid), .dst_sid(dst_sid),
+    .set_stb(sb.settings_bus.set_stb), .set_addr(sb.settings_bus.set_addr), .set_data(sb.settings_bus.set_data),
+    .i_tdata(m_axis.axis.tdata[31:0]), .i_tlast(m_axis.axis.tlast), .i_tvalid(m_axis.axis.tvalid), .i_tready(m_axis.axis.tready), .i_tuser(m_axis.axis.tdata[159:32]),
+    .o_tdata(s_axis.axis.tdata[31:0]), .o_tlast(s_axis.axis.tlast), .o_tvalid(s_axis.axis.tvalid), .o_tready(s_axis.axis.tready), .o_tuser(s_axis.axis.tdata[159:32]),
+    .m_axis_data_tdata(m_axis_data_tdata), .m_axis_data_tlast(m_axis_data_tlast),
+    .m_axis_data_tvalid(m_axis_data_tvalid), .m_axis_data_tready(m_axis_data_tready),
+    .s_axis_data_tdata(s_axis_data_tdata), .s_axis_data_tlast(s_axis_data_tlast),
+    .s_axis_data_tvalid(s_axis_data_tvalid), .s_axis_data_tready(s_axis_data_tready),
+    .warning_long_throttle(warning_long_throttle),
+    .error_extra_outputs(error_extra_outputs),
+    .error_drop_pkt_lockup(error_drop_pkt_lockup));
+
+  // Simulate user logic that can handle various decimation / interpolation rates
+  // - Generates a word count sequence that is checked in the test_rate() task.
+  // - Introduces a single clock cycle delay which is useful for testing that
+  //   the DUT is not reliant on user logic having a large built in delay.
+  integer rate_n, rate_m, count_n, count_m, count_in, count_out;
+  always @(posedge clk) begin
+    if (reset | clear_user | clear) begin
+      s_axis_data_tlast  <= 1'b0;
+      count_n            <= 1;
+      count_m            <= 1;
+      count_in           <= 0;
+      count_out          <= 0;
+    end else begin
+      // Rate change = N/M
+      if (m_axis_data_tvalid & m_axis_data_tready) begin
+        if (count_n == rate_n) begin
+          count_n        <= 1;
+          count_in       <= count_in + 1;
+        end else begin
+          count_n        <= count_n + 1;
+        end
+      end
+      if (count_in != count_out) begin
+        if (s_axis_data_tvalid & s_axis_data_tready) begin
+          if (count_m == rate_m) begin
+            count_m          <= 1;
+            count_out        <= count_out + 1;
+          end else begin
+            count_m          <= count_m + 1;
+          end
+        end
+      end
+    end
+  end
+
+  assign s_axis_data_tdata  = {count_out[15:0], count_m[15:0]};
+  assign s_axis_data_tvalid = (count_in != count_out);
+  assign m_axis_data_tready = s_axis_data_tready;
+
+  // Used with test 3 to count output clock cycles
+  int clock_cnt;
+  logic clock_cnt_en = 1'b0;
+  logic clock_cnt_start = 1'b0;
+  always @(posedge clk) begin
+    if (clock_cnt_en == 1'b1) begin
+      // Wait until output data starts
+      if (s_axis.axis.tvalid & ~clock_cnt_start) begin
+        clock_cnt_start <= 1'b1;
+        clock_cnt       <= clock_cnt + 1;
+      end else if (clock_cnt_start) begin
+        clock_cnt       <= clock_cnt + 1;
+      end
+    end else begin
+      clock_cnt_start <= 1'b0;
+      clock_cnt       <= 0;
+    end
+  end
+
+  /********************************************************
+  ** Verification
+  ********************************************************/
+  task random_wait(int unsigned min_cycles, int unsigned max_cycles);
+    begin
+      int unsigned num_cycles;
+      do begin
+        num_cycles = $random() & (2**($clog2(max_cycles))-1);
+      end while ((num_cycles < min_cycles) || (num_cycles > max_cycles));
+
+      if (num_cycles != 0) begin
+        for (int unsigned i = 0; i < num_cycles; i++) begin
+          @(posedge clk);
+        end
+        @(negedge clk); // Realign with negedge
+      end
+    end
+  endtask
+
+  task test_rate(int n, int m, int num_words, int spp = 16, bit rand_delay_in = 0, bit rand_delay_out = 0);
+    begin
+      clear = 1'b1;
+      @(posedge clk);
+      @(posedge clk);
+      clear = 1'b0;
+      @(posedge clk);
+      @(posedge clk);
+      rate_n = n;
+      rate_m = m;
+      sb.write(SR_N_ADDR, n);
+      sb.write(SR_M_ADDR, m);
+      @(posedge clk);
+      fork
+      begin
+        cvita_hdr_t send_header;
+        int words_left_to_send, words_to_send;
+        logic [31:0] words_sent;
+        real timestamp;
+        timestamp = 0.0;
+        words_sent = 0;
+        words_left_to_send = num_words;
+
+        while (words_left_to_send > 0) begin
+          // Setup header
+          send_header = '{default:0};
+          send_header.has_time = 1;
+          send_header.timestamp = longint'(timestamp);
+          send_header.eob = (words_left_to_send <= spp);
+          if (words_left_to_send >= spp) begin
+            send_header.length = 16+4*spp;
+            words_to_send = spp;
+            words_left_to_send -= spp;
+          end else begin
+            send_header.length = 16+4*words_left_to_send;
+            words_to_send = words_left_to_send;
+            words_left_to_send = 0;
+          end
+          // Send packet
+          for (int i = 0; i < words_to_send; i++) begin
+            if (rand_delay_in) random_wait(0,2*spp);
+            m_axis.push_word({send_header,words_sent + i},i == words_to_send-1);
+          end
+          words_sent += words_to_send;
+          // Update seq num, timestamp
+          send_header.seqnum++;
+          timestamp += (1.0*m/n)*words_to_send;
+        end
+      end
+      begin
+        string s;
+        cvita_hdr_t recv_header;
+        logic last, expected_eob;
+        real timestamp;
+        logic [63:0] expected_timestamp;
+        logic [31:0] word;
+        logic [15:0] word_cnt_div_m, word_cnt_div_m_frac;
+        logic [15:0] word_cnt_div_spp_frac;
+        int words_left_to_recv, words_recvd;
+        timestamp = 0.0;
+        expected_timestamp = 0; // Timestamp starts at 0
+        word_cnt_div_spp_frac = 0;
+        word_cnt_div_m = 0;
+        word_cnt_div_m_frac = 0;
+        words_recvd = 0;
+        words_left_to_recv = $floor(num_words/n)*m; // Order matters!
+
+        while (words_left_to_recv > 0) begin
+          s_axis.pull_word({recv_header,word},last);
+          word_cnt_div_spp_frac++;
+          word_cnt_div_m_frac++;
+          words_recvd++;
+          words_left_to_recv--;
+          timestamp += 1.0*n;
+          // Check packet length
+          if ((word_cnt_div_spp_frac == spp) || (words_left_to_recv == 0)) begin
+            `ASSERT_FATAL(last == 1, "Incorrect packet length! Last not asserted!");
+            word_cnt_div_spp_frac = 0;
+          end else begin
+            $sformat(s, "Incorrect packet length! Expected: %0d, Actual %0d", spp, words_recvd);
+            `ASSERT_FATAL(last == 0, s);
+          end
+          // Check for EOB
+          if (last) begin
+            words_recvd = 0;
+            expected_eob = (words_left_to_recv == 0);
+            $sformat(s, "Incorrect EOB state! Expected: %0d, Actual %0d", expected_eob, recv_header.eob);
+            `ASSERT_FATAL(recv_header.eob == expected_eob, s);
+          end
+          // Check timestamp
+          if (last) begin
+            $sformat(s, "Incorrect timestamp! Expected: %0d, Actual %0d", expected_timestamp, recv_header.timestamp);
+            `ASSERT_FATAL(recv_header.timestamp == expected_timestamp, s);
+            expected_timestamp = longint'(timestamp);
+          end
+          // Check word
+          $sformat(s, "Incorrect packet data! Expected: 0x%08h, Actual: 0x%08h", {word_cnt_div_m, word_cnt_div_m_frac}, word);
+          `ASSERT_FATAL(((word[31:16] == word_cnt_div_m) && (word[15:0] == word_cnt_div_m_frac)), s);
+          // Track number of received words, do at end of loop
+          if (word_cnt_div_m_frac == m) begin
+            word_cnt_div_m_frac = 0;
+            word_cnt_div_m++;
+          end
+        end
+      end
+      join
+    end
+  endtask
+
+  initial begin : tb_main
+    string s;
+    cvita_hdr_t tmp_header;
+    logic [63:0] word;
+    logic last;
+    integer spp, number_words;
+    spp = 16;
+
+    /********************************************************
+    ** Test 1 -- Reset
+    ********************************************************/
+    `TEST_CASE_START("Wait for Reset");
+    sb.reset();
+    m_axis.reset();
+    s_axis.reset();
+    while (reset) @(posedge clk);
+    `TEST_CASE_DONE(~reset);
+
+    /********************************************************
+    ** Test 2 -- Test various rates
+    ** - Try many decimation / interpolation rates (including 
+    **   fractional rates) and use randomized delays.
+    ********************************************************/
+    `TEST_CASE_START("Check various rates");
+    for (int _n = 1; _n <= MAX_N; _n++) begin
+      for (int _m = 1; _m <= MAX_M; _m++) begin
+        $display("Testing rate %0d:%0d", _n, _m);
+        test_rate(_n, _m, _n*spp*3, spp, 1, 1);
+      end
+    end
+    `TEST_CASE_DONE(1);
+
+    #2000; // Delay to make the tests visually distinct in waveform viewer
+
+    /********************************************************
+    ** Test 3 -- Test partial packets
+    ** - Send packets with extra data that is less than SPP.
+    **   Module should output the maximum number of samples
+    **   possible while dropping the "partial" sample.
+    ********************************************************/
+    `TEST_CASE_START("Test partial packets");
+    for (int _n = 1; _n <= MAX_N; _n++) begin
+      for (int _m = 1; _m <= MAX_M; _m++) begin
+        $display("Testing rate %0d:%0d", _n, _m);
+        test_rate(_n, _m, _n*spp + spp-1, spp, 1, 1);
+      end
+    end
+    `TEST_CASE_DONE(1);
+
+    #2000;
+
+    /********************************************************
+    ** Test 3 -- Test for bubble states
+    ** - Send many packets at full rate and make sure number
+    **   of input clock cycles == output clock cycles. If
+    **   they do not match, then the module likely has
+    **   bubble states that would prevent it from running
+    **   continuously at full rate.
+    ********************************************************/
+    `TEST_CASE_START("Test for bubble states");
+    clock_cnt_en = 1'b1;
+    number_words = 100000;
+    test_rate(1, 1, number_words, spp, 0, 0);
+    $sformat(s, "Incorrect number of clock cycles -- Possible bubble states detected! Expected: %0d, Actual: %0d", number_words, clock_cnt);
+    `ASSERT_FATAL(clock_cnt == number_words, s);
+    clock_cnt_en = 1'b0;
+    `TEST_CASE_DONE(1);
+
+    `TEST_BENCH_DONE;
+
+  end
+
+  // The warning, error signals should never assert.
+  initial begin
+    while (reset) @(posedge clk);
+    forever begin
+      @(posedge clk);
+      `ASSERT_FATAL(~warning_long_throttle,    "Throttle state deadlock!");
+      `ASSERT_FATAL(~error_extra_outputs,      "Extra outputs detected!");
+      `ASSERT_FATAL(~error_drop_pkt_lockup,    "Drop packet deadlock!");
+    end
+  end
+
+endmodule
diff --git a/fpga/usrp3/lib/sim/rfnoc/axi_rate_change/wave.do b/fpga/usrp3/lib/sim/rfnoc/axi_rate_change/wave.do
new file mode 100644
index 000000000..f16b9d5a7
--- /dev/null
+++ b/fpga/usrp3/lib/sim/rfnoc/axi_rate_change/wave.do
@@ -0,0 +1,115 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/clk
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/reset
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/clear
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/clear_user
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/active
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/i_tdata
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/i_tlast
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/i_tvalid
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/i_tready
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/i_tuser
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/word_cnt_div_n
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/word_cnt_div_n_frac
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/word_cnt_div_n_tdata
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/word_cnt_div_n_tready
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/word_cnt_div_n_tvalid
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/in_pkt_cnt
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/i_reg_tdata
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/i_reg_tlast
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/i_reg_tvalid
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/i_reg_tready
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/i_reg_tuser
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/m_axis_data_tdata
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/m_axis_data_tlast
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/m_axis_data_tvalid
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/m_axis_data_tready
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/s_axis_data_tdata
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/s_axis_data_tlast
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/s_axis_data_tvalid
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/s_axis_data_tready
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/out_payload_cnt
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/payload_length_out
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/word_cnt_div_m
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/word_cnt_div_n_fifo_tdata
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/word_cnt_div_n_fifo_tready
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/word_cnt_div_n_fifo_tvalid
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/first_pkt_out
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/vita_time_out
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/vita_time_accum
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/vita_time_reg
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/header_fifo_out_tready
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/header_fifo_out_tvalid
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/o_reg_tdata
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/o_reg_tlast
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/o_reg_tvalid
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/o_reg_tready
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/o_reg_tuser
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/o_tdata
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/o_tlast
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/o_tvalid
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/o_tready
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/o_tuser
+add wave -noupdate -divider {AXI Drop Partial Packet}
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/i_tdata
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/i_terror
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/i_tlast
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/i_tlast_int
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/i_tready
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/i_tvalid
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/in_cnt
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/large_pkt
+add wave -noupdate {/axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/o_tdata[32]}
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/o_tdata
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/o_tlast
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/o_tready
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/o_tvalid
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/small_pkt
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/flush
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/hold_last_sample
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/in_pkt_cnt
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/out_pkt_cnt
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/release_due_to_error
+add wave -noupdate -divider {AXI Drop Packet}
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/hold
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/i_tdata
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/i_tvalid
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/i_terror
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/i_tlast
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/i_tready
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/empty
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/full
+add wave -noupdate -radix unsigned /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/rd_addr
+add wave -noupdate -radix unsigned /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/wr_addr
+add wave -noupdate -radix unsigned /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/in_pkt_cnt
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/int_tdata
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/int_tvalid
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/int_tlast
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/int_tready
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/mem
+add wave -noupdate -radix hexadecimal /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/o_tdata
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/o_tvalid
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/o_tready
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/o_tlast
+add wave -noupdate -radix unsigned /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/out_pkt_cnt
+add wave -noupdate -radix unsigned /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/prev_wr_addr
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/n
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {1112517 ps} 0} {{Cursor 2} {1974349848 ps} 0}
+quietly wave cursor active 2
+configure wave -namecolwidth 633
+configure wave -valuecolwidth 184
+configure wave -justifyvalue left
+configure wave -signalnamewidth 0
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {1974303474 ps} {1974374671 ps}
diff --git a/fpga/usrp3/lib/sim/rfnoc/axi_wrapper/axi_wrapper_tb.v b/fpga/usrp3/lib/sim/rfnoc/axi_wrapper/axi_wrapper_tb.v
new file mode 100644
index 000000000..7a15d1d86
--- /dev/null
+++ b/fpga/usrp3/lib/sim/rfnoc/axi_wrapper/axi_wrapper_tb.v
@@ -0,0 +1,144 @@
+//
+// Copyright 2012-2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+module axi_wrapper_tb();
+   
+   xlnx_glbl glbl (.GSR(),.GTS());
+   
+   localparam STR_SINK_FIFOSIZE = 9;
+      
+   reg clk, reset;
+   always
+     #100 clk = ~clk;
+
+   initial clk = 0;
+   initial reset = 1;
+   initial #1000 reset = 0;
+   
+   initial $dumpfile("axi_wrapper_tb.vcd");
+   initial $dumpvars(0,axi_wrapper_tb);
+
+   initial #1000000 $finish;
+
+   wire [31:0] set_data;
+   wire [7:0]  set_addr;
+   wire        set_stb;
+
+   wire [63:0] noci_tdata[PORTS-1:0];
+   wire        noci_tlast[PORTS-1:0];
+   wire        noci_tvalid[PORTS-1:0];
+   wire        noci_tready[PORTS-1:0];
+
+   wire [63:0] noco_tdata[PORTS-1:0];
+   wire        noco_tlast[PORTS-1:0];
+   wire        noco_tvalid[PORTS-1:0];
+   wire        noco_tready[PORTS-1:0];
+
+   reg [63:0]  src_tdata;
+   reg 	       src_tlast, src_tvalid;
+   wire        src_tready;
+
+   localparam PORTS = 4;
+
+   wire [63:0] s1o_tdata, s1i_tdata;
+   wire        s1o_tlast, s1i_tlast, s1o_tvalid, s1i_tvalid, s1o_tready, s1i_tready;
+   
+   wire [31:0] pre_tdata, post_tdata;
+   wire        pre_tlast, post_tlast, pre_tvalid, post_tvalid, pre_tready, post_tready;
+   wire [127:0] pre_tuser, post_tuser;
+      
+   axi_wrapper #(.BASE(8), .NUM_AXI_CONFIG_BUS(1), .CONFIG_BUS_FIFO_DEPTH(5), .SIMPLE_MODE(1)) axi_wrapper_ce1
+     (.clk(clk), .reset(reset),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .i_tdata(src_tdata), .i_tlast(src_tlast), .i_tvalid(src_tvalid), .i_tready(src_tready),
+      .o_tdata(s1i_tdata), .o_tlast(s1i_tlast), .o_tvalid(s1i_tvalid), .o_tready(s1i_tready),
+      .m_axis_data_tdata(pre_tdata),
+      .m_axis_data_tuser(pre_tuser),
+      .m_axis_data_tlast(pre_tlast),
+      .m_axis_data_tvalid(pre_tvalid),
+      .m_axis_data_tready(pre_tready),
+      .s_axis_data_tdata(post_tdata),
+      .s_axis_data_tuser(post_tuser),
+      .s_axis_data_tlast(post_tlast),
+      .s_axis_data_tvalid(post_tvalid),
+      .s_axis_data_tready(post_tready)
+      );
+
+   axi_fifo #(.WIDTH(33)) afifo
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata({pre_tlast,pre_tdata}), .i_tvalid(pre_tvalid), .i_tready(pre_tready),
+      .o_tdata({post_tlast,post_tdata}), .o_tvalid(post_tvalid), .o_tready(post_tready));
+
+   assign s1i_tready = 1'b1;
+   
+
+   task SendPacket;
+      input [3:0]  flags;
+      input [11:0] seqnum;
+      input [15:0] len;
+      input [31:0] sid;
+      input [63:0] data;
+      
+      begin
+	 @(posedge clk);
+	 src_tdata <= { flags, seqnum, len+16'd8 + (flags[1] ? 16'd8 : 16'd0), sid };
+	 src_tlast <= 0;
+	 src_tvalid <= 1;
+	 @(posedge clk);
+	 while(~src_tready)
+	   @(posedge clk);
+
+	 // send time if flags request it
+	 if(flags[1])
+	   begin
+	      src_tdata <= 64'h0123_4567_89ab_cdef;
+	      src_tlast <= 0;
+	      src_tvalid <= 1;
+	      @(posedge clk);
+	      while(~src_tready)
+		@(posedge clk);
+	   end
+
+	 src_tdata <= data;
+	 repeat(len[15:3] + (len[2]|len[1]|len[0])- 1 )
+	   begin
+	      @(posedge clk);
+	      while(~src_tready)
+		@(posedge clk);
+	      src_tdata <= src_tdata + 64'd1;
+	   end
+	 src_tlast <= 1;
+	 @(posedge clk);
+	 while(~src_tready)
+	   @(posedge clk);
+	 src_tvalid <= 0;
+	 @(posedge clk);
+      end
+   endtask // SendPacket
+   
+   initial
+     begin
+	src_tdata <= 64'd0;
+	src_tlast <= 1'b0;
+	src_tvalid <= 1'b0;
+	@(negedge reset);
+	@(posedge clk);
+	
+	@(posedge clk);
+
+	#10000;
+	SendPacket(4'h0, 12'd7, 16'd64, 32'h0002_0003, 64'hAAAA_AAAA_0000_0000); // data packet
+	SendPacket(4'h0, 12'd8, 16'd68, 32'h0004_0005, 64'hBBBB_BBBB_0000_0000); // data packet
+	//SendPacket(4'h0, 12'd2, 16'd8, 32'h0000_0001, 64'hCCCC_CCCC_0000_0000); // data packet
+	//SendPacket(4'h0, 12'd3, 16'd8, 32'h0000_0001, 64'hDDDD_DDDD_0000_0000); // data packet
+	//SendPacket(4'h0, 12'd4, 16'd8, 32'h0000_0001, 64'hEEEE_EEEE_0000_0000); // data packet
+	//SendPacket(4'h0, 12'd5, 16'd8, 32'h0000_0001, 64'hFFFF_FFFF_0000_0000); // data packet
+	//SendPacket(4'h0, 12'd6, 16'd8, 32'h0000_0001, 64'h2222_2222_0000_0000); // data packet
+     end
+
+endmodule // axi_wrapper_tb
diff --git a/fpga/usrp3/lib/sim/rfnoc/axi_wrapper/build_axi_wrapper_tb b/fpga/usrp3/lib/sim/rfnoc/axi_wrapper/build_axi_wrapper_tb
new file mode 100755
index 000000000..49b8fe312
--- /dev/null
+++ b/fpga/usrp3/lib/sim/rfnoc/axi_wrapper/build_axi_wrapper_tb
@@ -0,0 +1 @@
+iverilog -o axi_wrapper_tb axi_wrapper_tb.v -y . -y ../control/ -y ../fifo/ -y /opt/Xilinx/14.6/ISE_DS/ISE/verilog/src/unisims/ -y ../packet_proc/ -y ../timing/ -y ../vita/ -y ../../top/x300/coregen -y /opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/XilinxCoreLib -y ../coregen/ -y ../ -y ../../../usrp2/models/ -Wall
diff --git a/fpga/usrp3/lib/sim/rfnoc/chdr_deframer/chdr_deframer_tb.v b/fpga/usrp3/lib/sim/rfnoc/chdr_deframer/chdr_deframer_tb.v
new file mode 100644
index 000000000..312ca478d
--- /dev/null
+++ b/fpga/usrp3/lib/sim/rfnoc/chdr_deframer/chdr_deframer_tb.v
@@ -0,0 +1,87 @@
+//
+// Copyright 2012-2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+//`timescale 1ns
+module chdr_deframer_tb();
+   
+   reg clk, reset;
+   always
+     #100 clk = ~clk;
+
+   initial $dumpfile("chdr_deframer_tb.vcd");
+   initial $dumpvars(0,chdr_deframer_tb);
+
+   reg [63:0] i_tdata;
+   reg i_tlast, i_tvalid;
+   wire i_tready;
+
+   wire [31:0] o_tdata;
+   wire [127:0] o_tuser;
+   wire        o_tlast, o_tvalid;
+
+   reg 	       o_tready = 1;
+
+   wire [63:0] int_tdata;
+   wire        int_tlast, int_tvalid, int_tready;
+   
+   axi_fifo #(.SIZE(10), .WIDTH(65)) fifo
+     (.clk(clk), .reset(reset), .clear(0),
+      .i_tdata({i_tlast, i_tdata}), .i_tvalid(i_tvalid), .i_tready(i_tready),
+      .o_tdata({int_tlast, int_tdata}), .o_tvalid(int_tvalid), .o_tready(int_tready));
+   
+   chdr_deframer chdr_deframer
+     (.clk(clk), .reset(reset), .clear(0),
+      .i_tdata(int_tdata), .i_tlast(int_tlast), .i_tvalid(int_tvalid), .i_tready(int_tready),
+      .o_tdata(o_tdata), .o_tuser(o_tuser), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready));
+
+   reg [63:0]  hdr, vtime, data;
+   
+   initial
+     begin
+	clk = 0;
+	reset = 1;
+	i_tlast = 0;
+	i_tvalid = 0;
+	hdr = 64'hFF00_AAB9_BEEF_0000;
+	vtime = 64'h8888_7777_6666_0000;
+	data = 64'hEEEE_0000_FFFF_0001;
+	#1000 reset = 0;
+	repeat (10)
+	  @(posedge clk);
+	repeat (6)
+	  begin
+	     #1 i_tdata = hdr;
+	     #1 i_tlast = 0;
+	     #1 i_tvalid = 1;
+	     @(posedge clk);
+	     #1 i_tdata = vtime;
+	     @(posedge clk);
+	     #1 hdr = hdr + 1;
+	     #1 vtime = vtime + 1;
+	     repeat (10)
+	       begin
+		  #1 i_tdata = data;
+		  #1 data = data + 64'h0000_0002_0000_0002;
+		  @(posedge clk);
+	       end
+	     #1 i_tdata = data;
+	     #1 data = data + 64'h0000_0002_0000_0002;
+	     #1 i_tlast <= 1;
+	     @(posedge clk);
+	  end // repeat (20)
+	#1 i_tvalid <= 0;
+	#200000 $finish;
+     end
+
+   always @(posedge clk)
+     if(o_tvalid & o_tready)
+       if(o_tlast)
+	 $display("%x    LAST",o_tdata);
+       else
+	 $display("%x",o_tdata);
+   
+endmodule // chdr_deframer_tb
diff --git a/fpga/usrp3/lib/sim/rfnoc/chdr_framer/chdr_framer_tb.v b/fpga/usrp3/lib/sim/rfnoc/chdr_framer/chdr_framer_tb.v
new file mode 100644
index 000000000..71b507e35
--- /dev/null
+++ b/fpga/usrp3/lib/sim/rfnoc/chdr_framer/chdr_framer_tb.v
@@ -0,0 +1,80 @@
+//
+// Copyright 2012-2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+//`timescale 1ns
+module chdr_framer_tb();
+   
+   reg clk, reset;
+   always
+     #100 clk = ~clk;
+
+   initial $dumpfile("chdr_framer_tb.vcd");
+   initial $dumpvars(0,chdr_framer_tb);
+
+   reg [31:0] i_tdata;
+   reg [127:0] i_tuser;
+   reg i_tlast, i_tvalid;
+   wire i_tready;
+
+   wire [63:0] o_tdata;
+   wire        o_tlast, o_tvalid;
+
+   reg 	       o_tready = 0;
+   
+   chdr_framer #(.SIZE(10)) chdr_framer
+     (.clk(clk), .reset(reset), .clear(0),
+      .i_tdata(i_tdata), .i_tuser(i_tuser), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready),
+      .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready));
+
+   always 
+     begin
+	#1 o_tready = 1;
+	repeat (200)
+	  @(posedge clk);
+	#1 o_tready = 0;
+	repeat (120)
+	  @(posedge clk);
+     end
+		   
+	    
+   initial
+     begin
+	clk = 0;
+	reset = 1;
+	i_tlast = 0;
+	i_tvalid = 0;
+	i_tdata = 32'hBEEF_0000;
+	i_tuser = 128'hF123_4567_89ab_cdef_0011_2233_4455_0000;
+	#1000 reset = 0;
+	repeat (10)
+	  @(posedge clk);
+	#1 i_tvalid = 1;
+	repeat (400)
+	  begin
+	     #1 i_tlast = 0;
+	     repeat (22)
+	       begin
+		  #1 i_tdata = i_tdata + 1;
+		  @(posedge clk);
+	       end
+	     #1 i_tdata = i_tdata + 1;
+	     #1 i_tlast = 1;
+	     @(posedge clk);
+	     #1 i_tuser <= i_tuser + 1;
+	  end // repeat (20)
+	#1 i_tvalid <= 0;
+	#100000 $finish;
+     end
+
+   always @(posedge clk)
+     if(o_tvalid & o_tready)
+       if(o_tlast)
+	 $display("%x    LAST",o_tdata);
+       else
+	 $display("%x",o_tdata);
+   
+endmodule // chdr_framer_tb
diff --git a/fpga/usrp3/lib/sim/rfnoc/display_samples.grc b/fpga/usrp3/lib/sim/rfnoc/display_samples.grc
new file mode 100644
index 000000000..d900da4cc
--- /dev/null
+++ b/fpga/usrp3/lib/sim/rfnoc/display_samples.grc
@@ -0,0 +1,413 @@
+<?xml version='1.0' encoding='ASCII'?>
+<flow_graph>
+  <timestamp>Wed May 28 15:07:06 2014</timestamp>
+  <block>
+    <key>options</key>
+    <param>
+      <key>id</key>
+      <value>top_block</value>
+    </param>
+    <param>
+      <key>_enabled</key>
+      <value>True</value>
+    </param>
+    <param>
+      <key>title</key>
+      <value></value>
+    </param>
+    <param>
+      <key>author</key>
+      <value></value>
+    </param>
+    <param>
+      <key>description</key>
+      <value></value>
+    </param>
+    <param>
+      <key>window_size</key>
+      <value>1280, 1024</value>
+    </param>
+    <param>
+      <key>generate_options</key>
+      <value>wx_gui</value>
+    </param>
+    <param>
+      <key>category</key>
+      <value>Custom</value>
+    </param>
+    <param>
+      <key>run_options</key>
+      <value>prompt</value>
+    </param>
+    <param>
+      <key>run</key>
+      <value>True</value>
+    </param>
+    <param>
+      <key>max_nouts</key>
+      <value>0</value>
+    </param>
+    <param>
+      <key>realtime_scheduling</key>
+      <value></value>
+    </param>
+    <param>
+      <key>_coordinate</key>
+      <value>(10, 10)</value>
+    </param>
+    <param>
+      <key>_rotation</key>
+      <value>0</value>
+    </param>
+  </block>
+  <block>
+    <key>variable</key>
+    <param>
+      <key>id</key>
+      <value>samp_rate</value>
+    </param>
+    <param>
+      <key>_enabled</key>
+      <value>True</value>
+    </param>
+    <param>
+      <key>value</key>
+      <value>32000</value>
+    </param>
+    <param>
+      <key>_coordinate</key>
+      <value>(10, 170)</value>
+    </param>
+    <param>
+      <key>_rotation</key>
+      <value>0</value>
+    </param>
+  </block>
+  <block>
+    <key>blocks_interleaved_short_to_complex</key>
+    <param>
+      <key>id</key>
+      <value>blocks_interleaved_short_to_complex_0</value>
+    </param>
+    <param>
+      <key>_enabled</key>
+      <value>True</value>
+    </param>
+    <param>
+      <key>vector_input</key>
+      <value>False</value>
+    </param>
+    <param>
+      <key>affinity</key>
+      <value></value>
+    </param>
+    <param>
+      <key>minoutbuf</key>
+      <value>0</value>
+    </param>
+    <param>
+      <key>maxoutbuf</key>
+      <value>0</value>
+    </param>
+    <param>
+      <key>_coordinate</key>
+      <value>(296, 296)</value>
+    </param>
+    <param>
+      <key>_rotation</key>
+      <value>0</value>
+    </param>
+  </block>
+  <block>
+    <key>blocks_throttle</key>
+    <param>
+      <key>id</key>
+      <value>blocks_throttle_0</value>
+    </param>
+    <param>
+      <key>_enabled</key>
+      <value>True</value>
+    </param>
+    <param>
+      <key>type</key>
+      <value>complex</value>
+    </param>
+    <param>
+      <key>samples_per_second</key>
+      <value>samp_rate</value>
+    </param>
+    <param>
+      <key>vlen</key>
+      <value>1</value>
+    </param>
+    <param>
+      <key>ignoretag</key>
+      <value>True</value>
+    </param>
+    <param>
+      <key>affinity</key>
+      <value></value>
+    </param>
+    <param>
+      <key>minoutbuf</key>
+      <value>0</value>
+    </param>
+    <param>
+      <key>maxoutbuf</key>
+      <value>0</value>
+    </param>
+    <param>
+      <key>_coordinate</key>
+      <value>(524, 220)</value>
+    </param>
+    <param>
+      <key>_rotation</key>
+      <value>0</value>
+    </param>
+  </block>
+  <block>
+    <key>blocks_file_source</key>
+    <param>
+      <key>id</key>
+      <value>blocks_file_source_0</value>
+    </param>
+    <param>
+      <key>_enabled</key>
+      <value>True</value>
+    </param>
+    <param>
+      <key>file</key>
+      <value>output.dat</value>
+    </param>
+    <param>
+      <key>type</key>
+      <value>short</value>
+    </param>
+    <param>
+      <key>repeat</key>
+      <value>True</value>
+    </param>
+    <param>
+      <key>vlen</key>
+      <value>1</value>
+    </param>
+    <param>
+      <key>affinity</key>
+      <value></value>
+    </param>
+    <param>
+      <key>minoutbuf</key>
+      <value>0</value>
+    </param>
+    <param>
+      <key>maxoutbuf</key>
+      <value>0</value>
+    </param>
+    <param>
+      <key>_coordinate</key>
+      <value>(165, 203)</value>
+    </param>
+    <param>
+      <key>_rotation</key>
+      <value>0</value>
+    </param>
+  </block>
+  <block>
+    <key>wxgui_fftsink2</key>
+    <param>
+      <key>id</key>
+      <value>wxgui_fftsink2_0</value>
+    </param>
+    <param>
+      <key>_enabled</key>
+      <value>False</value>
+    </param>
+    <param>
+      <key>type</key>
+      <value>complex</value>
+    </param>
+    <param>
+      <key>title</key>
+      <value>FFT Plot</value>
+    </param>
+    <param>
+      <key>samp_rate</key>
+      <value>samp_rate</value>
+    </param>
+    <param>
+      <key>baseband_freq</key>
+      <value>0</value>
+    </param>
+    <param>
+      <key>y_per_div</key>
+      <value>10</value>
+    </param>
+    <param>
+      <key>y_divs</key>
+      <value>10</value>
+    </param>
+    <param>
+      <key>ref_level</key>
+      <value>0</value>
+    </param>
+    <param>
+      <key>ref_scale</key>
+      <value>2.0</value>
+    </param>
+    <param>
+      <key>fft_size</key>
+      <value>1024</value>
+    </param>
+    <param>
+      <key>fft_rate</key>
+      <value>15</value>
+    </param>
+    <param>
+      <key>peak_hold</key>
+      <value>False</value>
+    </param>
+    <param>
+      <key>average</key>
+      <value>False</value>
+    </param>
+    <param>
+      <key>avg_alpha</key>
+      <value>0</value>
+    </param>
+    <param>
+      <key>win</key>
+      <value>None</value>
+    </param>
+    <param>
+      <key>win_size</key>
+      <value></value>
+    </param>
+    <param>
+      <key>grid_pos</key>
+      <value></value>
+    </param>
+    <param>
+      <key>notebook</key>
+      <value></value>
+    </param>
+    <param>
+      <key>freqvar</key>
+      <value>None</value>
+    </param>
+    <param>
+      <key>affinity</key>
+      <value></value>
+    </param>
+    <param>
+      <key>_coordinate</key>
+      <value>(751, 242)</value>
+    </param>
+    <param>
+      <key>_rotation</key>
+      <value>0</value>
+    </param>
+  </block>
+  <block>
+    <key>wxgui_scopesink2</key>
+    <param>
+      <key>id</key>
+      <value>wxgui_scopesink2_0</value>
+    </param>
+    <param>
+      <key>_enabled</key>
+      <value>True</value>
+    </param>
+    <param>
+      <key>type</key>
+      <value>complex</value>
+    </param>
+    <param>
+      <key>title</key>
+      <value>Scope Plot</value>
+    </param>
+    <param>
+      <key>samp_rate</key>
+      <value>samp_rate</value>
+    </param>
+    <param>
+      <key>v_scale</key>
+      <value>0</value>
+    </param>
+    <param>
+      <key>v_offset</key>
+      <value>0</value>
+    </param>
+    <param>
+      <key>t_scale</key>
+      <value>0</value>
+    </param>
+    <param>
+      <key>ac_couple</key>
+      <value>False</value>
+    </param>
+    <param>
+      <key>xy_mode</key>
+      <value>False</value>
+    </param>
+    <param>
+      <key>num_inputs</key>
+      <value>1</value>
+    </param>
+    <param>
+      <key>win_size</key>
+      <value></value>
+    </param>
+    <param>
+      <key>grid_pos</key>
+      <value></value>
+    </param>
+    <param>
+      <key>notebook</key>
+      <value></value>
+    </param>
+    <param>
+      <key>trig_mode</key>
+      <value>wxgui.TRIG_MODE_AUTO</value>
+    </param>
+    <param>
+      <key>y_axis_label</key>
+      <value>Counts</value>
+    </param>
+    <param>
+      <key>affinity</key>
+      <value></value>
+    </param>
+    <param>
+      <key>_coordinate</key>
+      <value>(750, 134)</value>
+    </param>
+    <param>
+      <key>_rotation</key>
+      <value>0</value>
+    </param>
+  </block>
+  <connection>
+    <source_block_id>blocks_file_source_0</source_block_id>
+    <sink_block_id>blocks_interleaved_short_to_complex_0</sink_block_id>
+    <source_key>0</source_key>
+    <sink_key>0</sink_key>
+  </connection>
+  <connection>
+    <source_block_id>blocks_interleaved_short_to_complex_0</source_block_id>
+    <sink_block_id>blocks_throttle_0</sink_block_id>
+    <source_key>0</source_key>
+    <sink_key>0</sink_key>
+  </connection>
+  <connection>
+    <source_block_id>blocks_throttle_0</source_block_id>
+    <sink_block_id>wxgui_scopesink2_0</sink_block_id>
+    <source_key>0</source_key>
+    <sink_key>0</sink_key>
+  </connection>
+  <connection>
+    <source_block_id>blocks_throttle_0</source_block_id>
+    <sink_block_id>wxgui_fftsink2_0</sink_block_id>
+    <source_key>0</source_key>
+    <sink_key>0</sink_key>
+  </connection>
+</flow_graph>
diff --git a/fpga/usrp3/lib/sim/rfnoc/gen_samples.grc b/fpga/usrp3/lib/sim/rfnoc/gen_samples.grc
new file mode 100644
index 000000000..568c538ba
--- /dev/null
+++ b/fpga/usrp3/lib/sim/rfnoc/gen_samples.grc
@@ -0,0 +1,381 @@
+<?xml version='1.0' encoding='ASCII'?>
+<flow_graph>
+  <timestamp>Wed May 28 15:55:45 2014</timestamp>
+  <block>
+    <key>options</key>
+    <param>
+      <key>id</key>
+      <value>top_block</value>
+    </param>
+    <param>
+      <key>_enabled</key>
+      <value>True</value>
+    </param>
+    <param>
+      <key>title</key>
+      <value></value>
+    </param>
+    <param>
+      <key>author</key>
+      <value></value>
+    </param>
+    <param>
+      <key>description</key>
+      <value></value>
+    </param>
+    <param>
+      <key>window_size</key>
+      <value>1280, 1024</value>
+    </param>
+    <param>
+      <key>generate_options</key>
+      <value>wx_gui</value>
+    </param>
+    <param>
+      <key>category</key>
+      <value>Custom</value>
+    </param>
+    <param>
+      <key>run_options</key>
+      <value>prompt</value>
+    </param>
+    <param>
+      <key>run</key>
+      <value>True</value>
+    </param>
+    <param>
+      <key>max_nouts</key>
+      <value>0</value>
+    </param>
+    <param>
+      <key>realtime_scheduling</key>
+      <value></value>
+    </param>
+    <param>
+      <key>_coordinate</key>
+      <value>(10, 10)</value>
+    </param>
+    <param>
+      <key>_rotation</key>
+      <value>0</value>
+    </param>
+  </block>
+  <block>
+    <key>variable</key>
+    <param>
+      <key>id</key>
+      <value>samp_rate</value>
+    </param>
+    <param>
+      <key>_enabled</key>
+      <value>True</value>
+    </param>
+    <param>
+      <key>value</key>
+      <value>32000</value>
+    </param>
+    <param>
+      <key>_coordinate</key>
+      <value>(10, 170)</value>
+    </param>
+    <param>
+      <key>_rotation</key>
+      <value>0</value>
+    </param>
+  </block>
+  <block>
+    <key>blocks_complex_to_interleaved_short</key>
+    <param>
+      <key>id</key>
+      <value>blocks_complex_to_interleaved_short_0</value>
+    </param>
+    <param>
+      <key>_enabled</key>
+      <value>True</value>
+    </param>
+    <param>
+      <key>affinity</key>
+      <value></value>
+    </param>
+    <param>
+      <key>minoutbuf</key>
+      <value>0</value>
+    </param>
+    <param>
+      <key>maxoutbuf</key>
+      <value>0</value>
+    </param>
+    <param>
+      <key>_coordinate</key>
+      <value>(631, 265)</value>
+    </param>
+    <param>
+      <key>_rotation</key>
+      <value>0</value>
+    </param>
+  </block>
+  <block>
+    <key>blocks_file_sink</key>
+    <param>
+      <key>id</key>
+      <value>blocks_file_sink_0</value>
+    </param>
+    <param>
+      <key>_enabled</key>
+      <value>True</value>
+    </param>
+    <param>
+      <key>file</key>
+      <value>test.dat</value>
+    </param>
+    <param>
+      <key>type</key>
+      <value>short</value>
+    </param>
+    <param>
+      <key>vlen</key>
+      <value>1</value>
+    </param>
+    <param>
+      <key>unbuffered</key>
+      <value>False</value>
+    </param>
+    <param>
+      <key>append</key>
+      <value>False</value>
+    </param>
+    <param>
+      <key>affinity</key>
+      <value></value>
+    </param>
+    <param>
+      <key>_coordinate</key>
+      <value>(769, 142)</value>
+    </param>
+    <param>
+      <key>_rotation</key>
+      <value>0</value>
+    </param>
+  </block>
+  <block>
+    <key>wxgui_fftsink2</key>
+    <param>
+      <key>id</key>
+      <value>wxgui_fftsink2_0</value>
+    </param>
+    <param>
+      <key>_enabled</key>
+      <value>True</value>
+    </param>
+    <param>
+      <key>type</key>
+      <value>complex</value>
+    </param>
+    <param>
+      <key>title</key>
+      <value>FFT Plot</value>
+    </param>
+    <param>
+      <key>samp_rate</key>
+      <value>samp_rate</value>
+    </param>
+    <param>
+      <key>baseband_freq</key>
+      <value>0</value>
+    </param>
+    <param>
+      <key>y_per_div</key>
+      <value>10</value>
+    </param>
+    <param>
+      <key>y_divs</key>
+      <value>10</value>
+    </param>
+    <param>
+      <key>ref_level</key>
+      <value>0</value>
+    </param>
+    <param>
+      <key>ref_scale</key>
+      <value>2.0</value>
+    </param>
+    <param>
+      <key>fft_size</key>
+      <value>1024</value>
+    </param>
+    <param>
+      <key>fft_rate</key>
+      <value>15</value>
+    </param>
+    <param>
+      <key>peak_hold</key>
+      <value>False</value>
+    </param>
+    <param>
+      <key>average</key>
+      <value>False</value>
+    </param>
+    <param>
+      <key>avg_alpha</key>
+      <value>0</value>
+    </param>
+    <param>
+      <key>win</key>
+      <value>None</value>
+    </param>
+    <param>
+      <key>win_size</key>
+      <value></value>
+    </param>
+    <param>
+      <key>grid_pos</key>
+      <value></value>
+    </param>
+    <param>
+      <key>notebook</key>
+      <value></value>
+    </param>
+    <param>
+      <key>freqvar</key>
+      <value>None</value>
+    </param>
+    <param>
+      <key>affinity</key>
+      <value></value>
+    </param>
+    <param>
+      <key>_coordinate</key>
+      <value>(626, 319)</value>
+    </param>
+    <param>
+      <key>_rotation</key>
+      <value>0</value>
+    </param>
+  </block>
+  <block>
+    <key>blocks_throttle</key>
+    <param>
+      <key>id</key>
+      <value>blocks_throttle_0</value>
+    </param>
+    <param>
+      <key>_enabled</key>
+      <value>True</value>
+    </param>
+    <param>
+      <key>type</key>
+      <value>complex</value>
+    </param>
+    <param>
+      <key>samples_per_second</key>
+      <value>samp_rate</value>
+    </param>
+    <param>
+      <key>vlen</key>
+      <value>1</value>
+    </param>
+    <param>
+      <key>ignoretag</key>
+      <value>True</value>
+    </param>
+    <param>
+      <key>affinity</key>
+      <value></value>
+    </param>
+    <param>
+      <key>minoutbuf</key>
+      <value>0</value>
+    </param>
+    <param>
+      <key>maxoutbuf</key>
+      <value>0</value>
+    </param>
+    <param>
+      <key>_coordinate</key>
+      <value>(433, 164)</value>
+    </param>
+    <param>
+      <key>_rotation</key>
+      <value>0</value>
+    </param>
+  </block>
+  <block>
+    <key>analog_sig_source_x</key>
+    <param>
+      <key>id</key>
+      <value>analog_sig_source_x_0</value>
+    </param>
+    <param>
+      <key>_enabled</key>
+      <value>True</value>
+    </param>
+    <param>
+      <key>type</key>
+      <value>complex</value>
+    </param>
+    <param>
+      <key>samp_rate</key>
+      <value>samp_rate</value>
+    </param>
+    <param>
+      <key>waveform</key>
+      <value>analog.GR_COS_WAVE</value>
+    </param>
+    <param>
+      <key>freq</key>
+      <value>123.2435</value>
+    </param>
+    <param>
+      <key>amp</key>
+      <value>32000</value>
+    </param>
+    <param>
+      <key>offset</key>
+      <value>0</value>
+    </param>
+    <param>
+      <key>affinity</key>
+      <value></value>
+    </param>
+    <param>
+      <key>minoutbuf</key>
+      <value>0</value>
+    </param>
+    <param>
+      <key>maxoutbuf</key>
+      <value>0</value>
+    </param>
+    <param>
+      <key>_coordinate</key>
+      <value>(218, 177)</value>
+    </param>
+    <param>
+      <key>_rotation</key>
+      <value>0</value>
+    </param>
+  </block>
+  <connection>
+    <source_block_id>analog_sig_source_x_0</source_block_id>
+    <sink_block_id>blocks_throttle_0</sink_block_id>
+    <source_key>0</source_key>
+    <sink_key>0</sink_key>
+  </connection>
+  <connection>
+    <source_block_id>blocks_throttle_0</source_block_id>
+    <sink_block_id>blocks_complex_to_interleaved_short_0</sink_block_id>
+    <source_key>0</source_key>
+    <sink_key>0</sink_key>
+  </connection>
+  <connection>
+    <source_block_id>blocks_complex_to_interleaved_short_0</source_block_id>
+    <sink_block_id>blocks_file_sink_0</sink_block_id>
+    <source_key>0</source_key>
+    <sink_key>0</sink_key>
+  </connection>
+  <connection>
+    <source_block_id>blocks_throttle_0</source_block_id>
+    <sink_block_id>wxgui_fftsink2_0</sink_block_id>
+    <source_key>0</source_key>
+    <sink_key>0</sink_key>
+  </connection>
+</flow_graph>
diff --git a/fpga/usrp3/lib/sim/rfnoc/moving_sum/build_moving_sum_tb b/fpga/usrp3/lib/sim/rfnoc/moving_sum/build_moving_sum_tb
new file mode 100755
index 000000000..f7fd1e9c7
--- /dev/null
+++ b/fpga/usrp3/lib/sim/rfnoc/moving_sum/build_moving_sum_tb
@@ -0,0 +1 @@
+iverilog -o moving_sum_tb -y . -y ../control/ -y ../fifo/ moving_sum_tb.v -y /opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/unisims/ -Wall
diff --git a/fpga/usrp3/lib/sim/rfnoc/moving_sum/moving_sum_tb.v b/fpga/usrp3/lib/sim/rfnoc/moving_sum/moving_sum_tb.v
new file mode 100644
index 000000000..4ce455af5
--- /dev/null
+++ b/fpga/usrp3/lib/sim/rfnoc/moving_sum/moving_sum_tb.v
@@ -0,0 +1,43 @@
+//
+// Copyright 2012-2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+module moving_sum_tb();
+   
+   //xlnx_glbl glbl (.GSR(),.GTS());
+   
+   localparam STR_SINK_FIFOSIZE = 9;
+      
+   reg clk, reset;
+   always
+     #100 clk = ~clk;
+
+   initial clk = 0;
+   initial reset = 1;
+   initial #1000 reset = 0;
+   
+   initial $dumpfile("moving_sum_tb.vcd");
+   initial $dumpvars(0,moving_sum_tb);
+
+   initial #1000000 $finish;
+
+   wire [15:0] i_tdata;
+   wire [25:0] o_tdata;
+   wire        i_tvalid, i_tready, o_tvalid, o_tready;
+   
+   moving_sum #(.MAX_LEN_LOG2(10), .WIDTH(16)) moving_sum
+     (.clk(clk), .reset(reset), .clear(0),
+      .len(20),
+      .i_tdata(i_tdata), .i_tlast(), .i_tvalid(i_tvalid), .i_tready(i_tready),
+      .o_tdata(o_tdata), .o_tlast(), .o_tvalid(o_tvalid), .o_tready(o_tready));
+
+   assign i_tdata = 1;
+   assign i_tvalid = 1;
+   assign o_tready = 1;
+   
+      
+endmodule // moving_sum_tb
diff --git a/fpga/usrp3/lib/sim/rfnoc/mult/mult_tb.v b/fpga/usrp3/lib/sim/rfnoc/mult/mult_tb.v
new file mode 100644
index 000000000..32b0d47fd
--- /dev/null
+++ b/fpga/usrp3/lib/sim/rfnoc/mult/mult_tb.v
@@ -0,0 +1,75 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+module mult_tb();
+   
+   xlnx_glbl glbl (.GSR(),.GTS());
+   
+   localparam STR_SINK_FIFOSIZE = 9;
+      
+   reg clk, reset;
+   always
+     #100 clk = ~clk;
+
+   initial clk = 0;
+   initial reset = 1;
+   initial #1000 reset = 0;
+   
+   initial $dumpfile("mult_tb.vcd");
+   initial $dumpvars(0,mult_tb);
+
+   initial #1000000 $finish;
+
+   localparam AW=25;
+   localparam BW=18;
+   localparam PW=48;
+   
+   wire [AW-1:0] a_tdata;
+   wire [BW-1:0] b_tdata;
+   wire [PW-1:0] p_tdata;
+   
+   wire 	 a_tlast, a_tvalid, a_tready, b_tlast, b_tvalid, b_tready;
+   wire 	 p_tlast, p_tvalid;
+   reg 		 p_tready = 0;
+
+   reg 		 ai_tvalid = 0;
+   reg 		 bi_tvalid = 0;
+   
+   counter #(.WIDTH(AW)) ca
+     (.clk(clk), .reset(reset), .clear(0),
+      .max(20),
+      .i_tlast(0), .i_tvalid(ai_tvalid), .i_tready(),
+      .o_tdata(a_tdata), .o_tlast(a_tlast), .o_tvalid(a_tvalid), .o_tready(a_tready));
+   
+   counter #(.WIDTH(BW)) cb
+     (.clk(clk), .reset(reset), .clear(0),
+      .max(20),
+      .i_tlast(0), .i_tvalid(bi_tvalid), .i_tready(),
+      .o_tdata(b_tdata), .o_tlast(b_tlast), .o_tvalid(b_tvalid), .o_tready(b_tready));
+   
+   mult #(.WIDTH_A(AW), .WIDTH_B(BW), .WIDTH_P(PW), .LATENCY(4)) mult
+     (.clk(clk), .reset(reset),
+      .a_tdata(a_tdata), .a_tlast(a_tlast), .a_tvalid(a_tvalid), .a_tready(a_tready),
+      .b_tdata(b_tdata), .b_tlast(b_tlast), .b_tvalid(b_tvalid), .b_tready(b_tready),
+      .p_tdata(p_tdata), .p_tlast(p_tlast), .p_tvalid(p_tvalid), .p_tready(p_tready));
+
+   initial
+     begin
+	@(negedge reset);
+	repeat (100)
+	  @(posedge clk);
+	ai_tvalid <= 1;
+	repeat (10)
+	  @(posedge clk);
+	bi_tvalid <= 1;
+	repeat (10)
+	  @(posedge clk);
+	p_tready <= 1;
+     end
+      
+endmodule // mult_tb
diff --git a/fpga/usrp3/lib/sim/rfnoc/mult_add/mult_add_tb.v b/fpga/usrp3/lib/sim/rfnoc/mult_add/mult_add_tb.v
new file mode 100644
index 000000000..23e772aba
--- /dev/null
+++ b/fpga/usrp3/lib/sim/rfnoc/mult_add/mult_add_tb.v
@@ -0,0 +1,90 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+module mult_add_tb();
+   
+   xlnx_glbl glbl (.GSR(),.GTS());
+   
+   localparam STR_SINK_FIFOSIZE = 9;
+      
+   reg clk, reset;
+   always
+     #100 clk = ~clk;
+
+   initial clk = 0;
+   initial reset = 1;
+   initial #1000 reset = 0;
+   
+   initial $dumpfile("mult_add_tb.vcd");
+   initial $dumpvars(0,mult_add_tb);
+
+   initial #1000000 $finish;
+
+   localparam AW=25;
+   localparam BW=18;
+   localparam PW=48;
+   
+   wire [AW-1:0] a_tdata;
+   wire [BW-1:0] b_tdata;
+   wire [PW-1:0] pin_tdata;
+   wire [PW-1:0] pout_tdata;
+   
+   wire 	 a_tlast, a_tvalid, a_tready, b_tlast, b_tvalid, b_tready;
+   wire 	 pin_tlast, pin_tvalid;
+   wire 	 pout_tlast, pout_tvalid;
+   wire 	 pin_tready;
+   reg 		 pout_tready = 0;
+
+   reg 		 ai_tvalid = 0;
+   reg 		 bi_tvalid = 0;
+   reg 		 pi_tvalid = 0;
+   
+   counter #(.WIDTH(AW)) ca
+     (.clk(clk), .reset(reset), .clear(0),
+      .max(25'd20),
+      .i_tlast(0), .i_tvalid(ai_tvalid), .i_tready(),
+      .o_tdata(a_tdata), .o_tlast(a_tlast), .o_tvalid(a_tvalid), .o_tready(a_tready));
+   
+   counter #(.WIDTH(BW)) cb
+     (.clk(clk), .reset(reset), .clear(0),
+      .max(18'd20),
+      .i_tlast(0), .i_tvalid(bi_tvalid), .i_tready(),
+      .o_tdata(b_tdata), .o_tlast(b_tlast), .o_tvalid(b_tvalid), .o_tready(b_tready));
+   
+   counter #(.WIDTH(PW)) cp
+     (.clk(clk), .reset(reset), .clear(0),
+      .max(48'd20),
+      .i_tlast(0), .i_tvalid(pi_tvalid), .i_tready(),
+      .o_tdata(pin_tdata), .o_tlast(pin_tlast), .o_tvalid(pin_tvalid), .o_tready(pin_tready));
+   
+   mult_add #(.WIDTH_A(AW), .WIDTH_B(BW), .WIDTH_P(PW),
+	      .LATENCY(3), .CASCADE_IN(1), .CASCADE_OUT(1)) mult_add
+     (.clk(clk), .reset(reset),
+      .a_tdata(a_tdata), .a_tlast(a_tlast), .a_tvalid(a_tvalid), .a_tready(a_tready),
+      .b_tdata(b_tdata), .b_tlast(b_tlast), .b_tvalid(b_tvalid), .b_tready(b_tready),
+      .c_tdata(pin_tdata), .c_tlast(pin_tlast), .c_tvalid(pin_tvalid), .c_tready(pin_tready),
+      .p_tdata(pout_tdata), .p_tlast(pout_tlast), .p_tvalid(pout_tvalid), .p_tready(pout_tready));
+
+   initial
+     begin
+	@(negedge reset);
+	repeat (100)
+	  @(posedge clk);
+	ai_tvalid <= 1;
+	repeat (10)
+	  @(posedge clk);
+	bi_tvalid <= 1;
+	repeat (10)
+	  @(posedge clk);
+	pi_tvalid <= 1;
+	repeat (10)
+	  @(posedge clk);
+	pout_tready <= 1;
+     end
+      
+endmodule // mult_add_tb
diff --git a/fpga/usrp3/lib/sim/rfnoc/null_source/null_source_tb.v b/fpga/usrp3/lib/sim/rfnoc/null_source/null_source_tb.v
new file mode 100644
index 000000000..c9cf29111
--- /dev/null
+++ b/fpga/usrp3/lib/sim/rfnoc/null_source/null_source_tb.v
@@ -0,0 +1,80 @@
+//
+// Copyright 2012-2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+module null_source_tb();
+   
+   reg clk, reset;
+   always
+     #100 clk = ~clk;
+
+   initial clk = 0;
+   initial reset = 1;
+   initial #1000 reset = 0;
+   
+   initial $dumpfile("null_source_tb.vcd");
+   initial $dumpvars(0,null_source_tb);
+
+   //initial #10000000 $finish;
+
+   reg [31:0] set_data;
+   reg [7:0]  set_addr;
+   reg        set_stb=0;
+
+   wire [63:0] src_tdata;
+   wire	       src_tlast, src_tvalid;
+   wire        src_tready;
+
+   assign src_tready = 1'b1;
+   
+   localparam PORTS = 4;
+
+   null_source #(.BASE(0)) axi_wrapper_ce1
+     (.clk(clk), .reset(reset),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .o_tdata(src_tdata), .o_tlast(src_tlast), .o_tvalid(src_tvalid), .o_tready(src_tready)     );
+
+   initial
+     begin
+
+	@(negedge reset);
+	@(posedge clk);
+	#100000;
+	@(posedge clk);
+	set_stb <= 1;
+	set_addr <= 0;
+	set_data <= 32'hDEADBEEF;
+	@(posedge clk);
+	set_stb <= 1;
+	set_addr <= 1;  // Len
+	set_data <= 32'h8;
+	@(posedge clk);
+	set_stb <= 1;
+	set_addr <= 2;
+	set_data <= 32'h20; // Rate
+	@(posedge clk);
+	set_stb <= 1;
+	set_addr <= 3;
+	set_data <= 1;     // enable
+	@(posedge clk);
+	set_stb <= 0;
+	@(posedge clk);
+	#1000000;
+	@(posedge clk);
+	set_stb <= 1;
+	set_addr <= 3;
+	set_data <= 0;     // disable
+	@(posedge clk);
+	set_stb <= 0;
+	#1000000;
+
+	$finish;
+	
+	
+     end
+
+endmodule // null_source_tb
diff --git a/fpga/usrp3/lib/sim/rfnoc/window/build_window_tb b/fpga/usrp3/lib/sim/rfnoc/window/build_window_tb
new file mode 100755
index 000000000..1af299fd4
--- /dev/null
+++ b/fpga/usrp3/lib/sim/rfnoc/window/build_window_tb
@@ -0,0 +1 @@
+iverilog -o window_tb window_tb.v -y ../coregen -y ../../../usrp2/models -y . -y ../control/ -y ../fifo/ -y /opt/Xilinx/14.6/ISE_DS/ISE/verilog/src/unisims/ -y ../packet_proc/ -y ../timing/ -y ../vita/
diff --git a/fpga/usrp3/lib/sim/rfnoc/window/window_tb.v b/fpga/usrp3/lib/sim/rfnoc/window/window_tb.v
new file mode 100644
index 000000000..2449057c8
--- /dev/null
+++ b/fpga/usrp3/lib/sim/rfnoc/window/window_tb.v
@@ -0,0 +1,341 @@
+`timescale 1ns/1ps
+
+//
+// Copyright 2012-2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+module window_tb();
+   xlnx_glbl glbl (.GSR(),.GTS());
+
+   localparam STR_SINK_FIFOSIZE = 11;
+  
+   reg clk, reset;
+ 
+   localparam PORTS = 5;
+
+   wire [63:0] noci_tdata[PORTS-1:0];
+   wire [PORTS-1:0]       noci_tlast;
+   wire [PORTS-1:0]       noci_tvalid;
+   wire [PORTS-1:0]       noci_tready;
+
+   wire [63:0] noco_tdata[PORTS-1:0];
+   wire [PORTS-1:0]       noco_tlast;
+   wire [PORTS-1:0]       noco_tvalid;
+   wire [PORTS-1:0]       noco_tready;
+   
+   wire [63:0] src_tdata;
+   wire	       src_tlast, src_tvalid;
+   wire        src_tready;
+
+   reg [63:0]  cmdout_tdata;
+   reg 	       cmdout_tlast, cmdout_tvalid;
+   wire        cmdout_tready;
+
+   wire [63:0] dst_tdata;
+   wire        dst_tlast, dst_tvalid;
+   wire        dst_tready = 1;
+ 	       
+   reg 	       set_stb_xbar;
+   reg [15:0]  set_addr_xbar;
+   reg [31:0]  set_data_xbar;
+
+   always
+     #100 clk = ~clk;
+
+   initial clk = 0;
+   initial reset = 1;
+   initial #1000 reset = 0;
+   
+   initial $dumpfile("window_tb.vcd");
+   initial $dumpvars(0,window_tb);
+
+   initial #3000000 $finish;
+
+
+   axi_crossbar #(.FIFO_WIDTH(64), .DST_WIDTH(16), .NUM_INPUTS(PORTS), .NUM_OUTPUTS(PORTS)) crossbar
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .local_addr(8'd0),
+      .pkt_present({noci_tvalid[4],noci_tvalid[3],noci_tvalid[2],noci_tvalid[1],noci_tvalid[0]}),
+      
+      .i_tdata({noci_tdata[4],noci_tdata[3],noci_tdata[2],noci_tdata[1],noci_tdata[0]}),
+      .i_tlast({noci_tlast[4],noci_tlast[3],noci_tlast[2],noci_tlast[1],noci_tlast[0]}),
+      .i_tvalid({noci_tvalid[4],noci_tvalid[3],noci_tvalid[2],noci_tvalid[1],noci_tvalid[0]}),
+      .i_tready({noci_tready[4],noci_tready[3],noci_tready[2],noci_tready[1],noci_tready[0]}),
+
+      .o_tdata({noco_tdata[4],noco_tdata[3],noco_tdata[2],noco_tdata[1],noco_tdata[0]}),
+      .o_tlast({noco_tlast[4],noco_tlast[3],noco_tlast[2],noco_tlast[1],noco_tlast[0]}),
+      .o_tvalid({noco_tvalid[4],noco_tvalid[3],noco_tvalid[2],noco_tvalid[1],noco_tvalid[0]}),
+      .o_tready({noco_tready[4],noco_tready[3],noco_tready[2],noco_tready[1],noco_tready[0]}),
+
+      .set_stb(set_stb_xbar), .set_addr(set_addr_xbar), .set_data(set_data_xbar),
+      .rb_rd_stb(1'b0), .rb_addr(4'd0), .rb_data());
+   
+   // Generator on port 0
+   wire        set_stb_0;
+   wire [7:0]  set_addr_0;
+   wire [31:0] set_data_0;
+   
+   noc_shell #(.STR_SINK_FIFOSIZE(STR_SINK_FIFOSIZE)) noc_shell_0
+     (.bus_clk(clk), .bus_rst(reset),
+      .i_tdata(noco_tdata[0]), .i_tlast(noco_tlast[0]), .i_tvalid(noco_tvalid[0]), .i_tready(noco_tready[0]),
+      .o_tdata(noci_tdata[0]), .o_tlast(noci_tlast[0]), .o_tvalid(noci_tvalid[0]), .o_tready(noci_tready[0]),
+      .clk(clk), .reset(reset),
+      .set_data(set_data_0), .set_addr(set_addr_0), .set_stb(set_stb_0), .rb_data(64'd0),
+
+      .cmdout_tdata(64'h0), .cmdout_tlast(1'b0), .cmdout_tvalid(1'b0), .cmdout_tready(),
+      .ackin_tdata(), .ackin_tlast(), .ackin_tvalid(), .ackin_tready(1'b1),
+      
+      .str_sink_tdata(), .str_sink_tlast(), .str_sink_tvalid(), .str_sink_tready(1'b1), // unused port
+      .str_src_tdata(src_tdata), .str_src_tlast(src_tlast), .str_src_tvalid(src_tvalid), .str_src_tready(src_tready)
+      );
+
+   file_source #(.BASE(8), .FILENAME("test.dat")) file_source
+     (.clk(clk), .reset(reset),
+      .set_data(set_data_0), .set_addr(set_addr_0), .set_stb(set_stb_0),
+      .o_tdata(src_tdata), .o_tlast(src_tlast), .o_tvalid(src_tvalid), .o_tready(src_tready));
+      
+   // Simple FIR on port 1
+   wire [31:0] set_data_1;
+   wire [7:0]  set_addr_1;
+   wire        set_stb_1;
+   wire [63:0] s1o_tdata, s1i_tdata;
+   wire        s1o_tlast, s1i_tlast, s1o_tvalid, s1i_tvalid, s1o_tready, s1i_tready;
+
+   wire [31:0] pre_tdata, post_tdata;
+   wire        pre_tlast, pre_tvalid, pre_tready;
+   wire        post_tlast, post_tvalid, post_tready;
+
+   wire [15:0] pre_i = pre_tdata[31:16];
+   wire [15:0] pre_q = pre_tdata[15:0];
+   wire [15:0] post_i = post_tdata[31:16];
+   wire [15:0] post_q = post_tdata[15:0];
+   
+   noc_shell #(.STR_SINK_FIFOSIZE(STR_SINK_FIFOSIZE)) noc_shell_1
+     (.bus_clk(clk), .bus_rst(reset),
+      .i_tdata(noco_tdata[1]), .i_tlast(noco_tlast[1]), .i_tvalid(noco_tvalid[1]), .i_tready(noco_tready[1]),
+      .o_tdata(noci_tdata[1]), .o_tlast(noci_tlast[1]), .o_tvalid(noci_tvalid[1]), .o_tready(noci_tready[1]),
+      .clk(clk), .reset(reset),
+      .set_data(set_data_1), .set_addr(set_addr_1), .set_stb(set_stb_1), .rb_data(64'd0),
+
+      .cmdout_tdata(64'h0), .cmdout_tlast(1'b0), .cmdout_tvalid(1'b0), .cmdout_tready(),
+      .ackin_tdata(), .ackin_tlast(), .ackin_tvalid(), .ackin_tready(1'b1),
+      
+      .str_sink_tdata(s1o_tdata), .str_sink_tlast(s1o_tlast), .str_sink_tvalid(s1o_tvalid), .str_sink_tready(s1o_tready),
+      .str_src_tdata(s1i_tdata), .str_src_tlast(s1i_tlast), .str_src_tvalid(s1i_tvalid), .str_src_tready(s1i_tready)
+      );
+
+   wire [31:0] axis_config_tdata1;
+   wire        axis_config_tvalid1, axis_config_tready1, axis_config_tlast1;
+   
+   axi_wrapper #(.BASE(8)) axi_wrapper_ce1
+     (.clk(clk), .reset(reset),
+      .set_stb(set_stb_1), .set_addr(set_addr_1), .set_data(set_data_1),
+      .i_tdata(s1o_tdata), .i_tlast(s1o_tlast), .i_tvalid(s1o_tvalid), .i_tready(s1o_tready),
+      .o_tdata(s1i_tdata), .o_tlast(s1i_tlast), .o_tvalid(s1i_tvalid), .o_tready(s1i_tready),
+      .m_axis_data_tdata(pre_tdata),
+      .m_axis_data_tlast(pre_tlast),
+      .m_axis_data_tvalid(pre_tvalid),
+      .m_axis_data_tready(pre_tready),
+      .s_axis_data_tdata(post_tdata),
+      .s_axis_data_tlast(post_tlast),
+      .s_axis_data_tvalid(post_tvalid),
+      .s_axis_data_tready(post_tready),
+      .m_axis_config_tdata(axis_config_tdata1),
+      .m_axis_config_tlast(axis_config_tlast1),
+      .m_axis_config_tvalid(axis_config_tvalid1),
+      .m_axis_config_tready(axis_config_tready1)
+      );
+
+   window #(.BASE(0)) window
+     (.clk(clk), .reset(reset), .clear(clear),
+      .set_stb(set_stb_1), .set_addr(set_addr_1), .set_data(set_data_1),
+      .i_tdata(pre_tdata), .i_tlast(pre_tlast), .i_tvalid(pre_tvalid), .i_tready(pre_tready),
+      .o_tdata(post_tdata), .o_tlast(post_tlast), .o_tvalid(post_tvalid), .o_tready(post_tready));
+
+   assign axis_config_tready1 = 1'b1;
+   
+   // Dumper on port 2
+   noc_shell #(.STR_SINK_FIFOSIZE(STR_SINK_FIFOSIZE)) noc_shell_2
+     (.bus_clk(clk), .bus_rst(reset),
+      .i_tdata(noco_tdata[2]), .i_tlast(noco_tlast[2]), .i_tvalid(noco_tvalid[2]), .i_tready(noco_tready[2]),
+      .o_tdata(noci_tdata[2]), .o_tlast(noci_tlast[2]), .o_tvalid(noci_tvalid[2]), .o_tready(noci_tready[2]),
+      
+      .clk(clk), .reset(reset),
+      .set_data(), .set_addr(), .set_stb(), .rb_data(64'd0),
+
+      .cmdout_tdata(64'h0), .cmdout_tlast(1'b0), .cmdout_tvalid(1'b0), .cmdout_tready(),
+      .ackin_tdata(), .ackin_tlast(), .ackin_tvalid(), .ackin_tready(1'b1),
+      
+      .str_sink_tdata(dst_tdata), .str_sink_tlast(dst_tlast), .str_sink_tvalid(dst_tvalid), .str_sink_tready(dst_tready),
+      .str_src_tdata(64'd0), .str_src_tlast(1'd0), .str_src_tvalid(1'b0), .str_src_tready() // unused port
+      );
+
+   // Control Source on port 3
+   noc_shell #(.STR_SINK_FIFOSIZE(STR_SINK_FIFOSIZE)) noc_shell_3
+     (.bus_clk(clk), .bus_rst(reset),
+      .i_tdata(noco_tdata[3]), .i_tlast(noco_tlast[3]), .i_tvalid(noco_tvalid[3]), .i_tready(noco_tready[3]),
+      .o_tdata(noci_tdata[3]), .o_tlast(noci_tlast[3]), .o_tvalid(noci_tvalid[3]), .o_tready(noci_tready[3]),
+      
+      .clk(clk), .reset(reset),
+      .set_data(), .set_addr(), .set_stb(), .rb_data(64'd0),
+
+      .cmdout_tdata(cmdout_tdata), .cmdout_tlast(cmdout_tlast), .cmdout_tvalid(cmdout_tvalid), .cmdout_tready(cmdout_tready),
+      .ackin_tdata(), .ackin_tlast(), .ackin_tvalid(), .ackin_tready(1'b1),
+      
+      .str_sink_tdata(), .str_sink_tlast(), .str_sink_tvalid(), .str_sink_tready(1'b1), // unused port
+      .str_src_tdata(64'd0), .str_src_tlast(1'd0), .str_src_tvalid(1'b0), .str_src_tready() // unused port
+      );
+
+   // ////////////////////////////////////////////////////////////////////////////////////
+   
+   task SetXbar;
+      input [15:0] start_reg;
+      input [7:0]  start_val;
+      
+      begin
+	 repeat (PORTS)
+	   begin
+	      repeat (1)
+		begin
+		   SetXbar_reg(start_reg,start_val);
+		   start_reg <= start_reg + 1;
+		   @(posedge clk);
+		end
+	      start_val <= start_val + 1;
+	      @(posedge clk);
+	   end
+      end
+   endtask // SetXbar
+   
+   task SetXbar_reg;
+      input [15:0] addr;
+      input [31:0] data;
+      begin
+	 @(posedge clk);
+	 set_stb_xbar <= 1'b1;
+	 set_addr_xbar <= addr;
+	 set_data_xbar <= data;
+	 @(posedge clk);
+	 set_stb_xbar <= 1'b0;
+	 @(posedge clk);
+      end
+   endtask // set_xbar
+
+   task SendCtrlPacket;
+      input [11:0] seqnum;
+      input [31:0] sid;
+      input [63:0] data;
+      
+      begin
+	 @(posedge clk);
+	 cmdout_tdata <= { 4'h8, seqnum, 16'h16, sid };
+	 cmdout_tlast <= 0;
+	 cmdout_tvalid <= 1;
+	 while(~cmdout_tready) #1;
+	 
+	 @(posedge clk);
+	 cmdout_tdata <= data;
+	 cmdout_tlast <= 1;
+	 while(~cmdout_tready) #1;
+	 
+	 @(posedge clk);
+	 cmdout_tvalid <= 0;
+	 @(posedge clk);
+      end
+   endtask // SendCtrlPacket
+
+   initial
+     begin
+	cmdout_tdata <= 64'd0;
+	cmdout_tlast <= 1'b0;
+	cmdout_tvalid <= 1'b0;
+	
+	@(negedge reset);
+	@(posedge clk);
+	SetXbar(256,0);
+	
+	@(posedge clk);
+	// Port 0
+	SendCtrlPacket(12'd0, 32'h0003_0000, {32'h0, 32'h0000_0003}); // Command packet to set up source control window size
+	SendCtrlPacket(12'd0, 32'h0003_0000, {32'h1, 32'h0000_0001}); // Command packet to set up source control window enable
+	SendCtrlPacket(12'd0, 32'h0003_0000, {32'h3, 32'h8000_0001}); // Command packet to set up flow control
+	SendCtrlPacket(12'd0, 32'h0003_0000, {32'h8, 32'h0000_0001}); // Command packet to set up SID
+	SendCtrlPacket(12'd0, 32'h0003_0000, {32'hA, 32'h0000_0002}); // Command packet to set up Rate
+	SendCtrlPacket(12'd0, 32'h0003_0000, {32'hB, 32'h0000_0001}); // Command packet to set up send_time_field
+	SendCtrlPacket(12'd0, 32'h0003_0000, {32'h9, 32'h0000_0200}); // Command packet to set up Len
+	#10000;
+	// Port 1
+	SendCtrlPacket(12'd0, 32'h0003_0001, {32'h0, 32'h0000_0013}); // Command packet to set up source control window size
+	SendCtrlPacket(12'd0, 32'h0003_0001, {32'h1, 32'h0000_0001}); // Command packet to set up source control window enable
+	SendCtrlPacket(12'd0, 32'h0003_0001, {32'h3, 32'h8000_0001}); // Command packet to set up flow control
+	SendCtrlPacket(12'd0, 32'h0003_0001, {32'h8, 32'h0001_0002}); // Rewrite SID, send on to port 2
+
+
+	#10000;
+	// Port 2
+	SendCtrlPacket(12'd0, 32'h0003_0002, {32'h0, 32'h0000_0003}); // Command packet to set up source control window size
+	SendCtrlPacket(12'd0, 32'h0003_0002, {32'h1, 32'h0000_0001}); // Command packet to set up source control window enable
+	SendCtrlPacket(12'd0, 32'h0003_0002, {32'h3, 32'h8000_0001}); // Command packet to set up flow control
+
+	#1000000;
+	// WINDOW filter
+	SendCtrlPacket(12'd0, 32'h0003_0001, {32'h10, 32'd0});  // frame_len  (FFTsize)
+	SendCtrlPacket(12'd0, 32'h0003_0001, {32'h10, 32'd1});  // frame_len  (FFTsize)
+	SendCtrlPacket(12'd0, 32'h0003_0001, {32'h10, 32'd2});  // frame_len  (FFTsize)
+	SendCtrlPacket(12'd0, 32'h0003_0001, {32'h10, 32'd3});  // frame_len  (FFTsize)
+	SendCtrlPacket(12'd0, 32'h0003_0001, {32'h10, 32'd4});  // frame_len  (FFTsize)
+	SendCtrlPacket(12'd0, 32'h0003_0001, {32'h10, 32'd5});  // frame_len  (FFTsize)
+	SendCtrlPacket(12'd0, 32'h0003_0001, {32'h10, 32'd6});  // frame_len  (FFTsize)
+	SendCtrlPacket(12'd0, 32'h0003_0001, {32'h10, 32'd7});  // frame_len  (FFTsize)
+	SendCtrlPacket(12'd0, 32'h0003_0001, {32'h11, 32'd8});  // frame_len  (FFTsize)
+
+	#1000000;
+	SendCtrlPacket(12'd0, 32'h0003_0001, {32'h10, 32'd100000});  // frame_len  (FFTsize)
+	SendCtrlPacket(12'd0, 32'h0003_0001, {32'h10, 32'd100000});  // frame_len  (FFTsize)
+	SendCtrlPacket(12'd0, 32'h0003_0001, {32'h10, 32'd100000});  // frame_len  (FFTsize)
+	SendCtrlPacket(12'd0, 32'h0003_0001, {32'h10, 32'd100000});  // frame_len  (FFTsize)
+	SendCtrlPacket(12'd0, 32'h0003_0001, {32'h10, 32'd100000});  // frame_len  (FFTsize)
+	SendCtrlPacket(12'd0, 32'h0003_0001, {32'h10, 32'd100000});  // frame_len  (FFTsize)
+	SendCtrlPacket(12'd0, 32'h0003_0001, {32'h10, 32'd100000});  // frame_len  (FFTsize)
+	SendCtrlPacket(12'd0, 32'h0003_0001, {32'h10, 32'd100000});  // frame_len  (FFTsize)
+	SendCtrlPacket(12'd0, 32'h0003_0001, {32'h11, 32'd100000});  // frame_len  (FFTsize)
+
+     end
+
+   reg in_packet = 0;
+
+   integer outfile;
+   
+   initial
+     begin
+	outfile = $fopen("output.dat","wb");
+	//src_tready <= 1'b1;
+     end
+
+   wire signed  [15:0] a,b,c,d;
+   assign a = src_tdata[63:48];
+   assign b = src_tdata[47:32];
+   assign c = src_tdata[31:16];
+   assign d = src_tdata[15:0];
+
+   always @(posedge clk)
+     if(src_tready & src_tvalid)
+       begin
+	  if(src_tlast)
+	    in_packet <= 0;
+	  else
+	    in_packet <= 1;
+	  if(in_packet)
+	    begin
+	       //$fwrite(outfile,"%u",{q_out[15:0],i_out[15:0]}); // Correct endianness for GR
+	       //$write("%d,%d,%d,%d,",a,b,c,d);
+	       $fwrite(outfile,"%u",{dst_tdata[47:32],dst_tdata[63:48]});
+	       $fwrite(outfile,"%u",{dst_tdata[15:0],dst_tdata[31:16]});
+	    end
+       end
+
+endmodule // window_tb
diff --git a/fpga/usrp3/lib/sim/simple_gemac/ll8_to_axi64/ll8_to_axi64_tb.v b/fpga/usrp3/lib/sim/simple_gemac/ll8_to_axi64/ll8_to_axi64_tb.v
new file mode 100644
index 000000000..ef10a7c9a
--- /dev/null
+++ b/fpga/usrp3/lib/sim/simple_gemac/ll8_to_axi64/ll8_to_axi64_tb.v
@@ -0,0 +1,100 @@
+//
+// Copyright 2016 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+`timescale 1ns/1ps
+
+module ll8_to_axi64_tb();
+
+   reg clk    = 0;
+   reg reset  = 1;
+   
+   always #10 clk = ~clk;
+   
+   initial $dumpfile("ll8_to_axi64_tb.vcd");
+   initial $dumpvars(0,ll8_to_axi64_tb);
+
+   initial
+     begin
+	#1000 reset = 0;
+	#2000000;
+	$finish;
+     end
+   
+   wire [63:0]  tdata, tdata_int;
+   wire [3:0] 	tuser, tuser_int;
+   wire 	tlast, tlast_int;
+   wire		tvalid, tvalid_int, tready, tready_int;
+
+   reg [7:0] 	ll_data;
+   reg 		ll_eof, ll_error, ll_src_rdy;
+   wire 	ll_dst_rdy;
+
+   wire [7:0] 	ll_data2;
+   wire 	ll_eof2, ll_src_rdy2, ll_dst_rdy2;
+   
+   localparam RPT_COUNT = 12;
+   
+   initial
+     begin
+	ll_src_rdy <= 0;
+ 
+	while(reset)
+	  @(posedge clk);
+
+	@(posedge clk);
+	
+	{ll_error, ll_eof, ll_data} <= { 1'b0, 1'b0, 8'hA0 };
+	repeat(RPT_COUNT-1)
+	  begin
+	     ll_src_rdy <= 1;
+	     @(posedge clk);
+	     ll_data <= ll_data + 1;
+	  end
+	ll_eof <= 1;
+	ll_data <= ll_data + 1;
+	@(posedge clk);
+
+	{ll_error, ll_eof, ll_data} <= { 1'b0, 1'b0, 8'hC0 };
+	repeat(RPT_COUNT-1)
+	  begin
+	     ll_src_rdy <= 1;
+	     @(posedge clk);
+	     ll_data <= ll_data + 1;
+	  end
+	ll_eof <= 1; ll_error <= 1;
+	ll_data <= ll_data + 1;
+	@(posedge clk);
+	ll_src_rdy <= 1'b0;
+
+     end
+
+   ll8_to_axi64 #(.START_BYTE(6), .LABEL(8'h89)) ll8_to_axi64
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .ll_data(ll_data), .ll_eof(ll_eof), .ll_error(ll_error), .ll_src_rdy(ll_src_rdy), .ll_dst_rdy(ll_dst_rdy),
+      .axi64_tdata(tdata), .axi64_tlast(tlast), .axi64_tuser(tuser), .axi64_tvalid(tvalid), .axi64_tready(tready) );
+   
+   axi_fifo_short #(.WIDTH(69)) axi_fifo_short
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata({tlast,tuser,tdata}), .i_tvalid(tvalid), .i_tready(tready),
+      .o_tdata({tlast_int,tuser_int,tdata_int}), .o_tvalid(tvalid_int), .o_tready(tready_int));
+
+   axi64_to_ll8 #(.START_BYTE(6)) axi64_to_ll8
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .axi64_tdata(tdata_int), .axi64_tlast(tlast_int), .axi64_tuser(tuser_int), .axi64_tvalid(tvalid_int), .axi64_tready(tready_int),
+      .ll_data(ll_data2), .ll_eof(ll_eof2), .ll_src_rdy(ll_src_rdy2), .ll_dst_rdy(ll_dst_rdy2) );
+
+   /*
+   always @(posedge clk)
+     if(ll_src_rdy2 & ll_dst_rdy2)
+       $display("EOF %x\tDATA %x",ll_eof2, ll_data2);
+
+   */
+   assign ll_dst_rdy2 = 1;
+   
+   always @(posedge clk)
+     if(tvalid_int & tready_int)
+       $display("TERR %x\tTUSER %x\tTLAST %x\tTDATA %x",tuser_int[3],tuser_int[2:0], tlast_int, tdata_int);
+   
+endmodule // ll8_to_axi64_tb
diff --git a/fpga/usrp3/lib/sim/simple_gemac/simple_gemac_tb.v b/fpga/usrp3/lib/sim/simple_gemac/simple_gemac_tb.v
new file mode 100644
index 000000000..c65db6c98
--- /dev/null
+++ b/fpga/usrp3/lib/sim/simple_gemac/simple_gemac_tb.v
@@ -0,0 +1,208 @@
+//
+// Copyright 2011 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+
+
+module simple_gemac_tb;
+`include "eth_tasks.v"
+     
+   reg clk = 0;
+   reg reset = 1;
+
+   initial #1000 reset = 0;
+   always #50 clk = ~clk;
+
+   wire GMII_RX_DV, GMII_RX_ER, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK;
+   wire [7:0] GMII_RXD, GMII_TXD;
+
+   wire rx_valid, rx_error, rx_ack;
+   wire tx_ack, tx_valid, tx_error;
+   
+   wire [7:0] rx_data, tx_data;
+   
+   reg [15:0] pause_time;
+   reg pause_req      = 0;
+
+   wire GMII_RX_CLK   = GMII_GTX_CLK;
+
+   reg [7:0] FORCE_DAT_ERR = 0;
+   reg FORCE_ERR = 0;
+   
+   // Loopback
+   assign GMII_RX_DV  = GMII_TX_EN;
+   assign GMII_RX_ER  = GMII_TX_ER | FORCE_ERR;
+   assign GMII_RXD    = GMII_TXD ^ FORCE_DAT_ERR;
+
+   wire [47:0] ucast_addr = 48'hF1F2_F3F4_F5F6;
+   wire [47:0] mcast_addr = 0;
+   wire        pass_ucast  =1, pass_mcast=0, pass_bcast=1, pass_pause=0, pass_all=0;
+   
+   simple_gemac simple_gemac
+     (.clk125(clk),  .reset(reset),
+      .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),  
+      .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
+      .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),  
+      .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
+      .pause_req(pause_req), .pause_time(pause_time), .pause_en(1),
+      .ucast_addr(ucast_addr), .mcast_addr(mcast_addr),
+      .pass_ucast(pass_ucast), .pass_mcast(pass_mcast), .pass_bcast(pass_bcast), 
+      .pass_pause(pass_pause), .pass_all(pass_all),
+      .rx_clk(rx_clk), .rx_data(rx_data),
+      .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack),
+      .tx_clk(tx_clk), .tx_data(tx_data), 
+      .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack)
+      );
+
+   wire rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy;
+   wire rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2;
+   reg rx_ll_dst_rdy2 = 1;
+   wire [7:0] rx_ll_data, rx_ll_data2;
+   wire rx_ll_error, rx_ll_error2;
+   
+   rxmac_to_ll8 rx_adapt
+     (.clk(clk), .reset(reset), .clear(0),
+      .rx_data(rx_data), .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack),
+      .ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof), .ll_error(rx_ll_error),
+      .ll_src_rdy(rx_ll_src_rdy), .ll_dst_rdy(rx_ll_dst_rdy));
+
+   ll8_shortfifo rx_sfifo
+     (.clk(clk), .reset(reset), .clear(0),
+      .datain(rx_ll_data), .sof_i(rx_ll_sof), .eof_i(rx_ll_eof),
+      .error_i(rx_ll_error), .src_rdy_i(rx_ll_src_rdy), .dst_rdy_o(rx_ll_dst_rdy),
+      .dataout(rx_ll_data2), .sof_o(rx_ll_sof2), .eof_o(rx_ll_eof2),
+      .error_o(rx_ll_error2), .src_rdy_o(rx_ll_src_rdy2), .dst_rdy_i(rx_ll_dst_rdy2));
+
+   wire tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy;
+   reg tx_ll_sof2=0, tx_ll_eof2=0;
+   reg tx_ll_src_rdy2 = 0;
+   wire tx_ll_dst_rdy2;
+   wire [7:0] tx_ll_data;
+   reg [7:0] tx_ll_data2 = 0;
+   wire tx_ll_error;
+   wire tx_ll_error2 = 0;
+
+   ll8_shortfifo tx_sfifo
+     (.clk(clk), .reset(reset), .clear(clear),
+      .datain(tx_ll_data2), .sof_i(tx_ll_sof2), .eof_i(tx_ll_eof2),
+      .error_i(tx_ll_error2), .src_rdy_i(tx_ll_src_rdy2), .dst_rdy_o(tx_ll_dst_rdy2),
+      .dataout(tx_ll_data), .sof_o(tx_ll_sof), .eof_o(tx_ll_eof),
+      .error_o(tx_ll_error), .src_rdy_o(tx_ll_src_rdy), .dst_rdy_i(tx_ll_dst_rdy));
+   
+   ll8_to_txmac ll8_to_txmac
+     (.clk(clk), .reset(reset), .clear(clear),
+      .ll_data(tx_ll_data), .ll_sof(tx_ll_sof), .ll_eof(tx_ll_eof),
+      .ll_src_rdy(tx_ll_src_rdy), .ll_dst_rdy(tx_ll_dst_rdy),
+      .tx_data(tx_data), .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack));
+
+   initial $dumpfile("simple_gemac_tb.vcd");
+   initial $dumpvars(0,simple_gemac_tb);
+
+   integer i; 
+   reg [7:0] pkt_rom[0:65535];
+   reg [1023:0] ROMFile;
+   
+   initial
+     for (i=0;i<65536;i=i+1)
+       pkt_rom[i] <= 8'h0;
+
+   initial
+     begin
+	@(negedge reset);
+	repeat (10)
+	  @(posedge clk);
+	SendFlowCtrl(16'h0007);  // Send flow control
+	@(posedge clk);
+	#30000;
+	@(posedge clk);
+	SendFlowCtrl(16'h0009);  // Increas flow control before it expires
+	#10000;
+	@(posedge clk);
+	SendFlowCtrl(16'h0000);  // Cancel flow control before it expires
+	@(posedge clk); 
+
+	SendPacket_to_ll8(8'hAA,10);    // This packet gets dropped by the filters
+	repeat (10)
+	  @(posedge clk);
+
+ 	SendPacketFromFile_ll8(60,0,0);  // The rest are valid packets
+	repeat (10)
+	  @(posedge clk);
+
+ 	SendPacketFromFile_ll8(61,0,0);
+	repeat (10)
+	  @(posedge clk);
+	SendPacketFromFile_ll8(62,0,0);
+	repeat (10)
+	  @(posedge clk);
+	SendPacketFromFile_ll8(63,0,0);
+	repeat (1)
+	  @(posedge clk);
+	SendPacketFromFile_ll8(64,0,0);
+	repeat (10)
+	  @(posedge clk);
+	SendPacketFromFile_ll8(59,0,0);
+	repeat (1)
+	  @(posedge clk);
+	SendPacketFromFile_ll8(58,0,0);
+	repeat (1)
+	  @(posedge clk);
+	SendPacketFromFile_ll8(100,0,0);
+	repeat (1)
+	  @(posedge clk);
+	SendPacketFromFile_ll8(200,150,30);  // waiting 14 empties the fifo, 15 underruns
+	repeat (1)
+	  @(posedge clk);
+	SendPacketFromFile_ll8(100,0,30);
+	#10000 $finish;
+     end
+
+   // Force a CRC error
+    initial
+     begin
+	#90000;
+	@(posedge clk);
+	FORCE_DAT_ERR <= 8'h10;
+	@(posedge clk);
+	FORCE_DAT_ERR <= 8'h00;
+     end
+
+   // Force an RX_ER error (i.e. link loss)
+   initial
+     begin
+	#116000;
+	@(posedge clk);
+	FORCE_ERR <= 1;
+	@(posedge clk);
+	FORCE_ERR <= 0;
+     end
+
+   // Cause receive fifo to fill, causing an RX overrun
+   initial
+     begin
+	#126000;
+	@(posedge clk);
+	rx_ll_dst_rdy2 <= 0;
+	repeat (30)          // Repeat of 14 fills the shortfifo, but works.  15 overflows
+	  @(posedge clk);
+	rx_ll_dst_rdy2 <= 1;
+     end
+   
+   // Tests: Send and recv flow control, send and receive good packets, RX CRC err, RX_ER, RX overrun, TX underrun
+   // Still need to test: CRC errors on Pause Frames
+   
+   always @(posedge clk)
+     if(rx_ll_src_rdy2 & rx_ll_dst_rdy2)
+       begin
+	  if(rx_ll_sof2 & ~rx_ll_eof2)
+	    $display("RX-PKT-START %d",$time);
+	  $display("RX-PKT SOF %d EOF %d ERR%d DAT %x",rx_ll_sof2,rx_ll_eof2,rx_ll_error2,rx_ll_data2);
+	  if(rx_ll_eof2 & ~rx_ll_sof2)
+	    $display("RX-PKT-END %d",$time);
+       end
+   
+endmodule // simple_gemac_tb
diff --git a/fpga/usrp3/lib/sim/simple_gemac/simple_gemac_wrapper/simple_gemac_wrapper.build b/fpga/usrp3/lib/sim/simple_gemac/simple_gemac_wrapper/simple_gemac_wrapper.build
new file mode 100755
index 000000000..14e8500b3
--- /dev/null
+++ b/fpga/usrp3/lib/sim/simple_gemac/simple_gemac_wrapper/simple_gemac_wrapper.build
@@ -0,0 +1 @@
+iverilog -Wimplict -Wportbind -y ../fifo/ -y ../models/ -y . -y miim -y ../control -y ../coregen/ -y ../control_lib/ -o simple_gemac_wrapper_tb simple_gemac_wrapper_tb.v
diff --git a/fpga/usrp3/lib/sim/simple_gemac/simple_gemac_wrapper/simple_gemac_wrapper_tb.v b/fpga/usrp3/lib/sim/simple_gemac/simple_gemac_wrapper/simple_gemac_wrapper_tb.v
new file mode 100644
index 000000000..b89589234
--- /dev/null
+++ b/fpga/usrp3/lib/sim/simple_gemac/simple_gemac_wrapper/simple_gemac_wrapper_tb.v
@@ -0,0 +1,213 @@
+//
+// Copyright 2011 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+
+
+module simple_gemac_wrapper_tb;
+`include "eth_tasks_f36.v"
+     
+   reg reset   = 1;
+   initial #1000 reset = 0;
+   wire wb_rst 	= reset;
+
+   reg eth_clk     = 0;
+   always #50 eth_clk = ~eth_clk;
+
+   reg wb_clk 	= 0;
+   always #173 wb_clk = ~wb_clk;
+
+   reg sys_clk 	= 0;
+   always #77 sys_clk = ~ sys_clk;
+   
+   wire GMII_RX_DV, GMII_RX_ER, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK;
+   wire [7:0] GMII_RXD, GMII_TXD;
+
+   wire rx_valid, rx_error, rx_ack;
+   wire tx_ack, tx_valid, tx_error;
+   
+   wire [7:0] rx_data, tx_data;
+   
+   wire GMII_RX_CLK   = GMII_GTX_CLK;
+
+   reg [7:0] FORCE_DAT_ERR = 0;
+   reg FORCE_ERR = 0;
+   
+   // Loopback
+   assign GMII_RX_DV  = GMII_TX_EN;
+   assign GMII_RX_ER  = GMII_TX_ER | FORCE_ERR;
+   assign GMII_RXD    = GMII_TXD ^ FORCE_DAT_ERR;
+
+
+   wire [31:0] wb_dat_o;
+   reg [31:0]  wb_dat_i;
+   reg [7:0]   wb_adr;
+   reg 	       wb_stb=0, wb_cyc=0, wb_we=0;
+   wire        wb_ack;
+
+   reg [35:0]  tx_f36_data=0;
+   reg 	       tx_f36_src_rdy = 0;
+   wire        tx_f36_dst_rdy;
+   wire [35:0] rx_f36_data;
+   wire        rx_f36_src_rdy;
+   wire        rx_f36_dst_rdy = 1;
+   
+   simple_gemac_wrapper simple_gemac_wrapper
+     (.clk125(eth_clk),  .reset(reset),
+      .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),  
+      .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
+      .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),  
+      .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
+
+      .sys_clk(sys_clk), .rx_f36_data(rx_f36_data), .rx_f36_src_rdy(rx_f36_src_rdy), .rx_f36_dst_rdy(rx_f36_dst_rdy),
+      .tx_f36_data(tx_f36_data), .tx_f36_src_rdy(tx_f36_src_rdy), .tx_f36_dst_rdy(tx_f36_dst_rdy),
+
+      .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(wb_stb), .wb_cyc(wb_cyc), .wb_ack(wb_ack), .wb_we(wb_we),
+      .wb_adr(wb_adr), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o),
+
+      .mdio(), .mdc(),
+      .debug() );
+   
+   initial $dumpfile("simple_gemac_wrapper_tb.vcd");
+   initial $dumpvars(0,simple_gemac_wrapper_tb);
+
+   integer i; 
+   reg [7:0] pkt_rom[0:65535];
+   reg [1023:0] ROMFile;
+   
+   initial
+     for (i=0;i<65536;i=i+1)
+       pkt_rom[i] <= 8'h0;
+
+   initial
+     begin
+	@(negedge reset);
+	repeat (10)
+	  @(posedge wb_clk);
+	WishboneWR(0,6'b111101); 
+	WishboneWR(4,16'hA0B0);
+	WishboneWR(8,32'hC0D0_A1B1);
+	WishboneWR(12,16'h0000);
+	WishboneWR(16,32'h0000_0000);
+	
+	@(posedge eth_clk);
+	SendFlowCtrl(16'h0007);  // Send flow control
+	@(posedge eth_clk);
+	#30000;
+	@(posedge eth_clk);
+	SendFlowCtrl(16'h0009);  // Increase flow control before it expires
+	#10000;
+	@(posedge eth_clk);
+	SendFlowCtrl(16'h0000);  // Cancel flow control before it expires
+	@(posedge eth_clk); 
+
+	repeat (1000)
+	  @(posedge sys_clk);
+	SendPacket_to_fifo36(32'hA0B0C0D0,10);    // This packet gets dropped by the filters
+	repeat (1000)
+	  @(posedge sys_clk);
+
+	SendPacket_to_fifo36(32'hAABBCCDD,100);    // This packet gets dropped by the filters
+	repeat (10)
+	  @(posedge sys_clk);
+/*
+ 	SendPacketFromFile_f36(60,0,0);  // The rest are valid packets
+	repeat (10)
+	  @(posedge clk);
+
+ 	SendPacketFromFile_f36(61,0,0);
+	repeat (10)
+	  @(posedge clk);
+	SendPacketFromFile_f36(62,0,0);
+	repeat (10)
+	  @(posedge clk);
+	SendPacketFromFile_f36(63,0,0);
+	repeat (1)
+	  @(posedge clk);
+	SendPacketFromFile_f36(64,0,0);
+	repeat (10)
+	  @(posedge clk);
+	SendPacketFromFile_f36(59,0,0);
+	repeat (1)
+	  @(posedge clk);
+	SendPacketFromFile_f36(58,0,0);
+	repeat (1)
+	  @(posedge clk);
+	SendPacketFromFile_f36(100,0,0);
+	repeat (1)
+	  @(posedge clk);
+	SendPacketFromFile_f36(200,150,30);  // waiting 14 empties the fifo, 15 underruns
+	repeat (1)
+	  @(posedge clk);
+	SendPacketFromFile_f36(100,0,30);
+ */
+	#100000 $finish;
+     end
+
+   // Force a CRC error
+    initial
+     begin
+	#90000;
+	@(posedge eth_clk);
+	FORCE_DAT_ERR <= 8'h10;
+	@(posedge eth_clk);
+	FORCE_DAT_ERR <= 8'h00;
+     end
+
+   // Force an RX_ER error (i.e. link loss)
+   initial
+     begin
+	#116000;
+	@(posedge eth_clk);
+	FORCE_ERR <= 1;
+	@(posedge eth_clk);
+	FORCE_ERR <= 0;
+     end
+/*
+   // Cause receive fifo to fill, causing an RX overrun
+   initial
+     begin
+	#126000;
+	@(posedge clk);
+	rx_ll_dst_rdy2 <= 0;
+	repeat (30)          // Repeat of 14 fills the shortfifo, but works.  15 overflows
+	  @(posedge clk);
+	rx_ll_dst_rdy2 <= 1;
+     end
+  */
+   // Tests: Send and recv flow control, send and receive good packets, RX CRC err, RX_ER, RX overrun, TX underrun
+   // Still need to test: CRC errors on Pause Frames, MDIO, wishbone
+
+   task WishboneWR;
+      input [7:0] adr;
+      input [31:0] value;
+      begin
+	 wb_adr   <= adr;
+	 wb_dat_i <= value;
+	 wb_stb   <= 1;
+	 wb_cyc   <= 1;
+	 wb_we 	  <= 1;
+	 while (~wb_ack)
+	   @(posedge wb_clk);
+	 @(posedge wb_clk);
+	 wb_stb <= 0;
+	 wb_cyc <= 0;
+	 wb_we 	<= 0;
+      end
+   endtask // WishboneWR
+   /*
+   always @(posedge clk)
+     if(rx_ll_src_rdy2 & rx_ll_dst_rdy2)
+       begin
+	  if(rx_ll_sof2 & ~rx_ll_eof2)
+	    $display("RX-PKT-START %d",$time);
+	  $display("RX-PKT SOF %d EOF %d ERR%d DAT %x",rx_ll_sof2,rx_ll_eof2,rx_ll_error2,rx_ll_data2);
+	  if(rx_ll_eof2 & ~rx_ll_sof2)
+	    $display("RX-PKT-END %d",$time);
+       end
+   */
+endmodule // simple_gemac_wrapper_tb
diff --git a/fpga/usrp3/lib/sim/wishbone/simple_uart/simple_uart_tb.v b/fpga/usrp3/lib/sim/wishbone/simple_uart/simple_uart_tb.v
new file mode 100644
index 000000000..3a1ddda29
--- /dev/null
+++ b/fpga/usrp3/lib/sim/wishbone/simple_uart/simple_uart_tb.v
@@ -0,0 +1,132 @@
+//
+// Copyright 2016 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+module simple_uart_tb();
+   
+   localparam SUART_CLKDIV = 0;
+   localparam SUART_TXLEVEL = 1;
+   localparam SUART_RXLEVEL = 2;
+   localparam SUART_TXCHAR = 3;
+   localparam SUART_RXCHAR = 4;
+   
+   reg           clk;
+   reg 		 rst;
+
+   reg 		 we_i;
+   reg 		 stb_i;
+   reg 		 cyc_i;
+   wire 	 ack_o;
+   reg [2:0] 	 adr_i;
+   reg [31:0] 	 dat_i;
+   wire [31:0] 	 dat_o;
+   wire 	 rx_int_o;
+   wire 	 tx_int_o;
+   wire 	 tx_o;
+   reg 		 rx_i;
+   wire 	 baud_o;
+
+   reg [31:0] 	 read_data;
+   
+
+   initial 
+     clk = 0;
+
+   // 200MHz clock
+   always
+     #2.5 clk = ~clk;
+
+   initial begin
+      rst <= 0;
+      we_i <= 0;
+      stb_i <= 0;
+      cyc_i <= 0;
+      adr_i <= 0;
+      dat_i <= 0;
+      rx_i <= 0;
+   end
+   
+   
+   task write_wb;
+      input [31:0] data_in;
+      input [2:0]  addr_in;
+
+      begin
+	 @(negedge clk);	 
+	 dat_i <= data_in;
+	 adr_i <= addr_in;
+	 we_i <= 1;
+	 stb_i <= 1;
+	 cyc_i <= 1;
+	 @(negedge clk);
+	 while (ack_o == 0) begin
+	    @(negedge clk);
+	 end
+	 dat_i <= 0;
+	 adr_i <= 0;
+	 we_i <= 0;
+	 stb_i <= 0;
+	 cyc_i <= 0;
+      end
+   endtask // write_wb
+
+   
+   task read_wb;
+      output [31:0] data_out;
+      input [2:0]  addr_in;
+
+      begin
+	 @(negedge clk);	 
+	 adr_i <= addr_in;
+	 we_i <= 0;
+	 stb_i <= 1;
+	 cyc_i <= 1;
+	 @(negedge clk);
+	 while (ack_o == 0) begin
+	    @(negedge clk);
+	 end
+	 data_out <= dat_o;
+	 adr_i <= 0;
+	 stb_i <= 0;
+	 cyc_i <= 0;
+      end
+   endtask // write_wb
+
+   initial begin
+      @(negedge clk);    
+      rst <= 1;
+      repeat(10) @(negedge clk);
+      rst <= 0;
+      repeat(10) @(negedge clk);
+      write_wb(4'h0620,SUART_CLKDIV);
+      repeat(10) @(negedge clk);
+      read_wb(read_data,SUART_TXLEVEL);
+      repeat(10) @(negedge clk);
+   end // initial begin
+   
+   
+   
+   simple_uart
+     #(.CLKDIV_DEFAULT(16'd0))
+   simple_uart_i
+     (
+      .clk_i(clk),
+      .rst_i(rst),
+      .we_i(we_i),
+      .stb_i(stb_i),
+      .cyc_i(cyc_i),
+      .ack_o(ack_o),
+      .adr_i(adr_i),
+      .dat_i(dat_i),
+      .dat_o(dat_o),
+      .rx_int_o(rx_int_o),
+      .tx_int_o(tx_int_o), 
+      .tx_o(tx_o), 
+      .rx_i(rx_i),
+      .baud_o(baud_o)
+      );
+
+   
+
+endmodule // simple_uart_tb
diff --git a/fpga/usrp3/lib/simple_gemac/.gitignore b/fpga/usrp3/lib/simple_gemac/.gitignore
new file mode 100644
index 000000000..17f35e962
--- /dev/null
+++ b/fpga/usrp3/lib/simple_gemac/.gitignore
@@ -0,0 +1,4 @@
+/a.out
+/*.vcd
+simple_gemac_wrapper_tb
+
diff --git a/fpga/usrp3/lib/simple_gemac/Makefile.srcs b/fpga/usrp3/lib/simple_gemac/Makefile.srcs
new file mode 100644
index 000000000..c94a8b08c
--- /dev/null
+++ b/fpga/usrp3/lib/simple_gemac/Makefile.srcs
@@ -0,0 +1,25 @@
+#
+# Copyright 2010 Ettus Research LLC
+#
+
+##################################################
+# Simple GEMAC Sources
+##################################################
+SIMPLE_GEMAC_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/simple_gemac/, \
+simple_gemac_wrapper.v \
+simple_gemac.v \
+simple_gemac_tx.v \
+simple_gemac_rx.v \
+crc.v \
+delay_line.v \
+flow_ctrl_tx.v \
+flow_ctrl_rx.v \
+address_filter.v \
+address_filter_promisc.v \
+ll8_to_txmac.v \
+rxmac_to_ll8.v \
+ll8_to_axi64.v \
+axi64_to_ll8.v \
+gmii_to_axis.v \
+mdio.v \
+))
diff --git a/fpga/usrp3/lib/simple_gemac/address_filter.v b/fpga/usrp3/lib/simple_gemac/address_filter.v
new file mode 100644
index 000000000..a31f35e17
--- /dev/null
+++ b/fpga/usrp3/lib/simple_gemac/address_filter.v
@@ -0,0 +1,43 @@
+//
+// Copyright 2011 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+
+
+module address_filter
+  (input clk,
+   input reset,
+   input go,
+   input [7:0] data,
+   input [47:0] address,
+   output match,
+   output done);
+
+   reg [2:0] af_state;
+
+   always @(posedge clk)
+     if(reset)
+       af_state     <= 0;
+     else
+       if(go)
+	 af_state <= (data == address[47:40]) ? 1 : 7;
+       else
+	 case(af_state)
+	   1 : af_state <= (data == address[39:32]) ? 2 : 7;
+	   2 : af_state <= (data == address[31:24]) ? 3 : 7;
+	   3 : af_state <= (data == address[23:16]) ? 4 : 7;
+	   4 : af_state <= (data == address[15:8])  ? 5 : 7;
+	   5 : af_state <= (data == address[7:0]) ? 6 : 7;
+	   6, 7 : af_state <= 0;
+	 endcase // case (af_state)
+
+   assign match  = (af_state==6);
+   assign done 	 = (af_state==6)|(af_state==7);
+   
+endmodule // address_filter
+
+   
diff --git a/fpga/usrp3/lib/simple_gemac/address_filter_promisc.v b/fpga/usrp3/lib/simple_gemac/address_filter_promisc.v
new file mode 100644
index 000000000..cf992f867
--- /dev/null
+++ b/fpga/usrp3/lib/simple_gemac/address_filter_promisc.v
@@ -0,0 +1,40 @@
+//
+// Copyright 2011 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+
+
+module address_filter_promisc
+  (input clk,
+   input reset,
+   input go,
+   input [7:0] data,
+   output match,
+   output done);
+
+   reg [2:0] af_state;
+
+   always @(posedge clk)
+     if(reset)
+       af_state     <= 0;
+     else
+       if(go)
+	 af_state <= 1;//(data[0] == 1'b0) ? 1 : 7;
+       else
+	 case(af_state)
+	   1 : af_state <= 2;
+	   2 : af_state <= 3;
+	   3 : af_state <= 4;
+	   4 : af_state <= 5;
+	   5 : af_state <= 6;
+	   6, 7 : af_state <= 0;
+	 endcase // case (af_state)
+
+   assign match  = (af_state==6);
+   assign done 	 = (af_state==6)|(af_state==7);
+   
+endmodule // address_filter_promisc
diff --git a/fpga/usrp3/lib/simple_gemac/axi64_to_ll8.v b/fpga/usrp3/lib/simple_gemac/axi64_to_ll8.v
new file mode 100644
index 000000000..de0d6d8cc
--- /dev/null
+++ b/fpga/usrp3/lib/simple_gemac/axi64_to_ll8.v
@@ -0,0 +1,61 @@
+//
+// Copyright 2014 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+module axi64_to_ll8
+  #(parameter START_BYTE=6)
+   (input clk, input reset, input clear,
+    input [63:0] axi64_tdata, input axi64_tlast, input [3:0] axi64_tuser, input axi64_tvalid, output axi64_tready,
+    output [7:0] ll_data, output ll_eof, output ll_src_rdy, input ll_dst_rdy);
+
+   reg [7:0] 	 data_int;
+   wire 	 eof_int, valid_int, ready_int;
+
+   reg [2:0] 	 state = START_BYTE;
+   reg 		 eof, done;
+   reg [3:0] 	 occ;
+
+   wire [63:0] axi64_tdata_gated;
+   wire        axi64_tlast_gated;
+   wire [3:0]  axi64_tuser_gated;
+   wire        axi64_tvalid_gated;
+   wire        axi64_tready_gated;
+
+   axi_packet_gate #(
+     .WIDTH(68),
+     .SIZE(10)
+   ) axi64_packet_gater (
+     .clk(clk), .reset(reset), .clear(clear),
+     .i_tdata({axi64_tuser, axi64_tdata}), .i_tlast(axi64_tlast),
+     .i_tvalid(axi64_tvalid), .i_tready(axi64_tready),
+     .o_tdata({axi64_tuser_gated, axi64_tdata_gated}), .o_tlast(axi64_tlast_gated),
+     .o_tvalid(axi64_tvalid_gated), .o_tready(axi64_tready_gated)
+   );
+
+   always @(posedge clk)
+     if(reset | clear)
+       state <= START_BYTE;
+     else
+       if(valid_int & ready_int)
+	 if(eof_int)
+	   state <= START_BYTE;
+	 else
+	   state <= state + 3'd1;
+
+   assign valid_int = axi64_tvalid_gated;
+   assign axi64_tready_gated = ready_int & (eof_int | state == 7);
+   assign eof_int = axi64_tlast_gated & (axi64_tuser_gated[2:0] == (state + 3'd1));
+
+   always @*
+     data_int <= axi64_tdata_gated[state*8 +: 8];
+
+   axi_fifo_short #(.WIDTH(9)) ll8_fifo
+     (.clk(clk), .reset(reset), .clear(0),
+      .i_tdata({eof_int, data_int}), .i_tvalid(valid_int), .i_tready(ready_int),
+      .o_tdata({ll_eof, ll_data}), .o_tvalid(ll_src_rdy), .o_tready(ll_dst_rdy),
+      .space(), .occupied());
+
+endmodule // axi64_to_ll8
diff --git a/fpga/usrp3/lib/simple_gemac/crc.v b/fpga/usrp3/lib/simple_gemac/crc.v
new file mode 100644
index 000000000..6e1250c55
--- /dev/null
+++ b/fpga/usrp3/lib/simple_gemac/crc.v
@@ -0,0 +1,74 @@
+//
+// Copyright 2011 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+
+module crc
+  (input clk, 
+   input reset,
+   input clear, 
+   input [7:0] data,
+   input calc,
+   output [31:0] crc_out,
+   output match);
+   
+   function[31:0]  NextCRC;
+      input[7:0]      D;
+      input[31:0]     C;
+      reg[31:0]       NewCRC;
+      begin
+	 NewCRC[0]   = C[24]^C[30]^D[1]^D[7];
+	 NewCRC[1]   = C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
+	 NewCRC[2]   = C[26]^D[5]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
+	 NewCRC[3]   = C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
+	 NewCRC[4]   = C[28]^D[3]^C[27]^D[4]^C[26]^D[5]^C[24]^C[30]^D[1]^D[7];
+	 NewCRC[5]   = C[29]^D[2]^C[28]^D[3]^C[27]^D[4]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
+	 NewCRC[6]   = C[30]^D[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
+	 NewCRC[7]   = C[31]^D[0]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7];
+	 NewCRC[8]   = C[0]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7];
+	 NewCRC[9]   = C[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6];
+	 NewCRC[10]  = C[2]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7];
+	 NewCRC[11]  = C[3]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7];
+	 NewCRC[12]  = C[4]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7];
+	 NewCRC[13]  = C[5]^C[30]^D[1]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
+	 NewCRC[14]  = C[6]^C[31]^D[0]^C[30]^D[1]^C[28]^D[3]^C[27]^D[4]^C[26]^D[5];
+	 NewCRC[15]  = C[7]^C[31]^D[0]^C[29]^D[2]^C[28]^D[3]^C[27]^D[4];
+	 NewCRC[16]  = C[8]^C[29]^D[2]^C[28]^D[3]^C[24]^D[7];
+	 NewCRC[17]  = C[9]^C[30]^D[1]^C[29]^D[2]^C[25]^D[6];
+	 NewCRC[18]  = C[10]^C[31]^D[0]^C[30]^D[1]^C[26]^D[5];
+	 NewCRC[19]  = C[11]^C[31]^D[0]^C[27]^D[4];
+	 NewCRC[20]  = C[12]^C[28]^D[3];
+	 NewCRC[21]  = C[13]^C[29]^D[2];
+	 NewCRC[22]  = C[14]^C[24]^D[7];
+	 NewCRC[23]  = C[15]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7];
+	 NewCRC[24]  = C[16]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
+	 NewCRC[25]  = C[17]^C[27]^D[4]^C[26]^D[5];
+	 NewCRC[26]  = C[18]^C[28]^D[3]^C[27]^D[4]^C[24]^C[30]^D[1]^D[7];
+	 NewCRC[27]  = C[19]^C[29]^D[2]^C[28]^D[3]^C[25]^C[31]^D[0]^D[6];
+	 NewCRC[28]  = C[20]^C[30]^D[1]^C[29]^D[2]^C[26]^D[5];
+	 NewCRC[29]  = C[21]^C[31]^D[0]^C[30]^D[1]^C[27]^D[4];
+	 NewCRC[30]  = C[22]^C[31]^D[0]^C[28]^D[3];
+	 NewCRC[31]  = C[23]^C[29]^D[2];
+	 NextCRC     = NewCRC;
+      end
+   endfunction
+
+   reg [31:0] crc_reg;
+   always @ (posedge clk)
+     if (reset | clear)
+       crc_reg 	    <= 32'hffffffff;
+     else if (calc)
+       crc_reg 	    <= NextCRC(data,crc_reg);
+        
+   assign crc_out    = ~{crc_reg[24],crc_reg[25],crc_reg[26],crc_reg[27],crc_reg[28],crc_reg[29],crc_reg[30],crc_reg[31],
+		      crc_reg[16],crc_reg[17],crc_reg[18],crc_reg[19],crc_reg[20],crc_reg[21],crc_reg[22],crc_reg[23],
+		      crc_reg[8],crc_reg[9],crc_reg[10],crc_reg[11],crc_reg[12],crc_reg[13],crc_reg[14],crc_reg[15],
+		      crc_reg[0],crc_reg[1],crc_reg[2],crc_reg[3],crc_reg[4],crc_reg[5],crc_reg[6],crc_reg[7] };
+
+   assign match  = (crc_reg == 32'hc704_dd7b);
+		    
+endmodule // crc
diff --git a/fpga/usrp3/lib/simple_gemac/delay_line.v b/fpga/usrp3/lib/simple_gemac/delay_line.v
new file mode 100644
index 000000000..9e081b484
--- /dev/null
+++ b/fpga/usrp3/lib/simple_gemac/delay_line.v
@@ -0,0 +1,29 @@
+//
+// Copyright 2011 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+
+
+module delay_line
+  #(parameter WIDTH=32)
+   (input clk,
+    input [3:0] delay,
+    input [WIDTH-1:0] din,
+    output [WIDTH-1:0] dout);
+    
+   genvar 	       i;
+   generate
+      for (i=0;i<WIDTH;i=i+1)
+	begin : gen_delay
+	   SRL16E
+	     srl16e(.Q(dout[i]),
+		    .A0(delay[0]),.A1(delay[1]),.A2(delay[2]),.A3(delay[3]),
+		    .CE(1),.CLK(clk),.D(din[i]));
+	end
+   endgenerate
+
+endmodule // delay_line
diff --git a/fpga/usrp3/lib/simple_gemac/eth_tasks.v b/fpga/usrp3/lib/simple_gemac/eth_tasks.v
new file mode 100644
index 000000000..096ff3e34
--- /dev/null
+++ b/fpga/usrp3/lib/simple_gemac/eth_tasks.v
@@ -0,0 +1,164 @@
+//
+// Copyright 2011 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+
+
+task SendFlowCtrl;
+   input [15:0] fc_len;
+   begin
+      $display("Sending Flow Control, quanta = %d, time = %d", fc_len,$time);
+      pause_time <= fc_len;
+      @(posedge clk);
+      pause_req <= 1;
+      @(posedge clk);
+      pause_req <= 0;
+      $display("Sent Flow Control");
+   end
+endtask // SendFlowCtrl
+
+task SendPacket2MAC;
+   input tx_clk;
+   input [7:0] data_start;
+   input [31:0] data_len;
+   output [7:0] tx_data;
+   output tx_valid;
+   output tx_error;
+   input tx_ack;
+   reg [15:0] count;
+   begin
+      $display("Sending Packet Len=%d, %d", data_len, $time);
+      count <= 1;
+      tx_data  <= data_start;
+      tx_error <= 0;
+      tx_valid <= 1;
+      while(~tx_ack)
+	@(posedge tx_clk);
+      $display("Packet Accepted, %d", $time);
+      while(count < data_len)
+	begin
+	   tx_data <= tx_data + 1;
+	   count   <= count + 1;
+	   @(posedge clk);
+	end
+      tx_valid <= 0;
+      @(posedge tx_clk);
+   end
+endtask // SendPacket2MAC
+
+task SendPacket_to_ll8;
+   input [7:0] data_start;
+   input [15:0] data_len;
+//   output [7:0] tx_data;
+//   output tx_sof;
+//   output tx_eof;
+//   output tx_src_rdy;
+//   input tx_dst_rdy;
+   reg [15:0] count;
+   begin
+      $display("Sending Packet Len=%d, %d", data_len, $time);
+      count   <= 2;
+      tx_ll_data2 <= data_start;
+      tx_ll_src_rdy2 <= 1;
+      tx_ll_sof2  <= 1;
+      tx_ll_eof2  <= 0;
+      #1;
+      while(count < data_len)
+	begin
+	   while(~tx_ll_dst_rdy2)
+	     @(posedge clk);
+	   @(posedge clk);
+	   tx_ll_data2 = tx_ll_data2 + 1;
+	   count   = count + 1;
+	   tx_ll_sof2 <= 0;
+	end
+      tx_ll_eof2 	   <= 1;
+      while(~tx_ll_dst_rdy2)
+	@(posedge clk);
+      @(posedge clk);
+      tx_ll_src_rdy2 <= 0;
+   end
+endtask // SendPacket_to_ll8
+
+
+task SendPacketFromFile;
+   input clk;
+   input [31:0] data_len;
+   output [7:0] tx_data;
+   output tx_valid;
+   output tx_error;
+   input tx_ack;
+   reg [15:0] count;
+   begin
+      $display("Sending Packet From File Len=%d, %d",data_len,$time);
+      $readmemh("test_packet.mem",pkt_rom );     
+      count 	  = 0;
+      tx_data  = pkt_rom[count];
+      tx_error = 0;
+      tx_valid = 1;
+      while(~tx_ack)
+	@(posedge clk);
+      $display("Packet Accepted, %d",$time);
+      count = 1;
+      while(count < data_len)
+	begin
+	   tx_data = pkt_rom[count];
+	   count   = count + 1;
+	   @(posedge clk);
+	end
+      tx_valid <= 0;
+      @(posedge clk);
+   end
+endtask // SendPacketFromFile
+
+task Waiter;
+   input [31:0] wait_length;
+   begin
+      tx_ll_src_rdy2 <= 0;
+      repeat(wait_length)
+	@(posedge clk);
+      tx_ll_src_rdy2 <= 1;
+   end
+endtask // Waiter
+
+task SendPacketFromFile_ll8;
+   input [31:0] data_len;
+   input [31:0] wait_length;
+   input [31:0] wait_time;
+   
+   integer count;
+   begin
+      $display("Sending Packet From File to LL8 Len=%d, %d",data_len,$time);
+      $readmemh("test_packet.mem",pkt_rom );     
+
+      while(~tx_ll_dst_rdy2)
+	@(posedge clk);
+      tx_ll_data2 <= pkt_rom[0];
+      tx_ll_src_rdy2 <= 1;
+      tx_ll_sof2     <= 1;
+      tx_ll_eof2     <= 0;
+      @(posedge clk);
+      
+      for(i=1;i<data_len-1;i=i+1)
+	begin
+	   while(~tx_ll_dst_rdy2)
+	     @(posedge clk);
+	   tx_ll_data2 <= pkt_rom[i];
+	   tx_ll_sof2  <= 0;
+	   @(posedge clk);
+	   if(i==wait_time)
+	     Waiter(wait_length);
+	end
+      
+      while(~tx_ll_dst_rdy2)
+	@(posedge clk);
+      tx_ll_eof2 <= 1;
+      tx_ll_data2 <= pkt_rom[data_len-1];
+      @(posedge clk);
+      tx_ll_src_rdy2 <= 0;
+   end
+endtask // SendPacketFromFile_ll8
diff --git a/fpga/usrp3/lib/simple_gemac/flow_ctrl_rx.v b/fpga/usrp3/lib/simple_gemac/flow_ctrl_rx.v
new file mode 100644
index 000000000..8ea44133a
--- /dev/null
+++ b/fpga/usrp3/lib/simple_gemac/flow_ctrl_rx.v
@@ -0,0 +1,69 @@
+//
+// Copyright 2011 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+
+// RX side of flow control -- when we are running out of RX space, send a PAUSE
+
+module flow_ctrl_rx
+  (input pause_request_en, input [15:0] pause_time, input [15:0] pause_thresh,
+   input rx_clk, input rx_reset, input [15:0] rx_fifo_space,
+   input tx_clk, input tx_reset, output reg pause_req, output reg [15:0] pause_time_req
+   );
+   
+   // ******************************************************************************        
+   // Force our TX to send a PAUSE frame because our RX is nearly full
+   // ******************************************************************************
+
+   // RX Clock Domain
+   reg xon, xoff;
+   reg [21:0] countdown;
+
+   wire [15:0] pause_low_thresh = pause_thresh;
+   wire [15:0] pause_hi_thresh = 16'hFFFF;
+   wire [21:0] pq_reduced = {pause_time,6'd0} - 1700;
+   
+   always @(posedge rx_clk)
+     if(rx_reset)
+       xoff <= 0;
+     else
+       xoff <= (pause_request_en & (countdown==0) & (rx_fifo_space < pause_low_thresh));
+   
+   always @(posedge rx_clk)
+     if(rx_reset)
+       xon  <= 0;
+     else
+       xon  <= ((countdown!=0) & (rx_fifo_space > pause_hi_thresh));
+   
+   always @(posedge rx_clk)
+     if(rx_reset)
+       countdown <= 0;
+     else if(xoff)
+       countdown <= pq_reduced;
+     else if(xon)
+       countdown <= 0;
+     else if(countdown != 0)
+       countdown <= countdown - 1;
+
+   // Cross clock domains
+   wire        xon_tx, xoff_tx;
+   oneshot_2clk send_xon (.clk_in(rx_clk), .in(xon), .clk_out(tx_clk), .out(xon_tx));
+   oneshot_2clk send_xoff (.clk_in(rx_clk), .in(xoff), .clk_out(tx_clk), .out(xoff_tx));
+   
+   always @(posedge tx_clk)
+     if(xoff_tx)
+       pause_time_req <= pause_time;
+     else if(xon_tx)
+       pause_time_req <= 0;
+
+   always @(posedge tx_clk)
+     if(tx_reset)
+       pause_req      <= 0;
+     else 
+       pause_req      <= xon_tx | xoff_tx;
+   
+endmodule // flow_ctrl_rx
diff --git a/fpga/usrp3/lib/simple_gemac/flow_ctrl_tx.v b/fpga/usrp3/lib/simple_gemac/flow_ctrl_tx.v
new file mode 100644
index 000000000..34c90dc88
--- /dev/null
+++ b/fpga/usrp3/lib/simple_gemac/flow_ctrl_tx.v
@@ -0,0 +1,47 @@
+//
+// Copyright 2011 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+
+// TX side of flow control -- when other side sends PAUSE, we wait
+
+module flow_ctrl_tx
+  (input        rst,
+   input        tx_clk,
+   //host processor
+   input        tx_pause_en,
+   // From MAC_rx_ctrl
+   input [15:0] pause_quanta,
+   input        pause_quanta_val,
+   // MAC_tx_ctrl
+   output       pause_apply,
+   input        paused);
+     
+   // ******************************************************************************        
+   // Inhibit our TX from transmitting because they sent us a PAUSE frame
+   // ******************************************************************************
+
+   // Pauses are in units of 512 bit times, or 64 bytes/clock cycles, and can be
+   //   as big as 16 bits, so 22 bits are needed for the counter
+   
+   reg [15+6:0] pause_quanta_counter;
+   reg 		pqval_d1, pqval_d2;		
+
+   always @(posedge tx_clk) pqval_d1 <= pause_quanta_val;
+   always @(posedge tx_clk) pqval_d2 <= pqval_d1;
+
+   always @ (posedge tx_clk or posedge rst)
+     if (rst)
+       pause_quanta_counter <= 0;
+     else if (pqval_d1 & ~pqval_d2)
+       pause_quanta_counter <= {pause_quanta, 6'b0}; 
+     else if((pause_quanta_counter!=0) & paused)
+       pause_quanta_counter <= pause_quanta_counter - 1;
+
+   assign	pause_apply = tx_pause_en & (pause_quanta_counter != 0);
+   
+endmodule // flow_ctrl
diff --git a/fpga/usrp3/lib/simple_gemac/gmii_to_axis.v b/fpga/usrp3/lib/simple_gemac/gmii_to_axis.v
new file mode 100644
index 000000000..956f1cbcd
--- /dev/null
+++ b/fpga/usrp3/lib/simple_gemac/gmii_to_axis.v
@@ -0,0 +1,239 @@
+//
+// Copyright 2017 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module gmii_to_axis
+#(
+  parameter RX_FLOW_CTRL=0,
+  parameter PORTNUM=8'd0
+)
+(
+  input         clk125,
+  input         reset,
+
+  // GMII
+  output        gmii_gtx_clk,
+
+  output        gmii_tx_en,
+  output        gmii_tx_er,
+  output [7:0]  gmii_txd,
+
+  input         gmii_rx_clk,
+  input         gmii_rx_dv,
+  input         gmii_rx_er,
+  input [7:0]   gmii_rxd,
+
+  // Client FIFO Interfaces
+  input         sys_clk,
+  output [63:0] rx_tdata,
+  output [3:0]  rx_tuser,
+  output        rx_tlast,
+  output        rx_tvalid,
+  input         rx_tready,
+
+  input [63:0]  tx_tdata,
+  input [3:0]   tx_tuser,
+  input         tx_tlast,
+  input         tx_tvalid,
+  output        tx_tready,
+
+  output [31:0] debug_rx,
+  output [31:0] debug_tx
+);
+
+  wire clear = 1'b0;
+  wire [7:0] rx_data, tx_data;
+  wire tx_clk, tx_valid, tx_error, tx_ack;
+  wire rx_clk, rx_valid, rx_error, rx_ack;
+
+  wire        pause_req;
+  wire        pause_request_en, pause_respect_en;
+  wire [15:0] pause_time, pause_thresh, pause_time_req, rx_fifo_space;
+
+  wire [31:0] debug_state;
+
+  wire tx_reset, rx_reset;
+  reset_sync reset_sync_tx
+  (
+    .clk(tx_clk),
+    .reset_in(reset),
+    .reset_out(tx_reset)
+  );
+
+  reset_sync reset_sync_rx (
+    .clk(rx_clk),
+    .reset_in(reset),
+    .reset_out(rx_reset)
+  );
+
+  simple_gemac simple_gemac
+  (
+    .clk125(clk125),  .reset(reset),
+    .GMII_GTX_CLK(gmii_gtx_clk),
+    .GMII_TX_EN(gmii_tx_en),
+    .GMII_TX_ER(gmii_tx_er),
+    .GMII_TXD(gmii_txd),
+    .GMII_RX_CLK(gmii_rx_clk),
+    .GMII_RX_DV(gmii_rx_dv),
+    .GMII_RX_ER(gmii_rx_er),
+    .GMII_RXD(gmii_rxd),
+    .pause_req(RX_FLOW_CTRL ? pause_req : 1'b0),
+    .pause_time_req(RX_FLOW_CTRL ? pause_time_req : 16'd0),
+    .pause_respect_en(pause_respect_en),
+    .ucast_addr(48'h0),
+    .mcast_addr(48'h0),
+    .pass_ucast(1'b0),
+    .pass_mcast(1'b0),
+    .pass_bcast(1'b0),
+    .pass_pause(1'b0),
+    .pass_all(1'b1),
+    .rx_clk(rx_clk),
+    .rx_data(rx_data),
+    .rx_valid(rx_valid),
+    .rx_error(rx_error),
+    .rx_ack(rx_ack),
+    .tx_clk(tx_clk),
+    .tx_data(tx_data),
+    .tx_valid(tx_valid),
+    .tx_error(tx_error),
+    .tx_ack(tx_ack),
+    .debug(debug_state)
+  );
+
+  assign pause_respect_en = 1'b0;
+  assign pause_request_en = 1'b0;
+
+  ///////////////////////////////////////////////////////////////////////////////////////
+  // RX FIFO Chain
+  wire        rx_ll_eof;
+  wire        rx_ll_error;
+  wire        rx_ll_src_rdy;
+  wire        rx_ll_dst_rdy;
+  wire [7:0]  rx_ll_data;
+
+  wire [63:0] rx_tdata_int;
+  wire [3:0]  rx_tuser_int;
+  wire        rx_tlast_int;
+  wire        rx_tvalid_int;
+  wire        rx_tready_int;
+
+  rxmac_to_ll8 rxmac_to_ll8
+  (
+    .clk(rx_clk),
+    .reset(rx_reset),
+    .clear(clear),
+    .rx_data(rx_data),
+    .rx_valid(rx_valid),
+    .rx_error(rx_error),
+    .rx_ack(rx_ack),
+
+    .ll_data(rx_ll_data),
+    .ll_sof(),
+    .ll_eof(rx_ll_eof),
+    .ll_error(rx_ll_error),  // ignore sof
+    .ll_src_rdy(rx_ll_src_rdy),
+    .ll_dst_rdy(rx_ll_dst_rdy)
+  );
+
+  ll8_to_axi64 #(.START_BYTE(6), .LABEL(PORTNUM)) ll8_to_axi64
+  (
+    .clk(rx_clk),
+    .reset(rx_reset),
+    .clear(clear),
+    .ll_data(rx_ll_data),
+    .ll_eof(rx_ll_eof),
+    .ll_error(rx_ll_error),
+    .ll_src_rdy(rx_ll_src_rdy),
+    .ll_dst_rdy(rx_ll_dst_rdy),
+    .axi64_tdata(rx_tdata_int),
+    .axi64_tlast(rx_tlast_int),
+    .axi64_tuser(rx_tuser_int),
+    .axi64_tvalid(rx_tvalid_int),
+    .axi64_tready(rx_tready_int)
+  );
+
+  axi64_8k_2clk_fifo rxfifo_2clk
+  (
+    .s_aresetn(~rx_reset),
+    .s_aclk(rx_clk),
+    .s_axis_tvalid(rx_tvalid_int),
+    .s_axis_tready(rx_tready_int),
+    .s_axis_tdata(rx_tdata_int),
+    .s_axis_tlast(rx_tlast_int),
+    .s_axis_tuser(rx_tuser_int),
+    .axis_wr_data_count(),
+
+    .m_aclk(sys_clk),
+    .m_axis_tvalid(rx_tvalid),
+    .m_axis_tready(rx_tready),
+    .m_axis_tdata(rx_tdata),
+    .m_axis_tlast(rx_tlast),
+    .m_axis_tuser(rx_tuser),
+    .axis_rd_data_count()
+  );
+
+  ///////////////////////////////////////////////////////////////////////////////////////
+  // TX FIFO Chain
+  wire tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy;
+  wire [7:0] tx_ll_data;
+
+  wire [63:0] tx_tdata_int;
+  wire [3:0]  tx_tuser_int;
+  wire        tx_tlast_int;
+  wire        tx_tvalid_int;
+  wire        tx_tready_int;
+
+  axi64_8k_2clk_fifo txfifo_2clk
+  (
+    .s_aresetn(~tx_reset),
+    .s_aclk(sys_clk),
+    .s_axis_tvalid(tx_tvalid),
+    .s_axis_tready(tx_tready),
+    .s_axis_tdata(tx_tdata),
+    .s_axis_tlast(tx_tlast),
+    .s_axis_tuser(tx_tuser),
+    .axis_wr_data_count(),
+    .m_aclk(tx_clk),
+    .m_axis_tvalid(tx_tvalid_int),
+    .m_axis_tready(tx_tready_int),
+    .m_axis_tdata(tx_tdata_int),
+    .m_axis_tlast(tx_tlast_int),
+    .m_axis_tuser(tx_tuser_int),
+    .axis_rd_data_count()
+  );
+
+  axi64_to_ll8 #(.START_BYTE(6)) axi64_to_ll8
+  (
+    .clk(tx_clk),
+    .reset(tx_reset),
+    .clear(clear),
+    .axi64_tdata(tx_tdata_int),
+    .axi64_tlast(tx_tlast_int),
+    .axi64_tuser(tx_tuser_int),
+    .axi64_tvalid(tx_tvalid_int),
+    .axi64_tready(tx_tready_int),
+    .ll_data(tx_ll_data),
+    .ll_eof(tx_ll_eof),
+    .ll_src_rdy(tx_ll_src_rdy),
+    .ll_dst_rdy(tx_ll_dst_rdy)
+  );
+
+  ll8_to_txmac ll8_to_txmac
+  (
+    .clk(tx_clk),
+    .reset(tx_reset),
+    .clear(clear),
+    .ll_data(tx_ll_data),
+    .ll_eof(tx_ll_eof),
+    .ll_src_rdy(tx_ll_src_rdy),
+    .ll_dst_rdy(tx_ll_dst_rdy),
+    .tx_data(tx_data),
+    .tx_valid(tx_valid),
+    .tx_error(tx_error),
+    .tx_ack(tx_ack)
+  );
+
+endmodule
diff --git a/fpga/usrp3/lib/simple_gemac/ll8_to_axi64.v b/fpga/usrp3/lib/simple_gemac/ll8_to_axi64.v
new file mode 100644
index 000000000..22192cfd0
--- /dev/null
+++ b/fpga/usrp3/lib/simple_gemac/ll8_to_axi64.v
@@ -0,0 +1,94 @@
+//
+// Copyright 2014 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+// Takes 8-bit wide data on a Local-link fifo interface and converts to 64-bit wide axi
+//  Parameter START_BYTE controls which byte of the 8 the first incoming byte goes into
+//   Use START_BYTE=6 with ethernet to nicely align the words for processing of IP packets
+//  Parameter LABEL specifies a value to put in the high word of the very first packet.
+//   This is useful for labeling packets with the port it came from so downstream knows
+//   how to process it.  LABEL gets overwritten if START_BYTE = 0
+
+module ll8_to_axi64
+  #(parameter START_BYTE=6,
+    parameter LABEL=8'h00)
+   (input clk, input reset, input clear,
+    input [7:0] ll_data, input ll_eof, input ll_error, input ll_src_rdy, output ll_dst_rdy,
+    output [63:0] axi64_tdata, output axi64_tlast, output [3:0] axi64_tuser, output axi64_tvalid, input axi64_tready);
+
+   wire 	  error_int, eof_int;
+   wire [7:0] 	  data_int;
+   wire 	  valid_int, ready_int;
+   
+   axi_fifo_short #(.WIDTH(10)) ll8_fifo
+     (.clk(clk), .reset(reset), .clear(0),
+      .i_tdata({ll_error, ll_eof, ll_data}), .i_tvalid(ll_src_rdy), .i_tready(ll_dst_rdy),
+      .o_tdata({error_int, eof_int, data_int}), .o_tvalid(valid_int), .o_tready(ready_int),
+      .space(), .occupied());
+
+   wire [7:0] 	  label_wire = LABEL; // Enforces parameter width
+   
+   reg [3:0] 	  state = START_BYTE;
+   reg [63:0] 	  holding; // = {label_wire, 56'h0};
+   reg 		  err, eof, done;
+   reg [3:0] 	  occ;
+
+   localparam WAIT = 4'd8;
+   
+   always @(posedge clk)
+     if(reset | clear)
+       begin
+	  state <= START_BYTE;
+	  holding <= {56'h0, label_wire};
+	  err <= 1'b0;
+	  eof <= 1'b0;
+	  occ <= 3'd0;
+	  done <= 1'b0;
+       end
+     else
+       if(state == WAIT)
+	 begin
+	    state <= START_BYTE;
+	    done <= 1'b0;
+	    holding <= {56'h0, label_wire};
+	 end
+       else if(valid_int & ready_int)
+	 begin
+	    holding[state*8 +: 8] <= data_int;
+	    
+	    err <= error_int;
+	    eof <= eof_int;
+            if(error_int | eof_int)
+	      begin
+		 occ <= state+1;
+		 done <= 1'b1;
+		 state <= WAIT;
+	      end
+	    else if (state == 4'd7)
+	      begin
+		 occ <= 3'd0;
+		 done <= 1'b1;
+		 state <= 4'd0;
+	      end
+	    else
+	      begin
+		 occ <= 3'd0;
+		 done <= 1'b0;
+		 state <= state + 4'd1;
+	      end // else: !if(state == 4'd7)
+	    
+	 end // if (valid_int & ready_int)
+       else
+	 done <= 1'b0;
+   
+   assign axi64_tdata = holding;
+   assign axi64_tlast = eof;
+   assign axi64_tuser[3] = err;
+   assign axi64_tuser[2:0] = occ;
+
+   assign ready_int = axi64_tready & (state != WAIT);
+   assign axi64_tvalid = done;
+   		  
+endmodule // ll8_to_axi64
diff --git a/fpga/usrp3/lib/simple_gemac/ll8_to_axi64_tb.v b/fpga/usrp3/lib/simple_gemac/ll8_to_axi64_tb.v
new file mode 100644
index 000000000..3f86b41dd
--- /dev/null
+++ b/fpga/usrp3/lib/simple_gemac/ll8_to_axi64_tb.v
@@ -0,0 +1,100 @@
+//
+// Copyright 2014 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+`timescale 1ns/1ps
+
+module ll8_to_axi64_tb();
+
+   reg clk    = 0;
+   reg reset  = 1;
+   
+   always #10 clk = ~clk;
+   
+   initial $dumpfile("ll8_to_axi64_tb.vcd");
+   initial $dumpvars(0,ll8_to_axi64_tb);
+
+   initial
+     begin
+	#1000 reset = 0;
+	#2000000;
+	$finish;
+     end
+   
+   wire [63:0]  tdata, tdata_int;
+   wire [3:0] 	tuser, tuser_int;
+   wire 	tlast, tlast_int;
+   wire		tvalid, tvalid_int, tready, tready_int;
+
+   reg [7:0] 	ll_data;
+   reg 		ll_eof, ll_error, ll_src_rdy;
+   wire 	ll_dst_rdy;
+
+   wire [7:0] 	ll_data2;
+   wire 	ll_eof2, ll_src_rdy2, ll_dst_rdy2;
+   
+   localparam RPT_COUNT = 12;
+   
+   initial
+     begin
+	ll_src_rdy <= 0;
+ 
+	while(reset)
+	  @(posedge clk);
+
+	@(posedge clk);
+	
+	{ll_error, ll_eof, ll_data} <= { 1'b0, 1'b0, 8'hA0 };
+	repeat(RPT_COUNT-1)
+	  begin
+	     ll_src_rdy <= 1;
+	     @(posedge clk);
+	     ll_data <= ll_data + 1;
+	  end
+	ll_eof <= 1;
+	ll_data <= ll_data + 1;
+	@(posedge clk);
+
+	{ll_error, ll_eof, ll_data} <= { 1'b0, 1'b0, 8'hC0 };
+	repeat(RPT_COUNT-1)
+	  begin
+	     ll_src_rdy <= 1;
+	     @(posedge clk);
+	     ll_data <= ll_data + 1;
+	  end
+	ll_eof <= 1; ll_error <= 1;
+	ll_data <= ll_data + 1;
+	@(posedge clk);
+	ll_src_rdy <= 1'b0;
+
+     end
+
+   ll8_to_axi64 #(.START_BYTE(6), .LABEL(8'h89)) ll8_to_axi64
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .ll_data(ll_data), .ll_eof(ll_eof), .ll_error(ll_error), .ll_src_rdy(ll_src_rdy), .ll_dst_rdy(ll_dst_rdy),
+      .axi64_tdata(tdata), .axi64_tlast(tlast), .axi64_tuser(tuser), .axi64_tvalid(tvalid), .axi64_tready(tready) );
+   
+   axi_fifo_short #(.WIDTH(69)) axi_fifo_short
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata({tlast,tuser,tdata}), .i_tvalid(tvalid), .i_tready(tready),
+      .o_tdata({tlast_int,tuser_int,tdata_int}), .o_tvalid(tvalid_int), .o_tready(tready_int));
+
+   axi64_to_ll8 #(.START_BYTE(6)) axi64_to_ll8
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .axi64_tdata(tdata_int), .axi64_tlast(tlast_int), .axi64_tuser(tuser_int), .axi64_tvalid(tvalid_int), .axi64_tready(tready_int),
+      .ll_data(ll_data2), .ll_eof(ll_eof2), .ll_src_rdy(ll_src_rdy2), .ll_dst_rdy(ll_dst_rdy2) );
+
+   /*
+   always @(posedge clk)
+     if(ll_src_rdy2 & ll_dst_rdy2)
+       $display("EOF %x\tDATA %x",ll_eof2, ll_data2);
+
+   */
+   assign ll_dst_rdy2 = 1;
+   
+   always @(posedge clk)
+     if(tvalid_int & tready_int)
+       $display("TERR %x\tTUSER %x\tTLAST %x\tTDATA %x",tuser_int[3],tuser_int[2:0], tlast_int, tdata_int);
+   
+endmodule // ll8_to_axi64_tb
diff --git a/fpga/usrp3/lib/simple_gemac/ll8_to_txmac.v b/fpga/usrp3/lib/simple_gemac/ll8_to_txmac.v
new file mode 100644
index 000000000..6251ce73d
--- /dev/null
+++ b/fpga/usrp3/lib/simple_gemac/ll8_to_txmac.v
@@ -0,0 +1,51 @@
+//
+// Copyright 2011 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+
+module ll8_to_txmac
+  (input clk, input reset, input clear,
+   input [7:0] ll_data, input ll_eof, input ll_src_rdy, output ll_dst_rdy,
+   output [7:0] tx_data, output tx_valid, output tx_error, input tx_ack );
+
+   reg [2:0] xfer_state;
+
+   localparam XFER_IDLE      = 0;
+   localparam XFER_ACTIVE    = 1;
+   localparam XFER_WAIT1     = 2;
+   localparam XFER_UNDERRUN  = 3;
+   localparam XFER_DROP      = 4;
+   
+   always @(posedge clk)
+     if(reset | clear)
+       xfer_state 	    <= XFER_IDLE;
+     else
+       case(xfer_state)
+	 XFER_IDLE :
+	   if(tx_ack)
+	     xfer_state <= XFER_ACTIVE;
+	 XFER_ACTIVE :
+	   if(~ll_src_rdy)
+	     xfer_state <= XFER_UNDERRUN;
+	   else if(ll_eof)
+	     xfer_state <= XFER_WAIT1;
+	 XFER_WAIT1 :
+	   xfer_state <= XFER_IDLE;
+	 XFER_UNDERRUN :
+	   xfer_state <= XFER_DROP;
+	 XFER_DROP :
+	   if(ll_eof)
+	     xfer_state <= XFER_IDLE;
+       endcase // case (xfer_state)
+
+   assign ll_dst_rdy 	 = (xfer_state == XFER_ACTIVE) | tx_ack | (xfer_state == XFER_DROP);
+   assign tx_valid 	 = (ll_src_rdy & (xfer_state == XFER_IDLE))|(xfer_state == XFER_ACTIVE);
+   assign tx_data 	 = ll_data;
+   assign tx_error 	 = (xfer_state == XFER_UNDERRUN);
+   
+endmodule // ll8_to_txmac
+
diff --git a/fpga/usrp3/lib/simple_gemac/mdio.v b/fpga/usrp3/lib/simple_gemac/mdio.v
new file mode 100644
index 000000000..54b5e183c
--- /dev/null
+++ b/fpga/usrp3/lib/simple_gemac/mdio.v
@@ -0,0 +1,852 @@
+//
+// Copyright 2014 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Define MDIO to add support for clause 22 and clause 45 MDIO interface
+`define MDIO
+// If WB clock is 62.5MHz and max MDC spec is 2.5MHz, then divide by 25
+//`define MDC_HALF_PERIOD 13 // Closest int to 12.5
+`define MDC_HALF_PERIOD 100
+ 
+//  Registers
+`define CPUREG_MDIO_DATA    8'h10
+`define CPUREG_MDIO_ADDR    8'h14
+`define CPUREG_MDIO_OP      8'h18
+`define CPUREG_MDIO_CONTROL 8'h1c
+`define CPUREG_MDIO_STATUS  8'h1c
+`define CPUREG_GPIO         8'h20
+
+
+module mdio
+  (
+   // Wishbone Bus
+   input wb_clk_i, 
+   input wb_rst_i, 
+   input [7:0] wb_adr_i, 
+   input [31:0] wb_dat_i, 
+   input wb_we_i, 
+   input wb_stb_i, 
+   input wb_cyc_i, 
+   output reg [31:0] wb_dat_o, 
+   output wb_ack_o, 
+   output reg wb_int_o,
+   // MDIO
+   output reg mdc, 
+   output reg mdio_out, 
+   output reg mdio_tri,
+   input mdio_in
+   );
+
+  //
+  // State Declarations
+  //
+  parameter  
+    IDLE = 0,
+      PREAMBLE1 = 1,
+      PREAMBLE2 = 2,
+      PREAMBLE3 = 3,
+      PREAMBLE4 = 4,
+      PREAMBLE5 = 5,
+      PREAMBLE6 = 6,
+      PREAMBLE7 = 7,
+      PREAMBLE8 = 8,
+      PREAMBLE9 = 9,
+      PREAMBLE10 = 10,
+      PREAMBLE11 = 11,
+      PREAMBLE12 = 12,
+      PREAMBLE13 = 13,
+      PREAMBLE14 = 14,
+      PREAMBLE15 = 15,
+      PREAMBLE16 = 16,
+      PREAMBLE17 = 17,
+      PREAMBLE18 = 18,
+      PREAMBLE19 = 19,
+      PREAMBLE20 = 20,
+      PREAMBLE21 = 21,
+      PREAMBLE22 = 22,
+      PREAMBLE23 = 23,
+      PREAMBLE24 = 24,
+      PREAMBLE25 = 25,
+      PREAMBLE26 = 26,
+      PREAMBLE27 = 27,
+      PREAMBLE28 = 28,
+      PREAMBLE29 = 29,
+      PREAMBLE30 = 30,
+      PREAMBLE31 = 31,
+      PREAMBLE32 = 32,
+      START1 = 33,
+      C22_START2 = 34,
+      C45_START2 = 35,
+      OP1 = 36,
+      OP2 = 37,
+      PRTAD1 = 38,
+      PRTAD2 = 39,
+      PRTAD3 = 40,
+      PRTAD4 = 41,
+      PRTAD5 = 42,
+      DEVAD1 = 43,
+      DEVAD2 = 44,
+      DEVAD3 = 45,
+      DEVAD4 = 46,
+      DEVAD5 = 47,
+      TA1 = 48,
+      TA2 = 49,
+      TA3 = 50,
+      READ1 = 51,
+      READ2 = 52,
+      READ3 = 53,
+      READ4 = 54,
+      READ5 = 55,
+      READ6 = 56,
+      READ7 = 57,
+      READ8 = 58,
+      READ9 = 59,
+      READ10 = 60,
+      READ11 = 61,
+      READ12 = 62,
+      READ13 = 63,
+      READ14 = 64,
+      READ15 = 65,
+      READ16 = 66,
+      WRITE1 = 67,
+      WRITE2 = 68,
+      WRITE3 = 69,
+      WRITE4 = 70,
+      WRITE5 = 71,
+      WRITE6 = 72,
+      WRITE7 = 73,
+      WRITE8 = 74,
+      WRITE9 = 75,
+      WRITE10 = 76,
+      WRITE11 = 77,
+      WRITE12 = 78,
+      WRITE13 = 79,
+      WRITE14 = 80,
+      WRITE15 = 81,
+      WRITE16 = 82,
+      C45_ADDR1 = 83,
+      C45_ADDR2 = 84,
+      C45_ADDR3 = 85,
+      C45_ADDR4 = 86,
+      C45_ADDR5 = 87,
+      C45_ADDR6 = 88,
+      C45_ADDR7 = 89,
+      C45_ADDR8 = 90,
+      C45_ADDR9 = 91,
+      C45_ADDR10 = 92,
+      C45_ADDR11 = 93,
+      C45_ADDR12 = 94,
+      C45_ADDR13 = 95,
+      C45_ADDR14 = 96,
+      C45_ADDR15 = 97,
+      C45_ADDR16 = 98,
+      PREIDLE = 99;
+   
+   reg 	 cpuack;
+   reg [15:0] mdio_read_data;
+   reg [15:0] mdio_write_data;
+   reg [15:0] mdio_address;
+   reg [12:0] mdio_operation;
+   reg 	      mdio_control;
+   reg [7:0]  mdc_clk_count;
+   reg 	      mdc_falling_edge;
+   reg 	      mdio_running;
+   reg 	      mdio_done;
+   reg [7:0]  state;
+
+   
+   assign wb_ack_o = cpuack && wb_stb_i;
+   
+   always @(posedge wb_clk_i or posedge wb_rst_i) begin
+      
+      if (wb_rst_i == 1'b1) begin
+	 wb_dat_o <= 32'b0;
+         wb_int_o <= 1'b0;
+         cpuack <= 1'b0;
+
+	 mdio_address <= 0;
+	 mdio_operation <= 0;
+	 mdio_write_data <= 0;
+       	 mdio_running <= 0;
+      end
+      else begin
+	 
+	 wb_int_o <= 1'b0;
+	 cpuack <= wb_cyc_i && wb_stb_i;
+	 // Handshake to MDIO state machine to reset running flag in status.
+	 // Wait for falling MDC edge to prevent S/W race condition occuring
+	 // where done flag still asserted but running flag now cleared (repeatedly).
+	 if (mdio_done && mdc_falling_edge)
+	   mdio_running <= 0;
+
+	 //
+	 // Read access
+	 //
+	 if (wb_cyc_i && wb_stb_i && !wb_we_i) begin
+	    
+            case ({wb_adr_i[7:2], 2'b0})
+	      
+	      `CPUREG_MDIO_DATA: begin
+		 wb_dat_o <= {16'b0, mdio_read_data};
+	      end
+	      
+	      `CPUREG_MDIO_STATUS: begin
+		 wb_dat_o <= {31'b0, mdio_running};
+	      end
+
+              default: begin
+              end
+	      
+            endcase 
+         end
+	 
+         //
+         // Write access
+	 //
+         if (wb_cyc_i && wb_stb_i && wb_we_i) begin
+	    $display("reg write @ addr %x",({wb_adr_i[7:2], 2'b0}));
+	    
+            case ({wb_adr_i[7:2], 2'b0})
+	      
+	      `CPUREG_MDIO_DATA: begin
+		 mdio_write_data <= wb_dat_i[15:0];
+	      end
+
+	      `CPUREG_MDIO_ADDR: begin
+		 mdio_address <= wb_dat_i[15:0];
+	      end
+	      
+	      `CPUREG_MDIO_OP: begin
+		 mdio_operation <= wb_dat_i[12:0];
+	      end
+
+	      `CPUREG_MDIO_CONTROL: begin
+		 // Trigger mdio operation here. Cleared by state machine at end of bus transaction.
+		 if (wb_dat_i[0])
+		   mdio_running <= 1;		 
+	      end
+
+              default: begin
+              end
+	      
+            endcase
+	    
+         end
+	 
+      end
+      
+   end // always @ (posedge wb_clk_i or posedge wb_rst_i)
+
+
+   //
+   // Produce mdc clock as a signal synchronously from Wishbone clock.
+   //
+   always @(posedge wb_clk_i or posedge wb_rst_i)
+     if (wb_rst_i)
+       begin
+	  mdc_clk_count <= 1;
+	  mdc <= 0;
+	  mdc_falling_edge <= 0;	  
+       end
+     else if (mdc_clk_count == `MDC_HALF_PERIOD)
+       begin
+	  mdc_clk_count <= 1;
+	  mdc <= ~mdc;
+	  mdc_falling_edge <= mdc;	  
+       end
+     else
+       begin
+	  mdc_clk_count <= mdc_clk_count + 1;
+	  mdc_falling_edge <= 0;		   
+       end
+   
+   //
+   // MDIO state machine
+   //
+   always @(posedge wb_clk_i or posedge wb_rst_i)
+     if (wb_rst_i)
+       begin
+	  mdio_tri <= 1;
+	  mdio_out <= 0;
+	  mdio_done <= 0;
+	  mdio_read_data <= 0;
+	  state <= IDLE;
+       end
+     else if (mdc_falling_edge)
+       //
+       // This is the MDIO bus controller. Use falling edge of MDC.
+       //      
+       begin
+	  // Defaults	  
+	  mdio_tri <= 1;
+	  mdio_out <= 0;
+	  mdio_done <= 0;
+	  
+	  
+	  case(state)
+	    // IDLE.
+	    // In Clause 22 & 45 the master of the MDIO bus is tristate during idle.
+	    // 
+	    IDLE: begin
+	       mdio_tri <= 1;
+	       mdio_out <= 0;
+	       if (mdio_running)
+		 state <= PREAMBLE1;
+	    end
+	    // Preamble. All MDIO transactions begin witrh 32bits of 1 bits as a preamble.
+	    PREAMBLE1: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;  
+	       state <= PREAMBLE2;
+	    end
+	    PREAMBLE2: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;  
+	       state <= PREAMBLE3;
+	    end 
+	    PREAMBLE3: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;  
+	       state <= PREAMBLE4;
+	    end 
+	    PREAMBLE4: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;  
+	       state <= PREAMBLE5;
+	    end 
+	    PREAMBLE5: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;  
+	       state <= PREAMBLE6;
+	    end
+	    PREAMBLE6: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;  
+	       state <= PREAMBLE7;
+	    end
+	    PREAMBLE7: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;  
+	       state <= PREAMBLE8;
+	    end
+	    PREAMBLE8: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;
+	       state <= PREAMBLE9;
+	    end
+	    PREAMBLE9: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;
+	       state <= PREAMBLE10;
+	    end
+	    PREAMBLE10: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;
+	       state <= PREAMBLE11;
+	    end
+	    PREAMBLE11: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;  
+	       state <= PREAMBLE12;
+	    end
+	    PREAMBLE12: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;  
+	       state <= PREAMBLE13;
+	    end 
+	    PREAMBLE13: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;  
+	       state <= PREAMBLE14;
+	    end 
+	    PREAMBLE14: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;  
+	       state <= PREAMBLE15;
+	    end 
+	    PREAMBLE15: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;  
+	       state <= PREAMBLE16;
+	    end
+	    PREAMBLE16: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;  
+	       state <= PREAMBLE17;
+	    end
+	    PREAMBLE17: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;  
+	       state <= PREAMBLE18;
+	    end
+	    PREAMBLE18: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;
+	       state <= PREAMBLE19;
+	    end
+	    PREAMBLE19: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;
+	       state <= PREAMBLE20;
+	    end
+	    PREAMBLE20: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;
+	       state <= PREAMBLE21;
+	    end
+	    PREAMBLE21: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;  
+	       state <= PREAMBLE22;
+	    end
+	    PREAMBLE22: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;  
+	       state <= PREAMBLE23;
+	    end 
+	    PREAMBLE23: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;  
+	       state <= PREAMBLE24;
+	    end 
+	    PREAMBLE24: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;  
+	       state <= PREAMBLE25;
+	    end 
+	    PREAMBLE25: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;  
+	       state <= PREAMBLE26;
+	    end
+	    PREAMBLE26: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;  
+	       state <= PREAMBLE27;
+	    end
+	    PREAMBLE27: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;  
+	       state <= PREAMBLE28;
+	    end
+	    PREAMBLE28: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;
+	       state <= PREAMBLE29;
+	    end
+	    PREAMBLE29: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;
+	       state <= PREAMBLE30;
+	    end
+	    PREAMBLE30: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;
+	       state <= PREAMBLE31;
+	    end
+	    PREAMBLE31: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;
+	       state <= PREAMBLE32;
+	    end
+	    PREAMBLE32: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;
+	       state <= START1;
+	    end
+	    //
+	    // Start code for Clause 22 is 01 and Clause 45 is 00
+	    //
+	    START1: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 0;
+	       if (mdio_operation[12])
+		 // Clause 45 bit set.
+		 state <= C45_START2;
+	       else
+		 state <= C22_START2;	       
+	    end
+	    //
+	    // 2nd Clause 22 start bit is a 1
+	    //
+	    C22_START2: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;
+	       state <= OP1;
+	    end
+	    //
+	    // 2nd Clause 45 start bit is a 0
+	    //
+	    C45_START2: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 0;
+	       state <= OP1;
+	    end
+	    //
+	    // Both Clause 22 & 45 use 2 bits for operation and are compatable.
+	    // Note we don't screen here for illegal Clause 22 ops.
+	    //
+	    OP1: begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_operation[11];
+	       state <= OP2;
+	    end
+	    OP2: begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_operation[10];
+	       state <= PRTAD1;
+	    end
+	    //
+	    // Both Clause 22 & 45 use 2 sucsessive 5 bit fields to form a hierarchical address
+	    // though it's used slightly different between the 2 standards.
+	    //
+	    PRTAD1: begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_operation[9];
+	       state <= PRTAD2;	       
+	    end
+	    PRTAD2: begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_operation[8];
+	       state <= PRTAD3;	       
+	    end
+	    PRTAD3: begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_operation[7];
+	       state <= PRTAD4;	       
+	    end
+	    PRTAD4: begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_operation[6];
+	       state <= PRTAD5;	       
+	    end
+	    PRTAD5: begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_operation[5];
+	       state <= DEVAD1;	       
+	    end
+	    DEVAD1: begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_operation[4];
+	       state <= DEVAD2;	       
+	    end
+	    DEVAD2: begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_operation[3];
+	       state <= DEVAD3;	       
+	    end
+	    DEVAD3: begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_operation[2];
+	       state <= DEVAD4;	       
+	    end
+	    DEVAD4: begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_operation[1];
+	       state <= DEVAD5;	       
+	    end
+	    DEVAD5: begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_operation[0];
+	       state <= TA1;	       
+	    end
+	    //
+	    // Both Clause 22 & Clause 45 use the same turn around on the bus.
+	    // Reads have Z as the first bit and 0 driven by the slave for the 2nd bit.
+	    // Note that slaves drive the bus on the rising edge of MDC.
+	    // Writes and Address cycles have 10 driven by the master.
+	    //
+	    TA1: begin
+	    	// Clause22 write or clause45 write or address go to state TA2
+	       if ((mdio_operation[12:11] == 2'b10) || (mdio_operation[12:11] == 2'b01))
+		 begin
+		    mdio_tri <= 0;
+		    mdio_out <= 1;
+		    state <= TA2;
+		 end
+	       else // Read
+		 begin
+		    mdio_tri <= 1;
+		    state <= TA3;
+		 end
+	    end
+	    TA2: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 0;
+	       if (!mdio_operation[12]) // Clause 22 Write
+		 state <= WRITE1;
+	       else if (mdio_operation[10]) // Clause 45 Write
+		 state <= WRITE1;
+	       else // Clause 45 ADDRESS
+		 state <= C45_ADDR1;
+	    end
+	    TA3: begin
+	       mdio_tri <= 1;
+	       state <= READ1;
+	    end
+	    //
+	    // Clause 22 Reads and both forms of clause 45 Reads have the same bus transaction from here out.
+	    //
+	    READ1: begin
+	       mdio_tri <= 1;	
+	       mdio_read_data[15] <= mdio_in;
+	       state <= READ2;	    
+	    end
+	    READ2: begin
+	       mdio_tri <= 1;	
+	       mdio_read_data[14] <= mdio_in;
+	       state <= READ3;	    
+	    end
+	    READ3: begin
+	       mdio_tri <= 1;	
+	       mdio_read_data[13] <= mdio_in;
+	       state <= READ4;	    
+	    end
+	    READ4: begin
+	       mdio_tri <= 1;	
+	       mdio_read_data[12] <= mdio_in;
+	       state <= READ5;	    
+	    end
+	    READ5: begin
+	       mdio_tri <= 1;	
+	       mdio_read_data[11] <= mdio_in;
+	       state <= READ6;	    
+	    end
+	    READ6: begin
+	       mdio_tri <= 1;	
+	       mdio_read_data[10] <= mdio_in;
+	       state <= READ7;	    
+	    end
+	    READ7: begin
+	       mdio_tri <= 1;	
+	       mdio_read_data[9] <= mdio_in;
+	       state <= READ8;	    
+	    end
+	    READ8: begin
+	       mdio_tri <= 1;	
+	       mdio_read_data[8] <= mdio_in;
+	       state <= READ9;	    
+	    end
+	    READ9: begin
+	       mdio_tri <= 1;	
+	       mdio_read_data[7] <= mdio_in;
+	       state <= READ10;	    
+	    end
+	    READ10: begin
+	       mdio_tri <= 1;	
+	       mdio_read_data[6] <= mdio_in;
+	       state <= READ11;	    
+	    end
+	    READ11: begin
+	       mdio_tri <= 1;	
+	       mdio_read_data[5] <= mdio_in;
+	       state <= READ12;	    
+	    end
+	    READ12: begin
+	       mdio_tri <= 1;	
+	       mdio_read_data[4] <= mdio_in;
+	       state <= READ13;	    
+	    end
+	    READ13: begin
+	       mdio_tri <= 1;	
+	       mdio_read_data[3] <= mdio_in;
+	       state <= READ14;	    
+	    end
+	    READ14: begin
+	       mdio_tri <= 1;	
+	       mdio_read_data[2] <= mdio_in;
+	       state <= READ15;	    
+	    end
+	    READ15: begin
+	       mdio_tri <= 1;	
+	       mdio_read_data[1] <= mdio_in;
+	       state <= READ16;	    
+	    end
+	    READ16: begin
+	       mdio_tri <= 1;	
+	       mdio_read_data[0] <= mdio_in;
+	       state <= PREIDLE;	 
+	       mdio_done <= 1;	          
+	    end	    
+	    //
+	    // Write 16bits of data for all types of Write.
+	    //
+	    WRITE1:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_write_data[15];
+	       state <= WRITE2;
+	    end
+	    WRITE2:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_write_data[14];
+	       state <= WRITE3;
+	    end
+	    WRITE3:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_write_data[13];
+	       state <= WRITE4;
+	    end
+	    WRITE4:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_write_data[12];
+	       state <= WRITE5;
+	    end
+	    WRITE5:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_write_data[11];
+	       state <= WRITE6;
+	    end
+	    WRITE6:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_write_data[10];
+	       state <= WRITE7;
+	    end
+	    WRITE7:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_write_data[9];
+	       state <= WRITE8;
+	    end
+	    WRITE8:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_write_data[8];
+	       state <= WRITE9;
+	    end
+	    WRITE9:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_write_data[7];
+	       state <= WRITE10;
+	    end
+	    WRITE10:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_write_data[6];
+	       state <= WRITE11;
+	    end
+	    WRITE11:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_write_data[5];
+	       state <= WRITE12;
+	    end
+	    WRITE12:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_write_data[4];
+	       state <= WRITE13;
+	    end
+	    WRITE13:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_write_data[3];
+	       state <= WRITE14;
+	    end
+	    WRITE14:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_write_data[2];
+	       state <= WRITE15;
+	    end
+	    WRITE15:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_write_data[1];
+	       state <= WRITE16;
+	    end
+	    WRITE16:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_write_data[0];
+	       state <= PREIDLE;
+	       mdio_done <= 1;	       
+	    end
+	    //
+	    // Write 16bits of address for a Clause 45 Address transaction
+	    //
+	    C45_ADDR1:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_address[15];
+	       state <= C45_ADDR2;
+	    end
+	    C45_ADDR2:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_address[14];
+	       state <= C45_ADDR3;
+	    end
+	    C45_ADDR3:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_address[13];
+	       state <= C45_ADDR4;
+	    end
+	    C45_ADDR4:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_address[12];
+	       state <= C45_ADDR5;
+	    end
+	    C45_ADDR5:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_address[11];
+	       state <= C45_ADDR6;
+	    end
+	    C45_ADDR6:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_address[10];
+	       state <= C45_ADDR7;
+	    end
+	    C45_ADDR7:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_address[9];
+	       state <= C45_ADDR8;
+	    end
+	    C45_ADDR8:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_address[8];
+	       state <= C45_ADDR9;
+	    end
+	    C45_ADDR9:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_address[7];
+	       state <= C45_ADDR10;
+	    end
+	    C45_ADDR10:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_address[6];
+	       state <= C45_ADDR11;
+	    end
+	    C45_ADDR11:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_address[5];
+	       state <= C45_ADDR12;
+	    end
+	    C45_ADDR12:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_address[4];
+	       state <= C45_ADDR13;
+	    end
+	    C45_ADDR13:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_address[3];
+	       state <= C45_ADDR14;
+	    end
+	    C45_ADDR14:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_address[2];
+	       state <= C45_ADDR15;
+	    end
+	    C45_ADDR15:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_address[1];
+	       state <= C45_ADDR16;
+	    end
+	    C45_ADDR16:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_address[0];
+	       state <= PREIDLE;
+	       mdio_done <= 1;	       
+	    end
+	    //
+	    // PREIDLE allows the mdio_running bit to reset.
+	    //
+	    PREIDLE: begin
+	       state <= IDLE;
+	    end
+	  endcase // case(state)
+	  
+       end // if (mdc_falling_edge)
+
+   
+endmodule
+
diff --git a/fpga/usrp3/lib/simple_gemac/rxmac_to_ll8.v b/fpga/usrp3/lib/simple_gemac/rxmac_to_ll8.v
new file mode 100644
index 000000000..6c452a9eb
--- /dev/null
+++ b/fpga/usrp3/lib/simple_gemac/rxmac_to_ll8.v
@@ -0,0 +1,62 @@
+//
+// Copyright 2011 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+
+module rxmac_to_ll8
+  (input clk, input reset, input clear,
+   input [7:0] rx_data, input rx_valid, input rx_error, input rx_ack,
+   output [7:0] ll_data, output ll_sof, output ll_eof, output ll_error, output ll_src_rdy, input ll_dst_rdy );
+
+   reg [2:0] xfer_state;
+
+   localparam XFER_IDLE     = 0;
+   localparam XFER_ACTIVE   = 1;
+   localparam XFER_ERROR    = 2;
+   localparam XFER_ERROR2   = 3;
+   localparam XFER_OVERRUN  = 4;
+   localparam XFER_OVERRUN2 = 5;
+      
+   assign ll_data 	    = rx_data;
+   assign ll_src_rdy 	    = ((rx_valid & (xfer_state != XFER_OVERRUN2) )
+			       | (xfer_state == XFER_ERROR) 
+			       | (xfer_state == XFER_OVERRUN));
+   assign ll_sof 	    = ((xfer_state==XFER_IDLE)|(xfer_state==XFER_ERROR)|(xfer_state==XFER_OVERRUN));
+   assign ll_eof 	    = (rx_ack | (xfer_state==XFER_ERROR) | (xfer_state==XFER_OVERRUN));
+   assign ll_error 	    = (xfer_state == XFER_ERROR)|(xfer_state==XFER_OVERRUN);
+   
+   always @(posedge clk)
+     if(reset | clear)
+       xfer_state 	   <= XFER_IDLE;
+     else
+       case(xfer_state)
+	 XFER_IDLE :
+	   if(rx_valid)
+	     xfer_state <= XFER_ACTIVE;
+	 XFER_ACTIVE :
+	   if(rx_error)
+	     xfer_state <= XFER_ERROR;
+	   else if(~rx_valid)
+	     xfer_state <= XFER_IDLE;
+	   else if(~ll_dst_rdy)
+	     xfer_state <= XFER_OVERRUN;
+	 XFER_ERROR :
+	   if(ll_dst_rdy)
+	     xfer_state <= XFER_ERROR2;
+	 XFER_ERROR2 :
+	   if(~rx_error)
+	     xfer_state <= XFER_IDLE;
+	 XFER_OVERRUN :
+	   if(ll_dst_rdy)
+	     xfer_state <= XFER_OVERRUN2;
+	 XFER_OVERRUN2 :
+	   if(~rx_valid)
+	     xfer_state <= XFER_IDLE;
+       endcase // case (xfer_state)
+
+   
+endmodule // rxmac_to_ll8
diff --git a/fpga/usrp3/lib/simple_gemac/simple_gemac.v b/fpga/usrp3/lib/simple_gemac/simple_gemac.v
new file mode 100644
index 000000000..46bc518fc
--- /dev/null
+++ b/fpga/usrp3/lib/simple_gemac/simple_gemac.v
@@ -0,0 +1,72 @@
+//
+// Copyright 2011 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+
+module simple_gemac
+  (input clk125, input reset,
+   // GMII
+   output GMII_GTX_CLK, output GMII_TX_EN, output GMII_TX_ER, output [7:0] GMII_TXD,
+   input GMII_RX_CLK, input GMII_RX_DV, input GMII_RX_ER, input [7:0] GMII_RXD,
+
+   // Flow Control Interface
+   input pause_req, input [15:0] pause_time_req, input pause_respect_en,
+
+   // Settings
+   input [47:0] ucast_addr, input [47:0] mcast_addr,
+   input pass_ucast, input pass_mcast, input pass_bcast, input pass_pause, input pass_all,
+   
+   // RX Client Interface
+   output rx_clk, output [7:0] rx_data, output rx_valid, output rx_error, output rx_ack,
+
+   // TX Client Interface
+   output tx_clk, input [7:0] tx_data, input tx_valid, input tx_error, output tx_ack,
+
+   output [31:0] debug
+   );
+
+   localparam SGE_IFG 		     = 8'd12;  // 12 should be the absolute minimum
+
+   wire rst_rxclk, rst_txclk;   
+   reset_sync reset_sync_tx (.clk(tx_clk),.reset_in(reset),.reset_out(rst_txclk));
+   reset_sync reset_sync_rx (.clk(rx_clk),.reset_in(reset),.reset_out(rst_rxclk));
+
+   wire [15:0] pause_quanta_rcvd;
+   wire        pause_rcvd, pause_apply, paused;
+   
+   simple_gemac_tx simple_gemac_tx
+     (.clk125(clk125),.reset(rst_txclk),
+      .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),
+      .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
+      .tx_clk(tx_clk), .tx_data(tx_data), .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack),
+      .ifg(SGE_IFG), .mac_addr(ucast_addr),
+      .pause_req(pause_req), .pause_time(pause_time_req),  // We request flow control
+      .pause_apply(pause_apply), .paused(paused)  // We respect flow control
+      );
+
+   simple_gemac_rx simple_gemac_rx
+     (.reset(rst_rxclk),
+      .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), 
+      .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
+      .rx_clk(rx_clk), .rx_data(rx_data), .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack),
+      .ucast_addr(ucast_addr), .mcast_addr(mcast_addr),
+      .pass_ucast(pass_ucast), .pass_mcast(pass_mcast), .pass_bcast(pass_bcast), 
+      .pass_pause(pass_pause), .pass_all(pass_all),
+      .pause_quanta_rcvd(pause_quanta_rcvd), .pause_rcvd(pause_rcvd),
+      .debug(debug)
+      );
+
+   flow_ctrl_tx flow_ctrl_tx
+     (.rst(rst_txclk), .tx_clk(tx_clk),
+      .tx_pause_en(pause_respect_en),
+      .pause_quanta(pause_quanta_rcvd), // 16 bit value
+      .pause_quanta_val(pause_rcvd),
+      .pause_apply(pause_apply),
+      .paused(paused)
+      );
+
+endmodule // simple_gemac
diff --git a/fpga/usrp3/lib/simple_gemac/simple_gemac_rx.v b/fpga/usrp3/lib/simple_gemac/simple_gemac_rx.v
new file mode 100644
index 000000000..d63233b1b
--- /dev/null
+++ b/fpga/usrp3/lib/simple_gemac/simple_gemac_rx.v
@@ -0,0 +1,185 @@
+//
+// Copyright 2011 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+
+
+module simple_gemac_rx
+  (input reset,
+   input GMII_RX_CLK, input GMII_RX_DV, input GMII_RX_ER, input [7:0] GMII_RXD,
+   output rx_clk, output [7:0] rx_data, output reg rx_valid, output rx_error, output reg rx_ack,
+   input [47:0] ucast_addr, input [47:0] mcast_addr, 
+   input pass_ucast, input pass_mcast, input pass_bcast, input pass_pause, input pass_all,
+   output reg [15:0] pause_quanta_rcvd, output pause_rcvd,
+   output [31:0] debug );
+
+   localparam RX_IDLE 		  = 0;
+   localparam RX_PREAMBLE 	  = 1;
+   localparam RX_FRAME 		  = 2;
+   localparam RX_GOODFRAME 	  = 3;
+   localparam RX_DO_PAUSE 	  = 4;
+   localparam RX_ERROR 		  = 5;
+   localparam RX_DROP 		  = 6;
+
+   localparam RX_PAUSE 		  = 16;
+   localparam RX_PAUSE_CHK88 	  = RX_PAUSE + 5;
+   localparam RX_PAUSE_CHK08 	  = RX_PAUSE_CHK88 + 1;
+   localparam RX_PAUSE_CHK00 	  = RX_PAUSE_CHK08 + 1;
+   localparam RX_PAUSE_CHK01 	  = RX_PAUSE_CHK00 + 1;
+   localparam RX_PAUSE_STORE_MSB  = RX_PAUSE_CHK01 + 1;
+   localparam RX_PAUSE_STORE_LSB  = RX_PAUSE_STORE_MSB + 1;
+   localparam RX_PAUSE_WAIT_CRC   = RX_PAUSE_STORE_LSB + 1;
+   
+   reg [7:0] 	     rxd_d1;
+   reg rx_dv_d1, rx_er_d1;
+   assign rx_clk     = GMII_RX_CLK;
+   
+   always @(posedge rx_clk)
+     begin
+	rx_dv_d1    <= GMII_RX_DV;
+	rx_er_d1    <= GMII_RX_ER;
+	rxd_d1 	    <= GMII_RXD;
+     end
+
+   reg [7:0] rx_state;
+   wire [7:0] rxd_del;
+   wire rx_dv_del, rx_er_del;
+   reg go_filt;
+   
+   wire match_crc;
+   wire clear_crc 	 = rx_state == RX_IDLE;
+   wire calc_crc 	 = (rx_state == RX_FRAME) | rx_state[7:4]==4'h1;
+
+   localparam DELAY  = 6;
+   delay_line #(.WIDTH(10)) rx_delay
+     (.clk(rx_clk), .delay(DELAY), .din({rx_dv_d1,rx_er_d1,rxd_d1}),.dout({rx_dv_del,rx_er_del,rxd_del}));
+
+   always @(posedge rx_clk)
+     if(reset)
+       rx_ack 	   <= 0;
+     else
+       rx_ack <= (rx_state == RX_GOODFRAME);
+
+   wire is_ucast, is_bcast, is_mcast, is_pause, is_any_ucast;
+   wire keep_packet  = (pass_all & is_any_ucast) | (pass_ucast & is_ucast) | (pass_mcast & is_mcast) | 
+	(pass_bcast & is_bcast) | (pass_pause & is_pause);
+      
+   assign rx_data   = rxd_del;
+   assign rx_error  = (rx_state == RX_ERROR);
+
+   always @(posedge rx_clk)
+     if(reset)
+       rx_valid <= 0;
+     else if(keep_packet)
+       rx_valid <= 1;
+     else if((rx_state == RX_IDLE)|(rx_state == RX_ERROR))
+       rx_valid <= 0;
+   
+   address_filter af_ucast (.clk(rx_clk), .reset(reset), .go(go_filt), .data(rxd_d1),
+			    .address(ucast_addr), .match(is_ucast), .done());
+   address_filter af_mcast (.clk(rx_clk), .reset(reset), .go(go_filt), .data(rxd_d1),
+			    .address(mcast_addr), .match(is_mcast), .done());
+   address_filter af_bcast (.clk(rx_clk), .reset(reset), .go(go_filt), .data(rxd_d1),
+			    .address(48'hFFFF_FFFF_FFFF), .match(is_bcast), .done());
+   address_filter af_pause (.clk(rx_clk), .reset(reset), .go(go_filt), .data(rxd_d1),
+			    .address(48'h0180_c200_0001), .match(is_pause), .done());
+   address_filter_promisc af_promisc (.clk(rx_clk), .reset(reset), .go(go_filt), .data(rxd_d1),
+				      .match(is_any_ucast), .done());
+
+   always @(posedge rx_clk)
+     go_filt 			 <= (rx_state==RX_PREAMBLE) & (rxd_d1 == 8'hD5);
+
+   reg [15:0] pkt_len_ctr;
+   always @(posedge rx_clk)
+     if(reset |(rx_state == RX_IDLE))
+       pkt_len_ctr 	<= 0;
+     else
+       pkt_len_ctr 	<= pkt_len_ctr + 1;
+
+   localparam MIN_PAUSE_LEN = 71;  // 6
+   wire pkt_long_enough  = (pkt_len_ctr >= MIN_PAUSE_LEN);
+   always @(posedge rx_clk)
+     if(reset)
+       rx_state 	<= RX_IDLE;
+     else
+       if(rx_er_d1 & ~((rxd_d1==8'h0F)&(~rx_dv_d1)))  //Handle odd-length pkts from Xilinx IP.
+	 rx_state 	<= RX_ERROR;
+       else
+	 case(rx_state)
+	   RX_IDLE :
+	     if(rx_dv_d1)
+	       if(rxd_d1 == 8'h55)
+		 rx_state   <= RX_PREAMBLE;
+	       else
+		 rx_state   <= RX_ERROR;
+	   RX_PREAMBLE :
+	     if(~rx_dv_d1)
+	       rx_state   <= RX_ERROR;
+	     else if(rxd_d1 == 8'hD5)
+	       rx_state   <= RX_FRAME;
+	     else if(rxd_d1 != 8'h55)
+	       rx_state   <= RX_ERROR;
+	   RX_FRAME :
+	     if(is_pause)
+	       rx_state <= RX_PAUSE;
+	     else if(~rx_dv_d1)
+	       if(match_crc)
+		 rx_state <= RX_GOODFRAME;
+	       else
+		 rx_state <= RX_ERROR;
+	   RX_PAUSE_CHK88 :
+	     if(rxd_d1 != 8'h88)
+	       rx_state <= RX_DROP;
+	     else
+	       rx_state <= RX_PAUSE_CHK08;
+	   RX_PAUSE_CHK08 :
+	     if(rxd_d1 != 8'h08)
+	       rx_state <= RX_DROP;
+	     else
+	       rx_state <= RX_PAUSE_CHK00;
+	   RX_PAUSE_CHK00 :
+	     if(rxd_d1 != 8'h00)
+	       rx_state <= RX_DROP;
+	     else
+	       rx_state <= RX_PAUSE_CHK01;
+	   RX_PAUSE_CHK01 :
+	     if(rxd_d1 != 8'h01)
+	       rx_state <= RX_DROP;
+	     else
+	       rx_state <= RX_PAUSE_STORE_MSB;
+	   RX_PAUSE_WAIT_CRC :
+	     if(pkt_long_enough)
+	       if(match_crc)
+		 rx_state <= RX_DO_PAUSE;
+	       else
+		 rx_state <= RX_DROP;
+	   RX_DO_PAUSE :
+	     rx_state <= RX_IDLE;
+	   RX_GOODFRAME :
+	     rx_state <= RX_IDLE;
+	   RX_DROP, RX_ERROR :
+	     if(~rx_dv_d1)
+	       rx_state <= RX_IDLE;
+	   default
+	     rx_state <= rx_state + 1;
+	 endcase // case (rx_state)
+
+   assign pause_rcvd = (rx_state == RX_DO_PAUSE);
+   crc crc_check(.clk(rx_clk),.reset(reset),.clear(clear_crc),
+		 .data(rxd_d1),.calc(calc_crc),.crc_out(),.match(match_crc));
+
+   always @(posedge rx_clk)
+     if(reset)
+       pause_quanta_rcvd <= 0;
+     else if(rx_state == RX_PAUSE_STORE_MSB)
+       pause_quanta_rcvd[15:8] <= rxd_d1;
+     else if(rx_state == RX_PAUSE_STORE_LSB)
+       pause_quanta_rcvd[7:0] <= rxd_d1;
+   
+   assign debug = rx_state;
+   
+endmodule // simple_gemac_rx
diff --git a/fpga/usrp3/lib/simple_gemac/simple_gemac_tb.v b/fpga/usrp3/lib/simple_gemac/simple_gemac_tb.v
new file mode 100644
index 000000000..c65db6c98
--- /dev/null
+++ b/fpga/usrp3/lib/simple_gemac/simple_gemac_tb.v
@@ -0,0 +1,208 @@
+//
+// Copyright 2011 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+
+
+module simple_gemac_tb;
+`include "eth_tasks.v"
+     
+   reg clk = 0;
+   reg reset = 1;
+
+   initial #1000 reset = 0;
+   always #50 clk = ~clk;
+
+   wire GMII_RX_DV, GMII_RX_ER, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK;
+   wire [7:0] GMII_RXD, GMII_TXD;
+
+   wire rx_valid, rx_error, rx_ack;
+   wire tx_ack, tx_valid, tx_error;
+   
+   wire [7:0] rx_data, tx_data;
+   
+   reg [15:0] pause_time;
+   reg pause_req      = 0;
+
+   wire GMII_RX_CLK   = GMII_GTX_CLK;
+
+   reg [7:0] FORCE_DAT_ERR = 0;
+   reg FORCE_ERR = 0;
+   
+   // Loopback
+   assign GMII_RX_DV  = GMII_TX_EN;
+   assign GMII_RX_ER  = GMII_TX_ER | FORCE_ERR;
+   assign GMII_RXD    = GMII_TXD ^ FORCE_DAT_ERR;
+
+   wire [47:0] ucast_addr = 48'hF1F2_F3F4_F5F6;
+   wire [47:0] mcast_addr = 0;
+   wire        pass_ucast  =1, pass_mcast=0, pass_bcast=1, pass_pause=0, pass_all=0;
+   
+   simple_gemac simple_gemac
+     (.clk125(clk),  .reset(reset),
+      .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),  
+      .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
+      .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),  
+      .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
+      .pause_req(pause_req), .pause_time(pause_time), .pause_en(1),
+      .ucast_addr(ucast_addr), .mcast_addr(mcast_addr),
+      .pass_ucast(pass_ucast), .pass_mcast(pass_mcast), .pass_bcast(pass_bcast), 
+      .pass_pause(pass_pause), .pass_all(pass_all),
+      .rx_clk(rx_clk), .rx_data(rx_data),
+      .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack),
+      .tx_clk(tx_clk), .tx_data(tx_data), 
+      .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack)
+      );
+
+   wire rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy;
+   wire rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2;
+   reg rx_ll_dst_rdy2 = 1;
+   wire [7:0] rx_ll_data, rx_ll_data2;
+   wire rx_ll_error, rx_ll_error2;
+   
+   rxmac_to_ll8 rx_adapt
+     (.clk(clk), .reset(reset), .clear(0),
+      .rx_data(rx_data), .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack),
+      .ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof), .ll_error(rx_ll_error),
+      .ll_src_rdy(rx_ll_src_rdy), .ll_dst_rdy(rx_ll_dst_rdy));
+
+   ll8_shortfifo rx_sfifo
+     (.clk(clk), .reset(reset), .clear(0),
+      .datain(rx_ll_data), .sof_i(rx_ll_sof), .eof_i(rx_ll_eof),
+      .error_i(rx_ll_error), .src_rdy_i(rx_ll_src_rdy), .dst_rdy_o(rx_ll_dst_rdy),
+      .dataout(rx_ll_data2), .sof_o(rx_ll_sof2), .eof_o(rx_ll_eof2),
+      .error_o(rx_ll_error2), .src_rdy_o(rx_ll_src_rdy2), .dst_rdy_i(rx_ll_dst_rdy2));
+
+   wire tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy;
+   reg tx_ll_sof2=0, tx_ll_eof2=0;
+   reg tx_ll_src_rdy2 = 0;
+   wire tx_ll_dst_rdy2;
+   wire [7:0] tx_ll_data;
+   reg [7:0] tx_ll_data2 = 0;
+   wire tx_ll_error;
+   wire tx_ll_error2 = 0;
+
+   ll8_shortfifo tx_sfifo
+     (.clk(clk), .reset(reset), .clear(clear),
+      .datain(tx_ll_data2), .sof_i(tx_ll_sof2), .eof_i(tx_ll_eof2),
+      .error_i(tx_ll_error2), .src_rdy_i(tx_ll_src_rdy2), .dst_rdy_o(tx_ll_dst_rdy2),
+      .dataout(tx_ll_data), .sof_o(tx_ll_sof), .eof_o(tx_ll_eof),
+      .error_o(tx_ll_error), .src_rdy_o(tx_ll_src_rdy), .dst_rdy_i(tx_ll_dst_rdy));
+   
+   ll8_to_txmac ll8_to_txmac
+     (.clk(clk), .reset(reset), .clear(clear),
+      .ll_data(tx_ll_data), .ll_sof(tx_ll_sof), .ll_eof(tx_ll_eof),
+      .ll_src_rdy(tx_ll_src_rdy), .ll_dst_rdy(tx_ll_dst_rdy),
+      .tx_data(tx_data), .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack));
+
+   initial $dumpfile("simple_gemac_tb.vcd");
+   initial $dumpvars(0,simple_gemac_tb);
+
+   integer i; 
+   reg [7:0] pkt_rom[0:65535];
+   reg [1023:0] ROMFile;
+   
+   initial
+     for (i=0;i<65536;i=i+1)
+       pkt_rom[i] <= 8'h0;
+
+   initial
+     begin
+	@(negedge reset);
+	repeat (10)
+	  @(posedge clk);
+	SendFlowCtrl(16'h0007);  // Send flow control
+	@(posedge clk);
+	#30000;
+	@(posedge clk);
+	SendFlowCtrl(16'h0009);  // Increas flow control before it expires
+	#10000;
+	@(posedge clk);
+	SendFlowCtrl(16'h0000);  // Cancel flow control before it expires
+	@(posedge clk); 
+
+	SendPacket_to_ll8(8'hAA,10);    // This packet gets dropped by the filters
+	repeat (10)
+	  @(posedge clk);
+
+ 	SendPacketFromFile_ll8(60,0,0);  // The rest are valid packets
+	repeat (10)
+	  @(posedge clk);
+
+ 	SendPacketFromFile_ll8(61,0,0);
+	repeat (10)
+	  @(posedge clk);
+	SendPacketFromFile_ll8(62,0,0);
+	repeat (10)
+	  @(posedge clk);
+	SendPacketFromFile_ll8(63,0,0);
+	repeat (1)
+	  @(posedge clk);
+	SendPacketFromFile_ll8(64,0,0);
+	repeat (10)
+	  @(posedge clk);
+	SendPacketFromFile_ll8(59,0,0);
+	repeat (1)
+	  @(posedge clk);
+	SendPacketFromFile_ll8(58,0,0);
+	repeat (1)
+	  @(posedge clk);
+	SendPacketFromFile_ll8(100,0,0);
+	repeat (1)
+	  @(posedge clk);
+	SendPacketFromFile_ll8(200,150,30);  // waiting 14 empties the fifo, 15 underruns
+	repeat (1)
+	  @(posedge clk);
+	SendPacketFromFile_ll8(100,0,30);
+	#10000 $finish;
+     end
+
+   // Force a CRC error
+    initial
+     begin
+	#90000;
+	@(posedge clk);
+	FORCE_DAT_ERR <= 8'h10;
+	@(posedge clk);
+	FORCE_DAT_ERR <= 8'h00;
+     end
+
+   // Force an RX_ER error (i.e. link loss)
+   initial
+     begin
+	#116000;
+	@(posedge clk);
+	FORCE_ERR <= 1;
+	@(posedge clk);
+	FORCE_ERR <= 0;
+     end
+
+   // Cause receive fifo to fill, causing an RX overrun
+   initial
+     begin
+	#126000;
+	@(posedge clk);
+	rx_ll_dst_rdy2 <= 0;
+	repeat (30)          // Repeat of 14 fills the shortfifo, but works.  15 overflows
+	  @(posedge clk);
+	rx_ll_dst_rdy2 <= 1;
+     end
+   
+   // Tests: Send and recv flow control, send and receive good packets, RX CRC err, RX_ER, RX overrun, TX underrun
+   // Still need to test: CRC errors on Pause Frames
+   
+   always @(posedge clk)
+     if(rx_ll_src_rdy2 & rx_ll_dst_rdy2)
+       begin
+	  if(rx_ll_sof2 & ~rx_ll_eof2)
+	    $display("RX-PKT-START %d",$time);
+	  $display("RX-PKT SOF %d EOF %d ERR%d DAT %x",rx_ll_sof2,rx_ll_eof2,rx_ll_error2,rx_ll_data2);
+	  if(rx_ll_eof2 & ~rx_ll_sof2)
+	    $display("RX-PKT-END %d",$time);
+       end
+   
+endmodule // simple_gemac_tb
diff --git a/fpga/usrp3/lib/simple_gemac/simple_gemac_tx.v b/fpga/usrp3/lib/simple_gemac/simple_gemac_tx.v
new file mode 100644
index 000000000..555872fdb
--- /dev/null
+++ b/fpga/usrp3/lib/simple_gemac/simple_gemac_tx.v
@@ -0,0 +1,262 @@
+//
+// Copyright 2011 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+
+module simple_gemac_tx
+  (input clk125, input reset,
+   output GMII_GTX_CLK, output reg GMII_TX_EN, output reg GMII_TX_ER, output reg [7:0] GMII_TXD,
+   output tx_clk, input [7:0] tx_data, input tx_valid, input tx_error, output tx_ack,
+   input [7:0] ifg, input [47:0] mac_addr,
+   input pause_req, input [15:0] pause_time,
+   input pause_apply, output reg paused
+   );
+
+   reg tx_en_pre, tx_er_pre;
+   reg [7:0] txd_pre;
+   
+   assign GMII_GTX_CLK 	= clk125;
+   assign tx_clk 	= clk125;
+   
+   reg [7:0] tx_state;
+   reg [7:0] ifg_ctr;
+   reg [15:0] frame_len_ctr;
+   reg [7:0] pause_ctr, pause_dat;
+
+   wire in_ifg 		     = (ifg_ctr != 0);
+
+   wire [31:0] crc_out;
+   
+   localparam TX_IDLE 	     = 0;
+   localparam TX_PREAMBLE    = 1;
+   localparam TX_SOF_DEL     = TX_PREAMBLE + 7;
+   localparam TX_FIRSTBYTE   = TX_SOF_DEL + 1;
+   localparam TX_IN_FRAME    = TX_FIRSTBYTE + 1;
+   localparam TX_IN_FRAME_2  = TX_IN_FRAME + 1;
+   localparam TX_PAD 	     = TX_IN_FRAME_2 + 1;
+   localparam TX_CRC_0 	     = 16;
+   localparam TX_CRC_1 	     = TX_CRC_0 + 1;
+   localparam TX_CRC_2 	     = TX_CRC_0 + 2;
+   localparam TX_CRC_3 	     = TX_CRC_0 + 3;
+   localparam TX_ERROR 	     = 32;
+   localparam TX_PAUSE 	     = 55;
+   localparam TX_PAUSE_SOF   = TX_PAUSE + 7;
+   localparam TX_PAUSE_FIRST = TX_PAUSE_SOF + 1;
+   localparam TX_PAUSE_END   = TX_PAUSE_SOF + 18;
+
+   localparam MIN_FRAME_LEN  = 64 + 8 - 4; // Min frame length includes preamble but not CRC
+   localparam MAX_FRAME_LEN  = 8192;       // How big are the jumbo frames we want to handle?
+   always @(posedge tx_clk)
+     if(reset |(tx_state == TX_IDLE))
+       frame_len_ctr 	    <= 0;
+     else
+       frame_len_ctr 	    <= frame_len_ctr + 1;
+   
+   reg send_pause;
+   reg [15:0] pause_time_held;
+
+   always @(posedge tx_clk)
+     if(reset)
+       send_pause      <= 0;
+     else if(pause_req)
+       send_pause      <= 1;
+     else if(tx_state == TX_PAUSE)
+       send_pause      <= 0;
+
+   always @(posedge tx_clk)
+     if(pause_req)
+       pause_time_held <= pause_time;
+   
+   always @(posedge tx_clk)
+     if(reset)
+       tx_state        <= TX_IDLE;
+     else 
+       case(tx_state)
+	 TX_IDLE :
+	   if(~in_ifg)
+	     if(send_pause)
+	       tx_state <= TX_PAUSE;
+	     else if(tx_valid & ~pause_apply)
+	       tx_state <= TX_PREAMBLE;
+	 TX_FIRSTBYTE :
+	   if(tx_error)
+	     tx_state <= TX_ERROR;   // underrun
+	   else if(~tx_valid)
+	     tx_state <= TX_PAD;
+	   else
+	     tx_state <= TX_IN_FRAME;
+	 TX_IN_FRAME :
+	   if(tx_error)
+	     tx_state <= TX_ERROR;   // underrun
+	   else if(~tx_valid)
+	     tx_state <= TX_PAD;
+	   else if(frame_len_ctr == MIN_FRAME_LEN - 1)
+	     tx_state <= TX_IN_FRAME_2;
+	 TX_IN_FRAME_2 :
+	   if(tx_error)
+	     tx_state <= TX_ERROR;   // underrun
+	   else if(~tx_valid)
+	     tx_state <= TX_CRC_0;
+	 TX_PAD :
+	   if(frame_len_ctr == MIN_FRAME_LEN)
+	     tx_state <= TX_CRC_0;
+	 TX_CRC_3 :
+	   tx_state <= TX_IDLE;
+	 TX_ERROR :
+	   tx_state <= TX_IDLE;
+	 TX_PAUSE_END :
+	   tx_state <= TX_PAD;
+	 default :
+	   tx_state <= tx_state + 1;
+       endcase // case (tx_state)
+
+   always @(posedge tx_clk)
+     if(reset)
+       begin
+	  tx_en_pre <= 0;
+	  tx_er_pre <= 0;
+	  txd_pre   <= 0;
+       end
+     else
+       casex(tx_state)
+	 TX_IDLE :
+	   begin
+	      tx_en_pre <= 0;
+	      tx_er_pre <= 0;
+	      txd_pre <= 0;
+	   end
+	 TX_PREAMBLE, TX_PAUSE :
+	   begin
+	      txd_pre 	 <= 8'h55;
+	      tx_en_pre <= 1;
+	   end
+	 TX_SOF_DEL, TX_PAUSE_SOF :
+	   txd_pre <= 8'hD5;
+	 TX_FIRSTBYTE, TX_IN_FRAME, TX_IN_FRAME_2 :
+	   txd_pre <= tx_valid ? tx_data : 0;
+	 TX_ERROR :
+	   begin
+	      tx_er_pre <= 1;
+	      txd_pre 	 <= 0;
+	   end
+	 TX_CRC_3 :
+	   tx_en_pre <= 0;
+	 TX_PAD :
+	   txd_pre <= 0;
+	 TX_PAUSE_FIRST, 8'b01xx_xxxx :  // In Pause Frame
+	   txd_pre <= pause_dat;
+       endcase // case (tx_state)
+
+   localparam SGE_FLOW_CTRL_ADDR  = 48'h01_80_C2_00_00_01;
+   always @(posedge tx_clk)
+     case(tx_state)
+       TX_PAUSE_SOF :
+	 pause_dat    <= SGE_FLOW_CTRL_ADDR[47:40];  // Note everything must be 1 cycle early
+       TX_PAUSE_SOF + 1:
+	 pause_dat    <= SGE_FLOW_CTRL_ADDR[39:32];
+       TX_PAUSE_SOF + 2:
+	 pause_dat    <= SGE_FLOW_CTRL_ADDR[31:24];
+       TX_PAUSE_SOF + 3:
+	 pause_dat    <= SGE_FLOW_CTRL_ADDR[23:16];
+       TX_PAUSE_SOF + 4:
+	 pause_dat    <= SGE_FLOW_CTRL_ADDR[15:8];
+       TX_PAUSE_SOF + 5:
+	 pause_dat    <= SGE_FLOW_CTRL_ADDR[7:0];
+       TX_PAUSE_SOF + 6:
+	 pause_dat    <= mac_addr[47:40];
+       TX_PAUSE_SOF + 7:
+	 pause_dat    <= mac_addr[39:32];
+       TX_PAUSE_SOF + 8:
+	 pause_dat    <= mac_addr[31:24];
+       TX_PAUSE_SOF + 9:
+	 pause_dat    <= mac_addr[23:16];
+       TX_PAUSE_SOF + 10:
+	 pause_dat    <= mac_addr[15:8];
+       TX_PAUSE_SOF + 11:
+	 pause_dat <= mac_addr[7:0];
+       TX_PAUSE_SOF + 12:
+	 pause_dat <= 8'h88;   // Type = 8808 = MAC ctrl frame
+       TX_PAUSE_SOF + 13:
+	 pause_dat <= 8'h08;
+       TX_PAUSE_SOF + 14:
+	 pause_dat <= 8'h00;   // Opcode = 0001 = PAUSE
+       TX_PAUSE_SOF + 15:
+	 pause_dat <= 8'h01;
+       TX_PAUSE_SOF + 16:
+	 pause_dat <= pause_time_held[15:8];
+       TX_PAUSE_SOF + 17:
+	 pause_dat <= pause_time_held[7:0];
+     endcase // case (tx_state)
+   
+   wire start_ifg   = (tx_state == TX_CRC_3);
+   always @(posedge tx_clk)
+     if(reset)
+       ifg_ctr 	   <= 100;
+     else if(start_ifg)
+       ifg_ctr 	   <= ifg;
+     else if(ifg_ctr != 0)
+       ifg_ctr 	   <= ifg_ctr - 1;
+
+   wire clear_crc   = (tx_state == TX_IDLE);
+
+   wire calc_crc    = 
+	(tx_state==TX_IN_FRAME) |
+	(tx_state==TX_IN_FRAME_2) |
+	(tx_state==TX_PAD) |
+	(tx_state[6]);
+
+   crc crc(.clk(tx_clk), .reset(reset), .clear(clear_crc),
+	    .data(txd_pre), .calc(calc_crc), .crc_out(crc_out));
+
+   assign tx_ack    = (tx_state == TX_FIRSTBYTE);
+
+   always @(posedge tx_clk) 
+     begin
+	GMII_TX_EN <= tx_en_pre;
+	GMII_TX_ER <= tx_er_pre;
+	case(tx_state)
+	  TX_CRC_0 :
+	    GMII_TXD <= crc_out[31:24];
+	  TX_CRC_1 :
+	    GMII_TXD <= crc_out[23:16];
+	  TX_CRC_2 :
+	    GMII_TXD <= crc_out[15:8];
+	  TX_CRC_3 :
+	    GMII_TXD <= crc_out[7:0];
+	  default :
+	    GMII_TXD <= txd_pre;
+	endcase // case (tx_state)
+     end
+
+   // report that we are paused only when we get back to IDLE
+   always @(posedge tx_clk)
+     if(reset)
+       paused 	     <= 0;
+     else if(~pause_apply)
+       paused 	     <= 0;
+     else if(tx_state == TX_IDLE)
+       paused 	     <= 1;
+   
+endmodule // simple_gemac_tx
+
+// Testing code
+/*
+    reg [7:0] crc_ctr;
+   reg calc_crc_d1;
+   always @(posedge tx_clk) 
+     calc_crc_d1 <= calc_crc;
+   
+   always @(posedge tx_clk)
+     if(reset)
+       crc_ctr 	 <= 0;
+     else if(calc_crc)
+       crc_ctr 	 <= crc_ctr+1;
+     else if(calc_crc_d1)
+       $display("CRC COUNT = %d",crc_ctr);
+     else
+       crc_ctr <= 0;
+*/
diff --git a/fpga/usrp3/lib/simple_gemac/simple_gemac_wrapper.build b/fpga/usrp3/lib/simple_gemac/simple_gemac_wrapper.build
new file mode 100755
index 000000000..14e8500b3
--- /dev/null
+++ b/fpga/usrp3/lib/simple_gemac/simple_gemac_wrapper.build
@@ -0,0 +1 @@
+iverilog -Wimplict -Wportbind -y ../fifo/ -y ../models/ -y . -y miim -y ../control -y ../coregen/ -y ../control_lib/ -o simple_gemac_wrapper_tb simple_gemac_wrapper_tb.v
diff --git a/fpga/usrp3/lib/simple_gemac/simple_gemac_wrapper.v b/fpga/usrp3/lib/simple_gemac/simple_gemac_wrapper.v
new file mode 100644
index 000000000..aee2fde4d
--- /dev/null
+++ b/fpga/usrp3/lib/simple_gemac/simple_gemac_wrapper.v
@@ -0,0 +1,185 @@
+//
+// Copyright 2011 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+
+module simple_gemac_wrapper
+  #(parameter RX_FLOW_CTRL=0,
+    parameter PORTNUM=8'd0)
+   (input clk125, input reset,
+    // GMII
+    output GMII_GTX_CLK, output GMII_TX_EN, output GMII_TX_ER, output [7:0] GMII_TXD,
+    input GMII_RX_CLK, input GMII_RX_DV, input GMII_RX_ER, input [7:0] GMII_RXD,
+    
+    // Client FIFO Interfaces
+    input sys_clk,
+    output [63:0] rx_tdata, output [3:0] rx_tuser, output rx_tlast, output rx_tvalid, input rx_tready,
+    input [63:0] tx_tdata, input [3:0] tx_tuser, input tx_tlast, input tx_tvalid, output tx_tready,
+    
+
+    // Wishbone Bus
+    input wb_clk_i, 
+    input wb_rst_i, 
+    input [7:0] wb_adr_i, 
+    input [31:0] wb_dat_i, 
+    input wb_we_i, 
+    input wb_stb_i, 
+    input wb_cyc_i, 
+    output [31:0] wb_dat_o, 
+    output wb_ack_o, 
+    output wb_int_o,
+   
+    // MDIO
+    output mdc, 
+    input mdio_out, 
+    output mdio_tri,
+    output mdio_in,
+
+    // Debug
+    output [31:0] debug_rx,
+    output [31:0] debug_tx
+);
+
+   wire 	  clear = 0;
+   wire [7:0] 	  rx_data, tx_data;
+   wire 	  tx_clk, tx_valid, tx_error, tx_ack;
+   wire 	  rx_clk, rx_valid, rx_error, rx_ack;
+   
+   wire 	  pause_req;
+   wire 	  pause_request_en, pause_respect_en;
+   wire [15:0] 	  pause_time, pause_thresh, pause_time_req, rx_fifo_space;
+
+   wire [31:0] 	  debug_state;
+      
+   wire 	  tx_reset, rx_reset;
+   reset_sync reset_sync_tx (.clk(tx_clk),.reset_in(reset),.reset_out(tx_reset));
+   reset_sync reset_sync_rx (.clk(rx_clk),.reset_in(reset),.reset_out(rx_reset));
+   
+   simple_gemac simple_gemac
+     (.clk125(clk125),  .reset(reset),
+      .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),  
+      .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
+      .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),  
+      .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
+      .pause_req(RX_FLOW_CTRL ? pause_req : 1'b0), .pause_time_req(RX_FLOW_CTRL ? pause_time_req : 16'd0), 
+      .pause_respect_en(pause_respect_en),
+      .ucast_addr(48'h0), .mcast_addr(48'h0),
+      .pass_ucast(1'b0), .pass_mcast(1'b0), .pass_bcast(1'b0), 
+      .pass_pause(1'b0), .pass_all(1'b1),
+      .rx_clk(rx_clk), .rx_data(rx_data),
+      .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack),
+      .tx_clk(tx_clk), .tx_data(tx_data), 
+      .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack),
+      .debug(debug_state)
+      );
+   
+   assign pause_respect_en = 1'b0;
+   assign pause_request_en = 1'b0;
+
+   // /////////////////////////////////////////////////////////////////////////////////////
+   // RX FIFO Chain
+   wire 	  rx_ll_eof, rx_ll_error, rx_ll_src_rdy, rx_ll_dst_rdy;
+   wire [7:0] 	  rx_ll_data;
+   
+   wire [63:0] 	  rx_tdata_int;
+   wire [3:0] 	  rx_tuser_int;
+   wire 	  rx_tlast_int, rx_tvalid_int, rx_tready_int;
+   
+   rxmac_to_ll8 rxmac_to_ll8
+     (.clk(rx_clk), .reset(rx_reset), .clear(0),
+      .rx_data(rx_data), .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack),
+      .ll_data(rx_ll_data), .ll_sof(), .ll_eof(rx_ll_eof), .ll_error(rx_ll_error),  // ignore sof
+      .ll_src_rdy(rx_ll_src_rdy), .ll_dst_rdy(rx_ll_dst_rdy));
+
+   ll8_to_axi64 #(.START_BYTE(6), .LABEL(PORTNUM)) ll8_to_axi64
+     (.clk(rx_clk), .reset(rx_reset), .clear(0),
+      .ll_data(rx_ll_data), .ll_eof(rx_ll_eof), .ll_error(rx_ll_error), .ll_src_rdy(rx_ll_src_rdy), .ll_dst_rdy(rx_ll_dst_rdy),
+      .axi64_tdata(rx_tdata_int), .axi64_tlast(rx_tlast_int), .axi64_tuser(rx_tuser_int),
+      .axi64_tvalid(rx_tvalid_int), .axi64_tready(rx_tready_int));
+   
+   axi64_8k_2clk_fifo rxfifo_2clk
+     (.s_aresetn(~rx_reset),
+      .s_aclk(rx_clk),  .s_axis_tvalid(rx_tvalid_int),  .s_axis_tready(rx_tready_int),
+      .s_axis_tdata(rx_tdata_int),  .s_axis_tlast(rx_tlast_int), .s_axis_tuser(rx_tuser_int),
+      .axis_wr_data_count(),
+      
+      .m_aclk(sys_clk),  .m_axis_tvalid(rx_tvalid),  .m_axis_tready(rx_tready),
+      .m_axis_tdata(rx_tdata),  .m_axis_tlast(rx_tlast), .m_axis_tuser(rx_tuser),
+      .axis_rd_data_count() );
+   
+   // /////////////////////////////////////////////////////////////////////////////////////
+   // TX FIFO Chain
+   wire 	  tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy;
+   wire [7:0] 	  tx_ll_data;
+
+   wire [63:0] 	  tx_tdata_int;
+   wire [3:0] 	  tx_tuser_int;
+   wire 	  tx_tlast_int, tx_tvalid_int, tx_tready_int;
+   
+   axi64_8k_2clk_fifo txfifo_2clk
+     (.s_aresetn(~tx_reset),
+      .s_aclk(sys_clk),  .s_axis_tvalid(tx_tvalid),  .s_axis_tready(tx_tready),
+      .s_axis_tdata(tx_tdata),  .s_axis_tlast(tx_tlast), .s_axis_tuser(tx_tuser),
+      .axis_wr_data_count(),
+      
+      .m_aclk(tx_clk),  .m_axis_tvalid(tx_tvalid_int),  .m_axis_tready(tx_tready_int),
+      .m_axis_tdata(tx_tdata_int),  .m_axis_tlast(tx_tlast_int), .m_axis_tuser(tx_tuser_int),
+      .axis_rd_data_count() );
+   
+   axi64_to_ll8 #(.START_BYTE(6)) axi64_to_ll8
+     (.clk(tx_clk), .reset(tx_reset), .clear(0),
+      .axi64_tdata(tx_tdata_int), .axi64_tlast(tx_tlast_int), .axi64_tuser(tx_tuser_int),
+      .axi64_tvalid(tx_tvalid_int), .axi64_tready(tx_tready_int),
+      .ll_data(tx_ll_data), .ll_eof(tx_ll_eof), .ll_src_rdy(tx_ll_src_rdy), .ll_dst_rdy(tx_ll_dst_rdy));
+   
+   ll8_to_txmac ll8_to_txmac
+     (.clk(tx_clk), .reset(tx_reset), .clear(clear),
+      .ll_data(tx_ll_data), .ll_eof(tx_ll_eof), .ll_src_rdy(tx_ll_src_rdy), .ll_dst_rdy(tx_ll_dst_rdy),
+      .tx_data(tx_data), .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack));
+
+   // /////////////////////////////////////////////////////////////////////////////////////
+   // Flow Control
+   generate
+      if(RX_FLOW_CTRL==1)
+	flow_ctrl_rx flow_ctrl_rx
+	  (.pause_request_en(pause_request_en), .pause_time(pause_time), .pause_thresh(pause_thresh),
+	   .rx_clk(rx_clk), .rx_reset(rx_reset), .rx_fifo_space(rx_fifo_space),
+	   .tx_clk(tx_clk), .tx_reset(tx_reset), .pause_req(pause_req), .pause_time_req(pause_time_req));
+   endgenerate
+
+   assign debug_tx  = { { tx_ll_data },
+			{ 1'b0, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy, 4'b0 },
+			{ tx_valid, tx_error, tx_ack, 5'b0},
+			{ tx_data} };
+   assign debug_rx  = { { rx_ll_data },
+			{ rx_ll_error, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy, 4'b0 },
+			{ rx_valid, rx_error, rx_ack, 5'b0},
+			{ rx_data} };
+
+   //
+   // Wishbone MDIO controller
+   //
+   mdio mdio_gige_inst
+   (
+        .wb_clk_i(wb_clk_i),
+        .wb_rst_i(wb_rst_i),
+        .wb_adr_i(wb_adr_i),
+        .wb_dat_i(wb_dat_i),
+        .wb_we_i(wb_we_i),
+        .wb_stb_i(wb_stb_i),
+        .wb_cyc_i(wb_cyc_i),
+        .wb_dat_o(wb_dat_o),
+        .wb_ack_o(wb_ack_o),
+        .wb_int_o(wb_int_o),
+        .mdc(mdc),
+        .mdio_out(mdio_in), // Switch sense of in and out here for master and slave.
+        .mdio_tri(mdio_tri),
+        .mdio_in(mdio_out) // Switch sense of in and out here for master and slave.
+   );
+
+endmodule // simple_gemac_wrapper
+
diff --git a/fpga/usrp3/lib/simple_gemac/simple_gemac_wrapper_tb.v b/fpga/usrp3/lib/simple_gemac/simple_gemac_wrapper_tb.v
new file mode 100644
index 000000000..b89589234
--- /dev/null
+++ b/fpga/usrp3/lib/simple_gemac/simple_gemac_wrapper_tb.v
@@ -0,0 +1,213 @@
+//
+// Copyright 2011 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+
+
+module simple_gemac_wrapper_tb;
+`include "eth_tasks_f36.v"
+     
+   reg reset   = 1;
+   initial #1000 reset = 0;
+   wire wb_rst 	= reset;
+
+   reg eth_clk     = 0;
+   always #50 eth_clk = ~eth_clk;
+
+   reg wb_clk 	= 0;
+   always #173 wb_clk = ~wb_clk;
+
+   reg sys_clk 	= 0;
+   always #77 sys_clk = ~ sys_clk;
+   
+   wire GMII_RX_DV, GMII_RX_ER, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK;
+   wire [7:0] GMII_RXD, GMII_TXD;
+
+   wire rx_valid, rx_error, rx_ack;
+   wire tx_ack, tx_valid, tx_error;
+   
+   wire [7:0] rx_data, tx_data;
+   
+   wire GMII_RX_CLK   = GMII_GTX_CLK;
+
+   reg [7:0] FORCE_DAT_ERR = 0;
+   reg FORCE_ERR = 0;
+   
+   // Loopback
+   assign GMII_RX_DV  = GMII_TX_EN;
+   assign GMII_RX_ER  = GMII_TX_ER | FORCE_ERR;
+   assign GMII_RXD    = GMII_TXD ^ FORCE_DAT_ERR;
+
+
+   wire [31:0] wb_dat_o;
+   reg [31:0]  wb_dat_i;
+   reg [7:0]   wb_adr;
+   reg 	       wb_stb=0, wb_cyc=0, wb_we=0;
+   wire        wb_ack;
+
+   reg [35:0]  tx_f36_data=0;
+   reg 	       tx_f36_src_rdy = 0;
+   wire        tx_f36_dst_rdy;
+   wire [35:0] rx_f36_data;
+   wire        rx_f36_src_rdy;
+   wire        rx_f36_dst_rdy = 1;
+   
+   simple_gemac_wrapper simple_gemac_wrapper
+     (.clk125(eth_clk),  .reset(reset),
+      .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),  
+      .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
+      .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),  
+      .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
+
+      .sys_clk(sys_clk), .rx_f36_data(rx_f36_data), .rx_f36_src_rdy(rx_f36_src_rdy), .rx_f36_dst_rdy(rx_f36_dst_rdy),
+      .tx_f36_data(tx_f36_data), .tx_f36_src_rdy(tx_f36_src_rdy), .tx_f36_dst_rdy(tx_f36_dst_rdy),
+
+      .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(wb_stb), .wb_cyc(wb_cyc), .wb_ack(wb_ack), .wb_we(wb_we),
+      .wb_adr(wb_adr), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o),
+
+      .mdio(), .mdc(),
+      .debug() );
+   
+   initial $dumpfile("simple_gemac_wrapper_tb.vcd");
+   initial $dumpvars(0,simple_gemac_wrapper_tb);
+
+   integer i; 
+   reg [7:0] pkt_rom[0:65535];
+   reg [1023:0] ROMFile;
+   
+   initial
+     for (i=0;i<65536;i=i+1)
+       pkt_rom[i] <= 8'h0;
+
+   initial
+     begin
+	@(negedge reset);
+	repeat (10)
+	  @(posedge wb_clk);
+	WishboneWR(0,6'b111101); 
+	WishboneWR(4,16'hA0B0);
+	WishboneWR(8,32'hC0D0_A1B1);
+	WishboneWR(12,16'h0000);
+	WishboneWR(16,32'h0000_0000);
+	
+	@(posedge eth_clk);
+	SendFlowCtrl(16'h0007);  // Send flow control
+	@(posedge eth_clk);
+	#30000;
+	@(posedge eth_clk);
+	SendFlowCtrl(16'h0009);  // Increase flow control before it expires
+	#10000;
+	@(posedge eth_clk);
+	SendFlowCtrl(16'h0000);  // Cancel flow control before it expires
+	@(posedge eth_clk); 
+
+	repeat (1000)
+	  @(posedge sys_clk);
+	SendPacket_to_fifo36(32'hA0B0C0D0,10);    // This packet gets dropped by the filters
+	repeat (1000)
+	  @(posedge sys_clk);
+
+	SendPacket_to_fifo36(32'hAABBCCDD,100);    // This packet gets dropped by the filters
+	repeat (10)
+	  @(posedge sys_clk);
+/*
+ 	SendPacketFromFile_f36(60,0,0);  // The rest are valid packets
+	repeat (10)
+	  @(posedge clk);
+
+ 	SendPacketFromFile_f36(61,0,0);
+	repeat (10)
+	  @(posedge clk);
+	SendPacketFromFile_f36(62,0,0);
+	repeat (10)
+	  @(posedge clk);
+	SendPacketFromFile_f36(63,0,0);
+	repeat (1)
+	  @(posedge clk);
+	SendPacketFromFile_f36(64,0,0);
+	repeat (10)
+	  @(posedge clk);
+	SendPacketFromFile_f36(59,0,0);
+	repeat (1)
+	  @(posedge clk);
+	SendPacketFromFile_f36(58,0,0);
+	repeat (1)
+	  @(posedge clk);
+	SendPacketFromFile_f36(100,0,0);
+	repeat (1)
+	  @(posedge clk);
+	SendPacketFromFile_f36(200,150,30);  // waiting 14 empties the fifo, 15 underruns
+	repeat (1)
+	  @(posedge clk);
+	SendPacketFromFile_f36(100,0,30);
+ */
+	#100000 $finish;
+     end
+
+   // Force a CRC error
+    initial
+     begin
+	#90000;
+	@(posedge eth_clk);
+	FORCE_DAT_ERR <= 8'h10;
+	@(posedge eth_clk);
+	FORCE_DAT_ERR <= 8'h00;
+     end
+
+   // Force an RX_ER error (i.e. link loss)
+   initial
+     begin
+	#116000;
+	@(posedge eth_clk);
+	FORCE_ERR <= 1;
+	@(posedge eth_clk);
+	FORCE_ERR <= 0;
+     end
+/*
+   // Cause receive fifo to fill, causing an RX overrun
+   initial
+     begin
+	#126000;
+	@(posedge clk);
+	rx_ll_dst_rdy2 <= 0;
+	repeat (30)          // Repeat of 14 fills the shortfifo, but works.  15 overflows
+	  @(posedge clk);
+	rx_ll_dst_rdy2 <= 1;
+     end
+  */
+   // Tests: Send and recv flow control, send and receive good packets, RX CRC err, RX_ER, RX overrun, TX underrun
+   // Still need to test: CRC errors on Pause Frames, MDIO, wishbone
+
+   task WishboneWR;
+      input [7:0] adr;
+      input [31:0] value;
+      begin
+	 wb_adr   <= adr;
+	 wb_dat_i <= value;
+	 wb_stb   <= 1;
+	 wb_cyc   <= 1;
+	 wb_we 	  <= 1;
+	 while (~wb_ack)
+	   @(posedge wb_clk);
+	 @(posedge wb_clk);
+	 wb_stb <= 0;
+	 wb_cyc <= 0;
+	 wb_we 	<= 0;
+      end
+   endtask // WishboneWR
+   /*
+   always @(posedge clk)
+     if(rx_ll_src_rdy2 & rx_ll_dst_rdy2)
+       begin
+	  if(rx_ll_sof2 & ~rx_ll_eof2)
+	    $display("RX-PKT-START %d",$time);
+	  $display("RX-PKT SOF %d EOF %d ERR%d DAT %x",rx_ll_sof2,rx_ll_eof2,rx_ll_error2,rx_ll_data2);
+	  if(rx_ll_eof2 & ~rx_ll_sof2)
+	    $display("RX-PKT-END %d",$time);
+       end
+   */
+endmodule // simple_gemac_wrapper_tb
diff --git a/fpga/usrp3/lib/simple_gemac/test_packet.mem b/fpga/usrp3/lib/simple_gemac/test_packet.mem
new file mode 100644
index 000000000..7f41d3e42
--- /dev/null
+++ b/fpga/usrp3/lib/simple_gemac/test_packet.mem
@@ -0,0 +1,66 @@
+ff
+ff
+ff
+ff
+ff
+ff
+08
+00
+07
+5c
+2e
+e4
+08
+06
+00
+01
+08
+04
+06
+02
+00
+01
+08
+00
+07
+5c
+2e
+e4
+03
+64
+00
+00
+00
+00
+00
+00
+02
+64
+00
+3a
+f3
+5c
+4f
+12
+01
+10
+00
+01
+00
+00
+00
+00
+00
+00
+20
+41
+42
+41
+08
+00
+AA
+BB
+CC
+DD
+EE
+FF
diff --git a/fpga/usrp3/lib/timing/Makefile.srcs b/fpga/usrp3/lib/timing/Makefile.srcs
new file mode 100644
index 000000000..8d116c064
--- /dev/null
+++ b/fpga/usrp3/lib/timing/Makefile.srcs
@@ -0,0 +1,17 @@
+#
+# Copyright 2013 Ettus Research LLC
+# Copyright 2016 Ettus Research, a National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+##################################################
+# Timing Sources
+##################################################
+TIMING_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/timing/, \
+time_compare.v \
+timekeeper.v \
+pps_generator.v \
+pps_synchronizer.v \
+pulse_generator.v \
+))
diff --git a/fpga/usrp3/lib/timing/pps_generator.v b/fpga/usrp3/lib/timing/pps_generator.v
new file mode 100644
index 000000000..9142c3a48
--- /dev/null
+++ b/fpga/usrp3/lib/timing/pps_generator.v
@@ -0,0 +1,29 @@
+//
+// Copyright 2015 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module pps_generator #(
+   parameter CLK_FREQ   = 32'd10_000_000, //Min:10kHz, Max:4GHz
+   parameter DUTY_CYCLE = 25
+) (
+   input  clk,
+   input  reset,
+   output pps
+);
+    reg [31:0] count;
+
+    always @(posedge clk) begin
+        if (reset) begin
+            count <= 32'd0;
+        end else if (count >= CLK_FREQ - 1) begin
+            count <= 32'd0;
+        end else begin
+            count <= count + 32'd1;
+        end
+    end
+
+    assign pps = (count < ((CLK_FREQ / 100) * DUTY_CYCLE));
+endmodule //pps_generator
diff --git a/fpga/usrp3/lib/timing/pps_synchronizer.v b/fpga/usrp3/lib/timing/pps_synchronizer.v
new file mode 100644
index 000000000..c984e9c86
--- /dev/null
+++ b/fpga/usrp3/lib/timing/pps_synchronizer.v
@@ -0,0 +1,42 @@
+//
+// Copyright 2015 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module pps_synchronizer
+(
+   input      ref_clk,
+   input      timebase_clk,
+   input      pps_in,
+   output     pps_out,
+   output reg pps_count
+);
+   wire pps_refclk;
+   reg  pps_out_del;
+
+   //The input pps is treated an as async signal and is first synchronized
+   //to a common reference clock shared between multiple devices. It is then
+   //synchronized to the timebase clock which counts up the VITA time.
+   //The reference clock frequency must be equal to or smaller than the 
+   //timebase clock frequency to remove any time ambiguity.
+
+   //For robust synchronization across FPGA builds, the async delay for pps_in
+   //must be constrained along with the clock delay (or meet static timing there).
+   //The path length between the two synchronizers must also be constrained
+   synchronizer #(.INITIAL_VAL(1'b0), .FALSE_PATH_TO_IN(0)) pps_sync_refclk_inst (
+      .clk(ref_clk), .rst(1'b0 /* no reset */), .in(pps_in), .out(pps_refclk));
+
+   synchronizer #(.INITIAL_VAL(1'b0), .FALSE_PATH_TO_IN(0)) pps_sync_tbclk_inst (
+      .clk(timebase_clk), .rst(1'b0 /* no reset */), .in(pps_refclk), .out(pps_out));
+
+   //Implement a 1-bit counter to detect PPS edges
+   always @(posedge timebase_clk)
+      pps_out_del <= pps_out;
+
+   always @(posedge timebase_clk)
+      if (~pps_out_del && pps_out)
+         pps_count <= ~pps_count;
+
+endmodule //pps_synchronizer
diff --git a/fpga/usrp3/lib/timing/pulse_generator.v b/fpga/usrp3/lib/timing/pulse_generator.v
new file mode 100644
index 000000000..12a98f5aa
--- /dev/null
+++ b/fpga/usrp3/lib/timing/pulse_generator.v
@@ -0,0 +1,29 @@
+//
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: pulse_generator
+// Description:
+// Generates pulses of a given width at intervals of a given period based on
+// a given input clock.
+
+module pulse_generator #(parameter WIDTH = 32) (
+  input  wire             clk,          /* clock */
+  input  wire             reset,        /* reset */
+  input  wire [WIDTH-1:0] period,       /* period, in clk cycles */
+  input  wire [WIDTH-1:0] pulse_width,  /* pulse width, in clk cycles */
+  output reg              pulse         /* pulse */
+);
+  reg [WIDTH-1:0] count = 0;
+
+  always @(posedge clk) begin
+    if (reset | count <= 1)
+      count <= period;
+    else
+      count <= count - 1;
+
+    pulse <= (count > (period - pulse_width));
+  end
+
+endmodule //pulse_generator
diff --git a/fpga/usrp3/lib/timing/time_compare.v b/fpga/usrp3/lib/timing/time_compare.v
new file mode 100644
index 000000000..60b472d05
--- /dev/null
+++ b/fpga/usrp3/lib/timing/time_compare.v
@@ -0,0 +1,54 @@
+//
+// Copyright 2011-2012 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+
+// 64 bits worth of ticks
+//
+// Not concerned with clock wrapping, human race will likely have extermintated it's self by this time.
+//
+
+module time_compare
+  (
+   input clk,
+   input reset,
+   input [63:0] time_now,
+   input [63:0] trigger_time,
+   output now,
+   output early,
+   output late,
+   output too_early);
+
+/*
+   reg [63:0] time_diff;
+
+   always @(posedge clk) begin
+        if (reset) begin
+            time_diff <= 64'b0;
+            now <= 1'b0;
+            late <= 1'b0;
+            early <= 1'b0;
+        end
+        else begin
+          time_diff <= trigger_time - time_now;
+          now <= ~(|time_diff);
+          late <= time_diff[63];
+          early <= ~now & ~late;
+       end
+   end
+   //assign now = ~(|time_diff);
+   //assign late = time_diff[63];
+   //assign early = ~now & ~late;
+   assign too_early = 0; //not implemented
+*/
+
+    assign now = time_now == trigger_time;
+    assign late = time_now > trigger_time;
+    assign early = ~now & ~late;
+    assign too_early = 0; //not implemented
+
+endmodule // time_compare
diff --git a/fpga/usrp3/lib/timing/timekeeper.v b/fpga/usrp3/lib/timing/timekeeper.v
new file mode 100644
index 000000000..16b7f0fe6
--- /dev/null
+++ b/fpga/usrp3/lib/timing/timekeeper.v
@@ -0,0 +1,87 @@
+//
+// Copyright 2013-2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+module timekeeper
+  #(parameter SR_TIME_HI = 0,
+    parameter SR_TIME_LO = 1,
+    parameter SR_TIME_CTRL = 2,
+    parameter INCREMENT = 64'h1)
+   (input clk, input reset, input pps, input sync_in, input strobe,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    output reg [63:0] vita_time, output reg [63:0] vita_time_lastpps,
+    output reg sync_out);
+
+   //////////////////////////////////////////////////////////////////////////
+   // timer settings for this module
+   //////////////////////////////////////////////////////////////////////////
+   wire [63:0] time_at_next_event;
+   wire set_time_pps, set_time_now, set_time_sync;
+   wire cmd_trigger;
+
+   setting_reg #(.my_addr(SR_TIME_HI), .width(32)) sr_time_hi
+     (.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
+      .out(time_at_next_event[63:32]), .changed());
+
+   setting_reg #(.my_addr(SR_TIME_LO), .width(32)) sr_time_lo
+     (.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
+      .out(time_at_next_event[31:0]), .changed());
+
+   setting_reg #(.my_addr(SR_TIME_CTRL), .width(3)) sr_ctrl
+     (.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
+      .out({set_time_sync, set_time_pps, set_time_now}), .changed(cmd_trigger));
+
+   //////////////////////////////////////////////////////////////////////////
+   // PPS edge detection logic
+   //////////////////////////////////////////////////////////////////////////
+   reg pps_del, pps_del2;
+   always @(posedge clk)
+     {pps_del2,pps_del} <= {pps_del, pps};
+
+   wire pps_edge = !pps_del2 & pps_del;
+
+   //////////////////////////////////////////////////////////////////////////
+   // arm the trigger to latch a new time when the ctrl register is written
+   //////////////////////////////////////////////////////////////////////////
+   reg armed;
+   wire time_event = armed && ((set_time_now) || (set_time_pps && pps_edge) || (set_time_sync && sync_in));
+   always @(posedge clk) begin
+     if (reset) armed <= 1'b0;
+     else if (cmd_trigger) armed <= 1'b1;
+     else if (time_event) armed <= 1'b0;
+   end
+
+   //////////////////////////////////////////////////////////////////////////
+   // vita time tracker - update every tick or when we get an "event"
+   //////////////////////////////////////////////////////////////////////////
+   always @(posedge clk) begin
+     sync_out <= 1'b0;
+     if(reset) begin
+       vita_time <= 64'h0;
+     end else begin
+         if (time_event) begin
+           sync_out <= 1'b1;
+           vita_time <= time_at_next_event;
+         end else if (strobe) begin
+	   vita_time <= vita_time + INCREMENT;
+         end
+     end
+   end
+
+   //////////////////////////////////////////////////////////////////////////
+   // track the time at last pps so host can detect the pps
+   //////////////////////////////////////////////////////////////////////////
+   always @(posedge clk)
+     if(reset)
+       vita_time_lastpps <= 64'h0;
+     else if(pps_edge)
+       if(time_event)
+         vita_time_lastpps <= time_at_next_event;
+       else
+         vita_time_lastpps <= vita_time + INCREMENT;
+
+endmodule // timekeeper
diff --git a/fpga/usrp3/lib/vita_200/.gitignore b/fpga/usrp3/lib/vita_200/.gitignore
new file mode 100644
index 000000000..4ab6ae4ba
--- /dev/null
+++ b/fpga/usrp3/lib/vita_200/.gitignore
@@ -0,0 +1 @@
+*tb
diff --git a/fpga/usrp3/lib/vita_200/Makefile.srcs b/fpga/usrp3/lib/vita_200/Makefile.srcs
new file mode 100644
index 000000000..7ed57cd7c
--- /dev/null
+++ b/fpga/usrp3/lib/vita_200/Makefile.srcs
@@ -0,0 +1,35 @@
+#
+# Copyright 2013 Ettus Research LLC
+# Copyright 2016 Ettus Research, a National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+##################################################
+# VITA Sources
+##################################################
+VITA_200_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/vita_200/, \
+chdr_12sc_to_16sc.v \
+chdr_16sc_to_12sc.v \
+chdr_16sc_to_32f.v \
+chdr_16sc_to_8sc.v \
+chdr_16sc_to_xxxx_chain.v \
+chdr_16s_to_32f.v \
+chdr_16s_to_8s.v \
+chdr_32f_to_16sc.v \
+chdr_32f_to_16s.v \
+chdr_8sc_to_16sc.v \
+chdr_8s_to_16s.v \
+chdr_xxxx_to_16sc_chain.v \
+context_packet_gen.v \
+float_to_iq.v \
+iq_to_float.v \
+new_rx_control.v \
+new_rx_framer.v \
+new_tx_control.v \
+new_tx_deframer.v \
+trigger_context_pkt.v \
+tx_responder.v \
+xxf_to_xxs.v \
+xxs_to_xxf.v \
+))
diff --git a/fpga/usrp3/lib/vita_200/build_12_to_16 b/fpga/usrp3/lib/vita_200/build_12_to_16
new file mode 100755
index 000000000..a897a966e
--- /dev/null
+++ b/fpga/usrp3/lib/vita_200/build_12_to_16
@@ -0,0 +1 @@
+iverilog -y . -y ../dsp/ -y ../control/ -Wall chdr_12sc_to_16sc_tb.v -o chdr_12sc_to_16sc_tb
diff --git a/fpga/usrp3/lib/vita_200/build_16_to_12 b/fpga/usrp3/lib/vita_200/build_16_to_12
new file mode 100755
index 000000000..45e354e9e
--- /dev/null
+++ b/fpga/usrp3/lib/vita_200/build_16_to_12
@@ -0,0 +1 @@
+iverilog -y . -y ../dsp/ -y ../control/ -Wall chdr_16sc_to_12sc_tb.v -o chdr_16sc_to_12sc_tb
diff --git a/fpga/usrp3/lib/vita_200/build_16_to_8 b/fpga/usrp3/lib/vita_200/build_16_to_8
new file mode 100755
index 000000000..9c32aa7cd
--- /dev/null
+++ b/fpga/usrp3/lib/vita_200/build_16_to_8
@@ -0,0 +1,2 @@
+iverilog -y . -y ../dsp/ -y ../control/ -Wall chdr_16sc_to_8sc_tb.v -o chdr_16sc_to_8sc_tb
+
diff --git a/fpga/usrp3/lib/vita_200/build_8_to_16 b/fpga/usrp3/lib/vita_200/build_8_to_16
new file mode 100755
index 000000000..17116b481
--- /dev/null
+++ b/fpga/usrp3/lib/vita_200/build_8_to_16
@@ -0,0 +1,2 @@
+iverilog -y . -y ../dsp/ -y ../control/ -Wall chdr_8sc_to_16sc_tb.v -o chdr_8sc_to_16sc_tb
+
diff --git a/fpga/usrp3/lib/vita_200/chdr_12sc_to_16sc.v b/fpga/usrp3/lib/vita_200/chdr_12sc_to_16sc.v
new file mode 100644
index 000000000..fd7851bf8
--- /dev/null
+++ b/fpga/usrp3/lib/vita_200/chdr_12sc_to_16sc.v
@@ -0,0 +1,179 @@
+//
+// Copyright 2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+
+
+
+
+module chdr_12sc_to_16sc
+  #(parameter BASE = 0)
+   ( input set_stb, input [7:0] set_addr, input [31:0] set_data,
+     //input side of device
+     input 	       clk, input reset,
+     input [63:0]      i_tdata,
+     input 	       i_tlast,
+     input 	       i_tvalid,
+     output 	       i_tready,
+     //output side of device
+     output reg [63:0] o_tdata,
+     output 	       o_tlast,
+     output 	       o_tvalid,
+     input 	       o_tready,
+
+     output [31:0]     debug
+     );
+   
+
+   
+   
+   
+   wire 	       chdr_has_hdr = 1'b1;
+   wire 	       chdr_has_time = i_tdata[61];
+   wire 	       chdr_has_tlr = 1'b0;
+
+   wire [15:0] 	       chdr_header_lines = chdr_has_time? 16 : 8;  
+   wire [15:0] 	       just_samples_in = i_tdata[47:32] - chdr_header_lines;
+
+   //calculating output length based on input ( 4/3*input = output)
+
+   wire [30:0] 	       calc_output_len = ({just_samples_in,14'h0} + {just_samples_in,12'h0} + {just_samples_in,10'h0} + {just_samples_in,8'h0} + {just_samples_in,6'h0} + {just_samples_in,4'h0} + {just_samples_in,2'h0}+{just_samples_in} +'b0001000000000000)<<2;
+
+   wire [15:0] 	       samples = calc_output_len[30:16];
+   wire [15:0] 	       chdr_payload_lines = samples + chdr_header_lines;
+   
+
+   reg 		       has_exline;
+   reg 		       in_exline;
+   
+   
+   
+   wire 	       set_sid;
+   wire [15:0] 	       my_newhome;
+   
+
+   setting_reg #(.my_addr(BASE), .width(17)) new_destination
+     (.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
+      .out({set_sid, my_newhome[15:0]}));
+
+   localparam HEADER = 3'd0; // IDLE
+   localparam TIME     = 3'd1;
+   localparam ODD_LINE_ZERO = 3'd2;
+   localparam EVEN_LINE_ONE = 3'd3;
+   localparam ODD_LINE_TWO = 3'd4;
+   localparam EVEN_LINE_THREE = 3'd5;
+   
+   reg [2:0] 	       state;
+
+   
+
+   always @(posedge clk) begin
+      
+      if (reset) begin
+         state <= HEADER;	 
+      end
+      
+      else if (o_tvalid && o_tready) case(state)
+
+
+				       HEADER: begin
+					  has_exline <= ( (samples[4:2] == 5) || (samples[4:2] == 7) || (samples[4:2] == 0));
+					  state <= (chdr_has_time)? TIME : ODD_LINE_ZERO;
+				       end
+				       
+				       TIME: begin
+					  state <= (i_tlast)? HEADER: ODD_LINE_ZERO; 
+				       end
+
+				       ODD_LINE_ZERO: begin
+					  if ((i_tlast & !has_exline) || in_exline) begin
+					     state <= HEADER;
+					     in_exline <= 0;
+					  end
+					  else if (i_tlast & has_exline) begin
+					     in_exline <= 1;
+					     state <= EVEN_LINE_ONE;
+					  end
+					  else
+					    state <= EVEN_LINE_ONE;
+				       end
+
+				       EVEN_LINE_ONE: begin
+					  if ((i_tlast & !has_exline) || in_exline) begin
+					     state <= HEADER;
+					     in_exline <= 0;
+					  end
+					  else if (i_tlast & has_exline) begin
+					     in_exline <= 1;
+					     state <= ODD_LINE_TWO;
+					  end
+					  else
+					    state <= ODD_LINE_TWO;
+				       end
+				       
+				       ODD_LINE_TWO: begin
+					  if ((i_tlast & !has_exline) || in_exline) begin
+					     state <= HEADER;
+					     in_exline <= 0;
+					  end
+					  else if (i_tlast & has_exline) begin
+					     in_exline <= 1;
+					     state <= EVEN_LINE_THREE;
+					  end
+					  else
+					    state <= EVEN_LINE_THREE;
+				       end 
+				       
+				       EVEN_LINE_THREE: begin
+					  if (in_exline) begin
+					     state <= HEADER;
+					     in_exline <= 0;
+					  end
+					  else
+					    state <= ODD_LINE_ZERO;
+				       end 
+				       
+				       default: state <= HEADER;
+				       
+				     endcase
+   end
+
+
+   //hold data after each input xfer
+   reg [63:0] 	       hold_tdata;
+   always @(posedge clk) begin
+      if (i_tvalid && i_tready) hold_tdata <= i_tdata;
+   end
+
+   //main mux
+   
+   always @(*)
+     case(state)
+
+       HEADER: o_tdata <= {i_tdata[63:48],chdr_payload_lines,
+			   set_sid ? {i_tdata[15:0], my_newhome[15:0]}:i_tdata[31:0]};
+       
+       TIME: o_tdata <= i_tdata;
+       
+       ODD_LINE_ZERO: o_tdata <= {i_tdata[63:52], 4'h0, i_tdata[51:40], 4'h0, i_tdata[39:28],4'h0, i_tdata[27:16], 4'h0};
+       
+       EVEN_LINE_ONE: o_tdata <= {hold_tdata[15:4],4'h0,hold_tdata[3:0],i_tdata[63:56],4'h0,i_tdata[55:44], 4'h0,i_tdata[43:32],4'h0};
+       
+       ODD_LINE_TWO: o_tdata <= {hold_tdata[31:20], 4'h0, hold_tdata[19:8],4'h0, hold_tdata[7:0],i_tdata[63:60],4'h0,i_tdata[59:48],4'h0};
+       
+       EVEN_LINE_THREE: o_tdata <= {hold_tdata[47:36],4'h0,hold_tdata[35:24],4'h0,hold_tdata[23:12],4'h0,hold_tdata[11:0],4'h0};
+       
+
+       default: o_tdata <= i_tdata;
+       
+     endcase
+   
+   assign o_tvalid = (in_exline)? 1'b1: i_tvalid;
+   assign i_tready = (state != EVEN_LINE_THREE) & o_tready & !in_exline;
+   assign o_tlast  = (has_exline)? in_exline: ((state != EVEN_LINE_THREE) && i_tlast);
+
+endmodule
diff --git a/fpga/usrp3/lib/vita_200/chdr_12sc_to_16sc_tb.v b/fpga/usrp3/lib/vita_200/chdr_12sc_to_16sc_tb.v
new file mode 100644
index 000000000..067965543
--- /dev/null
+++ b/fpga/usrp3/lib/vita_200/chdr_12sc_to_16sc_tb.v
@@ -0,0 +1,193 @@
+//
+// Copyright 2016 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+`timescale 1ns/1ps
+
+module chdr_12sc_to_16sc_tb();
+   
+   reg clk = 0;
+   reg reset = 1;
+   //generate clock
+   always #10 clk = ~clk; 
+
+   initial $dumpfile("chdr_12sc_to_16sc_tb.vcd");
+   initial $dumpvars(0,chdr_12sc_to_16sc_tb);
+   
+   //tells when to finish
+   initial
+     begin
+   	#50 reset = 0;
+   	#50000; 
+   	$finish;
+     end
+
+   //setting registers and wire
+   reg [63:0] i_tdata;
+   reg        i_tlast = 0;
+   reg        i_tvalid = 0;
+   wire       i_tready ;
+   reg [7:0]  set_addr;
+   reg [31:0] set_data;
+   reg 	      set_stb;
+   
+
+   wire [63:0] o_tdata;
+   wire        o_tlast;
+   
+   wire	       o_tvalid;
+   reg 	       o_tready;
+
+   chdr_12sc_to_16sc #(.BASE(89))dut
+     (.clk(clk), .reset(reset),
+      .set_data(set_data), .set_stb(set_stb), .set_addr(set_addr),
+      .i_tdata(i_tdata), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready),
+      .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready), .debug());
+   
+   //if you want to feed a bigger input change array sizes here
+
+   reg [63:0]  data[0:11];
+   initial $readmemh("from12_to_x.hex", data);
+
+   //test packet loop
+   task test_packet;
+      input [15:0] len;
+      input [31:0] sid;
+      reg [1:0]    index;
+      
+      begin
+	 index <= 0;
+	 @(posedge clk) ;
+	 //send header 
+   	 i_tdata = {1'b0, 1'b0, 1'b1, 1'b0, 12'h0, (len + 16'd16),sid};
+	 i_tvalid <= 1;
+	 i_tlast <= 0;
+	 @(posedge clk);
+	 while (i_tready != 1)
+	   @(posedge clk);
+	 i_tdata <= {64'b0};
+   	 @(posedge clk);
+	 while (i_tready != 1)
+	   @(posedge clk);
+	 
+	 //-1 for last bit accounting
+	 repeat (len[15:3] + (len[2]|len[1]|len[0]) - 1)
+	   begin
+	      i_tdata <= {data[index]}; 
+   	      index <= index+1;
+	      @(posedge clk);
+	      while (i_tready != 1)
+		@(posedge clk);     
+	   end
+   	 i_tlast <= 1'b1;
+	 i_tdata <= {data[index]}; 
+	 @(posedge clk);
+	 while (i_tready != 1)
+	   @(posedge clk);
+	 
+	 i_tvalid <= 0;
+      end
+   endtask // test_packet
+
+   //test_destination loop
+
+   task test_destination;
+      input enable;
+      input [15:0] dest_home;
+      
+      
+      begin
+         @(posedge clk);
+         
+         set_data <= {enable,dest_home};
+         set_addr <= 89;
+         set_stb <= 1;
+         
+         @(posedge clk);
+         set_stb <= 0;
+      end
+   endtask
+
+
+
+   
+   
+   //main loop	
+   initial
+     begin
+	i_tvalid <= 0;
+	o_tready <= 1;
+	i_tdata <= 0;
+	
+	@(negedge reset);
+	@(posedge clk);
+	@(posedge clk);
+
+
+//testing ending positions
+
+//from 1 to 7 should be line zero
+/*
+	test_destination(1,16'hFEED);
+	test_packet(0, 32'hDEAD_BEEF);
+	#100
+*/
+
+	test_destination(1,16'hFEED);
+	test_packet(3, 32'hDEAD_BEEF);
+	#100
+
+	test_destination(1,16'hFEED);
+	test_packet(6, 32'hDEAD_BEEF);
+	#100
+
+	test_destination(1,16'hFEED);
+	test_packet(9, 32'hDEAD_BEEF);
+	#100
+
+
+
+
+//from 8 to 13 should be line one
+
+	test_destination(1,16'hFEED);
+	test_packet(12, 32'hDEAD_BEEF);
+	#100
+
+	test_destination(1,16'hFEED);
+	test_packet(15, 32'hDEAD_BEEF);
+	#100
+
+	test_destination(1,16'hFEED);
+	test_packet(18, 32'hDEAD_BEEF);
+	#100
+
+	test_destination(1,16'hFEED);
+	test_packet(21, 32'hDEAD_BEEF);
+	#100
+
+	
+	test_destination(1,16'hFEED);
+	test_packet(24, 32'hDEAD_BEEF);
+	
+	#100
+
+	test_destination(1,16'hFEED);
+	test_packet(27, 32'hDEAD_BEEF);
+	  
+
+	
+
+	  
+
+
+	
+
+	
+
+     end
+
+
+
+endmodule
diff --git a/fpga/usrp3/lib/vita_200/chdr_16s_to_32f.v b/fpga/usrp3/lib/vita_200/chdr_16s_to_32f.v
new file mode 100644
index 000000000..2e4ff76d2
--- /dev/null
+++ b/fpga/usrp3/lib/vita_200/chdr_16s_to_32f.v
@@ -0,0 +1,171 @@
+//
+// Copyright 2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module chdr_16s_to_32f #
+(
+  parameter BASE = 0
+)
+(
+  input              clk,
+  input              rst,
+
+  // axi4 stream slave interface
+  input [63:0]       i_tdata,
+  input              i_tvalid,
+  input              i_tlast,
+  output             i_tready,
+
+  // axi4 stream master interface
+  output reg [63:0]  o_tdata,
+  output             o_tvalid,
+  output             o_tlast,
+  input              o_tready,
+
+  // settings bus slave interface
+  input              set_stb,
+  input [7:0]        set_addr,
+  input [31:0]       set_data,
+
+  output [63:0]      debug
+);
+
+  reg [1:0] state;
+  localparam HEADER  = 2'd0;
+  localparam TIME    = 2'd1;
+  localparam ODD     = 2'd2;
+  localparam EVEN    = 2'd3;
+
+  // split up the input for lazyness reasons
+  wire [15:0] fixed0 = i_tdata[63:48];
+  wire [15:0] fixed1 = i_tdata[47:32];
+  wire [15:0] fixed2 = i_tdata[31:16];
+  wire [15:0] fixed3 = i_tdata[15:0];
+
+  // mux the inputs
+  wire [15:0] fixed_muxed0 = (state == ODD) ? fixed0 : fixed2;
+  wire [15:0] fixed_muxed1 = (state == ODD) ? fixed1 : fixed3;
+
+  wire [31:0] float0;
+  wire [31:0] float1;
+
+  // Parametrize the converter as Q15 to IEEE 754 single precision float
+  xxs_to_xxf #
+  (
+    .FBITS(32),
+    .MBITS(23),
+    .EBITS(8),
+    .RADIX(15),
+    .QWIDTH(16)
+  ) q2f0
+  (
+    .i_fixed(fixed_muxed0),
+    .o_float(float0)
+  );
+
+  // Parametrize the converter as Q15 to IEEE 754 single precision float
+  xxs_to_xxf #
+  (
+    .FBITS(32),
+    .MBITS(23),
+    .EBITS(8),
+    .RADIX(15),
+    .QWIDTH(16)
+  ) q2f1
+  (
+    .i_fixed(fixed_muxed1),
+    .o_float(float1)
+  );
+
+  // Make routing (SID) available via settings bus
+  wire        set_sid;
+  wire [15:0] new_sid_dst;
+
+  setting_reg #
+  (
+    .my_addr(BASE),
+    .width(17)
+  ) new_destination
+  ( .clk(clk),
+    .rst(rst),
+    .strobe(set_stb),
+    .addr(set_addr),
+    .in(set_data),
+    .out({set_sid, new_sid_dst[15:0]}),
+    .changed()
+  );
+
+  // Parse CHDR info
+  wire        chdr_has_time = i_tdata[61];
+  // CHDR has either 8 bytes of header or 16 if VITA time is included.
+  wire [15:0] chdr_header_bytes = chdr_has_time ? 16 : 8;
+  // Calculate size of samples input in bytes by taking CHDR size field
+  // and subtracting header length.
+  wire [15:0] sample_byte_count_in = i_tdata[47:32] - chdr_header_bytes;
+  // Calculate size of samples to be EVEN by taking input size
+  // and multiplying by two as sizeof(float) = 2 * sizeof(Q15)
+  wire [15:0] sample_byte_count_out = sample_byte_count_in << 1;
+  // Calculate size of output CHDR packet by adding back header size to new
+  // payload size.
+  wire [15:0] output_chdr_pkt_size = sample_byte_count_out + chdr_header_bytes;
+
+  reg end_on_odd;
+
+  always @(posedge clk)
+    if (rst) begin
+      state <= HEADER;
+      end_on_odd <= 1'b0;
+    end
+
+    else case(state)
+      HEADER:
+        if (o_tready && i_tvalid) begin
+          state <= chdr_has_time ? TIME : ODD;
+          end_on_odd <= |sample_byte_count_in[2:0];
+        end
+
+      TIME:
+        if (o_tready && i_tvalid) begin
+          // If we get a premature end of burst go back
+          // to searching for the start of a new packet.
+          state <= i_tlast ? HEADER : ODD;
+        end
+
+      ODD:
+        if (o_tready && i_tvalid) begin
+          state <= (i_tlast && end_on_odd) ? HEADER : EVEN;
+        end
+
+      EVEN:
+        if (o_tready && i_tvalid) begin
+          state <= i_tlast ? HEADER : ODD;
+        end
+
+      default:
+        state <= HEADER;
+    endcase
+
+  always @(*)
+    case(state)
+      // Populate header with CHDR fields
+      HEADER:
+        o_tdata = {i_tdata[63:48], output_chdr_pkt_size,
+                   set_sid ? {i_tdata[15:0], new_sid_dst[15:0]} : i_tdata[31:0]};
+      TIME:
+        o_tdata = i_tdata;
+      ODD:
+        o_tdata = {float0, float1};
+      EVEN:
+        o_tdata = {float0, float1};
+      default :
+        o_tdata = i_tdata;
+    endcase
+
+  assign o_tvalid  = i_tvalid;
+  assign i_tready  = (o_tready && state != ODD) || (i_tlast && end_on_odd);
+  assign o_tlast   = i_tlast && ((state == EVEN) || (state == ODD) && end_on_odd);
+
+endmodule
diff --git a/fpga/usrp3/lib/vita_200/chdr_16s_to_8s.v b/fpga/usrp3/lib/vita_200/chdr_16s_to_8s.v
new file mode 100644
index 000000000..70507b2a9
--- /dev/null
+++ b/fpga/usrp3/lib/vita_200/chdr_16s_to_8s.v
@@ -0,0 +1,204 @@
+//
+// Copyright 2013, 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+module chdr_16s_to_8s
+#(
+  parameter BASE=0
+)
+(
+  input clk,
+  input rst,
+
+  // axi4 stream slave interface
+  input [63:0]      i_tdata,
+  input             i_tlast,
+  input             i_tvalid,
+  output            i_tready,
+
+  // axi4 stream master interface
+  output reg [63:0] o_tdata,
+  output            o_tlast,
+  output            o_tvalid,
+  input             o_tready,
+
+  // settings bus slave interface
+  input             set_stb,
+  input [7:0]       set_addr,
+  input [31:0]      set_data,
+
+  output [31:0] debug
+);
+
+  // split up for lazyness reasons
+  wire [15:0] fixed0 = i_tdata[63:48];
+  wire [15:0] fixed1 = i_tdata[47:32];
+  wire [15:0] fixed2 = i_tdata[31:16];
+  wire [15:0] fixed3 = i_tdata[15:0];
+
+  wire [7:0] rounded_cur0;
+  wire [7:0] rounded_cur1;
+  wire [7:0] rounded_cur2;
+  wire [7:0] rounded_cur3;
+
+  // Parse CHDR info
+  wire        chdr_has_time = i_tdata[61];
+  // CHDR has either 8 bytes of header or 16 if VITA time is included.
+  wire [15:0] chdr_header_bytes = chdr_has_time ? 16 : 8;
+  // Calculate size of samples input in bytes by taking CHDR size filed
+  // and subtracting header length.
+  wire [15:0] sample_byte_count_in = i_tdata[47:32] - chdr_header_bytes;
+  // Calculate size of samples to be output by taking input size
+  // and dividing by two as sizeof(Q15) = 2*sizeof(Q7)
+  wire [15:0] sample_byte_count_out = sample_byte_count_in >> 1;
+  // Calculate size of output CHDR packet by adding back header size to new
+  // payload size.
+  wire [15:0] output_chdr_pkt_size = sample_byte_count_out + chdr_header_bytes;
+
+  // Make routing (SID) available via settings bus
+  wire        set_sid;
+  wire [15:0] new_sid_dst;
+
+  setting_reg #
+  (
+    .my_addr(BASE),
+    .width(17)
+  )
+  new_destination
+  (
+    .clk(clk),
+    .rst(rst),
+    .strobe(set_stb),
+    .addr(set_addr),
+    .in(set_data),
+    .out({set_sid, new_sid_dst[15:0]}),
+    .changed()
+  );
+
+  wire handshake_ok = o_tready & i_tvalid;
+
+  reg [7:0] rounded_old0;
+  reg [7:0] rounded_old1;
+  reg [7:0] rounded_old2;
+  reg [7:0] rounded_old3;
+
+  // respect your elders, yo
+  always @ (posedge clk)
+    if (rst)
+      {rounded_old0, rounded_old1, rounded_old2, rounded_old3} <= 32'h0;
+    else if (handshake_ok) begin
+      {rounded_old0, rounded_old1} <= {rounded_cur0, rounded_cur1};
+      {rounded_old2, rounded_old3} <= {rounded_cur2, rounded_cur3};
+  end
+
+  localparam HEADER  = 2'd0;
+  localparam TIME    = 2'd1;
+  localparam PREPARE = 2'd2;
+  localparam OUTPUT  = 2'd3;
+
+  reg [1:0] state;
+
+  always @(posedge clk) begin
+    if (rst)
+      state <= HEADER;
+    else case(state)
+      HEADER:
+        // In case we see a i_last we just wait for the
+        // next header here, otherwise move on to the next states
+        if (handshake_ok & !i_tlast)
+          state <= chdr_has_time ? TIME : PREPARE;
+
+      TIME:
+        // If we get a premature end of burst go back
+        // to searching for the start of a new packet
+        if (handshake_ok)
+          state <= i_tlast ? HEADER: PREPARE;
+
+      PREPARE:
+        if (handshake_ok)
+          state <= i_tlast ? HEADER: OUTPUT;
+
+      OUTPUT:
+        if (handshake_ok)
+          state <= i_tlast ? HEADER: PREPARE;
+
+      default:
+        state <= HEADER;
+
+    endcase
+  end
+
+  round #
+  (
+    .bits_in(16),
+    .bits_out(8)
+  )
+  round0
+  (
+    .in(fixed0),
+    .out(rounded_cur0),
+    .err()
+  );
+
+  round #
+  (
+    .bits_in(16),
+    .bits_out(8)
+  )
+  round1
+  (
+    .in(fixed1),
+    .out(rounded_cur1),
+    .err()
+  );
+
+  round #
+  (
+    .bits_in(16),
+    .bits_out(8)
+  )
+  round2
+  (
+    .in(fixed2),
+    .out(rounded_cur2),
+    .err()
+  );
+
+  round #
+  (
+    .bits_in(16),
+    .bits_out(8))
+  round3
+  (
+    .in(fixed3),
+    .out(rounded_cur3),
+    .err()
+  );
+
+  always @(*)
+    case(state)
+      HEADER:
+        o_tdata = {i_tdata[63:48], output_chdr_pkt_size,
+                   set_sid ? {i_tdata[15:0], new_sid_dst[15:0]} : i_tdata[31:0]};
+      TIME:
+        o_tdata = i_tdata;
+      PREPARE:
+        // Here the second half of this stuff is invalid, as the header will
+        // take care of that by setting the correct length field,
+        // we assign the same to simplify the mux
+        o_tdata = {rounded_cur0, rounded_cur1, rounded_cur2, rounded_cur3,
+                   rounded_cur0, rounded_cur1, rounded_cur2, rounded_cur3};
+      OUTPUT:
+        o_tdata = {rounded_old0, rounded_old1, rounded_old2, rounded_old3,
+                   rounded_cur0, rounded_cur1, rounded_cur2, rounded_cur3};
+      default:
+        o_tdata = i_tdata;
+    endcase
+
+   assign o_tvalid = i_tvalid && (state != PREPARE || i_tlast);
+   assign i_tready = o_tready || (state == PREPARE && !i_tlast);
+   assign o_tlast  = i_tlast;
+
+endmodule
diff --git a/fpga/usrp3/lib/vita_200/chdr_16sc_to_12sc.v b/fpga/usrp3/lib/vita_200/chdr_16sc_to_12sc.v
new file mode 100644
index 000000000..7f595ee12
--- /dev/null
+++ b/fpga/usrp3/lib/vita_200/chdr_16sc_to_12sc.v
@@ -0,0 +1,227 @@
+//
+// Copyright 2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+module chdr_16sc_to_12sc
+  #(parameter BASE=0)
+  (
+    // Clocks and resets
+    input               clk,
+    input               reset,
+    // Settings bus
+    input               set_stb,
+    input [7:0]         set_addr,
+    input [31:0]        set_data,
+    // Input CHDR bus
+    input [63:0]        i_tdata,
+    input               i_tlast,
+    input               i_tvalid,
+    output              i_tready,
+    // Output CHDR bus
+    output reg [63:0]   o_tdata,
+    output              o_tlast,
+    output              o_tvalid,
+    input               o_tready,
+    // Debug
+    output [31:0]       debug
+  );
+
+  wire 		chdr_has_time = i_tdata[61];
+
+  wire [11:0]   q0;
+  wire [11:0]   i0;
+  wire [11:0]   q1;
+  wire [11:0]   i1;
+  wire [11:0]   q2;
+  wire [11:0]   i2;
+
+  wire [16:0]   round_q0;
+  wire [16:0]   round_i0;
+  wire [16:0]   round_q1;
+  wire [16:0]   round_i1;
+  wire [16:0]   round_q2;
+  wire [16:0]   round_i2;
+
+  // Pipeline register
+  reg [63:0]    line_buff;
+
+  // CHDR has either 8 bytes of header or 16 if VITA time is included.
+  wire [15:0]   chdr_header_lines = chdr_has_time? 16 : 8;
+  // Calculate size of samples input in bytes by taking CHDR size filed and subtracting header length.
+  wire [15:0]   sample_byte_count_in = i_tdata[47:32] - chdr_header_lines;
+  // Calculate size of samples to be output by taking input size and scaling by 3/4
+  wire [15:0]   sample_byte_count_out = (sample_byte_count_in*3) >> 2;
+  // Calculate size of output CHDR packet by adding back header size to new payload size.
+  wire [15:0]   output_chdr_pkt_size = sample_byte_count_out + chdr_header_lines;
+
+  reg           odd;
+
+  wire          set_sid;
+  wire [15:0]   new_sid_dst;
+
+  setting_reg #(.my_addr(BASE), .width(17)) new_destination
+    (.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
+    .out({set_sid, new_sid_dst[15:0]}));
+
+  // state machine
+
+  localparam    HEADER    = 3'd0;
+  localparam    TIME      = 3'd1;
+  localparam    SAMPLE1   = 3'd2;
+  localparam    SAMPLE2   = 3'd3;
+  localparam    SAMPLE3   = 3'd4;
+  localparam    SAMPLE4   = 3'd5;
+  localparam    RESIDUAL  = 3'd6;
+
+  reg [2:0]     state;
+
+  always @(posedge clk)
+    if (reset) begin
+      state <= HEADER;
+      line_buff <= 0;
+    end else begin
+      case(state)
+        //
+        // Process header
+        // Check for timestamp.  Byte count conversion is done above.
+        //
+        HEADER: begin
+          if (i_tvalid & i_tready) begin
+            odd <= sample_byte_count_in [2];
+            // If the input packet had time, then add time to output packet
+            state <= (i_tdata[61])? TIME: SAMPLE1;
+          end
+        end
+        //
+        // Process time field
+        //
+        TIME: begin
+          if (i_tvalid & i_tready) begin
+            // If we get a premature end of line go back to searching for start of new packet.
+            state <= (i_tlast) ? HEADER: SAMPLE1;
+          end
+        end
+        //
+        // There are 3 lines of output data for each 4 lines of input data.
+        // The 4 sample states below represent the 4 lines of input.
+        // They are repeatedly cycled until all data is consumed.
+        //
+        // Process first line
+        // The 8 bytes are converted to 6 bytes, so there is not enough for an
+        // 8-byte output line.  Store the data unless this is the last line in
+        // the packet.
+        //
+        SAMPLE1: begin
+          if (i_tvalid & i_tready) begin
+            if (i_tlast) begin
+              line_buff <= 0;
+              state <= HEADER;
+            end else begin
+              // Save data to buffer - no output
+              line_buff <= {q0,i0,q1,i1,16'd0};
+              state <= SAMPLE2;
+            end
+          end
+        end
+        //
+        // Process second line
+        // Output a line comprised of the 6 bytes from the fist line and
+        // 2 bytes from this line.  Store the remaining 4 bytes.
+        //
+        SAMPLE2: begin
+          if (i_tvalid & i_tready) begin
+            line_buff <= {i0[7:0],q1,i1,32'd0};
+            state <= i_tlast ? RESIDUAL : SAMPLE3;
+          end
+        end
+        //
+        // Process third line
+        // Output line comprised of the 4 remaining bytes from the second line
+        // and 4 bytes from this line.  Store the remaining 2 bytes unless this
+        // is the last line in the packet and the number of samples is odd.
+        //
+        SAMPLE3: begin
+          if (i_tvalid & i_tready) begin
+            line_buff <= (i_tlast & odd) ? 0 : {q1[3:0],i1,48'd0};
+            if (i_tlast)
+                state <= odd ? HEADER : RESIDUAL;
+            else
+              state <= SAMPLE4;
+          end
+        end
+        //
+        // Process fourth line
+        // Output line comprised of the remaining 2 bytes from the third line
+        // and the 6 bytes from this line.
+        //
+        SAMPLE4: begin
+          if (i_tvalid & i_tready) begin
+            line_buff <= 0;
+            state <= i_tlast ? HEADER : SAMPLE1;
+          end
+        end
+        //
+        // Pause input to output residual data in buffer
+        //
+        RESIDUAL: begin
+          if (o_tvalid & o_tready) begin
+            line_buff <= 0;
+            state <= HEADER;
+          end
+        end
+        //
+        // Should never get here.
+        //
+        default: state <= HEADER;
+
+       endcase
+     end
+
+
+  // Add rounding value into 16bit samples before trunctaion
+  assign	round_q0 = ({i_tdata[63],i_tdata[63:48]} + 'h0008);
+  assign	round_i0 = ({i_tdata[47],i_tdata[47:32]} + 'h0008);
+  // Truncate with saturation to 12bits precision.
+  assign 	q0 = (round_q0[16:15] == 2'b01) ? 12'h7FF : ((round_q0[16:15] == 2'b10) ? 12'h800 : round_q0[15:4]);
+  assign	i0 = (round_i0[16:15] == 2'b01) ? 12'h7FF : ((round_i0[16:15] == 2'b10) ? 12'h800 : round_i0[15:4]);
+  // Add rounding value into 16bit samples before trunctaion
+  assign 	round_q1 = ({i_tdata[31],i_tdata[31:16]} + 'h0008);
+  assign 	round_i1 = ({i_tdata[15],i_tdata[15:0]} + 'h0008);
+  // Truncate with saturation to 12bits precision.
+  assign 	q1 = (round_q1[16:15] == 2'b01) ? 12'h3FF : ((round_q1[16:15] == 2'b10) ? 12'h800 : round_q1[15:4]);
+  assign	i1 = (round_i1[16:15] == 2'b01) ? 12'h3FF : ((round_i1[16:15] == 2'b10) ? 12'h800 : round_i1[15:4]);
+
+  //
+  // Mux Output data
+  //
+  always @(*)
+    case(state)
+      // Populate header with CHDR fields
+      HEADER: o_tdata = {i_tdata[63:48], output_chdr_pkt_size,
+        set_sid ? {i_tdata[15:0], new_sid_dst[15:0]}:i_tdata[31:0]};
+      // Add 64bit VITA time to packet
+      TIME: o_tdata = i_tdata;
+      // Only output if i_tlast in SAMPLE1 state
+      SAMPLE1: o_tdata = {q0,i0,q1, i1, 16'b0};
+      SAMPLE2: o_tdata = {line_buff[63:16], q0, i0[11:8]};
+      SAMPLE3: o_tdata = {line_buff[63:32], q0, i0,q1[11:4]};
+      SAMPLE4: o_tdata = {line_buff[63:48], q0, i0, q1, i1};
+      RESIDUAL: o_tdata = line_buff;
+      default : o_tdata = i_tdata;
+    endcase // case(state)
+
+
+  assign  o_tvalid = state == RESIDUAL || (i_tvalid &&
+                        (state != SAMPLE1 || state == SAMPLE1 && i_tlast));
+
+  assign  i_tready = (o_tready && state != RESIDUAL);
+
+  wire need_extra_line = state == SAMPLE1 || state == SAMPLE2 ||
+                          (state == SAMPLE3 && ~odd);
+  assign  o_tlast = state == RESIDUAL || (i_tlast & ~need_extra_line);
+
+endmodule
diff --git a/fpga/usrp3/lib/vita_200/chdr_16sc_to_12sc_tb.v b/fpga/usrp3/lib/vita_200/chdr_16sc_to_12sc_tb.v
new file mode 100644
index 000000000..607bc448a
--- /dev/null
+++ b/fpga/usrp3/lib/vita_200/chdr_16sc_to_12sc_tb.v
@@ -0,0 +1,170 @@
+//
+// Copyright 2016 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+//Purpose: to test 8 to 16 converter
+`timescale 1ns/1ps
+
+module chdr_16sc_to_12sc_tb();
+   
+   reg clk = 0;
+   reg reset = 1;
+   //generate clock
+   always #10 clk = ~clk; 
+
+   initial $dumpfile("chdr_16sc_to_12sc_tb.vcd");
+   initial $dumpvars(0,chdr_16sc_to_12sc_tb);
+   
+   //tells when to finish
+   initial
+     begin
+   	#50 reset = 0;
+   	#50000; 
+   	$finish;
+     end
+
+   //setting registers and wire
+   reg [63:0] i_tdata;
+   reg        i_tlast = 0;
+   reg        i_tvalid = 0;
+   wire       i_tready ;
+   reg [7:0]  set_addr;
+   reg [31:0] set_data;
+   reg 	      set_stb;
+   
+
+   wire [63:0] o_tdata;
+   wire        o_tlast;
+   
+   wire	       o_tvalid;
+   reg 	       o_tready;
+
+   chdr_16sc_to_12sc #(.BASE(89))dut
+     (.clk(clk), .reset(reset),
+      .set_data(set_data), .set_stb(set_stb), .set_addr(set_addr),
+      .i_tdata(i_tdata), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready),
+      .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready), .debug());
+   
+   //if you want to feed a bigger input change array sizes here
+
+   reg [63:0]  data[0:7];
+   initial $readmemh("from16_to_x.hex", data);
+
+   //test packet loop
+   task test_packet;
+      input [15:0] len;
+      input [31:0] sid;
+      reg [1:0]    index;
+      
+      begin
+	 index <= 0;
+	 @(posedge clk) ;
+	 //send header 
+   	 i_tdata = {1'b0, 1'b0, 1'b1, 1'b0, 12'h0, len + 16'd16,sid};
+	 i_tvalid <= 1;
+	 i_tlast <= 0;
+	 @(posedge clk);
+	 while (i_tready != 1)
+	   @(posedge clk);
+	 i_tdata <= {64'b0};
+   	 @(posedge clk);
+	 while (i_tready != 1)
+	   @(posedge clk);
+	 
+	 //-1 for last bit accounting
+	repeat (len[15:3] + (len[2]|len[1]|len[0]) - 1)
+	   begin
+	      i_tdata <= {data[index]}; 
+   	      index <= index+1;
+	      //while (i_tready != 1)
+		//@(posedge clk);
+	      @(posedge clk);
+	      while (i_tready != 1)
+		@(posedge clk);
+	      
+	   end
+   	 i_tlast <= 1'b1;
+	 i_tdata <= {data[index]}; 
+
+	 @(posedge clk);
+	 while (i_tready != 1)
+	   @(posedge clk);
+	 
+	 i_tvalid <= 0;
+      end
+   endtask // test_packet
+
+   //test_destination loop
+
+   task test_destination;
+      input enable;
+      input [15:0] dest_home;
+      
+      
+      begin
+         @(posedge clk);
+         
+         set_data <= {enable,dest_home};
+         set_addr <= 89;
+         set_stb <= 1;
+         
+         @(posedge clk);
+         set_stb <= 0;
+      end
+   endtask
+
+
+
+   
+   
+   //main loop	
+   initial
+     begin
+	i_tvalid <= 0;
+	o_tready <= 1;
+	
+	i_tdata <= 0;
+	
+	@(negedge reset);
+	@(posedge clk);
+	@(posedge clk);
+
+//end on line one
+//1
+	test_destination(1,16'hFEED);
+	test_packet(4, 32'hDEAD_BEEF);
+//2
+	test_destination(1,16'hFEED);
+	test_packet(8, 32'hDEAD_BEEF);
+//3
+	test_destination(1,16'hFEED);
+	test_packet(12, 32'hDEAD_BEEF);
+//4
+
+	test_destination(1,16'hFEED);
+	test_packet(16, 32'hDEAD_BEEF);
+//5
+	test_destination(1,16'hFEED);
+	test_packet(20, 32'hDEAD_BEEF);
+//6
+	test_destination(1,16'hFEED);
+	test_packet(24, 32'hDEAD_BEEF);
+
+//end on line two 
+
+//7
+
+	test_destination(1,16'hFEED);
+	test_packet(28, 32'hDEAD_BEEF);
+//8
+	
+	test_destination(1,16'hFEED);
+	test_packet(32, 32'hDEAD_BEEF);
+	
+
+     end
+
+
+
+endmodule
diff --git a/fpga/usrp3/lib/vita_200/chdr_16sc_to_32f.v b/fpga/usrp3/lib/vita_200/chdr_16sc_to_32f.v
new file mode 100644
index 000000000..1991b3d31
--- /dev/null
+++ b/fpga/usrp3/lib/vita_200/chdr_16sc_to_32f.v
@@ -0,0 +1,141 @@
+//
+// Copyright 2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+
+
+
+module chdr_16sc_to_32f
+  #(parameter BASE=0)
+   ( input clk, input reset, input set_stb, input [7:0] set_addr,
+    input [31:0]      set_data,
+    input [63:0]      i_tdata,
+    input 	      i_tlast,
+    input 	      i_tvalid,
+    output 	      i_tready,
+
+   
+    output reg [63:0] o_tdata,
+    output 	      o_tlast,
+    output 	      o_tvalid,
+    input 	      o_tready,
+
+    output [31:0]     debug
+    );
+
+
+   wire [31:0] 	      s0_real;
+   wire [31:0] 	      s0_imag;
+   wire [31:0] 	      s1_real;
+   wire [31:0] 	      s1_imag;
+
+
+   wire 	      chdr_has_hdr = 1'b1;
+   wire 	      chdr_has_time = i_tdata[61];
+   wire 	      chdr_has_tlr = 1'b0;
+
+ 	      
+   //chdr length calculations
+
+   wire [15:0] 	      chdr_header_lines = chdr_has_time? 16:8;
+   wire [15:0] 	      samples = ((i_tdata[47:32] - chdr_header_lines) << 1);
+   wire [15:0] 	      i_samples = (i_tdata[47:32] - chdr_header_lines);
+   
+
+   wire [15:0] 	      chdr_payload_lines = samples + chdr_header_lines;
+
+   
+   
+    wire 	      set_sid;
+   wire [15:0] 	      my_newhome;
+
+   setting_reg #(.my_addr(BASE), .width(17)) new_destination
+     (.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),.out({set_sid, my_newhome[15:0]}));
+
+ 
+
+		    
+   
+   //state machines
+   localparam HEADER        = 2'd0;//IDLE
+   localparam TIME          = 2'd1;
+   localparam ODD           = 2'd2;
+   localparam EVEN          = 2'd3;
+   reg [1:0] 	      state;
+   reg      end_on_odd;
+   
+   
+ 	      
+   
+
+   always @(posedge clk) begin
+      
+      
+      if (reset) begin
+	 state <= HEADER;
+	 end_on_odd <= 1'b0;
+      end
+      else if (o_tready && i_tvalid)  case(state)
+
+	     HEADER: begin
+		   state <= (i_tdata[61])? TIME : ODD;
+		   end_on_odd <= (i_samples[2:1] == 2 || i_samples[2:1] == 1);	
+	     end
+
+	     TIME: begin
+		   state <= (i_tlast)? HEADER: ODD;
+	     end
+
+	     ODD: begin
+		   state <= (i_tlast & end_on_odd)? HEADER:EVEN;
+	     end
+
+	     EVEN: begin
+		  state <= (i_tlast) ? HEADER: ODD;
+	     end
+					
+		default: state <= HEADER;
+	   endcase
+   end
+   
+
+ 
+
+   iq_to_float #(.BITS_IN(16), .BITS_OUT(32))
+   iq_to_float_imag0 (.in(i_tdata[63:48]), .out(s0_imag[31:0]));
+   
+   iq_to_float #(.BITS_IN(16), .BITS_OUT(32))
+   iq_to_float_real0 (.in(i_tdata[47:32]), .out(s0_real[31:0]));
+
+   iq_to_float #(.BITS_IN(16), .BITS_OUT(32))
+   iq_to_float_imag1 (.in(i_tdata[31:16]), .out(s1_imag[31:0]));	
+
+   iq_to_float #(.BITS_IN(16), .BITS_OUT(32))
+   iq_to_float_real1 (.in(i_tdata[15:0]), .out(s1_real[31:0]));	
+   
+
+
+
+
+   always @(*) 
+     case(state)
+     
+       HEADER: o_tdata <= {i_tdata[63:48], chdr_payload_lines,
+			  set_sid ? {i_tdata[15:0], my_newhome[15:0]}:i_tdata[31:0]};
+       TIME: o_tdata <= i_tdata;
+       ODD: o_tdata <= {s0_imag,s0_real};
+       EVEN: o_tdata <= {s1_imag,s1_real};
+  
+       
+       default : o_tdata = i_tdata;
+     endcase
+   
+   assign o_tvalid = i_tvalid;
+   assign i_tready = o_tready && ((state != ODD) || (i_tlast && end_on_odd));
+   assign o_tlast  = i_tlast && ((state == EVEN) || (state == ODD && end_on_odd));
+
+endmodule
diff --git a/fpga/usrp3/lib/vita_200/chdr_16sc_to_32f_tb.v b/fpga/usrp3/lib/vita_200/chdr_16sc_to_32f_tb.v
new file mode 100644
index 000000000..eb3273938
--- /dev/null
+++ b/fpga/usrp3/lib/vita_200/chdr_16sc_to_32f_tb.v
@@ -0,0 +1,150 @@
+//
+// Copyright 2016 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+//Purpose: to test 8 to 16 converter
+`timescale 1ns/1ps
+
+module chdr_16sc_to_32f_tb();
+
+   reg clk = 0;
+   reg reset = 1;
+   //generate clock
+   always #10 clk = ~clk; 
+
+   initial $dumpfile("chdr_16sc_to_32f_tb.vcd");
+   initial $dumpvars(0,chdr_16sc_to_32f_tb);
+   
+
+   //tells when to finish
+   initial
+     begin
+   	#50 reset = 0;
+   	#50000; 
+   	$finish;
+     end
+
+   //setting registers and wire
+   reg [63:0] i_tdata;
+   reg        i_tlast = 0;
+   reg        i_tvalid = 0;
+   wire       i_tready ;
+   reg [7:0] set_addr;
+   reg [31:0] set_data;
+   reg set_stb;
+   
+
+   wire [63:0] o_tdata;
+   wire        o_tlast;
+   
+   wire	       o_tvalid;
+   reg 	       o_tready;
+
+   chdr_16sc_to_32f #(.BASE(89))dut
+    (.clk(clk), .reset(reset),
+       .set_data(set_data), .set_stb(set_stb), .set_addr(set_addr),
+      .i_tdata(i_tdata), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready),
+      .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready), .debug());
+   
+
+//change [15:0] to whatever amount of samples you want to test. however float to iq was tested thouroughly independently. so it works
+  reg [15:0]data[0:15];
+  initial $readmemh("iq_to_float_input.txt", data);
+
+//test packet loop
+  task test_packet;
+      input [15:0] len;
+      input [31:0] sid;
+      reg [3:0] index;
+            
+      begin
+
+	  index <= 0;
+	 
+	 
+	 @(posedge clk);
+	 //send header 
+   	 i_tdata <= {1'b0, 1'b0, 1'b1, 1'b0, 12'h0, (len + 16'd16),sid};
+	 i_tvalid <= 1;
+	 i_tlast <= 0;
+	 
+	 @(posedge clk);
+	 while (i_tready != 1)
+	   @(posedge clk);
+	 i_tdata <= {64'b0};
+	 
+   	 @(posedge clk);
+	 while (i_tready != 1)
+	   @(posedge clk);
+     //-1 for last bit accounting
+	  repeat (len[15:3] + (len[2]|len[1]|len[0])-1)
+	   begin
+	      i_tdata <= {data[index], data[index+1], data[index+2], data[index+3]}; 
+   	      index <= index+4;
+	      
+	      @(posedge clk);
+	      while (i_tready != 1)
+		@(posedge clk);
+	   end
+   	 i_tlast <= 1'b1;
+	 i_tdata <= {data[index], data[index+1], data[index+2], data[index+3]}; 
+	 
+   
+	 @(posedge clk);
+	 while (i_tready != 1)
+	   @(posedge clk);
+	 i_tvalid <= 0;
+      end
+   endtask // test_packet
+
+//test_destination loop
+
+   task test_destination;
+      input enable;
+      input [15:0] dest_home;
+      
+      
+      begin
+         @(posedge clk);
+            
+         set_data <= {enable,dest_home};
+         set_addr <= 89;
+         set_stb <= 1;
+            
+         @(posedge clk);
+         set_stb <= 0;
+         end
+      endtask
+	
+//main loop	
+   initial
+     begin
+	i_tvalid <= 0;
+	o_tready <= 1;
+	
+    i_tdata <= 0;
+   
+	@(negedge reset);
+	@(posedge clk);
+	@(posedge clk);
+
+
+	test_destination(1,16'hFEED);
+	test_packet(2, 32'hDEAD_BEEF);
+
+	test_destination(1,16'hFEED);
+	test_packet(4, 32'hDEAD_BEEF);
+
+	test_destination(1,16'hFEED);
+	test_packet(6, 32'hDEAD_BEEF);
+
+	test_destination(1,16'hFEED);
+	test_packet(8, 32'hDEAD_BEEF);
+
+     end
+
+
+
+
+endmodule
diff --git a/fpga/usrp3/lib/vita_200/chdr_16sc_to_8sc.v b/fpga/usrp3/lib/vita_200/chdr_16sc_to_8sc.v
new file mode 100644
index 000000000..286354bea
--- /dev/null
+++ b/fpga/usrp3/lib/vita_200/chdr_16sc_to_8sc.v
@@ -0,0 +1,198 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module chdr_16sc_to_8sc
+  #(parameter BASE=0)
+   (input clk, input reset,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    //input side of device
+    input [63:0] i_tdata,
+    input i_tlast,
+    input i_tvalid,
+    output i_tready,
+    //output side of device
+    output reg [63:0] o_tdata,
+    output o_tlast,
+    output o_tvalid,
+    input o_tready,
+
+    output [31:0] debug
+    );
+   
+   //pipeline register
+   reg [63:0] 	  hold_tdata;
+   //bit assignments
+   wire    chdr_has_hdr = 1'b1;
+   wire    chdr_has_time = i_tdata[61];
+   wire    chdr_has_tlr = 1'b0;
+
+   wire [7:0]    rounded_i1;
+   wire [7:0]    rounded_q1;
+   wire [7:0]    rounded_i0;
+   wire [7:0]    rounded_q0;
+
+   wire [7:0]    rounded_i2;
+   wire [7:0]    rounded_q2;
+   wire [7:0]    rounded_i3;
+   wire [7:0]    rounded_q3;
+
+   //chdr length calculations
+   wire [15:0]    chdr_header_lines8 = chdr_has_time? 16 : 8;
+
+   wire [15:0]    chdr_almost_payload_lines8 = ((i_tdata[47:32] - chdr_header_lines8) >> 1);
+
+   wire [15:0]    chdr_payload_lines8 = chdr_almost_payload_lines8 + chdr_header_lines8;
+   wire [15:0]    my_newhome;
+
+   wire    set_sid;
+   
+   setting_reg #(.my_addr(BASE), .width(17)) new_destination
+     (.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
+      .out({set_sid, my_newhome[15:0]}));
+
+   localparam HEADER        = 2'd0;//IDLE
+   localparam TIME          = 2'd1;
+   localparam ODD           = 2'd2;
+   localparam EVEN          = 2'd3;
+   
+
+   reg [1:0]       state;
+   
+
+
+   always @(posedge clk) begin
+      if (reset) begin
+        state <= HEADER;
+        hold_tdata <= 0;
+      end	
+      else case(state)
+
+        HEADER: begin
+          if (i_tvalid && o_tready) begin
+            state <= (i_tdata[61])? TIME : ODD;
+          end
+
+        end
+
+        TIME: begin
+          if (i_tvalid && o_tready) begin
+            state <= (i_tlast)? HEADER: ODD;
+            hold_tdata <= i_tdata;
+          end
+        end
+
+        ODD: begin
+          if (i_tvalid) begin
+            if (i_tlast) begin
+              if(o_tready)
+                state <= HEADER;
+            end
+            else begin
+              state <= EVEN;
+              hold_tdata <= i_tdata;
+            end
+          end
+        end
+
+        EVEN: begin
+          if (i_tvalid && o_tready)
+            state <= (i_tlast) ? HEADER: ODD;
+          hold_tdata <= i_tdata;
+    
+        end
+              
+       default: state <= HEADER;
+       
+     endcase
+   end
+   
+   //assign 8 bit i and q signals from this line and last
+   
+   //new data processing
+   round #(.bits_in(16),
+     .bits_out(8))
+   round_i2
+     (.in(i_tdata[63:48]), 
+      .out(rounded_i2[7:0])
+      );
+
+   round #(.bits_in(16),
+           .bits_out(8))
+   round_q2
+     (.in(i_tdata[47:32]),
+      .out(rounded_q2[7:0])
+      );
+
+   round #(.bits_in(16),
+           .bits_out(8))
+   round_i3
+     (.in(i_tdata[31:16]),
+      .out(rounded_i3[7:0])
+      );
+
+   round #(.bits_in(16),
+           .bits_out(8))
+   round_q3
+     (.in(i_tdata[15:0]),
+      .out(rounded_q3[7:0])
+      );
+
+   // old data processing 
+   round #(.bits_in(16),
+     .bits_out(8))
+   round_i0(.in(hold_tdata[63:48]), .out(rounded_i0[7:0])
+      );
+
+   round #(.bits_in(16),
+           .bits_out(8))
+   round_q0
+     (.in(hold_tdata[47:32]),
+      .out(rounded_q0[7:0])
+      );
+
+   round #(.bits_in(16),
+           .bits_out(8))
+   round_i1
+     (.in(hold_tdata[31:16]),
+      .out(rounded_i1[7:0])
+      );
+
+   round #(.bits_in(16),
+           .bits_out(8))
+   round_q1
+     (.in(hold_tdata[15:0]),
+      .out(rounded_q1[7:0])
+      );
+   
+   // main mux
+   always @(*) 
+     case(state)
+       HEADER: o_tdata = {i_tdata[63:48], chdr_payload_lines8,
+        set_sid ? {i_tdata[15:0], my_newhome[15:0]}:i_tdata[31:0]};
+       TIME: o_tdata = i_tdata;
+       ODD: o_tdata = {rounded_i2, rounded_q2, rounded_i3, rounded_q3,rounded_i0, rounded_q0, rounded_i1, rounded_q1};
+       EVEN: o_tdata = {rounded_i0, rounded_q0, rounded_i1, rounded_q1,rounded_i2, rounded_q2, rounded_i3, rounded_q3};
+       default : o_tdata = i_tdata;
+     endcase
+   
+   assign o_tvalid = i_tvalid && (state != ODD || i_tlast);
+   assign i_tready = o_tready || (state == ODD && !i_tlast);
+   assign o_tlast  = i_tlast;
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/fpga/usrp3/lib/vita_200/chdr_16sc_to_8sc_tb.v b/fpga/usrp3/lib/vita_200/chdr_16sc_to_8sc_tb.v
new file mode 100644
index 000000000..bca0dc6de
--- /dev/null
+++ b/fpga/usrp3/lib/vita_200/chdr_16sc_to_8sc_tb.v
@@ -0,0 +1,151 @@
+//
+// Copyright 2016 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+`timescale 1ns/1ps
+
+module chdr_16sc_to_8sc_tb();
+
+   reg clk = 0;
+   reg reset = 1;
+   //generate clock
+   always #10 clk = ~clk; 
+
+   initial $dumpfile("chdr_16sc_to_8sc_tb.vcd");
+   initial $dumpvars(0,chdr_16sc_to_8sc_tb);
+   
+   //tells when to finish
+   initial
+     begin
+   	#50 reset = 0;
+   	#50000; 
+   	$finish;
+     end
+
+   //setting registers and wire
+   reg [63:0] i_tdata;
+   reg        i_tlast = 0;
+   reg        i_tvalid = 0;
+   wire       i_tready;
+
+   wire [63:0] o_tdata;
+   wire        o_tlast;
+   
+   wire	       o_tvalid;
+   reg 	       o_tready;
+
+   reg [7:0]   set_addr;
+   reg [31:0]  set_data;
+   reg 	       set_stb;
+
+   chdr_16sc_to_8sc #(.BASE(89))dut
+     (.clk(clk), .reset(reset),
+      .set_data(set_data), .set_stb(set_stb), .set_addr(set_addr),
+      .i_tdata(i_tdata), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready),
+      .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready), .debug());
+
+   reg [63:0]  data[0:7];
+   initial $readmemh("from16_to_x.hex", data);
+   task test_packet;
+      input [15:0] len;
+      input [31:0] sid;
+      reg [4:0]    index;
+      
+      begin
+
+	 index <= 0;
+	 @(posedge clk) ;
+	 //send header 
+   	 i_tdata <= {4'h2 /* flags */ , 12'h0 /* seqnum */, (len + 16'd16), sid};
+	 i_tvalid <= 1;
+	 i_tlast <= 0;
+	 @(posedge clk);
+	 while (i_tready != 1)
+	   @(posedge clk);
+	 i_tdata <= {64'b0};
+   	 @(posedge clk);
+	 while (i_tready != 1)
+	   @(posedge clk);
+	 //-1 for last bit accounting
+	 repeat (len[15:3] + (len[2]|len[1]|len[0])-1)
+	   begin
+	      i_tdata <= {data[index]}; 
+	      index <= index+1;
+	      @(posedge clk);
+	      while (i_tready != 1)
+		@(posedge clk);
+	   end
+   	 i_tlast <= 1'b1;
+	 i_tdata <= {data[index]}; 
+	 @(posedge clk);
+	 while (i_tready != 1)
+	   @(posedge clk);
+	 i_tvalid <= 0;
+      end
+   endtask // test_packet
+
+   task test_destination;
+      input enable;
+      input [15:0] dest_home;
+      
+      
+      begin
+         @(posedge clk);
+         
+         set_data <= {enable,dest_home};
+         set_addr <= 89;
+         set_stb <= 1;
+         
+         @(posedge clk);
+         set_stb <= 0;
+      end
+   endtask
+   
+   
+   initial
+     begin
+	i_tvalid <= 0;
+	o_tready <= 1;
+	
+	i_tdata <= 0;
+	
+	@(negedge reset);
+	@(posedge clk);
+	@(posedge clk);
+
+	test_destination(1,16'hFEED);
+	test_packet(2, 32'hDEAD_BEEF);
+
+	test_destination(1,16'hFEED);
+	test_packet(4, 32'hDEAD_BEEF);
+
+	test_destination(1,16'hFEED);
+	test_packet(6, 32'hDEAD_BEEF);
+
+	test_destination(1,16'hFEED);
+	test_packet(8, 32'hDEAD_BEEF);
+
+	test_destination(1,16'hFEED);
+	test_packet(10, 32'hDEAD_BEEF);
+
+	test_destination(1,16'hFEED);
+	test_packet(12, 32'hDEAD_BEEF);
+
+	test_destination(1,16'hFEED);
+	test_packet(14, 32'hDEAD_BEEF);
+
+	test_destination(1,16'hFEED);
+	test_packet(16, 32'hDEAD_BEEF);
+
+	test_destination(1,16'hFEED);
+	test_packet(32, 32'hDEAD_BEEF);
+
+	
+     end
+
+
+   
+
+
+endmodule
diff --git a/fpga/usrp3/lib/vita_200/chdr_16sc_to_xxxx_chain.v b/fpga/usrp3/lib/vita_200/chdr_16sc_to_xxxx_chain.v
new file mode 100644
index 000000000..7d33b67f5
--- /dev/null
+++ b/fpga/usrp3/lib/vita_200/chdr_16sc_to_xxxx_chain.v
@@ -0,0 +1,108 @@
+//
+// Copyright 2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+//selectable conversion chain
+
+module chdr_16sc_to_xxxx_chain
+  #(parameter BASE = 0)
+   (input 	  clk, input reset,
+
+    input 	  set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+    input [63:0]  i_tdata,
+    input 	  i_tlast,
+    input 	  i_tvalid,
+    output 	  i_tready,
+
+    output [63:0] o_tdata,
+    output 	  o_tlast,
+    output 	  o_tvalid,
+    input 	  o_tready,
+
+    output [31:0] debug
+    );
+
+   //------------------------------------------------------------------
+   // Demux destination setting register - safe switch for demux
+   //------------------------------------------------------------------
+   wire [1:0] 	  demux_dst;
+   setting_reg #(.my_addr(BASE), .width(2), .at_reset(2'b00)) sr_demux_dst
+     (.clk(clk),.rst(reset),
+      .strobe(set_stb),.addr(set_addr), .in(set_data),
+      .out({demux_dst}),.changed());
+
+   //------------------------------------------------------------------
+   // All FIFO IO lines
+   //------------------------------------------------------------------
+   wire [63:0] 	  i0_tdata; wire i0_tlast, i0_tvalid, i0_tready;
+   wire [63:0] 	  i1_tdata; wire i1_tlast, i1_tvalid, i1_tready;
+   wire [63:0] 	  i2_tdata; wire i2_tlast, i2_tvalid, i2_tready;
+   wire [63:0] 	  i3_tdata; wire i3_tlast, i3_tvalid, i3_tready;
+
+   wire [63:0] 	  o0_tdata; wire o0_tlast, o0_tvalid, o0_tready;
+   wire [63:0] 	  o1_tdata; wire o1_tlast, o1_tvalid, o1_tready;
+   wire [63:0] 	  o2_tdata; wire o2_tlast, o2_tvalid, o2_tready;
+   wire [63:0] 	  o3_tdata; wire o3_tlast, o3_tvalid, o3_tready;
+
+   //------------------------------------------------------------------
+   // Instantiate converters
+   //------------------------------------------------------------------
+   assign {o0_tdata, o0_tlast, o0_tvalid, i0_tready} = {i0_tdata, i0_tlast, i0_tvalid, o0_tready};
+   //assign {o1_tdata, o1_tlast, o1_tvalid, i1_tready} = {i1_tdata, i1_tlast, i1_tvalid, o1_tready};
+   //assign {o2_tdata, o2_tlast, o2_tvalid, i2_tready} = {i2_tdata, i2_tlast, i2_tvalid, o2_tready};
+   //assign {o3_tdata, o3_tlast, o3_tvalid, i3_tready} = {i3_tdata, i3_tlast, i3_tvalid, o3_tready};
+
+   //leave path 0 for pass through
+   
+   chdr_16sc_to_12sc
+     #(.BASE(89)) convert_16sc_to_12sc
+      
+       (.clk(clk), .reset(reset),.set_data(0), .set_stb(0), .set_addr(0),
+       .i_tdata(i1_tdata), .i_tlast(i1_tlast), .i_tvalid(i1_tvalid), .i_tready(i1_tready),
+       .o_tdata(o1_tdata), .o_tlast(o1_tlast), .o_tvalid(o1_tvalid), .o_tready(o1_tready)
+       );
+
+   chdr_16sc_to_32f
+     #(.BASE(89)) convert_16sc_to_32f
+      
+       (.clk(clk), .reset(reset),.set_data(0), .set_stb(0), .set_addr(0),
+       .i_tdata(i2_tdata), .i_tlast(i2_tlast), .i_tvalid(i2_tvalid), .i_tready(i2_tready),
+       .o_tdata(o2_tdata), .o_tlast(o2_tlast), .o_tvalid(o2_tvalid), .o_tready(o2_tready)
+       );
+
+   chdr_16sc_to_8sc #(.BASE(89)) convert_16sc_to_8sc
+     (.clk(clk), .reset(reset),.set_data(0), .set_stb(0), .set_addr(0),
+      .i_tdata(i3_tdata), .i_tlast(i3_tlast), .i_tvalid(i3_tvalid), .i_tready(i3_tready),
+      .o_tdata(o3_tdata), .o_tlast(o3_tlast), .o_tvalid(o3_tvalid), .o_tready(o3_tready)
+      );
+   
+
+   //------------------------------------------------------------------
+   // Ingress and Egress muxing
+   //------------------------------------------------------------------
+   //assign {o_tdata, o_tlast, o_tvalid, i_tready} = {i_tdata, i_tlast, i_tvalid, o_tready};
+   ///*
+   axi_demux4 #(.ACTIVE_CHAN(4'b1111), .WIDTH(64), .BUFFER(1)) demux_pack_chain
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .header(), .dest(demux_dst),
+      .i_tdata(i_tdata), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready),
+      .o0_tdata(i0_tdata), .o0_tlast(i0_tlast), .o0_tvalid(i0_tvalid), .o0_tready(i0_tready),
+      .o1_tdata(i1_tdata), .o1_tlast(i1_tlast), .o1_tvalid(i1_tvalid), .o1_tready(i1_tready),
+      .o2_tdata(i2_tdata), .o2_tlast(i2_tlast), .o2_tvalid(i2_tvalid), .o2_tready(i2_tready),
+      .o3_tdata(i3_tdata), .o3_tlast(i3_tlast), .o3_tvalid(i3_tvalid), .o3_tready(i3_tready));
+
+   axi_mux4 #(.PRIO(1), .WIDTH(64), .BUFFER(1)) mux_pack_chain
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i0_tdata(o0_tdata), .i0_tlast(o0_tlast), .i0_tvalid(o0_tvalid), .i0_tready(o0_tready),
+      .i1_tdata(o1_tdata), .i1_tlast(o1_tlast), .i1_tvalid(o1_tvalid), .i1_tready(o1_tready),
+      .i2_tdata(o2_tdata), .i2_tlast(o2_tlast), .i2_tvalid(o2_tvalid), .i2_tready(o2_tready),
+      .i3_tdata(o3_tdata), .i3_tlast(o3_tlast), .i3_tvalid(o3_tvalid), .i3_tready(o3_tready),
+      .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready));
+   //*/
+
+endmodule //chdr_16sc_to_xxxx_chain
diff --git a/fpga/usrp3/lib/vita_200/chdr_32f_to_16s.v b/fpga/usrp3/lib/vita_200/chdr_32f_to_16s.v
new file mode 100644
index 000000000..c18fd34e5
--- /dev/null
+++ b/fpga/usrp3/lib/vita_200/chdr_32f_to_16s.v
@@ -0,0 +1,183 @@
+//
+// Copyright 2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module chdr_32f_to_16s #
+(
+  parameter BASE = 0
+)
+(
+  input              clk,
+  input              rst,
+
+  // axi4 stream slave interface
+  input [63:0]       i_tdata,
+  input              i_tvalid,
+  input              i_tlast,
+  output             i_tready,
+
+  // axi4 stream master interface
+  output reg [63:0]  o_tdata,
+  output             o_tvalid,
+  output             o_tlast,
+  input              o_tready,
+
+  // settings bus slave interface
+  input              set_stb,
+  input [7:0]        set_addr,
+  input [31:0]       set_data,
+
+  output [63:0]      debug
+);
+
+
+  wire [31:0] float0 = i_tdata[63:32];
+  wire [31:0] float1 = i_tdata[31:0];
+
+  wire [15:0] fixed1_cur;
+  wire [15:0] fixed0_cur;
+
+  // Parametrize the converter as IEEE 754 single precision float to Q15
+  xxf_to_xxs #
+  (
+    .FBITS(32),
+    .MBITS(23),
+    .EBITS(8),
+    .RADIX(15),
+    .QWIDTH(16)
+  ) f2q0
+  (
+    .i_float(float0),
+    .o_fixed(fixed0_cur)
+  );
+
+  // Parametrize the converter as IEEE 754 single precision float to Q15
+  xxf_to_xxs #
+  (
+    .FBITS(32),
+    .MBITS(23),
+    .EBITS(8),
+    .RADIX(15),
+    .QWIDTH(16)
+  ) f2q1
+  (
+    .i_float(float1),
+    .o_fixed(fixed1_cur)
+  );
+
+  // As we need two cycles for one output cycle store the output in regs
+  reg [15:0] fixed1_old;
+  reg [15:0] fixed0_old;
+
+  wire handshake_ok = o_tready & i_tvalid;
+
+  always @ (posedge clk)
+    if (rst)
+      {fixed0_old, fixed1_old} <= {16'h0, 16'h0};
+    else if (handshake_ok)
+      {fixed0_old, fixed1_old} <= {fixed0_cur, fixed1_cur};
+
+  // Make routing (SID) available via settings bus
+  wire        set_sid;
+  wire [15:0] new_sid_dst;
+
+  setting_reg #
+  (
+    .my_addr(BASE),
+    .width(17)
+  ) new_destination
+  ( .clk(clk),
+    .rst(rst),
+    .strobe(set_stb),
+    .addr(set_addr),
+    .in(set_data),
+    .out({set_sid, new_sid_dst[15:0]}),
+    .changed()
+  );
+
+  // Parse CHDR info
+  wire        chdr_has_time = i_tdata[61];
+  // CHDR has either 8 bytes of header or 16 if VITA time is included.
+  wire [15:0] chdr_header_bytes = chdr_has_time ? 16 : 8;
+  // Calculate size of samples input in bytes by taking CHDR size filed
+  // and subtracting header length.
+  wire [15:0] sample_byte_count_in = i_tdata[47:32] - chdr_header_bytes;
+  // Calculate size of samples to be output by taking input size
+  // and dividing by two as sizeof(Q15) = 2*sizeof(float)
+  wire [15:0] sample_byte_count_out = sample_byte_count_in >> 1;
+  // Calculate size of output CHDR packet by adding back header size to new
+  // payload size.
+  wire [15:0] output_chdr_pkt_size = sample_byte_count_out + chdr_header_bytes;
+
+  localparam HEADER  = 2'd0;
+  localparam TIME    = 2'd1;
+  localparam PREPARE = 2'd2;
+  localparam OUTPUT  = 2'd3;
+
+
+  reg [1:0] state;
+
+  always @(posedge clk)
+    if (rst) begin
+      state <= HEADER;
+    end
+
+    else case(state)
+      HEADER:
+        // In case we see a i_last we just wait for the
+        // next header here, otherwise move on to the next states
+        if (handshake_ok & !i_tlast) begin
+          state <= chdr_has_time ? TIME : PREPARE;
+        end
+
+      TIME:
+        if (handshake_ok) begin
+          // If we get a premature end of burst go back
+          // to searching for the start of a new packet.
+          state <= i_tlast ? HEADER : PREPARE;
+        end
+
+      PREPARE:
+        if (handshake_ok) begin
+          state <= i_tlast ? HEADER : OUTPUT;
+        end
+
+      OUTPUT:
+        if (handshake_ok) begin
+          state <= i_tlast ? HEADER : PREPARE;
+        end
+
+      default:
+        state <= HEADER;
+    endcase
+
+  always @(*)
+    case(state)
+      // Populate header with CHDR fields
+      HEADER:
+        o_tdata = {i_tdata[63:48], output_chdr_pkt_size,
+                   set_sid ? {i_tdata[15:0], new_sid_dst[15:0]} : i_tdata[31:0]};
+      TIME:
+        o_tdata = i_tdata;
+      PREPARE:
+        // The bits [31:0] of o_tdata are useless. The header will take
+        // care of this by setting the correct length.
+        o_tdata = {fixed0_cur[15:0], fixed1_cur[15:0], 32'h0};
+      OUTPUT:
+        o_tdata = {fixed0_old[15:0], fixed1_old[15:0],
+                   fixed0_cur[15:0], fixed1_cur[15:0]};
+      default :
+        o_tdata = i_tdata;
+    endcase
+
+  // Either the input is valid and is directly output (HEADER, TIME, EOB),
+  // or we need to be in the 'OUTPUT' state ({fixed0_old, fixed1_old} contains correct old
+  // line)
+  assign o_tvalid = (i_tvalid && state != PREPARE) || i_tvalid && i_tlast;
+  assign i_tready = o_tready || (state == PREPARE && !i_tlast);
+  assign o_tlast  = i_tlast;
+
+endmodule
diff --git a/fpga/usrp3/lib/vita_200/chdr_32f_to_16sc.v b/fpga/usrp3/lib/vita_200/chdr_32f_to_16sc.v
new file mode 100644
index 000000000..30f829b8a
--- /dev/null
+++ b/fpga/usrp3/lib/vita_200/chdr_32f_to_16sc.v
@@ -0,0 +1,145 @@
+//
+// Copyright 2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+
+module chdr_32f_to_16sc
+  #(parameter BASE=0)
+   (input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    
+    input 	      clk, input reset,
+    input [63:0]      i_tdata,
+    input 	      i_tlast,
+    input 	      i_tvalid,
+    output 	      i_tready,
+  
+    output reg [63:0] o_tdata,
+    output 	      o_tlast,
+    output 	      o_tvalid,
+    input 	      o_tready,
+
+    output [31:0]     debug
+    );
+
+ 
+   wire 	      chdr_has_hdr = 1'b1;
+   wire 	      chdr_has_time = i_tdata[61];
+   wire 	      chdr_has_tlr = 1'b0;
+
+   wire [15:0] 	      s0_imag;
+   wire [15:0] 	      s0_real;
+   wire [15:0] 	      s1_imag;
+   wire [15:0] 	      s1_real;
+   
+
+   reg [15:0] 	      imag0;
+   reg [15:0] 	      real0;
+   wire [15:0] 	      imag1;
+   wire [15:0] 	      real1;
+   
+
+
+
+   
+
+
+   //chdr length calculations
+   wire [15:0] 	      chdr_header_lines = chdr_has_time? 16 : 8;
+
+   wire [15:0] 	      samples = ((i_tdata[47:32] - chdr_header_lines) >> 1);
+
+   wire [15:0] 	      chdr_payload_lines = samples + chdr_header_lines;
+
+
+   wire 	      set_sid;
+   wire [15:0] 	      my_newhome;
+
+   setting_reg #(.my_addr(BASE), .width(17)) new_destination
+     (.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
+      .out({set_sid, my_newhome[15:0]}));
+
+ 
+
+   localparam HEADER        = 2'd0;//IDLE
+   localparam TIME    = 2'd1;
+   localparam ODD           = 2'd2;
+   localparam EVEN          = 2'd3;
+
+   reg [1:0] 	      state;
+   
+   always @(posedge clk) begin
+      if (reset) begin
+         state <= HEADER;
+
+      end
+      else if (i_tvalid && i_tready) case(state)
+
+	      HEADER: begin
+		if (!i_tlast) state <= (i_tdata[61])? TIME : ODD;
+	      end
+	      
+	      TIME: begin
+		state <= (i_tlast)? HEADER: ODD;
+	      end
+	      
+	      ODD: begin
+		state <= (i_tlast)? HEADER: EVEN;
+	      end
+
+	      EVEN: begin
+		state <= (i_tlast)? HEADER: ODD;
+	      end
+	      
+	      default: state <= HEADER;
+	    endcase
+   end // always @ (posedge clk)
+
+   //hold data after each input transfer
+   reg [63:0] 	       hold_tdata;
+   always @(posedge clk) begin
+    	if (i_tvalid && i_tready) hold_tdata <= i_tdata;
+   end
+
+
+   
+   float_to_iq #(.BITS_IN(32),.BITS_OUT(16))
+   float_to_iq_imag0 (.in(i_tdata[63:32]),.out(s1_imag[15:0]));
+
+   float_to_iq #(.BITS_IN(32),.BITS_OUT(16))
+   float_to_iq_real0 (.in(i_tdata[31:0]),.out(s1_real[15:0]));
+
+   
+   float_to_iq #(.BITS_IN(32),.BITS_OUT(16))
+   float_to_iq_imag1 (.in(hold_tdata[63:32]),.out(s0_imag[15:0]));
+
+   
+   float_to_iq #(.BITS_IN(32),.BITS_OUT(16))
+   float_to_iq_real1 (.in(hold_tdata[31:0]),.out(s0_real[15:0]));
+
+
+   
+
+   always @(*) 
+     case(state)
+       
+       HEADER: o_tdata <= {i_tdata[63:48], chdr_payload_lines,
+			   set_sid ? {i_tdata[15:0], my_newhome[15:0]}:i_tdata[31:0]};
+       TIME: o_tdata <= i_tdata;
+       ODD: o_tdata <= {s1_imag, s1_real, 32'h0};
+       EVEN: o_tdata <= {s0_imag, s0_real, s1_imag, s1_real};
+       
+      default : o_tdata = i_tdata;
+     endcase
+   
+   assign o_tvalid =  i_tvalid && (state != ODD || i_tlast);  
+   assign i_tready =  o_tready || (state == ODD && !i_tlast); 
+   assign o_tlast  = i_tlast;
+
+endmodule
+
+
+
diff --git a/fpga/usrp3/lib/vita_200/chdr_32f_to_16sc_tb.v b/fpga/usrp3/lib/vita_200/chdr_32f_to_16sc_tb.v
new file mode 100644
index 000000000..c798d94eb
--- /dev/null
+++ b/fpga/usrp3/lib/vita_200/chdr_32f_to_16sc_tb.v
@@ -0,0 +1,157 @@
+//
+// Copyright 2016 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+`timescale 1ns/1ps
+
+module chdr_32f_to_16sc_tb();
+
+   reg clk = 0;
+   reg reset = 1;
+   //generate clock
+   always #10 clk = ~clk; 
+
+   initial $dumpfile("chdr_32f_to_16sc_tb.vcd");
+   initial $dumpvars(0,chdr_32f_to_16sc_tb);
+   
+
+
+   //tells when to finish
+   initial
+     begin
+   	#50 reset = 0;
+   	#50000; 
+   	$finish;
+     end
+
+   //setting registers and wire
+   reg [63:0] i_tdata;
+   reg        i_tlast = 0;
+   reg        i_tvalid = 0;
+   wire       i_tready;
+
+   wire [63:0] o_tdata;
+   wire        o_tlast;
+   
+   wire	       o_tvalid;
+   reg 	       o_tready;
+
+   reg [7:0] set_addr;
+   reg [31:0] set_data;
+   reg set_stb;
+
+   chdr_32f_to_16sc #(.BASE(89))dut
+     (.clk(clk), .reset(reset),
+      .set_data(set_data), .set_stb(set_stb), .set_addr(set_addr),
+      .i_tdata(i_tdata), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready),
+      .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready), .debug());
+
+
+  reg [31:0]data[0:7];
+  initial $readmemh("iq_to_float_output.txt", data);
+ 
+   
+  task test_packet;
+      input [15:0] len;
+      input [31:0] sid;
+      reg [4:0] index;
+            
+      begin
+
+	index <= 0;
+	 
+	 
+	 @(posedge clk) ;
+	 //send header 
+   	 i_tdata <= {1'b0, 1'b0, 1'b1, 1'b0, 12'h0, (len + 16'd16), sid};
+	 i_tvalid <= 1;
+	 i_tlast <= 0;
+	 @(posedge clk);
+	 while (i_tready != 1)
+	   @(posedge clk);
+	 i_tdata <= {64'b0};
+	
+   	 @(posedge clk);
+	 while (i_tready != 1)
+	   @(posedge clk);
+     //-1 for last bit accounting
+	 repeat (len[15:3] + (len[2]|len[1]|len[0]) - 1)
+	   begin
+	      
+	      i_tdata <= {data[index],data[index+1]};
+   	      index <= index+2;
+	      
+	      @(posedge clk);
+	 while (i_tready != 1)
+	   @(posedge clk);
+	   end
+	 
+
+	 
+   	 i_tlast <= 1'b1;
+	 i_tdata <= {data[index], data[index+1]};
+
+	 
+
+	 @(posedge clk);
+	 while (i_tready != 1)
+	   @(posedge clk);
+	 i_tvalid <= 0;
+      end
+   endtask // test_packet
+
+ task test_destination;
+      input enable;
+      input [15:0] dest_home;
+      
+      
+      begin
+         @(posedge clk);
+            
+         set_data <= {enable,dest_home};
+         set_addr <= 89;
+         set_stb <= 1;
+            
+         @(posedge clk);
+         set_stb <= 0;
+         end
+      endtask
+	
+	
+   initial
+     begin
+	i_tvalid <= 0;
+	o_tready <= 1;
+	
+    	i_tdata <= 0;
+   
+	@(negedge reset);
+	@(posedge clk);
+	@(posedge clk);
+
+
+	test_destination(1,16'hFEED);
+	test_packet(4, 32'hDEAD_BEEF);
+
+	test_destination(1,16'hFEED);
+	test_packet(8, 32'hDEAD_BEEF);
+
+	test_destination(1,16'hFEED);
+	test_packet(16, 32'hDEAD_BEEF);
+
+	test_destination(1,16'hFEED);
+	test_packet(20, 32'hDEAD_BEEF);
+
+	test_destination(1,16'hFEED);
+	test_packet(24, 32'hDEAD_BEEF);
+
+	test_destination(1,16'hFEED);
+	test_packet(28, 32'hDEAD_BEEF);
+	
+     end
+
+ 
+
+
+endmodule
diff --git a/fpga/usrp3/lib/vita_200/chdr_8s_to_16s.v b/fpga/usrp3/lib/vita_200/chdr_8s_to_16s.v
new file mode 100644
index 000000000..09ad0bd3c
--- /dev/null
+++ b/fpga/usrp3/lib/vita_200/chdr_8s_to_16s.v
@@ -0,0 +1,144 @@
+//
+// Copyright 2013, 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module chdr_8s_to_16s #
+(
+  parameter BASE=0
+)
+(
+  input             clk,
+  input             rst,
+
+  // axi4 stream slave interface
+  input [63:0]      i_tdata,
+  input             i_tlast,
+  input             i_tvalid,
+  output            i_tready,
+
+  // axi4 stream master interface
+  output reg [63:0] o_tdata,
+  output            o_tlast,
+  output            o_tvalid,
+  input             o_tready,
+
+  // settings bus slave interface
+  input             set_stb,
+  input [7:0]       set_addr,
+  input [31:0]      set_data,
+
+  output [31:0]     debug
+);
+
+  // split up the input for lazyness reasons
+  wire [7:0] fixed0 = i_tdata[63:56];
+  wire [7:0] fixed1 = i_tdata[55:48];
+  wire [7:0] fixed2 = i_tdata[47:40];
+  wire [7:0] fixed3 = i_tdata[39:32];
+  wire [7:0] fixed4 = i_tdata[31:24];
+  wire [7:0] fixed5 = i_tdata[23:16];
+  wire [7:0] fixed6 = i_tdata[15:8];
+  wire [7:0] fixed7 = i_tdata[7:0];
+
+  // Parse CHDR info
+  wire chdr_has_time = i_tdata[61];
+  // CHDR has either 8 bytes of header or 16 if VITA time is included.
+  wire [15:0] chdr_header_bytes = chdr_has_time ? 16 : 8;
+  // Calculate size of samples input in bytes by taking CHDR size field
+  // and subtracting header length.
+  wire [15:0] sample_byte_count_in = i_tdata[47:32] - chdr_header_bytes;
+  // Calculate size of samples by taking input size
+  // and multiplying by two
+  wire [15:0] sample_byte_count_out = sample_byte_count_in << 1;
+  // Calculate size of output CHDR packet by adding back header size to new
+  // payload size.
+  wire [15:0] output_chdr_pkt_size = sample_byte_count_out + chdr_header_bytes;
+
+  // Make routing (SID) available via settings bus
+  wire        set_sid;
+  wire [15:0] new_sid_dst;
+
+
+  setting_reg #
+  (
+    .my_addr(BASE),
+    .width(17)
+  )
+  new_destination
+  (
+    .clk(clk),
+    .rst(rst),
+    .strobe(set_stb),
+    .addr(set_addr),
+    .in(set_data),
+    .out({set_sid, new_sid_dst[15:0]}),
+    .changed()
+  );
+
+  wire handshake_ok = i_tvalid & o_tready;
+
+  //state declarations
+  localparam HEADER  = 2'd0;
+  localparam TIME    = 2'd1;
+  localparam ODD     = 2'd2;
+  localparam EVEN    = 2'd3;
+
+  reg [1:0] state;
+  reg       end_on_odd;
+
+  always @(posedge clk) begin
+   if (rst) begin
+     state <= HEADER;
+     end_on_odd <= 1'b0;
+   end
+   else case(state)
+     HEADER:
+       // if we get a premature end of burst,
+       // we just stick around for the next header
+       if (handshake_ok & !i_tlast) begin
+         state <= (i_tdata[61])? TIME : ODD;
+         end_on_odd <= (i_tdata[34:32] > 0) && (i_tdata[34:32] < 5);
+       end
+
+     TIME:
+       // if we get a premature i_tlast we bail out, else proceed
+       if (handshake_ok)
+         state <= (i_tlast)? HEADER: ODD;
+
+     ODD:
+       if (handshake_ok)
+         state <= (i_tlast & end_on_odd) ? HEADER : EVEN;
+
+     EVEN:
+       if (handshake_ok)
+         state <= (i_tlast) ? HEADER: ODD;
+
+     default:
+       state <= HEADER;
+
+    endcase
+end
+
+  always @(*)
+    case(state)
+      HEADER:
+        o_tdata = {i_tdata[63:48], output_chdr_pkt_size,
+                    set_sid ? {i_tdata[15:0], new_sid_dst[15:0]} : i_tdata[31:0]};
+      TIME:
+        o_tdata = i_tdata;
+      ODD:
+        o_tdata = {fixed0, 8'h0, fixed1, 8'h0, fixed2, 8'h0, fixed3, 8'h0};
+      EVEN:
+        o_tdata = {fixed4, 8'h0, fixed5, 8'h0, fixed6, 8'h0, fixed7, 8'h0};
+      default:
+        o_tdata = i_tdata;
+    endcase
+
+   assign o_tvalid = i_tvalid;
+   assign i_tready = o_tready && ((state != ODD) || (i_tlast & end_on_odd));
+   assign o_tlast  = i_tlast && ((state == EVEN) || ((state == ODD) & end_on_odd));
+
+endmodule
diff --git a/fpga/usrp3/lib/vita_200/chdr_8sc_to_16sc.hex b/fpga/usrp3/lib/vita_200/chdr_8sc_to_16sc.hex
new file mode 100644
index 000000000..b7cfd19fd
--- /dev/null
+++ b/fpga/usrp3/lib/vita_200/chdr_8sc_to_16sc.hex
@@ -0,0 +1,5 @@
+7F805A6B11006792
+88990011CCDD00AA
+
+
+
diff --git a/fpga/usrp3/lib/vita_200/chdr_8sc_to_16sc.v b/fpga/usrp3/lib/vita_200/chdr_8sc_to_16sc.v
new file mode 100644
index 000000000..1f5d99f5b
--- /dev/null
+++ b/fpga/usrp3/lib/vita_200/chdr_8sc_to_16sc.v
@@ -0,0 +1,122 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module chdr_8sc_to_16sc
+  #(parameter BASE=0)
+   (input clk, input reset,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+    input [63:0] i_tdata,
+    input  i_tlast,
+    input  i_tvalid,
+    output i_tready,
+
+    output reg [63:0] o_tdata,
+    output        o_tlast,
+    output        o_tvalid,
+    input         o_tready,
+
+    output [31:0] debug
+    );
+
+   //bit assignments
+   wire 	  chdr_has_hdr = 1'b1;
+   wire 	  chdr_has_time = i_tdata[61];
+   wire 	  chdr_has_tlr = 1'b0;
+   wire 	  set_sid;
+
+   //chdr length calculations
+   wire [15:0] 	  chdr_header_lines16 = chdr_has_time? 16 : 8;
+
+   wire [15:0] 	  chdr_almost_payload_lines16 = ((i_tdata[47:32] - chdr_header_lines16) << 1);
+
+   wire [15:0] 	  chdr_payload_lines16 = chdr_almost_payload_lines16 + chdr_header_lines16;
+
+   //new destination reg set
+   wire [15:0] 	  my_newhome;
+
+
+   setting_reg #(.my_addr(BASE), .width(17)) new_destination
+     (.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
+      .out({set_sid, my_newhome[15:0]}));
+
+
+   //state declarations
+
+
+   localparam HEADER        = 2'd0;//IDLE
+   localparam TIME = 2'd1;
+   localparam ODD           = 2'd2;
+   localparam EVEN          = 2'd3;
+
+   reg [1:0] 	   state;
+   reg 		   end_on_odd;
+
+   always @(posedge clk) begin
+      if (reset) begin
+         state <= HEADER;
+	 end_on_odd <= 1'b0;
+      end
+      else case(state)
+
+             HEADER: begin
+		if (i_tvalid && o_tready) begin
+		   state <= (i_tdata[61])? TIME : ODD;
+           	   end_on_odd <= (i_tdata[34:32] > 0) && (i_tdata[34:32] < 5);
+		end
+
+             end
+
+             TIME: begin
+		if (i_tvalid && o_tready) begin
+
+		   state <= (i_tlast)? HEADER: ODD;
+		end
+             end
+
+             ODD: begin
+		if (i_tvalid && o_tready) begin
+		   state <= (i_tlast & end_on_odd) ? HEADER : EVEN;
+		end
+             end
+
+             EVEN: begin
+		if (i_tvalid && o_tready)
+		  state <= (i_tlast) ? HEADER: ODD;
+             end
+	     default: state <= HEADER;
+	     
+	   endcase
+   end
+   
+   always @(*) 
+     case(state)
+	HEADER: o_tdata <= {i_tdata[63:48], chdr_payload_lines16,
+			  set_sid ? {i_tdata[15:0], my_newhome[15:0]}:i_tdata[31:0]};
+	TIME: o_tdata <= i_tdata;
+       ODD: o_tdata <= {i_tdata[63:56], 8'h0, i_tdata[55:48] , 8'h0, i_tdata[47:40], 8'h0, i_tdata[39:32] , 8'h0};
+       EVEN: o_tdata <= {i_tdata[31:24], 8'h0, i_tdata[23:16], 8'h0, i_tdata[15:8], 8'h0, i_tdata[7:0], 8'h0};
+   
+       
+       default : o_tdata = i_tdata;
+     endcase
+      
+   assign o_tvalid = i_tvalid;
+   assign i_tready = o_tready && ((state != ODD) || (i_tlast & end_on_odd));
+   assign o_tlast  = i_tlast && ((state == EVEN)||((state == ODD) & end_on_odd));
+
+endmodule
+
+
+
+
+
+
+
+
+
+
diff --git a/fpga/usrp3/lib/vita_200/chdr_8sc_to_16sc_tb.v b/fpga/usrp3/lib/vita_200/chdr_8sc_to_16sc_tb.v
new file mode 100644
index 000000000..f3cd06da0
--- /dev/null
+++ b/fpga/usrp3/lib/vita_200/chdr_8sc_to_16sc_tb.v
@@ -0,0 +1,153 @@
+//
+// Copyright 2016 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+//Purpose: to test 8 to 16 converter
+`timescale 1ns/1ps
+
+module chdr_8sc_to_16sc_tb();
+   
+   reg clk = 0;
+   reg reset = 1;
+   //generate clock
+   always #10 clk = ~clk; 
+
+   initial $dumpfile("chdr_8sc_to_16sc_tb.vcd");
+   initial $dumpvars(0,chdr_8sc_to_16sc_tb);
+   
+   //tells when to finish
+   initial
+     begin
+   	#50 reset = 0;
+   	#50000; 
+   	$finish;
+     end
+
+   //setting registers and wire
+   reg [63:0] i_tdata;
+   reg        i_tlast = 0;
+   reg        i_tvalid = 0;
+   wire       i_tready ;
+   reg [7:0]  set_addr;
+   reg [31:0] set_data;
+   reg 	      set_stb;
+   
+
+   wire [63:0] o_tdata;
+   wire        o_tlast;
+   
+   wire	       o_tvalid;
+   reg 	       o_tready;
+
+   chdr_8sc_to_16sc #(.BASE(89))dut
+     (.clk(clk), .reset(reset),
+      .set_data(set_data), .set_stb(set_stb), .set_addr(set_addr),
+      .i_tdata(i_tdata), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready),
+      .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready), .debug());
+   
+   //if you want to feed a bigger input change array sizes here
+
+   reg [63:0]  data[0:7];
+   initial $readmemh("from8_to_x.hex", data);
+
+   //test packet loop
+   task test_packet;
+      input [15:0] len;
+      input [31:0] sid;
+      reg [1:0]    index;
+      
+      begin
+	 index <= 0;
+	 @(posedge clk) ;
+	 //send header 
+   	 i_tdata <= {1'b0, 1'b0, 1'b1, 1'b0, 12'h0, (len + 16'd16),sid};
+	 i_tvalid <= 1;
+	 i_tlast <= 0;
+	 @(posedge clk);
+	 while (i_tready != 1)
+	   @(posedge clk);
+	 i_tdata <= {64'b0};
+   	 @(posedge clk);
+	 while (i_tready != 1)
+	   @(posedge clk);
+	 //-1 for last bit accounting
+	 repeat ( len[15:3] + (len[2]|len[1]|len[0]) - 1 )
+	   begin
+	      i_tdata <= {data[index]}; 
+   	      index <= index+1;
+	      @(posedge clk);
+	      while (i_tready != 1)
+		@(posedge clk);
+	   end
+   	 i_tlast <= 1'b1;
+	 i_tdata <= {data[index]}; 
+	 @(posedge clk);
+	 while (i_tready != 1)
+	   @(posedge clk);
+	 i_tvalid <= 0;
+      end
+   endtask // test_packet
+
+   //test_destination loop
+
+   task test_destination;
+      input enable;
+      input [15:0] dest_home;
+      
+      
+      begin
+         @(posedge clk);
+         
+         set_data <= {enable,dest_home};
+         set_addr <= 89;
+         set_stb <= 1;
+         
+         @(posedge clk);
+         set_stb <= 0;
+      end
+   endtask
+
+
+
+   
+   
+   //main loop	
+   initial
+     begin
+	i_tvalid <= 0;
+	o_tready <= 1;
+	
+	i_tdata <= 0;
+	
+	@(negedge reset);
+	@(posedge clk);
+	@(posedge clk);
+
+	/* Uncomment to test without changed sid
+	 test_destination(0,16'hFEED);
+	 test_packet(20, 32'hDEAD_BEEF);
+	 */
+	test_destination(1,16'hFEED);
+	test_packet(2, 32'hDEAD_BEEF);
+	#1000;
+	test_packet(4, 32'hDEAD_BEEF);
+	#1000;
+	test_packet(6, 32'hDEAD_BEEF);
+	#1000;
+	test_packet(8, 32'hDEAD_BEEF);
+	#1000;
+	test_packet(10, 32'hDEAD_BEEF);
+	#1000;
+	test_packet(12, 32'hDEAD_BEEF);
+	#1000;
+	test_packet(14, 32'hDEAD_BEEF);
+	#1000;
+	test_packet(16, 32'hDEAD_BEEF);
+	#1000;
+	
+     end
+
+
+
+endmodule
diff --git a/fpga/usrp3/lib/vita_200/chdr_xxxx_to_16sc_chain.v b/fpga/usrp3/lib/vita_200/chdr_xxxx_to_16sc_chain.v
new file mode 100644
index 000000000..a0837c1c6
--- /dev/null
+++ b/fpga/usrp3/lib/vita_200/chdr_xxxx_to_16sc_chain.v
@@ -0,0 +1,110 @@
+
+//
+// Copyright 2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+//selectable conversion chain
+
+module chdr_xxxx_to_16sc_chain
+  #(parameter BASE = 0)
+   (input 	  clk, input reset,
+
+    input 	  set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+    input [63:0]  i_tdata,
+    input 	  i_tlast,
+    input 	  i_tvalid,
+    output 	  i_tready,
+
+    output [63:0] o_tdata,
+    output 	  o_tlast,
+    output 	  o_tvalid,
+    input 	  o_tready,
+
+    output [31:0] debug
+    );
+
+   //------------------------------------------------------------------
+   // Demux destination setting register - safe switch for demux
+   //------------------------------------------------------------------
+   wire [1:0] 	  demux_dst;
+   setting_reg #(.my_addr(BASE), .width(2), .at_reset(2'b00)) sr_demux_dst
+     (.clk(clk),.rst(reset),
+      .strobe(set_stb),.addr(set_addr), .in(set_data),
+      .out({demux_dst}),.changed());
+
+   //------------------------------------------------------------------
+   // All FIFO IO lines
+   //------------------------------------------------------------------
+   wire [63:0] 	  i0_tdata; wire i0_tlast, i0_tvalid, i0_tready;
+   wire [63:0] 	  i1_tdata; wire i1_tlast, i1_tvalid, i1_tready;
+   wire [63:0] 	  i2_tdata; wire i2_tlast, i2_tvalid, i2_tready;
+   wire [63:0] 	  i3_tdata; wire i3_tlast, i3_tvalid, i3_tready;
+
+   wire [63:0] 	  o0_tdata; wire o0_tlast, o0_tvalid, o0_tready;
+   wire [63:0] 	  o1_tdata; wire o1_tlast, o1_tvalid, o1_tready;
+   wire [63:0] 	  o2_tdata; wire o2_tlast, o2_tvalid, o2_tready;
+   wire [63:0] 	  o3_tdata; wire o3_tlast, o3_tvalid, o3_tready;
+
+   //------------------------------------------------------------------
+   // Instantiate converters
+   //------------------------------------------------------------------
+   assign {o0_tdata, o0_tlast, o0_tvalid, i0_tready} = {i0_tdata, i0_tlast, i0_tvalid, o0_tready};
+   //assign {o1_tdata, o1_tlast, o1_tvalid, i1_tready} = {i1_tdata, i1_tlast, i1_tvalid, o1_tready};
+   //assign {o2_tdata, o2_tlast, o2_tvalid, i2_tready} = {i2_tdata, i2_tlast, i2_tvalid, o2_tready};
+   //assign {o3_tdata, o3_tlast, o3_tvalid, i3_tready} = {i3_tdata, i3_tlast, i3_tvalid, o3_tready};
+
+   //leave path 0 for pass through
+   
+    chdr_12sc_to_16sc
+    #(.BASE(89)) convert_12sc_to_16sc
+    
+    (.clk(clk), .reset(reset),.set_data(0), .set_stb(0), .set_addr(0),
+    .i_tdata(i1_tdata), .i_tlast(i1_tlast), .i_tvalid(i1_tvalid), .i_tready(i1_tready),
+    .o_tdata(o1_tdata), .o_tlast(o1_tlast), .o_tvalid(o1_tvalid), .o_tready(o1_tready)
+    );
+
+    chdr_32f_to_16sc
+    #(.BASE(89)) convert_32f_to_16sc
+    
+    (.clk(clk), .reset(reset),.set_data(0), .set_stb(0), .set_addr(0),
+    .i_tdata(i2_tdata), .i_tlast(i2_tlast), .i_tvalid(i2_tvalid), .i_tready(i2_tready),
+    .o_tdata(o2_tdata), .o_tlast(o2_tlast), .o_tvalid(o2_tvalid), .o_tready(o2_tready)
+    );
+
+    
+   chdr_8sc_to_16sc #(.BASE(89)) convert_8sc_to_16sc
+     (.clk(clk), .reset(reset),.set_data(0), .set_stb(0), .set_addr(0),
+      .i_tdata(i3_tdata), .i_tlast(i3_tlast), .i_tvalid(i3_tvalid), .i_tready(i3_tready),
+      .o_tdata(o3_tdata), .o_tlast(o3_tlast), .o_tvalid(o3_tvalid), .o_tready(o3_tready)
+      );
+   
+
+   //------------------------------------------------------------------
+   // Ingress and Egress muxing
+   //------------------------------------------------------------------
+   //assign {o_tdata, o_tlast, o_tvalid, i_tready} = {i_tdata, i_tlast, i_tvalid, o_tready};
+   ///*
+   axi_demux4 #(.ACTIVE_CHAN(4'b1111), .WIDTH(64), .BUFFER(1)) demux_pack_chain
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .header(), .dest(demux_dst),
+      .i_tdata(i_tdata), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready),
+      .o0_tdata(i0_tdata), .o0_tlast(i0_tlast), .o0_tvalid(i0_tvalid), .o0_tready(i0_tready),
+      .o1_tdata(i1_tdata), .o1_tlast(i1_tlast), .o1_tvalid(i1_tvalid), .o1_tready(i1_tready),
+      .o2_tdata(i2_tdata), .o2_tlast(i2_tlast), .o2_tvalid(i2_tvalid), .o2_tready(i2_tready),
+      .o3_tdata(i3_tdata), .o3_tlast(i3_tlast), .o3_tvalid(i3_tvalid), .o3_tready(i3_tready));
+
+   axi_mux4 #(.PRIO(1), .WIDTH(64), .BUFFER(1)) mux_pack_chain
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i0_tdata(o0_tdata), .i0_tlast(o0_tlast), .i0_tvalid(o0_tvalid), .i0_tready(o0_tready),
+      .i1_tdata(o1_tdata), .i1_tlast(o1_tlast), .i1_tvalid(o1_tvalid), .i1_tready(o1_tready),
+      .i2_tdata(o2_tdata), .i2_tlast(o2_tlast), .i2_tvalid(o2_tvalid), .i2_tready(o2_tready),
+      .i3_tdata(o3_tdata), .i3_tlast(o3_tlast), .i3_tvalid(o3_tvalid), .i3_tready(o3_tready),
+      .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready));
+   //*/
+
+endmodule //chdr_xxxx_to_16sc_chain
diff --git a/fpga/usrp3/lib/vita_200/context_packet_gen.v b/fpga/usrp3/lib/vita_200/context_packet_gen.v
new file mode 100644
index 000000000..52f07a931
--- /dev/null
+++ b/fpga/usrp3/lib/vita_200/context_packet_gen.v
@@ -0,0 +1,57 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module context_packet_gen
+  (input clk, input reset, input clear,
+   input trigger,
+   input [11:0] seqnum,
+   input [31:0] sid,
+   input [63:0] body,
+   input [63:0] vita_time,
+
+   output done,
+   output reg [63:0] o_tdata, output o_tlast, output o_tvalid, input o_tready);
+   
+   reg [1:0] 	     cp_state;
+   localparam CP_IDLE = 2'd0;
+   localparam CP_HEAD = 2'd1;
+   localparam CP_TIME = 2'd2;
+   localparam CP_DATA = 2'd3;
+   
+   always @(posedge clk)
+     if(reset|clear)
+       cp_state <= CP_IDLE;
+     else
+       case(cp_state)
+	 CP_IDLE :
+	   if(trigger)
+	     cp_state <= CP_HEAD;
+	 CP_HEAD :
+	   if(o_tready)
+	     cp_state <= CP_TIME;
+	 CP_TIME :
+	   if(o_tready)
+	     cp_state <= CP_DATA;
+	 CP_DATA :
+	   if(o_tready)
+	     cp_state <= CP_IDLE;
+       endcase // case (cp_state)
+
+   assign o_tvalid = (cp_state != CP_IDLE);
+   assign o_tlast = (cp_state == CP_DATA);
+
+   always @*
+     case(cp_state)
+       CP_HEAD : o_tdata <= { 4'hA, seqnum, 16'd24, sid };
+       CP_TIME : o_tdata <= vita_time;
+       CP_DATA : o_tdata <= body;
+       default : o_tdata <= body;
+     endcase // case (cp_state)
+
+   assign done = o_tlast & o_tvalid & o_tready;
+   
+endmodule // context_packet_gen
diff --git a/fpga/usrp3/lib/vita_200/float_to_iq.v b/fpga/usrp3/lib/vita_200/float_to_iq.v
new file mode 100644
index 000000000..8c438b57f
--- /dev/null
+++ b/fpga/usrp3/lib/vita_200/float_to_iq.v
@@ -0,0 +1,86 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module float_to_iq
+
+  #(parameter BITS_IN = 32,
+    parameter BITS_OUT = 16
+    )
+
+   (
+
+    input [31:0]   in,
+    output [15:0] out
+    );
+
+   //flags
+
+   wire 		   neg_inf;
+   wire 		   pos_inf;
+   wire 		   denorm;
+   wire tiny_exp;
+   
+
+
+   assign pos_inf = (in[31] == 0 && in[30:23] == 1 && in[22:0] == 0);
+   assign neg_inf = (in[31] == 1 && in[30:23] == 1 && in[22:0] == 0);
+   assign denorm = (in[30:23] == 0);
+   assign tiny_exp = (in[30:23] < 'd111);
+   
+   
+   
+
+
+
+   wire [23:0] 		   implied_bit_fraction;
+   wire [24:0] 		   operation_round;
+   wire [15:0] 		   round_fraction;
+   wire [15:0] 		   shifted_fraction;
+   wire [7:0] 		   shift_val;
+
+   wire [22:0] 		   true_frac;
+   
+
+   
+   
+   assign shift_val = (in[30:23] > 127)? (in[30:23] - 127): (127 - in[30:23]);
+   assign implied_bit_fraction = {1'b1,in[22:0]};
+ 
+   
+   
+   assign operation_round = (implied_bit_fraction + 'h000080);
+   
+
+   //testing for overflow
+   assign round_fraction = (operation_round[24] == 0)?(operation_round[23:8]):(16'h7FFF);
+   //shift the rounded value
+   wire [15:0] shift = round_fraction >> (15 - shift_val);
+   //2's complement the shifted output if the signed bit is 1
+   wire [15:0] final_val = (in[31] == 1)?(~shift + 1'b1):shift;
+   
+   
+
+   assign out = (pos_inf)?{1'b0,15'h7FFF}:(neg_inf)?{1'b1,15'h8000}:(denorm || tiny_exp)? 16'b0: final_val;
+   
+
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/fpga/usrp3/lib/vita_200/float_to_iq_tb.v b/fpga/usrp3/lib/vita_200/float_to_iq_tb.v
new file mode 100644
index 000000000..e403cf079
--- /dev/null
+++ b/fpga/usrp3/lib/vita_200/float_to_iq_tb.v
@@ -0,0 +1,74 @@
+//
+// Copyright 2016 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+module float_to_iq_tb();
+
+reg clk, reset;
+
+integer x,file;
+reg [31:0]  in;
+wire [15:0] out;
+
+initial clk = 0;
+
+always #10 clk = ~clk;
+
+initial $dumpfile("float_to_iq_tb.vcd");
+initial $dumpvars(0,float_to_iq_tb);
+
+initial 
+   begin
+
+      x <= 0;
+      reset <= 1;
+      in <= 0;
+      file = $fopen("float_to_iq_VER.txt");
+
+      repeat(65536) @(posedge clk);
+      reset <=0;
+      repeat(65536) @(posedge clk)
+         begin
+            in <= data[x];
+            x <= x+1;
+            $fdisplayh(file,out);
+         end
+         $fclose(file);
+         repeat(65536) @(posedge clk);
+         $finish;
+      end
+
+      float_to_iq #(.BITS_IN(32),.BITS_OUT(16))
+      dut 
+         (
+            .in(in), .out(out), .clk(clk), .reset(reset)
+         );
+//input
+         reg    [31:0] data [0:65535];
+         initial $readmemh("iq_to_float_output.txt",data);
+//golden output
+//
+/*
+         reg    [15:0] out_array [0:65535];
+         initial $readmemh("my_data.txt",out_array);
+         reg fail;
+         initial 
+            fail <= 0;
+//compare golden output with your output
+
+         always @(posedge clk) begin
+            if (out != out_array[index]) begin
+               $display("Line %d : Expected %x, got %x",index,out_array[index],out);
+            fail <= 1;
+         end
+      end
+*/
+         end
+
+
+
+
+
+         endmodule
+
diff --git a/fpga/usrp3/lib/vita_200/from12_to_x.hex b/fpga/usrp3/lib/vita_200/from12_to_x.hex
new file mode 100644
index 000000000..32d8cc754
--- /dev/null
+++ b/fpga/usrp3/lib/vita_200/from12_to_x.hex
@@ -0,0 +1,12 @@
+7FF8000001115AB6
+B6EEFEE599A577E9
+F0005AB800CCE7FF
+F0005AB800CCE7FF
+B6EEFEE599A577E9
+7FF8000001115AB6
+B6EEFEE599A577E9
+7FF8000001115AB6
+B6EEFEE599A577E9
+9999ACCAEEEEFFFF
+7878000065568799
+6543111122223333
diff --git a/fpga/usrp3/lib/vita_200/from16_to_x.hex b/fpga/usrp3/lib/vita_200/from16_to_x.hex
new file mode 100644
index 000000000..e26b06234
--- /dev/null
+++ b/fpga/usrp3/lib/vita_200/from16_to_x.hex
@@ -0,0 +1,8 @@
+8000FFFF7FFF1111
+00005A6BEEEE9999
+7AAAEEEE7FFF0000
+5AB890874676BBBB
+EEEE888800007FFF
+DACCCADBEEFFEED0
+FEEDBEEF0000BAAB
+CAB8000BACEDEED0
diff --git a/fpga/usrp3/lib/vita_200/from8_to_x.hex b/fpga/usrp3/lib/vita_200/from8_to_x.hex
new file mode 100644
index 000000000..5b4bcb016
--- /dev/null
+++ b/fpga/usrp3/lib/vita_200/from8_to_x.hex
@@ -0,0 +1,12 @@
+8000FFFF7FFF1111
+00005A6BEEEE9999
+7AAAEEEE7FFF0000
+7AAAEEEE7FFF0000
+7AAAEEEE7FFF0000
+7AAAEEEE7FFF0000
+7AAAEEEE7FFF0000
+7AAAEEEE7FFF0000
+7AAAEEEE7FFF0000
+7AAAEEEE7FFF0000
+7AAAEEEE7FFF0000
+7AAAEEEE7FFF0000
diff --git a/fpga/usrp3/lib/vita_200/generate_bits.cpp b/fpga/usrp3/lib/vita_200/generate_bits.cpp
new file mode 100644
index 000000000..f5ea60fc1
--- /dev/null
+++ b/fpga/usrp3/lib/vita_200/generate_bits.cpp
@@ -0,0 +1,87 @@
+//PURPOSE: C test bench for floating point converter IQ_to_FLOAT
+
+#include <cstdlib>
+#include <iostream>
+#include <stdio.h>
+#include <stdlib.h>
+#include <bitset>
+#include <cmath>
+#include "math.h"
+#include <iomanip>
+
+using namespace std;
+//INITIAL TESTING PURPOSES: Use if you want to print individual bits	
+	template <typename T>
+
+	void print_bits(T n) {
+		T mask = 1 << (sizeof(T)*8-1);
+		while (mask) {
+			cout << ((mask & n) ? "1" : "0");
+			mask >>= 1;
+		}
+	cout << endl;
+	}
+
+	int main()	{
+		
+
+		FILE *convFile;
+		FILE *newFile;
+
+
+		
+		
+
+
+		convFile = fopen("iq_to_float_input.txt", "w");
+		newFile =  fopen("iq_to_float_output.txt", "w");
+        //iterate through test cases
+    
+        for (signed int i = -0x8000; i <= 0x7FFF; i++)   {
+
+		float end = float(i*exp2(-15));
+        
+
+		unsigned int n = *(reinterpret_cast<unsigned int*>(&end));
+
+        //IN CASE YOU NEED TO LOOK AT SPECIFIC EXPONENT, FRAC, ETC VALUES
+        //ACTIVATE BY UNCOMMENTING
+        /*
+
+		unsigned int signed_bit = n>>31;
+		
+		unsigned int exp =  ((n>>23) &0xFF);
+		
+		unsigned int frac =  (n &0x7FFFFF);
+
+		cout << "end: " << end << endl;
+		cout << "n: " << hex << n << endl;
+
+
+
+		cout << "signed bit:" << hex << signed_bit << endl;
+		cout << "exp: " << hex <<  exp << endl;
+		cout << "fract: " << hex << frac << endl;
+
+		float f = *(float*)&n;
+		cout << "f" << f << endl;
+*/		
+		
+	//	print_bits<unsigned short>(start);
+	//	print_bits<unsigned int>(n);
+	    unsigned int something = i;
+        something &= 0xFFFF;
+
+		fprintf(convFile, "%x\n",something);
+		fprintf(newFile, "%x\n",n);
+        }
+
+	fclose(convFile);
+	fclose(newFile);
+
+
+	return 0;
+} 
+	 
+
+	
diff --git a/fpga/usrp3/lib/vita_200/iq_to_float.v b/fpga/usrp3/lib/vita_200/iq_to_float.v
new file mode 100644
index 000000000..74d56e1f8
--- /dev/null
+++ b/fpga/usrp3/lib/vita_200/iq_to_float.v
@@ -0,0 +1,72 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module iq_to_float
+
+  #(parameter BITS_IN =16,
+    parameter BITS_OUT = 32
+    )
+   (
+    input [15:0] in,
+    output [31:0] out
+    );
+
+   //imaginary
+
+   //2s complement
+   wire [15:0] unsigned_mag;
+   wire [15:0] complement;
+
+   //leading bit registers
+   wire [15:0] lead;
+   wire [15:0] reversed_mag;
+
+   //16-4 encoder
+   wire [3:0] binary_out;
+
+   wire [22:0] fraction;
+   wire [7:0] exponent;
+
+   wire [15:0] binary_in;
+
+   binary_encoder #(.SIZE(16))
+   encoding (.in(binary_in),.out(binary_out));
+
+   // Detect sign, if negative detected perform 2's complement
+   assign unsigned_mag = (in[15] == 1)?((~in[15:0])+1'b1):in[15:0];
+
+   //detect leading one
+   assign complement = ((~reversed_mag[BITS_IN-1:0])+1'b1);
+   assign lead = complement & reversed_mag;
+
+   //calculate fraction and exponent using shift value generated
+   wire [15:0] pre_frac = unsigned_mag << ((15 - binary_out));
+   assign fraction = {pre_frac[14:0],8'h0};
+   assign exponent = (in == 16'b0)?(8'b0):(binary_out +'d127);
+
+   //construct the output
+   assign out = {in[15], exponent, fraction};
+
+   //reverse the signed input
+   genvar r;
+
+   generate
+      for (r = 0; r < 16; r = r+1) begin:bit_reverse
+	assign reversed_mag[r] = unsigned_mag[BITS_IN-r-1];
+      end
+   endgenerate
+
+   //reversed the output of the detect the leading bit procedure
+   genvar i;
+   generate
+     for (i= 0; i < 16; i = i+1) begin: i_rev
+       assign binary_in[i] = lead[BITS_IN-i-1];
+     end
+   endgenerate
+endmodule
+
+
diff --git a/fpga/usrp3/lib/vita_200/iq_to_float_input.txt b/fpga/usrp3/lib/vita_200/iq_to_float_input.txt
new file mode 100644
index 000000000..c2efee360
--- /dev/null
+++ b/fpga/usrp3/lib/vita_200/iq_to_float_input.txt
@@ -0,0 +1,65536 @@
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diff --git a/fpga/usrp3/lib/vita_200/iq_to_float_output.txt b/fpga/usrp3/lib/vita_200/iq_to_float_output.txt
new file mode 100644
index 000000000..f1e10da1c
--- /dev/null
+++ b/fpga/usrp3/lib/vita_200/iq_to_float_output.txt
@@ -0,0 +1,65536 @@
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diff --git a/fpga/usrp3/lib/vita_200/iq_to_float_tb.v b/fpga/usrp3/lib/vita_200/iq_to_float_tb.v
new file mode 100644
index 000000000..932320a6a
--- /dev/null
+++ b/fpga/usrp3/lib/vita_200/iq_to_float_tb.v
@@ -0,0 +1,66 @@
+//
+// Copyright 2016 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+module iq_to_float_tb();
+
+
+   reg clk, reset;
+   integer x,file;
+   reg [15:0] in;
+   wire [31:0] out;
+   
+   initial clk = 0;
+   
+   always #10 clk = ~clk;
+
+   initial $dumpfile("iq_to_float_tb.vcd");
+   initial $dumpvars(0,iq_to_float_tb);
+   integer f;
+   initial
+    
+     begin
+	x <= 0;
+	reset <= 1;
+	in <= 0;
+    file = $fopen("iq_to_float_VER.txt");
+	
+	repeat(65536) @(posedge clk);
+	reset <= 0;
+	repeat(65536) @(posedge clk)
+	  begin
+	     in <= data[x];
+	     x  <= x+1;
+         $fdisplayh(file,out);
+	  end
+      $fclose(file);
+	
+	     
+	repeat(65536) @(posedge clk);
+	$finish;
+
+     end
+   
+  
+   
+
+    iq_to_float #(.BITS_IN(16), .BITS_OUT(32))
+   dut
+     (
+      .in(in), .out(out), .clk(clk), .reset(reset)
+      );
+
+   
+
+   reg 	     [15:0] data [0:65535];
+   initial $readmemh("iq_to_float_input.txt",data);
+
+  
+
+	
+	
+   
+   
+endmodule
+
diff --git a/fpga/usrp3/lib/vita_200/new_rx_control.v b/fpga/usrp3/lib/vita_200/new_rx_control.v
new file mode 100644
index 000000000..0896b7815
--- /dev/null
+++ b/fpga/usrp3/lib/vita_200/new_rx_control.v
@@ -0,0 +1,260 @@
+//
+// Copyright 2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+// HALT brings RX to an idle state as quickly as possible if RX is running
+// without running the risk of leaving a packet fragment in downstream FIFO's.
+// HALT also flushes all remaining pending commands in the commmand FIFO.
+// Unlike STOP, HALT doesn't ever create an ERROR packet.
+
+
+module new_rx_control
+  #(parameter BASE=0)
+   (input clk, input reset, input clear,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    
+    input [63:0] vita_time,
+    
+    // DDC connections
+    output run, output eob,
+    input strobe, input full,
+    input [11:0] seqnum,
+    input [31:0] sid,
+
+    output [63:0] err_tdata, output err_tlast, output err_tvalid, input err_tready,
+    output reg [3:0] ibs_state,
+    output [31:0] debug
+    );
+
+   wire [31:0] 	  command_i;
+   wire [63:0] 	  time_i;
+   wire 	  store_command;
+
+   wire 	  send_imm, chain, reload, stop;
+   wire [27:0] 	  numlines;
+   wire [63:0] 	  rcvtime;
+
+   wire 	  now, early, late;
+   wire 	  command_valid;
+   reg 		  command_ready;
+   
+   reg 		  chain_sav, reload_sav;
+
+   
+   reg 		  clear_halt;
+   reg 		  halt;
+   wire 	  set_halt;
+    
+   reg [63:0] 	  err_tdata_int;
+   wire 	  err_tlast_int;
+   wire 	  err_tvalid_int;
+   wire 	  err_tready_int;
+   
+
+   setting_reg #(.my_addr(BASE)) sr_cmd
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(command_i),.changed());
+
+   setting_reg #(.my_addr(BASE+1)) sr_time_h
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(time_i[63:32]),.changed());
+   
+   setting_reg #(.my_addr(BASE+2)) sr_time_l
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(time_i[31:0]),.changed(store_command));
+
+   setting_reg #(.my_addr(BASE+3)) sr_rx_halt
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(),.changed(set_halt));
+
+   always @(posedge clk)
+     if (reset | clear | clear_halt)
+       halt <= 1'b0;
+     else
+       halt <= set_halt;
+   
+   
+   axi_fifo_short #(.WIDTH(96)) commandfifo
+     (.clk(clk),.reset(reset),.clear(clear | clear_halt),
+      .i_tdata({command_i,time_i}), .i_tvalid(store_command), .i_tready(),
+      .o_tdata({send_imm,chain,reload,stop,numlines,rcvtime}),
+      .o_tvalid(command_valid), .o_tready(command_ready),
+      .occupied(), .space() );
+
+   time_compare 
+     time_compare (.clk(clk), .reset(reset), .time_now(vita_time), .trigger_time(rcvtime), 
+		   .now(now), .early(early), .late(late), .too_early());
+
+   localparam IBS_IDLE         = 0;
+   localparam IBS_RUNNING      = 1;
+   
+   localparam IBS_OVERRUN      = 2;
+   localparam IBS_OVR_TIME     = 3;
+   localparam IBS_OVR_DATA     = 4;
+   
+   localparam IBS_BROKENCHAIN  = 5;
+   localparam IBS_BRK_TIME     = 6;
+   localparam IBS_BRK_DATA     = 7;
+      
+   localparam IBS_LATECMD      = 8;
+   localparam IBS_LATE_TIME    = 9;
+   localparam IBS_LATE_DATA    = 10;
+   
+   localparam IBS_ZEROLEN      = 11;
+   localparam IBS_ZERO_TIME    = 12;
+   localparam IBS_ZERO_DATA    = 13;
+   
+   reg [27:0] 	  lines_left, repeat_lines;
+
+   
+   always @(posedge clk)
+     if(reset | clear)
+       begin
+	  ibs_state <= IBS_IDLE;
+	  chain_sav <= 1'b0;
+	  reload_sav <= 1'b0;
+	  clear_halt <= 1'b0;
+       end
+     else
+       case (ibs_state)
+	 IBS_IDLE : begin
+	   clear_halt <= 1'b0; // Incase we got here through a HALT.
+	   if (command_valid)
+	     // There is a valid command to pop from FIFO.
+	     if (stop) begin
+		// Stop bit set in this command, go idle.
+		ibs_state <= IBS_IDLE;//IBS_ZEROLEN;
+	     end else if (late & ~send_imm) begin
+		// Got this command later than its execution time.
+		ibs_state <= IBS_LATECMD;
+	     end else if (now | send_imm) begin
+		// Either its time to run this command or it should run immediately without a time.
+		ibs_state <= IBS_RUNNING;
+		lines_left <= numlines;
+		repeat_lines <= numlines;
+		chain_sav <= chain;
+		reload_sav <= reload;
+	     end
+	 end // case: IBS_IDLE
+	 
+	 IBS_RUNNING : begin 
+	    if (strobe) begin 
+	       if (full) begin
+		  // Framing FIFO is full and we have just overrun.
+		  ibs_state <= IBS_OVERRUN;
+	       end else if (lines_left == 1) begin
+		  // Provide Halt mechanism used to bring RX into known IDLE state
+		  // at re-initialization.
+		  if (halt) begin
+		     ibs_state <= IBS_IDLE;
+		     clear_halt <= 1'b1;
+		  end else if (chain_sav) begin
+		     // If chain_sav is true then execute the next command now this one finished.
+		     if (command_valid) begin
+			lines_left <= numlines;
+			repeat_lines <= numlines;
+			chain_sav <= chain;
+			reload_sav <= reload;
+			// If the new command includes stop then go idle.
+			if (stop) begin
+			   ibs_state <= IBS_IDLE;
+			end
+		     end else if (reload_sav) begin
+			// There is no new command to pop from FIFO so re-run previous command.
+			lines_left <= repeat_lines;
+		     end else begin
+			// Chain has been broken, no commands left in FIFO and reload not set.
+			ibs_state <= IBS_BROKENCHAIN;
+		     end
+		  end else begin // if (chain_sav)
+		     // Chain is not true, so don't look for new command, instead go idle.
+		     ibs_state <= IBS_IDLE;
+		  end
+	       end else begin // if (lines_left == 1)
+		  // Still counting down lines in current command.
+		  lines_left <= lines_left - 28'd1;
+	       end
+	    end // if (strobe)
+	 end // case: IBS_RUNNING
+	 
+	 
+	IBS_OVERRUN: if(err_tready_int) ibs_state <= IBS_OVR_TIME;
+	IBS_OVR_TIME: if(err_tready_int) ibs_state <= IBS_OVR_DATA;
+	IBS_OVR_DATA: if(err_tready_int) ibs_state <= IBS_IDLE;
+
+	IBS_BROKENCHAIN: if(err_tready_int) ibs_state <= IBS_BRK_TIME;
+	IBS_BRK_TIME: if(err_tready_int) ibs_state <= IBS_BRK_DATA;
+	IBS_BRK_DATA: if(err_tready_int) ibs_state <= IBS_IDLE;
+
+	IBS_LATECMD: if(err_tready_int) ibs_state <= IBS_LATE_TIME;
+	IBS_LATE_TIME: if(err_tready_int) ibs_state <= IBS_LATE_DATA;
+	IBS_LATE_DATA: if(err_tready_int) ibs_state <= IBS_IDLE;
+
+	IBS_ZEROLEN: if(err_tready_int) ibs_state <= IBS_ZERO_TIME;
+	IBS_ZERO_TIME: if(err_tready_int) ibs_state <= IBS_ZERO_DATA;
+	IBS_ZERO_DATA: if(err_tready_int) ibs_state <= IBS_IDLE;
+
+	default: ibs_state <= IBS_IDLE;
+
+       endcase // case (ibs_state)
+
+   always @*
+     case(ibs_state)
+       IBS_IDLE    : command_ready <= stop | late | now | send_imm;
+       IBS_RUNNING : command_ready <= strobe & (lines_left == 1) & chain_sav;
+       default     : command_ready <= 1'b0;
+     endcase // case (ibs_state)
+
+   assign run = (ibs_state == IBS_RUNNING);
+   assign eob = strobe && (lines_left == 1) && ( !chain_sav || (command_valid && stop) || (!command_valid && !reload_sav) || halt);
+
+   always @*
+     case (ibs_state)
+       IBS_OVERRUN : err_tdata_int <= { 4'hA, seqnum, 16'd24, sid };
+       IBS_OVR_TIME : err_tdata_int <= vita_time;
+       IBS_OVR_DATA : err_tdata_int <= {32'h8, 32'b0};
+
+       IBS_BROKENCHAIN : err_tdata_int <= { 4'hA, seqnum, 16'd24, sid };
+       IBS_BRK_TIME : err_tdata_int <= vita_time;
+       IBS_BRK_DATA : err_tdata_int <= {32'h4, 32'b0};
+
+       IBS_LATECMD : err_tdata_int <= { 4'hA, seqnum, 16'd24, sid };
+       IBS_LATE_TIME : err_tdata_int <= vita_time;
+       IBS_LATE_DATA : err_tdata_int <= {32'h2, 32'b0};
+
+       IBS_ZEROLEN : err_tdata_int <= { 4'hA, seqnum, 16'd24, sid };
+       IBS_ZERO_TIME : err_tdata_int <= vita_time;
+       IBS_ZERO_DATA : err_tdata_int <= {32'hd, 32'b0};
+
+       default : err_tdata_int <= {32'he, 32'b0};
+     endcase // case (ibs_state)
+   
+   assign err_tlast_int = (ibs_state == IBS_OVR_DATA) 
+     | (ibs_state == IBS_BRK_DATA) 
+       | (ibs_state == IBS_LATE_DATA) 
+	 | (ibs_state == IBS_ZERO_DATA);
+   
+   assign err_tvalid_int = ibs_state >= IBS_OVERRUN;
+
+
+   assign debug[27:0] = lines_left;
+   assign debug[28] = stop;
+   assign debug[29] = halt;
+   assign debug[30] = command_valid;
+   assign debug[31] = command_ready;
+   
+   axi_fifo_short #(.WIDTH(65)) output_fifo
+     (
+      .clk(clk), .reset(reset), .clear(clear),
+      .i_tdata({err_tlast_int,err_tdata_int}), .i_tvalid(err_tvalid_int), .i_tready(err_tready_int),
+      .o_tdata({err_tlast,err_tdata}), .o_tvalid(err_tvalid), .o_tready(err_tready),
+      .space(), .occupied()
+      );
+
+
+   
+endmodule // new_rx_control
diff --git a/fpga/usrp3/lib/vita_200/new_rx_framer.v b/fpga/usrp3/lib/vita_200/new_rx_framer.v
new file mode 100644
index 000000000..df91aff72
--- /dev/null
+++ b/fpga/usrp3/lib/vita_200/new_rx_framer.v
@@ -0,0 +1,282 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module new_rx_framer
+  #(
+    parameter BASE=0,
+    parameter CHIPSCOPE=0,
+    parameter SAMPLE_FIFO_SIZE=10
+    )
+   (input clk, input reset, input clear,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+    input [63:0] vita_time,
+
+    input strobe,
+    input [31:0] sample,
+    input run,
+    input eob,
+    output full,
+    output reg [11:0] seqnum,
+    output [31:0] sid,
+
+    output [63:0] o_tdata, output o_tlast, output o_tvalid, input o_tready,
+
+    output [31:0] debug
+    );
+
+   reg [15:0] 	  len;
+   reg [63:0] 	  hold_time;
+
+   wire [63:0] 	  dfifo_tdata;
+   wire 	  dfifo_tlast, dfifo_tvalid, dfifo_tready;
+
+   wire [80:0] 	  hfifo_tdata;
+   wire 	  hfifo_tvalid, hfifo_tready;
+
+   wire [63:0] 	  o_tdata_int;
+   wire 	  o_tlast_int, o_tvalid_int, o_tready_int;
+
+   wire [15:0] 	  sample_space;
+
+   wire [15:0] 	  maxlen;
+   reg [31:0] 	  holding;
+
+
+   // FIXME need to handle case where hdr fifo is full (i.e. too many tiny packets)
+   assign full = (sample_space == 16'd0) | (sample_space == 16'd1) | ~hdr_tready;
+
+   setting_reg #(.my_addr(BASE), .width(16)) sr_maxlen
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(maxlen),.changed());
+
+   wire sid_changed;
+   setting_reg #(.my_addr(BASE+1), .width(32)) sr_sid
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(sid),.changed(sid_changed));
+
+   localparam START = 0;
+   localparam SECOND = 1;
+   localparam FIRST = 2;
+
+   reg [1:0] 	  instate;
+   reg [15:0] 	  numsamps;
+   reg 		  nearly_eop;
+
+
+   always @(posedge clk)
+     if(reset | clear)
+       begin
+	  instate <= START;
+	  numsamps <= 0;
+	  nearly_eop <= 0;
+
+       end
+     else if (run)
+       case(instate)
+	 //
+	 // Start a new packet in this state
+	 //
+	 START :
+	   if(strobe)
+	     if(eop)
+	       begin
+		  instate <= START;
+		  numsamps <= 0;
+		  nearly_eop <= 0;
+	       end
+	     else
+	       begin
+		  instate <= SECOND;
+		  numsamps <= numsamps + 1;
+		  nearly_eop <= (numsamps >= (maxlen-2));
+	       end // else: !if(eop)
+	 //
+	 // Second 32 bit sample in a 64bit word
+	 //
+	 SECOND :
+	   if(strobe)
+	     if(eop)
+	       begin
+		  instate <= START;
+		  numsamps <= 0;
+		  nearly_eop <= 0;
+	       end
+	     else
+	       begin
+		  instate <= FIRST;
+		  numsamps <= numsamps + 1;
+		  nearly_eop <= (numsamps >= (maxlen-2));
+	       end // else: !if(eop)
+	 //
+	 // First 32bit sample in a 64bit word.
+	 //
+	 FIRST :
+	   if(strobe)
+	     if(eop)
+	       begin
+		  instate <= START;
+		  numsamps <= 0;
+		  nearly_eop <= 0;
+	       end
+	     else
+	       begin
+		  instate <= SECOND;
+		  numsamps <= numsamps + 1;
+		  nearly_eop <= (numsamps >= (maxlen-2));
+	       end
+       endcase // case (instate)
+     else  begin
+	  instate <= START;
+	  numsamps <= 0;
+	  nearly_eop <= 0;
+     end
+
+
+   always @(posedge clk)
+     if(strobe && run)
+       begin
+	  holding <= sample;
+	  if(instate == START)
+	    hold_time <= vita_time;
+       end
+
+   always @(posedge clk)
+     if(reset | clear)
+       len <= 5;
+     else
+       if(strobe && run)
+	 if(sample_tlast)
+	   len <= 5;
+	 else
+	   len <= len + 1;
+
+   always @(posedge clk)
+     if(reset | clear | sid_changed)
+       seqnum <= 12'd0;
+     else
+       if(o_tlast_int & o_tvalid_int & o_tready_int)
+	 seqnum <= seqnum + 12'd1;
+
+
+
+   wire 	  eop = eob | nearly_eop | full;
+
+   wire [63:0] 	  sample_tdata = (instate == SECOND) ? {holding, sample} : {sample, 32'h0};
+   wire 	  sample_tlast = eop;
+   wire 	  sample_tvalid = run & strobe & ( (instate == SECOND) | eop );
+   wire 	  sample_tready;
+
+   wire [80:0] 	  hdr_tdata = {eob,len[13:0],2'b0,(instate == START) ? vita_time : hold_time};
+   wire 	  hdr_tvalid = sample_tlast && sample_tvalid && sample_tready;
+   wire 	  hdr_tready;
+
+   wire [80:0] 	  hfifo_tdata_tmp;
+   wire 	  hfifo_tvalid_tmp, hfifo_tready_tmp;
+
+
+
+   axi_fifo #(.WIDTH(65), .SIZE(SAMPLE_FIFO_SIZE)) datafifo
+     (.clk(clk), .reset(reset), .clear(clear),
+      .i_tdata({sample_tlast,sample_tdata}), .i_tvalid(sample_tvalid), .i_tready(sample_tready),
+      .o_tdata({dfifo_tlast,dfifo_tdata}), .o_tvalid(dfifo_tvalid), .o_tready(dfifo_tready),
+      .space(sample_space), .occupied());
+
+   axi_fifo_short #(.WIDTH(81)) hdrfifo
+     (.clk(clk), .reset(reset), .clear(clear),
+      .i_tdata(hdr_tdata), .i_tvalid(hdr_tvalid), .i_tready(hdr_tready),
+      .o_tdata(hfifo_tdata_tmp), .o_tvalid(hfifo_tvalid_tmp), .o_tready(hfifo_tready_tmp),
+      .space(), .occupied());
+
+   axi_fifo_short #(.WIDTH(81)) hdrfifo2
+     (.clk(clk), .reset(reset), .clear(clear),
+      .i_tdata(hfifo_tdata_tmp), .i_tvalid(hfifo_tvalid_tmp), .i_tready(hfifo_tready_tmp),
+      .o_tdata(hfifo_tdata), .o_tvalid(hfifo_tvalid), .o_tready(hfifo_tready),
+      .space(), .occupied());
+
+
+
+
+   // The output state machine is responsible for forming output packets.
+   // Output packets are formed by combining the entries in the header fifo,
+   // and the samples in the data fifo. A single entry in the header fifo
+   // contains both the compressed header and the 64 bit time stamp.
+
+   reg [1:0] 	  outstate;
+   localparam OUT_IDLE = 2'd0;
+   localparam OUT_HEAD = 2'd1;
+   localparam OUT_TIME = 2'd2;
+   localparam OUT_BODY = 2'd3;
+
+   always @(posedge clk)
+     if(reset | clear)
+       outstate <= OUT_IDLE;
+     else
+       case(outstate)
+	 OUT_IDLE :
+	   if(hfifo_tvalid) //having a header signals a complete packet
+	     outstate <= OUT_HEAD;
+	 OUT_HEAD :
+	   if(o_tvalid_int && o_tready_int)
+	     outstate <= OUT_TIME;
+	 OUT_TIME :
+	   if(o_tvalid_int && o_tready_int)
+	     outstate <= OUT_BODY;
+	 OUT_BODY :
+	   if(o_tvalid_int && o_tready_int && o_tlast_int)
+	     outstate <= OUT_IDLE;
+       endcase // case (outstate)
+
+   //output data mux feeds from single line of header fifo or the data fifo
+   assign o_tdata_int = (outstate == OUT_HEAD) ? { 3'b001, hfifo_tdata[80], seqnum, hfifo_tdata[79:64], sid} :
+			(outstate == OUT_TIME) ? hfifo_tdata[63:0] : dfifo_tdata;
+
+   //output the last signal from the data fifo
+   assign o_tlast_int = (outstate == OUT_BODY) ? dfifo_tlast : 1'b0;
+
+   //output valid connected to data valid in non-IDLE states
+   assign o_tvalid_int = (outstate != OUT_IDLE) & dfifo_tvalid;
+
+   //only pop from header fifo on the very last transaction
+   assign hfifo_tready = o_tvalid_int && o_tready_int && o_tlast_int;
+
+   //connect data fifo ready with out ready in the BODY state
+   assign dfifo_tready = (outstate == OUT_BODY) ? o_tready_int : 1'b0;
+
+   axi_fifo_short #(.WIDTH(65)) output_fifo
+     (.clk(clk), .reset(reset), .clear(clear),
+      .i_tdata({o_tlast_int, o_tdata_int}), .i_tvalid(o_tvalid_int), .i_tready(o_tready_int),
+      .o_tdata({o_tlast, o_tdata}), .o_tvalid(o_tvalid), .o_tready(o_tready),
+      .space(), .occupied());
+/* -----\/----- EXCLUDED -----\/-----
+
+    assign debug[3:0] =  {instate, outstate};
+    assign debug[7:4] =  {1'b0, sample_tlast, sample_tvalid, sample_tready};
+    assign debug[11:8] =  {1'b0, 1'b0, hfifo_tvalid, hfifo_tready};
+    assign debug[15:12] =  {1'b0, dfifo_tlast, dfifo_tvalid, dfifo_tready};
+    assign debug[19:16] =  {1'b0, o_tlast_int, o_tvalid_int, o_tready_int};
+ -----/\----- EXCLUDED -----/\----- */
+
+   assign debug = {
+		   sample_tlast, //15
+		   sample_tvalid,//14
+		   sample_tready,//13
+		   dfifo_tvalid, //12
+		   dfifo_tready, //11
+		   hdr_tvalid,   //10
+		   hdr_tready,   //9
+		   hfifo_tvalid, //8
+		   hfifo_tready, //7
+		   eob,           //6
+		   nearly_eop,    //5
+		   full,          //4
+		   outstate[1:0], //3:2
+		   instate[1:0]   //1:0
+		   };
+
+
+endmodule // new_rx_framer
diff --git a/fpga/usrp3/lib/vita_200/new_rx_tb.v b/fpga/usrp3/lib/vita_200/new_rx_tb.v
new file mode 100644
index 000000000..045650192
--- /dev/null
+++ b/fpga/usrp3/lib/vita_200/new_rx_tb.v
@@ -0,0 +1,140 @@
+//
+// Copyright 2016 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+`timescale 1ns/1ps
+
+module new_rx_tb();
+
+   reg clk    = 0;
+   reg reset  = 1;
+   
+   always #10 clk = ~clk;
+   
+   initial $dumpfile("new_rx_tb.vcd");
+   initial $dumpvars(0,new_rx_tb);
+
+   initial
+     begin
+	#1000 reset = 0;
+	#30000;
+	$finish;
+     end
+   
+   reg [7:0]   set_addr;
+   reg [31:0]  set_data;
+   reg 	       set_stb = 1'b0;
+   
+   reg [63:0]  vita_time;
+   reg [31:0]  sample;
+   reg 	       strobe;
+   
+   wire        run, full;
+
+   wire [63:0] err_tdata;
+   wire        err_tlast, err_tvalid, err_tready;
+
+   wire [63:0] o_tdata;
+   wire        o_tlast, o_tvalid;
+   reg 	       o_tready;
+   
+   task send_command;
+      input [63:0] send_time;
+      input 	   send_at;
+      input 	   chain;
+      input 	   reload;
+      input 	   stop;
+      input [31:0] len;
+
+      begin
+	 set_stb <= 1;
+	 set_addr <= 0;
+	 set_data <= { send_at, chain, reload, stop, len };
+	 @(posedge clk);
+	 set_stb <= 1;
+	 set_addr <= 1;
+	 set_data <= send_time[63:32];
+	 @(posedge clk);
+	 set_stb <= 1;
+	 set_addr <= 2;
+	 set_data <= send_time[31:0];
+	 @(posedge clk);
+	 set_stb <= 0;
+	 @(posedge clk);
+      end
+   endtask // send_command
+   
+   initial
+     begin
+	o_tready <= 0;
+	while(reset)
+	  @(posedge clk);
+	set_stb <= 1;   // Set Max Length of Packet
+	set_addr <= 8; 
+	set_data <= 18;
+	@(posedge clk);
+	set_stb <= 1;   // Set SID
+	set_addr <= 9; 
+	set_data <= 32'hF00D_1234;
+	@(posedge clk);
+	
+	send_command(64'h100/*time*/, 1/*send at*/, 0/*chain*/, 0/*reload*/,0/*stop*/,150/*len*/);
+	send_command(64'h200/*time*/, 1/*send at*/, 0/*chain*/, 0/*reload*/,0/*stop*/,4/*len*/);
+	//send_command(64'h100/*time*/, 1/*send at*/, 0/*chain*/, 0/*reload*/,0/*stop*/,5/*len*/);
+
+	#8000;
+	o_tready <= 1;
+     end // initial begin
+   
+   always @(posedge clk)
+     if(reset)
+       vita_time <= 0;
+     else
+       vita_time <= vita_time + 1;
+
+   new_rx_control #(.BASE(0)) rx_control
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .vita_time(vita_time),
+      .run(run), .eob(eob), .strobe(strobe), .full(full),
+      .err_tdata(err_tdata), .err_tlast(err_tlast), .err_tvalid(err_tvalid), .err_tready(err_tready),
+      .debug());
+
+   new_rx_framer #(.BASE(8)) rx_framer
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .vita_time(vita_time),
+      .strobe(strobe), .sample(sample), .run(run), .eob(eob), .full(full),
+      .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready)
+      );
+   
+   always @*
+     strobe <= run;
+
+   /*
+   always @(posedge clk)
+     if(reset)
+       sample <= 0;
+     else if(run)
+       sample <= sample + 1;
+    */
+   always @* sample <= vita_time[31:0];
+   
+   always @(posedge clk)
+     if(o_tvalid & o_tready)
+       if(o_tlast)
+	 $display("%x\tLAST\n",o_tdata);
+       else
+	 $display("%x",o_tdata);
+
+   assign err_tready = 1;
+   
+   always @(posedge clk)
+     if(err_tvalid & err_tready)
+       if(err_tlast)
+	 $display("\t\t\t\tERR LAST \t%x",err_tdata);
+       else
+	 $display("\t\t\t\tERR\t\t%x",err_tdata);
+   
+endmodule // new_rx_tb
diff --git a/fpga/usrp3/lib/vita_200/new_tx_control.v b/fpga/usrp3/lib/vita_200/new_tx_control.v
new file mode 100644
index 000000000..b694c09af
--- /dev/null
+++ b/fpga/usrp3/lib/vita_200/new_tx_control.v
@@ -0,0 +1,198 @@
+//
+// Copyright 2014-2016 Ettus Research
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+module new_tx_control
+  #(parameter BASE=0)
+   (input clk, input reset, input clear,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+    input [63:0] vita_time,
+    output reg ack_or_error,
+    output packet_consumed,
+    output [11:0] seqnum,
+    output reg [63:0] error_code,
+    output [31:0] sid,
+
+    // From tx_deframer
+    input [175:0] sample_tdata,
+    input sample_tvalid,
+    output sample_tready,
+
+    // To DSP Core
+    output [31:0] sample,
+    output run,    input strobe,
+
+    output [31:0] debug
+);
+
+   wire [31:0] sample1 = sample_tdata[31:0];
+   wire [31:0] sample0 = sample_tdata[63:32];
+   wire [63:0] send_time = sample_tdata[127:64];
+
+   assign sid = sample_tdata[159:128];
+   assign seqnum = sample_tdata[171:160];
+
+   wire eop = sample_tdata[172];
+   wire eob = sample_tdata[173];
+   wire send_at = sample_tdata[174];
+   wire odd = sample_tdata[175];
+
+   wire now, early, late, too_early;
+   wire policy_next_burst, policy_next_packet, policy_wait;
+   wire clear_seqnum_int;
+
+   setting_reg #(.my_addr(BASE), .width(3)) sr_error_policy
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({policy_next_burst,policy_next_packet,policy_wait}),.changed(clear_seqnum_int));
+
+   time_compare
+     time_compare (.clk(clk), .reset(reset), .time_now(vita_time), .trigger_time(send_time),
+                   .now(now), .early(early), .late(late), .too_early(too_early));
+
+   assign run = (state == ST_SAMP0) | (state == ST_SAMP1);
+   assign sample = (state == ST_SAMP0) ? sample0 : sample1;
+
+   reg [2:0] state;
+
+   localparam ST_IDLE  = 0;
+   localparam ST_SAMP0 = 1;
+   localparam ST_SAMP1 = 2;
+   localparam ST_ERROR = 3;
+   localparam ST_WAIT  = 4;
+
+   reg [11:0] expected_seqnum;
+
+   wire [63:0] CODE_EOB_ACK            = {32'd1,20'd0,seqnum};
+   wire [63:0] CODE_UNDERRUN           = {32'd2,20'd0,seqnum};
+   wire [63:0] CODE_SEQ_ERROR          = {32'd4,4'd0,expected_seqnum,4'd0,seqnum};
+   wire [63:0] CODE_TIME_ERROR         = {32'd8,20'd0,seqnum};
+   wire [63:0] CODE_UNDERRUN_MIDPKT    = {32'd16,20'd0,seqnum};
+   wire [63:0] CODE_SEQ_ERROR_MIDBURST = {32'd32,4'd0,expected_seqnum,4'd0,seqnum};
+
+   reg clear_seqnum_latch;
+
+   wire burst_start = sample_tvalid & (~send_at | now);
+   wire last_sample = sample_tvalid & sample_tready & eop;
+   wire time_to_clear = clear_seqnum_latch && (
+                        (last_sample && eob) ||
+                        (state == ST_ERROR) ||
+                        (state == ST_IDLE && ~burst_start));
+
+   always @(posedge clk) begin
+     if(reset | clear) begin
+       expected_seqnum <= 12'd0;
+       clear_seqnum_latch <= 0;
+     end else begin
+       if(clear_seqnum_int) begin
+         clear_seqnum_latch <= 1;
+       end
+       if(time_to_clear) begin
+         expected_seqnum <= 12'd0;
+         clear_seqnum_latch <= 0;
+       end else if(last_sample) begin
+         expected_seqnum <= seqnum + 12'd1;
+       end
+     end
+   end
+
+   always @(posedge clk)
+     if(reset | clear) begin
+       state <= ST_IDLE;
+       ack_or_error <= 1'b0;
+       error_code <= 64'd0;
+     end else begin
+       case(state)
+       ST_IDLE :
+         begin
+            ack_or_error <= 1'b0;
+            if(sample_tvalid)
+          if(~send_at | now)
+            if(expected_seqnum != seqnum)
+              begin
+                state <= ST_ERROR;
+                ack_or_error <= 1'b1;
+                error_code <= CODE_SEQ_ERROR;
+              end
+            else
+              state <= ST_SAMP0;
+          else if(late)
+            begin
+              state <= ST_ERROR;
+              ack_or_error <= 1'b1;
+              error_code <= CODE_TIME_ERROR;
+            end
+         end // case: ST_IDLE
+       ST_SAMP0 :
+         if(strobe)
+           if(~sample_tvalid)
+             begin
+               state <= ST_ERROR;
+               ack_or_error <= 1'b1;
+               error_code <= CODE_UNDERRUN;
+             end
+           else if(eop & odd & eob)
+             begin
+               state <= ST_IDLE;
+               ack_or_error <= 1'b1;
+               error_code <= CODE_EOB_ACK;
+             end
+           else if(eop & odd)
+             state <= ST_SAMP0;
+           else if(expected_seqnum != seqnum)
+             begin
+               state <= ST_ERROR;
+               ack_or_error <= 1'b1;
+               error_code <= CODE_SEQ_ERROR_MIDBURST;
+             end
+           else
+             state <= ST_SAMP1;
+       ST_SAMP1 :
+         if(strobe)
+           if(eop & eob)
+             begin
+               state <= ST_IDLE;
+               ack_or_error <= 1'b1;
+               error_code <= CODE_EOB_ACK;
+             end
+           else
+             state <= ST_SAMP0;
+       ST_ERROR :
+         begin
+           ack_or_error <= 1'b0;
+             if(sample_tvalid & eop)
+               if(policy_next_packet | (policy_next_burst & eob)) begin
+                 state <= ST_IDLE;
+               end
+          // FIXME: Implement a wait state or remove wait policy
+          // else if(policy_wait)
+          //   state <= ST_WAIT;
+         end
+       endcase // case (state)
+     end
+
+   assign sample_tready = (state == ST_ERROR) | (strobe & ( (state == ST_SAMP1) | ((state == ST_SAMP0) & eop & odd) ) );
+
+   assign packet_consumed = eop & sample_tvalid & sample_tready;
+
+   assign debug = {
+     error_code[37:32], // [30:25]
+     error_code[11:0], // [24:13]
+     sample_tvalid, //[12]
+     now, // [11]
+     early, // [10]
+     late, // [9]
+     too_early, // [8]
+     strobe,  // [7]
+     eop, // [6]
+     eob, // [5]
+     send_at, // [4]
+     odd,  // [3]
+     state[2:0] //  [2:0]
+   };
+
+endmodule // new_tx_control
diff --git a/fpga/usrp3/lib/vita_200/new_tx_control_tb.v b/fpga/usrp3/lib/vita_200/new_tx_control_tb.v
new file mode 100644
index 000000000..de33ce14c
--- /dev/null
+++ b/fpga/usrp3/lib/vita_200/new_tx_control_tb.v
@@ -0,0 +1,145 @@
+//
+// Copyright 2016 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+`timescale 1ns/1ps
+
+module new_tx_control_tb();
+
+   reg clk    = 0;
+   reg reset  = 1;
+   
+   always #10 clk = ~clk;
+   
+   initial $dumpfile("new_tx_control_tb.vcd");
+   initial $dumpvars(0,new_tx_control_tb);
+
+   initial
+     begin
+	#1000 reset = 0;
+	#30000;
+	$finish;
+     end
+   
+   reg [143:0]  tdata;
+   reg 		tlast;
+   wire 	tlast_int;
+   reg 		tvalid = 1'b0;
+   wire 	tready;
+   
+   reg [7:0] 	set_addr;
+   reg [31:0] 	set_data;
+   reg 		set_stb = 1'b0;
+   
+   reg [31:0] 	samp0, samp1;
+   
+   task send_packet;
+      input [31:0] count;
+      input [31:0] start_data;
+      input [63:0] send_time;
+      input [11:0] pkt_seqnum;
+      input 	   eop;
+      input 	   eob;
+      input 	   send_at;
+      input 	   odd;
+      
+      begin
+	 // Send a packet
+	 samp0 <= start_data;
+	 samp1 <= start_data + 1;
+	 @(posedge clk);
+	 repeat (count-1)
+	   begin
+	      tdata <= { 1'b0,send_at,1'b0,1'b0,1'b0,pkt_seqnum,send_time,samp0,samp1 };
+	      tvalid <= 1;
+	      samp0 <= samp0 + 2;
+	      samp1 <= samp1 + 2;
+	      @(posedge clk);
+	   end
+	 
+	 tdata <= { odd,send_at,1'b0,eob,eop,pkt_seqnum,send_time,samp0,samp1 };
+	 @(posedge clk);
+	 
+	 tvalid <= 0;	 
+	 @(posedge clk);
+      end
+   endtask // send_packet
+   
+   initial
+     begin
+	tvalid <= 1'b0;
+	while(reset)
+	  @(posedge clk);
+	set_addr <= 8'd0;
+	set_data <= 32'd2;
+	set_stb <= 1'b1;
+	@(posedge clk);
+	set_stb <= 1'b0;
+	
+	// Single Packet burst, timed
+	send_packet(3/*count*/,32'hA000_0000/*data*/,64'h100/*time*/,1/*SEQ*/,1/*EOP*/,1/*eob*/,1/*timed*/,0/*odd*/);
+
+	// 2 packet burst, timed
+	//send_packet(3/*count*/,32'hB000_0000/*data*/,64'h200/*time*/,2/*SEQ*/,1/*EOP*/,0/*eob*/,1/*timed*/,0/*odd*/);
+	//send_packet(3/*count*/,32'hC000_0000/*data*/,64'h0/*time*/,3/*SEQ*/,1/*EOP*/,1/*eob*/,0/*timed*/,0/*odd*/);
+	
+	// single odd packet
+	//send_packet(3/*count*/,32'h0A00_0000/*data*/,64'h300/*time*/,4/*SEQ*/,1/*EOP*/,1/*eob*/,1/*timed*/,1/*odd*/);
+
+	// 2 packet burst, timed, odd
+	//send_packet(3/*count*/,32'hD000_0000/*data*/,64'h400/*time*/,5/*SEQ*/,1/*EOP*/,0/*eob*/,1/*timed*/,1/*odd*/);
+	//send_packet(3/*count*/,32'hE000_0000/*data*/,64'd0/*time*/,6/*SEQ*/,1/*EOP*/,1/*eob*/,0/*timed*/,1/*odd*/);
+
+	// 2 packet burst, untimed, no eob set
+	//send_packet(3/*count*/,32'hF000_0000/*data*/,64'd0/*time*/,7/*SEQ*/,1/*EOP*/,0/*eob*/,0/*timed*/,0/*odd*/);
+	//send_packet(3/*count*/,32'h9000_0000/*data*/,64'd0/*time*/,8/*SEQ*/,1/*EOP*/,0/*eob*/,0/*timed*/,0/*odd*/);
+	
+	// single packet late
+	send_packet(3/*count*/,32'hD000_0000/*data*/,64'h0/*time*/,4/*SEQ*/,1/*EOP*/,1/*eob*/,1/*timed*/,1/*odd*/);
+
+     end
+
+   reg [63:0] vita_time;
+   wire [31:0] sample;
+   wire [143:0] sample_tdata;
+   wire 	sample_tready, sample_tvalid;
+   wire [11:0] 	seqnum;
+   wire [31:0] 	error_code;
+   
+   always @(posedge clk)
+     if(reset)
+       vita_time <= 0;
+     else
+       vita_time <= vita_time + 1;
+   
+   axi_fifo #(.WIDTH(144)) axi_fifo_short
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata(tdata), .i_tvalid(tvalid), .i_tready(tready),
+      .o_tdata(sample_tdata), .o_tvalid(sample_tvalid), .o_tready(sample_tready));
+
+   new_tx_control new_tx_control
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+
+      .vita_time(vita_time),
+      .error(error), .ack(ack), .packet_consumed(consumed), .seqnum(seqnum), .error_code(error_code),
+
+      .sample_tdata(sample_tdata), .sample_tvalid(sample_tvalid), .sample_tready(sample_tready),
+
+      .sample(sample), .run(run), .strobe(strobe),
+      .debug()
+      );
+
+   assign strobe = run;
+   
+   always @(posedge clk)
+     begin
+	if(strobe)
+	  $display("%x\t%x", vita_time, sample);
+	if(consumed) $display("CONSUMED %x", seqnum);
+	if(ack) $display("ACK %x", seqnum);
+	if(error) $display("ERROR %x\t%x", seqnum,error_code);
+     end
+   
+endmodule // new_tx_control_tb
diff --git a/fpga/usrp3/lib/vita_200/new_tx_deframer.v b/fpga/usrp3/lib/vita_200/new_tx_deframer.v
new file mode 100644
index 000000000..73920fe44
--- /dev/null
+++ b/fpga/usrp3/lib/vita_200/new_tx_deframer.v
@@ -0,0 +1,97 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module new_tx_deframer
+  (input clk, input reset, input clear,
+   input [63:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
+   output [175:0] sample_tdata, output sample_tvalid, input sample_tready, output [31:0] debug);
+
+   reg 		  odd, send_at, eob;
+   reg [11:0] 	  seqnum;
+   reg [31:0] 	  sid;
+   reg [63:0] 	  send_time;
+      
+   wire [175:0]   fifo_tdata = { odd, send_at, eob, i_tlast, seqnum/*12*/, sid, send_time/*64*/, i_tdata/*64*/ };
+   wire 	  fifo_tvalid, fifo_tready;
+
+   reg [1:0] 	  td_state;
+   localparam TD_HEAD = 0;
+   localparam TD_TIME = 1;
+   localparam TD_BODY = 2;
+   localparam TD_DUMP = 3;
+
+   always @(posedge clk)
+     if(reset | clear)
+       begin
+	  td_state <= TD_HEAD;
+	  odd <= 1'b0;
+	  send_at <= 1'b0;
+	  eob <= 1'b0;
+	  seqnum <= 12'd0;
+	  sid <= 32'd0;
+	  send_time <= 64'h0;
+       end // if (reset | clear)
+     else
+       case(td_state)
+	 TD_HEAD :
+	   if(i_tvalid)
+	     begin
+		if(~i_tlast)
+		  if(i_tdata[63])
+		    td_state <= TD_DUMP;
+		  else if(i_tdata[61])
+		    td_state <= TD_TIME;
+		  else
+		    td_state <= TD_BODY;
+		odd <= i_tdata[34];
+		send_at <= i_tdata[61];
+		eob <= i_tdata[60];
+		seqnum <= i_tdata[59:48];
+		sid <= i_tdata[31:0];
+		// FIXME record trailer, length, and SID here
+	     end
+	 TD_TIME :
+	   if(i_tvalid)
+	     begin
+		send_time <= i_tdata;
+		if(~i_tlast)
+		  td_state <= TD_BODY;
+		else
+		  td_state <= TD_HEAD;
+	     end
+	 TD_BODY :
+	   if(i_tvalid & fifo_tready)
+	     if(i_tlast)
+	       td_state <= TD_HEAD;
+	 TD_DUMP :
+	   if(i_tvalid)
+	     if(i_tlast)
+	       td_state <= TD_HEAD;
+       endcase // case (td_state)
+
+   assign fifo_tvalid = i_tvalid & (td_state == TD_BODY);
+   assign i_tready = (td_state == TD_BODY) ? fifo_tready : 1'b1;
+   
+   axi_fifo_short #(.WIDTH(176)) ofifo
+     (.clk(clk), .reset(reset), .clear(clear),
+      .i_tdata(fifo_tdata), .i_tvalid(fifo_tvalid), .i_tready(fifo_tready),
+      .o_tdata(sample_tdata), .o_tvalid(sample_tvalid), .o_tready(sample_tready),
+      .space(), .occupied());
+
+
+   assign debug = {
+		   sample_tvalid, // [8]
+		   sample_tready, // [7]
+		   i_tvalid,  // [6]
+		   i_tready,  // [5]
+		   td_state,  // [4:3]
+		   odd,       // [2]
+		   send_at,   // [1]
+		   eob        // [0]
+		   };
+   
+endmodule // new_tx_deframer
diff --git a/fpga/usrp3/lib/vita_200/new_tx_tb.v b/fpga/usrp3/lib/vita_200/new_tx_tb.v
new file mode 100644
index 000000000..29926fd78
--- /dev/null
+++ b/fpga/usrp3/lib/vita_200/new_tx_tb.v
@@ -0,0 +1,366 @@
+//
+// Copyright 2016 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+`timescale 1ns/1ps
+
+module new_tx_tb();
+`ifdef ISIM
+`else //iverilog implied.
+   xlnx_glbl glbl (.GSR(),.GTS());
+`endif
+   
+
+   localparam SR_TX_DSP        = 8;
+   localparam SR_TX_RESPONDER  = 16;
+   localparam SR_TX_CTRL       = 24;
+      
+   localparam SR_CYCLES =    SR_TX_RESPONDER + 0;
+   localparam SR_PACKETS =   SR_TX_RESPONDER + 1;
+   
+   localparam SR_PHASE_INC =    SR_TX_DSP + 0;
+   localparam SR_SCALE_FACTOR = SR_TX_DSP + 1;
+   localparam SR_INTERP =       SR_TX_DSP + 2;
+
+   localparam SR_ERROR_POLICY = SR_TX_CTRL + 0;
+   
+
+   reg clk    = 0;
+   reg reset  = 1;
+   
+   always #10 clk = ~clk;
+   
+   initial $dumpfile("new_tx_tb.vcd");
+   initial $dumpvars(0,new_tx_tb);
+   wire run, strobe;
+   
+   initial
+     begin
+	#1000 reset = 0;
+	#30000;
+	$finish;
+     end
+   
+   reg [63:0]  tdata;
+   reg 	       tlast;
+   reg 	       tvalid = 1'b0;
+   wire        tready;
+
+   wire [63:0] i_tdata;
+   wire        i_tlast, i_tvalid, i_tready;
+   
+   reg [7:0]   set_addr;
+   reg [31:0]  set_data;
+   reg 	       set_stb = 1'b0;
+   
+   reg [63:0]  vita_time;
+   wire [31:0] sample;
+   
+   wire [175:0] sample_tdata;
+   wire 	sample_tready, sample_tvalid;
+   
+   wire [11:0] 	seqnum;
+   wire [63:0] 	error_code;
+   wire [31:0] 	sid;
+   
+   reg [31:0] 	samp0, samp1;
+
+   reg [11:0] 	seqno;
+
+   wire 	ack_or_error, packet_consumed;
+   
+   
+   //
+   // Task Libaray
+   //
+   task write_setting_bus;
+      input [7:0] address;
+      input [31:0] data;
+
+      begin
+
+	 @(negedge clk);
+	 set_stb = 1'b0;
+	 set_addr = 8'h0;
+	 set_data = 32'h0;
+	 @(negedge clk);
+	 set_stb = 1'b1;
+	 set_addr = address;
+	 set_data = data;
+	 @(negedge clk);
+	 set_stb = 1'b0;
+	 set_addr = 8'h0;
+	 set_data = 32'h0;
+
+      end
+   endtask // write_setting_bus
+
+
+   task send_ramp;
+      input [31:0] burst_count;
+      input [31:0] len;
+      input [31:0] sid;
+
+      reg [31:0] data;
+
+      begin
+	 seqno = 0;
+	 data = 0;
+	 send_packet(len, data, 0, seqno, (burst_count==1), 0, sid);
+	 seqno = seqno + 1;
+	 data <= data + len;
+
+	 if(burst_count > 2)
+	   repeat (burst_count - 2)
+	     begin
+		send_packet(len, data, 64'h0, seqno, 0, 0, sid);
+		seqno = seqno + 1;
+		data <= data + len;
+	     end
+	 if(burst_count > 1)
+	   send_packet(len, data, 64'h0, seqno, 1, 0, sid);
+      end
+   endtask // send_ramp
+
+
+   task send_dc;
+      input [31:0] burst_count;
+      input [31:0] len;
+      input [31:0] sid;
+
+      reg [31:0] data;
+
+      begin
+	 seqno = 0;
+	 data = 1 << 14;
+	 send_packet(len, data, 0, seqno, (burst_count==1), 0, sid);
+	 seqno = seqno + 1;
+
+
+	 if(burst_count > 2)
+	   repeat (burst_count - 2)
+	     begin
+		send_packet(len, data, 64'h0, seqno, 0, 0, sid);
+		seqno = seqno + 1;
+
+	     end
+	 if(burst_count > 1)
+	   send_packet(len, data, 64'h0, seqno, 1, 0, sid);
+      end
+   endtask // send_ramp
+
+   task send_burst;
+      input [31:0] burst_count;
+      input [31:0] len;
+      input [31:0] start_data;
+      input [63:0] send_time;
+      input [11:0] start_seqnum;
+      input 	   send_at;
+      input [31:0] sid;
+      
+      begin
+	 seqno = start_seqnum;
+	 send_packet(len, {seqno,start_data[15:0]}, send_time, seqno, (burst_count==1), send_at, sid);
+	 seqno = seqno + 1;
+	 
+	 if(burst_count > 2)
+	   repeat (burst_count - 2)
+	     begin
+		send_packet(len, {seqno,start_data[15:0]}, 64'h0, seqno, 0, 0, sid);
+		seqno = seqno + 1;
+	     end
+	 if(burst_count > 1)
+	   send_packet(len, {seqno,start_data[15:0]}, 64'h0, seqno, 1, 0, sid);
+      end
+   endtask // send_burst
+
+   task send_burst_with_seqid_error;
+      input [31:0] burst_count;
+      input [31:0] len;
+      input [31:0] start_data;
+      input [63:0] send_time;
+      input [11:0] start_seqnum;
+      input 	   send_at;
+      input [31:0] sid;
+
+     
+      begin
+	 seqno = start_seqnum;
+	 send_packet(len, {seqno,start_data[15:0]}, send_time, seqno, (burst_count==1), send_at, sid);
+	 seqno = seqno + 1;
+	 
+	 if(burst_count > 2)
+	   repeat (burst_count - 2)
+	     begin
+		// Add a SeqID error in the middle of the packet burst
+		if (seqno == (start_seqnum + burst_count/2))
+		  seqno = seqno + 1;
+		send_packet(len, {seqno,start_data[15:0]}, 64'h0, seqno, 0, 0, sid);
+		seqno = seqno + 1;
+	     end
+	 if(burst_count > 1)
+	   send_packet(len, {seqno,start_data[15:0]}, 64'h0, seqno, 1, 0, sid);
+      end
+   endtask // send_burst
+   
+   task send_packet;
+      input [31:0] len;
+      input [31:0] start_data;
+      input [63:0] send_time;
+      input [11:0] pkt_seqnum;
+      input 	   eob;
+      input 	   send_at;
+      input [31:0] sid;
+      
+      begin
+	 // Send a packet
+	 samp0 <= start_data;
+	 samp1 <= start_data + 1;
+	 @(posedge clk);
+
+	 tlast <= 0;
+	 tdata <= { 1'b0, 1'b0 /*trl*/, send_at, eob, pkt_seqnum, len[15:0]+16'd2+send_at+send_at, sid };
+	 tvalid <= 1;
+	 @(posedge clk)
+	 if(send_at)
+	   begin
+	      tdata <= send_time;
+	      @(posedge clk);
+	   end
+
+	 repeat (len[31:1]+len[0]-1)
+	   begin
+	      tdata <= {samp0,samp1};
+	      samp0 <= samp0 + 2;
+	      samp1 <= samp1 + 2;
+	      @(posedge clk);
+	   end
+	 
+	 tdata <= {samp0,samp1};
+	 tlast <= 1'b1;
+	 @(posedge clk);
+	 tvalid <= 0;	 
+	 @(posedge clk);
+      end
+   endtask // send_packet
+
+`ifdef SIM_SCRIPT
+   // Load simulation script from local directory
+`include "simulation_script.v"
+   
+`else
+   initial
+     begin
+	tvalid <= 1'b0;
+	while(reset)
+	  @(posedge clk);
+	write_setting_bus(SR_ERROR_POLICY,32'h4);
+	write_setting_bus(SR_PACKETS,32'h8000_0002);
+
+	write_setting_bus(SR_INTERP,32'h1);
+	
+	send_burst(2/*count*/,5/*len*/,32'hA000_0000/*start*/,64'h100/*time*/,12'h000/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
+	//send_burst(3/*count*/,6/*len*/,32'hB000_0000/*start*/,64'h0/*time*/,12'h004/*seqnum*/,0/*sendat*/, 32'hDEADBEEF/*sid*/);
+
+	//Intra burst seq_id error
+	send_burst_with_seqid_error(8/*count*/,10/*len*/,32'hC000_0000/*start*/,64'h200/*time*/,12'h002/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
+
+	
+	// Inter burst sequence error
+	send_burst(2/*count*/,10/*len*/,32'hC000_0000/*start*/,64'h300/*time*/,12'h015/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
+
+	// Single Packet burst, timed
+	//send_packet(3/*count*/,32'hA000_0000/*data*/,64'h100/*time*/,1/*SEQ*/,1/*EOP*/,1/*eob*/,1/*timed*/,0/*odd*/);
+
+	// 2 packet burst, timed
+	//send_packet(3/*count*/,32'hB000_0000/*data*/,64'h200/*time*/,2/*SEQ*/,1/*EOP*/,0/*eob*/,1/*timed*/,0/*odd*/);
+	//send_packet(3/*count*/,32'hC000_0000/*data*/,64'h0/*time*/,3/*SEQ*/,1/*EOP*/,1/*eob*/,0/*timed*/,0/*odd*/);
+	
+	// single odd packet
+	//send_packet(3/*count*/,32'h0A00_0000/*data*/,64'h300/*time*/,4/*SEQ*/,1/*EOP*/,1/*eob*/,1/*timed*/,1/*odd*/);
+
+	// 2 packet burst, timed, odd
+	//send_packet(3/*count*/,32'hD000_0000/*data*/,64'h400/*time*/,5/*SEQ*/,1/*EOP*/,0/*eob*/,1/*timed*/,1/*odd*/);
+	//send_packet(3/*count*/,32'hE000_0000/*data*/,64'd0/*time*/,6/*SEQ*/,1/*EOP*/,1/*eob*/,0/*timed*/,1/*odd*/);
+
+	// 2 packet burst, untimed, no eob set
+	//send_packet(3/*count*/,32'hF000_0000/*data*/,64'd0/*time*/,7/*SEQ*/,1/*EOP*/,0/*eob*/,0/*timed*/,0/*odd*/);
+	//send_packet(3/*count*/,32'h9000_0000/*data*/,64'd0/*time*/,8/*SEQ*/,1/*EOP*/,0/*eob*/,0/*timed*/,0/*odd*/);
+	
+	// single packet late
+	//send_packet(3/*count*/,32'hD000_0000/*data*/,64'h0/*time*/,4/*SEQ*/,1/*EOP*/,1/*eob*/,1/*timed*/,1/*odd*/);
+
+     end
+`endif // !`ifdef SIM_SCRIPT
+   
+   always @(posedge clk)
+     if(reset)
+       vita_time <= 0;
+     else
+       vita_time <= vita_time + 1;
+   
+   axi_fifo #(.WIDTH(65)) axi_fifo_short
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata({tlast,tdata}), .i_tvalid(tvalid), .i_tready(tready),
+      .o_tdata({i_tlast,i_tdata}), .o_tvalid(i_tvalid), .o_tready(i_tready));
+
+   new_tx_deframer new_tx_deframer
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata(i_tdata), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready),
+      .sample_tdata(sample_tdata), .sample_tvalid(sample_tvalid), .sample_tready(sample_tready));
+   
+   new_tx_control #(.BASE(SR_TX_CTRL)) new_tx_control
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+
+      .vita_time(vita_time),
+      .ack_or_error(ack_or_error), .packet_consumed(packet_consumed),
+      .seqnum(seqnum), .error_code(error_code), .sid(sid),
+
+      .sample_tdata(sample_tdata), .sample_tvalid(sample_tvalid), .sample_tready(sample_tready),
+
+      .sample(sample), .run(run), .strobe(strobe),
+      .debug()
+      );
+
+   wire [63:0] o_tdata;
+   wire        o_tlast, o_tvalid, o_tready;
+   assign o_tready = 1;
+   
+   tx_responder #(.BASE(SR_TX_RESPONDER)) tx_responder
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .ack_or_error(ack_or_error), .packet_consumed(packet_consumed),
+      .seqnum(seqnum), .error_code(error_code), .sid(sid),
+      .vita_time(vita_time),
+      .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready));
+   
+   always @(posedge clk)
+     if(o_tvalid & o_tready)
+       $display("\t\t\t\t\tRESP %x\t%x",o_tdata,o_tlast);
+   
+   always @(posedge clk)
+     if(~reset)
+       begin
+	  if(strobe & run)
+	    $display("%x\t%x", vita_time, sample);
+	  if(strobe & ~run) $display("Spurious Strobe at time %x",vita_time);
+	  if(packet_consumed) $display("CONSUMED %x", seqnum);
+	  if(ack_or_error)
+	    if(error_code[63:32] == 1)
+	      $display("ACK -- SEQNUM %x", error_code[31:0]);
+	    else
+	      $display("ERROR -- SEQNUM %x ERRCODE %x", error_code[31:0],error_code[63:32]);
+       end
+   
+   wire [23:0] tx_fe_i, tx_fe_q;
+
+   duc_chain #(.BASE(SR_TX_DSP), .DSPNO(0), .WIDTH(24)) duc_chain
+     (.clk(clk), .rst(reset), .clr(1'b0),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .tx_fe_i(tx_fe_i),.tx_fe_q(tx_fe_q),
+      .sample(sample), .run(run), .strobe(strobe),
+      .debug() );
+   
+endmodule // new_tx_tb
diff --git a/fpga/usrp3/lib/vita_200/trigger_context_pkt.v b/fpga/usrp3/lib/vita_200/trigger_context_pkt.v
new file mode 100644
index 000000000..6837422e7
--- /dev/null
+++ b/fpga/usrp3/lib/vita_200/trigger_context_pkt.v
@@ -0,0 +1,53 @@
+//
+// Copyright 2011 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+
+
+module trigger_context_pkt
+  #(parameter BASE=0)
+   (input clk, input reset, input clear,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    input packet_consumed, output trigger);
+
+   wire [23:0] cycles;
+   wire [15:0] packets;
+   wire [6:0]  dummy1;
+   wire [14:0] dummy2;
+   wire        enable_cycle, enable_consumed;
+   reg [30:0]  cycle_count, packet_count;
+
+   
+   setting_reg #(.my_addr(BASE), .at_reset(0)) sr_cycles
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({enable_cycle,dummy1,cycles}),.changed());
+
+   setting_reg #(.my_addr(BASE+1), .at_reset(0)) sr_packets
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({enable_consumed,dummy2,packets}),.changed());
+
+   always @(posedge clk)
+     if(reset | clear)
+       cycle_count <= 0;
+     else
+       if(trigger)
+	 cycle_count <= 0;
+       else if((enable_cycle & packet_consumed) | (cycle_count != 0))
+	 cycle_count <= cycle_count + 1;
+
+   always @(posedge clk)
+     if(reset | clear)
+       packet_count <= 0;
+     else
+       if(trigger)
+	 packet_count <= 0;
+       else if(packet_consumed & enable_consumed)
+	 packet_count <= packet_count + 1;
+
+   assign trigger = (enable_cycle & (cycle_count >= cycles)) | (enable_consumed & (packet_count >= packets));
+   
+endmodule // trigger_context_pkt
diff --git a/fpga/usrp3/lib/vita_200/tx_responder.v b/fpga/usrp3/lib/vita_200/tx_responder.v
new file mode 100644
index 000000000..dd2090b77
--- /dev/null
+++ b/fpga/usrp3/lib/vita_200/tx_responder.v
@@ -0,0 +1,57 @@
+//
+// Copyright 2016 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module tx_responder
+  #(parameter BASE = 0)
+   (input clk, input reset, input clear,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    
+    input ack_or_error, input packet_consumed,
+    input [11:0] seqnum,
+    input [63:0] error_code,
+    input [31:0] sid,
+    
+    input [63:0] vita_time,
+    output [63:0] o_tdata, output o_tlast, output o_tvalid, input o_tready);
+
+   reg [11:0] 	  seqnum_int;
+
+   always @(posedge clk)
+     if(packet_consumed)
+       seqnum_int <= seqnum;
+   
+   wire 	  trigger_fc, trigger_ctxt;
+   wire [95:0] 	  msg_data = { sid[15:0], sid[31:16], (ack_or_error ? error_code : {32'h0,20'h0,seqnum_int}) };
+   wire [95:0] 	  ctxt_data;
+
+   reg [11:0] 	  reply_seqnum;
+   wire 	  done;
+   
+   always @(posedge clk)
+     if(reset | clear)
+       reply_seqnum <= 12'd0;
+     else if(done)
+       reply_seqnum <= reply_seqnum + 12'd1;
+   
+   trigger_context_pkt #(.BASE(BASE)) trig
+     (.clk(clk), .reset(reset), .clear(clear),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .packet_consumed(packet_consumed), .trigger(trigger_fc));
+
+   axi_fifo_short #(.WIDTH(64+32)) ack_queue
+     (.clk(clk), .reset(reset), .clear(clear),
+      .i_tdata(msg_data), .i_tvalid(ack_or_error | trigger_fc), .i_tready(),
+      .o_tdata(ctxt_data), .o_tvalid(trigger_ctxt), .o_tready(done),
+      .space(), .occupied());
+   
+   context_packet_gen ack_err_gen
+     (.clk(clk), .reset(reset), .clear(clear),
+      .trigger(trigger_ctxt), .seqnum(reply_seqnum), .sid(ctxt_data[95:64]),
+      .body(ctxt_data[63:0]), .vita_time(vita_time),
+      .done(done),
+      .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready));
+      
+endmodule // tx_responder
diff --git a/fpga/usrp3/lib/vita_200/xxf_to_xxs.v b/fpga/usrp3/lib/vita_200/xxf_to_xxs.v
new file mode 100644
index 000000000..a64b612c9
--- /dev/null
+++ b/fpga/usrp3/lib/vita_200/xxf_to_xxs.v
@@ -0,0 +1,77 @@
+//
+// Copyright 2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module xxf_to_xxs
+#(
+  parameter FBITS = 32,               // # of bits for the float
+  parameter integer QWIDTH = 16       // # of bits in total, e.g. 16 for a Q15
+)
+(
+  input      [FBITS-1:0]   i_float,
+  output reg [QWIDTH-1:0]  o_fixed
+);
+
+  // # of bits for the mantissa
+  parameter MBITS = 23;
+
+  // # of bits for the exponent
+  parameter integer EBITS = 8;
+
+  // # of fractional bits, e.g. 15 for Q15
+  parameter integer RADIX = 15;
+
+  // the bias for the exponent
+  parameter integer BIAS = (1 << EBITS -1) - 1;
+
+  // the min/max values displayable in Qx.x format
+  parameter integer MIN = 1 << RADIX;
+  parameter integer MAX = (1 << RADIX) - 1;
+
+  parameter integer SDIFF = RADIX - MBITS - BIAS;
+
+  // Dissect the IEEE 754 float
+  wire             is_neg   = i_float[FBITS-1];
+  wire [EBITS-1:0] exponent = i_float[MBITS+EBITS-1:MBITS];
+  wire [MBITS-1:0] mantissa = i_float[MBITS-1:0];
+
+  // check for +/- zero
+  wire is_zero    = (exponent == 'h0) && (mantissa == 'h0);
+
+  // check for normal / denormalized
+  wire is_denorm  = (exponent == 'h0) && (mantissa != 'h0);
+  wire is_norm    = !is_denorm;
+
+  // check for infty TODO: parametrize!
+  wire is_inf     = (exponent == 'hff) && (mantissa == 'h0);
+
+  // check for NaN TODO: parametrize!
+  wire is_nan     = (exponent == 'hff) && (mantissa != 'h0);
+
+  // calculate shift
+  wire signed [EBITS-1:0] shift = $signed(SDIFF[EBITS-1:0])
+                                + $signed(exponent);
+
+  wire [FBITS-1:0] shifted_mant = (shift < 0) ?
+                                  {1'b1, mantissa} >> -shift
+                                : {1'b1, mantissa} >> -shift;
+
+  // if shifted value cannot be displayed by Q15 numbers, truncate to MAX/MIN
+  wire [QWIDTH-1:0] sat_mant    = (shifted_mant > 16'h8000 && is_neg) ?
+                                  MIN
+                                : (shifted_mant > 16'h7fff && !is_neg) ?
+                                  MAX : shifted_mant;
+
+  always @(*) begin
+    if (is_inf)
+      o_fixed = (is_neg) ? MIN : MAX;
+    else if (is_denorm || is_zero)
+      o_fixed = 16'h0;
+    else begin
+      o_fixed = (is_neg) ? ~sat_mant + 1 : sat_mant;
+    end
+  end
+endmodule
diff --git a/fpga/usrp3/lib/vita_200/xxs_to_xxf.v b/fpga/usrp3/lib/vita_200/xxs_to_xxf.v
new file mode 100644
index 000000000..7b12a0e64
--- /dev/null
+++ b/fpga/usrp3/lib/vita_200/xxs_to_xxf.v
@@ -0,0 +1,88 @@
+//
+// Copyright 2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+//
+
+`define log2(N) ( N < 2    ? 0 : \
+                  N < 4    ? 1 : \
+                  N < 8    ? 2 : \
+                  N < 16   ? 3 : \
+                  N < 32   ? 4 : \
+                  N < 64   ? 5 : \
+                  N < 128  ? 6 : \
+                  N < 256  ? 7 : \
+                  N < 512  ? 8 : \
+                  N < 1024 ? 9 : \
+                             10 \
+                )
+
+module xxs_to_xxf
+#(
+  parameter FBITS = 32,               // # of bits for the float
+  parameter integer QWIDTH = 16       // # of bits in total, e.g. 16 for a Q15
+)
+(
+  input  [QWIDTH-1:0] i_fixed,
+  output [FBITS-1:0]  o_float
+);
+
+  // # of bits for the mantissa
+  parameter MBITS = 23;
+
+  // # of bits for the exponent
+  parameter integer EBITS = 8;
+
+  // # of fractional bits, e.g. 15 for Q15
+  parameter integer RADIX = 15;
+
+  // the bias for the exponent
+  parameter integer BIAS = (1 << EBITS -1) - 1;
+
+  // the padding for the mantissa
+  parameter         PADDING = {(MBITS-QWIDTH){1'b0}};
+
+  // Check for sign
+  wire              is_neg   = i_fixed[QWIDTH-1];
+  // Check for zero
+  wire              is_zero  = i_fixed == 'h0;
+  // Get absolute value
+  wire [QWIDTH-1:0] abs      = is_neg ? ~i_fixed + 1 : i_fixed;
+
+  wire [`log2(QWIDTH)-1:0] leading_zero;
+
+  wire [QWIDTH-1:0] shift = QWIDTH-leading_zero;
+
+  wire [QWIDTH-1:0] abs_shifted = abs << shift;
+
+  wire [MBITS-1:0]  mantissa;
+  wire [EBITS-1:0]  exponent;
+
+  // Determine the position of the leading zero
+  // using priority encoding.
+  priority_encoder #
+  (
+    .WIDTH(QWIDTH)
+  )
+  pe0
+  (
+    .in(abs),
+    .out(leading_zero)
+  );
+
+  // This was only tested for the case MBITS > QWIDTH
+  generate
+  if (MBITS > QWIDTH) begin
+    assign mantissa = is_zero ? 23'h0 : {abs_shifted, PADDING};
+  end
+  else begin
+    assign mantissa = abs_shifted[QWIDTH-1:QWIDTH-MBITS];
+  end
+  endgenerate
+
+  assign exponent = is_zero ? 8'h0 : BIAS + QWIDTH - RADIX - shift;
+
+  assign o_float = {is_neg, exponent, mantissa};
+endmodule
diff --git a/fpga/usrp3/lib/vivado_ipi/axi_bitq/axi_bitq.vhd b/fpga/usrp3/lib/vivado_ipi/axi_bitq/axi_bitq.vhd
new file mode 100644
index 000000000..322f706a4
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/axi_bitq/axi_bitq.vhd
@@ -0,0 +1,223 @@
+--
+-- Copyright 2018 Ettus Research, A National Instruments Company
+--
+-- SPDX-License-Identifier: LGPL-3.0
+--
+-- Module: axi_bitq
+-- Description: Simple IP to shift bits in/out (primarily for JTAG)
+-- axi_bitq is the processor interface to the bitq_fsm module
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.bitq_fsm;
+
+entity axi_bitq is
+port (
+  bit_clk  : inout std_logic;
+  bit_in   : in    std_logic;
+  bit_out  : inout std_logic;
+  bit_stb  : inout std_logic;
+
+  S_AXI_ACLK     : in  std_logic;
+  S_AXI_ARESETN  : in  std_logic;
+  S_AXI_AWADDR   : in  std_logic_vector(3 downto 0);
+  S_AXI_AWVALID  : in  std_logic;
+  S_AXI_AWREADY  : out std_logic;
+  S_AXI_WDATA    : in  std_logic_vector(31 downto 0);
+  S_AXI_WSTRB    : in  std_logic_vector(3 downto 0);
+  S_AXI_WVALID   : in  std_logic;
+  S_AXI_WREADY   : out std_logic;
+  S_AXI_BRESP    : out std_logic_vector(1 downto 0);
+  S_AXI_BVALID   : out std_logic;
+  S_AXI_BREADY   : in  std_logic;
+  S_AXI_ARADDR   : in  std_logic_vector(3 downto 0);
+  S_AXI_ARVALID  : in  std_logic;
+  S_AXI_ARREADY  : out std_logic;
+  S_AXI_RDATA    : out std_logic_vector(31 downto 0);
+  S_AXI_RRESP    : out std_logic_vector(1 downto 0);
+  S_AXI_RVALID   : out std_logic;
+  S_AXI_RREADY   : in  std_logic
+);
+end axi_bitq;
+
+architecture arch of axi_bitq is
+  signal read_token       : std_logic;
+  signal write_addr       : std_logic_vector(3 downto 0);
+  signal write_strb       : std_logic_vector(3 downto 0);
+  signal write_addr_token : std_logic;
+  signal write_data       : std_logic_vector(31 downto 0);
+  signal write_data_token : std_logic;
+
+  signal wr_data          : std_logic_vector(31 downto 0);
+  signal stb_data         : std_logic_vector(31 downto 0);
+  signal rd_data          : std_logic_vector(31 downto 0);
+  signal prescalar        : std_logic_vector(7 downto 0);
+  signal len              : std_logic_vector(4 downto 0);
+  signal ready            : std_logic;
+  signal start            : std_logic;
+  signal bitq_rstn        : std_logic;
+  signal bitq_soft_rst    : std_logic;
+
+begin
+
+  S_AXI_ARREADY <= not read_token;
+  S_AXI_RVALID <= read_token;
+  S_AXI_RRESP <= "00";
+
+  S_AXI_AWREADY <= not write_addr_token;
+  S_AXI_WREADY <= not write_data_token;
+  S_AXI_BVALID <= write_addr_token and write_data_token;
+  S_AXI_BRESP <= "00";
+
+  --Register reads
+  read_proc : process (S_AXI_ACLK)
+    variable read_addr : std_logic_vector(S_AXI_ARADDR'left downto S_AXI_ARADDR'right+2);
+  begin
+  if rising_edge(S_AXI_ACLK) then
+    read_addr := S_AXI_ARADDR(S_AXI_ARADDR'left downto S_AXI_ARADDR'right+2);
+
+    if (S_AXI_ARESETN = '0') then
+      read_token <= '0';
+    elsif (S_AXI_ARVALID = '1') and (read_token = '0') then
+      read_token <= '1';
+    elsif (S_AXI_RREADY = '1') and (read_token = '1') then
+      read_token <= '0';
+    end if;
+
+    if (S_AXI_ARVALID = '1') and (read_token = '0') then
+      S_AXI_RDATA <= (others => '0');
+
+      case read_addr is
+      when "00" => 
+        S_AXI_RDATA(31 downto 0) <= wr_data;
+      when "01" =>
+        S_AXI_RDATA(31 downto 0) <= stb_data;
+      when "10" =>
+        S_AXI_RDATA(7 downto 0) <= prescalar;
+        S_AXI_RDATA(12 downto 8) <= len;
+        S_AXI_RDATA(31) <= ready;
+      when "11" =>
+        S_AXI_RDATA(31 downto 0) <= rd_data;
+      when others =>
+        null;
+      end case;
+
+    end if;
+  end if;
+  end process read_proc;
+
+  write_proc : process (S_AXI_ACLK)
+  begin
+  if rising_edge(S_AXI_ACLK) then
+    if (S_AXI_ARESETN = '0') then
+      write_addr_token <= '0';
+      write_data_token <= '0';
+      write_strb <= (others => '0');
+    else
+      if (S_AXI_AWVALID = '1') and (write_addr_token = '0') then
+        write_addr_token <= '1';
+      elsif (S_AXI_BREADY = '1') and (write_addr_token = '1') and (write_data_token = '1') then
+        write_addr_token <= '0';
+      end if;
+
+      if (S_AXI_WVALID = '1') and (write_data_token = '0') then
+        write_data_token <= '1';
+      elsif (S_AXI_BREADY = '1') and (write_addr_token = '1') and (write_data_token = '1') then
+        write_data_token <= '0';
+      end if;
+    end if;
+
+    if (S_AXI_AWVALID = '1') and (write_addr_token = '0') then
+      write_addr <= S_AXI_AWADDR;
+    end if;
+
+    if (S_AXI_WVALID = '1') and (write_data_token = '0') then
+      write_data <= S_AXI_WDATA;
+      write_strb <= S_AXI_WSTRB;
+    end if;
+  end if;
+  end process write_proc;
+
+  write_reg : process (S_AXI_ACLK)
+  begin
+  if rising_edge(S_AXI_ACLK) then
+    bitq_soft_rst <= '0';
+    start <= '0';
+
+    if (S_AXI_ARESETN = '0') or (bitq_soft_rst = '1') then
+      bitq_soft_rst <= '0';
+      start <= '0';
+    elsif (write_addr_token = '1') and (write_data_token = '1') then
+      case write_addr(write_addr'left downto 2) is
+      when "00" => 
+        if (write_strb(0) = '1') and (ready = '1') then
+          wr_data(7 downto 0) <= write_data(7 downto 0);
+        end if;
+        if (write_strb(1) = '1') and (ready = '1') then
+          wr_data(15 downto 8) <= write_data(15 downto 8);
+        end if;
+        if (write_strb(2) = '1') and (ready = '1') then
+          wr_data(23 downto 16) <= write_data(23 downto 16);
+        end if;
+        if (write_strb(3) = '1') and (ready = '1') then
+          wr_data(31 downto 24) <= write_data(31 downto 24);
+        end if;
+      when "01" => 
+        if (write_strb(0) = '1') and (ready = '1') then
+          stb_data(7 downto 0) <= write_data(7 downto 0);
+        end if;
+        if (write_strb(1) = '1') and (ready = '1') then
+          stb_data(15 downto 8) <= write_data(15 downto 8);
+        end if;
+        if (write_strb(2) = '1') and (ready = '1') then
+          stb_data(23 downto 16) <= write_data(23 downto 16);
+        end if;
+        if (write_strb(3) = '1') and (ready = '1') then
+          stb_data(31 downto 24) <= write_data(31 downto 24);
+        end if;
+      when "10" =>
+        if (write_strb(0) = '1') and (ready = '1') then
+          prescalar <= write_data(7 downto 0);
+        end if;
+        if (write_strb(1) = '1') and (ready = '1') then
+          len <= write_data(12 downto 8);
+          if (write_strb(3) = '0') or (write_data(31) = '0') then
+            start <= '1';
+          end if;
+        end if;
+        if (write_strb(3) = '1') then
+          bitq_soft_rst <= write_data(31);
+        end if;
+      when "11" => --Read only register
+        null;
+      when others =>
+        null;
+      end case;
+    end if;
+  end if;
+  end process write_reg;
+
+  bitq_rstn <= '0' when (S_AXI_ARESETN = '0') or (bitq_soft_rst = '1') else '1';
+
+  bitq_ctrl : entity bitq_fsm
+  port map (
+    clk  => S_AXI_ACLK,
+    rstn => S_AXI_ARESETN,
+    prescalar => prescalar,
+  
+    bit_clk  => bit_clk,
+    bit_in   => bit_in,
+    bit_out  => bit_out,
+    bit_stb  => bit_stb,
+    start    => start,
+    len      => len,
+    ready    => ready,
+    wr_data  => wr_data,
+    stb_data => stb_data,
+    rd_data  => rd_data
+  );
+
+end arch;
+
diff --git a/fpga/usrp3/lib/vivado_ipi/axi_bitq/bitq_fsm.vhd b/fpga/usrp3/lib/vivado_ipi/axi_bitq/bitq_fsm.vhd
new file mode 100644
index 000000000..ed7ab4a50
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/axi_bitq/bitq_fsm.vhd
@@ -0,0 +1,128 @@
+--
+-- Copyright 2018 Ettus Research, A National Instruments Company
+--
+-- SPDX-License-Identifier: LGPL-3.0
+--
+-- Module: bitq_fsm
+-- Description: Simple IP to shift bits in/out (primarily for JTAG)
+-- bitq_fsm implements the state machine underlying the IP
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity bitq_fsm is
+port (
+  clk  : in std_logic;
+  rstn : in std_logic;
+  prescalar : in std_logic_vector(7 downto 0);
+
+  bit_clk  : inout std_logic;
+  bit_in   : in    std_logic;
+  bit_out  : inout std_logic;
+  bit_stb  : inout std_logic;
+  start    : in std_logic;
+  ready    : out std_logic;
+  len      : in std_logic_vector(4 downto 0);
+  wr_data  : in std_logic_vector(31 downto 0);
+  stb_data : in std_logic_vector(31 downto 0);
+  rd_data  : out std_logic_vector(31 downto 0)
+
+);
+
+end bitq_fsm;
+
+architecture arch of bitq_fsm is
+  type bitq_state_t is (IDLE, LOW, HIGH);
+  signal bitq_state : bitq_state_t;
+
+  signal bit_clk_count  : unsigned(7 downto 0);
+  signal bit_count  : unsigned(5 downto 0);
+
+  signal bit_out_r  : std_logic;
+  signal bit_stb_r  : std_logic;
+
+  signal rd_data_r  : std_logic_vector(31 downto 0);
+
+begin
+  rd_data <= rd_data_r;
+
+  gen_io : process (bitq_state, bit_count, bit_out_r, bit_stb_r)
+  begin
+    case (bitq_state) is
+    when IDLE =>
+      bit_clk <= 'Z';
+      bit_out <= 'Z';
+      bit_stb <= 'Z';
+      ready   <= '1';
+    when LOW =>
+      bit_clk <= '0';
+      bit_out <= bit_out_r;
+      bit_stb <= bit_stb_r;
+      ready <= '0';
+    when HIGH =>
+      bit_clk <= '1';
+      bit_out <= bit_out_r;
+      bit_stb <= bit_stb_r;
+      ready <= '0';
+    when others =>
+      bit_clk <= 'Z';
+      bit_out <= 'Z';
+      bit_stb <= 'Z';
+      ready   <= '1';
+    end case;
+  end process;
+
+  bit_clk_gen : process (clk)
+  begin
+  if rising_edge(clk) then
+    if (rstn = '0') or (bitq_state = IDLE) or
+       (bit_clk_count = 0) then
+      bit_clk_count <= unsigned(prescalar);
+    elsif (bit_clk_count /= 0) then
+      bit_clk_count <= bit_clk_count - 1;
+    end if;
+  end if;
+  end process bit_clk_gen;
+
+  fsm : process (clk)
+  begin
+  if rising_edge(clk) then
+    if (rstn = '0') then
+      bitq_state <= IDLE;
+      bit_count <= to_unsigned(0, bit_count'length);
+      rd_data_r <= (others => '0');
+    else
+      case bitq_state is
+      when IDLE =>
+        bit_count <= to_unsigned(0, bit_count'length);
+
+        if (start = '1') then
+          bitq_state <= LOW;
+          rd_data_r <= (others => '0');
+          bit_out_r <= wr_data(0);
+          bit_stb_r <= stb_data(0);
+        end if;
+      when LOW =>
+        if (bit_clk_count = 0) then
+          rd_data_r(to_integer(bit_count)) <= bit_in;
+          bit_count <= bit_count + 1;
+          bitq_state <= HIGH; --Rising edge
+        end if;
+      when HIGH =>
+        if (bit_clk_count = 0) then
+          if (bit_count > unsigned('0' & len)) then
+            bitq_state <= IDLE;
+          else
+            bit_out_r <= wr_data(to_integer(bit_count));
+            bit_stb_r <= stb_data(to_integer(bit_count));
+            bitq_state <= LOW; --Falling edge
+          end if;
+        end if;
+      end case;
+    end if;
+  end if;
+  end process fsm;
+
+end arch;
+
diff --git a/fpga/usrp3/lib/vivado_ipi/axi_bitq/component.xml b/fpga/usrp3/lib/vivado_ipi/axi_bitq/component.xml
new file mode 100644
index 000000000..2f22a5911
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/axi_bitq/component.xml
@@ -0,0 +1,719 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>ettus.com</spirit:vendor>
+  <spirit:library>ip</spirit:library>
+  <spirit:name>axi_bitq</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>S_AXI</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="S_AXI"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S_AXI_ARESETN</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_ARESETN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_ARESETN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S_AXI_ACLK</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_ACLK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.ASSOCIATED_BUSIF">S_AXI</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.ASSOCIATED_RESET">S_AXI_ARESETN</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:memoryMaps>
+    <spirit:memoryMap>
+      <spirit:name>S_AXI</spirit:name>
+      <spirit:addressBlock>
+        <spirit:name>reg0</spirit:name>
+        <spirit:baseAddress spirit:format="bitString" spirit:resolve="user" spirit:bitStringLength="32">0</spirit:baseAddress>
+        <spirit:range spirit:format="long" spirit:resolve="user" spirit:minimum="4096" spirit:rangeType="long">16</spirit:range>
+        <spirit:width spirit:format="long" spirit:resolve="user">32</spirit:width>
+        <spirit:usage>register</spirit:usage>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+  </spirit:memoryMaps>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+        <spirit:displayName>Synthesis</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+        <spirit:language>VHDL</spirit:language>
+        <spirit:modelName>axi_bitq</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>7ba7202f</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+        <spirit:displayName>Simulation</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:language>VHDL</spirit:language>
+        <spirit:modelName>axi_bitq</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>7ba7202f</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_xpgui</spirit:name>
+        <spirit:displayName>UI Layout</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>f92e9879</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_testbench</spirit:name>
+        <spirit:displayName>Test Bench</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:simulation.testbench</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_testbench_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>657bd79f</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+    </spirit:views>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>bit_clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>inout</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>bit_in</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>bit_out</spirit:name>
+        <spirit:wire>
+          <spirit:direction>inout</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>bit_stb</spirit:name>
+        <spirit:wire>
+          <spirit:direction>inout</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_ACLK</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_ARESETN</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_AWADDR</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">3</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_AWVALID</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_AWREADY</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_WDATA</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_WSTRB</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">3</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_WVALID</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_WREADY</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_BRESP</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_BVALID</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_BREADY</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_ARADDR</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">3</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_ARVALID</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_ARREADY</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_RDATA</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_RRESP</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_RVALID</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_RREADY</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+  </spirit:model>
+  <spirit:choices>
+    <spirit:choice>
+      <spirit:name>choice_list_9d8b0d81</spirit:name>
+      <spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
+      <spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
+    </spirit:choice>
+  </spirit:choices>
+  <spirit:fileSets>
+    <spirit:fileSet>
+      <spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>bitq_fsm.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>axi_bitq.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>CHECKSUM_7f11f7eb</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>bitq_fsm.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>axi_bitq.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_xpgui_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>xgui/axi_bitq_v1_0.tcl</spirit:name>
+        <spirit:fileType>tclSource</spirit:fileType>
+        <spirit:userFileType>CHECKSUM_f92e9879</spirit:userFileType>
+        <spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_testbench_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>test/bitq_fsm_test.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>axi_bitq_v1_0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">axi_bitq_v1_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:supportedFamilies>
+        <xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
+      </xilinx:supportedFamilies>
+      <xilinx:taxonomies>
+        <xilinx:taxonomy>/EttusResearch</xilinx:taxonomy>
+      </xilinx:taxonomies>
+      <xilinx:displayName>axi_bitq_v1_0</xilinx:displayName>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+      <xilinx:upgrades>
+        <xilinx:canUpgradeFrom>user.org:user:axi_bitq:1.0</xilinx:canUpgradeFrom>
+      </xilinx:upgrades>
+      <xilinx:coreCreationDateTime>2018-01-17T16:36:23Z</xilinx:coreCreationDateTime>
+      <xilinx:tags>
+        <xilinx:tag xilinx:name="nopcore"/>
+        <xilinx:tag xilinx:name="user.org:user:axi_bitq:1.0_ARCHIVE_LOCATION">usrp3/lib/vivado_ipi/axi_bitq</xilinx:tag>
+        <xilinx:tag xilinx:name="ettus.com:user:axi_bitq:1.0_ARCHIVE_LOCATION">usrp3/lib/vivado_ipi/axi_bitq</xilinx:tag>
+        <xilinx:tag xilinx:name="ettus.com:ip:axi_bitq:1.0_ARCHIVE_LOCATION">usrp3/lib/vivado_ipi/axi_bitq</xilinx:tag>
+      </xilinx:tags>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2015.4</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="2663de75"/>
+      <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="da330753"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="3da6ad7f"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="15d3ec9b"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="0252408f"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/fpga/usrp3/lib/vivado_ipi/axi_bitq/test/bitq_fsm_test.vhd b/fpga/usrp3/lib/vivado_ipi/axi_bitq/test/bitq_fsm_test.vhd
new file mode 100644
index 000000000..a7bc95fe6
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/axi_bitq/test/bitq_fsm_test.vhd
@@ -0,0 +1,95 @@
+--
+-- Copyright 2018 Ettus Research, A National Instruments Company
+--
+-- SPDX-License-Identifier: LGPL-3.0
+--
+-- Module: bitq_fsm_test
+-- Description: Manually-checked tester for bitq_fsm
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.bitq_fsm;
+
+entity bitq_fsm_test is
+end bitq_fsm_test;
+
+architecture sim of bitq_fsm_test is
+  signal clk  : std_logic := '0';
+  signal rstn : std_logic;
+
+  signal wr_data   : std_logic_vector(31 downto 0);
+  signal stb_data  : std_logic_vector(31 downto 0);
+  signal rd_data   : std_logic_vector(31 downto 0);
+  signal prescalar : std_logic_vector(7 downto 0);
+  signal len       : std_logic_vector(4 downto 0);
+  signal ready     : std_logic;
+  signal start     : std_logic;
+
+  signal bit_clk : std_logic;
+  signal bit_in : std_logic;
+  signal bit_out : std_logic;
+  signal bit_stb : std_logic;
+
+  constant HALFCYCLE : time := 5 ns;
+  constant CYCLE : time := 2*HALFCYCLE;
+
+begin
+
+  process
+  begin
+    wait for HALFCYCLE;
+    clk <= not clk;
+  end process;
+
+  process
+  begin
+    rstn <= '0';
+    start <= '0';
+    len <= "11111";
+    bit_in <= '0';
+    prescalar <= X"02";
+    wait for CYCLE;
+    rstn <= '1';
+    wait for CYCLE;
+    wr_data <= X"ABCDEF01";
+    stb_data <= X"FF7F7700";
+    wait for CYCLE;
+    start <= '1';
+    wait for CYCLE;
+    start <= '0';
+    wait until ready = '1';
+    wait for CYCLE;
+    start <= '1';
+    wait for CYCLE;
+    start <= '0';
+    bit_in <= '1';
+    wait until ready = '1';
+    wait for CYCLE;
+    bit_in <= '0';
+    wait for CYCLE;
+    report "End of Test";
+  end process;
+
+  dut : entity work.bitq_fsm
+  port map (
+    clk  => clk,
+    rstn => rstn,
+    prescalar => prescalar,
+  
+    bit_clk  => bit_clk,
+    bit_in   => bit_in,
+    bit_out  => bit_out,
+    bit_stb  => bit_stb,
+    start    => start,
+    len      => len,
+    ready    => ready,
+    wr_data  => wr_data,
+    stb_data => stb_data,
+    rd_data  => rd_data
+  );
+
+end sim;
+
diff --git a/fpga/usrp3/lib/vivado_ipi/axi_bitq/xgui/axi_bitq_v1_0.tcl b/fpga/usrp3/lib/vivado_ipi/axi_bitq/xgui/axi_bitq_v1_0.tcl
new file mode 100644
index 000000000..0db18e9a9
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/axi_bitq/xgui/axi_bitq_v1_0.tcl
@@ -0,0 +1,10 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  ipgui::add_page $IPINST -name "Page 0"
+
+
+}
+
+
diff --git a/fpga/usrp3/lib/vivado_ipi/axi_dmac/2d_transfer.v b/fpga/usrp3/lib/vivado_ipi/axi_dmac/2d_transfer.v
new file mode 100644
index 000000000..13f4e2dff
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/axi_dmac/2d_transfer.v
@@ -0,0 +1,142 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2013(c) Analog Devices, Inc.
+//  Author: Lars-Peter Clausen <lars@metafoo.de>
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+module dmac_2d_transfer (
+  input req_aclk,
+  input req_aresetn,
+
+  input req_valid,
+  output reg req_ready,
+
+  input [31:BYTES_PER_BEAT_WIDTH_DEST] req_dest_address,
+  input [31:BYTES_PER_BEAT_WIDTH_SRC] req_src_address,
+  input [DMA_LENGTH_WIDTH-1:0] req_x_length,
+  input [DMA_LENGTH_WIDTH-1:0] req_y_length,
+  input [DMA_LENGTH_WIDTH-1:0] req_dest_stride,
+  input [DMA_LENGTH_WIDTH-1:0] req_src_stride,
+  input req_sync_transfer_start,
+  output reg req_eot,
+  
+  output reg out_req_valid,
+  input out_req_ready,
+  output [31:BYTES_PER_BEAT_WIDTH_DEST] out_req_dest_address,
+  output [31:BYTES_PER_BEAT_WIDTH_SRC] out_req_src_address,
+  output [DMA_LENGTH_WIDTH-1:0] out_req_length,
+  output reg out_req_sync_transfer_start,
+  input out_eot
+);
+
+parameter DMA_LENGTH_WIDTH = 24;
+parameter BYTES_PER_BEAT_WIDTH_SRC = 3;
+parameter BYTES_PER_BEAT_WIDTH_DEST = 3;
+
+reg [31:BYTES_PER_BEAT_WIDTH_DEST] dest_address;
+reg [31:BYTES_PER_BEAT_WIDTH_SRC] src_address;
+reg [DMA_LENGTH_WIDTH-1:0] x_length;
+reg [DMA_LENGTH_WIDTH-1:0] y_length;
+reg [DMA_LENGTH_WIDTH-1:0] dest_stride;
+reg [DMA_LENGTH_WIDTH-1:0] src_stride;
+
+reg [1:0] req_id;
+reg [1:0] eot_id;
+reg [3:0] last_req;
+
+assign out_req_dest_address = dest_address;
+assign out_req_src_address = src_address;
+assign out_req_length = x_length;
+
+always @(posedge req_aclk)
+begin
+  if (req_aresetn == 1'b0) begin
+    req_id <= 2'b0;
+    eot_id <= 2'b0;
+    req_eot <= 1'b0;
+  end else begin
+    if (out_req_valid && out_req_ready) begin
+      req_id <= req_id + 1'b1;
+      last_req[req_id] <= y_length == 0;
+    end
+    req_eot <= 1'b0;
+    if (out_eot) begin
+      eot_id <= eot_id + 1'b1;
+      req_eot <= last_req[eot_id];
+    end
+  end
+end
+
+always @(posedge req_aclk)
+begin
+  if (req_aresetn == 1'b0) begin
+    dest_address <= 'h00;
+    src_address <= 'h00;
+    x_length <= 'h00;
+    y_length <= 'h00;
+    dest_stride <= 'h00;
+    src_stride <= 'h00;
+    req_ready <= 1'b1;
+    out_req_valid <= 1'b0;
+    out_req_sync_transfer_start <= 1'b0;
+  end else begin
+    if (req_ready) begin
+      if (req_valid) begin
+        dest_address <= req_dest_address;
+        src_address <= req_src_address;
+        x_length <= req_x_length;
+        y_length <= req_y_length;
+        dest_stride <= req_dest_stride;
+        src_stride <= req_src_stride;
+        out_req_sync_transfer_start <= req_sync_transfer_start;
+        req_ready <= 1'b0;
+        out_req_valid <= 1'b1;
+      end
+    end else begin
+      if (out_req_valid && out_req_ready) begin
+        dest_address <= dest_address + dest_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST];
+        src_address <= src_address + src_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC];
+        y_length <= y_length - 1'b1;
+        out_req_sync_transfer_start <= 1'b0;
+        if (y_length == 0) begin
+          out_req_valid <= 1'b0;
+          req_ready <= 1'b1;
+        end
+      end
+    end
+  end
+end
+
+endmodule
diff --git a/fpga/usrp3/lib/vivado_ipi/axi_dmac/address_generator.v b/fpga/usrp3/lib/vivado_ipi/axi_dmac/address_generator.v
new file mode 100644
index 000000000..8e38486d5
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/axi_dmac/address_generator.v
@@ -0,0 +1,161 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2013(c) Analog Devices, Inc.
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+module dmac_address_generator (
+  input                        clk,
+  input                        resetn,
+
+  input                        req_valid,
+  output reg                   req_ready,
+  input [31:BYTES_PER_BEAT_WIDTH] req_address,
+  input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
+
+  output reg [ID_WIDTH-1:0]  id,
+  input [ID_WIDTH-1:0]       request_id,
+  input                        sync_id,
+
+  input                        eot,
+
+  input                        enable,
+  input                        pause,
+  output reg                   enabled,
+
+  input                        addr_ready,
+  output reg                   addr_valid,
+  output     [31:0]            addr,
+  output     [ 7:0]            len,
+  output     [ 2:0]            size,
+  output     [ 1:0]            burst,
+  output     [ 2:0]            prot,
+  output     [ 3:0]            cache
+);
+
+
+parameter ID_WIDTH = 3;
+parameter DMA_DATA_WIDTH = 64;
+parameter BEATS_PER_BURST_WIDTH = 4;
+parameter BYTES_PER_BEAT_WIDTH = $clog2(DMA_DATA_WIDTH/8);
+localparam MAX_BEATS_PER_BURST = 2**(BEATS_PER_BURST_WIDTH);
+
+`include "inc_id.h"
+
+assign burst = 2'b01;
+assign prot = 3'b000;
+assign cache = 4'b0011;
+assign len = length;
+assign size = $clog2(DMA_DATA_WIDTH/8);
+
+reg [7:0] length = 'h0;
+reg [31-BYTES_PER_BEAT_WIDTH:0] address = 'h00;
+reg [BEATS_PER_BURST_WIDTH-1:0] last_burst_len = 'h00;
+assign addr = {address, {BYTES_PER_BEAT_WIDTH{1'b0}}};
+
+reg addr_valid_d1;
+reg last = 1'b0;
+
+// If we already asserted addr_valid we have to wait until it is accepted before
+// we can disable the address generator.
+always @(posedge clk) begin
+  if (resetn == 1'b0) begin
+    enabled <= 1'b0;
+  end else begin
+    if (enable)
+      enabled <= 1'b1;
+    else if (~addr_valid)
+      enabled <= 1'b0;
+  end
+end
+
+always @(posedge clk) begin
+  if (addr_valid == 1'b0) begin
+    if (eot == 1'b1)
+      length <= last_burst_len;
+    else
+      length <= MAX_BEATS_PER_BURST - 1;
+  end
+end
+
+always @(posedge clk) begin
+  if (resetn == 1'b0) begin
+    last <= 1'b0;
+  end else if (addr_valid == 1'b0) begin
+    last <= eot;
+  end
+end
+
+always @(posedge clk) begin
+  if (resetn == 1'b0) begin
+    address <= 'h00;
+    last_burst_len <= 'h00;
+    req_ready <= 1'b1;
+    addr_valid <= 1'b0;
+  end else begin
+    if (~enabled) begin
+      req_ready <= 1'b1;
+    end else if (req_ready) begin
+      if (req_valid && enable) begin
+        address <= req_address;
+        req_ready <= 1'b0;
+        last_burst_len <= req_last_burst_length;
+      end
+    end else begin
+      if (addr_valid && addr_ready) begin
+        address <= address + MAX_BEATS_PER_BURST;
+        addr_valid <= 1'b0;
+        if (last)
+          req_ready <= 1'b1;
+      end else if (id != request_id && enable) begin
+        addr_valid <= 1'b1;
+      end
+    end
+  end
+end
+
+always @(posedge clk) begin
+  if (resetn == 1'b0) begin
+    id <='h0;
+    addr_valid_d1 <= 1'b0;
+  end else begin
+    addr_valid_d1 <= addr_valid;
+    if ((addr_valid && ~addr_valid_d1) ||
+      (sync_id && id != request_id))
+      id <= inc_id(id);
+
+  end
+end
+
+endmodule
diff --git a/fpga/usrp3/lib/vivado_ipi/axi_dmac/axi_dmac.v b/fpga/usrp3/lib/vivado_ipi/axi_dmac/axi_dmac.v
new file mode 100644
index 000000000..ad8019792
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/axi_dmac/axi_dmac.v
@@ -0,0 +1,672 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2013(c) Analog Devices, Inc.
+//  Author: Lars-Peter Clausen <lars@metafoo.de>
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+// Source: git://github.com/analogdevicesinc/hdl.git
+// Commit hash: 04843795d8d6a496c00ee91b437d57924bc1cbf1
+
+module axi_dmac (
+  // Slave AXI interface
+  input s_axi_aclk,
+  input s_axi_aresetn,
+
+  input         s_axi_awvalid,
+  input  [31:0] s_axi_awaddr,
+  output        s_axi_awready,
+  input   [2:0] s_axi_awprot,
+  input         s_axi_wvalid,
+  input  [31:0] s_axi_wdata,
+  input  [ 3:0] s_axi_wstrb,
+  output        s_axi_wready,
+  output        s_axi_bvalid,
+  output [ 1:0] s_axi_bresp,
+  input         s_axi_bready,
+  input         s_axi_arvalid,
+  input  [31:0] s_axi_araddr,
+  output        s_axi_arready,
+  input   [2:0] s_axi_arprot,
+  output        s_axi_rvalid,
+  input         s_axi_rready,
+  output [ 1:0] s_axi_rresp,
+  output [31:0] s_axi_rdata,
+
+  // Interrupt
+  output reg irq,
+
+  // Master AXI interface
+  input                                    m_dest_axi_aclk,
+  input                                    m_dest_axi_aresetn,
+
+  // Write address
+  output [31:0]                            m_dest_axi_awaddr,
+  output [7-(4*DMA_AXI_PROTOCOL_DEST):0] m_dest_axi_awlen,
+  output [ 2:0]                            m_dest_axi_awsize,
+  output [ 1:0]                            m_dest_axi_awburst,
+  output [ 2:0]                            m_dest_axi_awprot,
+  output [ 3:0]                            m_dest_axi_awcache,
+  output                                   m_dest_axi_awvalid,
+  input                                    m_dest_axi_awready,
+
+  // Write data
+  output [DMA_DATA_WIDTH_DEST-1:0]       m_dest_axi_wdata,
+  output [(DMA_DATA_WIDTH_DEST/8)-1:0]   m_dest_axi_wstrb,
+  input                                    m_dest_axi_wready,
+  output                                   m_dest_axi_wvalid,
+  output                                   m_dest_axi_wlast,
+
+  // Write response
+  input                                    m_dest_axi_bvalid,
+  input  [ 1:0]                            m_dest_axi_bresp,
+  output                                   m_dest_axi_bready,
+
+  // Unused read interface
+  output                                   m_dest_axi_arvalid,
+  output [31:0]                            m_dest_axi_araddr,
+  output [7-(4*DMA_AXI_PROTOCOL_DEST):0] m_dest_axi_arlen,
+  output [ 2:0]                            m_dest_axi_arsize,
+  output [ 1:0]                            m_dest_axi_arburst,
+  output [ 3:0]                            m_dest_axi_arcache,
+  output [ 2:0]                            m_dest_axi_arprot,
+  input                                    m_dest_axi_arready,
+  input                                    m_dest_axi_rvalid,
+  input  [ 1:0]                            m_dest_axi_rresp,
+  input  [DMA_DATA_WIDTH_DEST-1:0]       m_dest_axi_rdata,
+  output                                   m_dest_axi_rready,
+
+  // Master AXI interface
+  input                                    m_src_axi_aclk,
+  input                                    m_src_axi_aresetn,
+
+  // Read address
+  input                                    m_src_axi_arready,
+  output                                   m_src_axi_arvalid,
+  output [31:0]                            m_src_axi_araddr,
+  output [7-(4*DMA_AXI_PROTOCOL_SRC):0]  m_src_axi_arlen,
+  output [ 2:0]                            m_src_axi_arsize,
+  output [ 1:0]                            m_src_axi_arburst,
+  output [ 2:0]                            m_src_axi_arprot,
+  output [ 3:0]                            m_src_axi_arcache,
+
+  // Read data and response
+  input  [DMA_DATA_WIDTH_SRC-1:0]        m_src_axi_rdata,
+  output                                   m_src_axi_rready,
+  input                                    m_src_axi_rvalid,
+  input  [ 1:0]                            m_src_axi_rresp,
+
+  // Unused write interface
+  output                                   m_src_axi_awvalid,
+  output [31:0]                            m_src_axi_awaddr,
+  output [7-(4*DMA_AXI_PROTOCOL_SRC):0]  m_src_axi_awlen,
+  output [ 2:0]                            m_src_axi_awsize,
+  output [ 1:0]                            m_src_axi_awburst,
+  output [ 3:0]                            m_src_axi_awcache,
+  output [ 2:0]                            m_src_axi_awprot,
+  input                                    m_src_axi_awready,
+  output                                   m_src_axi_wvalid,
+  output [DMA_DATA_WIDTH_SRC-1:0]        m_src_axi_wdata,
+  output [(DMA_DATA_WIDTH_SRC/8)-1:0]    m_src_axi_wstrb,
+  output                                   m_src_axi_wlast,
+  input                                    m_src_axi_wready,
+  input                                    m_src_axi_bvalid,
+  input  [ 1:0]                            m_src_axi_bresp,
+  output                                   m_src_axi_bready,
+
+  // Slave streaming AXI interface
+  input                                    s_axis_aclk,
+  output                                   s_axis_ready,
+  input                                    s_axis_valid,
+  input  [DMA_DATA_WIDTH_SRC-1:0]        s_axis_data,
+  input  [0:0]                             s_axis_user,
+  output                                   s_axis_xfer_req,
+
+  // Master streaming AXI interface
+  input                                    m_axis_aclk,
+  input                                    m_axis_ready,
+  output                                   m_axis_valid,
+  output [DMA_DATA_WIDTH_DEST-1:0]       m_axis_data,
+        output                                   m_axis_last,
+        output                                   m_axis_xfer_req,
+
+  // Input FIFO interface
+  input                                    fifo_wr_clk,
+  input                                    fifo_wr_en,
+  input  [DMA_DATA_WIDTH_SRC-1:0]        fifo_wr_din,
+  output                                   fifo_wr_overflow,
+  input                                    fifo_wr_sync,
+  output                                   fifo_wr_xfer_req,
+
+  // Input FIFO interface
+  input                                    fifo_rd_clk,
+  input                                    fifo_rd_en,
+  output                                   fifo_rd_valid,
+  output [DMA_DATA_WIDTH_DEST-1:0]       fifo_rd_dout,
+  output                                   fifo_rd_underflow,
+        output                                   fifo_rd_xfer_req
+);
+
+parameter ID = 0;
+
+parameter DMA_DATA_WIDTH_SRC = 64;
+parameter DMA_DATA_WIDTH_DEST = 64;
+parameter DMA_LENGTH_WIDTH = 24;
+parameter DMA_2D_TRANSFER = 1;
+
+parameter ASYNC_CLK_REQ_SRC = 1;
+parameter ASYNC_CLK_SRC_DEST = 1;
+parameter ASYNC_CLK_DEST_REQ = 1;
+
+parameter AXI_SLICE_DEST = 0;
+parameter AXI_SLICE_SRC = 0;
+parameter SYNC_TRANSFER_START = 0;
+parameter CYCLIC = 1;
+
+parameter DMA_AXI_PROTOCOL_DEST = 0;
+parameter DMA_AXI_PROTOCOL_SRC = 0;
+parameter DMA_TYPE_DEST = 0;
+parameter DMA_TYPE_SRC = 2;
+
+parameter MAX_BYTES_PER_BURST = 128;
+parameter FIFO_SIZE = 4; // In bursts
+
+localparam DMA_TYPE_AXI_MM = 0;
+localparam DMA_TYPE_AXI_STREAM = 1;
+localparam DMA_TYPE_FIFO = 2;
+
+localparam PCORE_VERSION = 'h00040062;
+
+localparam HAS_DEST_ADDR = DMA_TYPE_DEST == DMA_TYPE_AXI_MM;
+localparam HAS_SRC_ADDR = DMA_TYPE_SRC == DMA_TYPE_AXI_MM;
+
+// Argh... "[Synth 8-2722] system function call clog2 is not allowed here"
+localparam BYTES_PER_BEAT_WIDTH_DEST = DMA_DATA_WIDTH_DEST > 1024 ? 8 :
+  DMA_DATA_WIDTH_DEST > 512 ? 7 :
+  DMA_DATA_WIDTH_DEST > 256 ? 6 :
+  DMA_DATA_WIDTH_DEST > 128 ? 5 :
+  DMA_DATA_WIDTH_DEST > 64 ? 4 :
+  DMA_DATA_WIDTH_DEST > 32 ? 3 :
+  DMA_DATA_WIDTH_DEST > 16 ? 2 :
+  DMA_DATA_WIDTH_DEST > 8 ? 1 : 0;
+localparam BYTES_PER_BEAT_WIDTH_SRC = DMA_DATA_WIDTH_SRC > 1024 ? 8 :
+  DMA_DATA_WIDTH_SRC > 512 ? 7 :
+  DMA_DATA_WIDTH_SRC > 256 ? 6 :
+  DMA_DATA_WIDTH_SRC > 128 ? 5 :
+  DMA_DATA_WIDTH_SRC > 64 ? 4 :
+  DMA_DATA_WIDTH_SRC > 32 ? 3 :
+  DMA_DATA_WIDTH_SRC > 16 ? 2 :
+  DMA_DATA_WIDTH_SRC > 8 ? 1 : 0;
+localparam ID_WIDTH = (FIFO_SIZE) > 64 ? 8 :
+  (FIFO_SIZE) > 32 ? 7 :
+  (FIFO_SIZE) > 16 ? 6 :
+  (FIFO_SIZE) > 8 ? 5 :
+  (FIFO_SIZE) > 4 ? 4 :
+  (FIFO_SIZE) > 2 ? 3 :
+  (FIFO_SIZE) > 1 ? 2 : 1;
+
+// Register interface signals
+reg  [31:0]  up_rdata = 'd0;
+reg          up_wack = 1'b0;
+reg          up_rack = 1'b0;
+wire         up_wreq;
+wire         up_rreq;
+wire [31:0]  up_wdata;
+wire [11:0]  up_waddr;
+wire [11:0]  up_raddr;
+
+// Scratch register
+reg [31:0] up_scratch = 'h00;
+
+// Control bits
+reg up_enable = 'h00;
+reg up_pause = 'h00;
+
+// Start and end of transfer
+wire up_eot; // Asserted for one cycle when a transfer has been completed
+wire up_sot; // Asserted for one cycle when a transfer has been queued
+
+// Interupt handling
+reg [1:0] up_irq_mask = 'h3;
+reg [1:0] up_irq_source = 'h0;
+wire [1:0] up_irq_pending;
+wire [1:0] up_irq_trigger;
+wire [1:0] up_irq_source_clear;
+
+// DMA transfer signals
+reg  up_dma_req_valid = 1'b0;
+wire up_dma_req_ready;
+
+reg [1:0] up_transfer_id = 2'b0;
+reg [1:0] up_transfer_id_eot = 2'b0;
+reg [3:0] up_transfer_done_bitmap = 4'b0;
+reg       up_axis_xlast = 1'b1;
+
+reg [31:BYTES_PER_BEAT_WIDTH_DEST]   up_dma_dest_address = 'h00;
+reg [31:BYTES_PER_BEAT_WIDTH_SRC]   up_dma_src_address = 'h00;
+reg [DMA_LENGTH_WIDTH-1:0] up_dma_x_length = 'h00;
+reg [DMA_LENGTH_WIDTH-1:0] up_dma_y_length = 'h00;
+reg [DMA_LENGTH_WIDTH-1:0] up_dma_src_stride = 'h00;
+reg [DMA_LENGTH_WIDTH-1:0] up_dma_dest_stride = 'h00;
+reg up_dma_cyclic = CYCLIC;
+wire up_dma_sync_transfer_start = SYNC_TRANSFER_START ? 1'b1 : 1'b0;
+
+// ID signals from the DMAC, just for debugging
+wire [ID_WIDTH-1:0] dest_request_id;
+wire [ID_WIDTH-1:0] dest_data_id;
+wire [ID_WIDTH-1:0] dest_address_id;
+wire [ID_WIDTH-1:0] dest_response_id;
+wire [ID_WIDTH-1:0] src_request_id;
+wire [ID_WIDTH-1:0] src_data_id;
+wire [ID_WIDTH-1:0] src_address_id;
+wire [ID_WIDTH-1:0] src_response_id;
+wire [7:0] dbg_status;
+
+assign m_dest_axi_araddr = 'd0;
+assign m_dest_axi_arlen = 'd0;
+assign m_dest_axi_arsize = 'd0;
+assign m_dest_axi_arburst = 'd0;
+assign m_dest_axi_arcache = 'd0;
+assign m_dest_axi_arprot = 'd0;
+assign m_src_axi_awaddr = 'd0;
+assign m_src_axi_awlen = 'd0;
+assign m_src_axi_awsize = 'd0;
+assign m_src_axi_awburst = 'd0;
+assign m_src_axi_awcache = 'd0;
+assign m_src_axi_awprot = 'd0;
+assign m_src_axi_wdata = 'd0;
+assign m_src_axi_wstrb = 'd0;
+assign m_src_axi_wlast = 'd0;
+
+up_axi #(
+  .ADDRESS_WIDTH (12)
+) i_up_axi (
+  .up_rstn(s_axi_aresetn),
+  .up_clk(s_axi_aclk),
+  .up_axi_awvalid(s_axi_awvalid),
+  .up_axi_awaddr(s_axi_awaddr),
+  .up_axi_awready(s_axi_awready),
+  .up_axi_wvalid(s_axi_wvalid),
+  .up_axi_wdata(s_axi_wdata),
+  .up_axi_wstrb(s_axi_wstrb),
+  .up_axi_wready(s_axi_wready),
+  .up_axi_bvalid(s_axi_bvalid),
+  .up_axi_bresp(s_axi_bresp),
+  .up_axi_bready(s_axi_bready),
+  .up_axi_arvalid(s_axi_arvalid),
+  .up_axi_araddr(s_axi_araddr),
+  .up_axi_arready(s_axi_arready),
+  .up_axi_rvalid(s_axi_rvalid),
+  .up_axi_rresp(s_axi_rresp),
+  .up_axi_rdata(s_axi_rdata),
+  .up_axi_rready(s_axi_rready),
+  .up_wreq(up_wreq),
+  .up_waddr(up_waddr),
+  .up_wdata(up_wdata),
+  .up_wack(up_wack),
+  .up_rreq(up_rreq),
+  .up_raddr(up_raddr),
+  .up_rdata(up_rdata),
+  .up_rack(up_rack)
+);
+
+// IRQ handling
+assign up_irq_pending = ~up_irq_mask & up_irq_source;
+assign up_irq_trigger  = {up_eot, up_sot};
+assign up_irq_source_clear = (up_wreq == 1'b1 && up_waddr == 12'h021) ? up_wdata[1:0] : 0;
+
+always @(posedge s_axi_aclk)
+begin
+  if (s_axi_aresetn == 1'b0)
+    irq <= 1'b0;
+  else
+    irq <= |up_irq_pending;
+end
+
+always @(posedge s_axi_aclk)
+begin
+  if (s_axi_aresetn == 1'b0) begin
+    up_irq_source <= 2'b00;
+  end else begin
+    up_irq_source <= up_irq_trigger | (up_irq_source & ~up_irq_source_clear);
+  end
+end
+
+// Register Interface
+
+always @(posedge s_axi_aclk)
+begin
+  if (s_axi_aresetn == 1'b0) begin
+    up_enable <= 'h00;
+    up_pause <= 'h00;
+    up_dma_src_address <= 'h00;
+    up_dma_dest_address <= 'h00;
+    up_dma_y_length <= 'h00;
+    up_dma_x_length <= 'h00;
+    up_dma_dest_stride <= 'h00;
+    up_dma_src_stride <= 'h00;
+    up_irq_mask <= 3'b11;
+    up_dma_req_valid <= 1'b0;
+    up_scratch <= 'h00;
+    up_wack <= 1'b0;
+  end else begin
+    up_wack <= up_wreq;
+    if (up_enable == 1'b1) begin
+      if (up_wreq && up_waddr == 12'h102) begin
+        up_dma_req_valid <= up_dma_req_valid | up_wdata[0];
+      end else if (up_sot) begin
+        up_dma_req_valid <= 1'b0;
+      end
+    end else begin
+      up_dma_req_valid <= 1'b0;
+    end
+
+    if (up_wreq) begin
+      case (up_waddr)
+      12'h002: up_scratch <= up_wdata;
+      12'h020: up_irq_mask <= up_wdata;
+      12'h100: {up_pause, up_enable} <= up_wdata[1:0];
+                        12'h103: begin
+                          if (CYCLIC) up_dma_cyclic <= up_wdata[0];
+                          up_axis_xlast <= up_wdata[1];
+                        end
+      12'h104: up_dma_dest_address <= up_wdata[31:BYTES_PER_BEAT_WIDTH_DEST];
+      12'h105: up_dma_src_address <= up_wdata[31:BYTES_PER_BEAT_WIDTH_SRC];
+      12'h106: up_dma_x_length <= up_wdata[DMA_LENGTH_WIDTH-1:0];
+      12'h107: up_dma_y_length <= up_wdata[DMA_LENGTH_WIDTH-1:0];
+      12'h108: up_dma_dest_stride <= up_wdata[DMA_LENGTH_WIDTH-1:0];
+      12'h109: up_dma_src_stride <= up_wdata[DMA_LENGTH_WIDTH-1:0];
+      endcase
+    end
+  end
+end
+
+always @(posedge s_axi_aclk)
+begin
+  if (s_axi_aresetn == 1'b0) begin
+    up_rack <= 'd0;
+    up_rdata <= 'h00;
+  end else begin
+    up_rack <= up_rreq;
+    case (up_raddr)
+    12'h000: up_rdata <= PCORE_VERSION;
+    12'h001: up_rdata <= ID;
+    12'h002: up_rdata <= up_scratch;
+    12'h003: up_rdata <= 32'h444d4143; // "DMAC"
+    12'h020: up_rdata <= up_irq_mask;
+    12'h021: up_rdata <= up_irq_pending;
+    12'h022: up_rdata <= up_irq_source;
+    12'h100: up_rdata <= {up_pause, up_enable};
+    12'h101: up_rdata <= up_transfer_id;
+    12'h102: up_rdata <= up_dma_req_valid;
+    12'h103: up_rdata <= {30'h00, up_axis_xlast, up_dma_cyclic}; // Flags
+    12'h104: up_rdata <= HAS_DEST_ADDR ? {up_dma_dest_address,{BYTES_PER_BEAT_WIDTH_DEST{1'b0}}} : 'h00;
+    12'h105: up_rdata <= HAS_SRC_ADDR ? {up_dma_src_address,{BYTES_PER_BEAT_WIDTH_SRC{1'b0}}} : 'h00;
+    12'h106: up_rdata <= up_dma_x_length;
+    12'h107: up_rdata <= DMA_2D_TRANSFER ? up_dma_y_length : 'h00;
+    12'h108: up_rdata <= DMA_2D_TRANSFER ? up_dma_dest_stride : 'h00;
+    12'h109: up_rdata <= DMA_2D_TRANSFER ? up_dma_src_stride : 'h00;
+    12'h10a: up_rdata <= up_transfer_done_bitmap;
+    12'h10b: up_rdata <= up_transfer_id_eot;
+    12'h10c: up_rdata <= 'h00; // Status
+    12'h10d: up_rdata <= m_dest_axi_awaddr; //HAS_DEST_ADDR ? 'h00 : 'h00; // Current dest address
+    12'h10e: up_rdata <= m_src_axi_araddr; //HAS_SRC_ADDR ? 'h00 : 'h00; // Current src address
+    12'h10f: up_rdata <= {src_response_id, 1'b0, src_data_id, 1'b0, src_address_id, 1'b0, src_request_id,
+              1'b0, dest_response_id, 1'b0, dest_data_id, 1'b0, dest_address_id, 1'b0, dest_request_id};
+    12'h110: up_rdata <= dbg_status;
+    default: up_rdata <= 'h00;
+    endcase
+  end
+end
+
+// Request ID and Request done bitmap handling
+always @(posedge s_axi_aclk)
+begin
+  if (s_axi_aresetn == 1'b0 || up_enable == 1'b0) begin
+    up_transfer_id <= 'h0;
+    up_transfer_id_eot <= 'h0;
+    up_transfer_done_bitmap <= 'h0;
+  end begin
+    if (up_dma_req_valid == 1'b1 && up_dma_req_ready == 1'b1) begin
+      up_transfer_id <= up_transfer_id + 1'b1;
+      up_transfer_done_bitmap[up_transfer_id] <= 1'b0;
+    end
+    if (up_eot == 1'b1) begin
+      up_transfer_done_bitmap[up_transfer_id_eot] <= 1'b1;
+      up_transfer_id_eot <= up_transfer_id_eot + 1'b1;
+    end
+  end
+end
+
+wire dma_req_valid;
+wire dma_req_ready;
+wire [31:BYTES_PER_BEAT_WIDTH_DEST] dma_req_dest_address;
+wire [31:BYTES_PER_BEAT_WIDTH_SRC] dma_req_src_address;
+wire [DMA_LENGTH_WIDTH-1:0] dma_req_length;
+wire dma_req_eot;
+wire dma_req_sync_transfer_start;
+wire up_req_eot;
+
+assign up_sot = up_dma_cyclic ? 1'b0 : up_dma_req_valid & up_dma_req_ready;
+assign up_eot = up_dma_cyclic ? 1'b0 : up_req_eot;
+
+
+generate if (DMA_2D_TRANSFER == 1) begin
+
+dmac_2d_transfer #(
+  .DMA_LENGTH_WIDTH(DMA_LENGTH_WIDTH),
+  .BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST),
+  .BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC)
+) i_2d_transfer (
+  .req_aclk(s_axi_aclk),
+  .req_aresetn(s_axi_aresetn),
+
+  .req_eot(up_req_eot),
+
+  .req_valid(up_dma_req_valid),
+  .req_ready(up_dma_req_ready),
+  .req_dest_address(up_dma_dest_address),
+  .req_src_address(up_dma_src_address),
+  .req_x_length(up_dma_x_length),
+  .req_y_length(up_dma_y_length),
+  .req_dest_stride(up_dma_dest_stride),
+  .req_src_stride(up_dma_src_stride),
+  .req_sync_transfer_start(up_dma_sync_transfer_start),
+
+  .out_req_valid(dma_req_valid),
+  .out_req_ready(dma_req_ready),
+  .out_req_dest_address(dma_req_dest_address),
+  .out_req_src_address(dma_req_src_address),
+  .out_req_length(dma_req_length),
+  .out_req_sync_transfer_start(dma_req_sync_transfer_start),
+  .out_eot(dma_req_eot)
+);
+
+end else begin
+
+assign dma_req_valid = up_dma_req_valid;
+assign up_dma_req_ready = dma_req_ready;
+assign dma_req_dest_address = up_dma_dest_address;
+assign dma_req_src_address = up_dma_src_address;
+assign dma_req_length = up_dma_x_length;
+assign dma_req_sync_transfer_start = up_dma_sync_transfer_start;
+assign up_req_eot = dma_req_eot;
+
+end endgenerate
+
+dmac_request_arb #(
+  .DMA_DATA_WIDTH_SRC(DMA_DATA_WIDTH_SRC),
+  .DMA_DATA_WIDTH_DEST(DMA_DATA_WIDTH_DEST),
+  .DMA_LENGTH_WIDTH(DMA_LENGTH_WIDTH),
+  .BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST),
+  .BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC),
+  .DMA_TYPE_DEST(DMA_TYPE_DEST),
+  .DMA_TYPE_SRC(DMA_TYPE_SRC),
+  .ASYNC_CLK_REQ_SRC(ASYNC_CLK_REQ_SRC),
+  .ASYNC_CLK_SRC_DEST(ASYNC_CLK_SRC_DEST),
+  .ASYNC_CLK_DEST_REQ(ASYNC_CLK_DEST_REQ),
+  .AXI_SLICE_DEST(AXI_SLICE_DEST),
+  .AXI_SLICE_SRC(AXI_SLICE_SRC),
+  .MAX_BYTES_PER_BURST(MAX_BYTES_PER_BURST),
+  .FIFO_SIZE(FIFO_SIZE),
+  .ID_WIDTH(ID_WIDTH)
+) i_request_arb (
+  .req_aclk(s_axi_aclk),
+  .req_aresetn(s_axi_aresetn),
+
+  .enable(up_enable),
+  .pause(up_pause),
+
+  .req_valid(dma_req_valid),
+  .req_ready(dma_req_ready),
+  .req_dest_address(dma_req_dest_address),
+  .req_src_address(dma_req_src_address),
+  .req_length(dma_req_length),
+        .req_xlast(up_axis_xlast),
+  .req_sync_transfer_start(dma_req_sync_transfer_start),
+
+  .eot(dma_req_eot),
+
+
+  .m_dest_axi_aclk(m_dest_axi_aclk),
+  .m_dest_axi_aresetn(m_dest_axi_aresetn),
+  .m_src_axi_aclk(m_src_axi_aclk),
+  .m_src_axi_aresetn(m_src_axi_aresetn),
+
+
+  .m_axi_awaddr(m_dest_axi_awaddr),
+  .m_axi_awlen(m_dest_axi_awlen),
+  .m_axi_awsize(m_dest_axi_awsize),
+  .m_axi_awburst(m_dest_axi_awburst),
+  .m_axi_awprot(m_dest_axi_awprot),
+  .m_axi_awcache(m_dest_axi_awcache),
+  .m_axi_awvalid(m_dest_axi_awvalid),
+  .m_axi_awready(m_dest_axi_awready),
+
+
+  .m_axi_wdata(m_dest_axi_wdata),
+  .m_axi_wstrb(m_dest_axi_wstrb),
+  .m_axi_wready(m_dest_axi_wready),
+  .m_axi_wvalid(m_dest_axi_wvalid),
+  .m_axi_wlast(m_dest_axi_wlast),
+
+
+  .m_axi_bvalid(m_dest_axi_bvalid),
+  .m_axi_bresp(m_dest_axi_bresp),
+  .m_axi_bready(m_dest_axi_bready),
+
+
+  .m_axi_arready(m_src_axi_arready),
+  .m_axi_arvalid(m_src_axi_arvalid),
+  .m_axi_araddr(m_src_axi_araddr),
+  .m_axi_arlen(m_src_axi_arlen),
+  .m_axi_arsize(m_src_axi_arsize),
+  .m_axi_arburst(m_src_axi_arburst),
+  .m_axi_arprot(m_src_axi_arprot),
+  .m_axi_arcache(m_src_axi_arcache),
+
+
+  .m_axi_rdata(m_src_axi_rdata),
+  .m_axi_rready(m_src_axi_rready),
+  .m_axi_rvalid(m_src_axi_rvalid),
+  .m_axi_rresp(m_src_axi_rresp),
+
+
+  .s_axis_aclk(s_axis_aclk),
+  .s_axis_ready(s_axis_ready),
+  .s_axis_valid(s_axis_valid),
+  .s_axis_data(s_axis_data),
+  .s_axis_user(s_axis_user),
+  .s_axis_xfer_req(s_axis_xfer_req),
+
+
+  .m_axis_aclk(m_axis_aclk),
+  .m_axis_ready(m_axis_ready),
+  .m_axis_valid(m_axis_valid),
+  .m_axis_data(m_axis_data),
+        .m_axis_last(m_axis_last),
+        .m_axis_xfer_req(m_axis_xfer_req),
+
+
+  .fifo_wr_clk(fifo_wr_clk),
+  .fifo_wr_en(fifo_wr_en),
+  .fifo_wr_din(fifo_wr_din),
+  .fifo_wr_overflow(fifo_wr_overflow),
+  .fifo_wr_sync(fifo_wr_sync),
+  .fifo_wr_xfer_req(fifo_wr_xfer_req),
+
+
+  .fifo_rd_clk(fifo_rd_clk),
+  .fifo_rd_en(fifo_rd_en),
+  .fifo_rd_valid(fifo_rd_valid),
+  .fifo_rd_dout(fifo_rd_dout),
+  .fifo_rd_underflow(fifo_rd_underflow),
+        .fifo_rd_xfer_req(fifo_rd_xfer_req),
+
+  // DBG
+  .dbg_dest_request_id(dest_request_id),
+  .dbg_dest_address_id(dest_address_id),
+  .dbg_dest_data_id(dest_data_id),
+  .dbg_dest_response_id(dest_response_id),
+  .dbg_src_request_id(src_request_id),
+  .dbg_src_address_id(src_address_id),
+  .dbg_src_data_id(src_data_id),
+  .dbg_src_response_id(src_response_id),
+  .dbg_status(dbg_status)
+);
+
+assign m_dest_axi_arvalid = 1'b0;
+assign m_dest_axi_rready = 1'b0;
+assign m_dest_axi_araddr = 'h0;
+assign m_dest_axi_arlen = 'h0;
+assign m_dest_axi_arsize = 'h0;
+assign m_dest_axi_arburst = 'h0;
+assign m_dest_axi_arcache = 'h0;
+assign m_dest_axi_arprot = 'h0;
+
+assign m_src_axi_awvalid = 1'b0;
+assign m_src_axi_wvalid = 1'b0;
+assign m_src_axi_bready = 1'b0;
+assign m_src_axi_awvalid = 'h0;
+assign m_src_axi_awaddr = 'h0;
+assign m_src_axi_awlen = 'h0;
+assign m_src_axi_awsize = 'h0;
+assign m_src_axi_awburst = 'h0;
+assign m_src_axi_awcache = 'h0;
+assign m_src_axi_awprot = 'h0;
+assign m_src_axi_wvalid = 'h0;
+assign m_src_axi_wdata = 'h0;
+assign m_src_axi_wstrb = 'h0;
+assign m_src_axi_wlast = 'h0;
+
+endmodule
diff --git a/fpga/usrp3/lib/vivado_ipi/axi_dmac/axi_dmac_constr.ttcl b/fpga/usrp3/lib/vivado_ipi/axi_dmac/axi_dmac_constr.ttcl
new file mode 100644
index 000000000..a2cabf55f
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/axi_dmac/axi_dmac_constr.ttcl
@@ -0,0 +1,167 @@
+<: set ComponentName [getComponentNameString] :>
+<: setOutputDirectory "./" :>
+<: setFileName [ttcl_add $ComponentName "_constr"] :>
+<: setFileExtension ".xdc" :>
+<: setFileProcessingOrder late :>
+<: set async_dest_req [getBooleanValue "ASYNC_CLK_DEST_REQ"] :>
+<: set async_req_src [getBooleanValue "ASYNC_CLK_REQ_SRC"] :>
+<: set async_src_dest [getBooleanValue "ASYNC_CLK_SRC_DEST"] :>
+
+set req_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
+set src_clk [get_clocks -of_objects [get_ports -quiet {fifo_wr_clk s_axis_aclk m_src_axi_aclk}]]
+set dest_clk [get_clocks -of_objects [get_ports -quiet {fifo_rd_clk m_axis_aclk m_dest_axi_aclk}]]
+
+<: if {$async_req_src || $async_src_dest || $async_dest_req} { :>
+set_property ASYNC_REG TRUE \
+	[get_cells -quiet -hier *cdc_sync_stage1_reg*] \
+	[get_cells -quiet -hier *cdc_sync_stage2_reg*]
+
+<: } :>
+<: if {$async_req_src} { :>
+set_max_delay -quiet -datapath_only \
+	-from $req_clk \
+	-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
+		-filter {NAME =~ *i_sync_src_request_id* && IS_SEQUENTIAL}] \
+	[get_property -min PERIOD $req_clk]
+
+set_false_path -quiet \
+	-from $src_clk \
+	-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
+		-filter {NAME =~ *i_sync_status_src* && IS_SEQUENTIAL}]
+
+set_false_path -quiet \
+	-from $req_clk \
+	-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
+		-filter {NAME =~ *i_sync_control_src* && IS_SEQUENTIAL}]
+
+set_max_delay -quiet -datapath_only \
+	-from $req_clk \
+	-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
+		-filter {NAME =~ *i_src_req_fifo/i_waddr_sync* && IS_SEQUENTIAL}] \
+	[get_property -min PERIOD $req_clk]
+
+set_max_delay -quiet -datapath_only \
+	-from $src_clk \
+	-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
+		-filter {NAME =~ *i_src_req_fifo/i_raddr_sync* && IS_SEQUENTIAL}] \
+	[get_property -min PERIOD $src_clk]
+
+set_max_delay -quiet -datapath_only \
+	-from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \
+		-filter {NAME =~ *i_src_req_fifo* && IS_SEQUENTIAL}] \
+	-to $src_clk \
+	[get_property -min PERIOD $src_clk]
+
+set_max_delay -quiet -datapath_only \
+	-from [get_cells -quiet -hier *eot_mem_reg* \
+		-filter {NAME =~ *i_request_arb* && IS_SEQUENTIAL}] \
+	-to $src_clk \
+	[get_property -min PERIOD $src_clk]
+
+<: } :>
+<: if {$async_dest_req} { :>
+set_max_delay -quiet -datapath_only \
+	-from $dest_clk \
+	-to [get_cells -hier *cdc_sync_stage1_reg* \
+		-filter {NAME =~ *i_sync_req_response_id* && IS_SEQUENTIAL}] \
+	[get_property -min PERIOD $dest_clk]
+
+set_false_path -quiet \
+	-from $dest_clk \
+	-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
+		-filter {NAME =~ *i_sync_status_dest* && IS_SEQUENTIAL}]
+
+set_false_path -quiet \
+	-from $req_clk \
+	-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
+		-filter {NAME =~ *i_sync_control_dest* && IS_SEQUENTIAL}]
+
+set_max_delay -quiet -datapath_only \
+	-from $req_clk \
+	-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
+		-filter {NAME =~ *i_dest_req_fifo/i_waddr_sync* && IS_SEQUENTIAL}] \
+	[get_property -min PERIOD $req_clk]
+
+set_max_delay -quiet -datapath_only \
+	-from $dest_clk \
+	-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
+		-filter {NAME =~ *i_dest_req_fifo/i_raddr_sync* && IS_SEQUENTIAL}] \
+	[get_property -min PERIOD $dest_clk]
+
+set_max_delay -quiet -datapath_only \
+	-from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \
+		-filter {NAME =~ *i_dest_req_fifo* && IS_SEQUENTIAL}] \
+	-to $dest_clk \
+	[get_property -min PERIOD $dest_clk]
+
+set_max_delay -quiet -datapath_only \
+	-from $dest_clk \
+	-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
+		-filter {NAME =~ *i_dest_response_fifo/i_waddr_sync* && IS_SEQUENTIAL}] \
+	[get_property -min PERIOD $dest_clk]
+
+set_max_delay -quiet -datapath_only \
+	-from $req_clk \
+	-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
+		-filter {NAME =~ *i_dest_response_fifo/i_raddr_sync* && IS_SEQUENTIAL}] \
+	[get_property -min PERIOD $req_clk]
+set_max_delay -quiet -datapath_only \
+	-from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \
+		-filter {NAME =~ *i_dest_response_fifo* && IS_SEQUENTIAL}] \
+	-to $req_clk \
+	[get_property -min PERIOD $req_clk]
+
+set_max_delay -quiet -datapath_only \
+	-from [get_cells -quiet -hier *eot_mem_reg* \
+		-filter {NAME =~ *i_request_arb* && IS_SEQUENTIAL}] \
+	-to $dest_clk \
+	[get_property -min PERIOD $dest_clk]
+
+<: } :>
+<: if {$async_src_dest} { :>
+set_max_delay -quiet -datapath_only \
+	-from $src_clk \
+	-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
+		-filter {NAME =~ *i_sync_dest_request_id* && IS_SEQUENTIAL}] \
+	[get_property -min PERIOD $src_clk]
+
+set_max_delay -quiet -datapath_only \
+	-from $src_clk \
+	-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
+		-filter {NAME =~ *i_fifo/i_address_gray/i_waddr_sync* && IS_SEQUENTIAL}] \
+	[get_property -min PERIOD $src_clk]
+
+set_max_delay -quiet -datapath_only \
+	-from $dest_clk \
+	-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
+		-filter {NAME =~ *i_fifo/i_address_gray/i_raddr_sync* && IS_SEQUENTIAL}] \
+	[get_property -min PERIOD $dest_clk]
+
+# In SDP mode REGCEB should not be connected. When inferring the BRAM the tools
+# do it anyway. The signal is not used by the BRAM though. But since the clock
+# associated with REGCEB is the write clock and not the read clock we get a
+# timing problem. Mark the path as a false path so it is not timed.
+set_false_path -quiet \
+	-to [get_pins -hier *ram_reg*/REGCEB -filter {NAME =~ *i_fifo*}]
+
+<: } :>
+# Reset signals
+set_false_path -quiet \
+	-from $req_clk \
+	-to [get_pins -quiet -hier *reset_shift_reg*/PRE]
+
+# Ignore timing for debug signals to register map
+set_false_path -quiet \
+	-from [get_cells -quiet -hier *cdc_sync_stage2_reg* \
+		-filter {name =~ *i_sync_src_request_id* && IS_SEQUENTIAL}] \
+	-to [get_cells -quiet -hier *up_rdata_reg* -filter {IS_SEQUENTIAL}]
+set_false_path -quiet \
+	-from [get_cells -quiet -hier *cdc_sync_stage2_reg* \
+		-filter {name =~ *i_sync_dest_request_id* && IS_SEQUENTIAL}] \
+	-to [get_cells -quiet -hier *up_rdata_reg* -filter {IS_SEQUENTIAL}]
+set_false_path -quiet \
+	-from [get_cells -quiet -hier *id_reg* -filter {name =~ *i_request_arb* && IS_SEQUENTIAL}] \
+	-to [get_cells -quiet -hier *up_rdata_reg* -filter {IS_SEQUENTIAL}]
+set_false_path -quiet \
+	-from [get_cells -quiet -hier *address_reg* -filter {name =~ *i_addr_gen* && IS_SEQUENTIAL}] \
+	-to [get_cells -quiet -hier *up_rdata_reg* -filter {IS_SEQUENTIAL}]
diff --git a/fpga/usrp3/lib/vivado_ipi/axi_dmac/axi_register_slice.v b/fpga/usrp3/lib/vivado_ipi/axi_dmac/axi_register_slice.v
new file mode 100644
index 000000000..159f0d0fe
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/axi_dmac/axi_register_slice.v
@@ -0,0 +1,139 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2013(c) Analog Devices, Inc.
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+module axi_register_slice (
+  input clk,
+  input resetn,
+
+  input s_axi_valid,
+  output s_axi_ready,
+  input [DATA_WIDTH-1:0] s_axi_data,
+
+  output m_axi_valid,
+  input m_axi_ready,
+  output [DATA_WIDTH-1:0] m_axi_data
+);
+
+parameter DATA_WIDTH = 32;
+
+parameter FORWARD_REGISTERED = 0;
+parameter BACKWARD_REGISTERED = 0;
+
+/*
+ s_axi_data  -> bwd_data     -> fwd_data(1)  -> m_axi_data
+ s_axi_valid -> bwd_valid    -> fwd_valid(1) -> m_axi_valid
+ s_axi_ready <- bwd_ready(2) <- fwd_ready <- m_axi_ready
+
+ (1) FORWARD_REGISTERED inserts a set of FF before m_axi_data and m_axi_valid
+ (2) BACKWARD_REGISTERED insters a FF before s_axi_ready
+*/
+
+wire [DATA_WIDTH-1:0] bwd_data_s;
+wire bwd_valid_s;
+wire bwd_ready_s;
+wire [DATA_WIDTH-1:0] fwd_data_s;
+wire fwd_valid_s;
+wire fwd_ready_s;
+
+generate if (FORWARD_REGISTERED == 1) begin
+
+reg fwd_valid = 1'b0;
+reg [DATA_WIDTH-1:0] fwd_data = 'h00;
+
+assign fwd_ready_s = ~fwd_valid | m_axi_ready;
+assign fwd_valid_s = fwd_valid;
+assign fwd_data_s = fwd_data;
+
+always @(posedge clk) begin
+  if (~fwd_valid | m_axi_ready)
+    fwd_data <= bwd_data_s;
+end
+
+always @(posedge clk) begin
+  if (resetn == 1'b0) begin
+    fwd_valid <= 1'b0;
+  end else begin 
+    if (bwd_valid_s)
+      fwd_valid <= 1'b1;
+    else if (m_axi_ready)
+      fwd_valid <= 1'b0;
+  end
+end
+
+end else begin
+assign fwd_data_s = bwd_data_s;
+assign fwd_valid_s = bwd_valid_s;
+assign fwd_ready_s = m_axi_ready;
+end
+endgenerate
+
+generate if (BACKWARD_REGISTERED == 1) begin
+
+reg bwd_ready = 1'b1;
+reg [DATA_WIDTH-1:0] bwd_data = 'h00;
+
+assign bwd_valid_s = ~bwd_ready | s_axi_valid;
+assign bwd_data_s = bwd_ready ? s_axi_data : bwd_data;
+assign bwd_ready_s = bwd_ready;
+
+always @(posedge clk) begin
+  if (bwd_ready)
+    bwd_data <= s_axi_data;
+end
+
+always @(posedge clk) begin
+  if (resetn == 1'b0) begin
+    bwd_ready <= 1'b1;
+  end else begin
+    if (fwd_ready_s)
+      bwd_ready <= 1'b1;
+    else if (s_axi_valid)
+      bwd_ready <= 1'b0;
+  end
+end
+
+end else begin
+assign bwd_valid_s = s_axi_valid;
+assign bwd_data_s = s_axi_data;
+assign bwd_ready_s = fwd_ready_s;
+end endgenerate
+
+assign m_axi_data = fwd_data_s;
+assign m_axi_valid = fwd_valid_s;
+assign s_axi_ready = bwd_ready_s;
+
+endmodule
diff --git a/fpga/usrp3/lib/vivado_ipi/axi_dmac/bd/bd.tcl b/fpga/usrp3/lib/vivado_ipi/axi_dmac/bd/bd.tcl
new file mode 100644
index 000000000..d67f5134c
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/axi_dmac/bd/bd.tcl
@@ -0,0 +1,115 @@
+
+proc init {cellpath otherInfo} {
+	set ip [get_bd_cells $cellpath]
+
+	bd::mark_propagate_override $ip \
+		"ASYNC_CLK_REQ_SRC ASYNC_CLK_SRC_DEST ASYNC_CLK_DEST_REQ"
+
+	# On ZYNQ the core is most likely connected to the AXI3 HP ports so use AXI3
+	# as the default.
+	set family [string tolower [get_property FAMILY [get_property PART [current_project]]]]
+	if {$family == "zynq"} {
+		set axi_protocol 1
+	} else {
+		set axi_protocol 0
+	}
+
+	foreach dir {SRC DEST} {
+		# This is a bit of a hack, but we can't change the protocol if the type
+		# is not AXI MM
+		set old [get_property "CONFIG.DMA_TYPE_${dir}" $ip]
+		set_property "CONFIG.DMA_TYPE_${dir}" "0" $ip
+		set_property "CONFIG.DMA_AXI_PROTOCOL_${dir}" $axi_protocol $ip
+		set_property "CONFIG.DMA_TYPE_${dir}" $old $ip
+	}
+}
+
+proc post_config_ip {cellpath otherinfo} {
+	set ip [get_bd_cells $cellpath]
+
+	# Update AXI interface properties according to configuration
+	set max_bytes_per_burst [get_property "CONFIG.MAX_BYTES_PER_BURST" $ip]
+	set fifo_size [get_property "CONFIG.FIFO_SIZE" $ip]
+
+	foreach dir {"SRC" "DEST"} {
+		set type [get_property "CONFIG.DMA_TYPE_$dir" $ip]
+		if {$type != 0} {
+			continue
+		}
+
+		set data_width [get_property "CONFIG.DMA_DATA_WIDTH_$dir" $ip]
+		set max_beats_per_burst [expr {int(ceil($max_bytes_per_burst * 8.0 / $data_width))}]
+
+		set intf [get_bd_intf_pins [format "%s/m_%s_axi" $cellpath [string tolower $dir]]]
+		set_property CONFIG.MAX_BURST_LENGTH $max_beats_per_burst $intf
+
+		# The core issues as many requests as the amount of data the FIFO can hold
+		if {$dir == "SRC"} {
+			set_property CONFIG.NUM_WRITE_OUTSTANDING 0 $intf
+			set_property CONFIG.NUM_READ_OUTSTANDING $fifo_size $intf
+		} else {
+			set_property CONFIG.NUM_WRITE_OUTSTANDING $fifo_size $intf
+			set_property CONFIG.NUM_READ_OUTSTANDING 0 $intf
+		}
+	}
+}
+
+proc axi_dmac_detect_async_clk { cellpath ip param_name clk_a clk_b } {
+	set param_src [get_property "CONFIG.$param_name.VALUE_SRC" $ip]
+	if {[string equal $param_src "USER"]} {
+		return;
+	}
+
+	set clk_domain_a [get_property CONFIG.CLK_DOMAIN $clk_a]
+	set clk_domain_b [get_property CONFIG.CLK_DOMAIN $clk_b]
+	set clk_freq_a [get_property CONFIG.FREQ_HZ $clk_a]
+	set clk_freq_b [get_property CONFIG.FREQ_HZ $clk_b]
+	set clk_phase_a [get_property CONFIG.PHASE $clk_a]
+	set clk_phase_b [get_property CONFIG.PHASE $clk_b]
+
+	# Only mark it as sync if we can make sure that it is sync, if the
+	# relationship of the clocks is unknown mark it as async
+	if {$clk_domain_a != {} && $clk_domain_b != {} && \
+		$clk_domain_a == $clk_domain_b && $clk_freq_a == $clk_freq_b && \
+		$clk_phase_a == $clk_phase_b} {
+		set clk_async 0
+	} else {
+		set clk_async 1
+	}
+
+	set_property "CONFIG.$param_name" $clk_async $ip
+
+#	if {$clk_async == 0} {
+#		bd::send_msg -of $cellpath -type INFO -msg_id 1 -text "$clk_a and $clk_b are synchronous"
+#	} else {
+#		bd::send_msg -of $cellpath -type INFO -msg_id 1 -text "$clk_a and $clk_b are asynchronous"
+#	}
+}
+
+proc propagate {cellpath otherinfo} {
+	set ip [get_bd_cells $cellpath]
+	set src_type [get_property CONFIG.DMA_TYPE_SRC $ip]
+	set dest_type [get_property CONFIG.DMA_TYPE_DEST $ip]
+
+	set req_clk [get_bd_pins "$ip/s_axi_aclk"]
+
+	if {$src_type == 2} {
+		set src_clk [get_bd_pins "$ip/fifo_wr_clk"]
+	} elseif {$src_type == 1} {
+		set src_clk [get_bd_pins "$ip/s_axis_aclk"]
+	} else {
+		set src_clk [get_bd_pins "$ip/m_src_axi_aclk"]
+	}
+
+	if {$dest_type == 2} {
+		set dest_clk [get_bd_pins "$ip/fifo_rd_clk"]
+	} elseif {$dest_type == 1} {
+		set dest_clk [get_bd_pins "$ip/m_axis_aclk"]
+	} else {
+		set dest_clk [get_bd_pins "$ip/m_dest_axi_aclk"]
+	}
+
+	axi_dmac_detect_async_clk $cellpath $ip "ASYNC_CLK_REQ_SRC" $req_clk $src_clk
+	axi_dmac_detect_async_clk $cellpath $ip "ASYNC_CLK_SRC_DEST" $src_clk $dest_clk
+	axi_dmac_detect_async_clk $cellpath $ip "ASYNC_CLK_DEST_REQ" $dest_clk $req_clk
+}
diff --git a/fpga/usrp3/lib/vivado_ipi/axi_dmac/component.xml b/fpga/usrp3/lib/vivado_ipi/axi_dmac/component.xml
new file mode 100644
index 000000000..a3626529e
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/axi_dmac/component.xml
@@ -0,0 +1,4107 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>analog.com</spirit:vendor>
+  <spirit:library>user</spirit:library>
+  <spirit:name>axi_dmac</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>s_axi</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="s_axi"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>s_axi_aclk</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_aclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.ASSOCIATED_BUSIF">s_axi</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.ASSOCIATED_RESET">s_axi_aresetn</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>s_axi_aresetn</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_aresetn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_ARESETN.POLARITY" spirit:choiceRef="choice_list_74b5137e">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>m_dest_axi</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="m_dest_axi"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_dest_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_dest_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_dest_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_dest_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_dest_axi_awcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_dest_axi_awprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_dest_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_dest_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_dest_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_dest_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_dest_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_dest_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_dest_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_dest_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_dest_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_dest_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_dest_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_dest_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_dest_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_dest_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_dest_axi_arcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_dest_axi_arprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_dest_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_dest_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_dest_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_dest_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_dest_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_dest_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_DEST_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.m_dest_axi" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.DMA_TYPE_DEST&apos;)) = 0)">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>m_src_axi</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="m_src_axi"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_src_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_src_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_src_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_src_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_src_axi_awcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_src_axi_awprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_src_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_src_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_src_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_src_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_src_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_src_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_src_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_src_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_src_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_src_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_src_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_src_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_src_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_src_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_src_axi_arcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_src_axi_arprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_src_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_src_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_src_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_src_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_src_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_src_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_SRC_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.m_src_axi" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.DMA_TYPE_SRC&apos;)) = 0)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>m_dest_axi_aresetn</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_dest_axi_aresetn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_DEST_AXI_ARESETN.POLARITY" spirit:choiceRef="choice_list_74b5137e">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>m_src_axi_aresetn</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_src_axi_aresetn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_SRC_AXI_ARESETN.POLARITY" spirit:choiceRef="choice_list_74b5137e">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>m_dest_axi_aclk</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_dest_axi_aclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_DEST_AXI_ACLK.ASSOCIATED_BUSIF">m_dest_axi</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_DEST_AXI_ACLK.ASSOCIATED_RESET">m_dest_axi_aresetn</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>m_src_axi_aclk</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_src_axi_aclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_SRC_AXI_ACLK.ASSOCIATED_BUSIF">m_src_axi</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_SRC_AXI_ACLK.ASSOCIATED_RESET">m_src_axi_aresetn</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>irq</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>irq</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.IRQ.SENSITIVITY" spirit:choiceRef="choice_list_9ca20931">LEVEL_HIGH</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>s_axis</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_valid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_data</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_user</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.s_axis" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.DMA_TYPE_SRC&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>s_axis_signal_clock</spirit:name>
+      <spirit:displayName>s_axis_signal_clock</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_aclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS_SIGNAL_CLOCK.ASSOCIATED_BUSIF">s_axis</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>m_axis</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_valid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_data</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_last</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.m_axis" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.DMA_TYPE_DEST&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>m_axis_signal_clock</spirit:name>
+      <spirit:displayName>m_axis_signal_clock</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_aclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS_SIGNAL_CLOCK.ASSOCIATED_BUSIF">m_axis</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>fifo_wr</spirit:name>
+      <spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="fifo_wr" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="fifo_wr_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>fifo_wr_en</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
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+      <spirit:name>xilinx_blockdiagram_analog_com_user_util_axis_resize_1_0__ref_view_fileset</spirit:name>
+      <spirit:vendorExtensions>
+        <xilinx:subCoreRef>
+          <xilinx:componentRef xilinx:vendor="analog.com" xilinx:library="user" xilinx:name="util_axis_resize" xilinx:version="1.0"/>
+        </xilinx:subCoreRef>
+      </spirit:vendorExtensions>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_blockdiagram_analog_com_user_util_axis_fifo_1_0__ref_view_fileset</spirit:name>
+      <spirit:vendorExtensions>
+        <xilinx:subCoreRef>
+          <xilinx:componentRef xilinx:vendor="analog.com" xilinx:library="user" xilinx:name="util_axis_fifo" xilinx:version="1.0"/>
+        </xilinx:subCoreRef>
+      </spirit:vendorExtensions>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_utilityxitfiles_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>gui/axi_dmac_v1_0.gtcl</spirit:name>
+        <spirit:userFileType>GTCL</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>ADI AXI DMA Controller</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>ID</spirit:name>
+      <spirit:displayName>Core ID</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ID">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>DMA_DATA_WIDTH_SRC</spirit:name>
+      <spirit:displayName>Bus Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DMA_DATA_WIDTH_SRC" spirit:choiceRef="choice_list_259f6857">64</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>DMA_DATA_WIDTH_DEST</spirit:name>
+      <spirit:displayName>Bus Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DMA_DATA_WIDTH_DEST" spirit:choiceRef="choice_list_259f6857">64</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>DMA_LENGTH_WIDTH</spirit:name>
+      <spirit:displayName>DMA Transfer Length Register Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DMA_LENGTH_WIDTH" spirit:minimum="8" spirit:maximum="32" spirit:rangeType="long">24</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>DMA_2D_TRANSFER</spirit:name>
+      <spirit:displayName>2D Transfer Support</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.DMA_2D_TRANSFER">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ASYNC_CLK_REQ_SRC</spirit:name>
+      <spirit:displayName>Request and Source Clock Asynchronous</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ASYNC_CLK_REQ_SRC">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ASYNC_CLK_SRC_DEST</spirit:name>
+      <spirit:displayName>Source and Destination Clock Asynchronous</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ASYNC_CLK_SRC_DEST">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ASYNC_CLK_DEST_REQ</spirit:name>
+      <spirit:displayName>Destination and Request Clock Asynchronous</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ASYNC_CLK_DEST_REQ">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXI_SLICE_DEST</spirit:name>
+      <spirit:displayName>Insert Register Slice</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_SLICE_DEST">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXI_SLICE_SRC</spirit:name>
+      <spirit:displayName>Insert Register Slice</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_SLICE_SRC">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>SYNC_TRANSFER_START</spirit:name>
+      <spirit:displayName>Transfer Start Synchronization Support</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.SYNC_TRANSFER_START">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CYCLIC</spirit:name>
+      <spirit:displayName>Cyclic Transfer Support</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CYCLIC">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>DMA_AXI_PROTOCOL_DEST</spirit:name>
+      <spirit:displayName>AXI Protocol</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DMA_AXI_PROTOCOL_DEST" spirit:choiceRef="choice_pairs_8bd59fa5">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>DMA_AXI_PROTOCOL_SRC</spirit:name>
+      <spirit:displayName>AXI Protocol</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DMA_AXI_PROTOCOL_SRC" spirit:choiceRef="choice_pairs_8bd59fa5">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.DMA_AXI_PROTOCOL_SRC">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>DMA_TYPE_DEST</spirit:name>
+      <spirit:displayName>Type</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DMA_TYPE_DEST" spirit:choiceRef="choice_pairs_1293c054">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>DMA_TYPE_SRC</spirit:name>
+      <spirit:displayName>Type</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DMA_TYPE_SRC" spirit:choiceRef="choice_pairs_1293c054">2</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MAX_BYTES_PER_BURST</spirit:name>
+      <spirit:displayName>Maximum Bytes per Burst</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MAX_BYTES_PER_BURST">128</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>FIFO_SIZE</spirit:name>
+      <spirit:displayName>FIFO Size (In Bursts)</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FIFO_SIZE">4</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">axi_dmac_v1_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:supportedFamilies>
+        <xilinx:family xilinx:lifeCycle="Production">virtex7</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">qvirtex7</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">kintex7</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">kintex7l</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">qkintex7</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">qkintex7l</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">artix7</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">artix7l</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">aartix7</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">qartix7</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">qzynq</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">azynq</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">virtexu</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">kintexuplus</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">zynquplus</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">kintexu</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Beta">virtexuplus</xilinx:family>
+      </xilinx:supportedFamilies>
+      <xilinx:taxonomies>
+        <xilinx:taxonomy>/Analog_Devices</xilinx:taxonomy>
+      </xilinx:taxonomies>
+      <xilinx:displayName>ADI AXI DMA Controller</xilinx:displayName>
+      <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
+      <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+      <xilinx:coreCreationDateTime>2017-04-20T23:54:12Z</xilinx:coreCreationDateTime>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2015.4</xilinx:xilinxVersion>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/fpga/usrp3/lib/vivado_ipi/axi_dmac/data_mover.v b/fpga/usrp3/lib/vivado_ipi/axi_dmac/data_mover.v
new file mode 100644
index 000000000..1f1b9dc04
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/axi_dmac/data_mover.v
@@ -0,0 +1,176 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2013(c) Analog Devices, Inc.
+//  Author: Lars-Peter Clausen <lars@metafoo.de>
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+module dmac_data_mover (
+  input clk,
+  input resetn,
+
+  input [ID_WIDTH-1:0] request_id,
+  output [ID_WIDTH-1:0] response_id,
+  input sync_id,
+  input eot,
+
+  input enable,
+  output reg enabled,
+
+  output xfer_req,
+
+  output s_axi_ready,
+  input s_axi_valid,
+  input [DATA_WIDTH-1:0] s_axi_data,
+
+  input m_axi_ready,
+  output m_axi_valid,
+  output [DATA_WIDTH-1:0] m_axi_data,
+  output m_axi_last,
+
+  input req_valid,
+  output req_ready,
+  input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length
+);
+
+parameter ID_WIDTH = 3;
+parameter DATA_WIDTH = 64;
+parameter DISABLE_WAIT_FOR_ID = 1;
+parameter BEATS_PER_BURST_WIDTH = 4;
+parameter LAST = 0; /* 0 = last asserted at the end of each burst, 1 = last only asserted at the end of the transfer */
+
+localparam MAX_BEATS_PER_BURST = 2**(BEATS_PER_BURST_WIDTH);
+
+`include "inc_id.h"
+
+reg [BEATS_PER_BURST_WIDTH-1:0] last_burst_length = 'h00;
+reg [BEATS_PER_BURST_WIDTH-1:0] beat_counter = 'h00;
+reg [ID_WIDTH-1:0] id = 'h00;
+reg [ID_WIDTH-1:0] id_next = 'h00;
+
+reg pending_burst = 1'b0;
+reg active = 1'b0;
+reg last_eot = 1'b0;
+reg last_non_eot = 1'b0;
+
+wire last_load;
+wire last;
+
+assign xfer_req = active;
+
+assign response_id = id;
+
+assign last = eot ? last_eot : last_non_eot;
+
+assign s_axi_ready = m_axi_ready & pending_burst & active;
+assign m_axi_valid = s_axi_valid & pending_burst & active;
+assign m_axi_data = s_axi_data;
+assign m_axi_last = LAST ? (last_eot & eot) : last;
+
+// If we want to support zero delay between transfers we have to assert
+// req_ready on the same cycle on which the last load happens.
+assign last_load = s_axi_ready && s_axi_valid && last_eot && eot;
+assign req_ready = last_load || ~active;
+
+always @(posedge clk) begin
+  if (resetn == 1'b0) begin
+    enabled <= 1'b0;
+  end else begin
+    if (enable) begin
+      enabled <= 1'b1;
+    end else begin
+      if (DISABLE_WAIT_FOR_ID == 0) begin
+        // We are not allowed to just deassert valid, so wait until the
+        // current beat has been accepted
+        if (~s_axi_valid || m_axi_ready)
+          enabled <= 1'b0;
+      end else begin
+        // For memory mapped AXI busses we have to complete all pending
+        // burst requests before we can disable the data mover.
+        if (response_id == request_id)
+          enabled <= 1'b0;
+      end
+    end
+  end
+end
+
+always @(posedge clk) begin
+  if (req_ready) begin
+    last_eot <= req_last_burst_length == 'h0; 
+    last_non_eot <= 1'b0;
+    beat_counter <= 'h1;
+  end else if (s_axi_ready && s_axi_valid) begin
+    last_eot <= beat_counter == last_burst_length;
+    last_non_eot <= beat_counter == MAX_BEATS_PER_BURST - 1;
+    beat_counter <= beat_counter + 1;
+  end
+end
+
+always @(posedge clk) begin
+  if (req_ready)
+    last_burst_length <= req_last_burst_length;
+end
+
+always @(posedge clk) begin
+  if (enabled == 1'b0 || resetn == 1'b0) begin
+    active <= 1'b0;
+  end else if (req_valid) begin
+    active <= 1'b1;
+  end else if (last_load) begin
+    active <= 1'b0;
+  end
+end
+
+always @(*)
+begin
+  if ((s_axi_ready && s_axi_valid && last) ||
+    (sync_id && pending_burst))
+    id_next <= inc_id(id);
+  else
+    id_next <= id;
+end
+
+always @(posedge clk) begin
+  if (resetn == 1'b0) begin
+    id <= 'h0;
+  end else begin
+    id <= id_next;
+  end
+end
+
+always @(posedge clk) begin
+  pending_burst <= id_next != request_id;
+end
+
+endmodule
diff --git a/fpga/usrp3/lib/vivado_ipi/axi_dmac/dest_axi_mm.v b/fpga/usrp3/lib/vivado_ipi/axi_dmac/dest_axi_mm.v
new file mode 100644
index 000000000..93f351e3f
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/axi_dmac/dest_axi_mm.v
@@ -0,0 +1,232 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2013(c) Analog Devices, Inc.
+//  Author: Lars-Peter Clausen <lars@metafoo.de>
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+module dmac_dest_mm_axi (
+  input                               m_axi_aclk,
+  input                               m_axi_aresetn,
+
+  input                               req_valid,
+  output                              req_ready,
+  input [31:BYTES_PER_BEAT_WIDTH]   req_address,
+  input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
+  input [BYTES_PER_BEAT_WIDTH-1:0]  req_last_beat_bytes,
+
+  input                               enable,
+  output                              enabled,
+  input                               pause,
+  input                               sync_id,
+  output                              sync_id_ret,
+
+  output                              response_valid,
+  input                               response_ready,
+  output [1:0]                        response_resp,
+  output                              response_resp_eot,
+
+  input  [ID_WIDTH-1:0]             request_id,
+  output [ID_WIDTH-1:0]             response_id,
+
+  output [ID_WIDTH-1:0]             data_id,
+  output [ID_WIDTH-1:0]             address_id,
+  input                               data_eot,
+  input                               address_eot,
+  input                               response_eot,
+
+  input                               fifo_valid,
+  output                              fifo_ready,
+  input [DMA_DATA_WIDTH-1:0]        fifo_data,
+
+  // Write address
+  input                               m_axi_awready,
+  output                              m_axi_awvalid,
+  output [31:0]                       m_axi_awaddr,
+  output [ 7:0]                       m_axi_awlen,
+  output [ 2:0]                       m_axi_awsize,
+  output [ 1:0]                       m_axi_awburst,
+  output [ 2:0]                       m_axi_awprot,
+  output [ 3:0]                       m_axi_awcache,
+
+  // Write data
+  output [DMA_DATA_WIDTH-1:0]     m_axi_wdata,
+  output [(DMA_DATA_WIDTH/8)-1:0] m_axi_wstrb,
+  input                               m_axi_wready,
+  output                              m_axi_wvalid,
+  output                              m_axi_wlast,
+
+  // Write response
+  input                               m_axi_bvalid,
+  input  [ 1:0]                       m_axi_bresp,
+  output                              m_axi_bready
+);
+
+parameter ID_WIDTH = 3;
+parameter DMA_DATA_WIDTH = 64;
+parameter BYTES_PER_BEAT_WIDTH = $clog2(DMA_DATA_WIDTH/8);
+parameter BEATS_PER_BURST_WIDTH = 4;
+
+reg [(DMA_DATA_WIDTH/8)-1:0] wstrb;
+
+wire address_req_valid;
+wire address_req_ready;
+wire data_req_valid;
+wire data_req_ready;
+
+wire address_enabled;
+wire data_enabled;
+assign sync_id_ret = sync_id;
+
+wire _fifo_ready;
+assign fifo_ready = _fifo_ready | ~enabled;
+
+splitter #(
+  .NUM_M(2)
+) i_req_splitter (
+  .clk(m_axi_aclk),
+  .resetn(m_axi_aresetn),
+  .s_valid(req_valid),
+  .s_ready(req_ready),
+  .m_valid({
+    address_req_valid,
+    data_req_valid
+  }),
+  .m_ready({
+    address_req_ready,
+    data_req_ready
+  })
+);
+
+dmac_address_generator #(
+  .ID_WIDTH(ID_WIDTH),
+  .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH),
+  .BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH),
+  .DMA_DATA_WIDTH(DMA_DATA_WIDTH)
+) i_addr_gen (
+  .clk(m_axi_aclk),
+  .resetn(m_axi_aresetn),
+
+  .enable(enable),
+  .enabled(address_enabled),
+  .pause(pause),
+
+  .id(address_id),
+  .request_id(request_id),
+  .sync_id(sync_id),
+
+  .req_valid(address_req_valid),
+  .req_ready(address_req_ready),
+  .req_address(req_address),
+  .req_last_burst_length(req_last_burst_length),
+
+  .eot(address_eot),
+
+  .addr_ready(m_axi_awready),
+  .addr_valid(m_axi_awvalid),
+  .addr(m_axi_awaddr),
+  .len(m_axi_awlen),
+  .size(m_axi_awsize),
+  .burst(m_axi_awburst),
+  .prot(m_axi_awprot),
+  .cache(m_axi_awcache)
+);
+
+dmac_data_mover # (
+  .ID_WIDTH(ID_WIDTH),
+  .DATA_WIDTH(DMA_DATA_WIDTH),
+  .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH)
+) i_data_mover (
+  .clk(m_axi_aclk),
+  .resetn(m_axi_aresetn),
+
+  .enable(address_enabled),
+  .enabled(data_enabled),
+
+  .xfer_req(),
+
+  .request_id(address_id),
+  .response_id(data_id),
+  .sync_id(sync_id),
+  .eot(data_eot),
+
+  .req_valid(data_req_valid),
+  .req_ready(data_req_ready),
+  .req_last_burst_length(req_last_burst_length),
+
+  .s_axi_valid(fifo_valid),
+  .s_axi_ready(_fifo_ready),
+  .s_axi_data(fifo_data),
+  .m_axi_valid(m_axi_wvalid),
+  .m_axi_ready(m_axi_wready),
+  .m_axi_data(m_axi_wdata),
+  .m_axi_last(m_axi_wlast)
+);
+
+always @(*)
+begin
+  if (data_eot & m_axi_wlast) begin
+    wstrb <= (1 << (req_last_beat_bytes + 1)) - 1;
+  end else begin
+    wstrb <= {(DMA_DATA_WIDTH/8){1'b1}};
+  end
+end
+
+assign m_axi_wstrb = wstrb;
+ 
+dmac_response_handler #(
+  .ID_WIDTH(ID_WIDTH)
+) i_response_handler (
+  .clk(m_axi_aclk),
+  .resetn(m_axi_aresetn),
+  .bvalid(m_axi_bvalid),
+  .bready(m_axi_bready),
+  .bresp(m_axi_bresp),
+
+  .enable(data_enabled),
+  .enabled(enabled),
+
+  .id(response_id),
+  .request_id(data_id),
+  .sync_id(sync_id),
+
+  .eot(response_eot),
+
+  .resp_valid(response_valid),
+  .resp_ready(response_ready),
+  .resp_resp(response_resp),
+  .resp_eot(response_resp_eot)
+);
+
+endmodule
diff --git a/fpga/usrp3/lib/vivado_ipi/axi_dmac/dest_axi_stream.v b/fpga/usrp3/lib/vivado_ipi/axi_dmac/dest_axi_stream.v
new file mode 100644
index 000000000..3b3da3397
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/axi_dmac/dest_axi_stream.v
@@ -0,0 +1,154 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2013(c) Analog Devices, Inc.
+//  Author: Lars-Peter Clausen <lars@metafoo.de>
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+module dmac_dest_axi_stream (
+  input s_axis_aclk,
+  input s_axis_aresetn,
+
+  input enable,
+  output enabled,
+  input sync_id,
+  output sync_id_ret,
+        output xfer_req,
+
+  input [ID_WIDTH-1:0] request_id,
+  output [ID_WIDTH-1:0] response_id,
+  output [ID_WIDTH-1:0] data_id,
+  input data_eot,
+  input response_eot,
+
+  input m_axis_ready,
+  output m_axis_valid,
+  output [S_AXIS_DATA_WIDTH-1:0] m_axis_data,
+        output m_axis_last,
+
+  output fifo_ready,
+  input fifo_valid,
+  input [S_AXIS_DATA_WIDTH-1:0] fifo_data,
+
+  input req_valid,
+  output req_ready,
+  input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
+        input req_xlast,
+
+  output response_valid,
+  input response_ready,
+  output response_resp_eot,
+  output [1:0] response_resp
+);
+
+parameter ID_WIDTH = 3;
+parameter S_AXIS_DATA_WIDTH = 64;
+parameter BEATS_PER_BURST_WIDTH = 4;
+
+reg req_xlast_d = 1'b0;
+
+assign sync_id_ret = sync_id;
+wire data_enabled;
+wire _fifo_ready;
+wire m_axis_last_s;
+
+// We are not allowed to just de-assert valid, but if the streaming target does
+// not accept any samples anymore we'd lock up the DMA core. So retain the last
+// beat when disabled until it is accepted. But if in the meantime the DMA core
+// is re-enabled and new data becomes available overwrite the old.
+
+always @(posedge s_axis_aclk) begin
+  if(req_ready == 1'b1) begin
+    req_xlast_d <= req_xlast;
+  end
+end
+
+assign m_axis_last = (req_xlast_d == 1'b1) ? m_axis_last_s : 1'b0;
+
+dmac_data_mover # (
+  .ID_WIDTH(ID_WIDTH),
+  .DATA_WIDTH(S_AXIS_DATA_WIDTH),
+  .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH),
+  .DISABLE_WAIT_FOR_ID(0),
+  .LAST(1)
+) i_data_mover (
+  .clk(s_axis_aclk),
+  .resetn(s_axis_aresetn),
+
+  .enable(enable),
+  .enabled(data_enabled),
+  .sync_id(sync_id),
+        .xfer_req(xfer_req),
+
+  .request_id(request_id),
+  .response_id(data_id),
+  .eot(data_eot),
+
+  .req_valid(req_valid),
+  .req_ready(req_ready),
+  .req_last_burst_length(req_last_burst_length),
+
+  .m_axi_ready(m_axis_ready),
+  .m_axi_valid(m_axis_valid),
+  .m_axi_data(m_axis_data),
+        .m_axi_last(m_axis_last_s),
+  .s_axi_ready(_fifo_ready),
+  .s_axi_valid(fifo_valid),
+  .s_axi_data(fifo_data)
+);
+
+dmac_response_generator # (
+  .ID_WIDTH(ID_WIDTH)
+) i_response_generator (
+  .clk(s_axis_aclk),
+  .resetn(s_axis_aresetn),
+
+  .enable(data_enabled),
+  .enabled(enabled),
+  .sync_id(sync_id),
+
+  .request_id(data_id),
+  .response_id(response_id),
+
+  .eot(response_eot),
+
+  .resp_valid(response_valid),
+  .resp_ready(response_ready),
+  .resp_eot(response_resp_eot),
+  .resp_resp(response_resp)
+);
+
+assign fifo_ready = _fifo_ready | ~enabled;
+
+endmodule
diff --git a/fpga/usrp3/lib/vivado_ipi/axi_dmac/dest_fifo_inf.v b/fpga/usrp3/lib/vivado_ipi/axi_dmac/dest_fifo_inf.v
new file mode 100644
index 000000000..fccac5d7a
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/axi_dmac/dest_fifo_inf.v
@@ -0,0 +1,154 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2013(c) Analog Devices, Inc.
+//  Author: Lars-Peter Clausen <lars@metafoo.de>
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+module dmac_dest_fifo_inf (
+  input clk,
+  input resetn,
+
+  input enable,
+  output enabled,
+  input sync_id,
+  output sync_id_ret,
+
+  input [ID_WIDTH-1:0] request_id,
+  output [ID_WIDTH-1:0] response_id,
+  output [ID_WIDTH-1:0] data_id,
+  input data_eot,
+  input response_eot,
+
+  input en,
+  output [DATA_WIDTH-1:0] dout,
+  output valid,
+  output underflow,
+
+        output xfer_req,
+
+  output fifo_ready,
+  input fifo_valid,
+  input [DATA_WIDTH-1:0] fifo_data,
+
+  input req_valid,
+  output req_ready,
+  input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
+
+  output response_valid,
+  input response_ready,
+  output response_resp_eot,
+  output [1:0] response_resp
+);
+
+parameter ID_WIDTH = 3;
+parameter DATA_WIDTH = 64;
+parameter BEATS_PER_BURST_WIDTH = 4;
+
+assign sync_id_ret = sync_id;
+wire data_enabled;
+
+wire _fifo_ready;
+assign fifo_ready = _fifo_ready | ~enabled;
+
+reg en_d1;
+wire data_ready;
+wire data_valid;
+
+always @(posedge clk)
+begin
+  if (resetn == 1'b0) begin
+    en_d1 <= 1'b0;
+  end else begin
+    en_d1 <= en;
+  end
+end
+
+assign underflow = en_d1 & (~data_valid | ~enable);
+assign data_ready = en_d1 & (data_valid | ~enable);
+assign valid = en_d1 & data_valid & enable;
+
+dmac_data_mover # (
+  .ID_WIDTH(ID_WIDTH),
+  .DATA_WIDTH(DATA_WIDTH),
+  .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH),
+  .DISABLE_WAIT_FOR_ID(0)
+) i_data_mover (
+  .clk(clk),
+  .resetn(resetn),
+
+  .enable(enable),
+  .enabled(data_enabled),
+  .sync_id(sync_id),
+        .xfer_req(xfer_req),
+
+  .request_id(request_id),
+  .response_id(data_id),
+  .eot(data_eot),
+  
+  .req_valid(req_valid),
+  .req_ready(req_ready),
+  .req_last_burst_length(req_last_burst_length),
+
+  .s_axi_ready(_fifo_ready),
+  .s_axi_valid(fifo_valid),
+  .s_axi_data(fifo_data),
+  .m_axi_ready(data_ready),
+  .m_axi_valid(data_valid),
+  .m_axi_data(dout),
+  .m_axi_last()
+);
+
+dmac_response_generator # (
+  .ID_WIDTH(ID_WIDTH)
+) i_response_generator (
+  .clk(clk),
+  .resetn(resetn),
+
+  .enable(data_enabled),
+  .enabled(enabled),
+  .sync_id(sync_id),
+
+  .request_id(data_id),
+  .response_id(response_id),
+
+  .eot(response_eot),
+
+  .resp_valid(response_valid),
+  .resp_ready(response_ready),
+  .resp_eot(response_resp_eot),
+  .resp_resp(response_resp)
+);
+
+endmodule
diff --git a/fpga/usrp3/lib/vivado_ipi/axi_dmac/gui/axi_dmac_v1_0.gtcl b/fpga/usrp3/lib/vivado_ipi/axi_dmac/gui/axi_dmac_v1_0.gtcl
new file mode 100644
index 000000000..f932a6695
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/axi_dmac/gui/axi_dmac_v1_0.gtcl
@@ -0,0 +1,4 @@
+# This file is automatically written.  Do not modify.
+proc gen_USERPARAMETER_SYNC_TRANSFER_START_ENABLEMENT {DMA_TYPE_SRC } {expr $DMA_TYPE_SRC != 0}
+proc gen_USERPARAMETER_DMA_AXI_PROTOCOL_SRC_ENABLEMENT {DMA_TYPE_SRC } {expr $DMA_TYPE_SRC == 0}
+proc gen_USERPARAMETER_DMA_AXI_PROTOCOL_DEST_ENABLEMENT {DMA_TYPE_DEST } {expr $DMA_TYPE_DEST == 0}
diff --git a/fpga/usrp3/lib/vivado_ipi/axi_dmac/inc_id.h b/fpga/usrp3/lib/vivado_ipi/axi_dmac/inc_id.h
new file mode 100644
index 000000000..0aaebde0d
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/axi_dmac/inc_id.h
@@ -0,0 +1,67 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2013(c) Analog Devices, Inc.
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+function [ID_WIDTH-1:0] g2b;
+	input [ID_WIDTH-1:0] g;
+	reg   [ID_WIDTH-1:0] b;
+	integer i;
+	begin
+		b[ID_WIDTH-1] = g[ID_WIDTH-1];
+		for (i = ID_WIDTH - 2; i >= 0; i =  i - 1)
+			b[i] = b[i + 1] ^ g[i];
+		g2b = b;
+	end
+endfunction
+
+function [ID_WIDTH-1:0] b2g;
+	input [ID_WIDTH-1:0] b;
+	reg [ID_WIDTH-1:0] g;
+	integer i;
+	begin
+		g[ID_WIDTH-1] = b[ID_WIDTH-1];
+		for (i = ID_WIDTH - 2; i >= 0; i = i -1)
+				g[i] = b[i + 1] ^ b[i];
+		b2g = g;
+	end
+endfunction
+
+function [ID_WIDTH:0] inc_id;
+input [ID_WIDTH:0] id;
+begin
+	inc_id = b2g(g2b(id) + 1);
+end
+endfunction
diff --git a/fpga/usrp3/lib/vivado_ipi/axi_dmac/request_arb.v b/fpga/usrp3/lib/vivado_ipi/axi_dmac/request_arb.v
new file mode 100644
index 000000000..706d2cedc
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/axi_dmac/request_arb.v
@@ -0,0 +1,1115 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2013(c) Analog Devices, Inc.
+//  Author: Lars-Peter Clausen <lars@metafoo.de>
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+module dmac_request_arb (
+  input req_aclk,
+  input req_aresetn,
+
+  input req_valid,
+  output req_ready,
+  input [31:BYTES_PER_BEAT_WIDTH_DEST] req_dest_address,
+  input [31:BYTES_PER_BEAT_WIDTH_SRC] req_src_address,
+  input [DMA_LENGTH_WIDTH-1:0] req_length,
+        input req_xlast,
+  input req_sync_transfer_start,
+
+  output reg eot,
+
+  input                               enable,
+  input                               pause,
+
+  // Master AXI interface
+  input                               m_dest_axi_aclk,
+  input                               m_dest_axi_aresetn,
+  input                               m_src_axi_aclk,
+  input                               m_src_axi_aresetn,
+
+  // Write address
+  output [31:0]                       m_axi_awaddr,
+  output [ 7:0]                       m_axi_awlen,
+  output [ 2:0]                       m_axi_awsize,
+  output [ 1:0]                       m_axi_awburst,
+  output [ 2:0]                       m_axi_awprot,
+  output [ 3:0]                       m_axi_awcache,
+  output                              m_axi_awvalid,
+  input                               m_axi_awready,
+
+  // Write data
+  output [DMA_DATA_WIDTH_DEST-1:0]     m_axi_wdata,
+  output [(DMA_DATA_WIDTH_DEST/8)-1:0] m_axi_wstrb,
+  input                               m_axi_wready,
+  output                              m_axi_wvalid,
+  output                              m_axi_wlast,
+
+  // Write response
+  input                               m_axi_bvalid,
+  input  [ 1:0]                       m_axi_bresp,
+  output                              m_axi_bready,
+
+  // Read address
+  input                               m_axi_arready,
+  output                              m_axi_arvalid,
+  output [31:0]                       m_axi_araddr,
+  output [ 7:0]                       m_axi_arlen,
+  output [ 2:0]                       m_axi_arsize,
+  output [ 1:0]                       m_axi_arburst,
+  output [ 2:0]                       m_axi_arprot,
+  output [ 3:0]                       m_axi_arcache,
+
+  // Read data and response
+  input  [DMA_DATA_WIDTH_SRC-1:0]   m_axi_rdata,
+  output                              m_axi_rready,
+  input                               m_axi_rvalid,
+  input  [ 1:0]                       m_axi_rresp,
+
+  // Slave streaming AXI interface
+  input                               s_axis_aclk,
+  output                              s_axis_ready,
+  input                               s_axis_valid,
+  input  [DMA_DATA_WIDTH_SRC-1:0]   s_axis_data,
+  input  [0:0]                        s_axis_user,
+  output                              s_axis_xfer_req,
+
+  // Master streaming AXI interface
+  input                               m_axis_aclk,
+  input                               m_axis_ready,
+  output                              m_axis_valid,
+  output [DMA_DATA_WIDTH_DEST-1:0]  m_axis_data,
+        output                              m_axis_last,
+        output                              m_axis_xfer_req,
+
+  // Input FIFO interface
+  input                               fifo_wr_clk,
+  input                               fifo_wr_en,
+  input  [DMA_DATA_WIDTH_SRC-1:0]   fifo_wr_din,
+  output                              fifo_wr_overflow,
+  input                               fifo_wr_sync,
+  output                              fifo_wr_xfer_req,
+
+  // Input FIFO interface
+  input                               fifo_rd_clk,
+  input                               fifo_rd_en,
+  output                              fifo_rd_valid,
+  output [DMA_DATA_WIDTH_DEST-1:0]  fifo_rd_dout,
+  output                              fifo_rd_underflow,
+        output                              fifo_rd_xfer_req,
+
+  output [ID_WIDTH-1:0]        dbg_dest_request_id,
+  output [ID_WIDTH-1:0]        dbg_dest_address_id,
+  output [ID_WIDTH-1:0]        dbg_dest_data_id,
+  output [ID_WIDTH-1:0]        dbg_dest_response_id,
+  output [ID_WIDTH-1:0]        dbg_src_request_id,
+  output [ID_WIDTH-1:0]        dbg_src_address_id,
+  output [ID_WIDTH-1:0]        dbg_src_data_id,
+  output [ID_WIDTH-1:0]        dbg_src_response_id,
+  output [7:0]                        dbg_status
+);
+
+parameter DMA_DATA_WIDTH_SRC = 64;
+parameter DMA_DATA_WIDTH_DEST = 64;
+parameter DMA_LENGTH_WIDTH = 24;
+
+parameter BYTES_PER_BEAT_WIDTH_DEST = $clog2(DMA_DATA_WIDTH_DEST/8);
+parameter BYTES_PER_BEAT_WIDTH_SRC = $clog2(DMA_DATA_WIDTH_SRC/8);
+
+parameter DMA_TYPE_DEST = DMA_TYPE_MM_AXI;
+parameter DMA_TYPE_SRC = DMA_TYPE_FIFO;
+
+parameter ASYNC_CLK_REQ_SRC = 1;
+parameter ASYNC_CLK_SRC_DEST = 1;
+parameter ASYNC_CLK_DEST_REQ = 1;
+
+parameter AXI_SLICE_DEST = 0;
+parameter AXI_SLICE_SRC = 0;
+
+parameter MAX_BYTES_PER_BURST = 128;
+parameter FIFO_SIZE = 4;
+
+parameter ID_WIDTH = $clog2(FIFO_SIZE*2);
+
+localparam DMA_TYPE_MM_AXI = 0;
+localparam DMA_TYPE_STREAM_AXI = 1;
+localparam DMA_TYPE_FIFO = 2;
+
+localparam DMA_ADDRESS_WIDTH_DEST = 32 - BYTES_PER_BEAT_WIDTH_DEST;
+localparam DMA_ADDRESS_WIDTH_SRC = 32 - BYTES_PER_BEAT_WIDTH_SRC;
+
+localparam DMA_DATA_WIDTH = DMA_DATA_WIDTH_SRC < DMA_DATA_WIDTH_DEST ?
+  DMA_DATA_WIDTH_DEST : DMA_DATA_WIDTH_SRC;
+
+
+
+// Bytes per burst is the same for both dest and src, but bytes per beat may
+// differ, so beats per burst may also differ
+
+parameter BYTES_PER_BURST_WIDTH = $clog2(MAX_BYTES_PER_BURST);
+localparam BEATS_PER_BURST_WIDTH_SRC = BYTES_PER_BURST_WIDTH - BYTES_PER_BEAT_WIDTH_SRC;
+localparam BEATS_PER_BURST_WIDTH_DEST = BYTES_PER_BURST_WIDTH - BYTES_PER_BEAT_WIDTH_DEST;
+
+localparam BURSTS_PER_TRANSFER_WIDTH = DMA_LENGTH_WIDTH - BYTES_PER_BURST_WIDTH;
+
+reg [0:2**ID_WIDTH-1] eot_mem;
+wire request_eot;
+
+wire [ID_WIDTH-1:0] request_id;
+wire [ID_WIDTH-1:0] response_id;
+
+wire enabled_src;
+wire enabled_dest;
+wire sync_id;
+wire sync_id_ret_dest;
+wire sync_id_ret_src;
+
+wire dest_enable;
+wire dest_enabled;
+wire dest_pause;
+wire dest_sync_id;
+wire dest_sync_id_ret;
+wire src_enable;
+wire src_enabled;
+wire src_pause;
+wire src_sync_id;
+wire src_sync_id_ret;
+
+wire req_dest_valid;
+wire req_dest_ready;
+wire req_dest_empty;
+wire req_src_valid;
+wire req_src_ready;
+wire req_src_empty;
+
+wire dest_clk;
+wire dest_resetn;
+wire dest_req_valid;
+wire dest_req_ready;
+wire [DMA_ADDRESS_WIDTH_DEST-1:0] dest_req_address;
+wire [BEATS_PER_BURST_WIDTH_DEST-1:0] dest_req_last_burst_length;
+wire [BYTES_PER_BEAT_WIDTH_DEST-1:0] dest_req_last_beat_bytes;
+wire dest_req_xlast;
+
+wire dest_response_valid;
+wire dest_response_ready;
+wire dest_response_empty;
+wire [1:0] dest_response_resp;
+wire dest_response_resp_eot;
+
+wire [ID_WIDTH-1:0] dest_request_id;
+wire [ID_WIDTH-1:0] dest_response_id;
+
+wire dest_valid;
+wire dest_ready;
+wire [DMA_DATA_WIDTH_DEST-1:0] dest_data;
+wire dest_fifo_repacked_valid;
+wire dest_fifo_repacked_ready;
+wire [DMA_DATA_WIDTH_DEST-1:0] dest_fifo_repacked_data;
+wire dest_fifo_valid;
+wire dest_fifo_ready;
+wire [DMA_DATA_WIDTH-1:0] dest_fifo_data;
+
+wire src_clk;
+wire src_resetn;
+wire src_req_valid;
+wire src_req_ready;
+wire [DMA_ADDRESS_WIDTH_SRC-1:0] src_req_address;
+wire [BEATS_PER_BURST_WIDTH_SRC-1:0] src_req_last_burst_length;
+wire src_req_sync_transfer_start;
+
+wire src_response_valid;
+wire src_response_ready;
+wire src_response_empty;
+wire [1:0] src_response_resp;
+
+wire [ID_WIDTH-1:0] src_request_id;
+wire [ID_WIDTH-1:0] src_response_id;
+
+wire src_valid;
+wire src_ready;
+wire [DMA_DATA_WIDTH_SRC-1:0] src_data;
+wire src_fifo_valid;
+wire src_fifo_ready;
+wire [DMA_DATA_WIDTH_SRC-1:0] src_fifo_data;
+wire src_fifo_repacked_valid;
+wire src_fifo_repacked_ready;
+wire [DMA_DATA_WIDTH-1:0] src_fifo_repacked_data;
+wire src_fifo_empty;
+
+wire fifo_empty;
+
+wire response_dest_valid;
+wire response_dest_ready = 1'b1;
+wire [1:0] response_dest_resp;
+wire response_dest_resp_eot;
+
+/* Unused for now
+wire response_src_valid;
+wire response_src_ready = 1'b1;
+wire [1:0] response_src_resp;
+*/
+
+assign dbg_dest_request_id = dest_request_id;
+assign dbg_dest_response_id = dest_response_id;
+assign dbg_src_request_id = src_request_id;
+assign dbg_src_response_id = src_response_id;
+
+assign sync_id = ~enabled_dest && ~enabled_src && request_id != response_id;
+
+reg enabled;
+reg do_enable;
+
+// Enable src and dest if we are in sync
+always @(posedge req_aclk)
+begin
+  if (req_aresetn == 1'b0) begin
+    do_enable <= 1'b0;
+  end else begin
+    if (enable) begin
+      // First make sure we are fully disabled
+      if (~sync_id_ret_dest && ~sync_id_ret_src &&
+        response_id == request_id && ~enabled_dest && ~enabled_src &&
+        req_dest_empty && req_src_empty && fifo_empty)
+        do_enable <= 1'b1;
+    end else begin
+      do_enable <= 1'b0;
+    end
+  end
+end
+
+// Flag enabled once both src and dest are enabled
+always @(posedge req_aclk)
+begin
+  if (req_aresetn == 1'b0) begin
+    enabled <= 1'b0;
+  end else begin
+    if (do_enable == 1'b0)
+      enabled <= 1'b0;
+    else if (enabled_dest && enabled_src)
+      enabled <= 1'b1;
+  end
+end
+
+assign dbg_status = {do_enable, enabled, enabled_dest, enabled_src, fifo_empty,
+  sync_id, sync_id_ret_dest, sync_id_ret_src};
+
+always @(posedge req_aclk)
+begin
+  eot_mem[request_id] <= request_eot;
+end
+
+always @(posedge req_aclk)
+begin
+  if (req_aresetn == 1'b0) begin
+    eot <= 1'b0;
+  end else begin
+    eot <= response_dest_valid & response_dest_ready & response_dest_resp_eot;
+  end
+end
+
+generate if (ASYNC_CLK_REQ_SRC) begin
+
+wire src_async_resetn_source;
+
+if (DMA_TYPE_SRC == DMA_TYPE_MM_AXI) begin
+assign src_async_resetn_source = m_src_axi_aresetn;
+end else begin
+assign src_async_resetn_source = req_aresetn;
+end
+
+reg [2:0] src_reset_shift = 3'b111;
+assign src_resetn = ~src_reset_shift[2];
+
+always @(negedge src_async_resetn_source or posedge src_clk) begin
+  if (src_async_resetn_source == 1'b0)
+    src_reset_shift <= 3'b111;
+  else
+    src_reset_shift <= {src_reset_shift[1:0], 1'b0};
+end
+
+end else begin
+assign src_resetn = req_aresetn;
+end endgenerate
+
+generate if (ASYNC_CLK_DEST_REQ) begin
+wire dest_async_resetn_source;
+
+if (DMA_TYPE_DEST == DMA_TYPE_MM_AXI) begin
+assign dest_async_resetn_source = m_dest_axi_aresetn;
+end else begin
+assign dest_async_resetn_source = req_aresetn;
+end
+
+reg [2:0] dest_reset_shift = 3'b111;
+assign dest_resetn = ~dest_reset_shift[2];
+
+always @(negedge dest_async_resetn_source or posedge dest_clk) begin
+  if (dest_async_resetn_source == 1'b0)
+    dest_reset_shift <= 3'b111;
+  else
+    dest_reset_shift <= {dest_reset_shift[1:0], 1'b0};
+end
+
+end else begin
+assign dest_resetn = req_aresetn;
+end endgenerate
+
+generate if (DMA_TYPE_DEST == DMA_TYPE_MM_AXI) begin
+
+assign dest_clk = m_dest_axi_aclk;
+
+wire [ID_WIDTH-1:0] dest_data_id;
+wire [ID_WIDTH-1:0] dest_address_id;
+wire dest_address_eot = eot_mem[dest_address_id];
+wire dest_data_eot = eot_mem[dest_data_id];
+wire dest_response_eot = eot_mem[dest_response_id];
+
+assign dbg_dest_address_id = dest_address_id;
+assign dbg_dest_data_id = dest_data_id;
+
+dmac_dest_mm_axi #(
+  .ID_WIDTH(ID_WIDTH),
+  .DMA_DATA_WIDTH(DMA_DATA_WIDTH_DEST),
+  .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_DEST),
+  .BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH_DEST)
+) i_dest_dma_mm (
+  .m_axi_aclk(m_dest_axi_aclk),
+  .m_axi_aresetn(dest_resetn),
+
+  .enable(dest_enable),
+  .enabled(dest_enabled),
+  .pause(dest_pause),
+
+  .req_valid(dest_req_valid),
+  .req_ready(dest_req_ready),
+  .req_address(dest_req_address),
+  .req_last_burst_length(dest_req_last_burst_length),
+  .req_last_beat_bytes(dest_req_last_beat_bytes),
+
+  .response_valid(dest_response_valid),
+  .response_ready(dest_response_ready),
+  .response_resp(dest_response_resp),
+  .response_resp_eot(dest_response_resp_eot),
+
+  .request_id(dest_request_id),
+  .response_id(dest_response_id),
+  .sync_id(dest_sync_id),
+  .sync_id_ret(dest_sync_id_ret),
+
+  .data_id(dest_data_id),
+  .address_id(dest_address_id),
+
+  .address_eot(dest_address_eot),
+  .data_eot(dest_data_eot),
+  .response_eot(dest_response_eot),
+
+  .fifo_valid(dest_valid),
+  .fifo_ready(dest_ready),
+  .fifo_data(dest_data),
+
+  .m_axi_awready(m_axi_awready),
+  .m_axi_awvalid(m_axi_awvalid),
+  .m_axi_awaddr(m_axi_awaddr),
+  .m_axi_awlen(m_axi_awlen),
+  .m_axi_awsize(m_axi_awsize),
+  .m_axi_awburst(m_axi_awburst),
+  .m_axi_awprot(m_axi_awprot),
+  .m_axi_awcache(m_axi_awcache),
+  .m_axi_wready(m_axi_wready),
+  .m_axi_wvalid(m_axi_wvalid),
+  .m_axi_wdata(m_axi_wdata),
+  .m_axi_wstrb(m_axi_wstrb),
+  .m_axi_wlast(m_axi_wlast),
+
+  .m_axi_bvalid(m_axi_bvalid),
+  .m_axi_bresp(m_axi_bresp),
+  .m_axi_bready(m_axi_bready)
+);
+
+end else begin
+
+assign m_axi_awvalid = 1'b0;
+assign m_axi_awaddr = 'h00;
+assign m_axi_awlen = 'h00;
+assign m_axi_awsize = 'h00;
+assign m_axi_awburst = 'h00;
+assign m_axi_awprot = 'h00;
+assign m_axi_awcache = 'h00;
+
+assign m_axi_wvalid = 1'b0;
+assign m_axi_wdata = 'h00;
+assign m_axi_wstrb = 'h00;
+assign m_axi_wlast = 1'b0;
+
+assign m_axi_bready = 1'b0;
+
+end
+
+if (DMA_TYPE_DEST == DMA_TYPE_STREAM_AXI) begin
+
+assign dest_clk = m_axis_aclk;
+
+wire [ID_WIDTH-1:0] data_id;
+
+wire data_eot = eot_mem[data_id];
+wire response_eot = eot_mem[dest_response_id];
+
+assign dbg_dest_address_id = 'h00;
+assign dbg_dest_data_id = data_id;
+
+dmac_dest_axi_stream #(
+  .ID_WIDTH(ID_WIDTH),
+  .S_AXIS_DATA_WIDTH(DMA_DATA_WIDTH_DEST),
+  .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_DEST)
+) i_dest_dma_stream (
+  .s_axis_aclk(m_axis_aclk),
+  .s_axis_aresetn(dest_resetn),
+
+  .enable(dest_enable),
+  .enabled(dest_enabled),
+
+  .req_valid(dest_req_valid),
+  .req_ready(dest_req_ready),
+  .req_last_burst_length(dest_req_last_burst_length),
+        .req_xlast(dest_req_xlast),
+
+  .response_valid(dest_response_valid),
+  .response_ready(dest_response_ready),
+  .response_resp(dest_response_resp),
+  .response_resp_eot(dest_response_resp_eot),
+
+  .request_id(dest_request_id),
+  .response_id(dest_response_id),
+  .data_id(data_id),
+  .sync_id(dest_sync_id),
+  .sync_id_ret(dest_sync_id_ret),
+        .xfer_req(m_axis_xfer_req),
+
+  .data_eot(data_eot),
+  .response_eot(response_eot),
+
+  .fifo_valid(dest_valid),
+  .fifo_ready(dest_ready),
+  .fifo_data(dest_data),
+
+  .m_axis_valid(m_axis_valid),
+  .m_axis_ready(m_axis_ready),
+  .m_axis_data(m_axis_data),
+        .m_axis_last(m_axis_last)
+);
+
+end else begin
+
+assign m_axis_valid = 1'b0;
+assign m_axis_last = 1'b0;
+assign m_axis_xfer_req = 1'b0;
+assign m_axis_data = 'h00;
+
+end
+
+if (DMA_TYPE_DEST == DMA_TYPE_FIFO) begin
+
+assign dest_clk = fifo_rd_clk;
+
+wire [ID_WIDTH-1:0] data_id;
+
+wire data_eot = eot_mem[data_id];
+wire response_eot = eot_mem[dest_response_id];
+
+assign dbg_dest_address_id = 'h00;
+assign dbg_dest_data_id = data_id;
+
+dmac_dest_fifo_inf #(
+  .ID_WIDTH(ID_WIDTH),
+  .DATA_WIDTH(DMA_DATA_WIDTH_DEST),
+  .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_DEST)
+) i_dest_dma_fifo (
+  .clk(fifo_rd_clk),
+  .resetn(dest_resetn),
+
+  .enable(dest_enable),
+  .enabled(dest_enabled),
+
+  .req_valid(dest_req_valid),
+  .req_ready(dest_req_ready),
+  .req_last_burst_length(dest_req_last_burst_length),
+
+  .response_valid(dest_response_valid),
+  .response_ready(dest_response_ready),
+  .response_resp(dest_response_resp),
+  .response_resp_eot(dest_response_resp_eot),
+
+  .request_id(dest_request_id),
+  .response_id(dest_response_id),
+  .data_id(data_id),
+  .sync_id(dest_sync_id),
+  .sync_id_ret(dest_sync_id_ret),
+
+  .data_eot(data_eot),
+  .response_eot(response_eot),
+
+  .fifo_valid(dest_valid),
+  .fifo_ready(dest_ready),
+  .fifo_data(dest_data),
+
+  .en(fifo_rd_en),
+  .valid(fifo_rd_valid),
+  .dout(fifo_rd_dout),
+  .underflow(fifo_rd_underflow),
+        .xfer_req(fifo_rd_xfer_req)
+);
+
+end else begin
+
+assign fifo_rd_valid = 1'b0;
+assign fifo_rd_dout = 'h0;
+assign fifo_rd_underflow = 1'b0;
+assign fifo_rd_xfer_req = 1'b0;
+
+end endgenerate
+
+generate if (DMA_TYPE_SRC == DMA_TYPE_MM_AXI) begin
+
+assign src_clk = m_src_axi_aclk;
+
+wire [ID_WIDTH-1:0] src_data_id;
+wire [ID_WIDTH-1:0] src_address_id;
+wire src_address_eot = eot_mem[src_address_id];
+wire src_data_eot = eot_mem[src_data_id];
+
+assign dbg_src_address_id = src_address_id;
+assign dbg_src_data_id = src_data_id;
+
+dmac_src_mm_axi #(
+  .ID_WIDTH(ID_WIDTH),
+  .DMA_DATA_WIDTH(DMA_DATA_WIDTH_SRC),
+  .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC),
+  .BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH_SRC)
+) i_src_dma_mm (
+  .m_axi_aclk(m_src_axi_aclk),
+  .m_axi_aresetn(src_resetn),
+
+  .pause(src_pause),
+  .enable(src_enable),
+  .enabled(src_enabled),
+  .sync_id(src_sync_id),
+  .sync_id_ret(src_sync_id_ret),
+
+  .req_valid(src_req_valid),
+  .req_ready(src_req_ready),
+  .req_address(src_req_address),
+  .req_last_burst_length(src_req_last_burst_length),
+
+  .response_valid(src_response_valid),
+  .response_ready(src_response_ready),
+  .response_resp(src_response_resp),
+
+  .request_id(src_request_id),
+  .response_id(src_response_id),
+  .address_id(src_address_id),
+  .data_id(src_data_id),
+
+  .address_eot(src_address_eot),
+  .data_eot(src_data_eot),
+
+  .fifo_valid(src_valid),
+  .fifo_ready(src_ready),
+  .fifo_data(src_data),
+
+  .m_axi_arready(m_axi_arready),
+  .m_axi_arvalid(m_axi_arvalid),
+  .m_axi_araddr(m_axi_araddr),
+  .m_axi_arlen(m_axi_arlen),
+  .m_axi_arsize(m_axi_arsize),
+  .m_axi_arburst(m_axi_arburst),
+  .m_axi_arprot(m_axi_arprot),
+  .m_axi_arcache(m_axi_arcache),
+
+  .m_axi_rready(m_axi_rready),
+  .m_axi_rvalid(m_axi_rvalid),
+  .m_axi_rdata(m_axi_rdata),
+  .m_axi_rresp(m_axi_rresp)
+);
+
+end else begin
+
+assign m_axi_arvalid = 1'b0;
+assign m_axi_araddr = 'h00;
+assign m_axi_arlen = 'h00;
+assign m_axi_arsize = 'h00;
+assign m_axi_arburst = 'h00;
+assign m_axi_arcache = 'h00;
+assign m_axi_arprot = 'h00;
+assign m_axi_rready = 1'b0;
+
+end
+
+if (DMA_TYPE_SRC == DMA_TYPE_STREAM_AXI) begin
+
+assign src_clk = s_axis_aclk;
+
+wire src_eot = eot_mem[src_response_id];
+
+assign dbg_src_address_id = 'h00;
+assign dbg_src_data_id = 'h00;
+
+/* TODO */
+assign src_response_valid = 1'b0;
+assign src_response_resp = 2'b0;
+
+dmac_src_axi_stream #(
+  .ID_WIDTH(ID_WIDTH),
+  .S_AXIS_DATA_WIDTH(DMA_DATA_WIDTH_SRC),
+  .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC)
+) i_src_dma_stream (
+  .s_axis_aclk(s_axis_aclk),
+  .s_axis_aresetn(src_resetn),
+
+  .enable(src_enable),
+  .enabled(src_enabled),
+  .sync_id(src_sync_id),
+  .sync_id_ret(src_sync_id_ret),
+
+  .req_valid(src_req_valid),
+  .req_ready(src_req_ready),
+  .req_last_burst_length(src_req_last_burst_length),
+  .req_sync_transfer_start(src_req_sync_transfer_start),
+
+  .request_id(src_request_id),
+  .response_id(src_response_id),
+
+  .eot(src_eot),
+
+  .fifo_valid(src_valid),
+  .fifo_ready(src_ready),
+  .fifo_data(src_data),
+
+  .s_axis_valid(s_axis_valid),
+  .s_axis_ready(s_axis_ready),
+  .s_axis_data(s_axis_data),
+  .s_axis_user(s_axis_user),
+  .s_axis_xfer_req(s_axis_xfer_req)
+);
+
+end else begin
+
+assign s_axis_ready = 1'b0;
+assign s_axis_xfer_req = 1'b0;
+
+end
+
+if (DMA_TYPE_SRC == DMA_TYPE_FIFO) begin
+
+assign src_clk = fifo_wr_clk;
+
+wire src_eot = eot_mem[src_response_id];
+
+assign dbg_src_address_id = 'h00;
+assign dbg_src_data_id = 'h00;
+
+/* TODO */
+assign src_response_valid = 1'b0;
+assign src_response_resp = 2'b0;
+
+dmac_src_fifo_inf #(
+  .ID_WIDTH(ID_WIDTH),
+  .DATA_WIDTH(DMA_DATA_WIDTH_SRC),
+  .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC)
+) i_src_dma_fifo (
+  .clk(fifo_wr_clk),
+  .resetn(src_resetn),
+
+  .enable(src_enable),
+  .enabled(src_enabled),
+  .sync_id(src_sync_id),
+  .sync_id_ret(src_sync_id_ret),
+
+  .req_valid(src_req_valid),
+  .req_ready(src_req_ready),
+  .req_last_burst_length(src_req_last_burst_length),
+  .req_sync_transfer_start(src_req_sync_transfer_start),
+
+  .request_id(src_request_id),
+  .response_id(src_response_id),
+
+  .eot(src_eot),
+
+  .fifo_valid(src_valid),
+  .fifo_ready(src_ready),
+  .fifo_data(src_data),
+
+  .en(fifo_wr_en),
+  .din(fifo_wr_din),
+  .overflow(fifo_wr_overflow),
+  .sync(fifo_wr_sync),
+  .xfer_req(fifo_wr_xfer_req)
+);
+
+end else begin
+
+assign fifo_wr_overflow = 1'b0;
+assign fifo_wr_xfer_req = 1'b0;
+
+end endgenerate
+
+sync_bits #(
+  .NUM_OF_BITS(ID_WIDTH),
+  .ASYNC_CLK(ASYNC_CLK_REQ_SRC)
+) i_sync_src_request_id (
+  .out_clk(src_clk),
+  .out_resetn(src_resetn),
+  .in(request_id),
+  .out(src_request_id)
+);
+
+sync_bits #(
+  .NUM_OF_BITS(ID_WIDTH),
+  .ASYNC_CLK(ASYNC_CLK_SRC_DEST)
+) i_sync_dest_request_id (
+  .out_clk(dest_clk),
+  .out_resetn(dest_resetn),
+  .in(src_response_id),
+  .out(dest_request_id)
+);
+
+sync_bits #(
+  .NUM_OF_BITS(ID_WIDTH),
+  .ASYNC_CLK(ASYNC_CLK_DEST_REQ)
+) i_sync_req_response_id (
+  .out_clk(req_aclk),
+  .out_resetn(req_aresetn),
+  .in(dest_response_id),
+  .out(response_id)
+);
+
+axi_register_slice #(
+  .DATA_WIDTH(DMA_DATA_WIDTH_SRC),
+  .FORWARD_REGISTERED(AXI_SLICE_SRC),
+  .BACKWARD_REGISTERED(AXI_SLICE_SRC)
+) i_src_slice (
+  .clk(src_clk),
+  .resetn(src_resetn),
+  .s_axi_valid(src_valid),
+  .s_axi_ready(src_ready),
+  .s_axi_data(src_data),
+  .m_axi_valid(src_fifo_valid),
+  .m_axi_ready(src_fifo_ready),
+  .m_axi_data(src_fifo_data)
+);
+
+util_axis_resize #(
+  .SLAVE_DATA_WIDTH(DMA_DATA_WIDTH_SRC),
+  .MASTER_DATA_WIDTH(DMA_DATA_WIDTH)
+) i_src_repack (
+  .clk(src_clk),
+  .resetn(src_resetn & src_enable),
+  .s_valid(src_fifo_valid),
+  .s_ready(src_fifo_ready),
+  .s_data(src_fifo_data),
+  .m_valid(src_fifo_repacked_valid),
+  .m_ready(src_fifo_repacked_ready),
+  .m_data(src_fifo_repacked_data)
+);
+
+util_axis_fifo #(
+  .DATA_WIDTH(DMA_DATA_WIDTH),
+  .ADDRESS_WIDTH($clog2(MAX_BYTES_PER_BURST / (DMA_DATA_WIDTH / 8) * FIFO_SIZE)),
+  .ASYNC_CLK(ASYNC_CLK_SRC_DEST)
+) i_fifo (
+  .s_axis_aclk(src_clk),
+  .s_axis_aresetn(src_resetn),
+  .s_axis_valid(src_fifo_repacked_valid),
+  .s_axis_ready(src_fifo_repacked_ready),
+  .s_axis_data(src_fifo_repacked_data),
+  .s_axis_empty(src_fifo_empty),
+  .s_axis_room(),
+
+  .m_axis_aclk(dest_clk),
+  .m_axis_aresetn(dest_resetn),
+  .m_axis_valid(dest_fifo_valid),
+  .m_axis_ready(dest_fifo_ready),
+  .m_axis_data(dest_fifo_data),
+  .m_axis_level()
+);
+
+util_axis_resize #(
+  .SLAVE_DATA_WIDTH(DMA_DATA_WIDTH),
+  .MASTER_DATA_WIDTH(DMA_DATA_WIDTH_DEST)
+) i_dest_repack (
+  .clk(dest_clk),
+  .resetn(dest_resetn & dest_enable),
+  .s_valid(dest_fifo_valid),
+  .s_ready(dest_fifo_ready),
+  .s_data(dest_fifo_data),
+  .m_valid(dest_fifo_repacked_valid),
+  .m_ready(dest_fifo_repacked_ready),
+  .m_data(dest_fifo_repacked_data)
+);
+
+wire _dest_valid;
+wire _dest_ready;
+wire [DMA_DATA_WIDTH_DEST-1:0] _dest_data;
+
+axi_register_slice #(
+  .DATA_WIDTH(DMA_DATA_WIDTH_DEST),
+  .FORWARD_REGISTERED(AXI_SLICE_DEST)
+) i_dest_slice2 (
+  .clk(dest_clk),
+  .resetn(dest_resetn),
+  .s_axi_valid(dest_fifo_repacked_valid),
+  .s_axi_ready(dest_fifo_repacked_ready),
+  .s_axi_data(dest_fifo_repacked_data),
+  .m_axi_valid(_dest_valid),
+  .m_axi_ready(_dest_ready),
+  .m_axi_data(_dest_data)
+);
+
+axi_register_slice #(
+  .DATA_WIDTH(DMA_DATA_WIDTH_DEST),
+  .FORWARD_REGISTERED(AXI_SLICE_DEST),
+  .BACKWARD_REGISTERED(AXI_SLICE_DEST)
+) i_dest_slice (
+  .clk(dest_clk),
+  .resetn(dest_resetn),
+  .s_axi_valid(_dest_valid),
+  .s_axi_ready(_dest_ready),
+  .s_axi_data(_dest_data),
+  .m_axi_valid(dest_valid),
+  .m_axi_ready(dest_ready),
+  .m_axi_data(dest_data)
+);
+
+
+// We do not accept any requests until all components are enabled
+reg _req_valid = 1'b0;
+wire _req_ready;
+
+always @(posedge req_aclk)
+begin
+  if (req_aresetn == 1'b0) begin
+    _req_valid <= 1'b0;
+  end else begin
+    if (_req_valid == 1'b1 && _req_ready == 1'b1) begin
+      _req_valid <= 1'b0;
+    end else if (req_valid == 1'b1 && enabled == 1'b1) begin
+      _req_valid <= 1'b1;
+    end
+  end
+end
+
+assign req_ready = _req_ready & _req_valid & enable;
+
+splitter #(
+  .NUM_M(3)
+) i_req_splitter (
+  .clk(req_aclk),
+  .resetn(req_aresetn),
+  .s_valid(_req_valid),
+  .s_ready(_req_ready),
+  .m_valid({
+    req_gen_valid,
+    req_dest_valid,
+    req_src_valid
+  }),
+  .m_ready({
+    req_gen_ready,
+    req_dest_ready,
+    req_src_ready
+  })
+);
+
+util_axis_fifo #(
+  .DATA_WIDTH(DMA_ADDRESS_WIDTH_DEST + BEATS_PER_BURST_WIDTH_DEST + BYTES_PER_BEAT_WIDTH_DEST + 1),
+  .ADDRESS_WIDTH(0),
+  .ASYNC_CLK(ASYNC_CLK_DEST_REQ)
+) i_dest_req_fifo (
+  .s_axis_aclk(req_aclk),
+  .s_axis_aresetn(req_aresetn),
+  .s_axis_valid(req_dest_valid),
+  .s_axis_ready(req_dest_ready),
+  .s_axis_empty(req_dest_empty),
+  .s_axis_data({
+    req_dest_address,
+    req_length[BYTES_PER_BURST_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST],
+    req_length[BYTES_PER_BEAT_WIDTH_DEST-1:0],
+                req_xlast
+  }),
+  .s_axis_room(),
+
+  .m_axis_aclk(dest_clk),
+  .m_axis_aresetn(dest_resetn),
+  .m_axis_valid(dest_req_valid),
+  .m_axis_ready(dest_req_ready),
+  .m_axis_data({
+    dest_req_address,
+    dest_req_last_burst_length,
+    dest_req_last_beat_bytes,
+                dest_req_xlast
+  }),
+  .m_axis_level()
+);
+
+util_axis_fifo #(
+  .DATA_WIDTH(DMA_ADDRESS_WIDTH_SRC + BEATS_PER_BURST_WIDTH_SRC + 1),
+  .ADDRESS_WIDTH(0),
+  .ASYNC_CLK(ASYNC_CLK_REQ_SRC)
+) i_src_req_fifo (
+  .s_axis_aclk(req_aclk),
+  .s_axis_aresetn(req_aresetn),
+  .s_axis_valid(req_src_valid),
+  .s_axis_ready(req_src_ready),
+  .s_axis_empty(req_src_empty),
+  .s_axis_data({
+    req_src_address,
+    req_length[BYTES_PER_BURST_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC],
+    req_sync_transfer_start
+  }),
+  .s_axis_room(),
+
+  .m_axis_aclk(src_clk),
+  .m_axis_aresetn(src_resetn),
+  .m_axis_valid(src_req_valid),
+  .m_axis_ready(src_req_ready),
+  .m_axis_data({
+    src_req_address,
+    src_req_last_burst_length,
+    src_req_sync_transfer_start
+  }),
+  .m_axis_level()
+);
+
+util_axis_fifo #(
+  .DATA_WIDTH(1),
+  .ADDRESS_WIDTH(0),
+  .ASYNC_CLK(ASYNC_CLK_DEST_REQ)
+) i_dest_response_fifo (
+  .s_axis_aclk(dest_clk),
+  .s_axis_aresetn(dest_resetn),
+  .s_axis_valid(dest_response_valid),
+  .s_axis_ready(dest_response_ready),
+  .s_axis_empty(dest_response_empty),
+  .s_axis_data(dest_response_resp_eot),
+  .s_axis_room(),
+
+  .m_axis_aclk(req_aclk),
+  .m_axis_aresetn(req_aresetn),
+  .m_axis_valid(response_dest_valid),
+  .m_axis_ready(response_dest_ready),
+  .m_axis_data(response_dest_resp_eot),
+  .m_axis_level()
+);
+
+/* Unused for now
+util_axis_fifo #(
+  .DATA_WIDTH(2),
+  .ADDRESS_WIDTH(0),
+  .ASYNC_CLK(ASYNC_CLK_REQ_SRC)
+) i_src_response_fifo (
+  .s_axis_aclk(src_clk),
+  .s_axis_aresetn(src_resetn),
+  .s_axis_valid(src_response_valid),
+  .s_axis_ready(src_response_ready),
+  .s_axis_empty(src_response_empty),
+  .s_axis_data(src_response_resp),
+  .m_axis_aclk(req_aclk),
+  .m_axis_aresetn(req_aresetn),
+  .m_axis_valid(response_src_valid),
+  .m_axis_ready(response_src_ready),
+  .m_axis_data(response_src_resp)
+);*/
+assign src_response_empty = 1'b1;
+assign src_response_ready = 1'b1;
+
+dmac_request_generator #(
+  .ID_WIDTH(ID_WIDTH),
+  .BURSTS_PER_TRANSFER_WIDTH(BURSTS_PER_TRANSFER_WIDTH)
+) i_req_gen (
+  .req_aclk(req_aclk),
+  .req_aresetn(req_aresetn),
+
+  .request_id(request_id),
+  .response_id(response_id),
+
+  .req_valid(req_gen_valid),
+  .req_ready(req_gen_ready),
+  .req_burst_count(req_length[DMA_LENGTH_WIDTH-1:BYTES_PER_BURST_WIDTH]),
+
+  .enable(do_enable),
+  .pause(pause),
+
+  .eot(request_eot)
+);
+
+sync_bits #(
+  .NUM_OF_BITS(3),
+  .ASYNC_CLK(ASYNC_CLK_DEST_REQ)
+) i_sync_control_dest (
+  .out_clk(dest_clk),
+  .out_resetn(dest_resetn),
+  .in({do_enable, pause, sync_id}),
+  .out({dest_enable, dest_pause, dest_sync_id})
+);
+
+sync_bits #(
+  .NUM_OF_BITS(2),
+  .ASYNC_CLK(ASYNC_CLK_DEST_REQ)
+) i_sync_status_dest (
+  .out_clk(req_aclk),
+  .out_resetn(req_aresetn),
+  .in({dest_enabled | ~dest_response_empty, dest_sync_id_ret}),
+  .out({enabled_dest, sync_id_ret_dest})
+);
+
+sync_bits #(
+  .NUM_OF_BITS(3),
+  .ASYNC_CLK(ASYNC_CLK_REQ_SRC)
+) i_sync_control_src (
+  .out_clk(src_clk),
+  .out_resetn(src_resetn),
+  .in({do_enable, pause, sync_id}),
+  .out({src_enable, src_pause, src_sync_id})
+);
+
+sync_bits #(
+  .NUM_OF_BITS(3),
+  .ASYNC_CLK(ASYNC_CLK_REQ_SRC)
+) i_sync_status_src (
+  .out_clk(req_aclk),
+  .out_resetn(req_aresetn),
+  .in({src_enabled | ~src_response_empty, src_sync_id_ret, src_fifo_empty}),
+  .out({enabled_src, sync_id_ret_src, fifo_empty})
+);
+
+endmodule
diff --git a/fpga/usrp3/lib/vivado_ipi/axi_dmac/request_generator.v b/fpga/usrp3/lib/vivado_ipi/axi_dmac/request_generator.v
new file mode 100644
index 000000000..d56a5e8c5
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/axi_dmac/request_generator.v
@@ -0,0 +1,98 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2013(c) Analog Devices, Inc.
+//  Author: Lars-Peter Clausen <lars@metafoo.de>
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+module dmac_request_generator (
+  input req_aclk,
+  input req_aresetn,
+
+  output [ID_WIDTH-1:0] request_id,
+  input [ID_WIDTH-1:0] response_id,
+
+  input req_valid,
+  output reg req_ready,
+  input [BURSTS_PER_TRANSFER_WIDTH-1:0] req_burst_count,
+
+  input enable,
+  input pause,
+
+  output eot
+);
+
+parameter ID_WIDTH = 3;
+parameter BURSTS_PER_TRANSFER_WIDTH = 17;
+
+`include "inc_id.h"
+
+/*
+ * Here we only need to count the number of bursts, which means we can ignore
+ * the lower bits of the byte count. The last last burst may not contain the
+ * maximum number of bytes, but the address_generator and data_mover will take
+ * care that only the requested ammount of bytes is transfered.
+ */
+
+reg [BURSTS_PER_TRANSFER_WIDTH-1:0] burst_count = 'h00;
+reg [ID_WIDTH-1:0] id;
+wire [ID_WIDTH-1:0] id_next = inc_id(id);
+
+assign eot = burst_count == 'h00;
+assign request_id = id;
+
+always @(posedge req_aclk)
+begin
+  if (req_aresetn == 1'b0) begin
+    burst_count <= 'h00;
+    id <= 'h0;
+    req_ready <= 1'b1;
+  end else if (enable == 1'b0) begin
+    req_ready <= 1'b1;
+  end else begin
+    if (req_ready) begin
+      if (req_valid && enable) begin
+        burst_count <= req_burst_count;
+        req_ready <= 1'b0;
+      end
+    end else if (response_id != id_next && ~pause) begin
+      if (eot)
+        req_ready <= 1'b1;
+      burst_count <= burst_count - 1'b1;
+      id <= id_next;
+    end
+  end
+end
+
+endmodule
diff --git a/fpga/usrp3/lib/vivado_ipi/axi_dmac/resp.h b/fpga/usrp3/lib/vivado_ipi/axi_dmac/resp.h
new file mode 100644
index 000000000..a3a738357
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/axi_dmac/resp.h
@@ -0,0 +1,4 @@
+localparam RESP_OKAY = 2'b00;
+localparam RESP_EXOKAY = 2'b01;
+localparam RESP_SLVERR = 2'b10;
+localparam RESP_DECERR = 2'b11;
diff --git a/fpga/usrp3/lib/vivado_ipi/axi_dmac/response_generator.v b/fpga/usrp3/lib/vivado_ipi/axi_dmac/response_generator.v
new file mode 100644
index 000000000..61104d36f
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/axi_dmac/response_generator.v
@@ -0,0 +1,90 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2013(c) Analog Devices, Inc.
+//  Author: Lars-Peter Clausen <lars@metafoo.de>
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+module dmac_response_generator (
+  input clk,
+  input resetn,
+
+  input enable,
+  output reg enabled,
+
+  input [ID_WIDTH-1:0] request_id,
+  output reg [ID_WIDTH-1:0] response_id,
+  input sync_id,
+
+  input eot,
+
+  output resp_valid,
+  input resp_ready,
+  output resp_eot,
+  output [1:0] resp_resp
+);
+
+parameter ID_WIDTH = 3;
+
+`include "inc_id.h"
+`include "resp.h"
+
+assign resp_resp = RESP_OKAY;
+assign resp_eot = eot;
+
+assign resp_valid = request_id != response_id && enabled;
+
+// We have to wait for all responses before we can disable the response handler
+always @(posedge clk) begin
+  if (resetn == 1'b0) begin
+    enabled <= 1'b0;
+  end else begin
+    if (enable)
+      enabled <= 1'b1;
+    else if (request_id == response_id)
+      enabled <= 1'b0;
+  end
+end
+
+always @(posedge clk) begin
+  if (resetn == 1'b0) begin
+    response_id <= 'h0;
+  end else begin
+    if ((resp_valid && resp_ready) ||
+      (sync_id && response_id != request_id))
+      response_id <= inc_id(response_id);
+  end
+end
+
+endmodule
diff --git a/fpga/usrp3/lib/vivado_ipi/axi_dmac/response_handler.v b/fpga/usrp3/lib/vivado_ipi/axi_dmac/response_handler.v
new file mode 100644
index 000000000..cd64ba7e7
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/axi_dmac/response_handler.v
@@ -0,0 +1,97 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2013(c) Analog Devices, Inc.
+//  Author: Lars-Peter Clausen <lars@metafoo.de>
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+module dmac_response_handler (
+  input clk,
+  input resetn,
+
+  input bvalid,
+  output bready,
+  input [1:0] bresp,
+
+  output reg [ID_WIDTH-1:0] id,
+  input [ID_WIDTH-1:0] request_id,
+  input sync_id,
+
+  input enable,
+  output reg enabled,
+
+  input eot,
+
+  output resp_valid,
+  input resp_ready,
+  output resp_eot,
+  output [1:0] resp_resp
+);
+
+parameter ID_WIDTH = 3;
+
+`include "resp.h"
+`include "inc_id.h"
+
+assign resp_resp = bresp;
+assign resp_eot = eot;
+
+wire active = id != request_id && enabled;
+
+assign bready = active && resp_ready;
+assign resp_valid = active && bvalid;
+
+// We have to wait for all responses before we can disable the response handler
+always @(posedge clk) begin
+  if (resetn == 1'b0) begin
+    enabled <= 1'b0;
+  end else begin
+  if (enable)
+      enabled <= 1'b1;
+  else if (request_id == id)
+      enabled <= 1'b0;
+  end
+end
+
+always @(posedge clk) begin
+  if (resetn == 1'b0) begin
+    id <= 'h0;
+  end else begin
+    if ((bready && bvalid) ||
+        (sync_id && id != request_id))
+      id <= inc_id(id);
+  end
+end
+
+endmodule
diff --git a/fpga/usrp3/lib/vivado_ipi/axi_dmac/splitter.v b/fpga/usrp3/lib/vivado_ipi/axi_dmac/splitter.v
new file mode 100644
index 000000000..4fee19f95
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/axi_dmac/splitter.v
@@ -0,0 +1,69 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2013(c) Analog Devices, Inc.
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+
+module splitter (
+  input clk,
+  input resetn,
+
+  input s_valid,
+  output s_ready,
+
+  output [NUM_M-1:0] m_valid,
+  input [NUM_M-1:0] m_ready
+);
+
+parameter NUM_M = 2;
+
+reg [NUM_M-1:0] acked;
+
+assign s_ready = &(m_ready | acked);
+assign m_valid = s_valid ? ~acked : {NUM_M{1'b0}};
+
+always @(posedge clk)
+begin
+  if (resetn == 1'b0) begin
+    acked <= {NUM_M{1'b0}};
+  end else begin
+    if (s_valid & s_ready)
+      acked <= {NUM_M{1'b0}};
+    else
+      acked <= acked | (m_ready & m_valid);
+  end
+end
+
+endmodule
diff --git a/fpga/usrp3/lib/vivado_ipi/axi_dmac/src_axi_mm.v b/fpga/usrp3/lib/vivado_ipi/axi_dmac/src_axi_mm.v
new file mode 100644
index 000000000..c1a06b0d8
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/axi_dmac/src_axi_mm.v
@@ -0,0 +1,199 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2013(c) Analog Devices, Inc.
+//  Author: Lars-Peter Clausen <lars@metafoo.de>
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+module dmac_src_mm_axi (
+  input                           m_axi_aclk,
+  input                           m_axi_aresetn,
+
+  input                           req_valid,
+  output                          req_ready,
+  input [31:BYTES_PER_BEAT_WIDTH]    req_address,
+  input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
+
+  input                           enable,
+  output                          enabled,
+  input                           pause,
+  input                           sync_id,
+  output                          sync_id_ret,
+
+  output                          response_valid,
+  input                           response_ready,
+  output [1:0]                    response_resp,
+
+  input  [ID_WIDTH-1:0]         request_id,
+  output [ID_WIDTH-1:0]         response_id,
+
+  output [ID_WIDTH-1:0]         data_id,
+  output [ID_WIDTH-1:0]         address_id,
+  input                           data_eot,
+  input                           address_eot,
+
+  output                          fifo_valid,
+  input                           fifo_ready,
+  output [DMA_DATA_WIDTH-1:0]   fifo_data,
+
+  // Read address
+  input                            m_axi_arready,
+  output                           m_axi_arvalid,
+  output [31:0]                    m_axi_araddr,
+  output [ 7:0]                    m_axi_arlen,
+  output [ 2:0]                    m_axi_arsize,
+  output [ 1:0]                    m_axi_arburst,
+  output [ 2:0]                    m_axi_arprot,
+  output [ 3:0]                    m_axi_arcache,
+
+  // Read data and response
+  input  [DMA_DATA_WIDTH-1:0]    m_axi_rdata,
+  output                           m_axi_rready,
+  input                            m_axi_rvalid,
+  input  [ 1:0]                    m_axi_rresp
+);
+
+parameter ID_WIDTH = 3;
+parameter DMA_DATA_WIDTH = 64;
+parameter BYTES_PER_BEAT_WIDTH = 3;
+parameter BEATS_PER_BURST_WIDTH = 4;
+
+`include "resp.h"
+
+wire address_enabled;
+
+wire address_req_valid;
+wire address_req_ready;
+wire data_req_valid;
+wire data_req_ready;
+
+assign sync_id_ret = sync_id;
+assign response_id = data_id;
+
+assign response_valid = 1'b0;
+assign response_resp = RESP_OKAY;
+
+splitter #(
+  .NUM_M(2)
+) i_req_splitter (
+  .clk(m_axi_aclk),
+  .resetn(m_axi_aresetn),
+  .s_valid(req_valid),
+  .s_ready(req_ready),
+  .m_valid({
+    address_req_valid,
+    data_req_valid
+  }),
+  .m_ready({
+    address_req_ready,
+    data_req_ready
+  })
+);
+
+dmac_address_generator #(
+  .ID_WIDTH(ID_WIDTH),
+  .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH),
+  .BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH),
+  .DMA_DATA_WIDTH(DMA_DATA_WIDTH)
+) i_addr_gen (
+  .clk(m_axi_aclk),
+  .resetn(m_axi_aresetn),
+
+  .enable(enable),
+  .enabled(address_enabled),
+  .pause(pause),
+  .sync_id(sync_id),
+
+  .request_id(request_id),
+  .id(address_id),
+
+  .req_valid(address_req_valid),
+  .req_ready(address_req_ready),
+  .req_address(req_address),
+  .req_last_burst_length(req_last_burst_length),
+
+  .eot(address_eot),
+
+  .addr_ready(m_axi_arready),
+  .addr_valid(m_axi_arvalid),
+  .addr(m_axi_araddr),
+  .len(m_axi_arlen),
+  .size(m_axi_arsize),
+  .burst(m_axi_arburst),
+  .prot(m_axi_arprot),
+  .cache(m_axi_arcache)
+);
+
+dmac_data_mover # (
+  .ID_WIDTH(ID_WIDTH),
+  .DATA_WIDTH(DMA_DATA_WIDTH),
+  .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH)
+) i_data_mover (
+  .clk(m_axi_aclk),
+  .resetn(m_axi_aresetn),
+
+  .enable(address_enabled),
+  .enabled(enabled),
+  .sync_id(sync_id),
+
+  .xfer_req(),
+
+  .request_id(address_id),
+  .response_id(data_id),
+  .eot(data_eot),
+
+  .req_valid(data_req_valid),
+  .req_ready(data_req_ready),
+  .req_last_burst_length(req_last_burst_length),
+
+  .s_axi_valid(m_axi_rvalid),
+  .s_axi_ready(m_axi_rready),
+  .s_axi_data(m_axi_rdata),
+  .m_axi_valid(fifo_valid),
+  .m_axi_ready(fifo_ready),
+  .m_axi_data(fifo_data),
+  .m_axi_last()
+);
+
+reg [1:0] rresp;
+
+always @(posedge m_axi_aclk)
+begin
+  if (m_axi_rvalid && m_axi_rready) begin
+    if (m_axi_rresp != 2'b0)
+      rresp <= m_axi_rresp;
+  end
+end
+
+endmodule
diff --git a/fpga/usrp3/lib/vivado_ipi/axi_dmac/src_axi_stream.v b/fpga/usrp3/lib/vivado_ipi/axi_dmac/src_axi_stream.v
new file mode 100644
index 000000000..a2c41a928
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/axi_dmac/src_axi_stream.v
@@ -0,0 +1,123 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2013(c) Analog Devices, Inc.
+//  Author: Lars-Peter Clausen <lars@metafoo.de>
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+module dmac_src_axi_stream (
+  input s_axis_aclk,
+  input s_axis_aresetn,
+
+  input enable,
+  output enabled,
+  input sync_id,
+  output sync_id_ret,
+
+  input [ID_WIDTH-1:0] request_id,
+  output [ID_WIDTH-1:0] response_id,
+  input eot,
+
+  output s_axis_ready,
+  input s_axis_valid,
+  input [S_AXIS_DATA_WIDTH-1:0] s_axis_data,
+  input [0:0] s_axis_user,
+  output s_axis_xfer_req,
+
+  input fifo_ready,
+  output fifo_valid,
+  output [S_AXIS_DATA_WIDTH-1:0] fifo_data,
+
+  input req_valid,
+  output req_ready,
+  input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
+  input req_sync_transfer_start
+);
+
+parameter ID_WIDTH = 3;
+parameter S_AXIS_DATA_WIDTH = 64;
+parameter LENGTH_WIDTH = 24;
+parameter BEATS_PER_BURST_WIDTH = 4;
+
+reg needs_sync = 1'b0;
+wire sync = s_axis_user[0];
+wire has_sync = ~needs_sync | sync;
+wire sync_valid = s_axis_valid & has_sync;
+assign sync_id_ret = sync_id;
+
+always @(posedge s_axis_aclk)
+begin
+  if (s_axis_aresetn == 1'b0) begin
+    needs_sync <= 1'b0;
+  end else begin
+    if (s_axis_valid && s_axis_ready && sync) begin
+      needs_sync <= 1'b0;
+    end else if (req_valid && req_ready) begin
+      needs_sync <= req_sync_transfer_start;
+    end
+  end
+end
+
+dmac_data_mover # (
+  .ID_WIDTH(ID_WIDTH),
+  .DATA_WIDTH(S_AXIS_DATA_WIDTH),
+  .DISABLE_WAIT_FOR_ID(0),
+  .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH)
+) i_data_mover (
+  .clk(s_axis_aclk),
+  .resetn(s_axis_aresetn),
+
+  .enable(enable),
+  .enabled(enabled),
+  .sync_id(sync_id),
+
+  .xfer_req(s_axis_xfer_req),
+
+  .request_id(request_id),
+  .response_id(response_id),
+  .eot(eot),
+  
+  .req_valid(req_valid),
+  .req_ready(req_ready),
+  .req_last_burst_length(req_last_burst_length),
+
+  .s_axi_ready(s_axis_ready),
+  .s_axi_valid(sync_valid),
+  .s_axi_data(s_axis_data),
+  .m_axi_ready(fifo_ready),
+  .m_axi_valid(fifo_valid),
+  .m_axi_data(fifo_data)
+);
+
+endmodule
diff --git a/fpga/usrp3/lib/vivado_ipi/axi_dmac/src_fifo_inf.v b/fpga/usrp3/lib/vivado_ipi/axi_dmac/src_fifo_inf.v
new file mode 100644
index 000000000..633cc1ab4
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/axi_dmac/src_fifo_inf.v
@@ -0,0 +1,138 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2013(c) Analog Devices, Inc.
+//  Author: Lars-Peter Clausen <lars@metafoo.de>
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+module dmac_src_fifo_inf (
+  input clk,
+  input resetn,
+
+  input enable,
+  output enabled,
+  input sync_id,
+  output sync_id_ret,
+
+  input [ID_WIDTH-1:0] request_id,
+  output [ID_WIDTH-1:0] response_id,
+  input eot,
+
+  input en,
+  input [DATA_WIDTH-1:0] din,
+  output reg overflow,
+  input sync,
+  output xfer_req,
+
+  input fifo_ready,
+  output fifo_valid,
+  output [DATA_WIDTH-1:0] fifo_data,
+
+  input req_valid,
+  output req_ready,
+  input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
+  input req_sync_transfer_start
+);
+
+parameter ID_WIDTH = 3;
+parameter DATA_WIDTH = 64;
+parameter BEATS_PER_BURST_WIDTH = 4;
+
+wire ready;
+
+reg needs_sync = 1'b0;
+wire has_sync = ~needs_sync | sync;
+wire sync_valid = en & ready & has_sync;
+
+always @(posedge clk)
+begin
+  if (resetn == 1'b0) begin
+    needs_sync <= 1'b0;
+  end else begin
+    if (ready && en && sync) begin
+      needs_sync <= 1'b0;
+    end else if (req_valid && req_ready) begin
+      needs_sync <= req_sync_transfer_start;
+    end
+  end
+end
+
+always @(posedge clk)
+begin
+  if (resetn == 1'b0) begin
+    overflow <= 1'b0;
+  end else begin
+    if (enable) begin
+      overflow <= en & ~ready;
+    end else begin
+      overflow <= en;
+    end
+  end
+end
+
+assign sync_id_ret = sync_id;
+
+dmac_data_mover # (
+  .ID_WIDTH(ID_WIDTH),
+  .DATA_WIDTH(DATA_WIDTH),
+  .DISABLE_WAIT_FOR_ID(0),
+  .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH)
+) i_data_mover (
+  .clk(clk),
+  .resetn(resetn),
+
+  .enable(enable),
+  .enabled(enabled),
+  .sync_id(sync_id),
+
+  .xfer_req(xfer_req),
+
+  .request_id(request_id),
+  .response_id(response_id),
+  .eot(eot),
+  
+  .req_valid(req_valid),
+  .req_ready(req_ready),
+  .req_last_burst_length(req_last_burst_length),
+
+  .s_axi_ready(ready),
+  .s_axi_valid(sync_valid),
+  .s_axi_data(din),
+  .m_axi_ready(fifo_ready),
+  .m_axi_valid(fifo_valid),
+  .m_axi_data(fifo_data),
+  .m_axi_last()
+);
+
+endmodule
diff --git a/fpga/usrp3/lib/vivado_ipi/axi_dmac/sync_bits.v b/fpga/usrp3/lib/vivado_ipi/axi_dmac/sync_bits.v
new file mode 100644
index 000000000..2530f047b
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/axi_dmac/sync_bits.v
@@ -0,0 +1,76 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2013(c) Analog Devices, Inc.
+//  Author: Lars-Peter Clausen <lars@metafoo.de>
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+/*
+ * Helper module for synchronizing bit signals from one clock domain to another.
+ * It uses the standard approach of 2 FF in series.
+ * Note, that while the module allows to synchronize multiple bits at once it is
+ * only able to synchronize multi-bit signals where at max one bit changes per
+ * clock cycle (e.g. a gray counter).
+ */
+module sync_bits
+(
+  input [NUM_OF_BITS-1:0] in,
+  input out_resetn,
+  input out_clk,
+  output [NUM_OF_BITS-1:0] out
+);
+
+// Number of bits to synchronize
+parameter NUM_OF_BITS = 1;
+// Whether input and output clocks are asynchronous, if 0 the synchronizer will
+// be bypassed and the output signal equals the input signal.
+parameter ASYNC_CLK = 1;
+
+reg [NUM_OF_BITS-1:0] cdc_sync_stage1 = 'h0;
+reg [NUM_OF_BITS-1:0] cdc_sync_stage2 = 'h0;
+
+always @(posedge out_clk)
+begin
+  if (out_resetn == 1'b0) begin
+    cdc_sync_stage1 <= 'b0;
+    cdc_sync_stage2 <= 'b0;
+  end else begin
+    cdc_sync_stage1 <= in;
+    cdc_sync_stage2 <= cdc_sync_stage1;
+  end
+end
+
+assign out = ASYNC_CLK ? cdc_sync_stage2 : in;
+
+endmodule
diff --git a/fpga/usrp3/lib/vivado_ipi/axi_dmac/up_axi.v b/fpga/usrp3/lib/vivado_ipi/axi_dmac/up_axi.v
new file mode 100644
index 000000000..db62e659a
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/axi_dmac/up_axi.v
@@ -0,0 +1,272 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module up_axi (
+
+  // reset and clocks
+
+  up_rstn,
+  up_clk,
+
+  // axi4 interface
+
+  up_axi_awvalid,
+  up_axi_awaddr,
+  up_axi_awready,
+  up_axi_wvalid,
+  up_axi_wdata,
+  up_axi_wstrb,
+  up_axi_wready,
+  up_axi_bvalid,
+  up_axi_bresp,
+  up_axi_bready,
+  up_axi_arvalid,
+  up_axi_araddr,
+  up_axi_arready,
+  up_axi_rvalid,
+  up_axi_rresp,
+  up_axi_rdata,
+  up_axi_rready,
+
+  // pcore interface
+
+  up_wreq,
+  up_waddr,
+  up_wdata,
+  up_wack,
+  up_rreq,
+  up_raddr,
+  up_rdata,
+  up_rack);
+
+  // parameters
+
+  parameter   ADDRESS_WIDTH = 14;
+  localparam  AW = ADDRESS_WIDTH - 1;
+
+  // reset and clocks
+
+  input           up_rstn;
+  input           up_clk;
+
+  // axi4 interface
+
+  input           up_axi_awvalid;
+  input   [31:0]  up_axi_awaddr;
+  output          up_axi_awready;
+  input           up_axi_wvalid;
+  input   [31:0]  up_axi_wdata;
+  input   [ 3:0]  up_axi_wstrb;
+  output          up_axi_wready;
+  output          up_axi_bvalid;
+  output  [ 1:0]  up_axi_bresp;
+  input           up_axi_bready;
+  input           up_axi_arvalid;
+  input   [31:0]  up_axi_araddr;
+  output          up_axi_arready;
+  output          up_axi_rvalid;
+  output  [ 1:0]  up_axi_rresp;
+  output  [31:0]  up_axi_rdata;
+  input           up_axi_rready;
+
+  // pcore interface
+
+  output          up_wreq;
+  output  [AW:0]  up_waddr;
+  output  [31:0]  up_wdata;
+  input           up_wack;
+  output          up_rreq;
+  output  [AW:0]  up_raddr;
+  input   [31:0]  up_rdata;
+  input           up_rack;
+
+  // internal registers
+
+  reg             up_axi_awready = 'd0;
+  reg             up_axi_wready = 'd0;
+  reg             up_axi_bvalid = 'd0;
+  reg             up_wack_d = 'd0;
+  reg             up_wsel = 'd0;
+  reg             up_wreq = 'd0;
+  reg     [AW:0]  up_waddr = 'd0;
+  reg     [31:0]  up_wdata = 'd0;
+  reg     [ 4:0]  up_wcount = 'd0;
+  reg             up_axi_arready = 'd0;
+  reg             up_axi_rvalid = 'd0;
+  reg     [31:0]  up_axi_rdata = 'd0;
+  reg             up_rack_d = 'd0;
+  reg     [31:0]  up_rdata_d = 'd0;
+  reg             up_rsel = 'd0;
+  reg             up_rreq = 'd0;
+  reg     [AW:0]  up_raddr = 'd0;
+  reg     [ 4:0]  up_rcount = 'd0;
+
+  // internal signals
+
+  wire            up_wack_s;
+  wire            up_rack_s;
+  wire    [31:0]  up_rdata_s;
+
+  // write channel interface
+
+  assign up_axi_bresp = 2'd0;
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 1'b0) begin
+      up_axi_awready <= 'd0;
+      up_axi_wready <= 'd0;
+      up_axi_bvalid <= 'd0;
+    end else begin
+      if (up_axi_awready == 1'b1) begin
+        up_axi_awready <= 1'b0;
+      end else if (up_wack_s == 1'b1) begin
+        up_axi_awready <= 1'b1;
+      end
+      if (up_axi_wready == 1'b1) begin
+        up_axi_wready <= 1'b0;
+      end else if (up_wack_s == 1'b1) begin
+        up_axi_wready <= 1'b1;
+      end
+      if ((up_axi_bready == 1'b1) && (up_axi_bvalid == 1'b1)) begin
+        up_axi_bvalid <= 1'b0;
+      end else if (up_wack_d == 1'b1) begin
+        up_axi_bvalid <= 1'b1;
+      end
+    end
+  end
+
+  assign up_wack_s = (up_wcount == 5'h1f) ? 1'b1 : (up_wcount[4] & up_wack);
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 1'b0) begin
+      up_wack_d <= 'd0;
+      up_wsel <= 'd0;
+      up_wreq <= 'd0;
+      up_waddr <= 'd0;
+      up_wdata <= 'd0;
+      up_wcount <= 'd0;
+    end else begin
+      up_wack_d <= up_wack_s;
+      if (up_wsel == 1'b1) begin
+        if ((up_axi_bready == 1'b1) && (up_axi_bvalid == 1'b1)) begin
+          up_wsel <= 1'b0;
+        end
+        up_wreq <= 1'b0;
+        up_waddr <= up_waddr;
+        up_wdata <= up_wdata;
+      end else begin
+        up_wsel <= up_axi_awvalid & up_axi_wvalid;
+        up_wreq <= up_axi_awvalid & up_axi_wvalid;
+        up_waddr <= up_axi_awaddr[AW+2:2];
+        up_wdata <= up_axi_wdata;
+      end
+      if (up_wack_s == 1'b1) begin
+        up_wcount <= 5'h00;
+      end else if (up_wcount[4] == 1'b1) begin
+        up_wcount <= up_wcount + 1'b1;
+      end else if (up_wreq == 1'b1) begin
+        up_wcount <= 5'h10;
+      end
+    end
+  end
+
+  // read channel interface
+
+  assign up_axi_rresp = 2'd0;
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 1'b0) begin
+      up_axi_arready <= 'd0;
+      up_axi_rvalid <= 'd0;
+      up_axi_rdata <= 'd0;
+    end else begin
+      if (up_axi_arready == 1'b1) begin
+        up_axi_arready <= 1'b0;
+      end else if (up_rack_s == 1'b1) begin
+        up_axi_arready <= 1'b1;
+      end
+      if ((up_axi_rready == 1'b1) && (up_axi_rvalid == 1'b1)) begin
+        up_axi_rvalid <= 1'b0;
+        up_axi_rdata <= 32'd0;
+      end else if (up_rack_d == 1'b1) begin
+        up_axi_rvalid <= 1'b1;
+        up_axi_rdata <= up_rdata_d;
+      end
+    end
+  end
+
+  assign up_rack_s = (up_rcount == 5'h1f) ? 1'b1 : (up_rcount[4] & up_rack);
+  assign up_rdata_s = (up_rcount == 5'h1f) ? {2{16'hdead}} : up_rdata;
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 1'b0) begin
+      up_rack_d <= 'd0;
+      up_rdata_d <= 'd0;
+      up_rsel <= 'd0;
+      up_rreq <= 'd0;
+      up_raddr <= 'd0;
+      up_rcount <= 'd0;
+    end else begin
+      up_rack_d <= up_rack_s;
+      up_rdata_d <= up_rdata_s;
+      if (up_rsel == 1'b1) begin
+        if ((up_axi_rready == 1'b1) && (up_axi_rvalid == 1'b1)) begin
+          up_rsel <= 1'b0;
+        end
+        up_rreq <= 1'b0;
+        up_raddr <= up_raddr;
+      end else begin
+        up_rsel <= up_axi_arvalid;
+        up_rreq <= up_axi_arvalid;
+        up_raddr <= up_axi_araddr[AW+2:2];
+      end
+      if (up_rack_s == 1'b1) begin
+        up_rcount <= 5'h00;
+      end else if (up_rcount[4] == 1'b1) begin
+        up_rcount <= up_rcount + 1'b1;
+      end else if (up_rreq == 1'b1) begin
+        up_rcount <= 5'h10;
+      end
+    end
+  end
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
diff --git a/fpga/usrp3/lib/vivado_ipi/axi_dmac/xgui/axi_dmac_v1_0.tcl b/fpga/usrp3/lib/vivado_ipi/axi_dmac/xgui/axi_dmac_v1_0.tcl
new file mode 100644
index 000000000..f750a2f9c
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/axi_dmac/xgui/axi_dmac_v1_0.tcl
@@ -0,0 +1,329 @@
+
+# Loading additional proc with user specified bodies to compute parameter values.
+source [file join [file dirname [file dirname [info script]]] gui/axi_dmac_v1_0.gtcl]
+
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+  #Adding Group
+  set DMA_Endpoint_Configuration [ipgui::add_group $IPINST -name "DMA Endpoint Configuration" -parent ${Page_0} -layout horizontal]
+  #Adding Group
+  set Source [ipgui::add_group $IPINST -name "Source" -parent ${DMA_Endpoint_Configuration}]
+  ipgui::add_param $IPINST -name "DMA_TYPE_SRC" -parent ${Source} -widget comboBox
+  ipgui::add_param $IPINST -name "DMA_AXI_PROTOCOL_SRC" -parent ${Source} -widget comboBox
+  ipgui::add_param $IPINST -name "DMA_DATA_WIDTH_SRC" -parent ${Source}
+  ipgui::add_param $IPINST -name "AXI_SLICE_SRC" -parent ${Source}
+  ipgui::add_param $IPINST -name "SYNC_TRANSFER_START" -parent ${Source}
+
+  #Adding Group
+  set Destination [ipgui::add_group $IPINST -name "Destination" -parent ${DMA_Endpoint_Configuration}]
+  ipgui::add_param $IPINST -name "DMA_TYPE_DEST" -parent ${Destination} -widget comboBox
+  ipgui::add_param $IPINST -name "DMA_AXI_PROTOCOL_DEST" -parent ${Destination} -widget comboBox
+  ipgui::add_param $IPINST -name "DMA_DATA_WIDTH_DEST" -parent ${Destination}
+  ipgui::add_param $IPINST -name "AXI_SLICE_DEST" -parent ${Destination}
+
+
+  #Adding Group
+  set General_Configuration [ipgui::add_group $IPINST -name "General Configuration" -parent ${Page_0}]
+  ipgui::add_param $IPINST -name "ID" -parent ${General_Configuration}
+  ipgui::add_param $IPINST -name "DMA_LENGTH_WIDTH" -parent ${General_Configuration}
+  ipgui::add_param $IPINST -name "FIFO_SIZE" -parent ${General_Configuration}
+  ipgui::add_param $IPINST -name "MAX_BYTES_PER_BURST" -parent ${General_Configuration}
+
+  #Adding Group
+  set Features [ipgui::add_group $IPINST -name "Features" -parent ${Page_0}]
+  ipgui::add_param $IPINST -name "CYCLIC" -parent ${Features}
+  ipgui::add_param $IPINST -name "DMA_2D_TRANSFER" -parent ${Features}
+
+  #Adding Group
+  set Clock_Domain_Configuration [ipgui::add_group $IPINST -name "Clock Domain Configuration" -parent ${Page_0}]
+  ipgui::add_param $IPINST -name "ASYNC_CLK_REQ_SRC" -parent ${Clock_Domain_Configuration}
+  ipgui::add_param $IPINST -name "ASYNC_CLK_SRC_DEST" -parent ${Clock_Domain_Configuration}
+  ipgui::add_param $IPINST -name "ASYNC_CLK_DEST_REQ" -parent ${Clock_Domain_Configuration}
+
+
+
+}
+
+proc update_PARAM_VALUE.DMA_AXI_PROTOCOL_DEST { PARAM_VALUE.DMA_AXI_PROTOCOL_DEST PARAM_VALUE.DMA_TYPE_DEST } {
+	# Procedure called to update DMA_AXI_PROTOCOL_DEST when any of the dependent parameters in the arguments change
+	
+	set DMA_AXI_PROTOCOL_DEST ${PARAM_VALUE.DMA_AXI_PROTOCOL_DEST}
+	set DMA_TYPE_DEST ${PARAM_VALUE.DMA_TYPE_DEST}
+	set values(DMA_TYPE_DEST) [get_property value $DMA_TYPE_DEST]
+	if { [gen_USERPARAMETER_DMA_AXI_PROTOCOL_DEST_ENABLEMENT $values(DMA_TYPE_DEST)] } {
+		set_property enabled true $DMA_AXI_PROTOCOL_DEST
+	} else {
+		set_property enabled false $DMA_AXI_PROTOCOL_DEST
+	}
+}
+
+proc validate_PARAM_VALUE.DMA_AXI_PROTOCOL_DEST { PARAM_VALUE.DMA_AXI_PROTOCOL_DEST } {
+	# Procedure called to validate DMA_AXI_PROTOCOL_DEST
+	return true
+}
+
+proc update_PARAM_VALUE.DMA_AXI_PROTOCOL_SRC { PARAM_VALUE.DMA_AXI_PROTOCOL_SRC PARAM_VALUE.DMA_TYPE_SRC } {
+	# Procedure called to update DMA_AXI_PROTOCOL_SRC when any of the dependent parameters in the arguments change
+	
+	set DMA_AXI_PROTOCOL_SRC ${PARAM_VALUE.DMA_AXI_PROTOCOL_SRC}
+	set DMA_TYPE_SRC ${PARAM_VALUE.DMA_TYPE_SRC}
+	set values(DMA_TYPE_SRC) [get_property value $DMA_TYPE_SRC]
+	if { [gen_USERPARAMETER_DMA_AXI_PROTOCOL_SRC_ENABLEMENT $values(DMA_TYPE_SRC)] } {
+		set_property enabled true $DMA_AXI_PROTOCOL_SRC
+	} else {
+		set_property enabled false $DMA_AXI_PROTOCOL_SRC
+	}
+}
+
+proc validate_PARAM_VALUE.DMA_AXI_PROTOCOL_SRC { PARAM_VALUE.DMA_AXI_PROTOCOL_SRC } {
+	# Procedure called to validate DMA_AXI_PROTOCOL_SRC
+	return true
+}
+
+proc update_PARAM_VALUE.SYNC_TRANSFER_START { PARAM_VALUE.SYNC_TRANSFER_START PARAM_VALUE.DMA_TYPE_SRC } {
+	# Procedure called to update SYNC_TRANSFER_START when any of the dependent parameters in the arguments change
+	
+	set SYNC_TRANSFER_START ${PARAM_VALUE.SYNC_TRANSFER_START}
+	set DMA_TYPE_SRC ${PARAM_VALUE.DMA_TYPE_SRC}
+	set values(DMA_TYPE_SRC) [get_property value $DMA_TYPE_SRC]
+	if { [gen_USERPARAMETER_SYNC_TRANSFER_START_ENABLEMENT $values(DMA_TYPE_SRC)] } {
+		set_property enabled true $SYNC_TRANSFER_START
+	} else {
+		set_property enabled false $SYNC_TRANSFER_START
+	}
+}
+
+proc validate_PARAM_VALUE.SYNC_TRANSFER_START { PARAM_VALUE.SYNC_TRANSFER_START } {
+	# Procedure called to validate SYNC_TRANSFER_START
+	return true
+}
+
+proc update_PARAM_VALUE.ASYNC_CLK_DEST_REQ { PARAM_VALUE.ASYNC_CLK_DEST_REQ } {
+	# Procedure called to update ASYNC_CLK_DEST_REQ when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.ASYNC_CLK_DEST_REQ { PARAM_VALUE.ASYNC_CLK_DEST_REQ } {
+	# Procedure called to validate ASYNC_CLK_DEST_REQ
+	return true
+}
+
+proc update_PARAM_VALUE.ASYNC_CLK_REQ_SRC { PARAM_VALUE.ASYNC_CLK_REQ_SRC } {
+	# Procedure called to update ASYNC_CLK_REQ_SRC when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.ASYNC_CLK_REQ_SRC { PARAM_VALUE.ASYNC_CLK_REQ_SRC } {
+	# Procedure called to validate ASYNC_CLK_REQ_SRC
+	return true
+}
+
+proc update_PARAM_VALUE.ASYNC_CLK_SRC_DEST { PARAM_VALUE.ASYNC_CLK_SRC_DEST } {
+	# Procedure called to update ASYNC_CLK_SRC_DEST when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.ASYNC_CLK_SRC_DEST { PARAM_VALUE.ASYNC_CLK_SRC_DEST } {
+	# Procedure called to validate ASYNC_CLK_SRC_DEST
+	return true
+}
+
+proc update_PARAM_VALUE.AXI_SLICE_DEST { PARAM_VALUE.AXI_SLICE_DEST } {
+	# Procedure called to update AXI_SLICE_DEST when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.AXI_SLICE_DEST { PARAM_VALUE.AXI_SLICE_DEST } {
+	# Procedure called to validate AXI_SLICE_DEST
+	return true
+}
+
+proc update_PARAM_VALUE.AXI_SLICE_SRC { PARAM_VALUE.AXI_SLICE_SRC } {
+	# Procedure called to update AXI_SLICE_SRC when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.AXI_SLICE_SRC { PARAM_VALUE.AXI_SLICE_SRC } {
+	# Procedure called to validate AXI_SLICE_SRC
+	return true
+}
+
+proc update_PARAM_VALUE.CYCLIC { PARAM_VALUE.CYCLIC } {
+	# Procedure called to update CYCLIC when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.CYCLIC { PARAM_VALUE.CYCLIC } {
+	# Procedure called to validate CYCLIC
+	return true
+}
+
+proc update_PARAM_VALUE.DMA_2D_TRANSFER { PARAM_VALUE.DMA_2D_TRANSFER } {
+	# Procedure called to update DMA_2D_TRANSFER when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.DMA_2D_TRANSFER { PARAM_VALUE.DMA_2D_TRANSFER } {
+	# Procedure called to validate DMA_2D_TRANSFER
+	return true
+}
+
+proc update_PARAM_VALUE.DMA_DATA_WIDTH_DEST { PARAM_VALUE.DMA_DATA_WIDTH_DEST } {
+	# Procedure called to update DMA_DATA_WIDTH_DEST when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.DMA_DATA_WIDTH_DEST { PARAM_VALUE.DMA_DATA_WIDTH_DEST } {
+	# Procedure called to validate DMA_DATA_WIDTH_DEST
+	return true
+}
+
+proc update_PARAM_VALUE.DMA_DATA_WIDTH_SRC { PARAM_VALUE.DMA_DATA_WIDTH_SRC } {
+	# Procedure called to update DMA_DATA_WIDTH_SRC when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.DMA_DATA_WIDTH_SRC { PARAM_VALUE.DMA_DATA_WIDTH_SRC } {
+	# Procedure called to validate DMA_DATA_WIDTH_SRC
+	return true
+}
+
+proc update_PARAM_VALUE.DMA_LENGTH_WIDTH { PARAM_VALUE.DMA_LENGTH_WIDTH } {
+	# Procedure called to update DMA_LENGTH_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.DMA_LENGTH_WIDTH { PARAM_VALUE.DMA_LENGTH_WIDTH } {
+	# Procedure called to validate DMA_LENGTH_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.DMA_TYPE_DEST { PARAM_VALUE.DMA_TYPE_DEST } {
+	# Procedure called to update DMA_TYPE_DEST when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.DMA_TYPE_DEST { PARAM_VALUE.DMA_TYPE_DEST } {
+	# Procedure called to validate DMA_TYPE_DEST
+	return true
+}
+
+proc update_PARAM_VALUE.DMA_TYPE_SRC { PARAM_VALUE.DMA_TYPE_SRC } {
+	# Procedure called to update DMA_TYPE_SRC when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.DMA_TYPE_SRC { PARAM_VALUE.DMA_TYPE_SRC } {
+	# Procedure called to validate DMA_TYPE_SRC
+	return true
+}
+
+proc update_PARAM_VALUE.FIFO_SIZE { PARAM_VALUE.FIFO_SIZE } {
+	# Procedure called to update FIFO_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.FIFO_SIZE { PARAM_VALUE.FIFO_SIZE } {
+	# Procedure called to validate FIFO_SIZE
+	return true
+}
+
+proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } {
+	# Procedure called to update ID when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } {
+	# Procedure called to validate ID
+	return true
+}
+
+proc update_PARAM_VALUE.MAX_BYTES_PER_BURST { PARAM_VALUE.MAX_BYTES_PER_BURST } {
+	# Procedure called to update MAX_BYTES_PER_BURST when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.MAX_BYTES_PER_BURST { PARAM_VALUE.MAX_BYTES_PER_BURST } {
+	# Procedure called to validate MAX_BYTES_PER_BURST
+	return true
+}
+
+
+proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID}
+}
+
+proc update_MODELPARAM_VALUE.DMA_DATA_WIDTH_SRC { MODELPARAM_VALUE.DMA_DATA_WIDTH_SRC PARAM_VALUE.DMA_DATA_WIDTH_SRC } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.DMA_DATA_WIDTH_SRC}] ${MODELPARAM_VALUE.DMA_DATA_WIDTH_SRC}
+}
+
+proc update_MODELPARAM_VALUE.DMA_DATA_WIDTH_DEST { MODELPARAM_VALUE.DMA_DATA_WIDTH_DEST PARAM_VALUE.DMA_DATA_WIDTH_DEST } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.DMA_DATA_WIDTH_DEST}] ${MODELPARAM_VALUE.DMA_DATA_WIDTH_DEST}
+}
+
+proc update_MODELPARAM_VALUE.DMA_LENGTH_WIDTH { MODELPARAM_VALUE.DMA_LENGTH_WIDTH PARAM_VALUE.DMA_LENGTH_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.DMA_LENGTH_WIDTH}] ${MODELPARAM_VALUE.DMA_LENGTH_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.DMA_2D_TRANSFER { MODELPARAM_VALUE.DMA_2D_TRANSFER PARAM_VALUE.DMA_2D_TRANSFER } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.DMA_2D_TRANSFER}] ${MODELPARAM_VALUE.DMA_2D_TRANSFER}
+}
+
+proc update_MODELPARAM_VALUE.ASYNC_CLK_REQ_SRC { MODELPARAM_VALUE.ASYNC_CLK_REQ_SRC PARAM_VALUE.ASYNC_CLK_REQ_SRC } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.ASYNC_CLK_REQ_SRC}] ${MODELPARAM_VALUE.ASYNC_CLK_REQ_SRC}
+}
+
+proc update_MODELPARAM_VALUE.ASYNC_CLK_SRC_DEST { MODELPARAM_VALUE.ASYNC_CLK_SRC_DEST PARAM_VALUE.ASYNC_CLK_SRC_DEST } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.ASYNC_CLK_SRC_DEST}] ${MODELPARAM_VALUE.ASYNC_CLK_SRC_DEST}
+}
+
+proc update_MODELPARAM_VALUE.ASYNC_CLK_DEST_REQ { MODELPARAM_VALUE.ASYNC_CLK_DEST_REQ PARAM_VALUE.ASYNC_CLK_DEST_REQ } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.ASYNC_CLK_DEST_REQ}] ${MODELPARAM_VALUE.ASYNC_CLK_DEST_REQ}
+}
+
+proc update_MODELPARAM_VALUE.AXI_SLICE_DEST { MODELPARAM_VALUE.AXI_SLICE_DEST PARAM_VALUE.AXI_SLICE_DEST } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.AXI_SLICE_DEST}] ${MODELPARAM_VALUE.AXI_SLICE_DEST}
+}
+
+proc update_MODELPARAM_VALUE.AXI_SLICE_SRC { MODELPARAM_VALUE.AXI_SLICE_SRC PARAM_VALUE.AXI_SLICE_SRC } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.AXI_SLICE_SRC}] ${MODELPARAM_VALUE.AXI_SLICE_SRC}
+}
+
+proc update_MODELPARAM_VALUE.SYNC_TRANSFER_START { MODELPARAM_VALUE.SYNC_TRANSFER_START PARAM_VALUE.SYNC_TRANSFER_START } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.SYNC_TRANSFER_START}] ${MODELPARAM_VALUE.SYNC_TRANSFER_START}
+}
+
+proc update_MODELPARAM_VALUE.CYCLIC { MODELPARAM_VALUE.CYCLIC PARAM_VALUE.CYCLIC } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.CYCLIC}] ${MODELPARAM_VALUE.CYCLIC}
+}
+
+proc update_MODELPARAM_VALUE.DMA_AXI_PROTOCOL_DEST { MODELPARAM_VALUE.DMA_AXI_PROTOCOL_DEST PARAM_VALUE.DMA_AXI_PROTOCOL_DEST } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.DMA_AXI_PROTOCOL_DEST}] ${MODELPARAM_VALUE.DMA_AXI_PROTOCOL_DEST}
+}
+
+proc update_MODELPARAM_VALUE.DMA_AXI_PROTOCOL_SRC { MODELPARAM_VALUE.DMA_AXI_PROTOCOL_SRC PARAM_VALUE.DMA_AXI_PROTOCOL_SRC } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.DMA_AXI_PROTOCOL_SRC}] ${MODELPARAM_VALUE.DMA_AXI_PROTOCOL_SRC}
+}
+
+proc update_MODELPARAM_VALUE.DMA_TYPE_DEST { MODELPARAM_VALUE.DMA_TYPE_DEST PARAM_VALUE.DMA_TYPE_DEST } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.DMA_TYPE_DEST}] ${MODELPARAM_VALUE.DMA_TYPE_DEST}
+}
+
+proc update_MODELPARAM_VALUE.DMA_TYPE_SRC { MODELPARAM_VALUE.DMA_TYPE_SRC PARAM_VALUE.DMA_TYPE_SRC } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.DMA_TYPE_SRC}] ${MODELPARAM_VALUE.DMA_TYPE_SRC}
+}
+
+proc update_MODELPARAM_VALUE.MAX_BYTES_PER_BURST { MODELPARAM_VALUE.MAX_BYTES_PER_BURST PARAM_VALUE.MAX_BYTES_PER_BURST } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.MAX_BYTES_PER_BURST}] ${MODELPARAM_VALUE.MAX_BYTES_PER_BURST}
+}
+
+proc update_MODELPARAM_VALUE.FIFO_SIZE { MODELPARAM_VALUE.FIFO_SIZE PARAM_VALUE.FIFO_SIZE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.FIFO_SIZE}] ${MODELPARAM_VALUE.FIFO_SIZE}
+}
+
diff --git a/fpga/usrp3/lib/vivado_ipi/axi_regfile/axi_regfile.vhd b/fpga/usrp3/lib/vivado_ipi/axi_regfile/axi_regfile.vhd
new file mode 100644
index 000000000..3ec84543f
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/axi_regfile/axi_regfile.vhd
@@ -0,0 +1,144 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity axi_regfile is
+generic (
+	NUM_REGS : integer := 16
+);
+port (
+	regs : out std_logic_vector(NUM_REGS*32-1 downto 0);
+
+	S_AXI_ACLK	: in std_logic;
+	S_AXI_ARESETN	: in std_logic;
+	S_AXI_AWADDR	: in std_logic_vector(11 downto 0);
+	S_AXI_AWVALID	: in std_logic;
+	S_AXI_AWREADY	: out std_logic;
+	S_AXI_WDATA	: in std_logic_vector(31 downto 0);
+	S_AXI_WSTRB	: in std_logic_vector(3 downto 0);
+	S_AXI_WVALID	: in std_logic;
+	S_AXI_WREADY	: out std_logic;
+	S_AXI_BRESP	: out std_logic_vector(1 downto 0);
+	S_AXI_BVALID	: out std_logic;
+	S_AXI_BREADY	: in std_logic;
+	S_AXI_ARADDR	: in std_logic_vector(11 downto 0);
+	S_AXI_ARVALID	: in std_logic;
+	S_AXI_ARREADY	: out std_logic;
+	S_AXI_RDATA	: out std_logic_vector(31 downto 0);
+	S_AXI_RRESP	: out std_logic_vector(1 downto 0);
+	S_AXI_RVALID	: out std_logic;
+	S_AXI_RREADY	: in std_logic
+);
+end axi_regfile;
+
+architecture arch of axi_regfile is
+	type regfile_t is array (integer range <>) of std_logic_vector(31 downto 0);
+	signal read_token : std_logic;
+	signal write_addr : std_logic_vector(S_AXI_AWADDR'left downto S_AXI_AWADDR'right);
+	signal write_strb : std_logic_vector(3 downto 0);
+	signal write_addr_token : std_logic;
+	signal write_data : std_logic_vector(31 downto 0);
+	signal write_data_token : std_logic;
+	signal soft_reset : std_logic;
+	signal regs_r     : regfile_t(NUM_REGS-1 downto 0);
+begin
+
+	S_AXI_ARREADY <= not read_token;
+	S_AXI_RVALID <= read_token;
+	S_AXI_RRESP <= "00";
+
+	S_AXI_AWREADY <= not write_addr_token;
+	S_AXI_WREADY <= not write_data_token;
+	S_AXI_BVALID <= write_addr_token and write_data_token;
+	S_AXI_BRESP <= "00";
+
+	--Port assignment from registers
+	reg_distribution : process (regs_r)
+	begin
+		for i in 0 to NUM_REGS-1 loop
+			regs(32*(i+1)-1 downto 32*i) <= regs_r(i);
+		end loop;
+	end process reg_distribution;
+
+	--Register reads
+	read_proc : process (S_AXI_ACLK)
+		variable read_addr : integer; 
+	begin
+	if rising_edge(S_AXI_ACLK) then
+		read_addr := to_integer(unsigned(S_AXI_ARADDR(S_AXI_ARADDR'left downto S_AXI_ARADDR'right+2)));
+
+		if (S_AXI_ARESETN = '0') then
+			read_token <= '0';
+		elsif (S_AXI_ARVALID = '1') and (read_token = '0') then
+			read_token <= '1';
+		elsif (S_AXI_RREADY = '1') and (read_token = '1') then
+			read_token <= '0';
+		end if;
+
+		if (S_AXI_ARVALID = '1') and (read_token = '0') then
+			S_AXI_RDATA <= (others => '0');
+			for i in 0 to NUM_REGS-1 loop
+				if (read_addr = i) then
+					S_AXI_RDATA <= regs_r(i);
+				end if;
+			end loop;
+		end if;
+	end if;
+	end process read_proc;
+
+	write_proc : process (S_AXI_ACLK)
+	begin
+	if rising_edge(S_AXI_ACLK) then
+		if (S_AXI_ARESETN = '0') then
+			write_addr_token <= '0';
+			write_data_token <= '0';
+			write_strb <= (others => '0');
+		else
+			if (S_AXI_AWVALID = '1') and (write_addr_token = '0') then
+				write_addr_token <= '1';
+			elsif (S_AXI_BREADY = '1') and (write_addr_token = '1') and (write_data_token = '1') then
+				write_addr_token <= '0';
+			end if;
+
+			if (S_AXI_WVALID = '1') and (write_data_token = '0') then
+				write_data_token <= '1';
+			elsif (S_AXI_BREADY = '1') and (write_addr_token = '1') and (write_data_token = '1') then
+				write_data_token <= '0';
+			end if;
+		end if;
+
+		if (S_AXI_AWVALID = '1') and (write_addr_token = '0') then
+			write_addr <= S_AXI_AWADDR;
+		end if;
+
+		if (S_AXI_WVALID = '1') and (write_data_token = '0') then
+			write_data <= S_AXI_WDATA;
+			write_strb <= S_AXI_WSTRB;
+		end if;
+	end if;
+	end process write_proc;
+
+	-- Update registers on write
+	write_reg : process (S_AXI_ACLK)
+		variable write_addr_int : integer;
+	begin
+	if rising_edge(S_AXI_ACLK) then
+		write_addr_int := to_integer(unsigned(write_addr(write_addr'left downto 2)));
+
+		if (S_AXI_ARESETN = '0') or (soft_reset = '1') then
+			--Initial states for each signal
+			soft_reset <= '0';
+		elsif (write_addr_token = '1') and (write_data_token = '1') then
+			for i in 0 to NUM_REGS-1 loop
+				if (write_addr_int = i) then
+					for j in write_strb'left downto write_strb'right loop
+						regs_r(i)(j*8+7 downto j*8) <= write_data(j*8+7 downto j*8);
+					end loop;
+				end if;
+			end loop;
+		end if;
+	end if;
+	end process write_reg;
+
+end arch;
+
diff --git a/fpga/usrp3/lib/vivado_ipi/axi_regfile/component.xml b/fpga/usrp3/lib/vivado_ipi/axi_regfile/component.xml
new file mode 100644
index 000000000..fc0e6382d
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/axi_regfile/component.xml
@@ -0,0 +1,661 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>ettus.com</spirit:vendor>
+  <spirit:library>ip</spirit:library>
+  <spirit:name>axi_regfile</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>S_AXI</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="S_AXI"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S_AXI_ACLK</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_ACLK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.ASSOCIATED_BUSIF">S_AXI</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.ASSOCIATED_RESET">S_AXI_ARESETN</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S_AXI_ARESETN</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_ARESETN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_ARESETN.POLARITY" spirit:choiceRef="choice_list_74b5137e">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:memoryMaps>
+    <spirit:memoryMap>
+      <spirit:name>S_AXI</spirit:name>
+      <spirit:addressBlock>
+        <spirit:name>regs</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">4096</spirit:range>
+        <spirit:width spirit:format="long">0</spirit:width>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+  </spirit:memoryMaps>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+        <spirit:displayName>Synthesis</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+        <spirit:language>VHDL</spirit:language>
+        <spirit:modelName>axi_regfile</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>876922da</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+        <spirit:displayName>Simulation</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:language>VHDL</spirit:language>
+        <spirit:modelName>axi_regfile</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>876922da</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_xpgui</spirit:name>
+        <spirit:displayName>UI Layout</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>012f1d4f</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+    </spirit:views>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>regs</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.NUM_REGS&apos;)) * 32) - 1)">511</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_ACLK</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_ARESETN</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_AWADDR</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">11</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_AWVALID</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_AWREADY</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_WDATA</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_WSTRB</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">3</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_WVALID</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_WREADY</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_BRESP</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_BVALID</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_BREADY</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_ARADDR</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">11</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_ARVALID</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_ARREADY</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_RDATA</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_RRESP</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_RVALID</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_RREADY</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
+        <spirit:name>NUM_REGS</spirit:name>
+        <spirit:displayName>Num Regs</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.NUM_REGS">16</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:choices>
+    <spirit:choice>
+      <spirit:name>choice_list_74b5137e</spirit:name>
+      <spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
+      <spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
+    </spirit:choice>
+  </spirit:choices>
+  <spirit:fileSets>
+    <spirit:fileSet>
+      <spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>axi_regfile.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>CHECKSUM_876922da</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>axi_regfile.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_xpgui_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>xgui/axi_regfile_v1_0.tcl</spirit:name>
+        <spirit:fileType>tclSource</spirit:fileType>
+        <spirit:userFileType>CHECKSUM_012f1d4f</spirit:userFileType>
+        <spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>axi_regfile_v1_0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>NUM_REGS</spirit:name>
+      <spirit:displayName>Num Regs</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NUM_REGS" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">16</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">axi_regfile_v1_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:supportedFamilies>
+        <xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
+      </xilinx:supportedFamilies>
+      <xilinx:taxonomies>
+        <xilinx:taxonomy>/EttusResearch</xilinx:taxonomy>
+      </xilinx:taxonomies>
+      <xilinx:displayName>axi_regfile_v1_0</xilinx:displayName>
+      <xilinx:coreRevision>2</xilinx:coreRevision>
+      <xilinx:coreCreationDateTime>2017-06-02T21:40:33Z</xilinx:coreCreationDateTime>
+      <xilinx:tags>
+        <xilinx:tag xilinx:name="nopcore"/>
+        <xilinx:tag xilinx:name="ettus.com:ip:axi_regfile:1.0_ARCHIVE_LOCATION">usrp3/lib/vivado_ipi/axi_regfile</xilinx:tag>
+      </xilinx:tags>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2015.4</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="93ec0ca8"/>
+      <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="3fb862bd"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="3c1bd853"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="172f3ad0"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="d473f965"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="cbb0b4a6"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/fpga/usrp3/lib/vivado_ipi/axi_regfile/xgui/axi_regfile_v1_0.tcl b/fpga/usrp3/lib/vivado_ipi/axi_regfile/xgui/axi_regfile_v1_0.tcl
new file mode 100644
index 000000000..0ab7d0eca
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/axi_regfile/xgui/axi_regfile_v1_0.tcl
@@ -0,0 +1,25 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+  ipgui::add_param $IPINST -name "NUM_REGS" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.NUM_REGS { PARAM_VALUE.NUM_REGS } {
+	# Procedure called to update NUM_REGS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.NUM_REGS { PARAM_VALUE.NUM_REGS } {
+	# Procedure called to validate NUM_REGS
+	return true
+}
+
+
+proc update_MODELPARAM_VALUE.NUM_REGS { MODELPARAM_VALUE.NUM_REGS PARAM_VALUE.NUM_REGS } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.NUM_REGS}] ${MODELPARAM_VALUE.NUM_REGS}
+}
+
diff --git a/fpga/usrp3/lib/vivado_ipi/interfaces/fifo_rd.xml b/fpga/usrp3/lib/vivado_ipi/interfaces/fifo_rd.xml
new file mode 100644
index 000000000..66d44bdbd
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/interfaces/fifo_rd.xml
@@ -0,0 +1,13 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>analog.com</spirit:vendor>
+  <spirit:library>interface</spirit:library>
+  <spirit:name>fifo_rd</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:directConnection>false</spirit:directConnection>
+  <spirit:isAddressable>false</spirit:isAddressable>
+  <spirit:extends spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="fifo_read" spirit:version="1.0"/>
+  <spirit:maxMasters>1</spirit:maxMasters>
+  <spirit:maxSlaves>1</spirit:maxSlaves>
+  <spirit:description>FIFO Read Interface</spirit:description>
+</spirit:busDefinition>
diff --git a/fpga/usrp3/lib/vivado_ipi/interfaces/fifo_rd_rtl.xml b/fpga/usrp3/lib/vivado_ipi/interfaces/fifo_rd_rtl.xml
new file mode 100644
index 000000000..3c15f7203
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/interfaces/fifo_rd_rtl.xml
@@ -0,0 +1,69 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>analog.com</spirit:vendor>
+  <spirit:library>interface</spirit:library>
+  <spirit:name>fifo_rd_rtl</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="fifo_rd" spirit:version="1.0"/>
+  <spirit:ports>
+    <spirit:port>
+      <spirit:logicalName>DATA</spirit:logicalName>
+      <spirit:description>FIFO Read Data</spirit:description>
+      <spirit:wire>
+        <spirit:qualifier>
+          <spirit:isData>true</spirit:isData>
+        </spirit:qualifier>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onSlave>
+        <spirit:defaultValue>0</spirit:defaultValue>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>EN</spirit:logicalName>
+      <spirit:description>FIFO Read Enable</spirit:description>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+        <spirit:defaultValue>0</spirit:defaultValue>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>UNDERFLOW</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:width>1</spirit:width>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>VALID</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+  </spirit:ports>
+</spirit:abstractionDefinition>
diff --git a/fpga/usrp3/lib/vivado_ipi/interfaces/fifo_wr.xml b/fpga/usrp3/lib/vivado_ipi/interfaces/fifo_wr.xml
new file mode 100644
index 000000000..8e1f4d781
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/interfaces/fifo_wr.xml
@@ -0,0 +1,13 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>analog.com</spirit:vendor>
+  <spirit:library>interface</spirit:library>
+  <spirit:name>fifo_wr</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:directConnection>false</spirit:directConnection>
+  <spirit:isAddressable>false</spirit:isAddressable>
+  <spirit:extends spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="fifo_write" spirit:version="1.0"/>
+  <spirit:maxMasters>1</spirit:maxMasters>
+  <spirit:maxSlaves>1</spirit:maxSlaves>
+  <spirit:description>FIFO Write Interface</spirit:description>
+</spirit:busDefinition>
diff --git a/fpga/usrp3/lib/vivado_ipi/interfaces/fifo_wr_rtl.xml b/fpga/usrp3/lib/vivado_ipi/interfaces/fifo_wr_rtl.xml
new file mode 100644
index 000000000..49509dbfa
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/interfaces/fifo_wr_rtl.xml
@@ -0,0 +1,88 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>analog.com</spirit:vendor>
+  <spirit:library>interface</spirit:library>
+  <spirit:name>fifo_wr_rtl</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="fifo_wr" spirit:version="1.0"/>
+  <spirit:ports>
+    <spirit:port>
+      <spirit:logicalName>DATA</spirit:logicalName>
+      <spirit:description/>
+      <spirit:wire>
+        <spirit:qualifier>
+          <spirit:isData>true</spirit:isData>
+        </spirit:qualifier>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+        <spirit:defaultValue>0</spirit:defaultValue>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>EN</spirit:logicalName>
+      <spirit:description/>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+        <spirit:defaultValue>0</spirit:defaultValue>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>OVERFLOW</spirit:logicalName>
+      <spirit:description/>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>optional</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>optional</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onSlave>
+        <spirit:defaultValue>0</spirit:defaultValue>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>SYNC</spirit:logicalName>
+      <spirit:description/>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>optional</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>optional</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+        <spirit:defaultValue>0</spirit:defaultValue>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>XFER_REQ</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+      </spirit:wire>
+    </spirit:port>
+  </spirit:ports>
+</spirit:abstractionDefinition>
diff --git a/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_pll.xml b/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_pll.xml
new file mode 100644
index 000000000..583c1f242
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_pll.xml
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>ADI</spirit:vendor>
+  <spirit:library>user</spirit:library>
+  <spirit:name>if_gt_pll</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:directConnection>false</spirit:directConnection>
+  <spirit:isAddressable>false</spirit:isAddressable>
+  <spirit:maxMasters>1</spirit:maxMasters>
+  <spirit:maxSlaves>1</spirit:maxSlaves>
+</spirit:busDefinition>
diff --git a/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_pll_rtl.xml b/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_pll_rtl.xml
new file mode 100644
index 000000000..58d14d2f7
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_pll_rtl.xml
@@ -0,0 +1,46 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>ADI</spirit:vendor>
+  <spirit:library>user</spirit:library>
+  <spirit:name>if_gt_pll_rtl</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busType spirit:vendor="ADI" spirit:library="user" spirit:name="if_gt_pll" spirit:version="1.0"/>
+  <spirit:ports>
+    <spirit:port>
+      <spirit:logicalName>cpll_rst_m</spirit:logicalName>
+      <spirit:wire>
+        <spirit:qualifier>
+          <spirit:isReset>true</spirit:isReset>
+        </spirit:qualifier>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>cpll_ref_clk_in</spirit:logicalName>
+      <spirit:wire>
+        <spirit:qualifier>
+          <spirit:isClock>true</spirit:isClock>
+        </spirit:qualifier>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+  </spirit:ports>
+</spirit:abstractionDefinition>
diff --git a/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_qpll.xml b/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_qpll.xml
new file mode 100644
index 000000000..12e43a4c0
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_qpll.xml
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>ADI</spirit:vendor>
+  <spirit:library>user</spirit:library>
+  <spirit:name>if_gt_qpll</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:directConnection>false</spirit:directConnection>
+  <spirit:isAddressable>false</spirit:isAddressable>
+  <spirit:maxMasters>1</spirit:maxMasters>
+  <spirit:maxSlaves>1</spirit:maxSlaves>
+</spirit:busDefinition>
diff --git a/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_qpll_rtl.xml b/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_qpll_rtl.xml
new file mode 100644
index 000000000..486cb8b61
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_qpll_rtl.xml
@@ -0,0 +1,46 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>ADI</spirit:vendor>
+  <spirit:library>user</spirit:library>
+  <spirit:name>if_gt_qpll_rtl</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busType spirit:vendor="ADI" spirit:library="user" spirit:name="if_gt_qpll" spirit:version="1.0"/>
+  <spirit:ports>
+    <spirit:port>
+      <spirit:logicalName>qpll_rst</spirit:logicalName>
+      <spirit:wire>
+        <spirit:qualifier>
+          <spirit:isReset>true</spirit:isReset>
+        </spirit:qualifier>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>qpll_ref_clk</spirit:logicalName>
+      <spirit:wire>
+        <spirit:qualifier>
+          <spirit:isClock>true</spirit:isClock>
+        </spirit:qualifier>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+  </spirit:ports>
+</spirit:abstractionDefinition>
diff --git a/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_rx.xml b/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_rx.xml
new file mode 100644
index 000000000..24e435073
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_rx.xml
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>ADI</spirit:vendor>
+  <spirit:library>user</spirit:library>
+  <spirit:name>if_gt_rx</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:directConnection>false</spirit:directConnection>
+  <spirit:isAddressable>false</spirit:isAddressable>
+  <spirit:maxMasters>1</spirit:maxMasters>
+  <spirit:maxSlaves>1</spirit:maxSlaves>
+</spirit:busDefinition>
diff --git a/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_rx_ksig.xml b/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_rx_ksig.xml
new file mode 100644
index 000000000..a8cae5ade
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_rx_ksig.xml
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>ADI</spirit:vendor>
+  <spirit:library>user</spirit:library>
+  <spirit:name>if_gt_rx_ksig</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:directConnection>false</spirit:directConnection>
+  <spirit:isAddressable>false</spirit:isAddressable>
+  <spirit:maxMasters>1</spirit:maxMasters>
+  <spirit:maxSlaves>1</spirit:maxSlaves>
+</spirit:busDefinition>
diff --git a/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_rx_ksig_rtl.xml b/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_rx_ksig_rtl.xml
new file mode 100644
index 000000000..4e09e7982
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_rx_ksig_rtl.xml
@@ -0,0 +1,85 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>ADI</spirit:vendor>
+  <spirit:library>user</spirit:library>
+  <spirit:name>if_gt_rx_ksig_rtl</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busType spirit:vendor="ADI" spirit:library="user" spirit:name="if_gt_rx_ksig" spirit:version="1.0"/>
+  <spirit:ports>
+    <spirit:port>
+      <spirit:logicalName>rx_gt_ilas_f</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>4</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>4</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>rx_gt_ilas_q</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>4</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>4</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>rx_gt_ilas_a</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>4</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>4</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>rx_gt_ilas_r</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>4</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>4</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>rx_gt_cgs_k</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>4</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>4</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+  </spirit:ports>
+</spirit:abstractionDefinition>
diff --git a/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_rx_rtl.xml b/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_rx_rtl.xml
new file mode 100644
index 000000000..e2e49d1c3
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_rx_rtl.xml
@@ -0,0 +1,409 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>ADI</spirit:vendor>
+  <spirit:library>user</spirit:library>
+  <spirit:name>if_gt_rx_rtl</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busType spirit:vendor="ADI" spirit:library="user" spirit:name="if_gt_rx" spirit:version="1.0"/>
+  <spirit:ports>
+    <spirit:port>
+      <spirit:logicalName>rx_p</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>rx_n</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>rx_rst</spirit:logicalName>
+      <spirit:wire>
+        <spirit:qualifier>
+          <spirit:isReset>true</spirit:isReset>
+        </spirit:qualifier>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>rx_rst_m</spirit:logicalName>
+      <spirit:wire>
+        <spirit:qualifier>
+          <spirit:isReset>true</spirit:isReset>
+        </spirit:qualifier>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>rx_pll_rst</spirit:logicalName>
+      <spirit:wire>
+        <spirit:qualifier>
+          <spirit:isReset>true</spirit:isReset>
+        </spirit:qualifier>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>rx_gt_rst</spirit:logicalName>
+      <spirit:wire>
+        <spirit:qualifier>
+          <spirit:isReset>true</spirit:isReset>
+        </spirit:qualifier>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>rx_gt_rst_m</spirit:logicalName>
+      <spirit:wire>
+        <spirit:qualifier>
+          <spirit:isReset>true</spirit:isReset>
+        </spirit:qualifier>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>rx_pll_locked</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>rx_pll_locked_m</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>rx_user_ready</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>rx_user_ready_m</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>rx_rst_done</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>rx_rst_done_m</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>rx_out_clk</spirit:logicalName>
+      <spirit:wire>
+        <spirit:qualifier>
+          <spirit:isClock>true</spirit:isClock>
+        </spirit:qualifier>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>rx_clk</spirit:logicalName>
+      <spirit:wire>
+        <spirit:qualifier>
+          <spirit:isClock>true</spirit:isClock>
+        </spirit:qualifier>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>rx_sysref</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>rx_sync</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>rx_sof</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>rx_data</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>32</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>32</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>rx_ip_rst</spirit:logicalName>
+      <spirit:wire>
+        <spirit:qualifier>
+          <spirit:isReset>true</spirit:isReset>
+        </spirit:qualifier>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>rx_ip_sof</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>4</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>4</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>rx_ip_data</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>32</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>32</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>rx_ip_sysref</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>rx_ip_sync</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>rx_ip_rst_done</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+  </spirit:ports>
+</spirit:abstractionDefinition>
diff --git a/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_tx.xml b/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_tx.xml
new file mode 100644
index 000000000..50eca29d0
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_tx.xml
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>ADI</spirit:vendor>
+  <spirit:library>user</spirit:library>
+  <spirit:name>if_gt_tx</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:directConnection>false</spirit:directConnection>
+  <spirit:isAddressable>false</spirit:isAddressable>
+  <spirit:maxMasters>1</spirit:maxMasters>
+  <spirit:maxSlaves>1</spirit:maxSlaves>
+</spirit:busDefinition>
diff --git a/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_tx_rtl.xml b/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_tx_rtl.xml
new file mode 100644
index 000000000..faaa387f2
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_tx_rtl.xml
@@ -0,0 +1,379 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>ADI</spirit:vendor>
+  <spirit:library>user</spirit:library>
+  <spirit:name>if_gt_tx_rtl</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busType spirit:vendor="ADI" spirit:library="user" spirit:name="if_gt_tx" spirit:version="1.0"/>
+  <spirit:ports>
+    <spirit:port>
+      <spirit:logicalName>tx_p</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>tx_n</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>tx_rst</spirit:logicalName>
+      <spirit:wire>
+        <spirit:qualifier>
+          <spirit:isReset>true</spirit:isReset>
+        </spirit:qualifier>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>tx_rst_m</spirit:logicalName>
+      <spirit:wire>
+        <spirit:qualifier>
+          <spirit:isReset>true</spirit:isReset>
+        </spirit:qualifier>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>tx_pll_rst</spirit:logicalName>
+      <spirit:wire>
+        <spirit:qualifier>
+          <spirit:isReset>true</spirit:isReset>
+        </spirit:qualifier>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>tx_gt_rst</spirit:logicalName>
+      <spirit:wire>
+        <spirit:qualifier>
+          <spirit:isReset>true</spirit:isReset>
+        </spirit:qualifier>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>tx_gt_rst_m</spirit:logicalName>
+      <spirit:wire>
+        <spirit:qualifier>
+          <spirit:isReset>true</spirit:isReset>
+        </spirit:qualifier>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>tx_pll_locked</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>tx_pll_locked_m</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>tx_user_ready</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>tx_user_ready_m</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>tx_rst_done</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>tx_rst_done_m</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>tx_out_clk</spirit:logicalName>
+      <spirit:wire>
+        <spirit:qualifier>
+          <spirit:isClock>true</spirit:isClock>
+        </spirit:qualifier>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>tx_clk</spirit:logicalName>
+      <spirit:wire>
+        <spirit:qualifier>
+          <spirit:isClock>true</spirit:isClock>
+        </spirit:qualifier>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>tx_sysref</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>tx_sync</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>tx_data</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>32</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>32</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>tx_ip_rst</spirit:logicalName>
+      <spirit:wire>
+        <spirit:qualifier>
+          <spirit:isReset>true</spirit:isReset>
+        </spirit:qualifier>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>tx_ip_data</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>32</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>32</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>tx_ip_sysref</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>tx_ip_sync</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>tx_ip_rst_done</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+  </spirit:ports>
+</spirit:abstractionDefinition>
diff --git a/fpga/usrp3/lib/vivado_ipi/interfaces/if_xcvr_ch.xml b/fpga/usrp3/lib/vivado_ipi/interfaces/if_xcvr_ch.xml
new file mode 100644
index 000000000..32a225486
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/interfaces/if_xcvr_ch.xml
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>ADI</spirit:vendor>
+  <spirit:library>user</spirit:library>
+  <spirit:name>if_xcvr_ch</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:directConnection>false</spirit:directConnection>
+  <spirit:isAddressable>false</spirit:isAddressable>
+  <spirit:maxMasters>1</spirit:maxMasters>
+  <spirit:maxSlaves>1</spirit:maxSlaves>
+</spirit:busDefinition>
diff --git a/fpga/usrp3/lib/vivado_ipi/interfaces/if_xcvr_ch_rtl.xml b/fpga/usrp3/lib/vivado_ipi/interfaces/if_xcvr_ch_rtl.xml
new file mode 100644
index 000000000..ba01aef9c
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/interfaces/if_xcvr_ch_rtl.xml
@@ -0,0 +1,235 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>ADI</spirit:vendor>
+  <spirit:library>user</spirit:library>
+  <spirit:name>if_xcvr_ch_rtl</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busType spirit:vendor="ADI" spirit:library="user" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
+  <spirit:ports>
+    <spirit:port>
+      <spirit:logicalName>pll_locked</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>rst</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>user_ready</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>rst_done</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>lpm_dfe_n</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>rate</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>3</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>3</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>sys_clk_sel</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>2</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>2</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>out_clk_sel</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>3</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>3</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>sel</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>8</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>8</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>enb</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>addr</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>12</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>12</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>wr</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>wdata</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>16</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>16</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>rdata</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>16</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>16</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>ready</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+  </spirit:ports>
+</spirit:abstractionDefinition>
diff --git a/fpga/usrp3/lib/vivado_ipi/interfaces/if_xcvr_cm.xml b/fpga/usrp3/lib/vivado_ipi/interfaces/if_xcvr_cm.xml
new file mode 100644
index 000000000..218fd3686
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/interfaces/if_xcvr_cm.xml
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>ADI</spirit:vendor>
+  <spirit:library>user</spirit:library>
+  <spirit:name>if_xcvr_cm</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:directConnection>false</spirit:directConnection>
+  <spirit:isAddressable>false</spirit:isAddressable>
+  <spirit:maxMasters>1</spirit:maxMasters>
+  <spirit:maxSlaves>1</spirit:maxSlaves>
+</spirit:busDefinition>
diff --git a/fpga/usrp3/lib/vivado_ipi/interfaces/if_xcvr_cm_rtl.xml b/fpga/usrp3/lib/vivado_ipi/interfaces/if_xcvr_cm_rtl.xml
new file mode 100644
index 000000000..beb223077
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/interfaces/if_xcvr_cm_rtl.xml
@@ -0,0 +1,115 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>ADI</spirit:vendor>
+  <spirit:library>user</spirit:library>
+  <spirit:name>if_xcvr_cm_rtl</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busType spirit:vendor="ADI" spirit:library="user" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
+  <spirit:ports>
+    <spirit:port>
+      <spirit:logicalName>sel</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>8</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>8</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>enb</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>addr</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>12</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>12</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>wr</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>wdata</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>16</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>16</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>rdata</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>16</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>16</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>ready</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>out</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+  </spirit:ports>
+</spirit:abstractionDefinition>
diff --git a/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/Makefile b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/Makefile
new file mode 100644
index 000000000..d1e77a7b1
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/Makefile
@@ -0,0 +1,51 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+M_DEPS += ../common/sync_bits.v
+M_DEPS += ../common/sync_gray.v
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_ip.tcl
+M_DEPS += address_gray.v
+M_DEPS += address_gray_pipelined.v
+M_DEPS += address_sync.v
+M_DEPS += util_axis_fifo.v
+M_DEPS += util_axis_fifo_ip.tcl
+
+M_VIVADO := vivado -mode batch -source
+
+M_FLIST := *.cache
+M_FLIST += *.data
+M_FLIST += *.xpr
+M_FLIST += *.log
+M_FLIST += component.xml
+M_FLIST += *.jou
+M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
+M_FLIST += .Xil
+
+
+
+.PHONY: all clean clean-all
+all: util_axis_fifo.xpr
+
+
+clean:clean-all
+
+
+clean-all:
+	rm -rf $(M_FLIST)
+
+
+util_axis_fifo.xpr: $(M_DEPS)
+	-rm -rf $(M_FLIST)
+	$(M_VIVADO) util_axis_fifo_ip.tcl  >> util_axis_fifo_ip.log 2>&1
+
+####################################################################################
+####################################################################################
diff --git a/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/address_gray.v b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/address_gray.v
new file mode 100644
index 000000000..5c912179d
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/address_gray.v
@@ -0,0 +1,156 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2013(c) Analog Devices, Inc.
+//  Author: Lars-Peter Clausen <lars@metafoo.de>
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+module fifo_address_gray (
+  input m_axis_aclk,
+  input m_axis_aresetn,
+  input m_axis_ready,
+  output reg m_axis_valid,
+  output reg [ADDRESS_WIDTH:0] m_axis_level,
+
+  input s_axis_aclk,
+  input s_axis_aresetn,
+  output reg s_axis_ready,
+  input s_axis_valid,
+  output reg s_axis_empty,
+  output [ADDRESS_WIDTH-1:0] s_axis_waddr,
+  output reg [ADDRESS_WIDTH:0] s_axis_room
+);
+
+parameter ADDRESS_WIDTH = 4;
+
+reg [ADDRESS_WIDTH:0] _s_axis_waddr = 'h00;
+reg [ADDRESS_WIDTH:0] _s_axis_waddr_next;
+
+reg [ADDRESS_WIDTH:0] _m_axis_raddr = 'h00;
+reg [ADDRESS_WIDTH:0] _m_axis_raddr_next;
+
+reg [ADDRESS_WIDTH:0] s_axis_waddr_gray = 'h00;
+wire [ADDRESS_WIDTH:0] s_axis_waddr_gray_next;
+wire [ADDRESS_WIDTH:0] s_axis_raddr_gray;
+
+reg [ADDRESS_WIDTH:0] m_axis_raddr_gray = 'h00;
+wire [ADDRESS_WIDTH:0] m_axis_raddr_gray_next;
+wire [ADDRESS_WIDTH:0] m_axis_waddr_gray;
+
+assign s_axis_waddr = _s_axis_waddr[ADDRESS_WIDTH-1:0];
+
+always @(*)
+begin
+  if (s_axis_ready && s_axis_valid)
+    _s_axis_waddr_next <= _s_axis_waddr + 1;
+  else
+    _s_axis_waddr_next <= _s_axis_waddr;
+end
+
+assign s_axis_waddr_gray_next = _s_axis_waddr_next ^ _s_axis_waddr_next[ADDRESS_WIDTH:1];
+
+always @(posedge s_axis_aclk)
+begin
+  if (s_axis_aresetn == 1'b0) begin
+    _s_axis_waddr <= 'h00;
+    s_axis_waddr_gray <= 'h00;
+  end else begin
+    _s_axis_waddr <= _s_axis_waddr_next;
+    s_axis_waddr_gray <= s_axis_waddr_gray_next;
+  end
+end
+
+always @(*)
+begin
+  if (m_axis_ready && m_axis_valid)
+    _m_axis_raddr_next <= _m_axis_raddr + 1;
+  else
+    _m_axis_raddr_next <= _m_axis_raddr;
+end
+
+assign m_axis_raddr_gray_next = _m_axis_raddr_next ^ _m_axis_raddr_next[ADDRESS_WIDTH:1];
+
+always @(posedge m_axis_aclk)
+begin
+  if (m_axis_aresetn == 1'b0) begin
+    _m_axis_raddr <= 'h00;
+    m_axis_raddr_gray <= 'h00;
+  end else begin
+    _m_axis_raddr <= _m_axis_raddr_next;
+    m_axis_raddr_gray <= m_axis_raddr_gray_next;
+  end
+end
+
+sync_bits #(
+  .NUM_OF_BITS(ADDRESS_WIDTH + 1)
+) i_waddr_sync (
+  .out_clk(m_axis_aclk),
+  .out_resetn(m_axis_aresetn),
+  .in(s_axis_waddr_gray),
+  .out(m_axis_waddr_gray)
+);
+
+sync_bits #(
+  .NUM_OF_BITS(ADDRESS_WIDTH + 1)
+) i_raddr_sync (
+  .out_clk(s_axis_aclk),
+  .out_resetn(s_axis_aresetn),
+  .in(m_axis_raddr_gray),
+  .out(s_axis_raddr_gray)
+);
+
+always @(posedge s_axis_aclk)
+begin
+  if (s_axis_aresetn == 1'b0) begin
+    s_axis_ready <= 1'b1;
+    s_axis_empty <= 1'b1;
+  end else begin
+    s_axis_ready <= (s_axis_raddr_gray[ADDRESS_WIDTH] == s_axis_waddr_gray_next[ADDRESS_WIDTH] ||
+      s_axis_raddr_gray[ADDRESS_WIDTH-1] == s_axis_waddr_gray_next[ADDRESS_WIDTH-1] ||
+      s_axis_raddr_gray[ADDRESS_WIDTH-2:0] != s_axis_waddr_gray_next[ADDRESS_WIDTH-2:0]);
+    s_axis_empty <= s_axis_raddr_gray == s_axis_waddr_gray_next;
+  end
+end
+
+always @(posedge m_axis_aclk)
+begin
+  if (s_axis_aresetn == 1'b0)
+    m_axis_valid <= 1'b0;
+  else begin
+    m_axis_valid <= m_axis_waddr_gray != m_axis_raddr_gray_next;
+  end
+end
+
+endmodule
+
diff --git a/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/address_gray_pipelined.v b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/address_gray_pipelined.v
new file mode 100644
index 000000000..ed7055b39
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/address_gray_pipelined.v
@@ -0,0 +1,151 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2013(c) Analog Devices, Inc.
+//  Author: Lars-Peter Clausen <lars@metafoo.de>
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+module fifo_address_gray_pipelined (
+  input m_axis_aclk,
+  input m_axis_aresetn,
+  input m_axis_ready,
+  output reg m_axis_valid,
+  output [ADDRESS_WIDTH-1:0] m_axis_raddr,
+  output reg [ADDRESS_WIDTH:0] m_axis_level,
+
+  input s_axis_aclk,
+  input s_axis_aresetn,
+  output reg s_axis_ready,
+  input s_axis_valid,
+  output reg s_axis_empty,
+  output [ADDRESS_WIDTH-1:0] s_axis_waddr,
+  output reg [ADDRESS_WIDTH:0] s_axis_room
+);
+
+parameter ADDRESS_WIDTH = 4;
+
+reg [ADDRESS_WIDTH:0] _s_axis_waddr = 'h00;
+reg [ADDRESS_WIDTH:0] _s_axis_waddr_next;
+wire [ADDRESS_WIDTH:0] _s_axis_raddr;
+
+reg [ADDRESS_WIDTH:0] _m_axis_raddr = 'h00;
+reg [ADDRESS_WIDTH:0] _m_axis_raddr_next;
+wire [ADDRESS_WIDTH:0] _m_axis_waddr;
+
+assign s_axis_waddr = _s_axis_waddr[ADDRESS_WIDTH-1:0];
+assign m_axis_raddr = _m_axis_raddr[ADDRESS_WIDTH-1:0];
+
+always @(*)
+begin
+  if (s_axis_ready && s_axis_valid)
+    _s_axis_waddr_next <= _s_axis_waddr + 1;
+  else
+    _s_axis_waddr_next <= _s_axis_waddr;
+end
+
+always @(posedge s_axis_aclk)
+begin
+  if (s_axis_aresetn == 1'b0) begin
+    _s_axis_waddr <= 'h00;
+  end else begin
+    _s_axis_waddr <= _s_axis_waddr_next;
+  end
+end
+
+always @(*)
+begin
+  if (m_axis_ready && m_axis_valid)
+    _m_axis_raddr_next <= _m_axis_raddr + 1;
+  else
+    _m_axis_raddr_next <= _m_axis_raddr;
+end
+
+always @(posedge m_axis_aclk)
+begin
+  if (m_axis_aresetn == 1'b0) begin
+    _m_axis_raddr <= 'h00;
+  end else begin
+    _m_axis_raddr <= _m_axis_raddr_next;
+  end
+end
+
+sync_gray #(
+  .DATA_WIDTH(ADDRESS_WIDTH + 1)
+) i_waddr_sync (
+  .in_clk(s_axis_aclk),
+  .in_resetn(s_axis_aresetn),
+  .out_clk(m_axis_aclk),
+  .out_resetn(m_axis_aresetn),
+  .in_count(_s_axis_waddr),
+  .out_count(_m_axis_waddr)
+);
+
+sync_gray #(
+  .DATA_WIDTH(ADDRESS_WIDTH + 1)
+) i_raddr_sync (
+  .in_clk(m_axis_aclk),
+  .in_resetn(m_axis_aresetn),
+  .out_clk(s_axis_aclk),
+  .out_resetn(s_axis_aresetn),
+  .in_count(_m_axis_raddr),
+  .out_count(_s_axis_raddr)
+);
+
+always @(posedge s_axis_aclk)
+begin
+  if (s_axis_aresetn == 1'b0) begin
+    s_axis_ready <= 1'b1;
+    s_axis_empty <= 1'b1;
+    s_axis_room <= 2**ADDRESS_WIDTH;
+  end else begin
+    s_axis_ready <= (_s_axis_raddr[ADDRESS_WIDTH] == _s_axis_waddr_next[ADDRESS_WIDTH] ||
+      _s_axis_raddr[ADDRESS_WIDTH-1:0] != _s_axis_waddr_next[ADDRESS_WIDTH-1:0]);
+    s_axis_empty <= _s_axis_raddr == _s_axis_waddr_next;
+    s_axis_room <= _s_axis_raddr - _s_axis_waddr_next + 2**ADDRESS_WIDTH;
+  end
+end
+
+always @(posedge m_axis_aclk)
+begin
+  if (m_axis_aresetn == 1'b0) begin
+    m_axis_valid <= 1'b0;
+    m_axis_level <= 'h00;
+  end else begin
+    m_axis_valid <= _m_axis_waddr != _m_axis_raddr_next;
+    m_axis_level <= _m_axis_waddr - _m_axis_raddr_next;
+  end
+end
+
+endmodule
+
diff --git a/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/address_sync.v b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/address_sync.v
new file mode 100644
index 000000000..6c94dba9c
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/address_sync.v
@@ -0,0 +1,108 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2013(c) Analog Devices, Inc.
+//  Author: Lars-Peter Clausen <lars@metafoo.de>
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+module fifo_address_sync (
+  input clk,
+  input resetn,
+
+  input m_axis_ready,
+  output reg m_axis_valid,
+  output reg  [ADDRESS_WIDTH-1:0] m_axis_raddr,
+  output [ADDRESS_WIDTH:0] m_axis_level,
+
+  output reg s_axis_ready,
+  input s_axis_valid,
+  output reg s_axis_empty,
+  output reg [ADDRESS_WIDTH-1:0] s_axis_waddr,
+  output [ADDRESS_WIDTH:0] s_axis_room
+);
+
+parameter ADDRESS_WIDTH = 4;
+
+reg [ADDRESS_WIDTH:0] room = 2**ADDRESS_WIDTH;
+reg [ADDRESS_WIDTH:0] level = 'h00;
+reg [ADDRESS_WIDTH:0] level_next;
+
+assign s_axis_room = room;
+assign m_axis_level = level;
+
+wire read = m_axis_ready & m_axis_valid;
+wire write = s_axis_ready & s_axis_valid;
+
+always @(posedge clk)
+begin
+  if (resetn == 1'b0) begin
+    s_axis_waddr <= 'h00;
+    m_axis_raddr <= 'h00;
+  end else begin
+    if (write)
+      s_axis_waddr <= s_axis_waddr + 1'b1;
+    if (read)
+      m_axis_raddr <= m_axis_raddr + 1'b1;
+  end
+end
+
+always @(*)
+begin
+  if (read & ~write)
+    level_next <= level - 1'b1;
+  else if (~read & write)
+    level_next <= level + 1'b1;
+  else
+    level_next <= level;
+end
+
+always @(posedge clk)
+begin
+  if (resetn == 1'b0) begin
+    m_axis_valid <= 1'b0;
+    s_axis_ready <= 1'b0;
+    level <= 'h00;
+    room <= 2**ADDRESS_WIDTH;
+    s_axis_empty <= 'h00;
+  end else begin
+    level <= level_next;
+    room <= 2**ADDRESS_WIDTH - level_next;
+    m_axis_valid <= level_next != 0;
+    s_axis_ready <= level_next != 2**ADDRESS_WIDTH;
+    s_axis_empty <= level_next == 0;
+  end
+end
+
+endmodule
+
diff --git a/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/component.xml b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/component.xml
new file mode 100644
index 000000000..44d9a2af4
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/component.xml
@@ -0,0 +1,542 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>analog.com</spirit:vendor>
+  <spirit:library>user</spirit:library>
+  <spirit:name>util_axis_fifo</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>S_AXIS</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_valid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_data</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_AXIS</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_valid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_data</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_AXIS_signal_clock</spirit:name>
+      <spirit:displayName>M_AXIS_signal_clock</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_aclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS_SIGNAL_CLOCK.ASSOCIATED_BUSIF">M_AXIS</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS_SIGNAL_CLOCK.ASSOCIATED_RESET">m_axis_aresetn</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_AXIS_signal_reset</spirit:name>
+      <spirit:displayName>M_AXIS_signal_reset</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_aresetn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS_SIGNAL_RESET.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S_AXIS_signal_clock</spirit:name>
+      <spirit:displayName>S_AXIS_signal_clock</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_aclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS_SIGNAL_CLOCK.ASSOCIATED_BUSIF">S_AXIS</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS_SIGNAL_CLOCK.ASSOCIATED_RESET">m_axis_aresetn</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S_AXIS_signal_reset</spirit:name>
+      <spirit:displayName>S_AXIS_signal_reset</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_aresetn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS_SIGNAL_RESET.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+        <spirit:displayName>Synthesis</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+        <spirit:language>Verilog</spirit:language>
+        <spirit:modelName>util_axis_fifo</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+        <spirit:displayName>Simulation</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:language>Verilog</spirit:language>
+        <spirit:modelName>util_axis_fifo</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_xpgui</spirit:name>
+        <spirit:displayName>UI Layout</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
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+          <spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
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+    </spirit:views>
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+        <spirit:name>m_axis_aclk</spirit:name>
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+        <spirit:name>m_axis_ready</spirit:name>
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+        <spirit:name>m_axis_valid</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>m_axis_data</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
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+          </spirit:vector>
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+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>m_axis_level</spirit:name>
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+            </spirit:wireTypeDef>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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+        <spirit:name>s_axis_aresetn</spirit:name>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axis_valid</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axis_data</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
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+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axis_empty</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axis_room</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.ADDRESS_WIDTH&apos;))">4</spirit:left>
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+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
+        <spirit:name>DATA_WIDTH</spirit:name>
+        <spirit:displayName>Data Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DATA_WIDTH">64</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>ASYNC_CLK</spirit:name>
+        <spirit:displayName>Async Clk</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ASYNC_CLK">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>ADDRESS_WIDTH</spirit:name>
+        <spirit:displayName>Address Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ADDRESS_WIDTH">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>S_AXIS_REGISTERED</spirit:name>
+        <spirit:displayName>S Axis Registered</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.S_AXIS_REGISTERED">1</spirit:value>
+      </spirit:modelParameter>
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+      <spirit:file>
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+        <spirit:fileType>verilogSource</spirit:fileType>
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+        <spirit:name>address_gray_pipelined.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>address_sync.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>util_axis_fifo.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>CHECKSUM_239993f9</spirit:userFileType>
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+      <spirit:file>
+        <spirit:name>sync_gray.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+      </spirit:file>
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+        <spirit:name>sync_bits.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
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+      <spirit:file>
+        <spirit:name>address_gray_pipelined.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
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+        <spirit:name>address_sync.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+      </spirit:file>
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+        <spirit:name>util_axis_fifo.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
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+      <spirit:file>
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+        <spirit:fileType>tclSource</spirit:fileType>
+        <spirit:userFileType>CHECKSUM_13c68e4c</spirit:userFileType>
+        <spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>util_axis_fifo_v1_0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>DATA_WIDTH</spirit:name>
+      <spirit:displayName>Data Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DATA_WIDTH">64</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ASYNC_CLK</spirit:name>
+      <spirit:displayName>Async Clk</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ASYNC_CLK">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ADDRESS_WIDTH</spirit:name>
+      <spirit:displayName>Address Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ADDRESS_WIDTH">4</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>S_AXIS_REGISTERED</spirit:name>
+      <spirit:displayName>S Axis Registered</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.S_AXIS_REGISTERED">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">util_axis_fifo_v1_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:supportedFamilies>
+        <xilinx:family xilinx:lifeCycle="Production">virtex7</xilinx:family>
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+      <xilinx:coreCreationDateTime>2017-04-20T23:50:31Z</xilinx:coreCreationDateTime>
+    </xilinx:coreExtensions>
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diff --git a/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/sync_bits.v b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/sync_bits.v
new file mode 100644
index 000000000..2530f047b
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/sync_bits.v
@@ -0,0 +1,76 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2013(c) Analog Devices, Inc.
+//  Author: Lars-Peter Clausen <lars@metafoo.de>
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+/*
+ * Helper module for synchronizing bit signals from one clock domain to another.
+ * It uses the standard approach of 2 FF in series.
+ * Note, that while the module allows to synchronize multiple bits at once it is
+ * only able to synchronize multi-bit signals where at max one bit changes per
+ * clock cycle (e.g. a gray counter).
+ */
+module sync_bits
+(
+  input [NUM_OF_BITS-1:0] in,
+  input out_resetn,
+  input out_clk,
+  output [NUM_OF_BITS-1:0] out
+);
+
+// Number of bits to synchronize
+parameter NUM_OF_BITS = 1;
+// Whether input and output clocks are asynchronous, if 0 the synchronizer will
+// be bypassed and the output signal equals the input signal.
+parameter ASYNC_CLK = 1;
+
+reg [NUM_OF_BITS-1:0] cdc_sync_stage1 = 'h0;
+reg [NUM_OF_BITS-1:0] cdc_sync_stage2 = 'h0;
+
+always @(posedge out_clk)
+begin
+  if (out_resetn == 1'b0) begin
+    cdc_sync_stage1 <= 'b0;
+    cdc_sync_stage2 <= 'b0;
+  end else begin
+    cdc_sync_stage1 <= in;
+    cdc_sync_stage2 <= cdc_sync_stage1;
+  end
+end
+
+assign out = ASYNC_CLK ? cdc_sync_stage2 : in;
+
+endmodule
diff --git a/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/sync_gray.v b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/sync_gray.v
new file mode 100644
index 000000000..2b67e1266
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/sync_gray.v
@@ -0,0 +1,111 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2013(c) Analog Devices, Inc.
+//  Author: Lars-Peter Clausen <lars@metafoo.de>
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+/*
+ * Helper module for synchronizing a counter from one clock domain to another
+ * using gray code. To work correctly the counter must not change its value by
+ * more than one in one clock cycle in the source domain. I.e. the value may
+ * change by either -1, 0 or +1.
+ */
+module sync_gray (
+  input in_clk,
+  input in_resetn,
+  input [DATA_WIDTH-1:0] in_count,
+  input out_resetn,
+  input out_clk,
+  output [DATA_WIDTH-1:0] out_count
+);
+
+// Bit-width of the counter
+parameter DATA_WIDTH = 1;
+// Whether the input and output clock are asynchronous, if set to 0 the
+// synchronizer will be bypassed and out_count will be in_count.
+parameter ASYNC_CLK = 1;
+
+reg [DATA_WIDTH-1:0] cdc_sync_stage0 = 'h0;
+reg [DATA_WIDTH-1:0] cdc_sync_stage1 = 'h0;
+reg [DATA_WIDTH-1:0] cdc_sync_stage2 = 'h0;
+reg [DATA_WIDTH-1:0] out_count_m = 'h0;
+
+function [DATA_WIDTH-1:0] g2b;
+  input [DATA_WIDTH-1:0] g;
+  reg   [DATA_WIDTH-1:0] b;
+  integer i;
+  begin
+    b[DATA_WIDTH-1] = g[DATA_WIDTH-1];
+    for (i = DATA_WIDTH - 2; i >= 0; i =  i - 1)
+      b[i] = b[i + 1] ^ g[i];
+    g2b = b;
+  end
+endfunction
+
+function [DATA_WIDTH-1:0] b2g;
+  input [DATA_WIDTH-1:0] b;
+  reg [DATA_WIDTH-1:0] g;
+  integer i;
+  begin
+    g[DATA_WIDTH-1] = b[DATA_WIDTH-1];
+    for (i = DATA_WIDTH - 2; i >= 0; i = i -1)
+        g[i] = b[i + 1] ^ b[i];
+    b2g = g;
+  end
+endfunction
+
+always @(posedge in_clk) begin
+  if (in_resetn == 1'b0) begin
+    cdc_sync_stage0 <= 'h00;
+  end else begin
+    cdc_sync_stage0 <= b2g(in_count);
+  end
+end
+
+always @(posedge out_clk) begin
+  if (out_resetn == 1'b0) begin
+    cdc_sync_stage1 <= 'h00;
+    cdc_sync_stage2 <= 'h00;
+    out_count_m <= 'h00;
+  end else begin
+    cdc_sync_stage1 <= cdc_sync_stage0;
+    cdc_sync_stage2 <= cdc_sync_stage1;
+    out_count_m <= g2b(cdc_sync_stage2);
+  end
+end
+
+assign out_count = ASYNC_CLK ? out_count_m : in_count;
+
+endmodule
diff --git a/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/util_axis_fifo.v b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/util_axis_fifo.v
new file mode 100644
index 000000000..f2661daa1
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/util_axis_fifo.v
@@ -0,0 +1,215 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2013(c) Analog Devices, Inc.
+//  Author: Lars-Peter Clausen <lars@metafoo.de>
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+// Source: git://github.com/analogdevicesinc/hdl.git
+// Commit hash: 04843795d8d6a496c00ee91b437d57924bc1cbf1
+
+module util_axis_fifo (
+  input m_axis_aclk,
+  input m_axis_aresetn,
+  input m_axis_ready,
+  output m_axis_valid,
+  output [DATA_WIDTH-1:0] m_axis_data,
+  output [ADDRESS_WIDTH:0] m_axis_level,
+
+  input s_axis_aclk,
+  input s_axis_aresetn,
+  output s_axis_ready,
+  input s_axis_valid,
+  input [DATA_WIDTH-1:0] s_axis_data,
+  output s_axis_empty,
+  output [ADDRESS_WIDTH:0] s_axis_room
+);
+
+parameter DATA_WIDTH = 64;
+parameter ASYNC_CLK = 1;
+parameter ADDRESS_WIDTH = 4;
+parameter S_AXIS_REGISTERED = 1;
+
+generate if (ADDRESS_WIDTH == 0) begin
+
+reg [DATA_WIDTH-1:0] cdc_sync_fifo_ram;
+reg s_axis_waddr = 1'b0;
+reg m_axis_raddr = 1'b0;
+
+wire m_axis_waddr;
+wire s_axis_raddr;
+
+sync_bits #(
+  .NUM_OF_BITS(1),
+  .ASYNC_CLK(ASYNC_CLK)
+) i_waddr_sync (
+  .out_clk(m_axis_aclk),
+  .out_resetn(m_axis_aresetn),
+  .in(s_axis_waddr),
+  .out(m_axis_waddr)
+);
+
+sync_bits #(
+  .NUM_OF_BITS(1),
+  .ASYNC_CLK(ASYNC_CLK)
+) i_raddr_sync (
+  .out_clk(s_axis_aclk),
+  .out_resetn(s_axis_aresetn),
+  .in(m_axis_raddr),
+  .out(s_axis_raddr)
+);
+
+assign m_axis_valid = m_axis_raddr != m_axis_waddr;
+assign m_axis_level = m_axis_valid;
+assign s_axis_ready = s_axis_raddr == s_axis_waddr;
+assign s_axis_empty = s_axis_ready;
+assign s_axis_room = s_axis_ready;
+
+always @(posedge s_axis_aclk) begin
+  if (s_axis_ready)
+    cdc_sync_fifo_ram <= s_axis_data;
+end
+
+always @(posedge s_axis_aclk) begin
+  if (s_axis_aresetn == 1'b0) begin
+    s_axis_waddr <= 1'b0;
+  end else begin
+    if (s_axis_ready & s_axis_valid) begin
+      s_axis_waddr <= s_axis_waddr + 1'b1;
+    end
+  end
+end
+
+always @(posedge m_axis_aclk) begin
+  if (m_axis_aresetn == 1'b0) begin
+    m_axis_raddr <= 1'b0;
+  end else begin
+    if (m_axis_valid & m_axis_ready)
+      m_axis_raddr <= m_axis_raddr + 1'b1;
+  end
+end
+
+assign m_axis_data = cdc_sync_fifo_ram;
+
+end else begin
+
+reg [DATA_WIDTH-1:0] ram[0:2**ADDRESS_WIDTH-1];
+
+wire [ADDRESS_WIDTH-1:0] s_axis_waddr;
+wire [ADDRESS_WIDTH-1:0] m_axis_raddr;
+wire _m_axis_ready;
+wire _m_axis_valid;
+
+if (ASYNC_CLK == 1) begin
+
+fifo_address_gray_pipelined #(
+  .ADDRESS_WIDTH(ADDRESS_WIDTH)
+) i_address_gray (
+  .m_axis_aclk(m_axis_aclk),
+  .m_axis_aresetn(m_axis_aresetn),
+  .m_axis_ready(_m_axis_ready),
+  .m_axis_valid(_m_axis_valid),
+  .m_axis_raddr(m_axis_raddr),
+  .m_axis_level(m_axis_level),
+
+  .s_axis_aclk(s_axis_aclk),
+  .s_axis_aresetn(s_axis_aresetn),
+  .s_axis_ready(s_axis_ready),
+  .s_axis_valid(s_axis_valid),
+  .s_axis_empty(s_axis_empty),
+  .s_axis_waddr(s_axis_waddr),
+  .s_axis_room(s_axis_room)
+);
+
+end else begin
+
+fifo_address_sync #(
+  .ADDRESS_WIDTH(ADDRESS_WIDTH)
+) i_address_sync (
+  .clk(m_axis_aclk),
+  .resetn(m_axis_aresetn),
+  .m_axis_ready(_m_axis_ready),
+  .m_axis_valid(_m_axis_valid),
+  .m_axis_raddr(m_axis_raddr),
+  .m_axis_level(m_axis_level),
+
+  .s_axis_ready(s_axis_ready),
+  .s_axis_valid(s_axis_valid),
+  .s_axis_empty(s_axis_empty),
+  .s_axis_waddr(s_axis_waddr),
+  .s_axis_room(s_axis_room)
+);
+
+end
+
+always @(posedge s_axis_aclk) begin
+  if (s_axis_ready)
+    ram[s_axis_waddr] <= s_axis_data;
+end
+
+if (S_AXIS_REGISTERED == 1) begin
+
+reg [DATA_WIDTH-1:0] data;
+reg valid;
+
+always @(posedge m_axis_aclk) begin
+  if (m_axis_aresetn == 1'b0) begin
+    valid <= 1'b0;
+  end else begin
+    if (_m_axis_valid)
+      valid <= 1'b1;
+    else if (m_axis_ready)
+      valid <= 1'b0;
+  end
+end
+
+always @(posedge m_axis_aclk) begin
+  if (~valid || m_axis_ready)
+    data <= ram[m_axis_raddr];
+end
+
+assign _m_axis_ready = ~valid || m_axis_ready;
+assign m_axis_data = data;
+assign m_axis_valid = valid;
+
+end else begin
+
+assign _m_axis_ready = m_axis_ready;
+assign m_axis_valid = _m_axis_valid;
+assign m_axis_data = ram[m_axis_raddr];
+
+end
+
+end endgenerate
+
+endmodule
diff --git a/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/util_axis_fifo_ip.tcl b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/util_axis_fifo_ip.tcl
new file mode 100644
index 000000000..014409288
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/util_axis_fifo_ip.tcl
@@ -0,0 +1,38 @@
+
+source ../scripts/adi_env.tcl
+source $ad_hdl_dir/library/scripts/adi_ip.tcl
+
+adi_ip_create util_axis_fifo
+adi_ip_files util_axis_fifo [list \
+	"$ad_hdl_dir/library/common/sync_bits.v" \
+	"$ad_hdl_dir/library/common/sync_gray.v" \
+	"address_gray.v" \
+	"address_gray_pipelined.v" \
+	"address_sync.v" \
+	"util_axis_fifo.v" \
+]
+
+adi_ip_properties_lite util_axis_fifo
+
+adi_add_bus "S_AXIS" "slave" \
+	"xilinx.com:interface:axis_rtl:1.0" \
+	"xilinx.com:interface:axis:1.0" \
+	{
+		{"s_axis_valid" "TVALID"} \
+		{"s_axis_ready" "TREADY"} \
+		{"s_axis_data" "TDATA"} \
+	}
+
+adi_add_bus "M_AXIS" "master" \
+	"xilinx.com:interface:axis_rtl:1.0" \
+	"xilinx.com:interface:axis:1.0" \
+	{
+		{"m_axis_valid" "TVALID"} \
+		{"m_axis_ready" "TREADY"} \
+		{"m_axis_data" "TDATA"} \
+	}
+
+adi_add_bus_clock "m_axis_aclk" "M_AXIS" "m_axis_aresetn"
+adi_add_bus_clock "s_axis_aclk" "S_AXIS" "m_axis_aresetn"
+
+ipx::save_core [ipx::current_core]
diff --git a/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/xgui/util_axis_fifo_v1_0.tcl b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/xgui/util_axis_fifo_v1_0.tcl
new file mode 100644
index 000000000..0f2092e6a
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/xgui/util_axis_fifo_v1_0.tcl
@@ -0,0 +1,70 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+  ipgui::add_param $IPINST -name "ADDRESS_WIDTH" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "ASYNC_CLK" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "DATA_WIDTH" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "S_AXIS_REGISTERED" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.ADDRESS_WIDTH { PARAM_VALUE.ADDRESS_WIDTH } {
+	# Procedure called to update ADDRESS_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.ADDRESS_WIDTH { PARAM_VALUE.ADDRESS_WIDTH } {
+	# Procedure called to validate ADDRESS_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.ASYNC_CLK { PARAM_VALUE.ASYNC_CLK } {
+	# Procedure called to update ASYNC_CLK when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.ASYNC_CLK { PARAM_VALUE.ASYNC_CLK } {
+	# Procedure called to validate ASYNC_CLK
+	return true
+}
+
+proc update_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } {
+	# Procedure called to update DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } {
+	# Procedure called to validate DATA_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.S_AXIS_REGISTERED { PARAM_VALUE.S_AXIS_REGISTERED } {
+	# Procedure called to update S_AXIS_REGISTERED when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.S_AXIS_REGISTERED { PARAM_VALUE.S_AXIS_REGISTERED } {
+	# Procedure called to validate S_AXIS_REGISTERED
+	return true
+}
+
+
+proc update_MODELPARAM_VALUE.DATA_WIDTH { MODELPARAM_VALUE.DATA_WIDTH PARAM_VALUE.DATA_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.DATA_WIDTH}] ${MODELPARAM_VALUE.DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.ASYNC_CLK { MODELPARAM_VALUE.ASYNC_CLK PARAM_VALUE.ASYNC_CLK } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.ASYNC_CLK}] ${MODELPARAM_VALUE.ASYNC_CLK}
+}
+
+proc update_MODELPARAM_VALUE.ADDRESS_WIDTH { MODELPARAM_VALUE.ADDRESS_WIDTH PARAM_VALUE.ADDRESS_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.ADDRESS_WIDTH}] ${MODELPARAM_VALUE.ADDRESS_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.S_AXIS_REGISTERED { MODELPARAM_VALUE.S_AXIS_REGISTERED PARAM_VALUE.S_AXIS_REGISTERED } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.S_AXIS_REGISTERED}] ${MODELPARAM_VALUE.S_AXIS_REGISTERED}
+}
+
diff --git a/fpga/usrp3/lib/vivado_ipi/util_axis_resize/component.xml b/fpga/usrp3/lib/vivado_ipi/util_axis_resize/component.xml
new file mode 100644
index 000000000..1b502fdf5
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/util_axis_resize/component.xml
@@ -0,0 +1,373 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>analog.com</spirit:vendor>
+  <spirit:library>user</spirit:library>
+  <spirit:name>util_axis_resize</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>s_axis</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_valid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_data</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>m_axis</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_valid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_data</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>s_axis_m_axis_signal_clock</spirit:name>
+      <spirit:displayName>s_axis_m_axis_signal_clock</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS_M_AXIS_SIGNAL_CLOCK.ASSOCIATED_BUSIF">s_axis:m_axis</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS_M_AXIS_SIGNAL_CLOCK.ASSOCIATED_RESET">resetn</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>s_axis_m_axis_signal_reset</spirit:name>
+      <spirit:displayName>s_axis_m_axis_signal_reset</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>resetn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS_M_AXIS_SIGNAL_RESET.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+        <spirit:displayName>Synthesis</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+        <spirit:language>Verilog</spirit:language>
+        <spirit:modelName>util_axis_resize</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+        <spirit:displayName>Simulation</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:language>Verilog</spirit:language>
+        <spirit:modelName>util_axis_resize</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_xpgui</spirit:name>
+        <spirit:displayName>UI Layout</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+      </spirit:view>
+    </spirit:views>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>resetn</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_valid</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_ready</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_data</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.SLAVE_DATA_WIDTH&apos;)) - 1)">63</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>m_valid</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>m_ready</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>m_data</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.MASTER_DATA_WIDTH&apos;)) - 1)">63</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
+        <spirit:name>MASTER_DATA_WIDTH</spirit:name>
+        <spirit:displayName>Master Data Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MASTER_DATA_WIDTH">64</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>SLAVE_DATA_WIDTH</spirit:name>
+        <spirit:displayName>Slave Data Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SLAVE_DATA_WIDTH">64</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>BIG_ENDIAN</spirit:name>
+        <spirit:displayName>Big Endian</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BIG_ENDIAN">0</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:fileSets>
+    <spirit:fileSet>
+      <spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>util_axis_resize.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>CHECKSUM_2fed12e2</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>util_axis_resize.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_xpgui_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>xgui/util_axis_resize_v1_0.tcl</spirit:name>
+        <spirit:fileType>tclSource</spirit:fileType>
+        <spirit:userFileType>CHECKSUM_9664bffc</spirit:userFileType>
+        <spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>util_axis_resize_v1_0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>MASTER_DATA_WIDTH</spirit:name>
+      <spirit:displayName>Master Data Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MASTER_DATA_WIDTH">64</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>SLAVE_DATA_WIDTH</spirit:name>
+      <spirit:displayName>Slave Data Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SLAVE_DATA_WIDTH">64</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>BIG_ENDIAN</spirit:name>
+      <spirit:displayName>Big Endian</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.BIG_ENDIAN">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">util_axis_resize_v1_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:supportedFamilies>
+        <xilinx:family xilinx:lifeCycle="Production">virtex7</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">qvirtex7</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">kintex7</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">kintex7l</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">qkintex7</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">qkintex7l</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">artix7</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">artix7l</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">aartix7</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">qartix7</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">qzynq</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">azynq</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">virtexu</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">kintexuplus</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">zynquplus</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">kintexu</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Beta">virtexuplus</xilinx:family>
+      </xilinx:supportedFamilies>
+      <xilinx:taxonomies>
+        <xilinx:taxonomy>/Analog_Devices</xilinx:taxonomy>
+      </xilinx:taxonomies>
+      <xilinx:displayName>util_axis_resize_v1_0</xilinx:displayName>
+      <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
+      <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+      <xilinx:coreCreationDateTime>2017-04-20T23:54:03Z</xilinx:coreCreationDateTime>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2015.4</xilinx:xilinxVersion>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/fpga/usrp3/lib/vivado_ipi/util_axis_resize/util_axis_resize.v b/fpga/usrp3/lib/vivado_ipi/util_axis_resize/util_axis_resize.v
new file mode 100644
index 000000000..5dcd9518a
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/util_axis_resize/util_axis_resize.v
@@ -0,0 +1,156 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2013(c) Analog Devices, Inc.
+//  Author: Lars-Peter Clausen <lars@metafoo.de>
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+// Source: git://github.com/analogdevicesinc/hdl.git
+// Commit hash: 04843795d8d6a496c00ee91b437d57924bc1cbf1
+
+module util_axis_resize (
+  input                       clk,
+  input                       resetn,
+
+  input                       s_valid,
+  output                      s_ready,
+  input [SLAVE_DATA_WIDTH-1:0]  s_data,
+
+  output                      m_valid,
+  input                       m_ready,
+  output [MASTER_DATA_WIDTH-1:0] m_data
+);
+
+parameter MASTER_DATA_WIDTH = 64;
+parameter SLAVE_DATA_WIDTH = 64;
+parameter BIG_ENDIAN = 0;
+
+generate if (SLAVE_DATA_WIDTH == MASTER_DATA_WIDTH) begin
+
+assign m_valid = s_valid;
+assign s_ready = m_ready;
+assign m_data = s_data;
+
+end else if (SLAVE_DATA_WIDTH < MASTER_DATA_WIDTH) begin
+
+localparam RATIO = MASTER_DATA_WIDTH / SLAVE_DATA_WIDTH;
+
+reg [MASTER_DATA_WIDTH-1:0] data;
+reg [$clog2(RATIO)-1:0] count;
+reg valid;
+
+always @(posedge clk)
+begin
+  if (resetn == 1'b0) begin
+    count <= RATIO - 1;
+    valid <= 1'b0;
+  end else begin
+    if (count == 'h00 && s_ready == 1'b1 && s_valid == 1'b1)
+      valid <= 1'b1;
+    else if (m_ready == 1'b1)
+      valid <= 1'b0;
+
+    if (s_ready == 1'b1 && s_valid == 1'b1) begin
+      if (count == 'h00)
+        count <= RATIO - 1;
+      else
+        count <= count - 1'b1;
+    end
+  end
+end
+
+always @(posedge clk)
+begin
+  if (s_ready == 1'b1 && s_valid == 1'b1)
+    if (BIG_ENDIAN == 1) begin
+      data <= {data[MASTER_DATA_WIDTH-SLAVE_DATA_WIDTH-1:0], s_data};
+    end else begin
+      data <= {s_data, data[MASTER_DATA_WIDTH-1:SLAVE_DATA_WIDTH]};
+    end
+end
+
+assign s_ready = ~valid || m_ready;
+assign m_valid = valid;
+assign m_data = data;
+
+end else begin
+
+localparam RATIO = SLAVE_DATA_WIDTH / MASTER_DATA_WIDTH;
+
+reg [SLAVE_DATA_WIDTH-1:0] data;
+reg [$clog2(RATIO)-1:0] count;
+reg valid;
+
+always @(posedge clk)
+begin
+  if (resetn == 1'b0) begin
+    count <= RATIO - 1;
+    valid <= 1'b0;
+  end else begin
+    if (s_valid == 1'b1 && s_ready == 1'b1)
+      valid <= 1'b1;
+    else if (count == 'h0 && m_ready == 1'b1 && m_valid == 1'b1)
+      valid <= 1'b0;
+
+    if (m_ready == 1'b1 && m_valid == 1'b1) begin
+      if (count == 'h00)
+        count <= RATIO - 1;
+      else
+        count <= count - 1'b1;
+    end
+  end
+end
+
+always @(posedge clk)
+begin
+  if (s_ready == 1'b1 && s_valid == 1'b1) begin
+    data <= s_data;
+  end else if (m_ready == 1'b1 && m_valid == 1'b1) begin
+    if (BIG_ENDIAN == 1) begin
+      data[SLAVE_DATA_WIDTH-1:MASTER_DATA_WIDTH] <= data[SLAVE_DATA_WIDTH-MASTER_DATA_WIDTH-1:0];
+    end else begin
+      data[SLAVE_DATA_WIDTH-MASTER_DATA_WIDTH-1:0] <= data[SLAVE_DATA_WIDTH-1:MASTER_DATA_WIDTH];
+    end
+  end
+end
+
+assign s_ready = ~valid || (m_ready && count == 'h0);
+assign m_valid = valid;
+assign m_data = BIG_ENDIAN == 1 ?
+  data[SLAVE_DATA_WIDTH-1:SLAVE_DATA_WIDTH-MASTER_DATA_WIDTH] :
+  data[MASTER_DATA_WIDTH-1:0];
+
+end
+endgenerate
+
+endmodule
diff --git a/fpga/usrp3/lib/vivado_ipi/util_axis_resize/xgui/util_axis_resize_v1_0.tcl b/fpga/usrp3/lib/vivado_ipi/util_axis_resize/xgui/util_axis_resize_v1_0.tcl
new file mode 100644
index 000000000..5d2fe72d8
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/util_axis_resize/xgui/util_axis_resize_v1_0.tcl
@@ -0,0 +1,55 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+  ipgui::add_param $IPINST -name "BIG_ENDIAN" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "MASTER_DATA_WIDTH" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "SLAVE_DATA_WIDTH" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.BIG_ENDIAN { PARAM_VALUE.BIG_ENDIAN } {
+	# Procedure called to update BIG_ENDIAN when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.BIG_ENDIAN { PARAM_VALUE.BIG_ENDIAN } {
+	# Procedure called to validate BIG_ENDIAN
+	return true
+}
+
+proc update_PARAM_VALUE.MASTER_DATA_WIDTH { PARAM_VALUE.MASTER_DATA_WIDTH } {
+	# Procedure called to update MASTER_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.MASTER_DATA_WIDTH { PARAM_VALUE.MASTER_DATA_WIDTH } {
+	# Procedure called to validate MASTER_DATA_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.SLAVE_DATA_WIDTH { PARAM_VALUE.SLAVE_DATA_WIDTH } {
+	# Procedure called to update SLAVE_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.SLAVE_DATA_WIDTH { PARAM_VALUE.SLAVE_DATA_WIDTH } {
+	# Procedure called to validate SLAVE_DATA_WIDTH
+	return true
+}
+
+
+proc update_MODELPARAM_VALUE.MASTER_DATA_WIDTH { MODELPARAM_VALUE.MASTER_DATA_WIDTH PARAM_VALUE.MASTER_DATA_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.MASTER_DATA_WIDTH}] ${MODELPARAM_VALUE.MASTER_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.SLAVE_DATA_WIDTH { MODELPARAM_VALUE.SLAVE_DATA_WIDTH PARAM_VALUE.SLAVE_DATA_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.SLAVE_DATA_WIDTH}] ${MODELPARAM_VALUE.SLAVE_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.BIG_ENDIAN { MODELPARAM_VALUE.BIG_ENDIAN PARAM_VALUE.BIG_ENDIAN } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.BIG_ENDIAN}] ${MODELPARAM_VALUE.BIG_ENDIAN}
+}
+
diff --git a/fpga/usrp3/lib/wb_spi/Makefile.srcs b/fpga/usrp3/lib/wb_spi/Makefile.srcs
new file mode 100644
index 000000000..43048a126
--- /dev/null
+++ b/fpga/usrp3/lib/wb_spi/Makefile.srcs
@@ -0,0 +1,14 @@
+#
+# Copyright 2013 Ettus Research LLC
+#
+
+##################################################
+# Control Lib Sources
+##################################################
+WB_SPI_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/wb_spi/, \
+rtl/verilog/spi_clgen.v \
+rtl/verilog/spi_defines.v \
+rtl/verilog/spi_shift.v \
+rtl/verilog/spi_top16.v \
+rtl/verilog/spi_top.v \
+))
diff --git a/fpga/usrp3/lib/wb_spi/bench/verilog/spi_slave_model.v b/fpga/usrp3/lib/wb_spi/bench/verilog/spi_slave_model.v
new file mode 100644
index 000000000..dfdaed929
--- /dev/null
+++ b/fpga/usrp3/lib/wb_spi/bench/verilog/spi_slave_model.v
@@ -0,0 +1,73 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  spi_slave_model.v                                           ////
+////                                                              ////
+////  This file is part of the SPI IP core project                ////
+////  http://www.opencores.org/projects/spi/                      ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Simon Srot (simons@opencores.org)                     ////
+////                                                              ////
+////  All additional information is avaliable in the Readme.txt   ////
+////  file.                                                       ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2002 Authors                                   ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+`include "timescale.v"
+
+module spi_slave_model (rst, ss, sclk, mosi, miso);
+
+  input         rst;            // reset
+  input         ss;             // slave select
+  input         sclk;           // serial clock
+  input         mosi;           // master out slave in
+  output        miso;           // master in slave out
+
+  reg           miso;
+
+  reg           rx_negedge;     // slave receiving on negedge
+  reg           tx_negedge;     // slave transmiting on negedge
+  reg    [31:0] data;           // data register
+
+  parameter     Tp = 1;
+
+  always @(posedge(sclk && !rx_negedge) or negedge(sclk && rx_negedge) or rst)
+  begin
+    if (rst)
+      data <= #Tp 32'b0;
+    else if (!ss)
+      data <= #Tp {data[30:0], mosi};
+  end
+
+  always @(posedge(sclk && !tx_negedge) or negedge(sclk && tx_negedge))
+  begin
+    miso <= #Tp data[31];
+  end
+
+endmodule
+      
diff --git a/fpga/usrp3/lib/wb_spi/bench/verilog/tb_spi_top.v b/fpga/usrp3/lib/wb_spi/bench/verilog/tb_spi_top.v
new file mode 100644
index 000000000..529c0aca1
--- /dev/null
+++ b/fpga/usrp3/lib/wb_spi/bench/verilog/tb_spi_top.v
@@ -0,0 +1,339 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  tb_spi_top.v                                                ////
+////                                                              ////
+////  This file is part of the SPI IP core project                ////
+////  http://www.opencores.org/projects/spi/                      ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Simon Srot (simons@opencores.org)                     ////
+////                                                              ////
+////  Based on:                                                   ////
+////      - i2c/bench/verilog/tst_bench_top.v                     ////
+////        Copyright (C) 2001 Richard Herveille                  ////
+////                                                              ////
+////  All additional information is avaliable in the Readme.txt   ////
+////  file.                                                       ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2002 Authors                                   ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+`include "timescale.v"
+
+module tb_spi_top();
+
+  reg         clk;
+  reg         rst;
+  wire [31:0] adr;
+  wire [31:0] dat_i, dat_o;
+  wire        we;
+  wire  [3:0] sel;
+  wire        stb;
+  wire        cyc;
+  wire        ack;
+  wire        err;
+  wire        int;
+
+  wire  [7:0] ss;
+  wire        sclk;
+  wire        mosi;
+  wire        miso;
+
+  reg  [31:0] q;
+  reg  [31:0] q1;
+  reg  [31:0] q2;
+  reg  [31:0] q3;
+  reg  [31:0] result;
+
+  parameter SPI_RX_0   = 5'h0;
+  parameter SPI_RX_1   = 5'h4;
+  parameter SPI_RX_2   = 5'h8;
+  parameter SPI_RX_3   = 5'hc;
+  parameter SPI_TX_0   = 5'h0;
+  parameter SPI_TX_1   = 5'h4;
+  parameter SPI_TX_2   = 5'h8;
+  parameter SPI_TX_3   = 5'hc;
+  parameter SPI_CTRL   = 5'h10;
+  parameter SPI_DIVIDE = 5'h14;
+  parameter SPI_SS     = 5'h18;
+
+  // Generate clock
+  always #5 clk = ~clk;
+
+  // Wishbone master model
+  wb_master_model #(32, 32) i_wb_master (
+    .clk(clk), .rst(rst),
+    .adr(adr), .din(dat_i), .dout(dat_o),
+    .cyc(cyc), .stb(stb), .we(we), .sel(sel), .ack(ack), .err(err), .rty(1'b0)
+  );
+
+  // SPI master core
+  spi_top i_spi_top (
+    .wb_clk_i(clk), .wb_rst_i(rst), 
+    .wb_adr_i(adr[4:0]), .wb_dat_i(dat_o), .wb_dat_o(dat_i), 
+    .wb_sel_i(sel), .wb_we_i(we), .wb_stb_i(stb), 
+    .wb_cyc_i(cyc), .wb_ack_o(ack), .wb_err_o(err), .wb_int_o(int),
+    .ss_pad_o(ss), .sclk_pad_o(sclk), .mosi_pad_o(mosi), .miso_pad_i(miso) 
+  );
+
+  // SPI slave model
+  spi_slave_model i_spi_slave (
+    .rst(rst), .ss(ss[0]), .sclk(sclk), .mosi(mosi), .miso(miso)
+  );
+
+  initial
+    begin
+      $display("\nstatus: %t Testbench started\n\n", $time);
+
+      $dumpfile("bench.vcd");
+      $dumpvars(1, tb_spi_top);
+      $dumpvars(1, tb_spi_top.i_spi_slave);
+
+      // Initial values
+      clk = 0;
+
+      i_spi_slave.rx_negedge = 1'b0;
+      i_spi_slave.tx_negedge = 1'b0;
+
+      result = 32'h0;
+
+      // Reset system
+      rst = 1'b0; // negate reset
+      #2;
+      rst = 1'b1; // assert reset
+      repeat(20) @(posedge clk);
+      rst = 1'b0; // negate reset
+
+      $display("status: %t done reset", $time);
+      
+      @(posedge clk);
+
+      // Program core
+      i_wb_master.wb_write(0, SPI_DIVIDE, 32'h00); // set devider register
+      i_wb_master.wb_write(0, SPI_TX_0, 32'h5a);   // set tx register to 0x5a
+      i_wb_master.wb_write(0, SPI_CTRL, 32'h208);   // set 8 bit transfer
+      i_wb_master.wb_write(0, SPI_SS, 32'h01);     // set ss 0
+
+      $display("status: %t programmed registers", $time);
+
+      i_wb_master.wb_cmp(0, SPI_DIVIDE, 32'h00);   // verify devider register
+      i_wb_master.wb_cmp(0, SPI_TX_0, 32'h5a);     // verify tx register
+      i_wb_master.wb_cmp(0, SPI_CTRL, 32'h208);     // verify tx register
+      i_wb_master.wb_cmp(0, SPI_SS, 32'h01);       // verify ss register
+
+      $display("status: %t verified registers", $time);
+
+      i_spi_slave.rx_negedge = 1'b1;
+      i_spi_slave.tx_negedge = 1'b0;
+      i_spi_slave.data[31:0] = 32'ha5967e5a;
+      i_wb_master.wb_write(0, SPI_CTRL, 32'h308);   // set 8 bit transfer, start transfer
+
+      $display("status: %t generate transfer:  8 bit, msb first, tx posedge, rx negedge", $time);
+
+      // Check bsy bit
+      i_wb_master.wb_read(0, SPI_CTRL, q);
+      while (q[8])
+        i_wb_master.wb_read(1, SPI_CTRL, q);
+
+      i_wb_master.wb_read(1, SPI_RX_0, q);
+      result = result + q;
+
+      if (i_spi_slave.data[7:0] == 8'h5a && q == 32'h000000a5)
+        $display("status: %t transfer completed: ok", $time);
+      else
+        $display("status: %t transfer completed: nok", $time);
+
+      i_spi_slave.rx_negedge = 1'b0;
+      i_spi_slave.tx_negedge = 1'b1;
+      i_wb_master.wb_write(0, SPI_TX_0, 32'ha5);
+      i_wb_master.wb_write(0, SPI_CTRL, 32'h408);   // set 8 bit transfer, tx negedge
+      i_wb_master.wb_write(0, SPI_CTRL, 32'h508);   // set 8 bit transfer, tx negedge, start transfer
+
+      $display("status: %t generate transfer:  8 bit, msb first, tx negedge, rx posedge", $time);
+
+      // Check bsy bit
+      i_wb_master.wb_read(0, SPI_CTRL, q);
+      while (q[8])
+        i_wb_master.wb_read(1, SPI_CTRL, q);
+
+      i_wb_master.wb_read(1, SPI_RX_0, q);
+      result = result + q;
+
+      if (i_spi_slave.data[7:0] == 8'ha5 && q == 32'h00000096)
+        $display("status: %t transfer completed: ok", $time);
+      else
+        $display("status: %t transfer completed: nok", $time);
+
+      i_spi_slave.rx_negedge = 1'b0;
+      i_spi_slave.tx_negedge = 1'b1;
+      i_wb_master.wb_write(0, SPI_TX_0, 32'h5aa5);
+      i_wb_master.wb_write(0, SPI_CTRL, 32'hc10);   // set 16 bit transfer, tx negedge, lsb
+      i_wb_master.wb_write(0, SPI_CTRL, 32'hd10);   // set 16 bit transfer, tx negedge, start transfer
+
+      $display("status: %t generate transfer: 16 bit, lsb first, tx negedge, rx posedge", $time);
+
+      // Check bsy bit
+      i_wb_master.wb_read(0, SPI_CTRL, q);
+      while (q[8])
+        i_wb_master.wb_read(1, SPI_CTRL, q);
+
+      i_wb_master.wb_read(1, SPI_RX_0, q);
+      result = result + q;
+
+      if (i_spi_slave.data[15:0] == 16'ha55a && q == 32'h00005a7e)
+        $display("status: %t transfer completed: ok", $time);
+      else
+        $display("status: %t transfer completed: nok", $time);
+
+      i_spi_slave.rx_negedge = 1'b1;
+      i_spi_slave.tx_negedge = 1'b0;
+      i_wb_master.wb_write(0, SPI_TX_0, 32'h76543210);
+      i_wb_master.wb_write(0, SPI_TX_1, 32'hfedcba98);
+      i_wb_master.wb_write(0, SPI_CTRL, 32'h1a40);   // set 64 bit transfer, rx negedge, lsb
+      i_wb_master.wb_write(0, SPI_CTRL, 32'h1b40);   // set 64 bit transfer, rx negedge, start transfer
+
+      $display("status: %t generate transfer: 64 bit, lsb first, tx posedge, rx negedge", $time);
+
+      // Check bsy bit
+      i_wb_master.wb_read(0, SPI_CTRL, q);
+      while (q[8])
+        i_wb_master.wb_read(1, SPI_CTRL, q);
+
+      i_wb_master.wb_read(1, SPI_RX_0, q);
+      result = result + q;
+      i_wb_master.wb_read(1, SPI_RX_1, q1);
+      result = result + q1;
+
+      if (i_spi_slave.data == 32'h195d3b7f && q == 32'h5aa5a55a && q1 == 32'h76543210)
+        $display("status: %t transfer completed: ok", $time);
+      else
+        $display("status: %t transfer completed: nok", $time);
+
+      i_spi_slave.rx_negedge = 1'b0;
+      i_spi_slave.tx_negedge = 1'b1;
+      i_wb_master.wb_write(0, SPI_TX_0, 32'hccddeeff);
+      i_wb_master.wb_write(0, SPI_TX_1, 32'h8899aabb);
+      i_wb_master.wb_write(0, SPI_TX_2, 32'h44556677);
+      i_wb_master.wb_write(0, SPI_TX_3, 32'h00112233);
+      i_wb_master.wb_write(0, SPI_CTRL, 32'h400);
+      i_wb_master.wb_write(0, SPI_CTRL, 32'h500);
+
+      $display("status: %t generate transfer: 128 bit, msb first, tx posedge, rx negedge", $time);
+
+      // Check bsy bit
+      i_wb_master.wb_read(0, SPI_CTRL, q);
+      while (q[8])
+        i_wb_master.wb_read(1, SPI_CTRL, q);
+
+      i_wb_master.wb_read(1, SPI_RX_0, q);
+      result = result + q;
+      i_wb_master.wb_read(1, SPI_RX_1, q1);
+      result = result + q1;
+      i_wb_master.wb_read(1, SPI_RX_2, q2);
+      result = result + q2;
+      i_wb_master.wb_read(1, SPI_RX_3, q3);
+      result = result + q3;
+
+      if (i_spi_slave.data == 32'hccddeeff && q == 32'h8899aabb && q1 == 32'h44556677 && q2 == 32'h00112233 && q3 == 32'h195d3b7f)
+        $display("status: %t transfer completed: ok", $time);
+      else
+        $display("status: %t transfer completed: nok", $time);
+
+      i_spi_slave.rx_negedge = 1'b0;
+      i_spi_slave.tx_negedge = 1'b1;
+      i_wb_master.wb_write(0, SPI_TX_0, 32'haa55a5a5);
+      i_wb_master.wb_write(0, SPI_CTRL, 32'h1420);
+      i_wb_master.wb_write(0, SPI_CTRL, 32'h1520);
+
+      $display("status: %t generate transfer: 32 bit, msb first, tx negedge, rx posedge, ie", $time);
+
+      // Check interrupt signal
+      while (!int)
+        @(posedge clk);
+
+      i_wb_master.wb_read(1, SPI_RX_0, q);
+      result = result + q;
+    
+      @(posedge clk);
+      if (!int && i_spi_slave.data == 32'haa55a5a5 && q == 32'hccddeeff)
+        $display("status: %t transfer completed: ok", $time);
+      else
+        $display("status: %t transfer completed: nok", $time);
+
+      i_spi_slave.rx_negedge = 1'b1;
+      i_spi_slave.tx_negedge = 1'b0;
+      i_wb_master.wb_write(0, SPI_TX_0, 32'h01248421);
+      i_wb_master.wb_write(0, SPI_CTRL, 32'h3220);
+      i_wb_master.wb_write(0, SPI_CTRL, 32'h3320);
+
+      $display("status: %t generate transfer: 32 bit, msb first, tx posedge, rx negedge, ie, ass", $time);
+
+      while (!int)
+        @(posedge clk);
+
+      i_wb_master.wb_read(1, SPI_RX_0, q);
+      result = result + q;
+
+      @(posedge clk);
+      if (!int && i_spi_slave.data == 32'h01248421 && q == 32'haa55a5a5)
+        $display("status: %t transfer completed: ok", $time);
+      else
+        $display("status: %t transfer completed: nok", $time);
+
+      i_spi_slave.rx_negedge = 1'b1;
+      i_spi_slave.tx_negedge = 1'b0;
+      i_wb_master.wb_write(0, SPI_TX_0, 32'h1);
+      i_wb_master.wb_write(0, SPI_CTRL, 32'h3201);
+      i_wb_master.wb_write(0, SPI_CTRL, 32'h3301);
+
+      $display("status: %t generate transfer: 1 bit, msb first, tx posedge, rx negedge, ie, ass", $time);
+
+      while (!int)
+        @(posedge clk);
+
+      i_wb_master.wb_read(1, SPI_RX_0, q);
+      result = result + q;
+
+      @(posedge clk);
+      if (!int && i_spi_slave.data == 32'h02490843 && q == 32'h0)
+        $display("status: %t transfer completed: ok", $time);
+      else
+        $display("status: %t transfer completed: nok", $time);
+
+      $display("\n\nstatus: %t Testbench done", $time);
+
+      #25000; // wait 25us
+
+      $display("report (%h)", (result ^ 32'h2e8b36ab) + 32'hdeaddead);
+      $display("exit (%h)", result ^ 32'h2e8b36ab);
+
+      $stop;
+    end
+
+endmodule
+
+
diff --git a/fpga/usrp3/lib/wb_spi/bench/verilog/wb_master_model.v b/fpga/usrp3/lib/wb_spi/bench/verilog/wb_master_model.v
new file mode 100644
index 000000000..3f8b7ee6a
--- /dev/null
+++ b/fpga/usrp3/lib/wb_spi/bench/verilog/wb_master_model.v
@@ -0,0 +1,176 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  wb_master_model.v                                           ////
+////                                                              ////
+////  This file is part of the SPI IP core project                ////
+////  http://www.opencores.org/projects/spi/                      ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Simon Srot (simons@opencores.org)                     ////
+////                                                              ////
+////  Based on:                                                   ////
+////      - i2c/bench/verilog/wb_master_model.v                   ////
+////        Copyright (C) 2001 Richard Herveille                  ////
+////                                                              ////
+////  All additional information is avaliable in the Readme.txt   ////
+////  file.                                                       ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2002 Authors                                   ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+`include "timescale.v"
+
+module wb_master_model(clk, rst, adr, din, dout, cyc, stb, we, sel, ack, err, rty);
+
+  parameter dwidth = 32;
+  parameter awidth = 32;
+  
+  input                  clk, rst;
+  output [awidth   -1:0] adr;
+  input  [dwidth   -1:0] din;
+  output [dwidth   -1:0] dout;
+  output                 cyc, stb;
+  output                 we;
+  output [dwidth/8 -1:0] sel;
+  input                  ack, err, rty;
+  
+  // Internal signals
+  reg    [awidth   -1:0] adr;
+  reg    [dwidth   -1:0] dout;
+  reg                    cyc, stb;
+  reg                    we;
+  reg    [dwidth/8 -1:0] sel;
+         
+  reg    [dwidth   -1:0] q;
+  
+  // Memory Logic
+  initial
+    begin
+      adr  = {awidth{1'bx}};
+      dout = {dwidth{1'bx}};
+      cyc  = 1'b0;
+      stb  = 1'bx;
+      we   = 1'hx;
+      sel  = {dwidth/8{1'bx}};
+      #1;
+    end
+  
+  // Wishbone write cycle
+  task wb_write;
+    input   delay;
+    integer delay;
+  
+    input [awidth -1:0] a;
+    input [dwidth -1:0] d;
+  
+    begin
+  
+      // wait initial delay
+      repeat(delay) @(posedge clk);
+  
+      // assert wishbone signal
+      #1;
+      adr  = a;
+      dout = d;
+      cyc  = 1'b1;
+      stb  = 1'b1;
+      we   = 1'b1;
+      sel  = {dwidth/8{1'b1}};
+      @(posedge clk);
+  
+      // wait for acknowledge from slave
+      while(~ack) @(posedge clk);
+  
+      // negate wishbone signals
+      #1;
+      cyc  = 1'b0;
+      stb  = 1'bx;
+      adr  = {awidth{1'bx}};
+      dout = {dwidth{1'bx}};
+      we   = 1'hx;
+      sel  = {dwidth/8{1'bx}};
+  
+    end
+  endtask
+  
+  // Wishbone read cycle
+  task wb_read;
+    input   delay;
+    integer delay;
+  
+    input  [awidth -1:0]  a;
+    output  [dwidth -1:0] d;
+  
+    begin
+  
+      // wait initial delay
+      repeat(delay) @(posedge clk);
+  
+      // assert wishbone signals
+      #1;
+      adr  = a;
+      dout = {dwidth{1'bx}};
+      cyc  = 1'b1;
+      stb  = 1'b1;
+      we   = 1'b0;
+      sel  = {dwidth/8{1'b1}};
+      @(posedge clk);
+  
+      // wait for acknowledge from slave
+      while(~ack) @(posedge clk);
+  
+      // negate wishbone signals
+      #1;
+      cyc  = 1'b0;
+      stb  = 1'bx;
+      adr  = {awidth{1'bx}};
+      dout = {dwidth{1'bx}};
+      we   = 1'hx;
+      sel  = {dwidth/8{1'bx}};
+      d    = din;
+  
+    end
+  endtask
+  
+  // Wishbone compare cycle (read data from location and compare with expected data)
+  task wb_cmp;
+    input   delay;
+    integer delay;
+  
+    input [awidth -1:0] a;
+    input [dwidth -1:0] d_exp;
+  
+    begin
+      wb_read (delay, a, q);
+
+    if (d_exp !== q)
+      $display("Data compare error. Received %h, expected %h at time %t", q, d_exp, $time);
+    end
+  endtask
+  
+endmodule
+ 
diff --git a/fpga/usrp3/lib/wb_spi/doc/spi.pdf b/fpga/usrp3/lib/wb_spi/doc/spi.pdf
new file mode 100644
index 000000000..d88ee2807
Binary files /dev/null and b/fpga/usrp3/lib/wb_spi/doc/spi.pdf differ
diff --git a/fpga/usrp3/lib/wb_spi/doc/src/spi.doc b/fpga/usrp3/lib/wb_spi/doc/src/spi.doc
new file mode 100755
index 000000000..b04700177
Binary files /dev/null and b/fpga/usrp3/lib/wb_spi/doc/src/spi.doc differ
diff --git a/fpga/usrp3/lib/wb_spi/rtl/verilog/spi_clgen.v b/fpga/usrp3/lib/wb_spi/rtl/verilog/spi_clgen.v
new file mode 100644
index 000000000..2d9c34f40
--- /dev/null
+++ b/fpga/usrp3/lib/wb_spi/rtl/verilog/spi_clgen.v
@@ -0,0 +1,105 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  spi_clgen.v                                                 ////
+////                                                              ////
+////  This file is part of the SPI IP core project                ////
+////  http://www.opencores.org/projects/spi/                      ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Simon Srot (simons@opencores.org)                     ////
+////                                                              ////
+////  All additional information is avaliable in the Readme.txt   ////
+////  file.                                                       ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2002 Authors                                   ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+`include "spi_defines.v"
+
+module spi_clgen (clk_in, rst, go, enable, last_clk, divider, clk_out, pos_edge, neg_edge); 
+
+  input                            clk_in;   // input clock (system clock)
+  input                            rst;      // reset
+  input                            enable;   // clock enable
+  input                            go;       // start transfer
+  input                            last_clk; // last clock
+  input     [`SPI_DIVIDER_LEN-1:0] divider;  // clock divider (output clock is divided by this value)
+  output                           clk_out;  // output clock
+  output                           pos_edge; // pulse marking positive edge of clk_out
+  output                           neg_edge; // pulse marking negative edge of clk_out
+                            
+  reg                              clk_out;
+  reg                              pos_edge;
+  reg                              neg_edge;
+                            
+  reg       [`SPI_DIVIDER_LEN-1:0] cnt;      // clock counter 
+  wire                             cnt_zero; // conter is equal to zero
+  wire                             cnt_one;  // conter is equal to one
+  
+  
+  assign cnt_zero = cnt == {`SPI_DIVIDER_LEN{1'b0}};
+  assign cnt_one  = cnt == {{`SPI_DIVIDER_LEN-1{1'b0}}, 1'b1};
+  
+  // Counter counts half period
+  always @(posedge clk_in)
+  begin
+    if(rst)
+      cnt <= {`SPI_DIVIDER_LEN{1'b1}};
+    else
+      begin
+        if(!enable || cnt_zero)
+          cnt <= divider;
+        else
+          cnt <= cnt - {{`SPI_DIVIDER_LEN-1{1'b0}}, 1'b1};
+      end
+  end
+  
+  // clk_out is asserted every other half period
+  always @(posedge clk_in)
+  begin
+    if(rst)
+      clk_out <= 1'b0;
+    else
+      clk_out <= (enable && cnt_zero && (!last_clk || clk_out)) ? ~clk_out : clk_out;
+  end
+   
+  // Pos and neg edge signals
+  always @(posedge clk_in)
+  begin
+    if(rst)
+      begin
+        pos_edge  <= 1'b0;
+        neg_edge  <= 1'b0;
+      end
+    else
+      begin
+        pos_edge  <= (enable && !clk_out && cnt_one) || (!(|divider) && clk_out) || (!(|divider) && go && !enable);
+        neg_edge  <= (enable && clk_out && cnt_one) || (!(|divider) && !clk_out && enable);
+      end
+  end
+endmodule
+ 
diff --git a/fpga/usrp3/lib/wb_spi/rtl/verilog/spi_defines.v b/fpga/usrp3/lib/wb_spi/rtl/verilog/spi_defines.v
new file mode 100644
index 000000000..28b4f2fd3
--- /dev/null
+++ b/fpga/usrp3/lib/wb_spi/rtl/verilog/spi_defines.v
@@ -0,0 +1,161 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  spi_define.v                                                ////
+////                                                              ////
+////  This file is part of the SPI IP core project                ////
+////  http://www.opencores.org/projects/spi/                      ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Simon Srot (simons@opencores.org)                     ////
+////                                                              ////
+////  All additional information is avaliable in the Readme.txt   ////
+////  file.                                                       ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2002 Authors                                   ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+//
+// Number of bits used for devider register. If used in system with
+// low frequency of system clock this can be reduced.
+// Use SPI_DIVIDER_LEN for fine tuning theexact number.
+//
+`define SPI_DIVIDER_LEN_8
+//`define SPI_DIVIDER_LEN_16
+//`define SPI_DIVIDER_LEN_24
+//`define SPI_DIVIDER_LEN_32
+
+`ifdef SPI_DIVIDER_LEN_8
+  `define SPI_DIVIDER_LEN       8    // Can be set from 1 to 8
+`endif                                                          
+`ifdef SPI_DIVIDER_LEN_16                                       
+  `define SPI_DIVIDER_LEN       16   // Can be set from 9 to 16
+`endif                                                          
+`ifdef SPI_DIVIDER_LEN_24                                       
+  `define SPI_DIVIDER_LEN       24   // Can be set from 17 to 24
+`endif                                                          
+`ifdef SPI_DIVIDER_LEN_32                                       
+  `define SPI_DIVIDER_LEN       32   // Can be set from 25 to 32 
+`endif
+
+//
+// Maximum nuber of bits that can be send/received at once. 
+// Use SPI_MAX_CHAR for fine tuning the exact number, when using
+// SPI_MAX_CHAR_32, SPI_MAX_CHAR_24, SPI_MAX_CHAR_16, SPI_MAX_CHAR_8.
+//
+`ifndef SPI_MAX_CHAR_64
+  `define SPI_MAX_CHAR_128
+`endif
+//`define SPI_MAX_CHAR_64
+//`define SPI_MAX_CHAR_32
+//`define SPI_MAX_CHAR_24
+//`define SPI_MAX_CHAR_16
+//`define SPI_MAX_CHAR_8
+
+`ifdef SPI_MAX_CHAR_128
+  `define SPI_MAX_CHAR          128  // Can only be set to 128 
+  `define SPI_CHAR_LEN_BITS     7
+`endif
+`ifdef SPI_MAX_CHAR_64
+  `define SPI_MAX_CHAR          64   // Can only be set to 64 
+  `define SPI_CHAR_LEN_BITS     6
+`endif
+`ifdef SPI_MAX_CHAR_32
+  `define SPI_MAX_CHAR          32   // Can be set from 25 to 32 
+  `define SPI_CHAR_LEN_BITS     5
+`endif
+`ifdef SPI_MAX_CHAR_24
+  `define SPI_MAX_CHAR          24   // Can be set from 17 to 24 
+  `define SPI_CHAR_LEN_BITS     5
+`endif
+`ifdef SPI_MAX_CHAR_16
+  `define SPI_MAX_CHAR          16   // Can be set from 9 to 16 
+  `define SPI_CHAR_LEN_BITS     4
+`endif
+`ifdef SPI_MAX_CHAR_8
+  `define SPI_MAX_CHAR          8    // Can be set from 1 to 8 
+  `define SPI_CHAR_LEN_BITS     3
+`endif
+
+//
+// Number of device select signals. Use SPI_SS_NB for fine tuning the 
+// exact number.
+//
+//`define SPI_SS_NB_8
+`define SPI_SS_NB_16
+//`define SPI_SS_NB_24
+//`define SPI_SS_NB_32
+
+`ifdef SPI_SS_NB_8
+  `define SPI_SS_NB             8    // Can be set from 1 to 8
+`endif
+`ifdef SPI_SS_NB_16
+  `define SPI_SS_NB             16   // Can be set from 9 to 16
+`endif
+`ifdef SPI_SS_NB_24
+  `define SPI_SS_NB             24   // Can be set from 17 to 24
+`endif
+`ifdef SPI_SS_NB_32
+  `define SPI_SS_NB             32   // Can be set from 25 to 32
+`endif
+
+//
+// Bits of WISHBONE address used for partial decoding of SPI registers.
+//
+`define SPI_OFS_BITS	          4:2
+
+//
+// Register offset
+//
+`define SPI_RX_0                0
+`define SPI_RX_1                1
+`define SPI_RX_2                2
+`define SPI_RX_3                3
+`define SPI_TX_0                0
+`define SPI_TX_1                1
+`define SPI_TX_2                2
+`define SPI_TX_3                3
+`define SPI_CTRL                4
+`define SPI_DIVIDE              5
+`define SPI_SS                  6
+
+//
+// Number of bits in ctrl register
+//
+`define SPI_CTRL_BIT_NB         14
+
+//
+// Control register bit position
+//
+`define SPI_CTRL_ASS            13
+`define SPI_CTRL_IE             12
+`define SPI_CTRL_LSB            11
+`define SPI_CTRL_TX_NEGEDGE     10
+`define SPI_CTRL_RX_NEGEDGE     9
+`define SPI_CTRL_GO             8
+`define SPI_CTRL_RES_1          7
+`define SPI_CTRL_CHAR_LEN       6:0
+
diff --git a/fpga/usrp3/lib/wb_spi/rtl/verilog/spi_shift.v b/fpga/usrp3/lib/wb_spi/rtl/verilog/spi_shift.v
new file mode 100644
index 000000000..ac3bb3f48
--- /dev/null
+++ b/fpga/usrp3/lib/wb_spi/rtl/verilog/spi_shift.v
@@ -0,0 +1,235 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  spi_shift.v                                                 ////
+////                                                              ////
+////  This file is part of the SPI IP core project                ////
+////  http://www.opencores.org/projects/spi/                      ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Simon Srot (simons@opencores.org)                     ////
+////                                                              ////
+////  All additional information is avaliable in the Readme.txt   ////
+////  file.                                                       ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2002 Authors                                   ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+`include "spi_defines.v"
+
+module spi_shift (clk, rst, latch, byte_sel, len, lsb, go,
+                  pos_edge, neg_edge, rx_negedge, tx_negedge,
+                  tip, last, 
+                  p_in, p_out, s_clk, s_in, s_out);
+
+  input                          clk;          // system clock
+  input                          rst;          // reset
+  input                    [3:0] latch;        // latch signal for storing the data in shift register
+  input                    [3:0] byte_sel;     // byte select signals for storing the data in shift register
+  input [`SPI_CHAR_LEN_BITS-1:0] len;          // data len in bits (minus one)
+  input                          lsb;          // lbs first on the line
+  input                          go;           // start stansfer
+  input                          pos_edge;     // recognize posedge of sclk
+  input                          neg_edge;     // recognize negedge of sclk
+  input                          rx_negedge;   // s_in is sampled on negative edge 
+  input                          tx_negedge;   // s_out is driven on negative edge
+  output                         tip;          // transfer in progress
+  output                         last;         // last bit
+  input                   [31:0] p_in;         // parallel in
+  output     [`SPI_MAX_CHAR-1:0] p_out;        // parallel out
+  input                          s_clk;        // serial clock
+  input                          s_in;         // serial in
+  output                         s_out;        // serial out
+                                               
+  reg                            s_out;        
+  reg                            tip;
+                              
+  reg     [`SPI_CHAR_LEN_BITS:0] cnt;          // data bit count
+  reg        [`SPI_MAX_CHAR-1:0] data;         // shift register
+  wire    [`SPI_CHAR_LEN_BITS:0] tx_bit_pos;   // next bit position
+  wire    [`SPI_CHAR_LEN_BITS:0] rx_bit_pos;   // next bit position
+  wire                           rx_clk;       // rx clock enable
+  wire                           tx_clk;       // tx clock enable
+  
+  assign p_out = data;
+  
+  assign tx_bit_pos = lsb ? {!(|len), len} - cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1};
+  assign rx_bit_pos = lsb ? {!(|len), len} - (rx_negedge ? cnt + {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1} : cnt) : 
+                            (rx_negedge ? cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1});
+  
+  assign last = !(|cnt);
+  
+  assign rx_clk = (rx_negedge ? neg_edge : pos_edge) && (!last || s_clk);
+  assign tx_clk = (tx_negedge ? neg_edge : pos_edge) && !last;
+  
+  // Character bit counter
+  always @(posedge clk)
+  begin
+    if(rst)
+      cnt <= {`SPI_CHAR_LEN_BITS+1{1'b0}};
+    else
+      begin
+        if(tip)
+          cnt <= pos_edge ? (cnt - {{`SPI_CHAR_LEN_BITS{1'b0}}, 1'b1}) : cnt;
+        else
+          cnt <= !(|len) ? {1'b1, {`SPI_CHAR_LEN_BITS{1'b0}}} : {1'b0, len};
+      end
+  end
+  
+  // Transfer in progress
+  always @(posedge clk)
+  begin
+    if(rst)
+      tip <= 1'b0;
+  else if(go && ~tip)
+    tip <= 1'b1;
+  else if(tip && last && pos_edge)
+    tip <= 1'b0;
+  end
+  
+  // Sending bits to the line
+  always @(posedge clk)
+  begin
+    if (rst)
+      s_out   <= 1'b0;
+    else
+      s_out <= (tx_clk || !tip) ? data[tx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] : s_out;
+  end
+  
+  // Receiving bits from the line
+  always @(posedge clk)
+  begin
+    if (rst)
+      data   <= {`SPI_MAX_CHAR{1'b0}};
+`ifdef SPI_MAX_CHAR_128
+    else if (latch[0] && !tip)
+      begin
+        if (byte_sel[3])
+          data[31:24] <= p_in[31:24];
+        if (byte_sel[2])
+          data[23:16] <= p_in[23:16];
+        if (byte_sel[1])
+          data[15:8] <= p_in[15:8];
+        if (byte_sel[0])
+          data[7:0] <= p_in[7:0];
+      end
+    else if (latch[1] && !tip)
+      begin
+        if (byte_sel[3])
+          data[63:56] <= p_in[31:24];
+        if (byte_sel[2])
+          data[55:48] <= p_in[23:16];
+        if (byte_sel[1])
+          data[47:40] <= p_in[15:8];
+        if (byte_sel[0])
+          data[39:32] <= p_in[7:0];
+      end
+    else if (latch[2] && !tip)
+      begin
+        if (byte_sel[3])
+          data[95:88] <= p_in[31:24];
+        if (byte_sel[2])
+          data[87:80] <= p_in[23:16];
+        if (byte_sel[1])
+          data[79:72] <= p_in[15:8];
+        if (byte_sel[0])
+          data[71:64] <= p_in[7:0];
+      end
+    else if (latch[3] && !tip)
+      begin
+        if (byte_sel[3])
+          data[127:120] <= p_in[31:24];
+        if (byte_sel[2])
+          data[119:112] <= p_in[23:16];
+        if (byte_sel[1])
+          data[111:104] <= p_in[15:8];
+        if (byte_sel[0])
+          data[103:96] <= p_in[7:0];
+      end
+`else
+`ifdef SPI_MAX_CHAR_64
+    else if (latch[0] && !tip)
+      begin
+        if (byte_sel[3])
+          data[31:24] <= p_in[31:24];
+        if (byte_sel[2])
+          data[23:16] <= p_in[23:16];
+        if (byte_sel[1])
+          data[15:8] <= p_in[15:8];
+        if (byte_sel[0])
+          data[7:0] <= p_in[7:0];
+      end
+    else if (latch[1] && !tip)
+      begin
+        if (byte_sel[3])
+          data[63:56] <= p_in[31:24];
+        if (byte_sel[2])
+          data[55:48] <= p_in[23:16];
+        if (byte_sel[1])
+          data[47:40] <= p_in[15:8];
+        if (byte_sel[0])
+          data[39:32] <= p_in[7:0];
+      end
+`else
+    else if (latch[0] && !tip)
+      begin
+      `ifdef SPI_MAX_CHAR_8
+        if (byte_sel[0])
+          data[`SPI_MAX_CHAR-1:0] <= p_in[`SPI_MAX_CHAR-1:0];
+      `endif
+      `ifdef SPI_MAX_CHAR_16
+        if (byte_sel[0])
+          data[7:0] <= p_in[7:0];
+        if (byte_sel[1])
+          data[`SPI_MAX_CHAR-1:8] <= p_in[`SPI_MAX_CHAR-1:8];
+      `endif
+      `ifdef SPI_MAX_CHAR_24
+        if (byte_sel[0])
+          data[7:0] <= p_in[7:0];
+        if (byte_sel[1])
+          data[15:8] <= p_in[15:8];
+        if (byte_sel[2])
+          data[`SPI_MAX_CHAR-1:16] <= p_in[`SPI_MAX_CHAR-1:16];
+      `endif
+      `ifdef SPI_MAX_CHAR_32
+        if (byte_sel[0])
+          data[7:0] <= p_in[7:0];
+        if (byte_sel[1])
+          data[15:8] <= p_in[15:8];
+        if (byte_sel[2])
+          data[23:16] <= p_in[23:16];
+        if (byte_sel[3])
+          data[`SPI_MAX_CHAR-1:24] <= p_in[`SPI_MAX_CHAR-1:24];
+      `endif
+      end
+`endif
+`endif
+    else
+      data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] <= rx_clk ? s_in : data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]];
+  end
+  
+endmodule
+
diff --git a/fpga/usrp3/lib/wb_spi/rtl/verilog/spi_top.v b/fpga/usrp3/lib/wb_spi/rtl/verilog/spi_top.v
new file mode 100644
index 000000000..acd1e4fbf
--- /dev/null
+++ b/fpga/usrp3/lib/wb_spi/rtl/verilog/spi_top.v
@@ -0,0 +1,289 @@
+
+// Modified 2010 by Matt Ettus to remove old verilog style
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  spi_top.v                                                   ////
+////                                                              ////
+////  This file is part of the SPI IP core project                ////
+////  http://www.opencores.org/projects/spi/                      ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Simon Srot (simons@opencores.org)                     ////
+////                                                              ////
+////  All additional information is avaliable in the Readme.txt   ////
+////  file.                                                       ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2002 Authors                                   ////
+////
+//// SPDX-License-Identifier: LGPL-3.0-or-later
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+
+`include "spi_defines.v"
+
+module spi_top
+(
+  // Wishbone signals
+  wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_sel_i,
+  wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_err_o, wb_int_o,
+
+  // SPI signals
+  ss_pad_o, sclk_pad_o, mosi_pad_o, miso_pad_i
+);
+
+  // Wishbone signals
+  input                            wb_clk_i;         // master clock input
+  input                            wb_rst_i;         // synchronous active high reset
+  input                      [4:0] wb_adr_i;         // lower address bits
+  input                   [32-1:0] wb_dat_i;         // databus input
+  output                  [32-1:0] wb_dat_o;         // databus output
+  input                      [3:0] wb_sel_i;         // byte select inputs
+  input                            wb_we_i;          // write enable input
+  input                            wb_stb_i;         // stobe/core select signal
+  input                            wb_cyc_i;         // valid bus cycle input
+  output                           wb_ack_o;         // bus cycle acknowledge output
+  output                           wb_err_o;         // termination w/ error
+  output                           wb_int_o;         // interrupt request signal output
+                                                     
+  // SPI signals                                     
+  output          [`SPI_SS_NB-1:0] ss_pad_o;         // slave select
+  output                           sclk_pad_o;       // serial clock
+  output                           mosi_pad_o;       // master out slave in
+  input                            miso_pad_i;       // master in slave out
+                                                     
+  reg                     [32-1:0] wb_dat_o;
+  reg                              wb_ack_o;
+  reg                              wb_int_o;
+                                               
+  // Internal signals
+  reg       [`SPI_DIVIDER_LEN-1:0] divider;          // Divider register
+  reg       [`SPI_CTRL_BIT_NB-1:0] ctrl;             // Control and status register
+  reg             [`SPI_SS_NB-1:0] ss;               // Slave select register
+  reg                     [32-1:0] wb_dat;           // wb data out
+  wire         [`SPI_MAX_CHAR-1:0] rx;               // Rx register
+  wire                             rx_negedge;       // miso is sampled on negative edge
+  wire                             tx_negedge;       // mosi is driven on negative edge
+  wire    [`SPI_CHAR_LEN_BITS-1:0] char_len;         // char len
+  wire                             go;               // go
+  wire                             lsb;              // lsb first on line
+  wire                             ie;               // interrupt enable
+  wire                             ass;              // automatic slave select
+  wire                             spi_divider_sel;  // divider register select
+  wire                             spi_ctrl_sel;     // ctrl register select
+  wire                       [3:0] spi_tx_sel;       // tx_l register select
+  wire                             spi_ss_sel;       // ss register select
+  wire                             tip;              // transfer in progress
+  wire                             pos_edge;         // recognize posedge of sclk
+  wire                             neg_edge;         // recognize negedge of sclk
+  wire                             last_bit;         // marks last character bit
+  
+  // Address decoder
+  assign spi_divider_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_DIVIDE);
+  assign spi_ctrl_sel    = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_CTRL);
+  assign spi_tx_sel[0]   = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_0);
+  assign spi_tx_sel[1]   = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_1);
+  assign spi_tx_sel[2]   = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_2);
+  assign spi_tx_sel[3]   = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_3);
+  assign spi_ss_sel      = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_SS);
+  
+  // Read from registers
+  always @(wb_adr_i or rx or ctrl or divider or ss)
+  begin
+    case (wb_adr_i[`SPI_OFS_BITS])
+`ifdef SPI_MAX_CHAR_128
+      `SPI_RX_0:    wb_dat = rx[31:0];
+      `SPI_RX_1:    wb_dat = rx[63:32];
+      `SPI_RX_2:    wb_dat = rx[95:64];
+      `SPI_RX_3:    wb_dat = {{128-`SPI_MAX_CHAR{1'b0}}, rx[`SPI_MAX_CHAR-1:96]};
+`else
+`ifdef SPI_MAX_CHAR_64
+      `SPI_RX_0:    wb_dat = rx[31:0];
+      `SPI_RX_1:    wb_dat = {{64-`SPI_MAX_CHAR{1'b0}}, rx[`SPI_MAX_CHAR-1:32]};
+      `SPI_RX_2:    wb_dat = 32'b0;
+      `SPI_RX_3:    wb_dat = 32'b0;
+`else
+      `SPI_RX_0:    wb_dat = {{32-`SPI_MAX_CHAR{1'b0}}, rx[`SPI_MAX_CHAR-1:0]};
+      `SPI_RX_1:    wb_dat = 32'b0;
+      `SPI_RX_2:    wb_dat = 32'b0;
+      `SPI_RX_3:    wb_dat = 32'b0;
+`endif
+`endif
+      `SPI_CTRL:    wb_dat = {{32-`SPI_CTRL_BIT_NB{1'b0}}, ctrl};
+      `SPI_DIVIDE:  wb_dat = {{32-`SPI_DIVIDER_LEN{1'b0}}, divider};
+      `SPI_SS:      wb_dat = {{32-`SPI_SS_NB{1'b0}}, ss};
+      default:      wb_dat = 32'bx;
+    endcase
+  end
+  
+  // Wb data out
+  always @(posedge wb_clk_i)
+  begin
+    if (wb_rst_i)
+      wb_dat_o <= 32'b0;
+    else
+      wb_dat_o <= wb_dat;
+  end
+  
+  // Wb acknowledge
+  always @(posedge wb_clk_i)
+  begin
+    if (wb_rst_i)
+      wb_ack_o <= 1'b0;
+    else
+      wb_ack_o <= wb_cyc_i & wb_stb_i & ~wb_ack_o;
+  end
+  
+  // Wb error
+  assign wb_err_o = 1'b0;
+  
+  // Interrupt
+  always @(posedge wb_clk_i)
+  begin
+    if (wb_rst_i)
+      wb_int_o <= 1'b0;
+    else if (ie && tip && last_bit && pos_edge)
+      wb_int_o <= 1'b1;
+    else if (wb_ack_o)
+      wb_int_o <= 1'b0;
+  end
+  
+  // Divider register
+  always @(posedge wb_clk_i)
+  begin
+    if (wb_rst_i)
+        divider <= {`SPI_DIVIDER_LEN{1'b0}};
+    else if (spi_divider_sel && wb_we_i && !tip)
+      begin
+      `ifdef SPI_DIVIDER_LEN_8
+        if (wb_sel_i[0])
+          divider <= wb_dat_i[`SPI_DIVIDER_LEN-1:0];
+      `endif
+      `ifdef SPI_DIVIDER_LEN_16
+        if (wb_sel_i[0])
+          divider[7:0] <= wb_dat_i[7:0];
+        if (wb_sel_i[1])
+          divider[`SPI_DIVIDER_LEN-1:8] <= wb_dat_i[`SPI_DIVIDER_LEN-1:8];
+      `endif
+      `ifdef SPI_DIVIDER_LEN_24
+        if (wb_sel_i[0])
+          divider[7:0] <= wb_dat_i[7:0];
+        if (wb_sel_i[1])
+          divider[15:8] <= wb_dat_i[15:8];
+        if (wb_sel_i[2])
+          divider[`SPI_DIVIDER_LEN-1:16] <= wb_dat_i[`SPI_DIVIDER_LEN-1:16];
+      `endif
+      `ifdef SPI_DIVIDER_LEN_32
+        if (wb_sel_i[0])
+          divider[7:0] <= wb_dat_i[7:0];
+        if (wb_sel_i[1])
+          divider[15:8] <= wb_dat_i[15:8];
+        if (wb_sel_i[2])
+          divider[23:16] <= wb_dat_i[23:16];
+        if (wb_sel_i[3])
+          divider[`SPI_DIVIDER_LEN-1:24] <= wb_dat_i[`SPI_DIVIDER_LEN-1:24];
+      `endif
+      end
+  end
+  
+  // Ctrl register
+  always @(posedge wb_clk_i)
+  begin
+    if (wb_rst_i)
+      ctrl <= {`SPI_CTRL_BIT_NB{1'b0}};
+    else if(spi_ctrl_sel && wb_we_i && !tip)
+      begin
+        if (wb_sel_i[0])
+          ctrl[7:0] <= wb_dat_i[7:0] | {7'b0, ctrl[0]};
+        if (wb_sel_i[1])
+          ctrl[`SPI_CTRL_BIT_NB-1:8] <= wb_dat_i[`SPI_CTRL_BIT_NB-1:8];
+      end
+    else if(tip && last_bit && pos_edge)
+      ctrl[`SPI_CTRL_GO] <= 1'b0;
+  end
+  
+  assign rx_negedge = ctrl[`SPI_CTRL_RX_NEGEDGE];
+  assign tx_negedge = ctrl[`SPI_CTRL_TX_NEGEDGE];
+  assign go         = ctrl[`SPI_CTRL_GO];
+  assign char_len   = ctrl[`SPI_CTRL_CHAR_LEN];
+  assign lsb        = ctrl[`SPI_CTRL_LSB];
+  assign ie         = ctrl[`SPI_CTRL_IE];
+  assign ass        = ctrl[`SPI_CTRL_ASS];
+  
+  // Slave select register
+  always @(posedge wb_clk_i)
+  begin
+    if (wb_rst_i)
+      ss <= {`SPI_SS_NB{1'b0}};
+    else if(spi_ss_sel && wb_we_i && !tip)
+      begin
+      `ifdef SPI_SS_NB_8
+        if (wb_sel_i[0])
+          ss <= wb_dat_i[`SPI_SS_NB-1:0];
+      `endif
+      `ifdef SPI_SS_NB_16
+        if (wb_sel_i[0])
+          ss[7:0] <= wb_dat_i[7:0];
+        if (wb_sel_i[1])
+          ss[`SPI_SS_NB-1:8] <= wb_dat_i[`SPI_SS_NB-1:8];
+      `endif
+      `ifdef SPI_SS_NB_24
+        if (wb_sel_i[0])
+          ss[7:0] <= wb_dat_i[7:0];
+        if (wb_sel_i[1])
+          ss[15:8] <= wb_dat_i[15:8];
+        if (wb_sel_i[2])
+          ss[`SPI_SS_NB-1:16] <= wb_dat_i[`SPI_SS_NB-1:16];
+      `endif
+      `ifdef SPI_SS_NB_32
+        if (wb_sel_i[0])
+          ss[7:0] <= wb_dat_i[7:0];
+        if (wb_sel_i[1])
+          ss[15:8] <= wb_dat_i[15:8];
+        if (wb_sel_i[2])
+          ss[23:16] <= wb_dat_i[23:16];
+        if (wb_sel_i[3])
+          ss[`SPI_SS_NB-1:24] <= wb_dat_i[`SPI_SS_NB-1:24];
+      `endif
+      end
+  end
+  
+  assign ss_pad_o = ~((ss & {`SPI_SS_NB{tip & ass}}) | (ss & {`SPI_SS_NB{!ass}}));
+  
+  spi_clgen clgen (.clk_in(wb_clk_i), .rst(wb_rst_i), .go(go), .enable(tip), .last_clk(last_bit),
+                   .divider(divider), .clk_out(sclk_pad_o), .pos_edge(pos_edge), 
+                   .neg_edge(neg_edge));
+  
+  spi_shift shift (.clk(wb_clk_i), .rst(wb_rst_i), .len(char_len[`SPI_CHAR_LEN_BITS-1:0]),
+                   .latch(spi_tx_sel[3:0] & {4{wb_we_i}}), .byte_sel(wb_sel_i), .lsb(lsb), 
+                   .go(go), .pos_edge(pos_edge), .neg_edge(neg_edge), 
+                   .rx_negedge(rx_negedge), .tx_negedge(tx_negedge),
+                   .tip(tip), .last(last_bit), 
+                   .p_in(wb_dat_i), .p_out(rx), 
+                   .s_clk(sclk_pad_o), .s_in(miso_pad_i), .s_out(mosi_pad_o));
+endmodule
+  
diff --git a/fpga/usrp3/lib/wb_spi/rtl/verilog/spi_top16.v b/fpga/usrp3/lib/wb_spi/rtl/verilog/spi_top16.v
new file mode 100644
index 000000000..1dc7d4c39
--- /dev/null
+++ b/fpga/usrp3/lib/wb_spi/rtl/verilog/spi_top16.v
@@ -0,0 +1,184 @@
+
+// Modified 2010 by Matt Ettus to remove old verilog style and
+// allow 16-bit operation
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  spi_top.v                                                   ////
+////                                                              ////
+////  This file is part of the SPI IP core project                ////
+////  http://www.opencores.org/projects/spi/                      ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Simon Srot (simons@opencores.org)                     ////
+////                                                              ////
+////  All additional information is avaliable in the Readme.txt   ////
+////  file.                                                       ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2002 Authors                                   ////
+////
+//// SPDX-License-Identifier: LGPL-3.0-or-later
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+
+`include "spi_defines.v"
+
+module spi_top16
+  (input wb_clk_i, input wb_rst_i, 
+   input [4:0] wb_adr_i, 
+   input [15:0] wb_dat_i, 
+   output reg [15:0] wb_dat_o, 
+   input [1:0] wb_sel_i,
+   input wb_we_i, input wb_stb_i, input wb_cyc_i, 
+   output reg wb_ack_o, output wb_err_o, output reg wb_int_o,
+   
+   // SPI signals
+   output [15:0] ss_pad_o, output sclk_pad_o, output mosi_pad_o, input miso_pad_i);
+   
+   // Internal signals
+   reg [15:0] divider;          // Divider register
+   reg [`SPI_CTRL_BIT_NB-1:0] ctrl;             // Control and status register
+   reg [15:0] 		      ss;               // Slave select register
+   reg [31:0] 		      wb_dat;           // wb data out
+   wire [31:0] 		      rx;               // Rx register
+   wire 		      rx_negedge;       // miso is sampled on negative edge
+   wire 		      tx_negedge;       // mosi is driven on negative edge
+   wire [`SPI_CHAR_LEN_BITS-1:0] char_len;         // char len
+   wire 			 go;               // go
+   wire 			 lsb;              // lsb first on line
+   wire 			 ie;               // interrupt enable
+   wire 			 ass;              // automatic slave select
+   wire 			 spi_divider_sel;  // divider register select
+   wire 			 spi_ctrl_sel;     // ctrl register select
+   wire [3:0] 			 spi_tx_sel;       // tx_l register select
+   wire 			 spi_ss_sel;       // ss register select
+   wire 			 tip;              // transfer in progress
+   wire 			 pos_edge;         // recognize posedge of sclk
+   wire 			 neg_edge;         // recognize negedge of sclk
+   wire 			 last_bit;         // marks last character bit
+   
+   // Address decoder
+   assign spi_divider_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_DIVIDE);
+   assign spi_ctrl_sel    = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_CTRL);
+   assign spi_tx_sel[0]   = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_0);
+   assign spi_tx_sel[1]   = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_1);
+   assign spi_tx_sel[2]   = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_2);
+   assign spi_tx_sel[3]   = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_3);
+   assign spi_ss_sel      = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_SS);
+   
+   always @(wb_adr_i or rx or ctrl or divider or ss)
+     case (wb_adr_i[4:2])   
+       `SPI_RX_0:    wb_dat = rx[31:0];
+       `SPI_CTRL:    wb_dat = {{32-`SPI_CTRL_BIT_NB{1'b0}}, ctrl};
+       `SPI_DIVIDE:  wb_dat = {16'b0, divider};
+       `SPI_SS:      wb_dat = {16'b0, ss};
+       default : wb_dat = 32'd0;
+     endcase // case (wb_adr_i[4:2])
+   
+   always @(posedge wb_clk_i)
+     if (wb_rst_i)
+       wb_dat_o <= 32'b0;
+     else
+       wb_dat_o <= wb_adr_i[1] ? wb_dat[31:16] : wb_dat[15:0];
+   
+   always @(posedge wb_clk_i)
+     if (wb_rst_i)
+       wb_ack_o <= 1'b0;
+     else
+       wb_ack_o <= wb_cyc_i & wb_stb_i & ~wb_ack_o;
+   
+   assign wb_err_o = 1'b0;
+   
+   // Interrupt
+   always @(posedge wb_clk_i)
+     if (wb_rst_i)
+       wb_int_o <= 1'b0;
+     else if (ie && tip && last_bit && pos_edge)
+       wb_int_o <= 1'b1;
+     else if (wb_ack_o)
+       wb_int_o <= 1'b0;
+   
+   // Divider register
+   always @(posedge wb_clk_i)
+     if (wb_rst_i)
+       divider <= 16'b0;
+     else if (spi_divider_sel && wb_we_i && !tip && ~wb_adr_i[1])
+       divider <= wb_dat_i;
+   
+   // Ctrl register
+   always @(posedge wb_clk_i)
+     if (wb_rst_i)
+       ctrl <= {`SPI_CTRL_BIT_NB{1'b0}};
+     else if(spi_ctrl_sel && wb_we_i && !tip && ~wb_adr_i[1])
+       begin
+          if (wb_sel_i[0])
+            ctrl[7:0] <= wb_dat_i[7:0] | {7'b0, ctrl[0]};
+          if (wb_sel_i[1])
+            ctrl[`SPI_CTRL_BIT_NB-1:8] <= wb_dat_i[`SPI_CTRL_BIT_NB-1:8];
+       end
+     else if(tip && last_bit && pos_edge)
+       ctrl[`SPI_CTRL_GO] <= 1'b0;
+   
+   assign rx_negedge = ctrl[`SPI_CTRL_RX_NEGEDGE];
+   assign tx_negedge = ctrl[`SPI_CTRL_TX_NEGEDGE];
+   assign go         = ctrl[`SPI_CTRL_GO];
+   assign char_len   = ctrl[`SPI_CTRL_CHAR_LEN];
+   assign lsb        = ctrl[`SPI_CTRL_LSB];
+   assign ie         = ctrl[`SPI_CTRL_IE];
+   assign ass        = ctrl[`SPI_CTRL_ASS];
+   
+   // Slave select register
+   always @(posedge wb_clk_i)
+     if (wb_rst_i)
+       ss <= 16'b0;
+     else if(spi_ss_sel && wb_we_i && !tip & ~wb_adr_i[1])
+       begin
+          if (wb_sel_i[0])
+            ss[7:0] <= wb_dat_i[7:0];
+          if (wb_sel_i[1])
+            ss[15:8] <= wb_dat_i[15:8];
+       end
+   
+   assign ss_pad_o = ~((ss & {16{tip & ass}}) | (ss & {16{!ass}}));
+   
+   spi_clgen clgen (.clk_in(wb_clk_i), .rst(wb_rst_i), .go(go), .enable(tip), .last_clk(last_bit),
+                    .divider(divider[`SPI_DIVIDER_LEN-1:0]), .clk_out(sclk_pad_o), .pos_edge(pos_edge), 
+                    .neg_edge(neg_edge));
+
+   wire [3:0] new_sels = { (wb_adr_i[1] & wb_sel_i[1]), (wb_adr_i[1] & wb_sel_i[0]), 
+			   (~wb_adr_i[1] & wb_sel_i[1]), (~wb_adr_i[1] & wb_sel_i[0]) };
+   
+   
+   spi_shift shift (.clk(wb_clk_i), .rst(wb_rst_i), .len(char_len[`SPI_CHAR_LEN_BITS-1:0]),
+                    .latch(spi_tx_sel[3:0] & {4{wb_we_i}}), .byte_sel(new_sels), .lsb(lsb), 
+                    .go(go), .pos_edge(pos_edge), .neg_edge(neg_edge), 
+                    .rx_negedge(rx_negedge), .tx_negedge(tx_negedge),
+                    .tip(tip), .last(last_bit), 
+                    .p_in({wb_dat_i,wb_dat_i}), .p_out(rx), 
+                    .s_clk(sclk_pad_o), .s_in(miso_pad_i), .s_out(mosi_pad_o));
+
+endmodule // spi_top16
diff --git a/fpga/usrp3/lib/wb_spi/sim/rtl_sim/run/rtl.fl b/fpga/usrp3/lib/wb_spi/sim/rtl_sim/run/rtl.fl
new file mode 100644
index 000000000..d84a0840d
--- /dev/null
+++ b/fpga/usrp3/lib/wb_spi/sim/rtl_sim/run/rtl.fl
@@ -0,0 +1,3 @@
+spi_top.v
+spi_clgen.v
+spi_shift.v
diff --git a/fpga/usrp3/lib/wb_spi/sim/rtl_sim/run/run_sim b/fpga/usrp3/lib/wb_spi/sim/rtl_sim/run/run_sim
new file mode 100755
index 000000000..1b13a35b9
--- /dev/null
+++ b/fpga/usrp3/lib/wb_spi/sim/rtl_sim/run/run_sim
@@ -0,0 +1,108 @@
+#!/bin/csh -f
+
+set current_par = 0
+set output_waveform = 0
+while ( $current_par < $# )
+    @ current_par = $current_par + 1
+    case wave:
+        @ output_waveform = 1
+        breaksw
+    default:
+        echo 'Unknown option "'$argv[$current_par]'"!'
+        exit
+        breaksw
+    endsw
+end
+
+echo "TEST: spi"
+
+#echo "-CDSLIB ./cds.lib"               > ncvlog.args
+#echo "-HDLVAR ./hdl.var"              >> ncvlog.args
+echo "-MESSAGES"                       > ncvlog.args
+echo "-INCDIR ../../../bench/verilog" >> ncvlog.args
+echo "-INCDIR ../../../rtl/verilog"   >> ncvlog.args
+echo "-NOCOPYRIGHT"                   >> ncvlog.args
+echo "-UPDATE"                        >> ncvlog.args
+echo "-LOGFILE ncvlog.log"            >> ncvlog.args
+
+foreach filename ( `cat ./rtl.fl` )
+    echo "../../../rtl/verilog/"$filename >> ncvlog.args
+end
+
+foreach filename ( `cat ./sim.fl` )
+    echo "../../../bench/verilog/"$filename >> ncvlog.args
+end
+
+ncvlog -f ncvlog.args
+if ($status != 0) then
+  echo "STATUS: failed"
+  exit
+endif
+
+
+echo "-MESSAGES"                             > ncelab.args
+echo "-NOCOPYRIGHT"                         >> ncelab.args
+#echo "-CDSLIB ./cds.lib"                    >> ncelab.args
+#echo "-HDLVAR ./hdl.var"                    >> ncelab.args
+echo "-LOGFILE ncelab.log"                  >> ncelab.args
+echo "-SNAPSHOT worklib.tb_spi_top:v"       >> ncelab.args
+echo "-NOTIMINGCHECKS"                      >> ncelab.args
+echo "-ACCESS +RWC"                         >> ncelab.args
+echo "tb_spi_top"                           >> ncelab.args
+
+ncelab -f ncelab.args
+if ($status != 0) then
+  echo "STATUS: failed"
+  exit
+endif
+
+
+echo "-MESSAGES"                   > ncsim.args
+echo "-NOCOPYRIGHT"               >> ncsim.args
+#echo "-CDSLIB ./cds.lib"          >> ncsim.args
+#echo "-HDLVAR ./hdl.var"          >> ncsim.args
+echo "-INPUT ncsim.tcl"           >> ncsim.args
+echo "-LOGFILE ncsim.log"         >> ncsim.args
+echo "worklib.tb_spi_top:v"       >> ncsim.args
+
+if ( $output_waveform ) then
+    echo "database -open waves -shm -into ../out/wav"                         > ./ncsim.tcl
+    echo "probe -create -database waves -shm tb_spi_top -all -depth all"      >> ./ncsim.tcl
+    echo "stop -create -time 25000000 -relative"                              >> ./ncsim.tcl
+    echo "run"                                                                >> ./ncsim.tcl
+else
+    echo "stop -create -time 25000000 -relative"                              >> ./ncsim.tcl
+    echo "run"  > ./ncsim.tcl
+endif
+
+echo "exit" >> ncsim.tcl
+
+ncsim -LICQUEUE -f ./ncsim.args
+
+set exit_line_nb = `sed -n '/exit/=' < ./ncsim.log`
+
+set dead_line_nb = 0
+
+if ( $exit_line_nb ) then
+
+  @ dead_line_nb = $exit_line_nb - 1
+  set exit_line=`sed -n $exit_line_nb's/exit/&/gp' < ./ncsim.log`
+  set dead_line=`sed -n $dead_line_nb's/report/&/gp' < ./ncsim.log`
+
+  if ( "$dead_line" == "report (deaddead)" ) then
+    if ( "$exit_line" == "exit (00000000)"   ) then
+      echo "STATUS: passed"  #|tee -a ./run_sim.log 2>&1
+    else
+      echo "STATUS: failed"  #|tee -a ./run_sim.log 2>&1
+    endif
+  else
+    echo "STATUS: failed"
+  endif
+
+endif
+
+exit
+
+
+
+
diff --git a/fpga/usrp3/lib/wb_spi/sim/rtl_sim/run/sim.fl b/fpga/usrp3/lib/wb_spi/sim/rtl_sim/run/sim.fl
new file mode 100644
index 000000000..283aad1f8
--- /dev/null
+++ b/fpga/usrp3/lib/wb_spi/sim/rtl_sim/run/sim.fl
@@ -0,0 +1,3 @@
+tb_spi_top.v
+wb_master_model.v
+spi_slave_model.v
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/Makefile.srcs b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/Makefile.srcs
new file mode 100644
index 000000000..fce6adefa
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/Makefile.srcs
@@ -0,0 +1,176 @@
+#
+# Copyright 2018 Ettus Research LLC
+#
+
+##################################################
+# White Rabbit Sources
+##################################################
+WHITE_RABBIT_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/white_rabbit/wr_cores_v4_2/, \
+platform/xilinx/wr_gtp_phy/family7-gtx/whiterabbit_gtxe2_channel_wrapper_gt.vhd \
+platform/xilinx/wr_gtp_phy/spartan6/gtp_phase_align.vhd \
+platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd \
+platform/xilinx/wr_gtp_phy/spartan6/whiterabbitgtp_wrapper_tile_spartan6.vhd \
+ip_cores/general-cores/modules/common/gc_reset.vhd \
+ip_cores/general-cores/modules/genrams/genram_pkg.vhd \
+ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd \
+ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd \
+modules/fabric/wr_fabric_pkg.vhd \
+ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd \
+ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd \
+ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd \
+ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd \
+ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd \
+ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd \
+ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd \
+modules/wr_streamers/escape_detector.vhd \
+modules/wr_streamers/dropping_buffer.vhd \
+modules/wr_streamers/escape_inserter.vhd \
+modules/wr_softpll_ng/softpll_pkg.vhd \
+modules/wrc_core/wrc_diags_pkg.vhd \
+modules/wrc_core/wrc_syscon_pkg.vhd \
+modules/wr_endpoint/endpoint_pkg.vhd \
+modules/wrc_core/wrcore_pkg.vhd \
+modules/wr_streamers/streamers_pkg.vhd \
+modules/wr_streamers/xrx_streamers_stats.vhd \
+modules/wr_streamers/xtx_streamers_stats.vhd \
+modules/timing/pulse_stamper.vhd \
+modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd \
+modules/wr_streamers/streamers_priv_pkg.vhd \
+modules/wr_streamers/xrtx_streamers_stats.vhd \
+modules/wr_streamers/wr_streamers_wb.vhd \
+modules/wr_pps_gen/pps_gen_wb.vhd \
+ip_cores/general-cores/modules/common/gencores_pkg.vhd \
+ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd \
+modules/wr_softpll_ng/spll_aligner.vhd \
+modules/wr_endpoint/ep_registers_pkg.vhd \
+modules/wr_endpoint/endpoint_private_pkg.vhd \
+modules/wr_endpoint/ep_leds_controller.vhd \
+modules/wr_endpoint/ep_sync_detect.vhd \
+modules/wr_endpoint/ep_sync_detect_16bit.vhd \
+ip_cores/general-cores/modules/common/gc_extend_pulse.vhd \
+modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd \
+modules/wr_endpoint/ep_autonegotiation.vhd \
+modules/wr_endpoint/ep_tx_packet_injection.vhd \
+modules/wr_endpoint/ep_tx_inject_ctrl.vhd \
+modules/wr_endpoint/ep_tx_header_processor.vhd \
+modules/wr_endpoint/ep_rx_vlan_unit.vhd \
+ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd \
+ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd \
+ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd \
+ip_cores/general-cores/modules/common/gc_sync_register.vhd \
+modules/wr_endpoint/ep_rx_oob_insert.vhd \
+ip_cores/general-cores/modules/common/gc_crc_gen.vhd \
+modules/wr_endpoint/ep_crc32_pkg.vhd \
+modules/wr_endpoint/ep_rx_crc_size_check.vhd \
+modules/wr_endpoint/ep_rtu_header_extract.vhd \
+modules/wr_endpoint/ep_rx_status_reg_insert.vhd \
+modules/wr_endpoint/ep_rx_wb_master.vhd \
+modules/wr_endpoint/ep_ts_counter.vhd \
+modules/wr_endpoint/ep_wishbone_controller.vhd \
+ip_cores/general-cores/modules/common/gc_sync_ffs.vhd \
+ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
+ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd \
+modules/wr_mini_nic/minic_wbgen2_pkg.vhd \
+modules/wr_mini_nic/minic_wb_slave.vhd \
+ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v \
+ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v \
+ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v \
+ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v \
+ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v \
+ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v \
+ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v \
+ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd \
+ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd \
+ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd \
+ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd \
+ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd \
+ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd \
+ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd \
+ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd \
+ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v \
+modules/wrc_core/wrc_syscon_wb.vhd \
+ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd \
+ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd \
+ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd \
+ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd \
+ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd \
+ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd \
+ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd \
+ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v \
+modules/wrc_core/wrc_diags_wb.vhd \
+ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd \
+ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd \
+ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd \
+ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd \
+modules/fabric/xwrf_mux.vhd \
+ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/axi4_pkg.vhd \
+ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd \
+ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd \
+board/eeprom/sfp_eeprom.vhd \
+platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq.vhd \
+platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gt.vhd \
+platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper.vhd \
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+ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd \
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+ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd \
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+ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd \
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+modules/wr_endpoint/wr_endpoint.vhd \
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+ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd \
+ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd \
+ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd \
+ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd \
+ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd \
+ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd \
+ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd \
+modules/wrc_core/wr_core.vhd \
+modules/wrc_core/xwr_core.vhd \
+board/common/wr_board_pkg.vhd \
+board/common/xwrc_board_common.vhd \
+))
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/bin/sdbfs/sdbfs-empty-i2c-eeprom.bin b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/bin/sdbfs/sdbfs-empty-i2c-eeprom.bin
new file mode 100644
index 000000000..825733426
Binary files /dev/null and b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/bin/sdbfs/sdbfs-empty-i2c-eeprom.bin differ
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/bin/sdbfs/sdbfs-svec-flash.bin b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/bin/sdbfs/sdbfs-svec-flash.bin
new file mode 100644
index 000000000..0da8a2b8e
Binary files /dev/null and b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/bin/sdbfs/sdbfs-svec-flash.bin differ
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/bin/wrpc/wrc_phy16.bram b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/bin/wrpc/wrc_phy16.bram
new file mode 100644
index 000000000..05fabcd35
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/bin/wrpc/wrc_phy16.bram
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new file mode 100644
index 000000000..d02bac529
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/bin/wrpc/wrc_phy8.bram
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diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/bin/wrpc/wrc_phy8.mif b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/bin/wrpc/wrc_phy8.mif
new file mode 100644
index 000000000..83f979eb6
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/bin/wrpc/wrc_phy8.mif
@@ -0,0 +1,32775 @@
+DEPTH = 32768;
+WIDTH = 32;
+ADDRESS_RADIX = HEX;
+DATA_RADIX = HEX;
+CONTENT
+BEGIN
+0 : 98000000;
+1 : D0000000;
+2 : D0200000;
+3 : 78010000;
+4 : 38210000;
+5 : D0E10000;
+6 : F800003A;
+7 : 34000000;
+8 : 00000000;
+9 : 00000000;
+a : 00000000;
+b : 00000000;
+c : 00000000;
+d : 00000000;
+e : 00000000;
+f : 00000000;
+10 : 00000000;
+11 : 00000000;
+12 : 00000000;
+13 : 00000000;
+14 : 00000000;
+15 : 00000000;
+16 : 00000000;
+17 : 00000000;
+18 : 00000000;
+19 : 00000000;
+1a : 00000000;
+1b : 00000000;
+1c : 00000000;
+1d : 00000000;
+1e : 00000000;
+1f : 00000000;
+20 : 57525043;
+21 : 2D2D2D2D;
+22 : 01234567;
+23 : 89ABCDEF;
+24 : 0001BFD8;
+25 : 00000000;
+26 : 00019828;
+27 : 0001AD84;
+28 : 00000000;
+29 : 02140000;
+2a : 00000000;
+2b : 00000000;
+2c : 00000000;
+2d : 00000000;
+2e : 00000000;
+2f : 00000000;
+30 : 5B9D0000;
+31 : F800001E;
+32 : 34010002;
+33 : F800519E;
+34 : E000002E;
+35 : 34000000;
+36 : 34000000;
+37 : 34000000;
+38 : 00000000;
+39 : 00000000;
+3a : 00000000;
+3b : 00000000;
+3c : 00000000;
+3d : 00000000;
+3e : 00000000;
+3f : 00000000;
+40 : 98000000;
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diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/bin/wrpc/wrc_phy8_sim.bram b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/bin/wrpc/wrc_phy8_sim.bram
new file mode 100644
index 000000000..8d4e519ba
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/bin/wrpc/wrc_phy8_sim.bram
@@ -0,0 +1,32768 @@
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diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/bin/wrpc/wrc_phy8_sim.mif b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/bin/wrpc/wrc_phy8_sim.mif
new file mode 100644
index 000000000..1680114ee
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/bin/wrpc/wrc_phy8_sim.mif
@@ -0,0 +1,32775 @@
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+1787 : 00000000;
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+7f50 : 00000000;
+7f51 : 00000000;
+7f52 : 00000000;
+7f53 : 00000000;
+7f54 : 00000000;
+7f55 : 00000000;
+7f56 : 00000000;
+7f57 : 00000000;
+7f58 : 00000000;
+7f59 : 00000000;
+7f5a : 00000000;
+7f5b : 00000000;
+7f5c : 00000000;
+7f5d : 00000000;
+7f5e : 00000000;
+7f5f : 00000000;
+7f60 : 00000000;
+7f61 : 00000000;
+7f62 : 00000000;
+7f63 : 00000000;
+7f64 : 00000000;
+7f65 : 00000000;
+7f66 : 00000000;
+7f67 : 00000000;
+7f68 : 00000000;
+7f69 : 00000000;
+7f6a : 00000000;
+7f6b : 00000000;
+7f6c : 00000000;
+7f6d : 00000000;
+7f6e : 00000000;
+7f6f : 00000000;
+7f70 : 00000000;
+7f71 : 00000000;
+7f72 : 00000000;
+7f73 : 00000000;
+7f74 : 00000000;
+7f75 : 00000000;
+7f76 : 00000000;
+7f77 : 00000000;
+7f78 : 00000000;
+7f79 : 00000000;
+7f7a : 00000000;
+7f7b : 00000000;
+7f7c : 00000000;
+7f7d : 00000000;
+7f7e : 00000000;
+7f7f : 00000000;
+7f80 : 00000000;
+7f81 : 00000000;
+7f82 : 00000000;
+7f83 : 00000000;
+7f84 : 00000000;
+7f85 : 00000000;
+7f86 : 00000000;
+7f87 : 00000000;
+7f88 : 00000000;
+7f89 : 00000000;
+7f8a : 00000000;
+7f8b : 00000000;
+7f8c : 00000000;
+7f8d : 00000000;
+7f8e : 00000000;
+7f8f : 00000000;
+7f90 : 00000000;
+7f91 : 00000000;
+7f92 : 00000000;
+7f93 : 00000000;
+7f94 : 00000000;
+7f95 : 00000000;
+7f96 : 00000000;
+7f97 : 00000000;
+7f98 : 00000000;
+7f99 : 00000000;
+7f9a : 00000000;
+7f9b : 00000000;
+7f9c : 00000000;
+7f9d : 00000000;
+7f9e : 00000000;
+7f9f : 00000000;
+7fa0 : 00000000;
+7fa1 : 00000000;
+7fa2 : 00000000;
+7fa3 : 00000000;
+7fa4 : 00000000;
+7fa5 : 00000000;
+7fa6 : 00000000;
+7fa7 : 00000000;
+7fa8 : 00000000;
+7fa9 : 00000000;
+7faa : 00000000;
+7fab : 00000000;
+7fac : 00000000;
+7fad : 00000000;
+7fae : 00000000;
+7faf : 00000000;
+7fb0 : 00000000;
+7fb1 : 00000000;
+7fb2 : 00000000;
+7fb3 : 00000000;
+7fb4 : 00000000;
+7fb5 : 00000000;
+7fb6 : 00000000;
+7fb7 : 00000000;
+7fb8 : 00000000;
+7fb9 : 00000000;
+7fba : 00000000;
+7fbb : 00000000;
+7fbc : 00000000;
+7fbd : 00000000;
+7fbe : 00000000;
+7fbf : 00000000;
+7fc0 : 00000000;
+7fc1 : 00000000;
+7fc2 : 00000000;
+7fc3 : 00000000;
+7fc4 : 00000000;
+7fc5 : 00000000;
+7fc6 : 00000000;
+7fc7 : 00000000;
+7fc8 : 00000000;
+7fc9 : 00000000;
+7fca : 00000000;
+7fcb : 00000000;
+7fcc : 00000000;
+7fcd : 00000000;
+7fce : 00000000;
+7fcf : 00000000;
+7fd0 : 00000000;
+7fd1 : 00000000;
+7fd2 : 00000000;
+7fd3 : 00000000;
+7fd4 : 00000000;
+7fd5 : 00000000;
+7fd6 : 00000000;
+7fd7 : 00000000;
+7fd8 : 00000000;
+7fd9 : 00000000;
+7fda : 00000000;
+7fdb : 00000000;
+7fdc : 00000000;
+7fdd : 00000000;
+7fde : 00000000;
+7fdf : 00000000;
+7fe0 : 00000000;
+7fe1 : 00000000;
+7fe2 : 00000000;
+7fe3 : 00000000;
+7fe4 : 00000000;
+7fe5 : 00000000;
+7fe6 : 00000000;
+7fe7 : 00000000;
+7fe8 : 00000000;
+7fe9 : 00000000;
+7fea : 00000000;
+7feb : 00000000;
+7fec : 00000000;
+7fed : 00000000;
+7fee : 00000000;
+7fef : 00000000;
+7ff0 : 00000000;
+7ff1 : 00000000;
+7ff2 : 00000000;
+7ff3 : 00000000;
+7ff4 : 00000000;
+7ff5 : 00000000;
+7ff6 : 00000000;
+7ff7 : 00000000;
+7ff8 : 00000000;
+7ff9 : 00000000;
+7ffa : 00000000;
+7ffb : 00000000;
+7ffc : 00000000;
+7ffd : 00000000;
+7ffe : 00000000;
+7fff : 00000000;
+END;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/board/common/wr_board_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/board/common/wr_board_pkg.vhd
new file mode 100644
index 000000000..81a61a583
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/board/common/wr_board_pkg.vhd
@@ -0,0 +1,359 @@
+-------------------------------------------------------------------------------
+-- Title      : Common WRPC Wrapper package
+-- Project    : WR PTP Core
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
+-------------------------------------------------------------------------------
+-- File       : xwrc_board_common.vhd
+-- Company    : CERN (BE-CO-HT)
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2017 CERN
+--
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-- 
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.wishbone_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.endpoint_pkg.all;
+use work.wrcore_pkg.all;
+use work.streamers_pkg.all;
+
+package wr_board_pkg is
+
+  type t_board_fabric_iface is (PLAIN, STREAMERS, ETHERBONE, always_last_invalid);
+
+  -- TODO: using these default paths requires absolute path. If relative path is used,
+  --       they work only for reference designs by chance. Once we figure out how to
+  --       automatically figure out absolute path of <wr-cores location>/bin/wrpc, we
+  --       will be able to use this concept in f_find_default_lm32_firmware()
+  constant dpram_initf_default_altera_phy8     : string := "";
+  constant dpram_initf_default_xilinx_phy8     : string := "";
+  constant dpram_initf_default_altera_phy8_sim : string := "";
+  constant dpram_initf_default_xilinx_phy8_sim : string := "";
+
+  procedure f_check_fabric_iface_type (
+    constant iface_type : in t_board_fabric_iface);
+
+  procedure f_check_diag_id (
+    constant diag_id, diag_ver : in integer);
+
+  function f_str2iface_type (
+    constant iface_str : string(1 to 9))
+    return t_board_fabric_iface;
+
+  function f_pick_diag_val (
+    iface           : t_board_fabric_iface;
+    streamers_val   : integer;
+    application_val : integer
+    ) return integer;
+
+  function f_pick_diag_size (
+    iface            : t_board_fabric_iface;
+    streamers_size   : integer;
+    application_size : integer
+    ) return integer;
+
+  function f_vectorize_diag (
+    diag_in          : t_generic_word_array;
+    diag_vector_size : integer)
+    return std_logic_vector;
+
+  function f_de_vectorize_diag (
+    diag_in          : std_logic_vector;
+    diag_vector_size : integer)
+    return t_generic_word_array;
+
+  function f_find_default_lm32_firmware (
+    dpram_initf : string;
+    simulation  : integer;
+    pcs_16_bit  : boolean)
+    return string;
+
+  component xwrc_board_common is
+    generic (
+      g_simulation                : integer                        := 0;
+      g_with_external_clock_input : boolean                        := TRUE;
+      g_board_name                : string                         := "NA  ";
+      g_flash_secsz_kb            : integer                        := 256;        -- default for M25P128
+      g_flash_sdbfs_baddr         : integer                        := 16#600000#; -- default for M25P128
+      g_phys_uart                 : boolean                        := TRUE;
+      g_virtual_uart              : boolean                        := TRUE;
+      g_aux_clks                  : integer                        := 0;
+      g_ep_rxbuf_size             : integer                        := 1024;
+      g_tx_runt_padding           : boolean                        := TRUE;
+      g_dpram_initf               : string                         := "";
+      g_dpram_size                : integer                        := 131072/4;
+      g_interface_mode            : t_wishbone_interface_mode      := PIPELINED;
+      g_address_granularity       : t_wishbone_address_granularity := BYTE;
+      g_aux_sdb                   : t_sdb_device                   := c_wrc_periph3_sdb;
+      g_softpll_enable_debugger   : boolean                        := FALSE;
+      g_vuart_fifo_size           : integer                        := 1024;
+      g_pcs_16bit                 : boolean                        := FALSE;
+      g_diag_id                   : integer                        := 0;
+      g_diag_ver                  : integer                        := 0;
+      g_diag_ro_size              : integer                        := 0;
+      g_diag_rw_size              : integer                        := 0;
+      g_streamers_op_mode         : t_streamers_op_mode            := TX_AND_RX;
+      g_tx_streamer_params        : t_tx_streamer_params           := c_tx_streamer_params_defaut;
+      g_rx_streamer_params        : t_rx_streamer_params           := c_rx_streamer_params_defaut;
+      g_fabric_iface              : t_board_fabric_iface           := PLAIN);
+    port (
+      clk_sys_i            : in  std_logic;
+      clk_dmtd_i           : in  std_logic;
+      clk_ref_i            : in  std_logic;
+      clk_aux_i            : in  std_logic_vector(g_aux_clks-1 downto 0)          := (others => '0');
+      clk_10m_ext_i        : in  std_logic                                        := '0';
+      clk_ext_mul_i        : in  std_logic                                        := '0';
+      clk_ext_mul_locked_i : in  std_logic                                        := '1';
+      clk_ext_stopped_i    : in  std_logic                                        := '0';
+      clk_ext_rst_o        : out std_logic;
+      pps_ext_i            : in  std_logic                                        := '0';
+      rst_n_i              : in  std_logic;
+      dac_hpll_load_p1_o   : out std_logic;
+      dac_hpll_data_o      : out std_logic_vector(15 downto 0);
+      dac_dpll_load_p1_o   : out std_logic;
+      dac_dpll_data_o      : out std_logic_vector(15 downto 0);
+      phy8_o               : out t_phy_8bits_from_wrc;
+      phy8_i               : in  t_phy_8bits_to_wrc                               := c_dummy_phy8_to_wrc;
+      phy16_o              : out t_phy_16bits_from_wrc;
+      phy16_i              : in  t_phy_16bits_to_wrc                              := c_dummy_phy16_to_wrc;
+      scl_o                : out std_logic;
+      scl_i                : in  std_logic                                        := '1';
+      sda_o                : out std_logic;
+      sda_i                : in  std_logic                                        := '1';
+      sfp_scl_o            : out std_logic;
+      sfp_scl_i            : in  std_logic                                        := '1';
+      sfp_sda_o            : out std_logic;
+      sfp_sda_i            : in  std_logic                                        := '1';
+      sfp_det_i            : in  std_logic;
+      spi_sclk_o           : out std_logic;
+      spi_ncs_o            : out std_logic;
+      spi_mosi_o           : out std_logic;
+      spi_miso_i           : in  std_logic                                        := '0';
+      uart_rxd_i           : in  std_logic                                        := '0';
+      uart_txd_o           : out std_logic;
+      owr_pwren_o          : out std_logic_vector(1 downto 0);
+      owr_en_o             : out std_logic_vector(1 downto 0);
+      owr_i                : in  std_logic_vector(1 downto 0)                     := (others => '1');
+      wb_slave_i           : in  t_wishbone_slave_in                              := cc_dummy_slave_in;
+      wb_slave_o           : out t_wishbone_slave_out;
+      aux_master_o         : out t_wishbone_master_out;
+      aux_master_i         : in  t_wishbone_master_in                             := cc_dummy_master_in;
+      wrf_src_o            : out t_wrf_source_out;
+      wrf_src_i            : in  t_wrf_source_in                                  := c_dummy_src_in;
+      wrf_snk_o            : out t_wrf_sink_out;
+      wrf_snk_i            : in  t_wrf_sink_in                                    := c_dummy_snk_in;
+      wrs_tx_data_i        : in  std_logic_vector(g_tx_streamer_params.data_width-1 downto 0) := (others => '0');
+      wrs_tx_valid_i       : in  std_logic                                        := '0';
+      wrs_tx_dreq_o        : out std_logic;
+      wrs_tx_last_i        : in  std_logic                                        := '1';
+      wrs_tx_flush_i       : in  std_logic                                        := '0';
+      wrs_rx_first_o       : out std_logic;
+      wrs_rx_last_o        : out std_logic;
+      wrs_rx_data_o        : out std_logic_vector(g_rx_streamer_params.data_width-1 downto 0);
+      wrs_rx_valid_o       : out std_logic;
+      wrs_rx_dreq_i        : in  std_logic                                        := '0';
+      wrs_tx_cfg_i         : in t_tx_streamer_cfg := c_tx_streamer_cfg_default;
+      wrs_rx_cfg_i         : in t_rx_streamer_cfg := c_rx_streamer_cfg_default;
+      wb_eth_master_o      : out t_wishbone_master_out;
+      wb_eth_master_i      : in  t_wishbone_master_in                             := cc_dummy_master_in;
+      aux_diag_i           : in  t_generic_word_array(g_diag_ro_size-1 downto 0)  := (others => (others => '0'));
+      aux_diag_o           : out t_generic_word_array(g_diag_rw_size-1 downto 0);
+      tm_dac_value_o       : out std_logic_vector(23 downto 0);
+      tm_dac_wr_o          : out std_logic_vector(g_aux_clks-1 downto 0);
+      tm_clk_aux_lock_en_i : in  std_logic_vector(g_aux_clks-1 downto 0)          := (others => '0');
+      tm_clk_aux_locked_o  : out std_logic_vector(g_aux_clks-1 downto 0);
+      timestamps_o         : out t_txtsu_timestamp;
+      timestamps_ack_i     : in  std_logic                                        := '1';
+      abscal_txts_o        : out std_logic;
+      abscal_rxts_o        : out std_logic;
+      fc_tx_pause_req_i    : in  std_logic                                        := '0';
+      fc_tx_pause_delay_i  : in  std_logic_vector(15 downto 0)                    := x"0000";
+      fc_tx_pause_ready_o  : out std_logic;
+      tm_link_up_o         : out std_logic;
+      tm_time_valid_o      : out std_logic;
+      tm_tai_o             : out std_logic_vector(39 downto 0);
+      tm_cycles_o          : out std_logic_vector(27 downto 0);
+      led_act_o            : out std_logic;
+      led_link_o           : out std_logic;
+      btn1_i               : in  std_logic                                        := '1';
+      btn2_i               : in  std_logic                                        := '1';
+      pps_csync_o          : out std_logic;
+      pps_p_o              : out std_logic;
+      pps_led_o            : out std_logic;
+      link_ok_o            : out std_logic);
+  end component xwrc_board_common;
+
+end wr_board_pkg;
+
+package body wr_board_pkg is
+
+  procedure f_check_fabric_iface_type (
+    constant iface_type : in t_board_fabric_iface) is
+  begin
+    if iface_type >= always_last_invalid then
+      assert FALSE
+        report "WR PTP core fabric interface [" & t_board_fabric_iface'image(iface_type) & "] is not supported"
+        severity FAILURE;
+    end if;
+  end procedure f_check_fabric_iface_type;
+
+  procedure f_check_diag_id (
+    constant diag_id, diag_ver : in integer) is
+  begin
+    assert (diag_id /= 1) report
+      "g_diag_id=1 is reserved for wr_streamers and cannot be set by users"
+      severity FAILURE;
+
+    assert (not (diag_id /= 0 and diag_ver = 0)) report
+      "If diag_id is set by the user (diag_id > 1), g_diag_ver must be at least 1"
+      severity FAILURE;
+  end procedure f_check_diag_id;
+
+  function f_str2iface_type (
+    constant iface_str : string(1 to 9))
+    return t_board_fabric_iface is
+    variable result : t_board_fabric_iface;
+  begin
+    case iface_str is
+      when "PLAINFBRC" => result := PLAIN;
+      when "STREAMERS" => result := STREAMERS;
+      when "ETHERBONE" => result := ETHERBONE;
+      when others      => result := always_last_invalid;
+    end case;
+    return result;
+  end function f_str2iface_type;
+
+  -- this function decides what is the diag_id/ver used in the WRPC and MIB for access
+  -- via SNMP
+  function f_pick_diag_val (
+    iface           : t_board_fabric_iface;
+    streamers_val   : integer;
+    application_val : integer
+    ) return integer is
+  begin
+    -- streamers are enabled and application/user does nto use diags (no vector specified),
+    -- use default streamer's id/ver
+    if(iface = STREAMERS and application_val = 0) then
+      return streamers_val;
+    else  -- otherwise, use id/ver specified by the user/application. This is the case also
+      -- when streamers are used.
+      return application_val;
+    end if;
+  end f_pick_diag_val;
+
+  -- provide the size of the final diag array.
+  function f_pick_diag_size (
+    iface            : t_board_fabric_iface;
+    streamers_size   : integer;
+    application_size : integer
+    ) return integer is
+  begin
+    -- when streamers are used, concatenate the array of streamers and application/user
+    if(iface = STREAMERS) then
+      return (streamers_size+application_size);
+    else  -- otherwise, only the size provided by the application/user
+      return application_size;
+    end if;
+  end f_pick_diag_size;
+
+  function f_vectorize_diag (
+    diag_in          : t_generic_word_array;
+    diag_vector_size : integer)
+    return std_logic_vector is
+    variable result : std_logic_vector(diag_vector_size-1 downto 0);
+  begin
+    assert (diag_vector_size mod 32 = 0) report
+      "g_diag_ro/w_vector_width must have value that is a mutiple of 32"
+      severity FAILURE;
+    for i in 0 to diag_vector_size/32-1 loop
+      result(i*32-31 downto i*32) := diag_in(i);
+    end loop;
+    return result;
+  end function f_vectorize_diag;
+
+  function f_de_vectorize_diag (
+    diag_in          : std_logic_vector;
+    diag_vector_size : integer)
+    return t_generic_word_array is
+    variable result : t_generic_word_array(diag_vector_size/32-1 downto 0);
+  begin
+    assert (diag_vector_size mod 32 = 0) report
+      "g_diag_ro/w_vector_width must have value that is a mutiple of 32"
+      severity FAILURE;
+    for i in 0 to diag_vector_size/32-1 loop
+      result(i) := diag_in(i*32-31 downto i*32);
+    end loop;
+    return result;
+  end function f_de_vectorize_diag;
+
+  function f_find_default_lm32_firmware (
+    dpram_initf : string;
+    simulation  : integer;
+    pcs_16_bit  : boolean)
+    return string is
+  begin
+    if((dpram_initf = "default_altera" or dpram_initf = "default_xilinx") and
+       pcs_16_bit = TRUE) then
+      assert FALSE
+        report "[Board:Software for LM32 in WR Core] No release binary for " &
+        "pcs_16_bit." severity FAILURE;
+      return "";
+    elsif (dpram_initf /= "default_altera" and dpram_initf /= "default_xilinx") then
+      report "[Board:Software for LM32 in WR Core]  Using user-provided LM32 " &
+        "firmware ("&dpram_initf&")." severity NOTE;
+      return dpram_initf;
+    elsif (simulation = 0 and dpram_initf = "default_altera" and pcs_16_bit = FALSE and
+           dpram_initf_default_altera_phy8 /= "") then
+      report "[Board:Software for LM32 in WR Core] Using release LM32 firmware " &
+        "(altera, phy8)." severity NOTE;
+      return dpram_initf_default_altera_phy8;
+    elsif (simulation = 0 and dpram_initf = "default_xilinx" and pcs_16_bit = FALSE and
+           dpram_initf_default_xilinx_phy8 /= "") then
+      report "[Board:Software for LM32 in WR Core] Using release LM32 firmware " &
+        "(xilnix, phy8)" severity NOTE;
+      return dpram_initf_default_xilinx_phy8;
+    elsif (simulation = 1 and dpram_initf = "default_altera" and pcs_16_bit = FALSE and
+           dpram_initf_default_altera_phy8_sim /= "") then
+      report "Board:[Software for LM32 in WR Core] Using release LM32 firmware " &
+        "(altera, phy8, sim)." severity NOTE;
+      return dpram_initf_default_altera_phy8_sim;
+    elsif (simulation = 1 and dpram_initf = "default_xilinx" and pcs_16_bit = FALSE and
+           dpram_initf_default_xilinx_phy8_sim /= "") then
+      report "[Board:Software for LM32 in WR Core] Using release LM32 firmware " &
+        "(xilinx, phy8, sim)." severity NOTE;
+      return dpram_initf_default_xilinx_phy8_sim;
+    else
+      assert FALSE
+        report "[Board:Software for LM32 in WR Core] Default inclussion of LM32" &
+        "binary with software is not supported yet. In your instantiation" &
+        "of the board (xwrc_board_{spec,svec,vfchd} set g_dpram_initf to the" &
+        "correct path, i.e." &
+        "<your wr-cores location>/bin/wrpc/wrc_phy8_sim.{bram, mif} " severity FAILURE;
+      return "";
+    end if;
+  end function;
+
+end package body wr_board_pkg;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/board/common/xwrc_board_common.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/board/common/xwrc_board_common.vhd
new file mode 100644
index 000000000..1ec195920
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/board/common/xwrc_board_common.vhd
@@ -0,0 +1,552 @@
+-------------------------------------------------------------------------------
+-- Title      : Common WRPC Wrapper
+-- Project    : WR PTP Core
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
+-------------------------------------------------------------------------------
+-- File       : xwrc_board_common.vhd
+-- Company    : CERN (BE-CO-HT)
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Wrapper for WR PTP core with common features shared between
+-- the various supported boards. These include the core itself, as well as
+-- a selection of fabric interfaces between the core and the application.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2017 CERN
+--
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-- 
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.gencores_pkg.all;
+use work.wrcore_pkg.all;
+use work.wishbone_pkg.all;
+use work.etherbone_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.endpoint_pkg.all;
+use work.streamers_pkg.all;
+use work.wr_board_pkg.all;
+
+entity xwrc_board_common is
+  generic(
+    g_simulation                : integer                        := 0;
+    g_with_external_clock_input : boolean                        := TRUE;
+    g_board_name                : string                         := "NA  ";
+    g_flash_secsz_kb            : integer                        := 256;        -- default for M25P128
+    g_flash_sdbfs_baddr         : integer                        := 16#600000#; -- default for M25P128
+    g_phys_uart                 : boolean                        := TRUE;
+    g_virtual_uart              : boolean                        := TRUE;
+    g_aux_clks                  : integer                        := 0;
+    g_ep_rxbuf_size             : integer                        := 1024;
+    g_tx_runt_padding           : boolean                        := TRUE;
+    g_dpram_initf               : string                         := "";
+    g_dpram_size                : integer                        := 131072/4;
+    g_interface_mode            : t_wishbone_interface_mode      := PIPELINED;
+    g_address_granularity       : t_wishbone_address_granularity := BYTE;
+    g_aux_sdb                   : t_sdb_device                   := c_wrc_periph3_sdb;
+    g_softpll_enable_debugger   : boolean                        := FALSE;
+    g_vuart_fifo_size           : integer                        := 1024;
+    g_pcs_16bit                 : boolean                        := FALSE;
+    g_diag_id                   : integer                        := 0;
+    g_diag_ver                  : integer                        := 0;
+    g_diag_ro_size              : integer                        := 0;
+    g_diag_rw_size              : integer                        := 0;
+    g_streamers_op_mode         : t_streamers_op_mode            := TX_AND_RX;
+    g_tx_streamer_params        : t_tx_streamer_params           := c_tx_streamer_params_defaut;
+    g_rx_streamer_params        : t_rx_streamer_params           := c_rx_streamer_params_defaut;
+    g_fabric_iface              : t_board_fabric_iface           := PLAIN);
+  port(
+    ---------------------------------------------------------------------------
+    -- Clocks/resets
+    ---------------------------------------------------------------------------
+    -- system reference clock (any frequency <= f(clk_ref_i))
+    clk_sys_i : in std_logic;
+
+    -- DDMTD offset clock (125.x MHz)
+    clk_dmtd_i : in std_logic;
+
+    -- Timing reference (125 MHz)
+    clk_ref_i : in std_logic;
+
+    -- Aux clock (i.e. the FMC clock), which can be disciplined by the WR Core
+    clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
+
+    -- External 10 MHz reference (cesium, GPSDO, etc.), used in Grandmaster mode
+    clk_10m_ext_i : in std_logic := '0';
+
+    clk_ext_mul_i        : in  std_logic := '0';
+    clk_ext_mul_locked_i : in  std_logic := '1';
+    clk_ext_stopped_i    : in  std_logic := '0';
+    clk_ext_rst_o        : out std_logic;
+
+    -- External PPS input (cesium, GPSDO, etc.), used in Grandmaster mode
+    pps_ext_i : in std_logic := '0';
+
+    rst_n_i : in std_logic;
+
+    ---------------------------------------------------------------------------
+    --Timing system
+    ---------------------------------------------------------------------------
+    dac_hpll_load_p1_o : out std_logic;
+    dac_hpll_data_o    : out std_logic_vector(15 downto 0);
+
+    dac_dpll_load_p1_o : out std_logic;
+    dac_dpll_data_o    : out std_logic_vector(15 downto 0);
+
+    ---------------------------------------------------------------------------
+    -- PHY I/f
+    ---------------------------------------------------------------------------
+    phy8_o  : out t_phy_8bits_from_wrc;
+    phy8_i  : in  t_phy_8bits_to_wrc  := c_dummy_phy8_to_wrc;
+    phy16_o : out t_phy_16bits_from_wrc;
+    phy16_i : in  t_phy_16bits_to_wrc := c_dummy_phy16_to_wrc;
+
+    ---------------------------------------------------------------------------
+    -- I2C EEPROM
+    ---------------------------------------------------------------------------
+    scl_o : out std_logic;
+    scl_i : in  std_logic := '1';
+    sda_o : out std_logic;
+    sda_i : in  std_logic := '1';
+
+    ---------------------------------------------------------------------------
+    -- SFP management info
+    ---------------------------------------------------------------------------
+    sfp_scl_o : out std_logic;
+    sfp_scl_i : in  std_logic := '1';
+    sfp_sda_o : out std_logic;
+    sfp_sda_i : in  std_logic := '1';
+    sfp_det_i : in  std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Flash memory SPI interface
+    ---------------------------------------------------------------------------
+    spi_sclk_o : out std_logic;
+    spi_ncs_o  : out std_logic;
+    spi_mosi_o : out std_logic;
+    spi_miso_i : in  std_logic := '0';
+
+    ---------------------------------------------------------------------------
+    --UART
+    ---------------------------------------------------------------------------
+    uart_rxd_i : in  std_logic := '0';
+    uart_txd_o : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- 1-wire
+    ---------------------------------------------------------------------------
+    owr_pwren_o : out std_logic_vector(1 downto 0);
+    owr_en_o    : out std_logic_vector(1 downto 0);
+    owr_i       : in  std_logic_vector(1 downto 0) := (others => '1');
+
+    ---------------------------------------------------------------------------
+    --External WB interface
+    ---------------------------------------------------------------------------
+    wb_slave_i : in  t_wishbone_slave_in := cc_dummy_slave_in;
+    wb_slave_o : out t_wishbone_slave_out;
+
+    aux_master_o : out t_wishbone_master_out;
+    aux_master_i : in  t_wishbone_master_in := cc_dummy_master_in;
+
+    ---------------------------------------------------------------------------
+    -- External Fabric I/F (when g_fabric_iface = PLAIN)
+    ---------------------------------------------------------------------------
+    wrf_src_o : out t_wrf_source_out;
+    wrf_src_i : in  t_wrf_source_in := c_dummy_src_in;
+    wrf_snk_o : out t_wrf_sink_out;
+    wrf_snk_i : in  t_wrf_sink_in   := c_dummy_snk_in;
+
+    ---------------------------------------------------------------------------
+    -- WR streamers (when g_fabric_iface = STREAMERS)
+    ---------------------------------------------------------------------------
+    wrs_tx_data_i  : in  std_logic_vector(g_tx_streamer_params.data_width-1 downto 0) := (others => '0');
+    wrs_tx_valid_i : in  std_logic                                        := '0';
+    wrs_tx_dreq_o  : out std_logic;
+    wrs_tx_last_i  : in  std_logic                                        := '1';
+    wrs_tx_flush_i : in  std_logic                                        := '0';
+    wrs_rx_first_o : out std_logic;
+    wrs_rx_last_o  : out std_logic;
+    wrs_rx_data_o  : out std_logic_vector(g_rx_streamer_params.data_width-1 downto 0);
+    wrs_rx_valid_o : out std_logic;
+    wrs_rx_dreq_i  : in  std_logic                                        := '0';
+    wrs_tx_cfg_i   : in t_tx_streamer_cfg := c_tx_streamer_cfg_default;
+    wrs_rx_cfg_i   : in t_rx_streamer_cfg := c_rx_streamer_cfg_default;
+    ---------------------------------------------------------------------------
+    -- Etherbone WB master interface (when g_fabric_iface = ETHERBONE)
+    ---------------------------------------------------------------------------
+    wb_eth_master_o : out t_wishbone_master_out;
+    wb_eth_master_i : in  t_wishbone_master_in := cc_dummy_master_in;
+
+    ---------------------------------------------------------------------------
+    -- Generic diagnostics interface (access from WRPC via SNMP or uart console
+    ---------------------------------------------------------------------------
+    aux_diag_i : in  t_generic_word_array(g_diag_ro_size-1 downto 0) := (others => (others => '0'));
+    aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0);
+
+    ---------------------------------------------------------------------------
+    -- Aux clocks control
+    ---------------------------------------------------------------------------
+    tm_dac_value_o       : out std_logic_vector(23 downto 0);
+    tm_dac_wr_o          : out std_logic_vector(g_aux_clks-1 downto 0);
+    tm_clk_aux_lock_en_i : in  std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
+    tm_clk_aux_locked_o  : out std_logic_vector(g_aux_clks-1 downto 0);
+
+    ---------------------------------------------------------------------------
+    -- External Tx Timestamping I/F
+    ---------------------------------------------------------------------------
+    timestamps_o     : out t_txtsu_timestamp;
+    timestamps_ack_i : in  std_logic := '1';
+
+    -----------------------------------------
+    -- Timestamp helper signals, used for Absolute Calibration
+    -----------------------------------------
+    abscal_txts_o               : out std_logic;
+    abscal_rxts_o               : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Pause Frame Control
+    ---------------------------------------------------------------------------
+    fc_tx_pause_req_i   : in  std_logic                     := '0';
+    fc_tx_pause_delay_i : in  std_logic_vector(15 downto 0) := x"0000";
+    fc_tx_pause_ready_o : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Timecode I/F
+    ---------------------------------------------------------------------------
+    tm_link_up_o    : out std_logic;
+    tm_time_valid_o : out std_logic;
+    tm_tai_o        : out std_logic_vector(39 downto 0);
+    tm_cycles_o     : out std_logic_vector(27 downto 0);
+
+    ---------------------------------------------------------------------------
+    -- Buttons, LEDs and PPS output
+    ---------------------------------------------------------------------------
+    led_act_o  : out std_logic;
+    led_link_o : out std_logic;
+    btn1_i     : in  std_logic := '1';
+    btn2_i     : in  std_logic := '1';
+    -- 1PPS output
+    pps_csync_o : out std_logic;
+    pps_p_o     : out std_logic;
+    pps_led_o   : out std_logic;
+    -- Link ok indication
+    link_ok_o : out std_logic
+    );
+
+end entity xwrc_board_common;
+
+
+architecture struct of xwrc_board_common is
+
+  -----------------------------------------------------------------------------
+  -- Signals
+  -----------------------------------------------------------------------------
+
+  -- Timecode interface
+  signal tm_time_valid : std_logic;
+  signal tm_tai        : std_logic_vector(39 downto 0);
+  signal tm_cycles     : std_logic_vector(27 downto 0);
+
+  -- WR fabric interface
+  signal wrf_src_out : t_wrf_source_out;
+  signal wrf_src_in  : t_wrf_source_in;
+  signal wrf_snk_out : t_wrf_sink_out;
+  signal wrf_snk_in  : t_wrf_sink_in;
+
+  -- Aux WB interface
+  signal aux_master_out : t_wishbone_master_out;
+  signal aux_master_in  : t_wishbone_master_in;
+  signal aux_rst_n      : std_logic;
+
+  -- Aux diagnostics:
+  -- 1) streamers have their own ID not to be used by the users
+  -- 2) regardless whether streamers are enabled nor not, application can use diagnostics
+  -- 3) if application uses diagnostics, it must specify diag_id > 1, diag_ver should start
+  --    with 1.
+  -- Application diagnostic words are added after streamer's diagnostics in the array that
+  -- goes to/from WRPC
+
+  constant c_streamers_diag_id  : integer := 1;  -- id reserved for streamers
+  constant c_streamers_diag_ver : integer := 2;  -- version that will be probably increased
+  -- when more diagnostics is added to streamers
+
+  -- final values that go to WRPC generics (depend on configuration)
+  constant c_diag_id  : integer := f_pick_diag_val(g_fabric_iface, c_streamers_diag_id, g_diag_id);
+  constant c_diag_ver : integer := f_pick_diag_val(g_fabric_iface, c_streamers_diag_ver, g_diag_id);
+
+  constant c_diag_ro_size : integer := f_pick_diag_size(g_fabric_iface, c_WR_STREAMERS_ARR_SIZE_OUT, g_diag_ro_size);
+  constant c_diag_rw_size : integer := f_pick_diag_size(g_fabric_iface, c_WR_STREAMERS_ARR_SIZE_IN, g_diag_rw_size);
+
+  -- WR SNMP
+  signal aux_diag_in  : t_generic_word_array(c_diag_ro_size-1 downto 0);
+  signal aux_diag_out : t_generic_word_array(c_diag_rw_size-1 downto 0);
+
+  -- link state
+  signal link_ok      : std_logic;
+
+begin  -- architecture struct
+
+  -- Check for unsupported fabric interface type
+  f_check_fabric_iface_type(g_fabric_iface);
+
+  -- check whether diag id and version are correct, i.e.:
+  -- * diag_id =1 is reserved for wr_streamers and cannot be used
+  -- * diag_ver values should start with 1
+  f_check_diag_id(g_diag_id, g_diag_ver);
+
+  -----------------------------------------------------------------------------
+  -- The WR PTP core itself
+  -----------------------------------------------------------------------------
+
+  cmp_xwr_core : xwr_core
+    generic map (
+      g_simulation                => g_simulation,
+      g_with_external_clock_input => g_with_external_clock_input,
+      g_board_name                => g_board_name,
+      g_flash_secsz_kb            => g_flash_secsz_kb,
+      g_flash_sdbfs_baddr         => g_flash_sdbfs_baddr,
+      g_phys_uart                 => g_phys_uart,
+      g_virtual_uart              => g_virtual_uart,
+      g_aux_clks                  => g_aux_clks,
+      g_ep_rxbuf_size             => g_ep_rxbuf_size,
+      g_tx_runt_padding           => g_tx_runt_padding,
+      g_dpram_initf               => f_find_default_lm32_firmware(g_dpram_initf, g_simulation, g_pcs_16bit),
+      g_dpram_size                => g_dpram_size,
+      g_interface_mode            => g_interface_mode,
+      g_address_granularity       => g_address_granularity,
+      g_aux_sdb                   => g_aux_sdb,
+      g_softpll_enable_debugger   => g_softpll_enable_debugger,
+      g_vuart_fifo_size           => g_vuart_fifo_size,
+      g_pcs_16bit                 => g_pcs_16bit,
+      g_records_for_phy           => TRUE,
+      g_diag_id                   => c_diag_id,
+      g_diag_ver                  => c_diag_ver,
+      g_diag_ro_size              => c_diag_ro_size,
+      g_diag_rw_size              => c_diag_rw_size)
+    port map (
+      clk_sys_i            => clk_sys_i,
+      clk_dmtd_i           => clk_dmtd_i,
+      clk_ref_i            => clk_ref_i,
+      clk_aux_i            => clk_aux_i,
+      clk_ext_i            => clk_10m_ext_i,
+      clk_ext_mul_i        => clk_ext_mul_i,
+      clk_ext_mul_locked_i => clk_ext_mul_locked_i,
+      clk_ext_stopped_i    => clk_ext_stopped_i,
+      clk_ext_rst_o        => clk_ext_rst_o,
+      pps_ext_i            => pps_ext_i,
+      rst_n_i              => rst_n_i,
+      dac_hpll_load_p1_o   => dac_hpll_load_p1_o,
+      dac_hpll_data_o      => dac_hpll_data_o,
+      dac_dpll_load_p1_o   => dac_dpll_load_p1_o,
+      dac_dpll_data_o      => dac_dpll_data_o,
+      phy_ref_clk_i        => '0',
+      phy_tx_data_o        => open,
+      phy_tx_k_o           => open,
+      phy_tx_disparity_i   => '0',
+      phy_tx_enc_err_i     => '0',
+      phy_rx_data_i        => (others => '0'),
+      phy_rx_rbclk_i       => '0',
+      phy_rx_k_i           => (others => '0'),
+      phy_rx_enc_err_i     => '0',
+      phy_rx_bitslide_i    => (others => '0'),
+      phy_rst_o            => open,
+      phy_rdy_i            => '1',
+      phy_loopen_o         => open,
+      phy_loopen_vec_o     => open,
+      phy_tx_prbs_sel_o    => open,
+      phy_sfp_tx_fault_i   => '0',
+      phy_sfp_los_i        => '0',
+      phy_sfp_tx_disable_o => open,
+      phy8_o               => phy8_o,
+      phy8_i               => phy8_i,
+      phy16_o              => phy16_o,
+      phy16_i              => phy16_i,
+      led_act_o            => led_act_o,
+      led_link_o           => led_link_o,
+      scl_o                => scl_o,
+      scl_i                => scl_i,
+      sda_o                => sda_o,
+      sda_i                => sda_i,
+      sfp_scl_o            => sfp_scl_o,
+      sfp_scl_i            => sfp_scl_i,
+      sfp_sda_o            => sfp_sda_o,
+      sfp_sda_i            => sfp_sda_i,
+      sfp_det_i            => sfp_det_i,
+      btn1_i               => btn1_i,
+      btn2_i               => btn2_i,
+      spi_sclk_o           => spi_sclk_o,
+      spi_ncs_o            => spi_ncs_o,
+      spi_mosi_o           => spi_mosi_o,
+      spi_miso_i           => spi_miso_i,
+      uart_rxd_i           => uart_rxd_i,
+      uart_txd_o           => uart_txd_o,
+      owr_pwren_o          => owr_pwren_o,
+      owr_en_o             => owr_en_o,
+      owr_i                => owr_i,
+      slave_i              => wb_slave_i,
+      slave_o              => wb_slave_o,
+      aux_master_o         => aux_master_out,
+      aux_master_i         => aux_master_in,
+      wrf_src_o            => wrf_src_out,
+      wrf_src_i            => wrf_src_in,
+      wrf_snk_o            => wrf_snk_out,
+      wrf_snk_i            => wrf_snk_in,
+      timestamps_o         => timestamps_o,
+      timestamps_ack_i     => timestamps_ack_i,
+      abscal_txts_o        => abscal_txts_o,
+      abscal_rxts_o        => abscal_rxts_o,
+      fc_tx_pause_req_i    => fc_tx_pause_req_i,
+      fc_tx_pause_delay_i  => fc_tx_pause_delay_i,
+      fc_tx_pause_ready_o  => fc_tx_pause_ready_o,
+      tm_link_up_o         => tm_link_up_o,
+      tm_dac_value_o       => tm_dac_value_o,
+      tm_dac_wr_o          => tm_dac_wr_o,
+      tm_clk_aux_lock_en_i => tm_clk_aux_lock_en_i,
+      tm_clk_aux_locked_o  => tm_clk_aux_locked_o,
+      tm_time_valid_o      => tm_time_valid,
+      tm_tai_o             => tm_tai,
+      tm_cycles_o          => tm_cycles,
+      pps_csync_o          => pps_csync_o,
+      pps_p_o              => pps_p_o,
+      pps_led_o            => pps_led_o,
+      rst_aux_n_o          => aux_rst_n,
+      aux_diag_i           => aux_diag_in,
+      aux_diag_o           => aux_diag_out,
+      link_ok_o            => link_ok);
+
+  link_ok_o       <= link_ok;
+  tm_time_valid_o <= tm_time_valid;
+  tm_tai_o        <= tm_tai;
+  tm_cycles_o     <= tm_cycles;
+
+  gen_wr_streamers : if (g_fabric_iface = STREAMERS) generate
+
+    cmp_xwr_streamers : xwr_streamers
+      generic map (
+        g_streamers_op_mode  => g_streamers_op_mode,
+        g_tx_streamer_params => g_tx_streamer_params,
+        g_rx_streamer_params => g_rx_streamer_params,
+        g_simulation         => g_simulation)
+      port map (
+        clk_sys_i       => clk_sys_i,
+        rst_n_i         => rst_n_i,
+        src_i           => wrf_snk_out,
+        src_o           => wrf_snk_in,
+        snk_i           => wrf_src_out,
+        snk_o           => wrf_src_in,
+        tx_data_i       => wrs_tx_data_i,
+        tx_valid_i      => wrs_tx_valid_i,
+        tx_dreq_o       => wrs_tx_dreq_o,
+        tx_last_p1_i    => wrs_tx_last_i,
+        tx_flush_p1_i   => wrs_tx_flush_i,
+        rx_first_p1_o   => wrs_rx_first_o,
+        rx_last_p1_o    => wrs_rx_last_o,
+        rx_data_o       => wrs_rx_data_o,
+        rx_valid_o      => wrs_rx_valid_o,
+        rx_dreq_i       => wrs_rx_dreq_i,
+        clk_ref_i       => clk_ref_i,
+        tm_time_valid_i => tm_time_valid,
+        tm_tai_i        => tm_tai,
+        tm_cycles_i     => tm_cycles,
+        link_ok_i       => link_ok,
+        wb_slave_i      => aux_master_out,
+        wb_slave_o      => aux_master_in,
+        snmp_array_o    => aux_diag_in(c_WR_STREAMERS_ARR_SIZE_OUT-1 downto 0),
+        snmp_array_i    => aux_diag_out(c_WR_STREAMERS_ARR_SIZE_IN-1 downto 0),
+        tx_streamer_cfg_i=> wrs_tx_cfg_i,
+        rx_streamer_cfg_i=> wrs_rx_cfg_i);
+
+    -- unused output ports
+    wrf_src_o <= c_dummy_snk_in;
+    wrf_snk_o <= c_dummy_src_in;
+
+    aux_master_o    <= cc_dummy_master_out;
+    wb_eth_master_o <= cc_dummy_master_out;
+
+    aux_diag_in(c_diag_ro_size-1 downto c_WR_STREAMERS_ARR_SIZE_OUT) <= aux_diag_i;
+    aux_diag_o                                                   <= aux_diag_out(c_diag_rw_size-1 downto c_WR_STREAMERS_ARR_SIZE_IN);
+
+  end generate gen_wr_streamers;
+
+  gen_etherbone : if (g_fabric_iface = ETHERBONE) generate
+
+    cmp_eb_ethernet_slave : eb_ethernet_slave
+      generic map (
+        g_sdb_address => x"0000000000030000")
+      port map (
+        clk_i       => clk_sys_i,
+        nRst_i      => aux_rst_n,
+        src_o       => wrf_snk_in,
+        src_i       => wrf_snk_out,
+        snk_o       => wrf_src_in,
+        snk_i       => wrf_src_out,
+        cfg_slave_o => aux_master_in,
+        cfg_slave_i => aux_master_out,
+        master_o    => wb_eth_master_o,
+        master_i    => wb_eth_master_i);
+
+    -- unused output ports
+    wrf_src_o <= c_dummy_snk_in;
+    wrf_snk_o <= c_dummy_src_in;
+
+    wrs_tx_dreq_o  <= '0';
+    wrs_rx_first_o <= '0';
+    wrs_rx_last_o  <= '0';
+    wrs_rx_valid_o <= '0';
+    wrs_rx_data_o  <= (others => '0');
+
+    aux_master_o <= cc_dummy_master_out;
+
+    -- unused inputs to WR PTP core
+    aux_diag_in <= aux_diag_i;
+    aux_diag_o  <= aux_diag_out;
+
+  end generate gen_etherbone;
+
+  gen_wr_fabric : if (g_fabric_iface = PLAIN) generate
+
+    wrf_src_o <= wrf_src_out;
+    wrf_snk_o <= wrf_snk_out;
+
+    wrf_src_in <= wrf_src_i;
+    wrf_snk_in <= wrf_snk_i;
+
+    -- unused output ports
+    wrs_tx_dreq_o  <= '0';
+    wrs_rx_first_o <= '0';
+    wrs_rx_last_o  <= '0';
+    wrs_rx_valid_o <= '0';
+    wrs_rx_data_o  <= (others => '0');
+
+    wb_eth_master_o <= cc_dummy_master_out;
+
+    aux_master_in <= aux_master_i;
+    aux_master_o  <= aux_master_out;
+
+    -- unused inputs to WR PTP core
+    aux_diag_in <= aux_diag_i;
+    aux_diag_o  <= aux_diag_out;
+
+  end generate gen_wr_fabric;
+
+end architecture struct;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/board/eeprom/sfp_eeprom.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/board/eeprom/sfp_eeprom.vhd
new file mode 100644
index 000000000..673b361d2
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/board/eeprom/sfp_eeprom.vhd
@@ -0,0 +1,161 @@
+-------------------------------------------------------------------------------
+--
+-- File: sfp_eeprom.vhd
+-- Author: National Instruments
+-- Original Project: N310
+-- Date: 22 February 2018
+--
+-------------------------------------------------------------------------------
+-- Copyright 2018 Ettus Research, A National Instruments Company
+-- SPDX-License-Identifier: LGPL-3.0
+-------------------------------------------------------------------------------
+--
+-- Purpose:
+--
+-- Responds to I2C reads from the WRC to pretend to be an AXGE SFP module.
+--
+-------------------------------------------------------------------------------
+
+library IEEE;
+
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+
+entity sfp_eeprom is
+
+  port (
+    -- clock & reset
+    clk_i     : in std_logic;
+    sfp_scl   : in std_logic;
+    sfp_sda_i : in std_logic;
+    sfp_sda_o : out std_logic
+  );
+end sfp_eeprom;
+
+
+architecture syn of sfp_eeprom is
+
+  signal SfpSdaIn_ms    : std_logic := '0';
+  signal SfpSdaIn       : std_logic := '0';
+  signal SfpSdaInDel    : std_logic := '0';
+  signal SfpScl_ms      : std_logic := '0';
+  signal SfpScl         : std_logic := '0';
+  signal SfpSclDel      : std_logic := '0';
+  signal SfpSdaOut      : std_logic := '1';
+
+  signal ClockRe        : boolean := false;
+  signal ClockFe        : boolean := false;
+  signal DataFe         : boolean := false;
+  signal DataRe         : boolean := false;
+  signal Running        : boolean := false;
+  signal ReadSel        : boolean := false;
+
+  signal BitCount       : integer range -1 to 7 := 7;
+  signal AddrCount      : unsigned(4 downto 0) := (others=>'0');
+  signal ByteCount      : integer range 0 to 143;
+
+  type   Eeprom_t       is array(0 to 143) of std_logic_vector(7 downto 0);
+  signal Eeprom         : Eeprom_t := (
+  X"03", X"04", X"07", X"00", X"00", X"00", X"40", X"00", X"00", X"00", X"00", X"01", X"0d", X"00", X"0a", X"64",
+  X"00", X"00", X"00", X"00", X"41", X"78", X"63", X"65", X"6e", X"20", X"50", X"68", X"6f", X"74", X"6f", X"6e",
+  X"69", X"63", X"73", X"20", X"00", X"00", X"17", X"2d", X"41", X"58", X"47", X"45", X"2d", X"31", X"32", X"35",
+  X"34", X"2d", X"30", X"35", X"33", X"31", X"20", X"20", X"56", X"31", X"2e", X"31", X"05", X"1e", X"00", X"51",
+  X"00", X"1a", X"00", X"00", X"41", X"58", X"31", X"36", X"35", X"30", X"30", X"30", X"30", X"36", X"37", X"36",
+  X"39", X"20", X"20", X"20", X"31", X"36", X"31", X"32", X"30", X"38", X"20", X"20", X"00", X"00", X"00", X"bd",
+  X"45", X"58", X"54", X"52", X"45", X"4d", X"45", X"4c", X"59", X"20", X"43", X"4f", X"4d", X"50", X"41", X"54",
+  X"49", X"42", X"4c", X"45", X"20", X"20", X"20", X"20", X"20", X"20", X"20", X"20", X"20", X"20", X"20", X"20",
+  X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF");
+
+  -- AXGE Optical
+  --      0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
+  -- 00: 03 04 07 00 00 00 40 00 00 00 00 01 0d 00 0a 64    ???...@....??.?d
+  -- 10: 00 00 00 00 41 78 63 65 6e 20 50 68 6f 74 6f 6e    ....Axcen Photon
+  -- 20: 69 63 73 20 00 00 17 2d 41 58 47 45 2d 31 32 35    ics ..?-AXGE-125
+  -- 30: 34 2d 30 35 33 31 20 20 56 31 2e 31 05 1e 00 51    4-0531  V1.1??.Q
+  -- 40: 00 1a 00 00 41 58 31 36 35 30 30 30 30 36 37 36    .?..AX1650000676
+  -- 50: 39 20 20 20 31 36 31 32 30 38 20 20 00 00 00 bd    9   161208  ...?
+  -- 60: 45 58 54 52 45 4d 45 4c 59 20 43 4f 4d 50 41 54    EXTREMELY COMPAT
+  -- 70: 49 42 4c 45 20 20 20 20 20 20 20 20 20 20 20 20    IBLE
+  -- 80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
+
+begin
+
+  sfp_sda_o <= SfpSdaOut;
+
+  -- Double syncs on the I2C lines
+  process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      SfpSdaIn_ms  <= sfp_sda_i;
+      SfpSdaIn     <= SfpSdaIn_ms;
+      SfpSdaInDel  <= SfpSdaIn;
+
+      SfpScl_ms    <= sfp_scl;
+      SfpScl       <= SfpScl_ms;
+      SfpSclDel    <= SfpScl;
+    end if;
+  end process;
+
+  ClockRe <= SfpScl='1' and SfpSclDel='0';
+  ClockFe <= SfpScl='0' and SfpSclDel='1';
+  DataRe  <= SfpSdaIn='1' and SfpSdaInDel='0';
+  DataFe  <= SfpSdaIn='0' and SfpSdaInDel='1';
+
+  process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      SfpSdaOut <= '1';
+      if (DataFe and SfpScl='1') or not Running then   -- detect start condition
+        BitCount <= 7;
+        AddrCount <= (others=>'0');
+        --ByteCount <= 0;
+        Running <= true;
+        ReadSel <= false;
+      else                            -- if running, then start generating data
+        if DataRe and SfpScl='1' then -- detect stop condition
+          Running <= false;
+        elsif AddrCount<9 then
+          if ClockFe then
+            AddrCount <= AddrCOunt + 1;
+            if AddrCount=8 then
+              if SfpSdaIn='0' then      -- reset byte count for write operation
+                ByteCount <= 0;
+              end if;
+              ReadSel <= SfpSdaIn='1';
+            end if;
+          end if;
+        elsif AddrCount=9 then
+          SfpSdaOut <= '0';           -- output ACK and hold it for a clock tick
+          if ClockFe then
+            AddrCount <= AddrCOunt + 1;
+          end if;
+        else
+          if BitCount>=0 then         -- shift out 8 bits if it's a read
+            if ReadSel then
+              SfpSdaOut <= Eeprom(ByteCount)(BitCount);
+            else
+              SfpSdaOut <= '1';
+            end if;
+            if ClockFe then
+              BitCount <= BitCOunt - 1;
+            end if;
+          else                        -- ignore ACK, update byte counter
+            SfpSdaOut <= '0';
+            if ClockFe then
+              if ReadSel then
+                if ByteCount<143 then
+                  ByteCount <= ByteCount + 1;
+                else
+                  ByteCount <= 143;    -- play X"FF" for all remaining bytes
+                end if;
+              end if;
+              BitCount <= 7;
+            end if;
+          end if;
+        end if;
+      end if;                         -- Running
+    end if;
+  end process;
+
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/board/eeprom/tb_sfp_eeprom.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/board/eeprom/tb_sfp_eeprom.vhd
new file mode 100644
index 000000000..4eec0765c
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/board/eeprom/tb_sfp_eeprom.vhd
@@ -0,0 +1,96 @@
+-------------------------------------------------------------------------------
+--
+-- File: tb_sfp_eeprom.vhd
+-- Author: National Instruments
+-- Original Project: N310
+-- Date: 22 February 2018
+--
+-------------------------------------------------------------------------------
+-- Copyright 2018 Ettus Research, A National Instruments Company
+-- SPDX-License-Identifier: LGPL-3.0
+-------------------------------------------------------------------------------
+--
+-- Purpose:
+--
+-- Testbench for sfp_eeprom.vhd
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.numeric_std.all;
+
+entity tb_sfp_eeprom is
+end tb_sfp_eeprom;
+
+architecture test of tb_sfp_eeprom is
+
+  constant kHalfPeriod    : time := 25 ns;
+
+  signal clk_i     : std_logic := '1';
+  signal sfp_scl   : std_logic := '1';
+  signal sfp_sda_i : std_logic := '1';
+  signal sfp_sda_o : std_logic := '1';
+
+
+  signal StopSim : boolean := false;
+
+  -- This procedure waits for X rising edges of Clk
+  procedure ClkWait (X : integer := 1) is
+  begin
+    for i in 1 to X loop
+      wait until rising_edge(clk_i);
+    end loop;
+  end procedure ClkWait;
+
+  component sfp_eeprom
+  port (
+    clk_i     : in std_logic;
+    sfp_scl   : in std_logic;
+    sfp_sda_i : in std_logic;
+    sfp_sda_o : out std_logic);
+  end component;
+
+begin
+
+  -- Set up the clock(s)
+  clk_i <= not clk_i after kHalfPeriod when not StopSim else '0';
+
+
+  DUT: sfp_eeprom
+    port map (
+      clk_i => clk_i,
+      sfp_scl => sfp_scl,
+      sfp_sda_i => sfp_sda_i,
+      sfp_sda_o => sfp_sda_o );
+
+
+  Sim: process
+  begin
+    for K in 0 to 1 loop
+      wait for 210 ns;
+      -- send start condition
+      sfp_sda_i <= '0';
+      wait for 210 ns;
+      sfp_scl <= '0';
+      wait for 210 ns;
+      for I in 0 to 150 loop
+        for J in 0 to 8 loop
+          sfp_scl <= '1';
+          wait for 210 ns;
+          sfp_scl <= '0';
+          wait for 210 ns;
+        end loop;
+        wait for 210 ns;
+      end loop;
+      sfp_scl <= '1';
+      wait for 210 ns;
+      sfp_sda_i <= '1';
+      wait for 210 ns;
+    end loop;
+    StopSim <= true;
+    wait;
+  end process Sim;
+
+
+end test;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/board/fasec/wr_fasec_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/board/fasec/wr_fasec_pkg.vhd
new file mode 100644
index 000000000..eeb3c81b9
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/board/fasec/wr_fasec_pkg.vhd
@@ -0,0 +1,198 @@
+-------------------------------------------------------------------------------
+-- Title      : WRPC Wrapper for FASEC package
+-- Project    : WR PTP Core
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
+-------------------------------------------------------------------------------
+-- File       : wr_fasec_pkg.vhd
+-- Author(s)  : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
+-- Company    : CERN (BE-CO-HT)
+-- Created    : 2017-08-02
+-- Last update: 2017-09-07
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2017 CERN
+--
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-- 
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.wishbone_pkg.all;
+use work.wrcore_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.endpoint_pkg.all;
+use work.wr_board_pkg.all;
+use work.streamers_pkg.all;
+
+package wr_fasec_pkg is
+
+  component xwrc_board_fasec
+    generic(
+      g_simulation                : integer              := 0;
+      g_with_external_clock_input : boolean              := TRUE;
+      g_aux_clks                  : integer              := 0;
+      g_fabric_iface              : t_board_fabric_iface := plain;
+      g_streamers_op_mode         : t_streamers_op_mode  := TX_AND_RX;
+      g_tx_streamer_params        : t_tx_streamer_params := c_tx_streamer_params_defaut;
+      g_rx_streamer_params        : t_rx_streamer_params := c_rx_streamer_params_defaut;
+      g_dpram_initf               : string               := "default_xilinx";
+      g_diag_id                   : integer              := 0;
+      g_diag_ver                  : integer              := 0;
+      g_diag_ro_size              : integer              := 0;
+      g_diag_rw_size              : integer              := 0);
+    port (
+      areset_n_i          : in  std_logic;
+      areset_edge_n_i     : in  std_logic := '1';
+      clk_20m_vcxo_i      : in  std_logic;
+      clk_125m_pllref_p_i : in  std_logic;
+      clk_125m_pllref_n_i : in  std_logic;
+      clk_125m_gtp_n_i    : in  std_logic;
+      clk_125m_gtp_p_i    : in  std_logic;
+      clk_aux_i           : in  std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
+      clk_10m_ext_i       : in  std_logic                               := '0';
+      pps_ext_i           : in  std_logic                               := '0';
+      clk_sys_62m5_o      : out std_logic;
+      clk_ref_125m_o      : out std_logic;
+      rst_sys_62m5_n_o    : out std_logic;
+      rst_ref_125m_n_o    : out std_logic;
+  
+      plldac_sclk_o   : out std_logic;
+      plldac_din_o    : out std_logic;
+      pll25dac_cs_n_o : out std_logic;
+      pll20dac_cs_n_o : out std_logic;
+  
+      sfp_txp_o         : out std_logic;
+      sfp_txn_o         : out std_logic;
+      sfp_rxp_i         : in  std_logic;
+      sfp_rxn_i         : in  std_logic;
+      sfp_det_i         : in  std_logic := '1';
+      sfp_sda_i         : in  std_logic;
+      sfp_sda_o         : out std_logic;
+      sfp_sda_t         : out std_logic;
+      sfp_scl_i         : in  std_logic;
+      sfp_scl_o         : out std_logic;
+      sfp_scl_t         : out std_logic;
+      sfp_rate_select_o : out std_logic;
+      sfp_tx_fault_i    : in  std_logic := '0';
+      sfp_tx_disable_o  : out std_logic;
+      sfp_los_i         : in  std_logic := '0';
+  
+      eeprom_sda_i : in  std_logic;
+      eeprom_sda_o : out std_logic;
+      eeprom_sda_t : out std_logic;
+      eeprom_scl_i : in  std_logic;
+      eeprom_scl_o : out std_logic;
+      eeprom_scl_t : out std_logic;
+    
+      thermo_id_i : in  std_logic;
+      thermo_id_o : out std_logic;
+      thermo_id_t : out std_logic;
+      uart_rxd_i : in  std_logic;
+      uart_txd_o : out std_logic;
+  
+      flash_sclk_o : out std_logic;
+      flash_ncs_o  : out std_logic;
+      flash_mosi_o : out std_logic;
+      flash_miso_i : in  std_logic := '0';
+  
+      aux_master_o : out t_wishbone_master_out;
+      aux_master_i : in  t_wishbone_master_in := cc_dummy_master_in;
+  
+      s00_axi_aclk_o  : out std_logic;
+      s00_axi_aresetn : in  std_logic;
+      s00_axi_awaddr  : in std_logic_vector(31 downto 0);
+      s00_axi_awprot  : in  std_logic_vector(2 downto 0);
+      s00_axi_awvalid : in  std_logic;
+      s00_axi_awready : out std_logic;
+      s00_axi_wdata   : in std_logic_vector(31 downto 0);
+      s00_axi_wstrb   : in std_logic_vector(3 downto 0);
+      s00_axi_wvalid  : in  std_logic;
+      s00_axi_wready  : out std_logic;
+      s00_axi_bresp   : out std_logic_vector(1 downto 0);
+      s00_axi_bvalid  : out std_logic;
+      s00_axi_bready  : in std_logic;
+      s00_axi_araddr  : in std_logic_vector(31 downto 0);
+      s00_axi_arprot  : in std_logic_vector(2 downto 0);
+      s00_axi_arvalid : in std_logic;
+      s00_axi_arready : out std_logic;
+      s00_axi_rdata   : out std_logic_vector(31 downto 0);
+      s00_axi_rresp   : out std_logic_vector(1 downto 0);
+      s00_axi_rvalid  : out std_logic;
+      s00_axi_rready  : in std_logic;
+      s00_axi_rlast   : out std_logic;
+      axi_int_o       : out std_logic;
+  
+      wrf_src_o : out t_wrf_source_out;
+      wrf_src_i : in  t_wrf_source_in := c_dummy_src_in;
+      wrf_snk_o : out t_wrf_sink_out;
+      wrf_snk_i : in  t_wrf_sink_in   := c_dummy_snk_in;
+  
+      wrs_tx_data_i  : in  std_logic_vector(g_tx_streamer_params.data_width-1 downto 0) := (others => '0');
+      wrs_tx_valid_i : in  std_logic                                        := '0';
+      wrs_tx_dreq_o  : out std_logic;
+      wrs_tx_last_i  : in  std_logic                                        := '1';
+      wrs_tx_flush_i : in  std_logic                                        := '0';
+      wrs_tx_cfg_i   : in  t_tx_streamer_cfg                                := c_tx_streamer_cfg_default;
+      wrs_rx_first_o : out std_logic;
+      wrs_rx_last_o  : out std_logic;
+      wrs_rx_data_o  : out std_logic_vector(g_rx_streamer_params.data_width-1 downto 0);
+      wrs_rx_valid_o : out std_logic;
+      wrs_rx_dreq_i  : in  std_logic                                        := '0';
+      wrs_rx_cfg_i   : in t_rx_streamer_cfg                                 := c_rx_streamer_cfg_default;
+
+      wb_eth_master_o : out t_wishbone_master_out;
+      wb_eth_master_i : in  t_wishbone_master_in := cc_dummy_master_in;
+  
+      aux_diag_i : in  t_generic_word_array(g_diag_ro_size-1 downto 0) := (others => (others => '0'));
+      aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0);
+  
+      tm_dac_value_o       : out std_logic_vector(23 downto 0);
+      tm_dac_wr_o          : out std_logic_vector(g_aux_clks-1 downto 0);
+      tm_clk_aux_lock_en_i : in  std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
+      tm_clk_aux_locked_o  : out std_logic_vector(g_aux_clks-1 downto 0);
+  
+      timestamps_o     : out t_txtsu_timestamp;
+      timestamps_ack_i : in  std_logic := '1';
+  
+      abscal_txts_o       : out std_logic;
+      abscal_rxts_o       : out std_logic;
+  
+      fc_tx_pause_req_i   : in  std_logic                     := '0';
+      fc_tx_pause_delay_i : in  std_logic_vector(15 downto 0) := x"0000";
+      fc_tx_pause_ready_o : out std_logic;
+  
+      tm_link_up_o    : out std_logic;
+      tm_time_valid_o : out std_logic;
+      tm_tai_o        : out std_logic_vector(39 downto 0);
+      tm_cycles_o     : out std_logic_vector(27 downto 0);
+  
+      led_act_o  : out std_logic;
+      led_link_o : out std_logic;
+      btn1_i     : in  std_logic := '1';
+      btn2_i     : in  std_logic := '1';
+      pps_p_o    : out std_logic;
+      pps_led_o  : out std_logic;
+      link_ok_o  : out std_logic);
+  end component xwrc_board_fasec;
+
+end wr_fasec_pkg;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/board/fasec/wrc_board_fasec.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/board/fasec/wrc_board_fasec.vhd
new file mode 100644
index 000000000..3aeca64b7
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/board/fasec/wrc_board_fasec.vhd
@@ -0,0 +1,599 @@
+-------------------------------------------------------------------------------
+-- Title      : WRPC Wrapper for FASEC
+-- Project    : WR PTP Core
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
+-------------------------------------------------------------------------------
+-- File       : wrc_board_fasec.vhd
+-- Author(s)  : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
+-- Company    : CERN (BE-CO-HT)
+-- Created    : 2017-08-02
+-- Last update: 2017-09-07
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Top-level wrapper for WR PTP core including all the modules
+-- needed to operate the core on the FASEC board.
+-- Version with no VHDL records on the top-level (mainly for Verilog
+-- instantiation).
+-- http://www.ohwr.org/projects/fasec/
+-------------------------------------------------------------------------------
+-- Copyright (c) 2017 CERN
+-------------------------------------------------------------------------------
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-- 
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.gencores_pkg.all;
+use work.wrcore_pkg.all;
+use work.wishbone_pkg.all;
+use work.etherbone_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.endpoint_pkg.all;
+use work.streamers_pkg.all;
+use work.wr_xilinx_pkg.all;
+use work.wr_board_pkg.all;
+use work.wr_fasec_pkg.all;
+
+entity wrc_board_fasec is
+  generic(
+    -- set to 1 to speed up some initialization processes during simulation
+    g_simulation                : integer := 0;
+    -- Select whether to include external ref clock input
+    g_with_external_clock_input : integer := 0;
+    -- Number of aux clocks syntonized by WRPC to WR timebase
+    g_aux_clks                  : integer := 0;
+    -- "plainfbrc" = expose WRC fabric interface
+    -- "streamers" = attach WRC streamers to fabric interface
+    -- "etherbone" = attach Etherbone slave to fabric interface
+    g_fabric_iface              : string  := "plainfbrc";
+    -- parameters configuration when g_fabric_iface = "streamers" (otherwise ignored)
+    --g_streamers_op_mode        : t_streamers_op_mode  := TX_AND_RX;
+    --g_tx_streamer_params       : t_tx_streamer_params := c_tx_streamer_params_defaut;
+    --g_rx_streamer_params       : t_rx_streamer_params := c_rx_streamer_params_defaut;
+    -- memory initialisation file for embedded CPU
+    g_dpram_initf               : string  := "../../../../bin/wrpc/wrc_phy16.bram";
+    -- identification (id and ver) of the layout of words in the generic diag interface
+    g_diag_id                   : integer := 0;
+    g_diag_ver                  : integer := 0;
+    -- size the generic diag interface
+    g_diag_ro_vector_width      : integer := 0;
+    g_diag_rw_vector_width      : integer := 0
+    );
+  port (
+    ---------------------------------------------------------------------------
+    -- Clocks/resets
+    ---------------------------------------------------------------------------
+    -- Reset from system fpga
+    areset_n_i          : in  std_logic;
+    -- Optional reset input active low with rising edge detection. Does not
+    -- reset PLLs.
+    --areset_edge_n_i     : in  std_logic := '1';
+    -- Clock inputs from the board
+    clk_20m_vcxo_i      : in  std_logic;
+    clk_125m_pllref_p_i : in  std_logic;
+    clk_125m_pllref_n_i : in  std_logic;
+    clk_125m_gtp_n_i    : in  std_logic;
+    clk_125m_gtp_p_i    : in  std_logic;
+    -- 10MHz ext ref clock input (g_with_external_clock_input = TRUE)
+    clk_10m_ext_i       : in  std_logic := '0';
+    -- External PPS input (g_with_external_clock_input = TRUE)
+    pps_ext_i           : in  std_logic := '0';
+    -- 62.5MHz sys clock output
+    clk_sys_62m5_o      : out std_logic;
+    -- 125MHz ref clock output
+    clk_ref_125m_o      : out std_logic;
+    -- active low reset outputs, synchronous to 62m5 and 125m clocks
+    rst_sys_62m5_n_o    : out std_logic;
+    rst_ref_125m_n_o    : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Shared SPI interface to DACs
+    ---------------------------------------------------------------------------
+    plldac_sclk_o   : out std_logic;
+    plldac_din_o    : out std_logic;
+    pll25dac_cs_n_o : out std_logic;
+    pll20dac_cs_n_o : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- SFP I/O for transceiver and SFP management info
+    ---------------------------------------------------------------------------
+    sfp_tx_p_o         : out std_logic;
+    sfp_tx_n_o         : out std_logic;
+    sfp_rx_p_i         : in  std_logic;
+    sfp_rx_n_i         : in  std_logic;
+    sfp_det_i         : in  std_logic := '1';
+    sfp_sda_i         : in  std_logic;
+    sfp_sda_o         : out std_logic;
+    sfp_sda_t         : out std_logic;
+    sfp_scl_i         : in  std_logic;
+    sfp_scl_o         : out std_logic;
+    sfp_scl_t         : out std_logic;
+    sfp_rate_select_o : out std_logic;
+    sfp_tx_fault_i    : in  std_logic := '0';
+    sfp_tx_disable_o  : out std_logic;
+    sfp_los_i         : in  std_logic := '0';
+
+    ---------------------------------------------------------------------------
+    -- I2C EEPROM
+    ---------------------------------------------------------------------------
+    eeprom_sda_i : in  std_logic;
+    eeprom_sda_o : out std_logic;
+    eeprom_sda_t : out std_logic;
+    eeprom_scl_i : in  std_logic;
+    eeprom_scl_o : out std_logic;
+    eeprom_scl_t : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Onewire interface
+    ---------------------------------------------------------------------------
+    thermo_id_i : in  std_logic;
+    thermo_id_o : out std_logic;
+    thermo_id_t : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- UART
+    ---------------------------------------------------------------------------
+    uart_rxd_i : in  std_logic;
+    uart_txd_o : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Flash memory SPI interface
+    ---------------------------------------------------------------------------
+    --flash_sclk_o : out std_logic;
+    --flash_ncs_o  : out std_logic;
+    --flash_mosi_o : out std_logic;
+    --flash_miso_i : in  std_logic;
+
+    ---------------------------------------------------------------------------
+    -- External WB interface
+    ---------------------------------------------------------------------------
+    --aux_master_adr_o   : out std_logic_vector(c_wishbone_address_width-1 downto 0);
+    --aux_master_dat_o   : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+    --aux_master_dat_i   : in  std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
+    --aux_master_sel_o   : out std_logic_vector(c_wishbone_address_width/8-1 downto 0);
+    --aux_master_we_o    : out std_logic;
+    --aux_master_cyc_o   : out std_logic;
+    --aux_master_stb_o   : out std_logic;
+    --aux_master_ack_i   : in  std_logic                                          := '0';
+    --aux_master_int_i   : in  std_logic                                          := '0';
+    --aux_master_err_i   : in  std_logic                                          := '0';
+    --aux_master_rty_i   : in  std_logic                                          := '0';
+    --aux_master_stall_i : in  std_logic                                          := '0';
+
+    ------------------------------------------
+    -- Axi Slave Bus Interface S00_AXI
+    ------------------------------------------
+    s00_axi_aclk_o  : out std_logic;
+    s00_axi_aresetn : in  std_logic := '1';
+    s00_axi_awaddr  : in  std_logic_vector(31 downto 0) := (others=>'0');
+    --s00_axi_awprot  : in  std_logic_vector(2 downto 0);
+    s00_axi_awvalid : in  std_logic := '0';
+    s00_axi_awready : out std_logic;
+    s00_axi_wdata   : in  std_logic_vector(31 downto 0) := (others=>'0');
+    s00_axi_wstrb   : in  std_logic_vector(3 downto 0)  := (others=>'0');
+    s00_axi_wvalid  : in  std_logic := '0';
+    s00_axi_wready  : out std_logic;
+    s00_axi_bresp   : out std_logic_vector(1 downto 0);
+    s00_axi_bvalid  : out std_logic;
+    s00_axi_bready  : in  std_logic := '0';
+    s00_axi_araddr  : in  std_logic_vector(31 downto 0) := (others=>'0');
+    --s00_axi_arprot  : in std_logic_vector(2 downto 0);
+    s00_axi_arvalid : in  std_logic := '0';
+    s00_axi_arready : out std_logic;
+    s00_axi_rdata   : out std_logic_vector(31 downto 0);
+    s00_axi_rresp   : out std_logic_vector(1 downto 0);
+    s00_axi_rvalid  : out std_logic;
+    s00_axi_rready  : in  std_logic := '0';
+    s00_axi_rlast   : out std_logic;
+    axi_int_o       : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- WR fabric interface (when g_fabric_iface = "plain")
+    ---------------------------------------------------------------------------
+    --wrf_src_adr_o   : out std_logic_vector(1 downto 0);
+    --wrf_src_dat_o   : out std_logic_vector(15 downto 0);
+    --wrf_src_cyc_o   : out std_logic;
+    --wrf_src_stb_o   : out std_logic;
+    --wrf_src_we_o    : out std_logic;
+    --wrf_src_sel_o   : out std_logic_vector(1 downto 0);
+    --wrf_src_ack_i   : in  std_logic;
+    --wrf_src_stall_i : in  std_logic;
+    --wrf_src_err_i   : in  std_logic;
+    --wrf_src_rty_i   : in  std_logic;
+    --wrf_snk_adr_i   : in  std_logic_vector(1 downto 0);
+    --wrf_snk_dat_i   : in  std_logic_vector(15 downto 0);
+    --wrf_snk_cyc_i   : in  std_logic;
+    --wrf_snk_stb_i   : in  std_logic;
+    --wrf_snk_we_i    : in  std_logic;
+    --wrf_snk_sel_i   : in  std_logic_vector(1 downto 0);
+    --wrf_snk_ack_o   : out std_logic;
+    --wrf_snk_stall_o : out std_logic;
+    --wrf_snk_err_o   : out std_logic;
+    --wrf_snk_rty_o   : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- WR streamers (when g_fabric_iface = "streamers")
+    ---------------------------------------------------------------------------
+    ----wrs_tx_data_i  : in  std_logic_vector(c_tx_streamer_params_defaut.data_width-1 downto 0) := (others => '0');
+    --wrs_tx_data_i  : in  std_logic_vector(31 downto 0) := (others => '0');
+    --wrs_tx_valid_i : in  std_logic                                        := '0';
+    --wrs_tx_dreq_o  : out std_logic;
+    --wrs_tx_last_i  : in  std_logic                                        := '1';
+    --wrs_tx_flush_i : in  std_logic                                        := '0';
+    --wrs_tx_cfg_mac_l_i : in  std_logic_vector(47 downto 0)                := x"000000000000";
+    --wrs_tx_cfg_mac_t_i : in  std_logic_vector(47 downto 0)                := x"ffffffffffff";
+    --wrs_tx_cfg_etype_i : in  std_logic_vector(15 downto 0)                := x"dbff";
+    --wrs_rx_first_o : out std_logic;
+    --wrs_rx_last_o  : out std_logic;
+    ----wrs_rx_data_o  : out std_logic_vector(c_rx_streamer_params_defaut.data_width-1 downto 0);
+    --wrs_rx_data_o  : out std_logic_vector(31 downto 0);
+    --wrs_rx_valid_o : out std_logic;
+    --wrs_rx_dreq_i  : in  std_logic                                        := '0';
+    --wrs_rx_cfg_mac_l_i : in std_logic_vector(47 downto 0)                 := x"000000000000";
+    --wrs_rx_cfg_mac_r_i : in std_logic_vector(47 downto 0)                 := x"000000000000";
+    --wrs_rx_cfg_etype_i : in std_logic_vector(15 downto 0)                 := x"dbff";
+    --wrs_rx_cfg_acc_b_i : in std_logic                                     := '1';
+    --wrs_rx_cfg_flt_r_i : in std_logic                                     := '0';
+    --wrs_rx_cfg_fix_l_i : in std_logic_vector(27 downto 0)                 := x"0000000";
+    ---------------------------------------------------------------------------
+    -- Etherbone WB master interface (when g_fabric_iface = "etherbone")
+    ---------------------------------------------------------------------------
+    --wb_eth_adr_o   : out std_logic_vector(c_wishbone_address_width-1 downto 0);
+    --wb_eth_dat_o   : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+    --wb_eth_dat_i   : in  std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
+    --wb_eth_sel_o   : out std_logic_vector(c_wishbone_address_width/8-1 downto 0);
+    --wb_eth_we_o    : out std_logic;
+    --wb_eth_cyc_o   : out std_logic;
+    --wb_eth_stb_o   : out std_logic;
+    --wb_eth_ack_i   : in  std_logic                                          := '0';
+    --wb_eth_int_i   : in  std_logic                                          := '0';
+    --wb_eth_err_i   : in  std_logic                                          := '0';
+    --wb_eth_rty_i   : in  std_logic                                          := '0';
+    --wb_eth_stall_i : in  std_logic                                          := '0';
+
+    ---------------------------------------------------------------------------
+    -- Generic diagnostics interface (access from WRPC via SNMP or uart console
+    ---------------------------------------------------------------------------
+    --aux_diag_i : in  std_logic_vector(g_diag_ro_vector_width - 1 downto 0) := (others => '0');
+    --aux_diag_o : out std_logic_vector(g_diag_rw_vector_width - 1 downto 0) := (others => '0');
+
+    ---------------------------------------------------------------------------
+    -- Aux clocks control
+    ---------------------------------------------------------------------------
+    --tm_dac_value_o       : out std_logic_vector(23 downto 0);
+    --tm_dac_wr_o          : out std_logic_vector(g_aux_clks-1 downto 0);
+    --tm_clk_aux_lock_en_i : in  std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
+    --tm_clk_aux_locked_o  : out std_logic_vector(g_aux_clks-1 downto 0);
+
+    ---------------------------------------------------------------------------
+    -- External Tx Timestamping I/F
+    ---------------------------------------------------------------------------
+    --tstamps_stb_o       : out std_logic;
+    --tstamps_tsval_o     : out std_logic_vector(31 downto 0);
+    --tstamps_port_id_o   : out std_logic_vector(5 downto 0);
+    --tstamps_frame_id_o  : out std_logic_vector(15 downto 0);
+    --tstamps_incorrect_o : out std_logic;
+    --tstamps_ack_i       : in  std_logic := '1';
+
+    -----------------------------------------
+    -- Timestamp helper signals, used for Absolute Calibration
+    -----------------------------------------
+    --abscal_txts_o       : out std_logic;
+    --abscal_rxts_o       : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Pause Frame Control
+    ---------------------------------------------------------------------------
+    --fc_tx_pause_req_i   : in  std_logic                     := '0';
+    --fc_tx_pause_delay_i : in  std_logic_vector(15 downto 0) := x"0000";
+    --fc_tx_pause_ready_o : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Timecode I/F
+    ---------------------------------------------------------------------------
+    --tm_link_up_o    : out std_logic;
+    --tm_time_valid_o : out std_logic;
+    --tm_tai_o        : out std_logic_vector(39 downto 0);
+    --tm_cycles_o     : out std_logic_vector(27 downto 0);
+
+    ---------------------------------------------------------------------------
+    -- Buttons, LEDs and PPS output
+    ---------------------------------------------------------------------------
+    led_act_o  : out std_logic;
+    led_link_o : out std_logic;
+    --btn1_i     : in  std_logic := '1';
+    --btn2_i     : in  std_logic := '1';
+    -- 1PPS output
+    pps_p_o    : out std_logic;
+    pps_led_o  : out std_logic;
+    -- Link ok indication
+    link_ok_o  : out std_logic
+    );
+
+end entity wrc_board_fasec;
+
+
+architecture std_wrapper of wrc_board_fasec is
+
+  -----------------------------------------------------------------------------
+  -- Signals
+  -----------------------------------------------------------------------------
+
+  -- WR fabric interface
+  signal wrf_src_out : t_wrf_source_out;
+  signal wrf_src_in  : t_wrf_source_in;
+  signal wrf_snk_out : t_wrf_sink_out;
+  signal wrf_snk_in  : t_wrf_sink_in;
+
+  signal aux_master_out : t_wishbone_master_out;
+  signal aux_master_in  : t_wishbone_master_in;
+
+  -- Etherbone interface
+  signal wb_eth_master_out : t_wishbone_master_out;
+  signal wb_eth_master_in  : t_wishbone_master_in;
+
+  -- Aux diagnostics
+  constant c_diag_ro_size : integer := g_diag_ro_vector_width/32;
+  constant c_diag_rw_size : integer := g_diag_rw_vector_width/32;
+
+  signal aux_diag_in  : t_generic_word_array(c_diag_ro_size-1 downto 0);
+  signal aux_diag_out : t_generic_word_array(c_diag_rw_size-1 downto 0);
+
+  -- External Tx Timestamping I/F
+  signal timestamps_out : t_txtsu_timestamp;
+
+  -- streamers config
+  signal wrs_tx_cfg_in  : t_tx_streamer_cfg;
+  signal wrs_rx_cfg_in  : t_rx_streamer_cfg;
+
+  -- axi signals
+  signal s_axi_araddr : std_logic_vector(31 downto 0);
+  signal s_axi_awaddr : std_logic_vector(31 downto 0);
+
+begin  -- architecture struct
+
+  -- Map top-level signals to internal records
+  --aux_master_adr_o <= aux_master_out.adr;
+  --aux_master_dat_o <= aux_master_out.dat;
+  --aux_master_cyc_o <= aux_master_out.cyc;
+  --aux_master_stb_o <= aux_master_out.stb;
+  --aux_master_sel_o <= aux_master_out.sel;
+  --aux_master_we_o  <= aux_master_out.we;
+
+  --aux_master_in.dat   <= aux_master_dat_i;
+  --aux_master_in.ack   <= aux_master_ack_i;
+  --aux_master_in.int   <= aux_master_int_i;
+  --aux_master_in.err   <= aux_master_err_i;
+  --aux_master_in.rty   <= aux_master_rty_i;
+  --aux_master_in.stall <= aux_master_stall_i;
+
+  --wrf_src_adr_o    <= wrf_src_out.adr;
+  --wrf_src_dat_o    <= wrf_src_out.dat;
+  --wrf_src_cyc_o    <= wrf_src_out.cyc;
+  --wrf_src_stb_o    <= wrf_src_out.stb;
+  --wrf_src_we_o     <= wrf_src_out.we;
+  --wrf_src_sel_o    <= wrf_src_out.sel;
+  --wrf_src_in.ack   <= wrf_src_ack_i;
+  --wrf_src_in.stall <= wrf_src_stall_i;
+  --wrf_src_in.err   <= wrf_src_err_i;
+  --wrf_src_in.rty   <= wrf_src_rty_i;
+
+  --wrf_snk_in.adr  <= wrf_snk_adr_i;
+  --wrf_snk_in.dat  <= wrf_snk_dat_i;
+  --wrf_snk_in.cyc  <= wrf_snk_cyc_i;
+  --wrf_snk_in.stb  <= wrf_snk_stb_i;
+  --wrf_snk_in.we   <= wrf_snk_we_i;
+  --wrf_snk_in.sel  <= wrf_snk_sel_i;
+  --wrf_snk_ack_o   <= wrf_snk_out.ack;
+  --wrf_snk_stall_o <= wrf_snk_out.stall;
+  --wrf_snk_err_o   <= wrf_snk_out.err;
+  --wrf_snk_rty_o   <= wrf_snk_out.rty;
+
+
+  --wb_eth_adr_o <= wb_eth_master_out.adr;
+  --wb_eth_dat_o <= wb_eth_master_out.dat;
+  --wb_eth_cyc_o <= wb_eth_master_out.cyc;
+  --wb_eth_stb_o <= wb_eth_master_out.stb;
+  --wb_eth_sel_o <= wb_eth_master_out.sel;
+  --wb_eth_we_o  <= wb_eth_master_out.we;
+
+  --wb_eth_master_in.dat   <= wb_eth_dat_i;
+  --wb_eth_master_in.ack   <= wb_eth_ack_i;
+  --wb_eth_master_in.int   <= wb_eth_int_i;
+  --wb_eth_master_in.err   <= wb_eth_err_i;
+  --wb_eth_master_in.rty   <= wb_eth_rty_i;
+  --wb_eth_master_in.stall <= wb_eth_stall_i;
+
+  --aux_diag_in <= f_de_vectorize_diag(aux_diag_i, g_diag_ro_vector_width);
+  --aux_diag_o  <= f_vectorize_diag(aux_diag_out, g_diag_rw_vector_width);
+
+  --tstamps_stb_o      <= timestamps_out.stb;
+  --tstamps_tsval_o    <= timestamps_out.tsval;
+  --tstamps_port_id_o  <= timestamps_out.port_id;
+  --tstamps_frame_id_o <= timestamps_out.frame_id;
+
+  --wrs_tx_cfg_in.mac_local         <= wrs_tx_cfg_mac_l_i;
+  --wrs_tx_cfg_in.mac_target        <= wrs_tx_cfg_mac_t_i;
+  --wrs_tx_cfg_in.ethertype         <= wrs_tx_cfg_etype_i;
+
+  --wrs_rx_cfg_in.mac_local         <= wrs_rx_cfg_mac_l_i;
+  --wrs_rx_cfg_in.mac_remote        <= wrs_rx_cfg_mac_r_i;
+  --wrs_rx_cfg_in.ethertype         <= wrs_rx_cfg_etype_i;
+  --wrs_rx_cfg_in.accept_broadcasts <= wrs_rx_cfg_acc_b_i;
+  --wrs_rx_cfg_in.filter_remote     <= wrs_rx_cfg_flt_r_i;
+  --wrs_rx_cfg_in.fixed_latency     <= wrs_rx_cfg_fix_l_i;
+
+  -- axi supports word-addressing only, i.e. per 4 bytes; shift for wb-bridge
+  s_axi_araddr  <= "00" & s00_axi_araddr(31 downto 2);
+  s_axi_awaddr  <= "00" & s00_axi_awaddr(31 downto 2);
+  -- Instantiate the records-based module
+  cmp_xwrc_board_fasec : xwrc_board_fasec
+    generic map (
+      g_simulation                => g_simulation,
+      g_with_external_clock_input => f_int2bool(g_with_external_clock_input),
+      g_aux_clks                  => g_aux_clks,
+      g_fabric_iface              => f_str2iface_type(g_fabric_iface),
+      g_streamers_op_mode         => TX_AND_RX,
+      g_tx_streamer_params        => c_tx_streamer_params_defaut,
+      g_rx_streamer_params        => c_rx_streamer_params_defaut,
+      g_dpram_initf               => g_dpram_initf,
+      g_diag_id                   => g_diag_id,
+      g_diag_ver                  => g_diag_ver,
+      g_diag_ro_size              => c_diag_ro_size,
+      g_diag_rw_size              => c_diag_rw_size)
+    port map (
+      areset_n_i           => areset_n_i,
+      --areset_edge_n_i      => areset_edge_n_i,
+      clk_20m_vcxo_i       => clk_20m_vcxo_i,
+      clk_125m_pllref_p_i  => clk_125m_pllref_p_i,
+      clk_125m_pllref_n_i  => clk_125m_pllref_n_i,
+      clk_125m_gtp_n_i     => clk_125m_gtp_n_i,
+      clk_125m_gtp_p_i     => clk_125m_gtp_p_i,
+      clk_10m_ext_i        => clk_10m_ext_i,
+      pps_ext_i            => pps_ext_i,
+      clk_sys_62m5_o       => clk_sys_62m5_o,
+      clk_ref_125m_o       => clk_ref_125m_o,
+      rst_sys_62m5_n_o     => rst_sys_62m5_n_o,
+      rst_ref_125m_n_o     => rst_ref_125m_n_o,
+      --
+      plldac_sclk_o        => plldac_sclk_o,
+      plldac_din_o         => plldac_din_o,
+      pll25dac_cs_n_o      => pll25dac_cs_n_o,
+      pll20dac_cs_n_o      => pll20dac_cs_n_o,
+      --
+      sfp_txp_o            => sfp_tx_p_o,
+      sfp_txn_o            => sfp_tx_n_o,
+      sfp_rxp_i            => sfp_rx_p_i,
+      sfp_rxn_i            => sfp_rx_n_i,
+      sfp_det_i            => sfp_det_i,
+      sfp_sda_i            => sfp_sda_i,
+      sfp_sda_o            => sfp_sda_o,
+      sfp_sda_t            => sfp_sda_t,
+      sfp_scl_i            => sfp_scl_i,
+      sfp_scl_o            => sfp_scl_o,
+      sfp_scl_t            => sfp_scl_t,
+      sfp_rate_select_o    => sfp_rate_select_o,
+      sfp_tx_fault_i       => sfp_tx_fault_i,
+      sfp_tx_disable_o     => sfp_tx_disable_o,
+      sfp_los_i            => sfp_los_i,
+      --
+      eeprom_sda_i => eeprom_sda_i,
+      eeprom_sda_o => eeprom_sda_o,
+      eeprom_sda_t => eeprom_sda_t,
+      eeprom_scl_i => eeprom_scl_i,
+      eeprom_scl_o => eeprom_scl_o,
+      eeprom_scl_t => eeprom_scl_t,
+      --
+      thermo_id_i  => thermo_id_i,
+      thermo_id_o  => thermo_id_o,
+      thermo_id_t  => thermo_id_t,
+      --
+      uart_rxd_i           => uart_rxd_i,
+      uart_txd_o           => uart_txd_o,
+      --
+      --flash_sclk_o         => flash_sclk_o,
+      --flash_ncs_o          => flash_ncs_o,
+      --flash_mosi_o         => flash_mosi_o,
+      --flash_miso_i         => flash_miso_i,
+      --
+      --aux_master_o         => aux_master_out,
+      --aux_master_i         => aux_master_in,
+      --
+      s00_axi_aclk_o       => s00_axi_aclk_o,
+      s00_axi_aresetn      => s00_axi_aresetn,
+      s00_axi_awaddr       => s_axi_awaddr,
+      s00_axi_awprot       => (others=>'0'), --s00_axi_awprot,
+      s00_axi_awvalid      => s00_axi_awvalid,
+      s00_axi_awready      => s00_axi_awready,
+      s00_axi_wdata        => s00_axi_wdata,
+      s00_axi_wstrb        => s00_axi_wstrb,
+      s00_axi_wvalid       => s00_axi_wvalid,
+      s00_axi_wready       => s00_axi_wready,
+      s00_axi_bresp        => s00_axi_bresp,
+      s00_axi_bvalid       => s00_axi_bvalid,
+      s00_axi_bready       => s00_axi_bready,
+      s00_axi_araddr       => s_axi_araddr,
+      s00_axi_arprot       => (others=>'0'), --s00_axi_arprot,
+      s00_axi_arvalid      => s00_axi_arvalid,
+      s00_axi_arready      => s00_axi_arready,
+      s00_axi_rdata        => s00_axi_rdata,
+      s00_axi_rresp        => s00_axi_rresp,
+      s00_axi_rvalid       => s00_axi_rvalid,
+      s00_axi_rready       => s00_axi_rready,
+      s00_axi_rlast        => s00_axi_rlast,
+      axi_int_o            => axi_int_o,
+      --
+      --wrf_src_o            => wrf_src_out,
+      --wrf_src_i            => wrf_src_in,
+      --wrf_snk_o            => wrf_snk_out,
+      --wrf_snk_i            => wrf_snk_in,
+      --
+      --wrs_tx_data_i        => wrs_tx_data_i,
+      --wrs_tx_valid_i       => wrs_tx_valid_i,
+      --wrs_tx_dreq_o        => wrs_tx_dreq_o,
+      --wrs_tx_last_i        => wrs_tx_last_i,
+      --wrs_tx_flush_i       => wrs_tx_flush_i,
+      --wrs_tx_cfg_i         => wrs_tx_cfg_in,
+      --wrs_rx_first_o       => wrs_rx_first_o,
+      --wrs_rx_last_o        => wrs_rx_last_o,
+      --wrs_rx_data_o        => wrs_rx_data_o,
+      --wrs_rx_valid_o       => wrs_rx_valid_o,
+      --wrs_rx_dreq_i        => wrs_rx_dreq_i,
+      --wrs_rx_cfg_i         => wrs_rx_cfg_in,
+      --
+      --wb_eth_master_o      => wb_eth_master_out,
+      --wb_eth_master_i      => wb_eth_master_in,
+      --
+      --aux_diag_i           => aux_diag_in,
+      --aux_diag_o           => aux_diag_out,
+      --
+      --tm_dac_value_o       => tm_dac_value_o,
+      --tm_dac_wr_o          => tm_dac_wr_o,
+      --tm_clk_aux_lock_en_i => tm_clk_aux_lock_en_i,
+      --tm_clk_aux_locked_o  => tm_clk_aux_locked_o,
+      --
+      --timestamps_o         => timestamps_out,
+      --timestamps_ack_i     => tstamps_ack_i,
+      --
+      --abscal_txts_o        => abscal_txts_o,
+      --abscal_rxts_o        => abscal_rxts_o,
+      --
+      --fc_tx_pause_req_i    => fc_tx_pause_req_i,
+      --fc_tx_pause_delay_i  => fc_tx_pause_delay_i,
+      --fc_tx_pause_ready_o  => fc_tx_pause_ready_o,
+      --
+      --tm_link_up_o         => tm_link_up_o,
+      --tm_time_valid_o      => tm_time_valid_o,
+      --tm_tai_o             => tm_tai_o,
+      --tm_cycles_o          => tm_cycles_o,
+      --
+      led_act_o            => led_act_o,
+      led_link_o           => led_link_o,
+      --btn1_i               => btn1_i,
+      --btn2_i               => btn2_i,
+      --
+      pps_p_o              => pps_p_o,
+      pps_led_o            => pps_led_o,
+      --
+      link_ok_o            => link_ok_o);
+
+end architecture std_wrapper;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/board/fasec/xwrc_board_fasec.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/board/fasec/xwrc_board_fasec.vhd
new file mode 100644
index 000000000..30bc6f3ed
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/board/fasec/xwrc_board_fasec.vhd
@@ -0,0 +1,623 @@
+-------------------------------------------------------------------------------
+-- Title      : WRPC Wrapper for FASEC
+-- Project    : WR PTP Core
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
+-------------------------------------------------------------------------------
+-- File       : xwrc_board_fasec.vhd
+-- Author(s)  : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
+-- Company    : CERN (BE-CO-HT)
+-- Created    : 2017-08-02
+-- Last update: 2017-08-02
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Top-level wrapper for WR PTP core including all the modules
+-- needed to operate the core on the FASEC board.
+-- http://www.ohwr.org/projects/fasec/
+-------------------------------------------------------------------------------
+-- Copyright (c) 2017 CERN
+-------------------------------------------------------------------------------
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-- 
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.gencores_pkg.all;
+use work.wrcore_pkg.all;
+use work.wishbone_pkg.all;
+use work.etherbone_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.endpoint_pkg.all;
+use work.streamers_pkg.all;
+use work.wr_xilinx_pkg.all;
+use work.wr_board_pkg.all;
+use work.wr_fasec_pkg.all;
+use work.axi4_pkg.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity xwrc_board_fasec is
+  generic(
+    -- set to 1 to speed up some initialization processes during simulation
+    g_simulation                : integer              := 0;
+    -- Select whether to include external ref clock input
+    g_with_external_clock_input : boolean              := TRUE;
+    -- Number of aux clocks syntonized by WRPC to WR timebase
+    g_aux_clks                  : integer              := 0;
+    -- plain     = expose WRC fabric interface
+    -- streamers = attach WRC streamers to fabric interface
+    -- etherbone = attach Etherbone slave to fabric interface
+    g_fabric_iface              : t_board_fabric_iface := plain;
+    -- parameters configuration when g_fabric_iface = "streamers" (otherwise ignored)
+    g_streamers_op_mode        : t_streamers_op_mode  := TX_AND_RX;
+    g_tx_streamer_params       : t_tx_streamer_params := c_tx_streamer_params_defaut;
+    g_rx_streamer_params       : t_rx_streamer_params := c_rx_streamer_params_defaut;
+    -- memory initialisation file for embedded CPU
+    g_dpram_initf               : string               := "/home/greg/wr/wr-cores/bin/wrpc/wrc_phy16.bram";
+    -- identification (id and ver) of the layout of words in the generic diag interface
+    g_diag_id                   : integer              := 0;
+    g_diag_ver                  : integer              := 0;
+    -- size the generic diag interface
+    g_diag_ro_size              : integer              := 0;
+    g_diag_rw_size              : integer              := 0
+    );
+  port (
+    ---------------------------------------------------------------------------
+    -- Clocks/resets
+    ---------------------------------------------------------------------------
+    -- Reset input (active low, can be async)
+    areset_n_i          : in  std_logic;
+    -- Optional reset input active low with rising edge detection. Does not
+    -- reset PLLs.
+    areset_edge_n_i     : in  std_logic := '1';
+    -- Clock inputs from the board
+    clk_20m_vcxo_i      : in  std_logic;
+    clk_125m_pllref_p_i : in  std_logic;
+    clk_125m_pllref_n_i : in  std_logic;
+    clk_125m_gtp_n_i    : in  std_logic;
+    clk_125m_gtp_p_i    : in  std_logic;
+    -- Aux clocks, which can be disciplined by the WR Core
+    clk_aux_i           : in  std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
+    -- 10MHz ext ref clock input (g_with_external_clock_input = TRUE)
+    clk_10m_ext_i       : in  std_logic                               := '0';
+    -- External PPS input (g_with_external_clock_input = TRUE)
+    pps_ext_i           : in  std_logic                               := '0';
+    -- 62.5MHz sys clock output
+    clk_sys_62m5_o      : out std_logic;
+    -- 125MHz ref clock output
+    clk_ref_125m_o      : out std_logic;
+    -- active low reset outputs, synchronous to 62m5 and 125m clocks
+    rst_sys_62m5_n_o    : out std_logic;
+    rst_ref_125m_n_o    : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Shared SPI interface to DACs
+    ---------------------------------------------------------------------------
+    plldac_sclk_o   : out std_logic;
+    plldac_din_o    : out std_logic;
+    pll25dac_cs_n_o : out std_logic;
+    pll20dac_cs_n_o : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- SFP I/O for transceiver and SFP management info
+    ---------------------------------------------------------------------------
+    sfp_txp_o         : out std_logic;
+    sfp_txn_o         : out std_logic;
+    sfp_rxp_i         : in  std_logic;
+    sfp_rxn_i         : in  std_logic;
+    sfp_det_i         : in  std_logic := '1';
+    sfp_sda_i         : in  std_logic;
+    sfp_sda_o         : out std_logic;
+    sfp_sda_t         : out std_logic;
+    sfp_scl_i         : in  std_logic;
+    sfp_scl_o         : out std_logic;
+    sfp_scl_t         : out std_logic;
+    sfp_rate_select_o : out std_logic;
+    sfp_tx_fault_i    : in  std_logic := '0';
+    sfp_tx_disable_o  : out std_logic;
+    sfp_los_i         : in  std_logic := '0';
+
+    ---------------------------------------------------------------------------
+    -- I2C EEPROM
+    ---------------------------------------------------------------------------
+    eeprom_sda_i : in  std_logic;
+    eeprom_sda_o : out std_logic;
+    eeprom_sda_t : out std_logic;
+    eeprom_scl_i : in  std_logic;
+    eeprom_scl_o : out std_logic;
+    eeprom_scl_t : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Onewire interface
+    ---------------------------------------------------------------------------
+    thermo_id_i : in  std_logic;
+    thermo_id_o : out std_logic;
+    thermo_id_t : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- UART
+    ---------------------------------------------------------------------------
+    uart_rxd_i : in  std_logic;
+    uart_txd_o : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Flash memory SPI interface
+    ---------------------------------------------------------------------------
+    flash_sclk_o : out std_logic;
+    flash_ncs_o  : out std_logic;
+    flash_mosi_o : out std_logic;
+    flash_miso_i : in  std_logic;
+
+    ---------------------------------------------------------------------------
+    -- External WB interface
+    ---------------------------------------------------------------------------
+    aux_master_o : out t_wishbone_master_out;
+    aux_master_i : in  t_wishbone_master_in := cc_dummy_master_in;
+
+    ------------------------------------------
+    -- Axi Slave Bus Interface S00_AXI
+    ------------------------------------------
+    -- aclk provided by this IP, wire to master!
+    s00_axi_aclk_o  : out std_logic;
+    s00_axi_aresetn : in  std_logic;
+    s00_axi_awaddr  : in std_logic_vector(31 downto 0);
+    s00_axi_awprot  : in  std_logic_vector(2 downto 0);
+    s00_axi_awvalid : in  std_logic;
+    s00_axi_awready : out std_logic;
+    s00_axi_wdata   : in std_logic_vector(31 downto 0);
+    s00_axi_wstrb   : in std_logic_vector(3 downto 0);
+    s00_axi_wvalid  : in  std_logic;
+    s00_axi_wready  : out std_logic;
+    s00_axi_bresp   : out std_logic_vector(1 downto 0);
+    s00_axi_bvalid  : out std_logic;
+    s00_axi_bready  : in std_logic;
+    s00_axi_araddr  : in std_logic_vector(31 downto 0);
+    s00_axi_arprot  : in std_logic_vector(2 downto 0);
+    s00_axi_arvalid : in std_logic;
+    s00_axi_arready : out std_logic;
+    s00_axi_rdata   : out std_logic_vector(31 downto 0);
+    s00_axi_rresp   : out std_logic_vector(1 downto 0);
+    s00_axi_rvalid  : out std_logic;
+    s00_axi_rready  : in std_logic;
+    s00_axi_rlast   : out std_logic;
+    axi_int_o       : out std_logic;  -- axi interrupt signal
+
+    ---------------------------------------------------------------------------
+    -- WR fabric interface (when g_fabric_iface = "plainfbrc")
+    ---------------------------------------------------------------------------
+    wrf_src_o : out t_wrf_source_out;
+    wrf_src_i : in  t_wrf_source_in := c_dummy_src_in;
+    wrf_snk_o : out t_wrf_sink_out;
+    wrf_snk_i : in  t_wrf_sink_in   := c_dummy_snk_in;
+
+    ---------------------------------------------------------------------------
+    -- WR streamers (when g_fabric_iface = "streamers")
+    ---------------------------------------------------------------------------
+    wrs_tx_data_i  : in  std_logic_vector(g_tx_streamer_params.data_width-1 downto 0) := (others => '0');
+    wrs_tx_valid_i : in  std_logic                                        := '0';
+    wrs_tx_dreq_o  : out std_logic;
+    wrs_tx_last_i  : in  std_logic                                        := '1';
+    wrs_tx_flush_i : in  std_logic                                        := '0';
+    wrs_tx_cfg_i   : in  t_tx_streamer_cfg                                := c_tx_streamer_cfg_default;
+    wrs_rx_first_o : out std_logic;
+    wrs_rx_last_o  : out std_logic;
+    wrs_rx_data_o  : out std_logic_vector(g_rx_streamer_params.data_width-1 downto 0);
+    wrs_rx_valid_o : out std_logic;
+    wrs_rx_dreq_i  : in  std_logic                                        := '0';
+    wrs_rx_cfg_i   : in t_rx_streamer_cfg                                 := c_rx_streamer_cfg_default;
+    ---------------------------------------------------------------------------
+    -- Etherbone WB master interface (when g_fabric_iface = "etherbone")
+    ---------------------------------------------------------------------------
+    wb_eth_master_o : out t_wishbone_master_out;
+    wb_eth_master_i : in  t_wishbone_master_in := cc_dummy_master_in;
+
+    ---------------------------------------------------------------------------
+    -- Generic diagnostics interface (access from WRPC via SNMP or uart console
+    ---------------------------------------------------------------------------
+    aux_diag_i : in  t_generic_word_array(g_diag_ro_size-1 downto 0) := (others => (others => '0'));
+    aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0);
+
+    ---------------------------------------------------------------------------
+    -- Aux clocks control
+    ---------------------------------------------------------------------------
+    tm_dac_value_o       : out std_logic_vector(23 downto 0);
+    tm_dac_wr_o          : out std_logic_vector(g_aux_clks-1 downto 0);
+    tm_clk_aux_lock_en_i : in  std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
+    tm_clk_aux_locked_o  : out std_logic_vector(g_aux_clks-1 downto 0);
+
+    ---------------------------------------------------------------------------
+    -- External Tx Timestamping I/F
+    ---------------------------------------------------------------------------
+    timestamps_o     : out t_txtsu_timestamp;
+    timestamps_ack_i : in  std_logic := '1';
+
+    -----------------------------------------
+    -- Timestamp helper signals, used for Absolute Calibration
+    -----------------------------------------
+    abscal_txts_o       : out std_logic;
+    abscal_rxts_o       : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Pause Frame Control
+    ---------------------------------------------------------------------------
+    fc_tx_pause_req_i   : in  std_logic                     := '0';
+    fc_tx_pause_delay_i : in  std_logic_vector(15 downto 0) := x"0000";
+    fc_tx_pause_ready_o : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Timecode I/F
+    ---------------------------------------------------------------------------
+    tm_link_up_o    : out std_logic;
+    tm_time_valid_o : out std_logic;
+    tm_tai_o        : out std_logic_vector(39 downto 0);
+    tm_cycles_o     : out std_logic_vector(27 downto 0);
+
+    ---------------------------------------------------------------------------
+    -- Buttons, LEDs and PPS output
+    ---------------------------------------------------------------------------
+    led_act_o  : out std_logic;
+    led_link_o : out std_logic;
+    btn1_i     : in  std_logic := '1';
+    btn2_i     : in  std_logic := '1';
+    -- 1PPS output
+    pps_p_o    : out std_logic;
+    pps_led_o  : out std_logic;
+    -- Link ok indication
+    link_ok_o  : out std_logic
+    );
+
+end entity xwrc_board_fasec;
+
+
+architecture struct of xwrc_board_fasec is
+
+  -----------------------------------------------------------------------------
+  -- Signals
+  -----------------------------------------------------------------------------
+
+  -- IBUFDS
+  signal clk_125m_pllref_buf : std_logic;
+
+  -- PLLs, clocks
+  signal clk_pll_62m5 : std_logic;
+  signal clk_pll_125m : std_logic;
+  signal clk_pll_dmtd : std_logic;
+  signal pll_locked   : std_logic;
+  signal clk_10m_ext  : std_logic;
+
+  -- Reset logic
+  signal areset_edge_ppulse : std_logic;
+  signal rst_62m5_n         : std_logic;
+  signal rstlogic_arst_n    : std_logic;
+  signal rstlogic_clk_in    : std_logic_vector(1 downto 0);
+  signal rstlogic_rst_out   : std_logic_vector(1 downto 0);
+
+  -- PLL DAC ARB
+  signal dac_hpll_load_p1 : std_logic;
+  signal dac_hpll_data    : std_logic_vector(15 downto 0);
+  signal dac_dpll_load_p1 : std_logic;
+  signal dac_dpll_data    : std_logic_vector(15 downto 0);
+
+  -- OneWire
+  signal onewire_in : std_logic_vector(1 downto 0);
+  signal onewire_en : std_logic_vector(1 downto 0);
+
+  -- PHY
+  signal phy16_to_wrc   : t_phy_16bits_to_wrc;
+  signal phy16_from_wrc : t_phy_16bits_from_wrc;
+
+  -- External reference
+  signal ext_ref_mul         : std_logic;
+  signal ext_ref_mul_locked  : std_logic;
+  signal ext_ref_mul_stopped : std_logic;
+  signal ext_ref_rst         : std_logic;
+
+  -- WRC WB Slave interface
+  signal wb_slave_out : t_wishbone_slave_out;
+  signal wb_slave_in  : t_wishbone_slave_in;
+  signal zero : std_logic;
+
+begin  -- architecture struct
+
+  -----------------------------------------------------------------------------
+  -- Platform-dependent part (PHY, PLLs, buffers, etc)
+  -----------------------------------------------------------------------------
+
+  cmp_ibufgds_pllref : IBUFGDS
+    generic map (
+      DIFF_TERM    => TRUE,
+      IBUF_LOW_PWR => TRUE,
+      IOSTANDARD   => "DEFAULT")
+    port map (
+      O  => clk_125m_pllref_buf,
+      I  => clk_125m_pllref_p_i,
+      IB => clk_125m_pllref_n_i);
+
+  cmp_xwrc_platform : xwrc_platform_xilinx
+    generic map (
+      g_fpga_family               => "kintex7",
+      g_with_external_clock_input => g_with_external_clock_input,
+      g_use_default_plls          => TRUE,
+      g_simulation                => g_simulation)
+    port map (
+      areset_n_i            => areset_n_i,
+      clk_10m_ext_i         => clk_10m_ext_i,
+      clk_20m_vcxo_i        => clk_20m_vcxo_i,
+      clk_125m_pllref_i     => clk_125m_pllref_buf,
+      clk_125m_gtp_p_i      => clk_125m_gtp_p_i,
+      clk_125m_gtp_n_i      => clk_125m_gtp_n_i,
+      sfp_txn_o             => sfp_txn_o,
+      sfp_txp_o             => sfp_txp_o,
+      sfp_rxn_i             => sfp_rxn_i,
+      sfp_rxp_i             => sfp_rxp_i,
+      sfp_tx_fault_i        => sfp_tx_fault_i,
+      sfp_los_i             => sfp_los_i,
+      sfp_tx_disable_o      => sfp_tx_disable_o,
+      clk_62m5_sys_o        => clk_pll_62m5,
+      clk_125m_ref_o        => clk_pll_125m,
+      clk_62m5_dmtd_o       => clk_pll_dmtd,
+      pll_locked_o          => pll_locked,
+      clk_10m_ext_o         => clk_10m_ext,
+      phy16_o               => phy16_to_wrc,
+      phy16_i               => phy16_from_wrc,
+      ext_ref_mul_o         => ext_ref_mul,
+      ext_ref_mul_locked_o  => ext_ref_mul_locked,
+      ext_ref_mul_stopped_o => ext_ref_mul_stopped,
+      ext_ref_rst_i         => ext_ref_rst);
+
+  clk_sys_62m5_o <= clk_pll_62m5;
+  clk_ref_125m_o <= clk_pll_125m;
+
+  -----------------------------------------------------------------------------
+  -- Reset logic
+  -----------------------------------------------------------------------------
+  -- Detect when areset_edge_n_i goes high (end of reset) and use this edge to
+  -- generate rstlogic_arst_n. This is needed to connect optional reset like PCIe
+  -- reset. When baord runs standalone, we need to ignore PCIe reset being
+  -- constantly low.
+  cmp_arst_edge: gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_pll_62m5,
+      rst_n_i  => '1',
+      data_i   => areset_edge_n_i,
+      ppulse_o => areset_edge_ppulse);
+
+  -- logic AND of all async reset sources (active low)
+  rstlogic_arst_n <= pll_locked and areset_n_i and (not areset_edge_ppulse);
+
+  -- concatenation of all clocks required to have synced resets
+  rstlogic_clk_in(0) <= clk_pll_62m5;
+  rstlogic_clk_in(1) <= clk_pll_125m;
+
+  cmp_rstlogic_reset : gc_reset
+    generic map (
+      g_clocks    => 2,                           -- 62.5MHz, 125MHz
+      g_logdelay  => 4,                           -- 16 clock cycles
+      g_syncdepth => 3)                           -- length of sync chains
+    port map (
+      free_clk_i => clk_125m_pllref_buf,
+      locked_i   => rstlogic_arst_n,
+      clks_i     => rstlogic_clk_in,
+      rstn_o     => rstlogic_rst_out);
+
+  -- distribution of resets (already synchronized to their clock domains)
+  rst_62m5_n <= rstlogic_rst_out(0);
+
+  rst_sys_62m5_n_o <= rst_62m5_n;
+  rst_ref_125m_n_o <= rstlogic_rst_out(1);
+
+  -----------------------------------------------------------------------------
+  -- 2x SPI DAC
+  -----------------------------------------------------------------------------
+
+  cmp_dac_arb : spec_serial_dac_arb
+    generic map (
+      g_invert_sclk    => FALSE,
+      g_num_extra_bits => 8)
+    port map (
+      clk_i         => clk_pll_62m5,
+      rst_n_i       => rst_62m5_n,
+      val1_i        => dac_dpll_data,
+      load1_i       => dac_dpll_load_p1,
+      val2_i        => dac_hpll_data,
+      load2_i       => dac_hpll_load_p1,
+      dac_cs_n_o(0) => pll25dac_cs_n_o,
+      dac_cs_n_o(1) => pll20dac_cs_n_o,
+      dac_sclk_o    => plldac_sclk_o,
+      dac_din_o     => plldac_din_o);
+
+  -----------------------------------------------------------------------------
+  -- The WR PTP core with optional fabric interface attached
+  -----------------------------------------------------------------------------
+
+  cmp_board_common : xwrc_board_common
+    generic map (
+      g_simulation                => g_simulation,
+      g_with_external_clock_input => g_with_external_clock_input,
+      g_board_name                => "FSEC",
+      g_phys_uart                 => TRUE,
+      g_virtual_uart              => TRUE,
+      g_aux_clks                  => g_aux_clks,
+      g_ep_rxbuf_size             => 1024,
+      g_tx_runt_padding           => TRUE,
+      g_dpram_initf               => g_dpram_initf,
+      g_dpram_size                => 131072/4,
+      g_interface_mode            => PIPELINED,
+      g_address_granularity       => BYTE,
+      g_aux_sdb                   => c_wrc_periph3_sdb,
+      g_softpll_enable_debugger   => FALSE,
+      g_vuart_fifo_size           => 1024,
+      g_pcs_16bit                 => TRUE,
+      g_diag_id                   => g_diag_id,
+      g_diag_ver                  => g_diag_ver,
+      g_diag_ro_size              => g_diag_ro_size,
+      g_diag_rw_size              => g_diag_rw_size,
+      g_streamers_op_mode         => g_streamers_op_mode,
+      g_tx_streamer_params        => g_tx_streamer_params,
+      g_rx_streamer_params        => g_rx_streamer_params,
+      g_fabric_iface              => g_fabric_iface
+      )
+    port map (
+      clk_sys_i            => clk_pll_62m5,
+      clk_dmtd_i           => clk_pll_dmtd,
+      clk_ref_i            => clk_pll_125m,
+      clk_aux_i            => clk_aux_i,
+      clk_10m_ext_i        => clk_10m_ext,
+      clk_ext_mul_i        => ext_ref_mul,
+      clk_ext_mul_locked_i => ext_ref_mul_locked,
+      clk_ext_stopped_i    => ext_ref_mul_stopped,
+      clk_ext_rst_o        => ext_ref_rst,
+      pps_ext_i            => pps_ext_i,
+      rst_n_i              => rst_62m5_n,
+      dac_hpll_load_p1_o   => dac_hpll_load_p1,
+      dac_hpll_data_o      => dac_hpll_data,
+      dac_dpll_load_p1_o   => dac_dpll_load_p1,
+      dac_dpll_data_o      => dac_dpll_data,
+      phy16_o              => phy16_from_wrc,
+      phy16_i              => phy16_to_wrc,
+      scl_o                => eeprom_scl_t,
+      scl_i                => eeprom_scl_i,
+      sda_o                => eeprom_sda_t,
+      sda_i                => eeprom_sda_i,
+      sfp_scl_o            => sfp_scl_t,
+      sfp_scl_i            => sfp_scl_i,
+      sfp_sda_o            => sfp_sda_t,
+      sfp_sda_i            => sfp_sda_i,
+      sfp_det_i            => sfp_det_i,
+      spi_sclk_o           => flash_sclk_o,
+      spi_ncs_o            => flash_ncs_o,
+      spi_mosi_o           => flash_mosi_o,
+      spi_miso_i           => flash_miso_i,
+      uart_rxd_i           => uart_rxd_i,
+      uart_txd_o           => uart_txd_o,
+      owr_pwren_o          => open,
+      owr_en_o             => onewire_en,
+      owr_i                => onewire_in,
+      wb_slave_i           => wb_slave_in,
+      wb_slave_o           => wb_slave_out,
+      aux_master_o         => aux_master_o,
+      aux_master_i         => aux_master_i,
+      wrf_src_o            => wrf_src_o,
+      wrf_src_i            => wrf_src_i,
+      wrf_snk_o            => wrf_snk_o,
+      wrf_snk_i            => wrf_snk_i,
+      wrs_tx_data_i        => wrs_tx_data_i,
+      wrs_tx_valid_i       => wrs_tx_valid_i,
+      wrs_tx_dreq_o        => wrs_tx_dreq_o,
+      wrs_tx_last_i        => wrs_tx_last_i,
+      wrs_tx_flush_i       => wrs_tx_flush_i,
+      wrs_tx_cfg_i         => wrs_tx_cfg_i,
+      wrs_rx_first_o       => wrs_rx_first_o,
+      wrs_rx_last_o        => wrs_rx_last_o,
+      wrs_rx_data_o        => wrs_rx_data_o,
+      wrs_rx_valid_o       => wrs_rx_valid_o,
+      wrs_rx_dreq_i        => wrs_rx_dreq_i,
+      wrs_rx_cfg_i         => wrs_rx_cfg_i,
+      wb_eth_master_o      => wb_eth_master_o,
+      wb_eth_master_i      => wb_eth_master_i,
+      aux_diag_i           => aux_diag_i,
+      aux_diag_o           => aux_diag_o,
+      tm_dac_value_o       => tm_dac_value_o,
+      tm_dac_wr_o          => tm_dac_wr_o,
+      tm_clk_aux_lock_en_i => tm_clk_aux_lock_en_i,
+      tm_clk_aux_locked_o  => tm_clk_aux_locked_o,
+      timestamps_o         => timestamps_o,
+      timestamps_ack_i     => timestamps_ack_i,
+      abscal_txts_o        => abscal_txts_o,
+      abscal_rxts_o        => abscal_rxts_o,
+      fc_tx_pause_req_i    => fc_tx_pause_req_i,
+      fc_tx_pause_delay_i  => fc_tx_pause_delay_i,
+      fc_tx_pause_ready_o  => fc_tx_pause_ready_o,
+      tm_link_up_o         => tm_link_up_o,
+      tm_time_valid_o      => tm_time_valid_o,
+      tm_tai_o             => tm_tai_o,
+      tm_cycles_o          => tm_cycles_o,
+      led_act_o            => led_act_o,
+      led_link_o           => led_link_o,
+      btn1_i               => btn1_i,
+      btn2_i               => btn2_i,
+      pps_p_o              => pps_p_o,
+      pps_led_o            => pps_led_o,
+      link_ok_o            => link_ok_o);
+
+  sfp_rate_select_o <= '1';
+
+  --onewire_oen_o <= onewire_en(0);
+  --onewire_in(0) <= onewire_i;
+  --onewire_in(1) <= '1';
+
+  thermo_id_t <= '0' when onewire_en(0) = '1' else '1';
+  thermo_id_o <= '0';
+  onewire_in(0) <= thermo_id_i;
+  onewire_in(1) <= '1';
+
+  eeprom_sda_o <= '0';
+  eeprom_scl_o <= '0';
+  sfp_sda_o    <= '0';
+  sfp_scl_o    <= '0';
+
+  s00_axi_aclk_o <= clk_pll_62m5;
+
+  zero <= '0';
+  cmp_axi4lite_wbm: wb_axi4lite_bridge
+    port map (
+      clk_sys_i => clk_pll_62m5,
+      rst_n_i   => s00_axi_aresetn,
+
+      AWADDR  => s00_axi_awaddr, 
+      AWVALID => s00_axi_awvalid,
+      AWREADY => s00_axi_awready,
+      WDATA   => s00_axi_wdata,
+      WSTRB   => s00_axi_wstrb,
+      WVALID  => s00_axi_wvalid,
+      WREADY  => s00_axi_wready,
+      WLAST   => zero,
+      BRESP   => s00_axi_bresp,
+      BVALID  => s00_axi_bvalid,
+      BREADY  => s00_axi_bready,
+      ARADDR  => s00_axi_araddr,
+      ARVALID => s00_axi_arvalid,
+      ARREADY => s00_axi_arready,
+      RDATA   => s00_axi_rdata,
+      RRESP   => s00_axi_rresp,
+      RVALID  => s00_axi_rvalid,
+      RREADY  => s00_axi_rready,
+      RLAST   => s00_axi_rlast,
+
+      wb_adr  => wb_slave_in.adr,
+      wb_dat_m2s => wb_slave_in.dat,
+      wb_sel => wb_slave_in.sel,
+      wb_cyc => wb_slave_in.cyc,
+      wb_stb => wb_slave_in.stb,
+      wb_we  => wb_slave_in.we,
+
+      wb_dat_s2m => wb_slave_out.dat,
+      wb_err     => wb_slave_out.err,
+      wb_rty     => wb_slave_out.rty,
+      wb_ack     => wb_slave_out.ack,
+      wb_stall   => wb_slave_out.stall
+    );
+  
+
+end architecture struct;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd
new file mode 100644
index 000000000..684633eba
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd
@@ -0,0 +1,177 @@
+------------------------------------------------------------------------------
+-- Title      : Etherbone Config Master FIFO
+-- Project    : Etherbone Core
+------------------------------------------------------------------------------
+-- File       : eb_cfg_fifo.vhd
+-- Author     : Wesley W. Terpstra
+-- Company    : GSI
+-- Created    : 2013-04-08
+-- Last update: 2013-04-08
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Buffers Config space requests
+-------------------------------------------------------------------------------
+-- Copyright (c) 2013 GSI
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2013-04-08  1.0      terpstra        Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.wishbone_pkg.all;
+use work.eb_internals_pkg.all;
+
+entity eb_cfg_fifo is
+  generic(
+    g_sdb_address : t_wishbone_address);
+  port(
+    clk_i       : in  std_logic;
+    rstn_i      : in  std_logic;
+    
+    errreg_i    : in  std_logic_vector(63 downto 0);
+    
+    cfg_i       : in  t_wishbone_slave_in;
+    cfg_o       : out t_wishbone_slave_out;
+    
+    fsm_stb_i   : in  std_logic;
+    fsm_adr_i   : in  t_wishbone_address;
+    fsm_full_o  : out std_logic;
+
+    mux_pop_i   : in  std_logic;
+    mux_dat_o   : out t_wishbone_data;
+    mux_empty_o : out std_logic;
+    
+    my_mac_o    : out std_logic_vector(47 downto 0);
+    my_ip_o     : out std_logic_vector(31 downto 0);
+    my_port_o   : out std_logic_vector(15 downto 0));
+end eb_cfg_fifo;
+
+architecture rtl of eb_cfg_fifo is
+  
+  constant c_pad  : std_logic_vector(31 downto 16) := (others => '0');
+  
+  signal r_mac  : std_logic_vector(6*8-1 downto 0);
+  signal r_ip   : std_logic_vector(4*8-1 downto 0);
+  signal r_port : std_logic_vector(2*8-1 downto 0);
+  
+  signal s_fsm_adr     : std_logic_vector(2 downto 0);
+  signal s_fifo_adr    : std_logic_vector(2 downto 0);
+  signal s_fifo_empty  : std_logic;
+  signal s_fifo_pop    : std_logic;
+  signal r_cache_empty : std_logic;
+  signal r_cache_adr   : std_logic_vector(2 downto 0);
+  
+  impure function update(x : std_logic_vector) return std_logic_vector is
+    alias    y : std_logic_vector(x'length-1 downto 0) is x;
+    variable o : std_logic_vector(x'length-1 downto 0);
+  begin
+    for i in (y'length/8)-1 downto 0 loop
+      if cfg_i.sel(i) = '1' then
+        o(i*8+7 downto i*8) := cfg_i.dat(i*8+7 downto i*8);
+      else
+        o(i*8+7 downto i*8) := y(i*8+7 downto i*8);
+      end if;
+    end loop;
+    
+    return o;
+  end update;
+  
+begin
+
+  cfg_o.int <= '0';
+  cfg_o.err <= '0';
+  cfg_o.rty <= '0';
+  cfg_o.stall <= '0';
+
+  cfg_wbs : process(rstn_i, clk_i) is
+  begin
+    if rstn_i = '0' then
+      r_mac  <= x"D15EA5EDBEEF";
+      r_ip   <= x"C0A80064";
+      r_port <= x"EBD0";
+      
+      cfg_o.ack <= '0';
+      cfg_o.dat <= (others => '0');
+    elsif rising_edge(clk_i) then
+      if cfg_i.cyc = '1' and cfg_i.stb = '1' and cfg_i.we = '1' then
+        case to_integer(unsigned(cfg_i.adr(4 downto 2))) is
+          when 4 => r_mac(47 downto 32) <= update(r_mac(47 downto 32));
+          when 5 => r_mac(31 downto  0) <= update(r_mac(31 downto  0));
+          when 6 => r_ip   <= update(r_ip);
+          when 7 => r_port <= update(r_port);
+          when others => null;
+        end case;
+      end if;
+      
+      cfg_o.ack <= cfg_i.cyc and cfg_i.stb;
+      
+      case to_integer(unsigned(cfg_i.adr(4 downto 2))) is
+        when 0 => cfg_o.dat <= errreg_i(63 downto 32);
+        when 1 => cfg_o.dat <= errreg_i(31 downto  0);
+        when 2 => cfg_o.dat <= (others => '0');
+        when 3 => cfg_o.dat <= g_sdb_address;
+        when 4 => cfg_o.dat <= c_pad & r_mac(47 downto 32);
+        when 5 => cfg_o.dat <= r_mac(31 downto 0);
+        when 6 => cfg_o.dat <= r_ip;
+        when others => cfg_o.dat <= c_pad & r_port;
+      end case;
+      
+    end if;
+  end process;
+
+  -- Discard writes.
+  s_fsm_adr  <= fsm_adr_i(4 downto 2);
+  
+  fifo : eb_fifo
+    generic map(
+      g_width => 3,
+      g_size  => c_queue_depth)
+    port map(
+      clk_i     => clk_i,
+      rstn_i    => rstn_i,
+      w_full_o  => fsm_full_o,
+      w_push_i  => fsm_stb_i,
+      w_dat_i   => s_fsm_adr,
+      r_empty_o => s_fifo_empty,
+      r_pop_i   => s_fifo_pop,
+      r_dat_o   => s_fifo_adr);
+      
+  s_fifo_pop <= not s_fifo_empty and (r_cache_empty or mux_pop_i);
+  
+  cache : process(rstn_i, clk_i) is
+  begin
+    if rstn_i = '0' then
+      r_cache_empty <= '1';
+      r_cache_adr   <= (others => '0');
+    elsif rising_edge(clk_i) then
+      if r_cache_empty = '1' or mux_pop_i = '1' then
+        r_cache_empty <= s_fifo_empty;
+        r_cache_adr   <= s_fifo_adr;
+      end if;
+    end if;
+  end process;
+  
+  mux_empty_o <= r_cache_empty;
+  
+  with r_cache_adr select 
+  mux_dat_o <= 
+    errreg_i(63 downto 32)      when "000",
+    errreg_i(31 downto  0)      when "001",
+    x"00000000"                 when "010",
+    g_sdb_address               when "011",
+    c_pad & r_mac(47 downto 32) when "100",
+            r_mac(31 downto  0) when "101",
+    r_ip                        when "110",
+    c_pad & r_port              when others;
+    
+  my_mac_o  <= r_mac;
+  my_ip_o   <= r_ip;
+  my_port_o <= r_port;
+
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd
new file mode 100644
index 000000000..6eb2c9df2
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd
@@ -0,0 +1,101 @@
+--! @file eb_checksum.vhd
+--! @brief IP checksum generator for EtherBone
+--!
+--! Copyright (C) 2011-2012 GSI Helmholtz Centre for Heavy Ion Research GmbH 
+--!
+--! Important details about its implementation
+--! should go in these comments.
+--!
+--! @author Mathias Kreider <m.kreider@gsi.de>
+--!
+--! @bug No know bugs.
+--!
+--------------------------------------------------------------------------------
+--! This library is free software; you can redistribute it and/or
+--! modify it under the terms of the GNU Lesser General Public
+--! License as published by the Free Software Foundation; either
+--! version 3 of the License, or (at your option) any later version.
+--!
+--! This library is distributed in the hope that it will be useful,
+--! but WITHOUT ANY WARRANTY; without even the implied warranty of
+--! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+--! Lesser General Public License for more details.
+--!  
+--! You should have received a copy of the GNU Lesser General Public
+--! License along with this library. If not, see <http://www.gnu.org/licenses/>.
+---------------------------------------------------------------------------------
+
+---! Standard library
+library IEEE;
+--! Standard packages    
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+--! Additional library
+library work;
+--! Additional packages    
+use work.eb_hdr_pkg.all;
+
+entity eb_checksum is 
+  port(
+    clk_i  : in  std_logic;
+    nRst_i : in  std_logic;
+    en_i   : in  std_logic; 
+    data_i : in  std_logic_vector(15 downto 0);
+    done_o : out std_logic;
+    sum_o  : out std_logic_vector(15 downto 0));
+end eb_checksum;
+
+architecture behavioral of eb_checksum is
+  constant c_width : natural := 28;
+  type t_state is (S_IDLE, S_ADDUP);
+
+  signal state : t_state := S_IDLE;
+  signal sum   : unsigned(c_width-1 downto 0);
+
+  function f_wrap(sum : unsigned) return unsigned is
+    variable sum0, sum1 : unsigned(16 downto 0);
+  begin
+    sum0 := resize(sum(15 downto 0), 17) + resize(sum(c_width-1 downto 16), 17);
+    sum1 := resize(sum(15 downto 0), 17) + resize(sum(c_width-1 downto 16), 17) + 1;
+    if sum0(16) = '1' then
+      return sum1(15 downto 0);
+    else
+      return sum0(15 downto 0);
+    end if;
+  end f_wrap;
+  
+begin
+
+  sum_o <= std_logic_vector(sum(15 downto 0));
+  
+  adder: process(clk_i, nRst_i)
+  begin
+    if nRst_i = '0' then
+      done_o <= '0';
+      state  <= S_IDLE;
+      sum    <= (others => '0');
+    elsif rising_edge(clk_i) then
+      case state is
+        
+        when S_IDLE =>
+          done_o <= '0';
+          if en_i = '1' then
+            state <= S_ADDUP;
+            sum <= resize(unsigned(data_i), c_width);
+          end if;
+        
+        when S_ADDUP =>
+          if en_i = '0' then
+            sum <= resize(f_wrap(sum), c_width);
+            done_o <= '1';
+            state <= S_IDLE;
+          else 
+            sum <= sum + resize(unsigned(data_i), c_width);
+          end if;
+        
+      end case;
+    end if;
+  end process;
+  
+end behavioral;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd
new file mode 100644
index 000000000..24bab963d
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd
@@ -0,0 +1,123 @@
+------------------------------------------------------------------------------
+-- Title      : Etherbone Commit FIFO
+-- Project    : Etherbone Core
+------------------------------------------------------------------------------
+-- File       : eb_fifo.vhd
+-- Author     : Wesley W. Terpstra
+-- Company    : GSI
+-- Created    : 2013-04-29
+-- Last update: 2013-04-29
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: A FIFO which can commit/abort a sequence of writes
+-------------------------------------------------------------------------------
+-- Copyright (c) 2013 GSI
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2013-04-08  1.0      terpstra        Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.wishbone_pkg.all;
+use work.eb_internals_pkg.all;
+use work.genram_pkg.all;
+
+-- r_dat_o is valid when r_empty_o=0 (show ahead)
+-- w_dat_i is valid when w_push_i =1
+-- r_pop_i  affects r_empty_o on the next cycle
+-- w_push_i affects w_full_o  on the next cycle
+entity eb_commit_fifo is
+  generic(
+    g_width : natural;
+    g_size  : natural);
+  port(
+    clk_i      : in  std_logic;
+    rstn_i     : in  std_logic;
+    w_full_o   : out std_logic;
+    w_push_i   : in  std_logic;
+    w_dat_i    : in  std_logic_vector(g_width-1 downto 0);
+    w_commit_i : in  std_logic;
+    w_abort_i  : in  std_logic;
+    r_empty_o  : out std_logic;
+    r_pop_i    : in  std_logic;
+    r_dat_o    : out std_logic_vector(g_width-1 downto 0));
+end eb_commit_fifo;
+
+architecture rtl of eb_commit_fifo is
+  constant c_depth : natural := f_ceil_log2(g_size);
+  
+  signal r_idx  : unsigned(c_depth downto 0);
+  signal w_idx  : unsigned(c_depth downto 0);
+  signal e_idx  : unsigned(c_depth downto 0);
+  signal r_idx1 : unsigned(c_depth downto 0);
+  signal w_idx1 : unsigned(c_depth downto 0);
+  
+  constant c_low  : unsigned(c_depth-1 downto 0) := (others => '0');
+  constant c_high : unsigned(c_depth   downto 0) := '1' & c_low;
+  
+begin
+
+  ram : generic_simple_dpram
+    generic map(
+      g_data_width => g_width,
+      g_size       => 2**c_depth,
+      g_dual_clock => false)
+    port map(
+      rst_n_i => rstn_i,
+      clka_i  => clk_i,
+      bwea_i  => (others => '1'),
+      wea_i   => w_push_i,
+      aa_i    => std_logic_vector(w_idx(c_depth-1 downto 0)),
+      da_i    => w_dat_i,
+      clkb_i  => clk_i,
+      ab_i    => std_logic_vector(r_idx1(c_depth-1 downto 0)),
+      qb_o    => r_dat_o);
+  
+  r_idx1 <= (r_idx+1) when r_pop_i ='1' else r_idx;
+  w_idx1 <= (w_idx+1) when w_push_i='1' else w_idx;
+  
+  main : process(rstn_i, clk_i) is
+  begin
+    if rstn_i = '0' then
+      r_idx     <= (others => '0');
+      e_idx     <= (others => '0');
+      w_idx     <= (others => '0');
+      w_full_o  <= '0';
+      r_empty_o <= '1';
+    elsif rising_edge(clk_i) then
+      r_idx <= r_idx1;
+      
+      if w_commit_i = '1' then
+        e_idx <= w_idx1;
+      end if;
+      
+      if w_abort_i = '1' then
+        w_idx <= e_idx;
+      else
+        w_idx <= w_idx1;
+      end if;
+      
+      -- Compare the newest pointers
+      if (w_idx1 xor c_high) = r_idx1 then
+        w_full_o <= '1';
+      else
+        w_full_o <= '0';
+      end if;
+      
+      -- Use the OLD write pointer to prevent read-during-write
+      if e_idx = r_idx1 then
+        r_empty_o <= '1';
+      else
+        r_empty_o <= '0';
+      end if;
+      
+    end if;
+  end process;
+
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd
new file mode 100644
index 000000000..e4e60e3dd
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd
@@ -0,0 +1,183 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+library work;
+use work.wishbone_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.eb_hdr_pkg.all;
+
+entity eb_eth_rx is
+  generic(
+    g_mtu : natural);
+  port(
+    clk_i     : in  std_logic;
+    rst_n_i   : in  std_logic;
+    snk_i     : in  t_wrf_sink_in;
+    snk_o     : out t_wrf_sink_out;
+    master_o  : out t_wishbone_master_out;
+    master_i  : in  t_wishbone_master_in;
+    stb_o     : out std_logic;
+    stall_i   : in  std_logic;
+    mac_o     : out std_logic_vector(47 downto 0);
+    ip_o      : out std_logic_vector(31 downto 0);
+    port_o    : out std_logic_vector(15 downto 0);
+    length_o  : out unsigned(15 downto 0));
+end eb_eth_rx;
+
+architecture rtl of eb_eth_rx is
+  subtype t_index is unsigned(f_ceil_log2(g_mtu)-1 downto 0);
+  
+  type t_state is (S_DROP, S_WAIT, S_ETHERNET, S_IP, S_UDP, S_STB);
+  
+  -- Two bytes at a time
+  constant c_step : natural := 2;
+  
+  signal r_state      : t_state;
+  signal r_state_next : t_state;
+  signal r_count      : t_index;
+  
+  signal r_ack    : std_logic;
+  signal r_pass   : std_logic;
+  signal r_shift  : std_logic_vector(c_ip_len*8-1 downto 0);
+  signal r_stb    : std_logic;
+  signal r_mac    : std_logic_vector(47 downto 0);
+  signal r_ip     : std_logic_vector(31 downto 0);
+  signal r_port   : std_logic_vector(15 downto 0);
+  signal r_length : unsigned(15 downto 0);
+  
+  signal s_stall   : std_logic;
+  signal s_eth_hdr : t_eth_hdr;
+  signal s_ip_hdr  : t_ip_hdr;
+  signal s_udp_hdr : t_udp_hdr;
+  signal s_optlen  : unsigned(3 downto 0);
+  signal s_shift  : std_logic_vector(c_ip_len*8-1 downto 0);
+  
+  function f_step(x : natural) return t_index is
+  begin
+    return to_unsigned(x/2 - 1, t_index'length);
+  end function;
+begin
+
+  master_o.cyc <= snk_i.cyc;
+  master_o.stb <= (r_pass and snk_i.stb) when snk_i.adr = c_WRF_DATA else '0';
+  master_o.adr <= (others => '0');
+  master_o.sel <= "0011";
+  master_o.we  <= '1';
+  master_o.dat(31 downto 16) <= (others => '0');
+  master_o.dat(15 downto  0) <= snk_i.dat;
+  
+  snk_o.ack <= r_ack;
+  snk_o.err <= '0';
+  snk_o.rty <= '0';
+  snk_o.stall <= s_stall;
+  
+  stb_o    <= r_stb;
+  mac_o    <= r_mac;
+  ip_o     <= r_ip;
+  port_o   <= r_port;
+  length_o <= r_length;
+  
+  s_stall <= r_stb when r_state = S_UDP else (r_pass and master_i.stall);
+  
+  -- These are valid when header is fully shifted in
+  s_shift   <= r_shift(r_shift'left-16 downto 0) & snk_i.dat;
+  s_eth_hdr <= f_parse_eth(s_shift);
+  s_ip_hdr  <= f_parse_ip (s_shift);
+  s_udp_hdr <= f_parse_udp(s_shift);
+  
+  s_optlen <= unsigned(s_ip_hdr.ihl)-5;
+
+  fsm : process(clk_i, rst_n_i) is
+  begin
+    if rst_n_i = '0' then
+      r_state      <= S_WAIT;
+      r_state_next <= S_ETHERNET;
+      r_count      <= f_step(c_eth_len);
+      
+      r_ack    <= '0';
+      r_pass   <= '0';
+      r_shift  <= (others => '0');
+      r_stb    <= '0';
+      r_mac    <= (others => '0');
+      r_ip     <= (others => '0');
+      r_port   <= (others => '0');
+      r_length <= (others => '0');
+    elsif rising_edge(clk_i) then
+      r_ack   <= snk_i.cyc and snk_i.stb and not s_stall;
+      r_stb   <= r_stb and stall_i;
+      
+      if snk_i.cyc = '0' then
+        r_pass       <= '0';
+        r_state      <= S_WAIT;
+        r_state_next <= S_ETHERNET;
+        r_count      <= f_step(c_eth_len);
+      elsif snk_i.stb = '1' and s_stall = '0' and snk_i.adr = c_WRF_DATA then
+      
+        -- defaults
+        r_state      <= S_WAIT;
+        r_state_next <= S_DROP;
+        r_count      <= r_count - 1;
+        r_shift      <= s_shift;
+        
+        case r_state is
+          -- special states
+          when S_DROP => 
+            r_state <= S_DROP;
+            r_pass <= '0';
+            
+          when S_WAIT =>
+            r_state_next <= r_state_next;
+            if r_count = to_unsigned(1, r_count'length) then
+              r_state <= r_state_next;
+            end if;
+          
+          -- payload states
+          when S_ETHERNET =>
+            r_mac <= s_eth_hdr.src;
+            
+            r_count <= f_step(c_ip_len);
+            if s_eth_hdr.typ = c_eth_typ_ip then
+              r_state_next <= S_IP;
+            else
+              r_state <= S_DROP;
+            end if;
+          
+          when S_IP =>
+            r_ip <= s_ip_hdr.src;
+            
+            r_count <= f_step(to_integer(s_optlen)*4 + c_udp_len);
+            if s_ip_hdr.ver = x"4" and unsigned(s_ip_hdr.ihl) >= 5 and s_ip_hdr.pro = c_ip_typ_udp then
+              r_state_next <= S_UDP;
+            else
+              r_state <= S_DROP;
+            end if;
+          
+          when S_UDP =>
+            r_port   <= s_udp_hdr.src;
+            r_length <= unsigned(s_udp_hdr.len);
+            
+            -- Raise stb four bytes after fsm starts (=> fsm will TX)
+            r_count <= f_step(4);
+            
+            -- Enforce MTU and 4-byte alignment
+            if unsigned(s_udp_hdr.len) >= 12 and 
+               unsigned(s_udp_hdr.len) <= g_mtu-c_ip_len and
+               s_udp_hdr.len(1 downto 0) = "00" then
+              r_pass <= '1'; -- Feed future bytes to etherbone fsm
+              r_state_next <= S_STB;
+            else
+              r_state <= S_DROP;
+            end if;
+          
+          when S_STB =>
+            r_stb   <= '1'; -- this must be 4 bytes after r_pass='1'
+            r_count <= f_step(to_integer(r_length)-c_udp_len-4);
+            r_state_next <= S_DROP;
+          
+        end case;
+      end if;
+    end if;
+  end process;
+  
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd
new file mode 100644
index 000000000..661c7712d
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd
@@ -0,0 +1,332 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+library work;
+use work.wishbone_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.eb_internals_pkg.all;
+use work.eb_hdr_pkg.all;
+
+entity eb_eth_tx is
+  generic(
+    g_mtu : natural);
+  port(
+    clk_i        : in  std_logic;
+    rst_n_i      : in  std_logic;
+    src_i        : in  t_wrf_source_in;
+    src_o        : out t_wrf_source_out;
+    slave_o      : out t_wishbone_slave_out;
+    slave_i      : in  t_wishbone_slave_in;
+    stb_i        : in  std_logic;
+    stall_o      : out std_logic;
+    mac_i        : in  std_logic_vector(47 downto 0);
+    ip_i         : in  std_logic_vector(31 downto 0);
+    port_i       : in  std_logic_vector(15 downto 0);
+    length_i     : in  unsigned(15 downto 0);
+    skip_stb_i   : in  std_logic;
+    skip_stall_o : out std_logic;
+    my_mac_i     : in  std_logic_vector(47 downto 0);
+    my_ip_i      : in  std_logic_vector(31 downto 0);
+    my_port_i    : in  std_logic_vector(15 downto 0));
+end eb_eth_tx;
+
+architecture rtl of eb_eth_tx is
+  type t_state is (S_WRF_STATUS, S_ETHERNET, S_IP, S_UDP, S_DONE, S_WAIT, S_PAYLOAD, S_RUNT, S_LOWER, S_SKIP, S_PUSH);
+  type t_sum_state is (S_CONST, S_DST_HI, S_DST_LO, S_SRC_HI, S_SRC_LO, S_LENGTH, S_DONE);
+  
+  signal r_state  : t_state;
+  signal r_staten : t_state;
+  signal r_count  : unsigned(4 downto 0);
+  
+  signal r_ready  : std_logic;
+  signal r_mac    : std_logic_vector(47 downto 0);
+  signal r_ip     : std_logic_vector(31 downto 0);
+  signal r_port   : std_logic_vector(15 downto 0);
+  signal r_length : unsigned(15 downto 0);
+
+  signal r_hdr_stb : std_logic;
+  signal r_shift   : std_logic_vector(c_ip_len*8-1 downto 0);
+  signal r_ack     : std_logic;
+  signal s_stall   : std_logic;
+  
+  signal s_buf_stb    : std_logic;
+  signal s_buf_full   : std_logic;
+  signal s_buf_push   : std_logic;
+  signal s_buf_commit : std_logic;
+  signal s_buf_abort  : std_logic;
+  signal s_buf_cyc    : std_logic;
+  signal s_buf_data   : std_logic_vector(15 downto 0);
+  signal r_buf_typ    : std_logic;
+  
+  signal r_tx_cyc   : std_logic;
+  signal s_tx_empty : std_logic;
+  signal s_tx_pop   : std_logic;
+  signal s_tx_cyc   : std_logic;
+  signal s_tx_typ   : std_logic;
+  signal s_tx_dat   : std_logic_vector(15 downto 0);
+  
+  signal r_sum_state : t_sum_state;
+  signal r_sum_en    : std_logic;
+  signal r_sum_data  : std_logic_vector(15 downto 0);
+  signal s_sum_done  : std_logic_vector(15 downto 0);
+  
+  constant c_hdr_len  : natural := c_ip_len;
+  constant c_runt_min : natural := 46 - c_ip_len;
+  
+  function f_send_eth(dst, src : std_logic_vector(47 downto 0)) return std_logic_vector is
+    variable o : std_logic_vector(c_hdr_len*8-1 downto 0) := (others => '-');
+    variable eth : t_eth_hdr := c_eth_init;
+  begin
+    eth.dst := dst;
+    eth.src := src;
+    o(o'left downto (c_hdr_len-c_eth_len)*8) := f_format_eth(eth);
+    return o;
+  end function;
+  
+  function f_send_ip(dst, src : std_logic_vector(31 downto 0); len : unsigned(15 downto 0); sum : std_logic_vector(15 downto 0)) return std_logic_vector is
+    variable o : std_logic_vector(c_hdr_len*8-1 downto 0) := (others => '-');
+    variable ip : t_ip_hdr := c_ip_init;
+  begin
+    ip.tol := std_logic_vector(len+20);
+    ip.dst := dst;
+    ip.src := src;
+    ip.sum := not sum;
+    o(o'left downto (c_hdr_len-c_ip_len)*8) := f_format_ip(ip);
+    return o;
+  end function;
+  
+  function f_send_udp(dst, src : std_logic_vector(15 downto 0); len : unsigned(15 downto 0)) return std_logic_vector is
+    variable o : std_logic_vector(c_hdr_len*8-1 downto 0) := (others => '-');
+    variable udp : t_udp_hdr := c_udp_init;
+  begin
+    udp.src := src;
+    udp.dst := dst;
+    udp.len := std_logic_vector(len);
+    o(o'left downto (c_hdr_len-c_udp_len)*8) := f_format_udp(udp);
+    return o;
+  end function;
+  
+  function f_step(x : natural) return unsigned is
+  begin
+    return to_unsigned(x/2 - 1, 5);
+  end function;
+  
+begin
+
+  tx : eb_commit_fifo
+    generic map(
+      g_width => 18,
+      g_size  => (g_mtu+c_eth_len)/2)
+    port map(
+      clk_i      => clk_i,
+      rstn_i     => rst_n_i,
+      w_full_o   => s_buf_full,
+      w_push_i   => s_buf_push,
+      w_commit_i => s_buf_commit,
+      w_abort_i  => s_buf_abort,
+      r_empty_o  => s_tx_empty,
+      r_pop_i    => s_tx_pop,
+      w_dat_i(17)          => s_buf_cyc,
+      w_dat_i(16)          => r_buf_typ,
+      w_dat_i(15 downto 0) => s_buf_data,
+      r_dat_o(17)          => s_tx_cyc,
+      r_dat_o(16)          => s_tx_typ,
+      r_dat_o(15 downto 0) => s_tx_dat);
+  
+  slave_o.ack <= r_ack;
+  slave_o.int <= '0';
+  slave_o.rty <= '0';
+  slave_o.err <= '0';
+  slave_o.stall <= s_stall;
+  slave_o.dat <= (others => '0');
+  
+  stall_o <= r_ready; -- already have params
+  
+  s_stall      <= s_buf_full when r_state=S_PAYLOAD else '1';
+  skip_stall_o <= '0' when r_state=S_SKIP else '1';
+  s_buf_stb    <= (slave_i.cyc and slave_i.stb) when r_state=S_PAYLOAD else r_hdr_stb;
+  s_buf_push   <= s_buf_stb and not s_buf_full;
+  s_buf_abort  <= '1' when r_state=S_SKIP  else '0';
+  s_buf_commit <= '1' when r_state=S_LOWER else '0';
+  s_buf_cyc    <= '0' when r_state=S_LOWER else '1';
+  s_buf_data   <= slave_i.dat(15 downto 0) when r_state=S_PAYLOAD else r_shift(r_shift'left downto r_shift'left-15);
+  
+  hdr : process(clk_i, rst_n_i) is
+  begin
+    if rst_n_i = '0' then
+      r_state   <= S_WRF_STATUS;
+      r_staten  <= S_WRF_STATUS;
+      r_count   <= (others => '0');
+      r_ready   <= '0';
+      r_mac     <= (others => '0');
+      r_ip      <= (others => '0');
+      r_port    <= (others => '0');
+      r_length  <= (others => '0');
+      r_hdr_stb <= '0';
+      r_ack     <= '0';
+      r_shift   <= (others => '-');
+      r_tx_cyc  <= '0';
+    elsif rising_edge(clk_i) then
+      r_ack <= slave_i.cyc and slave_i.stb and not s_stall;
+      
+      if s_tx_empty = '0' then
+        r_tx_cyc <= s_tx_cyc;
+      end if;
+      
+      if stb_i = '1' and r_ready = '0' then
+        r_mac    <= mac_i;
+        r_ip     <= ip_i;
+        r_port   <= port_i;
+        r_length <= length_i;
+        r_ready  <= '1';
+      end if;
+      
+      case r_state is
+        when S_WRF_STATUS =>
+          if r_ready = '1' then
+            r_hdr_stb <= '1';
+            r_buf_typ <= '1';
+            r_shift   <= (others => '0');
+            r_state   <= S_ETHERNET;
+          end if;
+        
+        when S_ETHERNET =>
+          if s_buf_full = '0' then
+            r_buf_typ <= '0';
+            r_shift   <= f_send_eth(r_mac, my_mac_i);
+            r_count   <= f_step(c_eth_len);
+            r_staten  <= S_IP;
+            r_state   <= S_PUSH;
+          end if;
+          
+        when S_IP =>
+          if s_buf_full = '0' then
+            r_shift  <= f_send_ip(r_ip, my_ip_i, r_length, s_sum_done);
+            r_count  <= f_step(c_ip_len);
+            r_staten <= S_UDP;
+            r_state  <= S_PUSH;
+          end if;
+        
+        when S_UDP =>
+          if s_buf_full = '0' then
+            r_shift  <= f_send_udp(r_port, my_port_i, r_length);
+            r_count  <= f_step(c_udp_len);
+            r_staten <= S_DONE;
+            r_state  <= S_PUSH;
+          end if;
+        
+        when S_DONE =>
+          if s_buf_full = '0' then
+            r_ready   <= '0'; -- can latch next header params
+            r_hdr_stb <= '0'; -- nothing more from the header side of things
+            
+            -- After payload, may need to add runt padding
+            r_shift <= (others => '0');
+            
+            if r_length < c_runt_min then
+              r_staten <= S_RUNT;
+              r_count <= f_step(c_runt_min - to_integer(r_length));
+            else
+              r_staten <= S_LOWER;
+              r_count <= (others => '-');
+            end if;
+            
+            -- Make sure we don't skip the payload!
+            if slave_i.cyc = '1' then
+              r_state <= S_PAYLOAD;
+            elsif skip_stb_i = '1' then
+              r_state <= S_SKIP;
+            else
+              r_state <= S_WAIT;
+            end if;
+          end if;
+          
+        when S_WAIT =>
+          if slave_i.cyc = '1' then
+            r_state <= S_PAYLOAD;
+          elsif skip_stb_i = '1' then
+            r_state <= S_SKIP;
+          end if;
+        
+        when S_PAYLOAD =>
+          if slave_i.cyc = '0' then
+            r_hdr_stb <= '1';
+            r_state <= r_staten;
+          end if;
+        
+        when S_RUNT =>
+          if s_buf_full = '0' then
+            r_state   <= S_PUSH;
+            r_staten  <= S_LOWER;
+          end if;
+        
+        when S_LOWER =>
+          if s_buf_full = '0' then
+            r_hdr_stb <= '0';
+            r_state <= S_WRF_STATUS;
+          end if;
+        
+        when S_SKIP =>
+          r_state <= S_WRF_STATUS;
+        
+        when S_PUSH =>
+          if s_buf_full = '0' then
+            r_count <= r_count - 1;
+            r_shift <= r_shift(r_shift'left-16 downto 0) & x"0000";
+            
+            if r_count = to_unsigned(1, r_count'length) then
+              r_state <= r_staten;
+            end if;
+          end if;
+          
+      end case;
+    end if;
+  end process;
+
+  src_o.cyc <= s_tx_cyc when s_tx_empty='0' else r_tx_cyc;
+  src_o.stb <= not s_tx_empty;
+  src_o.adr <= c_WRF_STATUS when s_tx_typ='1' else c_WRF_DATA;
+  src_o.we  <= '1';
+  src_o.sel <= "11";
+  src_o.dat <= s_tx_dat;
+  
+  s_tx_pop <= not s_tx_empty and not (s_tx_cyc and src_i.stall);
+  
+  sum : eb_checksum
+    port map(
+      clk_i => clk_i,
+      nRst_i => rst_n_i,
+      en_i   => r_sum_en,
+      data_i => r_sum_data,
+      done_o => open,
+      sum_o  => s_sum_done);
+  
+  sum_header : process(clk_i, rst_n_i) is
+  begin
+    if rst_n_i = '0' then
+      r_sum_state <= S_CONST;
+      r_sum_en    <= '0';
+      r_sum_data  <= (others => '0');
+    elsif rising_edge(clk_i) then
+    
+      case r_sum_state is
+        when S_CONST =>
+          r_sum_data <= f_checksum(f_format_ip(c_ip_init));
+          if stb_i = '1' and r_ready = '0' then
+            r_sum_en    <= '1';
+            r_sum_state <= S_DST_HI;
+          end if;
+        
+        when S_DST_HI => r_sum_state <= S_DST_LO; r_sum_data <=    r_ip(31 downto 16);
+        when S_DST_LO => r_sum_state <= S_SRC_HI; r_sum_data <=    r_ip(15 downto  0);
+        when S_SRC_HI => r_sum_state <= S_SRC_LO; r_sum_data <= my_ip_i(31 downto 16);
+        when S_SRC_LO => r_sum_state <= S_LENGTH; r_sum_data <= my_ip_i(15 downto  0);
+        when S_LENGTH => r_sum_state <= S_DONE;   r_sum_data <= std_logic_vector(r_length+20);
+        when S_DONE   => r_sum_state <= S_CONST;  r_sum_en <= '0';
+      end case;
+      
+    end if;
+  end process;
+  
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd
new file mode 100644
index 000000000..304333085
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd
@@ -0,0 +1,164 @@
+--! @file eb_ethernet_slave.vhd
+--! @brief Top file for EtherBone core
+--!
+--! Copyright (C) 2011-2012 GSI Helmholtz Centre for Heavy Ion Research GmbH 
+--!
+--! Important details about its implementation
+--! should go in these comments.
+--!
+--! @author Mathias Kreider <m.kreider@gsi.de>
+--! @author Wesley W. Terpstra <w.terpstra@gsi.de>
+--!
+--------------------------------------------------------------------------------
+--! This library is free software; you can redistribute it and/or
+--! modify it under the terms of the GNU Lesser General Public
+--! License as published by the Free Software Foundation; either
+--! version 3 of the License, or (at your option) any later version.
+--!
+--! This library is distributed in the hope that it will be useful,
+--! but WITHOUT ANY WARRANTY; without even the implied warranty of
+--! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+--! Lesser General Public License for more details.
+--!  
+--! You should have received a copy of the GNU Lesser General Public
+--! License along with this library. If not, see <http://www.gnu.org/licenses/>.
+---------------------------------------------------------------------------------
+
+--! Standard library
+library IEEE;
+--! Standard packages    
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+library work;
+use work.etherbone_pkg.all;
+use work.eb_hdr_pkg.all;
+use work.wishbone_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.eb_internals_pkg.all;
+
+entity eb_ethernet_slave is
+  generic(
+    g_sdb_address    : std_logic_vector(63 downto 0);
+    g_timeout_cycles : natural;
+    g_mtu            : natural);
+  port(
+    clk_i       : in  std_logic;
+    nRst_i      : in  std_logic;
+    snk_i       : in  t_wrf_sink_in;
+    snk_o       : out t_wrf_sink_out;
+    src_o       : out t_wrf_source_out;
+    src_i       : in  t_wrf_source_in;
+    cfg_slave_o : out t_wishbone_slave_out;
+    cfg_slave_i : in  t_wishbone_slave_in;
+    master_o    : out t_wishbone_master_out;
+    master_i    : in  t_wishbone_master_in);
+end eb_ethernet_slave;
+
+
+architecture rtl of eb_ethernet_slave is
+  signal s_his_mac,  s_my_mac  : std_logic_vector(47 downto 0);
+  signal s_his_ip,   s_my_ip   : std_logic_vector(31 downto 0);
+  signal s_his_port, s_my_port : std_logic_vector(15 downto 0);
+  
+  signal s_tx_stb     : std_logic;
+  signal s_tx_stall   : std_logic;
+  signal s_skip_stb   : std_logic;
+  signal s_skip_stall : std_logic;
+  signal s_length     : unsigned(15 downto 0); -- of UDP in words
+  
+  signal s_rx2widen   : t_wishbone_master_out;
+  signal s_widen2rx   : t_wishbone_master_in;
+  signal s_widen2fsm  : t_wishbone_master_out;
+  signal s_fsm2widen  : t_wishbone_master_in;
+  signal s_fsm2narrow : t_wishbone_master_out;
+  signal s_narrow2fsm : t_wishbone_master_in;
+  signal s_narrow2tx  : t_wishbone_master_out;
+  signal s_tx2narrow  : t_wishbone_master_in;
+  
+begin
+  rx : eb_eth_rx
+    generic map(
+      g_mtu => g_mtu)
+    port map(
+      clk_i     => clk_i,
+      rst_n_i   => nRst_i,
+      snk_i     => snk_i,
+      snk_o     => snk_o,
+      master_o  => s_rx2widen,
+      master_i  => s_widen2rx,
+      stb_o     => s_tx_stb,
+      stall_i   => s_tx_stall,
+      mac_o     => s_his_mac,
+      ip_o      => s_his_ip,
+      port_o    => s_his_port,
+      length_o  => s_length);
+  
+  widen : eb_stream_widen
+    generic map(
+      g_slave_width  => 16,
+      g_master_width => 32)
+    port map(
+      clk_i    => clk_i,
+      rst_n_i  => nRst_i,
+      slave_i  => s_rx2widen,
+      slave_o  => s_widen2rx,
+      master_i => s_fsm2widen,
+      master_o => s_widen2fsm);
+      
+  eb : eb_slave_top
+    generic map(
+      g_sdb_address    => g_sdb_address(31 downto 0),
+      g_timeout_cycles => g_timeout_cycles)
+    port map(
+      clk_i        => clk_i,
+      nRst_i       => nRst_i,
+      EB_RX_i      => s_widen2fsm,
+      EB_RX_o      => s_fsm2widen,
+      EB_TX_i      => s_narrow2fsm,
+      EB_TX_o      => s_fsm2narrow,
+      skip_stb_o   => s_skip_stb,
+      skip_stall_i => s_skip_stall,
+      WB_config_i  => cfg_slave_i,
+      WB_config_o  => cfg_slave_o,
+      WB_master_i  => master_i,
+      WB_master_o  => master_o,
+      my_mac_o     => s_my_mac,
+      my_ip_o      => s_my_ip,
+      my_port_o    => s_my_port);
+
+  narrow : eb_stream_narrow
+    generic map(
+      g_slave_width  => 32,
+      g_master_width => 16)
+    port map(
+      clk_i    => clk_i,
+      rst_n_i  => nRst_i,
+      slave_i  => s_fsm2narrow,
+      slave_o  => s_narrow2fsm,
+      master_i => s_tx2narrow,
+      master_o => s_narrow2tx);
+
+  tx : eb_eth_tx
+    generic map(
+      g_mtu => g_mtu)
+    port map(
+      clk_i        => clk_i,
+      rst_n_i      => nRst_i,
+      src_i        => src_i,
+      src_o        => src_o,
+      slave_o      => s_tx2narrow,
+      slave_i      => s_narrow2tx,
+      stb_i        => s_tx_stb,
+      stall_o      => s_tx_stall,
+      mac_i        => s_his_mac,
+      ip_i         => s_his_ip,
+      port_i       => s_his_port,
+      length_i     => s_length,
+      skip_stb_i   => s_skip_stb,
+      skip_stall_o => s_skip_stall,
+      my_mac_i     => s_my_mac,
+      my_ip_i      => s_my_ip,
+      my_port_i    => s_my_port);
+  
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd
new file mode 100644
index 000000000..22ac21364
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd
@@ -0,0 +1,112 @@
+------------------------------------------------------------------------------
+-- Title      : Etherbone FIFO
+-- Project    : Etherbone Core
+------------------------------------------------------------------------------
+-- File       : eb_fifo.vhd
+-- Author     : Wesley W. Terpstra
+-- Company    : GSI
+-- Created    : 2013-04-08
+-- Last update: 2013-04-08
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: A convenience wrapper for FIFOs used in Etherbone
+-------------------------------------------------------------------------------
+-- Copyright (c) 2013 GSI
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2013-04-08  1.0      terpstra        Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.wishbone_pkg.all;
+use work.eb_internals_pkg.all;
+use work.genram_pkg.all;
+
+-- r_dat_o is valid when r_empty_o=0 (show ahead)
+-- w_dat_i is valid when w_push_i =1
+-- r_pop_i  affects r_empty_o on the next cycle
+-- w_push_i affects w_full_o  on the next cycle
+entity eb_fifo is
+  generic(
+    g_width : natural;
+    g_size  : natural);
+  port(
+    clk_i     : in  std_logic;
+    rstn_i    : in  std_logic;
+    w_full_o  : out std_logic;
+    w_push_i  : in  std_logic;
+    w_dat_i   : in  std_logic_vector(g_width-1 downto 0);
+    r_empty_o : out std_logic;
+    r_pop_i   : in  std_logic;
+    r_dat_o   : out std_logic_vector(g_width-1 downto 0));
+end eb_fifo;
+
+architecture rtl of eb_fifo is
+  constant c_depth : natural := f_ceil_log2(g_size);
+  
+  signal r_idx  : unsigned(c_depth downto 0);
+  signal w_idx  : unsigned(c_depth downto 0);
+  signal r_idx1 : unsigned(c_depth downto 0);
+  signal w_idx1 : unsigned(c_depth downto 0);
+  
+  constant c_low  : unsigned(c_depth-1 downto 0) := (others => '0');
+  constant c_high : unsigned(c_depth   downto 0) := '1' & c_low;
+  
+begin
+
+  ram : generic_simple_dpram
+    generic map(
+      g_data_width => g_width,
+      g_size       => g_size,
+      g_dual_clock => false)
+    port map(
+      rst_n_i => rstn_i,
+      
+      clka_i  => clk_i,
+      bwea_i  => (others => '1'),
+      wea_i   => w_push_i,
+      aa_i    => std_logic_vector(w_idx(c_depth-1 downto 0)),
+      da_i    => w_dat_i,
+      
+      clkb_i  => clk_i,
+      ab_i    => std_logic_vector(r_idx1(c_depth-1 downto 0)),
+      qb_o    => r_dat_o);
+  
+  r_idx1 <= (r_idx+1) when r_pop_i ='1' else r_idx;
+  w_idx1 <= (w_idx+1) when w_push_i='1' else w_idx;
+  
+  main : process(rstn_i, clk_i) is
+  begin
+    if rstn_i = '0' then
+      r_idx     <= (others => '0');
+      w_idx     <= (others => '0');
+      w_full_o  <= '0';
+      r_empty_o <= '1';
+    elsif rising_edge(clk_i) then
+      r_idx <= r_idx1;
+      w_idx <= w_idx1;
+      
+      -- Compare the newest pointers
+      if (w_idx1 xor c_high) = r_idx1 then
+        w_full_o <= '1';
+      else
+        w_full_o <= '0';
+      end if;
+      
+      -- Use the OLD write pointer to prevent read-during-write
+      if w_idx = r_idx1 then
+        r_empty_o <= '1';
+      else
+        r_empty_o <= '0';
+      end if;
+      
+    end if;
+  end process;
+
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd
new file mode 100644
index 000000000..c7d40aa07
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd
@@ -0,0 +1,271 @@
+--! @file eb_hdr_pkg.vhd
+--! @brief EtherBone Header definitions - Eth, IPV4, UDP, EB
+--!
+--! Copyright (C) 2011-2012 GSI Helmholtz Centre for Heavy Ion Research GmbH 
+--!
+--! Important details about its implementation
+--! should go in these comments.
+--!
+--! @author Mathias Kreider <m.kreider@gsi.de>
+--! @author Wesley W. Terpstra <w.terpstra@gsi.de>
+--!
+--------------------------------------------------------------------------------
+--! This library is free software; you can redistribute it and/or
+--! modify it under the terms of the GNU Lesser General Public
+--! License as published by the Free Software Foundation; either
+--! version 3 of the License, or (at your option) any later version.
+--!
+--! This library is distributed in the hope that it will be useful,
+--! but WITHOUT ANY WARRANTY; without even the implied warranty of
+--! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+--! Lesser General Public License for more details.
+--!  
+--! You should have received a copy of the GNU Lesser General Public
+--! License along with this library. If not, see <http://www.gnu.org/licenses/>.
+---------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+library work;
+use work.wishbone_pkg.all;
+
+package eb_hdr_pkg is
+
+  constant c_eth_typ_ip : std_logic_vector((2*8)-1 downto 0) := x"0800";
+  type t_eth_hdr is record
+    dst : std_logic_vector((6*8)-1 downto 0); 
+    src : std_logic_vector((6*8)-1 downto 0);
+    typ : std_logic_vector((2*8)-1 downto 0);
+  end record;
+  constant c_eth_len : natural := 14;
+  constant c_eth_init : t_eth_hdr := (
+    dst => (others => '0'), -- set!
+    src => (others => '0'), -- set!
+    typ => c_eth_typ_ip);
+  
+  constant c_ip_typ_udp : std_logic_vector(7 downto 0) := x"11";
+  type t_ip_hdr is record
+    ver : std_logic_vector(3 downto 0);
+    ihl : std_logic_vector(3 downto 0);
+    tos : std_logic_vector(7 downto 0);
+    tol : std_logic_vector(15 downto 0);
+    id  : std_logic_vector(15 downto 0);
+    flg : std_logic_vector(2 downto 0);
+    fro : std_logic_vector(12 downto 0);
+    ttl : std_logic_vector(7 downto 0);
+    pro : std_logic_vector(7 downto 0);
+    sum : std_logic_vector(15 downto 0);
+    src : std_logic_vector(31 downto 0);
+    dst : std_logic_vector(31 downto 0);
+  end record;
+  constant c_ip_len : natural := 20;
+  constant c_ip_init : t_ip_hdr := (
+    ver => x"4",
+    ihl => x"5",
+    tos => x"00",
+    tol => (others => '0'),  -- set!
+    id  => (others => '0'),
+    flg => "010", -- don't fragment
+    fro => (others => '0'),
+    ttl => x"3f",
+    pro => c_ip_typ_udp,
+    sum => (others => '0'),  -- set!
+    src => (others => '0'),  -- set!
+    dst => (others => '0')); -- set!
+  
+  type t_udp_hdr is record
+    src : std_logic_vector(15 downto 0);
+    dst : std_logic_vector(15 downto 0);
+    len : std_logic_vector(15 downto 0);
+    sum : std_logic_vector(15 downto 0);
+  end record;
+  constant c_udp_len : natural := 8;
+  constant c_udp_init : t_udp_hdr := (
+    src => (others => '0'),  -- set!
+    dst => (others => '0'),  -- set!
+    len => (others => '0'),  -- set!
+    sum => (others => '0'));
+  
+  constant c_eb_magic : std_logic_vector(15 downto 0) := x"4e6f";
+  constant c_eb_ver   : std_logic_vector(3 downto 0) := x"1";
+  type t_eb_hdr is record
+    magic       : std_logic_vector(15 downto 0);
+    ver         : std_logic_vector(3 downto 0);
+    res1        : std_logic;
+    no_response : std_logic;
+    probe_res   : std_logic;
+    probe       : std_logic;
+    addr_size   : std_logic_vector(3 downto 0);
+    data_size   : std_logic_vector(3 downto 0);
+  end record;
+  constant c_eb_len : natural := 4;
+  constant c_eb_init : t_eb_hdr := (
+    magic       => c_eb_magic,
+    ver         => c_eb_ver,
+    res1        => '0',
+    no_response => '1',
+    probe_res   => '0',
+    probe       => '0',
+    addr_size   => x"4", -- 32-bit only
+    data_size   => x"4");
+  
+  type t_rec_hdr is record
+    bca_cfg  : std_logic;
+    rca_cfg  : std_logic;
+    rd_fifo  : std_logic;
+    res1     : std_logic;
+    drop_cyc : std_logic;
+    wca_cfg  : std_logic;
+    wr_fifo  : std_logic;
+    res2     : std_logic;
+    sel      : std_logic_vector(7 downto 0);
+    wr_cnt   : unsigned(7 downto 0);
+    rd_cnt   : unsigned(7 downto 0);
+  end record;
+  constant c_rec_len : natural := 4;
+  constant c_rec_init : t_rec_hdr := (
+    bca_cfg  => '0',
+    rca_cfg  => '0',
+    rd_fifo  => '0',
+    res1     => '0',
+    drop_cyc => '0',
+    wca_cfg  => '0',
+    wr_fifo  => '0',
+    res2     => '0',
+    sel      => (others => '0'),
+    wr_cnt   => (others => '0'),
+    rd_cnt   => (others => '0'));
+  
+  function f_parse_eth(x : std_logic_vector) return t_eth_hdr;
+  function f_parse_ip (x : std_logic_vector) return t_ip_hdr;
+  function f_parse_udp(x : std_logic_vector) return t_udp_hdr;
+  function f_parse_eb (x : std_logic_vector) return t_eb_hdr;
+  function f_parse_rec(x : std_logic_vector) return t_rec_hdr;
+  
+  function f_format_eth(x : t_eth_hdr) return std_logic_vector; --(c_eth_len*8-1 downto 0);
+  function f_format_ip (x : t_ip_hdr)  return std_logic_vector; --(c_ip_len *8-1 downto 0);
+  function f_format_udp(x : t_udp_hdr) return std_logic_vector; --(c_udp_len*8-1 downto 0);
+  function f_format_eb (x : t_eb_hdr)  return std_logic_vector; --(c_eb_len *8-1 downto 0);
+  function f_format_rec(x : t_rec_hdr) return std_logic_vector; --(c_rec_len*8-1 downto 0);
+  
+  -- To be used only on constants!
+  function f_checksum(x : std_logic_vector) return std_logic_vector;
+  
+end package;
+
+package body eb_hdr_pkg is
+
+  function f_parse_eth(x : std_logic_vector) return t_eth_hdr is
+    variable o : t_eth_hdr;
+  begin
+    o.dst := x(111 downto 64);
+    o.src := x( 63 downto 16);
+    o.typ := x( 15 downto  0);
+    return o;
+  end function;
+   
+  function f_parse_ip(x : std_logic_vector) return t_ip_hdr is
+    variable o : t_ip_hdr;
+  begin
+    o.ver := x(159 downto 156);
+    o.ihl := x(155 downto 152);
+    o.tos := x(151 downto 144);
+    o.tol := x(143 downto 128);
+    o.id  := x(127 downto 112);
+    o.flg := x(111 downto 109);
+    o.fro := x(108 downto 96);
+    o.ttl := x(95 downto 88);
+    o.pro := x(87 downto 80);
+    o.sum := x(79 downto 64);
+    o.src := x(63 downto 32);
+    o.dst := x(31 downto 0);
+    return o;
+  end function;
+   
+  function f_parse_udp(x : std_logic_vector) return t_udp_hdr is
+    variable o : t_udp_hdr;
+  begin
+    o.src := x(63 downto 48);
+    o.dst := x(47 downto 32);
+    o.len := x(31 downto 16);
+    o.sum := x(15 downto  0);
+    return o;
+  end function;
+  
+  function f_parse_eb(x : std_logic_vector) return t_eb_hdr is
+    variable o : t_eb_hdr;
+  begin
+    o.magic       := x(31 downto 16);
+    o.ver         := x(15 downto 12);
+    o.res1        := x(11);
+    o.no_response := x(10);
+    o.probe_res   := x(9);
+    o.probe       := x(8);
+    o.addr_size   := x( 7 downto  4);
+    o.data_size   := x( 3 downto  0);
+    return o;
+  end function;
+   
+  function f_parse_rec(x : std_logic_vector) return t_rec_hdr is
+    variable o : t_rec_hdr;
+  begin
+    o.bca_cfg  := x(31);
+    o.rca_cfg  := x(30);
+    o.rd_fifo  := x(29);
+    o.res1     := x(28);
+    o.drop_cyc := x(27);
+    o.wca_cfg  := x(26);
+    o.wr_fifo  := x(25);
+    o.res2     := x(24);
+    o.sel      := x(23 downto 16);
+    o.wr_cnt   := unsigned(x(15 downto 8));
+    o.rd_cnt   := unsigned(x( 7 downto 0));
+    return o;
+  end function;
+   
+  function f_format_eth(x : t_eth_hdr) return std_logic_vector is
+  begin
+    return x.dst & x.src & x.typ;
+  end function;
+  
+  function f_format_ip (x : t_ip_hdr) return std_logic_vector is
+  begin
+    return x.ver & x.ihl & x.tos & x.tol & x.id  & x.flg &
+           x.fro & x.ttl & x.pro & x.sum & x.src & x.dst;
+  end function;
+  
+  function f_format_udp(x : t_udp_hdr) return std_logic_vector is
+  begin
+    return x.src & x.dst & x.len & x.sum;
+  end function;
+  
+  function f_format_eb (x : t_eb_hdr)  return std_logic_vector is
+  begin
+    return x.magic & x.ver & x.res1 & x.no_response & x.probe_res &
+           x.probe & x.addr_size & x.data_size;
+  end function;
+  
+  function f_format_rec(x : t_rec_hdr) return std_logic_vector is
+  begin
+    return x.bca_cfg  & x.rca_cfg & x.rd_fifo & x.res1 & 
+           x.drop_cyc & x.wca_cfg & x.wr_fifo & x.res2 & 
+           x.sel & std_logic_vector(x.wr_cnt) & std_logic_vector(x.rd_cnt);
+  end function;
+  
+  function f_checksum(x : std_logic_vector) return std_logic_vector is
+    alias y : std_logic_vector((x'length/16)*16-1 downto 0) is x;
+    variable o : unsigned(16 downto 0) := (others => '0');
+  begin
+    for i in y'length/16-1 downto 0 loop
+      o := o + ('0' & unsigned(y(i*16+15 downto i*16)));
+      if o(16) = '1' then
+        o := o + 1;
+        o(16) := '0';
+      end if;
+    end loop;
+    return std_logic_vector(o(15 downto 0));
+  end function;
+  
+end package body;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd
new file mode 100644
index 000000000..27fc5a893
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd
@@ -0,0 +1,418 @@
+library IEEE;
+--! Standard packages
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+--! Additional library
+library work;
+use work.wishbone_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.eb_hdr_pkg.all;
+
+package eb_internals_pkg is 
+
+  subtype t_tag is std_logic_vector(2 downto 0);
+
+  constant c_tag_drop_tx : t_tag := "000";
+  constant c_tag_skip_tx : t_tag := "001";
+  constant c_tag_pass_tx : t_tag := "010";
+  constant c_tag_pass_on : t_tag := "011";
+  constant c_tag_cfg_req : t_tag := "100";
+  constant c_tag_cfg_ign : t_tag := "101";
+  constant c_tag_wbm_req : t_tag := "110";
+  constant c_tag_wbm_ign : t_tag := "111";
+  
+  constant c_queue_depth : natural := 32;
+
+  component eb_slave_top is
+    generic(
+      g_sdb_address    : t_wishbone_address;
+      g_timeout_cycles : natural);
+    port(
+      clk_i       : in std_logic;  --! System Clk
+      nRst_i      : in std_logic;  --! active low sync reset
+
+      EB_RX_i     : in  t_wishbone_slave_in;   --! Streaming wishbone(record) sink from RX transport protocol block
+      EB_RX_o     : out t_wishbone_slave_out;  --! Streaming WB sink flow control to RX transport protocol block
+      EB_TX_i     : in  t_wishbone_master_in;  --! Streaming WB src flow control from TX transport protocol block
+      EB_TX_o     : out t_wishbone_master_out; --! Streaming WB src to TX transport protocol block
+      
+      skip_stb_o  : out std_logic; --! Does a packet get discarded?
+      skip_stall_i: in  std_logic;
+
+      WB_config_i : in  t_wishbone_slave_in;    --! WB V4 interface to WB interconnect/device(s)
+      WB_config_o : out t_wishbone_slave_out;   --! WB V4 interface to WB interconnect/device(s)
+      WB_master_i : in  t_wishbone_master_in;   --! WB V4 interface to WB interconnect/device(s)
+      WB_master_o : out t_wishbone_master_out;  --! WB V4 interface to WB interconnect/device(s)
+      
+      my_mac_o    : out std_logic_vector(47 downto 0);
+      my_ip_o     : out std_logic_vector(31 downto 0);
+      my_port_o   : out std_logic_vector(15 downto 0));
+  end component;
+
+  component eb_slave_fsm is
+    port(
+      clk_i       : in  std_logic;
+      rstn_i      : in  std_logic;
+      
+      rx_cyc_i    : in  std_logic;
+      rx_stb_i    : in  std_logic;
+      rx_dat_i    : in  t_wishbone_data;
+      rx_stall_o  : out std_logic;
+      
+      tag_stb_o   : out std_logic;
+      tag_dat_o   : out t_tag;
+      tag_full_i  : in  std_logic;
+      
+      pass_stb_o  : out std_logic;
+      pass_dat_o  : out t_wishbone_data;
+      pass_full_i : in  std_logic;
+      
+      cfg_stb_o   : out std_logic;
+      cfg_adr_o   : out t_wishbone_address;
+      cfg_full_i  : in  std_logic;
+      
+      wbm_stb_o   : out std_logic;
+      wbm_full_i  : in  std_logic;
+      wbm_busy_i  : in  std_logic;
+      
+      master_o       : out t_wishbone_master_out;
+      master_stall_i : in  std_logic);
+  end component;
+
+  component eb_fifo is
+    generic(
+      g_width : natural;
+      g_size  : natural);
+    port(
+      clk_i     : in  std_logic;
+      rstn_i    : in  std_logic;
+      w_full_o  : out std_logic;
+      w_push_i  : in  std_logic;
+      w_dat_i   : in  std_logic_vector(g_width-1 downto 0);
+      r_empty_o : out std_logic;
+      r_pop_i   : in  std_logic;
+      r_dat_o   : out std_logic_vector(g_width-1 downto 0));
+  end component;
+
+  component eb_commit_fifo is
+    generic(
+      g_width : natural;
+      g_size  : natural);
+    port(
+      clk_i      : in  std_logic;
+      rstn_i     : in  std_logic;
+      w_full_o   : out std_logic;
+      w_push_i   : in  std_logic;
+      w_dat_i    : in  std_logic_vector(g_width-1 downto 0);
+      w_commit_i : in  std_logic;
+      w_abort_i  : in  std_logic;
+      r_empty_o  : out std_logic;
+      r_pop_i    : in  std_logic;
+      r_dat_o    : out std_logic_vector(g_width-1 downto 0));
+  end component;
+  
+  component eb_tx_mux is
+    port(
+      clk_i       : in  std_logic;
+      rstn_i      : in  std_logic;
+      
+      tag_pop_o   : out std_logic;
+      tag_dat_i   : in  t_tag;
+      tag_empty_i : in  std_logic;
+      
+      pass_pop_o   : out std_logic;
+      pass_dat_i   : in  t_wishbone_data;
+      pass_empty_i : in  std_logic;
+      
+      cfg_pop_o    : out std_logic;
+      cfg_dat_i    : in  t_wishbone_data;
+      cfg_empty_i  : in  std_logic;
+      
+      wbm_pop_o    : out std_logic;
+      wbm_dat_i    : in  t_wishbone_data;
+      wbm_empty_i  : in  std_logic;
+      
+      skip_stb_o   : out std_logic;
+      skip_stall_i : in  std_logic;
+      
+      tx_cyc_o     : out std_logic;
+      tx_stb_o     : out std_logic;
+      tx_dat_o     : out t_wishbone_data;
+      tx_stall_i   : in  std_logic);
+  end component;
+
+  component eb_tag_fifo is
+    port(
+      clk_i       : in  std_logic;
+      rstn_i      : in  std_logic;
+      
+      fsm_stb_i   : in  std_logic;
+      fsm_dat_i   : in  t_tag;
+      fsm_full_o  : out std_logic;
+
+      mux_pop_i   : in  std_logic;
+      mux_dat_o   : out t_tag;
+      mux_empty_o : out std_logic);
+  end component;
+
+  component eb_pass_fifo is
+    port(
+      clk_i       : in  std_logic;
+      rstn_i      : in  std_logic;
+      
+      fsm_stb_i   : in  std_logic;
+      fsm_dat_i   : in  t_wishbone_data;
+      fsm_full_o  : out std_logic;
+
+      mux_pop_i   : in  std_logic;
+      mux_dat_o   : out t_wishbone_data;
+      mux_empty_o : out std_logic);
+  end component;
+
+  component eb_cfg_fifo is
+    generic(
+      g_sdb_address : t_wishbone_address);
+    port(
+      clk_i       : in  std_logic;
+      rstn_i      : in  std_logic;
+      
+      errreg_i    : in  std_logic_vector(63 downto 0);
+      
+      cfg_i       : in  t_wishbone_slave_in;
+      cfg_o       : out t_wishbone_slave_out;
+      
+      fsm_stb_i   : in  std_logic;
+      fsm_adr_i   : in  t_wishbone_address;
+      fsm_full_o  : out std_logic;
+
+      mux_pop_i   : in  std_logic;
+      mux_dat_o   : out t_wishbone_data;
+      mux_empty_o : out std_logic;
+      
+      my_mac_o    : out std_logic_vector(47 downto 0);
+      my_ip_o     : out std_logic_vector(31 downto 0);
+      my_port_o   : out std_logic_vector(15 downto 0));
+  end component;
+
+  component eb_wbm_fifo is
+    generic(
+      g_timeout_cycles : natural);
+    port(
+      clk_i       : in  std_logic;
+      rstn_i      : in  std_logic;
+      
+      errreg_o    : out std_logic_vector(63 downto 0);
+      wb_i        : in  t_wishbone_master_in;
+      
+      fsm_stb_i   : in  std_logic;
+      fsm_full_o  : out std_logic;
+      fsm_busy_o  : out std_logic;
+
+      mux_pop_i   : in  std_logic;
+      mux_dat_o   : out t_wishbone_data;
+      mux_empty_o : out std_logic);
+  end component;
+  
+  component eb_stream_narrow is
+    generic(
+      g_slave_width  : natural;
+      g_master_width : natural);
+    port(
+      clk_i    : in  std_logic;
+      rst_n_i  : in  std_logic;
+      slave_i  : in  t_wishbone_slave_in;
+      slave_o  : out t_wishbone_slave_out;
+      master_i : in  t_wishbone_master_in;
+      master_o : out t_wishbone_master_out);
+  end component;
+
+  component eb_stream_widen is
+    generic(
+      g_slave_width  : natural;
+      g_master_width : natural);
+    port(
+      clk_i    : in  std_logic;
+      rst_n_i  : in  std_logic;
+      slave_i  : in  t_wishbone_slave_in;
+      slave_o  : out t_wishbone_slave_out;
+      master_i : in  t_wishbone_master_in;
+      master_o : out t_wishbone_master_out);
+  end component;
+  
+  component eb_checksum is
+    port(
+      clk_i  : in  std_logic;
+      nRst_i : in  std_logic;
+      en_i   : in  std_logic; 
+      data_i : in  std_logic_vector(15 downto 0);
+      done_o : out std_logic;
+      sum_o  : out std_logic_vector(15 downto 0));
+  end component;
+  
+  component eb_eth_rx is
+    generic(
+      g_mtu : natural);
+    port(
+      clk_i     : in  std_logic;
+      rst_n_i   : in  std_logic;
+      snk_i     : in  t_wrf_sink_in;
+      snk_o     : out t_wrf_sink_out;
+      master_o  : out t_wishbone_master_out;
+      master_i  : in  t_wishbone_master_in;
+      stb_o     : out std_logic;
+      stall_i   : in  std_logic;
+      mac_o     : out std_logic_vector(47 downto 0);
+      ip_o      : out std_logic_vector(31 downto 0);
+      port_o    : out std_logic_vector(15 downto 0);
+      length_o  : out unsigned(15 downto 0));
+  end component;
+  
+  component eb_eth_tx is
+    generic(
+      g_mtu : natural);
+    port(
+      clk_i        : in  std_logic;
+      rst_n_i      : in  std_logic;
+      src_i        : in  t_wrf_source_in;
+      src_o        : out t_wrf_source_out;
+      slave_o      : out t_wishbone_slave_out;
+      slave_i      : in  t_wishbone_slave_in;
+      stb_i        : in  std_logic;
+      stall_o      : out std_logic;
+      mac_i        : in  std_logic_vector(47 downto 0);
+      ip_i         : in  std_logic_vector(31 downto 0);
+      port_i       : in  std_logic_vector(15 downto 0);
+      length_i     : in  unsigned(15 downto 0);
+      skip_stb_i   : in  std_logic;
+      skip_stall_o : out std_logic;
+      my_mac_i     : in  std_logic_vector(47 downto 0);
+      my_ip_i      : in  std_logic_vector(31 downto 0);
+      my_port_i    : in  std_logic_vector(15 downto 0));
+  end component;
+
+----------------------------------------------------------------- 
+-- EB Master Stuff
+----------------------------------------------------------------- 
+ 
+
+ 
+   component eb_master_wb_if is
+    generic(g_adr_bits_hi : natural;
+      g_mtu         : natural);
+    port(
+      clk_i       : in  std_logic;
+      rst_n_i     : in  std_logic;
+      
+      slave_i     : in  t_wishbone_slave_in;
+      slave_o     : out t_wishbone_slave_out;
+      
+      byte_cnt_i  : in std_logic_vector(15 downto 0);
+      error_i     : in std_logic_vector(0 downto 0);
+      
+      
+      clear_o     : out std_logic;
+      flush_o     : out std_logic;
+      
+      my_mac_o    : out std_logic_vector(47 downto 0);
+      my_ip_o     : out std_logic_vector(31 downto 0);
+      my_port_o   : out std_logic_vector(15 downto 0);
+      
+      his_mac_o   : out std_logic_vector(47 downto 0); 
+      his_ip_o    : out std_logic_vector(31 downto 0);
+      his_port_o  : out std_logic_vector(15 downto 0); 
+      length_o    : out unsigned(15 downto 0);
+      max_ops_o   : out unsigned(15 downto 0);
+      adr_hi_o    : out std_logic_vector(g_adr_bits_hi-1 downto 0);
+      eb_opt_o    : out t_rec_hdr;
+      
+      udp_raw_o   : out std_logic;
+      udp_we_o    : out std_logic;
+      udp_valid_i : in  std_logic;   
+      udp_data_o  : out std_logic_vector(31 downto 0));
+   end component;
+  
+  
+   component eb_framer is
+   port(
+    clk_i           : in   std_logic;            -- WB Clock
+    rst_n_i         : in   std_logic;            -- async reset
+
+    slave_i         : in   t_wishbone_slave_in;  -- WB op. -> not WB compliant, but the record format is convenient
+    slave_o         : out  t_wishbone_slave_out;  -- flow control    
+    master_o        : out  t_wishbone_master_out;
+    master_i        : in   t_wishbone_master_in; 
+    
+    byte_cnt_o      : out  std_logic_vector(15 downto 0);
+    ovf_o           : out  std_logic;
+       
+    tx_send_now_i   : in   std_logic;
+    tx_flush_o      : out  std_logic; 
+    max_ops_i       : in   unsigned(15 downto 0);
+    length_i        : in   unsigned(15 downto 0); 
+    cfg_rec_hdr_i   : in   t_rec_hdr -- EB cfg information, eg read from cfg space etc
+   );    
+   end component;
+  
+   component eb_record_gen is
+   port(
+      clk_i           : in  std_logic;            
+      rst_n_i         : in  std_logic;            
+
+      slave_i         : in  t_wishbone_slave_in;  
+      slave_stall_o   : out std_logic;              
+      slave_ack_o     : out std_logic;
+      
+      rec_valid_o     : out std_logic;            
+      rec_hdr_o       : out t_rec_hdr;          
+      rec_adr_rd_o    : out t_wishbone_data; 
+      rec_adr_wr_o    : out t_wishbone_address; 
+      rec_ack_i       : in std_logic;             
+      byte_cnt_o    : out unsigned(15 downto 0); 
+      cfg_rec_hdr_i   : in t_rec_hdr);   
+   end component ;
+  
+  component eb_master_eth_tx is
+  generic(
+    g_mtu : natural);
+  port(
+    clk_i        : in  std_logic;
+    rst_n_i      : in  std_logic;
+    src_i        : in  t_wrf_source_in;
+    src_o        : out t_wrf_source_out;
+    slave_o      : out t_wishbone_slave_out;
+    slave_i      : in  t_wishbone_slave_in;
+    stb_i        : in  std_logic;
+    stall_o      : out std_logic;
+    mac_i        : in  std_logic_vector(47 downto 0);
+    ip_i         : in  std_logic_vector(31 downto 0);
+    port_i       : in  std_logic_vector(15 downto 0);
+    skip_stb_i   : in  std_logic;
+    skip_stall_o : out std_logic;
+    my_mac_i     : in  std_logic_vector(47 downto 0);
+    my_ip_i      : in  std_logic_vector(31 downto 0);
+    my_port_i    : in  std_logic_vector(15 downto 0)
+    );
+   end component;
+   
+   component eb_commit_len_fifo is
+  generic(
+    g_width : natural;
+    g_size  : natural);
+  port(
+    clk_i      : in  std_logic;
+    rstn_i     : in  std_logic;
+    w_cnt_o    : out unsigned(f_ceil_log2(g_size) downto 0);
+    r_cnt_o    : out unsigned(f_ceil_log2(g_size) downto 0);
+    w_full_o   : out std_logic;
+    w_push_i   : in  std_logic;
+    w_dat_i    : in  std_logic_vector(g_width-1 downto 0);
+    w_commit_i : in  std_logic;
+    w_abort_i  : in  std_logic;
+    r_empty_o  : out std_logic;
+    r_pop_i    : in  std_logic;
+    r_dat_o    : out std_logic_vector(g_width-1 downto 0)
+    );
+   end component;
+  
+end package;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd
new file mode 100644
index 000000000..df04798ff
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd
@@ -0,0 +1,61 @@
+------------------------------------------------------------------------------
+-- Title      : Etherbone Pass FIFO
+-- Project    : Etherbone Core
+------------------------------------------------------------------------------
+-- File       : eb_pass_fifo.vhd
+-- Author     : Wesley W. Terpstra
+-- Company    : GSI
+-- Created    : 2013-04-08
+-- Last update: 2013-04-08
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Records protocol data that should be put into response
+-------------------------------------------------------------------------------
+-- Copyright (c) 2013 GSI
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2013-04-08  1.0      terpstra        Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.wishbone_pkg.all;
+use work.eb_internals_pkg.all;
+
+entity eb_pass_fifo is
+  port(
+    clk_i       : in  std_logic;
+    rstn_i      : in  std_logic;
+    
+    fsm_stb_i   : in  std_logic;
+    fsm_dat_i   : in  t_wishbone_data;
+    fsm_full_o  : out std_logic;
+
+    mux_pop_i   : in  std_logic;
+    mux_dat_o   : out t_wishbone_data;
+    mux_empty_o : out std_logic);
+end eb_pass_fifo;
+
+architecture rtl of eb_pass_fifo is
+begin
+
+  fifo : eb_fifo
+    generic map(
+      g_width => c_wishbone_data_width,
+      g_size  => c_queue_depth)
+    port map(
+      clk_i     => clk_i,
+      rstn_i    => rstn_i,
+      w_full_o  => fsm_full_o,
+      w_push_i  => fsm_stb_i,
+      w_dat_i   => fsm_dat_i,
+      r_empty_o => mux_empty_o,
+      r_pop_i   => mux_pop_i,
+      r_dat_o   => mux_dat_o);
+      
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd
new file mode 100644
index 000000000..9eb991a7c
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd
@@ -0,0 +1,353 @@
+library IEEE;
+--! Standard packages
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+--! Additional library
+library work;
+--! Additional packages
+use work.eb_internals_pkg.all;
+use work.eb_hdr_pkg.all;
+use work.wishbone_pkg.all;
+
+entity eb_slave_fsm is
+  port(
+    clk_i       : in  std_logic;
+    rstn_i      : in  std_logic;
+    
+    rx_cyc_i    : in  std_logic;
+    rx_stb_i    : in  std_logic;
+    rx_dat_i    : in  t_wishbone_data;
+    rx_stall_o  : out std_logic;
+    
+    tag_stb_o   : out std_logic;
+    tag_dat_o   : out t_tag;
+    tag_full_i  : in  std_logic;
+    
+    pass_stb_o  : out std_logic;
+    pass_dat_o  : out t_wishbone_data;
+    pass_full_i : in  std_logic;
+    
+    cfg_stb_o   : out std_logic;
+    cfg_adr_o   : out t_wishbone_address;
+    cfg_full_i  : in  std_logic;
+    
+    wbm_stb_o   : out std_logic;
+    wbm_full_i  : in  std_logic;
+    wbm_busy_i  : in  std_logic;
+    
+    master_o       : out t_wishbone_master_out;
+    master_stall_i : in  std_logic);
+    
+end entity;
+
+architecture behavioral of eb_slave_fsm is
+
+  type t_state_RX is (S_EB_HDR, S_PROBE_DROP, S_PROBE_ID, S_CYC_HDR, S_WR_ADR, S_WRITE, S_RD_ADR, S_READ, S_DROP);
+  
+  signal r_tag_stb_o    : std_logic;
+  signal r_tag_dat_o    : t_tag;
+  signal r_pass_stb_o   : std_logic;
+  signal r_pass_dat_o   : t_wishbone_data;
+  signal r_cfg_stb_o    : std_logic;
+  signal r_wbm_stb_o    : std_logic;
+  signal r_master_cyc_o : std_logic;
+  signal r_master_stb_o : std_logic;
+  signal r_master_we_o  : std_logic;
+  signal r_master_adr_o : t_wishbone_address;
+  signal r_master_dat_o : t_wishbone_data;
+  signal r_wr_adr       : unsigned(t_wishbone_address'range);
+  signal r_rx_rec_hdr   : t_rec_hdr;
+  signal r_tx_rec_hdr   : t_rec_hdr;
+  signal r_rx_cyc       : std_logic;
+  signal r_state        : t_state_RX;
+  signal s_stall        : std_logic;
+  signal s_wbm_busy     : std_logic;
+  signal s_rx_eb_hdr    : t_eb_hdr;
+  signal s_tx_eb_hdr    : t_eb_hdr;
+  signal s_rx_rec_hdr   : t_rec_hdr;
+  signal s_tx_rec_hdr   : t_rec_hdr;
+  
+  function f_reply_eb(rx_eb_hdr : t_eb_hdr) return t_eb_hdr is
+    variable tx_eb_hdr : t_eb_hdr := c_eb_init;
+  begin
+    tx_eb_hdr.probe_res := rx_eb_hdr.probe;
+    return tx_eb_hdr;
+  end function;
+
+  function f_reply_rec(rx_rec_hdr : t_rec_hdr) return t_rec_hdr is
+    variable tx_rec_hdr : t_rec_hdr := C_rec_init;
+  begin
+    tx_rec_hdr.WCA_CFG  := rx_rec_hdr.BCA_CFG;
+    tx_rec_hdr.RD_FIFO  := '0';
+    tx_rec_hdr.RD_CNT   := (others => '0');
+    tx_rec_hdr.WR_FIFO  := rx_rec_hdr.RD_FIFO;
+    tx_rec_hdr.WR_CNT   := rx_rec_hdr.RD_CNT;
+    tx_rec_hdr.SEL      := rx_rec_hdr.SEL;
+    tx_rec_hdr.DROP_CYC := rx_rec_hdr.DROP_CYC;
+    return tx_rec_hdr;
+  end function;
+
+begin
+              
+  rx_stall_o <= s_stall;
+  tag_stb_o  <= r_tag_stb_o;
+  tag_dat_o  <= r_tag_dat_o;
+  pass_stb_o <= r_pass_stb_o;
+  pass_dat_o <= r_pass_dat_o;
+  cfg_stb_o  <= r_cfg_stb_o;
+  cfg_adr_o  <= r_master_adr_o;
+  wbm_stb_o  <= r_wbm_stb_o;
+  
+  s_wbm_busy   <= wbm_busy_i or r_wbm_stb_o; -- cope with 1 cycle latency
+  master_o.cyc <= r_master_cyc_o or s_wbm_busy;
+  master_o.stb <= r_master_stb_o;
+  master_o.we  <= r_master_we_o;
+  master_o.adr <= r_master_adr_o;
+  master_o.dat <= r_master_dat_o;
+  master_o.sel <= r_rx_rec_hdr.sel(master_o.sel'range);
+  
+  -- Stall the RX path if:
+  --   Any TX FIFO is full
+  --   We are pushing a strobe that is stalled
+  --   We are waiting to lower the cycle line
+  s_stall <= tag_full_i OR pass_full_i OR cfg_full_i OR wbm_full_i OR 
+             (r_master_stb_o and master_stall_i) OR
+             (not r_master_cyc_o and s_wbm_busy);
+  
+  s_rx_eb_hdr <= f_parse_eb(rx_dat_i);
+  s_tx_eb_hdr <= f_reply_eb(s_rx_eb_hdr);
+  
+  s_rx_rec_hdr <= f_parse_rec(rx_dat_i);
+  s_tx_rec_hdr <= f_reply_rec(s_rx_rec_hdr);
+  
+  fsm : process(clk_i, rstn_i) is
+  begin
+    if (rstn_i = '0') then
+      r_tag_stb_o    <= '0';
+      r_tag_dat_o    <= (others => '0');
+      r_pass_stb_o   <= '0';
+      r_pass_dat_o   <= (others => '0');
+      r_cfg_stb_o    <= '0';
+      r_wbm_stb_o    <= '0';
+      r_master_cyc_o <= '0';
+      r_master_stb_o <= '0';
+      r_master_we_o  <= '0';
+      r_master_adr_o <= (others => '0');
+      r_master_dat_o <= (others => '0');
+      r_wr_adr       <= (others => '0');
+      r_rx_rec_hdr   <= c_rec_init;
+      r_tx_rec_hdr   <= c_rec_init;
+      r_rx_cyc       <= '0';
+      r_state        <= S_EB_HDR;
+    elsif rising_edge(clk_i) then
+    
+      -- By default, write nowhere in particular
+      r_tag_stb_o  <= '0';
+      r_pass_stb_o <= '0';
+      r_cfg_stb_o  <= '0';
+      r_wbm_stb_o  <= '0';
+      
+      -- Lower strobe line when it is queued
+      r_master_stb_o <= r_master_stb_o and master_stall_i;
+      
+      -- Register to enable detecting falling edge
+      r_rx_cyc <= rx_cyc_i;
+      
+      if(rx_cyc_i = '0') then
+        -- expect a new negotiation header
+        r_state <= S_EB_HDR; 
+        -- guard against improperly terminated streams
+        r_master_cyc_o <= '0'; 
+        
+        -- On falling edge of RX cycle line, push a tag to drop TX cycle
+        if r_rx_cyc = '1' then
+          r_tag_stb_o <= '1';
+          r_tag_dat_o <= c_tag_drop_tx;
+        end if;
+      elsif(rx_stb_i = '1' and s_stall = '0') then
+        -- Every non-error state must write something
+        
+        case r_state is
+          when s_EB_HDR =>
+            -- supported EB header?
+            if (s_rx_eb_hdr.magic = c_eb_magic and s_rx_eb_hdr.ver = c_eb_ver) then
+              -- Raise TX cycle line if this needs to be sent
+              if s_rx_eb_hdr.no_response = '1' then
+                r_tag_stb_o  <= '1';
+                r_tag_dat_o  <= c_tag_skip_tx;
+              else
+                -- Write the header using pass fifo
+                r_tag_stb_o  <= '1';
+                r_tag_dat_o  <= c_tag_pass_tx;
+                r_pass_stb_o <= '1';
+                r_pass_dat_o <= f_format_eb(s_tx_eb_hdr);
+              end if;
+              
+              if s_rx_eb_hdr.probe = '1' then
+                if s_rx_eb_hdr.addr_size(2) = '1' and
+                   s_rx_eb_hdr.data_size(2) = '1' then
+                  -- Allow follow-up payload for stream channels
+                  r_state <= S_PROBE_ID; 
+                else
+                  -- Does not support 32-bit? drop anything after probe id
+                  r_state <= S_PROBE_DROP;
+                end if;  
+              else -- not a probe
+                if s_rx_eb_hdr.addr_size = x"4" or
+                   s_rx_eb_hdr.data_size = x"4" then
+                  -- Must be the exactly right format if not a probe!
+                  r_state <= S_CYC_HDR;
+                else
+                  -- Do the best we can ... report proper EB header and pad with 0s
+                  r_state <= S_DROP;
+                end if;  
+              end if;
+            else  --bad eb header. drop all til cycle line is lowered again
+              r_tag_stb_o <= '1';
+              r_tag_dat_o <= c_tag_skip_tx;
+              r_state     <= S_DROP;
+            end if;
+          
+          when S_PROBE_DROP =>
+            -- Write the probe-id using pass fifo
+            r_tag_stb_o  <= '1';
+            r_tag_dat_o  <= c_tag_pass_on;
+            r_pass_stb_o <= '1';
+            r_pass_dat_o <= rx_dat_i;
+            
+            r_state <= s_DROP;
+          
+          when S_PROBE_ID =>
+            -- Write the probe-id using pass fifo
+            r_tag_stb_o  <= '1';
+            r_tag_dat_o  <= c_tag_pass_on;
+            r_pass_stb_o <= '1';
+            r_pass_dat_o <= rx_dat_i;
+            
+            r_state <= s_CYC_HDR;
+          
+          when S_CYC_HDR  =>
+            r_tx_rec_hdr  <= s_tx_rec_hdr;
+            r_rx_rec_hdr  <= s_rx_rec_hdr;
+            
+            -- Write padding/header using pass fifo
+            r_tag_stb_o  <= '1';
+            r_tag_dat_o  <= c_tag_pass_on;
+            r_pass_stb_o <= '1';
+            
+            if (s_rx_rec_hdr.WR_CNT /= 0) then
+              --padding logic 1. insert padding instead of the header                                  
+              r_pass_dat_o <= x"00000000";
+              r_state <= S_WR_ADR;  
+            elsif (s_rx_rec_hdr.RD_CNT /= 0) then
+              --no writes, no padding. insert the header
+              r_pass_dat_o <= f_format_rec(s_tx_rec_hdr);
+              r_state <= S_RD_ADR;
+            else
+              --no writes, no padding. insert the header 
+              r_pass_dat_o <= f_format_rec(s_tx_rec_hdr);
+              
+              r_master_cyc_o <= r_master_cyc_o and not s_rx_rec_hdr.DROP_CYC;
+              r_state <= S_CYC_HDR;
+            end if;
+            
+          when S_WR_ADR =>
+            r_wr_adr <= unsigned(rx_dat_i);
+            
+            -- Write padding using pass fifo
+            r_tag_stb_o  <= '1';
+            r_tag_dat_o  <= c_tag_pass_on;
+            r_pass_stb_o <= '1';
+            r_pass_dat_o <= x"00000000";
+            
+            r_state <= S_WRITE;
+          
+          when S_WRITE =>
+            r_master_we_o  <= '1';
+            r_master_adr_o <= std_logic_vector(r_wr_adr);
+            r_master_dat_o <= rx_dat_i;
+            
+            if(r_rx_rec_hdr.WR_FIFO = '0') then
+              r_wr_adr <= r_wr_adr + 4;
+            end if;
+            
+            -- Write padding/header using pass fifo
+            r_tag_stb_o  <= '1';
+            r_pass_stb_o <= '1';
+            
+            -- Writes need their output discarded
+            if r_rx_rec_hdr.WCA_CFG = '1' then
+              r_cfg_stb_o    <= '1';
+              r_tag_dat_o    <= c_tag_cfg_ign;
+            else
+              r_wbm_stb_o    <= '1';
+              r_tag_dat_o    <= c_tag_wbm_ign;
+              r_master_cyc_o <= '1';
+              r_master_stb_o <= '1';
+            end if;
+            
+            if (r_rx_rec_hdr.WR_CNT /= 1) then
+              r_pass_dat_o <= x"00000000";
+            else
+              r_pass_dat_o <= f_format_rec(r_tx_rec_hdr);
+              
+              if (r_rx_rec_hdr.RD_CNT /= 0) then
+                r_state <= S_RD_ADR;
+              else
+                r_master_cyc_o <= r_master_cyc_o and not r_rx_rec_hdr.DROP_CYC;  
+                r_state <= S_CYC_HDR;
+              end if;
+            end if;
+            
+            r_rx_rec_hdr.WR_CNT <= r_rx_rec_hdr.WR_CNT - 1;
+              
+          when S_RD_ADR =>
+            -- Copy address using pass fifo
+            r_tag_stb_o  <= '1';
+            r_tag_dat_o  <= c_tag_pass_on;
+            r_pass_stb_o <= '1';
+            r_pass_dat_o <= rx_dat_i; --pass the rx readback address as base write address to tx
+            
+            r_state <= S_READ;
+            
+          when S_READ =>
+            r_master_we_o  <= '0';
+            r_master_adr_o <= rx_dat_i;
+            
+            -- Get data from either cfg or wbm fifos
+            r_tag_stb_o <= '1';
+            
+            if r_rx_rec_hdr.RCA_CFG = '1' then
+              r_cfg_stb_o <= '1';
+              r_tag_dat_o <= c_tag_cfg_req;
+            else
+              r_wbm_stb_o <= '1';
+              r_tag_dat_o <= c_tag_wbm_req;
+              r_master_cyc_o <= '1';
+              r_master_stb_o <= '1';
+            end if;
+            
+            if(r_rx_rec_hdr.RD_CNT = 1) then
+              r_master_cyc_o <= r_master_cyc_o and not r_rx_rec_hdr.DROP_CYC;  
+              r_state <= S_CYC_HDR;
+            end if;
+            
+            r_rx_rec_hdr.RD_CNT <= r_rx_rec_hdr.RD_CNT - 1;
+            
+          when S_DROP =>
+            -- preserve packet length
+            r_tag_stb_o  <= '1';
+            r_tag_dat_o  <= c_tag_pass_on;
+            r_pass_stb_o <= '1';
+            r_pass_dat_o <= (others => '0');
+
+          when others =>
+            r_state <= S_DROP;
+        
+        end case;
+      end if; --rx_stb_i
+    end if; --clk edge  
+  end process;
+
+end architecture;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd
new file mode 100644
index 000000000..4003d37b5
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd
@@ -0,0 +1,205 @@
+------------------------------------------------------------------------------
+-- Title      : Etherbone Slave
+-- Project    : Etherbone Core
+------------------------------------------------------------------------------
+-- File       : eb_slave.vhd
+-- Author     : Wesley W. Terpstra
+-- Company    : GSI
+-- Created    : 2013-04-08
+-- Last update: 2013-04-08
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Connect all the components of an Etherbone slave
+-------------------------------------------------------------------------------
+-- Copyright (c) 2013 GSI
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2013-04-08  1.0      terpstra        Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.wishbone_pkg.all;
+use work.eb_internals_pkg.all;
+
+entity eb_slave_top is
+  generic(
+    g_sdb_address    : t_wishbone_address;
+    g_timeout_cycles : natural);
+  port(
+    clk_i       : in std_logic;  --! System Clk
+    nRst_i      : in std_logic;  --! active low sync reset
+
+    EB_RX_i     : in  t_wishbone_slave_in;   --! Streaming wishbone(record) sink from RX transport protocol block
+    EB_RX_o     : out t_wishbone_slave_out;  --! Streaming WB sink flow control to RX transport protocol block
+    EB_TX_i     : in  t_wishbone_master_in;  --! Streaming WB src flow control from TX transport protocol block
+    EB_TX_o     : out t_wishbone_master_out; --! Streaming WB src to TX transport protocol block
+    
+    skip_stb_o  : out std_logic; --! Does a packet get discarded?
+    skip_stall_i: in  std_logic;
+
+    WB_config_i : in  t_wishbone_slave_in;    --! WB V4 interface to WB interconnect/device(s)
+    WB_config_o : out t_wishbone_slave_out;   --! WB V4 interface to WB interconnect/device(s)
+    WB_master_i : in  t_wishbone_master_in;   --! WB V4 interface to WB interconnect/device(s)
+    WB_master_o : out t_wishbone_master_out;  --! WB V4 interface to WB interconnect/device(s)
+    
+    my_mac_o    : out std_logic_vector(47 downto 0);
+    my_ip_o     : out std_logic_vector(31 downto 0);
+    my_port_o   : out std_logic_vector(15 downto 0));
+end eb_slave_top;
+
+architecture rtl of eb_slave_top is
+  signal rstn_i : std_logic;
+  
+  signal errreg         : std_logic_vector(63 downto 0);
+  signal rx_stall       : std_logic;
+  
+  signal fsm_tag_stb    : std_logic;
+  signal fsm_tag_dat    : t_tag;
+  signal tag_fsm_full   : std_logic;
+  signal fsm_pass_stb   : std_logic;
+  signal fsm_pass_dat   : t_wishbone_data;
+  signal pass_fsm_full  : std_logic;
+  signal fsm_cfg_stb    : std_logic;
+  signal fsm_cfg_adr    : t_wishbone_address;
+  signal cfg_fsm_full   : std_logic;
+  signal fsm_wbm_stb    : std_logic;
+  signal wbm_fsm_full   : std_logic;
+  signal wbm_fsm_busy   : std_logic;
+  
+  signal mux_tag_pop    : std_logic;
+  signal tag_mux_dat    : t_tag;
+  signal tag_mux_empty  : std_logic;
+  signal mux_pass_pop   : std_logic;
+  signal pass_mux_dat   : t_wishbone_data;
+  signal pass_mux_empty : std_logic;
+  signal mux_cfg_pop    : std_logic;
+  signal cfg_mux_dat    : t_wishbone_data;
+  signal cfg_mux_empty  : std_logic;
+  signal mux_wbm_pop    : std_logic;
+  signal wbm_mux_dat    : t_wishbone_data;
+  signal wbm_mux_empty  : std_logic;
+  
+begin
+
+  rstn_i <= nRst_i;
+  
+  EB_RX_o.ack <= EB_RX_i.cyc and EB_RX_i.stb and not rx_stall;
+  EB_RX_o.err <= '0';
+  EB_RX_o.rty <= '0';
+  EB_RX_o.int <= '0';
+  EB_RX_o.stall <= rx_stall;
+  EB_RX_o.dat <= (others => '0');
+  
+  fsm : eb_slave_fsm 
+    port map(
+      clk_i       => clk_i,
+      rstn_i      => rstn_i,
+      rx_cyc_i    => EB_RX_i.cyc,
+      rx_stb_i    => EB_RX_i.stb,
+      rx_dat_i    => EB_RX_i.dat,
+      rx_stall_o  => rx_stall,
+      tag_stb_o   => fsm_tag_stb,
+      tag_dat_o   => fsm_tag_dat,
+      tag_full_i  => tag_fsm_full,
+      pass_stb_o  => fsm_pass_stb,
+      pass_dat_o  => fsm_pass_dat,
+      pass_full_i => pass_fsm_full,
+      cfg_stb_o   => fsm_cfg_stb,
+      cfg_adr_o   => fsm_cfg_adr,
+      cfg_full_i  => cfg_fsm_full,
+      wbm_stb_o   => fsm_wbm_stb,
+      wbm_full_i  => wbm_fsm_full,
+      wbm_busy_i  => wbm_fsm_busy,
+      master_o    => WB_master_o,
+      master_stall_i => WB_master_i.stall);
+
+  EB_TX_o.we  <= '1';
+  EB_TX_o.sel <= (others => '1');
+  EB_TX_o.adr <= (others => '0');
+  
+  mux : eb_tx_mux
+    port map (
+      clk_i        => clk_i,
+      rstn_i       => rstn_i,
+      tag_pop_o    => mux_tag_pop,
+      tag_dat_i    => tag_mux_dat,
+      tag_empty_i  => tag_mux_empty,
+      pass_pop_o   => mux_pass_pop,
+      pass_dat_i   => pass_mux_dat,
+      pass_empty_i => pass_mux_empty,
+      cfg_pop_o    => mux_cfg_pop,
+      cfg_dat_i    => cfg_mux_dat,
+      cfg_empty_i  => cfg_mux_empty,
+      wbm_pop_o    => mux_wbm_pop,
+      wbm_dat_i    => wbm_mux_dat,
+      wbm_empty_i  => wbm_mux_empty,
+      skip_stb_o   => skip_stb_o,
+      skip_stall_i => skip_stall_i,
+      tx_cyc_o     => EB_TX_o.cyc,
+      tx_stb_o     => EB_TX_o.stb,
+      tx_dat_o     => EB_TX_o.dat,
+      tx_stall_i   => EB_TX_i.stall);
+
+  tag : eb_tag_fifo
+    port map(
+      clk_i       => clk_i,
+      rstn_i      => rstn_i,
+      fsm_stb_i   => fsm_tag_stb,
+      fsm_dat_i   => fsm_tag_dat,
+      fsm_full_o  => tag_fsm_full,
+      mux_pop_i   => mux_tag_pop,
+      mux_dat_o   => tag_mux_dat,
+      mux_empty_o => tag_mux_empty);
+
+  pass : eb_pass_fifo
+    port map(
+      clk_i       => clk_i,
+      rstn_i      => rstn_i,
+      fsm_stb_i   => fsm_pass_stb,
+      fsm_dat_i   => fsm_pass_dat,
+      fsm_full_o  => pass_fsm_full,
+      mux_pop_i   => mux_pass_pop,
+      mux_dat_o   => pass_mux_dat,
+      mux_empty_o => pass_mux_empty);
+
+  cfg : eb_cfg_fifo
+    generic map(
+      g_sdb_address => g_sdb_address)
+    port map(
+      clk_i       => clk_i,
+      rstn_i      => rstn_i,
+      errreg_i    => errreg,
+      cfg_i       => WB_config_i,
+      cfg_o       => WB_config_o,
+      fsm_stb_i   => fsm_cfg_stb,
+      fsm_adr_i   => fsm_cfg_adr,
+      fsm_full_o  => cfg_fsm_full,
+      mux_pop_i   => mux_cfg_pop,
+      mux_dat_o   => cfg_mux_dat,
+      mux_empty_o => cfg_mux_empty,
+      my_mac_o    => my_mac_o,
+      my_ip_o     => my_ip_o,
+      my_port_o   => my_port_o);
+
+  wbm : eb_wbm_fifo
+    generic map(
+      g_timeout_cycles => g_timeout_cycles)
+    port map(
+      clk_i       => clk_i,
+      rstn_i      => rstn_i,
+      errreg_o    => errreg,
+      wb_i        => WB_master_i,
+      fsm_stb_i   => fsm_wbm_stb,
+      fsm_full_o  => wbm_fsm_full,
+      fsm_busy_o  => wbm_fsm_busy,
+      mux_pop_i   => mux_wbm_pop,
+      mux_dat_o   => wbm_mux_dat,
+      mux_empty_o => wbm_mux_empty);
+
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd
new file mode 100644
index 000000000..268c13ed1
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd
@@ -0,0 +1,150 @@
+--! @file eb_stream_narrow.vhd
+--! @brief Adapts the width of a wishbone data stream.
+--!
+--! Copyright (C) 2013 GSI Helmholtz Centre for Heavy Ion Research GmbH 
+--!
+--! Fairly simple state-machine
+--!
+--! @author Wesley W. Terpstra <w.terpstra@gsi.de>
+--!
+--------------------------------------------------------------------------------
+--! This library is free software; you can redistribute it and/or
+--! modify it under the terms of the GNU Lesser General Public
+--! License as published by the Free Software Foundation; either
+--! version 3 of the License, or (at your option) any later version.
+--!
+--! This library is distributed in the hope that it will be useful,
+--! but WITHOUT ANY WARRANTY; without even the implied warranty of
+--! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+--! Lesser General Public License for more details.
+--!  
+--! You should have received a copy of the GNU Lesser General Public
+--! License along with this library. If not, see <http://www.gnu.org/licenses/>.
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.wishbone_pkg.all;
+use work.eb_internals_pkg.all;
+use work.genram_pkg.all;
+
+-- Completely breaks/ignores: adr, sel, we, ack, err
+entity eb_stream_narrow is
+  generic(
+    g_slave_width  : natural;
+    g_master_width : natural);
+  port(
+    clk_i    : in  std_logic;
+    rst_n_i  : in  std_logic;
+    slave_i  : in  t_wishbone_slave_in;
+    slave_o  : out t_wishbone_slave_out;
+    master_i : in  t_wishbone_master_in;
+    master_o : out t_wishbone_master_out);
+end eb_stream_narrow;
+
+architecture rtl of eb_stream_narrow is
+  
+  subtype t_index is unsigned(f_ceil_log2(g_slave_width/g_master_width)-1 downto 0);
+  constant c_max  : t_index := to_unsigned(g_slave_width/g_master_width-1, t_index'length);
+  constant c_one  : t_index := to_unsigned(1, t_index'length);
+  constant c_zero : t_index := (others => '0');
+
+  signal r_ack       : std_logic;
+  signal r_cyc       : std_logic;
+  signal r_drop      : std_logic; -- need to report any cycle line drops
+  signal r_stb       : std_logic;
+  signal r_last      : std_logic; -- '1' when r_idx = 0
+  signal r_idx       : t_index;
+  signal r_dat       : std_logic_vector(g_master_width-1 downto 0);
+  signal s_stall     : std_logic;
+  signal s_cyc_cases : std_logic_vector(2 downto 0);
+  
+begin
+
+  assert (g_slave_width <= c_wishbone_data_width)
+  report "g_master_width can not exceed wishbone data width"
+  severity error;
+
+  assert (g_slave_width mod g_master_width = 0)
+  report "g_master_width must divide g_slave_width"
+  severity error;
+
+  assert (g_master_width < g_slave_width)
+  report "g_master_width must be < g_slave_width"
+  severity error;
+
+  -- Outputs
+  slave_o.ack   <= r_ack;
+  slave_o.err   <= '0';
+  slave_o.stall <= s_stall;
+  slave_o.dat   <= (others => '0');
+  
+  master_o.cyc <= r_cyc;
+  master_o.stb <= r_stb;
+  master_o.we  <= '1';
+  master_o.adr <= (others => '0');
+  master_o.dat(c_wishbone_data_width-1 downto g_master_width) <= (others => '0');
+  master_o.dat(g_master_width-1 downto 0) <= r_dat;
+  
+  output_sel : for i in t_wishbone_byte_select'range generate
+    master_o.sel(i) <= '1' when (i*8 < g_master_width) else '0';
+  end generate;
+  
+  -- Actual logic
+  s_stall <= not r_last or master_i.stall or r_drop;
+  s_cyc_cases(2) <= r_drop;
+  s_cyc_cases(1) <= r_stb;
+  s_cyc_cases(0) <= slave_i.cyc;
+  
+  main : process(clk_i, rst_n_i) is
+  begin
+    if rst_n_i = '0' then
+      r_ack   <= '0';
+      r_cyc   <= '0';
+      r_drop  <= '0';
+      r_stb   <= '0';
+      r_last  <= '0';
+      r_idx   <= c_max;
+      r_dat   <= (others => '0');
+    elsif rising_edge(clk_i) then
+      r_ack <= slave_i.cyc and slave_i.stb and not s_stall;
+      
+      -- Make sure we always report cycle line changes
+      case s_cyc_cases is
+        when "000"  => r_cyc <= '0'; r_drop <= '0'; -- can end cycle immediately
+        when "001"  => r_cyc <= '1'; r_drop <= '0'; -- start new cycle
+        when "010"  => r_cyc <= '1'; r_drop <= '1'; -- report this!
+        when "011"  => r_cyc <= '1'; r_drop <= '0'; -- operation in progress
+        when "100"  => r_cyc <= '0'; r_drop <= '0'; -- reported!
+        when "101"  => r_cyc <= '0'; r_drop <= '0'; -- reported!
+        when others => r_cyc <= '1'; r_drop <= '1'; -- wait for r_stb to fall
+      end case;
+
+      -- When strobing and stalled the process is blocked
+      if (r_stb and master_i.stall) = '0' then
+        -- Steal data from the stalled request
+        r_dat <= slave_i.dat((to_integer(r_idx)+1)*g_master_width-1 downto to_integer(r_idx)*g_master_width);
+        -- If the slave has no new data for us, stop strobing
+        if r_idx = c_max and (slave_i.cyc and slave_i.stb and not r_drop) = '0' then
+          r_stb <= '0';
+        else
+          r_stb <= '1';
+          if r_idx = c_one then
+            r_last <= '1';
+          else
+            r_last <= '0';
+          end if;
+          if r_idx = c_zero then
+            r_idx <= c_max;
+          else
+            r_idx <= r_idx - 1;
+          end if;
+        end if;
+      end if;
+    end if;
+  end process;
+
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd
new file mode 100644
index 000000000..049646600
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd
@@ -0,0 +1,145 @@
+--! @file eb_stream_adapt.vhd
+--! @brief Adapts the width of a wishbone data stream.
+--!
+--! Copyright (C) 2013 GSI Helmholtz Centre for Heavy Ion Research GmbH 
+--!
+--! Fairly simple state-machine
+--!
+--! @author Wesley W. Terpstra <w.terpstra@gsi.de>
+--!
+--------------------------------------------------------------------------------
+--! This library is free software; you can redistribute it and/or
+--! modify it under the terms of the GNU Lesser General Public
+--! License as published by the Free Software Foundation; either
+--! version 3 of the License, or (at your option) any later version.
+--!
+--! This library is distributed in the hope that it will be useful,
+--! but WITHOUT ANY WARRANTY; without even the implied warranty of
+--! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+--! Lesser General Public License for more details.
+--!  
+--! You should have received a copy of the GNU Lesser General Public
+--! License along with this library. If not, see <http://www.gnu.org/licenses/>.
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.wishbone_pkg.all;
+use work.eb_internals_pkg.all;
+use work.genram_pkg.all;
+
+-- Completely breaks/ignores: adr, sel, we, ack, err
+entity eb_stream_widen is
+  generic(
+    g_slave_width  : natural;
+    g_master_width : natural);
+  port(
+    clk_i    : in  std_logic;
+    rst_n_i  : in  std_logic;
+    slave_i  : in  t_wishbone_slave_in;
+    slave_o  : out t_wishbone_slave_out;
+    master_i : in  t_wishbone_master_in;
+    master_o : out t_wishbone_master_out);
+end eb_stream_widen;
+
+architecture rtl of eb_stream_widen is
+  
+  subtype t_index is unsigned(f_ceil_log2(g_master_width/g_slave_width)-1 downto 0);
+  constant c_max  : t_index := to_unsigned(g_master_width/g_slave_width-1, t_index'length);
+  constant c_zero : t_index := (others => '0');
+
+  signal r_ack       : std_logic;
+  signal r_cyc       : std_logic;
+  signal r_drop      : std_logic; -- need to report any cycle line drops
+  signal r_stb       : std_logic;
+  signal r_idx       : t_index;
+  signal r_dat       : t_wishbone_data;
+  signal s_stall     : std_logic;
+  signal s_cyc_cases : std_logic_vector(2 downto 0);
+  
+begin
+
+  assert (g_master_width <= c_wishbone_data_width)
+  report "g_master_width can not exceed wishbone data width"
+  severity error;
+
+  assert (g_master_width mod g_slave_width = 0)
+  report "g_slave_width must divide g_master_width"
+  severity error;
+
+  assert (g_master_width > g_slave_width)
+  report "g_slave_width must be < g_master_width"
+  severity error;
+
+  -- Outputs
+  slave_o.ack   <= r_ack;
+  slave_o.err   <= '0';
+  slave_o.stall <= s_stall;
+  slave_o.dat   <= (others => '0');
+  
+  master_o.cyc <= r_cyc;
+  master_o.stb <= r_stb;
+  master_o.we  <= '1';
+  master_o.adr <= (others => '0');
+  master_o.dat <= r_dat;
+  
+  output_sel : for i in t_wishbone_byte_select'range generate
+    master_o.sel(i) <= '1' when (i*8 < g_master_width) else '0';
+  end generate;
+
+  -- Actual logic
+  s_stall <= (r_stb and master_i.stall) or r_drop;
+  s_cyc_cases(2) <= r_drop;
+  s_cyc_cases(1) <= r_stb;
+  s_cyc_cases(0) <= slave_i.cyc;
+  
+  main : process(clk_i, rst_n_i) is
+  begin
+    if rst_n_i = '0' then
+      r_ack  <= '0';
+      r_cyc  <= '0';
+      r_drop <= '0';
+      r_stb  <= '0';
+      r_idx  <= c_max;
+      r_dat  <= (others => '0');
+    elsif rising_edge(clk_i) then
+      r_ack <= slave_i.cyc and slave_i.stb and not s_stall;
+      
+      -- Make sure we always report cycle line changes
+      case s_cyc_cases is
+        when "000"  => r_cyc <= '0'; r_drop <= '0'; -- can end cycle immediately
+        when "001"  => r_cyc <= '1'; r_drop <= '0'; -- start new cycle
+        when "010"  => r_cyc <= '1'; r_drop <= '1'; -- report this!
+        when "011"  => r_cyc <= '1'; r_drop <= '0'; -- operation in progress
+        when "100"  => r_cyc <= '0'; r_drop <= '0'; -- reported!
+        when "101"  => r_cyc <= '0'; r_drop <= '0'; -- reported!
+        when others => r_cyc <= '1'; r_drop <= '1'; -- wait for r_stb to fall
+      end case;
+      
+      -- Transfer done?
+      if (r_stb and not master_i.stall) = '1' then
+        r_stb <= '0';
+      end if;
+      
+      -- Did the slave push us data?
+      if slave_i.cyc = '0' then
+        r_idx <= c_max; -- reset counter to restore alignment
+        -- leave r_stb/r_dat unchanged!
+      elsif (slave_i.stb and not s_stall) = '1' then
+        r_dat(((to_integer(r_idx)+1)*g_slave_width)-1 downto to_integer(r_idx)*g_slave_width) <= 
+          slave_i.dat(g_slave_width-1 downto 0);
+        if r_idx = c_zero then
+          r_idx <= c_max;
+          r_stb <= '1';
+        else
+          r_idx <= r_idx - 1;
+        end if;
+      end if;
+      
+    end if;
+  end process;
+  
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd
new file mode 100644
index 000000000..015e32bb0
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd
@@ -0,0 +1,61 @@
+------------------------------------------------------------------------------
+-- Title      : Etherbone Tag FIFO
+-- Project    : Etherbone Core
+------------------------------------------------------------------------------
+-- File       : eb_tag_fifo.vhd
+-- Author     : Wesley W. Terpstra
+-- Company    : GSI
+-- Created    : 2013-04-08
+-- Last update: 2013-04-08
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Tracks which channel the MUX should pop next
+-------------------------------------------------------------------------------
+-- Copyright (c) 2013 GSI
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2013-04-08  1.0      terpstra        Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.wishbone_pkg.all;
+use work.eb_internals_pkg.all;
+
+entity eb_tag_fifo is
+  port(
+    clk_i       : in  std_logic;
+    rstn_i      : in  std_logic;
+    
+    fsm_stb_i   : in  std_logic;
+    fsm_dat_i   : in  t_tag;
+    fsm_full_o  : out std_logic;
+
+    mux_pop_i   : in  std_logic;
+    mux_dat_o   : out t_tag;
+    mux_empty_o : out std_logic);
+end eb_tag_fifo;
+
+architecture rtl of eb_tag_fifo is
+begin
+
+  fifo : eb_fifo
+    generic map(
+      g_width => t_tag'length,
+      g_size  => c_queue_depth)
+    port map(
+      clk_i     => clk_i,
+      rstn_i    => rstn_i,
+      w_full_o  => fsm_full_o,
+      w_push_i  => fsm_stb_i,
+      w_dat_i   => fsm_dat_i,
+      r_empty_o => mux_empty_o,
+      r_pop_i   => mux_pop_i,
+      r_dat_o   => mux_dat_o);
+      
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd
new file mode 100644
index 000000000..2c2c4c345
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd
@@ -0,0 +1,170 @@
+------------------------------------------------------------------------------
+-- Title      : Etherbone TX MUX
+-- Project    : Etherbone Core
+------------------------------------------------------------------------------
+-- File       : eb_tux_mux.vhd
+-- Author     : Wesley W. Terpstra
+-- Company    : GSI
+-- Created    : 2013-04-08
+-- Last update: 2013-04-08
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Combines output streams into a packet
+-------------------------------------------------------------------------------
+-- Copyright (c) 2013 GSI
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2013-04-08  1.0      terpstra        Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.wishbone_pkg.all;
+use work.eb_internals_pkg.all;
+
+entity eb_tx_mux is
+  port(
+    clk_i       : in  std_logic;
+    rstn_i      : in  std_logic;
+    
+    tag_pop_o   : out std_logic;
+    tag_dat_i   : in  t_tag;
+    tag_empty_i : in  std_logic;
+    
+    pass_pop_o   : out std_logic;
+    pass_dat_i   : in  t_wishbone_data;
+    pass_empty_i : in  std_logic;
+    
+    cfg_pop_o    : out std_logic;
+    cfg_dat_i    : in  t_wishbone_data;
+    cfg_empty_i  : in  std_logic;
+    
+    wbm_pop_o    : out std_logic;
+    wbm_dat_i    : in  t_wishbone_data;
+    wbm_empty_i  : in  std_logic;
+    
+    skip_stb_o   : out std_logic;
+    skip_stall_i : in  std_logic;
+    
+    tx_cyc_o     : out std_logic;
+    tx_stb_o     : out std_logic;
+    tx_dat_o     : out t_wishbone_data;
+    tx_stall_i   : in  std_logic);
+end eb_tx_mux;
+
+architecture rtl of eb_tx_mux is
+
+  signal r_skip      : std_logic;
+  signal r_tx_cyc    : std_logic;
+  signal r_tx_stb    : std_logic;
+  signal s_can_tx    : std_logic;
+  signal s_dat_mux   : t_wishbone_data;
+  signal s_tag_mux   : std_logic;
+  signal s_pass_mux  : std_logic;
+  signal s_cfg_mux   : std_logic;
+  signal s_wbm_mux   : std_logic;
+  signal s_tag_pop   : std_logic;
+  signal r_tag_valid : std_logic;
+  signal r_tag_value : t_tag;
+  
+begin
+
+  -- We can write whenever TX is unstalled and/or not full
+  s_can_tx <= not ((r_tx_cyc and r_tx_stb and tx_stall_i) or (r_skip and skip_stall_i));
+  
+  skip_stb_o <= r_skip;
+  tx_cyc_o   <= r_tx_cyc;
+  tx_stb_o   <= r_tx_stb;
+  
+  tx_out : process(rstn_i, clk_i) is
+  begin
+    if rstn_i = '0' then
+      r_skip   <= '0';
+      r_tx_cyc <= '0';
+      r_tx_stb <= '0';
+      tx_dat_o <= (others => '0');
+    elsif rising_edge(clk_i) then
+      if s_can_tx = '1' then -- is prior operation complete?
+        r_tx_stb <= not s_tag_mux and r_tag_valid;
+        r_skip <= '0';
+        tx_dat_o <= s_dat_mux;
+        -- Control the TX cycle line
+        if r_tag_valid = '1' then
+          case r_tag_value is
+            when c_tag_drop_tx => r_tx_cyc <= '0';
+            when c_tag_pass_tx => r_tx_cyc <= '1';
+            when c_tag_skip_tx => r_skip   <= '1';
+            when others        => null;
+          end case;
+        end if;
+      end if;
+    end if;
+  end process;
+  
+  with r_tag_value select
+  s_dat_mux <= 
+    pass_dat_i      when c_tag_pass_tx,
+    pass_dat_i      when c_tag_pass_on,
+    cfg_dat_i       when c_tag_cfg_req,
+    pass_dat_i      when c_tag_cfg_ign,
+    wbm_dat_i       when c_tag_wbm_req,
+    pass_dat_i      when c_tag_wbm_ign,
+    (others => '-') when others; -- c_tag_skip_tx, c_tag_drop_tx
+  
+  with r_tag_value select
+  s_tag_mux <=
+    pass_empty_i                  when c_tag_pass_tx,
+    pass_empty_i                  when c_tag_pass_on,
+    cfg_empty_i                   when c_tag_cfg_req,
+    (pass_empty_i or cfg_empty_i) when c_tag_cfg_ign,
+    wbm_empty_i                   when c_tag_wbm_req,
+    (pass_empty_i or wbm_empty_i) when c_tag_wbm_ign,
+    '0'                           when others; -- c_tag_skip_tx, c_tag_drop_tx
+  
+  with r_tag_value select
+  s_pass_mux <=
+    pass_empty_i                  when c_tag_pass_tx,
+    pass_empty_i                  when c_tag_pass_on,
+    (pass_empty_i or cfg_empty_i) when c_tag_cfg_ign,
+    (pass_empty_i or wbm_empty_i) when c_tag_wbm_ign,
+    '1'                           when others; -- c_tag_skip_tx, c_tag_drop_tx, c_tag_cfg_req, c_tag_wbm_req
+  
+  with r_tag_value select
+  s_cfg_mux <=
+    cfg_empty_i                   when c_tag_cfg_req,
+    (pass_empty_i or cfg_empty_i) when c_tag_cfg_ign,
+    '1'                           when others;
+  
+  with r_tag_value select
+  s_wbm_mux <=
+    wbm_empty_i                   when c_tag_wbm_req,
+    (pass_empty_i or wbm_empty_i) when c_tag_wbm_ign,
+    '1'                           when others;
+  
+  -- Pop the queue we fed into TX
+  pass_pop_o <= s_can_tx and r_tag_valid and not s_pass_mux;
+  cfg_pop_o  <= s_can_tx and r_tag_valid and not s_cfg_mux;
+  wbm_pop_o  <= s_can_tx and r_tag_valid and not s_wbm_mux;
+  s_tag_pop  <= s_can_tx and r_tag_valid and not s_tag_mux;
+  
+  -- Pop the tag FIFO if the register is empty/emptied
+  tag_pop_o <= not tag_empty_i and (s_tag_pop or not r_tag_valid);
+  tag_in : process(rstn_i, clk_i) is
+  begin
+    if rstn_i = '0' then
+      r_tag_valid <= '0';
+      r_tag_value <= c_tag_drop_tx;
+    elsif rising_edge(clk_i) then
+      if s_tag_pop = '1' or r_tag_valid = '0' then
+        r_tag_valid <= not tag_empty_i;
+        r_tag_value <= tag_dat_i;
+      end if;
+    end if;
+  end process;
+  
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd
new file mode 100644
index 000000000..245863e42
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd
@@ -0,0 +1,171 @@
+------------------------------------------------------------------------------
+-- Title      : Etherbone Wishbone Master FIFO
+-- Project    : Etherbone Core
+------------------------------------------------------------------------------
+-- File       : eb_wbm_fifo.vhd
+-- Author     : Wesley W. Terpstra
+-- Company    : GSI
+-- Created    : 2013-04-08
+-- Last update: 2013-04-08
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Buffers Wishbone requests to resulting data
+-------------------------------------------------------------------------------
+-- Copyright (c) 2013 GSI
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2013-04-08  1.0      terpstra        Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.wishbone_pkg.all;
+use work.eb_internals_pkg.all;
+
+entity eb_wbm_fifo is
+  generic(
+    g_timeout_cycles : natural);
+  port(
+    clk_i       : in  std_logic;
+    rstn_i      : in  std_logic;
+    
+    errreg_o    : out std_logic_vector(63 downto 0);
+    wb_i        : in  t_wishbone_master_in;
+    
+    fsm_stb_i   : in  std_logic;
+    fsm_busy_o  : out std_logic;
+    fsm_full_o  : out std_logic;
+
+    mux_pop_i   : in  std_logic;
+    mux_dat_o   : out t_wishbone_data;
+    mux_empty_o : out std_logic);
+end eb_wbm_fifo;
+
+architecture rtl of eb_wbm_fifo is
+  
+  constant c_size  : natural := c_queue_depth;
+  constant c_sbits : natural := f_ceil_log2(c_size);
+  constant c_tbits : natural := f_ceil_log2(g_timeout_cycles);
+  
+  signal s_wb_i_rdy    : std_logic;                     -- 1 when a strobe ackd
+  signal r_inflight    : unsigned(c_sbits-1 downto 0);  -- # unacked strobes
+  signal r_busy        : std_logic;                     -- 1 when r_inflight > 0
+  signal r_queued      : unsigned(c_sbits-1 downto 0);  -- # unpoped strobes (>= r_inflight)
+  signal r_full        : std_logic;                     -- 1 when r_queued > 0
+  signal r_timeout     : unsigned(c_tbits-1 downto 0);  -- counts downto 0 between acks
+  signal r_kill_ack    : std_logic;                     -- 1 when r_timeout expires
+  signal r_errreg      : std_logic_vector(63 downto 0); -- shifts in ack when data pops
+  signal s_ack         : std_logic;                     -- ack of ready data
+  
+begin
+
+  s_wb_i_rdy <= wb_i.ack or wb_i.err or wb_i.rty or r_kill_ack;
+  
+  fsm_busy_o <= r_busy;
+  busy : process(rstn_i, clk_i) is
+  begin
+    if rstn_i = '0' then
+      r_busy <= '0';
+      r_inflight <= (others => '0');
+    elsif rising_edge(clk_i) then
+      if fsm_stb_i = '1' then
+        if s_wb_i_rdy = '1' then         -- push+pop
+          r_inflight <= r_inflight;
+        else                             -- push
+          r_busy <= '1';
+          r_inflight <= r_inflight + 1;
+        end if;
+      else
+        if s_wb_i_rdy = '1' then         -- pop
+          if r_inflight = 1 then
+            r_busy <= '0';
+          end if;
+          r_inflight <= r_inflight - 1;
+        else                             -- noop
+          r_inflight <= r_inflight;
+        end if;
+      end if;
+    end if;
+  end process;
+  
+  fsm_full_o <= r_full;
+  full : process(rstn_i, clk_i) is
+  begin
+    if rstn_i = '0' then
+      r_full <= '0';
+      r_queued <= (others => '0');
+    elsif rising_edge(clk_i) then
+      if fsm_stb_i = '1' then
+        if mux_pop_i = '1' then          -- push+pop
+          r_queued <= r_queued;
+        else                             -- push
+          if r_queued = c_size-1 then
+            r_full <= '1';
+          end if;
+          r_queued <= r_queued + 1;
+        end if;
+      else
+        if mux_pop_i = '1' then          -- pop
+          r_full <= '0';
+          r_queued <= r_queued - 1;
+        else                             -- noop
+          r_queued <= r_queued;
+        end if;
+      end if;
+    end if;
+  end process;
+  
+  kill_ack : process(rstn_i, clk_i) is
+  begin
+    if rstn_i = '0' then
+      r_kill_ack <= '0';
+      r_timeout  <= to_unsigned(g_timeout_cycles, r_timeout'length);
+    elsif rising_edge(clk_i) then
+      if s_wb_i_rdy = '1' or r_busy = '0' then -- ackd?
+        r_kill_ack <= '0';
+        r_timeout  <= to_unsigned(g_timeout_cycles, r_timeout'length);
+      else
+        if r_timeout = 1 then
+          r_kill_ack <= '1'; -- causes s_wb_i_rdy next cycle
+        end if;
+        r_timeout <= r_timeout - 1;
+      end if;
+    end if;
+  end process;
+  
+  datfifo : eb_fifo
+    generic map(
+      g_width => c_wishbone_data_width+1,
+      g_size  => c_size)
+    port map(
+      clk_i                           => clk_i,
+      rstn_i                          => rstn_i,
+      w_full_o                        => open,
+      w_push_i                        => s_wb_i_rdy,
+      w_dat_i(t_wishbone_data'range)  => wb_i.dat,
+      w_dat_i(t_wishbone_data'length) => wb_i.ack,
+      r_empty_o                       => mux_empty_o,
+      r_pop_i                         => mux_pop_i,
+      r_dat_o(t_wishbone_data'range)  => mux_dat_o,
+      r_dat_o(t_wishbone_data'length) => s_ack);
+  
+  -- Shift the error register during data pop
+  -- This ensures that it reflects state synchronous to the TX path
+  errreg_o <= r_errreg;
+  errreg : process(rstn_i, clk_i) is
+  begin
+    if rstn_i = '0' then
+      r_errreg <= (others => '0');
+    elsif rising_edge(clk_i) then
+      if mux_pop_i = '1' then
+        r_errreg <= r_errreg(r_errreg'left-1 downto 0) & (not s_ack);
+      end if;
+    end if;
+  end process;
+  
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd
new file mode 100644
index 000000000..394b1e878
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd
@@ -0,0 +1,168 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.wishbone_pkg.all;
+use work.wr_fabric_pkg.all;
+
+package etherbone_pkg is
+  constant c_etherbone_sdb : t_sdb_device := (
+    abi_class     => x"0000", -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"01",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"4", --32-bit port granularity
+    sdb_component => (
+    addr_first    => x"0000000000000000",
+    addr_last     => x"00000000000000ff",
+    product => (
+    vendor_id     => x"0000000000000651", -- GSI
+    device_id     => x"68202b22",
+    version       => x"00000001",
+    date          => x"20130211",
+    name          => "Etherbone-Config   ")));
+  
+  constant c_ebm_sdb : t_sdb_device := (
+    abi_class     => x"0000", -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"01",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"7", -- 8/16/32-bit port granularity
+    sdb_component => (
+    addr_first    => x"0000000000000000",
+    addr_last     => x"0000000000ffffff",
+    product => (
+    vendor_id     => x"0000000000000651", -- GSI
+    device_id     => x"00000815",
+    version       => x"00000002",
+    date          => x"20140615",
+    name          => "Etherbone_Master   ")));
+  
+  function f_hi_adr_bits(ebm : t_sdb_device) return natural;
+  
+  
+  component eb_raw_slave is
+    generic(
+      g_sdb_address    : std_logic_vector(63 downto 0);
+      g_timeout_cycles : natural := 6250000; -- 100 ms at 62.5MHz
+      g_bus_width      : natural);
+    port(
+      clk_i       : in  std_logic;
+      nRst_i      : in  std_logic;
+      snk_i       : in  t_wishbone_slave_in;
+      snk_o       : out t_wishbone_slave_out;
+      src_o       : out t_wishbone_master_out;
+      src_i       : in  t_wishbone_master_in;
+      cfg_slave_o : out t_wishbone_slave_out;
+      cfg_slave_i : in  t_wishbone_slave_in;
+      master_o    : out t_wishbone_master_out;
+      master_i    : in  t_wishbone_master_in);
+  end component;
+
+  component eb_master_slave_wrapper is
+  generic(
+    g_with_master         : boolean := false;
+    
+    g_ebs_sdb_address     : std_logic_vector(63 downto 0);
+    g_ebs_timeout_cycles  : natural := 6250000;
+    g_ebs_mtu             : natural := 1500;
+    
+    g_ebm_adr_bits_hi     : natural := f_hi_adr_bits(c_ebm_sdb)
+    
+    );
+  port(
+    clk_i           : in  std_logic;
+    nRst_i          : in  std_logic;
+    
+    --to wr core, ext wrf if 
+    snk_i           : in  t_wrf_sink_in;
+    snk_o           : out t_wrf_sink_out;
+    src_o           : out t_wrf_source_out;
+    src_i           : in  t_wrf_source_in;
+  
+    --ebs
+    ebs_cfg_slave_o : out t_wishbone_slave_out;
+    ebs_cfg_slave_i : in  t_wishbone_slave_in;
+    ebs_wb_master_o : out t_wishbone_master_out;
+    ebs_wb_master_i : in  t_wishbone_master_in;
+    
+    --ebm (optional)
+    ebm_wb_slave_i  : in  t_wishbone_slave_in;
+    ebm_wb_slave_o  : out t_wishbone_slave_out 
+     
+  );
+  end component;
+  
+  component eb_ethernet_slave is
+    generic(
+      g_sdb_address    : std_logic_vector(63 downto 0);
+      g_timeout_cycles : natural := 6250000; -- 100 ms at 62.5MHz
+      g_mtu            : natural := 1500);
+    port(
+      clk_i       : in  std_logic;
+      nRst_i      : in  std_logic;
+      snk_i       : in  t_wrf_sink_in;
+      snk_o       : out t_wrf_sink_out;
+      src_o       : out t_wrf_source_out;
+      src_i       : in  t_wrf_source_in;
+      cfg_slave_o : out t_wishbone_slave_out;
+      cfg_slave_i : in  t_wishbone_slave_in;
+      master_o    : out t_wishbone_master_out;
+      master_i    : in  t_wishbone_master_in);
+  end component;
+
+  -- Backwards compatability component; use eb_ethernet_slave
+  component eb_slave_core is
+    generic(
+      g_sdb_address    : std_logic_vector(63 downto 0);
+      g_timeout_cycles : natural := 6250000; -- 100 ms at 62.5MHz
+      g_mtu            : natural := 1500);
+    port(
+      clk_i       : in  std_logic;
+      nRst_i      : in  std_logic;
+      snk_i       : in  t_wrf_sink_in;
+      snk_o       : out t_wrf_sink_out;
+      src_o       : out t_wrf_source_out;
+      src_i       : in  t_wrf_source_in;
+      cfg_slave_o : out t_wishbone_slave_out;
+      cfg_slave_i : in  t_wishbone_slave_in;
+      master_o    : out t_wishbone_master_out;
+      master_i    : in  t_wishbone_master_in);
+  end component;
+  
+  component eb_master_top is
+generic(g_adr_bits_hi : natural := 8;
+        g_mtu : natural := 32);
+port(
+  clk_i         : in  std_logic;
+  rst_n_i       : in  std_logic;
+
+  slave_i       : in  t_wishbone_slave_in;
+  slave_o       : out t_wishbone_slave_out;
+  
+  framer_in   : out t_wishbone_slave_in;
+  framer_out  : out t_wishbone_slave_out;
+  
+  src_i         : in  t_wrf_source_in;
+  src_o         : out t_wrf_source_out
+);
+end component;
+
+
+
+end etherbone_pkg;
+
+package body etherbone_pkg is
+
+   -- gets correct number of high address bits from ebm sdb
+   function f_hi_adr_bits(ebm : t_sdb_device) return natural is
+      variable ret : natural := 2;
+      variable len : natural;
+   begin
+     len := f_hot_to_bin(ebm.sdb_component.addr_last);
+     ret := c_wishbone_address_width - (len - 2);
+     return ret;
+   end f_hi_adr_bits;
+
+end etherbone_pkg;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_crc_gen.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_crc_gen.vhd
new file mode 100644
index 000000000..e7d6b6665
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_crc_gen.vhd
@@ -0,0 +1,280 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- Ultimate CRC.                                                ----
+----                                                              ----
+---- This file is part of the ultimate CRC projectt               ----
+---- http://www.opencores.org/cores/ultimate_crc/                 ----
+----                                                              ----
+---- Description                                                  ----
+---- CRC generator/checker, parallel implementation.              ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Geir Drange, gedra@opencores.org                           ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2005 Authors and OPENCORES.ORG                 ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU General          ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.0 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU General Public License for more details.----
+----                                                              ----
+---- You should have received a copy of the GNU General           ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/gpl.txt                     ----
+----                                                              ----
+----------------------------------------------------------------------
+--
+-- CVS Revision History
+--
+-- $Log: ucrc_par.vhd,v $
+-- Revision 1.1  2005/05/09 15:58:38  gedra
+-- Parallel implementation
+--
+-- Modified by T.W. for use in GenCores library
+-- 
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.gencores_pkg.all;
+
+entity gc_crc_gen is
+  generic (
+-- polynomial of our CRC generator
+    g_polynomial              : std_logic_vector       := x"04C11DB7";
+-- initial (after-reset) value of CRC
+    g_init_value              : std_logic_vector       := x"ffffffff";
+-- residual value of CRC when matched
+    g_residue                 : std_logic_vector       := x"38fb2284";
+-- width of full data input word 
+    g_data_width              : integer range 2 to 256 := 16;
+-- width of smaller-than-full data input word
+    g_half_width              : integer range 2 to 256 := 8;
+-- use synchronous reset when 1
+    g_sync_reset              : integer range 0 to 1   := 0;
+-- dual-width mode (g_data_width - wide input word when 1 and g_half_width input
+-- word when 0)
+    g_dual_width              : integer range 0 to 1   := 0;
+-- if true, match_o output is registered, otherwise it's driven combinatorially
+    g_registered_match_output : boolean                := true;
+    g_registered_crc_output   : boolean                := true); 
+  port (
+    clk_i  : in std_logic;              -- clock
+    rst_i  : in std_logic;              -- reset, active high
+    en_i   : in std_logic;              -- enable input, active high
+    half_i : in std_logic;              -- 1: input word has g_half_width bits
+                                        -- 0: input word has g_data_width bits
+
+    data_i    : in std_logic_vector(g_data_width - 1 downto 0);  -- data input
+    restart_i : in std_logic := '0';
+
+    match_o : out std_logic;            -- CRC match flag: 1 - CRC matches
+
+    crc_o : out std_logic_vector(g_polynomial'length - 1 downto 0));  -- CRC
+                                                                      -- output value
+end gc_crc_gen;
+
+architecture rtl of gc_crc_gen is
+
+  function f_reverse_vector (a : in std_logic_vector)
+    return std_logic_vector is
+    variable v_result : std_logic_vector(a'reverse_range);
+  begin
+    for i in a'range loop
+      v_result(i) := a(i);
+    end loop;
+    return v_result;
+  end;
+
+  function f_reverse_bytes (a : in std_logic_vector)
+    return std_logic_vector is
+    variable tmp      : std_logic_vector(a'length-1 downto 0);
+    variable v_result : std_logic_vector(a'length-1 downto 0);
+  begin
+    tmp := a;
+    for i in tmp'range loop
+      v_result(i) := tmp(((tmp'length/8-1) - i/8)*8 + (i mod 8));
+    end loop;
+    return v_result;
+  end;
+
+
+  constant msb        : integer                        := g_polynomial'length - 1;
+  constant init_msb   : integer                        := g_init_value'length - 1;
+  constant p          : std_logic_vector(msb downto 0) := g_polynomial;
+  constant dw         : integer                        := g_data_width;
+  constant pw         : integer                        := g_polynomial'length;
+  type     fb_array is array (dw downto 1) of std_logic_vector(msb downto 0);
+  type     dmsb_array is array (dw downto 1) of std_logic_vector(msb downto 1);
+  signal   crca       : fb_array;
+  signal   da, ma     : dmsb_array;
+  signal   crc        : std_logic_vector(msb downto 0);
+  signal   arst, srst : std_logic;
+
+
+  signal data_i2           : std_logic_vector(g_data_width-1 downto 0);
+  signal en_d0             : std_logic;
+  signal crc_cur, crc_next : std_logic_vector(g_polynomial'length-1 downto 0);
+
+  
+begin
+
+-- Parameter checking: Invalid generics will abort simulation/synthesis
+  PCHK1 : if msb /= init_msb generate
+    process
+    begin
+      report "g_polynomial and g_init_value vectors must be equal length!"
+        severity failure;
+      wait;
+    end process;
+  end generate PCHK1;
+
+  PCHK2 : if (msb < 3) or (msb > 31) generate
+    process
+    begin
+      report "g_polynomial must be of order 4 to 32!"
+        severity failure;
+      wait;
+    end process;
+  end generate PCHK2;
+
+  PCHK3 : if p(0) /= '1' generate       -- LSB must be 1
+    process
+    begin
+      report "g_polynomial must have lsb set to 1!"
+        severity failure;
+      wait;
+    end process;
+  end generate PCHK3;
+
+  data_i2 <= f_reverse_bytes(data_i);
+
+  crc_cur <= g_init_value when restart_i = '1' else crc;
+
+-- Generate vector of each data bit
+  CA : for i in 1 to dw generate        -- data bits
+    DAT : for j in 1 to msb generate
+      da(i)(j) <= data_i2(i - 1);
+    end generate DAT;
+  end generate CA;
+
+-- Generate vector of each CRC MSB
+  MS0 : for i in 1 to msb generate
+    ma(1)(i) <= crc_cur(msb);
+  end generate MS0;
+  MSP : for i in 2 to dw generate
+    MSU : for j in 1 to msb generate
+      ma(i)(j) <= crca(i - 1)(msb);
+    end generate MSU;
+  end generate MSP;
+
+-- Generate feedback matrix
+  crca(1)(0)            <= da(1)(1) xor crc_cur(msb);
+  crca(1)(msb downto 1) <= crc_cur(msb - 1 downto 0) xor ((da(1) xor ma(1)) and p(msb downto 1));
+  FB : for i in 2 to dw generate
+    crca(i)(0)            <= da(i)(1) xor crca(i - 1)(msb);
+    crca(i)(msb downto 1) <= crca(i - 1)(msb - 1 downto 0) xor
+                             ((da(i) xor ma(i)) and p(msb downto 1));
+  end generate FB;
+
+-- Reset signal
+  SR : if g_sync_reset = 1 generate
+    srst <= rst_i;
+    arst <= '0';
+  end generate SR;
+  AR : if g_sync_reset = 0 generate
+    srst <= '0';
+    arst <= rst_i;
+  end generate AR;
+
+
+  CRCP : process (clk_i, arst)
+  begin
+    if arst = '1' then                  -- async. reset
+      crc     <= g_init_value;
+    elsif rising_edge(clk_i) then
+      if srst = '1' then                -- sync. reset
+        crc <= g_init_value;
+      elsif en_i = '1' then
+        
+        if(half_i = '1' and g_dual_width = 1) then
+          crc <= crca(g_half_width);
+        else
+          crc <= crca(g_data_width);
+        end if;
+      end if;
+    end if;
+  end process;
+
+  p_crc_next : process(crc, half_i, crca)
+  begin
+    if(g_registered_crc_output) then
+      crc_next <= f_reverse_bytes(f_reverse_vector(not crc));
+    else
+      if(half_i = '1' and g_dual_width = 1) then
+        crc_next <= f_reverse_bytes(f_reverse_vector(not crca(g_half_width)));
+      else
+        crc_next <= f_reverse_bytes(f_reverse_vector(not crca(g_data_width)));
+      end if;
+    end if;
+  end process;
+
+  p_crc_output : process(crc_next, crc, en_i)
+  begin
+    if(g_registered_crc_output) then
+      crc_o <= crc_next;
+    elsif(en_i = '1') then
+      crc_o <= crc_next;
+    else
+      crc_o <= f_reverse_bytes(f_reverse_vector(not crc));
+    end if;
+  end process;
+
+  gen_reg_match_output : if(g_registered_match_output) generate
+    
+    match_gen : process (clk_i, arst)
+    begin
+      if arst = '1' then                -- async. reset
+        match_o <= '0';
+        en_d0   <= '0';
+      elsif rising_edge(clk_i) then
+        if srst = '1' then              -- sync. reset
+          match_o <= '0';
+          en_d0   <= '0';
+        else
+          en_d0 <= en_i;
+
+          if(en_d0 = '1') then
+            if crc_next = g_residue then
+              match_o <= '1';
+            else
+              match_o <= '0';
+            end if;
+          end if;
+        end if;
+      end if;
+    end process;
+    
+  end generate gen_reg_match_output;
+
+  gen_comb_match_output : if (not g_registered_match_output) generate
+    match_o <= '1' when crc_next = g_residue else '0';
+  end generate gen_comb_match_output;
+end rtl;
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd
new file mode 100644
index 000000000..939d516a4
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd
@@ -0,0 +1,93 @@
+-------------------------------------------------------------------------------
+-- Title      : Pulse width extender
+-- Project    : General Cores library
+-------------------------------------------------------------------------------
+-- File       : gc_extend_pulse.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Created    : 2009-09-01
+-- Last update: 2012-06-19
+-- Platform   : FPGA-generic
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Description:
+-- Synchronous pulse extender. Generates a pulse of programmable width upon
+-- detection of a rising edge in the input.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2009-2011 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2009-09-01  0.9      twlostow        Created
+-- 2011-04-18  1.0      twlostow        Added comments & header
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.NUMERIC_STD.all;
+
+library work;
+use work.gencores_pkg.all;
+use work.genram_pkg.all;
+
+entity gc_extend_pulse is
+  
+  generic (
+    -- output pulse width in clk_i cycles
+    g_width : natural := 1000
+    );
+  port (
+    clk_i      : in  std_logic;
+    rst_n_i    : in  std_logic;
+    -- input pulse (synchronou to clk_i)
+    pulse_i    : in  std_logic;
+    -- extended output pulse
+    extended_o : out std_logic := '0');
+end gc_extend_pulse;
+
+architecture rtl of gc_extend_pulse is
+
+  signal cntr : unsigned(f_log2_size(g_width)-1 downto 0);
+  signal extended_int : std_logic;
+  
+begin  -- rtl
+
+  extend : process (clk_i, rst_n_i)
+  begin  -- process extend
+    if rst_n_i = '0' then                   -- asynchronous reset (active low)
+      extended_int <= '0';
+      cntr       <= (others => '0');
+    elsif clk_i'event and clk_i = '1' then  -- rising clock edge
+      if(pulse_i = '1') then
+        extended_int <= '1';
+        cntr       <= to_unsigned(g_width - 2, cntr'length);
+      elsif cntr /= to_unsigned(0, cntr'length) then
+        cntr <= cntr - 1;
+      else
+        extended_int <= '0';
+      end if;
+    end if;
+  end process extend;
+
+  extended_o <= pulse_i or extended_int;
+
+end rtl;
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd
new file mode 100644
index 000000000..39b15afc7
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd
@@ -0,0 +1,130 @@
+-------------------------------------------------------------------------------
+-- Title      : Frequency meter
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : gc_frequency_meter.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2012-2015 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.gencores_pkg.all;
+
+entity gc_frequency_meter is
+  generic(
+    g_with_internal_timebase : boolean := true;
+    g_clk_sys_freq           : integer;
+    g_counter_bits           : integer := 32);
+
+  port(
+    clk_sys_i    : in  std_logic;
+    clk_in_i     : in  std_logic;
+    rst_n_i      : in  std_logic;
+    pps_p1_i     : in  std_logic;
+    freq_o       : out std_logic_vector(g_counter_bits-1 downto 0);
+    freq_valid_o : out std_logic
+    );
+
+end gc_frequency_meter;
+
+
+architecture behavioral of gc_frequency_meter is
+
+  signal gate_pulse, gate_pulse_synced : std_logic;
+
+  signal cntr_gate : unsigned(g_counter_bits-1 downto 0);
+  signal cntr_meas : unsigned(g_counter_bits-1 downto 0);
+  signal freq_reg  : std_logic_vector(g_counter_bits-1 downto 0);
+
+begin
+
+  gen_internal_timebase : if(g_with_internal_timebase = true) generate
+
+    p_gate_counter : process(clk_sys_i)
+    begin
+      if rising_edge(clk_sys_i) then
+        if rst_n_i = '0' then
+          cntr_gate  <= (others => '0');
+          gate_pulse <= '0';
+        else
+          if(cntr_gate = g_clk_sys_freq-1) then
+            cntr_gate  <= (others => '0');
+            gate_pulse <= '1';
+          else
+            cntr_gate  <= cntr_gate + 1;
+            gate_pulse <= '0';
+          end if;
+        end if;
+      end if;
+    end process;
+
+  U_Sync_Gate : gc_pulse_synchronizer
+    port map (
+      clk_in_i  => clk_sys_i,
+      clk_out_i => clk_in_i,
+      rst_n_i   => rst_n_i,
+      d_ready_o => freq_valid_o,
+      d_p_i     => gate_pulse,
+      q_p_o     => gate_pulse_synced);
+
+  end generate gen_internal_timebase;
+
+  gen_external_timebase : if(g_with_internal_timebase = false) generate
+
+    U_Sync_Gate : gc_pulse_synchronizer
+    port map (
+      clk_in_i  => clk_sys_i,
+      clk_out_i => clk_in_i,
+      rst_n_i   => rst_n_i,
+      d_ready_o => freq_valid_o,
+      d_p_i     => pps_p1_i,
+      q_p_o     => gate_pulse_synced);
+
+  end generate gen_external_timebase;
+
+
+  p_freq_counter : process (clk_in_i, rst_n_i)
+  begin
+    if rst_n_i = '0' then               -- asynchronous reset (active low)
+      cntr_meas <= (others => '0');
+      freq_reg  <= (others => '0');
+    elsif rising_edge(clk_in_i) then
+      
+      if(gate_pulse_synced = '1') then
+        freq_reg  <= std_logic_vector(cntr_meas);
+        cntr_meas <= (others => '0');
+      else
+        cntr_meas <= cntr_meas + 1;
+      end if;
+    end if;
+  end process p_freq_counter;
+
+  freq_o <= freq_reg;
+end behavioral;
+
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd
new file mode 100644
index 000000000..1707450d1
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd
@@ -0,0 +1,134 @@
+-------------------------------------------------------------------------------
+-- Title      : Pulse synchronizer
+-- Project    : General Cores Library 
+-------------------------------------------------------------------------------
+-- File       : gc_pulse_synchronizer.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2012-01-10
+-- Last update: 2012-08-29
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Full feedback pulse synchronizer (works independently of the
+-- input/output clock domain frequency ratio)
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2012-01-12  1.0      twlostow        Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.gencores_pkg.all;
+
+entity gc_pulse_synchronizer is
+  
+  port (
+    -- pulse input clock
+    clk_in_i  : in  std_logic;
+    -- pulse output clock
+    clk_out_i : in  std_logic;
+    -- system reset (clk_in_i domain)
+    rst_n_i   : in  std_logic;
+    -- pulse input ready (clk_in_i domain). When HI, a pulse coming to d_p_i will be
+    -- correctly transferred to q_p_o.
+    d_ready_o : out std_logic;
+    -- pulse input (clk_in_i domain)
+    d_p_i     : in  std_logic;
+    -- pulse output (clk_out_i domain)
+    q_p_o     : out std_logic);
+
+end gc_pulse_synchronizer;
+
+architecture rtl of gc_pulse_synchronizer is
+
+  constant c_sync_stages : integer := 3;
+
+  signal ready, d_p_d0 : std_logic;
+
+  signal in_ext, out_ext : std_logic;
+  signal out_feedback    : std_logic;
+
+  signal d_in2out : std_logic_vector(c_sync_stages-1 downto 0);
+  signal d_out2in : std_logic_vector(c_sync_stages-1 downto 0);
+
+begin  -- rtl
+
+  process(clk_out_i, rst_n_i)
+  begin
+    if rst_n_i = '0' then
+      d_in2out <= (others => '0');
+      out_ext <= '0';
+    elsif rising_edge(clk_out_i) then
+      d_in2out <= d_in2out(c_sync_stages-2 downto 0) & in_ext;
+      out_ext <= d_in2out(c_sync_stages-1);
+    end if;
+  end process;
+
+
+  process(clk_in_i, rst_n_i)
+  begin
+    if rst_n_i = '0' then
+      d_out2in <= (others => '0');
+    elsif rising_edge(clk_in_i) then
+      d_out2in <= d_out2in(c_sync_stages-2 downto 0) & out_ext;
+    end if;
+  end process;
+
+  out_feedback <= d_out2in(c_sync_stages-1);
+
+  p_input_ack : process(clk_in_i, rst_n_i)
+  begin
+    if rst_n_i = '0' then
+      ready  <= '1';
+      in_ext <= '0';
+      d_p_d0 <= '0';
+    elsif rising_edge(clk_in_i) then
+
+      d_p_d0 <= d_p_i;
+      
+      if(ready = '1' and d_p_i = '1' and d_p_d0 = '0') then
+        in_ext <= '1';
+        ready  <= '0';
+      elsif(in_ext = '1' and out_feedback = '1') then
+        in_ext <= '0';
+      elsif(in_ext = '0' and out_feedback = '0') then
+        ready <= '1';
+      end if;
+    end if;
+  end process;
+
+  p_drive_output : process(clk_out_i, rst_n_i)
+  begin
+    if rst_n_i = '0' then
+      q_p_o <= '0';
+    elsif rising_edge(clk_out_i) then
+      q_p_o <= not out_ext and d_in2out(c_sync_stages-1);
+    end if;
+  end process;
+
+  d_ready_o <= ready;
+
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd
new file mode 100644
index 000000000..280c72bd8
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd
@@ -0,0 +1,132 @@
+-------------------------------------------------------------------------------
+-- Title      : Pulse synchronizer
+-- Project    : General Cores Library 
+-------------------------------------------------------------------------------
+-- File       : gc_pulse_synchronizer2.vhd
+-- Author     : Tomasz Wlostowski, Wesley Terpstra
+-- Company    : CERN BE-CO-HT
+-- Created    : 2012-01-10
+-- Last update: 2012-08-29
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Full feedback pulse synchronizer (works independently of the
+-- input/output clock domain frequency ratio)
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2012-01-12  1.0      twlostow        Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.gencores_pkg.all;
+
+entity gc_pulse_synchronizer2 is
+  port (
+    -- pulse input clock
+    clk_in_i    : in  std_logic;
+    rst_in_n_i  : in  std_logic;
+    -- pulse output clock
+    clk_out_i   : in  std_logic;
+    rst_out_n_i : in  std_logic;
+    
+    -- pulse input ready (clk_in_i domain). When HI, a pulse coming to d_p_i will be
+    -- correctly transferred to q_p_o.
+    d_ready_o : out std_logic;
+    -- pulse input (clk_in_i domain)
+    d_p_i     : in  std_logic;
+    -- pulse output (clk_out_i domain)
+    q_p_o     : out std_logic);
+
+end gc_pulse_synchronizer2;
+
+architecture rtl of gc_pulse_synchronizer2 is
+
+  constant c_sync_stages : integer := 3;
+
+  signal ready, d_p_d0 : std_logic;
+
+  signal in_ext, out_ext : std_logic;
+  signal out_feedback    : std_logic;
+
+  signal d_in2out : std_logic_vector(c_sync_stages-1 downto 0);
+  signal d_out2in : std_logic_vector(c_sync_stages-1 downto 0);
+
+begin  -- rtl
+
+  process(clk_out_i, rst_out_n_i)
+  begin
+    if rst_out_n_i = '0' then
+      d_in2out <= (others => '0');
+      out_ext <= '0';
+    elsif rising_edge(clk_out_i) then
+      d_in2out <= d_in2out(c_sync_stages-2 downto 0) & in_ext;
+      out_ext <= d_in2out(c_sync_stages-1);
+    end if;
+  end process;
+
+
+  process(clk_in_i, rst_in_n_i)
+  begin
+    if rst_in_n_i = '0' then
+      d_out2in <= (others => '0');
+    elsif rising_edge(clk_in_i) then
+      d_out2in <= d_out2in(c_sync_stages-2 downto 0) & out_ext;
+    end if;
+  end process;
+
+  out_feedback <= d_out2in(c_sync_stages-1);
+
+  p_input_ack : process(clk_in_i, rst_in_n_i)
+  begin
+    if rst_in_n_i = '0' then
+      ready  <= '1';
+      in_ext <= '0';
+      d_p_d0 <= '0';
+    elsif rising_edge(clk_in_i) then
+
+      d_p_d0 <= d_p_i;
+      
+      if(ready = '1' and d_p_i = '1' and d_p_d0 = '0') then
+        in_ext <= not in_ext;
+        ready  <= '0';
+      elsif(in_ext = out_feedback) then
+        ready <= '1';
+      end if;
+    end if;
+  end process;
+
+  p_drive_output : process(clk_out_i, rst_out_n_i)
+  begin
+    if rst_out_n_i = '0' then
+      q_p_o <= '0';
+    elsif rising_edge(clk_out_i) then
+      q_p_o <= out_ext xor d_in2out(c_sync_stages-1);
+    end if;
+  end process;
+
+  d_ready_o <= ready;
+
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_reset.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_reset.vhd
new file mode 100644
index 000000000..e4fa0a493
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_reset.vhd
@@ -0,0 +1,87 @@
+-------------------------------------------------------------------------------
+-- Title      : Reset synchronizer and generator
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : gc_reset.vhd
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2012-2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity gc_reset is
+  generic(
+    g_clocks    : natural := 1;
+    g_logdelay  : natural := 10;
+    g_syncdepth : natural := 3);
+  port(
+    free_clk_i : in  std_logic;
+    locked_i   : in  std_logic := '1'; -- All the PLL locked signals ANDed together
+    clks_i     : in  std_logic_vector(g_clocks-1 downto 0);
+    rstn_o     : out std_logic_vector(g_clocks-1 downto 0));
+end gc_reset;
+
+architecture rtl of gc_reset is
+  subtype t_shifter is std_logic_vector(g_syncdepth-1 downto 0);
+  type t_shifters is array(natural range <>) of t_shifter;
+  
+  signal shifters : t_shifters(g_clocks-1 downto 0) := (others => (others => '0')); -- start reset
+  signal locked_count : unsigned(g_logdelay-1 downto 0) := (others => '0');
+  signal master_rstn : std_logic := '0';
+begin
+  lock : process(free_clk_i, locked_i)
+    constant locked_done : unsigned(g_logdelay-1 downto 0) := (others => '1');
+  begin
+    -- Asynchronous reset
+    if locked_i = '0' then
+      master_rstn <= '0';
+      locked_count <= (others => '0');
+    else
+      if rising_edge(free_clk_i) then
+        if locked_count = locked_done then
+          master_rstn <= '1';
+        else
+          master_rstn <= '0';
+          locked_count <= locked_count + 1;
+        end if;
+      end if;
+    end if;
+  end process;
+  
+  -- Generate the sync chains for each clock domain
+  syncs : for i in g_clocks-1 downto 0 generate
+    sync : process(clks_i(i))
+    begin
+      if rising_edge(clks_i(i)) then
+        shifters(i) <= master_rstn & shifters(i)(g_syncdepth-1 downto 1);
+      end if;
+    end process;
+  end generate;
+
+  -- Output the synchronized reset
+  rstn : for i in g_clocks-1 downto 0 generate
+    rstn_o(i) <= shifters(i)(0);
+  end generate;
+  
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd
new file mode 100644
index 000000000..6603c0297
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd
@@ -0,0 +1,125 @@
+-------------------------------------------------------------------------------
+-- Title      : Synchronizer chain
+-- Project    : White Rabbit 
+-------------------------------------------------------------------------------
+-- File       : gc_sync_ffs.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-Co-HT
+-- Created    : 2010-06-14
+-- Last update: 2017-02-03
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'87
+-------------------------------------------------------------------------------
+-- Description: Synchronizer chain and edge detector.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2009 - 2017 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2010-06-14  1.0      twlostow        Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity gc_sync_ffs is
+  generic(
+    g_sync_edge : string := "positive"
+    );
+  port(
+    clk_i    : in  std_logic;  -- clock from the destination clock domain
+    rst_n_i  : in  std_logic;           -- reset
+    data_i   : in  std_logic;           -- async input
+    synced_o : out std_logic;           -- synchronized output
+    npulse_o : out std_logic;  -- negative edge detect output (single-clock
+    -- pulse)
+    ppulse_o : out std_logic   -- positive edge detect output (single-clock
+   -- pulse)
+    );
+end gc_sync_ffs;
+
+-- make Altera Quartus quiet regarding unknown attributes:
+-- altera message_off 10335
+
+architecture behavioral of gc_sync_ffs is
+  signal sync0, sync1, sync2 : std_logic;
+
+  attribute shreg_extract : string;
+  attribute shreg_extract of sync0  : signal is "no";
+  attribute shreg_extract of sync1  : signal is "no";
+  attribute shreg_extract of sync2  : signal is "no";
+
+  attribute keep : string;
+  attribute keep of sync0  : signal is "true";
+  attribute keep of sync1  : signal is "true";
+
+  -- synchronizer attribute for Vivado
+  attribute ASYNC_REG : string;
+  attribute ASYNC_REG of sync0 : signal is "true";
+  attribute ASYNC_REG of sync1 : signal is "true";
+  attribute ASYNC_REG of sync2 : signal is "true";
+
+begin
+
+
+  sync_posedge : if (g_sync_edge = "positive") generate
+    process(clk_i, rst_n_i)
+    begin
+      if(rst_n_i = '0') then
+        sync0    <= '0';
+        sync1    <= '0';
+        sync2    <= '0';
+        synced_o <= '0';
+        npulse_o <= '0';
+        ppulse_o <= '0';
+      elsif rising_edge(clk_i) then
+        sync0    <= data_i;
+        sync1    <= sync0;
+        sync2    <= sync1;
+        synced_o <= sync1;
+        npulse_o <= sync2 and not sync1;
+        ppulse_o <= not sync2 and sync1;
+      end if;
+    end process;
+  end generate sync_posedge;
+
+  sync_negedge : if(g_sync_edge = "negative") generate
+    process(clk_i, rst_n_i)
+    begin
+      if(rst_n_i = '0') then
+        sync0    <= '0';
+        sync1    <= '0';
+        sync2    <= '0';
+        synced_o <= '0';
+        npulse_o <= '0';
+        ppulse_o <= '0';
+      elsif falling_edge(clk_i) then
+        sync0    <= data_i;
+        sync1    <= sync0;
+        sync2    <= sync1;
+        synced_o <= sync1;
+        npulse_o <= sync2 and not sync1;
+        ppulse_o <= not sync2 and sync1;
+      end if;
+    end process;
+  end generate sync_negedge;
+  
+end behavioral;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_sync_register.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_sync_register.vhd
new file mode 100644
index 000000000..8d43ef443
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_sync_register.vhd
@@ -0,0 +1,88 @@
+-------------------------------------------------------------------------------
+-- Title      : Parametrized synchronizer
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : gc_sync_register.vhd
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2014-2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+--  Modifications:
+--      2016-08-24: by Jan Pospisil (j.pospisil@cern.ch)
+--          * added ASYNC_REG attribute for better timing analysis/simulation
+--            in Xilinx tools
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity gc_sync_register is
+  generic (
+    g_width : integer);
+  port (
+    clk_i     : in  std_logic;
+    rst_n_a_i : in  std_logic;
+    d_i       : in  std_logic_vector(g_width-1 downto 0);
+    q_o       : out std_logic_vector(g_width-1 downto 0));
+
+end gc_sync_register;
+
+-- make Altera Quartus quiet regarding unknown attributes:
+-- altera message_off 10335
+
+architecture rtl of gc_sync_register is
+
+  signal gc_sync_register_in : std_logic_vector(g_width-1 downto 0);
+  signal sync0, sync1        : std_logic_vector(g_width-1 downto 0);
+
+  attribute shreg_extract                        : string;
+  attribute shreg_extract of gc_sync_register_in : signal is "no";
+  attribute shreg_extract of sync0               : signal is "no";
+  attribute shreg_extract of sync1               : signal is "no";
+
+  attribute keep                        : string;
+  attribute keep of gc_sync_register_in : signal is "true";
+  attribute keep of sync0               : signal is "true";
+  attribute keep of sync1               : signal is "true";
+  
+  attribute async_reg                        : string;
+  attribute async_reg of gc_sync_register_in : signal is "true";
+  attribute async_reg of sync0               : signal is "true";
+  attribute async_reg of sync1               : signal is "true";
+
+begin
+
+  process(clk_i, rst_n_a_i)
+  begin
+    if(rst_n_a_i = '0') then
+      sync1 <= (others => '0');
+      sync0 <= (others => '0');
+    elsif rising_edge(clk_i) then
+      sync0 <= gc_sync_register_in;
+      sync1 <= sync0;
+    end if;
+  end process;
+
+  gc_sync_register_in <= d_i;
+  q_o                 <= sync1;
+  
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gencores_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gencores_pkg.vhd
new file mode 100644
index 000000000..4e6d39fe7
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gencores_pkg.vhd
@@ -0,0 +1,674 @@
+-------------------------------------------------------------------------------
+-- Title      : General cores VHDL package
+-- Project    : General Cores library
+-------------------------------------------------------------------------------
+-- File       : gencores_pkg.vhd
+-- Author     : Tomasz Wlostowski
+--              Theodor-Adrian Stana
+--              Matthieu Cattin
+--              Dimitrios Lampridis
+-- Company    : CERN
+-- Created    : 2009-09-01
+-- Last update: 2017-10-11
+-- Platform   : FPGA-generic
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Description:
+-- Package incorporating simple VHDL modules and functions, which are used
+-- in the WR and other OHWR projects.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2009-2016 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.genram_pkg.all;
+
+package gencores_pkg is
+
+  --============================================================================
+  -- Component instantiations
+  --============================================================================
+
+  ------------------------------------------------------------------------------
+  -- Pulse extender
+  ------------------------------------------------------------------------------
+  component gc_extend_pulse
+    generic (
+      g_width : natural);
+    port (
+      clk_i      : in  std_logic;
+      rst_n_i    : in  std_logic;
+      pulse_i    : in  std_logic;
+      extended_o : out std_logic);
+  end component;
+
+  ------------------------------------------------------------------------------
+  -- CRC generator
+  ------------------------------------------------------------------------------
+  component gc_crc_gen
+    generic (
+      g_polynomial              : std_logic_vector       := x"04C11DB7";
+      g_init_value              : std_logic_vector       := x"ffffffff";
+      g_residue                 : std_logic_vector       := x"38fb2284";
+      g_data_width              : integer range 2 to 256 := 16;
+      g_half_width              : integer range 2 to 256 := 8;
+      g_sync_reset              : integer range 0 to 1   := 1;
+      g_dual_width              : integer range 0 to 1   := 0;
+      g_registered_match_output : boolean                := true;
+      g_registered_crc_output   : boolean                := true);
+    port (
+      clk_i     : in  std_logic;
+      rst_i     : in  std_logic;
+      en_i      : in  std_logic;
+      half_i    : in  std_logic;
+      restart_i : in  std_logic := '0';
+      data_i    : in  std_logic_vector(g_data_width - 1 downto 0);
+      match_o   : out std_logic;
+      crc_o     : out std_logic_vector(g_polynomial'length - 1 downto 0));
+  end component;
+
+  ------------------------------------------------------------------------------
+  -- Moving average
+  ------------------------------------------------------------------------------
+  component gc_moving_average
+    generic (
+      g_data_width : natural;
+      g_avg_log2   : natural range 1 to 8);
+    port (
+      rst_n_i    : in  std_logic;
+      clk_i      : in  std_logic;
+      din_i      : in  std_logic_vector(g_data_width-1 downto 0);
+      dout_o     : out std_logic_vector(g_data_width+g_avg_log2-1 downto 0);
+      dout_stb_o : out std_logic);
+  end component;
+
+  ------------------------------------------------------------------------------
+  -- Delay line
+  ------------------------------------------------------------------------------
+  component gc_delay_line
+    generic (
+      g_delay : integer;
+      g_width : integer);
+    port (
+      clk_i   : in  std_logic;
+      rst_n_i : in  std_logic;
+      d_i     : in  std_logic_vector(g_width -1 downto 0);
+      q_o     : out std_logic_vector(g_width -1 downto 0);
+      ready_o : out std_logic);
+  end component;
+
+  ------------------------------------------------------------------------------
+  -- PI controller
+  ------------------------------------------------------------------------------
+  component gc_dual_pi_controller
+    generic (
+      g_error_bits          : integer;
+      g_dacval_bits         : integer;
+      g_output_bias         : integer;
+      g_integrator_fracbits : integer;
+      g_integrator_overbits : integer;
+      g_coef_bits           : integer);
+    port (
+      clk_sys_i         : in  std_logic;
+      rst_n_sysclk_i    : in  std_logic;
+      phase_err_i       : in  std_logic_vector(g_error_bits-1 downto 0);
+      phase_err_stb_p_i : in  std_logic;
+      freq_err_i        : in  std_logic_vector(g_error_bits-1 downto 0);
+      freq_err_stb_p_i  : in  std_logic;
+      mode_sel_i        : in  std_logic;
+      dac_val_o         : out std_logic_vector(g_dacval_bits-1 downto 0);
+      dac_val_stb_p_o   : out std_logic;
+      pll_pcr_enable_i  : in  std_logic;
+      pll_pcr_force_f_i : in  std_logic;
+      pll_fbgr_f_kp_i   : in  std_logic_vector(g_coef_bits-1 downto 0);
+      pll_fbgr_f_ki_i   : in  std_logic_vector(g_coef_bits-1 downto 0);
+      pll_pbgr_p_kp_i   : in  std_logic_vector(g_coef_bits-1 downto 0);
+      pll_pbgr_p_ki_i   : in  std_logic_vector(g_coef_bits-1 downto 0));
+  end component;
+
+  ------------------------------------------------------------------------------
+  -- Serial 16-bit DAC interface (SPI/QSPI/MICROWIRE compatible)
+  ------------------------------------------------------------------------------
+  component gc_serial_dac
+    generic (
+      g_num_data_bits  : integer;
+      g_num_extra_bits : integer;
+      g_num_cs_select  : integer;
+      g_sclk_polarity  : integer);
+    port (
+      clk_i         : in  std_logic;
+      rst_n_i       : in  std_logic;
+      value_i       : in  std_logic_vector(g_num_data_bits-1 downto 0);
+      cs_sel_i      : in  std_logic_vector(g_num_cs_select-1 downto 0);
+      load_i        : in  std_logic;
+      sclk_divsel_i : in  std_logic_vector(2 downto 0);
+      dac_cs_n_o    : out std_logic_vector(g_num_cs_select-1 downto 0);
+      dac_sclk_o    : out std_logic;
+      dac_sdata_o   : out std_logic;
+      busy_o        : out std_logic);
+  end component;
+
+  ------------------------------------------------------------------------------
+  -- Synchronisation FF chain
+  ------------------------------------------------------------------------------
+  component gc_sync_ffs
+    generic (
+      g_sync_edge : string := "positive");
+    port (
+      clk_i    : in  std_logic;
+      rst_n_i  : in  std_logic;
+      data_i   : in  std_logic;
+      synced_o : out std_logic;
+      npulse_o : out std_logic;
+      ppulse_o : out std_logic);
+  end component;
+
+  ------------------------------------------------------------------------------
+  -- Pulse synchroniser
+  ------------------------------------------------------------------------------
+  component gc_pulse_synchronizer
+    port (
+      clk_in_i  : in  std_logic;
+      clk_out_i : in  std_logic;
+      rst_n_i   : in  std_logic;
+      d_ready_o : out std_logic;
+      d_p_i     : in  std_logic;
+      q_p_o     : out std_logic);
+  end component;
+
+  ------------------------------------------------------------------------------
+  -- Pulse synchroniser (with reset from both clock domains)
+  ------------------------------------------------------------------------------
+  component gc_pulse_synchronizer2 is
+    port (
+      clk_in_i    : in  std_logic;
+      rst_in_n_i  : in  std_logic;
+      clk_out_i   : in  std_logic;
+      rst_out_n_i : in  std_logic;
+      d_ready_o   : out std_logic;
+      d_p_i       : in  std_logic;
+      q_p_o       : out std_logic);
+  end component;
+
+  ------------------------------------------------------------------------------
+  -- Frequency meter
+  ------------------------------------------------------------------------------
+  component gc_frequency_meter
+    generic (
+      g_with_internal_timebase : boolean;
+      g_clk_sys_freq           : integer;
+      g_counter_bits           : integer);
+    port (
+      clk_sys_i    : in  std_logic;
+      clk_in_i     : in  std_logic;
+      rst_n_i      : in  std_logic;
+      pps_p1_i     : in  std_logic;
+      freq_o       : out std_logic_vector(g_counter_bits-1 downto 0);
+      freq_valid_o : out std_logic);
+  end component;
+
+  ------------------------------------------------------------------------------
+  -- Time-division multiplexer with round robin arbitration
+  ------------------------------------------------------------------------------
+  component gc_arbitrated_mux
+    generic (
+      g_num_inputs : integer;
+      g_width      : integer);
+    port (
+      clk_i        : in  std_logic;
+      rst_n_i      : in  std_logic;
+      d_i          : in  std_logic_vector(g_num_inputs * g_width-1 downto 0);
+      d_valid_i    : in  std_logic_vector(g_num_inputs-1 downto 0);
+      d_req_o      : out std_logic_vector(g_num_inputs-1 downto 0);
+      q_o          : out std_logic_vector(g_width-1 downto 0);
+      q_valid_o    : out std_logic;
+      q_input_id_o : out std_logic_vector(f_log2_size(g_num_inputs)-1 downto 0));
+  end component;
+
+  ------------------------------------------------------------------------------
+  -- Power-On reset generator
+  ------------------------------------------------------------------------------
+  component gc_reset is
+    generic(
+      g_clocks    : natural := 1;
+      g_logdelay  : natural := 10;
+      g_syncdepth : natural := 3);
+    port(
+      free_clk_i : in  std_logic;
+      locked_i   : in  std_logic := '1';  -- All the PLL locked signals ANDed together
+      clks_i     : in  std_logic_vector(g_clocks-1 downto 0);
+      rstn_o     : out std_logic_vector(g_clocks-1 downto 0));
+  end component;
+
+  ------------------------------------------------------------------------------
+  -- Power-On reset generator of synchronous single reset from multiple
+  -- asynchronous input reset signals
+  ------------------------------------------------------------------------------
+  component gc_single_reset_gen is
+    generic(
+      g_out_reg_depth     : natural :=2;
+      g_rst_in_num        : natural :=2);
+    port (
+      clk_i               : in std_logic;
+      rst_signals_n_a_i   : in std_logic_vector(g_rst_in_num-1 downto 0);
+      rst_n_o             : out std_logic
+    );
+  end component;
+
+  ------------------------------------------------------------------------------
+  -- Round robin arbiter
+  ------------------------------------------------------------------------------
+  component gc_rr_arbiter
+    generic (
+      g_size : integer);
+    port (
+      clk_i        : in  std_logic;
+      rst_n_i      : in  std_logic;
+      req_i        : in  std_logic_vector(g_size-1 downto 0);
+      grant_o      : out std_logic_vector(g_size-1 downto 0);
+      grant_comb_o : out std_logic_vector(g_size-1 downto 0));
+  end component;
+
+  ------------------------------------------------------------------------------
+  -- Pack or unpack words
+  ------------------------------------------------------------------------------
+  component gc_word_packer
+    generic (
+      g_input_width  : integer;
+      g_output_width : integer);
+    port (
+      clk_i     : in  std_logic;
+      rst_n_i   : in  std_logic;
+      d_i       : in  std_logic_vector(g_input_width-1 downto 0);
+      d_valid_i : in  std_logic;
+      d_req_o   : out std_logic;
+      flush_i   : in  std_logic := '0';
+      q_o       : out std_logic_vector(g_output_width-1 downto 0);
+      q_valid_o : out std_logic;
+      q_req_i   : in  std_logic);
+  end component;
+
+  ------------------------------------------------------------------------------
+  -- Adder
+  ------------------------------------------------------------------------------
+  component gc_big_adder is
+    generic(
+      g_data_bits : natural := 64;
+      g_parts     : natural := 4);
+    port(
+      clk_i   : in  std_logic;
+      stall_i : in  std_logic := '0';
+      a_i     : in  std_logic_vector(g_data_bits-1 downto 0);
+      b_i     : in  std_logic_vector(g_data_bits-1 downto 0);
+      c_i     : in  std_logic := '0';
+      c1_o    : out std_logic;
+      x2_o    : out std_logic_vector(g_data_bits-1 downto 0);
+      c2_o    : out std_logic);
+  end component;
+
+  ------------------------------------------------------------------------------
+  -- I2C slave
+  ------------------------------------------------------------------------------
+  constant c_i2cs_idle      : std_logic_vector(1 downto 0) := "00";
+  constant c_i2cs_addr_good : std_logic_vector(1 downto 0) := "01";
+  constant c_i2cs_rd_done   : std_logic_vector(1 downto 0) := "10";
+  constant c_i2cs_wr_done   : std_logic_vector(1 downto 0) := "11";
+
+  component gc_i2c_slave is
+    generic
+      (
+        -- Length of glitch filter
+        -- 0 - SCL and SDA lines are passed only through synchronizer
+        -- 1 - one clk_i glitches filtered
+        -- 2 - two clk_i glitches filtered
+        g_gf_len        : natural := 0;
+        g_auto_addr_ack : boolean := FALSE
+        );
+    port
+      (
+        -- Clock, reset ports
+        clk_i   : in std_logic;
+        rst_n_i : in std_logic;
+
+        -- I2C lines
+        scl_i    : in  std_logic;
+        scl_o    : out std_logic;
+        scl_en_o : out std_logic;
+        sda_i    : in  std_logic;
+        sda_o    : out std_logic;
+        sda_en_o : out std_logic;
+
+        -- Slave address
+        i2c_addr_i : in std_logic_vector(6 downto 0);
+
+        -- ACK input, should be set after done_p_o = '1'
+        -- (note that the bit is reversed wrt I2C ACK bit)
+        -- '1' - ACK
+        -- '0' - NACK
+        ack_i : in std_logic;
+
+        -- Byte to send, should be loaded while done_p_o = '1'
+        tx_byte_i : in std_logic_vector(7 downto 0);
+
+        -- Received byte, valid after done_p_o = '1'
+        rx_byte_o : out std_logic_vector(7 downto 0);
+
+        -- Pulse outputs signaling various I2C actions
+        -- Start and stop conditions
+        i2c_sta_p_o   : out std_logic;
+        i2c_sto_p_o   : out std_logic;
+        -- Received address corresponds addr_i
+        addr_good_p_o : out std_logic;
+        -- Read and write done
+        r_done_p_o    : out std_logic;
+        w_done_p_o    : out std_logic;
+
+        -- I2C bus operation, set after address detection
+        -- '0' - write
+        -- '1' - read
+        op_o : out std_logic
+        );
+  end component gc_i2c_slave;
+
+  ------------------------------------------------------------------------------
+  -- Glitch filter
+  ------------------------------------------------------------------------------
+  component gc_glitch_filt is
+    generic
+      (
+        -- Length of glitch filter:
+        -- g_len = 1 => data width should be > 1 clk_i cycle
+        -- g_len = 2 => data width should be > 2 clk_i cycle
+        -- etc.
+        g_len : natural := 4
+        );
+    port
+      (
+        clk_i   : in std_logic;
+        rst_n_i : in std_logic;
+
+        -- Data input
+        dat_i : in std_logic;
+
+        -- Data output
+        -- latency: g_len+1 clk_i cycles
+        dat_o : out std_logic
+        );
+  end component gc_glitch_filt;
+
+  ------------------------------------------------------------------------------
+  -- Dynamic glitch filter
+  ------------------------------------------------------------------------------
+  component gc_dyn_glitch_filt is
+    generic
+      (
+        -- Number of bit of the glitch filter length input
+        g_len_width : natural := 8
+        );
+    port
+      (
+        clk_i   : in std_logic;
+        rst_n_i : in std_logic;
+
+        -- Glitch filter length
+        len_i : in std_logic_vector(g_len_width-1 downto 0);
+
+        -- Data input
+        dat_i : in std_logic;
+
+        -- Data output
+        -- latency: g_len+1 clk_i cycles
+        dat_o : out std_logic
+        );
+  end component gc_dyn_glitch_filt;
+
+  ------------------------------------------------------------------------------
+  -- FSM Watchdog Timer
+  ------------------------------------------------------------------------------
+  component gc_fsm_watchdog is
+    generic
+      (
+        -- Maximum value of watchdog timer in clk_i cycles
+        g_wdt_max : positive := 65535
+        );
+    port
+      (
+        -- Clock and active-low reset line
+        clk_i   : in std_logic;
+        rst_n_i : in std_logic;
+
+        -- Active-high watchdog timer reset line, synchronous to clk_i
+        wdt_rst_i : in std_logic;
+
+        -- Active-high reset output, synchronous to clk_i
+        fsm_rst_o : out std_logic
+        );
+  end component gc_fsm_watchdog;
+
+  ------------------------------------------------------------------------------
+  -- Bicolor LED controller
+  ------------------------------------------------------------------------------
+  constant c_led_red       : std_logic_vector(1 downto 0) := "10";
+  constant c_led_green     : std_logic_vector(1 downto 0) := "01";
+  constant c_led_red_green : std_logic_vector(1 downto 0) := "11";
+  constant c_led_off       : std_logic_vector(1 downto 0) := "00";
+
+  component gc_bicolor_led_ctrl
+    generic(
+      g_nb_column    : natural := 4;
+      g_nb_line      : natural := 2;
+      g_clk_freq     : natural := 125000000;  -- in Hz
+      g_refresh_rate : natural := 250         -- in Hz
+      );
+    port
+      (
+        rst_n_i         : in  std_logic;
+        clk_i           : in  std_logic;
+        led_intensity_i : in  std_logic_vector(6 downto 0);
+        led_state_i     : in  std_logic_vector((g_nb_line * g_nb_column * 2) - 1 downto 0);
+        column_o        : out std_logic_vector(g_nb_column - 1 downto 0);
+        line_o          : out std_logic_vector(g_nb_line - 1 downto 0);
+        line_oen_o      : out std_logic_vector(g_nb_line - 1 downto 0)
+        );
+  end component;
+
+  component gc_sync_register is
+    generic (
+      g_width : integer);
+    port (
+      clk_i     : in  std_logic;
+      rst_n_a_i : in  std_logic;
+      d_i       : in  std_logic_vector(g_width-1 downto 0);
+      q_o       : out std_logic_vector(g_width-1 downto 0));
+  end component gc_sync_register;
+
+  component gc_async_signals_input_stage is
+    generic (
+      g_signal_num                 : integer;
+      g_extended_pulse_width       : integer;
+      g_dglitch_filter_len         : integer);
+    port (
+      clk_i                        : in std_logic;
+      rst_n_i                      : in std_logic;
+      signals_a_i                  : in  std_logic_vector(g_signal_num-1 downto 0);
+      config_active_i              : in  std_logic_vector(g_signal_num-1 downto 0);
+      signals_o                    : out std_logic_vector(g_signal_num-1 downto 0);
+      signals_p1_o                 : out std_logic_vector(g_signal_num-1 downto 0);
+      signals_pN_o                 : out std_logic_vector(g_signal_num-1 downto 0));
+  end component;
+
+  --============================================================================
+  -- Procedures and functions
+  --============================================================================
+  procedure f_rr_arbitrate (
+    signal req       : in  std_logic_vector;
+    signal pre_grant : in  std_logic_vector;
+    signal grant     : out std_logic_vector);
+  function f_onehot_decode(x : std_logic_vector; size : integer) return std_logic_vector;
+
+  function f_big_ripple(a, b : std_logic_vector; c : std_logic) return std_logic_vector;
+  function f_gray_encode(x   : std_logic_vector) return std_logic_vector;
+  function f_gray_decode(x   : std_logic_vector; step : natural) return std_logic_vector;
+  function log2_ceil(N       : natural) return positive;
+
+  function f_bool2int (b : boolean) return natural;
+  function f_int2bool (n : natural) return boolean;
+
+end package;
+
+package body gencores_pkg is
+
+  ------------------------------------------------------------------------------
+  -- Simple round-robin arbiter:
+  --  req = requests (1 = pending request),
+  --  pre_grant = previous grant vector (1 cycle delay)
+  --  grant = new grant vector
+  ------------------------------------------------------------------------------
+  procedure f_rr_arbitrate (
+    signal req       : in  std_logic_vector;
+    signal pre_grant : in  std_logic_vector;
+    signal grant     : out std_logic_vector)is
+
+    variable reqs  : std_logic_vector(req'length - 1 downto 0);
+    variable gnts  : std_logic_vector(req'length - 1 downto 0);
+    variable gnt   : std_logic_vector(req'length - 1 downto 0);
+    variable gntM  : std_logic_vector(req'length - 1 downto 0);
+    variable zeros : std_logic_vector(req'length - 1 downto 0);
+
+  begin
+    zeros := (others => '0');
+
+    -- bit twiddling magic :
+    gnt  := req and std_logic_vector(unsigned(not req) + 1);
+    reqs := req and not (std_logic_vector(unsigned(pre_grant) - 1) or pre_grant);
+    gnts := reqs and std_logic_vector(unsigned(not reqs)+1);
+
+    if(reqs = zeros) then
+      gntM := gnt;
+    else
+      gntM := gnts;
+    end if;
+
+    if((req and pre_grant) = zeros) then
+      grant <= gntM;
+    else
+      grant <= pre_grant;
+    end if;
+
+  end f_rr_arbitrate;
+
+  function f_onehot_decode(x : std_logic_vector; size : integer) return std_logic_vector is
+  begin
+    for j in 0 to x'left loop
+      if x(j) /= '0' then
+        return std_logic_vector(to_unsigned(j, size));
+      end if;
+    end loop;  -- i
+    return std_logic_vector(to_unsigned(0, size));
+  end f_onehot_decode;
+
+
+
+  ------------------------------------------------------------------------------
+  -- Carry ripple
+  ------------------------------------------------------------------------------
+  function f_big_ripple(a, b : std_logic_vector; c : std_logic) return std_logic_vector is
+    constant len        : natural := a'length;
+    variable aw, bw, rw : std_logic_vector(len+1 downto 0);
+    variable x          : std_logic_vector(len downto 0);
+  begin
+    aw := "0" & a & c;
+    bw := "0" & b & c;
+    rw := std_logic_vector(unsigned(aw) + unsigned(bw));
+    x  := rw(len+1 downto 1);
+    return x;
+  end f_big_ripple;
+
+
+  ------------------------------------------------------------------------------
+  -- Gray encoder
+  ------------------------------------------------------------------------------
+  function f_gray_encode(x : std_logic_vector) return std_logic_vector is
+    variable o : std_logic_vector(x'length downto 0);
+  begin
+    o := (x & '0') xor ('0' & x);
+    return o(x'length downto 1);
+  end f_gray_encode;
+
+  ------------------------------------------------------------------------------
+  -- Gray decoder
+  --  call with step=1
+  ------------------------------------------------------------------------------
+  function f_gray_decode(x : std_logic_vector; step : natural) return std_logic_vector is
+    constant len : natural                          := x'length;
+    alias y      : std_logic_vector(len-1 downto 0) is x;
+    variable z   : std_logic_vector(len-1 downto 0) := (others => '0');
+  begin
+    if step >= len then
+      return y;
+    else
+      z(len-step-1 downto 0) := y(len-1 downto step);
+      return f_gray_decode(y xor z, step+step);
+    end if;
+  end f_gray_decode;
+
+  ------------------------------------------------------------------------------
+  -- Returns log of 2 of a natural number
+  ------------------------------------------------------------------------------
+  function log2_ceil(N : natural) return positive is
+  begin
+    if N <= 2 then
+      return 1;
+    elsif N mod 2 = 0 then
+      return 1 + log2_ceil(N/2);
+    else
+      return 1 + log2_ceil((N+1)/2);
+    end if;
+  end;
+
+  ------------------------------------------------------------------------------
+  -- Converts a boolean to natural integer (false -> 0, true -> 1)
+  ------------------------------------------------------------------------------
+  function f_bool2int (b : boolean) return natural is
+  begin
+    if b then
+      return 1;
+    else
+      return 0;
+    end if;
+  end;
+
+  ------------------------------------------------------------------------------
+  -- Converts a natural integer to boolean (0 -> false, any positive -> true)
+  ------------------------------------------------------------------------------
+  function f_int2bool (n : natural) return boolean is
+  begin
+    if n = 0 then
+      return false;
+    else
+      return true;
+    end if;
+  end;
+
+end gencores_pkg;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd
new file mode 100644
index 000000000..9158a4fdb
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd
@@ -0,0 +1,168 @@
+----------------------------------------------------------------------------
+----                                                                    ----
+----                                                                    ----
+---- This file is part of the srl_fifo project                          ----
+---- http://www.opencores.org/cores/srl_fifo                            ----
+----                                                                    ----
+---- Description                                                        ----
+---- Implementation of srl_fifo IP core according to                    ----
+---- srl_fifo IP core specification document.                           ----
+----                                                                    ----
+---- To Do:                                                             ----
+----    NA                                                              ----
+----                                                                    ----
+---- Author(s):                                                         ----
+----   Andrew Mulcock, amulcock@opencores.org                           ----
+----                                                                    ----
+---- Modified for WR Project by Tomasz Wlostowski                       ----
+----------------------------------------------------------------------------
+----                                                                    ----
+---- Copyright (C) 2008 Authors and OPENCORES.ORG                       ----
+----                                                                    ----
+---- This source file may be used and distributed without               ----
+---- restriction provided that this copyright statement is not          ----
+---- removed from the file and that any derivative work contains        ----
+---- the original copyright notice and the associated disclaimer.       ----
+----                                                                    ----
+---- This source file is free software; you can redistribute it         ----
+---- and/or modify it under the terms of the GNU Lesser General         ----
+---- Public License as published by the Free Software Foundation;       ----
+---- either version 2.1 of the License, or (at your option) any         ----
+---- later version.                                                     ----
+----                                                                    ----
+---- This source is distributed in the hope that it will be             ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied         ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR            ----
+---- PURPOSE. See the GNU Lesser General Public License for more        ----
+---- details.                                                           ----
+----                                                                    ----
+---- You should have received a copy of the GNU Lesser General          ----
+---- Public License along with this source; if not, download it         ----
+---- from http://www.opencores.org/lgpl.shtml                           ----
+----                                                                    ----
+----------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use ieee.NUMERIC_STD.all;
+
+use work.genram_pkg.all;
+
+entity generic_shiftreg_fifo is
+  generic (
+    g_data_width : integer := 128;
+    g_size       : integer := 32
+    );          
+  port (
+    rst_n_i : in std_logic := '1';
+    clk_i   : in std_logic;
+
+    d_i  : in  std_logic_vector(g_data_width-1 downto 0);
+    we_i : in  std_logic;
+    q_o  : out std_logic_vector(g_data_width-1 downto 0);
+    rd_i : in  std_logic;
+
+    full_o        : out std_logic;
+    almost_full_o : out std_logic;
+    q_valid_o     : out std_logic
+    );
+
+end generic_shiftreg_fifo;
+
+architecture rtl of generic_shiftreg_fifo is
+
+  component gc_shiftreg
+    generic (
+      g_size : integer);
+    port (
+      clk_i : in  std_logic;
+      en_i  : in  std_logic;
+      d_i   : in  std_logic;
+      q_o   : out std_logic;
+      a_i   : in  std_logic_vector(f_log2_size(g_size)-1 downto 0));
+  end component;
+
+  signal pointer : integer range 0 to g_size-1 := 0;
+
+  signal srl_addr            : std_logic_vector(f_log2_size(g_size)-1 downto 0) := (others => '0');
+  signal pointer_zero        : std_logic;
+  signal pointer_full        : std_logic;
+  signal pointer_almost_full : std_logic;
+  signal empty               : std_logic := '1';
+  signal valid_count         : std_logic;
+  signal do_write            : std_logic;
+begin
+
+-- Valid write, high when valid to write data to the store.
+
+  do_write <= '1' when (rd_i = '1' and we_i = '1')
+              or (we_i = '1' and pointer_full = '0') else '0';
+
+
+  gen_sregs : for i in 0 to g_data_width-1 generate
+    U_SRLx : gc_shiftreg
+      generic map (
+        g_size => g_size)
+      port map (
+        clk_i => clk_i,
+        en_i  => do_write,
+        d_i   => d_i(i),
+        q_o   => q_o(i),
+        a_i   => srl_addr);
+  end generate gen_sregs;
+
+  srl_addr <= std_logic_vector(to_unsigned(pointer, srl_addr'length));
+
+  p_empty_logic : process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        empty <= '1';
+      elsif empty = '1' and we_i = '1' then
+        empty <= '0';
+      elsif pointer_zero = '1' and rd_i = '1' and we_i = '0' then
+        empty <= '1';
+      end if;
+    end if;
+  end process;
+
+--      W       R       Action
+--      0       0       pointer <= pointer
+--      0       1       pointer <= pointer - 1  Read, but no write, so less data in counter
+--      1       0       pointer <= pointer + 1  Write, but no read, so more data in fifo
+--      1       1       pointer <= pointer              Read and write, so same number of words in fifo
+--
+  
+  valid_count <= '1' when (
+    (we_i = '1' and rd_i = '0' and pointer_full = '0' and empty = '0')
+    or
+    (we_i = '0' and rd_i = '1' and pointer_zero = '0')
+    ) else '0';
+
+  p_gen_address : process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        pointer <= 0;
+      elsif valid_count = '1' then
+        if we_i = '1' then
+          pointer <= pointer + 1;
+        else
+          pointer <= pointer - 1;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  -- Detect when pointer is zero and maximum
+  pointer_zero        <= '1' when pointer = 0                                else '0';
+  pointer_full        <= '1' when pointer = g_size - 1                       else '0';
+  pointer_almost_full <= '1' when pointer_full = '1' or pointer = g_size -3 or pointer = g_size - 2 else '0';
+
+
+  -- assign internal signals to outputs
+  full_o        <= pointer_full;
+  almost_full_o <= pointer_almost_full;
+  q_valid_o     <= not empty;
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd
new file mode 100644
index 000000000..bf24ea561
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd
@@ -0,0 +1,326 @@
+-------------------------------------------------------------------------------
+-- Title      : Parametrizable asynchronous FIFO (Generic version)
+-- Project    : Generics RAMs and FIFOs collection
+-------------------------------------------------------------------------------
+-- File       : generic_async_fifo.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2011-01-25
+-- Last update: 2014-07-31
+-- Platform   :
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Dual-clock asynchronous FIFO.
+-- - configurable data width and size
+-- - configurable full/empty/almost full/almost empty/word count signals
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011 CERN
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2011-01-25  1.0      twlostow        Created
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.genram_pkg.all;
+use work.gencores_pkg.all;
+
+entity inferred_async_fifo is
+
+  generic (
+    g_data_width : natural;
+    g_size       : natural;
+    g_show_ahead : boolean := false;
+
+    -- Read-side flag selection
+    g_with_rd_empty        : boolean := true;   -- with empty flag
+    g_with_rd_full         : boolean := false;  -- with full flag
+    g_with_rd_almost_empty : boolean := false;
+    g_with_rd_almost_full  : boolean := false;
+    g_with_rd_count        : boolean := false;  -- with words counter
+
+    g_with_wr_empty        : boolean := false;
+    g_with_wr_full         : boolean := true;
+    g_with_wr_almost_empty : boolean := false;
+    g_with_wr_almost_full  : boolean := false;
+    g_with_wr_count        : boolean := false;
+
+    g_almost_empty_threshold : integer;  -- threshold for almost empty flag
+    g_almost_full_threshold  : integer   -- threshold for almost full flag
+    );
+
+  port (
+    rst_n_i : in std_logic := '1';
+
+
+    -- write port
+    clk_wr_i : in std_logic;
+    d_i      : in std_logic_vector(g_data_width-1 downto 0);
+    we_i     : in std_logic;
+
+    wr_empty_o        : out std_logic;
+    wr_full_o         : out std_logic;
+    wr_almost_empty_o : out std_logic; -- TODO: assign
+    wr_almost_full_o  : out std_logic;
+    wr_count_o        : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
+
+    -- read port
+    clk_rd_i : in  std_logic;
+    q_o      : out std_logic_vector(g_data_width-1 downto 0);
+    rd_i     : in  std_logic;
+
+    rd_empty_o        : out std_logic;
+    rd_full_o         : out std_logic;
+    rd_almost_empty_o : out std_logic;
+    rd_almost_full_o  : out std_logic; -- TODO: assign
+    rd_count_o        : out std_logic_vector(f_log2_size(g_size)-1 downto 0)
+    );
+
+end inferred_async_fifo;
+
+
+architecture syn of inferred_async_fifo is
+
+  function f_bin2gray(bin : std_logic_vector) return std_logic_vector is
+  begin
+    return bin(bin'left) & (bin(bin'left-1 downto 0) xor bin(bin'left downto 1));
+  end f_bin2gray;
+
+  function f_gray2bin(gray : std_logic_vector) return std_logic_vector is
+    variable bin : std_logic_vector(gray'left downto 0);
+  begin
+    -- gray to binary
+    for i in 0 to gray'left loop
+      bin(i) := '0';
+      for j in i to gray'left loop
+        bin(i) := bin(i) xor gray(j);
+      end loop;  -- j
+    end loop;  -- i
+    return bin;
+  end f_gray2bin;
+
+  constant c_counter_bits : integer := f_log2_size(g_size) + 1;
+  subtype t_counter is std_logic_vector(c_counter_bits-1 downto 0);
+
+  type t_counter_block is record
+    bin, bin_next, gray, gray_next : t_counter;
+    bin_x, gray_x, gray_xm         : t_counter;
+  end record;
+
+  type   t_mem_type is array (0 to g_size-1) of std_logic_vector(g_data_width-1 downto 0);
+  signal mem : t_mem_type;
+
+  signal rcb, wcb                          : t_counter_block;
+
+  
+  signal full_int, empty_int               : std_logic;
+  signal almost_full_int, almost_empty_int : std_logic;
+  signal going_full                        : std_logic;
+
+  signal wr_count, rd_count : t_counter;
+  signal rd_int, we_int : std_logic;
+
+  signal wr_empty_xm, wr_empty_x : std_logic;
+  signal rd_full_xm, rd_full_x   : std_logic;
+
+  signal almost_full_x, almost_full_xm   : std_logic;
+  signal almost_empty_x, almost_empty_xm : std_logic;
+
+begin  -- syn
+
+  rd_int <= rd_i and not empty_int;
+  we_int <= we_i and not full_int;
+
+  p_mem_write : process(clk_wr_i)
+  begin
+    if rising_edge(clk_wr_i) then
+      if(we_int = '1') then
+        mem(to_integer(unsigned(wcb.bin(wcb.bin'left-1 downto 0)))) <= d_i;
+      end if;
+    end if;
+  end process;
+
+  p_mem_read : process(clk_rd_i)
+  begin
+    if rising_edge(clk_rd_i) then
+      if(rd_int = '1') then
+        q_o <= mem(to_integer(unsigned(rcb.bin(rcb.bin'left-1 downto 0))));
+      end if;
+    end if;
+  end process;
+
+  wcb.bin_next  <= std_logic_vector(unsigned(wcb.bin) + 1);
+  wcb.gray_next <= f_bin2gray(wcb.bin_next);
+
+  p_write_ptr : process(clk_wr_i, rst_n_i)
+  begin
+    if rst_n_i = '0' then
+      wcb.bin  <= (others => '0');
+      wcb.gray <= (others => '0');
+    elsif rising_edge(clk_wr_i) then
+      if(we_int = '1') then
+        wcb.bin  <= wcb.bin_next;
+        wcb.gray <= wcb.gray_next;
+      end if;
+    end if;
+  end process;
+
+  rcb.bin_next  <= std_logic_vector(unsigned(rcb.bin) + 1);
+  rcb.gray_next <= f_bin2gray(rcb.bin_next);
+
+  p_read_ptr : process(clk_rd_i, rst_n_i)
+  begin
+    if rst_n_i = '0' then
+      rcb.bin  <= (others => '0');
+      rcb.gray <= (others => '0');
+    elsif rising_edge(clk_rd_i) then
+      if(rd_int = '1') then
+        rcb.bin  <= rcb.bin_next;
+        rcb.gray <= rcb.gray_next;
+      end if;
+    end if;
+  end process;
+
+    U_Sync1: gc_sync_register
+    generic map (
+      g_width => c_counter_bits)
+    port map (
+      clk_i    => clk_wr_i,
+      rst_n_a_i  => rst_n_i,
+      d_i  => rcb.gray,
+      q_o => rcb.gray_x);
+
+    U_Sync2: gc_sync_register
+    generic map (
+      g_width => c_counter_bits)
+    port map (
+      clk_i    => clk_rd_i,
+      rst_n_a_i  => rst_n_i,
+      d_i   => wcb.gray,
+      q_o => wcb.gray_x);
+
+  wcb.bin_x <= f_gray2bin(wcb.gray_x);
+  rcb.bin_x <= f_gray2bin(rcb.gray_x);
+
+  p_gen_empty : process(clk_rd_i, rst_n_i)
+  begin
+    if rst_n_i = '0' then
+      empty_int <= '1';
+    elsif rising_edge (clk_rd_i) then
+      if(rcb.gray = wcb.gray_x or (rd_int = '1' and (wcb.gray_x = rcb.gray_next))) then
+        empty_int <= '1';
+      else
+        empty_int <= '0';
+      end if;
+    end if;
+  end process;
+
+  U_Sync_Empty: gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_wr_i,
+      rst_n_i  => rst_n_i,
+      data_i   => empty_int,
+      synced_o => wr_empty_x);
+
+  U_Sync_Full: gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_rd_i,
+      rst_n_i  => rst_n_i,
+      data_i   => full_int,
+      synced_o => rd_full_x);
+ 
+  
+
+  rd_empty_o <= empty_int;
+  wr_empty_o <= wr_empty_x;
+
+  p_gen_going_full : process(we_int, wcb, rcb)
+  begin
+    if ((wcb.bin (wcb.bin'left-1 downto 0) = rcb.bin_x(rcb.bin_x'left-1 downto 0))
+        and (wcb.bin(wcb.bin'left) /= rcb.bin_x(wcb.bin_x'left))) then
+      going_full <= '1';
+    elsif (we_int = '1'
+           and (wcb.bin_next(wcb.bin'left-1 downto 0) = rcb.bin_x(rcb.bin_x'left-1 downto 0))
+           and (wcb.bin_next(wcb.bin'left) /= rcb.bin_x(rcb.bin_x'left))) then
+      going_full <= '1';
+    else
+      going_full <= '0';
+    end if;
+  end process;
+
+  p_register_full : process(clk_wr_i, rst_n_i)
+  begin
+    if rst_n_i = '0' then
+      full_int <= '0';
+    elsif rising_edge (clk_wr_i) then
+      full_int <= going_full;
+    end if;
+  end process;
+
+  wr_full_o <= full_int;
+  rd_full_o <= rd_full_x;
+
+  p_reg_almost_full : process(clk_wr_i, rst_n_i)
+  begin
+    if rst_n_i = '0' then
+      almost_full_int <= '0';
+    elsif rising_edge(clk_wr_i) then
+      wr_count <= std_logic_vector(unsigned(wcb.bin) - unsigned(rcb.bin_x));
+      if (unsigned(wr_count) >= g_almost_full_threshold) then
+        almost_full_int <= '1';
+      else
+        almost_full_int <= '0';
+      end if;
+    end if;
+  end process;
+
+  U_Sync_AlmostFull: gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_rd_i,
+      rst_n_i  => rst_n_i,
+      data_i   => almost_full_int,
+      synced_o => almost_full_x);
+
+  wr_almost_full_o  <= almost_full_int;
+  rd_almost_full_o  <= almost_full_x;
+
+  p_reg_almost_empty : process(clk_rd_i, rst_n_i)
+  begin
+    if rst_n_i = '0' then
+      almost_empty_int <= '1';
+    elsif rising_edge(clk_rd_i) then
+      rd_count     <= std_logic_vector(unsigned(wcb.bin_x) - unsigned(rcb.bin));
+      if (unsigned(rd_count) <= g_almost_empty_threshold) then
+        almost_empty_int <= '1';
+      else
+        almost_empty_int <= '0';
+      end if;
+    end if;
+  end process;
+
+  U_Sync_AlmostEmpty: gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_wr_i,
+      rst_n_i  => rst_n_i,
+      data_i   => almost_empty_int,
+      synced_o => almost_empty_x);
+
+  rd_almost_empty_o <= almost_empty_int;
+  wr_almost_empty_o <= almost_empty_x;
+
+  wr_count_o <= std_logic_vector(wr_count(f_log2_size(g_size)-1 downto 0));
+  rd_count_o <= std_logic_vector(rd_count(f_log2_size(g_size)-1 downto 0));
+
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd
new file mode 100644
index 000000000..c70a83003
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd
@@ -0,0 +1,261 @@
+-------------------------------------------------------------------------------
+-- Title      : Parametrizable synchronous FIFO (Generic version)
+-- Project    : Generics RAMs and FIFOs collection
+-------------------------------------------------------------------------------
+-- File       : generic_sync_fifo_std.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2011-01-25
+-- Last update: 2017-02-03
+-- Platform   : 
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Single-clock FIFO. 
+-- - configurable data width and size
+-- - configurable full/empty/almost full/almost empty/word count signals
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011-2017 CERN
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2011-01-25  1.0      twlostow        Created
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.genram_pkg.all;
+
+entity inferred_sync_fifo is
+
+  generic (
+    g_data_width : natural;
+    g_size       : natural;
+    g_show_ahead : boolean := false;
+
+    -- Read-side flag selection
+    g_with_empty        : boolean := true;   -- with empty flag
+    g_with_full         : boolean := true;   -- with full flag
+    g_with_almost_empty : boolean := false;
+    g_with_almost_full  : boolean := false;
+    g_with_count        : boolean := false;  -- with words counter
+
+    g_almost_empty_threshold : integer := 0;  -- threshold for almost empty flag
+    g_almost_full_threshold  : integer := 0;  -- threshold for almost full flag
+
+    g_register_flag_outputs : boolean := true
+    );
+
+  port (
+    rst_n_i : in std_logic := '1';
+
+    clk_i : in std_logic;
+    d_i   : in std_logic_vector(g_data_width-1 downto 0);
+    we_i  : in std_logic;
+
+    q_o  : out std_logic_vector(g_data_width-1 downto 0);
+    rd_i : in  std_logic;
+
+    empty_o        : out std_logic;
+    full_o         : out std_logic;
+    almost_empty_o : out std_logic;
+    almost_full_o  : out std_logic;
+    count_o        : out std_logic_vector(f_log2_size(g_size)-1 downto 0)
+    );
+
+end inferred_sync_fifo;
+
+architecture syn of inferred_sync_fifo is
+
+  constant c_pointer_width                         : integer := f_log2_size(g_size);
+  signal   rd_ptr, wr_ptr, wr_ptr_d0, rd_ptr_muxed : unsigned(c_pointer_width-1 downto 0);
+  signal   usedw                                   : unsigned(c_pointer_width downto 0);
+  signal   full, empty                             : std_logic;
+  signal   q_int                                   : std_logic_vector(g_data_width-1 downto 0);
+  signal   we_int, rd_int                          : std_logic;
+  signal   guard_bit                               : std_logic;
+
+  signal q_comb : std_logic_vector(g_data_width-1 downto 0);
+  
+begin  -- syn
+
+  we_int <= we_i and not full;
+  rd_int <= rd_i and not empty;
+  
+  U_FIFO_Ram : generic_dpram
+    generic map (
+      g_data_width               => g_data_width,
+      g_size                     => g_size,
+      g_with_byte_enable         => false,
+      g_addr_conflict_resolution => "dont_care",
+      g_dual_clock               => false)
+    port map (
+      rst_n_i => rst_n_i,
+      clka_i  => clk_i,
+      wea_i   => we_int,
+      aa_i    => std_logic_vector(wr_ptr(c_pointer_width-1 downto 0)),
+      da_i    => d_i,
+      clkb_i  => '0',
+      ab_i    => std_logic_vector(rd_ptr_muxed(c_pointer_width-1 downto 0)),
+      qb_o    => q_comb);
+
+  process(rd_ptr, rd_i, rd_int)
+  begin
+    if(rd_int = '1' and g_show_ahead) then
+      rd_ptr_muxed <= rd_ptr + 1;
+    elsif((rd_int = '1' and not g_show_ahead) or (g_show_ahead)) then
+      rd_ptr_muxed <= rd_ptr;
+    else
+      rd_ptr_muxed <= rd_ptr - 1;
+    end if;
+  end process;
+
+  q_o <= q_comb;
+
+  p_pointers : process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        wr_ptr <= (others => '0');
+        rd_ptr <= (others => '0');
+      else
+        if(we_int = '1') then
+          wr_ptr <= wr_ptr + 1;
+        end if;
+
+        if(rd_int = '1') then
+          rd_ptr <= rd_ptr + 1;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  gen_comb_flags_showahead : if(g_show_ahead = true) generate
+
+    process(clk_i)
+    begin
+      if rising_edge(clk_i) then
+        if ((rd_ptr + 1 = wr_ptr and rd_int = '1') or (rd_ptr = wr_ptr)) then
+          empty <= '1';
+        else
+          empty <= '0';
+        end if;
+      end if;
+    end process;
+    full <= '1' when (wr_ptr + 1 = rd_ptr) else '0';
+
+  end generate gen_comb_flags_showahead;
+
+  gen_comb_flags : if(g_register_flag_outputs = false and g_show_ahead = false) generate
+    empty <= '1' when (wr_ptr = rd_ptr and guard_bit = '0') else '0';
+    full  <= '1' when (wr_ptr = rd_ptr and guard_bit = '1') else '0';
+
+    p_guard_bit : process(clk_i)
+    begin
+      if rising_edge(clk_i) then
+        if rst_n_i = '0' then
+          guard_bit <= '0';
+        elsif(wr_ptr + 1 = rd_ptr and we_int = '1') then
+          guard_bit <= '1';
+        elsif(rd_i = '1') then
+          guard_bit <= '0';
+        end if;
+      end if;
+    end process;
+  end generate gen_comb_flags;
+
+  gen_registered_flags : if(g_register_flag_outputs = true and g_show_ahead = false) generate
+    p_reg_flags : process(clk_i)
+    begin
+      if rising_edge(clk_i) then
+        
+        if(rst_n_i = '0') then
+          full  <= '0';
+          empty <= '1';
+        else
+          if(usedw = 1 and rd_int = '1' and we_int = '0') then
+            empty <= '1';
+          elsif(we_int = '1' and rd_int = '0') then
+            empty <= '0';
+          end if;
+
+          if(usedw = g_size-2 and we_int = '1' and rd_int = '0') then
+            full <= '1';
+          elsif(usedw = g_size-1 and rd_int = '1' and we_int = '0') then
+            full <= '0';
+          end if;
+        end if;
+        
+      end if;
+    end process;
+  end generate gen_registered_flags;
+
+
+  gen_with_word_counter : if(g_with_count or g_with_almost_empty or g_with_almost_full or g_register_flag_outputs) generate
+    p_usedw_counter : process(clk_i)
+    begin
+      if rising_edge(clk_i) then
+        if rst_n_i = '0' then
+          usedw <= (others => '0');
+        else
+          if(we_int = '1' and rd_int = '0') then
+            usedw <= usedw + 1;
+          elsif(we_int = '0' and rd_int = '1') then
+            usedw <= usedw - 1;
+          end if;
+        end if;
+      end if;
+    end process;
+
+    count_o <= std_logic_vector(usedw(c_pointer_width-1 downto 0));
+
+  end generate gen_with_word_counter;
+
+  gen_with_almost_full : if(g_with_almost_full) generate
+    process(clk_i)
+    begin
+      if rising_edge(clk_i) then
+        if rst_n_i = '0' then
+          almost_full_o <= '0';
+        else
+          if(usedw = g_almost_full_threshold-1) and (we_int = '1' and rd_int = '0') then
+            almost_full_o <= '1';
+          elsif (usedw = g_almost_full_threshold) and (rd_int = '1' and we_int = '0') then
+            almost_full_o <= '0';
+          end if;
+        end if;
+      end if;
+    end process;
+  end generate gen_with_almost_full;
+
+  gen_without_almost_full : if(not g_with_almost_full) generate
+    almost_full_o <= '0';
+  end generate gen_without_almost_full;
+
+  gen_with_almost_empty : if(g_with_almost_empty) generate
+    process(clk_i)
+    begin
+      if rising_edge(clk_i) then
+        if rst_n_i = '0' then
+          almost_empty_o <= '1';
+        else
+          if(usedw = g_almost_empty_threshold+1) and (rd_int = '1' and we_int = '0') then
+            almost_empty_o <= '1';
+          elsif (usedw = g_almost_empty_threshold) and (we_int = '1' and rd_int = '0') then
+            almost_empty_o <= '0';
+          end if;
+        end if;
+      end if;
+    end process;
+  end generate gen_with_almost_empty;
+
+  gen_without_almost_empty : if(not g_with_almost_empty) generate
+    almost_empty_o <= '0';
+  end generate gen_without_almost_empty;
+
+  full_o  <= full;
+  empty_o <= empty;
+
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd
new file mode 100644
index 000000000..66fce2fe0
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd
@@ -0,0 +1,162 @@
+-------------------------------------------------------------------------------
+-- Title      : Parametrizable asynchronous FIFO (Generic version)
+-- Project    : Generics RAMs and FIFOs collection
+-------------------------------------------------------------------------------
+-- File       : generic_async_fifo.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2011-01-25
+-- Last update: 2012-07-03
+-- Platform   : 
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Dual-clock asynchronous FIFO. 
+-- - configurable data width and size
+-- - configurable full/empty/almost full/almost empty/word count signals
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011 CERN
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2011-01-25  1.0      twlostow        Created
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.genram_pkg.all;
+
+entity generic_async_fifo is
+
+  generic (
+    g_data_width : natural;
+    g_size       : natural;
+    g_show_ahead : boolean := false;
+
+    -- Read-side flag selection
+    g_with_rd_empty        : boolean := true;   -- with empty flag
+    g_with_rd_full         : boolean := false;  -- with full flag
+    g_with_rd_almost_empty : boolean := false;
+    g_with_rd_almost_full  : boolean := false;
+    g_with_rd_count        : boolean := false;  -- with words counter
+
+    g_with_wr_empty        : boolean := false;
+    g_with_wr_full         : boolean := true;
+    g_with_wr_almost_empty : boolean := false;
+    g_with_wr_almost_full  : boolean := false;
+    g_with_wr_count        : boolean := false;
+
+    g_almost_empty_threshold : integer;  -- threshold for almost empty flag
+    g_almost_full_threshold  : integer   -- threshold for almost full flag
+    );
+
+  port (
+    rst_n_i : in std_logic := '1';
+
+
+    -- write port
+    clk_wr_i : in std_logic;
+    d_i      : in std_logic_vector(g_data_width-1 downto 0);
+    we_i     : in std_logic;
+
+    wr_empty_o        : out std_logic;
+    wr_full_o         : out std_logic;
+    wr_almost_empty_o : out std_logic;
+    wr_almost_full_o  : out std_logic;
+    wr_count_o        : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
+
+    -- read port
+    clk_rd_i : in  std_logic;
+    q_o      : out std_logic_vector(g_data_width-1 downto 0);
+    rd_i     : in  std_logic;
+
+    rd_empty_o        : out std_logic;
+    rd_full_o         : out std_logic;
+    rd_almost_empty_o : out std_logic;
+    rd_almost_full_o  : out std_logic;
+    rd_count_o        : out std_logic_vector(f_log2_size(g_size)-1 downto 0)
+    );
+
+end generic_async_fifo;
+
+
+architecture syn of generic_async_fifo is
+  
+  component inferred_async_fifo
+    generic (
+      g_data_width             : natural;
+      g_size                   : natural;
+      g_show_ahead             : boolean;
+      g_with_rd_empty          : boolean;
+      g_with_rd_full           : boolean;
+      g_with_rd_almost_empty   : boolean;
+      g_with_rd_almost_full    : boolean;
+      g_with_rd_count          : boolean;
+      g_with_wr_empty          : boolean;
+      g_with_wr_full           : boolean;
+      g_with_wr_almost_empty   : boolean;
+      g_with_wr_almost_full    : boolean;
+      g_with_wr_count          : boolean;
+      g_almost_empty_threshold : integer;
+      g_almost_full_threshold  : integer);
+    port (
+      rst_n_i           : in  std_logic := '1';
+      clk_wr_i          : in  std_logic;
+      d_i               : in  std_logic_vector(g_data_width-1 downto 0);
+      we_i              : in  std_logic;
+      wr_empty_o        : out std_logic;
+      wr_full_o         : out std_logic;
+      wr_almost_empty_o : out std_logic;
+      wr_almost_full_o  : out std_logic;
+      wr_count_o        : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      clk_rd_i          : in  std_logic;
+      q_o               : out std_logic_vector(g_data_width-1 downto 0);
+      rd_i              : in  std_logic;
+      rd_empty_o        : out std_logic;
+      rd_full_o         : out std_logic;
+      rd_almost_empty_o : out std_logic;
+      rd_almost_full_o  : out std_logic;
+      rd_count_o        : out std_logic_vector(f_log2_size(g_size)-1 downto 0));
+  end component;
+
+
+begin  -- syn
+
+  U_Inferred_FIFO : inferred_async_fifo
+    generic map (
+      g_data_width             => g_data_width,
+      g_size                   => g_size,
+      g_show_ahead             => g_show_ahead,
+      g_with_rd_empty          => g_with_rd_empty,
+      g_with_rd_full           => g_with_rd_full,
+      g_with_rd_almost_empty   => g_with_rd_almost_empty,
+      g_with_rd_almost_full    => g_with_rd_almost_full,
+      g_with_rd_count          => g_with_rd_count,
+      g_with_wr_empty          => g_with_wr_empty,
+      g_with_wr_full           => g_with_wr_full,
+      g_with_wr_almost_empty   => g_with_wr_almost_empty,
+      g_with_wr_almost_full    => g_with_wr_almost_full,
+      g_with_wr_count          => g_with_wr_count,
+      g_almost_empty_threshold => g_almost_empty_threshold,
+      g_almost_full_threshold  => g_almost_full_threshold)
+    port map (
+      rst_n_i           => rst_n_i,
+      clk_wr_i          => clk_wr_i,
+      d_i               => d_i,
+      we_i              => we_i,
+      wr_empty_o        => wr_empty_o,
+      wr_full_o         => wr_full_o,
+      wr_almost_empty_o => wr_almost_empty_o,
+      wr_almost_full_o  => wr_almost_full_o,
+      wr_count_o        => wr_count_o,
+      clk_rd_i          => clk_rd_i,
+      q_o               => q_o,
+      rd_i              => rd_i,
+      rd_empty_o        => rd_empty_o,
+      rd_full_o         => rd_full_o,
+      rd_almost_empty_o => rd_almost_empty_o,
+      rd_almost_full_o  => rd_almost_full_o,
+      rd_count_o        => rd_count_o);
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd
new file mode 100644
index 000000000..fecd0882d
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd
@@ -0,0 +1,130 @@
+-------------------------------------------------------------------------------
+-- Title      : Parametrizable synchronous FIFO (Xilinx version)
+-- Project    : Generics RAMs and FIFOs collection
+-------------------------------------------------------------------------------
+-- File       : generic_sync_fifo.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2011-01-25
+-- Last update: 2012-07-03
+-- Platform   : 
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Single-clock FIFO. 
+-- - configurable data width and size
+-- - "show ahead" mode
+-- - configurable full/empty/almost full/almost empty/word count signals
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011 CERN
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2011-01-25  1.0      twlostow        Created
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.genram_pkg.all;
+
+entity generic_sync_fifo is
+
+  generic (
+    g_data_width : natural;
+    g_size       : natural;
+    g_show_ahead : boolean := false;
+
+    -- Read-side flag selection
+    g_with_empty        : boolean := true;   -- with empty flag
+    g_with_full         : boolean := true;   -- with full flag
+    g_with_almost_empty : boolean := false;
+    g_with_almost_full  : boolean := false;
+    g_with_count        : boolean := false;  -- with words counter
+
+    g_almost_empty_threshold : integer;  -- threshold for almost empty flag
+    g_almost_full_threshold  : integer;  -- threshold for almost full flag
+    g_register_flag_outputs  : boolean := true
+    );
+
+  port (
+    rst_n_i : in std_logic := '1';
+
+    clk_i : in std_logic;
+    d_i   : in std_logic_vector(g_data_width-1 downto 0);
+    we_i  : in std_logic;
+
+    q_o  : out std_logic_vector(g_data_width-1 downto 0);
+    rd_i : in  std_logic;
+
+    empty_o        : out std_logic;
+    full_o         : out std_logic;
+    almost_empty_o : out std_logic;
+    almost_full_o  : out std_logic;
+    count_o        : out std_logic_vector(f_log2_size(g_size)-1 downto 0)
+    );
+
+end generic_sync_fifo;
+
+architecture syn of generic_sync_fifo is
+
+  component inferred_sync_fifo
+    generic (
+      g_data_width             : natural;
+      g_size                   : natural;
+      g_show_ahead             : boolean;
+      g_with_empty             : boolean;
+      g_with_full              : boolean;
+      g_with_almost_empty      : boolean;
+      g_with_almost_full       : boolean;
+      g_with_count             : boolean;
+      g_almost_empty_threshold : integer;
+      g_almost_full_threshold  : integer;
+      g_register_flag_outputs  : boolean);
+    port (
+      rst_n_i        : in  std_logic := '1';
+      clk_i          : in  std_logic;
+      d_i            : in  std_logic_vector(g_data_width-1 downto 0);
+      we_i           : in  std_logic;
+      q_o            : out std_logic_vector(g_data_width-1 downto 0);
+      rd_i           : in  std_logic;
+      empty_o        : out std_logic;
+      full_o         : out std_logic;
+      almost_empty_o : out std_logic;
+      almost_full_o  : out std_logic;
+      count_o        : out std_logic_vector(f_log2_size(g_size)-1 downto 0));
+  end component;
+
+begin  -- syn
+
+  U_Inferred_FIFO : inferred_sync_fifo
+      generic map (
+        g_data_width             => g_data_width,
+        g_size                   => g_size,
+        g_show_ahead             => g_show_ahead,
+        g_with_empty             => g_with_empty,
+        g_with_full              => g_with_full,
+        g_with_almost_empty      => g_with_almost_empty,
+        g_with_almost_full       => g_with_almost_full,
+        g_with_count             => g_with_count,
+        g_almost_empty_threshold => g_almost_empty_threshold,
+        g_almost_full_threshold  => g_almost_full_threshold,
+        g_register_flag_outputs  => g_register_flag_outputs)
+
+      port map (
+        rst_n_i        => rst_n_i,
+        clk_i          => clk_i,
+        d_i            => d_i,
+        we_i           => we_i,
+        q_o            => q_o,
+        rd_i           => rd_i,
+        empty_o        => empty_o,
+        full_o         => full_o,
+        almost_empty_o => almost_empty_o,
+        almost_full_o  => almost_full_o,
+        count_o        => count_o);
+
+ 
+
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/genram_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/genram_pkg.vhd
new file mode 100644
index 000000000..c212bbf32
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/genram_pkg.vhd
@@ -0,0 +1,262 @@
+-------------------------------------------------------------------------------
+-- Title      : Main package file
+-- Project    : Generics RAMs and FIFOs collection
+-------------------------------------------------------------------------------
+-- File       : genram_pkg.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2011-01-25
+-- Last update: 2013-10-30
+-- Platform   : 
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2011 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2011-01-25  1.0      twlostow        Created
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package genram_pkg is
+
+  function f_log2_size (A       : natural) return natural;
+  function f_gen_dummy_vec (val : std_logic; size : natural) return std_logic_vector;
+  function f_zeros (size : integer) return std_logic_vector;
+  function f_check_bounds(x : integer; minx : integer; maxx : integer) return integer;
+
+  type t_generic_ram_init is array (integer range <>, integer range <>) of std_logic;
+  type t_ram8_type  is array (integer range <>) of std_logic_vector(7 downto 0);
+  type t_ram16_type is array (integer range <>) of std_logic_vector(15 downto 0);
+  type t_ram32_type is array (integer range <>) of std_logic_vector(31 downto 0);
+  
+  -- Single-port synchronous RAM
+  component generic_spram
+    generic (
+      g_data_width               : natural;
+      g_size                     : natural;
+      g_with_byte_enable         : boolean := false;
+      g_init_file                : string  := "none";
+      g_addr_conflict_resolution : string  := "dont_care") ;
+    port (
+      rst_n_i : in  std_logic;
+      clk_i   : in  std_logic;
+      bwe_i   : in  std_logic_vector((g_data_width+7)/8-1 downto 0):= f_gen_dummy_vec('1', (g_data_width+7)/8);
+      we_i    : in  std_logic;
+      a_i     : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      d_i     : in  std_logic_vector(g_data_width-1 downto 0) := f_gen_dummy_vec('0', g_data_width);
+      q_o     : out std_logic_vector(g_data_width-1 downto 0));
+  end component;
+
+  component generic_simple_dpram
+    generic (
+      g_data_width               : natural;
+      g_size                     : natural;
+      g_with_byte_enable         : boolean := false;
+      g_addr_conflict_resolution : string  := "dont_care";
+      g_init_file                : string  := "none";
+      g_dual_clock               : boolean := true);
+    port (
+      rst_n_i : in  std_logic := '1';
+      clka_i  : in  std_logic;
+      bwea_i  : in  std_logic_vector((g_data_width+7)/8 -1 downto 0) := f_gen_dummy_vec('1', (g_data_width+7)/8);
+      wea_i   : in  std_logic;
+      aa_i    : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      da_i    : in  std_logic_vector(g_data_width       -1 downto 0);
+      clkb_i  : in  std_logic;
+      ab_i    : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      qb_o    : out std_logic_vector(g_data_width       -1 downto 0));
+  end component;
+
+  component generic_dpram
+    generic (
+      g_data_width               : natural;
+      g_size                     : natural;
+      g_with_byte_enable         : boolean := false;
+      g_addr_conflict_resolution : string  := "dont_care";
+      g_init_file                : string  := "none";
+      g_dual_clock               : boolean := true);
+    port (
+      rst_n_i : in  std_logic := '1';
+      clka_i  : in  std_logic;
+      bwea_i  : in  std_logic_vector((g_data_width+7)/8-1 downto 0) := f_gen_dummy_vec('1', (g_data_width+7)/8);
+      wea_i   : in  std_logic := '0';
+      aa_i    : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      da_i    : in  std_logic_vector(g_data_width-1 downto 0) := f_gen_dummy_vec('0', g_data_width);
+      qa_o    : out std_logic_vector(g_data_width-1 downto 0);
+      clkb_i  : in  std_logic;
+      bweb_i  : in  std_logic_vector((g_data_width+7)/8-1 downto 0) := f_gen_dummy_vec('1', (g_data_width+7)/8);
+      web_i   : in  std_logic := '0';
+      ab_i    : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      db_i    : in  std_logic_vector(g_data_width-1 downto 0) := f_gen_dummy_vec('0', g_data_width);
+      qb_o    : out std_logic_vector(g_data_width-1 downto 0));
+  end component;
+
+  component generic_dpram_mixed
+    generic (
+      g_data_a_width             : natural;
+      g_data_b_width             : natural;
+      g_size                     : natural;
+      g_addr_conflict_resolution : string := "dont_care";
+      g_init_file                : string := "none";
+      g_dual_clock               : boolean := true);
+    port (
+      rst_n_i : in  std_logic := '1';
+      clka_i  : in  std_logic;
+      bwea_i  : in  std_logic_vector((g_data_a_width+7)/8-1 downto 0) := f_gen_dummy_vec('1', (g_data_a_width+7)/8);
+      wea_i   : in  std_logic := '0';
+      aa_i    : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      da_i    : in  std_logic_vector(g_data_a_width-1 downto 0) := f_gen_dummy_vec('0', g_data_a_width);
+      qa_o    : out std_logic_vector(g_data_a_width-1 downto 0);
+      clkb_i  : in  std_logic;
+      bweb_i  : in  std_logic_vector((g_data_b_width+7)/8-1 downto 0) := f_gen_dummy_vec('1', (g_data_b_width+7)/8);
+      web_i   : in  std_logic := '0';
+      ab_i    : in  std_logic_vector(f_log2_size(g_data_a_width*g_size/g_data_b_width)-1 downto 0);
+      db_i    : in  std_logic_vector(g_data_b_width-1 downto 0) := f_gen_dummy_vec('0', g_data_b_width);
+      qb_o    : out std_logic_vector(g_data_b_width-1 downto 0));
+  end component;
+
+  component generic_async_fifo
+    generic (
+      g_data_width             : natural;
+      g_size                   : natural;
+      g_show_ahead             : boolean := false;
+      g_with_rd_empty          : boolean := true;
+      g_with_rd_full           : boolean := false;
+      g_with_rd_almost_empty   : boolean := false;
+      g_with_rd_almost_full    : boolean := false;
+      g_with_rd_count          : boolean := false;
+      g_with_wr_empty          : boolean := false;
+      g_with_wr_full           : boolean := true;
+      g_with_wr_almost_empty   : boolean := false;
+      g_with_wr_almost_full    : boolean := false;
+      g_with_wr_count          : boolean := false;
+      g_almost_empty_threshold : integer := 0;
+      g_almost_full_threshold  : integer := 0);
+    port (
+      rst_n_i           : in  std_logic := '1';
+      clk_wr_i          : in  std_logic;
+      d_i               : in  std_logic_vector(g_data_width-1 downto 0);
+      we_i              : in  std_logic;
+      wr_empty_o        : out std_logic;
+      wr_full_o         : out std_logic;
+      wr_almost_empty_o : out std_logic;
+      wr_almost_full_o  : out std_logic;
+      wr_count_o        : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      clk_rd_i          : in  std_logic;
+      q_o               : out std_logic_vector(g_data_width-1 downto 0);
+      rd_i              : in  std_logic;
+      rd_empty_o        : out std_logic;
+      rd_full_o         : out std_logic;
+      rd_almost_empty_o : out std_logic;
+      rd_almost_full_o  : out std_logic;
+      rd_count_o        : out std_logic_vector(f_log2_size(g_size)-1 downto 0));
+  end component;
+
+
+  component generic_sync_fifo
+    generic (
+      g_data_width             : natural;
+      g_size                   : natural;
+      g_show_ahead             : boolean := false;
+      g_with_empty             : boolean := true;
+      g_with_full              : boolean := true;
+      g_with_almost_empty      : boolean := false;
+      g_with_almost_full       : boolean := false;
+      g_with_count             : boolean := false;
+      g_almost_empty_threshold : integer := 0;
+      g_almost_full_threshold  : integer := 0);
+    port (
+      rst_n_i        : in  std_logic := '1';
+      clk_i          : in  std_logic;
+      d_i            : in  std_logic_vector(g_data_width-1 downto 0);
+      we_i           : in  std_logic;
+      q_o            : out std_logic_vector(g_data_width-1 downto 0);
+      rd_i           : in  std_logic;
+      empty_o        : out std_logic;
+      full_o         : out std_logic;
+      almost_empty_o : out std_logic;
+      almost_full_o  : out std_logic;
+      count_o        : out std_logic_vector(f_log2_size(g_size)-1 downto 0));
+  end component;
+
+  component generic_shiftreg_fifo
+    generic (
+      g_data_width : integer;
+      g_size       : integer);
+    port (
+      rst_n_i       : in  std_logic := '1';
+      clk_i         : in  std_logic;
+      d_i           : in  std_logic_vector(g_data_width-1 downto 0);
+      we_i          : in  std_logic;
+      q_o           : out std_logic_vector(g_data_width-1 downto 0);
+      rd_i          : in  std_logic;
+      full_o        : out std_logic;
+      almost_full_o : out std_logic;
+      q_valid_o     : out std_logic
+      );
+  end component;
+  
+end genram_pkg;
+
+package body genram_pkg is
+
+  function f_log2_size (A : natural) return natural is
+  begin
+    for I in 1 to 64 loop               -- Works for up to 64 bits
+      if (2**I >= A) then
+        return(I);
+      end if;
+    end loop;
+    return(63);
+  end function f_log2_size;
+
+  function f_gen_dummy_vec (val : std_logic; size : natural) return std_logic_vector is
+    variable tmp : std_logic_vector(size-1 downto 0);
+  begin
+    for i in 0 to size-1 loop
+      tmp(i) := val;
+    end loop;  -- i
+    return tmp;
+  end f_gen_dummy_vec;
+
+  function f_zeros(size : integer)
+    return std_logic_vector is
+  begin
+    return std_logic_vector(to_unsigned(0, size));
+  end f_zeros;
+
+  function f_check_bounds(x : integer; minx : integer; maxx : integer) return integer is
+  begin
+    if(x < minx) then
+      return minx;
+    elsif(x > maxx) then
+      return maxx;
+    else
+      return x;
+    end if;
+  end f_check_bounds;
+
+end genram_pkg;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd
new file mode 100644
index 000000000..5bb1da6d3
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd
@@ -0,0 +1,251 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library std;
+use std.textio.all;
+
+library work;
+use work.genram_pkg.all;
+
+package memory_loader_pkg is
+
+  subtype t_meminit_array is t_generic_ram_init;
+
+  impure function f_load_mem_from_file
+    (file_name : in string;
+     mem_size  : in integer;
+     mem_width : in integer;
+     fail_if_notfound : boolean)
+    return t_meminit_array;
+
+  impure function f_load_mem32_from_file
+    (file_name : in string; mem_size  : in integer; fail_if_notfound : boolean)
+    return t_ram32_type;
+
+  impure function f_load_mem16_from_file
+    (file_name : in string; mem_size  : in integer; fail_if_notfound : boolean)
+    return t_ram16_type;
+
+  impure function f_load_mem8_from_file
+    (file_name : in string; mem_size  : in integer; fail_if_notfound : boolean)
+    return t_ram8_type;
+
+  impure function f_load_mem32_from_file_split
+    (file_name        : in string; mem_size : in integer;
+     fail_if_notfound : boolean; byte_idx : in integer)
+    return t_ram8_type;
+
+end memory_loader_pkg;
+
+package body memory_loader_pkg is
+
+  impure function f_load_mem_from_file
+    (file_name        : in string;
+     mem_size         : in integer;
+     mem_width        : in integer;
+     fail_if_notfound : boolean)
+    return t_meminit_array is
+
+    FILE f_in  : text;
+    variable l : line;
+    variable tmp_bv : bit_vector(mem_width-1 downto 0);
+    variable tmp_sv : std_logic_vector(mem_width-1 downto 0);
+    variable mem: t_meminit_array(0 to mem_size-1, mem_width-1 downto 0);
+    variable status   : file_open_status;
+  begin
+    if(file_name = "" or file_name = "none") then
+      mem:= (others => (others => '0'));
+      return mem;
+    end if;
+
+    file_open(status, f_in, file_name, read_mode);
+
+    if(status /= open_ok) then
+      if(fail_if_notfound) then
+        report "f_load_mem_from_file(): can't open file '"&file_name&"'" severity failure;
+      else
+        report "f_load_mem_from_file(): can't open file '"&file_name&"'" severity warning;
+      end if;
+    end if;
+
+    for I in 0 to mem_size-1 loop
+      readline (f_in, l);
+      -- read function gives us bit_vector
+      read (l, tmp_bv);
+      tmp_sv := to_stdlogicvector(tmp_bv);
+      for J in 0 to mem_width-1 loop
+        mem(i, j) := tmp_sv(j);
+      end loop;
+    end loop;
+
+    file_close(f_in);
+    return mem;
+  end f_load_mem_from_file;
+
+  -------------------------------------------------------------------
+  -- RAM initialization for most common sizes to speed-up synthesis
+  -------------------------------------------------------------------
+
+  impure function f_load_mem32_from_file
+    (file_name        : in string;
+     mem_size         : in integer;
+     fail_if_notfound : boolean)
+    return t_ram32_type is
+
+    FILE f_in  : text;
+    variable l : line;
+    variable tmp_bv : bit_vector(31 downto 0);
+    variable mem: t_ram32_type(0 to mem_size-1);
+    variable status   : file_open_status;
+  begin
+    if(file_name = "" or file_name = "none") then
+      mem:= (others => (others => '0'));
+      return mem;
+    end if;
+
+    file_open(status, f_in, file_name, read_mode);
+
+    if(status /= open_ok) then
+      if(fail_if_notfound) then
+        report "f_load_mem_from_file(): can't open file '"&file_name&"'" severity failure;
+      else
+        report "f_load_mem_from_file(): can't open file '"&file_name&"'" severity warning;
+      end if;
+    end if;
+
+    for I in 0 to mem_size-1 loop
+      readline (f_in, l);
+      -- read function gives us bit_vector
+      read (l, tmp_bv);
+      mem(I) := to_stdlogicvector(tmp_bv);
+    end loop;
+
+    file_close(f_in);
+    return mem;
+  end f_load_mem32_from_file;
+
+  -------------------------------------------------------------------
+
+  impure function f_load_mem16_from_file
+    (file_name        : in string;
+     mem_size         : in integer;
+     fail_if_notfound : boolean)
+    return t_ram16_type is
+
+    FILE f_in  : text;
+    variable l : line;
+    variable tmp_bv : bit_vector(15 downto 0);
+    variable mem: t_ram16_type(0 to mem_size-1);
+    variable status   : file_open_status;
+  begin
+    if(file_name = "" or file_name = "none") then
+      mem:= (others => (others => '0'));
+      return mem;
+    end if;
+
+    file_open(status, f_in, file_name, read_mode);
+
+    if(status /= open_ok) then
+      if(fail_if_notfound) then
+        report "f_load_mem_from_file(): can't open file '"&file_name&"'" severity failure;
+      else
+        report "f_load_mem_from_file(): can't open file '"&file_name&"'" severity warning;
+      end if;
+    end if;
+
+    for I in 0 to mem_size-1 loop
+      readline (f_in, l);
+      -- read function gives us bit_vector
+      read (l, tmp_bv);
+      mem(I) := to_stdlogicvector(tmp_bv);
+    end loop;
+
+    file_close(f_in);
+    return mem;
+  end f_load_mem16_from_file;
+
+  -------------------------------------------------------------------
+
+  impure function f_load_mem8_from_file
+    (file_name        : in string;
+     mem_size         : in integer;
+     fail_if_notfound : boolean)
+    return t_ram8_type is
+
+    FILE f_in  : text;
+    variable l : line;
+    variable tmp_bv : bit_vector(7 downto 0);
+    variable mem: t_ram8_type(0 to mem_size-1);
+    variable status   : file_open_status;
+  begin
+    if(file_name = "" or file_name = "none") then
+      mem:= (others => (others => '0'));
+      return mem;
+    end if;
+
+    file_open(status, f_in, file_name, read_mode);
+
+    if(status /= open_ok) then
+      if(fail_if_notfound) then
+        report "f_load_mem_from_file(): can't open file '"&file_name&"'" severity failure;
+      else
+        report "f_load_mem_from_file(): can't open file '"&file_name&"'" severity warning;
+      end if;
+    end if;
+
+    for I in 0 to mem_size-1 loop
+      readline (f_in, l);
+      -- read function gives us bit_vector
+      read (l, tmp_bv);
+      mem(I) := to_stdlogicvector(tmp_bv);
+    end loop;
+
+    file_close(f_in);
+    return mem;
+  end f_load_mem8_from_file;
+
+  -------------------------------------------------------------------
+  -- initialization for 32-bit RAM split into 4x 8-bit BRAM
+  -------------------------------------------------------------------
+
+  impure function f_load_mem32_from_file_split
+    (file_name        : in string;
+     mem_size         : in integer;
+     fail_if_notfound : boolean;
+     byte_idx         : in integer)
+    return t_ram8_type is
+
+    FILE f_in  : text;
+    variable l : line;
+    variable tmp_bv : bit_vector(31 downto 0);
+    variable mem: t_ram8_type(0 to mem_size-1);
+    variable status   : file_open_status;
+  begin
+    if(file_name = "" or file_name = "none") then
+      mem:= (others => (others => '0'));
+      return mem;
+    end if;
+
+    file_open(status, f_in, file_name, read_mode);
+
+    if(status /= open_ok) then
+      if(fail_if_notfound) then
+        report "f_load_mem_from_file(): can't open file '"&file_name&"'" severity failure;
+      else
+        report "f_load_mem_from_file(): can't open file '"&file_name&"'" severity warning;
+      end if;
+    end if;
+
+    for I in 0 to mem_size-1 loop
+      readline (f_in, l);
+      -- read function gives us bit_vector
+      read (l, tmp_bv);
+      mem(I) := to_stdlogicvector( tmp_bv((byte_idx+1)*8-1 downto byte_idx*8) );
+    end loop;
+
+    file_close(f_in);
+    return mem;
+  end f_load_mem32_from_file_split;
+
+end memory_loader_pkg;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd
new file mode 100644
index 000000000..87a4eee97
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd
@@ -0,0 +1,68 @@
+library ieee;
+
+use ieee.STD_LOGIC_1164.all;
+use ieee.NUMERIC_STD.all;
+
+use work.genram_pkg.all;
+
+entity gc_shiftreg is
+  
+  generic (
+    g_size : integer);
+
+  port (
+    clk_i : in  std_logic;
+    en_i  : in  std_logic;
+    d_i   : in  std_logic;
+    q_o   : out std_logic;
+    a_i   : in  std_logic_vector(f_log2_size(g_size)-1 downto 0));
+
+end gc_shiftreg;
+
+
+architecture wrapper of gc_shiftreg is
+
+  component SRLC32E
+    port (
+      Q   : out std_ulogic;
+      A   : in  std_logic_vector (4 downto 0);
+      CE  : in  std_ulogic;
+      CLK : in  std_ulogic;
+      D   : in  std_ulogic);
+  end component;
+
+  signal a  : std_logic_vector(4 downto 0);
+  signal sr : std_logic_vector(g_size-1 downto 0);
+  
+begin  -- wrapper
+
+  assert (g_size <= 32) report "gc_shiftreg[xilinx]: forced SRL32 implementation can be done only for 32-bit or smaller shift registers" severity warning;
+
+  a <= std_logic_vector(resize(unsigned(a_i), 5));
+
+  gen_srl32 : if(g_size <= 32) generate
+    U_SRLC32 : SRLC32E
+      port map (
+        Q   => q_o,
+        A   => a,
+        CE  => en_i,
+        CLK => clk_i,
+        D   => d_i);
+  end generate gen_srl32;
+
+  gen_inferred : if(g_size > 32) generate
+
+    p_srl : process(clk_i)
+    begin
+      if rising_edge(clk_i) then
+        if en_i = '1' then
+          sr <= sr(sr'left - 1 downto 0) & d_i;
+        end if;
+      end if;
+    end process;
+
+    q_o <= sr(TO_INTEGER(unsigned(a_i)));
+  end generate gen_inferred;
+  
+
+end wrapper;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd
new file mode 100644
index 000000000..db5a42b04
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd
@@ -0,0 +1,235 @@
+-------------------------------------------------------------------------------
+-- Title      : Parametrizable dual-port synchronous RAM (Xilinx version)
+-- Project    : Generics RAMs and FIFOs collection
+-------------------------------------------------------------------------------
+-- File       : generic_dpram.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2011-01-25
+-- Last update: 2012-03-16
+-- Platform   : 
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: True dual-port synchronous RAM for Xilinx FPGAs with:
+-- - configurable address and data bus width
+-- - byte-addressing mode (data bus width restricted to multiple of 8 bits)
+-- Todo:
+-- - loading initial contents from file
+-- - add support for read-first/write-first address conflict resulution (only
+--   supported by Xilinx in VHDL templates)
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011 CERN
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2011-01-25  1.0      twlostow        Created
+-- 2012-03-13  1.1      wterpstra       Added initial value as array
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.textio.all;
+
+library work;
+use work.genram_pkg.all;
+use work.memory_loader_pkg.all;
+
+entity generic_dpram is
+
+  generic (
+    -- standard parameters
+    g_data_width : natural := 32;
+    g_size       : natural := 16384;
+
+    g_with_byte_enable         : boolean := false;
+    g_addr_conflict_resolution : string  := "read_first";
+    g_init_file                : string  := "";
+    g_dual_clock               : boolean := true;
+    g_fail_if_file_not_found   : boolean := true
+    );
+
+  port (
+    rst_n_i : in std_logic := '1';      -- synchronous reset, active LO
+
+    -- Port A
+    clka_i : in  std_logic;
+    bwea_i : in  std_logic_vector((g_data_width+7)/8-1 downto 0);
+    wea_i  : in  std_logic;
+    aa_i   : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+    da_i   : in  std_logic_vector(g_data_width-1 downto 0);
+    qa_o   : out std_logic_vector(g_data_width-1 downto 0);
+    -- Port B
+
+    clkb_i : in  std_logic;
+    bweb_i : in  std_logic_vector((g_data_width+7)/8-1 downto 0);
+    web_i  : in  std_logic;
+    ab_i   : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+    db_i   : in  std_logic_vector(g_data_width-1 downto 0);
+    qb_o   : out std_logic_vector(g_data_width-1 downto 0)
+    );
+
+end generic_dpram;
+
+
+
+architecture syn of generic_dpram is
+
+  constant c_gen_split :boolean := (g_dual_clock = false and g_data_width=32 and
+      g_with_byte_enable=true and (g_addr_conflict_resolution="dont_care" or
+      g_addr_conflict_resolution="read_first"));
+  constant c_gen_sc    :boolean := (not c_gen_split) and (not g_dual_clock);
+  constant c_gen_dc    :boolean := g_dual_clock;
+
+  component generic_dpram_split
+    generic (
+      g_size                     : natural;
+      g_addr_conflict_resolution : string  := "dont_care";
+      g_init_file                : string  := "none";
+      g_fail_if_file_not_found   : boolean := true);
+    port (
+      rst_n_i : in  std_logic := '1';
+      clk_i   : in  std_logic;
+      bwea_i : in  std_logic_vector(3 downto 0);
+      wea_i  : in  std_logic;
+      aa_i   : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      da_i   : in  std_logic_vector(31 downto 0);
+      qa_o   : out std_logic_vector(31 downto 0);
+      bweb_i : in  std_logic_vector(3 downto 0);
+      web_i  : in  std_logic;
+      ab_i   : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      db_i   : in  std_logic_vector(31 downto 0);
+      qb_o   : out std_logic_vector(31 downto 0));
+  end component;
+
+  component generic_dpram_sameclock
+    generic (
+      g_data_width               : natural;
+      g_size                     : natural;
+      g_with_byte_enable         : boolean;
+      g_addr_conflict_resolution : string;
+      g_init_file                : string;
+      g_fail_if_file_not_found   : boolean);
+    port (
+      rst_n_i : in  std_logic := '1';
+      clk_i   : in  std_logic;
+      bwea_i  : in  std_logic_vector((g_data_width+7)/8-1 downto 0);
+      wea_i   : in  std_logic;
+      aa_i    : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      da_i    : in  std_logic_vector(g_data_width-1 downto 0);
+      qa_o    : out std_logic_vector(g_data_width-1 downto 0);
+      bweb_i  : in  std_logic_vector((g_data_width+7)/8-1 downto 0);
+      web_i   : in  std_logic;
+      ab_i    : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      db_i    : in  std_logic_vector(g_data_width-1 downto 0);
+      qb_o    : out std_logic_vector(g_data_width-1 downto 0));
+  end component;  
+
+  component generic_dpram_dualclock
+    generic (
+      g_data_width               : natural;
+      g_size                     : natural;
+      g_with_byte_enable         : boolean;
+      g_addr_conflict_resolution : string;
+      g_init_file                : string;
+      g_fail_if_file_not_found   : boolean);
+    port (
+      rst_n_i : in  std_logic := '1';
+      clka_i  : in  std_logic;
+      bwea_i  : in  std_logic_vector((g_data_width+7)/8-1 downto 0);
+      wea_i   : in  std_logic;
+      aa_i    : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      da_i    : in  std_logic_vector(g_data_width-1 downto 0);
+      qa_o    : out std_logic_vector(g_data_width-1 downto 0);
+      clkb_i  : in  std_logic;
+      bweb_i  : in  std_logic_vector((g_data_width+7)/8-1 downto 0);
+      web_i   : in  std_logic;
+      ab_i    : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      db_i    : in  std_logic_vector(g_data_width-1 downto 0);
+      qb_o    : out std_logic_vector(g_data_width-1 downto 0));
+  end component;
+
+begin
+
+  -- generic_dpram_split is like generic_dpram_sameclock, but hardcoded to
+  -- 32-bit data width and split into 4 BRAMs, each of them 8-bit wide. It's
+  -- better for Xilinx ISE, because it's unable to infer DPRAM with byte-write
+  -- enables without using huge number of LUTs.
+  -- Since it's hardcoded to 32-bits data width, we need to keep
+  -- generic_dpram_sameclock as well. For reasons why generic_dpram_split is
+  -- hardcoded to 32-bits please check the Note in generic_dpram_split.vhd.
+  gen_splitram: if c_gen_split generate
+    U_RAM_SPLIT: generic_dpram_split
+      generic map(
+        g_size                     => g_size,
+        g_addr_conflict_resolution => g_addr_conflict_resolution,
+        g_init_file                => g_init_file,
+        g_fail_if_file_not_found   => g_fail_if_file_not_found)
+      port map(
+        rst_n_i => rst_n_i,
+        clk_i   => clka_i,
+        bwea_i  => bwea_i,
+        wea_i   => wea_i,
+        aa_i    => aa_i,
+        da_i    => da_i,
+        qa_o    => qa_o,
+        bweb_i  => bweb_i,
+        web_i   => web_i,
+        ab_i    => ab_i,
+        db_i    => db_i,
+        qb_o    => qb_o);
+  end generate gen_splitram;
+
+  gen_single_clk : if c_gen_sc generate
+  U_RAM_SC: generic_dpram_sameclock
+    generic map (
+      g_data_width               => g_data_width,
+      g_size                     => g_size,
+      g_with_byte_enable         => g_with_byte_enable,
+      g_addr_conflict_resolution => g_addr_conflict_resolution,
+      g_init_file                => g_init_file,
+      g_fail_if_file_not_found   => g_fail_if_file_not_found)
+    port map (
+      rst_n_i => rst_n_i,
+      clk_i   => clka_i,
+      bwea_i  => bwea_i,
+      wea_i   => wea_i,
+      aa_i    => aa_i,
+      da_i    => da_i,
+      qa_o    => qa_o,
+      bweb_i  => bweb_i,
+      web_i   => web_i,
+      ab_i    => ab_i,
+      db_i    => db_i,
+      qb_o    => qb_o); 
+
+    
+  end generate gen_single_clk;
+
+  gen_dual_clk : if c_gen_dc generate
+    U_RAM_DC: generic_dpram_dualclock
+      generic map (
+        g_data_width               => g_data_width,
+        g_size                     => g_size,
+        g_with_byte_enable         => g_with_byte_enable,
+        g_addr_conflict_resolution => g_addr_conflict_resolution,
+        g_init_file                => g_init_file,
+        g_fail_if_file_not_found   => g_fail_if_file_not_found)
+      port map (
+        rst_n_i => rst_n_i,
+        clka_i  => clka_i,
+        bwea_i  => bwea_i,
+        wea_i   => wea_i,
+        aa_i    => aa_i,
+        da_i    => da_i,
+        qa_o    => qa_o,
+        clkb_i  => clkb_i,
+        bweb_i  => bweb_i,
+        web_i   => web_i,
+        ab_i    => ab_i,
+        db_i    => db_i,
+        qb_o    => qb_o);
+  end generate gen_dual_clk;
+
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd
new file mode 100644
index 000000000..9f3318d42
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd
@@ -0,0 +1,268 @@
+-------------------------------------------------------------------------------
+-- Title      : Parametrizable dual-port synchronous RAM (Xilinx version)
+-- Project    : Generics RAMs and FIFOs collection
+-------------------------------------------------------------------------------
+-- File       : generic_dpram.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2011-01-25
+-- Last update: 2012-03-28
+-- Platform   : 
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: True dual-port synchronous RAM for Xilinx FPGAs with:
+-- - configurable address and data bus width
+-- - byte-addressing mode (data bus width restricted to multiple of 8 bits)
+-- Todo:
+-- - loading initial contents from file
+-- - add support for read-first/write-first address conflict resulution (only
+--   supported by Xilinx in VHDL templates)
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011 CERN
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2011-01-25  1.0      twlostow        Created
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.textio.all;
+
+library work;
+use work.genram_pkg.all;
+use work.memory_loader_pkg.all;
+
+entity generic_dpram_dualclock is
+
+  generic (
+    -- standard parameters
+    g_data_width : natural := 32;
+    g_size       : natural := 16384;
+
+    g_with_byte_enable         : boolean := false;
+    g_addr_conflict_resolution : string  := "read_first";
+    g_init_file                : string  := "";
+    g_fail_if_file_not_found   : boolean := true
+    );
+
+  port (
+    rst_n_i : in std_logic := '1';      -- synchronous reset, active LO
+
+    -- Port A
+    clka_i : in  std_logic;
+    bwea_i : in  std_logic_vector((g_data_width+7)/8-1 downto 0);
+    wea_i  : in  std_logic;
+    aa_i   : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+    da_i   : in  std_logic_vector(g_data_width-1 downto 0);
+    qa_o   : out std_logic_vector(g_data_width-1 downto 0);
+    -- Port B
+
+    clkb_i : in  std_logic;
+    bweb_i : in  std_logic_vector((g_data_width+7)/8-1 downto 0);
+    web_i  : in  std_logic;
+    ab_i   : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+    db_i   : in  std_logic_vector(g_data_width-1 downto 0);
+    qb_o   : out std_logic_vector(g_data_width-1 downto 0)
+    );
+
+end generic_dpram_dualclock;
+
+
+
+architecture syn of generic_dpram_dualclock is
+
+  constant c_num_bytes : integer := (g_data_width+7)/8;
+
+
+  type t_ram_type is array(0 to g_size-1) of std_logic_vector(g_data_width-1 downto 0);
+
+  impure function f_file_to_ramtype return t_ram_type is
+    variable tmp    : t_ram_type;
+    variable n, pos : integer;
+    variable mem32  : t_ram32_type(0 to g_size-1);
+    variable mem16  : t_ram16_type(0 to g_size-1);
+    variable mem8   : t_ram8_type(0 to g_size-1);
+    variable arr    : t_meminit_array(0 to g_size-1, g_data_width-1 downto 0);
+  begin
+    -- If no file was given, there is nothing to convert, just return
+    if (g_init_file = "" or g_init_file = "none") then
+      tmp := (others=>(others=>'0'));
+      return tmp;
+    end if;
+
+    arr := f_load_mem_from_file(g_init_file, g_size, g_data_width, g_fail_if_file_not_found);
+    pos := 0;
+    while(pos < g_size)loop
+      n := 0;
+      -- avoid ISE loop iteration limit
+      while (pos < g_size and n < 4096) loop
+        for i in 0 to g_data_width-1 loop
+          tmp(pos)(i) := arr(pos, i);
+        end loop;  -- i
+        n   := n+1;
+        pos := pos + 1;
+      end loop;
+    end loop;
+    return tmp;
+  end f_file_to_ramtype;
+
+  function f_is_synthesis return boolean is
+  begin
+    -- synthesis translate_off
+    return false;
+    -- synthesis translate_on
+    return true;
+  end f_is_synthesis; 
+
+  shared variable ram : t_ram_type := f_file_to_ramtype;
+
+  signal s_we_a     : std_logic_vector(c_num_bytes-1 downto 0);
+  signal s_ram_in_a : std_logic_vector(g_data_width-1 downto 0);
+  signal s_we_b     : std_logic_vector(c_num_bytes-1 downto 0);
+  signal s_ram_in_b : std_logic_vector(g_data_width-1 downto 0);
+
+  signal clka_int : std_logic;
+  signal clkb_int : std_logic;
+
+  signal wea_rep, web_rep : std_logic_vector(c_num_bytes-1 downto 0);
+
+begin
+
+  wea_rep <= (others => wea_i);
+  web_rep <= (others => web_i);
+
+  s_we_a <= bwea_i and wea_rep;
+  s_we_b <= bweb_i and web_rep;
+
+  gen_with_byte_enable_readfirst : if(g_with_byte_enable = true and (g_addr_conflict_resolution = "read_first" or
+                                                                     g_addr_conflict_resolution = "dont_care")) generate
+
+
+    process (clka_i)
+    begin
+      if rising_edge(clka_i) then
+        if f_is_synthesis then
+          qa_o <= ram(to_integer(unsigned(aa_i)));
+        else
+          qa_o <= ram(to_integer(unsigned(aa_i)) mod g_size);
+        end if;
+        for i in 0 to c_num_bytes-1 loop
+          if s_we_a(i) = '1' then
+            ram(to_integer(unsigned(aa_i)))((i+1)*8-1 downto i*8) := da_i((i+1)*8-1 downto i*8);
+          end if;
+        end loop;
+      end if;
+    end process;
+
+
+    process (clkb_i)
+    begin
+      if rising_edge(clkb_i) then
+        if f_is_synthesis then
+          qb_o <= ram(to_integer(unsigned(ab_i)));
+        else
+          qb_o <= ram(to_integer(unsigned(ab_i)) mod g_size);
+        end if;
+        for i in 0 to c_num_bytes-1 loop
+          if s_we_b(i) = '1' then
+            ram(to_integer(unsigned(ab_i)))((i+1)*8-1 downto i*8)
+              := db_i((i+1)*8-1 downto i*8);
+          end if;
+        end loop;
+      end if;
+    end process;
+    
+
+
+
+  end generate gen_with_byte_enable_readfirst;
+
+
+
+  gen_without_byte_enable_readfirst : if(g_with_byte_enable = false and (g_addr_conflict_resolution = "read_first" or
+                                                                         g_addr_conflict_resolution = "dont_care")) generate
+
+    process(clka_i)
+    begin
+      if rising_edge(clka_i) then
+        qa_o <= ram(to_integer(unsigned(aa_i)));
+        if(wea_i = '1') then
+          ram(to_integer(unsigned(aa_i))) := da_i;
+        end if;
+      end if;
+    end process;
+
+
+    process(clkb_i)
+    begin
+      if rising_edge(clkb_i) then
+        qb_o <= ram(to_integer(unsigned(ab_i)));
+        if(web_i = '1') then
+          ram(to_integer(unsigned(ab_i))) := db_i;
+        end if;
+      end if;
+    end process;
+
+  end generate gen_without_byte_enable_readfirst;
+
+
+  gen_without_byte_enable_writefirst : if(g_with_byte_enable = false and g_addr_conflict_resolution = "write_first") generate
+
+    process(clka_i)
+    begin
+      if rising_edge(clka_i) then
+        if(wea_i = '1') then
+          ram(to_integer(unsigned(aa_i))) := da_i;
+          qa_o                            <= da_i;
+        else
+          qa_o <= ram(to_integer(unsigned(aa_i)));
+        end if;
+      end if;
+    end process;
+
+
+    process(clkb_i)
+    begin
+      if rising_edge(clkb_i) then
+        if(web_i = '1') then
+          ram(to_integer(unsigned(ab_i))) := db_i;
+          qb_o                            <= db_i;
+        else
+          qb_o <= ram(to_integer(unsigned(ab_i)));
+        end if;
+      end if;
+    end process;
+  end generate gen_without_byte_enable_writefirst;
+
+
+    gen_without_byte_enable_nochange : if(g_with_byte_enable = false and g_addr_conflict_resolution = "no_change") generate
+
+    process(clka_i)
+    begin
+      if rising_edge(clka_i) then
+        if(wea_i = '1') then
+          ram(to_integer(unsigned(aa_i))) := da_i;
+        else
+          qa_o <= ram(to_integer(unsigned(aa_i)));
+        end if;
+      end if;
+    end process;
+
+
+    process(clkb_i)
+    begin
+      if rising_edge(clkb_i) then
+        if(web_i = '1') then
+          ram(to_integer(unsigned(ab_i))) := db_i;
+        else
+          qb_o <= ram(to_integer(unsigned(ab_i)));
+        end if;
+      end if;
+    end process;
+  end generate gen_without_byte_enable_nochange;
+  
+
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd
new file mode 100644
index 000000000..49151486d
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd
@@ -0,0 +1,304 @@
+-------------------------------------------------------------------------------
+-- Title      : Parametrizable dual-port synchronous RAM (Xilinx version)
+-- Project    : Generics RAMs and FIFOs collection
+-------------------------------------------------------------------------------
+-- File       : generic_dpram_sameclock.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2011-01-25
+-- Last update: 2015-03-30
+-- Platform   : 
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: True dual-port synchronous RAM for Xilinx FPGAs with:
+-- - configurable address and data bus width
+-- - byte-addressing mode (data bus width restricted to multiple of 8 bits)
+-- Todo:
+-- - loading initial contents from file
+-- - add support for read-first/write-first address conflict resulution (only
+--   supported by Xilinx in VHDL templates)
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011 CERN
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2011-01-25  1.0      twlostow        Created
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.textio.all;
+
+library work;
+use work.genram_pkg.all;
+use work.memory_loader_pkg.all;
+
+entity generic_dpram_sameclock is
+
+  generic (
+    g_data_width : natural := 32;
+    g_size       : natural := 16384;
+
+    g_with_byte_enable         : boolean := false;
+    g_addr_conflict_resolution : string  := "read_first";
+    g_init_file                : string  := "";
+    g_fail_if_file_not_found   : boolean := true
+    );
+
+  port (
+    rst_n_i : in std_logic := '1';      -- synchronous reset, active LO
+
+    -- Port A
+    clk_i : in std_logic;
+
+    bwea_i : in  std_logic_vector((g_data_width+7)/8-1 downto 0);
+    wea_i  : in  std_logic;
+    aa_i   : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+    da_i   : in  std_logic_vector(g_data_width-1 downto 0);
+    qa_o   : out std_logic_vector(g_data_width-1 downto 0);
+
+    -- Port B
+    bweb_i : in  std_logic_vector((g_data_width+7)/8-1 downto 0);
+    web_i  : in  std_logic;
+    ab_i   : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+    db_i   : in  std_logic_vector(g_data_width-1 downto 0);
+    qb_o   : out std_logic_vector(g_data_width-1 downto 0)
+    );
+
+end generic_dpram_sameclock;
+
+
+
+architecture syn of generic_dpram_sameclock is
+
+  constant c_num_bytes : integer := (g_data_width + 7)/8;
+
+
+  type t_ram_type is array(0 to g_size-1) of std_logic_vector(g_data_width-1 downto 0);
+
+  impure function f_file_to_ramtype return t_ram_type is
+    variable tmp    : t_ram_type;
+    variable n, pos : integer;
+    variable mem32  : t_ram32_type(0 to g_size-1);
+    variable mem16  : t_ram16_type(0 to g_size-1);
+    variable mem8   : t_ram8_type(0 to g_size-1);
+    variable arr    : t_meminit_array(0 to g_size-1, g_data_width-1 downto 0);
+  begin
+    -- If no file was given, there is nothing to convert, just return
+    if (g_init_file = "" or g_init_file = "none") then
+      tmp := (others=>(others=>'0'));
+      return tmp;
+    end if;
+
+    arr := f_load_mem_from_file(g_init_file, g_size, g_data_width, g_fail_if_file_not_found);
+    pos := 0;
+    while(pos < g_size)loop
+      n := 0;
+      -- avoid ISE loop iteration limit
+      while (pos < g_size and n < 4096) loop
+        for i in 0 to g_data_width-1 loop
+          tmp(pos)(i) := arr(pos, i);
+        end loop;  -- i
+        n   := n+1;
+        pos := pos + 1;
+      end loop;
+    end loop;
+    return tmp;
+  end f_file_to_ramtype;
+
+  function f_is_synthesis return boolean is
+  begin
+    -- synthesis translate_off
+    return false;
+    -- synthesis translate_on
+    return true;
+  end f_is_synthesis; 
+
+
+  shared variable ram : t_ram_type := f_file_to_ramtype;
+
+  signal s_we_a     : std_logic_vector(c_num_bytes-1 downto 0);
+  signal s_ram_in_a : std_logic_vector(g_data_width-1 downto 0);
+  signal s_we_b     : std_logic_vector(c_num_bytes-1 downto 0);
+  signal s_ram_in_b : std_logic_vector(g_data_width-1 downto 0);
+
+  signal wea_rep, web_rep : std_logic_vector(c_num_bytes-1 downto 0);
+
+begin
+
+  wea_rep <= (others => wea_i);
+  web_rep <= (others => web_i);
+
+  s_we_a <= bwea_i and wea_rep;
+  s_we_b <= bweb_i and web_rep;
+
+  gen_with_byte_enable_readfirst : if(g_with_byte_enable = true and (g_addr_conflict_resolution = "read_first" or
+                                                                     g_addr_conflict_resolution = "dont_care")) generate
+
+    Port_A: process (clk_i)
+    begin
+      if rising_edge(clk_i) then
+        qa_o <= ram(f_check_bounds(to_integer(unsigned(aa_i)), 0, g_size-1));
+        for i in 0 to c_num_bytes-1 loop
+          if s_we_a(i) = '1' then
+            ram(f_check_bounds(to_integer(unsigned(aa_i)), 0, g_size-1))((i+1)*8-1 downto i*8) := da_i((i+1)*8-1 downto i*8);
+          end if;
+        end loop;
+      end if;
+    end process;
+
+    Port_B: process (clk_i)
+    begin
+      if rising_edge(clk_i) then
+        qb_o <= ram(f_check_bounds(to_integer(unsigned(ab_i)), 0, g_size-1));
+        for i in 0 to c_num_bytes-1 loop
+          if(s_we_b(i) = '1') then
+            ram(f_check_bounds(to_integer(unsigned(ab_i)), 0, g_size-1))((i+1)*8-1 downto i*8) := db_i((i+1)*8-1 downto i*8);
+          end if;
+        end loop;
+      end if;
+    end process;
+
+  end generate gen_with_byte_enable_readfirst;
+
+
+
+  gen_without_byte_enable_readfirst : if(g_with_byte_enable = false and (g_addr_conflict_resolution = "read_first" or
+                                                                         g_addr_conflict_resolution = "dont_care")) generate
+
+    Port_A: process(clk_i)
+    begin
+      if rising_edge(clk_i) then
+        if f_is_synthesis then
+          qa_o <= ram(to_integer(unsigned(aa_i)));
+        else
+          qa_o <= ram(to_integer(unsigned(aa_i)) mod g_size);
+        end if;
+        if(wea_i = '1') then
+          ram(to_integer(unsigned(aa_i))) := da_i;
+        end if;
+      end if;
+    end process;
+
+    Port_B: process(clk_i)
+    begin
+      if rising_edge(clk_i) then
+        if f_is_synthesis then
+          qb_o <= ram(to_integer(unsigned(ab_i)));
+        else
+          qb_o <= ram(to_integer(unsigned(ab_i)) mod g_size);
+        end if;
+        if(web_i = '1') then
+          ram(to_integer(unsigned(ab_i))) := db_i;
+        end if;
+      end if;
+    end process;
+  end generate gen_without_byte_enable_readfirst;
+
+  gen_without_byte_enable_writefirst : if(g_with_byte_enable = false and g_addr_conflict_resolution = "write_first") generate
+
+    Port_A: process(clk_i)
+    begin
+      if rising_edge(clk_i) then
+        if(wea_i = '1') then
+          ram(to_integer(unsigned(aa_i))) := da_i;
+          qa_o                            <= da_i;
+        else
+          if f_is_synthesis then
+            qa_o <= ram(to_integer(unsigned(aa_i)));
+          else
+            qa_o <= ram(to_integer(unsigned(aa_i)) mod g_size);
+          end if;
+        end if;
+      end if;
+    end process;
+
+    Port_B: process(clk_i)
+    begin
+      if rising_edge(clk_i) then
+        if(web_i = '1') then
+          ram(to_integer(unsigned(ab_i))) := db_i;
+          qb_o                            <= db_i;
+        else
+          if f_is_synthesis then
+            qb_o <= ram(to_integer(unsigned(ab_i)));
+          else
+            qb_o <= ram(to_integer(unsigned(ab_i)) mod g_size);
+          end if;
+        end if;
+      end if;
+    end process;
+
+  end generate gen_without_byte_enable_writefirst;
+
+
+  gen_without_byte_enable_nochange : if(g_with_byte_enable = false and g_addr_conflict_resolution = "no_change") generate
+
+    Port_A: process(clk_i)
+    begin
+      if rising_edge(clk_i) then
+        if(wea_i = '1') then
+          ram(to_integer(unsigned(aa_i))) := da_i;
+        else
+          if f_is_synthesis then
+            qa_o <= ram(to_integer(unsigned(aa_i)));
+          else
+            qa_o <= ram(to_integer(unsigned(aa_i)) mod g_size);
+          end if;
+        end if;
+      end if;
+    end process;
+
+    Port_B: process(clk_i)
+    begin
+      if rising_edge(clk_i) then
+        if(web_i = '1') then
+          ram(to_integer(unsigned(ab_i))) := db_i;
+        else
+          if f_is_synthesis then
+            qb_o <= ram(to_integer(unsigned(ab_i)));
+          else
+            qb_o <= ram(to_integer(unsigned(ab_i)) mod g_size);
+          end if;
+        end if;
+      end if;
+    end process;
+
+    
+  end generate gen_without_byte_enable_nochange;
+
+   gen_with_byte_enable_writefirst : if(g_with_byte_enable = true and (g_addr_conflict_resolution = "write_first")) generate
+
+    Port_A: process (clk_i)
+    begin
+      if rising_edge(clk_i) then
+        for i in 0 to c_num_bytes-1 loop
+          if s_we_a(i) = '1' then
+            ram(f_check_bounds(to_integer(unsigned(aa_i)), 0, g_size-1))((i+1)*8-1 downto i*8) := da_i((i+1)*8-1 downto i*8);
+            qa_o((i+1)*8-1 downto i*8)                                                         <= da_i((i+1)*8-1 downto i*8);
+          else
+            qa_o((i+1)*8-1 downto i*8) <= ram(f_check_bounds(to_integer(unsigned(aa_i)), 0, g_size-1))((i+1)*8-1 downto i*8);
+          end if;
+        end loop;
+      end if;
+    end process;
+
+    Port_B: process (clk_i)
+    begin
+      if rising_edge(clk_i) then
+        for i in 0 to c_num_bytes-1 loop
+          if s_we_b(i) = '1' then
+            ram(f_check_bounds(to_integer(unsigned(ab_i)), 0, g_size-1))((i+1)*8-1 downto i*8) := db_i((i+1)*8-1 downto i*8);
+            qb_o((i+1)*8-1 downto i*8)                                                         <= db_i((i+1)*8-1 downto i*8);
+          else
+            qb_o((i+1)*8-1 downto i*8) <= ram(f_check_bounds(to_integer(unsigned(ab_i)), 0, g_size-1))((i+1)*8-1 downto i*8);
+          end if;
+        end loop;
+      end if;
+    end process;
+
+  end generate gen_with_byte_enable_writefirst;
+
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd
new file mode 100644
index 000000000..b6d692bb8
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd
@@ -0,0 +1,233 @@
+-------------------------------------------------------------------------------
+-- Title      : Dual-port synchronous RAM with byte-write for Xilinx
+-------------------------------------------------------------------------------
+-- File       : generic_dpram_split.vhd
+-- Author     : Grzegorz Daniluk
+-- Company    : CERN BE-CO-HT
+-- Created    : 2017-02-13
+-- Last update: 2017-02-13
+-- Platform   : 
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: 
+-- This module is 32-bit RAM with byte-write enables. It was created for Xilinx
+-- FPGAs, since Xilinx ISE is unable to infer dual-port block-RAM with
+-- byte-writes (e.g. based on generic_dpram_sameclock.vhd module). When
+-- synthesizing generic_dpram_sameclock with g_with_byte_enable, ISE uses a lot
+-- of LUTs to get the byte-write behavior (instead of using the features of BRAM
+-- blocks).
+--
+-- Note:
+-- This module is hardcoded to 32-bits and 4 ram modules (ram0-3). It would be
+-- much cleaner to have a generic code and using ram(0 to g_data_width/8-1).
+-- However, it looks that ISE is not able to initialize 3-d array that would be
+-- needed in this case.
+-- I.e. this works:
+-- shared variable ram0 : t_split_ram := f_file_to_ramtype(0);
+-- shared variable ram1 : t_split_ram := f_file_to_ramtype(1);
+-- shared variable ram2 : t_split_ram := f_file_to_ramtype(2);
+-- shared variable ram3 : t_split_ram := f_file_to_ramtype(3);
+--
+-- but this doesn't:
+-- type t_split_ram_array is array(0 to 3) of t_split_ram;
+-- shared variable ram : t_split_ram_array := (f_file_to_ramtype(0),
+-- f_file_to_ramtype(1),f_file_to_ramtype(2),
+-- f_file_to_ramtype(3));
+-- 
+-- By "doesn't work" I mean that ISE does not fail during the synthesis, but RAM
+-- does not get initialized.
+-------------------------------------------------------------------------------
+-- Copyright (c) 2017 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.genram_pkg.all;
+use work.memory_loader_pkg.all;
+
+entity generic_dpram_split is
+  generic (
+    g_size                     : natural := 16384;
+    g_addr_conflict_resolution : string  := "read_first";
+    g_init_file                : string  := "";
+    g_fail_if_file_not_found   : boolean := true);
+  port (
+    rst_n_i : in std_logic := '1';
+    clk_i   : in std_logic;
+
+    -- Port A
+    bwea_i : in  std_logic_vector(3 downto 0);
+    wea_i  : in  std_logic;
+    aa_i   : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+    da_i   : in  std_logic_vector(31 downto 0);
+    qa_o   : out std_logic_vector(31 downto 0);
+
+    -- Port B
+    bweb_i : in  std_logic_vector(3 downto 0);
+    web_i  : in  std_logic;
+    ab_i   : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+    db_i   : in  std_logic_vector(31 downto 0);
+    qb_o   : out std_logic_vector(31 downto 0));
+end generic_dpram_split;
+
+architecture syn of generic_dpram_split is
+
+  constant c_data_width : integer := 32;
+  constant c_num_bytes  : integer := (c_data_width+7)/8;
+
+  type t_split_ram is array(0 to g_size-1) of std_logic_vector(7 downto 0);
+
+  impure function f_file_to_ramtype(idx : integer) return t_split_ram is
+    variable tmp    : t_split_ram;
+    variable mem8   : t_ram8_type(0 to g_size-1);
+  begin
+    -- If no file was given, there is nothing to convert, just return
+    if (g_init_file = "" or g_init_file = "none") then
+      tmp := (others=>(others=>'0'));
+      return tmp;
+    end if;
+
+    mem8 := f_load_mem32_from_file_split(g_init_file, g_size, g_fail_if_file_not_found, idx);
+    return t_split_ram(mem8);
+  end f_file_to_ramtype;
+
+  impure function f_file_contents return t_meminit_array is
+  begin
+    return f_load_mem_from_file(g_init_file, g_size, c_data_width, g_fail_if_file_not_found);
+  end f_file_contents;
+
+  shared variable ram0 : t_split_ram := f_file_to_ramtype(0);
+  shared variable ram1 : t_split_ram := f_file_to_ramtype(1);
+  shared variable ram2 : t_split_ram := f_file_to_ramtype(2);
+  shared variable ram3 : t_split_ram := f_file_to_ramtype(3);
+
+  signal s_we_a  : std_logic_vector(c_num_bytes-1 downto 0);
+  signal s_we_b  : std_logic_vector(c_num_bytes-1 downto 0);
+  signal wea_rep : std_logic_vector(c_num_bytes-1 downto 0);
+  signal web_rep : std_logic_vector(c_num_bytes-1 downto 0);
+
+begin
+
+  assert (g_addr_conflict_resolution = "read_first" or g_addr_conflict_resolution = "dont_care") 
+  report "generic_dpram_split: only read_first and dont_care supported for now" severity failure;
+
+  -- combine byte-write enable with write signals
+  wea_rep <= (others => wea_i);
+  web_rep <= (others => web_i);
+  s_we_a <= bwea_i and wea_rep;
+  s_we_b <= bweb_i and web_rep;
+
+  --------------------------------------------------
+  -- yes, I know this is 4 times exactly the same code for ram0,1,2,3,
+  -- but ISE fails to initialize BRAM when ram is an array (check Note
+  -- in the header of this file).
+  GEN_RAM0_Port_A: process (clk_i)
+  begin
+    if rising_edge(clk_i) then
+      qa_o(7 downto 0) <= ram0(f_check_bounds(to_integer(unsigned(aa_i)), 0, g_size-1));
+      if s_we_a(0) = '1' then
+        ram0(f_check_bounds(to_integer(unsigned(aa_i)), 0, g_size-1)) := da_i(7 downto 0);
+      end if;
+    end if;
+  end process;
+
+  GEN_RAM0_Port_B: process (clk_i)
+  begin
+    if rising_edge(clk_i) then
+      qb_o(7 downto 0) <= ram0(f_check_bounds(to_integer(unsigned(ab_i)), 0, g_size-1));
+      if s_we_b(0) = '1' then
+        ram0(f_check_bounds(to_integer(unsigned(ab_i)), 0, g_size-1)) := db_i(7 downto 0);
+      end if;
+    end if;
+  end process;
+
+  --------------------------------------------------
+
+  GEN_RAM1_Port_A: process (clk_i)
+  begin
+    if rising_edge(clk_i) then
+      qa_o(15 downto 8) <= ram1(f_check_bounds(to_integer(unsigned(aa_i)), 0, g_size-1));
+      if s_we_a(1) = '1' then
+        ram1(f_check_bounds(to_integer(unsigned(aa_i)), 0, g_size-1)) := da_i(15 downto 8);
+      end if;
+    end if;
+  end process;
+
+  GEN_RAM1_Port_B: process (clk_i)
+  begin
+    if rising_edge(clk_i) then
+      qb_o(15 downto 8) <= ram1(f_check_bounds(to_integer(unsigned(ab_i)), 0, g_size-1));
+      if s_we_b(1) = '1' then
+        ram1(f_check_bounds(to_integer(unsigned(ab_i)), 0, g_size-1)) := db_i(15 downto 8);
+      end if;
+    end if;
+  end process;
+
+  --------------------------------------------------
+
+  GEN_RAM2_Port_A: process (clk_i)
+  begin
+    if rising_edge(clk_i) then
+      qa_o(23 downto 16) <= ram2(f_check_bounds(to_integer(unsigned(aa_i)), 0, g_size-1));
+      if s_we_a(2) = '1' then
+        ram2(f_check_bounds(to_integer(unsigned(aa_i)), 0, g_size-1)) := da_i(23 downto 16);
+      end if;
+    end if;
+  end process;
+
+  GEN_RAM2_Port_B: process (clk_i)
+  begin
+    if rising_edge(clk_i) then
+      qb_o(23 downto 16) <= ram2(f_check_bounds(to_integer(unsigned(ab_i)), 0, g_size-1));
+      if s_we_b(2) = '1' then
+        ram2(f_check_bounds(to_integer(unsigned(ab_i)), 0, g_size-1)) := db_i(23 downto 16);
+      end if;
+    end if;
+  end process;
+
+  --------------------------------------------------
+
+  GEN_RAM3_Port_A: process (clk_i)
+  begin
+    if rising_edge(clk_i) then
+      qa_o(31 downto 24) <= ram3(f_check_bounds(to_integer(unsigned(aa_i)), 0, g_size-1));
+      if s_we_a(3) = '1' then
+        ram3(f_check_bounds(to_integer(unsigned(aa_i)), 0, g_size-1)) := da_i(31 downto 24);
+      end if;
+    end if;
+  end process;
+
+  GEN_RAM3_Port_B: process (clk_i)
+  begin
+    if rising_edge(clk_i) then
+      qb_o(31 downto 24) <= ram3(f_check_bounds(to_integer(unsigned(ab_i)), 0, g_size-1));
+      if s_we_b(3) = '1' then
+        ram3(f_check_bounds(to_integer(unsigned(ab_i)), 0, g_size-1)) := db_i(31 downto 24);
+      end if;
+    end if;
+  end process;
+
+  --------------------------------------------------
+
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd
new file mode 100644
index 000000000..5eb14729a
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd
@@ -0,0 +1,100 @@
+-------------------------------------------------------------------------------
+-- Title      : Parametrizable dual-port synchronous RAM (Xilinx version)
+-- Project    : Generics RAMs and FIFOs collection
+-------------------------------------------------------------------------------
+-- File       : generic_simple_dpram.vhd
+-- Author     : Wesley W. Terpstra
+-- Company    : GSI
+-- Created    : 2013-03-04
+-- Last update: 2013-10-30
+-- Platform   : 
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: True dual-port synchronous RAM for Xilinx FPGAs with:
+-- - configurable address and data bus width
+-- - byte-addressing mode (data bus width restricted to multiple of 8 bits)
+-- Todo:
+-- - loading initial contents from file
+-- - add support for read-first/write-first address conflict resulution (only
+--   supported by Xilinx in VHDL templates)
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011 CERN
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2013-03-04  1.0      wterpstra       Initial version: wrapper to generic_dpram
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.textio.all;
+
+library work;
+use work.genram_pkg.all;
+use work.memory_loader_pkg.all;
+
+entity generic_simple_dpram is
+
+  generic (
+    -- standard parameters
+    g_data_width : natural := 32;
+    g_size       : natural := 16384;
+
+    g_with_byte_enable         : boolean := false;
+    g_addr_conflict_resolution : string  := "read_first";
+    g_init_file                : string  := "";
+    g_dual_clock               : boolean := true;
+    g_fail_if_file_not_found   : boolean := true
+    );
+
+  port (
+    rst_n_i : in std_logic := '1';      -- synchronous reset, active LO
+
+    -- Port A
+    clka_i : in  std_logic;
+    bwea_i : in  std_logic_vector((g_data_width+7)/8-1 downto 0);
+    wea_i  : in  std_logic;
+    aa_i   : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+    da_i   : in  std_logic_vector(g_data_width-1 downto 0);
+    
+    -- Port B
+    clkb_i : in  std_logic;
+    ab_i   : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+    qb_o   : out std_logic_vector(g_data_width-1 downto 0)
+    );
+
+end generic_simple_dpram;
+
+
+
+architecture syn of generic_simple_dpram is
+
+begin
+
+  -- Works well enough until a Xilinx guru can optimize it.
+  true_dp : generic_dpram
+    generic map(
+      g_data_width               => g_data_width,
+      g_size                     => g_size,
+      g_with_byte_enable         => g_with_byte_enable,
+      g_addr_conflict_resolution => g_addr_conflict_resolution,
+      g_init_file                => g_init_file,
+      g_dual_clock               => g_dual_clock)
+    port map(
+      rst_n_i => rst_n_i,
+      clka_i  => clka_i,
+      bwea_i  => bwea_i,
+      wea_i   => wea_i,
+      aa_i    => aa_i,
+      da_i    => da_i,
+      qa_o    => open,
+      clkb_i  => clkb_i,
+      bweb_i  => f_zeros((g_data_width+7)/8),
+      web_i   => '0',
+      ab_i    => ab_i,
+      db_i    => f_zeros(g_data_width),
+      qb_o    => qb_o);
+
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/axi4_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/axi4_pkg.vhd
new file mode 100644
index 000000000..cde1f31bb
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/axi4_pkg.vhd
@@ -0,0 +1,253 @@
+-------------------------------------------------------------------------------
+-- Title      : AXI4Lite-to-WB bridge package
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : axi4_pkg.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.wishbone_pkg.all;
+
+package axi4_pkg is
+
+  -- AXI4-Full interface, master output ports, 32 bits
+  type t_axi4_full_master_out_32 is record
+    ARVALID : std_logic;
+    AWVALID : std_logic;
+    BREADY  : std_logic;
+    RREADY  : std_logic;
+    WLAST   : std_logic;
+    WVALID  : std_logic;
+    ARID    : std_logic_vector (11 downto 0);
+    AWID    : std_logic_vector (11 downto 0);
+    WID     : std_logic_vector (11 downto 0);
+    ARBURST : std_logic_vector (1 downto 0);
+    ARLOCK  : std_logic_vector (1 downto 0);
+    ARSIZE  : std_logic_vector (2 downto 0);
+    AWBURST : std_logic_vector (1 downto 0);
+    AWLOCK  : std_logic_vector (1 downto 0);
+    AWSIZE  : std_logic_vector (2 downto 0);
+    ARPROT  : std_logic_vector (2 downto 0);
+    AWPROT  : std_logic_vector (2 downto 0);
+    ARADDR  : std_logic_vector (31 downto 0);
+    AWADDR  : std_logic_vector (31 downto 0);
+    WDATA   : std_logic_vector (31 downto 0);
+    ARCACHE : std_logic_vector (3 downto 0);
+    ARLEN   : std_logic_vector (3 downto 0);
+    ARQOS   : std_logic_vector (3 downto 0);
+    AWCACHE : std_logic_vector (3 downto 0);
+    AWLEN   : std_logic_vector (3 downto 0);
+    AWQOS   : std_logic_vector (3 downto 0);
+    WSTRB   : std_logic_vector (3 downto 0);
+  end record;
+
+  -- AXI4-Full interface, master input ports, 32 bits
+  type t_axi4_full_master_in_32 is record
+    ARREADY : std_logic;
+    AWREADY : std_logic;
+    BVALID  : std_logic;
+    RLAST   : std_logic;
+    RVALID  : std_logic;
+    WREADY  : std_logic;
+    BID     : std_logic_vector (11 downto 0);
+    RID     : std_logic_vector (11 downto 0);
+    BRESP   : std_logic_vector (1 downto 0);
+    RRESP   : std_logic_vector (1 downto 0);
+    RDATA   : std_logic_vector (31 downto 0);
+  end record;
+
+  -- AXI4-Lite interface, master output ports, 32 bits
+  type t_axi4_lite_master_out_32 is record
+    ARVALID : std_logic;
+    AWVALID : std_logic;
+    BREADY  : std_logic;
+    RREADY  : std_logic;
+    WLAST   : std_logic;
+    WVALID  : std_logic;
+    ARADDR  : std_logic_vector (31 downto 0);
+    AWADDR  : std_logic_vector (31 downto 0);
+    WDATA   : std_logic_vector (31 downto 0);
+    WSTRB   : std_logic_vector (3 downto 0);
+  end record;
+
+  -- AXI4-Lite interface, master input ports, 32 bits
+  type t_axi4_lite_master_in_32 is record
+    ARREADY : std_logic;
+    AWREADY : std_logic;
+    BVALID  : std_logic;
+    RLAST   : std_logic;
+    RVALID  : std_logic;
+    WREADY  : std_logic;
+    BRESP   : std_logic_vector (1 downto 0);
+    RRESP   : std_logic_vector (1 downto 0);
+    RDATA   : std_logic_vector (31 downto 0);
+  end record;
+
+  constant c_axi4_lite_default_master_in_32 : t_axi4_lite_master_in_32 :=
+    (
+      AWREADY => '0',
+      ARREADY => '0',
+      BVALID  => '0',
+      RLAST   => '0',
+      RVALID  => '0',
+      WREADY  => '0',
+      BRESP   => "00",
+      RRESP   => "00",
+      RDATA   => (others => '0')
+      );
+
+
+  constant c_axi4_lite_default_master_out_32 : t_axi4_lite_master_out_32 :=
+    (
+      ARVALID => '0',
+      AWVALID => '0',
+      BREADY  => '0',
+      RREADY  => '0',
+      WLAST   => '0',
+      WVALID  => '0',
+      ARADDR  => (others => '0'),
+      AWADDR  => (others => '0'),
+      WDATA   => (others => '0'),
+      WSTRB   => (others => '0')
+      );
+
+
+
+  subtype t_axi4_lite_slave_in_32 is t_axi4_lite_master_out_32;
+  subtype t_axi4_lite_slave_out_32 is t_axi4_lite_master_in_32;
+
+  constant c_AXI4_RESP_OKAY   : std_logic_vector(1 downto 0) := "00";
+  constant c_AXI4_RESP_EXOKAY : std_logic_vector(1 downto 0) := "01";
+  constant c_AXI4_RESP_SLVERR : std_logic_vector(1 downto 0) := "10";
+  constant c_AXI4_RESP_DECERR : std_logic_vector(1 downto 0) := "11";
+
+    function f_axi4_full_to_lite (
+    f : t_axi4_full_master_out_32
+    )  return t_axi4_lite_master_out_32;
+  
+  function f_axi4_lite_to_full (
+    l : t_axi4_lite_master_in_32
+    )  return t_axi4_full_master_in_32;
+
+  component xwb_axi4lite_bridge is
+    port (
+      clk_sys_i    : in  std_logic;
+      rst_n_i      : in  std_logic;
+      axi4_slave_i : in  t_axi4_lite_slave_in_32;
+      axi4_slave_o : out t_axi4_lite_slave_out_32;
+      wb_master_o  : out t_wishbone_master_out;
+      wb_master_i  : in  t_wishbone_master_in);
+  end component xwb_axi4lite_bridge;
+
+  component wb_axi4lite_bridge is
+    port (
+      clk_sys_i : in std_logic;
+      rst_n_i   : in std_logic;
+  
+      ARVALID : in  std_logic;
+      AWVALID : in  std_logic;
+      BREADY  : in  std_logic;
+      RREADY  : in  std_logic;
+      WLAST   : in  std_logic;
+      WVALID  : in  std_logic;
+      ARADDR  : in  std_logic_vector (31 downto 0);
+      AWADDR  : in  std_logic_vector (31 downto 0);
+      WDATA   : in  std_logic_vector (31 downto 0);
+      WSTRB   : in  std_logic_vector (3 downto 0);
+      ARREADY : out std_logic;
+      AWREADY : out std_logic;
+      BVALID  : out std_logic;
+      RLAST   : out std_logic;
+      RVALID  : out std_logic;
+      WREADY  : out std_logic;
+      BRESP   : out std_logic_vector (1 downto 0);
+      RRESP   : out std_logic_vector (1 downto 0);
+      RDATA   : out std_logic_vector (31 downto 0);
+  
+      wb_adr : out std_logic_vector(c_wishbone_address_width-1 downto 0);
+      wb_dat_m2s : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+      wb_sel : out std_logic_vector(c_wishbone_data_width/8-1 downto 0);
+      wb_cyc : out std_logic;
+      wb_stb : out std_logic;
+      wb_we  : out std_logic;
+  
+      wb_dat_s2m   : in std_logic_vector(c_wishbone_data_width-1 downto 0);
+      wb_err   : in std_logic := '0';
+      wb_rty   : in std_logic := '0';
+      wb_ack   : in std_logic;
+      wb_stall : in std_logic
+      );
+  end component;
+  
+end package;
+
+package body axi4_pkg is
+
+    function f_axi4_full_to_lite (
+    f : t_axi4_full_master_out_32
+    )  return t_axi4_lite_master_out_32 is
+    variable l : t_axi4_lite_master_out_32;
+  begin
+
+    l.ARVALID := f.ARVALID;
+    l.AWVALID := f.AWVALID;
+    l.BREADY  := f.BREADY;
+    l.RREADY  := f.RREADY;
+    l.WLAST   := f.WLAST;
+    l.WVALID  := f.WVALID;
+    l.ARADDR  := f.ARADDR;
+    l.AWADDR  := f.AWADDR;
+    l.WDATA   := f.WDATA;
+    l.WSTRB   := f.WSTRB;
+
+    return l;
+    
+  end f_axi4_full_to_lite;
+
+  function f_axi4_lite_to_full (
+    l : t_axi4_lite_master_in_32
+    )  return t_axi4_full_master_in_32 is
+    variable f : t_axi4_full_master_in_32;
+  begin
+    f.ARREADY := l.ARREADY;
+    f.AWREADY := l.AWREADY;
+    f.BVALID  := l.BVALID;
+    f.RLAST   := l.RLAST;
+    f.RVALID  := l.RVALID;
+    f.WREADY  := l.WREADY;
+    f.BID     := (others => '0');
+    f.RID     := (others => '0');
+    f.BRESP   := l.BRESP;
+    f.RRESP   := l.RRESP;
+    f.RDATA   := l.RDATA;
+
+    return f;
+    
+  end f_axi4_lite_to_full;
+
+
+end package body;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd
new file mode 100644
index 000000000..b8e63eca3
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd
@@ -0,0 +1,131 @@
+-------------------------------------------------------------------------------
+-- Title      : AXI4Lite-to-WB bridge
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : wb_axi4lite_bridge.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.axi4_pkg.all;
+use work.wishbone_pkg.all;
+
+entity wb_axi4lite_bridge is
+  port (
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    ARVALID : in  std_logic;
+    AWVALID : in  std_logic;
+    BREADY  : in  std_logic;
+    RREADY  : in  std_logic;
+    WLAST   : in  std_logic;
+    WVALID  : in  std_logic;
+    ARADDR  : in  std_logic_vector (31 downto 0);
+    AWADDR  : in  std_logic_vector (31 downto 0);
+    WDATA   : in  std_logic_vector (31 downto 0);
+    WSTRB   : in  std_logic_vector (3 downto 0);
+    ARREADY : out std_logic;
+    AWREADY : out std_logic;
+    BVALID  : out std_logic;
+    RLAST   : out std_logic;
+    RVALID  : out std_logic;
+    WREADY  : out std_logic;
+    BRESP   : out std_logic_vector (1 downto 0);
+    RRESP   : out std_logic_vector (1 downto 0);
+    RDATA   : out std_logic_vector (31 downto 0);
+
+    wb_adr : out std_logic_vector(c_wishbone_address_width-1 downto 0);
+    wb_dat_m2s : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+    wb_sel : out std_logic_vector(c_wishbone_data_width/8-1 downto 0);
+    wb_cyc : out std_logic;
+    wb_stb : out std_logic;
+    wb_we  : out std_logic;
+
+    wb_dat_s2m   : in std_logic_vector(c_wishbone_data_width-1 downto 0);
+    wb_err   : in std_logic := '0';
+    wb_rty   : in std_logic := '0';
+    wb_ack   : in std_logic;
+    wb_stall : in std_logic
+    );
+
+end wb_axi4lite_bridge;
+
+architecture rtl of wb_axi4lite_bridge is
+
+  signal axi_in  : t_axi4_lite_master_out_32;
+  signal axi_out : t_axi4_lite_master_in_32;
+  signal wb_in   : t_wishbone_master_in;
+  signal wb_out  : t_wishbone_master_out;
+  
+begin
+
+  axi_in.ARVALID  <= ARVALID;
+  axi_in.AWVALID <= AWVALID;
+  axi_in.BREADY  <= BREADY;
+  axi_in.RREADY  <= RREADY;
+  axi_in.WLAST   <= WLAST;
+  axi_in.WVALID  <= WVALID;
+  axi_in.ARADDR  <= ARADDR;
+  axi_in.AWADDR  <= AWADDR;
+  axi_in.WDATA   <= WDATA;
+  axi_in.WSTRB   <= WSTRB;
+  ARREADY         <= axi_out.ARREADY;
+  AWREADY         <= axi_out.AWREADY;
+  BVALID          <= axi_out.BVALID;
+  RLAST           <= axi_out.RLAST;
+  RVALID          <= axi_out.RVALID;
+  WREADY          <= axi_out.WREADY;
+  BRESP           <= axi_out.BRESP;
+  RRESP           <= axi_out.RRESP;
+  RDATA           <= axi_out.RDATA;
+
+  wb_adr <= wb_out.adr;
+  wb_dat_m2s <= wb_out.dat;
+  wb_stb <= wb_out.stb;
+  wb_sel <= wb_out.sel;
+  wb_cyc <= wb_out.cyc;
+  wb_we <= wb_out.we;
+
+  wb_in.err <= wb_err;
+  wb_in.rty <= wb_rty;
+  wb_in.ack <= wb_ack;
+  wb_in.int <= '0';
+  wb_in.stall <= wb_stall;
+  wb_in.dat <= wb_dat_s2m;
+
+  U_Wrapped_Bridge : xwb_axi4lite_bridge
+    port map (
+      clk_sys_i    => clk_sys_i,
+      rst_n_i      => rst_n_i,
+      axi4_slave_i => axi_in,
+      axi4_slave_o => axi_out,
+      wb_master_o  => wb_out,
+      wb_master_i  => wb_in);
+  
+end rtl;
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd
new file mode 100644
index 000000000..51838931a
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd
@@ -0,0 +1,196 @@
+-------------------------------------------------------------------------------
+-- Title      : AXI4Lite-to-WB bridge wrapper
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : xwb_axi4lite_bridge.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.axi4_pkg.all;
+use work.wishbone_pkg.all;
+
+entity xwb_axi4lite_bridge is
+  port (
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    axi4_slave_i : in  t_axi4_lite_slave_in_32;
+    axi4_slave_o : out t_axi4_lite_slave_out_32;
+
+    wb_master_o : out t_wishbone_master_out;
+    wb_master_i : in  t_wishbone_master_in
+
+    );
+
+end xwb_axi4lite_bridge;
+
+architecture rtl of xwb_axi4lite_bridge is
+
+  constant c_timeout : integer := 256;
+
+  type t_state is
+    (IDLE, ISSUE_WRITE, ISSUE_READ, COMPLETE_WRITE, COMPLETE_READ, WAIT_ACK_READ, WAIT_ACK_WRITE, RESPONSE_READ, RESPONSE_WRITE);
+
+  signal state : t_state;
+
+  signal count : unsigned(10 downto 0);
+  
+begin
+
+  process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        axi4_slave_o    <= c_axi4_lite_default_master_in_32;
+        wb_master_o.cyc <= '0';
+        state           <= IDLE;
+      else
+        case state is
+          when IDLE =>
+            wb_master_o.cyc      <= '0';
+            axi4_slave_o.ARREADY <= '1';
+            axi4_slave_o.AWREADY <= '1';
+            axi4_slave_o.WREADY  <= '0';
+            axi4_slave_o.BVALID  <= '0';
+            axi4_slave_o.BRESP   <= (others => 'X');
+            axi4_slave_o.RDATA  <= (others => 'X');
+            axi4_slave_o.RRESP  <= (others => 'X');
+            axi4_slave_o.RVALID <= '0';
+            axi4_slave_o.RLAST <= '0';
+            
+            if(axi4_slave_i.AWVALID = '1') then
+              state           <= ISSUE_WRITE;
+              wb_master_o.adr <= axi4_slave_i.AWADDR;
+            elsif (axi4_slave_i.ARVALID = '1') then
+              state           <= ISSUE_READ;
+              wb_master_o.adr <= axi4_slave_i.ARADDR;
+            end if;
+
+          when ISSUE_WRITE =>
+            axi4_slave_o.WREADY <= '1';
+
+            wb_master_o.cyc <= '1';
+            wb_master_o.we  <= '1';
+
+            if(axi4_slave_i.WVALID = '1') then
+              wb_master_o.stb <= '1';
+              wb_master_o.sel <= axi4_slave_i.WSTRB;
+              wb_master_o.dat <= axi4_slave_i.WDATA;
+              state           <= COMPLETE_WRITE;
+            end if;
+
+          when ISSUE_READ =>
+
+            wb_master_o.cyc <= '1';
+            wb_master_o.stb <= '1';
+            wb_master_o.we  <= '0';
+            axi4_slave_o.RVALID <= '0';
+            axi4_slave_o.RLAST <= '0';
+            state <= COMPLETE_READ;
+
+          when COMPLETE_READ =>
+            if(wb_master_i.stall = '0') then
+              wb_master_o.stb <= '0';
+              if(wb_master_i.ack = '1') then
+                state <= IDLE;
+                axi4_slave_o.RRESP <= c_AXI4_RESP_EXOKAY;
+                axi4_slave_o.RDATA <= wb_master_i.dat;
+                axi4_slave_o.RVALID <= '1';
+                axi4_slave_o.RLAST <= '1';
+                wb_master_o.cyc    <= '0';
+              else
+                state <= WAIT_ACK_READ;
+                count <= (others => '0');
+              end if;
+            end if;
+
+            
+          when COMPLETE_WRITE =>
+            if(wb_master_i.stall = '0') then
+              wb_master_o.stb <= '0';
+              if(wb_master_i.ack = '1') then
+                state <= RESPONSE_WRITE;
+                axi4_slave_o.BRESP <= c_AXI4_RESP_EXOKAY;
+                wb_master_o.cyc    <= '0';
+              else
+                state <= WAIT_ACK_WRITE;
+                count <= (others => '0');
+              end if;
+            end if;
+
+
+          when WAIT_ACK_WRITE =>
+            if(wb_master_i.ack = '1') then
+              state              <= RESPONSE_WRITE;
+              axi4_slave_o.BRESP <= c_AXI4_RESP_EXOKAY;
+              wb_master_o.cyc    <= '0';
+            elsif count = c_timeout then
+              state              <= RESPONSE_WRITE;
+              axi4_slave_o.BRESP <= c_AXI4_RESP_SLVERR;
+              wb_master_o.cyc    <= '0';
+            end if;
+            count <= count + 1;
+
+          when WAIT_ACK_READ =>
+            if(wb_master_i.ack = '1') then
+              state              <= IDLE;
+              axi4_slave_o.RRESP <= c_AXI4_RESP_EXOKAY;
+              axi4_slave_o.RVALID <= '1';
+              axi4_slave_o.RLAST <= '1';
+              axi4_slave_o.RDATA <= wb_master_i.dat;
+              wb_master_o.cyc    <= '0';
+            elsif count = c_timeout then
+              state              <= IDLE;
+              axi4_slave_o.RRESP <= c_AXI4_RESP_SLVERR;
+              axi4_slave_o.RVALID <= '1';
+              axi4_slave_o.RLAST <= '1';
+              axi4_slave_o.RDATA <= (others => 'X');
+              wb_master_o.cyc    <= '0';
+            end if;
+            count <= count + 1;
+
+            
+          when RESPONSE_WRITE =>
+            if (axi4_slave_i.BREADY = '1') then
+              axi4_slave_o.BVALID <= '1';
+              state               <= IDLE;
+            end if;
+
+          when RESPONSE_READ => null;
+            
+            
+        end case;
+
+
+
+      end if;
+    end if;
+  end process;
+
+end rtl;
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd
new file mode 100644
index 000000000..9ca049b71
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd
@@ -0,0 +1,160 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.wishbone_pkg.all;
+
+entity sdb_rom is
+  generic(
+    g_layout   : t_sdb_record_array;
+    g_masters  : natural;
+    g_bus_end  : unsigned(63 downto 0);
+    g_sdb_name : string := "WB4-Crossbar-GSI   ");
+  port(
+    clk_sys_i  : in  std_logic;
+    master_i   : in  std_logic_vector(g_masters-1 downto 0);
+    slave_i    : in  t_wishbone_slave_in;
+    slave_o    : out t_wishbone_slave_out);
+end sdb_rom;
+
+architecture rtl of sdb_rom is
+  alias c_layout : t_sdb_record_array(g_layout'length downto 1) is g_layout;
+
+  -- The ROM must describe all slaves, the crossbar itself and the optional information records
+  constant c_used_entries   : natural := c_layout'high + 1;
+  constant c_rom_entries    : natural := 2**f_ceil_log2(c_used_entries); -- next power of 2
+  constant c_sdb_words      : natural := c_sdb_device_length / c_wishbone_data_width;
+  constant c_rom_words      : natural := c_rom_entries * c_sdb_words;
+  constant c_rom_depth      : natural := f_ceil_log2(c_rom_words);
+  constant c_rom_lowbits    : natural := f_ceil_log2(c_wishbone_data_width / 8);
+  constant c_sdb_name       : string  := f_string_fix_len(g_sdb_name , 19, ' ', false);
+  
+  -- Index of the MSI entry in SDB
+  type t_nat_array is array(g_masters-1 downto 0) of natural;
+  function f_master_positions return t_nat_array is
+    variable typ    : std_logic_vector(7 downto 0);
+    variable result : t_nat_array;
+    variable master : natural := 0;
+  begin
+    for rec in c_layout'low to c_layout'high loop
+      typ := c_layout(rec)(7 downto 0);
+      case typ is
+        when x"03" | x"f3" =>
+          assert master < g_masters
+          report "Too many msi records found"
+          severity failure;
+        
+          result(master) := rec;
+          master := master + 1;
+        
+        when others => null;
+      end case;
+    end loop;
+    
+    if master = 0 then
+      result := (others => 0);
+    else
+      assert master = g_masters
+      report "Insufficient msi records found (" & Integer'image(master) & "/" & Integer'image(g_masters) & ")"
+      severity failure;
+    end if;
+    return result;
+  end f_master_positions;
+  
+  constant c_master_positions : t_nat_array := f_master_positions;
+  constant c_msi              : boolean     := c_master_positions(0) /= 0;
+  
+  function f_msi_flag_index(y : std_logic_vector) return std_logic_vector is
+    variable offset : unsigned(c_rom_depth-1 downto 0) := (others => '0');
+    variable result : std_logic_vector(c_rom_depth-1 downto 0) := (others => '0');
+  begin
+    for i in c_master_positions'range loop
+      if c_msi then
+        offset := to_unsigned(c_master_positions(i)*16, offset'length);
+      end if;
+      for b in result'range loop
+        result(b) := result(b) or (offset(b) and y(i));
+      end loop;
+    end loop;
+    return result;
+  end f_msi_flag_index;
+  
+  type t_rom is array(c_rom_words-1 downto 0) of t_wishbone_data;
+
+  function f_build_rom
+    return t_rom 
+  is
+    variable res : t_rom := (others => (others => '0'));
+    variable sdb_record : t_sdb_record;
+    variable sdb_component : t_sdb_component;
+  begin
+    sdb_record(511 downto 480) := x"5344422D"  ;                                     -- sdb_magic
+    sdb_record(479 downto 464) := std_logic_vector(to_unsigned(c_used_entries, 16)); -- sdb_records
+    sdb_record(463 downto 456) := x"01";                                             -- sdb_version
+    sdb_record(455 downto 448) := x"00";                                             -- sdb_bus_type = sdb_wishbone
+    sdb_record(  7 downto   0) := x"00";                                             -- record_type  = sdb_interconnect
+    
+    sdb_component.addr_first := (others => '0');
+    sdb_component.addr_last  := std_logic_vector(g_bus_end);
+    sdb_component.product.vendor_id := x"0000000000000651"; -- GSI
+    sdb_component.product.device_id := x"e6a542c9";
+    sdb_component.product.version   := x"00000003";
+    sdb_component.product.date      := x"20120511";
+    sdb_component.product.name      := c_sdb_name;
+    sdb_record(447 downto   8) := f_sdb_embed_component(sdb_component, (others => '0'));
+    
+    for i in 0 to c_sdb_words-1 loop
+      res(c_sdb_words-1-i) := 
+        sdb_record((i+1)*c_wishbone_data_width-1 downto i*c_wishbone_data_width);
+    end loop;
+    
+    for idx in c_layout'range loop
+      sdb_record := c_layout(idx);
+      
+      -- All local/temporary types => empty record
+      if sdb_record(7 downto 4) = x"f" then
+        sdb_record(3 downto 0) := x"f";
+      end if;
+      
+      for i in 0 to c_sdb_words-1 loop
+        res((idx+1)*c_sdb_words-1-i) := 
+          sdb_record((i+1)*c_wishbone_data_width-1 downto i*c_wishbone_data_width);
+      end loop;
+    end loop;
+    
+    return res;
+  end f_build_rom;
+  
+  signal rom : t_rom := f_build_rom;
+
+  signal s_adr : unsigned(c_rom_depth-1 downto 0);
+  signal s_sel : unsigned(c_rom_depth-1 downto 0);
+  
+  signal r_rom  : t_wishbone_data;
+  signal r_flag : t_wishbone_data;
+  signal r_ack  : std_logic;
+
+begin
+
+  slave_o.dat <= r_rom or r_flag;
+  slave_o.ack <= r_ack;
+  slave_o.err   <= '0';
+  slave_o.rty   <= '0';
+  slave_o.stall <= '0';
+  slave_o.int   <= '0'; -- Tom sucks! This should not be here.
+
+  s_adr <= unsigned(slave_i.adr(c_rom_depth+c_rom_lowbits-1 downto c_rom_lowbits));
+  s_sel <= unsigned(f_msi_flag_index(master_i));
+  
+  slave_clk : process(clk_sys_i)
+  begin
+    if (rising_edge(clk_sys_i)) then
+      r_ack <= slave_i.cyc and slave_i.stb;
+      r_rom  <= rom(to_integer(s_adr));
+      r_flag <= (others => '0');
+      if s_adr = s_sel and c_msi then
+        r_flag(r_flag'high) <= '1';
+      end if;
+    end if;
+  end process;
+  
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd
new file mode 100644
index 000000000..265e3495b
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd
@@ -0,0 +1,427 @@
+-------------------------------------------------------------------------------
+-- Title      : An MxS Wishbone crossbar switch
+-- Project    : General Cores Library (gencores)
+-------------------------------------------------------------------------------
+-- File       : xwb_crossbar.vhd
+-- Author     : Wesley W. Terpstra
+-- Company    : GSI
+-- Created    : 2011-06-08
+-- Last update: 2011-09-22
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description:
+--
+-- An MxS Wishbone crossbar switch
+-- 
+-- All masters, slaves, and the crossbar itself must share the same WB clock.
+-- All participants must support the same data bus width. 
+-- 
+-- If a master raises STB_O with an address not mapped by the crossbar,
+-- ERR_I will be raised. If two masters address the same slave
+-- simultaneously, the lowest numbered master is granted access.
+-- 
+-- The implementation of this crossbar locks a master to a slave so long as
+-- CYC_O is held high. 
+-- 
+-- Synthesis/timing relevant facts:
+--   (m)asters, (s)laves, masked (a)ddress bits
+--   
+--   Area required       = O(ms log(ma))
+--   Arbitration depth   = O(log(msa))
+--   Master->Slave depth = O(log(m))
+--   Slave->Master depth = O(log(s))
+-- 
+--   If g_registered = false, arbitration depth is added to M->S and S->M.
+--
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011 GSI / Wesley W. Terpstra
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2012-03-05  3.0      wterpstra       made address generic and check overlap
+-- 2011-11-04  2.0      wterpstra       timing improvements
+-- 2011-06-08  1.0      wterpstra       import from SVN
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.wishbone_pkg.all;
+
+entity xwb_crossbar is
+  generic(
+    g_num_masters : integer := 2;
+    g_num_slaves  : integer := 1;
+    g_registered  : boolean := false;
+    -- Address of the slaves connected
+    g_address     : t_wishbone_address_array;
+    g_mask        : t_wishbone_address_array);
+  port(
+    clk_sys_i     : in  std_logic;
+    rst_n_i       : in  std_logic;
+    -- Master connections (INTERCON is a slave)
+    slave_i       : in  t_wishbone_slave_in_array(g_num_masters-1 downto 0);
+    slave_o       : out t_wishbone_slave_out_array(g_num_masters-1 downto 0);
+    -- Slave connections (INTERCON is a master)
+    master_i      : in  t_wishbone_master_in_array(g_num_slaves-1 downto 0);
+    master_o      : out t_wishbone_master_out_array(g_num_slaves-1 downto 0);
+    -- Master granted access to SDB for use by MSI crossbar (please ignore it)
+    sdb_sel_o     : out std_logic_vector(g_num_masters-1 downto 0));
+end xwb_crossbar;
+
+architecture rtl of xwb_crossbar is
+  alias c_address : t_wishbone_address_array(g_num_slaves-1 downto 0) is g_address;
+  alias c_mask    : t_wishbone_address_array(g_num_slaves-1 downto 0) is g_mask;
+
+  -- Confirm that no address ranges overlap
+  function f_ranges_ok
+    return boolean
+  is
+    constant zero  : t_wishbone_address := (others => '0');
+    constant align : std_logic_vector(f_ceil_log2(c_wishbone_data_width)-4 downto 0) := (others => '0');
+  begin
+    -- all (i,j) with 0 <= i < j < n
+    if g_num_slaves > 1 then
+      for i in 0 to g_num_slaves-2 loop
+        for j in i+1 to g_num_slaves-1 loop
+          assert not (((c_mask(i) and c_mask(j)) and (c_address(i) xor c_address(j))) = zero) or
+                 ((c_mask(i) or not c_address(i)) = zero) or -- disconnected slave?
+                 ((c_mask(j) or not c_address(j)) = zero)    -- disconnected slave?
+          report "Address ranges must be distinct (slaves " & 
+                 Integer'image(i) & "[" & f_bits2string(c_address(i)) & "/" &
+                                          f_bits2string(c_mask(i)) & "] & " & 
+                 Integer'image(j) & "[" & f_bits2string(c_address(j)) & "/" &
+                                          f_bits2string(c_mask(j)) & "])"
+          severity Failure;
+        end loop;
+      end loop;
+    end if;
+    for i in 0 to g_num_slaves-1 loop
+      assert (c_address(i) and not c_mask(i)) = zero or -- at least 1 bit outside mask
+             (not c_address(i) or c_mask(i))  = zero    -- all bits outside mask (= disconnected)
+      report "Address bits not in mask; slave #" & 
+             Integer'image(i) & "[" & f_bits2string(c_address(i)) & "/" &
+                                      f_bits2string(c_mask(i)) & "]"
+      severity Failure;
+      
+      assert c_mask(i)(align'range) = align
+      report "Address space smaller than a wishbone register; slave #" & 
+             Integer'image(i) & "[" & f_bits2string(c_address(i)) & "/" &
+                                      f_bits2string(c_mask(i)) & "]"
+      severity Failure;
+      
+      -- Working case
+      report "Mapping slave #" & 
+             Integer'image(i) & "[" & f_bits2string(c_address(i)) & "/" &
+                                      f_bits2string(c_mask(i)) & "]"
+      severity Note;
+    end loop;
+    return true;
+  end f_ranges_ok;
+  constant c_ok : boolean := f_ranges_ok;
+
+  -- Crossbar connection matrix
+  type matrix is array (g_num_masters-1 downto 0, g_num_slaves downto 0) of std_logic;
+  
+  -- Add an 'error' device to the list of slaves
+  signal master_ie : t_wishbone_master_in_array(g_num_slaves downto 0);
+  signal master_oe : t_wishbone_master_out_array(g_num_slaves downto 0);
+  signal virtual_ERR : std_logic;
+  
+  signal matrix_old : matrix; -- Registered connection matrix
+  signal matrix_new : matrix; -- The new values of the matrix
+
+  -- Either matrix_old or matrix_new, depending on g_registered
+  signal granted : matrix;
+  
+  -- 1 => 0    2 => 1    3..4 => 2     5..8 => 3
+  function log2(i : natural) return natural is
+  begin
+    if i <= 1
+    then return 0;
+    else return log2((i+1)/2) + 1;
+    end if;
+  end log2;
+  
+  -- 0 => 1    1 => 2      2 => 4      3 => 8
+  function pow2(i : natural) return natural is
+  begin
+    if i = 0
+    then return 1;
+    else return pow2(i-1)*2;
+    end if;
+  end pow2;
+  
+  -- If any of the bits are '1', the whole thing is '1'
+  -- This function makes the check explicitly have logarithmic depth.
+  function vector_OR(x : std_logic_vector)
+    return std_logic 
+  is
+    constant len : integer := x'length;
+    constant mid : integer := len / 2;
+    alias y : std_logic_vector(len-1 downto 0) is x;
+  begin
+    if len = 1 
+    then return y(0);
+    else return vector_OR(y(len-1 downto mid)) or
+                vector_OR(y(mid-1 downto 0));
+    end if;
+  end vector_OR;
+  
+  -- Kogge-Stone network of ORs.
+  -- A log(n) deep, n-wide circuit where:
+  --   output(i) = OR_{j<=i} input(j)
+  function ks_OR(input : std_logic_vector)
+    return std_logic_vector
+  is
+    constant width  : natural := input'length;
+    constant stages : natural := log2(width);
+    variable prev   : std_logic_vector(width-1 downto 0);
+    variable output : std_logic_vector(width-1 downto 0);
+  begin
+    prev := input;
+    if stages = 0 then
+      output := prev;
+    else
+      for l in 0 to stages-1 loop
+        for i in 0 to width-1 loop
+          if i >= pow2(l)
+          then output(i) := prev(i) or prev(i-pow2(l));
+          else output(i) := prev(i);
+          end if;
+        end loop;
+        prev := output;
+      end loop;
+    end if;
+    return output;
+  end ks_OR;
+  
+  -- Impure because it accesses c_{address, mask}
+  function matrix_logic(
+    matrix_old : matrix;
+    slave_i    : t_wishbone_slave_in_array(g_num_masters-1 downto 0))
+    return matrix
+  is
+    subtype row    is std_logic_vector(g_num_masters-1 downto 0);
+    subtype column is std_logic_vector(g_num_slaves    downto 0);
+    
+    variable tmp        : std_logic;
+    variable tmp_column : column;
+    variable tmp_row    : row;
+    
+    variable request    : matrix;  -- Which slaves do the masters address log(S) 
+    variable selected   : matrix;  -- Which master wins arbitration  log(M) request
+    variable sbusy      : column;  -- Does the slave's  previous connection persist?
+    variable mbusy      : row;     -- Does the master's previous connection persist?
+    variable matrix_new : matrix;
+  begin
+    -- A slave is busy iff it services an in-progress cycle
+    for slave in g_num_slaves downto 0 loop
+      for master in g_num_masters-1 downto 0 loop
+        tmp_row(master) := matrix_old(master, slave) and slave_i(master).CYC;
+      end loop;
+      sbusy(slave) := vector_OR(tmp_row);
+    end loop;
+    
+    -- A master is busy iff it services an in-progress cycle
+    for master in g_num_masters-1 downto 0 loop
+      for slave in g_num_slaves downto 0 loop
+        tmp_column(slave) := matrix_old(master, slave);
+      end loop;
+      mbusy(master) := vector_OR(tmp_column) and slave_i(master).CYC;
+    end loop;
+
+    -- Decode the request address to see if master wants access
+    for master in g_num_masters-1 downto 0 loop
+      for slave in g_num_slaves-1 downto 0 loop
+        tmp := not vector_OR((slave_i(master).ADR and c_mask(slave)) xor c_address(slave));
+        tmp_column(slave) := tmp;
+        request(master, slave) := slave_i(master).CYC and slave_i(master).STB and tmp;
+      end loop;
+      tmp_column(g_num_slaves) := '0';
+      -- If no slaves match request, bind to 'error device'
+      request(master, g_num_slaves) := slave_i(master).CYC and slave_i(master).STB and not vector_OR(tmp_column);
+    end loop;
+
+    -- Arbitrate among the requesting masters
+    -- Policy: lowest numbered master first
+    for slave in g_num_slaves downto 0 loop
+      -- OR together all the requests by higher priority masters
+      for master in 0 to g_num_masters-1 loop
+        tmp_row(master) := request(master, slave);
+      end loop;
+      tmp_row := ks_OR(tmp_row);
+      
+      -- Grant to highest priority master
+      selected(0, slave) := request(0, slave); -- master 0 always wins
+      if g_num_masters > 1 then
+        for master in 1 to g_num_masters-1 loop
+          selected(master, slave) := -- only if requested and no lower requests
+            not tmp_row(master-1) and request(master, slave);
+        end loop;
+      end if;
+    end loop;
+
+    -- Determine the master granted access
+    -- Policy: if cycle still in progress, preserve the previous choice
+    for slave in g_num_slaves downto 0 loop
+      for master in g_num_masters-1 downto 0 loop
+        if sbusy(slave) = '1' or mbusy(master) = '1' then
+          matrix_new(master, slave) := matrix_old(master, slave);
+        else
+          matrix_new(master, slave) := selected(master, slave);
+        end if;
+      end loop;
+    end loop;
+    
+    return matrix_new;
+  end matrix_logic;
+
+  subtype slave_row is std_logic_vector(g_num_masters-1 downto 0);
+  type slave_matrix is array (natural range <>) of slave_row;
+  
+  function slave_matrix_OR(x : slave_matrix)
+    return std_logic_vector is
+    variable result : std_logic_vector(x'LENGTH-1 downto 0);
+  begin
+    for i in x'LENGTH-1 downto 0 loop
+      result(i) := vector_OR(x(i));
+    end loop;
+    return result;
+  end slave_matrix_OR;
+  
+  -- Select the master pins the slave will receive
+  function slave_logic(slave   : integer;
+                       granted : matrix;
+                       slave_i : t_wishbone_slave_in_array(g_num_masters-1 downto 0))
+    return t_wishbone_master_out
+  is
+    variable CYC_row    : slave_row;
+    variable STB_row    : slave_row;
+    variable ADR_matrix : slave_matrix(c_wishbone_address_width-1 downto 0);
+    variable SEL_matrix : slave_matrix((c_wishbone_address_width/8)-1 downto 0);
+    variable WE_row     : slave_row;
+    variable DAT_matrix : slave_matrix(c_wishbone_data_width-1 downto 0);
+  begin
+    -- Rename all the signals ready for big_or
+    for master in g_num_masters-1 downto 0 loop
+      CYC_row(master) := slave_i(master).CYC and granted(master, slave);
+      STB_row(master) := slave_i(master).STB and granted(master, slave);
+      for bit in c_wishbone_address_width-1 downto 0 loop
+        ADR_matrix(bit)(master) := slave_i(master).ADR(bit) and granted(master, slave);
+      end loop;
+      for bit in (c_wishbone_address_width/8)-1 downto 0 loop
+        SEL_matrix(bit)(master) := slave_i(master).SEL(bit) and granted(master, slave);
+      end loop;
+      WE_row(master) := slave_i(master).WE and granted(master, slave);
+      for bit in c_wishbone_data_width-1 downto 0 loop
+        DAT_matrix(bit)(master) := slave_i(master).DAT(bit) and granted(master, slave);
+      end loop;
+    end loop;
+    
+    return (
+       CYC => vector_OR(CYC_row),
+       STB => vector_OR(STB_row),
+       ADR => slave_matrix_OR(ADR_matrix),
+       SEL => slave_matrix_OR(SEL_matrix),
+       WE  => vector_OR(WE_row),
+       DAT => slave_matrix_OR(DAT_matrix));
+  end slave_logic;
+
+  subtype master_row is std_logic_vector(g_num_slaves downto 0);
+  type master_matrix is array (natural range <>) of master_row;
+  
+  function master_matrix_OR(x : master_matrix)
+    return std_logic_vector is
+    variable result : std_logic_vector(x'LENGTH-1 downto 0);
+  begin
+    for i in x'LENGTH-1 downto 0 loop
+      result(i) := vector_OR(x(i));
+    end loop;
+    return result;
+  end master_matrix_OR;
+  
+  -- Select the slave pins the master will receive
+  function master_logic(master    : integer;
+                        granted   : matrix;
+                        master_ie : t_wishbone_master_in_array(g_num_slaves downto 0))
+    return t_wishbone_slave_out
+  is
+    variable ACK_row    : master_row;
+    variable ERR_row    : master_row;
+    variable RTY_row    : master_row;
+    variable STALL_row  : master_row;
+    variable DAT_matrix : master_matrix(c_wishbone_data_width-1 downto 0);
+  begin
+    -- We use inverted logic on STALL so that if no slave granted => stall
+    for slave in g_num_slaves downto 0 loop
+      ACK_row(slave) := master_ie(slave).ACK and granted(master, slave);
+      ERR_row(slave) := master_ie(slave).ERR and granted(master, slave);
+      RTY_row(slave) := master_ie(slave).RTY and granted(master, slave);
+      STALL_row(slave) := not master_ie(slave).STALL and granted(master, slave);
+      for bit in c_wishbone_data_width-1 downto 0 loop
+        DAT_matrix(bit)(slave) := master_ie(slave).DAT(bit) and granted(master, slave);
+      end loop;
+    end loop;
+    
+    return (
+      ACK => vector_OR(ACK_row),
+      ERR => vector_OR(ERR_row),
+      RTY => vector_OR(RTY_row),
+      STALL => not vector_OR(STALL_row),
+      DAT => master_matrix_OR(DAT_matrix),
+      INT => '0');
+  end master_logic;
+begin
+  -- The virtual error slave is pretty straight-forward:
+  master_o <= master_oe(g_num_slaves-1 downto 0);
+  master_ie(g_num_slaves-1 downto 0) <= master_i;
+  
+  master_ie(g_num_slaves) <= (
+    ACK   => '0', 
+    ERR   => virtual_ERR,
+    RTY   => '0', 
+    STALL => '0',
+    DAT   => (others => '0'),
+    INT   => '0');
+  virtual_error_slave : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      virtual_ERR <= master_oe(g_num_slaves).CYC and master_oe(g_num_slaves).STB;
+    end if;
+  end process virtual_error_slave;
+  
+  -- Copy the matrix to a register:
+  matrix_new <= matrix_logic(matrix_old, slave_i);
+  main : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        matrix_old <= (others => (others => '0'));
+      else
+        matrix_old <= matrix_new;
+      end if;
+    end if;
+  end process main;
+  
+  -- Is the crossbar combinatorial or registered
+  granted <= matrix_old when g_registered else matrix_new;
+
+  -- Make the slave connections
+  slave_matrixs : for slave in g_num_slaves downto 0 generate
+    master_oe(slave) <= slave_logic(slave, granted, slave_i);
+  end generate;
+
+  -- Make the master connections
+  master_matrixs : for master in g_num_masters-1 downto 0 generate
+    slave_o(master) <= master_logic(master, granted, master_ie);
+  end generate;
+  
+  -- Tell SDB which master is accessing it (SDB is last slave)
+  sdb_masters : for master in g_num_masters-1 downto 0 generate
+    sdb_sel_o(master) <= granted(master, g_num_slaves-1);
+  end generate;
+
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd
new file mode 100644
index 000000000..010fe078a
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd
@@ -0,0 +1,232 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.wishbone_pkg.all;
+
+entity xwb_sdb_crossbar is
+  generic(
+    g_num_masters : natural := 1;
+    g_num_slaves  : natural := 1;
+    g_registered  : boolean := false;
+    g_wraparound  : boolean := true;
+    g_layout      : t_sdb_record_array;
+    g_sdb_addr    : t_wishbone_address;
+    g_sdb_name    : string := "WB4-Crossbar-GSI   ");
+  port(
+    clk_sys_i     : in  std_logic;
+    rst_n_i       : in  std_logic;
+    -- Master connections (INTERCON is a slave)
+    slave_i       : in  t_wishbone_slave_in_array  (g_num_masters-1 downto 0);
+    slave_o       : out t_wishbone_slave_out_array (g_num_masters-1 downto 0);
+    msi_master_i  : in  t_wishbone_master_in_array (g_num_masters-1 downto 0) := (others => cc_dummy_master_in);
+    msi_master_o  : out t_wishbone_master_out_array(g_num_masters-1 downto 0);
+    -- Slave connections (INTERCON is a master)
+    master_i      : in  t_wishbone_master_in_array (g_num_slaves -1 downto 0);
+    master_o      : out t_wishbone_master_out_array(g_num_slaves -1 downto 0);
+    msi_slave_i   : in  t_wishbone_slave_in_array  (g_num_slaves -1 downto 0) := (others => cc_dummy_slave_in);
+    msi_slave_o   : out t_wishbone_slave_out_array (g_num_slaves -1 downto 0));
+end xwb_sdb_crossbar;
+
+architecture rtl of xwb_sdb_crossbar is
+  alias c_layout : t_sdb_record_array(g_layout'length-1 downto 0) is g_layout;
+  
+  -- Pretty print device name
+  function f_trim(s : string) return string is
+    variable cut : natural;
+  begin
+    byte : for i in s'length downto 1 loop
+      cut := i;
+      exit byte when s(i) /= ' ';
+    end loop;
+    return s(1 to cut);
+  end f_trim;
+
+  -- Step 1. Place the SDB ROM on the bus
+  -- How much space does the ROM need?
+  constant c_used_entries   : natural := c_layout'length + 1;
+  constant c_rom_entries    : natural := 2**f_ceil_log2(c_used_entries); -- next power of 2
+  constant c_sdb_bytes      : natural := c_sdb_device_length / 8;
+  constant c_rom_bytes      : natural := c_rom_entries * c_sdb_bytes;
+  
+  constant c_bus_last : unsigned := f_sdb_bus_end(g_wraparound, g_layout, g_sdb_addr, false);
+  constant c_msi_last : unsigned := f_sdb_bus_end(g_wraparound, g_layout, g_sdb_addr, true);
+
+  type t_addresses is record
+    bus_address : t_wishbone_address_array(g_num_slaves -1 downto 0);
+    bus_mask    : t_wishbone_address_array(g_num_slaves -1 downto 0);
+    msi_address : t_wishbone_address_array(g_num_masters-1 downto 0);
+    msi_mask    : t_wishbone_address_array(g_num_masters-1 downto 0);
+  end record t_addresses;
+
+  -- Step 3. Map device address begin values
+  function f_addresses return t_addresses is
+    variable result : t_addresses;
+    
+    variable typ     : std_logic_vector(7 downto 0);
+    variable sdb_component : t_sdb_component;
+    
+    variable address : t_wishbone_address;
+    variable extend  : std_logic_vector(63 downto 0) := (others => '0');
+    variable size    : unsigned(63 downto 0);
+    
+    variable bus_index : natural := 0;
+    variable msi_index : natural := 0;
+  begin
+    for i in c_layout'low to c_layout'high loop
+      typ := c_layout(i)(7 downto 0);
+      sdb_component := f_sdb_extract_component(c_layout(i)(447 downto 8));
+
+      if (typ(7) = '0') then --only do address checks on non-meta record types (typ >= 0x80)
+        -- Range must be valid
+        assert unsigned(sdb_component.addr_first) <= unsigned(sdb_component.addr_last)
+        report "Wishbone slave device #" & Integer'image(i) & " (" & f_trim(sdb_component.product.name) & ") sdb_component.addr_first (" & f_bits2string(sdb_component.addr_first) & ") must precede sdb_component.addr_last address (" & f_bits2string(sdb_component.addr_last) & ")."
+        severity Failure;
+
+        -- Address must fit within Wishbone address width
+        address := sdb_component.addr_first(address'range);
+        extend(address'range) := address;
+        assert sdb_component.addr_first = extend
+        report "Wishbone slave device #" & Integer'image(i) & " (" & f_trim(sdb_component.product.name) & ") sdb_component.addr_first (" & f_bits2string(sdb_component.addr_first) & " does not fit in t_wishbone_address."
+        severity Failure;
+        
+        size := unsigned(sdb_component.addr_last) - unsigned(sdb_component.addr_first);
+        -- size must be of the form 000000...00001111...1
+        assert (size and (size + 1)) = 0
+        report "Wishbone slave device #" & Integer'image(i) & " (" & f_trim(sdb_component.product.name) & ") has an address range that is not a power of 2 minus one (" & f_bits2string(std_logic_vector(size)) & "). This is not supported by the crossbar."
+        severity Warning;
+        
+        -- fix the size up to the form 000...0001111...11
+        for j in c_wishbone_address_width-2 downto 0 loop
+          size(j) := size(j) or size(j+1);
+        end loop;
+        
+        -- the base address must be aligned to the size
+        assert (unsigned(sdb_component.addr_first) and size) = 0
+        report "Wishbone slave device #" & Integer'image(i) & " (" & f_trim(sdb_component.product.name) & ") sdb_component.addr_first (" & f_bits2string(sdb_component.addr_first) & ") is not aligned. This is not supported by the crossbar."
+        severity Failure;
+
+      end if;
+
+      -- Record the address for posterity
+      case typ is
+        when x"01" | x"02" =>
+          assert bus_index < g_num_slaves
+          report "Too many device and bridge records found in g_layout"
+          severity Failure;
+          
+          size := c_bus_last - size;
+          result.bus_address(bus_index) := address;
+          result.bus_mask   (bus_index) := std_logic_vector(size(address'range));
+          bus_index := bus_index + 1;
+          
+        when x"03" =>
+          assert msi_index < g_num_masters
+          report "Too many msi records found in g_layout"
+          severity Failure;
+          
+          size := c_msi_last - size;
+          result.msi_address(msi_index) := address;
+          result.msi_mask   (msi_index) := std_logic_vector(size(address'range));
+          msi_index := msi_index + 1;
+
+        when x"f1" | x"f2" =>
+          result.bus_address(bus_index) := (others => '1');
+          result.bus_mask   (bus_index) := (others => '0');
+          bus_index := bus_index + 1;
+
+        when x"f3" =>
+          result.msi_address(msi_index) := (others => '1');
+          result.msi_mask   (msi_index) := (others => '0');
+          msi_index := msi_index + 1;
+        
+        when others => null;
+      end case;
+    end loop;
+    
+    -- There must be exactly the right number of slave SDB records
+    assert bus_index = g_num_slaves
+    report "Too few device and bridge records found in g_layout. Did you accidentally include meta records in the supplied number of slaves?"
+    severity Failure;
+    
+    -- It is OK to have no master records (backwards compat)
+    if msi_index = 0 then
+      result.msi_address := (others => (others => '1'));
+      result.msi_mask    := (others => (others => '0'));
+    else
+      assert msi_index = g_num_masters
+      report "Too few msi records found in g_layout"
+      severity Failure;
+    end if;
+    
+    return result;
+  end f_addresses;
+  
+  constant c_addresses : t_addresses := f_addresses;
+
+  -- Figure out the mask for the SDB slave
+  constant c_rom_mask : unsigned(63 downto 0) := 
+    c_bus_last - to_unsigned(c_rom_bytes-1, 64);
+  constant c_sdb_mask : t_wishbone_address := 
+    std_logic_vector(c_rom_mask(c_wishbone_address_width-1 downto 0));
+  
+  -- Fill bus crossbar parameters
+  constant c_address : t_wishbone_address_array(g_num_slaves downto 0) :=
+    g_sdb_addr & c_addresses.bus_address;
+  constant c_mask : t_wishbone_address_array(g_num_slaves downto 0) :=
+    c_sdb_mask & c_addresses.bus_mask;
+  
+  signal master_i_1 :  t_wishbone_master_in_array(g_num_slaves downto 0);
+  signal master_o_1 : t_wishbone_master_out_array(g_num_slaves downto 0);
+  signal sdb_sel    : std_logic_vector(g_num_masters-1 downto 0);
+
+begin
+
+  -- Pass-through all slave ports except SDB
+  master_i_1(g_num_slaves-1 downto 0) <=  master_i;
+  master_o <= master_o_1(g_num_slaves-1 downto 0);
+  
+  rom : sdb_rom
+    generic map(
+      g_layout   => c_layout,
+      g_masters  => g_num_masters,
+      g_bus_end  => c_bus_last,
+      g_sdb_name => g_sdb_name)
+    port map(
+      clk_sys_i => clk_sys_i,
+      master_i  => sdb_sel,
+      slave_i   => master_o_1(g_num_slaves),
+      slave_o   => master_i_1(g_num_slaves));
+  
+  crossbar : xwb_crossbar
+    generic map(
+      g_num_masters => g_num_masters,
+      g_num_slaves  => g_num_slaves + 1,
+      g_registered  => g_registered,
+      g_address     => c_address,
+      g_mask        => c_mask)
+    port map(
+      clk_sys_i     => clk_sys_i,
+      rst_n_i       => rst_n_i,
+      slave_i       => slave_i, 
+      slave_o       => slave_o, 
+      master_i      => master_i_1, 
+      master_o      => master_o_1,
+      sdb_sel_o     => sdb_sel);
+
+  msi : xwb_crossbar
+    generic map(
+      g_num_masters => g_num_slaves,
+      g_num_slaves  => g_num_masters,
+      g_registered  => g_registered,
+      g_address     => c_addresses.msi_address,
+      g_mask        => c_addresses.msi_mask)
+    port map(
+      clk_sys_i     => clk_sys_i,
+      rst_n_i       => rst_n_i,
+      slave_i       => msi_slave_i,
+      slave_o       => msi_slave_o,
+      master_i      => msi_master_i,
+      master_o      => msi_master_o,
+      sdb_sel_o     => open);
+
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd
new file mode 100644
index 000000000..71c3f3840
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd
@@ -0,0 +1,185 @@
+-------------------------------------------------------------------------------
+-- Title      : Dual-port RAM for WR core
+-- Project    : WhiteRabbit
+-------------------------------------------------------------------------------
+-- File       : wrc_dpram.vhd
+-- Author     : Grzegorz Daniluk
+-- Company    : CERN
+-- Created    : 2011-02-15
+-- Last update: 2017-02-03
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Description:
+--
+-- Dual port RAM with wishbone interface
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011-2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2011-02-15  1.0      greg.d          Created
+-- 2011-06-09  1.01     twlostow        Removed unnecessary generics
+-- 2011-21-09  1.02     twlostow        Struct-ized version
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+library work;
+use work.genram_pkg.all;
+use work.wishbone_pkg.all;
+
+entity xwb_dpram is
+  generic(
+    g_size                  : natural := 16384;
+    g_init_file             : string  := "";
+    g_must_have_init_file   : boolean := true;
+    g_slave1_interface_mode : t_wishbone_interface_mode;
+    g_slave2_interface_mode : t_wishbone_interface_mode;
+    g_slave1_granularity    : t_wishbone_address_granularity;
+    g_slave2_granularity    : t_wishbone_address_granularity
+    );
+  port(
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    slave1_i : in  t_wishbone_slave_in;
+    slave1_o : out t_wishbone_slave_out;
+    slave2_i : in  t_wishbone_slave_in;
+    slave2_o : out t_wishbone_slave_out
+    );
+end xwb_dpram;
+
+architecture struct of xwb_dpram is
+
+  signal s_wea  : std_logic;
+  signal s_web  : std_logic;
+  signal s_bwea : std_logic_vector(3 downto 0);
+  signal s_bweb : std_logic_vector(3 downto 0);
+
+  signal slave1_in  : t_wishbone_slave_in;
+  signal slave1_out : t_wishbone_slave_out;
+  signal slave2_in  : t_wishbone_slave_in;
+  signal slave2_out : t_wishbone_slave_out;
+  
+begin
+  U_Adapter1 : wb_slave_adapter
+    generic map (
+      g_master_use_struct  => true,
+      g_master_mode        => g_slave1_interface_mode,
+      g_master_granularity => WORD,
+      g_slave_use_struct   => true,
+      g_slave_mode         => g_slave1_interface_mode,
+      g_slave_granularity  => g_slave1_granularity)
+    port map (
+      clk_sys_i => clk_sys_i,
+      rst_n_i   => rst_n_i,
+      slave_i   => slave1_i,
+      slave_o   => slave1_o,
+      master_i  => slave1_out,
+      master_o  => slave1_in);
+
+  U_Adapter2 : wb_slave_adapter
+    generic map (
+      g_master_use_struct  => true,
+      g_master_mode        => g_slave2_interface_mode,
+      g_master_granularity => WORD,
+      g_slave_use_struct   => true,
+      g_slave_mode         => g_slave2_interface_mode,
+      g_slave_granularity  => g_slave2_granularity)
+    port map (
+      clk_sys_i => clk_sys_i,
+      rst_n_i   => rst_n_i,
+      slave_i   => slave2_i,
+      slave_o   => slave2_o,
+      master_i  => slave2_out,
+      master_o  => slave2_in);
+
+    U_DPRAM : generic_dpram
+      generic map(
+        -- standard parameters
+        g_data_width               => 32,
+        g_size                     => g_size,
+        g_with_byte_enable         => true,
+        g_addr_conflict_resolution => "dont_care",
+        g_init_file                => g_init_file,
+        g_dual_clock               => false
+        )
+      port map(
+        rst_n_i => rst_n_i,
+        -- Port A
+        clka_i  => clk_sys_i,
+        bwea_i  => s_bwea,
+        wea_i   => s_wea,
+        aa_i    => slave1_in.adr(f_log2_size(g_size)-1 downto 0),
+        da_i    => slave1_in.dat,
+        qa_o    => slave1_out.dat,
+        -- Port B
+        clkb_i  => clk_sys_i,
+        bweb_i  => s_bweb,
+        web_i   => s_web,
+        ab_i    => slave2_in.adr(f_log2_size(g_size)-1 downto 0),
+        db_i    => slave2_in.dat,
+        qb_o    => slave2_out.dat
+        );
+
+  -- I know this looks weird, but otherwise ISE generates distributed RAM instead of block
+  -- RAM
+  s_bwea <= slave1_in.sel when s_wea = '1' else f_zeros(c_wishbone_data_width/8);
+  s_bweb <= slave2_in.sel when s_web = '1' else f_zeros(c_wishbone_data_width/8);
+
+  s_wea <= slave1_in.we and slave1_in.stb and slave1_in.cyc;
+  s_web <= slave2_in.we and slave2_in.stb and slave2_in.cyc;
+
+  process(clk_sys_i)
+  begin
+    if(rising_edge(clk_sys_i)) then
+      if(rst_n_i = '0') then
+        slave1_out.ack <= '0';
+        slave2_out.ack <= '0';
+      else
+        if(slave1_out.ack = '1' and g_slave1_interface_mode = CLASSIC) then
+          slave1_out.ack <= '0';
+        else
+          slave1_out.ack <= slave1_in.cyc and slave1_in.stb;
+        end if;
+
+        if(slave2_out.ack = '1' and g_slave2_interface_mode = CLASSIC) then
+          slave2_out.ack <= '0';
+        else
+          slave2_out.ack <= slave2_in.cyc and slave2_in.stb;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  slave1_out.stall <= '0';
+  slave2_out.stall <= '0';
+  slave1_out.err   <= '0';
+  slave2_out.err   <= '0';
+  slave1_out.rty   <= '0';
+  slave2_out.rty   <= '0';
+  slave1_out.int   <= '0';
+  slave2_out.int   <= '0';
+  
+end struct;
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v
new file mode 100644
index 000000000..af57302c2
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v
@@ -0,0 +1,102181 @@
+
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+
+
+module lm32_top_full (
+    
+    clk_i,
+    rst_i,
+    
+
+    interrupt,
+
+    
+  
+    
+    
+
+     
+  
+
+    
+    I_DAT_I,
+    I_ACK_I,
+    I_ERR_I,
+    I_RTY_I,
+ 
+
+    
+    D_DAT_I,
+    D_ACK_I,
+    D_ERR_I,
+    D_RTY_I,
+    
+      
+    
+    
+    
+    
+
+    
+  
+
+    
+    I_DAT_O,
+    I_ADR_O,
+    I_CYC_O,
+    I_SEL_O,
+    I_STB_O,
+    I_WE_O,
+    I_CTI_O,
+    I_LOCK_O,
+    I_BTE_O,
+ 
+
+    
+    D_DAT_O,
+    D_ADR_O,
+    D_CYC_O,
+    D_SEL_O,
+    D_STB_O,
+    D_WE_O,
+    D_CTI_O,
+    D_LOCK_O,
+    D_BTE_O
+    );
+
+parameter eba_reset = 32'h00000000;
+parameter sdb_address = 32'h00000000;
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+
+
+input [ (32-1):0] interrupt;          
+
+
+  
+               
+                             
+
+    
+
+  
+
+input [ (32-1):0] I_DAT_I;                 
+input I_ACK_I;                                  
+input I_ERR_I;                                  
+input I_RTY_I;                                  
+ 
+
+
+input [ (32-1):0] D_DAT_I;                 
+input D_ACK_I;                                  
+input D_ERR_I;                                  
+input D_RTY_I;                                  
+
+
+
+
+
+  
+                               
+   
+       
+     
+           
+    
+           
+    
+
+
+
+  
+
+output [ (32-1):0] I_DAT_O;                
+wire   [ (32-1):0] I_DAT_O;
+output [ (32-1):0] I_ADR_O;                
+wire   [ (32-1):0] I_ADR_O;
+output I_CYC_O;                                 
+wire   I_CYC_O;
+output [ (4-1):0] I_SEL_O;         
+wire   [ (4-1):0] I_SEL_O;
+output I_STB_O;                                 
+wire   I_STB_O;
+output I_WE_O;                                  
+wire   I_WE_O;
+output [ (3-1):0] I_CTI_O;               
+wire   [ (3-1):0] I_CTI_O;
+output I_LOCK_O;                                
+wire   I_LOCK_O;
+output [ (2-1):0] I_BTE_O;               
+wire   [ (2-1):0] I_BTE_O;
+ 
+
+
+output [ (32-1):0] D_DAT_O;                
+wire   [ (32-1):0] D_DAT_O;
+output [ (32-1):0] D_ADR_O;                
+wire   [ (32-1):0] D_ADR_O;
+output D_CYC_O;                                 
+wire   D_CYC_O;
+output [ (4-1):0] D_SEL_O;         
+wire   [ (4-1):0] D_SEL_O;
+output D_STB_O;                                 
+wire   D_STB_O;
+output D_WE_O;                                  
+wire   D_WE_O;
+output [ (3-1):0] D_CTI_O;               
+wire   [ (3-1):0] D_CTI_O;
+output D_LOCK_O;                                
+wire   D_LOCK_O;
+output [ (2-1):0] D_BTE_O;               
+wire   [ (2-1):0] D_BTE_O;
+  
+
+
+
+ 
+  
+
+  
+  
+ 
+  
+  
+ 
+ 
+
+
+
+
+  
+
+                     
+                             
+                            
+                   
+                                 
+ 
+                                 
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+   
+
+lm32_cpu_full 
+	#(
+		.eba_reset(eba_reset),
+    .sdb_address(sdb_address)
+	) cpu (
+    
+    .clk_i                 (clk_i),
+  
+                   
+
+
+    .rst_i                 (rst_i),
+    
+  
+
+    .interrupt             (interrupt),
+ 
+
+    
+  
+               
+             
+
+     
+  
+    
+                  
+               
+                
+           
+
+
+  
+
+     
+    .I_DAT_I               (I_DAT_I),
+    .I_ACK_I               (I_ACK_I),
+    .I_ERR_I               (I_ERR_I),
+    .I_RTY_I               (I_RTY_I),
+ 
+
+    
+    .D_DAT_I               (D_DAT_I),
+    .D_ACK_I               (D_ACK_I),
+    .D_ERR_I               (D_ERR_I),
+    .D_RTY_I               (D_RTY_I),
+    
+  
+                  
+            
+           
+                 
+                
+ 
+                
+
+
+
+  
+                
+           
+
+
+      
+                
+               
+            
+            
+
+    
+  
+
+    
+    .I_DAT_O               (I_DAT_O),
+    .I_ADR_O               (I_ADR_O),
+    .I_CYC_O               (I_CYC_O),
+    .I_SEL_O               (I_SEL_O),
+    .I_STB_O               (I_STB_O),
+    .I_WE_O                (I_WE_O),
+    .I_CTI_O               (I_CTI_O),
+    .I_LOCK_O              (I_LOCK_O),
+    .I_BTE_O               (I_BTE_O),
+     
+
+    
+    .D_DAT_O               (D_DAT_O),
+    .D_ADR_O               (D_ADR_O),
+    .D_CYC_O               (D_CYC_O),
+    .D_SEL_O               (D_SEL_O),
+    .D_STB_O               (D_STB_O),
+    .D_WE_O                (D_WE_O),
+    .D_CTI_O               (D_CTI_O),
+    .D_LOCK_O              (D_LOCK_O),
+    .D_BTE_O               (D_BTE_O)
+    );
+   
+  		   
+
+  
+    
+                     
+                
+    
+                
+                     
+                
+                      
+                     
+    
+
+        
+   
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
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+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+           
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_mc_arithmetic_full (
+    
+    clk_i,
+    rst_i,
+    stall_d,
+    kill_x,
+  
+
+    divide_d,
+    modulus_d,
+ 
+
+  
+    
+
+
+  
+    
+    
+    
+
+
+    operand_0_d,
+    operand_1_d,
+    
+    result_x,
+  
+
+    divide_by_zero_x,
+ 
+
+    stall_request_x
+    );
+
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+input stall_d;                                  
+input kill_x;                                   
+  
+
+input divide_d;                                 
+input modulus_d;                                
+ 
+
+  
+                                
+
+
+  
+                              
+                             
+                             
+
+
+input [ (32-1):0] operand_0_d;
+input [ (32-1):0] operand_1_d;
+
+
+
+
+
+output [ (32-1):0] result_x;               
+reg    [ (32-1):0] result_x;
+  
+
+output divide_by_zero_x;                        
+reg    divide_by_zero_x;
+ 
+
+output stall_request_x;                         
+wire   stall_request_x;
+
+
+
+
+
+reg [ (32-1):0] p;                         
+reg [ (32-1):0] a;
+reg [ (32-1):0] b;
+  
+
+wire [32:0] t;
+ 
+
+
+reg [ 2:0] state;                 
+reg [5:0] cycles;                               
+
+  
+                               
+                                 
+
+
+
+
+
+
+
+
+assign stall_request_x = state !=  3'b000;
+
+  
+
+
+assign t = {p[ 32-2:0], a[ 32-1]} - b;
+ 
+
+
+  
+
+       
+
+
+
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        cycles <= {6{1'b0}};
+        p <= { 32{1'b0}};
+        a <= { 32{1'b0}};
+        b <= { 32{1'b0}};
+  
+          
+
+
+  
+
+        divide_by_zero_x <=  1'b0;
+ 
+
+        result_x <= { 32{1'b0}};
+        state <=  3'b000;
+    end
+    else
+    begin
+  
+
+        divide_by_zero_x <=  1'b0;
+ 
+
+        case (state)
+         3'b000:
+        begin
+            if (stall_d ==  1'b0)                 
+            begin          
+                cycles <=  32;
+                p <= 32'b0;
+                a <= operand_0_d;
+                b <= operand_1_d;                    
+  
+
+                if (divide_d ==  1'b1)
+                    state <=  3'b011 ;
+                if (modulus_d ==  1'b1)
+                    state <=  3'b010   ;
+ 
+                    
+  
+                   
+                      
+
+
+  
+                   
+                
+                      
+                      
+                      
+                      
+                      
+                
+                   
+                
+                      
+                      
+                      
+                      
+                      
+                
+
+
+            end            
+        end
+  
+
+         3'b011 :
+        begin
+            if (t[32] == 1'b0)
+            begin
+                p <= t[31:0];
+                a <= {a[ 32-2:0], 1'b1};
+            end
+            else 
+            begin
+                p <= {p[ 32-2:0], a[ 32-1]};
+                a <= {a[ 32-2:0], 1'b0};
+            end
+            result_x <= a;
+            if ((cycles ==  32'd0) || (kill_x ==  1'b1))
+            begin
+                
+                divide_by_zero_x <= b == { 32{1'b0}};
+                state <=  3'b000;
+            end
+            cycles <= cycles - 1'b1;
+        end
+         3'b010   :
+        begin
+            if (t[32] == 1'b0)
+            begin
+                p <= t[31:0];
+                a <= {a[ 32-2:0], 1'b1};
+            end
+            else 
+            begin
+                p <= {p[ 32-2:0], a[ 32-1]};
+                a <= {a[ 32-2:0], 1'b0};
+            end
+            result_x <= p;
+            if ((cycles ==  32'd0) || (kill_x ==  1'b1))
+            begin
+                
+                divide_by_zero_x <= b == { 32{1'b0}};
+                state <=  3'b000;
+            end
+            cycles <= cycles - 1'b1;
+        end
+ 
+        
+  
+        
+        
+               
+                    
+               
+               
+              
+                   
+                  
+                
+        
+
+     
+  
+        
+               
+               
+              
+                   
+                  
+                
+        
+        
+               
+               
+              
+                   
+                  
+                
+        
+
+   
+        endcase
+    end
+end 
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_cpu_full (
+    
+    clk_i,
+  
+    
+
+
+    rst_i,
+  
+    
+
+
+  
+   
+   
+   
+   
+   
+   
+
+
+
+    
+  
+
+    interrupt,
+ 
+
+    
+  
+    
+    
+
+     
+  
+    
+    
+     
+    
+    
+
+
+  
+
+    
+    I_DAT_I,
+    I_ACK_I,
+    I_ERR_I,
+    I_RTY_I,
+ 
+
+    
+    D_DAT_I,
+    D_ACK_I,
+    D_ERR_I,
+    D_RTY_I,
+    
+  
+    
+    
+    
+    
+    
+ 
+    
+
+
+
+  
+    
+    
+
+
+      
+    
+    
+    
+    
+
+    
+  
+
+    
+    I_DAT_O,
+    I_ADR_O,
+    I_CYC_O,
+    I_SEL_O,
+    I_STB_O,
+    I_WE_O,
+    I_CTI_O,
+    I_LOCK_O,
+    I_BTE_O,
+ 
+ 
+  
+    
+    
+    
+    
+    
+    
+    
+    
+           
+
+
+		 
+		 
+    
+    D_DAT_O,
+    D_ADR_O,
+    D_CYC_O,
+    D_SEL_O,
+    D_STB_O,
+    D_WE_O,
+    D_CTI_O,
+    D_LOCK_O,
+    D_BTE_O
+
+		 
+    );
+
+
+
+
+
+parameter eba_reset =  32'h00000000;                           
+  
+                            
+
+
+parameter sdb_address =   32'h00000000;
+
+  
+
+parameter icache_associativity =  1;     
+parameter icache_sets =  256;                       
+parameter icache_bytes_per_line =  16;   
+parameter icache_base_address =  32'h0;       
+parameter icache_limit =  32'h7fffffff;                     
+ 
+       
+                         
+     
+         
+                       
+
+
+
+  
+
+parameter dcache_associativity =  1;     
+parameter dcache_sets =  256;                       
+parameter dcache_bytes_per_line =  16;   
+parameter dcache_base_address =  32'h0;       
+parameter dcache_limit =  32'h7fffffff;                     
+ 
+       
+                         
+     
+         
+                       
+
+
+
+  
+                          
+
+
+parameter watchpoints = 0;
+ 
+
+  
+                          
+
+
+parameter breakpoints = 0;
+ 
+
+
+  
+
+parameter interrupts =  32;                         
+ 
+   
+
+
+
+
+
+
+
+input clk_i;                                    
+  
+                                   
+
+    
+input rst_i;                                    
+
+  
+
+input [ (32-1):0] interrupt;          
+ 
+
+
+  
+               
+                             
+
+    
+
+   
+                                  
+                               
+                
+  
+
+
+
+  
+
+input [ (32-1):0] I_DAT_I;                 
+input I_ACK_I;                                  
+input I_ERR_I;                                  
+input I_RTY_I;                                  
+ 
+
+
+input [ (32-1):0] D_DAT_I;                 
+input D_ACK_I;                                  
+input D_ERR_I;                                  
+input D_RTY_I;                                  
+
+
+
+
+
+  
+    
+     
+
+
+   
+   
+  
+                   
+     
+                           
+    
+                          
+    
+                 
+     
+                               
+    
+ 
+                               
+    
+
+
+
+
+  
+  
+    
+  
+    
+
+
+
+  
+                               
+   
+       
+     
+           
+    
+           
+    
+
+
+
+  
+
+output [ (32-1):0] I_DAT_O;                
+wire   [ (32-1):0] I_DAT_O;
+output [ (32-1):0] I_ADR_O;                
+wire   [ (32-1):0] I_ADR_O;
+output I_CYC_O;                                 
+wire   I_CYC_O;
+output [ (4-1):0] I_SEL_O;         
+wire   [ (4-1):0] I_SEL_O;
+output I_STB_O;                                 
+wire   I_STB_O;
+output I_WE_O;                                  
+wire   I_WE_O;
+output [ (3-1):0] I_CTI_O;               
+wire   [ (3-1):0] I_CTI_O;
+output I_LOCK_O;                                
+wire   I_LOCK_O;
+output [ (2-1):0] I_BTE_O;               
+wire   [ (2-1):0] I_BTE_O;
+ 
+
+
+output [ (32-1):0] D_DAT_O;                
+wire   [ (32-1):0] D_DAT_O;
+output [ (32-1):0] D_ADR_O;                
+wire   [ (32-1):0] D_ADR_O;
+output D_CYC_O;                                 
+wire   D_CYC_O;
+output [ (4-1):0] D_SEL_O;         
+wire   [ (4-1):0] D_SEL_O;
+output D_STB_O;                                 
+wire   D_STB_O;
+output D_WE_O;                                  
+wire   D_WE_O;
+output [ (3-1):0] D_CTI_O;               
+wire   [ (3-1):0] D_CTI_O;
+output D_LOCK_O;                                
+wire   D_LOCK_O;
+output [ (2-1):0] D_BTE_O;               
+wire   [ (2-1):0] D_BTE_O;
+
+  
+      
+     
+       
+      
+             
+
+
+   
+
+
+
+
+
+
+  
+
+reg valid_a;                                    
+ 
+
+reg valid_f;                                    
+reg valid_d;                                    
+reg valid_x;                                    
+reg valid_m;                                    
+reg valid_w;                                    
+   
+wire q_x;
+wire [ (32-1):0] immediate_d;              
+wire load_d;                                    
+reg load_x;                                     
+reg load_m;
+wire load_q_x;
+wire store_q_x;
+wire q_m;
+wire load_q_m;
+wire store_q_m;
+wire store_d;                                   
+reg store_x;
+reg store_m;
+wire [ 1:0] size_d;                   
+reg [ 1:0] size_x;
+wire branch_d;                                  
+wire branch_predict_d;                          
+wire branch_predict_taken_d;                    
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d;   
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_d;
+wire bi_unconditional;
+wire bi_conditional;
+reg branch_x;                                   
+reg branch_predict_x;
+reg branch_predict_taken_x;
+reg branch_m;
+reg branch_predict_m;
+reg branch_predict_taken_m;
+wire branch_mispredict_taken_m;                 
+wire branch_flushX_m;                           
+wire branch_reg_d;                              
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset_d;            
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_x;             
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_m;
+wire [ 0:0] d_result_sel_0_d; 
+wire [ 1:0] d_result_sel_1_d; 
+
+wire x_result_sel_csr_d;                        
+reg x_result_sel_csr_x;
+  
+
+wire q_d;
+wire x_result_sel_mc_arith_d;                   
+reg x_result_sel_mc_arith_x;
+ 
+
+      
+                       
+ 
+
+
+  
+
+wire x_result_sel_sext_d;                       
+reg x_result_sel_sext_x;
+ 
+
+wire x_result_sel_logic_d;                      
+  
+                        
+ 
+
+
+wire x_result_sel_add_d;                        
+reg x_result_sel_add_x;
+wire m_result_sel_compare_d;                    
+reg m_result_sel_compare_x;
+reg m_result_sel_compare_m;
+  
+
+wire m_result_sel_shift_d;                      
+reg m_result_sel_shift_x;
+reg m_result_sel_shift_m;
+ 
+
+wire w_result_sel_load_d;                       
+reg w_result_sel_load_x;
+reg w_result_sel_load_m;
+reg w_result_sel_load_w;
+  
+
+wire w_result_sel_mul_d;                        
+reg w_result_sel_mul_x;
+reg w_result_sel_mul_m;
+reg w_result_sel_mul_w;
+ 
+
+wire x_bypass_enable_d;                         
+reg x_bypass_enable_x;                          
+wire m_bypass_enable_d;                         
+reg m_bypass_enable_x;                          
+reg m_bypass_enable_m;
+wire sign_extend_d;                             
+reg sign_extend_x;
+wire write_enable_d;                            
+reg write_enable_x;
+wire write_enable_q_x;
+reg write_enable_m;
+wire write_enable_q_m;
+reg write_enable_w;
+wire write_enable_q_w;
+wire read_enable_0_d;                           
+wire [ (5-1):0] read_idx_0_d;          
+wire read_enable_1_d;                           
+wire [ (5-1):0] read_idx_1_d;          
+wire [ (5-1):0] write_idx_d;           
+reg [ (5-1):0] write_idx_x;            
+reg [ (5-1):0] write_idx_m;
+reg [ (5-1):0] write_idx_w;
+wire [ (4 -1):0] csr_d;                     
+reg  [ (4 -1):0] csr_x;                  
+wire [ (3-1):0] condition_d;         
+reg [ (3-1):0] condition_x;          
+  
+                                    
+                                     
+
+
+wire scall_d;                                   
+reg scall_x;    
+wire eret_d;                                    
+reg eret_x;
+wire eret_q_x;
+  
+ 
+ 
+
+
+  
+                                     
+ 
+ 
+ 
+ 
+ 
+
+
+
+wire csr_write_enable_d;                        
+reg csr_write_enable_x;
+wire csr_write_enable_q_x;
+  
+       
+
+
+
+  
+
+wire bus_error_d;                               
+reg bus_error_x;
+reg data_bus_error_exception_m;
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] memop_pc_w;
+ 
+
+
+reg [ (32-1):0] d_result_0;                
+reg [ (32-1):0] d_result_1;                
+reg [ (32-1):0] x_result;                  
+reg [ (32-1):0] m_result;                  
+reg [ (32-1):0] w_result;                  
+
+reg [ (32-1):0] operand_0_x;               
+reg [ (32-1):0] operand_1_x;               
+reg [ (32-1):0] store_operand_x;           
+reg [ (32-1):0] operand_m;                 
+reg [ (32-1):0] operand_w;                 
+
+
+  
+
+reg [ (32-1):0] reg_data_live_0;          
+reg [ (32-1):0] reg_data_live_1;  
+reg use_buf;                                    
+reg [ (32-1):0] reg_data_buf_0;
+reg [ (32-1):0] reg_data_buf_1;
+ 
+
+  
+
+ 
+     
+
+
+wire [ (32-1):0] reg_data_0;               
+wire [ (32-1):0] reg_data_1;               
+reg [ (32-1):0] bypass_data_0;             
+reg [ (32-1):0] bypass_data_1;             
+wire reg_write_enable_q_w;
+
+reg interlock;                                  
+
+wire stall_a;                                   
+wire stall_f;                                   
+wire stall_d;                                   
+wire stall_x;                                   
+wire stall_m;                                   
+
+
+wire adder_op_d;                                
+reg adder_op_x;                                 
+reg adder_op_x_n;                               
+wire [ (32-1):0] adder_result_x;           
+wire adder_overflow_x;                          
+wire adder_carry_n_x;                           
+
+
+wire [ 3:0] logic_op_d;           
+reg [ 3:0] logic_op_x;            
+wire [ (32-1):0] logic_result_x;           
+
+  
+
+
+wire [ (32-1):0] sextb_result_x;           
+wire [ (32-1):0] sexth_result_x;           
+wire [ (32-1):0] sext_result_x;            
+ 
+
+
+
+  
+
+  
+                                   
+                                     
+
+
+wire direction_d;                               
+reg direction_x;                                        
+wire [ (32-1):0] shifter_result_m;         
+ 
+
+  
+                               
+ 
+                              
+ 
+
+
+  
+           
+
+
+
+
+  
+
+wire [ (32-1):0] multiplier_result_w;      
+ 
+
+  
+                                 
+ 
+
+
+
+
+  
+
+wire divide_d;                                  
+wire divide_q_d;
+wire modulus_d;
+wire modulus_q_d;
+wire divide_by_zero_x;                          
+ 
+
+
+
+  
+
+wire mc_stall_request_x;                        
+wire [ (32-1):0] mc_result_x;
+ 
+
+
+
+  
+
+wire [ (32-1):0] interrupt_csr_read_data_x;
+ 
+
+wire [ (32-1):0] cfg;                      
+wire [ (32-1):0] cfg2;                     
+  
+                          
+
+
+reg [ (32-1):0] csr_read_data_x;           
+
+
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;                       
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;                       
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;                       
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;                       
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;                       
+  
+                          
+
+
+  
+
+wire [ (32-1):0] instruction_f;     
+ 
+
+
+
+wire [ (32-1):0] instruction_d;     
+  
+
+wire iflush;                                    
+wire icache_stall_request;                      
+wire icache_restart_request;                    
+wire icache_refill_request;                     
+wire icache_refilling;                          
+ 
+
+
+
+  
+
+wire dflush_x;                                  
+reg dflush_m;                                    
+wire dcache_stall_request;                      
+wire dcache_restart_request;                    
+wire dcache_refill_request;                     
+wire dcache_refilling;                          
+ 
+
+wire [ (32-1):0] load_data_w;              
+wire stall_wb_load;                             
+
+
+  
+ 
+          
+          
+
+ 
+                      
+        
+                    
+                           
+  
+ 
+  
+  
+ 
+
+ 
+                                 
+
+
+
+
+
+wire raw_x_0;                                   
+wire raw_x_1;                                   
+wire raw_m_0;                                   
+wire raw_m_1;                                   
+wire raw_w_0;                                   
+wire raw_w_1;                                   
+
+
+wire cmp_zero;                                  
+wire cmp_negative;                              
+wire cmp_overflow;                              
+wire cmp_carry_n;                               
+reg condition_met_x;                            
+reg condition_met_m;
+  
+    
+wire branch_taken_x;                            
+ 
+
+wire branch_taken_m;                            
+
+wire kill_f;                                    
+wire kill_d;                                    
+wire kill_x;                                    
+wire kill_m;                                    
+wire kill_w;                                    
+
+reg [ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8] eba;                 
+  
+                  
+
+
+reg [ (3-1):0] eid_x;                      
+  
+                        
+                        
+
+
+
+  
+ 
+                                      
+
+                                      
+ 
+ 
+                                
+                                 
+                          
+ 
+ 
+ 
+                      
+ 
+ 
+ 
+
+
+wire exception_x;                               
+reg exception_m;
+reg exception_w;
+wire exception_q_w;
+ 
+
+
+  
+  
+                            
+
+ 
+                            
+
+
+
+  
+
+wire interrupt_exception;                       
+ 
+
+  
+                       
+                       
+
+
+  
+
+   reg [ (32-1):0] data_bus_error_addr;
+   
+wire instruction_bus_error_exception;           
+wire data_bus_error_exception;                  
+ 
+
+  
+
+wire divide_by_zero_exception;                  
+ 
+
+wire system_call_exception;                     
+
+  
+
+reg data_bus_error_seen;                        
+ 
+
+
+   
+    
+
+
+     
+  
+                          
+   
+            
+   
+                          
+   
+
+    	      
+    	      
+    	      
+    	      
+    	      
+    	      
+   
+   
+
+
+   
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+lm32_instruction_unit_full #(
+    .eba_reset              (eba_reset),
+    .associativity          (icache_associativity),
+    .sets                   (icache_sets),
+    .bytes_per_line         (icache_bytes_per_line),
+    .base_address           (icache_base_address),
+    .limit                  (icache_limit)
+  ) instruction_unit (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    
+    .stall_a                (stall_a),
+    .stall_f                (stall_f),
+    .stall_d                (stall_d),
+    .stall_x                (stall_x),
+    .stall_m                (stall_m),
+    .valid_f                (valid_f),
+    .valid_d                (valid_d),
+    .kill_f                 (kill_f),
+    .branch_predict_taken_d (branch_predict_taken_d),
+    .branch_predict_address_d (branch_predict_address_d),
+  
+    
+    .branch_taken_x         (branch_taken_x),
+    .branch_target_x        (branch_target_x),
+ 
+
+    .exception_m            (exception_m),
+    .branch_taken_m         (branch_taken_m),
+    .branch_mispredict_taken_m (branch_mispredict_taken_m),
+    .branch_target_m        (branch_target_m),
+  
+
+    .iflush                 (iflush),
+ 
+
+  
+
+    .dcache_restart_request (dcache_restart_request),
+    .dcache_refill_request  (dcache_refill_request),
+    .dcache_refilling       (dcache_refilling),
+ 
+        
+  
+
+    
+    .i_dat_i                (I_DAT_I),
+    .i_ack_i                (I_ACK_I),
+    .i_err_i                (I_ERR_I),
+    .i_rty_i                (I_RTY_I),
+ 
+
+  
+           
+          
+            
+               
+
+
+    
+    
+    .pc_f                   (pc_f),
+    .pc_d                   (pc_d),
+    .pc_x                   (pc_x),
+    .pc_m                   (pc_m),
+    .pc_w                   (pc_w),
+  
+
+    .icache_stall_request   (icache_stall_request),
+    .icache_restart_request (icache_restart_request),
+    .icache_refill_request  (icache_refill_request),
+    .icache_refilling       (icache_refilling),
+ 
+
+  
+
+    
+    .i_dat_o                (I_DAT_O),
+    .i_adr_o                (I_ADR_O),
+    .i_cyc_o                (I_CYC_O),
+    .i_sel_o                (I_SEL_O),
+    .i_stb_o                (I_STB_O),
+    .i_we_o                 (I_WE_O),
+    .i_cti_o                (I_CTI_O),
+    .i_lock_o               (I_LOCK_O),
+    .i_bte_o                (I_BTE_O),
+ 
+ 
+
+  
+    
+    
+    
+
+
+		      	      
+  
+             
+       
+
+
+  
+
+    .bus_error_d            (bus_error_d),
+ 
+
+  
+
+    .instruction_f          (instruction_f),
+ 
+
+
+		      
+    .instruction_d          (instruction_d)
+
+
+		      
+    );
+
+
+lm32_decoder_full decoder (
+    
+    .instruction            (instruction_d),
+    
+    .d_result_sel_0         (d_result_sel_0_d),
+    .d_result_sel_1         (d_result_sel_1_d),
+    .x_result_sel_csr       (x_result_sel_csr_d),
+  
+
+    .x_result_sel_mc_arith  (x_result_sel_mc_arith_d),
+ 
+
+      
+         
+
+
+  
+
+    .x_result_sel_sext      (x_result_sel_sext_d),
+ 
+    
+    .x_result_sel_logic     (x_result_sel_logic_d),
+  
+          
+
+
+    .x_result_sel_add       (x_result_sel_add_d),
+    .m_result_sel_compare   (m_result_sel_compare_d),
+  
+
+    .m_result_sel_shift     (m_result_sel_shift_d),  
+ 
+    
+    .w_result_sel_load      (w_result_sel_load_d),
+  
+
+    .w_result_sel_mul       (w_result_sel_mul_d),
+ 
+
+    .x_bypass_enable        (x_bypass_enable_d),
+    .m_bypass_enable        (m_bypass_enable_d),
+    .read_enable_0          (read_enable_0_d),
+    .read_idx_0             (read_idx_0_d),
+    .read_enable_1          (read_enable_1_d),
+    .read_idx_1             (read_idx_1_d),
+    .write_enable           (write_enable_d),
+    .write_idx              (write_idx_d),
+    .immediate              (immediate_d),
+    .branch_offset          (branch_offset_d),
+    .load                   (load_d),
+    .store                  (store_d),
+    .size                   (size_d),
+    .sign_extend            (sign_extend_d),
+    .adder_op               (adder_op_d),
+    .logic_op               (logic_op_d),
+  
+
+    .direction              (direction_d),
+ 
+
+  
+                 
+                
+
+
+  
+                   
+
+
+  
+
+    .divide                 (divide_d),
+    .modulus                (modulus_d),
+ 
+
+    .branch                 (branch_d),
+    .bi_unconditional       (bi_unconditional),
+    .bi_conditional         (bi_conditional),
+    .branch_reg             (branch_reg_d),
+    .condition              (condition_d),
+  
+               
+
+
+    .scall                  (scall_d),
+    .eret                   (eret_d),
+  
+                       
+
+
+  
+                
+
+
+    .csr_write_enable       (csr_write_enable_d)
+    ); 
+
+
+lm32_load_store_unit_full #(
+    .associativity          (dcache_associativity),
+    .sets                   (dcache_sets),
+    .bytes_per_line         (dcache_bytes_per_line),
+    .base_address           (dcache_base_address),
+    .limit                  (dcache_limit)
+  ) load_store_unit (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    
+    .stall_a                (stall_a),
+    .stall_x                (stall_x),
+    .stall_m                (stall_m),
+    .kill_x                 (kill_x),
+    .kill_m                 (kill_m),
+    .exception_m            (exception_m),
+    .store_operand_x        (store_operand_x),
+    .load_store_address_x   (adder_result_x),
+    .load_store_address_m   (operand_m),
+    .load_store_address_w   (operand_w[1:0]),
+    .load_x                 (load_x),
+    .store_x                (store_x),
+    .load_q_x               (load_q_x),
+    .store_q_x              (store_q_x),
+    .load_q_m               (load_q_m),
+    .store_q_m              (store_q_m),
+    .sign_extend_x          (sign_extend_x),
+    .size_x                 (size_x),
+  
+
+    .dflush                 (dflush_m),
+ 
+
+
+  
+    
+    
+    
+    
+    
+    
+    
+
+
+		     
+    
+    .d_dat_i                (D_DAT_I),
+    .d_ack_i                (D_ACK_I),
+    .d_err_i                (D_ERR_I),
+    .d_rty_i                (D_RTY_I),
+    
+    
+  
+
+    .dcache_refill_request  (dcache_refill_request),
+    .dcache_restart_request (dcache_restart_request),
+    .dcache_stall_request   (dcache_stall_request),
+    .dcache_refilling       (dcache_refilling),
+ 
+    
+    .load_data_w            (load_data_w),
+    .stall_wb_load          (stall_wb_load),
+    
+    .d_dat_o                (D_DAT_O),
+    .d_adr_o                (D_ADR_O),
+    .d_cyc_o                (D_CYC_O),
+    .d_sel_o                (D_SEL_O),
+    .d_stb_o                (D_STB_O),
+    .d_we_o                 (D_WE_O),
+    .d_cti_o                (D_CTI_O),
+    .d_lock_o               (D_LOCK_O),
+    .d_bte_o                (D_BTE_O)
+    );      
+       
+
+lm32_adder adder (
+    
+    .adder_op_x             (adder_op_x),
+    .adder_op_x_n           (adder_op_x_n),
+    .operand_0_x            (operand_0_x),
+    .operand_1_x            (operand_1_x),
+    
+    .adder_result_x         (adder_result_x),
+    .adder_carry_n_x        (adder_carry_n_x),
+    .adder_overflow_x       (adder_overflow_x)
+    );
+
+
+lm32_logic_op logic_op (
+    
+    .logic_op_x             (logic_op_x),
+    .operand_0_x            (operand_0_x),
+
+    .operand_1_x            (operand_1_x),
+    
+    .logic_result_x         (logic_result_x)
+    );
+              
+  
+
+
+lm32_shifter shifter (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    .stall_x                (stall_x),
+    .direction_x            (direction_x),
+    .sign_extend_x          (sign_extend_x),
+    .operand_0_x            (operand_0_x),
+    .operand_1_x            (operand_1_x),
+    
+    .shifter_result_m       (shifter_result_m)
+    );
+ 
+
+
+  
+
+
+lm32_multiplier multiplier (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    .stall_x                (stall_x),
+    .stall_m                (stall_m),
+    .operand_0              (d_result_0),
+    .operand_1              (d_result_1),
+    
+    .result                 (multiplier_result_w)    
+    );
+ 
+
+
+  
+
+
+lm32_mc_arithmetic_full mc_arithmetic (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    .stall_d                (stall_d),
+    .kill_x                 (kill_x),
+  
+                  
+    .divide_d               (divide_q_d),
+    .modulus_d              (modulus_q_d),
+ 
+
+          
+                 
+
+
+  
+               
+              
+              
+
+    
+    .operand_0_d            (d_result_0),
+    .operand_1_d            (d_result_1),
+    
+    .result_x               (mc_result_x),
+  
+                  
+    .divide_by_zero_x       (divide_by_zero_x),
+ 
+
+    .stall_request_x        (mc_stall_request_x)
+    );
+ 
+
+              
+  
+
+
+lm32_interrupt_full interrupt_unit (
+    
+    .clk_i                  (clk_i), 
+    .rst_i                  (rst_i),
+    
+    .interrupt              (interrupt),
+    
+    .stall_x                (stall_x),
+  
+         
+            
+
+
+    .exception              (exception_q_w), 
+ 
+
+    .eret_q_x               (eret_q_x),
+  
+                   
+
+
+    .csr                    (csr_x),
+    .csr_write_data         (operand_1_x),
+    .csr_write_enable       (csr_write_enable_q_x),
+    
+    .interrupt_exception    (interrupt_exception),
+    
+    .csr_read_data          (interrupt_csr_read_data_x)
+    );
+ 
+
+
+  
+      
+      
+        
+   
+
+
+
+
+  
+
+  
+    
+                      
+                      
+    
+                   
+                
+                 
+            
+    
+ 
+                        
+             
+           
+                    
+
+ 
+             
+       
+
+ 
+                
+    
+    
+    
+ 
+          
+          
+
+ 
+      
+        
+                   
+           
+          
+            
+               
+
+ 
+                 
+                 
+
+    
+                 
+            
+    
+
+
+
+  
+
+ 
+                
+                
+    
+    
+                       
+                      
+                       
+                     
+                    
+       
+         
+             
+                      
+  
+	       
+      
+        
+                   
+	      
+	       
+      
+        
+                   
+	      
+
+ 
+                   
+                   
+                    
+                
+                        
+ 
+      
+
+
+    
+ 
+                      
+
+                      
+                   
+                   
+    
+
+
+
+
+
+  
+
+   
+           
+            
+          
+            
+
+
+             
+              
+    
+
+   wire [31:0] regfile_data_0, regfile_data_1;
+   reg [31:0]  w_result_d;
+   reg 	       regfile_raw_0, regfile_raw_0_nxt;
+   reg 	       regfile_raw_1, regfile_raw_1_nxt;
+   
+   
+             
+          
+
+   always @(reg_write_enable_q_w or write_idx_w or instruction_f)
+     begin
+	if (reg_write_enable_q_w
+	    && (write_idx_w == instruction_f[25:21]))
+	  regfile_raw_0_nxt = 1'b1;
+	else
+	  regfile_raw_0_nxt = 1'b0;
+	
+	if (reg_write_enable_q_w
+	    && (write_idx_w == instruction_f[20:16]))
+	  regfile_raw_1_nxt = 1'b1;
+	else
+	  regfile_raw_1_nxt = 1'b0;
+     end
+   
+   
+           
+           
+       
+
+   always @(regfile_raw_0 or w_result_d or regfile_data_0)
+     if (regfile_raw_0)
+       reg_data_live_0 = w_result_d;
+     else
+       reg_data_live_0 = regfile_data_0;
+   
+   
+           
+           
+       
+
+   always @(regfile_raw_1 or w_result_d or regfile_data_1)
+     if (regfile_raw_1)
+       reg_data_live_1 = w_result_d;
+     else
+       reg_data_live_1 = regfile_data_1;
+   
+   
+     
+
+   always @(posedge clk_i  )
+     if (rst_i ==  1'b1)
+       begin
+	  regfile_raw_0 <= 1'b0;
+	  regfile_raw_1 <= 1'b0;
+	  w_result_d <= 32'b0;
+       end
+     else
+       begin
+	  regfile_raw_0 <= regfile_raw_0_nxt;
+	  regfile_raw_1 <= regfile_raw_1_nxt;
+	  w_result_d <= w_result;
+       end
+   
+   
+      
+
+   
+   lm32_dp_ram
+     #(
+       
+       .addr_depth(1<<5),
+       .addr_width(5),
+       .data_width(32)
+       )
+   reg_0
+     (
+      
+      .clk_i	(clk_i),
+      .rst_i	(rst_i), 
+      .we_i	(reg_write_enable_q_w),
+      .wdata_i	(w_result),
+      .waddr_i	(write_idx_w),
+      .raddr_i	(instruction_f[25:21]),
+      
+      .rdata_o	(regfile_data_0)
+      );
+
+   lm32_dp_ram
+     #(
+       .addr_depth(1<<5),
+       .addr_width(5),
+       .data_width(32)
+       )
+   reg_1
+     (
+      
+      .clk_i	(clk_i),
+      .rst_i	(rst_i), 
+      .we_i	(reg_write_enable_q_w),
+      .wdata_i	(w_result),
+      .waddr_i	(write_idx_w),
+      .raddr_i	(instruction_f[20:16]),
+      
+      .rdata_o	(regfile_data_1)
+      );
+ 
+
+
+  
+   
+     
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+   
+     
+      
+      
+      
+      
+      
+      
+      
+        
+      
+       
+      
+      
+      
+   
+   
+     
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+   
+     
+      
+      
+      
+      
+      
+      
+      
+        
+      
+       
+      
+      
+      
+
+
+
+
+
+
+
+
+  
+
+
+assign reg_data_0 = use_buf ? reg_data_buf_0 : reg_data_live_0;
+assign reg_data_1 = use_buf ? reg_data_buf_1 : reg_data_live_1;
+ 
+
+  
+
+ 
+
+   
+   
+
+
+
+
+assign raw_x_0 = (write_idx_x == read_idx_0_d) && (write_enable_q_x ==  1'b1);
+assign raw_m_0 = (write_idx_m == read_idx_0_d) && (write_enable_q_m ==  1'b1);
+assign raw_w_0 = (write_idx_w == read_idx_0_d) && (write_enable_q_w ==  1'b1);
+assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x ==  1'b1);
+assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m ==  1'b1);
+assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w ==  1'b1);
+
+
+always @(*)
+begin
+    if (   (   (x_bypass_enable_x ==  1'b0)
+            && (   ((read_enable_0_d ==  1'b1) && (raw_x_0 ==  1'b1))
+                || ((read_enable_1_d ==  1'b1) && (raw_x_1 ==  1'b1))
+               )
+           )
+        || (   (m_bypass_enable_m ==  1'b0)
+            && (   ((read_enable_0_d ==  1'b1) && (raw_m_0 ==  1'b1))
+                || ((read_enable_1_d ==  1'b1) && (raw_m_1 ==  1'b1))
+               )
+           )
+       )
+        interlock =  1'b1;
+    else
+        interlock =  1'b0;
+end
+
+
+always @(*)
+begin
+    if (raw_x_0 ==  1'b1)        
+        bypass_data_0 = x_result;
+    else if (raw_m_0 ==  1'b1)
+        bypass_data_0 = m_result;
+    else if (raw_w_0 ==  1'b1)
+        bypass_data_0 = w_result;
+    else
+        bypass_data_0 = reg_data_0;
+end
+
+
+always @(*)
+begin
+    if (raw_x_1 ==  1'b1)
+        bypass_data_1 = x_result;
+    else if (raw_m_1 ==  1'b1)
+        bypass_data_1 = m_result;
+    else if (raw_w_1 ==  1'b1)
+        bypass_data_1 = w_result;
+    else
+        bypass_data_1 = reg_data_1;
+end
+
+   
+          
+       
+       
+     
+
+   assign branch_predict_d = bi_unconditional | bi_conditional;
+   assign branch_predict_taken_d = bi_unconditional ? 1'b1 : (bi_conditional ? instruction_d[15] : 1'b0);
+   
+   
+   assign branch_target_d = pc_d + branch_offset_d;
+
+   
+   
+   
+   assign branch_predict_address_d = branch_predict_taken_d ? branch_target_d : pc_f;
+
+
+always @(*)
+begin
+    d_result_0 = d_result_sel_0_d[0] ? {pc_f, 2'b00} : bypass_data_0; 
+    case (d_result_sel_1_d)
+     2'b00:      d_result_1 = { 32{1'b0}};
+     2'b01:     d_result_1 = bypass_data_1;
+     2'b10: d_result_1 = immediate_d;
+    default:                        d_result_1 = { 32{1'bx}};
+    endcase
+end
+
+      
+
+   
+   
+
+
+
+  
+
+
+assign sextb_result_x = {{24{operand_0_x[7]}}, operand_0_x[7:0]};
+assign sexth_result_x = {{16{operand_0_x[15]}}, operand_0_x[15:0]};
+assign sext_result_x = size_x ==  2'b00 ? sextb_result_x : sexth_result_x;
+ 
+
+
+  
+
+      
+
+
+
+
+assign cmp_zero = operand_0_x == operand_1_x;
+assign cmp_negative = adder_result_x[ 32-1];
+assign cmp_overflow = adder_overflow_x;
+assign cmp_carry_n = adder_carry_n_x;
+always @(*)
+begin
+    case (condition_x)
+     3'b000:   condition_met_x =  1'b1;
+     3'b110:   condition_met_x =  1'b1;
+     3'b001:    condition_met_x = cmp_zero;
+     3'b111:   condition_met_x = !cmp_zero;
+     3'b010:    condition_met_x = !cmp_zero && (cmp_negative == cmp_overflow);
+     3'b101:   condition_met_x = cmp_carry_n && !cmp_zero;
+     3'b011:   condition_met_x = cmp_negative == cmp_overflow;
+     3'b100:  condition_met_x = cmp_carry_n;
+    default:              condition_met_x = 1'bx;
+    endcase 
+end
+
+
+always @(*)
+begin
+    x_result =   x_result_sel_add_x ? adder_result_x 
+               : x_result_sel_csr_x ? csr_read_data_x
+  
+
+               : x_result_sel_sext_x ? sext_result_x
+ 
+
+  
+                  
+
+
+  
+                  
+
+
+  
+
+               : x_result_sel_mc_arith_x ? mc_result_x
+ 
+
+               : logic_result_x;
+end
+
+
+always @(*)
+begin
+    m_result =   m_result_sel_compare_m ? {{ 32-1{1'b0}}, condition_met_m}
+  
+
+               : m_result_sel_shift_m ? shifter_result_m
+ 
+
+               : operand_m; 
+end
+
+
+always @(*)
+begin
+    w_result =    w_result_sel_load_w ? load_data_w
+  
+
+                : w_result_sel_mul_w ? multiplier_result_w
+ 
+
+                : operand_w;
+end
+
+  
+    
+
+assign branch_taken_x =      (stall_x ==  1'b0)
+                          && (   (branch_x ==  1'b1)
+                              && ((condition_x ==  3'b000) || (condition_x ==  3'b110))
+                              && (valid_x ==  1'b1)
+                              && (branch_predict_x ==  1'b0)
+                             ); 
+ 
+
+
+
+assign branch_taken_m =      (stall_m ==  1'b0) 
+                          && (   (   (branch_m ==  1'b1) 
+                                  && (valid_m ==  1'b1)
+                                  && (   (   (condition_met_m ==  1'b1)
+					  && (branch_predict_taken_m ==  1'b0)
+					 )
+				      || (   (condition_met_m ==  1'b0)
+					  && (branch_predict_m ==  1'b1)
+					  && (branch_predict_taken_m ==  1'b1)
+					 )
+				     )
+                                 ) 
+                              || (exception_m ==  1'b1)
+                             );
+
+
+assign branch_mispredict_taken_m =    (condition_met_m ==  1'b0)
+                                   && (branch_predict_m ==  1'b1)
+	   			   && (branch_predict_taken_m ==  1'b1);
+   
+
+assign branch_flushX_m =    (stall_m ==  1'b0)
+                         && (   (   (branch_m ==  1'b1) 
+                                 && (valid_m ==  1'b1)
+			         && (   (condition_met_m ==  1'b1)
+				     || (   (condition_met_m ==  1'b0)
+					 && (branch_predict_m ==  1'b1)
+					 && (branch_predict_taken_m ==  1'b1)
+					)
+				    )
+			        )
+			     || (exception_m ==  1'b1)
+			    );
+
+
+assign kill_f =    (   (valid_d ==  1'b1)
+                    && (branch_predict_taken_d ==  1'b1)
+		   )
+                || (branch_taken_m ==  1'b1) 
+  
+    
+                || (branch_taken_x ==  1'b1)
+ 
+
+  
+
+                || (icache_refill_request ==  1'b1) 
+ 
+
+  
+                
+                || (dcache_refill_request ==  1'b1)
+ 
+
+                ;
+assign kill_d =    (branch_taken_m ==  1'b1) 
+  
+    
+                || (branch_taken_x ==  1'b1)
+ 
+
+  
+
+                || (icache_refill_request ==  1'b1)     
+ 
+                
+  
+                
+                || (dcache_refill_request ==  1'b1)
+ 
+
+                ;
+assign kill_x =    (branch_flushX_m ==  1'b1) 
+  
+                
+                || (dcache_refill_request ==  1'b1)
+ 
+
+                ;
+assign kill_m =     1'b0
+  
+                
+                || (dcache_refill_request ==  1'b1)
+ 
+
+                ;                
+assign kill_w =     1'b0
+  
+                
+                || (dcache_refill_request ==  1'b1)
+ 
+                
+                ;
+
+
+
+  
+              
+				         
+				     
+				     
+				 
+ 
+                                 
+
+                              
+
+
+
+  
+     
+
+
+
+  
+
+assign instruction_bus_error_exception = (   (bus_error_x ==  1'b1)
+                                          && (valid_x ==  1'b1)
+                                         );
+assign data_bus_error_exception = data_bus_error_seen ==  1'b1;
+ 
+
+
+  
+
+assign divide_by_zero_exception = divide_by_zero_x ==  1'b1;
+ 
+
+
+assign system_call_exception = (   (scall_x ==  1'b1)
+  
+
+                                && (valid_x ==  1'b1)
+ 
+
+			       );
+
+  
+      
+                            
+                         
+
+     
+ 
+                               
+
+ 
+                               
+                               
+
+ 
+                               
+
+ 
+                                  
+ 
+                                   
+                            
+ 
+ 				   
+				   
+
+                               
+
+                            
+
+         
+
+
+assign exception_x =           (system_call_exception ==  1'b1)
+  
+
+                            || (instruction_bus_error_exception ==  1'b1)
+                            || (data_bus_error_exception ==  1'b1)
+ 
+
+  
+
+                            || (divide_by_zero_exception ==  1'b1)
+ 
+
+  
+
+                            || (   (interrupt_exception ==  1'b1)
+  
+                                   
+
+                            
+  
+
+ 				&& (store_q_m ==  1'b0)
+				&& (D_CYC_O ==  1'b0)
+ 
+
+                               )
+ 
+
+                            ;
+ 
+
+
+  
+ 
+
+ 
+  
+      
+   
+      
+
+
+
+
+always @(*)
+begin
+  
+ 
+       
+          
+    
+     
+ 
+            
+          
+    
+
+            
+          
+    
+
+
+  
+
+         if (data_bus_error_exception ==  1'b1)
+        eid_x =  3'h4;
+    else
+         if (instruction_bus_error_exception ==  1'b1)
+        eid_x =  3'h2;
+    else
+ 
+
+  
+            
+          
+     
+
+
+  
+
+         if (divide_by_zero_exception ==  1'b1)
+        eid_x =  3'h5;
+    else
+ 
+
+  
+
+         if (   (interrupt_exception ==  1'b1)
+  
+                
+
+                            
+            )
+        eid_x =  3'h6;
+    else
+ 
+
+        eid_x =  3'h7;
+end
+
+
+
+assign stall_a = (stall_f ==  1'b1);
+                
+assign stall_f = (stall_d ==  1'b1);
+                
+assign stall_d =   (stall_x ==  1'b1) 
+                || (   (interlock ==  1'b1)
+                    && (kill_d ==  1'b0)
+                   ) 
+		|| (   (   (eret_d ==  1'b1)
+			|| (scall_d ==  1'b1)
+  
+
+			|| (bus_error_d ==  1'b1)
+ 
+
+		       )
+		    && (   (load_q_x ==  1'b1)
+			|| (load_q_m ==  1'b1)
+			|| (store_q_x ==  1'b1)
+			|| (store_q_m ==  1'b1)
+			|| (D_CYC_O ==  1'b1)
+		       )
+                    && (kill_d ==  1'b0)
+		   )
+  
+		         
+			   
+		       
+		          
+			   
+			   
+			   
+			   
+		       
+                       
+		   
+
+                   
+                || (   (csr_write_enable_d ==  1'b1)
+                    && (load_q_x ==  1'b1)
+                   )                      
+  
+                 
+                 
+                       
+		           
+			 
+			
+		    
+
+	
+                ;
+                
+assign stall_x =    (stall_m ==  1'b1)
+  
+
+                 || (   (mc_stall_request_x ==  1'b1)
+                     && (kill_x ==  1'b0)
+                    ) 
+ 
+
+
+	    
+                 ;
+
+assign stall_m =    (stall_wb_load ==  1'b1)
+  
+                    
+
+
+                 || (   (D_CYC_O ==  1'b1)
+                     && (   (store_m ==  1'b1)
+		         
+          
+          
+
+		  
+	 
+	
+
+          
+           
+          
+       
+
+  
+
+		         || ((store_x ==  1'b1) && (interrupt_exception ==  1'b1))
+ 
+
+                         || (load_m ==  1'b1)
+                         || (load_x ==  1'b1)
+                        ) 
+                    ) 
+ 
+                 
+  
+
+                 || (dcache_stall_request ==  1'b1)     
+ 
+                                    
+  
+
+                 || (icache_stall_request ==  1'b1)     
+                 || ((I_CYC_O ==  1'b1) && ((branch_m ==  1'b1) || (exception_m ==  1'b1))) 
+ 
+ 
+                                
+
+
+                               
+  
+                                  
+                        
+                    
+
+
+  
+                  
+   
+
+                 ;      
+
+
+
+
+  
+
+assign q_d = (valid_d ==  1'b1) && (kill_d ==  1'b0);
+ 
+
+  
+         
+         
+
+
+  
+         
+
+
+  
+
+assign divide_q_d = (divide_d ==  1'b1) && (q_d ==  1'b1);
+assign modulus_q_d = (modulus_d ==  1'b1) && (q_d ==  1'b1);
+ 
+
+assign q_x = (valid_x ==  1'b1) && (kill_x ==  1'b0);
+assign csr_write_enable_q_x = (csr_write_enable_x ==  1'b1) && (q_x ==  1'b1);
+assign eret_q_x = (eret_x ==  1'b1) && (q_x ==  1'b1);
+  
+         
+
+
+assign load_q_x = (load_x ==  1'b1) 
+               && (q_x ==  1'b1)
+  
+                  
+
+
+                  ;
+assign store_q_x = (store_x ==  1'b1) 
+               && (q_x ==  1'b1)
+  
+                  
+
+
+                  ;
+  
+         
+
+                              
+assign q_m = (valid_m ==  1'b1) && (kill_m ==  1'b0) && (exception_m ==  1'b0);
+assign load_q_m = (load_m ==  1'b1) && (q_m ==  1'b1);
+assign store_q_m = (store_m ==  1'b1) && (q_m ==  1'b1);
+  
+         
+                 
+
+
+assign exception_q_w = ((exception_w ==  1'b1) && (valid_w ==  1'b1));        
+ 
+
+
+assign write_enable_q_x = (write_enable_x ==  1'b1) && (valid_x ==  1'b1) && (branch_flushX_m ==  1'b0);
+assign write_enable_q_m = (write_enable_m ==  1'b1) && (valid_m ==  1'b1);
+assign write_enable_q_w = (write_enable_w ==  1'b1) && (valid_w ==  1'b1);
+
+assign reg_write_enable_q_w = (write_enable_w ==  1'b1) && (kill_w ==  1'b0) && (valid_w ==  1'b1);
+
+
+assign cfg = {
+               6'h02,
+              watchpoints[3:0],
+              breakpoints[3:0],
+              interrupts[5:0],
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+ 
+               1'b1
+ 
+              
+
+
+              };
+
+assign cfg2 = {
+		     30'b0,
+  
+		     
+
+
+		      1'b0,
+ 
+
+  
+		     
+
+
+		      1'b0
+ 
+
+		     };
+   
+
+  
+
+assign iflush = (   (csr_write_enable_d ==  1'b1) 
+                 && (csr_d ==  4 'h3)
+                 && (stall_d ==  1'b0)
+                 && (kill_d ==  1'b0)
+                 && (valid_d ==  1'b1))
+
+  
+             
+                     
+		    
+
+
+		 ;
+ 
+ 
+  
+
+assign dflush_x = (   (csr_write_enable_q_x ==  1'b1) 
+                   && (csr_x ==  4 'h4))
+
+  
+               
+                       
+		      
+
+
+		   ;
+ 
+ 
+
+
+assign csr_d = read_idx_0_d[ (4 -1):0];
+
+
+always @(*)
+begin
+    case (csr_x)
+  
+
+     4 'h0,
+     4 'h1,
+     4 'h2:   csr_read_data_x = interrupt_csr_read_data_x;  
+ 
+
+  
+         
+
+
+     4 'h6:  csr_read_data_x = cfg;
+     4 'h7:  csr_read_data_x = {eba, 8'h00};
+  
+        
+
+
+  
+          
+        
+
+
+     4 'ha: csr_read_data_x = cfg2;
+     4 'hb:  csr_read_data_x = sdb_address;
+  
+
+     4 'hc:  csr_read_data_x = data_bus_error_addr;
+ 
+
+      
+      
+    default:        csr_read_data_x = { 32{1'bx}};
+    endcase
+end
+
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        eba <= eba_reset[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+    else
+    begin
+        if ((csr_write_enable_q_x ==  1'b1) && (csr_x ==  4 'h7) && (stall_x ==  1'b0))
+            eba <= operand_1_x[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+  
+  
+              
+           
+ 
+  
+              
+           
+ 	 
+
+
+    end
+end
+
+  
+
+   
+
+       
+          
+    
+    
+                   
+              
+  
+   
+              
+           
+  
+   
+              
+           
+         
+ 
+    
+
+
+
+
+
+  
+   
+
+       
+          
+    
+            
+
+
+
+
+  
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        data_bus_error_seen <=  1'b0;
+    else
+    begin
+        
+        if ((D_ERR_I ==  1'b1) && (D_CYC_O ==  1'b1)) begin
+           data_bus_error_seen <=  1'b1;
+	   data_bus_error_addr <= D_ADR_O;
+	end
+        
+        if ((exception_m ==  1'b1) && (kill_m ==  1'b0))
+            data_bus_error_seen <=  1'b0;
+    end
+end
+ 
+
+ 
+
+
+  
+
+  
+
+always @(*)
+begin
+    if (   (icache_refill_request ==  1'b1) 
+        || (dcache_refill_request ==  1'b1)
+       )
+        valid_a =  1'b0;
+    else if (   (icache_restart_request ==  1'b1) 
+             || (dcache_restart_request ==  1'b1) 
+            ) 
+        valid_a =  1'b1;
+    else 
+        valid_a = !icache_refilling && !dcache_refilling;
+end 
+ 
+ 
+
+        
+          
+         
+          
+     
+          
+ 
+
+
+ 
+ 
+ 
+
+        
+          
+         
+          
+     
+          
+ 
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        valid_f <=  1'b0;
+        valid_d <=  1'b0;
+        valid_x <=  1'b0;
+        valid_m <=  1'b0;
+        valid_w <=  1'b0;
+    end
+    else
+    begin    
+        if ((kill_f ==  1'b1) || (stall_a ==  1'b0))
+  
+
+            valid_f <= valid_a;    
+ 
+              
+
+            
+        else if (stall_f ==  1'b0)
+            valid_f <=  1'b0;            
+
+        if (kill_d ==  1'b1)
+            valid_d <=  1'b0;
+        else if (stall_f ==  1'b0)
+            valid_d <= valid_f & !kill_f;
+        else if (stall_d ==  1'b0)
+            valid_d <=  1'b0;
+       
+        if (stall_d ==  1'b0)
+            valid_x <= valid_d & !kill_d;
+        else if (kill_x ==  1'b1)
+            valid_x <=  1'b0;
+        else if (stall_x ==  1'b0)
+            valid_x <=  1'b0;
+
+        if (kill_m ==  1'b1)
+            valid_m <=  1'b0;
+        else if (stall_x ==  1'b0)
+            valid_m <= valid_x & !kill_x;
+        else if (stall_m ==  1'b0)
+            valid_m <=  1'b0;
+
+        if (stall_m ==  1'b0)
+            valid_w <= valid_m & !kill_m;
+        else 
+            valid_w <=  1'b0;        
+    end
+end
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+  
+                 
+
+        
+        operand_0_x <= { 32{1'b0}};
+        operand_1_x <= { 32{1'b0}};
+        store_operand_x <= { 32{1'b0}};
+        branch_target_x <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};        
+        x_result_sel_csr_x <=  1'b0;
+  
+
+        x_result_sel_mc_arith_x <=  1'b0;
+ 
+
+      
+          
+
+
+  
+
+        x_result_sel_sext_x <=  1'b0;
+ 
+    
+  
+          
+
+
+        x_result_sel_add_x <=  1'b0;
+        m_result_sel_compare_x <=  1'b0;
+  
+
+        m_result_sel_shift_x <=  1'b0;
+ 
+    
+        w_result_sel_load_x <=  1'b0;
+  
+
+        w_result_sel_mul_x <=  1'b0;
+ 
+
+        x_bypass_enable_x <=  1'b0;
+        m_bypass_enable_x <=  1'b0;
+        write_enable_x <=  1'b0;
+        write_idx_x <= { 5{1'b0}};
+        csr_x <= { 4 {1'b0}};
+        load_x <=  1'b0;
+        store_x <=  1'b0;
+        size_x <= { 2{1'b0}};
+        sign_extend_x <=  1'b0;
+        adder_op_x <=  1'b0;
+        adder_op_x_n <=  1'b0;
+        logic_op_x <= 4'h0;
+  
+
+        direction_x <=  1'b0;
+ 
+
+  
+          
+
+
+
+        branch_x <=  1'b0;
+        branch_predict_x <=  1'b0;
+        branch_predict_taken_x <=  1'b0;
+        condition_x <=  3'b000;
+  
+          
+
+
+        scall_x <=  1'b0;
+        eret_x <=  1'b0;
+  
+          
+
+
+  
+
+        bus_error_x <=  1'b0;
+        data_bus_error_exception_m <=  1'b0;
+ 
+
+        csr_write_enable_x <=  1'b0;
+        operand_m <= { 32{1'b0}};
+        branch_target_m <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+        m_result_sel_compare_m <=  1'b0;
+  
+
+        m_result_sel_shift_m <=  1'b0;
+ 
+    
+        w_result_sel_load_m <=  1'b0;
+  
+
+        w_result_sel_mul_m <=  1'b0;
+ 
+
+        m_bypass_enable_m <=  1'b0;
+        branch_m <=  1'b0;
+        branch_predict_m <=  1'b0;
+	branch_predict_taken_m <=  1'b0;
+        exception_m <=  1'b0;
+        load_m <=  1'b0;
+        store_m <=  1'b0;
+        write_enable_m <=  1'b0;            
+        write_idx_m <= { 5{1'b0}};
+        condition_met_m <=  1'b0;
+  
+
+        dflush_m <=  1'b0;
+ 
+
+  
+          
+                  
+
+
+        operand_w <= { 32{1'b0}};        
+        w_result_sel_load_w <=  1'b0;
+  
+
+        w_result_sel_mul_w <=  1'b0;
+ 
+
+        write_idx_w <= { 5{1'b0}};        
+        write_enable_w <=  1'b0;
+  
+          
+                  
+
+
+        exception_w <=  1'b0;
+ 
+
+  
+
+        memop_pc_w <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ 
+
+    end
+    else
+    begin
+        
+       
+        if (stall_x ==  1'b0)
+        begin
+  
+                     
+
+        
+            operand_0_x <= d_result_0;
+            operand_1_x <= d_result_1;
+            store_operand_x <= bypass_data_1;
+            branch_target_x <= branch_reg_d ==  1'b1 ? bypass_data_0[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] : branch_target_d;            
+            x_result_sel_csr_x <= x_result_sel_csr_d;
+  
+
+            x_result_sel_mc_arith_x <= x_result_sel_mc_arith_d;
+ 
+
+      
+              
+
+
+  
+
+            x_result_sel_sext_x <= x_result_sel_sext_d;
+ 
+    
+  
+              
+
+
+            x_result_sel_add_x <= x_result_sel_add_d;
+            m_result_sel_compare_x <= m_result_sel_compare_d;
+  
+
+            m_result_sel_shift_x <= m_result_sel_shift_d;
+ 
+    
+            w_result_sel_load_x <= w_result_sel_load_d;
+  
+
+            w_result_sel_mul_x <= w_result_sel_mul_d;
+ 
+
+            x_bypass_enable_x <= x_bypass_enable_d;
+            m_bypass_enable_x <= m_bypass_enable_d;
+            load_x <= load_d;
+            store_x <= store_d;
+            branch_x <= branch_d;
+	    branch_predict_x <= branch_predict_d;
+	    branch_predict_taken_x <= branch_predict_taken_d;
+	    write_idx_x <= write_idx_d;
+            csr_x <= csr_d;
+            size_x <= size_d;
+            sign_extend_x <= sign_extend_d;
+            adder_op_x <= adder_op_d;
+            adder_op_x_n <= ~adder_op_d;
+            logic_op_x <= logic_op_d;
+  
+
+            direction_x <= direction_d;
+ 
+
+  
+              
+
+
+            condition_x <= condition_d;
+            csr_write_enable_x <= csr_write_enable_d;
+  
+              
+
+
+            scall_x <= scall_d;
+  
+
+            bus_error_x <= bus_error_d;
+ 
+
+            eret_x <= eret_d;
+  
+               
+
+
+            write_enable_x <= write_enable_d;
+        end
+        
+        
+
+        if (stall_m ==  1'b0)
+        begin
+            operand_m <= x_result;
+            m_result_sel_compare_m <= m_result_sel_compare_x;
+  
+
+            m_result_sel_shift_m <= m_result_sel_shift_x;
+ 
+    
+            if (exception_x ==  1'b1)
+            begin
+                w_result_sel_load_m <=  1'b0;
+  
+
+                w_result_sel_mul_m <=  1'b0;
+ 
+
+            end
+            else
+            begin
+                w_result_sel_load_m <= w_result_sel_load_x;
+  
+
+                w_result_sel_mul_m <= w_result_sel_mul_x;
+ 
+
+            end
+            m_bypass_enable_m <= m_bypass_enable_x;
+            load_m <= load_x;
+            store_m <= store_x;
+  
+    
+            branch_m <= branch_x && !branch_taken_x;
+ 
+              
+	      
+	      
+
+
+  
+	   
+	   
+	   
+	   
+	   
+                
+                  
+                
+                  
+             
+                  
+
+
+            if (exception_x ==  1'b1)
+                write_idx_m <=  5'd30;
+            else 
+                write_idx_m <= write_idx_x;
+ 
+
+            condition_met_m <= condition_met_x;
+  
+	      
+	        
+		     
+		        
+	           
+	     
+	           
+	   
+	       
+
+
+            branch_target_m <= exception_x ==  1'b1 ? {eba, eid_x, {3{1'b0}}} : branch_target_x;
+ 
+
+  
+              
+              
+
+
+  
+
+            dflush_m <= dflush_x;
+ 
+
+  
+ 
+               
+
+
+
+            write_enable_m <= exception_x ==  1'b1 ?  1'b1 : write_enable_x;            
+  
+              
+                      
+
+
+        end
+        
+        
+        if (stall_m ==  1'b0)
+        begin
+            if ((exception_x ==  1'b1) && (q_x ==  1'b1) && (stall_x ==  1'b0))
+                exception_m <=  1'b1;
+            else 
+                exception_m <=  1'b0;
+  
+
+	   data_bus_error_exception_m <=    (data_bus_error_exception ==  1'b1) 
+  
+					    
+
+
+					 ;
+ 
+
+	end
+                
+        
+  
+
+        operand_w <= exception_m ==  1'b1 ? (data_bus_error_exception_m ? {memop_pc_w, 2'b00} : {pc_m, 2'b00}) : m_result;
+ 
+                 
+
+
+        w_result_sel_load_w <= w_result_sel_load_m;
+  
+
+        w_result_sel_mul_w <= w_result_sel_mul_m;
+ 
+
+        write_idx_w <= write_idx_m;
+  
+          
+          
+ 
+           
+
+
+
+        write_enable_w <= write_enable_m;
+  
+          
+          
+
+
+        exception_w <= exception_m;
+ 
+
+  
+
+        if (   (stall_m ==  1'b0)
+            && (   (load_q_m ==  1'b1) 
+                || (store_q_m ==  1'b1)
+               )
+	   )
+          memop_pc_w <= pc_m;
+ 
+
+    end
+end
+
+  
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        use_buf <=  1'b0;
+        reg_data_buf_0 <= { 32{1'b0}};
+        reg_data_buf_1 <= { 32{1'b0}};
+    end
+    else
+    begin
+        if (stall_d ==  1'b0)
+            use_buf <=  1'b0;
+        else if (use_buf ==  1'b0)
+        begin        
+            reg_data_buf_0 <= reg_data_live_0;
+            reg_data_buf_1 <= reg_data_live_1;
+            use_buf <=  1'b1;
+        end        
+        if (reg_write_enable_q_w ==  1'b1)
+        begin
+            if (write_idx_w == read_idx_0_d)
+                reg_data_buf_0 <= w_result;
+            if (write_idx_w == read_idx_1_d)
+                reg_data_buf_1 <= w_result;
+        end
+    end
+end
+ 
+
+
+  
+
+ 
+
+   
+
+        
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+        
+     
+           
+            
+        
+
+
+
+
+  
+
+   
+
+       
+    
+          
+          
+          
+          
+          
+ 
+          
+
+          
+    
+    
+    
+          
+        
+ 
+               
+
+           
+
+                
+              
+              
+              
+              
+        
+        
+              
+        
+             
+        
+            
+                 
+            
+                
+                  
+                  
+            
+            
+              
+            
+              
+ 
+              
+
+        
+        
+        
+              
+ 
+              
+
+        
+    
+
+
+
+      
+
+
+
+
+
+        
+endmodule 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_load_store_unit_full 
+(
+    
+    clk_i,
+    rst_i,
+ 
+    stall_a,
+    stall_x,
+    stall_m,
+    kill_x,
+    kill_m,
+    exception_m,
+    store_operand_x,
+    load_store_address_x,
+    load_store_address_m,
+    load_store_address_w,
+    load_x,
+    store_x,
+    load_q_x,
+    store_q_x,
+    load_q_m,
+    store_q_m,
+    sign_extend_x,
+    size_x,
+  
+
+    dflush,
+ 
+
+    
+    d_dat_i,
+    d_ack_i,
+    d_err_i,
+    d_rty_i,
+    
+    
+  
+
+    dcache_refill_request,
+    dcache_restart_request,
+    dcache_stall_request,
+    dcache_refilling,
+ 
+    
+  
+    
+    
+    
+    
+    
+    
+    
+
+			     
+    load_data_w,
+    stall_wb_load,
+    
+    d_dat_o,
+    d_adr_o,
+    d_cyc_o,
+    d_sel_o,
+    d_stb_o,
+    d_we_o,
+    d_cti_o,
+    d_lock_o,
+    d_bte_o
+    );
+
+
+
+
+
+parameter associativity = 1;                            
+parameter sets = 512;                                   
+parameter bytes_per_line = 16;                          
+parameter base_address = 0;                             
+parameter limit = 0;                                    
+
+
+localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
+localparam addr_offset_lsb = 2;
+localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
+
+
+
+
+
+   input clk_i;                                            
+   
+input rst_i;                                            
+
+input stall_a;                                          
+input stall_x;                                          
+input stall_m;                                          
+input kill_x;                                           
+input kill_m;                                           
+input exception_m;                                      
+
+input [ (32-1):0] store_operand_x;                 
+input [ (32-1):0] load_store_address_x;            
+input [ (32-1):0] load_store_address_m;            
+input [1:0] load_store_address_w;                       
+input load_x;                                           
+input store_x;                                          
+input load_q_x;                                         
+input store_q_x;                                        
+input load_q_m;                                         
+input store_q_m;                                        
+input sign_extend_x;                                    
+input [ 1:0] size_x;                          
+
+  
+
+input dflush;                                           
+ 
+
+
+     
+     
+     
+      
+      
+            
+    	 
+   
+
+
+
+   reg 		 [31:0] iram_dat_d0;
+   reg 		 iram_en_d0;
+   wire 	 iram_en;
+   wire [31:0] 	 iram_data;
+   
+   
+   
+input [ (32-1):0] d_dat_i;                         
+input d_ack_i;                                          
+input d_err_i;                                          
+input d_rty_i;                                          
+
+
+
+
+
+  
+
+output dcache_refill_request;                           
+wire   dcache_refill_request;
+output dcache_restart_request;                          
+wire   dcache_restart_request;
+output dcache_stall_request;                            
+wire   dcache_stall_request;
+output dcache_refilling;
+wire   dcache_refilling;
+ 
+
+
+   
+output [ (32-1):0] load_data_w;                    
+reg    [ (32-1):0] load_data_w;
+output stall_wb_load;                                   
+reg    stall_wb_load;
+
+output [ (32-1):0] d_dat_o;                        
+reg    [ (32-1):0] d_dat_o;
+output [ (32-1):0] d_adr_o;                        
+reg    [ (32-1):0] d_adr_o;
+output d_cyc_o;                                         
+reg    d_cyc_o;
+output [ (4-1):0] d_sel_o;                 
+reg    [ (4-1):0] d_sel_o;
+output d_stb_o;                                         
+reg    d_stb_o; 
+output d_we_o;                                          
+reg    d_we_o;
+output [ (3-1):0] d_cti_o;                       
+reg    [ (3-1):0] d_cti_o;
+output d_lock_o;                                        
+reg    d_lock_o;
+output [ (2-1):0] d_bte_o;                       
+wire   [ (2-1):0] d_bte_o;
+
+
+
+
+
+
+reg [ 1:0] size_m;
+reg [ 1:0] size_w;
+reg sign_extend_m;
+reg sign_extend_w;
+reg [ (32-1):0] store_data_x;       
+reg [ (32-1):0] store_data_m;       
+reg [ (4-1):0] byte_enable_x;
+reg [ (4-1):0] byte_enable_m;
+wire [ (32-1):0] data_m;
+reg [ (32-1):0] data_w;
+
+   
+
+  
+
+wire dcache_select_x;                                   
+reg dcache_select_m;
+wire [ (32-1):0] dcache_data_m;                    
+wire [ (32-1):0] dcache_refill_address;            
+reg dcache_refill_ready;                                
+wire [ (3-1):0] first_cycle_type;                
+wire [ (3-1):0] next_cycle_type;                 
+wire last_word;                                         
+wire [ (32-1):0] first_address;                    
+ 
+
+  
+                                      
+ 
+                                      
+                    
+                      
+                        
+                  
+
+
+wire wb_select_x;                                       
+  
+                                      
+
+  
+    
+    
+   
+
+
+
+reg wb_select_m;
+reg [ (32-1):0] wb_data_m;                         
+reg wb_load_complete;                                   
+   
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+  
+
+
+lm32_dcache_full #(
+    .associativity          (associativity),
+    .sets                   (sets),
+    .bytes_per_line         (bytes_per_line),
+    .base_address           (base_address),
+    .limit                  (limit)
+    ) dcache ( 
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),      
+    .stall_a                (stall_a),
+    .stall_x                (stall_x),
+    .stall_m                (stall_m),
+    .address_x              (load_store_address_x),
+    .address_m              (load_store_address_m),
+    .load_q_m               (load_q_m & dcache_select_m),
+    .store_q_m              (store_q_m & dcache_select_m),
+    .store_data             (store_data_m),
+    .store_byte_select      (byte_enable_m & {4{dcache_select_m}}),
+    .refill_ready           (dcache_refill_ready),
+    .refill_data            (wb_data_m),
+    .dflush                 (dflush),
+    
+    .stall_request          (dcache_stall_request),
+    .restart_request        (dcache_restart_request),
+    .refill_request         (dcache_refill_request),
+    .refill_address         (dcache_refill_address),
+    .refilling              (dcache_refilling),
+    .load_data              (dcache_data_m)
+    );
+ 
+
+
+
+
+
+
+
+  
+            
+                             
+
+
+
+  
+            
+                             
+
+      
+        
+
+    
+       
+
+   
+
+    
+     
+       
+     
+         
+     
+
+          
+    
+   
+   
+
+
+   
+  
+
+   assign dcache_select_x =    (load_store_address_x >=  32'h0) 
+                            && (load_store_address_x <=  32'h7fffffff)
+  
+                               
+
+
+  
+                               
+
+
+                     ;
+ 
+
+	  
+   assign wb_select_x =     1'b1
+  
+
+                        && !dcache_select_x 
+ 
+
+  
+                         
+
+
+  
+                         
+
+
+                     ;
+
+
+always @(*)
+begin
+    case (size_x)
+     2'b00:  store_data_x = {4{store_operand_x[7:0]}};
+     2'b11: store_data_x = {2{store_operand_x[15:0]}};
+     2'b10:  store_data_x = store_operand_x;    
+    default:          store_data_x = { 32{1'bx}};
+    endcase
+end
+
+
+always @(*)
+begin
+    casez ({size_x, load_store_address_x[1:0]})
+    { 2'b00, 2'b11}:  byte_enable_x = 4'b0001;
+    { 2'b00, 2'b10}:  byte_enable_x = 4'b0010;
+    { 2'b00, 2'b01}:  byte_enable_x = 4'b0100;
+    { 2'b00, 2'b00}:  byte_enable_x = 4'b1000;
+    { 2'b11, 2'b1?}: byte_enable_x = 4'b0011;
+    { 2'b11, 2'b0?}: byte_enable_x = 4'b1100;
+    { 2'b10, 2'b??}:  byte_enable_x = 4'b1111;
+    default:                   byte_enable_x = 4'bxxxx;
+    endcase
+end
+
+  
+      
+            
+
+           
+	                            
+   
+   
+               
+        
+
+
+   
+  
+
+   
+   
+   
+         
+                    
+                       
+                      
+                        
+                     
+                        
+  
+   
+         
+                    
+                       
+                      
+                      
+  
+ 
+
+    
+   
+         
+                    
+                       
+                      
+                      
+  
+
+   
+   assign data_m = wb_select_m ==  1'b1 
+                   ? wb_data_m 
+                   : dcache_data_m;
+   
+
+  
+
+ 
+  
+   
+   
+         
+                     
+                      
+                      
+                      
+  
+   
+         
+                     
+                    
+  
+ 
+   
+   
+         
+                     
+                    
+
+  
+   
+      
+  
+ 
+
+
+
+
+always @(*)
+begin
+    casez ({size_w, load_store_address_w[1:0]})
+    { 2'b00, 2'b11}:  load_data_w = {{24{sign_extend_w & data_w[7]}}, data_w[7:0]};
+    { 2'b00, 2'b10}:  load_data_w = {{24{sign_extend_w & data_w[15]}}, data_w[15:8]};
+    { 2'b00, 2'b01}:  load_data_w = {{24{sign_extend_w & data_w[23]}}, data_w[23:16]};
+    { 2'b00, 2'b00}:  load_data_w = {{24{sign_extend_w & data_w[31]}}, data_w[31:24]};
+    { 2'b11, 2'b1?}: load_data_w = {{16{sign_extend_w & data_w[15]}}, data_w[15:0]};
+    { 2'b11, 2'b0?}: load_data_w = {{16{sign_extend_w & data_w[31]}}, data_w[31:16]};
+    { 2'b10, 2'b??}:  load_data_w = data_w;
+    default:                   load_data_w = { 32{1'bx}};
+    endcase
+end
+
+
+assign d_bte_o =  2'b00;
+
+  
+                
+
+generate 
+    case (bytes_per_line)
+    4:
+    begin
+assign first_cycle_type =  3'b111;
+assign next_cycle_type =  3'b111;
+assign last_word =  1'b1;
+assign first_address = {dcache_refill_address[ 32-1:2], 2'b00};
+    end
+    8:
+    begin
+assign first_cycle_type =  3'b010;
+assign next_cycle_type =  3'b111;
+assign last_word = (&d_adr_o[addr_offset_msb:addr_offset_lsb]) == 1'b1;
+assign first_address = {dcache_refill_address[ 32-1:addr_offset_msb+1], {addr_offset_width{1'b0}}, 2'b00};
+    end
+    16:
+    begin
+assign first_cycle_type =  3'b010;
+assign next_cycle_type = d_adr_o[addr_offset_msb] == 1'b1 ?  3'b111 :  3'b010;
+assign last_word = (&d_adr_o[addr_offset_msb:addr_offset_lsb]) == 1'b1;
+assign first_address = {dcache_refill_address[ 32-1:addr_offset_msb+1], {addr_offset_width{1'b0}}, 2'b00};
+    end
+    endcase
+endgenerate
+ 
+
+
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        d_cyc_o <=  1'b0;
+        d_stb_o <=  1'b0;
+        d_dat_o <= { 32{1'b0}};
+        d_adr_o <= { 32{1'b0}};
+        d_sel_o <= { 4{ 1'b0}};
+        d_we_o <=  1'b0;
+        d_cti_o <=  3'b111;
+        d_lock_o <=  1'b0;
+        wb_data_m <= { 32{1'b0}};
+        wb_load_complete <=  1'b0;
+        stall_wb_load <=  1'b0;
+  
+                
+        dcache_refill_ready <=  1'b0;
+ 
+                
+    end
+    else 
+    begin
+  
+ 
+        
+        dcache_refill_ready <=  1'b0;
+ 
+                
+        
+        if (d_cyc_o ==  1'b1)
+        begin
+            
+            if ((d_ack_i ==  1'b1) || (d_err_i ==  1'b1))
+            begin
+  
+                
+                if ((dcache_refilling ==  1'b1) && (!last_word))
+                begin
+                    
+                    d_adr_o[addr_offset_msb:addr_offset_lsb] <= d_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
+                end
+                else
+ 
+                
+                begin
+                    
+                    d_cyc_o <=  1'b0;
+                    d_stb_o <=  1'b0;
+                    d_lock_o <=  1'b0;
+                end
+  
+    
+                d_cti_o <= next_cycle_type;
+                
+                dcache_refill_ready <= dcache_refilling;
+ 
+
+                
+                wb_data_m <= d_dat_i;
+                
+                wb_load_complete <= !d_we_o;
+            end
+            
+        end
+        else 
+        begin
+  
+                
+            if (dcache_refill_request ==  1'b1)
+            begin
+                
+                d_adr_o <= first_address;
+                d_cyc_o <=  1'b1;
+                d_sel_o <= { 32/8{ 1'b1}};
+                d_stb_o <=  1'b1;                
+                d_we_o <=  1'b0;
+                d_cti_o <= first_cycle_type;
+                
+            end
+            else 
+ 
+            
+                 if (   (store_q_m ==  1'b1)
+                     && (stall_m ==  1'b0)
+  
+                        
+
+
+  
+		        
+
+			
+                    )
+            begin
+                
+                d_dat_o <= store_data_m;
+                d_adr_o <= load_store_address_m;
+                d_cyc_o <=  1'b1;
+                d_sel_o <= byte_enable_m;
+                d_stb_o <=  1'b1;
+                d_we_o <=  1'b1;
+                d_cti_o <=  3'b111;
+            end        
+            else if (   (load_q_m ==  1'b1) 
+                     && (wb_select_m ==  1'b1) 
+                     && (wb_load_complete ==  1'b0)
+                     
+                    )
+            begin
+                
+                stall_wb_load <=  1'b0;
+                d_adr_o <= load_store_address_m;
+                d_cyc_o <=  1'b1;
+                d_sel_o <= byte_enable_m;
+                d_stb_o <=  1'b1;
+                d_we_o <=  1'b0;
+                d_cti_o <=  3'b111;
+            end
+        end
+        
+        if (stall_m ==  1'b0)
+            wb_load_complete <=  1'b0;
+        
+        if ((load_q_x ==  1'b1) && (wb_select_x ==  1'b1) && (stall_x ==  1'b0))
+            stall_wb_load <=  1'b1;
+        
+        if ((kill_m ==  1'b1) || (exception_m ==  1'b1))
+            stall_wb_load <=  1'b0;
+    end
+end
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        sign_extend_m <=  1'b0;
+        size_m <= 2'b00;
+        byte_enable_m <=  1'b0;
+        store_data_m <= { 32{1'b0}};
+  
+
+        dcache_select_m <=  1'b0;
+ 
+
+  
+          
+
+
+  
+          
+			    
+
+
+        wb_select_m <=  1'b0;        
+    end
+    else
+    begin
+        if (stall_m ==  1'b0)
+        begin
+            sign_extend_m <= sign_extend_x;
+            size_m <= size_x;
+            byte_enable_m <= byte_enable_x;    
+            store_data_m <= store_data_x;
+  
+
+            dcache_select_m <= dcache_select_x;
+ 
+
+  
+              
+
+
+  
+              
+			    
+
+
+            wb_select_m <= wb_select_x;
+        end
+    end
+end
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        size_w <= 2'b00;
+        data_w <= { 32{1'b0}};
+        sign_extend_w <=  1'b0;
+    end
+    else
+    begin
+        size_w <= size_m;
+
+  
+         
+
+
+        data_w <= data_m;
+
+        sign_extend_w <= sign_extend_m;
+    end
+end
+
+
+
+
+
+
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_decoder_full (
+    
+    instruction,
+    
+    d_result_sel_0,
+    d_result_sel_1,        
+    x_result_sel_csr,
+  
+
+    x_result_sel_mc_arith,
+ 
+    
+      
+    
+
+
+  
+
+    x_result_sel_sext,
+ 
+    
+    x_result_sel_logic,
+  
+    
+
+
+    x_result_sel_add,
+    m_result_sel_compare,
+  
+
+    m_result_sel_shift,  
+ 
+    
+    w_result_sel_load,
+  
+
+    w_result_sel_mul,
+ 
+
+    x_bypass_enable,
+    m_bypass_enable,
+    read_enable_0,
+    read_idx_0,
+    read_enable_1,
+    read_idx_1,
+    write_enable,
+    write_idx,
+    immediate,
+    branch_offset,
+    load,
+    store,
+    size,
+    sign_extend,
+    adder_op,
+    logic_op,
+  
+
+    direction,
+ 
+
+  
+    
+    
+
+
+  
+    
+
+
+  
+
+    divide,
+    modulus,
+ 
+
+    branch,
+    branch_reg,
+    condition,
+    bi_conditional,
+    bi_unconditional,
+  
+    
+
+
+    scall,
+    eret,
+  
+    
+
+
+  
+    
+
+
+    csr_write_enable
+    );
+
+
+
+
+
+input [ (32-1):0] instruction;       
+
+
+
+
+
+output [ 0:0] d_result_sel_0;
+reg    [ 0:0] d_result_sel_0;
+output [ 1:0] d_result_sel_1;
+reg    [ 1:0] d_result_sel_1;
+output x_result_sel_csr;
+reg    x_result_sel_csr;
+  
+
+output x_result_sel_mc_arith;
+reg    x_result_sel_mc_arith;
+ 
+
+      
+ 
+    
+
+
+  
+
+output x_result_sel_sext;
+reg    x_result_sel_sext;
+ 
+
+output x_result_sel_logic;
+reg    x_result_sel_logic;
+  
+ 
+    
+
+
+output x_result_sel_add;
+reg    x_result_sel_add;
+output m_result_sel_compare;
+reg    m_result_sel_compare;
+  
+
+output m_result_sel_shift;
+reg    m_result_sel_shift;
+ 
+
+output w_result_sel_load;
+reg    w_result_sel_load;
+  
+
+output w_result_sel_mul;
+reg    w_result_sel_mul;
+ 
+
+output x_bypass_enable;
+wire   x_bypass_enable;
+output m_bypass_enable;
+wire   m_bypass_enable;
+output read_enable_0;
+wire   read_enable_0;
+output [ (5-1):0] read_idx_0;
+wire   [ (5-1):0] read_idx_0;
+output read_enable_1;
+wire   read_enable_1;
+output [ (5-1):0] read_idx_1;
+wire   [ (5-1):0] read_idx_1;
+output write_enable;
+wire   write_enable;
+output [ (5-1):0] write_idx;
+wire   [ (5-1):0] write_idx;
+output [ (32-1):0] immediate;
+wire   [ (32-1):0] immediate;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset;
+wire   [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset;
+output load;
+wire   load;
+output store;
+wire   store;
+output [ 1:0] size;
+wire   [ 1:0] size;
+output sign_extend;
+wire   sign_extend;
+output adder_op;
+wire   adder_op;
+output [ 3:0] logic_op;
+wire   [ 3:0] logic_op;
+  
+
+output direction;
+wire   direction;
+ 
+
+  
+ 
+   
+ 
+   
+
+
+  
+ 
+   
+
+
+  
+
+output divide;
+wire   divide;
+output modulus;
+wire   modulus;
+ 
+
+output branch;
+wire   branch;
+output branch_reg;
+wire   branch_reg;
+output [ (3-1):0] condition;
+wire   [ (3-1):0] condition;
+output bi_conditional;
+wire bi_conditional;
+output bi_unconditional;
+wire bi_unconditional;
+  
+ 
+   
+
+
+output scall;
+wire   scall;
+output eret;
+wire   eret;
+  
+ 
+   
+
+
+  
+  
+    
+
+
+output csr_write_enable;
+wire   csr_write_enable;
+
+
+
+
+
+wire [ (32-1):0] extended_immediate;       
+wire [ (32-1):0] high_immediate;           
+wire [ (32-1):0] call_immediate;           
+wire [ (32-1):0] branch_immediate;         
+wire sign_extend_immediate;                     
+wire select_high_immediate;                     
+wire select_call_immediate;                     
+
+wire op_add;
+wire op_and;
+wire op_andhi;
+wire op_b;
+wire op_bi;
+wire op_be;
+wire op_bg;
+wire op_bge;
+wire op_bgeu;
+wire op_bgu;
+wire op_bne;
+wire op_call;
+wire op_calli;
+wire op_cmpe;
+wire op_cmpg;
+wire op_cmpge;
+wire op_cmpgeu;
+wire op_cmpgu;
+wire op_cmpne;
+  
+
+wire op_divu;
+ 
+
+wire op_lb;
+wire op_lbu;
+wire op_lh;
+wire op_lhu;
+wire op_lw;
+  
+
+wire op_modu;
+ 
+
+  
+
+wire op_mul;
+ 
+
+wire op_nor;
+wire op_or;
+wire op_orhi;
+wire op_raise;
+wire op_rcsr;
+wire op_sb;
+  
+
+wire op_sextb;
+wire op_sexth;
+ 
+
+wire op_sh;
+  
+
+wire op_sl;
+ 
+
+wire op_sr;
+wire op_sru;
+wire op_sub;
+wire op_sw;
+  
+ 
+
+
+wire op_wcsr;
+wire op_xnor;
+wire op_xor;
+
+wire arith;
+wire logical;
+wire cmp;
+wire bra;
+wire call;
+  
+
+wire shift;
+ 
+
+  
+ 
+
+
+  
+
+wire sext;
+ 
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+assign op_add    = instruction[ 30:26] ==  5'b01101;
+assign op_and    = instruction[ 30:26] ==  5'b01000;
+assign op_andhi  = instruction[ 31:26] ==  6'b011000;
+assign op_b      = instruction[ 31:26] ==  6'b110000;
+assign op_bi     = instruction[ 31:26] ==  6'b111000;
+assign op_be     = instruction[ 31:26] ==  6'b010001;
+assign op_bg     = instruction[ 31:26] ==  6'b010010;
+assign op_bge    = instruction[ 31:26] ==  6'b010011;
+assign op_bgeu   = instruction[ 31:26] ==  6'b010100;
+assign op_bgu    = instruction[ 31:26] ==  6'b010101;
+assign op_bne    = instruction[ 31:26] ==  6'b010111;
+assign op_call   = instruction[ 31:26] ==  6'b110110;
+assign op_calli  = instruction[ 31:26] ==  6'b111110;
+assign op_cmpe   = instruction[ 30:26] ==  5'b11001;
+assign op_cmpg   = instruction[ 30:26] ==  5'b11010;
+assign op_cmpge  = instruction[ 30:26] ==  5'b11011;
+assign op_cmpgeu = instruction[ 30:26] ==  5'b11100;
+assign op_cmpgu  = instruction[ 30:26] ==  5'b11101;
+assign op_cmpne  = instruction[ 30:26] ==  5'b11111;
+  
+
+assign op_divu   = instruction[ 31:26] ==  6'b100011;
+ 
+
+assign op_lb     = instruction[ 31:26] ==  6'b000100;
+assign op_lbu    = instruction[ 31:26] ==  6'b010000;
+assign op_lh     = instruction[ 31:26] ==  6'b000111;
+assign op_lhu    = instruction[ 31:26] ==  6'b001011;
+assign op_lw     = instruction[ 31:26] ==  6'b001010;
+  
+
+assign op_modu   = instruction[ 31:26] ==  6'b110001;
+ 
+
+  
+
+assign op_mul    = instruction[ 30:26] ==  5'b00010;
+ 
+
+assign op_nor    = instruction[ 30:26] ==  5'b00001;
+assign op_or     = instruction[ 30:26] ==  5'b01110;
+assign op_orhi   = instruction[ 31:26] ==  6'b011110;
+assign op_raise  = instruction[ 31:26] ==  6'b101011;
+assign op_rcsr   = instruction[ 31:26] ==  6'b100100;
+assign op_sb     = instruction[ 31:26] ==  6'b001100;
+  
+
+assign op_sextb  = instruction[ 31:26] ==  6'b101100;
+assign op_sexth  = instruction[ 31:26] ==  6'b110111;
+ 
+
+assign op_sh     = instruction[ 31:26] ==  6'b000011;
+  
+
+assign op_sl     = instruction[ 30:26] ==  5'b01111;      
+ 
+
+assign op_sr     = instruction[ 30:26] ==  5'b00101;
+assign op_sru    = instruction[ 30:26] ==  5'b00000;
+assign op_sub    = instruction[ 31:26] ==  6'b110010;
+assign op_sw     = instruction[ 31:26] ==  6'b010110;
+  
+       
+
+
+assign op_wcsr   = instruction[ 31:26] ==  6'b110100;
+assign op_xnor   = instruction[ 30:26] ==  5'b01001;
+assign op_xor    = instruction[ 30:26] ==  5'b00110;
+
+
+assign arith = op_add | op_sub;
+assign logical = op_and | op_andhi | op_nor | op_or | op_orhi | op_xor | op_xnor;
+assign cmp = op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne;
+assign bi_conditional = op_be | op_bg | op_bge | op_bgeu  | op_bgu | op_bne;
+assign bi_unconditional = op_bi;
+assign bra = op_b | bi_unconditional | bi_conditional;
+assign call = op_call | op_calli;
+  
+
+assign shift = op_sl | op_sr | op_sru;
+ 
+
+  
+     
+
+
+  
+   
+     
+
+
+  
+
+assign sext = op_sextb | op_sexth;
+ 
+
+  
+   
+
+
+  
+
+assign divide = op_divu; 
+assign modulus = op_modu;
+ 
+
+assign load = op_lb | op_lbu | op_lh | op_lhu | op_lw;
+assign store = op_sb | op_sh | op_sw;
+
+
+always @(*)
+begin
+    
+    if (call) 
+        d_result_sel_0 =  1'b1;
+    else 
+        d_result_sel_0 =  1'b0;
+    if (call) 
+        d_result_sel_1 =  2'b00;         
+    else if ((instruction[31] == 1'b0) && !bra) 
+        d_result_sel_1 =  2'b10;
+    else
+        d_result_sel_1 =  2'b01; 
+    
+    x_result_sel_csr =  1'b0;
+  
+
+    x_result_sel_mc_arith =  1'b0;
+ 
+
+  
+      
+
+
+  
+
+    x_result_sel_sext =  1'b0;
+ 
+
+    x_result_sel_logic =  1'b0;
+          
+      
+
+
+    x_result_sel_add =  1'b0;
+    if (op_rcsr)
+        x_result_sel_csr =  1'b1;
+  
+    
+  
+         
+          
+
+
+  
+
+    else if (divide | modulus)
+        x_result_sel_mc_arith =  1'b1;        
+ 
+
+  
+      
+                      
+
+
+ 
+
+  
+      
+                  
+
+
+  
+
+    else if (sext)
+        x_result_sel_sext =  1'b1;
+ 
+        
+    else if (logical) 
+        x_result_sel_logic =  1'b1;
+          
+      
+          
+
+
+    else 
+        x_result_sel_add =  1'b1;        
+    
+    
+
+    m_result_sel_compare = cmp;
+  
+
+    m_result_sel_shift = shift;
+ 
+
+
+    
+    w_result_sel_load = load;
+  
+
+    w_result_sel_mul = op_mul; 
+ 
+
+end
+
+
+assign x_bypass_enable =  arith 
+                        | logical
+  
+                         
+                         
+
+                        
+  
+                         
+
+
+  
+
+                        | divide
+                        | modulus
+ 
+
+  
+                         
+
+                  
+  
+
+                        | sext 
+ 
+                        
+  
+                         
+
+
+                        | op_rcsr
+                        ;
+
+assign m_bypass_enable = x_bypass_enable 
+  
+
+                        | shift
+ 
+
+                        | cmp
+                        ;
+
+assign read_enable_0 = ~(op_bi | op_calli);
+assign read_idx_0 = instruction[25:21];
+
+assign read_enable_1 = ~(op_bi | op_calli | load);
+assign read_idx_1 = instruction[20:16];
+
+assign write_enable = ~(bra | op_raise | store | op_wcsr);
+assign write_idx = call
+                    ? 5'd29
+                    : instruction[31] == 1'b0 
+                        ? instruction[20:16] 
+                        : instruction[15:11];
+                        
+
+assign size = instruction[27:26];
+
+assign sign_extend = instruction[28];                      
+
+assign adder_op = op_sub | op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne | bra;
+
+assign logic_op = instruction[29:26];
+  
+
+
+assign direction = instruction[29];
+ 
+
+
+assign branch = bra | call;
+assign branch_reg = op_call | op_b;
+assign condition = instruction[28:26];      
+  
+     
+
+
+assign scall = op_raise & instruction[2];
+assign eret = op_b & (instruction[25:21] == 5'd30);
+  
+       
+
+
+  
+
+   
+
+
+
+assign csr_write_enable = op_wcsr;
+
+
+
+assign sign_extend_immediate = ~(op_and | op_cmpgeu | op_cmpgu | op_nor | op_or | op_xnor | op_xor);
+assign select_high_immediate = op_andhi | op_orhi;
+assign select_call_immediate = instruction[31];
+
+assign high_immediate = {instruction[15:0], 16'h0000};
+assign extended_immediate = {{16{sign_extend_immediate & instruction[15]}}, instruction[15:0]};
+assign call_immediate = {{6{instruction[25]}}, instruction[25:0]};
+assign branch_immediate = {{16{instruction[15]}}, instruction[15:0]};
+
+assign immediate = select_high_immediate ==  1'b1 
+                        ? high_immediate 
+                        : extended_immediate;
+   
+assign branch_offset = select_call_immediate ==  1'b1   
+                        ? (call_immediate[ (clogb2(32'h7fffffff-32'h0)-2)-1:0])
+                        : (branch_immediate[ (clogb2(32'h7fffffff-32'h0)-2)-1:0]);
+    
+endmodule 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_icache_full ( 
+    
+    clk_i,
+    rst_i,    
+    stall_a,
+    stall_f,
+    address_a,
+    address_f,
+    read_enable_f,
+    refill_ready,
+    refill_data,
+    iflush,
+  
+    
+
+
+    valid_d,
+    branch_predict_taken_d,
+    
+    stall_request,
+    restart_request,
+    refill_request,
+    refill_address,
+    refilling,
+    inst
+    );
+
+
+
+
+
+parameter associativity = 1;                            
+parameter sets = 512;                                   
+parameter bytes_per_line = 16;                          
+parameter base_address = 0;                             
+parameter limit = 0;                                    
+
+localparam addr_offset_width = clogb2(bytes_per_line)-1-2;
+localparam addr_set_width = clogb2(sets)-1;
+localparam addr_offset_lsb = 2;
+localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
+localparam addr_set_lsb = (addr_offset_msb+1);
+localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
+localparam addr_tag_lsb = (addr_set_msb+1);
+localparam addr_tag_msb = clogb2( 32'h7fffffff- 32'h0)-1;
+localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
+
+
+
+
+
+input clk_i;                                        
+input rst_i;                                        
+
+input stall_a;                                      
+input stall_f;                                      
+
+input valid_d;                                      
+input branch_predict_taken_d;                       
+   
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] address_a;                     
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] address_f;                     
+input read_enable_f;                                
+
+input refill_ready;                                 
+input [ (32-1):0] refill_data;          
+
+input iflush;                                       
+  
+                                      
+
+
+   
+
+
+
+
+output stall_request;                               
+wire   stall_request;
+output restart_request;                             
+reg    restart_request;
+output refill_request;                              
+wire   refill_request;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] refill_address;               
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] refill_address;               
+output refilling;                                   
+reg    refilling;
+output [ (32-1):0] inst;                
+wire   [ (32-1):0] inst;
+
+
+
+
+
+wire enable;
+wire [0:associativity-1] way_mem_we;
+wire [ (32-1):0] way_data[0:associativity-1];
+wire [ ((addr_tag_width+1)-1):1] way_tag[0:associativity-1];
+wire [0:associativity-1] way_valid;
+wire [0:associativity-1] way_match;
+wire miss;
+
+wire [ (addr_set_width-1):0] tmem_read_address;
+wire [ (addr_set_width-1):0] tmem_write_address;
+wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_read_address;
+wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_write_address;
+wire [ ((addr_tag_width+1)-1):0] tmem_write_data;
+
+reg [ 3:0] state;
+wire flushing;
+wire check;
+wire refill;
+
+reg [associativity-1:0] refill_way_select;
+reg [ addr_offset_msb:addr_offset_lsb] refill_offset;
+wire last_refill;
+reg [ (addr_set_width-1):0] flush_set;
+
+genvar i;
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+   generate
+      for (i = 0; i < associativity; i = i + 1)
+	begin : memories
+	   
+	   lm32_ram 
+	     #(
+	       
+	       .data_width                 (32),
+	       .address_width              ( (addr_offset_width+addr_set_width))
+
+) 
+	   way_0_data_ram 
+	     (
+	      
+	      .read_clk                   (clk_i),
+	      .write_clk                  (clk_i),
+	      .reset                      (rst_i),
+	      .read_address               (dmem_read_address),
+	      .enable_read                (enable),
+	      .write_address              (dmem_write_address),
+	      .enable_write               ( 1'b1),
+	      .write_enable               (way_mem_we[i]),
+	      .write_data                 (refill_data),    
+	      
+	      .read_data                  (way_data[i])
+	      );
+	   
+	   lm32_ram 
+	     #(
+	       
+	       .data_width                 ( (addr_tag_width+1)),
+	       .address_width              ( addr_set_width)
+
+	       ) 
+	   way_0_tag_ram 
+	     (
+	      
+	      .read_clk                   (clk_i),
+	      .write_clk                  (clk_i),
+	      .reset                      (rst_i),
+	      .read_address               (tmem_read_address),
+	      .enable_read                (enable),
+	      .write_address              (tmem_write_address),
+	      .enable_write               ( 1'b1),
+	      .write_enable               (way_mem_we[i] | flushing),
+	      .write_data                 (tmem_write_data),
+	      
+	      .read_data                  ({way_tag[i], way_valid[i]})
+	      );
+	   
+	end
+endgenerate
+
+
+
+
+
+
+generate
+    for (i = 0; i < associativity; i = i + 1)
+    begin : match
+assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_f[ addr_tag_msb:addr_tag_lsb],  1'b1});
+    end
+endgenerate
+
+
+generate
+    if (associativity == 1)
+    begin : inst_1
+assign inst = way_match[0] ? way_data[0] : 32'b0;
+    end
+    else if (associativity == 2)
+	 begin : inst_2
+assign inst = way_match[0] ? way_data[0] : (way_match[1] ? way_data[1] : 32'b0);
+    end
+endgenerate
+
+
+generate 
+    if (bytes_per_line > 4)
+assign dmem_write_address = {refill_address[ addr_set_msb:addr_set_lsb], refill_offset};
+    else
+assign dmem_write_address = refill_address[ addr_set_msb:addr_set_lsb];
+endgenerate
+    
+assign dmem_read_address = address_a[ addr_set_msb:addr_offset_lsb];
+
+
+assign tmem_read_address = address_a[ addr_set_msb:addr_set_lsb];
+assign tmem_write_address = flushing 
+                                ? flush_set
+                                : refill_address[ addr_set_msb:addr_set_lsb];
+
+
+generate 
+    if (bytes_per_line > 4)                            
+assign last_refill = refill_offset == {addr_offset_width{1'b1}};
+    else
+assign last_refill =  1'b1;
+endgenerate
+
+
+assign enable = (stall_a ==  1'b0);
+
+
+generate
+    if (associativity == 1) 
+    begin : we_1     
+assign way_mem_we[0] = (refill_ready ==  1'b1);
+    end
+    else
+    begin : we_2
+assign way_mem_we[0] = (refill_ready ==  1'b1) && (refill_way_select[0] ==  1'b1);
+assign way_mem_we[1] = (refill_ready ==  1'b1) && (refill_way_select[1] ==  1'b1);
+    end
+endgenerate                     
+
+
+assign tmem_write_data[ 0] = last_refill & !flushing;
+assign tmem_write_data[ ((addr_tag_width+1)-1):1] = refill_address[ addr_tag_msb:addr_tag_lsb];
+
+
+assign flushing = |state[1:0];
+assign check = state[2];
+assign refill = state[3];
+
+assign miss = (~(|way_match)) && (read_enable_f ==  1'b1) && (stall_f ==  1'b0) && !(valid_d && branch_predict_taken_d);
+assign stall_request = (check ==  1'b0);
+assign refill_request = (refill ==  1'b1);
+                      
+
+
+
+
+
+generate
+    if (associativity >= 2) 
+    begin : way_select      
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
+    else
+    begin        
+        if (miss ==  1'b1)
+            refill_way_select <= {refill_way_select[0], refill_way_select[1]};
+    end
+end
+    end
+endgenerate
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        refilling <=  1'b0;
+    else
+        refilling <= refill;
+end
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        state <=  4'b0001;
+        flush_set <= { addr_set_width{1'b1}};
+        refill_address <= { (clogb2(32'h7fffffff-32'h0)-2){1'bx}};
+        restart_request <=  1'b0;
+    end
+    else 
+    begin
+        case (state)
+
+        
+         4'b0001:
+        begin            
+            if (flush_set == { addr_set_width{1'b0}})
+                state <=  4'b0100;
+            flush_set <= flush_set - 1'b1;
+        end
+
+        
+         4'b0010:
+        begin            
+            if (flush_set == { addr_set_width{1'b0}})
+  
+	       
+                  
+	      
+
+
+		state <=  4'b0100;
+	   
+            flush_set <= flush_set - 1'b1;
+        end
+        
+        
+         4'b0100:
+        begin            
+            if (stall_a ==  1'b0)
+                restart_request <=  1'b0;
+            if (iflush ==  1'b1)
+            begin
+                refill_address <= address_f;
+                state <=  4'b0010;
+            end
+            else if (miss ==  1'b1)
+            begin
+                refill_address <= address_f;
+                state <=  4'b1000;
+            end
+        end
+
+        
+         4'b1000:
+        begin            
+            if (refill_ready ==  1'b1)
+            begin
+                if (last_refill ==  1'b1)
+                begin
+                    restart_request <=  1'b1;
+                    state <=  4'b0100;
+                end
+            end
+        end
+
+        endcase        
+    end
+end
+
+generate 
+    if (bytes_per_line > 4)
+    begin
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        refill_offset <= {addr_offset_width{1'b0}};
+    else 
+    begin
+        case (state)
+        
+        
+         4'b0100:
+        begin            
+            if (iflush ==  1'b1)
+                refill_offset <= {addr_offset_width{1'b0}};
+            else if (miss ==  1'b1)
+                refill_offset <= {addr_offset_width{1'b0}};
+        end
+
+        
+         4'b1000:
+        begin            
+            if (refill_ready ==  1'b1)
+                refill_offset <= refill_offset + 1'b1;
+        end
+
+        endcase        
+    end
+end
+    end
+endgenerate
+   
+endmodule
+
+ 
+
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+                  
+                    
+                 
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+             
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+                   
+               
+                 
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+                      
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+                    
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+                      
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+           
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+                
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+                  
+                    
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+              
+          
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+               
+                   
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+                 
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+               
+              
+          
+                   
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+                   
+                
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+  
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+
+
+
+module lm32_dcache_full ( 
+    
+    clk_i,
+    rst_i,    
+    stall_a,
+    stall_x,
+    stall_m,
+    address_x,
+    address_m,
+    load_q_m,
+    store_q_m,
+    store_data,
+    store_byte_select,
+    refill_ready,
+    refill_data,
+    dflush,
+    
+    stall_request,
+    restart_request,
+    refill_request,
+    refill_address,
+    refilling,
+    load_data
+    );
+
+
+
+
+
+parameter associativity = 1;                            
+parameter sets = 512;                                   
+parameter bytes_per_line = 16;                          
+parameter base_address = 0;                             
+parameter limit = 0;                                    
+
+localparam addr_offset_width = clogb2(bytes_per_line)-1-2;
+localparam addr_set_width = clogb2(sets)-1;
+localparam addr_offset_lsb = 2;
+localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
+localparam addr_set_lsb = (addr_offset_msb+1);
+localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
+localparam addr_tag_lsb = (addr_set_msb+1);
+localparam addr_tag_msb = clogb2( 32'h7fffffff- 32'h0)-1;
+localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
+
+
+
+
+
+input clk_i;                                            
+input rst_i;                                            
+
+input stall_a;                                          
+input stall_x;                                          
+input stall_m;                                          
+
+input [ (32-1):0] address_x;                       
+input [ (32-1):0] address_m;                       
+input load_q_m;                                         
+input store_q_m;                                        
+input [ (32-1):0] store_data;                      
+input [ (4-1):0] store_byte_select;        
+
+input refill_ready;                                     
+input [ (32-1):0] refill_data;                     
+
+input dflush;                                           
+
+
+
+
+
+output stall_request;                                   
+wire   stall_request;
+output restart_request;                                 
+reg    restart_request;
+output refill_request;                                  
+reg    refill_request;
+output [ (32-1):0] refill_address;                 
+reg    [ (32-1):0] refill_address;
+output refilling;                                       
+reg    refilling;
+output [ (32-1):0] load_data;                      
+wire   [ (32-1):0] load_data;
+
+
+
+
+
+wire read_port_enable;                                  
+wire write_port_enable;                                 
+wire [0:associativity-1] way_tmem_we;                   
+wire [0:associativity-1] way_dmem_we;                   
+wire [ (32-1):0] way_data[0:associativity-1];      
+wire [ ((addr_tag_width+1)-1):1] way_tag[0:associativity-1];
+wire [0:associativity-1] way_valid;                     
+wire [0:associativity-1] way_match;                     
+wire miss;                                              
+
+wire [ (addr_set_width-1):0] tmem_read_address;        
+wire [ (addr_set_width-1):0] tmem_write_address;       
+wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_read_address;        
+wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_write_address;       
+wire [ ((addr_tag_width+1)-1):0] tmem_write_data;               
+reg [ (32-1):0] dmem_write_data;                   
+
+reg [ 2:0] state;                         
+wire flushing;                                          
+wire check;                                             
+wire refill;                                            
+
+wire valid_store;                                       
+reg [associativity-1:0] refill_way_select;              
+reg [ addr_offset_msb:addr_offset_lsb] refill_offset;           
+wire last_refill;                                       
+reg [ (addr_set_width-1):0] flush_set;                 
+
+genvar i, j;
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+   generate
+      for (i = 0; i < associativity; i = i + 1)    
+	begin : memories
+	   
+           if ( (addr_offset_width+addr_set_width) < 11)
+             begin : data_memories
+		lm32_ram 
+		  #(
+		    
+		    .data_width (32),
+		    .address_width ( (addr_offset_width+addr_set_width))
+
+		    ) way_0_data_ram 
+		    (
+		     
+		     .read_clk (clk_i),
+		     .write_clk (clk_i),
+		     .reset (rst_i),
+		     .read_address (dmem_read_address),
+		     .enable_read (read_port_enable),
+		     .write_address (dmem_write_address),
+		     .enable_write (write_port_enable),
+		     .write_enable (way_dmem_we[i]),
+		     .write_data (dmem_write_data),    
+		     
+		     .read_data (way_data[i])
+		     );    
+             end
+           else
+             begin
+		for (j = 0; j < 4; j = j + 1)    
+		  begin : byte_memories
+		     lm32_ram 
+		       #(
+			 
+			 .data_width (8),
+			 .address_width ( (addr_offset_width+addr_set_width))
+
+			 ) way_0_data_ram 
+			 (
+			  
+			  .read_clk (clk_i),
+			  .write_clk (clk_i),
+			  .reset (rst_i),
+			  .read_address (dmem_read_address),
+			  .enable_read (read_port_enable),
+			  .write_address (dmem_write_address),
+			  .enable_write (write_port_enable),
+			  .write_enable (way_dmem_we[i] & (store_byte_select[j] | refill)),
+			  .write_data (dmem_write_data[(j+1)*8-1:j*8]),    
+			  
+			  .read_data (way_data[i][(j+1)*8-1:j*8])
+			  );
+		  end
+             end
+	   
+	   
+	   lm32_ram 
+	     #(
+	       
+	       .data_width ( (addr_tag_width+1)),
+	       .address_width ( addr_set_width)
+
+	       ) way_0_tag_ram 
+	       (
+		
+		.read_clk (clk_i),
+		.write_clk (clk_i),
+		.reset (rst_i),
+		.read_address (tmem_read_address),
+		.enable_read (read_port_enable),
+		.write_address (tmem_write_address),
+		.enable_write ( 1'b1),
+		.write_enable (way_tmem_we[i]),
+		.write_data (tmem_write_data),
+		
+		.read_data ({way_tag[i], way_valid[i]})
+		);
+	end
+      
+   endgenerate
+
+
+
+
+
+
+generate
+    for (i = 0; i < associativity; i = i + 1)
+    begin : match
+assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_m[ addr_tag_msb:addr_tag_lsb],  1'b1});
+    end
+endgenerate
+
+
+generate
+    if (associativity == 1)    
+	 begin : data_1
+assign load_data = way_data[0];
+    end
+    else if (associativity == 2)
+	 begin : data_2
+assign load_data = way_match[0] ? way_data[0] : way_data[1]; 
+    end
+endgenerate
+
+generate
+    if ( (addr_offset_width+addr_set_width) < 11)
+    begin
+
+always @(*)
+begin
+    if (refill ==  1'b1)
+        dmem_write_data = refill_data;
+    else
+    begin
+        dmem_write_data[ 7:0] = store_byte_select[0] ? store_data[ 7:0] : load_data[ 7:0];
+        dmem_write_data[ 15:8] = store_byte_select[1] ? store_data[ 15:8] : load_data[ 15:8];
+        dmem_write_data[ 23:16] = store_byte_select[2] ? store_data[ 23:16] : load_data[ 23:16];
+        dmem_write_data[ 31:24] = store_byte_select[3] ? store_data[ 31:24] : load_data[ 31:24];
+    end
+end
+    end
+    else
+    begin
+
+always @(*)
+begin
+    if (refill ==  1'b1)
+        dmem_write_data = refill_data;
+    else
+        dmem_write_data = store_data;
+end
+    end
+endgenerate
+
+
+generate 
+     if (bytes_per_line > 4)
+assign dmem_write_address = (refill ==  1'b1) 
+                            ? {refill_address[ addr_set_msb:addr_set_lsb], refill_offset}
+                            : address_m[ addr_set_msb:addr_offset_lsb];
+    else
+assign dmem_write_address = (refill ==  1'b1) 
+                            ? refill_address[ addr_set_msb:addr_set_lsb]
+                            : address_m[ addr_set_msb:addr_offset_lsb];
+endgenerate
+assign dmem_read_address = address_x[ addr_set_msb:addr_offset_lsb];
+
+assign tmem_write_address = (flushing ==  1'b1)
+                            ? flush_set
+                            : refill_address[ addr_set_msb:addr_set_lsb];
+assign tmem_read_address = address_x[ addr_set_msb:addr_set_lsb];
+
+
+generate 
+    if (bytes_per_line > 4)                            
+assign last_refill = refill_offset == {addr_offset_width{1'b1}};
+    else
+assign last_refill =  1'b1;
+endgenerate
+
+
+assign read_port_enable = (stall_x ==  1'b0);
+assign write_port_enable = (refill_ready ==  1'b1) || !stall_m;
+
+
+assign valid_store = (store_q_m ==  1'b1) && (check ==  1'b1);
+
+
+generate
+    if (associativity == 1) 
+    begin : we_1     
+assign way_dmem_we[0] = (refill_ready ==  1'b1) || ((valid_store ==  1'b1) && (way_match[0] ==  1'b1));
+assign way_tmem_we[0] = (refill_ready ==  1'b1) || (flushing ==  1'b1);
+    end 
+    else 
+    begin : we_2
+assign way_dmem_we[0] = ((refill_ready ==  1'b1) && (refill_way_select[0] ==  1'b1)) || ((valid_store ==  1'b1) && (way_match[0] ==  1'b1));
+assign way_dmem_we[1] = ((refill_ready ==  1'b1) && (refill_way_select[1] ==  1'b1)) || ((valid_store ==  1'b1) && (way_match[1] ==  1'b1));
+assign way_tmem_we[0] = ((refill_ready ==  1'b1) && (refill_way_select[0] ==  1'b1)) || (flushing ==  1'b1);
+assign way_tmem_we[1] = ((refill_ready ==  1'b1) && (refill_way_select[1] ==  1'b1)) || (flushing ==  1'b1);
+    end
+endgenerate
+
+
+assign tmem_write_data[ 0] = ((last_refill ==  1'b1) || (valid_store ==  1'b1)) && (flushing ==  1'b0);
+assign tmem_write_data[ ((addr_tag_width+1)-1):1] = refill_address[ addr_tag_msb:addr_tag_lsb];
+
+
+assign flushing = state[0];
+assign check = state[1];
+assign refill = state[2];
+
+assign miss = (~(|way_match)) && (load_q_m ==  1'b1) && (stall_m ==  1'b0);
+assign stall_request = (check ==  1'b0);
+                      
+
+
+
+
+
+generate
+    if (associativity >= 2) 
+    begin : way_select      
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
+    else
+    begin        
+        if (refill_request ==  1'b1)
+            refill_way_select <= {refill_way_select[0], refill_way_select[1]};
+    end
+end
+    end 
+endgenerate   
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        refilling <=  1'b0;
+    else 
+        refilling <= refill;
+end
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        state <=  3'b001;
+        flush_set <= { addr_set_width{1'b1}};
+        refill_request <=  1'b0;
+        refill_address <= { 32{1'bx}};
+        restart_request <=  1'b0;
+    end
+    else 
+    begin
+        case (state)
+
+        
+         3'b001:
+        begin
+            if (flush_set == { addr_set_width{1'b0}})
+                state <=  3'b010;
+            flush_set <= flush_set - 1'b1;
+        end
+        
+        
+         3'b010:
+        begin
+            if (stall_a ==  1'b0)
+                restart_request <=  1'b0;
+            if (miss ==  1'b1)
+            begin
+                refill_request <=  1'b1;
+                refill_address <= address_m;
+                state <=  3'b100;
+            end
+            else if (dflush ==  1'b1)
+                state <=  3'b001;
+        end
+
+        
+         3'b100:
+        begin
+            refill_request <=  1'b0;
+            if (refill_ready ==  1'b1)
+            begin
+                if (last_refill ==  1'b1)
+                begin
+                    restart_request <=  1'b1;
+                    state <=  3'b010;
+                end
+            end
+        end
+        
+        endcase        
+    end
+end
+
+generate
+    if (bytes_per_line > 4)
+    begin
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        refill_offset <= {addr_offset_width{1'b0}};
+    else 
+    begin
+        case (state)
+        
+        
+         3'b010:
+        begin
+            if (miss ==  1'b1)
+                refill_offset <= {addr_offset_width{1'b0}};
+        end
+
+        
+         3'b100:
+        begin
+            if (refill_ready ==  1'b1)
+                refill_offset <= refill_offset + 1'b1;
+        end
+        
+        endcase        
+    end
+end
+    end
+endgenerate
+
+endmodule
+
+ 
+
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+               
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+                  
+                 
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+                          
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+               
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+    
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+               
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+               
+      
+             
+                   
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+                
+                 
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+                 
+        
+              
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+    
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+               
+      
+   
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+       
+    
+          
+          
+    
+    
+    
+           
+        
+               
+                  
+                 
+                  
+        
+      
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+   
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+       
+          
+    
+    
+               
+              
+    
+    
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+   
+
+       
+    
+          
+          
+    
+    
+    
+               
+        
+              
+                
+                  
+             
+                  
+        
+         
+        
+        
+            
+                     
+                       
+                    
+                   
+               
+                   
+        
+        
+        
+            
+                   
+                  
+        
+        
+        
+            
+ 
+               
+                  
+             
+
+                            
+            
+                  
+                  
+            
+        
+        
+        
+            
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+               
+                  
+             
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+                  
+                    
+                 
+                   
+           
+             
+
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+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
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+                      
+
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+           
+             
+
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+                
+           
+
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+              
+               
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+                    
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+                
+
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+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_instruction_unit_full (
+    
+    clk_i,
+    rst_i,
+    
+    stall_a,
+    stall_f,
+    stall_d,
+    stall_x,
+    stall_m,
+    valid_f,
+    valid_d,
+    kill_f,
+    branch_predict_taken_d,
+    branch_predict_address_d,
+  
+    
+    branch_taken_x,
+    branch_target_x,
+ 
+
+    exception_m,
+    branch_taken_m,
+    branch_mispredict_taken_m,
+    branch_target_m,
+  
+
+    iflush,
+ 
+
+  
+
+    dcache_restart_request,
+    dcache_refill_request,
+    dcache_refilling,
+ 
+        
+  
+
+    
+    i_dat_i,
+    i_ack_i,
+    i_err_i,
+    i_rty_i,
+ 
+
+  
+    
+    
+    
+    
+
+
+    
+    
+    pc_f,
+    pc_d,
+    pc_x,
+    pc_m,
+    pc_w,
+  
+
+    icache_stall_request,
+    icache_restart_request,
+    icache_refill_request,
+    icache_refilling,
+ 
+
+  
+
+    
+    i_dat_o,
+    i_adr_o,
+    i_cyc_o,
+    i_sel_o,
+    i_stb_o,
+    i_we_o,
+    i_cti_o,
+    i_lock_o,
+    i_bte_o,
+ 
+
+  
+    
+    
+    
+
+
+  
+    
+    
+
+
+  
+
+    bus_error_d,
+ 
+
+  
+
+    instruction_f,
+ 
+    
+    instruction_d
+    );
+
+
+
+
+
+parameter eba_reset =  32'h00000000;                   
+parameter associativity = 1;                            
+parameter sets = 512;                                   
+parameter bytes_per_line = 16;                          
+parameter base_address = 0;                             
+parameter limit = 0;                                    
+
+
+localparam eba_reset_minus_4 = eba_reset - 4;
+localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
+localparam addr_offset_lsb = 2;
+localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
+
+
+
+
+  
+  
+   
+        
+   
+
+
+
+input clk_i;                                            
+input rst_i;                                            
+
+input stall_a;                                          
+input stall_f;                                          
+input stall_d;                                          
+input stall_x;                                          
+input stall_m;                                          
+input valid_f;                                          
+input valid_d;                                          
+input kill_f;                                           
+
+input branch_predict_taken_d;                           
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d;          
+   
+  
+    
+input branch_taken_x;                                   
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_x;                   
+ 
+
+input exception_m;
+input branch_taken_m;                                   
+input branch_mispredict_taken_m;                        
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_m;                   
+
+  
+
+input iflush;                                           
+ 
+
+  
+
+input dcache_restart_request;                           
+input dcache_refill_request;                            
+input dcache_refilling;
+ 
+        
+
+
+  
+
+input [ (32-1):0] i_dat_i;                         
+input i_ack_i;                                          
+input i_err_i;                                          
+input i_rty_i;                                          
+ 
+
+
+  
+                                  
+                                 
+                   
+                      
+
+
+
+
+
+
+        
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;                             
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;                             
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;                             
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;                             
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;                             
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;
+
+  
+
+output icache_stall_request;                            
+wire   icache_stall_request;
+output icache_restart_request;                          
+wire   icache_restart_request;
+output icache_refill_request;                           
+wire   icache_refill_request;
+output icache_refilling;                                
+wire   icache_refilling;
+ 
+
+
+  
+
+output [ (32-1):0] i_dat_o;                        
+  
+     
+
+
+wire   [ (32-1):0] i_dat_o;
+ 
+
+output [ (32-1):0] i_adr_o;                        
+reg    [ (32-1):0] i_adr_o;
+output i_cyc_o;                                         
+reg    i_cyc_o; 
+output [ (4-1):0] i_sel_o;                 
+  
+     
+
+
+wire   [ (4-1):0] i_sel_o;
+ 
+
+output i_stb_o;                                         
+reg    i_stb_o;
+output i_we_o;                                          
+  
+    
+
+
+wire   i_we_o;
+ 
+
+output [ (3-1):0] i_cti_o;                       
+reg    [ (3-1):0] i_cti_o;
+output i_lock_o;                                        
+reg    i_lock_o;
+output [ (2-1):0] i_bte_o;                       
+wire   [ (2-1):0] i_bte_o;
+ 
+
+
+  
+                   
+     
+                             
+   
+
+
+
+  
+
+output bus_error_d;                                     
+reg    bus_error_d;
+ 
+
+  
+
+output [ (32-1):0] instruction_f;           
+wire   [ (32-1):0] instruction_f;
+ 
+
+output [ (32-1):0] instruction_d;           
+reg    [ (32-1):0] instruction_d;
+
+
+
+
+
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_a;                                
+
+  
+
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] restart_address;                     
+ 
+
+
+  
+
+wire icache_read_enable_f;                              
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] icache_refill_address;              
+reg icache_refill_ready;                                
+reg [ (32-1):0] icache_refill_data;         
+wire [ (32-1):0] icache_data_f;             
+wire [ (3-1):0] first_cycle_type;                
+wire [ (3-1):0] next_cycle_type;                 
+wire last_word;                                         
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] first_address;                      
+ 
+ 
+                    
+
+
+
+  
+                                      
+    			     
+   
+
+
+  
+
+ 
+               
+
+
+
+  
+ 
+   
+
+   
+   reg 			     bus_error_f;          
+  
+
+ 
+
+  
+    		       
+
+
+   
+  
+                                         
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+  
+
+
+lm32_icache_full #(
+    .associativity          (associativity),
+    .sets                   (sets),
+    .bytes_per_line         (bytes_per_line),
+    .base_address           (base_address),
+    .limit                  (limit)
+    ) icache ( 
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),      
+    .stall_a                (stall_a),
+    .stall_f                (stall_f),
+    .branch_predict_taken_d (branch_predict_taken_d),
+    .valid_d                (valid_d),
+    .address_a              (pc_a),
+    .address_f              (pc_f),
+    .read_enable_f          (icache_read_enable_f),
+    .refill_ready           (icache_refill_ready),
+    .refill_data            (icache_refill_data),
+    .iflush                 (iflush),
+    
+    .stall_request          (icache_stall_request),
+    .restart_request        (icache_restart_request),
+    .refill_request         (icache_refill_request),
+    .refill_address         (icache_refill_address),
+    .refilling              (icache_refilling),
+    .inst                   (icache_data_f)
+    );
+ 
+
+
+
+
+
+
+  
+
+   
+   assign icache_read_enable_f =    (valid_f ==  1'b1)
+     && (kill_f ==  1'b0)
+   
+
+   && (dcache_restart_request ==  1'b0)
+  
+                         
+    
+				       
+ 
+       
+				    ;
+ 
+ 
+
+
+always @(*)
+begin
+    
+  
+
+    if (dcache_restart_request ==  1'b1)
+        pc_a = restart_address;
+    else 
+ 
+    
+      if (branch_taken_m ==  1'b1)
+	if ((branch_mispredict_taken_m ==  1'b1) && (exception_m ==  1'b0))
+	  pc_a = pc_x;
+	else
+          pc_a = branch_target_m;
+  
+    
+      else if (branch_taken_x ==  1'b1)
+        pc_a = branch_target_x;
+ 
+
+      else
+	if ( (valid_d ==  1'b1) && (branch_predict_taken_d ==  1'b1) )
+	  pc_a = branch_predict_address_d;
+	else
+  
+
+          if (icache_restart_request ==  1'b1)
+            pc_a = restart_address;
+	  else 
+ 
+        
+            pc_a = pc_f + 1'b1;
+end
+
+
+  
+      
+      
+        
+
+
+
+  
+
+     
+    	      
+
+     
+      
+	  
+       
+	  
+	
+	    
+     
+   
+   
+          
+
+
+  
+   
+
+
+                     
+
+  
+
+assign instruction_f = icache_data_f;
+ 
+   
+
+
+
+ 
+ 
+   
+
+  
+
+  
+
+
+assign i_dat_o = 32'd0;
+assign i_we_o =  1'b0;
+assign i_sel_o = 4'b1111;
+ 
+
+assign i_bte_o =  2'b00;
+ 
+
+
+  
+
+
+generate
+    case (bytes_per_line)
+    4:
+    begin
+assign first_cycle_type =  3'b111;
+assign next_cycle_type =  3'b111;
+assign last_word =  1'b1;
+assign first_address = icache_refill_address;
+    end
+    8:
+    begin
+assign first_cycle_type =  3'b010;
+assign next_cycle_type =  3'b111;
+assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 1'b1;
+assign first_address = {icache_refill_address[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
+    end
+    16:
+    begin
+assign first_cycle_type =  3'b010;
+assign next_cycle_type = i_adr_o[addr_offset_msb] == 1'b1 ?  3'b111 :  3'b010;
+assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 2'b11;
+assign first_address = {icache_refill_address[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
+    end
+    endcase
+endgenerate
+ 
+
+                     
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        pc_f <= eba_reset_minus_4[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2];
+        pc_d <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+        pc_x <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+        pc_m <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+        pc_w <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+    end
+    else
+    begin
+        if (stall_f ==  1'b0)
+            pc_f <= pc_a;
+        if (stall_d ==  1'b0)
+            pc_d <= pc_f;
+        if (stall_x ==  1'b0)
+            pc_x <= pc_d;
+        if (stall_m ==  1'b0)
+            pc_m <= pc_x;
+        pc_w <= pc_m;
+    end
+end
+
+  
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        restart_address <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+    else
+    begin
+  
+
+  
+        
+            
+            if (dcache_refill_request ==  1'b1)
+                restart_address <= pc_w;
+            else if ((icache_refill_request ==  1'b1) && (!dcache_refilling) && (!dcache_restart_request))
+                restart_address <= icache_refill_address;
+ 
+               
+                  
+
+
+ 
+         
+               
+                  
+
+
+
+    end
+end
+ 
+
+
+
+  
+   
+
+       
+          
+    
+    
+           
+              
+    
+
+
+
+
+  
+    
+                 
+ 
+
+     
+       
+       
+       
+       
+     
+
+   
+
+
+
+  
+
+   
+   
+                
+   always @(posedge clk_i  )
+     begin
+	if (rst_i ==  1'b1)
+	  begin
+             i_cyc_o <=  1'b0;
+             i_stb_o <=  1'b0;
+             i_adr_o <= { 32{1'b0}};
+             i_cti_o <=  3'b111;
+             i_lock_o <=  1'b0;
+             icache_refill_data <= { 32{1'b0}};
+             icache_refill_ready <=  1'b0;
+    
+
+             bus_error_f <=  1'b0;
+   
+
+    
+               
+               
+               
+  
+
+	  end
+	else
+	  begin   
+             icache_refill_ready <=  1'b0;
+             
+             if (i_cyc_o ==  1'b1)
+               begin
+		  
+		  if ((i_ack_i ==  1'b1) || (i_err_i ==  1'b1))
+		    begin
+    
+                          
+			 
+			      
+			             
+			        
+			          
+			 
+                       
+  
+
+			 begin
+			    if (last_word ==  1'b1)
+			      begin
+				 
+				 i_cyc_o <=  1'b0;
+				 i_stb_o <=  1'b0;
+				 i_lock_o <=  1'b0;
+			      end
+			    
+			    i_adr_o[addr_offset_msb:addr_offset_lsb] <= i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
+			    i_cti_o <= next_cycle_type;
+			    
+			    icache_refill_ready <=  1'b1;
+			    icache_refill_data <= i_dat_i;
+			 end
+		    end
+    
+
+		    
+
+		  if (i_err_i ==  1'b1)
+		    begin
+                       bus_error_f <=  1'b1;
+                       $display ("Instruction bus error. Address: %x", i_adr_o);
+		    end
+		   
+
+   
+
+               end
+             else
+               begin
+		  if ((icache_refill_request ==  1'b1) && (icache_refill_ready ==  1'b0))
+		    begin
+                       
+         
+                         
+  
+
+                       i_adr_o <= {first_address, 2'b00};
+                       i_cyc_o <=  1'b1;
+                       i_stb_o <=  1'b1;                
+                       i_cti_o <= first_cycle_type;
+                       
+    
+
+                       bus_error_f <=  1'b0;
+   
+
+		    end
+    
+		  
+		    
+                              
+			 
+			     
+			         
+			         
+			         
+			         
+			    
+			      
+			      
+			      
+			      
+			      
+			      
+			      
+			 
+		     
+  
+                    
+    
+
+		  
+		  
+     
+    
+		  if (branch_taken_x ==  1'b1)
+                    bus_error_f <=  1'b0;
+    
+
+		  if (branch_taken_m ==  1'b1)
+                    bus_error_f <=  1'b0;
+   
+
+               end
+	  end
+     end
+  
+      
+     
+	   
+	  
+               
+               
+               
+               
+               
+               
+   
+               
+  
+	  
+	
+	     
+             
+                
+               
+		  
+		        
+		    
+                       
+                         
+                         
+                       
+                         
+		    
+   
+		   
+		     
+		    
+                         
+                         
+		       
+		    
+		  
+  
+               
+             
+               
+		  
+		         
+    
+			    
+         
+			 
+		    
+                       
+        
+                         
+  
+                          
+                         
+                         
+   
+                         
+  
+		    
+		  
+		    
+	                      
+    
+			         
+         
+			      
+			 
+   
+			      
+  
+			 
+		    
+               
+	  
+     
+ 
+
+ 
+ 
+
+   
+   always @(posedge clk_i  )
+     begin
+	if (rst_i ==  1'b1)
+	  begin
+             instruction_d <= { 32{1'b0}};
+  
+
+             bus_error_d <=  1'b0;
+ 
+
+	  end
+	else
+	  begin
+             if (stall_d ==  1'b0)
+               begin
+		  instruction_d <= instruction_f;
+  
+
+		  bus_error_d <= bus_error_f;
+ 
+
+               end
+	  end
+     end  
+   
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+  
+
+                              
+                              
+                              
+
+
+                          
+                  
+                 
+              
+             
+                    
+                        
+                        
+
+
+                  
+         
+          
+          
+          
+          
+          
+      
+      
+         
+
+
+
+
+
+  
+    
+    
+    
+     
+    
+    
+    
+ 
+    
+    
+    
+    
+
+ 
+    
+    
+
+ 
+    
+
+    
+ 
+    
+    
+
+ 
+    
+    
+    
+    
+    
+    
+    
+
+ 
+    
+    
+
+    
+    
+    
+
+
+
+
+
+                                             
+                                             
+
+                                          
+                                       
+                        
+                              
+
+ 
+                                
+                                  
+                    
+                                           
+
+ 
+                    
+                              
+
+ 
+                                     
+
+
+
+
+
+       
+ 
+                
+    
+                
+    
+
+ 
+                            
+    
+              
+    
+                          
+    
+                                 
+    
+                                
+    
+                  
+            
+                     
+    
+
+ 
+                                       
+    
+                                       
+    
+
+  
+     
+  
+    
+             
+
+
+
+
+                           
+                         
+                       
+                     
+
+
+
+     
+  
+
+                  
+        
+                       
+        
+                       
+
+
+               
+ 
+         
+  
+  
+  
+  
+                          
+
+
+         
+
+
+
+
+
+ 
+      
+   
+      
+   
+
+                 
+
+                  
+             
+
+   
+
+ 
+   
+
+   
+
+
+                  
+     
+     
+         
+                 
+
+
+
+
+   
+   
+
+
+
+   
+
+       
+    
+          
+          
+          
+          
+    
+    
+    
+          
+          
+          
+          
+    
+
+
+
+   
+
+       
+    
+          
+          
+          
+ 
+          
+          
+          
+          
+
+ 
+          
+          
+
+                  
+          
+          
+          
+          
+
+    
+    
+    
+                  
+               
+        
+             
+            
+            
+                
+                  
+                  
+            
+            
+            
+                
+                  
+            
+            
+        
+
+ 
+        
+           
+        
+              
+              
+        
+
+         
+        
+        
+            
+                 
+            
+                                  
+                 
+ 
+                
+                
+                     
+ 
+                    
+                          
+                    
+                    
+                              
+                          
+                    
+                    
+                          
+                    
+                    
+                              
+                          
+                    
+                    
+                          
+                    
+                    
+                    
+      
+                              
+                                   
+
+                          
+                    
+                    
+                    
+      
+                              
+                                   
+
+                          
+                    
+                                                   
+                
+
+                  
+                
+                
+                      
+                      
+                                    
+                
+                
+                      
+                      
+                
+
+                
+                    
+                                
+            
+        
+ 
+        
+        
+                 
+            
+                  
+                  
+            
+        
+        
+        
+                 
+            
+                  
+                  
+            
+        
+        
+        
+                 
+            
+                  
+                  
+            
+        
+        
+        
+                 
+            
+                  
+                   
+                      
+                 
+                      
+            
+        
+        
+        
+                 
+            
+                  
+                  
+            
+        
+        
+        
+             
+            
+            
+            
+                  
+                  
+                  
+            
+            
+            
+            
+                  
+                  
+                  
+            
+            
+            
+                  
+                  
+                  
+            
+            
+        
+        
+        
+               
+                      
+                  
+                  
+                    
+                  
+                  
+            
+            
+        
+        
+              
+              
+              
+            
+
+        
+    
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_interrupt_full (
+    
+    clk_i, 
+    rst_i,
+    
+    interrupt,
+    
+    stall_x,
+  
+    
+    
+
+
+    exception,
+ 
+
+    eret_q_x,
+  
+    
+
+
+    csr,
+    csr_write_data,
+    csr_write_enable,
+    
+    interrupt_exception,
+    
+    csr_read_data
+    );
+
+
+
+
+
+parameter interrupts =  32;         
+
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+
+input [interrupts-1:0] interrupt;               
+
+input stall_x;                                  
+
+  
+                       
+                           
+
+
+input exception;                                
+ 
+
+input eret_q_x;                                 
+  
+                                  
+
+
+
+input [ (4 -1):0] csr;                      
+input [ (32-1):0] csr_write_data;          
+input csr_write_enable;                         
+
+
+
+
+
+output interrupt_exception;                     
+wire   interrupt_exception;
+
+output [ (32-1):0] csr_read_data;          
+reg    [ (32-1):0] csr_read_data;
+
+
+
+
+
+wire [interrupts-1:0] asserted;                 
+
+wire [interrupts-1:0] interrupt_n_exception;
+
+
+
+reg ie;                                         
+reg eie;                                        
+  
+                                         
+
+
+reg [interrupts-1:0] ip;                        
+reg [interrupts-1:0] im;                        
+
+
+
+
+
+
+assign interrupt_n_exception = ip & im;
+
+
+assign interrupt_exception = (|interrupt_n_exception) & ie;
+
+
+assign asserted = ip | interrupt;
+       
+generate
+    if (interrupts > 1) 
+    begin
+
+always @(*)
+begin
+    case (csr)
+     4 'h0:  csr_read_data = {{ 32-3{1'b0}}, 
+  
+                                    
+
+
+                                    1'b0,                                     
+ 
+
+                                    eie, 
+                                    ie
+                                   };
+     4 'h2:  csr_read_data = ip;
+     4 'h1:  csr_read_data = im;
+    default:       csr_read_data = { 32{1'bx}};
+    endcase
+end
+    end
+    else
+    begin
+
+always @(*)
+begin
+    case (csr)
+     4 'h0:  csr_read_data = {{ 32-3{1'b0}}, 
+  
+                                     
+
+
+                                    1'b0,                                    
+ 
+
+                                    eie, 
+                                    ie
+                                   };
+     4 'h2:  csr_read_data = ip;
+    default:       csr_read_data = { 32{1'bx}};
+      endcase
+end
+    end
+endgenerate
+    
+
+
+
+
+  
+
+   reg [ 10:0] eie_delay  = 0;
+
+   
+generate
+
+   
+    if (interrupts > 1)
+    begin
+
+always @(posedge clk_i  )
+  begin
+    if (rst_i ==  1'b1)
+    begin
+        ie                   <=  1'b0;
+        eie                  <=  1'b0;
+  
+                           
+
+
+        im                   <= {interrupts{1'b0}};
+        ip                   <= {interrupts{1'b0}};
+       eie_delay             <= 0;
+       
+    end
+    else
+    begin
+        
+        ip                   <= asserted;
+  
+           
+        
+            
+                           
+                            
+        
+            
+        
+            
+                           
+                            
+        
+
+
+        if (exception ==  1'b1)
+        begin
+            
+            eie              <= ie;
+            ie               <=  1'b0;
+        end
+ 
+
+        else if (stall_x ==  1'b0)
+        begin
+
+           if(eie_delay[0])
+             ie              <= eie;
+           
+           eie_delay         <= {1'b0, eie_delay[ 10:1]};
+
+            if (eret_q_x ==  1'b1) begin
+                
+               eie_delay[ 10] <=  1'b1;
+               eie_delay[ 10-1:0] <= 0;
+            end
+           
+                      
+           
+  
+                
+                
+                       
+
+
+            else if (csr_write_enable ==  1'b1)
+            begin
+                
+                if (csr ==  4 'h0)
+                begin
+                    ie  <= csr_write_data[0];
+                    eie <= csr_write_data[1];
+  
+                      
+
+
+                end
+                if (csr ==  4 'h1)
+                    im  <= csr_write_data[interrupts-1:0];
+                if (csr ==  4 'h2)
+                    ip  <= asserted & ~csr_write_data[interrupts-1:0];
+            end
+        end
+    end
+end
+    end
+else
+    begin
+
+always @(posedge clk_i  )
+  begin
+    if (rst_i ==  1'b1)
+    begin
+        ie              <=  1'b0;
+        eie             <=  1'b0;
+  
+                      
+
+
+        ip              <= {interrupts{1'b0}};
+       eie_delay        <= 0;
+    end
+    else
+    begin
+        
+        ip              <= asserted;
+  
+           
+        
+            
+                      
+                       
+        
+            
+        
+            
+                      
+                       
+        
+
+
+        if (exception ==  1'b1)
+        begin
+            
+            eie         <= ie;
+            ie          <=  1'b0;
+        end
+ 
+
+        else if (stall_x ==  1'b0)
+          begin
+
+             if(eie_delay[0])
+               ie              <= eie;
+           
+             eie_delay         <= {1'b0, eie_delay[ 10:1]};
+
+             if (eret_q_x ==  1'b1) begin
+                
+                eie_delay[ 10] <=  1'b1;
+                eie_delay[ 10-1:0] <= 0;
+             end
+           
+  
+                
+                
+                       
+
+
+            else if (csr_write_enable ==  1'b1)
+            begin
+                
+                if (csr ==  4 'h0)
+                begin
+                    ie  <= csr_write_data[0];
+                    eie <= csr_write_data[1];
+  
+                      
+
+
+                end
+                if (csr ==  4 'h2)
+                    ip  <= asserted & ~csr_write_data[interrupts-1:0];
+            end
+        end
+    end
+end
+    end
+endgenerate
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	 
+
+ 
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+  
+
+
+
+
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+ 
+
+
+
+  
+
+  
+
+ 
+
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+ 
+ 
+                    
+
+  
+                    
+
+
+
+  
+
+
+
+  
+
+  
+
+
+
+  
+
+  
+
+
+
+  
+
+  
+
+
+
+  
+ 
+
+
+  
+
+  
+
+ 
+
+ 
+
+
+
+  
+
+  
+
+ 
+ 
+ 
+
+
+
+
+
+
+  
+
+  
+
+  
+ 
+ 
+
+ 
+
+
+ 
+
+
+  
+
+  
+
+ 
+ 
+ 
+
+
+
+
+
+  
+
+  
+
+ 
+
+  
+ 
+
+
+  
+ 
+
+
+
+
+  
+
+  
+
+ 
+
+  
+ 
+
+
+
+
+  
+
+
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+ 
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+ 
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+ 
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+ 
+ 
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+  
+
+  
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+
+  
+
+  
+
+
+
+  
+
+  
+
+ 
+ 
+ 
+
+
+
+
+
+
+
+
+
+  
+
+  
+
+  
+
+
+
+
+
+
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+
+
+  
+
+
+
+
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+ 
+
+
+
+
+
+
+
+
+module lm32_top_full_debug (
+    
+    clk_i,
+    rst_i,
+    
+
+    interrupt,
+
+    
+  
+    
+    
+
+     
+  
+
+    
+    I_DAT_I,
+    I_ACK_I,
+    I_ERR_I,
+    I_RTY_I,
+ 
+
+    
+    D_DAT_I,
+    D_ACK_I,
+    D_ERR_I,
+    D_RTY_I,
+    
+      
+    
+    
+    
+    
+
+    
+  
+
+    
+    I_DAT_O,
+    I_ADR_O,
+    I_CYC_O,
+    I_SEL_O,
+    I_STB_O,
+    I_WE_O,
+    I_CTI_O,
+    I_LOCK_O,
+    I_BTE_O,
+ 
+
+    
+    D_DAT_O,
+    D_ADR_O,
+    D_CYC_O,
+    D_SEL_O,
+    D_STB_O,
+    D_WE_O,
+    D_CTI_O,
+    D_LOCK_O,
+    D_BTE_O
+    );
+
+parameter eba_reset = 32'h00000000;
+parameter sdb_address = 32'h00000000;
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+
+
+input [ (32-1):0] interrupt;          
+
+
+  
+               
+                             
+
+    
+
+  
+
+input [ (32-1):0] I_DAT_I;                 
+input I_ACK_I;                                  
+input I_ERR_I;                                  
+input I_RTY_I;                                  
+ 
+
+
+input [ (32-1):0] D_DAT_I;                 
+input D_ACK_I;                                  
+input D_ERR_I;                                  
+input D_RTY_I;                                  
+
+
+
+
+
+  
+                               
+   
+       
+     
+           
+    
+           
+    
+
+
+
+  
+
+output [ (32-1):0] I_DAT_O;                
+wire   [ (32-1):0] I_DAT_O;
+output [ (32-1):0] I_ADR_O;                
+wire   [ (32-1):0] I_ADR_O;
+output I_CYC_O;                                 
+wire   I_CYC_O;
+output [ (4-1):0] I_SEL_O;         
+wire   [ (4-1):0] I_SEL_O;
+output I_STB_O;                                 
+wire   I_STB_O;
+output I_WE_O;                                  
+wire   I_WE_O;
+output [ (3-1):0] I_CTI_O;               
+wire   [ (3-1):0] I_CTI_O;
+output I_LOCK_O;                                
+wire   I_LOCK_O;
+output [ (2-1):0] I_BTE_O;               
+wire   [ (2-1):0] I_BTE_O;
+ 
+
+
+output [ (32-1):0] D_DAT_O;                
+wire   [ (32-1):0] D_DAT_O;
+output [ (32-1):0] D_ADR_O;                
+wire   [ (32-1):0] D_ADR_O;
+output D_CYC_O;                                 
+wire   D_CYC_O;
+output [ (4-1):0] D_SEL_O;         
+wire   [ (4-1):0] D_SEL_O;
+output D_STB_O;                                 
+wire   D_STB_O;
+output D_WE_O;                                  
+wire   D_WE_O;
+output [ (3-1):0] D_CTI_O;               
+wire   [ (3-1):0] D_CTI_O;
+output D_LOCK_O;                                
+wire   D_LOCK_O;
+output [ (2-1):0] D_BTE_O;               
+wire   [ (2-1):0] D_BTE_O;
+  
+
+
+
+ 
+  
+
+
+wire [ 7:0] jtag_reg_d;
+wire [ 7:0] jtag_reg_q;
+wire jtag_update;
+wire [2:0] jtag_reg_addr_d;
+wire [2:0] jtag_reg_addr_q;
+wire jtck;
+wire jrstn;
+ 
+
+
+
+  
+
+                     
+                             
+                            
+                   
+                                 
+ 
+                                 
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+   
+
+lm32_cpu_full_debug 
+	#(
+		.eba_reset(eba_reset),
+    .sdb_address(sdb_address)
+	) cpu (
+    
+    .clk_i                 (clk_i),
+  
+                   
+
+
+    .rst_i                 (rst_i),
+    
+  
+
+    .interrupt             (interrupt),
+ 
+
+    
+  
+               
+             
+
+     
+  
+
+    
+    .jtag_clk              (jtck),
+    .jtag_update           (jtag_update),
+    .jtag_reg_q            (jtag_reg_q),
+    .jtag_reg_addr_q       (jtag_reg_addr_q),
+ 
+
+  
+
+     
+    .I_DAT_I               (I_DAT_I),
+    .I_ACK_I               (I_ACK_I),
+    .I_ERR_I               (I_ERR_I),
+    .I_RTY_I               (I_RTY_I),
+ 
+
+    
+    .D_DAT_I               (D_DAT_I),
+    .D_ACK_I               (D_ACK_I),
+    .D_ERR_I               (D_ERR_I),
+    .D_RTY_I               (D_RTY_I),
+    
+  
+                  
+            
+           
+                 
+                
+ 
+                
+
+
+
+  
+
+    .jtag_reg_d            (jtag_reg_d),
+    .jtag_reg_addr_d       (jtag_reg_addr_d),
+ 
+
+      
+                
+               
+            
+            
+
+    
+  
+
+    
+    .I_DAT_O               (I_DAT_O),
+    .I_ADR_O               (I_ADR_O),
+    .I_CYC_O               (I_CYC_O),
+    .I_SEL_O               (I_SEL_O),
+    .I_STB_O               (I_STB_O),
+    .I_WE_O                (I_WE_O),
+    .I_CTI_O               (I_CTI_O),
+    .I_LOCK_O              (I_LOCK_O),
+    .I_BTE_O               (I_BTE_O),
+     
+
+    
+    .D_DAT_O               (D_DAT_O),
+    .D_ADR_O               (D_ADR_O),
+    .D_CYC_O               (D_CYC_O),
+    .D_SEL_O               (D_SEL_O),
+    .D_STB_O               (D_STB_O),
+    .D_WE_O                (D_WE_O),
+    .D_CTI_O               (D_CTI_O),
+    .D_LOCK_O              (D_LOCK_O),
+    .D_BTE_O               (D_BTE_O)
+    );
+   
+  
+		   
+
+jtag_cores jtag_cores (
+    
+    .reg_d                 (jtag_reg_d),
+    .reg_addr_d            (jtag_reg_addr_d),
+    
+    .reg_update            (jtag_update),
+    .reg_q                 (jtag_reg_q),
+    .reg_addr_q            (jtag_reg_addr_q),
+    .jtck                  (jtck),
+    .jrstn                 (jrstn)
+    );
+ 
+        
+   
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+           
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_mc_arithmetic_full_debug (
+    
+    clk_i,
+    rst_i,
+    stall_d,
+    kill_x,
+  
+
+    divide_d,
+    modulus_d,
+ 
+
+  
+    
+
+
+  
+    
+    
+    
+
+
+    operand_0_d,
+    operand_1_d,
+    
+    result_x,
+  
+
+    divide_by_zero_x,
+ 
+
+    stall_request_x
+    );
+
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+input stall_d;                                  
+input kill_x;                                   
+  
+
+input divide_d;                                 
+input modulus_d;                                
+ 
+
+  
+                                
+
+
+  
+                              
+                             
+                             
+
+
+input [ (32-1):0] operand_0_d;
+input [ (32-1):0] operand_1_d;
+
+
+
+
+
+output [ (32-1):0] result_x;               
+reg    [ (32-1):0] result_x;
+  
+
+output divide_by_zero_x;                        
+reg    divide_by_zero_x;
+ 
+
+output stall_request_x;                         
+wire   stall_request_x;
+
+
+
+
+
+reg [ (32-1):0] p;                         
+reg [ (32-1):0] a;
+reg [ (32-1):0] b;
+  
+
+wire [32:0] t;
+ 
+
+
+reg [ 2:0] state;                 
+reg [5:0] cycles;                               
+
+  
+                               
+                                 
+
+
+
+
+
+
+
+
+assign stall_request_x = state !=  3'b000;
+
+  
+
+
+assign t = {p[ 32-2:0], a[ 32-1]} - b;
+ 
+
+
+  
+
+       
+
+
+
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        cycles <= {6{1'b0}};
+        p <= { 32{1'b0}};
+        a <= { 32{1'b0}};
+        b <= { 32{1'b0}};
+  
+          
+
+
+  
+
+        divide_by_zero_x <=  1'b0;
+ 
+
+        result_x <= { 32{1'b0}};
+        state <=  3'b000;
+    end
+    else
+    begin
+  
+
+        divide_by_zero_x <=  1'b0;
+ 
+
+        case (state)
+         3'b000:
+        begin
+            if (stall_d ==  1'b0)                 
+            begin          
+                cycles <=  32;
+                p <= 32'b0;
+                a <= operand_0_d;
+                b <= operand_1_d;                    
+  
+
+                if (divide_d ==  1'b1)
+                    state <=  3'b011 ;
+                if (modulus_d ==  1'b1)
+                    state <=  3'b010   ;
+ 
+                    
+  
+                   
+                      
+
+
+  
+                   
+                
+                      
+                      
+                      
+                      
+                      
+                
+                   
+                
+                      
+                      
+                      
+                      
+                      
+                
+
+
+            end            
+        end
+  
+
+         3'b011 :
+        begin
+            if (t[32] == 1'b0)
+            begin
+                p <= t[31:0];
+                a <= {a[ 32-2:0], 1'b1};
+            end
+            else 
+            begin
+                p <= {p[ 32-2:0], a[ 32-1]};
+                a <= {a[ 32-2:0], 1'b0};
+            end
+            result_x <= a;
+            if ((cycles ==  32'd0) || (kill_x ==  1'b1))
+            begin
+                
+                divide_by_zero_x <= b == { 32{1'b0}};
+                state <=  3'b000;
+            end
+            cycles <= cycles - 1'b1;
+        end
+         3'b010   :
+        begin
+            if (t[32] == 1'b0)
+            begin
+                p <= t[31:0];
+                a <= {a[ 32-2:0], 1'b1};
+            end
+            else 
+            begin
+                p <= {p[ 32-2:0], a[ 32-1]};
+                a <= {a[ 32-2:0], 1'b0};
+            end
+            result_x <= p;
+            if ((cycles ==  32'd0) || (kill_x ==  1'b1))
+            begin
+                
+                divide_by_zero_x <= b == { 32{1'b0}};
+                state <=  3'b000;
+            end
+            cycles <= cycles - 1'b1;
+        end
+ 
+        
+  
+        
+        
+               
+                    
+               
+               
+              
+                   
+                  
+                
+        
+
+     
+  
+        
+               
+               
+              
+                   
+                  
+                
+        
+        
+               
+               
+              
+                   
+                  
+                
+        
+
+   
+        endcase
+    end
+end 
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_cpu_full_debug (
+    
+    clk_i,
+  
+    
+
+
+    rst_i,
+  
+    
+
+
+  
+   
+   
+   
+   
+   
+   
+
+
+
+    
+  
+
+    interrupt,
+ 
+
+    
+  
+    
+    
+
+     
+  
+
+    
+    jtag_clk,
+    jtag_update, 
+    jtag_reg_q,
+    jtag_reg_addr_q,
+ 
+
+  
+
+    
+    I_DAT_I,
+    I_ACK_I,
+    I_ERR_I,
+    I_RTY_I,
+ 
+
+    
+    D_DAT_I,
+    D_ACK_I,
+    D_ERR_I,
+    D_RTY_I,
+    
+  
+    
+    
+    
+    
+    
+ 
+    
+
+
+
+  
+
+    jtag_reg_d,
+    jtag_reg_addr_d,
+ 
+
+      
+    
+    
+    
+    
+
+    
+  
+
+    
+    I_DAT_O,
+    I_ADR_O,
+    I_CYC_O,
+    I_SEL_O,
+    I_STB_O,
+    I_WE_O,
+    I_CTI_O,
+    I_LOCK_O,
+    I_BTE_O,
+ 
+ 
+  
+    
+    
+    
+    
+    
+    
+    
+    
+           
+
+
+		 
+		 
+    
+    D_DAT_O,
+    D_ADR_O,
+    D_CYC_O,
+    D_SEL_O,
+    D_STB_O,
+    D_WE_O,
+    D_CTI_O,
+    D_LOCK_O,
+    D_BTE_O
+
+		 
+    );
+
+
+
+
+
+parameter eba_reset =  32'h00000000;                           
+  
+
+parameter deba_reset =  32'h10000000;                         
+ 
+
+parameter sdb_address =   32'h00000000;
+
+  
+
+parameter icache_associativity =  1;     
+parameter icache_sets =  256;                       
+parameter icache_bytes_per_line =  16;   
+parameter icache_base_address =  32'h0;       
+parameter icache_limit =  32'h7fffffff;                     
+ 
+       
+                         
+     
+         
+                       
+
+
+
+  
+
+parameter dcache_associativity =  1;     
+parameter dcache_sets =  256;                       
+parameter dcache_bytes_per_line =  16;   
+parameter dcache_base_address =  32'h0;       
+parameter dcache_limit =  32'h7fffffff;                     
+ 
+       
+                         
+     
+         
+                       
+
+
+
+  
+
+parameter watchpoints =  32'h4;                       
+ 
+   
+
+
+  
+                          
+
+
+parameter breakpoints = 0;
+ 
+
+
+  
+
+parameter interrupts =  32;                         
+ 
+   
+
+
+
+
+
+
+
+input clk_i;                                    
+  
+                                   
+
+    
+input rst_i;                                    
+
+  
+
+input [ (32-1):0] interrupt;          
+ 
+
+
+  
+               
+                             
+
+    
+
+  
+ 
+input jtag_clk;                                 
+input jtag_update;                              
+input [ 7:0] jtag_reg_q;              
+input [2:0] jtag_reg_addr_q;
+ 
+
+
+  
+
+input [ (32-1):0] I_DAT_I;                 
+input I_ACK_I;                                  
+input I_ERR_I;                                  
+input I_RTY_I;                                  
+ 
+
+
+input [ (32-1):0] D_DAT_I;                 
+input D_ACK_I;                                  
+input D_ERR_I;                                  
+input D_RTY_I;                                  
+
+
+
+
+
+  
+    
+     
+
+
+   
+   
+  
+                   
+     
+                           
+    
+                          
+    
+                 
+     
+                               
+    
+ 
+                               
+    
+
+
+
+
+  
+
+output [ 7:0] jtag_reg_d;
+wire   [ 7:0] jtag_reg_d;
+output [2:0] jtag_reg_addr_d;
+wire   [2:0] jtag_reg_addr_d;
+ 
+
+
+  
+                               
+   
+       
+     
+           
+    
+           
+    
+
+
+
+  
+
+output [ (32-1):0] I_DAT_O;                
+wire   [ (32-1):0] I_DAT_O;
+output [ (32-1):0] I_ADR_O;                
+wire   [ (32-1):0] I_ADR_O;
+output I_CYC_O;                                 
+wire   I_CYC_O;
+output [ (4-1):0] I_SEL_O;         
+wire   [ (4-1):0] I_SEL_O;
+output I_STB_O;                                 
+wire   I_STB_O;
+output I_WE_O;                                  
+wire   I_WE_O;
+output [ (3-1):0] I_CTI_O;               
+wire   [ (3-1):0] I_CTI_O;
+output I_LOCK_O;                                
+wire   I_LOCK_O;
+output [ (2-1):0] I_BTE_O;               
+wire   [ (2-1):0] I_BTE_O;
+ 
+
+
+output [ (32-1):0] D_DAT_O;                
+wire   [ (32-1):0] D_DAT_O;
+output [ (32-1):0] D_ADR_O;                
+wire   [ (32-1):0] D_ADR_O;
+output D_CYC_O;                                 
+wire   D_CYC_O;
+output [ (4-1):0] D_SEL_O;         
+wire   [ (4-1):0] D_SEL_O;
+output D_STB_O;                                 
+wire   D_STB_O;
+output D_WE_O;                                  
+wire   D_WE_O;
+output [ (3-1):0] D_CTI_O;               
+wire   [ (3-1):0] D_CTI_O;
+output D_LOCK_O;                                
+wire   D_LOCK_O;
+output [ (2-1):0] D_BTE_O;               
+wire   [ (2-1):0] D_BTE_O;
+
+  
+      
+     
+       
+      
+             
+
+
+   
+
+
+
+
+
+
+  
+
+reg valid_a;                                    
+ 
+
+reg valid_f;                                    
+reg valid_d;                                    
+reg valid_x;                                    
+reg valid_m;                                    
+reg valid_w;                                    
+   
+wire q_x;
+wire [ (32-1):0] immediate_d;              
+wire load_d;                                    
+reg load_x;                                     
+reg load_m;
+wire load_q_x;
+wire store_q_x;
+wire q_m;
+wire load_q_m;
+wire store_q_m;
+wire store_d;                                   
+reg store_x;
+reg store_m;
+wire [ 1:0] size_d;                   
+reg [ 1:0] size_x;
+wire branch_d;                                  
+wire branch_predict_d;                          
+wire branch_predict_taken_d;                    
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d;   
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_d;
+wire bi_unconditional;
+wire bi_conditional;
+reg branch_x;                                   
+reg branch_predict_x;
+reg branch_predict_taken_x;
+reg branch_m;
+reg branch_predict_m;
+reg branch_predict_taken_m;
+wire branch_mispredict_taken_m;                 
+wire branch_flushX_m;                           
+wire branch_reg_d;                              
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset_d;            
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_x;             
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_m;
+wire [ 0:0] d_result_sel_0_d; 
+wire [ 1:0] d_result_sel_1_d; 
+
+wire x_result_sel_csr_d;                        
+reg x_result_sel_csr_x;
+  
+
+wire q_d;
+wire x_result_sel_mc_arith_d;                   
+reg x_result_sel_mc_arith_x;
+ 
+
+      
+                       
+ 
+
+
+  
+
+wire x_result_sel_sext_d;                       
+reg x_result_sel_sext_x;
+ 
+
+wire x_result_sel_logic_d;                      
+  
+                        
+ 
+
+
+wire x_result_sel_add_d;                        
+reg x_result_sel_add_x;
+wire m_result_sel_compare_d;                    
+reg m_result_sel_compare_x;
+reg m_result_sel_compare_m;
+  
+
+wire m_result_sel_shift_d;                      
+reg m_result_sel_shift_x;
+reg m_result_sel_shift_m;
+ 
+
+wire w_result_sel_load_d;                       
+reg w_result_sel_load_x;
+reg w_result_sel_load_m;
+reg w_result_sel_load_w;
+  
+
+wire w_result_sel_mul_d;                        
+reg w_result_sel_mul_x;
+reg w_result_sel_mul_m;
+reg w_result_sel_mul_w;
+ 
+
+wire x_bypass_enable_d;                         
+reg x_bypass_enable_x;                          
+wire m_bypass_enable_d;                         
+reg m_bypass_enable_x;                          
+reg m_bypass_enable_m;
+wire sign_extend_d;                             
+reg sign_extend_x;
+wire write_enable_d;                            
+reg write_enable_x;
+wire write_enable_q_x;
+reg write_enable_m;
+wire write_enable_q_m;
+reg write_enable_w;
+wire write_enable_q_w;
+wire read_enable_0_d;                           
+wire [ (5-1):0] read_idx_0_d;          
+wire read_enable_1_d;                           
+wire [ (5-1):0] read_idx_1_d;          
+wire [ (5-1):0] write_idx_d;           
+reg [ (5-1):0] write_idx_x;            
+reg [ (5-1):0] write_idx_m;
+reg [ (5-1):0] write_idx_w;
+wire [ (5-1):0] csr_d;                     
+reg  [ (5-1):0] csr_x;                  
+wire [ (3-1):0] condition_d;         
+reg [ (3-1):0] condition_x;          
+  
+
+wire break_d;                                   
+reg break_x;                                    
+ 
+
+wire scall_d;                                   
+reg scall_x;    
+wire eret_d;                                    
+reg eret_x;
+wire eret_q_x;
+  
+ 
+ 
+
+
+  
+
+wire bret_d;                                    
+reg bret_x;
+wire bret_q_x;
+  
+ 
+ 
+
+
+ 
+
+wire csr_write_enable_d;                        
+reg csr_write_enable_x;
+wire csr_write_enable_q_x;
+  
+       
+
+
+
+  
+
+wire bus_error_d;                               
+reg bus_error_x;
+reg data_bus_error_exception_m;
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] memop_pc_w;
+ 
+
+
+reg [ (32-1):0] d_result_0;                
+reg [ (32-1):0] d_result_1;                
+reg [ (32-1):0] x_result;                  
+reg [ (32-1):0] m_result;                  
+reg [ (32-1):0] w_result;                  
+
+reg [ (32-1):0] operand_0_x;               
+reg [ (32-1):0] operand_1_x;               
+reg [ (32-1):0] store_operand_x;           
+reg [ (32-1):0] operand_m;                 
+reg [ (32-1):0] operand_w;                 
+
+
+  
+
+reg [ (32-1):0] reg_data_live_0;          
+reg [ (32-1):0] reg_data_live_1;  
+reg use_buf;                                    
+reg [ (32-1):0] reg_data_buf_0;
+reg [ (32-1):0] reg_data_buf_1;
+ 
+
+  
+
+ 
+     
+
+
+wire [ (32-1):0] reg_data_0;               
+wire [ (32-1):0] reg_data_1;               
+reg [ (32-1):0] bypass_data_0;             
+reg [ (32-1):0] bypass_data_1;             
+wire reg_write_enable_q_w;
+
+reg interlock;                                  
+
+wire stall_a;                                   
+wire stall_f;                                   
+wire stall_d;                                   
+wire stall_x;                                   
+wire stall_m;                                   
+
+
+wire adder_op_d;                                
+reg adder_op_x;                                 
+reg adder_op_x_n;                               
+wire [ (32-1):0] adder_result_x;           
+wire adder_overflow_x;                          
+wire adder_carry_n_x;                           
+
+
+wire [ 3:0] logic_op_d;           
+reg [ 3:0] logic_op_x;            
+wire [ (32-1):0] logic_result_x;           
+
+  
+
+
+wire [ (32-1):0] sextb_result_x;           
+wire [ (32-1):0] sexth_result_x;           
+wire [ (32-1):0] sext_result_x;            
+ 
+
+
+
+  
+
+  
+                                   
+                                     
+
+
+wire direction_d;                               
+reg direction_x;                                        
+wire [ (32-1):0] shifter_result_m;         
+ 
+
+  
+                               
+ 
+                              
+ 
+
+
+  
+           
+
+
+
+
+  
+
+wire [ (32-1):0] multiplier_result_w;      
+ 
+
+  
+                                 
+ 
+
+
+
+
+  
+
+wire divide_d;                                  
+wire divide_q_d;
+wire modulus_d;
+wire modulus_q_d;
+wire divide_by_zero_x;                          
+ 
+
+
+
+  
+
+wire mc_stall_request_x;                        
+wire [ (32-1):0] mc_result_x;
+ 
+
+
+
+  
+
+wire [ (32-1):0] interrupt_csr_read_data_x;
+ 
+
+wire [ (32-1):0] cfg;                      
+wire [ (32-1):0] cfg2;                     
+  
+                          
+
+
+reg [ (32-1):0] csr_read_data_x;           
+
+
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;                       
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;                       
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;                       
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;                       
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;                       
+  
+                          
+
+
+  
+
+wire [ (32-1):0] instruction_f;     
+ 
+
+
+
+wire [ (32-1):0] instruction_d;     
+  
+
+wire iflush;                                    
+wire icache_stall_request;                      
+wire icache_restart_request;                    
+wire icache_refill_request;                     
+wire icache_refilling;                          
+ 
+
+
+
+  
+
+wire dflush_x;                                  
+reg dflush_m;                                    
+wire dcache_stall_request;                      
+wire dcache_restart_request;                    
+wire dcache_refill_request;                     
+wire dcache_refilling;                          
+ 
+
+wire [ (32-1):0] load_data_w;              
+wire stall_wb_load;                             
+
+
+  
+
+  
+
+wire [ (32-1):0] jtx_csr_read_data;        
+wire [ (32-1):0] jrx_csr_read_data;        
+ 
+
+  
+
+wire jtag_csr_write_enable;                     
+wire [ (32-1):0] jtag_csr_write_data;      
+wire [ (5-1):0] jtag_csr;                  
+wire jtag_read_enable;                          
+wire [ 7:0] jtag_read_data;
+wire jtag_write_enable;
+wire [ 7:0] jtag_write_data;
+wire [ (32-1):0] jtag_address;
+wire jtag_access_complete;
+ 
+
+  
+
+wire jtag_break;                                
+ 
+
+ 
+
+
+
+wire raw_x_0;                                   
+wire raw_x_1;                                   
+wire raw_m_0;                                   
+wire raw_m_1;                                   
+wire raw_w_0;                                   
+wire raw_w_1;                                   
+
+
+wire cmp_zero;                                  
+wire cmp_negative;                              
+wire cmp_overflow;                              
+wire cmp_carry_n;                               
+reg condition_met_x;                            
+reg condition_met_m;
+  
+    
+wire branch_taken_x;                            
+ 
+
+wire branch_taken_m;                            
+
+wire kill_f;                                    
+wire kill_d;                                    
+wire kill_x;                                    
+wire kill_m;                                    
+wire kill_w;                                    
+
+reg [ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8] eba;                 
+  
+
+reg [ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8] deba;                
+ 
+
+reg [ (3-1):0] eid_x;                      
+  
+                        
+                        
+
+
+
+  
+
+  
+
+wire dc_ss;                                     
+ 
+
+wire dc_re;                                     
+wire bp_match;
+wire wp_match;
+wire exception_x;                               
+reg exception_m;                                
+wire debug_exception_x;                         
+reg debug_exception_m;
+reg debug_exception_w;
+wire debug_exception_q_w;
+wire non_debug_exception_x;                     
+reg non_debug_exception_m;
+reg non_debug_exception_w;
+wire non_debug_exception_q_w;
+ 
+                                
+ 
+ 
+ 
+
+
+
+  
+
+  
+ 
+wire reset_exception;                           
+ 
+
+  
+                            
+
+
+ 
+
+  
+
+wire interrupt_exception;                       
+ 
+
+  
+
+wire breakpoint_exception;                      
+wire watchpoint_exception;                      
+ 
+
+  
+
+   reg [ (32-1):0] data_bus_error_addr;
+   
+wire instruction_bus_error_exception;           
+wire data_bus_error_exception;                  
+ 
+
+  
+
+wire divide_by_zero_exception;                  
+ 
+
+wire system_call_exception;                     
+
+  
+
+reg data_bus_error_seen;                        
+ 
+
+
+   
+    
+
+
+     
+  
+                          
+   
+            
+   
+                          
+   
+
+    	      
+    	      
+    	      
+    	      
+    	      
+    	      
+   
+   
+
+
+   
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+lm32_instruction_unit_full_debug #(
+    .eba_reset              (eba_reset),
+    .associativity          (icache_associativity),
+    .sets                   (icache_sets),
+    .bytes_per_line         (icache_bytes_per_line),
+    .base_address           (icache_base_address),
+    .limit                  (icache_limit)
+  ) instruction_unit (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    
+    .stall_a                (stall_a),
+    .stall_f                (stall_f),
+    .stall_d                (stall_d),
+    .stall_x                (stall_x),
+    .stall_m                (stall_m),
+    .valid_f                (valid_f),
+    .valid_d                (valid_d),
+    .kill_f                 (kill_f),
+    .branch_predict_taken_d (branch_predict_taken_d),
+    .branch_predict_address_d (branch_predict_address_d),
+  
+    
+    .branch_taken_x         (branch_taken_x),
+    .branch_target_x        (branch_target_x),
+ 
+
+    .exception_m            (exception_m),
+    .branch_taken_m         (branch_taken_m),
+    .branch_mispredict_taken_m (branch_mispredict_taken_m),
+    .branch_target_m        (branch_target_m),
+  
+
+    .iflush                 (iflush),
+ 
+
+  
+
+    .dcache_restart_request (dcache_restart_request),
+    .dcache_refill_request  (dcache_refill_request),
+    .dcache_refilling       (dcache_refilling),
+ 
+        
+  
+
+    
+    .i_dat_i                (I_DAT_I),
+    .i_ack_i                (I_ACK_I),
+    .i_err_i                (I_ERR_I),
+    .i_rty_i                (I_RTY_I),
+ 
+
+  
+
+    .jtag_read_enable       (jtag_read_enable),
+    .jtag_write_enable      (jtag_write_enable),
+    .jtag_write_data        (jtag_write_data),
+    .jtag_address           (jtag_address),
+ 
+
+    
+    
+    .pc_f                   (pc_f),
+    .pc_d                   (pc_d),
+    .pc_x                   (pc_x),
+    .pc_m                   (pc_m),
+    .pc_w                   (pc_w),
+  
+
+    .icache_stall_request   (icache_stall_request),
+    .icache_restart_request (icache_restart_request),
+    .icache_refill_request  (icache_refill_request),
+    .icache_refilling       (icache_refilling),
+ 
+
+  
+
+    
+    .i_dat_o                (I_DAT_O),
+    .i_adr_o                (I_ADR_O),
+    .i_cyc_o                (I_CYC_O),
+    .i_sel_o                (I_SEL_O),
+    .i_stb_o                (I_STB_O),
+    .i_we_o                 (I_WE_O),
+    .i_cti_o                (I_CTI_O),
+    .i_lock_o               (I_LOCK_O),
+    .i_bte_o                (I_BTE_O),
+ 
+ 
+
+  
+    
+    
+    
+
+
+		      	      
+  
+
+    .jtag_read_data         (jtag_read_data),
+    .jtag_access_complete   (jtag_access_complete),
+ 
+
+  
+
+    .bus_error_d            (bus_error_d),
+ 
+
+  
+
+    .instruction_f          (instruction_f),
+ 
+
+
+		      
+    .instruction_d          (instruction_d)
+
+
+		      
+    );
+
+
+lm32_decoder_full_debug decoder (
+    
+    .instruction            (instruction_d),
+    
+    .d_result_sel_0         (d_result_sel_0_d),
+    .d_result_sel_1         (d_result_sel_1_d),
+    .x_result_sel_csr       (x_result_sel_csr_d),
+  
+
+    .x_result_sel_mc_arith  (x_result_sel_mc_arith_d),
+ 
+
+      
+         
+
+
+  
+
+    .x_result_sel_sext      (x_result_sel_sext_d),
+ 
+    
+    .x_result_sel_logic     (x_result_sel_logic_d),
+  
+          
+
+
+    .x_result_sel_add       (x_result_sel_add_d),
+    .m_result_sel_compare   (m_result_sel_compare_d),
+  
+
+    .m_result_sel_shift     (m_result_sel_shift_d),  
+ 
+    
+    .w_result_sel_load      (w_result_sel_load_d),
+  
+
+    .w_result_sel_mul       (w_result_sel_mul_d),
+ 
+
+    .x_bypass_enable        (x_bypass_enable_d),
+    .m_bypass_enable        (m_bypass_enable_d),
+    .read_enable_0          (read_enable_0_d),
+    .read_idx_0             (read_idx_0_d),
+    .read_enable_1          (read_enable_1_d),
+    .read_idx_1             (read_idx_1_d),
+    .write_enable           (write_enable_d),
+    .write_idx              (write_idx_d),
+    .immediate              (immediate_d),
+    .branch_offset          (branch_offset_d),
+    .load                   (load_d),
+    .store                  (store_d),
+    .size                   (size_d),
+    .sign_extend            (sign_extend_d),
+    .adder_op               (adder_op_d),
+    .logic_op               (logic_op_d),
+  
+
+    .direction              (direction_d),
+ 
+
+  
+                 
+                
+
+
+  
+                   
+
+
+  
+
+    .divide                 (divide_d),
+    .modulus                (modulus_d),
+ 
+
+    .branch                 (branch_d),
+    .bi_unconditional       (bi_unconditional),
+    .bi_conditional         (bi_conditional),
+    .branch_reg             (branch_reg_d),
+    .condition              (condition_d),
+  
+
+    .break_opcode           (break_d),
+ 
+
+    .scall                  (scall_d),
+    .eret                   (eret_d),
+  
+
+    .bret                   (bret_d),
+ 
+
+  
+                
+
+
+    .csr_write_enable       (csr_write_enable_d)
+    ); 
+
+
+lm32_load_store_unit_full_debug #(
+    .associativity          (dcache_associativity),
+    .sets                   (dcache_sets),
+    .bytes_per_line         (dcache_bytes_per_line),
+    .base_address           (dcache_base_address),
+    .limit                  (dcache_limit)
+  ) load_store_unit (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    
+    .stall_a                (stall_a),
+    .stall_x                (stall_x),
+    .stall_m                (stall_m),
+    .kill_x                 (kill_x),
+    .kill_m                 (kill_m),
+    .exception_m            (exception_m),
+    .store_operand_x        (store_operand_x),
+    .load_store_address_x   (adder_result_x),
+    .load_store_address_m   (operand_m),
+    .load_store_address_w   (operand_w[1:0]),
+    .load_x                 (load_x),
+    .store_x                (store_x),
+    .load_q_x               (load_q_x),
+    .store_q_x              (store_q_x),
+    .load_q_m               (load_q_m),
+    .store_q_m              (store_q_m),
+    .sign_extend_x          (sign_extend_x),
+    .size_x                 (size_x),
+  
+
+    .dflush                 (dflush_m),
+ 
+
+
+  
+    
+    
+    
+    
+    
+    
+    
+
+
+		     
+    
+    .d_dat_i                (D_DAT_I),
+    .d_ack_i                (D_ACK_I),
+    .d_err_i                (D_ERR_I),
+    .d_rty_i                (D_RTY_I),
+    
+    
+  
+
+    .dcache_refill_request  (dcache_refill_request),
+    .dcache_restart_request (dcache_restart_request),
+    .dcache_stall_request   (dcache_stall_request),
+    .dcache_refilling       (dcache_refilling),
+ 
+    
+    .load_data_w            (load_data_w),
+    .stall_wb_load          (stall_wb_load),
+    
+    .d_dat_o                (D_DAT_O),
+    .d_adr_o                (D_ADR_O),
+    .d_cyc_o                (D_CYC_O),
+    .d_sel_o                (D_SEL_O),
+    .d_stb_o                (D_STB_O),
+    .d_we_o                 (D_WE_O),
+    .d_cti_o                (D_CTI_O),
+    .d_lock_o               (D_LOCK_O),
+    .d_bte_o                (D_BTE_O)
+    );      
+       
+
+lm32_adder adder (
+    
+    .adder_op_x             (adder_op_x),
+    .adder_op_x_n           (adder_op_x_n),
+    .operand_0_x            (operand_0_x),
+    .operand_1_x            (operand_1_x),
+    
+    .adder_result_x         (adder_result_x),
+    .adder_carry_n_x        (adder_carry_n_x),
+    .adder_overflow_x       (adder_overflow_x)
+    );
+
+
+lm32_logic_op logic_op (
+    
+    .logic_op_x             (logic_op_x),
+    .operand_0_x            (operand_0_x),
+
+    .operand_1_x            (operand_1_x),
+    
+    .logic_result_x         (logic_result_x)
+    );
+              
+  
+
+
+lm32_shifter shifter (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    .stall_x                (stall_x),
+    .direction_x            (direction_x),
+    .sign_extend_x          (sign_extend_x),
+    .operand_0_x            (operand_0_x),
+    .operand_1_x            (operand_1_x),
+    
+    .shifter_result_m       (shifter_result_m)
+    );
+ 
+
+
+  
+
+
+lm32_multiplier multiplier (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    .stall_x                (stall_x),
+    .stall_m                (stall_m),
+    .operand_0              (d_result_0),
+    .operand_1              (d_result_1),
+    
+    .result                 (multiplier_result_w)    
+    );
+ 
+
+
+  
+
+
+lm32_mc_arithmetic_full_debug mc_arithmetic (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    .stall_d                (stall_d),
+    .kill_x                 (kill_x),
+  
+                  
+    .divide_d               (divide_q_d),
+    .modulus_d              (modulus_q_d),
+ 
+
+          
+                 
+
+
+  
+               
+              
+              
+
+    
+    .operand_0_d            (d_result_0),
+    .operand_1_d            (d_result_1),
+    
+    .result_x               (mc_result_x),
+  
+                  
+    .divide_by_zero_x       (divide_by_zero_x),
+ 
+
+    .stall_request_x        (mc_stall_request_x)
+    );
+ 
+
+              
+  
+
+
+lm32_interrupt_full_debug interrupt_unit (
+    
+    .clk_i                  (clk_i), 
+    .rst_i                  (rst_i),
+    
+    .interrupt              (interrupt),
+    
+    .stall_x                (stall_x),
+  
+
+    .non_debug_exception    (non_debug_exception_q_w), 
+    .debug_exception        (debug_exception_q_w),
+ 
+                   
+
+
+    .eret_q_x               (eret_q_x),
+  
+
+    .bret_q_x               (bret_q_x),
+ 
+
+    .csr                    (csr_x),
+    .csr_write_data         (operand_1_x),
+    .csr_write_enable       (csr_write_enable_q_x),
+    
+    .interrupt_exception    (interrupt_exception),
+    
+    .csr_read_data          (interrupt_csr_read_data_x)
+    );
+ 
+
+
+  
+      
+      
+        
+   
+
+
+
+
+  
+
+
+lm32_jtag_full_debug jtag (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    
+    .jtag_clk               (jtag_clk),
+    .jtag_update            (jtag_update),
+    .jtag_reg_q             (jtag_reg_q),
+    .jtag_reg_addr_q        (jtag_reg_addr_q),
+    
+  
+
+    .csr                    (csr_x),
+    .csr_write_data         (operand_1_x),
+    .csr_write_enable       (csr_write_enable_q_x),
+    .stall_x                (stall_x),
+ 
+
+  
+
+    .jtag_read_data         (jtag_read_data),
+    .jtag_access_complete   (jtag_access_complete),
+ 
+
+  
+
+    .exception_q_w          (debug_exception_q_w || non_debug_exception_q_w),
+ 
+    
+    
+    
+  
+
+    .jtx_csr_read_data      (jtx_csr_read_data),
+    .jrx_csr_read_data      (jrx_csr_read_data),
+ 
+
+  
+
+    .jtag_csr_write_enable  (jtag_csr_write_enable),
+    .jtag_csr_write_data    (jtag_csr_write_data),
+    .jtag_csr               (jtag_csr),
+    .jtag_read_enable       (jtag_read_enable),
+    .jtag_write_enable      (jtag_write_enable),
+    .jtag_write_data        (jtag_write_data),
+    .jtag_address           (jtag_address),
+ 
+
+  
+
+    .jtag_break             (jtag_break),
+    .jtag_reset             (reset_exception),
+ 
+
+    
+    .jtag_reg_d             (jtag_reg_d),
+    .jtag_reg_addr_d        (jtag_reg_addr_d)
+    );
+ 
+
+
+  
+
+
+lm32_debug_full_debug #(
+    .breakpoints            (breakpoints),
+    .watchpoints            (watchpoints)
+  ) hw_debug (
+    
+    .clk_i                  (clk_i), 
+    .rst_i                  (rst_i),
+    .pc_x                   (pc_x),
+    .load_x                 (load_x),
+    .store_x                (store_x),
+    .load_store_address_x   (adder_result_x),
+    .csr_write_enable_x     (csr_write_enable_q_x),
+    .csr_write_data         (operand_1_x),
+    .csr_x                  (csr_x),
+   
+
+	        
+
+    .jtag_csr_write_enable  (jtag_csr_write_enable),
+    .jtag_csr_write_data    (jtag_csr_write_data),
+    .jtag_csr               (jtag_csr),
+	       
+
+	        
+      
+        
+                   
+	      
+
+ 
+
+  
+
+    .eret_q_x               (eret_q_x),
+    .bret_q_x               (bret_q_x),
+    .stall_x                (stall_x),
+    .exception_x            (exception_x),
+    .q_x                    (q_x),
+  
+
+    .dcache_refill_request  (dcache_refill_request),
+ 
+
+ 
+
+    
+  
+
+    .dc_ss                  (dc_ss),
+ 
+
+    .dc_re                  (dc_re),
+    .bp_match               (bp_match),
+    .wp_match               (wp_match)
+    );
+ 
+
+
+
+
+  
+
+   
+           
+            
+          
+            
+
+
+             
+              
+    
+
+   wire [31:0] regfile_data_0, regfile_data_1;
+   reg [31:0]  w_result_d;
+   reg 	       regfile_raw_0, regfile_raw_0_nxt;
+   reg 	       regfile_raw_1, regfile_raw_1_nxt;
+   
+   
+             
+          
+
+   always @(reg_write_enable_q_w or write_idx_w or instruction_f)
+     begin
+	if (reg_write_enable_q_w
+	    && (write_idx_w == instruction_f[25:21]))
+	  regfile_raw_0_nxt = 1'b1;
+	else
+	  regfile_raw_0_nxt = 1'b0;
+	
+	if (reg_write_enable_q_w
+	    && (write_idx_w == instruction_f[20:16]))
+	  regfile_raw_1_nxt = 1'b1;
+	else
+	  regfile_raw_1_nxt = 1'b0;
+     end
+   
+   
+           
+           
+       
+
+   always @(regfile_raw_0 or w_result_d or regfile_data_0)
+     if (regfile_raw_0)
+       reg_data_live_0 = w_result_d;
+     else
+       reg_data_live_0 = regfile_data_0;
+   
+   
+           
+           
+       
+
+   always @(regfile_raw_1 or w_result_d or regfile_data_1)
+     if (regfile_raw_1)
+       reg_data_live_1 = w_result_d;
+     else
+       reg_data_live_1 = regfile_data_1;
+   
+   
+     
+
+   always @(posedge clk_i  )
+     if (rst_i ==  1'b1)
+       begin
+	  regfile_raw_0 <= 1'b0;
+	  regfile_raw_1 <= 1'b0;
+	  w_result_d <= 32'b0;
+       end
+     else
+       begin
+	  regfile_raw_0 <= regfile_raw_0_nxt;
+	  regfile_raw_1 <= regfile_raw_1_nxt;
+	  w_result_d <= w_result;
+       end
+   
+   
+      
+
+   
+   lm32_dp_ram
+     #(
+       
+       .addr_depth(1<<5),
+       .addr_width(5),
+       .data_width(32)
+       )
+   reg_0
+     (
+      
+      .clk_i	(clk_i),
+      .rst_i	(rst_i), 
+      .we_i	(reg_write_enable_q_w),
+      .wdata_i	(w_result),
+      .waddr_i	(write_idx_w),
+      .raddr_i	(instruction_f[25:21]),
+      
+      .rdata_o	(regfile_data_0)
+      );
+
+   lm32_dp_ram
+     #(
+       .addr_depth(1<<5),
+       .addr_width(5),
+       .data_width(32)
+       )
+   reg_1
+     (
+      
+      .clk_i	(clk_i),
+      .rst_i	(rst_i), 
+      .we_i	(reg_write_enable_q_w),
+      .wdata_i	(w_result),
+      .waddr_i	(write_idx_w),
+      .raddr_i	(instruction_f[20:16]),
+      
+      .rdata_o	(regfile_data_1)
+      );
+ 
+
+
+  
+   
+     
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+   
+     
+      
+      
+      
+      
+      
+      
+      
+        
+      
+       
+      
+      
+      
+   
+   
+     
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+   
+     
+      
+      
+      
+      
+      
+      
+      
+        
+      
+       
+      
+      
+      
+
+
+
+
+
+
+
+
+  
+
+
+assign reg_data_0 = use_buf ? reg_data_buf_0 : reg_data_live_0;
+assign reg_data_1 = use_buf ? reg_data_buf_1 : reg_data_live_1;
+ 
+
+  
+
+ 
+
+   
+   
+
+
+
+
+assign raw_x_0 = (write_idx_x == read_idx_0_d) && (write_enable_q_x ==  1'b1);
+assign raw_m_0 = (write_idx_m == read_idx_0_d) && (write_enable_q_m ==  1'b1);
+assign raw_w_0 = (write_idx_w == read_idx_0_d) && (write_enable_q_w ==  1'b1);
+assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x ==  1'b1);
+assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m ==  1'b1);
+assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w ==  1'b1);
+
+
+always @(*)
+begin
+    if (   (   (x_bypass_enable_x ==  1'b0)
+            && (   ((read_enable_0_d ==  1'b1) && (raw_x_0 ==  1'b1))
+                || ((read_enable_1_d ==  1'b1) && (raw_x_1 ==  1'b1))
+               )
+           )
+        || (   (m_bypass_enable_m ==  1'b0)
+            && (   ((read_enable_0_d ==  1'b1) && (raw_m_0 ==  1'b1))
+                || ((read_enable_1_d ==  1'b1) && (raw_m_1 ==  1'b1))
+               )
+           )
+       )
+        interlock =  1'b1;
+    else
+        interlock =  1'b0;
+end
+
+
+always @(*)
+begin
+    if (raw_x_0 ==  1'b1)        
+        bypass_data_0 = x_result;
+    else if (raw_m_0 ==  1'b1)
+        bypass_data_0 = m_result;
+    else if (raw_w_0 ==  1'b1)
+        bypass_data_0 = w_result;
+    else
+        bypass_data_0 = reg_data_0;
+end
+
+
+always @(*)
+begin
+    if (raw_x_1 ==  1'b1)
+        bypass_data_1 = x_result;
+    else if (raw_m_1 ==  1'b1)
+        bypass_data_1 = m_result;
+    else if (raw_w_1 ==  1'b1)
+        bypass_data_1 = w_result;
+    else
+        bypass_data_1 = reg_data_1;
+end
+
+   
+          
+       
+       
+     
+
+   assign branch_predict_d = bi_unconditional | bi_conditional;
+   assign branch_predict_taken_d = bi_unconditional ? 1'b1 : (bi_conditional ? instruction_d[15] : 1'b0);
+   
+   
+   assign branch_target_d = pc_d + branch_offset_d;
+
+   
+   
+   
+   assign branch_predict_address_d = branch_predict_taken_d ? branch_target_d : pc_f;
+
+
+always @(*)
+begin
+    d_result_0 = d_result_sel_0_d[0] ? {pc_f, 2'b00} : bypass_data_0; 
+    case (d_result_sel_1_d)
+     2'b00:      d_result_1 = { 32{1'b0}};
+     2'b01:     d_result_1 = bypass_data_1;
+     2'b10: d_result_1 = immediate_d;
+    default:                        d_result_1 = { 32{1'bx}};
+    endcase
+end
+
+      
+
+   
+   
+
+
+
+  
+
+
+assign sextb_result_x = {{24{operand_0_x[7]}}, operand_0_x[7:0]};
+assign sexth_result_x = {{16{operand_0_x[15]}}, operand_0_x[15:0]};
+assign sext_result_x = size_x ==  2'b00 ? sextb_result_x : sexth_result_x;
+ 
+
+
+  
+
+      
+
+
+
+
+assign cmp_zero = operand_0_x == operand_1_x;
+assign cmp_negative = adder_result_x[ 32-1];
+assign cmp_overflow = adder_overflow_x;
+assign cmp_carry_n = adder_carry_n_x;
+always @(*)
+begin
+    case (condition_x)
+     3'b000:   condition_met_x =  1'b1;
+     3'b110:   condition_met_x =  1'b1;
+     3'b001:    condition_met_x = cmp_zero;
+     3'b111:   condition_met_x = !cmp_zero;
+     3'b010:    condition_met_x = !cmp_zero && (cmp_negative == cmp_overflow);
+     3'b101:   condition_met_x = cmp_carry_n && !cmp_zero;
+     3'b011:   condition_met_x = cmp_negative == cmp_overflow;
+     3'b100:  condition_met_x = cmp_carry_n;
+    default:              condition_met_x = 1'bx;
+    endcase 
+end
+
+
+always @(*)
+begin
+    x_result =   x_result_sel_add_x ? adder_result_x 
+               : x_result_sel_csr_x ? csr_read_data_x
+  
+
+               : x_result_sel_sext_x ? sext_result_x
+ 
+
+  
+                  
+
+
+  
+                  
+
+
+  
+
+               : x_result_sel_mc_arith_x ? mc_result_x
+ 
+
+               : logic_result_x;
+end
+
+
+always @(*)
+begin
+    m_result =   m_result_sel_compare_m ? {{ 32-1{1'b0}}, condition_met_m}
+  
+
+               : m_result_sel_shift_m ? shifter_result_m
+ 
+
+               : operand_m; 
+end
+
+
+always @(*)
+begin
+    w_result =    w_result_sel_load_w ? load_data_w
+  
+
+                : w_result_sel_mul_w ? multiplier_result_w
+ 
+
+                : operand_w;
+end
+
+  
+    
+
+assign branch_taken_x =      (stall_x ==  1'b0)
+                          && (   (branch_x ==  1'b1)
+                              && ((condition_x ==  3'b000) || (condition_x ==  3'b110))
+                              && (valid_x ==  1'b1)
+                              && (branch_predict_x ==  1'b0)
+                             ); 
+ 
+
+
+
+assign branch_taken_m =      (stall_m ==  1'b0) 
+                          && (   (   (branch_m ==  1'b1) 
+                                  && (valid_m ==  1'b1)
+                                  && (   (   (condition_met_m ==  1'b1)
+					  && (branch_predict_taken_m ==  1'b0)
+					 )
+				      || (   (condition_met_m ==  1'b0)
+					  && (branch_predict_m ==  1'b1)
+					  && (branch_predict_taken_m ==  1'b1)
+					 )
+				     )
+                                 ) 
+                              || (exception_m ==  1'b1)
+                             );
+
+
+assign branch_mispredict_taken_m =    (condition_met_m ==  1'b0)
+                                   && (branch_predict_m ==  1'b1)
+	   			   && (branch_predict_taken_m ==  1'b1);
+   
+
+assign branch_flushX_m =    (stall_m ==  1'b0)
+                         && (   (   (branch_m ==  1'b1) 
+                                 && (valid_m ==  1'b1)
+			         && (   (condition_met_m ==  1'b1)
+				     || (   (condition_met_m ==  1'b0)
+					 && (branch_predict_m ==  1'b1)
+					 && (branch_predict_taken_m ==  1'b1)
+					)
+				    )
+			        )
+			     || (exception_m ==  1'b1)
+			    );
+
+
+assign kill_f =    (   (valid_d ==  1'b1)
+                    && (branch_predict_taken_d ==  1'b1)
+		   )
+                || (branch_taken_m ==  1'b1) 
+  
+    
+                || (branch_taken_x ==  1'b1)
+ 
+
+  
+
+                || (icache_refill_request ==  1'b1) 
+ 
+
+  
+                
+                || (dcache_refill_request ==  1'b1)
+ 
+
+                ;
+assign kill_d =    (branch_taken_m ==  1'b1) 
+  
+    
+                || (branch_taken_x ==  1'b1)
+ 
+
+  
+
+                || (icache_refill_request ==  1'b1)     
+ 
+                
+  
+                
+                || (dcache_refill_request ==  1'b1)
+ 
+
+                ;
+assign kill_x =    (branch_flushX_m ==  1'b1) 
+  
+                
+                || (dcache_refill_request ==  1'b1)
+ 
+
+                ;
+assign kill_m =     1'b0
+  
+                
+                || (dcache_refill_request ==  1'b1)
+ 
+
+                ;                
+assign kill_w =     1'b0
+  
+                
+                || (dcache_refill_request ==  1'b1)
+ 
+                
+                ;
+
+
+
+  
+
+assign breakpoint_exception =    (   (   (break_x ==  1'b1)
+				      || (bp_match ==  1'b1)
+				     )
+				  && (valid_x ==  1'b1)
+				 )
+  
+
+                              || (jtag_break ==  1'b1)
+ 
+
+                              ;
+ 
+
+
+  
+
+assign watchpoint_exception = wp_match ==  1'b1;
+ 
+
+
+  
+
+assign instruction_bus_error_exception = (   (bus_error_x ==  1'b1)
+                                          && (valid_x ==  1'b1)
+                                         );
+assign data_bus_error_exception = data_bus_error_seen ==  1'b1;
+ 
+
+
+  
+
+assign divide_by_zero_exception = divide_by_zero_x ==  1'b1;
+ 
+
+
+assign system_call_exception = (   (scall_x ==  1'b1)
+  
+
+                                && (valid_x ==  1'b1)
+ 
+
+			       );
+
+  
+
+assign debug_exception_x =  (breakpoint_exception ==  1'b1)
+                         || (watchpoint_exception ==  1'b1)
+                         ;
+
+assign non_debug_exception_x = (system_call_exception ==  1'b1)
+  
+
+                            || (reset_exception ==  1'b1)
+ 
+
+  
+
+                            || (instruction_bus_error_exception ==  1'b1)
+                            || (data_bus_error_exception ==  1'b1)
+ 
+
+  
+
+                            || (divide_by_zero_exception ==  1'b1)
+ 
+
+  
+
+                            || (   (interrupt_exception ==  1'b1)
+  
+
+                                && (dc_ss ==  1'b0)
+ 
+                            
+  
+
+ 				&& (store_q_m ==  1'b0)
+				&& (D_CYC_O ==  1'b0)
+ 
+
+                               )
+ 
+
+                            ;
+
+assign exception_x = (debug_exception_x ==  1'b1) || (non_debug_exception_x ==  1'b1);
+ 
+               
+ 
+                               
+                               
+
+ 
+                               
+
+ 
+                                  
+ 
+                                   
+                            
+ 
+ 				   
+				   
+
+                               
+
+                            
+
+
+
+  
+ 
+
+ 
+  
+      
+   
+      
+
+
+
+
+always @(*)
+begin
+  
+
+  
+
+    if (reset_exception ==  1'b1)
+        eid_x =  3'h0;
+    else
+ 
+     
+  
+
+         if (data_bus_error_exception ==  1'b1)
+        eid_x =  3'h4;
+    else
+ 
+
+         if (breakpoint_exception ==  1'b1)
+        eid_x =  3'd1;
+    else
+ 
+
+  
+
+         if (data_bus_error_exception ==  1'b1)
+        eid_x =  3'h4;
+    else
+         if (instruction_bus_error_exception ==  1'b1)
+        eid_x =  3'h2;
+    else
+ 
+
+  
+
+         if (watchpoint_exception ==  1'b1)
+        eid_x =  3'd3;
+    else 
+ 
+
+  
+
+         if (divide_by_zero_exception ==  1'b1)
+        eid_x =  3'h5;
+    else
+ 
+
+  
+
+         if (   (interrupt_exception ==  1'b1)
+  
+
+             && (dc_ss ==  1'b0)
+ 
+                            
+            )
+        eid_x =  3'h6;
+    else
+ 
+
+        eid_x =  3'h7;
+end
+
+
+
+assign stall_a = (stall_f ==  1'b1);
+                
+assign stall_f = (stall_d ==  1'b1);
+                
+assign stall_d =   (stall_x ==  1'b1) 
+                || (   (interlock ==  1'b1)
+                    && (kill_d ==  1'b0)
+                   ) 
+		|| (   (   (eret_d ==  1'b1)
+			|| (scall_d ==  1'b1)
+  
+
+			|| (bus_error_d ==  1'b1)
+ 
+
+		       )
+		    && (   (load_q_x ==  1'b1)
+			|| (load_q_m ==  1'b1)
+			|| (store_q_x ==  1'b1)
+			|| (store_q_m ==  1'b1)
+			|| (D_CYC_O ==  1'b1)
+		       )
+                    && (kill_d ==  1'b0)
+		   )
+  
+
+		|| (   (   (break_d ==  1'b1)
+			|| (bret_d ==  1'b1)
+		       )
+		    && (   (load_q_x ==  1'b1)
+			|| (store_q_x ==  1'b1)
+			|| (load_q_m ==  1'b1)
+			|| (store_q_m ==  1'b1)
+			|| (D_CYC_O ==  1'b1)
+		       )
+                    && (kill_d ==  1'b0)
+		   )
+ 
+                   
+                || (   (csr_write_enable_d ==  1'b1)
+                    && (load_q_x ==  1'b1)
+                   )                      
+  
+                 
+                 
+                       
+		           
+			 
+			
+		    
+
+	
+                ;
+                
+assign stall_x =    (stall_m ==  1'b1)
+  
+
+                 || (   (mc_stall_request_x ==  1'b1)
+                     && (kill_x ==  1'b0)
+                    ) 
+ 
+
+
+	    
+                 ;
+
+assign stall_m =    (stall_wb_load ==  1'b1)
+  
+                    
+
+
+                 || (   (D_CYC_O ==  1'b1)
+                     && (   (store_m ==  1'b1)
+		         
+          
+          
+
+		  
+	 
+	
+
+          
+           
+          
+       
+
+  
+
+		         || ((store_x ==  1'b1) && (interrupt_exception ==  1'b1))
+ 
+
+                         || (load_m ==  1'b1)
+                         || (load_x ==  1'b1)
+                        ) 
+                    ) 
+ 
+                 
+  
+
+                 || (dcache_stall_request ==  1'b1)     
+ 
+                                    
+  
+
+                 || (icache_stall_request ==  1'b1)     
+                 || ((I_CYC_O ==  1'b1) && ((branch_m ==  1'b1) || (exception_m ==  1'b1))) 
+ 
+ 
+                                
+
+
+                               
+  
+                                  
+                        
+                    
+
+
+  
+                  
+   
+
+                 ;      
+
+
+
+
+  
+
+assign q_d = (valid_d ==  1'b1) && (kill_d ==  1'b0);
+ 
+
+  
+         
+         
+
+
+  
+         
+
+
+  
+
+assign divide_q_d = (divide_d ==  1'b1) && (q_d ==  1'b1);
+assign modulus_q_d = (modulus_d ==  1'b1) && (q_d ==  1'b1);
+ 
+
+assign q_x = (valid_x ==  1'b1) && (kill_x ==  1'b0);
+assign csr_write_enable_q_x = (csr_write_enable_x ==  1'b1) && (q_x ==  1'b1);
+assign eret_q_x = (eret_x ==  1'b1) && (q_x ==  1'b1);
+  
+
+assign bret_q_x = (bret_x ==  1'b1) && (q_x ==  1'b1);
+ 
+
+assign load_q_x = (load_x ==  1'b1) 
+               && (q_x ==  1'b1)
+  
+
+               && (bp_match ==  1'b0)
+ 
+
+                  ;
+assign store_q_x = (store_x ==  1'b1) 
+               && (q_x ==  1'b1)
+  
+
+               && (bp_match ==  1'b0)
+ 
+
+                  ;
+  
+         
+
+                              
+assign q_m = (valid_m ==  1'b1) && (kill_m ==  1'b0) && (exception_m ==  1'b0);
+assign load_q_m = (load_m ==  1'b1) && (q_m ==  1'b1);
+assign store_q_m = (store_m ==  1'b1) && (q_m ==  1'b1);
+  
+
+assign debug_exception_q_w = ((debug_exception_w ==  1'b1) && (valid_w ==  1'b1));
+assign non_debug_exception_q_w = ((non_debug_exception_w ==  1'b1) && (valid_w ==  1'b1));        
+ 
+                 
+
+
+
+assign write_enable_q_x = (write_enable_x ==  1'b1) && (valid_x ==  1'b1) && (branch_flushX_m ==  1'b0);
+assign write_enable_q_m = (write_enable_m ==  1'b1) && (valid_m ==  1'b1);
+assign write_enable_q_w = (write_enable_w ==  1'b1) && (valid_w ==  1'b1);
+
+assign reg_write_enable_q_w = (write_enable_w ==  1'b1) && (kill_w ==  1'b0) && (valid_w ==  1'b1);
+
+
+assign cfg = {
+               6'h02,
+              watchpoints[3:0],
+              breakpoints[3:0],
+              interrupts[5:0],
+  
+
+               1'b1,
+ 
+              
+
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+ 
+               1'b1
+ 
+              
+
+
+              };
+
+assign cfg2 = {
+		     30'b0,
+  
+		     
+
+
+		      1'b0,
+ 
+
+  
+		     
+
+
+		      1'b0
+ 
+
+		     };
+   
+
+  
+
+assign iflush = (   (csr_write_enable_d ==  1'b1) 
+                 && (csr_d ==  5'h3)
+                 && (stall_d ==  1'b0)
+                 && (kill_d ==  1'b0)
+                 && (valid_d ==  1'b1))
+
+  
+
+             ||
+                (   (jtag_csr_write_enable ==  1'b1)
+		 && (jtag_csr ==  5'h3))
+ 
+
+		 ;
+ 
+ 
+  
+
+assign dflush_x = (   (csr_write_enable_q_x ==  1'b1) 
+                   && (csr_x ==  5'h4))
+
+  
+
+               ||
+                  (   (jtag_csr_write_enable ==  1'b1)
+		   && (jtag_csr ==  5'h4))
+ 
+
+		   ;
+ 
+ 
+
+
+assign csr_d = read_idx_0_d[ (5-1):0];
+
+
+always @(*)
+begin
+    case (csr_x)
+  
+
+     5'h0,
+     5'h1,
+     5'h2:   csr_read_data_x = interrupt_csr_read_data_x;  
+ 
+
+  
+         
+
+
+     5'h6:  csr_read_data_x = cfg;
+     5'h7:  csr_read_data_x = {eba, 8'h00};
+  
+
+     5'h9: csr_read_data_x = {deba, 8'h00};
+ 
+
+  
+
+     5'he:  csr_read_data_x = jtx_csr_read_data;  
+     5'hf:  csr_read_data_x = jrx_csr_read_data;
+ 
+
+     5'ha: csr_read_data_x = cfg2;
+     5'hb:  csr_read_data_x = sdb_address;
+  
+
+     5'hc:  csr_read_data_x = data_bus_error_addr;
+ 
+
+      
+      
+    default:        csr_read_data_x = { 32{1'bx}};
+    endcase
+end
+
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        eba <= eba_reset[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+    else
+    begin
+        if ((csr_write_enable_q_x ==  1'b1) && (csr_x ==  5'h7) && (stall_x ==  1'b0))
+            eba <= operand_1_x[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+  
+
+   
+
+       if ((jtag_csr_write_enable ==  1'b1) && (jtag_csr ==  5'h7))
+         eba <= jtag_csr_write_data[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+  
+
+   
+              
+           
+ 
+	 
+ 
+
+    end
+end
+
+  
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        deba <= deba_reset[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+    else
+    begin
+        if ((csr_write_enable_q_x ==  1'b1) && (csr_x ==  5'h9) && (stall_x ==  1'b0))
+            deba <= operand_1_x[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+   
+
+    
+
+       if ((jtag_csr_write_enable ==  1'b1) && (jtag_csr ==  5'h9))
+         deba <= jtag_csr_write_data[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+   
+
+    
+              
+           
+  
+       
+  
+
+    end
+end
+ 
+
+
+
+  
+   
+
+       
+          
+    
+            
+
+
+
+
+  
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        data_bus_error_seen <=  1'b0;
+    else
+    begin
+        
+        if ((D_ERR_I ==  1'b1) && (D_CYC_O ==  1'b1)) begin
+           data_bus_error_seen <=  1'b1;
+	   data_bus_error_addr <= D_ADR_O;
+	end
+        
+        if ((exception_m ==  1'b1) && (kill_m ==  1'b0))
+            data_bus_error_seen <=  1'b0;
+    end
+end
+ 
+
+ 
+
+
+  
+
+  
+
+always @(*)
+begin
+    if (   (icache_refill_request ==  1'b1) 
+        || (dcache_refill_request ==  1'b1)
+       )
+        valid_a =  1'b0;
+    else if (   (icache_restart_request ==  1'b1) 
+             || (dcache_restart_request ==  1'b1) 
+            ) 
+        valid_a =  1'b1;
+    else 
+        valid_a = !icache_refilling && !dcache_refilling;
+end 
+ 
+ 
+
+        
+          
+         
+          
+     
+          
+ 
+
+
+ 
+ 
+ 
+
+        
+          
+         
+          
+     
+          
+ 
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        valid_f <=  1'b0;
+        valid_d <=  1'b0;
+        valid_x <=  1'b0;
+        valid_m <=  1'b0;
+        valid_w <=  1'b0;
+    end
+    else
+    begin    
+        if ((kill_f ==  1'b1) || (stall_a ==  1'b0))
+  
+
+            valid_f <= valid_a;    
+ 
+              
+
+            
+        else if (stall_f ==  1'b0)
+            valid_f <=  1'b0;            
+
+        if (kill_d ==  1'b1)
+            valid_d <=  1'b0;
+        else if (stall_f ==  1'b0)
+            valid_d <= valid_f & !kill_f;
+        else if (stall_d ==  1'b0)
+            valid_d <=  1'b0;
+       
+        if (stall_d ==  1'b0)
+            valid_x <= valid_d & !kill_d;
+        else if (kill_x ==  1'b1)
+            valid_x <=  1'b0;
+        else if (stall_x ==  1'b0)
+            valid_x <=  1'b0;
+
+        if (kill_m ==  1'b1)
+            valid_m <=  1'b0;
+        else if (stall_x ==  1'b0)
+            valid_m <= valid_x & !kill_x;
+        else if (stall_m ==  1'b0)
+            valid_m <=  1'b0;
+
+        if (stall_m ==  1'b0)
+            valid_w <= valid_m & !kill_m;
+        else 
+            valid_w <=  1'b0;        
+    end
+end
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+  
+                 
+
+        
+        operand_0_x <= { 32{1'b0}};
+        operand_1_x <= { 32{1'b0}};
+        store_operand_x <= { 32{1'b0}};
+        branch_target_x <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};        
+        x_result_sel_csr_x <=  1'b0;
+  
+
+        x_result_sel_mc_arith_x <=  1'b0;
+ 
+
+      
+          
+
+
+  
+
+        x_result_sel_sext_x <=  1'b0;
+ 
+    
+  
+          
+
+
+        x_result_sel_add_x <=  1'b0;
+        m_result_sel_compare_x <=  1'b0;
+  
+
+        m_result_sel_shift_x <=  1'b0;
+ 
+    
+        w_result_sel_load_x <=  1'b0;
+  
+
+        w_result_sel_mul_x <=  1'b0;
+ 
+
+        x_bypass_enable_x <=  1'b0;
+        m_bypass_enable_x <=  1'b0;
+        write_enable_x <=  1'b0;
+        write_idx_x <= { 5{1'b0}};
+        csr_x <= { 5{1'b0}};
+        load_x <=  1'b0;
+        store_x <=  1'b0;
+        size_x <= { 2{1'b0}};
+        sign_extend_x <=  1'b0;
+        adder_op_x <=  1'b0;
+        adder_op_x_n <=  1'b0;
+        logic_op_x <= 4'h0;
+  
+
+        direction_x <=  1'b0;
+ 
+
+  
+          
+
+
+
+        branch_x <=  1'b0;
+        branch_predict_x <=  1'b0;
+        branch_predict_taken_x <=  1'b0;
+        condition_x <=  3'b000;
+  
+
+        break_x <=  1'b0;
+ 
+
+        scall_x <=  1'b0;
+        eret_x <=  1'b0;
+  
+
+        bret_x <=  1'b0;
+ 
+
+  
+
+        bus_error_x <=  1'b0;
+        data_bus_error_exception_m <=  1'b0;
+ 
+
+        csr_write_enable_x <=  1'b0;
+        operand_m <= { 32{1'b0}};
+        branch_target_m <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+        m_result_sel_compare_m <=  1'b0;
+  
+
+        m_result_sel_shift_m <=  1'b0;
+ 
+    
+        w_result_sel_load_m <=  1'b0;
+  
+
+        w_result_sel_mul_m <=  1'b0;
+ 
+
+        m_bypass_enable_m <=  1'b0;
+        branch_m <=  1'b0;
+        branch_predict_m <=  1'b0;
+	branch_predict_taken_m <=  1'b0;
+        exception_m <=  1'b0;
+        load_m <=  1'b0;
+        store_m <=  1'b0;
+        write_enable_m <=  1'b0;            
+        write_idx_m <= { 5{1'b0}};
+        condition_met_m <=  1'b0;
+  
+
+        dflush_m <=  1'b0;
+ 
+
+  
+
+        debug_exception_m <=  1'b0;
+        non_debug_exception_m <=  1'b0;        
+ 
+
+        operand_w <= { 32{1'b0}};        
+        w_result_sel_load_w <=  1'b0;
+  
+
+        w_result_sel_mul_w <=  1'b0;
+ 
+
+        write_idx_w <= { 5{1'b0}};        
+        write_enable_w <=  1'b0;
+  
+
+        debug_exception_w <=  1'b0;
+        non_debug_exception_w <=  1'b0;        
+ 
+          
+
+
+  
+
+        memop_pc_w <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ 
+
+    end
+    else
+    begin
+        
+       
+        if (stall_x ==  1'b0)
+        begin
+  
+                     
+
+        
+            operand_0_x <= d_result_0;
+            operand_1_x <= d_result_1;
+            store_operand_x <= bypass_data_1;
+            branch_target_x <= branch_reg_d ==  1'b1 ? bypass_data_0[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] : branch_target_d;            
+            x_result_sel_csr_x <= x_result_sel_csr_d;
+  
+
+            x_result_sel_mc_arith_x <= x_result_sel_mc_arith_d;
+ 
+
+      
+              
+
+
+  
+
+            x_result_sel_sext_x <= x_result_sel_sext_d;
+ 
+    
+  
+              
+
+
+            x_result_sel_add_x <= x_result_sel_add_d;
+            m_result_sel_compare_x <= m_result_sel_compare_d;
+  
+
+            m_result_sel_shift_x <= m_result_sel_shift_d;
+ 
+    
+            w_result_sel_load_x <= w_result_sel_load_d;
+  
+
+            w_result_sel_mul_x <= w_result_sel_mul_d;
+ 
+
+            x_bypass_enable_x <= x_bypass_enable_d;
+            m_bypass_enable_x <= m_bypass_enable_d;
+            load_x <= load_d;
+            store_x <= store_d;
+            branch_x <= branch_d;
+	    branch_predict_x <= branch_predict_d;
+	    branch_predict_taken_x <= branch_predict_taken_d;
+	    write_idx_x <= write_idx_d;
+            csr_x <= csr_d;
+            size_x <= size_d;
+            sign_extend_x <= sign_extend_d;
+            adder_op_x <= adder_op_d;
+            adder_op_x_n <= ~adder_op_d;
+            logic_op_x <= logic_op_d;
+  
+
+            direction_x <= direction_d;
+ 
+
+  
+              
+
+
+            condition_x <= condition_d;
+            csr_write_enable_x <= csr_write_enable_d;
+  
+
+            break_x <= break_d;
+ 
+
+            scall_x <= scall_d;
+  
+
+            bus_error_x <= bus_error_d;
+ 
+
+            eret_x <= eret_d;
+  
+
+            bret_x <= bret_d; 
+ 
+
+            write_enable_x <= write_enable_d;
+        end
+        
+        
+
+        if (stall_m ==  1'b0)
+        begin
+            operand_m <= x_result;
+            m_result_sel_compare_m <= m_result_sel_compare_x;
+  
+
+            m_result_sel_shift_m <= m_result_sel_shift_x;
+ 
+    
+            if (exception_x ==  1'b1)
+            begin
+                w_result_sel_load_m <=  1'b0;
+  
+
+                w_result_sel_mul_m <=  1'b0;
+ 
+
+            end
+            else
+            begin
+                w_result_sel_load_m <= w_result_sel_load_x;
+  
+
+                w_result_sel_mul_m <= w_result_sel_mul_x;
+ 
+
+            end
+            m_bypass_enable_m <= m_bypass_enable_x;
+            load_m <= load_x;
+            store_m <= store_x;
+  
+    
+            branch_m <= branch_x && !branch_taken_x;
+ 
+              
+	      
+	      
+
+
+  
+
+	   
+	   
+	   
+	   
+	   
+            if (non_debug_exception_x ==  1'b1) 
+                write_idx_m <=  5'd30;
+            else if (debug_exception_x ==  1'b1)
+                write_idx_m <=  5'd31;
+            else 
+                write_idx_m <= write_idx_x;
+ 
+               
+                  
+             
+                  
+
+
+            condition_met_m <= condition_met_x;
+  
+
+	   if (exception_x ==  1'b1)
+	     if ((dc_re ==  1'b1)
+		 || ((debug_exception_x ==  1'b1) 
+		     && (non_debug_exception_x ==  1'b0)))
+	       branch_target_m <= {deba, eid_x, {3{1'b0}}};
+	     else
+	       branch_target_m <= {eba, eid_x, {3{1'b0}}};
+	   else
+	     branch_target_m <= branch_target_x;
+ 
+                      
+
+
+  
+              
+              
+
+
+  
+
+            dflush_m <= dflush_x;
+ 
+
+  
+ 
+               
+
+
+
+            write_enable_m <= exception_x ==  1'b1 ?  1'b1 : write_enable_x;            
+  
+
+            debug_exception_m <= debug_exception_x;
+            non_debug_exception_m <= non_debug_exception_x;        
+ 
+
+        end
+        
+        
+        if (stall_m ==  1'b0)
+        begin
+            if ((exception_x ==  1'b1) && (q_x ==  1'b1) && (stall_x ==  1'b0))
+                exception_m <=  1'b1;
+            else 
+                exception_m <=  1'b0;
+  
+
+	   data_bus_error_exception_m <=    (data_bus_error_exception ==  1'b1) 
+  
+
+					 && (reset_exception ==  1'b0)
+ 
+
+					 ;
+ 
+
+	end
+                
+        
+  
+
+        operand_w <= exception_m ==  1'b1 ? (data_bus_error_exception_m ? {memop_pc_w, 2'b00} : {pc_m, 2'b00}) : m_result;
+ 
+                 
+
+
+        w_result_sel_load_w <= w_result_sel_load_m;
+  
+
+        w_result_sel_mul_w <= w_result_sel_mul_m;
+ 
+
+        write_idx_w <= write_idx_m;
+  
+          
+          
+ 
+           
+
+
+
+        write_enable_w <= write_enable_m;
+  
+
+        debug_exception_w <= debug_exception_m;
+        non_debug_exception_w <= non_debug_exception_m;
+ 
+          
+
+
+  
+
+        if (   (stall_m ==  1'b0)
+            && (   (load_q_m ==  1'b1) 
+                || (store_q_m ==  1'b1)
+               )
+	   )
+          memop_pc_w <= pc_m;
+ 
+
+    end
+end
+
+  
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        use_buf <=  1'b0;
+        reg_data_buf_0 <= { 32{1'b0}};
+        reg_data_buf_1 <= { 32{1'b0}};
+    end
+    else
+    begin
+        if (stall_d ==  1'b0)
+            use_buf <=  1'b0;
+        else if (use_buf ==  1'b0)
+        begin        
+            reg_data_buf_0 <= reg_data_live_0;
+            reg_data_buf_1 <= reg_data_live_1;
+            use_buf <=  1'b1;
+        end        
+        if (reg_write_enable_q_w ==  1'b1)
+        begin
+            if (write_idx_w == read_idx_0_d)
+                reg_data_buf_0 <= w_result;
+            if (write_idx_w == read_idx_1_d)
+                reg_data_buf_1 <= w_result;
+        end
+    end
+end
+ 
+
+
+  
+
+ 
+
+   
+
+        
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+        
+     
+           
+            
+        
+
+
+
+
+  
+
+   
+
+       
+    
+          
+          
+          
+          
+          
+ 
+          
+
+          
+    
+    
+    
+          
+        
+ 
+               
+
+           
+
+                
+              
+              
+              
+              
+        
+        
+              
+        
+             
+        
+            
+                 
+            
+                
+                  
+                  
+            
+            
+              
+            
+              
+ 
+              
+
+        
+        
+        
+              
+ 
+              
+
+        
+    
+
+
+
+      
+
+
+
+
+
+        
+endmodule 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_load_store_unit_full_debug 
+(
+    
+    clk_i,
+    rst_i,
+ 
+    stall_a,
+    stall_x,
+    stall_m,
+    kill_x,
+    kill_m,
+    exception_m,
+    store_operand_x,
+    load_store_address_x,
+    load_store_address_m,
+    load_store_address_w,
+    load_x,
+    store_x,
+    load_q_x,
+    store_q_x,
+    load_q_m,
+    store_q_m,
+    sign_extend_x,
+    size_x,
+  
+
+    dflush,
+ 
+
+    
+    d_dat_i,
+    d_ack_i,
+    d_err_i,
+    d_rty_i,
+    
+    
+  
+
+    dcache_refill_request,
+    dcache_restart_request,
+    dcache_stall_request,
+    dcache_refilling,
+ 
+    
+  
+    
+    
+    
+    
+    
+    
+    
+
+			     
+    load_data_w,
+    stall_wb_load,
+    
+    d_dat_o,
+    d_adr_o,
+    d_cyc_o,
+    d_sel_o,
+    d_stb_o,
+    d_we_o,
+    d_cti_o,
+    d_lock_o,
+    d_bte_o
+    );
+
+
+
+
+
+parameter associativity = 1;                            
+parameter sets = 512;                                   
+parameter bytes_per_line = 16;                          
+parameter base_address = 0;                             
+parameter limit = 0;                                    
+
+
+localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
+localparam addr_offset_lsb = 2;
+localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
+
+
+
+
+
+   input clk_i;                                            
+   
+input rst_i;                                            
+
+input stall_a;                                          
+input stall_x;                                          
+input stall_m;                                          
+input kill_x;                                           
+input kill_m;                                           
+input exception_m;                                      
+
+input [ (32-1):0] store_operand_x;                 
+input [ (32-1):0] load_store_address_x;            
+input [ (32-1):0] load_store_address_m;            
+input [1:0] load_store_address_w;                       
+input load_x;                                           
+input store_x;                                          
+input load_q_x;                                         
+input store_q_x;                                        
+input load_q_m;                                         
+input store_q_m;                                        
+input sign_extend_x;                                    
+input [ 1:0] size_x;                          
+
+  
+
+input dflush;                                           
+ 
+
+
+     
+     
+     
+      
+      
+            
+    	 
+   
+
+
+
+   reg 		 [31:0] iram_dat_d0;
+   reg 		 iram_en_d0;
+   wire 	 iram_en;
+   wire [31:0] 	 iram_data;
+   
+   
+   
+input [ (32-1):0] d_dat_i;                         
+input d_ack_i;                                          
+input d_err_i;                                          
+input d_rty_i;                                          
+
+
+
+
+
+  
+
+output dcache_refill_request;                           
+wire   dcache_refill_request;
+output dcache_restart_request;                          
+wire   dcache_restart_request;
+output dcache_stall_request;                            
+wire   dcache_stall_request;
+output dcache_refilling;
+wire   dcache_refilling;
+ 
+
+
+   
+output [ (32-1):0] load_data_w;                    
+reg    [ (32-1):0] load_data_w;
+output stall_wb_load;                                   
+reg    stall_wb_load;
+
+output [ (32-1):0] d_dat_o;                        
+reg    [ (32-1):0] d_dat_o;
+output [ (32-1):0] d_adr_o;                        
+reg    [ (32-1):0] d_adr_o;
+output d_cyc_o;                                         
+reg    d_cyc_o;
+output [ (4-1):0] d_sel_o;                 
+reg    [ (4-1):0] d_sel_o;
+output d_stb_o;                                         
+reg    d_stb_o; 
+output d_we_o;                                          
+reg    d_we_o;
+output [ (3-1):0] d_cti_o;                       
+reg    [ (3-1):0] d_cti_o;
+output d_lock_o;                                        
+reg    d_lock_o;
+output [ (2-1):0] d_bte_o;                       
+wire   [ (2-1):0] d_bte_o;
+
+
+
+
+
+
+reg [ 1:0] size_m;
+reg [ 1:0] size_w;
+reg sign_extend_m;
+reg sign_extend_w;
+reg [ (32-1):0] store_data_x;       
+reg [ (32-1):0] store_data_m;       
+reg [ (4-1):0] byte_enable_x;
+reg [ (4-1):0] byte_enable_m;
+wire [ (32-1):0] data_m;
+reg [ (32-1):0] data_w;
+
+   
+
+  
+
+wire dcache_select_x;                                   
+reg dcache_select_m;
+wire [ (32-1):0] dcache_data_m;                    
+wire [ (32-1):0] dcache_refill_address;            
+reg dcache_refill_ready;                                
+wire [ (3-1):0] first_cycle_type;                
+wire [ (3-1):0] next_cycle_type;                 
+wire last_word;                                         
+wire [ (32-1):0] first_address;                    
+ 
+
+  
+                                      
+ 
+                                      
+                    
+                      
+                        
+                  
+
+
+wire wb_select_x;                                       
+  
+                                      
+
+  
+    
+    
+   
+
+
+
+reg wb_select_m;
+reg [ (32-1):0] wb_data_m;                         
+reg wb_load_complete;                                   
+   
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+  
+
+
+lm32_dcache_full_debug #(
+    .associativity          (associativity),
+    .sets                   (sets),
+    .bytes_per_line         (bytes_per_line),
+    .base_address           (base_address),
+    .limit                  (limit)
+    ) dcache ( 
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),      
+    .stall_a                (stall_a),
+    .stall_x                (stall_x),
+    .stall_m                (stall_m),
+    .address_x              (load_store_address_x),
+    .address_m              (load_store_address_m),
+    .load_q_m               (load_q_m & dcache_select_m),
+    .store_q_m              (store_q_m & dcache_select_m),
+    .store_data             (store_data_m),
+    .store_byte_select      (byte_enable_m & {4{dcache_select_m}}),
+    .refill_ready           (dcache_refill_ready),
+    .refill_data            (wb_data_m),
+    .dflush                 (dflush),
+    
+    .stall_request          (dcache_stall_request),
+    .restart_request        (dcache_restart_request),
+    .refill_request         (dcache_refill_request),
+    .refill_address         (dcache_refill_address),
+    .refilling              (dcache_refilling),
+    .load_data              (dcache_data_m)
+    );
+ 
+
+
+
+
+
+
+
+  
+            
+                             
+
+
+
+  
+            
+                             
+
+      
+        
+
+    
+       
+
+   
+
+    
+     
+       
+     
+         
+     
+
+          
+    
+   
+   
+
+
+   
+  
+
+   assign dcache_select_x =    (load_store_address_x >=  32'h0) 
+                            && (load_store_address_x <=  32'h7fffffff)
+  
+                               
+
+
+  
+                               
+
+
+                     ;
+ 
+
+	  
+   assign wb_select_x =     1'b1
+  
+
+                        && !dcache_select_x 
+ 
+
+  
+                         
+
+
+  
+                         
+
+
+                     ;
+
+
+always @(*)
+begin
+    case (size_x)
+     2'b00:  store_data_x = {4{store_operand_x[7:0]}};
+     2'b11: store_data_x = {2{store_operand_x[15:0]}};
+     2'b10:  store_data_x = store_operand_x;    
+    default:          store_data_x = { 32{1'bx}};
+    endcase
+end
+
+
+always @(*)
+begin
+    casez ({size_x, load_store_address_x[1:0]})
+    { 2'b00, 2'b11}:  byte_enable_x = 4'b0001;
+    { 2'b00, 2'b10}:  byte_enable_x = 4'b0010;
+    { 2'b00, 2'b01}:  byte_enable_x = 4'b0100;
+    { 2'b00, 2'b00}:  byte_enable_x = 4'b1000;
+    { 2'b11, 2'b1?}: byte_enable_x = 4'b0011;
+    { 2'b11, 2'b0?}: byte_enable_x = 4'b1100;
+    { 2'b10, 2'b??}:  byte_enable_x = 4'b1111;
+    default:                   byte_enable_x = 4'bxxxx;
+    endcase
+end
+
+  
+      
+            
+
+           
+	                            
+   
+   
+               
+        
+
+
+   
+  
+
+   
+   
+   
+         
+                    
+                       
+                      
+                        
+                     
+                        
+  
+   
+         
+                    
+                       
+                      
+                      
+  
+ 
+
+    
+   
+         
+                    
+                       
+                      
+                      
+  
+
+   
+   assign data_m = wb_select_m ==  1'b1 
+                   ? wb_data_m 
+                   : dcache_data_m;
+   
+
+  
+
+ 
+  
+   
+   
+         
+                     
+                      
+                      
+                      
+  
+   
+         
+                     
+                    
+  
+ 
+   
+   
+         
+                     
+                    
+
+  
+   
+      
+  
+ 
+
+
+
+
+always @(*)
+begin
+    casez ({size_w, load_store_address_w[1:0]})
+    { 2'b00, 2'b11}:  load_data_w = {{24{sign_extend_w & data_w[7]}}, data_w[7:0]};
+    { 2'b00, 2'b10}:  load_data_w = {{24{sign_extend_w & data_w[15]}}, data_w[15:8]};
+    { 2'b00, 2'b01}:  load_data_w = {{24{sign_extend_w & data_w[23]}}, data_w[23:16]};
+    { 2'b00, 2'b00}:  load_data_w = {{24{sign_extend_w & data_w[31]}}, data_w[31:24]};
+    { 2'b11, 2'b1?}: load_data_w = {{16{sign_extend_w & data_w[15]}}, data_w[15:0]};
+    { 2'b11, 2'b0?}: load_data_w = {{16{sign_extend_w & data_w[31]}}, data_w[31:16]};
+    { 2'b10, 2'b??}:  load_data_w = data_w;
+    default:                   load_data_w = { 32{1'bx}};
+    endcase
+end
+
+
+assign d_bte_o =  2'b00;
+
+  
+                
+
+generate 
+    case (bytes_per_line)
+    4:
+    begin
+assign first_cycle_type =  3'b111;
+assign next_cycle_type =  3'b111;
+assign last_word =  1'b1;
+assign first_address = {dcache_refill_address[ 32-1:2], 2'b00};
+    end
+    8:
+    begin
+assign first_cycle_type =  3'b010;
+assign next_cycle_type =  3'b111;
+assign last_word = (&d_adr_o[addr_offset_msb:addr_offset_lsb]) == 1'b1;
+assign first_address = {dcache_refill_address[ 32-1:addr_offset_msb+1], {addr_offset_width{1'b0}}, 2'b00};
+    end
+    16:
+    begin
+assign first_cycle_type =  3'b010;
+assign next_cycle_type = d_adr_o[addr_offset_msb] == 1'b1 ?  3'b111 :  3'b010;
+assign last_word = (&d_adr_o[addr_offset_msb:addr_offset_lsb]) == 1'b1;
+assign first_address = {dcache_refill_address[ 32-1:addr_offset_msb+1], {addr_offset_width{1'b0}}, 2'b00};
+    end
+    endcase
+endgenerate
+ 
+
+
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        d_cyc_o <=  1'b0;
+        d_stb_o <=  1'b0;
+        d_dat_o <= { 32{1'b0}};
+        d_adr_o <= { 32{1'b0}};
+        d_sel_o <= { 4{ 1'b0}};
+        d_we_o <=  1'b0;
+        d_cti_o <=  3'b111;
+        d_lock_o <=  1'b0;
+        wb_data_m <= { 32{1'b0}};
+        wb_load_complete <=  1'b0;
+        stall_wb_load <=  1'b0;
+  
+                
+        dcache_refill_ready <=  1'b0;
+ 
+                
+    end
+    else 
+    begin
+  
+ 
+        
+        dcache_refill_ready <=  1'b0;
+ 
+                
+        
+        if (d_cyc_o ==  1'b1)
+        begin
+            
+            if ((d_ack_i ==  1'b1) || (d_err_i ==  1'b1))
+            begin
+  
+                
+                if ((dcache_refilling ==  1'b1) && (!last_word))
+                begin
+                    
+                    d_adr_o[addr_offset_msb:addr_offset_lsb] <= d_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
+                end
+                else
+ 
+                
+                begin
+                    
+                    d_cyc_o <=  1'b0;
+                    d_stb_o <=  1'b0;
+                    d_lock_o <=  1'b0;
+                end
+  
+    
+                d_cti_o <= next_cycle_type;
+                
+                dcache_refill_ready <= dcache_refilling;
+ 
+
+                
+                wb_data_m <= d_dat_i;
+                
+                wb_load_complete <= !d_we_o;
+            end
+            
+        end
+        else 
+        begin
+  
+                
+            if (dcache_refill_request ==  1'b1)
+            begin
+                
+                d_adr_o <= first_address;
+                d_cyc_o <=  1'b1;
+                d_sel_o <= { 32/8{ 1'b1}};
+                d_stb_o <=  1'b1;                
+                d_we_o <=  1'b0;
+                d_cti_o <= first_cycle_type;
+                
+            end
+            else 
+ 
+            
+                 if (   (store_q_m ==  1'b1)
+                     && (stall_m ==  1'b0)
+  
+                        
+
+
+  
+		        
+
+			
+                    )
+            begin
+                
+                d_dat_o <= store_data_m;
+                d_adr_o <= load_store_address_m;
+                d_cyc_o <=  1'b1;
+                d_sel_o <= byte_enable_m;
+                d_stb_o <=  1'b1;
+                d_we_o <=  1'b1;
+                d_cti_o <=  3'b111;
+            end        
+            else if (   (load_q_m ==  1'b1) 
+                     && (wb_select_m ==  1'b1) 
+                     && (wb_load_complete ==  1'b0)
+                     
+                    )
+            begin
+                
+                stall_wb_load <=  1'b0;
+                d_adr_o <= load_store_address_m;
+                d_cyc_o <=  1'b1;
+                d_sel_o <= byte_enable_m;
+                d_stb_o <=  1'b1;
+                d_we_o <=  1'b0;
+                d_cti_o <=  3'b111;
+            end
+        end
+        
+        if (stall_m ==  1'b0)
+            wb_load_complete <=  1'b0;
+        
+        if ((load_q_x ==  1'b1) && (wb_select_x ==  1'b1) && (stall_x ==  1'b0))
+            stall_wb_load <=  1'b1;
+        
+        if ((kill_m ==  1'b1) || (exception_m ==  1'b1))
+            stall_wb_load <=  1'b0;
+    end
+end
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        sign_extend_m <=  1'b0;
+        size_m <= 2'b00;
+        byte_enable_m <=  1'b0;
+        store_data_m <= { 32{1'b0}};
+  
+
+        dcache_select_m <=  1'b0;
+ 
+
+  
+          
+
+
+  
+          
+			    
+
+
+        wb_select_m <=  1'b0;        
+    end
+    else
+    begin
+        if (stall_m ==  1'b0)
+        begin
+            sign_extend_m <= sign_extend_x;
+            size_m <= size_x;
+            byte_enable_m <= byte_enable_x;    
+            store_data_m <= store_data_x;
+  
+
+            dcache_select_m <= dcache_select_x;
+ 
+
+  
+              
+
+
+  
+              
+			    
+
+
+            wb_select_m <= wb_select_x;
+        end
+    end
+end
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        size_w <= 2'b00;
+        data_w <= { 32{1'b0}};
+        sign_extend_w <=  1'b0;
+    end
+    else
+    begin
+        size_w <= size_m;
+
+  
+         
+
+
+        data_w <= data_m;
+
+        sign_extend_w <= sign_extend_m;
+    end
+end
+
+
+
+
+
+
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_decoder_full_debug (
+    
+    instruction,
+    
+    d_result_sel_0,
+    d_result_sel_1,        
+    x_result_sel_csr,
+  
+
+    x_result_sel_mc_arith,
+ 
+    
+      
+    
+
+
+  
+
+    x_result_sel_sext,
+ 
+    
+    x_result_sel_logic,
+  
+    
+
+
+    x_result_sel_add,
+    m_result_sel_compare,
+  
+
+    m_result_sel_shift,  
+ 
+    
+    w_result_sel_load,
+  
+
+    w_result_sel_mul,
+ 
+
+    x_bypass_enable,
+    m_bypass_enable,
+    read_enable_0,
+    read_idx_0,
+    read_enable_1,
+    read_idx_1,
+    write_enable,
+    write_idx,
+    immediate,
+    branch_offset,
+    load,
+    store,
+    size,
+    sign_extend,
+    adder_op,
+    logic_op,
+  
+
+    direction,
+ 
+
+  
+    
+    
+
+
+  
+    
+
+
+  
+
+    divide,
+    modulus,
+ 
+
+    branch,
+    branch_reg,
+    condition,
+    bi_conditional,
+    bi_unconditional,
+  
+
+    break_opcode,
+ 
+
+    scall,
+    eret,
+  
+
+    bret,
+ 
+
+  
+    
+
+
+    csr_write_enable
+    );
+
+
+
+
+
+input [ (32-1):0] instruction;       
+
+
+
+
+
+output [ 0:0] d_result_sel_0;
+reg    [ 0:0] d_result_sel_0;
+output [ 1:0] d_result_sel_1;
+reg    [ 1:0] d_result_sel_1;
+output x_result_sel_csr;
+reg    x_result_sel_csr;
+  
+
+output x_result_sel_mc_arith;
+reg    x_result_sel_mc_arith;
+ 
+
+      
+ 
+    
+
+
+  
+
+output x_result_sel_sext;
+reg    x_result_sel_sext;
+ 
+
+output x_result_sel_logic;
+reg    x_result_sel_logic;
+  
+ 
+    
+
+
+output x_result_sel_add;
+reg    x_result_sel_add;
+output m_result_sel_compare;
+reg    m_result_sel_compare;
+  
+
+output m_result_sel_shift;
+reg    m_result_sel_shift;
+ 
+
+output w_result_sel_load;
+reg    w_result_sel_load;
+  
+
+output w_result_sel_mul;
+reg    w_result_sel_mul;
+ 
+
+output x_bypass_enable;
+wire   x_bypass_enable;
+output m_bypass_enable;
+wire   m_bypass_enable;
+output read_enable_0;
+wire   read_enable_0;
+output [ (5-1):0] read_idx_0;
+wire   [ (5-1):0] read_idx_0;
+output read_enable_1;
+wire   read_enable_1;
+output [ (5-1):0] read_idx_1;
+wire   [ (5-1):0] read_idx_1;
+output write_enable;
+wire   write_enable;
+output [ (5-1):0] write_idx;
+wire   [ (5-1):0] write_idx;
+output [ (32-1):0] immediate;
+wire   [ (32-1):0] immediate;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset;
+wire   [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset;
+output load;
+wire   load;
+output store;
+wire   store;
+output [ 1:0] size;
+wire   [ 1:0] size;
+output sign_extend;
+wire   sign_extend;
+output adder_op;
+wire   adder_op;
+output [ 3:0] logic_op;
+wire   [ 3:0] logic_op;
+  
+
+output direction;
+wire   direction;
+ 
+
+  
+ 
+   
+ 
+   
+
+
+  
+ 
+   
+
+
+  
+
+output divide;
+wire   divide;
+output modulus;
+wire   modulus;
+ 
+
+output branch;
+wire   branch;
+output branch_reg;
+wire   branch_reg;
+output [ (3-1):0] condition;
+wire   [ (3-1):0] condition;
+output bi_conditional;
+wire bi_conditional;
+output bi_unconditional;
+wire bi_unconditional;
+  
+
+output break_opcode;
+wire   break_opcode;
+ 
+
+output scall;
+wire   scall;
+output eret;
+wire   eret;
+  
+
+output bret;
+wire   bret;
+ 
+
+  
+  
+    
+
+
+output csr_write_enable;
+wire   csr_write_enable;
+
+
+
+
+
+wire [ (32-1):0] extended_immediate;       
+wire [ (32-1):0] high_immediate;           
+wire [ (32-1):0] call_immediate;           
+wire [ (32-1):0] branch_immediate;         
+wire sign_extend_immediate;                     
+wire select_high_immediate;                     
+wire select_call_immediate;                     
+
+wire op_add;
+wire op_and;
+wire op_andhi;
+wire op_b;
+wire op_bi;
+wire op_be;
+wire op_bg;
+wire op_bge;
+wire op_bgeu;
+wire op_bgu;
+wire op_bne;
+wire op_call;
+wire op_calli;
+wire op_cmpe;
+wire op_cmpg;
+wire op_cmpge;
+wire op_cmpgeu;
+wire op_cmpgu;
+wire op_cmpne;
+  
+
+wire op_divu;
+ 
+
+wire op_lb;
+wire op_lbu;
+wire op_lh;
+wire op_lhu;
+wire op_lw;
+  
+
+wire op_modu;
+ 
+
+  
+
+wire op_mul;
+ 
+
+wire op_nor;
+wire op_or;
+wire op_orhi;
+wire op_raise;
+wire op_rcsr;
+wire op_sb;
+  
+
+wire op_sextb;
+wire op_sexth;
+ 
+
+wire op_sh;
+  
+
+wire op_sl;
+ 
+
+wire op_sr;
+wire op_sru;
+wire op_sub;
+wire op_sw;
+  
+ 
+
+
+wire op_wcsr;
+wire op_xnor;
+wire op_xor;
+
+wire arith;
+wire logical;
+wire cmp;
+wire bra;
+wire call;
+  
+
+wire shift;
+ 
+
+  
+ 
+
+
+  
+
+wire sext;
+ 
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+assign op_add    = instruction[ 30:26] ==  5'b01101;
+assign op_and    = instruction[ 30:26] ==  5'b01000;
+assign op_andhi  = instruction[ 31:26] ==  6'b011000;
+assign op_b      = instruction[ 31:26] ==  6'b110000;
+assign op_bi     = instruction[ 31:26] ==  6'b111000;
+assign op_be     = instruction[ 31:26] ==  6'b010001;
+assign op_bg     = instruction[ 31:26] ==  6'b010010;
+assign op_bge    = instruction[ 31:26] ==  6'b010011;
+assign op_bgeu   = instruction[ 31:26] ==  6'b010100;
+assign op_bgu    = instruction[ 31:26] ==  6'b010101;
+assign op_bne    = instruction[ 31:26] ==  6'b010111;
+assign op_call   = instruction[ 31:26] ==  6'b110110;
+assign op_calli  = instruction[ 31:26] ==  6'b111110;
+assign op_cmpe   = instruction[ 30:26] ==  5'b11001;
+assign op_cmpg   = instruction[ 30:26] ==  5'b11010;
+assign op_cmpge  = instruction[ 30:26] ==  5'b11011;
+assign op_cmpgeu = instruction[ 30:26] ==  5'b11100;
+assign op_cmpgu  = instruction[ 30:26] ==  5'b11101;
+assign op_cmpne  = instruction[ 30:26] ==  5'b11111;
+  
+
+assign op_divu   = instruction[ 31:26] ==  6'b100011;
+ 
+
+assign op_lb     = instruction[ 31:26] ==  6'b000100;
+assign op_lbu    = instruction[ 31:26] ==  6'b010000;
+assign op_lh     = instruction[ 31:26] ==  6'b000111;
+assign op_lhu    = instruction[ 31:26] ==  6'b001011;
+assign op_lw     = instruction[ 31:26] ==  6'b001010;
+  
+
+assign op_modu   = instruction[ 31:26] ==  6'b110001;
+ 
+
+  
+
+assign op_mul    = instruction[ 30:26] ==  5'b00010;
+ 
+
+assign op_nor    = instruction[ 30:26] ==  5'b00001;
+assign op_or     = instruction[ 30:26] ==  5'b01110;
+assign op_orhi   = instruction[ 31:26] ==  6'b011110;
+assign op_raise  = instruction[ 31:26] ==  6'b101011;
+assign op_rcsr   = instruction[ 31:26] ==  6'b100100;
+assign op_sb     = instruction[ 31:26] ==  6'b001100;
+  
+
+assign op_sextb  = instruction[ 31:26] ==  6'b101100;
+assign op_sexth  = instruction[ 31:26] ==  6'b110111;
+ 
+
+assign op_sh     = instruction[ 31:26] ==  6'b000011;
+  
+
+assign op_sl     = instruction[ 30:26] ==  5'b01111;      
+ 
+
+assign op_sr     = instruction[ 30:26] ==  5'b00101;
+assign op_sru    = instruction[ 30:26] ==  5'b00000;
+assign op_sub    = instruction[ 31:26] ==  6'b110010;
+assign op_sw     = instruction[ 31:26] ==  6'b010110;
+  
+       
+
+
+assign op_wcsr   = instruction[ 31:26] ==  6'b110100;
+assign op_xnor   = instruction[ 30:26] ==  5'b01001;
+assign op_xor    = instruction[ 30:26] ==  5'b00110;
+
+
+assign arith = op_add | op_sub;
+assign logical = op_and | op_andhi | op_nor | op_or | op_orhi | op_xor | op_xnor;
+assign cmp = op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne;
+assign bi_conditional = op_be | op_bg | op_bge | op_bgeu  | op_bgu | op_bne;
+assign bi_unconditional = op_bi;
+assign bra = op_b | bi_unconditional | bi_conditional;
+assign call = op_call | op_calli;
+  
+
+assign shift = op_sl | op_sr | op_sru;
+ 
+
+  
+     
+
+
+  
+   
+     
+
+
+  
+
+assign sext = op_sextb | op_sexth;
+ 
+
+  
+   
+
+
+  
+
+assign divide = op_divu; 
+assign modulus = op_modu;
+ 
+
+assign load = op_lb | op_lbu | op_lh | op_lhu | op_lw;
+assign store = op_sb | op_sh | op_sw;
+
+
+always @(*)
+begin
+    
+    if (call) 
+        d_result_sel_0 =  1'b1;
+    else 
+        d_result_sel_0 =  1'b0;
+    if (call) 
+        d_result_sel_1 =  2'b00;         
+    else if ((instruction[31] == 1'b0) && !bra) 
+        d_result_sel_1 =  2'b10;
+    else
+        d_result_sel_1 =  2'b01; 
+    
+    x_result_sel_csr =  1'b0;
+  
+
+    x_result_sel_mc_arith =  1'b0;
+ 
+
+  
+      
+
+
+  
+
+    x_result_sel_sext =  1'b0;
+ 
+
+    x_result_sel_logic =  1'b0;
+          
+      
+
+
+    x_result_sel_add =  1'b0;
+    if (op_rcsr)
+        x_result_sel_csr =  1'b1;
+  
+    
+  
+         
+          
+
+
+  
+
+    else if (divide | modulus)
+        x_result_sel_mc_arith =  1'b1;        
+ 
+
+  
+      
+                      
+
+
+ 
+
+  
+      
+                  
+
+
+  
+
+    else if (sext)
+        x_result_sel_sext =  1'b1;
+ 
+        
+    else if (logical) 
+        x_result_sel_logic =  1'b1;
+          
+      
+          
+
+
+    else 
+        x_result_sel_add =  1'b1;        
+    
+    
+
+    m_result_sel_compare = cmp;
+  
+
+    m_result_sel_shift = shift;
+ 
+
+
+    
+    w_result_sel_load = load;
+  
+
+    w_result_sel_mul = op_mul; 
+ 
+
+end
+
+
+assign x_bypass_enable =  arith 
+                        | logical
+  
+                         
+                         
+
+                        
+  
+                         
+
+
+  
+
+                        | divide
+                        | modulus
+ 
+
+  
+                         
+
+                  
+  
+
+                        | sext 
+ 
+                        
+  
+                         
+
+
+                        | op_rcsr
+                        ;
+
+assign m_bypass_enable = x_bypass_enable 
+  
+
+                        | shift
+ 
+
+                        | cmp
+                        ;
+
+assign read_enable_0 = ~(op_bi | op_calli);
+assign read_idx_0 = instruction[25:21];
+
+assign read_enable_1 = ~(op_bi | op_calli | load);
+assign read_idx_1 = instruction[20:16];
+
+assign write_enable = ~(bra | op_raise | store | op_wcsr);
+assign write_idx = call
+                    ? 5'd29
+                    : instruction[31] == 1'b0 
+                        ? instruction[20:16] 
+                        : instruction[15:11];
+                        
+
+assign size = instruction[27:26];
+
+assign sign_extend = instruction[28];                      
+
+assign adder_op = op_sub | op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne | bra;
+
+assign logic_op = instruction[29:26];
+  
+
+
+assign direction = instruction[29];
+ 
+
+
+assign branch = bra | call;
+assign branch_reg = op_call | op_b;
+assign condition = instruction[28:26];      
+  
+
+assign break_opcode = op_raise & ~instruction[2];
+ 
+
+assign scall = op_raise & instruction[2];
+assign eret = op_b & (instruction[25:21] == 5'd30);
+  
+
+assign bret = op_b & (instruction[25:21] == 5'd31);
+ 
+
+  
+
+   
+
+
+
+assign csr_write_enable = op_wcsr;
+
+
+
+assign sign_extend_immediate = ~(op_and | op_cmpgeu | op_cmpgu | op_nor | op_or | op_xnor | op_xor);
+assign select_high_immediate = op_andhi | op_orhi;
+assign select_call_immediate = instruction[31];
+
+assign high_immediate = {instruction[15:0], 16'h0000};
+assign extended_immediate = {{16{sign_extend_immediate & instruction[15]}}, instruction[15:0]};
+assign call_immediate = {{6{instruction[25]}}, instruction[25:0]};
+assign branch_immediate = {{16{instruction[15]}}, instruction[15:0]};
+
+assign immediate = select_high_immediate ==  1'b1 
+                        ? high_immediate 
+                        : extended_immediate;
+   
+assign branch_offset = select_call_immediate ==  1'b1   
+                        ? (call_immediate[ (clogb2(32'h7fffffff-32'h0)-2)-1:0])
+                        : (branch_immediate[ (clogb2(32'h7fffffff-32'h0)-2)-1:0]);
+    
+endmodule 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_icache_full_debug ( 
+    
+    clk_i,
+    rst_i,    
+    stall_a,
+    stall_f,
+    address_a,
+    address_f,
+    read_enable_f,
+    refill_ready,
+    refill_data,
+    iflush,
+  
+    
+
+
+    valid_d,
+    branch_predict_taken_d,
+    
+    stall_request,
+    restart_request,
+    refill_request,
+    refill_address,
+    refilling,
+    inst
+    );
+
+
+
+
+
+parameter associativity = 1;                            
+parameter sets = 512;                                   
+parameter bytes_per_line = 16;                          
+parameter base_address = 0;                             
+parameter limit = 0;                                    
+
+localparam addr_offset_width = clogb2(bytes_per_line)-1-2;
+localparam addr_set_width = clogb2(sets)-1;
+localparam addr_offset_lsb = 2;
+localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
+localparam addr_set_lsb = (addr_offset_msb+1);
+localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
+localparam addr_tag_lsb = (addr_set_msb+1);
+localparam addr_tag_msb = clogb2( 32'h7fffffff- 32'h0)-1;
+localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
+
+
+
+
+
+input clk_i;                                        
+input rst_i;                                        
+
+input stall_a;                                      
+input stall_f;                                      
+
+input valid_d;                                      
+input branch_predict_taken_d;                       
+   
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] address_a;                     
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] address_f;                     
+input read_enable_f;                                
+
+input refill_ready;                                 
+input [ (32-1):0] refill_data;          
+
+input iflush;                                       
+  
+                                      
+
+
+   
+
+
+
+
+output stall_request;                               
+wire   stall_request;
+output restart_request;                             
+reg    restart_request;
+output refill_request;                              
+wire   refill_request;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] refill_address;               
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] refill_address;               
+output refilling;                                   
+reg    refilling;
+output [ (32-1):0] inst;                
+wire   [ (32-1):0] inst;
+
+
+
+
+
+wire enable;
+wire [0:associativity-1] way_mem_we;
+wire [ (32-1):0] way_data[0:associativity-1];
+wire [ ((addr_tag_width+1)-1):1] way_tag[0:associativity-1];
+wire [0:associativity-1] way_valid;
+wire [0:associativity-1] way_match;
+wire miss;
+
+wire [ (addr_set_width-1):0] tmem_read_address;
+wire [ (addr_set_width-1):0] tmem_write_address;
+wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_read_address;
+wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_write_address;
+wire [ ((addr_tag_width+1)-1):0] tmem_write_data;
+
+reg [ 3:0] state;
+wire flushing;
+wire check;
+wire refill;
+
+reg [associativity-1:0] refill_way_select;
+reg [ addr_offset_msb:addr_offset_lsb] refill_offset;
+wire last_refill;
+reg [ (addr_set_width-1):0] flush_set;
+
+genvar i;
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+   generate
+      for (i = 0; i < associativity; i = i + 1)
+	begin : memories
+	   
+	   lm32_ram 
+	     #(
+	       
+	       .data_width                 (32),
+	       .address_width              ( (addr_offset_width+addr_set_width))
+
+) 
+	   way_0_data_ram 
+	     (
+	      
+	      .read_clk                   (clk_i),
+	      .write_clk                  (clk_i),
+	      .reset                      (rst_i),
+	      .read_address               (dmem_read_address),
+	      .enable_read                (enable),
+	      .write_address              (dmem_write_address),
+	      .enable_write               ( 1'b1),
+	      .write_enable               (way_mem_we[i]),
+	      .write_data                 (refill_data),    
+	      
+	      .read_data                  (way_data[i])
+	      );
+	   
+	   lm32_ram 
+	     #(
+	       
+	       .data_width                 ( (addr_tag_width+1)),
+	       .address_width              ( addr_set_width)
+
+	       ) 
+	   way_0_tag_ram 
+	     (
+	      
+	      .read_clk                   (clk_i),
+	      .write_clk                  (clk_i),
+	      .reset                      (rst_i),
+	      .read_address               (tmem_read_address),
+	      .enable_read                (enable),
+	      .write_address              (tmem_write_address),
+	      .enable_write               ( 1'b1),
+	      .write_enable               (way_mem_we[i] | flushing),
+	      .write_data                 (tmem_write_data),
+	      
+	      .read_data                  ({way_tag[i], way_valid[i]})
+	      );
+	   
+	end
+endgenerate
+
+
+
+
+
+
+generate
+    for (i = 0; i < associativity; i = i + 1)
+    begin : match
+assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_f[ addr_tag_msb:addr_tag_lsb],  1'b1});
+    end
+endgenerate
+
+
+generate
+    if (associativity == 1)
+    begin : inst_1
+assign inst = way_match[0] ? way_data[0] : 32'b0;
+    end
+    else if (associativity == 2)
+	 begin : inst_2
+assign inst = way_match[0] ? way_data[0] : (way_match[1] ? way_data[1] : 32'b0);
+    end
+endgenerate
+
+
+generate 
+    if (bytes_per_line > 4)
+assign dmem_write_address = {refill_address[ addr_set_msb:addr_set_lsb], refill_offset};
+    else
+assign dmem_write_address = refill_address[ addr_set_msb:addr_set_lsb];
+endgenerate
+    
+assign dmem_read_address = address_a[ addr_set_msb:addr_offset_lsb];
+
+
+assign tmem_read_address = address_a[ addr_set_msb:addr_set_lsb];
+assign tmem_write_address = flushing 
+                                ? flush_set
+                                : refill_address[ addr_set_msb:addr_set_lsb];
+
+
+generate 
+    if (bytes_per_line > 4)                            
+assign last_refill = refill_offset == {addr_offset_width{1'b1}};
+    else
+assign last_refill =  1'b1;
+endgenerate
+
+
+assign enable = (stall_a ==  1'b0);
+
+
+generate
+    if (associativity == 1) 
+    begin : we_1     
+assign way_mem_we[0] = (refill_ready ==  1'b1);
+    end
+    else
+    begin : we_2
+assign way_mem_we[0] = (refill_ready ==  1'b1) && (refill_way_select[0] ==  1'b1);
+assign way_mem_we[1] = (refill_ready ==  1'b1) && (refill_way_select[1] ==  1'b1);
+    end
+endgenerate                     
+
+
+assign tmem_write_data[ 0] = last_refill & !flushing;
+assign tmem_write_data[ ((addr_tag_width+1)-1):1] = refill_address[ addr_tag_msb:addr_tag_lsb];
+
+
+assign flushing = |state[1:0];
+assign check = state[2];
+assign refill = state[3];
+
+assign miss = (~(|way_match)) && (read_enable_f ==  1'b1) && (stall_f ==  1'b0) && !(valid_d && branch_predict_taken_d);
+assign stall_request = (check ==  1'b0);
+assign refill_request = (refill ==  1'b1);
+                      
+
+
+
+
+
+generate
+    if (associativity >= 2) 
+    begin : way_select      
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
+    else
+    begin        
+        if (miss ==  1'b1)
+            refill_way_select <= {refill_way_select[0], refill_way_select[1]};
+    end
+end
+    end
+endgenerate
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        refilling <=  1'b0;
+    else
+        refilling <= refill;
+end
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        state <=  4'b0001;
+        flush_set <= { addr_set_width{1'b1}};
+        refill_address <= { (clogb2(32'h7fffffff-32'h0)-2){1'bx}};
+        restart_request <=  1'b0;
+    end
+    else 
+    begin
+        case (state)
+
+        
+         4'b0001:
+        begin            
+            if (flush_set == { addr_set_width{1'b0}})
+                state <=  4'b0100;
+            flush_set <= flush_set - 1'b1;
+        end
+
+        
+         4'b0010:
+        begin            
+            if (flush_set == { addr_set_width{1'b0}})
+  
+	       
+                  
+	      
+
+
+		state <=  4'b0100;
+	   
+            flush_set <= flush_set - 1'b1;
+        end
+        
+        
+         4'b0100:
+        begin            
+            if (stall_a ==  1'b0)
+                restart_request <=  1'b0;
+            if (iflush ==  1'b1)
+            begin
+                refill_address <= address_f;
+                state <=  4'b0010;
+            end
+            else if (miss ==  1'b1)
+            begin
+                refill_address <= address_f;
+                state <=  4'b1000;
+            end
+        end
+
+        
+         4'b1000:
+        begin            
+            if (refill_ready ==  1'b1)
+            begin
+                if (last_refill ==  1'b1)
+                begin
+                    restart_request <=  1'b1;
+                    state <=  4'b0100;
+                end
+            end
+        end
+
+        endcase        
+    end
+end
+
+generate 
+    if (bytes_per_line > 4)
+    begin
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        refill_offset <= {addr_offset_width{1'b0}};
+    else 
+    begin
+        case (state)
+        
+        
+         4'b0100:
+        begin            
+            if (iflush ==  1'b1)
+                refill_offset <= {addr_offset_width{1'b0}};
+            else if (miss ==  1'b1)
+                refill_offset <= {addr_offset_width{1'b0}};
+        end
+
+        
+         4'b1000:
+        begin            
+            if (refill_ready ==  1'b1)
+                refill_offset <= refill_offset + 1'b1;
+        end
+
+        endcase        
+    end
+end
+    end
+endgenerate
+   
+endmodule
+
+ 
+
+
+
+
+
+
+
+
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+
+
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+
+
+								 
+  
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+  
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+ 
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+ 
+
+     
+    
+   
+  
+
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+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
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+ 
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+ 
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+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
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+ 
+
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+
+
+
+                   
+             
+               
+
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+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
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+  
+
+
+  
+
+  
+
+  
+
+  
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+  
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+  
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+  
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+  
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+  
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_dcache_full_debug ( 
+    
+    clk_i,
+    rst_i,    
+    stall_a,
+    stall_x,
+    stall_m,
+    address_x,
+    address_m,
+    load_q_m,
+    store_q_m,
+    store_data,
+    store_byte_select,
+    refill_ready,
+    refill_data,
+    dflush,
+    
+    stall_request,
+    restart_request,
+    refill_request,
+    refill_address,
+    refilling,
+    load_data
+    );
+
+
+
+
+
+parameter associativity = 1;                            
+parameter sets = 512;                                   
+parameter bytes_per_line = 16;                          
+parameter base_address = 0;                             
+parameter limit = 0;                                    
+
+localparam addr_offset_width = clogb2(bytes_per_line)-1-2;
+localparam addr_set_width = clogb2(sets)-1;
+localparam addr_offset_lsb = 2;
+localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
+localparam addr_set_lsb = (addr_offset_msb+1);
+localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
+localparam addr_tag_lsb = (addr_set_msb+1);
+localparam addr_tag_msb = clogb2( 32'h7fffffff- 32'h0)-1;
+localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
+
+
+
+
+
+input clk_i;                                            
+input rst_i;                                            
+
+input stall_a;                                          
+input stall_x;                                          
+input stall_m;                                          
+
+input [ (32-1):0] address_x;                       
+input [ (32-1):0] address_m;                       
+input load_q_m;                                         
+input store_q_m;                                        
+input [ (32-1):0] store_data;                      
+input [ (4-1):0] store_byte_select;        
+
+input refill_ready;                                     
+input [ (32-1):0] refill_data;                     
+
+input dflush;                                           
+
+
+
+
+
+output stall_request;                                   
+wire   stall_request;
+output restart_request;                                 
+reg    restart_request;
+output refill_request;                                  
+reg    refill_request;
+output [ (32-1):0] refill_address;                 
+reg    [ (32-1):0] refill_address;
+output refilling;                                       
+reg    refilling;
+output [ (32-1):0] load_data;                      
+wire   [ (32-1):0] load_data;
+
+
+
+
+
+wire read_port_enable;                                  
+wire write_port_enable;                                 
+wire [0:associativity-1] way_tmem_we;                   
+wire [0:associativity-1] way_dmem_we;                   
+wire [ (32-1):0] way_data[0:associativity-1];      
+wire [ ((addr_tag_width+1)-1):1] way_tag[0:associativity-1];
+wire [0:associativity-1] way_valid;                     
+wire [0:associativity-1] way_match;                     
+wire miss;                                              
+
+wire [ (addr_set_width-1):0] tmem_read_address;        
+wire [ (addr_set_width-1):0] tmem_write_address;       
+wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_read_address;        
+wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_write_address;       
+wire [ ((addr_tag_width+1)-1):0] tmem_write_data;               
+reg [ (32-1):0] dmem_write_data;                   
+
+reg [ 2:0] state;                         
+wire flushing;                                          
+wire check;                                             
+wire refill;                                            
+
+wire valid_store;                                       
+reg [associativity-1:0] refill_way_select;              
+reg [ addr_offset_msb:addr_offset_lsb] refill_offset;           
+wire last_refill;                                       
+reg [ (addr_set_width-1):0] flush_set;                 
+
+genvar i, j;
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+   generate
+      for (i = 0; i < associativity; i = i + 1)    
+	begin : memories
+	   
+           if ( (addr_offset_width+addr_set_width) < 11)
+             begin : data_memories
+		lm32_ram 
+		  #(
+		    
+		    .data_width (32),
+		    .address_width ( (addr_offset_width+addr_set_width))
+
+		    ) way_0_data_ram 
+		    (
+		     
+		     .read_clk (clk_i),
+		     .write_clk (clk_i),
+		     .reset (rst_i),
+		     .read_address (dmem_read_address),
+		     .enable_read (read_port_enable),
+		     .write_address (dmem_write_address),
+		     .enable_write (write_port_enable),
+		     .write_enable (way_dmem_we[i]),
+		     .write_data (dmem_write_data),    
+		     
+		     .read_data (way_data[i])
+		     );    
+             end
+           else
+             begin
+		for (j = 0; j < 4; j = j + 1)    
+		  begin : byte_memories
+		     lm32_ram 
+		       #(
+			 
+			 .data_width (8),
+			 .address_width ( (addr_offset_width+addr_set_width))
+
+			 ) way_0_data_ram 
+			 (
+			  
+			  .read_clk (clk_i),
+			  .write_clk (clk_i),
+			  .reset (rst_i),
+			  .read_address (dmem_read_address),
+			  .enable_read (read_port_enable),
+			  .write_address (dmem_write_address),
+			  .enable_write (write_port_enable),
+			  .write_enable (way_dmem_we[i] & (store_byte_select[j] | refill)),
+			  .write_data (dmem_write_data[(j+1)*8-1:j*8]),    
+			  
+			  .read_data (way_data[i][(j+1)*8-1:j*8])
+			  );
+		  end
+             end
+	   
+	   
+	   lm32_ram 
+	     #(
+	       
+	       .data_width ( (addr_tag_width+1)),
+	       .address_width ( addr_set_width)
+
+	       ) way_0_tag_ram 
+	       (
+		
+		.read_clk (clk_i),
+		.write_clk (clk_i),
+		.reset (rst_i),
+		.read_address (tmem_read_address),
+		.enable_read (read_port_enable),
+		.write_address (tmem_write_address),
+		.enable_write ( 1'b1),
+		.write_enable (way_tmem_we[i]),
+		.write_data (tmem_write_data),
+		
+		.read_data ({way_tag[i], way_valid[i]})
+		);
+	end
+      
+   endgenerate
+
+
+
+
+
+
+generate
+    for (i = 0; i < associativity; i = i + 1)
+    begin : match
+assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_m[ addr_tag_msb:addr_tag_lsb],  1'b1});
+    end
+endgenerate
+
+
+generate
+    if (associativity == 1)    
+	 begin : data_1
+assign load_data = way_data[0];
+    end
+    else if (associativity == 2)
+	 begin : data_2
+assign load_data = way_match[0] ? way_data[0] : way_data[1]; 
+    end
+endgenerate
+
+generate
+    if ( (addr_offset_width+addr_set_width) < 11)
+    begin
+
+always @(*)
+begin
+    if (refill ==  1'b1)
+        dmem_write_data = refill_data;
+    else
+    begin
+        dmem_write_data[ 7:0] = store_byte_select[0] ? store_data[ 7:0] : load_data[ 7:0];
+        dmem_write_data[ 15:8] = store_byte_select[1] ? store_data[ 15:8] : load_data[ 15:8];
+        dmem_write_data[ 23:16] = store_byte_select[2] ? store_data[ 23:16] : load_data[ 23:16];
+        dmem_write_data[ 31:24] = store_byte_select[3] ? store_data[ 31:24] : load_data[ 31:24];
+    end
+end
+    end
+    else
+    begin
+
+always @(*)
+begin
+    if (refill ==  1'b1)
+        dmem_write_data = refill_data;
+    else
+        dmem_write_data = store_data;
+end
+    end
+endgenerate
+
+
+generate 
+     if (bytes_per_line > 4)
+assign dmem_write_address = (refill ==  1'b1) 
+                            ? {refill_address[ addr_set_msb:addr_set_lsb], refill_offset}
+                            : address_m[ addr_set_msb:addr_offset_lsb];
+    else
+assign dmem_write_address = (refill ==  1'b1) 
+                            ? refill_address[ addr_set_msb:addr_set_lsb]
+                            : address_m[ addr_set_msb:addr_offset_lsb];
+endgenerate
+assign dmem_read_address = address_x[ addr_set_msb:addr_offset_lsb];
+
+assign tmem_write_address = (flushing ==  1'b1)
+                            ? flush_set
+                            : refill_address[ addr_set_msb:addr_set_lsb];
+assign tmem_read_address = address_x[ addr_set_msb:addr_set_lsb];
+
+
+generate 
+    if (bytes_per_line > 4)                            
+assign last_refill = refill_offset == {addr_offset_width{1'b1}};
+    else
+assign last_refill =  1'b1;
+endgenerate
+
+
+assign read_port_enable = (stall_x ==  1'b0);
+assign write_port_enable = (refill_ready ==  1'b1) || !stall_m;
+
+
+assign valid_store = (store_q_m ==  1'b1) && (check ==  1'b1);
+
+
+generate
+    if (associativity == 1) 
+    begin : we_1     
+assign way_dmem_we[0] = (refill_ready ==  1'b1) || ((valid_store ==  1'b1) && (way_match[0] ==  1'b1));
+assign way_tmem_we[0] = (refill_ready ==  1'b1) || (flushing ==  1'b1);
+    end 
+    else 
+    begin : we_2
+assign way_dmem_we[0] = ((refill_ready ==  1'b1) && (refill_way_select[0] ==  1'b1)) || ((valid_store ==  1'b1) && (way_match[0] ==  1'b1));
+assign way_dmem_we[1] = ((refill_ready ==  1'b1) && (refill_way_select[1] ==  1'b1)) || ((valid_store ==  1'b1) && (way_match[1] ==  1'b1));
+assign way_tmem_we[0] = ((refill_ready ==  1'b1) && (refill_way_select[0] ==  1'b1)) || (flushing ==  1'b1);
+assign way_tmem_we[1] = ((refill_ready ==  1'b1) && (refill_way_select[1] ==  1'b1)) || (flushing ==  1'b1);
+    end
+endgenerate
+
+
+assign tmem_write_data[ 0] = ((last_refill ==  1'b1) || (valid_store ==  1'b1)) && (flushing ==  1'b0);
+assign tmem_write_data[ ((addr_tag_width+1)-1):1] = refill_address[ addr_tag_msb:addr_tag_lsb];
+
+
+assign flushing = state[0];
+assign check = state[1];
+assign refill = state[2];
+
+assign miss = (~(|way_match)) && (load_q_m ==  1'b1) && (stall_m ==  1'b0);
+assign stall_request = (check ==  1'b0);
+                      
+
+
+
+
+
+generate
+    if (associativity >= 2) 
+    begin : way_select      
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
+    else
+    begin        
+        if (refill_request ==  1'b1)
+            refill_way_select <= {refill_way_select[0], refill_way_select[1]};
+    end
+end
+    end 
+endgenerate   
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        refilling <=  1'b0;
+    else 
+        refilling <= refill;
+end
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        state <=  3'b001;
+        flush_set <= { addr_set_width{1'b1}};
+        refill_request <=  1'b0;
+        refill_address <= { 32{1'bx}};
+        restart_request <=  1'b0;
+    end
+    else 
+    begin
+        case (state)
+
+        
+         3'b001:
+        begin
+            if (flush_set == { addr_set_width{1'b0}})
+                state <=  3'b010;
+            flush_set <= flush_set - 1'b1;
+        end
+        
+        
+         3'b010:
+        begin
+            if (stall_a ==  1'b0)
+                restart_request <=  1'b0;
+            if (miss ==  1'b1)
+            begin
+                refill_request <=  1'b1;
+                refill_address <= address_m;
+                state <=  3'b100;
+            end
+            else if (dflush ==  1'b1)
+                state <=  3'b001;
+        end
+
+        
+         3'b100:
+        begin
+            refill_request <=  1'b0;
+            if (refill_ready ==  1'b1)
+            begin
+                if (last_refill ==  1'b1)
+                begin
+                    restart_request <=  1'b1;
+                    state <=  3'b010;
+                end
+            end
+        end
+        
+        endcase        
+    end
+end
+
+generate
+    if (bytes_per_line > 4)
+    begin
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        refill_offset <= {addr_offset_width{1'b0}};
+    else 
+    begin
+        case (state)
+        
+        
+         3'b010:
+        begin
+            if (miss ==  1'b1)
+                refill_offset <= {addr_offset_width{1'b0}};
+        end
+
+        
+         3'b100:
+        begin
+            if (refill_ready ==  1'b1)
+                refill_offset <= refill_offset + 1'b1;
+        end
+        
+        endcase        
+    end
+end
+    end
+endgenerate
+
+endmodule
+
+ 
+
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+                  
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+               
+                 
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+                    
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+                    
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+                
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+                
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+                  
+                    
+                   
+                  
+                   
+          
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+                   
+                     
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+                   
+                     
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+                    
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+                     
+                
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+                     
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+                     
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+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
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+                   
+             
+               
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+                  
+                    
+                 
+                   
+
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+                   
+                   
+                   
+                   
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+                  
+                  
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+                 
+                   
+               
+              
+          
+                   
+
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+                 
+                   
+                
+                
+                
+               
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+  
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+  
+
+  
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+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_debug_full_debug (
+    
+    clk_i, 
+    rst_i,
+    pc_x,
+    load_x,
+    store_x,
+    load_store_address_x,
+    csr_write_enable_x,
+    csr_write_data,
+    csr_x,
+  
+
+  
+
+    jtag_csr_write_enable,
+    jtag_csr_write_data,
+    jtag_csr,
+ 
+
+  
+   
+   
+   
+
+
+  
+
+
+		   
+  
+
+    eret_q_x,
+    bret_q_x,
+    stall_x,
+    exception_x,
+    q_x,
+  
+
+    dcache_refill_request,
+ 
+
+ 
+
+
+    
+  
+
+    dc_ss,
+ 
+
+    dc_re,
+    bp_match,
+    wp_match
+    );
+    
+
+
+
+
+parameter breakpoints = 0;                      
+parameter watchpoints = 0;                      
+
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;                      
+input load_x;                                   
+input store_x;                                  
+input [ (32-1):0] load_store_address_x;    
+input csr_write_enable_x;                       
+input [ (32-1):0] csr_write_data;          
+input [ (5-1):0] csr_x;                    
+  
+
+  
+
+input jtag_csr_write_enable;                    
+input [ (32-1):0] jtag_csr_write_data;     
+input [ (5-1):0] jtag_csr;                 
+ 
+
+     
+                          
+            
+                          
+
+
+ 
+
+
+
+  
+
+input eret_q_x;                                 
+input bret_q_x;                                 
+input stall_x;                                  
+input exception_x;                              
+input q_x;                                      
+  
+
+input dcache_refill_request;                    
+ 
+
+ 
+
+
+
+
+
+
+  
+
+output dc_ss;                                   
+reg    dc_ss;
+ 
+
+output dc_re;                                   
+reg    dc_re;
+output bp_match;                                
+wire   bp_match;        
+output wp_match;                                
+wire   wp_match;
+
+
+
+
+
+genvar i;                                       
+
+
+
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] bp_a[0:breakpoints-1];       
+reg bp_e[0:breakpoints-1];                      
+wire [0:breakpoints-1]bp_match_n;               
+
+reg [ 1:0] wpc_c[0:watchpoints-1];   
+reg [ (32-1):0] wp[0:watchpoints-1];       
+wire [0:watchpoints-1]wp_match_n;               
+
+wire debug_csr_write_enable;                    
+wire [ (32-1):0] debug_csr_write_data;     
+wire [ (5-1):0] debug_csr;                 
+
+  
+
+
+reg [ 2:0] state;           
+
+ 
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+generate
+    for (i = 0; i < breakpoints; i = i + 1)
+    begin : bp_comb
+assign bp_match_n[i] = ((bp_a[i] == pc_x) && (bp_e[i] ==  1'b1));
+    end
+endgenerate
+generate 
+  
+
+    if (breakpoints > 0) 
+assign bp_match = (|bp_match_n) || (state ==  3'b011);
+    else
+assign bp_match = state ==  3'b011;
+ 
+        
+   
+    
+   
+
+
+endgenerate    
+               
+
+generate 
+    for (i = 0; i < watchpoints; i = i + 1)
+    begin : wp_comb
+assign wp_match_n[i] = (wp[i] == load_store_address_x) && ((load_x & wpc_c[i][0]) | (store_x & wpc_c[i][1]));
+    end               
+endgenerate
+generate
+    if (watchpoints > 0) 
+assign wp_match = |wp_match_n;                
+    else
+assign wp_match =  1'b0;
+endgenerate
+                
+  
+                
+
+  
+
+assign debug_csr_write_enable = (csr_write_enable_x ==  1'b1) || (jtag_csr_write_enable ==  1'b1);
+assign debug_csr_write_data = jtag_csr_write_enable ==  1'b1 ? jtag_csr_write_data : csr_write_data;
+assign debug_csr = jtag_csr_write_enable ==  1'b1 ? jtag_csr : csr_x;
+ 
+
+   
+  
+         
+         
+         
+
+
+
+   
+ 
+   
+   
+   
+
+
+
+
+
+
+
+
+generate
+    for (i = 0; i < breakpoints; i = i + 1)
+    begin : bp_seq
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        bp_a[i] <= { (clogb2(32'h7fffffff-32'h0)-2){1'bx}};
+        bp_e[i] <=  1'b0;
+    end
+    else
+    begin
+        if ((debug_csr_write_enable ==  1'b1) && (debug_csr ==  5'h10 + i))
+        begin
+            bp_a[i] <= debug_csr_write_data[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2];
+            bp_e[i] <= debug_csr_write_data[0];
+        end
+    end
+end    
+    end
+endgenerate
+
+
+generate
+    for (i = 0; i < watchpoints; i = i + 1)
+    begin : wp_seq
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        wp[i] <= { 32{1'bx}};
+        wpc_c[i] <=  2'b00;
+    end
+    else
+    begin
+        if (debug_csr_write_enable ==  1'b1)
+        begin
+            if (debug_csr ==  5'h8)
+                wpc_c[i] <= debug_csr_write_data[3+i*2:2+i*2];
+            if (debug_csr ==  5'h18 + i)
+                wp[i] <= debug_csr_write_data;
+        end
+    end  
+end
+    end
+endgenerate
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        dc_re <=  1'b0;
+    else
+    begin
+        if ((debug_csr_write_enable ==  1'b1) && (debug_csr ==  5'h8))
+            dc_re <= debug_csr_write_data[1];
+    end
+end    
+
+  
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        state <=  3'b000;
+        dc_ss <=  1'b0;
+    end
+    else
+    begin
+        if ((debug_csr_write_enable ==  1'b1) && (debug_csr ==  5'h8))
+        begin
+            dc_ss <= debug_csr_write_data[0];
+            if (debug_csr_write_data[0] ==  1'b0) 
+                state <=  3'b000;
+            else 
+                state <=  3'b001;
+        end
+        case (state)
+         3'b001:
+        begin
+            
+            if (   (   (eret_q_x ==  1'b1)
+                    || (bret_q_x ==  1'b1)
+                    )
+                && (stall_x ==  1'b0)
+               )
+                state <=  3'b010; 
+        end
+         3'b010:
+        begin
+            
+            if ((q_x ==  1'b1) && (stall_x ==  1'b0))
+                state <=  3'b011;
+        end
+         3'b011:
+        begin
+            
+  
+
+            if (dcache_refill_request ==  1'b1)
+                state <=  3'b010;
+            else 
+ 
+
+                 if ((exception_x ==  1'b1) && (q_x ==  1'b1) && (stall_x ==  1'b0))
+            begin
+                dc_ss <=  1'b0;
+                state <=  3'b100;
+            end
+        end
+         3'b100:
+        begin
+            
+  
+
+            if (dcache_refill_request ==  1'b1)
+                state <=  3'b010;
+            else 
+ 
+
+                state <=  3'b000;
+        end
+        endcase
+    end
+end
+ 
+
+
+endmodule
+
+ 
+
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+ 
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+     
+    
+   
+  
+
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+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
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+ 
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+ 
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+ 
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+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
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+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_instruction_unit_full_debug (
+    
+    clk_i,
+    rst_i,
+    
+    stall_a,
+    stall_f,
+    stall_d,
+    stall_x,
+    stall_m,
+    valid_f,
+    valid_d,
+    kill_f,
+    branch_predict_taken_d,
+    branch_predict_address_d,
+  
+    
+    branch_taken_x,
+    branch_target_x,
+ 
+
+    exception_m,
+    branch_taken_m,
+    branch_mispredict_taken_m,
+    branch_target_m,
+  
+
+    iflush,
+ 
+
+  
+
+    dcache_restart_request,
+    dcache_refill_request,
+    dcache_refilling,
+ 
+        
+  
+
+    
+    i_dat_i,
+    i_ack_i,
+    i_err_i,
+    i_rty_i,
+ 
+
+  
+
+    jtag_read_enable,
+    jtag_write_enable,
+    jtag_write_data,
+    jtag_address,
+ 
+
+    
+    
+    pc_f,
+    pc_d,
+    pc_x,
+    pc_m,
+    pc_w,
+  
+
+    icache_stall_request,
+    icache_restart_request,
+    icache_refill_request,
+    icache_refilling,
+ 
+
+  
+
+    
+    i_dat_o,
+    i_adr_o,
+    i_cyc_o,
+    i_sel_o,
+    i_stb_o,
+    i_we_o,
+    i_cti_o,
+    i_lock_o,
+    i_bte_o,
+ 
+
+  
+    
+    
+    
+
+
+  
+
+    jtag_read_data,
+    jtag_access_complete,
+ 
+
+  
+
+    bus_error_d,
+ 
+
+  
+
+    instruction_f,
+ 
+    
+    instruction_d
+    );
+
+
+
+
+
+parameter eba_reset =  32'h00000000;                   
+parameter associativity = 1;                            
+parameter sets = 512;                                   
+parameter bytes_per_line = 16;                          
+parameter base_address = 0;                             
+parameter limit = 0;                                    
+
+
+localparam eba_reset_minus_4 = eba_reset - 4;
+localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
+localparam addr_offset_lsb = 2;
+localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
+
+
+
+
+  
+  
+   
+        
+   
+
+
+
+input clk_i;                                            
+input rst_i;                                            
+
+input stall_a;                                          
+input stall_f;                                          
+input stall_d;                                          
+input stall_x;                                          
+input stall_m;                                          
+input valid_f;                                          
+input valid_d;                                          
+input kill_f;                                           
+
+input branch_predict_taken_d;                           
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d;          
+   
+  
+    
+input branch_taken_x;                                   
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_x;                   
+ 
+
+input exception_m;
+input branch_taken_m;                                   
+input branch_mispredict_taken_m;                        
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_m;                   
+
+  
+
+input iflush;                                           
+ 
+
+  
+
+input dcache_restart_request;                           
+input dcache_refill_request;                            
+input dcache_refilling;
+ 
+        
+
+
+  
+
+input [ (32-1):0] i_dat_i;                         
+input i_ack_i;                                          
+input i_err_i;                                          
+input i_rty_i;                                          
+ 
+
+
+  
+
+input jtag_read_enable;                                 
+input jtag_write_enable;                                
+input [ 7:0] jtag_write_data;                 
+input [ (32-1):0] jtag_address;                    
+ 
+
+
+
+
+
+        
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;                             
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;                             
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;                             
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;                             
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;                             
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;
+
+  
+
+output icache_stall_request;                            
+wire   icache_stall_request;
+output icache_restart_request;                          
+wire   icache_restart_request;
+output icache_refill_request;                           
+wire   icache_refill_request;
+output icache_refilling;                                
+wire   icache_refilling;
+ 
+
+
+  
+
+output [ (32-1):0] i_dat_o;                        
+  
+
+reg    [ (32-1):0] i_dat_o;
+ 
+    
+
+
+output [ (32-1):0] i_adr_o;                        
+reg    [ (32-1):0] i_adr_o;
+output i_cyc_o;                                         
+reg    i_cyc_o; 
+output [ (4-1):0] i_sel_o;                 
+  
+
+reg    [ (4-1):0] i_sel_o;
+ 
+    
+
+
+output i_stb_o;                                         
+reg    i_stb_o;
+output i_we_o;                                          
+  
+
+reg    i_we_o;
+ 
+   
+
+
+output [ (3-1):0] i_cti_o;                       
+reg    [ (3-1):0] i_cti_o;
+output i_lock_o;                                        
+reg    i_lock_o;
+output [ (2-1):0] i_bte_o;                       
+wire   [ (2-1):0] i_bte_o;
+ 
+
+
+  
+
+output [ 7:0] jtag_read_data;                 
+reg    [ 7:0] jtag_read_data;
+output jtag_access_complete;                            
+wire   jtag_access_complete;
+ 
+
+
+  
+
+output bus_error_d;                                     
+reg    bus_error_d;
+ 
+
+  
+
+output [ (32-1):0] instruction_f;           
+wire   [ (32-1):0] instruction_f;
+ 
+
+output [ (32-1):0] instruction_d;           
+reg    [ (32-1):0] instruction_d;
+
+
+
+
+
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_a;                                
+
+  
+
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] restart_address;                     
+ 
+
+
+  
+
+wire icache_read_enable_f;                              
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] icache_refill_address;              
+reg icache_refill_ready;                                
+reg [ (32-1):0] icache_refill_data;         
+wire [ (32-1):0] icache_data_f;             
+wire [ (3-1):0] first_cycle_type;                
+wire [ (3-1):0] next_cycle_type;                 
+wire last_word;                                         
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] first_address;                      
+ 
+ 
+                    
+
+
+
+  
+                                      
+    			     
+   
+
+
+  
+
+ 
+               
+
+
+
+  
+ 
+   
+
+   
+   reg 			     bus_error_f;          
+  
+
+ 
+
+  
+    		       
+
+
+   
+  
+
+reg jtag_access;                                        
+ 
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+  
+
+
+lm32_icache_full_debug #(
+    .associativity          (associativity),
+    .sets                   (sets),
+    .bytes_per_line         (bytes_per_line),
+    .base_address           (base_address),
+    .limit                  (limit)
+    ) icache ( 
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),      
+    .stall_a                (stall_a),
+    .stall_f                (stall_f),
+    .branch_predict_taken_d (branch_predict_taken_d),
+    .valid_d                (valid_d),
+    .address_a              (pc_a),
+    .address_f              (pc_f),
+    .read_enable_f          (icache_read_enable_f),
+    .refill_ready           (icache_refill_ready),
+    .refill_data            (icache_refill_data),
+    .iflush                 (iflush),
+    
+    .stall_request          (icache_stall_request),
+    .restart_request        (icache_restart_request),
+    .refill_request         (icache_refill_request),
+    .refill_address         (icache_refill_address),
+    .refilling              (icache_refilling),
+    .inst                   (icache_data_f)
+    );
+ 
+
+
+
+
+
+
+  
+
+   
+   assign icache_read_enable_f =    (valid_f ==  1'b1)
+     && (kill_f ==  1'b0)
+   
+
+   && (dcache_restart_request ==  1'b0)
+  
+                         
+    
+				       
+ 
+       
+				    ;
+ 
+ 
+
+
+always @(*)
+begin
+    
+  
+
+    if (dcache_restart_request ==  1'b1)
+        pc_a = restart_address;
+    else 
+ 
+    
+      if (branch_taken_m ==  1'b1)
+	if ((branch_mispredict_taken_m ==  1'b1) && (exception_m ==  1'b0))
+	  pc_a = pc_x;
+	else
+          pc_a = branch_target_m;
+  
+    
+      else if (branch_taken_x ==  1'b1)
+        pc_a = branch_target_x;
+ 
+
+      else
+	if ( (valid_d ==  1'b1) && (branch_predict_taken_d ==  1'b1) )
+	  pc_a = branch_predict_address_d;
+	else
+  
+
+          if (icache_restart_request ==  1'b1)
+            pc_a = restart_address;
+	  else 
+ 
+        
+            pc_a = pc_f + 1'b1;
+end
+
+
+  
+      
+      
+        
+
+
+
+  
+
+     
+    	      
+
+     
+      
+	  
+       
+	  
+	
+	    
+     
+   
+   
+          
+
+
+  
+   
+
+
+                     
+
+  
+
+assign instruction_f = icache_data_f;
+ 
+   
+
+
+
+ 
+ 
+   
+
+  
+
+  
+
+ 
+   
+   
+   
+
+
+assign i_bte_o =  2'b00;
+ 
+
+
+  
+
+
+generate
+    case (bytes_per_line)
+    4:
+    begin
+assign first_cycle_type =  3'b111;
+assign next_cycle_type =  3'b111;
+assign last_word =  1'b1;
+assign first_address = icache_refill_address;
+    end
+    8:
+    begin
+assign first_cycle_type =  3'b010;
+assign next_cycle_type =  3'b111;
+assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 1'b1;
+assign first_address = {icache_refill_address[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
+    end
+    16:
+    begin
+assign first_cycle_type =  3'b010;
+assign next_cycle_type = i_adr_o[addr_offset_msb] == 1'b1 ?  3'b111 :  3'b010;
+assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 2'b11;
+assign first_address = {icache_refill_address[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
+    end
+    endcase
+endgenerate
+ 
+
+                     
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        pc_f <= eba_reset_minus_4[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2];
+        pc_d <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+        pc_x <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+        pc_m <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+        pc_w <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+    end
+    else
+    begin
+        if (stall_f ==  1'b0)
+            pc_f <= pc_a;
+        if (stall_d ==  1'b0)
+            pc_d <= pc_f;
+        if (stall_x ==  1'b0)
+            pc_x <= pc_d;
+        if (stall_m ==  1'b0)
+            pc_m <= pc_x;
+        pc_w <= pc_m;
+    end
+end
+
+  
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        restart_address <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+    else
+    begin
+  
+
+  
+        
+            
+            if (dcache_refill_request ==  1'b1)
+                restart_address <= pc_w;
+            else if ((icache_refill_request ==  1'b1) && (!dcache_refilling) && (!dcache_restart_request))
+                restart_address <= icache_refill_address;
+ 
+               
+                  
+
+
+ 
+         
+               
+                  
+
+
+
+    end
+end
+ 
+
+
+
+  
+   
+
+       
+          
+    
+    
+           
+              
+    
+
+
+
+
+  
+
+     
+
+assign jtag_access_complete = (i_cyc_o ==  1'b1) && ((i_ack_i ==  1'b1) || (i_err_i ==  1'b1)) && (jtag_access ==  1'b1);
+always @(*)
+begin
+    case (jtag_address[1:0])
+    2'b00: jtag_read_data = i_dat_i[ 31:24];
+    2'b01: jtag_read_data = i_dat_i[ 23:16];
+    2'b10: jtag_read_data = i_dat_i[ 15:8];
+    2'b11: jtag_read_data = i_dat_i[ 7:0];
+    endcase 
+end
+    
+
+ 
+
+
+  
+
+   
+   
+                
+   always @(posedge clk_i  )
+     begin
+	if (rst_i ==  1'b1)
+	  begin
+             i_cyc_o <=  1'b0;
+             i_stb_o <=  1'b0;
+             i_adr_o <= { 32{1'b0}};
+             i_cti_o <=  3'b111;
+             i_lock_o <=  1'b0;
+             icache_refill_data <= { 32{1'b0}};
+             icache_refill_ready <=  1'b0;
+    
+
+             bus_error_f <=  1'b0;
+   
+
+    
+
+             i_we_o <=  1'b0;
+             i_sel_o <= 4'b1111;
+             jtag_access <=  1'b0;
+   
+
+	  end
+	else
+	  begin   
+             icache_refill_ready <=  1'b0;
+             
+             if (i_cyc_o ==  1'b1)
+               begin
+		  
+		  if ((i_ack_i ==  1'b1) || (i_err_i ==  1'b1))
+		    begin
+    
+
+                       if (jtag_access ==  1'b1)
+			 begin
+			    i_cyc_o <=  1'b0;
+			    i_stb_o <=  1'b0;       
+			    i_we_o <=  1'b0;  
+			    jtag_access <=  1'b0;    
+			 end
+                       else
+   
+
+			 begin
+			    if (last_word ==  1'b1)
+			      begin
+				 
+				 i_cyc_o <=  1'b0;
+				 i_stb_o <=  1'b0;
+				 i_lock_o <=  1'b0;
+			      end
+			    
+			    i_adr_o[addr_offset_msb:addr_offset_lsb] <= i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
+			    i_cti_o <= next_cycle_type;
+			    
+			    icache_refill_ready <=  1'b1;
+			    icache_refill_data <= i_dat_i;
+			 end
+		    end
+    
+
+		    
+
+		  if (i_err_i ==  1'b1)
+		    begin
+                       bus_error_f <=  1'b1;
+                       $display ("Instruction bus error. Address: %x", i_adr_o);
+		    end
+		   
+
+   
+
+               end
+             else
+               begin
+		  if ((icache_refill_request ==  1'b1) && (icache_refill_ready ==  1'b0))
+		    begin
+                       
+    
+     
+                       i_sel_o <= 4'b1111;
+   
+
+                       i_adr_o <= {first_address, 2'b00};
+                       i_cyc_o <=  1'b1;
+                       i_stb_o <=  1'b1;                
+                       i_cti_o <= first_cycle_type;
+                       
+    
+
+                       bus_error_f <=  1'b0;
+   
+
+		    end
+    
+
+		  else
+		    begin
+                       if ((jtag_read_enable ==  1'b1) || (jtag_write_enable ==  1'b1))
+			 begin
+			    case (jtag_address[1:0])
+			      2'b00: i_sel_o <= 4'b1000;
+			      2'b01: i_sel_o <= 4'b0100;
+			      2'b10: i_sel_o <= 4'b0010;
+			      2'b11: i_sel_o <= 4'b0001;
+			    endcase
+			    i_adr_o <= jtag_address;
+			    i_dat_o <= {4{jtag_write_data}};
+			    i_cyc_o <=  1'b1;
+			    i_stb_o <=  1'b1;
+			    i_we_o <= jtag_write_enable;
+			    i_cti_o <=  3'b111;
+			    jtag_access <=  1'b1;
+			 end
+		    end 
+   
+                    
+    
+
+		  
+		  
+     
+    
+		  if (branch_taken_x ==  1'b1)
+                    bus_error_f <=  1'b0;
+    
+
+		  if (branch_taken_m ==  1'b1)
+                    bus_error_f <=  1'b0;
+   
+
+               end
+	  end
+     end
+  
+      
+     
+	   
+	  
+               
+               
+               
+               
+               
+               
+   
+               
+  
+	  
+	
+	     
+             
+                
+               
+		  
+		        
+		    
+                       
+                         
+                         
+                       
+                         
+		    
+   
+		   
+		     
+		    
+                         
+                         
+		       
+		    
+		  
+  
+               
+             
+               
+		  
+		         
+    
+			    
+         
+			 
+		    
+                       
+        
+                         
+  
+                          
+                         
+                         
+   
+                         
+  
+		    
+		  
+		    
+	                      
+    
+			         
+         
+			      
+			 
+   
+			      
+  
+			 
+		    
+               
+	  
+     
+ 
+
+ 
+ 
+
+   
+   always @(posedge clk_i  )
+     begin
+	if (rst_i ==  1'b1)
+	  begin
+             instruction_d <= { 32{1'b0}};
+  
+
+             bus_error_d <=  1'b0;
+ 
+
+	  end
+	else
+	  begin
+             if (stall_d ==  1'b0)
+               begin
+		  instruction_d <= instruction_f;
+  
+
+		  bus_error_d <= bus_error_f;
+ 
+
+               end
+	  end
+     end  
+   
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
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+ 
+ 
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+ 
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+ 
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+ 
+ 
+
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+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+  
+
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_jtag_full_debug (
+    
+    clk_i,
+    rst_i,
+    jtag_clk, 
+    jtag_update,
+    jtag_reg_q,
+    jtag_reg_addr_q,
+  
+
+    csr,
+    csr_write_enable,
+    csr_write_data,
+    stall_x,
+ 
+
+  
+
+    jtag_read_data,
+    jtag_access_complete,
+ 
+
+  
+
+    exception_q_w,
+ 
+
+    
+  
+
+    jtx_csr_read_data,
+    jrx_csr_read_data,
+ 
+
+  
+
+    jtag_csr_write_enable,
+    jtag_csr_write_data,
+    jtag_csr,
+    jtag_read_enable,
+    jtag_write_enable,
+    jtag_write_data,
+    jtag_address,
+ 
+
+  
+
+    jtag_break,
+    jtag_reset,
+ 
+
+    jtag_reg_d,
+    jtag_reg_addr_d
+    );
+
+
+
+
+
+input clk_i;                                            
+input rst_i;                                            
+
+input jtag_clk;                                         
+input jtag_update;                                      
+input [ 7:0] jtag_reg_q;                      
+input [2:0] jtag_reg_addr_q;                            
+
+  
+
+input [ (5-1):0] csr;                              
+input csr_write_enable;                                 
+input [ (32-1):0] csr_write_data;                  
+input stall_x;                                          
+ 
+
+  
+
+input [ 7:0] jtag_read_data;                  
+input jtag_access_complete;                             
+ 
+
+  
+
+input exception_q_w;                                    
+ 
+
+
+
+
+
+       
+  
+
+output [ (32-1):0] jtx_csr_read_data;              
+wire   [ (32-1):0] jtx_csr_read_data;
+output [ (32-1):0] jrx_csr_read_data;              
+wire   [ (32-1):0] jrx_csr_read_data;
+ 
+
+  
+
+output jtag_csr_write_enable;                           
+reg    jtag_csr_write_enable;
+output [ (32-1):0] jtag_csr_write_data;            
+wire   [ (32-1):0] jtag_csr_write_data;
+output [ (5-1):0] jtag_csr;                        
+wire   [ (5-1):0] jtag_csr;
+output jtag_read_enable;                                
+reg    jtag_read_enable;
+output jtag_write_enable;                               
+reg    jtag_write_enable;
+output [ 7:0] jtag_write_data;                
+wire   [ 7:0] jtag_write_data;        
+output [ (32-1):0] jtag_address;                   
+wire   [ (32-1):0] jtag_address;
+ 
+
+  
+
+output jtag_break;                                      
+reg    jtag_break;
+output jtag_reset;                                      
+reg    jtag_reset;
+ 
+
+output [ 7:0] jtag_reg_d;
+reg    [ 7:0] jtag_reg_d;
+output [2:0] jtag_reg_addr_d;
+wire   [2:0] jtag_reg_addr_d;
+             
+
+
+
+
+reg rx_update;                          
+reg rx_update_r;                        
+reg rx_update_r_r;                      
+reg rx_update_r_r_r;                    
+
+
+
+wire [ 7:0] rx_byte;   
+wire [2:0] rx_addr;
+
+  
+                 
+reg [ 7:0] uart_tx_byte;      
+reg uart_tx_valid;                      
+reg [ 7:0] uart_rx_byte;      
+reg uart_rx_valid;                      
+ 
+
+
+reg [ 3:0] command;             
+  
+
+reg [ 7:0] jtag_byte_0;       
+reg [ 7:0] jtag_byte_1;
+reg [ 7:0] jtag_byte_2;
+reg [ 7:0] jtag_byte_3;
+reg [ 7:0] jtag_byte_4;
+reg processing;                         
+ 
+
+
+reg [ 3:0] state;       
+
+
+
+
+
+  
+
+assign jtag_csr_write_data = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
+assign jtag_csr = jtag_byte_4[ (5-1):0];
+assign jtag_address = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
+assign jtag_write_data = jtag_byte_4;
+ 
+
+                 
+
+  
+                 
+assign jtag_reg_addr_d[1:0] = {uart_rx_valid, uart_tx_valid};         
+ 
+   
+
+
+  
+
+assign jtag_reg_addr_d[2] = processing;
+ 
+   
+
+
+
+  
+                 
+assign jtx_csr_read_data = {{ 32-9{1'b0}}, uart_tx_valid, 8'h00};
+assign jrx_csr_read_data = {{ 32-9{1'b0}}, uart_rx_valid, uart_rx_byte};
+ 
+         
+                 
+
+
+
+
+assign rx_byte = jtag_reg_q;
+assign rx_addr = jtag_reg_addr_q;
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        rx_update <= 1'b0;
+        rx_update_r <= 1'b0;
+        rx_update_r_r <= 1'b0;
+        rx_update_r_r_r <= 1'b0;
+    end
+    else
+    begin
+        rx_update <= jtag_update;
+        rx_update_r <= rx_update;
+        rx_update_r_r <= rx_update_r;
+        rx_update_r_r_r <= rx_update_r_r;
+    end
+end
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        state <=  4'h0;
+        command <= 4'b0000;
+        jtag_reg_d <= 8'h00;
+  
+
+        processing <=  1'b0;
+        jtag_csr_write_enable <=  1'b0;
+        jtag_read_enable <=  1'b0;
+        jtag_write_enable <=  1'b0;
+ 
+
+  
+
+        jtag_break <=  1'b0;
+        jtag_reset <=  1'b0;
+ 
+
+  
+                 
+        uart_tx_byte <= 8'h00;
+        uart_tx_valid <=  1'b0;
+        uart_rx_byte <= 8'h00;
+        uart_rx_valid <=  1'b0;
+ 
+
+    end
+    else
+    begin
+  
+                 
+        if ((csr_write_enable ==  1'b1) && (stall_x ==  1'b0))
+        begin
+            case (csr)
+             5'he:
+            begin
+                
+                uart_tx_byte <= csr_write_data[ 7:0];
+                uart_tx_valid <=  1'b1;
+            end
+             5'hf:
+            begin
+                
+                uart_rx_valid <=  1'b0;
+            end
+            endcase
+        end
+ 
+
+  
+
+        
+        if (exception_q_w ==  1'b1)
+        begin
+            jtag_break <=  1'b0;
+            jtag_reset <=  1'b0;
+        end
+ 
+
+        case (state)
+         4'h0:
+        begin
+            
+            if ((~rx_update_r_r_r & rx_update_r_r) ==  1'b1)
+            begin
+                command <= rx_byte[7:4];                
+                case (rx_addr)
+  
+
+                 3'b000:
+                begin
+                    case (rx_byte[7:4])
+  
+
+                     4'b0001:
+                        state <=  4'h1;
+                     4'b0011:
+                    begin
+                        {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
+                        state <=  4'h6;
+                    end
+                     4'b0010:
+                        state <=  4'h1;
+                     4'b0100:
+                    begin
+                        {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
+                        state <= 5;
+                    end
+                     4'b0101:
+                        state <=  4'h1;
+ 
+                    
+                     4'b0110:
+                    begin
+  
+     
+                        uart_rx_valid <=  1'b0;    
+                        uart_tx_valid <=  1'b0;         
+ 
+
+                        jtag_break <=  1'b1;
+                    end
+                     4'b0111:
+                    begin
+  
+     
+                        uart_rx_valid <=  1'b0;    
+                        uart_tx_valid <=  1'b0;         
+ 
+
+                        jtag_reset <=  1'b1;
+                    end
+                    endcase                               
+                end
+ 
+
+  
+                 
+                 3'b001:
+                begin
+                    uart_rx_byte <= rx_byte;
+                    uart_rx_valid <=  1'b1;
+                end                    
+                 3'b010:
+                begin
+                    jtag_reg_d <= uart_tx_byte;
+                    uart_tx_valid <=  1'b0;
+                end
+ 
+
+                default:
+                    ;
+                endcase                
+            end
+        end
+  
+
+         4'h1:
+        begin
+            if ((~rx_update_r_r_r & rx_update_r_r) ==  1'b1)
+            begin
+                jtag_byte_0 <= rx_byte;
+                state <=  4'h2;
+            end
+        end
+         4'h2:
+        begin
+            if ((~rx_update_r_r_r & rx_update_r_r) ==  1'b1)
+            begin
+                jtag_byte_1 <= rx_byte;
+                state <=  4'h3;
+            end
+        end
+         4'h3:
+        begin
+            if ((~rx_update_r_r_r & rx_update_r_r) ==  1'b1)
+            begin
+                jtag_byte_2 <= rx_byte;
+                state <=  4'h4;
+            end
+        end
+         4'h4:
+        begin
+            if ((~rx_update_r_r_r & rx_update_r_r) ==  1'b1)
+            begin
+                jtag_byte_3 <= rx_byte;
+                if (command ==  4'b0001)
+                    state <=  4'h6;
+                else 
+                    state <=  4'h5;
+            end
+        end
+         4'h5:
+        begin
+            if ((~rx_update_r_r_r & rx_update_r_r) ==  1'b1)
+            begin
+                jtag_byte_4 <= rx_byte;
+                state <=  4'h6;
+            end
+        end
+         4'h6:
+        begin
+            case (command)
+             4'b0001,
+             4'b0011:
+            begin
+                jtag_read_enable <=  1'b1;
+                processing <=  1'b1;
+                state <=  4'h7;
+            end
+             4'b0010,
+             4'b0100:
+            begin
+                jtag_write_enable <=  1'b1;
+                processing <=  1'b1;
+                state <=  4'h7;
+            end
+             4'b0101:
+            begin
+                jtag_csr_write_enable <=  1'b1;
+                processing <=  1'b1;
+                state <=  4'h8;
+            end
+            endcase
+        end
+         4'h7:
+        begin
+            if (jtag_access_complete ==  1'b1)
+            begin          
+                jtag_read_enable <=  1'b0;
+                jtag_reg_d <= jtag_read_data;
+                jtag_write_enable <=  1'b0;  
+                processing <=  1'b0;
+                state <=  4'h0;
+            end
+        end    
+         4'h8:
+        begin
+            jtag_csr_write_enable <=  1'b0;
+            processing <=  1'b0;
+            state <=  4'h0;
+        end    
+ 
+
+        endcase
+    end
+end
+  
+endmodule
+
+ 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_interrupt_full_debug (
+    
+    clk_i, 
+    rst_i,
+    
+    interrupt,
+    
+    stall_x,
+  
+
+    non_debug_exception,
+    debug_exception,
+ 
+    
+
+
+    eret_q_x,
+  
+
+    bret_q_x,
+ 
+
+    csr,
+    csr_write_data,
+    csr_write_enable,
+    
+    interrupt_exception,
+    
+    csr_read_data
+    );
+
+
+
+
+
+parameter interrupts =  32;         
+
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+
+input [interrupts-1:0] interrupt;               
+
+input stall_x;                                  
+
+  
+
+input non_debug_exception;                      
+input debug_exception;                          
+ 
+                                 
+
+
+input eret_q_x;                                 
+  
+
+input bret_q_x;                                 
+ 
+
+
+input [ (5-1):0] csr;                      
+input [ (32-1):0] csr_write_data;          
+input csr_write_enable;                         
+
+
+
+
+
+output interrupt_exception;                     
+wire   interrupt_exception;
+
+output [ (32-1):0] csr_read_data;          
+reg    [ (32-1):0] csr_read_data;
+
+
+
+
+
+wire [interrupts-1:0] asserted;                 
+
+wire [interrupts-1:0] interrupt_n_exception;
+
+
+
+reg ie;                                         
+reg eie;                                        
+  
+
+reg bie;                                        
+ 
+
+reg [interrupts-1:0] ip;                        
+reg [interrupts-1:0] im;                        
+
+
+
+
+
+
+assign interrupt_n_exception = ip & im;
+
+
+assign interrupt_exception = (|interrupt_n_exception) & ie;
+
+
+assign asserted = ip | interrupt;
+       
+generate
+    if (interrupts > 1) 
+    begin
+
+always @(*)
+begin
+    case (csr)
+     5'h0:  csr_read_data = {{ 32-3{1'b0}}, 
+  
+
+                                    bie,
+ 
+                                                                         
+
+
+                                    eie, 
+                                    ie
+                                   };
+     5'h2:  csr_read_data = ip;
+     5'h1:  csr_read_data = im;
+    default:       csr_read_data = { 32{1'bx}};
+    endcase
+end
+    end
+    else
+    begin
+
+always @(*)
+begin
+    case (csr)
+     5'h0:  csr_read_data = {{ 32-3{1'b0}}, 
+  
+
+                                    bie, 
+ 
+                                                                        
+
+
+                                    eie, 
+                                    ie
+                                   };
+     5'h2:  csr_read_data = ip;
+    default:       csr_read_data = { 32{1'bx}};
+      endcase
+end
+    end
+endgenerate
+    
+
+
+
+
+  
+
+   reg [ 10:0] eie_delay  = 0;
+
+   
+generate
+
+   
+    if (interrupts > 1)
+    begin
+
+always @(posedge clk_i  )
+  begin
+    if (rst_i ==  1'b1)
+    begin
+        ie                   <=  1'b0;
+        eie                  <=  1'b0;
+  
+
+        bie                  <=  1'b0;
+ 
+
+        im                   <= {interrupts{1'b0}};
+        ip                   <= {interrupts{1'b0}};
+       eie_delay             <= 0;
+       
+    end
+    else
+    begin
+        
+        ip                   <= asserted;
+  
+
+        if (non_debug_exception ==  1'b1)
+        begin
+            
+            eie              <= ie;
+            ie               <=  1'b0;
+        end
+        else if (debug_exception ==  1'b1)
+        begin
+            
+            bie              <= ie;
+            ie               <=  1'b0;
+        end
+ 
+           
+        
+            
+                           
+                            
+        
+
+
+        else if (stall_x ==  1'b0)
+        begin
+
+           if(eie_delay[0])
+             ie              <= eie;
+           
+           eie_delay         <= {1'b0, eie_delay[ 10:1]};
+
+            if (eret_q_x ==  1'b1) begin
+                
+               eie_delay[ 10] <=  1'b1;
+               eie_delay[ 10-1:0] <= 0;
+            end
+           
+                      
+           
+  
+
+            else if (bret_q_x ==  1'b1)
+                
+                ie      <= bie;
+ 
+
+            else if (csr_write_enable ==  1'b1)
+            begin
+                
+                if (csr ==  5'h0)
+                begin
+                    ie  <= csr_write_data[0];
+                    eie <= csr_write_data[1];
+  
+
+                    bie <= csr_write_data[2];
+ 
+
+                end
+                if (csr ==  5'h1)
+                    im  <= csr_write_data[interrupts-1:0];
+                if (csr ==  5'h2)
+                    ip  <= asserted & ~csr_write_data[interrupts-1:0];
+            end
+        end
+    end
+end
+    end
+else
+    begin
+
+always @(posedge clk_i  )
+  begin
+    if (rst_i ==  1'b1)
+    begin
+        ie              <=  1'b0;
+        eie             <=  1'b0;
+  
+
+        bie             <=  1'b0;
+ 
+
+        ip              <= {interrupts{1'b0}};
+       eie_delay        <= 0;
+    end
+    else
+    begin
+        
+        ip              <= asserted;
+  
+
+        if (non_debug_exception ==  1'b1)
+        begin
+            
+            eie         <= ie;
+            ie          <=  1'b0;
+        end
+        else if (debug_exception ==  1'b1)
+        begin
+            
+            bie         <= ie;
+            ie          <=  1'b0;
+        end
+ 
+           
+        
+            
+                      
+                       
+        
+
+
+        else if (stall_x ==  1'b0)
+          begin
+
+             if(eie_delay[0])
+               ie              <= eie;
+           
+             eie_delay         <= {1'b0, eie_delay[ 10:1]};
+
+             if (eret_q_x ==  1'b1) begin
+                
+                eie_delay[ 10] <=  1'b1;
+                eie_delay[ 10-1:0] <= 0;
+             end
+           
+  
+
+            else if (bret_q_x ==  1'b1)
+                
+                ie      <= bie;
+ 
+
+            else if (csr_write_enable ==  1'b1)
+            begin
+                
+                if (csr ==  5'h0)
+                begin
+                    ie  <= csr_write_data[0];
+                    eie <= csr_write_data[1];
+  
+
+                    bie <= csr_write_data[2];
+ 
+
+                end
+                if (csr ==  5'h2)
+                    ip  <= asserted & ~csr_write_data[interrupts-1:0];
+            end
+        end
+    end
+end
+    end
+endgenerate
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+	 
+	 
+	 
+	 
+	
+
+ 
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+  
+
+
+
+
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+ 
+
+
+
+  
+
+  
+
+ 
+
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+
+
+  
+                    
+
+
+  
+
+  
+
+ 
+  
+                    
+
+
+ 
+
+  
+
+
+
+  
+
+  
+
+
+
+  
+
+  
+
+
+
+  
+
+  
+
+
+
+  
+ 
+
+
+  
+ 
+
+
+ 
+
+
+
+  
+ 
+
+
+  
+ 
+
+
+ 
+
+ 
+
+
+
+  
+
+  
+
+  
+ 
+ 
+
+ 
+
+
+ 
+
+
+  
+
+  
+
+ 
+ 
+ 
+
+
+
+
+
+  
+ 
+
+
+  
+ 
+
+
+  
+ 
+
+
+
+
+  
+
+  
+
+ 
+
+  
+ 
+
+
+
+
+  
+
+
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+                   
+                     
+
+
+  
+                   
+                     
+
+
+  
+
+  
+
+ 
+
+ 
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+                      
+                    
+
+
+  
+
+  
+
+  
+
+  
+                     
+                     
+
+
+  
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+
+ 
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+  
+
+  
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+
+  
+
+  
+
+
+
+  
+ 
+
+
+  
+ 
+
+
+ 
+
+
+
+
+
+
+
+  
+
+  
+
+  
+
+
+
+
+
+
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+
+
+  
+
+
+
+
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+ 
+
+
+
+
+
+
+
+
+module lm32_top_medium (
+    
+    clk_i,
+    rst_i,
+    
+
+    interrupt,
+
+    
+  
+    
+    
+
+     
+  
+
+    
+    I_DAT_I,
+    I_ACK_I,
+    I_ERR_I,
+    I_RTY_I,
+ 
+
+    
+    D_DAT_I,
+    D_ACK_I,
+    D_ERR_I,
+    D_RTY_I,
+    
+      
+    
+    
+    
+    
+
+    
+  
+
+    
+    I_DAT_O,
+    I_ADR_O,
+    I_CYC_O,
+    I_SEL_O,
+    I_STB_O,
+    I_WE_O,
+    I_CTI_O,
+    I_LOCK_O,
+    I_BTE_O,
+ 
+
+    
+    D_DAT_O,
+    D_ADR_O,
+    D_CYC_O,
+    D_SEL_O,
+    D_STB_O,
+    D_WE_O,
+    D_CTI_O,
+    D_LOCK_O,
+    D_BTE_O
+    );
+
+parameter eba_reset = 32'h00000000;
+parameter sdb_address = 32'h00000000;
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+
+
+input [ (32-1):0] interrupt;          
+
+
+  
+               
+                             
+
+    
+
+  
+
+input [ (32-1):0] I_DAT_I;                 
+input I_ACK_I;                                  
+input I_ERR_I;                                  
+input I_RTY_I;                                  
+ 
+
+
+input [ (32-1):0] D_DAT_I;                 
+input D_ACK_I;                                  
+input D_ERR_I;                                  
+input D_RTY_I;                                  
+
+
+
+
+
+  
+                               
+   
+       
+     
+           
+    
+           
+    
+
+
+
+  
+
+output [ (32-1):0] I_DAT_O;                
+wire   [ (32-1):0] I_DAT_O;
+output [ (32-1):0] I_ADR_O;                
+wire   [ (32-1):0] I_ADR_O;
+output I_CYC_O;                                 
+wire   I_CYC_O;
+output [ (4-1):0] I_SEL_O;         
+wire   [ (4-1):0] I_SEL_O;
+output I_STB_O;                                 
+wire   I_STB_O;
+output I_WE_O;                                  
+wire   I_WE_O;
+output [ (3-1):0] I_CTI_O;               
+wire   [ (3-1):0] I_CTI_O;
+output I_LOCK_O;                                
+wire   I_LOCK_O;
+output [ (2-1):0] I_BTE_O;               
+wire   [ (2-1):0] I_BTE_O;
+ 
+
+
+output [ (32-1):0] D_DAT_O;                
+wire   [ (32-1):0] D_DAT_O;
+output [ (32-1):0] D_ADR_O;                
+wire   [ (32-1):0] D_ADR_O;
+output D_CYC_O;                                 
+wire   D_CYC_O;
+output [ (4-1):0] D_SEL_O;         
+wire   [ (4-1):0] D_SEL_O;
+output D_STB_O;                                 
+wire   D_STB_O;
+output D_WE_O;                                  
+wire   D_WE_O;
+output [ (3-1):0] D_CTI_O;               
+wire   [ (3-1):0] D_CTI_O;
+output D_LOCK_O;                                
+wire   D_LOCK_O;
+output [ (2-1):0] D_BTE_O;               
+wire   [ (2-1):0] D_BTE_O;
+  
+
+
+
+ 
+  
+
+  
+  
+ 
+  
+  
+ 
+ 
+
+
+
+
+  
+
+                     
+                             
+                            
+                   
+                                 
+ 
+                                 
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+   
+
+lm32_cpu_medium 
+	#(
+		.eba_reset(eba_reset),
+    .sdb_address(sdb_address)
+	) cpu (
+    
+    .clk_i                 (clk_i),
+  
+                   
+
+
+    .rst_i                 (rst_i),
+    
+  
+
+    .interrupt             (interrupt),
+ 
+
+    
+  
+               
+             
+
+     
+  
+    
+                  
+               
+                
+           
+
+
+  
+
+     
+    .I_DAT_I               (I_DAT_I),
+    .I_ACK_I               (I_ACK_I),
+    .I_ERR_I               (I_ERR_I),
+    .I_RTY_I               (I_RTY_I),
+ 
+
+    
+    .D_DAT_I               (D_DAT_I),
+    .D_ACK_I               (D_ACK_I),
+    .D_ERR_I               (D_ERR_I),
+    .D_RTY_I               (D_RTY_I),
+    
+  
+                  
+            
+           
+                 
+                
+ 
+                
+
+
+
+  
+                
+           
+
+
+      
+                
+               
+            
+            
+
+    
+  
+
+    
+    .I_DAT_O               (I_DAT_O),
+    .I_ADR_O               (I_ADR_O),
+    .I_CYC_O               (I_CYC_O),
+    .I_SEL_O               (I_SEL_O),
+    .I_STB_O               (I_STB_O),
+    .I_WE_O                (I_WE_O),
+    .I_CTI_O               (I_CTI_O),
+    .I_LOCK_O              (I_LOCK_O),
+    .I_BTE_O               (I_BTE_O),
+     
+
+    
+    .D_DAT_O               (D_DAT_O),
+    .D_ADR_O               (D_ADR_O),
+    .D_CYC_O               (D_CYC_O),
+    .D_SEL_O               (D_SEL_O),
+    .D_STB_O               (D_STB_O),
+    .D_WE_O                (D_WE_O),
+    .D_CTI_O               (D_CTI_O),
+    .D_LOCK_O              (D_LOCK_O),
+    .D_BTE_O               (D_BTE_O)
+    );
+   
+  		   
+
+  
+    
+                     
+                
+    
+                
+                     
+                
+                      
+                     
+    
+
+        
+   
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+           
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_mc_arithmetic_medium (
+    
+    clk_i,
+    rst_i,
+    stall_d,
+    kill_x,
+  
+    
+    
+
+
+  
+    
+
+
+  
+    
+    
+    
+
+
+    operand_0_d,
+    operand_1_d,
+    
+    result_x,
+  
+    
+
+
+    stall_request_x
+    );
+
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+input stall_d;                                  
+input kill_x;                                   
+  
+                                  
+                                 
+
+
+  
+                                
+
+
+  
+                              
+                             
+                             
+
+
+input [ (32-1):0] operand_0_d;
+input [ (32-1):0] operand_1_d;
+
+
+
+
+
+output [ (32-1):0] result_x;               
+reg    [ (32-1):0] result_x;
+  
+                         
+    
+
+
+output stall_request_x;                         
+wire   stall_request_x;
+
+
+
+
+
+reg [ (32-1):0] p;                         
+reg [ (32-1):0] a;
+reg [ (32-1):0] b;
+  
+  
+
+
+
+reg [ 2:0] state;                 
+reg [5:0] cycles;                               
+
+  
+                               
+                                 
+
+
+
+
+
+
+
+
+assign stall_request_x = state !=  3'b000;
+
+  
+
+      
+
+
+
+  
+
+       
+
+
+
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        cycles <= {6{1'b0}};
+        p <= { 32{1'b0}};
+        a <= { 32{1'b0}};
+        b <= { 32{1'b0}};
+  
+          
+
+
+  
+          
+
+
+        result_x <= { 32{1'b0}};
+        state <=  3'b000;
+    end
+    else
+    begin
+  
+          
+
+
+        case (state)
+         3'b000:
+        begin
+            if (stall_d ==  1'b0)                 
+            begin          
+                cycles <=  32;
+                p <= 32'b0;
+                a <= operand_0_d;
+                b <= operand_1_d;                    
+  
+                   
+                      
+                   
+                      
+
+                    
+  
+                   
+                      
+
+
+  
+                   
+                
+                      
+                      
+                      
+                      
+                      
+                
+                   
+                
+                      
+                      
+                      
+                      
+                      
+                
+
+
+            end            
+        end
+  
+        
+        
+               
+            
+                  
+                   
+            
+             
+            
+                   
+                   
+            
+              
+                   
+            
+                
+                    
+                  
+            
+                
+        
+        
+        
+               
+            
+                  
+                   
+            
+             
+            
+                   
+                   
+            
+              
+                   
+            
+                
+                    
+                  
+            
+                
+        
+
+        
+  
+        
+        
+               
+                    
+               
+               
+              
+                   
+                  
+                
+        
+
+     
+  
+        
+               
+               
+              
+                   
+                  
+                
+        
+        
+               
+               
+              
+                   
+                  
+                
+        
+
+   
+        endcase
+    end
+end 
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+  
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+
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+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
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+ 
+ 
+ 
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+ 
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+ 
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+ 
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+ 
+ 
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+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_cpu_medium (
+    
+    clk_i,
+  
+    
+
+
+    rst_i,
+  
+    
+
+
+  
+   
+   
+   
+   
+   
+   
+
+
+
+    
+  
+
+    interrupt,
+ 
+
+    
+  
+    
+    
+
+     
+  
+    
+    
+     
+    
+    
+
+
+  
+
+    
+    I_DAT_I,
+    I_ACK_I,
+    I_ERR_I,
+    I_RTY_I,
+ 
+
+    
+    D_DAT_I,
+    D_ACK_I,
+    D_ERR_I,
+    D_RTY_I,
+    
+  
+    
+    
+    
+    
+    
+ 
+    
+
+
+
+  
+    
+    
+
+
+      
+    
+    
+    
+    
+
+    
+  
+
+    
+    I_DAT_O,
+    I_ADR_O,
+    I_CYC_O,
+    I_SEL_O,
+    I_STB_O,
+    I_WE_O,
+    I_CTI_O,
+    I_LOCK_O,
+    I_BTE_O,
+ 
+ 
+  
+    
+    
+    
+    
+    
+    
+    
+    
+           
+
+
+		 
+		 
+    
+    D_DAT_O,
+    D_ADR_O,
+    D_CYC_O,
+    D_SEL_O,
+    D_STB_O,
+    D_WE_O,
+    D_CTI_O,
+    D_LOCK_O,
+    D_BTE_O
+
+		 
+    );
+
+
+
+
+
+parameter eba_reset =  32'h00000000;                           
+  
+                            
+
+
+parameter sdb_address =   32'h00000000;
+
+  
+        
+                          
+      
+          
+                        
+
+
+parameter icache_associativity = 1;    
+parameter icache_sets = 512;                      
+parameter icache_bytes_per_line = 16;  
+parameter icache_base_address = 0;      
+parameter icache_limit = 0;                    
+ 
+
+
+  
+        
+                          
+      
+          
+                        
+
+
+parameter dcache_associativity = 1;    
+parameter dcache_sets = 512;                      
+parameter dcache_bytes_per_line = 16;  
+parameter dcache_base_address = 0;      
+parameter dcache_limit = 0;                    
+ 
+
+
+  
+                          
+
+
+parameter watchpoints = 0;
+ 
+
+  
+                          
+
+
+parameter breakpoints = 0;
+ 
+
+
+  
+
+parameter interrupts =  32;                         
+ 
+   
+
+
+
+
+
+
+
+input clk_i;                                    
+  
+                                   
+
+    
+input rst_i;                                    
+
+  
+
+input [ (32-1):0] interrupt;          
+ 
+
+
+  
+               
+                             
+
+    
+
+   
+                                  
+                               
+                
+  
+
+
+
+  
+
+input [ (32-1):0] I_DAT_I;                 
+input I_ACK_I;                                  
+input I_ERR_I;                                  
+input I_RTY_I;                                  
+ 
+
+
+input [ (32-1):0] D_DAT_I;                 
+input D_ACK_I;                                  
+input D_ERR_I;                                  
+input D_RTY_I;                                  
+
+
+
+
+
+  
+    
+     
+
+
+   
+   
+  
+                   
+     
+                           
+    
+                          
+    
+                 
+     
+                               
+    
+ 
+                               
+    
+
+
+
+
+  
+  
+    
+  
+    
+
+
+
+  
+                               
+   
+       
+     
+           
+    
+           
+    
+
+
+
+  
+
+output [ (32-1):0] I_DAT_O;                
+wire   [ (32-1):0] I_DAT_O;
+output [ (32-1):0] I_ADR_O;                
+wire   [ (32-1):0] I_ADR_O;
+output I_CYC_O;                                 
+wire   I_CYC_O;
+output [ (4-1):0] I_SEL_O;         
+wire   [ (4-1):0] I_SEL_O;
+output I_STB_O;                                 
+wire   I_STB_O;
+output I_WE_O;                                  
+wire   I_WE_O;
+output [ (3-1):0] I_CTI_O;               
+wire   [ (3-1):0] I_CTI_O;
+output I_LOCK_O;                                
+wire   I_LOCK_O;
+output [ (2-1):0] I_BTE_O;               
+wire   [ (2-1):0] I_BTE_O;
+ 
+
+
+output [ (32-1):0] D_DAT_O;                
+wire   [ (32-1):0] D_DAT_O;
+output [ (32-1):0] D_ADR_O;                
+wire   [ (32-1):0] D_ADR_O;
+output D_CYC_O;                                 
+wire   D_CYC_O;
+output [ (4-1):0] D_SEL_O;         
+wire   [ (4-1):0] D_SEL_O;
+output D_STB_O;                                 
+wire   D_STB_O;
+output D_WE_O;                                  
+wire   D_WE_O;
+output [ (3-1):0] D_CTI_O;               
+wire   [ (3-1):0] D_CTI_O;
+output D_LOCK_O;                                
+wire   D_LOCK_O;
+output [ (2-1):0] D_BTE_O;               
+wire   [ (2-1):0] D_BTE_O;
+
+  
+      
+     
+       
+      
+             
+
+
+   
+
+
+
+
+
+
+  
+                                     
+
+
+reg valid_f;                                    
+reg valid_d;                                    
+reg valid_x;                                    
+reg valid_m;                                    
+reg valid_w;                                    
+   
+wire q_x;
+wire [ (32-1):0] immediate_d;              
+wire load_d;                                    
+reg load_x;                                     
+reg load_m;
+wire load_q_x;
+wire store_q_x;
+wire q_m;
+wire load_q_m;
+wire store_q_m;
+wire store_d;                                   
+reg store_x;
+reg store_m;
+wire [ 1:0] size_d;                   
+reg [ 1:0] size_x;
+wire branch_d;                                  
+wire branch_predict_d;                          
+wire branch_predict_taken_d;                    
+wire [ ((32-2)+2-1):2] branch_predict_address_d;   
+wire [ ((32-2)+2-1):2] branch_target_d;
+wire bi_unconditional;
+wire bi_conditional;
+reg branch_x;                                   
+reg branch_predict_x;
+reg branch_predict_taken_x;
+reg branch_m;
+reg branch_predict_m;
+reg branch_predict_taken_m;
+wire branch_mispredict_taken_m;                 
+wire branch_flushX_m;                           
+wire branch_reg_d;                              
+wire [ ((32-2)+2-1):2] branch_offset_d;            
+reg [ ((32-2)+2-1):2] branch_target_x;             
+reg [ ((32-2)+2-1):2] branch_target_m;
+wire [ 0:0] d_result_sel_0_d; 
+wire [ 1:0] d_result_sel_1_d; 
+
+wire x_result_sel_csr_d;                        
+reg x_result_sel_csr_x;
+  
+ 
+                    
+ 
+
+
+      
+                       
+ 
+
+
+  
+
+wire x_result_sel_sext_d;                       
+reg x_result_sel_sext_x;
+ 
+
+wire x_result_sel_logic_d;                      
+  
+                        
+ 
+
+
+wire x_result_sel_add_d;                        
+reg x_result_sel_add_x;
+wire m_result_sel_compare_d;                    
+reg m_result_sel_compare_x;
+reg m_result_sel_compare_m;
+  
+
+wire m_result_sel_shift_d;                      
+reg m_result_sel_shift_x;
+reg m_result_sel_shift_m;
+ 
+
+wire w_result_sel_load_d;                       
+reg w_result_sel_load_x;
+reg w_result_sel_load_m;
+reg w_result_sel_load_w;
+  
+
+wire w_result_sel_mul_d;                        
+reg w_result_sel_mul_x;
+reg w_result_sel_mul_m;
+reg w_result_sel_mul_w;
+ 
+
+wire x_bypass_enable_d;                         
+reg x_bypass_enable_x;                          
+wire m_bypass_enable_d;                         
+reg m_bypass_enable_x;                          
+reg m_bypass_enable_m;
+wire sign_extend_d;                             
+reg sign_extend_x;
+wire write_enable_d;                            
+reg write_enable_x;
+wire write_enable_q_x;
+reg write_enable_m;
+wire write_enable_q_m;
+reg write_enable_w;
+wire write_enable_q_w;
+wire read_enable_0_d;                           
+wire [ (5-1):0] read_idx_0_d;          
+wire read_enable_1_d;                           
+wire [ (5-1):0] read_idx_1_d;          
+wire [ (5-1):0] write_idx_d;           
+reg [ (5-1):0] write_idx_x;            
+reg [ (5-1):0] write_idx_m;
+reg [ (5-1):0] write_idx_w;
+wire [ (4 -1):0] csr_d;                     
+reg  [ (4 -1):0] csr_x;                  
+wire [ (3-1):0] condition_d;         
+reg [ (3-1):0] condition_x;          
+  
+                                    
+                                     
+
+
+wire scall_d;                                   
+reg scall_x;    
+wire eret_d;                                    
+reg eret_x;
+wire eret_q_x;
+  
+ 
+ 
+
+
+  
+                                     
+ 
+ 
+ 
+ 
+ 
+
+
+
+wire csr_write_enable_d;                        
+reg csr_write_enable_x;
+wire csr_write_enable_q_x;
+  
+       
+
+
+
+  
+                                
+ 
+ 
+  
+
+
+
+reg [ (32-1):0] d_result_0;                
+reg [ (32-1):0] d_result_1;                
+reg [ (32-1):0] x_result;                  
+reg [ (32-1):0] m_result;                  
+reg [ (32-1):0] w_result;                  
+
+reg [ (32-1):0] operand_0_x;               
+reg [ (32-1):0] operand_1_x;               
+reg [ (32-1):0] store_operand_x;           
+reg [ (32-1):0] operand_m;                 
+reg [ (32-1):0] operand_w;                 
+
+
+  
+
+reg [ (32-1):0] reg_data_live_0;          
+reg [ (32-1):0] reg_data_live_1;  
+reg use_buf;                                    
+reg [ (32-1):0] reg_data_buf_0;
+reg [ (32-1):0] reg_data_buf_1;
+ 
+
+  
+
+ 
+     
+
+
+wire [ (32-1):0] reg_data_0;               
+wire [ (32-1):0] reg_data_1;               
+reg [ (32-1):0] bypass_data_0;             
+reg [ (32-1):0] bypass_data_1;             
+wire reg_write_enable_q_w;
+
+reg interlock;                                  
+
+wire stall_a;                                   
+wire stall_f;                                   
+wire stall_d;                                   
+wire stall_x;                                   
+wire stall_m;                                   
+
+
+wire adder_op_d;                                
+reg adder_op_x;                                 
+reg adder_op_x_n;                               
+wire [ (32-1):0] adder_result_x;           
+wire adder_overflow_x;                          
+wire adder_carry_n_x;                           
+
+
+wire [ 3:0] logic_op_d;           
+reg [ 3:0] logic_op_x;            
+wire [ (32-1):0] logic_result_x;           
+
+  
+
+
+wire [ (32-1):0] sextb_result_x;           
+wire [ (32-1):0] sexth_result_x;           
+wire [ (32-1):0] sext_result_x;            
+ 
+
+
+
+  
+
+  
+                                   
+                                     
+
+
+wire direction_d;                               
+reg direction_x;                                        
+wire [ (32-1):0] shifter_result_m;         
+ 
+
+  
+                               
+ 
+                              
+ 
+
+
+  
+           
+
+
+
+
+  
+
+wire [ (32-1):0] multiplier_result_w;      
+ 
+
+  
+                                 
+ 
+
+
+
+
+  
+                                   
+ 
+ 
+ 
+                           
+
+
+
+
+  
+                         
+  
+
+
+
+
+  
+
+wire [ (32-1):0] interrupt_csr_read_data_x;
+ 
+
+wire [ (32-1):0] cfg;                      
+wire [ (32-1):0] cfg2;                     
+  
+                          
+
+
+reg [ (32-1):0] csr_read_data_x;           
+
+
+wire [ ((32-2)+2-1):2] pc_f;                       
+wire [ ((32-2)+2-1):2] pc_d;                       
+wire [ ((32-2)+2-1):2] pc_x;                       
+wire [ ((32-2)+2-1):2] pc_m;                       
+wire [ ((32-2)+2-1):2] pc_w;                       
+  
+                          
+
+
+  
+
+wire [ (32-1):0] instruction_f;     
+ 
+
+
+
+wire [ (32-1):0] instruction_d;     
+  
+                                     
+                       
+                     
+                      
+                           
+
+
+
+
+  
+                                   
+                                     
+                       
+                     
+                      
+                           
+
+
+wire [ (32-1):0] load_data_w;              
+wire stall_wb_load;                             
+
+
+  
+ 
+          
+          
+
+ 
+                      
+        
+                    
+                           
+  
+ 
+  
+  
+ 
+
+ 
+                                 
+
+
+
+
+
+wire raw_x_0;                                   
+wire raw_x_1;                                   
+wire raw_m_0;                                   
+wire raw_m_1;                                   
+wire raw_w_0;                                   
+wire raw_w_1;                                   
+
+
+wire cmp_zero;                                  
+wire cmp_negative;                              
+wire cmp_overflow;                              
+wire cmp_carry_n;                               
+reg condition_met_x;                            
+reg condition_met_m;
+      
+                             
+
+
+wire branch_taken_m;                            
+
+wire kill_f;                                    
+wire kill_d;                                    
+wire kill_x;                                    
+wire kill_m;                                    
+wire kill_w;                                    
+
+reg [ (32-2)+2-1:8] eba;                 
+  
+                  
+
+
+reg [ (3-1):0] eid_x;                      
+  
+                        
+                        
+
+
+
+  
+ 
+                                      
+
+                                      
+ 
+ 
+                                
+                                 
+                          
+ 
+ 
+ 
+                      
+ 
+ 
+ 
+
+
+wire exception_x;                               
+reg exception_m;
+reg exception_w;
+wire exception_q_w;
+ 
+
+
+  
+  
+                            
+
+ 
+                            
+
+
+
+  
+
+wire interrupt_exception;                       
+ 
+
+  
+                       
+                       
+
+
+  
+     
+   
+            
+                   
+
+
+  
+                   
+
+
+wire system_call_exception;                     
+
+  
+                         
+
+
+
+   
+    
+
+
+     
+  
+                          
+   
+            
+   
+                          
+   
+
+    	      
+    	      
+    	      
+    	      
+    	      
+    	      
+   
+   
+
+
+   
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+lm32_instruction_unit_medium #(
+    .eba_reset              (eba_reset),
+    .associativity          (icache_associativity),
+    .sets                   (icache_sets),
+    .bytes_per_line         (icache_bytes_per_line),
+    .base_address           (icache_base_address),
+    .limit                  (icache_limit)
+  ) instruction_unit (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    
+    .stall_a                (stall_a),
+    .stall_f                (stall_f),
+    .stall_d                (stall_d),
+    .stall_x                (stall_x),
+    .stall_m                (stall_m),
+    .valid_f                (valid_f),
+    .valid_d                (valid_d),
+    .kill_f                 (kill_f),
+    .branch_predict_taken_d (branch_predict_taken_d),
+    .branch_predict_address_d (branch_predict_address_d),
+      
+             
+            
+
+
+    .exception_m            (exception_m),
+    .branch_taken_m         (branch_taken_m),
+    .branch_mispredict_taken_m (branch_mispredict_taken_m),
+    .branch_target_m        (branch_target_m),
+  
+                     
+
+
+  
+     
+      
+           
+
+        
+  
+
+    
+    .i_dat_i                (I_DAT_I),
+    .i_ack_i                (I_ACK_I),
+    .i_err_i                (I_ERR_I),
+    .i_rty_i                (I_RTY_I),
+ 
+
+  
+           
+          
+            
+               
+
+
+    
+    
+    .pc_f                   (pc_f),
+    .pc_d                   (pc_d),
+    .pc_x                   (pc_x),
+    .pc_m                   (pc_m),
+    .pc_w                   (pc_w),
+  
+       
+     
+      
+           
+
+
+  
+
+    
+    .i_dat_o                (I_DAT_O),
+    .i_adr_o                (I_ADR_O),
+    .i_cyc_o                (I_CYC_O),
+    .i_sel_o                (I_SEL_O),
+    .i_stb_o                (I_STB_O),
+    .i_we_o                 (I_WE_O),
+    .i_cti_o                (I_CTI_O),
+    .i_lock_o               (I_LOCK_O),
+    .i_bte_o                (I_BTE_O),
+ 
+ 
+
+  
+    
+    
+    
+
+
+		      	      
+  
+             
+       
+
+
+  
+                
+
+
+  
+
+    .instruction_f          (instruction_f),
+ 
+
+
+		      
+    .instruction_d          (instruction_d)
+
+
+		      
+    );
+
+
+lm32_decoder_medium decoder (
+    
+    .instruction            (instruction_d),
+    
+    .d_result_sel_0         (d_result_sel_0_d),
+    .d_result_sel_1         (d_result_sel_1_d),
+    .x_result_sel_csr       (x_result_sel_csr_d),
+  
+      
+
+
+      
+         
+
+
+  
+
+    .x_result_sel_sext      (x_result_sel_sext_d),
+ 
+    
+    .x_result_sel_logic     (x_result_sel_logic_d),
+  
+          
+
+
+    .x_result_sel_add       (x_result_sel_add_d),
+    .m_result_sel_compare   (m_result_sel_compare_d),
+  
+
+    .m_result_sel_shift     (m_result_sel_shift_d),  
+ 
+    
+    .w_result_sel_load      (w_result_sel_load_d),
+  
+
+    .w_result_sel_mul       (w_result_sel_mul_d),
+ 
+
+    .x_bypass_enable        (x_bypass_enable_d),
+    .m_bypass_enable        (m_bypass_enable_d),
+    .read_enable_0          (read_enable_0_d),
+    .read_idx_0             (read_idx_0_d),
+    .read_enable_1          (read_enable_1_d),
+    .read_idx_1             (read_idx_1_d),
+    .write_enable           (write_enable_d),
+    .write_idx              (write_idx_d),
+    .immediate              (immediate_d),
+    .branch_offset          (branch_offset_d),
+    .load                   (load_d),
+    .store                  (store_d),
+    .size                   (size_d),
+    .sign_extend            (sign_extend_d),
+    .adder_op               (adder_op_d),
+    .logic_op               (logic_op_d),
+  
+
+    .direction              (direction_d),
+ 
+
+  
+                 
+                
+
+
+  
+                   
+
+
+  
+                     
+                    
+
+
+    .branch                 (branch_d),
+    .bi_unconditional       (bi_unconditional),
+    .bi_conditional         (bi_conditional),
+    .branch_reg             (branch_reg_d),
+    .condition              (condition_d),
+  
+               
+
+
+    .scall                  (scall_d),
+    .eret                   (eret_d),
+  
+                       
+
+
+  
+                
+
+
+    .csr_write_enable       (csr_write_enable_d)
+    ); 
+
+
+lm32_load_store_unit_medium #(
+    .associativity          (dcache_associativity),
+    .sets                   (dcache_sets),
+    .bytes_per_line         (dcache_bytes_per_line),
+    .base_address           (dcache_base_address),
+    .limit                  (dcache_limit)
+  ) load_store_unit (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    
+    .stall_a                (stall_a),
+    .stall_x                (stall_x),
+    .stall_m                (stall_m),
+    .kill_x                 (kill_x),
+    .kill_m                 (kill_m),
+    .exception_m            (exception_m),
+    .store_operand_x        (store_operand_x),
+    .load_store_address_x   (adder_result_x),
+    .load_store_address_m   (operand_m),
+    .load_store_address_w   (operand_w[1:0]),
+    .load_x                 (load_x),
+    .store_x                (store_x),
+    .load_q_x               (load_q_x),
+    .store_q_x              (store_q_x),
+    .load_q_m               (load_q_m),
+    .store_q_m              (store_q_m),
+    .sign_extend_x          (sign_extend_x),
+    .size_x                 (size_x),
+  
+                     
+
+
+
+  
+    
+    
+    
+    
+    
+    
+    
+
+
+		     
+    
+    .d_dat_i                (D_DAT_I),
+    .d_ack_i                (D_ACK_I),
+    .d_err_i                (D_ERR_I),
+    .d_rty_i                (D_RTY_I),
+    
+    
+  
+      
+     
+       
+           
+
+    
+    .load_data_w            (load_data_w),
+    .stall_wb_load          (stall_wb_load),
+    
+    .d_dat_o                (D_DAT_O),
+    .d_adr_o                (D_ADR_O),
+    .d_cyc_o                (D_CYC_O),
+    .d_sel_o                (D_SEL_O),
+    .d_stb_o                (D_STB_O),
+    .d_we_o                 (D_WE_O),
+    .d_cti_o                (D_CTI_O),
+    .d_lock_o               (D_LOCK_O),
+    .d_bte_o                (D_BTE_O)
+    );      
+       
+
+lm32_adder adder (
+    
+    .adder_op_x             (adder_op_x),
+    .adder_op_x_n           (adder_op_x_n),
+    .operand_0_x            (operand_0_x),
+    .operand_1_x            (operand_1_x),
+    
+    .adder_result_x         (adder_result_x),
+    .adder_carry_n_x        (adder_carry_n_x),
+    .adder_overflow_x       (adder_overflow_x)
+    );
+
+
+lm32_logic_op logic_op (
+    
+    .logic_op_x             (logic_op_x),
+    .operand_0_x            (operand_0_x),
+
+    .operand_1_x            (operand_1_x),
+    
+    .logic_result_x         (logic_result_x)
+    );
+              
+  
+
+
+lm32_shifter shifter (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    .stall_x                (stall_x),
+    .direction_x            (direction_x),
+    .sign_extend_x          (sign_extend_x),
+    .operand_0_x            (operand_0_x),
+    .operand_1_x            (operand_1_x),
+    
+    .shifter_result_m       (shifter_result_m)
+    );
+ 
+
+
+  
+
+
+lm32_multiplier multiplier (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    .stall_x                (stall_x),
+    .stall_m                (stall_m),
+    .operand_0              (d_result_0),
+    .operand_1              (d_result_1),
+    
+    .result                 (multiplier_result_w)    
+    );
+ 
+
+
+  
+
+  
+    
+                      
+                      
+                    
+                     
+                   
+                   
+                  
+
+         
+                 
+
+ 
+               
+              
+              
+    
+                
+                
+    
+                   
+                   
+           
+
+            
+    
+
+
+              
+  
+
+
+lm32_interrupt_medium interrupt_unit (
+    
+    .clk_i                  (clk_i), 
+    .rst_i                  (rst_i),
+    
+    .interrupt              (interrupt),
+    
+    .stall_x                (stall_x),
+  
+         
+            
+
+
+    .exception              (exception_q_w), 
+ 
+
+    .eret_q_x               (eret_q_x),
+  
+                   
+
+
+    .csr                    (csr_x),
+    .csr_write_data         (operand_1_x),
+    .csr_write_enable       (csr_write_enable_q_x),
+    
+    .interrupt_exception    (interrupt_exception),
+    
+    .csr_read_data          (interrupt_csr_read_data_x)
+    );
+ 
+
+
+  
+      
+      
+        
+   
+
+
+
+
+  
+
+  
+    
+                      
+                      
+    
+                   
+                
+                 
+            
+    
+ 
+                        
+             
+           
+                    
+
+ 
+             
+       
+
+ 
+                
+    
+    
+    
+ 
+          
+          
+
+ 
+      
+        
+                   
+           
+          
+            
+               
+
+ 
+                 
+                 
+
+    
+                 
+            
+    
+
+
+
+  
+
+ 
+                
+                
+    
+    
+                       
+                      
+                       
+                     
+                    
+       
+         
+             
+                      
+  
+	       
+      
+        
+                   
+	      
+	       
+      
+        
+                   
+	      
+
+ 
+                   
+                   
+                    
+                
+                        
+ 
+      
+
+
+    
+ 
+                      
+
+                      
+                   
+                   
+    
+
+
+
+
+
+  
+
+   
+           
+            
+          
+            
+
+
+             
+              
+    
+
+   wire [31:0] regfile_data_0, regfile_data_1;
+   reg [31:0]  w_result_d;
+   reg 	       regfile_raw_0, regfile_raw_0_nxt;
+   reg 	       regfile_raw_1, regfile_raw_1_nxt;
+   
+   
+             
+          
+
+   always @(reg_write_enable_q_w or write_idx_w or instruction_f)
+     begin
+	if (reg_write_enable_q_w
+	    && (write_idx_w == instruction_f[25:21]))
+	  regfile_raw_0_nxt = 1'b1;
+	else
+	  regfile_raw_0_nxt = 1'b0;
+	
+	if (reg_write_enable_q_w
+	    && (write_idx_w == instruction_f[20:16]))
+	  regfile_raw_1_nxt = 1'b1;
+	else
+	  regfile_raw_1_nxt = 1'b0;
+     end
+   
+   
+           
+           
+       
+
+   always @(regfile_raw_0 or w_result_d or regfile_data_0)
+     if (regfile_raw_0)
+       reg_data_live_0 = w_result_d;
+     else
+       reg_data_live_0 = regfile_data_0;
+   
+   
+           
+           
+       
+
+   always @(regfile_raw_1 or w_result_d or regfile_data_1)
+     if (regfile_raw_1)
+       reg_data_live_1 = w_result_d;
+     else
+       reg_data_live_1 = regfile_data_1;
+   
+   
+     
+
+   always @(posedge clk_i  )
+     if (rst_i ==  1'b1)
+       begin
+	  regfile_raw_0 <= 1'b0;
+	  regfile_raw_1 <= 1'b0;
+	  w_result_d <= 32'b0;
+       end
+     else
+       begin
+	  regfile_raw_0 <= regfile_raw_0_nxt;
+	  regfile_raw_1 <= regfile_raw_1_nxt;
+	  w_result_d <= w_result;
+       end
+   
+   
+      
+
+   
+   lm32_dp_ram
+     #(
+       
+       .addr_depth(1<<5),
+       .addr_width(5),
+       .data_width(32)
+       )
+   reg_0
+     (
+      
+      .clk_i	(clk_i),
+      .rst_i	(rst_i), 
+      .we_i	(reg_write_enable_q_w),
+      .wdata_i	(w_result),
+      .waddr_i	(write_idx_w),
+      .raddr_i	(instruction_f[25:21]),
+      
+      .rdata_o	(regfile_data_0)
+      );
+
+   lm32_dp_ram
+     #(
+       .addr_depth(1<<5),
+       .addr_width(5),
+       .data_width(32)
+       )
+   reg_1
+     (
+      
+      .clk_i	(clk_i),
+      .rst_i	(rst_i), 
+      .we_i	(reg_write_enable_q_w),
+      .wdata_i	(w_result),
+      .waddr_i	(write_idx_w),
+      .raddr_i	(instruction_f[20:16]),
+      
+      .rdata_o	(regfile_data_1)
+      );
+ 
+
+
+  
+   
+     
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+   
+     
+      
+      
+      
+      
+      
+      
+      
+        
+      
+       
+      
+      
+      
+   
+   
+     
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+   
+     
+      
+      
+      
+      
+      
+      
+      
+        
+      
+       
+      
+      
+      
+
+
+
+
+
+
+
+
+  
+
+
+assign reg_data_0 = use_buf ? reg_data_buf_0 : reg_data_live_0;
+assign reg_data_1 = use_buf ? reg_data_buf_1 : reg_data_live_1;
+ 
+
+  
+
+ 
+
+   
+   
+
+
+
+
+assign raw_x_0 = (write_idx_x == read_idx_0_d) && (write_enable_q_x ==  1'b1);
+assign raw_m_0 = (write_idx_m == read_idx_0_d) && (write_enable_q_m ==  1'b1);
+assign raw_w_0 = (write_idx_w == read_idx_0_d) && (write_enable_q_w ==  1'b1);
+assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x ==  1'b1);
+assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m ==  1'b1);
+assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w ==  1'b1);
+
+
+always @(*)
+begin
+    if (   (   (x_bypass_enable_x ==  1'b0)
+            && (   ((read_enable_0_d ==  1'b1) && (raw_x_0 ==  1'b1))
+                || ((read_enable_1_d ==  1'b1) && (raw_x_1 ==  1'b1))
+               )
+           )
+        || (   (m_bypass_enable_m ==  1'b0)
+            && (   ((read_enable_0_d ==  1'b1) && (raw_m_0 ==  1'b1))
+                || ((read_enable_1_d ==  1'b1) && (raw_m_1 ==  1'b1))
+               )
+           )
+       )
+        interlock =  1'b1;
+    else
+        interlock =  1'b0;
+end
+
+
+always @(*)
+begin
+    if (raw_x_0 ==  1'b1)        
+        bypass_data_0 = x_result;
+    else if (raw_m_0 ==  1'b1)
+        bypass_data_0 = m_result;
+    else if (raw_w_0 ==  1'b1)
+        bypass_data_0 = w_result;
+    else
+        bypass_data_0 = reg_data_0;
+end
+
+
+always @(*)
+begin
+    if (raw_x_1 ==  1'b1)
+        bypass_data_1 = x_result;
+    else if (raw_m_1 ==  1'b1)
+        bypass_data_1 = m_result;
+    else if (raw_w_1 ==  1'b1)
+        bypass_data_1 = w_result;
+    else
+        bypass_data_1 = reg_data_1;
+end
+
+   
+          
+       
+       
+     
+
+   assign branch_predict_d = bi_unconditional | bi_conditional;
+   assign branch_predict_taken_d = bi_unconditional ? 1'b1 : (bi_conditional ? instruction_d[15] : 1'b0);
+   
+   
+   assign branch_target_d = pc_d + branch_offset_d;
+
+   
+   
+   
+   assign branch_predict_address_d = branch_predict_taken_d ? branch_target_d : pc_f;
+
+
+always @(*)
+begin
+    d_result_0 = d_result_sel_0_d[0] ? {pc_f, 2'b00} : bypass_data_0; 
+    case (d_result_sel_1_d)
+     2'b00:      d_result_1 = { 32{1'b0}};
+     2'b01:     d_result_1 = bypass_data_1;
+     2'b10: d_result_1 = immediate_d;
+    default:                        d_result_1 = { 32{1'bx}};
+    endcase
+end
+
+      
+
+   
+   
+
+
+
+  
+
+
+assign sextb_result_x = {{24{operand_0_x[7]}}, operand_0_x[7:0]};
+assign sexth_result_x = {{16{operand_0_x[15]}}, operand_0_x[15:0]};
+assign sext_result_x = size_x ==  2'b00 ? sextb_result_x : sexth_result_x;
+ 
+
+
+  
+
+      
+
+
+
+
+assign cmp_zero = operand_0_x == operand_1_x;
+assign cmp_negative = adder_result_x[ 32-1];
+assign cmp_overflow = adder_overflow_x;
+assign cmp_carry_n = adder_carry_n_x;
+always @(*)
+begin
+    case (condition_x)
+     3'b000:   condition_met_x =  1'b1;
+     3'b110:   condition_met_x =  1'b1;
+     3'b001:    condition_met_x = cmp_zero;
+     3'b111:   condition_met_x = !cmp_zero;
+     3'b010:    condition_met_x = !cmp_zero && (cmp_negative == cmp_overflow);
+     3'b101:   condition_met_x = cmp_carry_n && !cmp_zero;
+     3'b011:   condition_met_x = cmp_negative == cmp_overflow;
+     3'b100:  condition_met_x = cmp_carry_n;
+    default:              condition_met_x = 1'bx;
+    endcase 
+end
+
+
+always @(*)
+begin
+    x_result =   x_result_sel_add_x ? adder_result_x 
+               : x_result_sel_csr_x ? csr_read_data_x
+  
+
+               : x_result_sel_sext_x ? sext_result_x
+ 
+
+  
+                  
+
+
+  
+                  
+
+
+  
+                  
+
+
+               : logic_result_x;
+end
+
+
+always @(*)
+begin
+    m_result =   m_result_sel_compare_m ? {{ 32-1{1'b0}}, condition_met_m}
+  
+
+               : m_result_sel_shift_m ? shifter_result_m
+ 
+
+               : operand_m; 
+end
+
+
+always @(*)
+begin
+    w_result =    w_result_sel_load_w ? load_data_w
+  
+
+                : w_result_sel_mul_w ? multiplier_result_w
+ 
+
+                : operand_w;
+end
+
+      
+
+          
+                                
+                                     
+                                 
+                                 
+                              
+
+
+
+
+assign branch_taken_m =      (stall_m ==  1'b0) 
+                          && (   (   (branch_m ==  1'b1) 
+                                  && (valid_m ==  1'b1)
+                                  && (   (   (condition_met_m ==  1'b1)
+					  && (branch_predict_taken_m ==  1'b0)
+					 )
+				      || (   (condition_met_m ==  1'b0)
+					  && (branch_predict_m ==  1'b1)
+					  && (branch_predict_taken_m ==  1'b1)
+					 )
+				     )
+                                 ) 
+                              || (exception_m ==  1'b1)
+                             );
+
+
+assign branch_mispredict_taken_m =    (condition_met_m ==  1'b0)
+                                   && (branch_predict_m ==  1'b1)
+	   			   && (branch_predict_taken_m ==  1'b1);
+   
+
+assign branch_flushX_m =    (stall_m ==  1'b0)
+                         && (   (   (branch_m ==  1'b1) 
+                                 && (valid_m ==  1'b1)
+			         && (   (condition_met_m ==  1'b1)
+				     || (   (condition_met_m ==  1'b0)
+					 && (branch_predict_m ==  1'b1)
+					 && (branch_predict_taken_m ==  1'b1)
+					)
+				    )
+			        )
+			     || (exception_m ==  1'b1)
+			    );
+
+
+assign kill_f =    (   (valid_d ==  1'b1)
+                    && (branch_predict_taken_d ==  1'b1)
+		   )
+                || (branch_taken_m ==  1'b1) 
+      
+                   
+
+
+  
+                    
+
+
+                  
+                   
+
+
+                ;
+assign kill_d =    (branch_taken_m ==  1'b1) 
+      
+                   
+
+
+  
+                        
+
+                
+                  
+                   
+
+
+                ;
+assign kill_x =    (branch_flushX_m ==  1'b1) 
+                  
+                   
+
+
+                ;
+assign kill_m =     1'b0
+                  
+                   
+
+
+                ;                
+assign kill_w =     1'b0
+                  
+                   
+
+                
+                ;
+
+
+
+  
+              
+				         
+				     
+				     
+				 
+ 
+                                 
+
+                              
+
+
+
+  
+     
+
+
+
+  
+        
+                                             
+                                         
+     
+
+
+
+  
+     
+
+
+
+assign system_call_exception = (   (scall_x ==  1'b1)
+  
+                                   
+
+
+			       );
+
+  
+      
+                            
+                         
+
+     
+ 
+                               
+
+ 
+                               
+                               
+
+ 
+                               
+
+ 
+                                  
+ 
+                                   
+                            
+ 
+ 				   
+				   
+
+                               
+
+                            
+
+         
+
+
+assign exception_x =           (system_call_exception ==  1'b1)
+  
+                               
+                               
+
+
+  
+                               
+
+
+  
+
+                            || (   (interrupt_exception ==  1'b1)
+  
+                                   
+
+                            
+  
+ 				   
+				   
+
+
+                               )
+ 
+
+                            ;
+ 
+
+
+  
+ 
+
+ 
+  
+      
+   
+      
+
+
+
+
+always @(*)
+begin
+  
+ 
+       
+          
+    
+     
+ 
+            
+          
+    
+
+            
+          
+    
+
+
+  
+            
+          
+    
+            
+          
+    
+
+
+  
+            
+          
+     
+
+
+  
+            
+          
+    
+
+
+  
+
+         if (   (interrupt_exception ==  1'b1)
+  
+                
+
+                            
+            )
+        eid_x =  3'h6;
+    else
+ 
+
+        eid_x =  3'h7;
+end
+
+
+
+assign stall_a = (stall_f ==  1'b1);
+                
+assign stall_f = (stall_d ==  1'b1);
+                
+assign stall_d =   (stall_x ==  1'b1) 
+                || (   (interlock ==  1'b1)
+                    && (kill_d ==  1'b0)
+                   ) 
+		|| (   (   (eret_d ==  1'b1)
+			|| (scall_d ==  1'b1)
+  
+			   
+
+
+		       )
+		    && (   (load_q_x ==  1'b1)
+			|| (load_q_m ==  1'b1)
+			|| (store_q_x ==  1'b1)
+			|| (store_q_m ==  1'b1)
+			|| (D_CYC_O ==  1'b1)
+		       )
+                    && (kill_d ==  1'b0)
+		   )
+  
+		         
+			   
+		       
+		          
+			   
+			   
+			   
+			   
+		       
+                       
+		   
+
+                   
+                || (   (csr_write_enable_d ==  1'b1)
+                    && (load_q_x ==  1'b1)
+                   )                      
+  
+                 
+                 
+                       
+		           
+			 
+			
+		    
+
+	
+                ;
+                
+assign stall_x =    (stall_m ==  1'b1)
+  
+                       
+                        
+                     
+
+
+
+	    
+                 ;
+
+assign stall_m =    (stall_wb_load ==  1'b1)
+  
+                    
+
+
+                 || (   (D_CYC_O ==  1'b1)
+                     && (   (store_m ==  1'b1)
+		         
+          
+          
+
+		  
+	 
+	
+
+          
+           
+          
+       
+
+  
+
+		         || ((store_x ==  1'b1) && (interrupt_exception ==  1'b1))
+ 
+
+                         || (load_m ==  1'b1)
+                         || (load_x ==  1'b1)
+                        ) 
+                    ) 
+ 
+                 
+  
+                         
+
+                                    
+  
+                         
+                             
+
+
+  
+
+                 || (I_CYC_O ==  1'b1)            
+ 
+
+ 
+                               
+  
+                                  
+                        
+                    
+
+
+  
+                  
+   
+
+                 ;      
+
+
+
+
+  
+         
+
+
+  
+         
+         
+
+
+  
+         
+
+
+  
+         
+         
+
+
+assign q_x = (valid_x ==  1'b1) && (kill_x ==  1'b0);
+assign csr_write_enable_q_x = (csr_write_enable_x ==  1'b1) && (q_x ==  1'b1);
+assign eret_q_x = (eret_x ==  1'b1) && (q_x ==  1'b1);
+  
+         
+
+
+assign load_q_x = (load_x ==  1'b1) 
+               && (q_x ==  1'b1)
+  
+                  
+
+
+                  ;
+assign store_q_x = (store_x ==  1'b1) 
+               && (q_x ==  1'b1)
+  
+                  
+
+
+                  ;
+  
+         
+
+                              
+assign q_m = (valid_m ==  1'b1) && (kill_m ==  1'b0) && (exception_m ==  1'b0);
+assign load_q_m = (load_m ==  1'b1) && (q_m ==  1'b1);
+assign store_q_m = (store_m ==  1'b1) && (q_m ==  1'b1);
+  
+         
+                 
+
+
+assign exception_q_w = ((exception_w ==  1'b1) && (valid_w ==  1'b1));        
+ 
+
+
+assign write_enable_q_x = (write_enable_x ==  1'b1) && (valid_x ==  1'b1) && (branch_flushX_m ==  1'b0);
+assign write_enable_q_m = (write_enable_m ==  1'b1) && (valid_m ==  1'b1);
+assign write_enable_q_w = (write_enable_w ==  1'b1) && (valid_w ==  1'b1);
+
+assign reg_write_enable_q_w = (write_enable_w ==  1'b1) && (kill_w ==  1'b0) && (valid_w ==  1'b1);
+
+
+assign cfg = {
+               6'h02,
+              watchpoints[3:0],
+              breakpoints[3:0],
+              interrupts[5:0],
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+ 
+               1'b1
+ 
+              
+
+
+              };
+
+assign cfg2 = {
+		     30'b0,
+  
+		     
+
+
+		      1'b0,
+ 
+
+  
+		     
+
+
+		      1'b0
+ 
+
+		     };
+   
+
+  
+         
+                    
+                    
+                    
+                    
+
+ 
+             
+                     
+		    
+
+		 
+
+ 
+  
+         
+                      
+
+ 
+               
+                       
+		      
+
+		   
+
+ 
+
+
+assign csr_d = read_idx_0_d[ (4 -1):0];
+
+
+always @(*)
+begin
+    case (csr_x)
+  
+
+     4 'h0,
+     4 'h1,
+     4 'h2:   csr_read_data_x = interrupt_csr_read_data_x;  
+ 
+
+  
+         
+
+
+     4 'h6:  csr_read_data_x = cfg;
+     4 'h7:  csr_read_data_x = {eba, 8'h00};
+  
+        
+
+
+  
+          
+        
+
+
+     4 'ha: csr_read_data_x = cfg2;
+     4 'hb:  csr_read_data_x = sdb_address;
+  
+        
+
+
+      
+      
+    default:        csr_read_data_x = { 32{1'bx}};
+    endcase
+end
+
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        eba <= eba_reset[ (32-2)+2-1:8];
+    else
+    begin
+        if ((csr_write_enable_q_x ==  1'b1) && (csr_x ==  4 'h7) && (stall_x ==  1'b0))
+            eba <= operand_1_x[ (32-2)+2-1:8];
+  
+  
+              
+           
+ 
+  
+              
+           
+ 	 
+
+
+    end
+end
+
+  
+
+   
+
+       
+          
+    
+    
+                   
+              
+  
+   
+              
+           
+  
+   
+              
+           
+         
+ 
+    
+
+
+
+
+
+  
+   
+
+       
+          
+    
+            
+
+
+
+
+  
+
+   
+
+       
+          
+    
+    
+        
+                
+             
+	     
+	
+        
+               
+              
+    
+
+
+
+ 
+
+
+  
+ 
+ 
+
+           
+           
+       
+          
+            
+                 
+             
+          
+     
+            
+ 
+
+ 
+
+        
+          
+         
+          
+     
+          
+ 
+
+
+
+  
+ 
+
+        
+          
+         
+          
+     
+          
+ 
+
+
+ 
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        valid_f <=  1'b0;
+        valid_d <=  1'b0;
+        valid_x <=  1'b0;
+        valid_m <=  1'b0;
+        valid_w <=  1'b0;
+    end
+    else
+    begin    
+        if ((kill_f ==  1'b1) || (stall_a ==  1'b0))
+  
+                  
+
+
+            valid_f <=  1'b1;
+ 
+            
+        else if (stall_f ==  1'b0)
+            valid_f <=  1'b0;            
+
+        if (kill_d ==  1'b1)
+            valid_d <=  1'b0;
+        else if (stall_f ==  1'b0)
+            valid_d <= valid_f & !kill_f;
+        else if (stall_d ==  1'b0)
+            valid_d <=  1'b0;
+       
+        if (stall_d ==  1'b0)
+            valid_x <= valid_d & !kill_d;
+        else if (kill_x ==  1'b1)
+            valid_x <=  1'b0;
+        else if (stall_x ==  1'b0)
+            valid_x <=  1'b0;
+
+        if (kill_m ==  1'b1)
+            valid_m <=  1'b0;
+        else if (stall_x ==  1'b0)
+            valid_m <= valid_x & !kill_x;
+        else if (stall_m ==  1'b0)
+            valid_m <=  1'b0;
+
+        if (stall_m ==  1'b0)
+            valid_w <= valid_m & !kill_m;
+        else 
+            valid_w <=  1'b0;        
+    end
+end
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+  
+                 
+
+        
+        operand_0_x <= { 32{1'b0}};
+        operand_1_x <= { 32{1'b0}};
+        store_operand_x <= { 32{1'b0}};
+        branch_target_x <= { (32-2){1'b0}};        
+        x_result_sel_csr_x <=  1'b0;
+  
+          
+
+
+      
+          
+
+
+  
+
+        x_result_sel_sext_x <=  1'b0;
+ 
+    
+  
+          
+
+
+        x_result_sel_add_x <=  1'b0;
+        m_result_sel_compare_x <=  1'b0;
+  
+
+        m_result_sel_shift_x <=  1'b0;
+ 
+    
+        w_result_sel_load_x <=  1'b0;
+  
+
+        w_result_sel_mul_x <=  1'b0;
+ 
+
+        x_bypass_enable_x <=  1'b0;
+        m_bypass_enable_x <=  1'b0;
+        write_enable_x <=  1'b0;
+        write_idx_x <= { 5{1'b0}};
+        csr_x <= { 4 {1'b0}};
+        load_x <=  1'b0;
+        store_x <=  1'b0;
+        size_x <= { 2{1'b0}};
+        sign_extend_x <=  1'b0;
+        adder_op_x <=  1'b0;
+        adder_op_x_n <=  1'b0;
+        logic_op_x <= 4'h0;
+  
+
+        direction_x <=  1'b0;
+ 
+
+  
+          
+
+
+
+        branch_x <=  1'b0;
+        branch_predict_x <=  1'b0;
+        branch_predict_taken_x <=  1'b0;
+        condition_x <=  3'b000;
+  
+          
+
+
+        scall_x <=  1'b0;
+        eret_x <=  1'b0;
+  
+          
+
+
+  
+          
+          
+
+
+        csr_write_enable_x <=  1'b0;
+        operand_m <= { 32{1'b0}};
+        branch_target_m <= { (32-2){1'b0}};
+        m_result_sel_compare_m <=  1'b0;
+  
+
+        m_result_sel_shift_m <=  1'b0;
+ 
+    
+        w_result_sel_load_m <=  1'b0;
+  
+
+        w_result_sel_mul_m <=  1'b0;
+ 
+
+        m_bypass_enable_m <=  1'b0;
+        branch_m <=  1'b0;
+        branch_predict_m <=  1'b0;
+	branch_predict_taken_m <=  1'b0;
+        exception_m <=  1'b0;
+        load_m <=  1'b0;
+        store_m <=  1'b0;
+        write_enable_m <=  1'b0;            
+        write_idx_m <= { 5{1'b0}};
+        condition_met_m <=  1'b0;
+  
+          
+
+
+  
+          
+                  
+
+
+        operand_w <= { 32{1'b0}};        
+        w_result_sel_load_w <=  1'b0;
+  
+
+        w_result_sel_mul_w <=  1'b0;
+ 
+
+        write_idx_w <= { 5{1'b0}};        
+        write_enable_w <=  1'b0;
+  
+          
+                  
+
+
+        exception_w <=  1'b0;
+ 
+
+  
+          
+
+
+    end
+    else
+    begin
+        
+       
+        if (stall_x ==  1'b0)
+        begin
+  
+                     
+
+        
+            operand_0_x <= d_result_0;
+            operand_1_x <= d_result_1;
+            store_operand_x <= bypass_data_1;
+            branch_target_x <= branch_reg_d ==  1'b1 ? bypass_data_0[ ((32-2)+2-1):2] : branch_target_d;            
+            x_result_sel_csr_x <= x_result_sel_csr_d;
+  
+              
+
+
+      
+              
+
+
+  
+
+            x_result_sel_sext_x <= x_result_sel_sext_d;
+ 
+    
+  
+              
+
+
+            x_result_sel_add_x <= x_result_sel_add_d;
+            m_result_sel_compare_x <= m_result_sel_compare_d;
+  
+
+            m_result_sel_shift_x <= m_result_sel_shift_d;
+ 
+    
+            w_result_sel_load_x <= w_result_sel_load_d;
+  
+
+            w_result_sel_mul_x <= w_result_sel_mul_d;
+ 
+
+            x_bypass_enable_x <= x_bypass_enable_d;
+            m_bypass_enable_x <= m_bypass_enable_d;
+            load_x <= load_d;
+            store_x <= store_d;
+            branch_x <= branch_d;
+	    branch_predict_x <= branch_predict_d;
+	    branch_predict_taken_x <= branch_predict_taken_d;
+	    write_idx_x <= write_idx_d;
+            csr_x <= csr_d;
+            size_x <= size_d;
+            sign_extend_x <= sign_extend_d;
+            adder_op_x <= adder_op_d;
+            adder_op_x_n <= ~adder_op_d;
+            logic_op_x <= logic_op_d;
+  
+
+            direction_x <= direction_d;
+ 
+
+  
+              
+
+
+            condition_x <= condition_d;
+            csr_write_enable_x <= csr_write_enable_d;
+  
+              
+
+
+            scall_x <= scall_d;
+  
+              
+
+
+            eret_x <= eret_d;
+  
+               
+
+
+            write_enable_x <= write_enable_d;
+        end
+        
+        
+
+        if (stall_m ==  1'b0)
+        begin
+            operand_m <= x_result;
+            m_result_sel_compare_m <= m_result_sel_compare_x;
+  
+
+            m_result_sel_shift_m <= m_result_sel_shift_x;
+ 
+    
+            if (exception_x ==  1'b1)
+            begin
+                w_result_sel_load_m <=  1'b0;
+  
+
+                w_result_sel_mul_m <=  1'b0;
+ 
+
+            end
+            else
+            begin
+                w_result_sel_load_m <= w_result_sel_load_x;
+  
+
+                w_result_sel_mul_m <= w_result_sel_mul_x;
+ 
+
+            end
+            m_bypass_enable_m <= m_bypass_enable_x;
+            load_m <= load_x;
+            store_m <= store_x;
+      
+                
+
+
+            branch_m <= branch_x;
+	    branch_predict_m <= branch_predict_x;
+	    branch_predict_taken_m <= branch_predict_taken_x;
+ 
+
+  
+	   
+	   
+	   
+	   
+	   
+                
+                  
+                
+                  
+             
+                  
+
+
+            if (exception_x ==  1'b1)
+                write_idx_m <=  5'd30;
+            else 
+                write_idx_m <= write_idx_x;
+ 
+
+            condition_met_m <= condition_met_x;
+  
+	      
+	        
+		     
+		        
+	           
+	     
+	           
+	   
+	       
+
+
+            branch_target_m <= exception_x ==  1'b1 ? {eba, eid_x, {3{1'b0}}} : branch_target_x;
+ 
+
+  
+              
+              
+
+
+  
+              
+
+
+  
+ 
+               
+
+
+
+            write_enable_m <= exception_x ==  1'b1 ?  1'b1 : write_enable_x;            
+  
+              
+                      
+
+
+        end
+        
+        
+        if (stall_m ==  1'b0)
+        begin
+            if ((exception_x ==  1'b1) && (q_x ==  1'b1) && (stall_x ==  1'b0))
+                exception_m <=  1'b1;
+            else 
+                exception_m <=  1'b0;
+  
+	           
+ 
+					    
+
+					 
+
+
+	end
+                
+        
+  
+                      
+
+
+        operand_w <= exception_m ==  1'b1 ? {pc_m, 2'b00} : m_result;
+ 
+
+        w_result_sel_load_w <= w_result_sel_load_m;
+  
+
+        w_result_sel_mul_w <= w_result_sel_mul_m;
+ 
+
+        write_idx_w <= write_idx_m;
+  
+          
+          
+ 
+           
+
+
+
+        write_enable_w <= write_enable_m;
+  
+          
+          
+
+
+        exception_w <= exception_m;
+ 
+
+  
+              
+                   
+                   
+               
+	   
+            
+
+
+    end
+end
+
+  
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        use_buf <=  1'b0;
+        reg_data_buf_0 <= { 32{1'b0}};
+        reg_data_buf_1 <= { 32{1'b0}};
+    end
+    else
+    begin
+        if (stall_d ==  1'b0)
+            use_buf <=  1'b0;
+        else if (use_buf ==  1'b0)
+        begin        
+            reg_data_buf_0 <= reg_data_live_0;
+            reg_data_buf_1 <= reg_data_live_1;
+            use_buf <=  1'b1;
+        end        
+        if (reg_write_enable_q_w ==  1'b1)
+        begin
+            if (write_idx_w == read_idx_0_d)
+                reg_data_buf_0 <= w_result;
+            if (write_idx_w == read_idx_1_d)
+                reg_data_buf_1 <= w_result;
+        end
+    end
+end
+ 
+
+
+  
+
+ 
+
+   
+
+        
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+        
+     
+           
+            
+        
+
+
+
+
+  
+
+   
+
+       
+    
+          
+          
+          
+          
+          
+ 
+          
+
+          
+    
+    
+    
+          
+        
+ 
+               
+
+           
+
+                
+              
+              
+              
+              
+        
+        
+              
+        
+             
+        
+            
+                 
+            
+                
+                  
+                  
+            
+            
+              
+            
+              
+ 
+              
+
+        
+        
+        
+              
+ 
+              
+
+        
+    
+
+
+
+      
+
+
+
+
+
+        
+endmodule 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_load_store_unit_medium 
+(
+    
+    clk_i,
+    rst_i,
+ 
+    stall_a,
+    stall_x,
+    stall_m,
+    kill_x,
+    kill_m,
+    exception_m,
+    store_operand_x,
+    load_store_address_x,
+    load_store_address_m,
+    load_store_address_w,
+    load_x,
+    store_x,
+    load_q_x,
+    store_q_x,
+    load_q_m,
+    store_q_m,
+    sign_extend_x,
+    size_x,
+  
+    
+
+
+    
+    d_dat_i,
+    d_ack_i,
+    d_err_i,
+    d_rty_i,
+    
+    
+  
+    
+    
+    
+    
+
+    
+  
+    
+    
+    
+    
+    
+    
+    
+
+			     
+    load_data_w,
+    stall_wb_load,
+    
+    d_dat_o,
+    d_adr_o,
+    d_cyc_o,
+    d_sel_o,
+    d_stb_o,
+    d_we_o,
+    d_cti_o,
+    d_lock_o,
+    d_bte_o
+    );
+
+
+
+
+
+parameter associativity = 1;                            
+parameter sets = 512;                                   
+parameter bytes_per_line = 16;                          
+parameter base_address = 0;                             
+parameter limit = 0;                                    
+
+
+localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
+localparam addr_offset_lsb = 2;
+localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
+
+
+
+
+
+   input clk_i;                                            
+   
+input rst_i;                                            
+
+input stall_a;                                          
+input stall_x;                                          
+input stall_m;                                          
+input kill_x;                                           
+input kill_m;                                           
+input exception_m;                                      
+
+input [ (32-1):0] store_operand_x;                 
+input [ (32-1):0] load_store_address_x;            
+input [ (32-1):0] load_store_address_m;            
+input [1:0] load_store_address_w;                       
+input load_x;                                           
+input store_x;                                          
+input load_q_x;                                         
+input store_q_x;                                        
+input load_q_m;                                         
+input store_q_m;                                        
+input sign_extend_x;                                    
+input [ 1:0] size_x;                          
+
+  
+                                            
+
+
+
+     
+     
+     
+      
+      
+            
+    	 
+   
+
+
+
+   reg 		 [31:0] iram_dat_d0;
+   reg 		 iram_en_d0;
+   wire 	 iram_en;
+   wire [31:0] 	 iram_data;
+   
+   
+   
+input [ (32-1):0] d_dat_i;                         
+input d_ack_i;                                          
+input d_err_i;                                          
+input d_rty_i;                                          
+
+
+
+
+
+  
+                            
+   
+                           
+   
+                             
+   
+ 
+   
+
+
+
+   
+output [ (32-1):0] load_data_w;                    
+reg    [ (32-1):0] load_data_w;
+output stall_wb_load;                                   
+reg    stall_wb_load;
+
+output [ (32-1):0] d_dat_o;                        
+reg    [ (32-1):0] d_dat_o;
+output [ (32-1):0] d_adr_o;                        
+reg    [ (32-1):0] d_adr_o;
+output d_cyc_o;                                         
+reg    d_cyc_o;
+output [ (4-1):0] d_sel_o;                 
+reg    [ (4-1):0] d_sel_o;
+output d_stb_o;                                         
+reg    d_stb_o; 
+output d_we_o;                                          
+reg    d_we_o;
+output [ (3-1):0] d_cti_o;                       
+reg    [ (3-1):0] d_cti_o;
+output d_lock_o;                                        
+reg    d_lock_o;
+output [ (2-1):0] d_bte_o;                       
+wire   [ (2-1):0] d_bte_o;
+
+
+
+
+
+
+reg [ 1:0] size_m;
+reg [ 1:0] size_w;
+reg sign_extend_m;
+reg sign_extend_w;
+reg [ (32-1):0] store_data_x;       
+reg [ (32-1):0] store_data_m;       
+reg [ (4-1):0] byte_enable_x;
+reg [ (4-1):0] byte_enable_m;
+wire [ (32-1):0] data_m;
+reg [ (32-1):0] data_w;
+
+   
+
+  
+                                    
+ 
+                      
+              
+                                 
+                  
+                   
+                                          
+                      
+
+
+  
+                                      
+ 
+                                      
+                    
+                      
+                        
+                  
+
+
+wire wb_select_x;                                       
+  
+                                      
+
+  
+    
+    
+   
+
+
+
+reg wb_select_m;
+reg [ (32-1):0] wb_data_m;                         
+reg wb_load_complete;                                   
+   
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+  
+
+ 
+              
+                       
+             
+               
+                      
+       
+    
+                      
+                            
+                    
+                    
+                    
+                  
+                  
+                     
+                    
+                 
+            
+               
+                
+                     
+    
+              
+            
+             
+             
+                  
+                  
+    
+
+
+
+
+
+
+
+
+  
+            
+                             
+
+
+
+  
+            
+                             
+
+      
+        
+
+    
+       
+
+   
+
+    
+     
+       
+     
+         
+     
+
+          
+    
+   
+   
+
+
+   
+  
+            
+                               
+ 
+                               
+
+ 
+                               
+
+                     
+
+
+	  
+   assign wb_select_x =     1'b1
+  
+                          
+
+
+  
+                         
+
+
+  
+                         
+
+
+                     ;
+
+
+always @(*)
+begin
+    case (size_x)
+     2'b00:  store_data_x = {4{store_operand_x[7:0]}};
+     2'b11: store_data_x = {2{store_operand_x[15:0]}};
+     2'b10:  store_data_x = store_operand_x;    
+    default:          store_data_x = { 32{1'bx}};
+    endcase
+end
+
+
+always @(*)
+begin
+    casez ({size_x, load_store_address_x[1:0]})
+    { 2'b00, 2'b11}:  byte_enable_x = 4'b0001;
+    { 2'b00, 2'b10}:  byte_enable_x = 4'b0010;
+    { 2'b00, 2'b01}:  byte_enable_x = 4'b0100;
+    { 2'b00, 2'b00}:  byte_enable_x = 4'b1000;
+    { 2'b11, 2'b1?}: byte_enable_x = 4'b0011;
+    { 2'b11, 2'b0?}: byte_enable_x = 4'b1100;
+    { 2'b10, 2'b??}:  byte_enable_x = 4'b1111;
+    default:                   byte_enable_x = 4'bxxxx;
+    endcase
+end
+
+  
+      
+            
+
+           
+	                            
+   
+   
+               
+        
+
+
+   
+  
+  
+   
+   
+         
+                    
+                       
+                      
+                        
+                     
+                        
+  
+   
+         
+                    
+                       
+                      
+                      
+  
+ 
+   
+   
+         
+                    
+                       
+                      
+                      
+  
+   
+         
+                     
+                    
+  
+ 
+
+
+   
+   
+   
+         
+                     
+                      
+                      
+                      
+  
+   
+         
+                     
+                    
+  
+ 
+
+    
+   
+         
+                     
+                    
+
+  
+
+   
+   assign data_m = wb_data_m;
+   
+
+  
+
+ 
+
+
+
+always @(*)
+begin
+    casez ({size_w, load_store_address_w[1:0]})
+    { 2'b00, 2'b11}:  load_data_w = {{24{sign_extend_w & data_w[7]}}, data_w[7:0]};
+    { 2'b00, 2'b10}:  load_data_w = {{24{sign_extend_w & data_w[15]}}, data_w[15:8]};
+    { 2'b00, 2'b01}:  load_data_w = {{24{sign_extend_w & data_w[23]}}, data_w[23:16]};
+    { 2'b00, 2'b00}:  load_data_w = {{24{sign_extend_w & data_w[31]}}, data_w[31:24]};
+    { 2'b11, 2'b1?}: load_data_w = {{16{sign_extend_w & data_w[15]}}, data_w[15:0]};
+    { 2'b11, 2'b0?}: load_data_w = {{16{sign_extend_w & data_w[31]}}, data_w[31:16]};
+    { 2'b10, 2'b??}:  load_data_w = data_w;
+    default:                   load_data_w = { 32{1'bx}};
+    endcase
+end
+
+
+assign d_bte_o =  2'b00;
+
+                  
+
+ 
+     
+    
+    
+   
+   
+   
+    
+    
+    
+    
+   
+   
+     
+     
+    
+    
+    
+   
+         
+     
+     
+    
+    
+
+
+
+
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        d_cyc_o <=  1'b0;
+        d_stb_o <=  1'b0;
+        d_dat_o <= { 32{1'b0}};
+        d_adr_o <= { 32{1'b0}};
+        d_sel_o <= { 4{ 1'b0}};
+        d_we_o <=  1'b0;
+        d_cti_o <=  3'b111;
+        d_lock_o <=  1'b0;
+        wb_data_m <= { 32{1'b0}};
+        wb_load_complete <=  1'b0;
+        stall_wb_load <=  1'b0;
+                  
+          
+
+                
+    end
+    else 
+    begin
+   
+        
+          
+
+                
+        
+        if (d_cyc_o ==  1'b1)
+        begin
+            
+            if ((d_ack_i ==  1'b1) || (d_err_i ==  1'b1))
+            begin
+                  
+                     
+                
+                    
+                        
+                
+                
+
+                
+                begin
+                    
+                    d_cyc_o <=  1'b0;
+                    d_stb_o <=  1'b0;
+                    d_lock_o <=  1'b0;
+                end
+      
+                  
+                
+                  
+
+
+                
+                wb_data_m <= d_dat_i;
+                
+                wb_load_complete <= !d_we_o;
+            end
+            
+        end
+        else 
+        begin
+                  
+               
+            
+                
+                  
+                  
+                  
+                                  
+                  
+                  
+                
+            
+             
+
+            
+                 if (   (store_q_m ==  1'b1)
+                     && (stall_m ==  1'b0)
+  
+                        
+
+
+  
+		        
+
+			
+                    )
+            begin
+                
+                d_dat_o <= store_data_m;
+                d_adr_o <= load_store_address_m;
+                d_cyc_o <=  1'b1;
+                d_sel_o <= byte_enable_m;
+                d_stb_o <=  1'b1;
+                d_we_o <=  1'b1;
+                d_cti_o <=  3'b111;
+            end        
+            else if (   (load_q_m ==  1'b1) 
+                     && (wb_select_m ==  1'b1) 
+                     && (wb_load_complete ==  1'b0)
+                     
+                    )
+            begin
+                
+                stall_wb_load <=  1'b0;
+                d_adr_o <= load_store_address_m;
+                d_cyc_o <=  1'b1;
+                d_sel_o <= byte_enable_m;
+                d_stb_o <=  1'b1;
+                d_we_o <=  1'b0;
+                d_cti_o <=  3'b111;
+            end
+        end
+        
+        if (stall_m ==  1'b0)
+            wb_load_complete <=  1'b0;
+        
+        if ((load_q_x ==  1'b1) && (wb_select_x ==  1'b1) && (stall_x ==  1'b0))
+            stall_wb_load <=  1'b1;
+        
+        if ((kill_m ==  1'b1) || (exception_m ==  1'b1))
+            stall_wb_load <=  1'b0;
+    end
+end
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        sign_extend_m <=  1'b0;
+        size_m <= 2'b00;
+        byte_enable_m <=  1'b0;
+        store_data_m <= { 32{1'b0}};
+  
+          
+
+
+  
+          
+
+
+  
+          
+			    
+
+
+        wb_select_m <=  1'b0;        
+    end
+    else
+    begin
+        if (stall_m ==  1'b0)
+        begin
+            sign_extend_m <= sign_extend_x;
+            size_m <= size_x;
+            byte_enable_m <= byte_enable_x;    
+            store_data_m <= store_data_x;
+  
+              
+
+
+  
+              
+
+
+  
+              
+			    
+
+
+            wb_select_m <= wb_select_x;
+        end
+    end
+end
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        size_w <= 2'b00;
+        data_w <= { 32{1'b0}};
+        sign_extend_w <=  1'b0;
+    end
+    else
+    begin
+        size_w <= size_m;
+
+  
+         
+
+
+        data_w <= data_m;
+
+        sign_extend_w <= sign_extend_m;
+    end
+end
+
+
+
+
+
+
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_decoder_medium (
+    
+    instruction,
+    
+    d_result_sel_0,
+    d_result_sel_1,        
+    x_result_sel_csr,
+  
+    
+
+    
+      
+    
+
+
+  
+
+    x_result_sel_sext,
+ 
+    
+    x_result_sel_logic,
+  
+    
+
+
+    x_result_sel_add,
+    m_result_sel_compare,
+  
+
+    m_result_sel_shift,  
+ 
+    
+    w_result_sel_load,
+  
+
+    w_result_sel_mul,
+ 
+
+    x_bypass_enable,
+    m_bypass_enable,
+    read_enable_0,
+    read_idx_0,
+    read_enable_1,
+    read_idx_1,
+    write_enable,
+    write_idx,
+    immediate,
+    branch_offset,
+    load,
+    store,
+    size,
+    sign_extend,
+    adder_op,
+    logic_op,
+  
+
+    direction,
+ 
+
+  
+    
+    
+
+
+  
+    
+
+
+  
+    
+    
+
+
+    branch,
+    branch_reg,
+    condition,
+    bi_conditional,
+    bi_unconditional,
+  
+    
+
+
+    scall,
+    eret,
+  
+    
+
+
+  
+    
+
+
+    csr_write_enable
+    );
+
+
+
+
+
+input [ (32-1):0] instruction;       
+
+
+
+
+
+output [ 0:0] d_result_sel_0;
+reg    [ 0:0] d_result_sel_0;
+output [ 1:0] d_result_sel_1;
+reg    [ 1:0] d_result_sel_1;
+output x_result_sel_csr;
+reg    x_result_sel_csr;
+  
+ 
+    
+
+
+      
+ 
+    
+
+
+  
+
+output x_result_sel_sext;
+reg    x_result_sel_sext;
+ 
+
+output x_result_sel_logic;
+reg    x_result_sel_logic;
+  
+ 
+    
+
+
+output x_result_sel_add;
+reg    x_result_sel_add;
+output m_result_sel_compare;
+reg    m_result_sel_compare;
+  
+
+output m_result_sel_shift;
+reg    m_result_sel_shift;
+ 
+
+output w_result_sel_load;
+reg    w_result_sel_load;
+  
+
+output w_result_sel_mul;
+reg    w_result_sel_mul;
+ 
+
+output x_bypass_enable;
+wire   x_bypass_enable;
+output m_bypass_enable;
+wire   m_bypass_enable;
+output read_enable_0;
+wire   read_enable_0;
+output [ (5-1):0] read_idx_0;
+wire   [ (5-1):0] read_idx_0;
+output read_enable_1;
+wire   read_enable_1;
+output [ (5-1):0] read_idx_1;
+wire   [ (5-1):0] read_idx_1;
+output write_enable;
+wire   write_enable;
+output [ (5-1):0] write_idx;
+wire   [ (5-1):0] write_idx;
+output [ (32-1):0] immediate;
+wire   [ (32-1):0] immediate;
+output [ ((32-2)+2-1):2] branch_offset;
+wire   [ ((32-2)+2-1):2] branch_offset;
+output load;
+wire   load;
+output store;
+wire   store;
+output [ 1:0] size;
+wire   [ 1:0] size;
+output sign_extend;
+wire   sign_extend;
+output adder_op;
+wire   adder_op;
+output [ 3:0] logic_op;
+wire   [ 3:0] logic_op;
+  
+
+output direction;
+wire   direction;
+ 
+
+  
+ 
+   
+ 
+   
+
+
+  
+ 
+   
+
+
+  
+ 
+   
+ 
+   
+
+
+output branch;
+wire   branch;
+output branch_reg;
+wire   branch_reg;
+output [ (3-1):0] condition;
+wire   [ (3-1):0] condition;
+output bi_conditional;
+wire bi_conditional;
+output bi_unconditional;
+wire bi_unconditional;
+  
+ 
+   
+
+
+output scall;
+wire   scall;
+output eret;
+wire   eret;
+  
+ 
+   
+
+
+  
+  
+    
+
+
+output csr_write_enable;
+wire   csr_write_enable;
+
+
+
+
+
+wire [ (32-1):0] extended_immediate;       
+wire [ (32-1):0] high_immediate;           
+wire [ (32-1):0] call_immediate;           
+wire [ (32-1):0] branch_immediate;         
+wire sign_extend_immediate;                     
+wire select_high_immediate;                     
+wire select_call_immediate;                     
+
+wire op_add;
+wire op_and;
+wire op_andhi;
+wire op_b;
+wire op_bi;
+wire op_be;
+wire op_bg;
+wire op_bge;
+wire op_bgeu;
+wire op_bgu;
+wire op_bne;
+wire op_call;
+wire op_calli;
+wire op_cmpe;
+wire op_cmpg;
+wire op_cmpge;
+wire op_cmpgeu;
+wire op_cmpgu;
+wire op_cmpne;
+  
+ 
+
+
+wire op_lb;
+wire op_lbu;
+wire op_lh;
+wire op_lhu;
+wire op_lw;
+  
+ 
+
+
+  
+
+wire op_mul;
+ 
+
+wire op_nor;
+wire op_or;
+wire op_orhi;
+wire op_raise;
+wire op_rcsr;
+wire op_sb;
+  
+
+wire op_sextb;
+wire op_sexth;
+ 
+
+wire op_sh;
+  
+
+wire op_sl;
+ 
+
+wire op_sr;
+wire op_sru;
+wire op_sub;
+wire op_sw;
+  
+ 
+
+
+wire op_wcsr;
+wire op_xnor;
+wire op_xor;
+
+wire arith;
+wire logical;
+wire cmp;
+wire bra;
+wire call;
+  
+
+wire shift;
+ 
+
+  
+ 
+
+
+  
+
+wire sext;
+ 
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+assign op_add    = instruction[ 30:26] ==  5'b01101;
+assign op_and    = instruction[ 30:26] ==  5'b01000;
+assign op_andhi  = instruction[ 31:26] ==  6'b011000;
+assign op_b      = instruction[ 31:26] ==  6'b110000;
+assign op_bi     = instruction[ 31:26] ==  6'b111000;
+assign op_be     = instruction[ 31:26] ==  6'b010001;
+assign op_bg     = instruction[ 31:26] ==  6'b010010;
+assign op_bge    = instruction[ 31:26] ==  6'b010011;
+assign op_bgeu   = instruction[ 31:26] ==  6'b010100;
+assign op_bgu    = instruction[ 31:26] ==  6'b010101;
+assign op_bne    = instruction[ 31:26] ==  6'b010111;
+assign op_call   = instruction[ 31:26] ==  6'b110110;
+assign op_calli  = instruction[ 31:26] ==  6'b111110;
+assign op_cmpe   = instruction[ 30:26] ==  5'b11001;
+assign op_cmpg   = instruction[ 30:26] ==  5'b11010;
+assign op_cmpge  = instruction[ 30:26] ==  5'b11011;
+assign op_cmpgeu = instruction[ 30:26] ==  5'b11100;
+assign op_cmpgu  = instruction[ 30:26] ==  5'b11101;
+assign op_cmpne  = instruction[ 30:26] ==  5'b11111;
+  
+       
+
+
+assign op_lb     = instruction[ 31:26] ==  6'b000100;
+assign op_lbu    = instruction[ 31:26] ==  6'b010000;
+assign op_lh     = instruction[ 31:26] ==  6'b000111;
+assign op_lhu    = instruction[ 31:26] ==  6'b001011;
+assign op_lw     = instruction[ 31:26] ==  6'b001010;
+  
+       
+
+
+  
+
+assign op_mul    = instruction[ 30:26] ==  5'b00010;
+ 
+
+assign op_nor    = instruction[ 30:26] ==  5'b00001;
+assign op_or     = instruction[ 30:26] ==  5'b01110;
+assign op_orhi   = instruction[ 31:26] ==  6'b011110;
+assign op_raise  = instruction[ 31:26] ==  6'b101011;
+assign op_rcsr   = instruction[ 31:26] ==  6'b100100;
+assign op_sb     = instruction[ 31:26] ==  6'b001100;
+  
+
+assign op_sextb  = instruction[ 31:26] ==  6'b101100;
+assign op_sexth  = instruction[ 31:26] ==  6'b110111;
+ 
+
+assign op_sh     = instruction[ 31:26] ==  6'b000011;
+  
+
+assign op_sl     = instruction[ 30:26] ==  5'b01111;      
+ 
+
+assign op_sr     = instruction[ 30:26] ==  5'b00101;
+assign op_sru    = instruction[ 30:26] ==  5'b00000;
+assign op_sub    = instruction[ 31:26] ==  6'b110010;
+assign op_sw     = instruction[ 31:26] ==  6'b010110;
+  
+       
+
+
+assign op_wcsr   = instruction[ 31:26] ==  6'b110100;
+assign op_xnor   = instruction[ 30:26] ==  5'b01001;
+assign op_xor    = instruction[ 30:26] ==  5'b00110;
+
+
+assign arith = op_add | op_sub;
+assign logical = op_and | op_andhi | op_nor | op_or | op_orhi | op_xor | op_xnor;
+assign cmp = op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne;
+assign bi_conditional = op_be | op_bg | op_bge | op_bgeu  | op_bgu | op_bne;
+assign bi_unconditional = op_bi;
+assign bra = op_b | bi_unconditional | bi_conditional;
+assign call = op_call | op_calli;
+  
+
+assign shift = op_sl | op_sr | op_sru;
+ 
+
+  
+     
+
+
+  
+   
+     
+
+
+  
+
+assign sext = op_sextb | op_sexth;
+ 
+
+  
+   
+
+
+  
+    
+   
+
+
+assign load = op_lb | op_lbu | op_lh | op_lhu | op_lw;
+assign store = op_sb | op_sh | op_sw;
+
+
+always @(*)
+begin
+    
+    if (call) 
+        d_result_sel_0 =  1'b1;
+    else 
+        d_result_sel_0 =  1'b0;
+    if (call) 
+        d_result_sel_1 =  2'b00;         
+    else if ((instruction[31] == 1'b0) && !bra) 
+        d_result_sel_1 =  2'b10;
+    else
+        d_result_sel_1 =  2'b01; 
+    
+    x_result_sel_csr =  1'b0;
+  
+      
+
+
+  
+      
+
+
+  
+
+    x_result_sel_sext =  1'b0;
+ 
+
+    x_result_sel_logic =  1'b0;
+          
+      
+
+
+    x_result_sel_add =  1'b0;
+    if (op_rcsr)
+        x_result_sel_csr =  1'b1;
+      
+ 
+         
+          
+
+ 
+        
+                  
+
+ 
+      
+                      
+
+
+
+  
+      
+                  
+
+
+  
+
+    else if (sext)
+        x_result_sel_sext =  1'b1;
+ 
+        
+    else if (logical) 
+        x_result_sel_logic =  1'b1;
+          
+      
+          
+
+
+    else 
+        x_result_sel_add =  1'b1;        
+    
+    
+
+    m_result_sel_compare = cmp;
+  
+
+    m_result_sel_shift = shift;
+ 
+
+
+    
+    w_result_sel_load = load;
+  
+
+    w_result_sel_mul = op_mul; 
+ 
+
+end
+
+
+assign x_bypass_enable =  arith 
+                        | logical
+  
+                         
+                         
+
+                        
+  
+                         
+
+
+  
+                         
+                         
+
+
+  
+                         
+
+                  
+  
+
+                        | sext 
+ 
+                        
+  
+                         
+
+
+                        | op_rcsr
+                        ;
+
+assign m_bypass_enable = x_bypass_enable 
+  
+
+                        | shift
+ 
+
+                        | cmp
+                        ;
+
+assign read_enable_0 = ~(op_bi | op_calli);
+assign read_idx_0 = instruction[25:21];
+
+assign read_enable_1 = ~(op_bi | op_calli | load);
+assign read_idx_1 = instruction[20:16];
+
+assign write_enable = ~(bra | op_raise | store | op_wcsr);
+assign write_idx = call
+                    ? 5'd29
+                    : instruction[31] == 1'b0 
+                        ? instruction[20:16] 
+                        : instruction[15:11];
+                        
+
+assign size = instruction[27:26];
+
+assign sign_extend = instruction[28];                      
+
+assign adder_op = op_sub | op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne | bra;
+
+assign logic_op = instruction[29:26];
+  
+
+
+assign direction = instruction[29];
+ 
+
+
+assign branch = bra | call;
+assign branch_reg = op_call | op_b;
+assign condition = instruction[28:26];      
+  
+     
+
+
+assign scall = op_raise & instruction[2];
+assign eret = op_b & (instruction[25:21] == 5'd30);
+  
+       
+
+
+  
+
+   
+
+
+
+assign csr_write_enable = op_wcsr;
+
+
+
+assign sign_extend_immediate = ~(op_and | op_cmpgeu | op_cmpgu | op_nor | op_or | op_xnor | op_xor);
+assign select_high_immediate = op_andhi | op_orhi;
+assign select_call_immediate = instruction[31];
+
+assign high_immediate = {instruction[15:0], 16'h0000};
+assign extended_immediate = {{16{sign_extend_immediate & instruction[15]}}, instruction[15:0]};
+assign call_immediate = {{6{instruction[25]}}, instruction[25:0]};
+assign branch_immediate = {{16{instruction[15]}}, instruction[15:0]};
+
+assign immediate = select_high_immediate ==  1'b1 
+                        ? high_immediate 
+                        : extended_immediate;
+   
+assign branch_offset = select_call_immediate ==  1'b1   
+                        ? (call_immediate[ (32-2)-1:0])
+                        : (branch_immediate[ (32-2)-1:0]);
+    
+endmodule 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+  
+
+           
+              
+              
+              
+
+           
+             
+           
+             
+
+                
+                  
+              
+            
+
+                 
+          
+               
+               
+              
+
+
+
+
+
+   
+    
+    
+        
+    
+    
+    
+    
+    
+    
+    
+    
+ 
+    
+
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+
+
+
+
+
+                               
+                                      
+                             
+                                
+                                       
+
+   
+   
+   
+   
+   
+   
+   
+   
+   
+
+
+
+
+
+                                         
+                                         
+
+                                       
+                                       
+
+                                       
+                        
+   
+                       
+                       
+                                 
+
+                                  
+            
+
+                                        
+ 
+                                      
+
+   
+
+
+
+
+                                
+   
+                              
+    
+                               
+   
+                 
+                    
+                                    
+    
+                  
+    
+
+
+
+
+
+ 
+  
+  
+  
+  
+  
+ 
+
+  
+  
+  
+  
+  
+
+  
+ 
+ 
+ 
+
+  
+  
+ 
+  
+
+ 
+
+
+
+
+
+ 
+
+
+
+
+
+   
+                 
+	  
+	   
+	    
+	     
+	       
+	                        
+	                     
+
+ 
+	    
+	     
+	      
+	                         
+	                        
+	                            
+	                     
+	                      
+	                    
+	                     
+	                     
+	                           
+	      
+	                        
+	      
+	   
+	    
+	     
+	       
+	                        
+	                     
+
+	        
+	    
+	     
+	      
+	                         
+	                        
+	                            
+	                     
+	                      
+	                    
+	                     
+	                       
+	                       
+	      
+	                         
+	      
+	   
+	
+
+
+
+
+
+
+
+
+               
+      
+       
+    
+
+
+
+
+       
+      
+       
+    
+        
+	   
+           
+    
+
+
+
+ 
+       
+    
+    
+   
+
+    
+   
+
+
+   
+    
+                                 
+                                 
+
+
+ 
+                                   
+     
+    
+   
+
+
+
+     
+
+
+
+        
+           
+     
+    
+    
+      
+         
+         
+    
+                     
+
+
+     
+   
+
+
+   
+   
+   
+
+               
+     
+     
+                      
+
+
+
+
+
+
+        
+            
+   
+
+       
+           
+    
+            
+           
+               
+    
+
+    
+
+
+
+   
+
+       
+          
+    
+          
+
+
+
+   
+
+       
+    
+          
+          
+          
+          
+    
+     
+    
+         
+
+        
+        
+                    
+               
+                  
+                
+        
+
+        
+        
+                    
+               
+ 
+	       
+                  
+	      
+
+		  
+	   
+                
+        
+        
+        
+        
+                    
+               
+                  
+               
+            
+                  
+                  
+            
+                
+            
+                  
+                  
+            
+        
+
+        
+        
+                    
+               
+            
+                   
+                
+                      
+                      
+                
+            
+        
+
+                
+    
+
+
+ 
+       
+    
+
+   
+
+       
+          
+     
+    
+         
+        
+        
+        
+                    
+               
+                  
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+        
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+                    
+               
+                    
+        
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+    
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+                    
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+                    
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+          
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+              
+                  
+                 
+            
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+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
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+           
+         
+       
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+          
+         
+     
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+               
+              
+          
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+                
+                
+                
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+           
+              
+              
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+             
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+                  
+              
+            
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+               
+               
+              
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+   
+    
+    
+        
+    
+    
+    
+    
+    
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+    
+    
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+    
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+    
+    
+    
+    
+    
+    
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+                                      
+                             
+                                
+                                       
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+   
+   
+   
+   
+   
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+          
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+                       
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+                                    
+   
+                                  
+    
+                                   
+    
+                   
+     
+                                        
+    
+                        
+    
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+                                   
+                                  
+                     
+                     
+        
+  
+                       
+                       
+                                               
+
+          
+         
+          
+         
+                 
+                     
+
+                           
+                                           
+                                              
+                                             
+
+                                        
+                
+             
+                                        
+                   
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+  
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+   
+                     
+	  
+	   
+              
+               
+		 
+		  
+		    
+		     
+		     
+
+		      
+		    
+		     
+		      
+		      
+		      
+		      
+		      
+		      
+		      
+		      
+		          
+		     
+		      
+		         
+             
+           
+             
+		               
+		    
+		      
+		       
+			 
+			  
+			  
+
+			   
+			 
+			  
+			   
+			   
+			   
+			   
+			   
+			   
+			   
+			       
+			       
+			  
+			   
+			  
+		  
+             
+	   
+	   
+	    
+	     
+	       
+	        
+	        
+
+	         
+	       
+		
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+		
+	
+      
+   
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+               
+      
+       
+    
+
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+           
+	   
+   
+    
+        
+	   
+        
+    
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+       
+    
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+ 
+
+       
+          
+    
+    
+              
+              
+              
+              
+    
+
+    
+    
+    
+
+ 
+
+       
+          
+    
+          
+
+    
+
+
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+ 
+        
+      
+                              
+                             
+    
+      
+                             
+                             
+
+   
+
+     
+                             
+                             
+   
+
+
+ 
+                                   
+     
+    
+   
+
+
+
+     
+       
+
+
+         
+
+
+
+        
+           
+             
+         
+     
+     
+      
+                 
+                 
+             
+             
+    
+
+
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+             
+   
+
+
+   
+   
+   
+
+           
+     
+                      
+
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+
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+
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+        
+            
+   
+
+       
+           
+    
+            
+           
+               
+    
+
+     
+   
+
+
+   
+
+       
+          
+     
+          
+
+
+
+   
+
+       
+    
+          
+          
+          
+          
+          
+    
+     
+    
+         
+
+        
+        
+        
+               
+                  
+                
+        
+        
+        
+        
+        
+               
+                  
+               
+            
+                  
+                  
+                  
+            
+                
+                  
+        
+
+        
+        
+        
+              
+               
+            
+                   
+                
+                      
+                      
+                
+            
+        
+        
+                
+    
+
+
+
+       
+    
+
+   
+
+       
+          
+     
+    
+         
+        
+        
+        
+        
+               
+                  
+        
+
+        
+        
+        
+               
+                    
+        
+        
+                
+    
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+    
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+    
+   
+  
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+ 
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+                  
+                    
+                 
+                   
+           
+             
+
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+                   
+               
+                 
+
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+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
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+                      
+
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+           
+             
+
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+                
+           
+
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+              
+               
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+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
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+                  
+                    
+                   
+                  
+                   
+          
+
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+                   
+                     
+
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+                   
+                     
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+                    
+                     
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+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
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+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
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+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
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+                   
+             
+               
+
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+                  
+                    
+                 
+                   
+
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+                   
+                   
+                   
+                   
+
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+                  
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+                 
+                   
+               
+              
+          
+                   
+
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+                 
+                   
+                
+                
+                
+               
+
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+
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+  
+
+
+                  
+                 
+         
+     
+     
+              
+
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+
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+  
+    
+     
+    
+    
+    
+    
+    
+    
+    
+    
+ 
+ 
+    
+    
+    
+
+ 
+   
+   
+   
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+ 
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+		   
+ 
+    
+    
+    
+    
+    
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+    
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+    
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+                                     
+                                     
+
+                        
+                                    
+                                   
+      
+                        
+            
+                      
+ 
+ 
+                     
+       
+                   
+
+    
+                          
+            
+                          
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+
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+ 
+                                  
+                                  
+                                   
+                               
+                                       
+ 
+                     
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+                                    
+    
+
+                                    
+    
+                                 
+           
+                                 
+   
+
+
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+
+
+                                        
+
+
+
+         
+                       
+                
+
+     
+         
+                
+
+                     
+       
+                   
+
+ 
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+             
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+ 
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+
+
+               
+      
+         
+    
+
+ 
+ 
+        
+       
+    
+     
+
+        
+   
+    
+   
+
+    
+               
+
+ 
+               
+      
+             
+                   
+
+
+        
+                   
+    
+   
+
+                
+                 
+
+ 
+         
+         
+         
+
+   
+ 
+         
+         
+         
+
+
+   
+
+   
+   
+   
+
+
+
+
+
+
+
+
+               
+      
+   
+
+       
+    
+          
+          
+    
+    
+    
+                 
+        
+              
+              
+        
+    
+    
+    
+
+
+
+
+               
+      
+   
+
+       
+    
+          
+          
+    
+    
+    
+           
+        
+               
+                  
+                 
+                  
+        
+      
+
+    
+
+
+
+   
+
+       
+          
+    
+    
+               
+              
+    
+    
+
+ 
+
+   
+
+       
+    
+          
+          
+    
+    
+    
+               
+        
+              
+                
+                  
+             
+                  
+        
+         
+        
+        
+            
+                     
+                       
+                    
+                   
+               
+                   
+        
+        
+        
+            
+                   
+                  
+        
+        
+        
+            
+ 
+               
+                  
+             
+
+                            
+            
+                  
+                  
+            
+        
+        
+        
+            
+ 
+               
+                  
+             
+
+                  
+        
+        
+    
+
+
+
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+  
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+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
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+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
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+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_instruction_unit_medium (
+    
+    clk_i,
+    rst_i,
+    
+    stall_a,
+    stall_f,
+    stall_d,
+    stall_x,
+    stall_m,
+    valid_f,
+    valid_d,
+    kill_f,
+    branch_predict_taken_d,
+    branch_predict_address_d,
+      
+    
+    
+
+
+    exception_m,
+    branch_taken_m,
+    branch_mispredict_taken_m,
+    branch_target_m,
+  
+    
+
+
+  
+    
+    
+    
+
+        
+  
+
+    
+    i_dat_i,
+    i_ack_i,
+    i_err_i,
+    i_rty_i,
+ 
+
+  
+    
+    
+    
+    
+
+
+    
+    
+    pc_f,
+    pc_d,
+    pc_x,
+    pc_m,
+    pc_w,
+  
+    
+    
+    
+    
+
+
+  
+
+    
+    i_dat_o,
+    i_adr_o,
+    i_cyc_o,
+    i_sel_o,
+    i_stb_o,
+    i_we_o,
+    i_cti_o,
+    i_lock_o,
+    i_bte_o,
+ 
+
+  
+    
+    
+    
+
+
+  
+    
+    
+
+
+  
+    
+
+
+  
+
+    instruction_f,
+ 
+    
+    instruction_d
+    );
+
+
+
+
+
+parameter eba_reset =  32'h00000000;                   
+parameter associativity = 1;                            
+parameter sets = 512;                                   
+parameter bytes_per_line = 16;                          
+parameter base_address = 0;                             
+parameter limit = 0;                                    
+
+
+localparam eba_reset_minus_4 = eba_reset - 4;
+localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
+localparam addr_offset_lsb = 2;
+localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
+
+
+
+
+  
+  
+   
+        
+   
+
+
+
+input clk_i;                                            
+input rst_i;                                            
+
+input stall_a;                                          
+input stall_f;                                          
+input stall_d;                                          
+input stall_x;                                          
+input stall_m;                                          
+input valid_f;                                          
+input valid_d;                                          
+input kill_f;                                           
+
+input branch_predict_taken_d;                           
+input [ ((32-2)+2-1):2] branch_predict_address_d;          
+   
+      
+                                    
+                     
+
+
+input exception_m;
+input branch_taken_m;                                   
+input branch_mispredict_taken_m;                        
+input [ ((32-2)+2-1):2] branch_target_m;                   
+
+  
+                                            
+
+
+  
+                            
+                             
+ 
+
+        
+
+
+  
+
+input [ (32-1):0] i_dat_i;                         
+input i_ack_i;                                          
+input i_err_i;                                          
+input i_rty_i;                                          
+ 
+
+
+  
+                                  
+                                 
+                   
+                      
+
+
+
+
+
+
+        
+output [ ((32-2)+2-1):2] pc_f;                             
+reg    [ ((32-2)+2-1):2] pc_f;
+output [ ((32-2)+2-1):2] pc_d;                             
+reg    [ ((32-2)+2-1):2] pc_d;
+output [ ((32-2)+2-1):2] pc_x;                             
+reg    [ ((32-2)+2-1):2] pc_x;
+output [ ((32-2)+2-1):2] pc_m;                             
+reg    [ ((32-2)+2-1):2] pc_m;
+output [ ((32-2)+2-1):2] pc_w;                             
+reg    [ ((32-2)+2-1):2] pc_w;
+
+  
+                             
+   
+                           
+   
+                            
+   
+                                 
+   
+
+
+
+  
+
+output [ (32-1):0] i_dat_o;                        
+  
+     
+
+
+wire   [ (32-1):0] i_dat_o;
+ 
+
+output [ (32-1):0] i_adr_o;                        
+reg    [ (32-1):0] i_adr_o;
+output i_cyc_o;                                         
+reg    i_cyc_o; 
+output [ (4-1):0] i_sel_o;                 
+  
+     
+
+
+wire   [ (4-1):0] i_sel_o;
+ 
+
+output i_stb_o;                                         
+reg    i_stb_o;
+output i_we_o;                                          
+  
+    
+
+
+wire   i_we_o;
+ 
+
+output [ (3-1):0] i_cti_o;                       
+reg    [ (3-1):0] i_cti_o;
+output i_lock_o;                                        
+reg    i_lock_o;
+output [ (2-1):0] i_bte_o;                       
+wire   [ (2-1):0] i_bte_o;
+ 
+
+
+  
+                   
+     
+                             
+   
+
+
+
+  
+                                      
+    
+
+
+  
+
+output [ (32-1):0] instruction_f;           
+wire   [ (32-1):0] instruction_f;
+ 
+
+output [ (32-1):0] instruction_d;           
+reg    [ (32-1):0] instruction_d;
+
+
+
+
+
+reg [ ((32-2)+2-1):2] pc_a;                                
+
+  
+                       
+
+
+
+  
+                               
+                
+                                 
+           
+               
+                  
+                   
+                                          
+                        
+
+
+  
+
+reg [ (32-1):0] wb_data_f;                  
+ 
+
+ 
+
+  
+                                      
+    			     
+   
+
+
+  
+
+ 
+               
+
+
+
+   
+  
+   
+    			               
+ 
+
+
+  
+    		       
+
+
+   
+  
+                                         
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+  
+
+ 
+              
+                       
+             
+               
+                      
+       
+    
+                      
+                            
+                    
+                    
+     
+                    
+                  
+                  
+              
+               
+                
+                     
+    
+              
+            
+             
+             
+                  
+                       
+    
+
+
+
+
+
+
+
+  
+   
+           
+        
+  
+      
+                          
+   
+				       
+        
+				    
+
+ 
+
+
+always @(*)
+begin
+    
+  
+       
+          
+     
+
+    
+      if (branch_taken_m ==  1'b1)
+	if ((branch_mispredict_taken_m ==  1'b1) && (exception_m ==  1'b0))
+	  pc_a = pc_x;
+	else
+          pc_a = branch_target_m;
+      
+          
+          
+
+
+      else
+	if ( (valid_d ==  1'b1) && (branch_predict_taken_d ==  1'b1) )
+	  pc_a = branch_predict_address_d;
+	else
+  
+             
+              
+	   
+
+        
+            pc_a = pc_f + 1'b1;
+end
+
+
+  
+      
+      
+        
+
+
+
+  
+
+     
+    	      
+
+     
+      
+	  
+       
+	  
+	
+	    
+     
+   
+   
+          
+
+
+  
+   
+
+
+                     
+
+  
+   
+
+
+assign instruction_f = wb_data_f;
+ 
+
+
+ 
+ 
+   
+
+  
+
+  
+
+
+assign i_dat_o = 32'd0;
+assign i_we_o =  1'b0;
+assign i_sel_o = 4'b1111;
+ 
+
+assign i_bte_o =  2'b00;
+ 
+
+
+  
+
+
+     
+    
+    
+   
+   
+   
+   
+    
+    
+    
+   
+   
+     
+    
+    
+    
+    
+   
+         
+     
+    
+    
+    
+
+
+
+                     
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        pc_f <= eba_reset_minus_4[ ((32-2)+2-1):2];
+        pc_d <= { (32-2){1'b0}};
+        pc_x <= { (32-2){1'b0}};
+        pc_m <= { (32-2){1'b0}};
+        pc_w <= { (32-2){1'b0}};
+    end
+    else
+    begin
+        if (stall_f ==  1'b0)
+            pc_f <= pc_a;
+        if (stall_d ==  1'b0)
+            pc_d <= pc_f;
+        if (stall_x ==  1'b0)
+            pc_x <= pc_d;
+        if (stall_m ==  1'b0)
+            pc_m <= pc_x;
+        pc_w <= pc_m;
+    end
+end
+
+  
+
+   
+
+       
+          
+    
+    
+ 
+         
+            
+               
+                  
+                    
+                  
+
+               
+                  
+
+
+         
+               
+                  
+
+
+    
+
+
+
+
+
+  
+   
+
+       
+          
+    
+    
+           
+              
+    
+
+
+
+
+  
+    
+                 
+ 
+
+     
+       
+       
+       
+       
+     
+
+   
+
+
+
+  
+
+   
+                   
+      
+     
+	   
+	  
+               
+               
+               
+               
+               
+               
+               
+   
+               
+  
+   
+               
+               
+               
+  
+	  
+	
+	     
+               
+             
+                
+               
+		  
+		         
+		    
+   
+                          
+			 
+			      
+			             
+			        
+			          
+			 
+                       
+  
+			 
+			       
+			      
+				 
+				   
+				   
+				   
+			      
+			    
+			        
+			      
+			    
+			      
+			      
+			 
+		    
+   
+		   
+		     
+		    
+                         
+                         
+		    
+		  
+  
+               
+             
+               
+		         
+		    
+                       
+        
+                         
+  
+                          
+                         
+                                         
+                         
+                       
+   
+                         
+  
+		    
+   
+		  
+		    
+                              
+			 
+			     
+			         
+			         
+			         
+			         
+			    
+			      
+			      
+			      
+			      
+			      
+			      
+			      
+			 
+		     
+                      
+   
+		  
+		  
+        
+		     
+                      
+   
+		     
+                      
+  
+               
+	  
+     
+ 
+
+   always @(posedge clk_i  )
+     begin
+	if (rst_i ==  1'b1)
+	  begin
+             i_cyc_o <=  1'b0;
+             i_stb_o <=  1'b0;
+             i_adr_o <= { 32{1'b0}};
+             i_cti_o <=  3'b111;
+             i_lock_o <=  1'b0;
+             wb_data_f <= { 32{1'b0}};
+    
+               
+  
+
+	  end
+	else
+	  begin   
+             
+             if (i_cyc_o ==  1'b1)
+               begin
+		  
+		  if((i_ack_i ==  1'b1) || (i_err_i ==  1'b1))
+		    begin
+                       
+                       i_cyc_o <=  1'b0;
+                       i_stb_o <=  1'b0;
+                       
+                       wb_data_f <= i_dat_i;
+		    end
+    
+		   
+		     
+		    
+                         
+                         
+		       
+		    
+		  
+  
+
+               end
+             else
+               begin
+		  
+		  if (   (stall_a ==  1'b0) 
+     
+			    
+  
+       
+			 )
+		    begin
+                       
+         
+                         
+  
+
+                       i_adr_o <= {pc_a, 2'b00};
+                       i_cyc_o <=  1'b1;
+                       i_stb_o <=  1'b1;
+    
+                         
+  
+
+		    end
+		  else
+		    begin
+	               if (   (stall_a ==  1'b0) 
+     
+			         
+  
+       
+			      )
+			 begin
+    
+			      
+  
+
+			 end
+		    end
+               end
+	  end
+     end
+  
+
+ 
+ 
+
+   
+   always @(posedge clk_i  )
+     begin
+	if (rst_i ==  1'b1)
+	  begin
+             instruction_d <= { 32{1'b0}};
+  
+               
+
+
+	  end
+	else
+	  begin
+             if (stall_d ==  1'b0)
+               begin
+		  instruction_d <= instruction_f;
+  
+		    
+
+
+               end
+	  end
+     end  
+   
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+  
+
+                              
+                              
+                              
+
+
+                          
+                  
+                 
+              
+             
+                    
+                        
+                        
+
+
+                  
+         
+          
+          
+          
+          
+          
+      
+      
+         
+
+
+
+
+
+  
+    
+    
+    
+     
+    
+    
+    
+ 
+    
+    
+    
+    
+
+ 
+    
+    
+
+ 
+    
+
+    
+ 
+    
+    
+
+ 
+    
+    
+    
+    
+    
+    
+    
+
+ 
+    
+    
+
+    
+    
+    
+
+
+
+
+
+                                             
+                                             
+
+                                          
+                                       
+                        
+                              
+
+ 
+                                
+                                  
+                    
+                                           
+
+ 
+                    
+                              
+
+ 
+                                     
+
+
+
+
+
+       
+ 
+                
+    
+                
+    
+
+ 
+                            
+    
+              
+    
+                          
+    
+                                 
+    
+                                
+    
+                  
+            
+                     
+    
+
+ 
+                                       
+    
+                                       
+    
+
+  
+     
+  
+    
+             
+
+
+
+
+                           
+                         
+                       
+                     
+
+
+
+     
+  
+
+                  
+        
+                       
+        
+                       
+
+
+               
+ 
+         
+  
+  
+  
+  
+                          
+
+
+         
+
+
+
+
+
+ 
+      
+   
+      
+   
+
+                 
+
+                  
+             
+
+   
+
+ 
+   
+
+   
+
+
+                  
+     
+     
+         
+                 
+
+
+
+
+   
+   
+
+
+
+   
+
+       
+    
+          
+          
+          
+          
+    
+    
+    
+          
+          
+          
+          
+    
+
+
+
+   
+
+       
+    
+          
+          
+          
+ 
+          
+          
+          
+          
+
+ 
+          
+          
+
+                  
+          
+          
+          
+          
+
+    
+    
+    
+                  
+               
+        
+             
+            
+            
+                
+                  
+                  
+            
+            
+            
+                
+                  
+            
+            
+        
+
+ 
+        
+           
+        
+              
+              
+        
+
+         
+        
+        
+            
+                 
+            
+                                  
+                 
+ 
+                
+                
+                     
+ 
+                    
+                          
+                    
+                    
+                              
+                          
+                    
+                    
+                          
+                    
+                    
+                              
+                          
+                    
+                    
+                          
+                    
+                    
+                    
+      
+                              
+                                   
+
+                          
+                    
+                    
+                    
+      
+                              
+                                   
+
+                          
+                    
+                                                   
+                
+
+                  
+                
+                
+                      
+                      
+                                    
+                
+                
+                      
+                      
+                
+
+                
+                    
+                                
+            
+        
+ 
+        
+        
+                 
+            
+                  
+                  
+            
+        
+        
+        
+                 
+            
+                  
+                  
+            
+        
+        
+        
+                 
+            
+                  
+                  
+            
+        
+        
+        
+                 
+            
+                  
+                   
+                      
+                 
+                      
+            
+        
+        
+        
+                 
+            
+                  
+                  
+            
+        
+        
+        
+             
+            
+            
+            
+                  
+                  
+                  
+            
+            
+            
+            
+                  
+                  
+                  
+            
+            
+            
+                  
+                  
+                  
+            
+            
+        
+        
+        
+               
+                      
+                  
+                  
+                    
+                  
+                  
+            
+            
+        
+        
+              
+              
+              
+            
+
+        
+    
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_interrupt_medium (
+    
+    clk_i, 
+    rst_i,
+    
+    interrupt,
+    
+    stall_x,
+  
+    
+    
+
+
+    exception,
+ 
+
+    eret_q_x,
+  
+    
+
+
+    csr,
+    csr_write_data,
+    csr_write_enable,
+    
+    interrupt_exception,
+    
+    csr_read_data
+    );
+
+
+
+
+
+parameter interrupts =  32;         
+
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+
+input [interrupts-1:0] interrupt;               
+
+input stall_x;                                  
+
+  
+                       
+                           
+
+
+input exception;                                
+ 
+
+input eret_q_x;                                 
+  
+                                  
+
+
+
+input [ (4 -1):0] csr;                      
+input [ (32-1):0] csr_write_data;          
+input csr_write_enable;                         
+
+
+
+
+
+output interrupt_exception;                     
+wire   interrupt_exception;
+
+output [ (32-1):0] csr_read_data;          
+reg    [ (32-1):0] csr_read_data;
+
+
+
+
+
+wire [interrupts-1:0] asserted;                 
+
+wire [interrupts-1:0] interrupt_n_exception;
+
+
+
+reg ie;                                         
+reg eie;                                        
+  
+                                         
+
+
+reg [interrupts-1:0] ip;                        
+reg [interrupts-1:0] im;                        
+
+
+
+
+
+
+assign interrupt_n_exception = ip & im;
+
+
+assign interrupt_exception = (|interrupt_n_exception) & ie;
+
+
+assign asserted = ip | interrupt;
+       
+generate
+    if (interrupts > 1) 
+    begin
+
+always @(*)
+begin
+    case (csr)
+     4 'h0:  csr_read_data = {{ 32-3{1'b0}}, 
+  
+                                    
+
+
+                                    1'b0,                                     
+ 
+
+                                    eie, 
+                                    ie
+                                   };
+     4 'h2:  csr_read_data = ip;
+     4 'h1:  csr_read_data = im;
+    default:       csr_read_data = { 32{1'bx}};
+    endcase
+end
+    end
+    else
+    begin
+
+always @(*)
+begin
+    case (csr)
+     4 'h0:  csr_read_data = {{ 32-3{1'b0}}, 
+  
+                                     
+
+
+                                    1'b0,                                    
+ 
+
+                                    eie, 
+                                    ie
+                                   };
+     4 'h2:  csr_read_data = ip;
+    default:       csr_read_data = { 32{1'bx}};
+      endcase
+end
+    end
+endgenerate
+    
+
+
+
+
+  
+
+   reg [ 10:0] eie_delay  = 0;
+
+   
+generate
+
+   
+    if (interrupts > 1)
+    begin
+
+always @(posedge clk_i  )
+  begin
+    if (rst_i ==  1'b1)
+    begin
+        ie                   <=  1'b0;
+        eie                  <=  1'b0;
+  
+                           
+
+
+        im                   <= {interrupts{1'b0}};
+        ip                   <= {interrupts{1'b0}};
+       eie_delay             <= 0;
+       
+    end
+    else
+    begin
+        
+        ip                   <= asserted;
+  
+           
+        
+            
+                           
+                            
+        
+            
+        
+            
+                           
+                            
+        
+
+
+        if (exception ==  1'b1)
+        begin
+            
+            eie              <= ie;
+            ie               <=  1'b0;
+        end
+ 
+
+        else if (stall_x ==  1'b0)
+        begin
+
+           if(eie_delay[0])
+             ie              <= eie;
+           
+           eie_delay         <= {1'b0, eie_delay[ 10:1]};
+
+            if (eret_q_x ==  1'b1) begin
+                
+               eie_delay[ 10] <=  1'b1;
+               eie_delay[ 10-1:0] <= 0;
+            end
+           
+                      
+           
+  
+                
+                
+                       
+
+
+            else if (csr_write_enable ==  1'b1)
+            begin
+                
+                if (csr ==  4 'h0)
+                begin
+                    ie  <= csr_write_data[0];
+                    eie <= csr_write_data[1];
+  
+                      
+
+
+                end
+                if (csr ==  4 'h1)
+                    im  <= csr_write_data[interrupts-1:0];
+                if (csr ==  4 'h2)
+                    ip  <= asserted & ~csr_write_data[interrupts-1:0];
+            end
+        end
+    end
+end
+    end
+else
+    begin
+
+always @(posedge clk_i  )
+  begin
+    if (rst_i ==  1'b1)
+    begin
+        ie              <=  1'b0;
+        eie             <=  1'b0;
+  
+                      
+
+
+        ip              <= {interrupts{1'b0}};
+       eie_delay        <= 0;
+    end
+    else
+    begin
+        
+        ip              <= asserted;
+  
+           
+        
+            
+                      
+                       
+        
+            
+        
+            
+                      
+                       
+        
+
+
+        if (exception ==  1'b1)
+        begin
+            
+            eie         <= ie;
+            ie          <=  1'b0;
+        end
+ 
+
+        else if (stall_x ==  1'b0)
+          begin
+
+             if(eie_delay[0])
+               ie              <= eie;
+           
+             eie_delay         <= {1'b0, eie_delay[ 10:1]};
+
+             if (eret_q_x ==  1'b1) begin
+                
+                eie_delay[ 10] <=  1'b1;
+                eie_delay[ 10-1:0] <= 0;
+             end
+           
+  
+                
+                
+                       
+
+
+            else if (csr_write_enable ==  1'b1)
+            begin
+                
+                if (csr ==  4 'h0)
+                begin
+                    ie  <= csr_write_data[0];
+                    eie <= csr_write_data[1];
+  
+                      
+
+
+                end
+                if (csr ==  4 'h2)
+                    ip  <= asserted & ~csr_write_data[interrupts-1:0];
+            end
+        end
+    end
+end
+    end
+endgenerate
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	 
+
+ 
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+  
+
+
+
+
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+ 
+
+
+
+  
+
+  
+
+ 
+
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+ 
+ 
+                    
+
+  
+                    
+
+
+
+  
+
+
+
+  
+
+  
+
+
+
+  
+
+  
+
+
+
+  
+
+  
+
+
+
+  
+ 
+
+
+  
+
+  
+
+ 
+
+ 
+
+
+
+  
+
+  
+
+ 
+ 
+ 
+
+
+
+
+
+
+  
+
+  
+
+  
+ 
+ 
+
+ 
+
+
+ 
+
+
+  
+
+  
+
+ 
+ 
+ 
+
+
+
+
+
+  
+ 
+
+
+  
+ 
+
+
+  
+ 
+
+
+
+
+  
+
+  
+
+ 
+
+  
+ 
+
+
+
+
+  
+
+
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+ 
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+ 
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+ 
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+ 
+ 
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+  
+
+  
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+
+  
+
+  
+
+
+
+  
+
+  
+
+ 
+ 
+ 
+
+
+
+
+
+
+
+
+
+  
+
+  
+
+  
+
+
+
+
+
+
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+
+
+  
+
+
+
+
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+ 
+
+
+
+
+
+
+
+
+module lm32_top_medium_debug (
+    
+    clk_i,
+    rst_i,
+    
+
+    interrupt,
+
+    
+  
+    
+    
+
+     
+  
+
+    
+    I_DAT_I,
+    I_ACK_I,
+    I_ERR_I,
+    I_RTY_I,
+ 
+
+    
+    D_DAT_I,
+    D_ACK_I,
+    D_ERR_I,
+    D_RTY_I,
+    
+      
+    
+    
+    
+    
+
+    
+  
+
+    
+    I_DAT_O,
+    I_ADR_O,
+    I_CYC_O,
+    I_SEL_O,
+    I_STB_O,
+    I_WE_O,
+    I_CTI_O,
+    I_LOCK_O,
+    I_BTE_O,
+ 
+
+    
+    D_DAT_O,
+    D_ADR_O,
+    D_CYC_O,
+    D_SEL_O,
+    D_STB_O,
+    D_WE_O,
+    D_CTI_O,
+    D_LOCK_O,
+    D_BTE_O
+    );
+
+parameter eba_reset = 32'h00000000;
+parameter sdb_address = 32'h00000000;
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+
+
+input [ (32-1):0] interrupt;          
+
+
+  
+               
+                             
+
+    
+
+  
+
+input [ (32-1):0] I_DAT_I;                 
+input I_ACK_I;                                  
+input I_ERR_I;                                  
+input I_RTY_I;                                  
+ 
+
+
+input [ (32-1):0] D_DAT_I;                 
+input D_ACK_I;                                  
+input D_ERR_I;                                  
+input D_RTY_I;                                  
+
+
+
+
+
+  
+                               
+   
+       
+     
+           
+    
+           
+    
+
+
+
+  
+
+output [ (32-1):0] I_DAT_O;                
+wire   [ (32-1):0] I_DAT_O;
+output [ (32-1):0] I_ADR_O;                
+wire   [ (32-1):0] I_ADR_O;
+output I_CYC_O;                                 
+wire   I_CYC_O;
+output [ (4-1):0] I_SEL_O;         
+wire   [ (4-1):0] I_SEL_O;
+output I_STB_O;                                 
+wire   I_STB_O;
+output I_WE_O;                                  
+wire   I_WE_O;
+output [ (3-1):0] I_CTI_O;               
+wire   [ (3-1):0] I_CTI_O;
+output I_LOCK_O;                                
+wire   I_LOCK_O;
+output [ (2-1):0] I_BTE_O;               
+wire   [ (2-1):0] I_BTE_O;
+ 
+
+
+output [ (32-1):0] D_DAT_O;                
+wire   [ (32-1):0] D_DAT_O;
+output [ (32-1):0] D_ADR_O;                
+wire   [ (32-1):0] D_ADR_O;
+output D_CYC_O;                                 
+wire   D_CYC_O;
+output [ (4-1):0] D_SEL_O;         
+wire   [ (4-1):0] D_SEL_O;
+output D_STB_O;                                 
+wire   D_STB_O;
+output D_WE_O;                                  
+wire   D_WE_O;
+output [ (3-1):0] D_CTI_O;               
+wire   [ (3-1):0] D_CTI_O;
+output D_LOCK_O;                                
+wire   D_LOCK_O;
+output [ (2-1):0] D_BTE_O;               
+wire   [ (2-1):0] D_BTE_O;
+  
+
+
+
+ 
+  
+
+
+wire [ 7:0] jtag_reg_d;
+wire [ 7:0] jtag_reg_q;
+wire jtag_update;
+wire [2:0] jtag_reg_addr_d;
+wire [2:0] jtag_reg_addr_q;
+wire jtck;
+wire jrstn;
+ 
+
+
+
+  
+
+                     
+                             
+                            
+                   
+                                 
+ 
+                                 
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+   
+
+lm32_cpu_medium_debug 
+	#(
+		.eba_reset(eba_reset),
+    .sdb_address(sdb_address)
+	) cpu (
+    
+    .clk_i                 (clk_i),
+  
+                   
+
+
+    .rst_i                 (rst_i),
+    
+  
+
+    .interrupt             (interrupt),
+ 
+
+    
+  
+               
+             
+
+     
+  
+
+    
+    .jtag_clk              (jtck),
+    .jtag_update           (jtag_update),
+    .jtag_reg_q            (jtag_reg_q),
+    .jtag_reg_addr_q       (jtag_reg_addr_q),
+ 
+
+  
+
+     
+    .I_DAT_I               (I_DAT_I),
+    .I_ACK_I               (I_ACK_I),
+    .I_ERR_I               (I_ERR_I),
+    .I_RTY_I               (I_RTY_I),
+ 
+
+    
+    .D_DAT_I               (D_DAT_I),
+    .D_ACK_I               (D_ACK_I),
+    .D_ERR_I               (D_ERR_I),
+    .D_RTY_I               (D_RTY_I),
+    
+  
+                  
+            
+           
+                 
+                
+ 
+                
+
+
+
+  
+
+    .jtag_reg_d            (jtag_reg_d),
+    .jtag_reg_addr_d       (jtag_reg_addr_d),
+ 
+
+      
+                
+               
+            
+            
+
+    
+  
+
+    
+    .I_DAT_O               (I_DAT_O),
+    .I_ADR_O               (I_ADR_O),
+    .I_CYC_O               (I_CYC_O),
+    .I_SEL_O               (I_SEL_O),
+    .I_STB_O               (I_STB_O),
+    .I_WE_O                (I_WE_O),
+    .I_CTI_O               (I_CTI_O),
+    .I_LOCK_O              (I_LOCK_O),
+    .I_BTE_O               (I_BTE_O),
+     
+
+    
+    .D_DAT_O               (D_DAT_O),
+    .D_ADR_O               (D_ADR_O),
+    .D_CYC_O               (D_CYC_O),
+    .D_SEL_O               (D_SEL_O),
+    .D_STB_O               (D_STB_O),
+    .D_WE_O                (D_WE_O),
+    .D_CTI_O               (D_CTI_O),
+    .D_LOCK_O              (D_LOCK_O),
+    .D_BTE_O               (D_BTE_O)
+    );
+   
+  
+		   
+
+jtag_cores jtag_cores (
+    
+    .reg_d                 (jtag_reg_d),
+    .reg_addr_d            (jtag_reg_addr_d),
+    
+    .reg_update            (jtag_update),
+    .reg_q                 (jtag_reg_q),
+    .reg_addr_q            (jtag_reg_addr_q),
+    .jtck                  (jtck),
+    .jrstn                 (jrstn)
+    );
+ 
+        
+   
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+           
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_mc_arithmetic_medium_debug (
+    
+    clk_i,
+    rst_i,
+    stall_d,
+    kill_x,
+  
+    
+    
+
+
+  
+    
+
+
+  
+    
+    
+    
+
+
+    operand_0_d,
+    operand_1_d,
+    
+    result_x,
+  
+    
+
+
+    stall_request_x
+    );
+
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+input stall_d;                                  
+input kill_x;                                   
+  
+                                  
+                                 
+
+
+  
+                                
+
+
+  
+                              
+                             
+                             
+
+
+input [ (32-1):0] operand_0_d;
+input [ (32-1):0] operand_1_d;
+
+
+
+
+
+output [ (32-1):0] result_x;               
+reg    [ (32-1):0] result_x;
+  
+                         
+    
+
+
+output stall_request_x;                         
+wire   stall_request_x;
+
+
+
+
+
+reg [ (32-1):0] p;                         
+reg [ (32-1):0] a;
+reg [ (32-1):0] b;
+  
+  
+
+
+
+reg [ 2:0] state;                 
+reg [5:0] cycles;                               
+
+  
+                               
+                                 
+
+
+
+
+
+
+
+
+assign stall_request_x = state !=  3'b000;
+
+  
+
+      
+
+
+
+  
+
+       
+
+
+
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        cycles <= {6{1'b0}};
+        p <= { 32{1'b0}};
+        a <= { 32{1'b0}};
+        b <= { 32{1'b0}};
+  
+          
+
+
+  
+          
+
+
+        result_x <= { 32{1'b0}};
+        state <=  3'b000;
+    end
+    else
+    begin
+  
+          
+
+
+        case (state)
+         3'b000:
+        begin
+            if (stall_d ==  1'b0)                 
+            begin          
+                cycles <=  32;
+                p <= 32'b0;
+                a <= operand_0_d;
+                b <= operand_1_d;                    
+  
+                   
+                      
+                   
+                      
+
+                    
+  
+                   
+                      
+
+
+  
+                   
+                
+                      
+                      
+                      
+                      
+                      
+                
+                   
+                
+                      
+                      
+                      
+                      
+                      
+                
+
+
+            end            
+        end
+  
+        
+        
+               
+            
+                  
+                   
+            
+             
+            
+                   
+                   
+            
+              
+                   
+            
+                
+                    
+                  
+            
+                
+        
+        
+        
+               
+            
+                  
+                   
+            
+             
+            
+                   
+                   
+            
+              
+                   
+            
+                
+                    
+                  
+            
+                
+        
+
+        
+  
+        
+        
+               
+                    
+               
+               
+              
+                   
+                  
+                
+        
+
+     
+  
+        
+               
+               
+              
+                   
+                  
+                
+        
+        
+               
+               
+              
+                   
+                  
+                
+        
+
+   
+        endcase
+    end
+end 
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_cpu_medium_debug (
+    
+    clk_i,
+  
+    
+
+
+    rst_i,
+  
+    
+
+
+  
+   
+   
+   
+   
+   
+   
+
+
+
+    
+  
+
+    interrupt,
+ 
+
+    
+  
+    
+    
+
+     
+  
+
+    
+    jtag_clk,
+    jtag_update, 
+    jtag_reg_q,
+    jtag_reg_addr_q,
+ 
+
+  
+
+    
+    I_DAT_I,
+    I_ACK_I,
+    I_ERR_I,
+    I_RTY_I,
+ 
+
+    
+    D_DAT_I,
+    D_ACK_I,
+    D_ERR_I,
+    D_RTY_I,
+    
+  
+    
+    
+    
+    
+    
+ 
+    
+
+
+
+  
+
+    jtag_reg_d,
+    jtag_reg_addr_d,
+ 
+
+      
+    
+    
+    
+    
+
+    
+  
+
+    
+    I_DAT_O,
+    I_ADR_O,
+    I_CYC_O,
+    I_SEL_O,
+    I_STB_O,
+    I_WE_O,
+    I_CTI_O,
+    I_LOCK_O,
+    I_BTE_O,
+ 
+ 
+  
+    
+    
+    
+    
+    
+    
+    
+    
+           
+
+
+		 
+		 
+    
+    D_DAT_O,
+    D_ADR_O,
+    D_CYC_O,
+    D_SEL_O,
+    D_STB_O,
+    D_WE_O,
+    D_CTI_O,
+    D_LOCK_O,
+    D_BTE_O
+
+		 
+    );
+
+
+
+
+
+parameter eba_reset =  32'h00000000;                           
+  
+
+parameter deba_reset =  32'h10000000;                         
+ 
+
+parameter sdb_address =   32'h00000000;
+
+  
+
+parameter icache_associativity =  1;     
+parameter icache_sets =  256;                       
+parameter icache_bytes_per_line =  16;   
+parameter icache_base_address =  32'h0;       
+parameter icache_limit =  32'h7fffffff;                     
+ 
+       
+                         
+     
+         
+                       
+
+
+
+  
+        
+                          
+      
+          
+                        
+
+
+parameter dcache_associativity = 1;    
+parameter dcache_sets = 512;                      
+parameter dcache_bytes_per_line = 16;  
+parameter dcache_base_address = 0;      
+parameter dcache_limit = 0;                    
+ 
+
+
+  
+
+parameter watchpoints =  32'h4;                       
+ 
+   
+
+
+  
+                          
+
+
+parameter breakpoints = 0;
+ 
+
+
+  
+
+parameter interrupts =  32;                         
+ 
+   
+
+
+
+
+
+
+
+input clk_i;                                    
+  
+                                   
+
+    
+input rst_i;                                    
+
+  
+
+input [ (32-1):0] interrupt;          
+ 
+
+
+  
+               
+                             
+
+    
+
+  
+ 
+input jtag_clk;                                 
+input jtag_update;                              
+input [ 7:0] jtag_reg_q;              
+input [2:0] jtag_reg_addr_q;
+ 
+
+
+  
+
+input [ (32-1):0] I_DAT_I;                 
+input I_ACK_I;                                  
+input I_ERR_I;                                  
+input I_RTY_I;                                  
+ 
+
+
+input [ (32-1):0] D_DAT_I;                 
+input D_ACK_I;                                  
+input D_ERR_I;                                  
+input D_RTY_I;                                  
+
+
+
+
+
+  
+    
+     
+
+
+   
+   
+  
+                   
+     
+                           
+    
+                          
+    
+                 
+     
+                               
+    
+ 
+                               
+    
+
+
+
+
+  
+
+output [ 7:0] jtag_reg_d;
+wire   [ 7:0] jtag_reg_d;
+output [2:0] jtag_reg_addr_d;
+wire   [2:0] jtag_reg_addr_d;
+ 
+
+
+  
+                               
+   
+       
+     
+           
+    
+           
+    
+
+
+
+  
+
+output [ (32-1):0] I_DAT_O;                
+wire   [ (32-1):0] I_DAT_O;
+output [ (32-1):0] I_ADR_O;                
+wire   [ (32-1):0] I_ADR_O;
+output I_CYC_O;                                 
+wire   I_CYC_O;
+output [ (4-1):0] I_SEL_O;         
+wire   [ (4-1):0] I_SEL_O;
+output I_STB_O;                                 
+wire   I_STB_O;
+output I_WE_O;                                  
+wire   I_WE_O;
+output [ (3-1):0] I_CTI_O;               
+wire   [ (3-1):0] I_CTI_O;
+output I_LOCK_O;                                
+wire   I_LOCK_O;
+output [ (2-1):0] I_BTE_O;               
+wire   [ (2-1):0] I_BTE_O;
+ 
+
+
+output [ (32-1):0] D_DAT_O;                
+wire   [ (32-1):0] D_DAT_O;
+output [ (32-1):0] D_ADR_O;                
+wire   [ (32-1):0] D_ADR_O;
+output D_CYC_O;                                 
+wire   D_CYC_O;
+output [ (4-1):0] D_SEL_O;         
+wire   [ (4-1):0] D_SEL_O;
+output D_STB_O;                                 
+wire   D_STB_O;
+output D_WE_O;                                  
+wire   D_WE_O;
+output [ (3-1):0] D_CTI_O;               
+wire   [ (3-1):0] D_CTI_O;
+output D_LOCK_O;                                
+wire   D_LOCK_O;
+output [ (2-1):0] D_BTE_O;               
+wire   [ (2-1):0] D_BTE_O;
+
+  
+      
+     
+       
+      
+             
+
+
+   
+
+
+
+
+
+
+  
+
+reg valid_a;                                    
+ 
+
+reg valid_f;                                    
+reg valid_d;                                    
+reg valid_x;                                    
+reg valid_m;                                    
+reg valid_w;                                    
+   
+wire q_x;
+wire [ (32-1):0] immediate_d;              
+wire load_d;                                    
+reg load_x;                                     
+reg load_m;
+wire load_q_x;
+wire store_q_x;
+wire q_m;
+wire load_q_m;
+wire store_q_m;
+wire store_d;                                   
+reg store_x;
+reg store_m;
+wire [ 1:0] size_d;                   
+reg [ 1:0] size_x;
+wire branch_d;                                  
+wire branch_predict_d;                          
+wire branch_predict_taken_d;                    
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d;   
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_d;
+wire bi_unconditional;
+wire bi_conditional;
+reg branch_x;                                   
+reg branch_predict_x;
+reg branch_predict_taken_x;
+reg branch_m;
+reg branch_predict_m;
+reg branch_predict_taken_m;
+wire branch_mispredict_taken_m;                 
+wire branch_flushX_m;                           
+wire branch_reg_d;                              
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset_d;            
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_x;             
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_m;
+wire [ 0:0] d_result_sel_0_d; 
+wire [ 1:0] d_result_sel_1_d; 
+
+wire x_result_sel_csr_d;                        
+reg x_result_sel_csr_x;
+  
+ 
+                    
+ 
+
+
+      
+                       
+ 
+
+
+  
+
+wire x_result_sel_sext_d;                       
+reg x_result_sel_sext_x;
+ 
+
+wire x_result_sel_logic_d;                      
+  
+                        
+ 
+
+
+wire x_result_sel_add_d;                        
+reg x_result_sel_add_x;
+wire m_result_sel_compare_d;                    
+reg m_result_sel_compare_x;
+reg m_result_sel_compare_m;
+  
+
+wire m_result_sel_shift_d;                      
+reg m_result_sel_shift_x;
+reg m_result_sel_shift_m;
+ 
+
+wire w_result_sel_load_d;                       
+reg w_result_sel_load_x;
+reg w_result_sel_load_m;
+reg w_result_sel_load_w;
+  
+
+wire w_result_sel_mul_d;                        
+reg w_result_sel_mul_x;
+reg w_result_sel_mul_m;
+reg w_result_sel_mul_w;
+ 
+
+wire x_bypass_enable_d;                         
+reg x_bypass_enable_x;                          
+wire m_bypass_enable_d;                         
+reg m_bypass_enable_x;                          
+reg m_bypass_enable_m;
+wire sign_extend_d;                             
+reg sign_extend_x;
+wire write_enable_d;                            
+reg write_enable_x;
+wire write_enable_q_x;
+reg write_enable_m;
+wire write_enable_q_m;
+reg write_enable_w;
+wire write_enable_q_w;
+wire read_enable_0_d;                           
+wire [ (5-1):0] read_idx_0_d;          
+wire read_enable_1_d;                           
+wire [ (5-1):0] read_idx_1_d;          
+wire [ (5-1):0] write_idx_d;           
+reg [ (5-1):0] write_idx_x;            
+reg [ (5-1):0] write_idx_m;
+reg [ (5-1):0] write_idx_w;
+wire [ (5-1):0] csr_d;                     
+reg  [ (5-1):0] csr_x;                  
+wire [ (3-1):0] condition_d;         
+reg [ (3-1):0] condition_x;          
+  
+
+wire break_d;                                   
+reg break_x;                                    
+ 
+
+wire scall_d;                                   
+reg scall_x;    
+wire eret_d;                                    
+reg eret_x;
+wire eret_q_x;
+  
+ 
+ 
+
+
+  
+
+wire bret_d;                                    
+reg bret_x;
+wire bret_q_x;
+  
+ 
+ 
+
+
+ 
+
+wire csr_write_enable_d;                        
+reg csr_write_enable_x;
+wire csr_write_enable_q_x;
+  
+       
+
+
+
+  
+                                
+ 
+ 
+  
+
+
+
+reg [ (32-1):0] d_result_0;                
+reg [ (32-1):0] d_result_1;                
+reg [ (32-1):0] x_result;                  
+reg [ (32-1):0] m_result;                  
+reg [ (32-1):0] w_result;                  
+
+reg [ (32-1):0] operand_0_x;               
+reg [ (32-1):0] operand_1_x;               
+reg [ (32-1):0] store_operand_x;           
+reg [ (32-1):0] operand_m;                 
+reg [ (32-1):0] operand_w;                 
+
+
+  
+
+reg [ (32-1):0] reg_data_live_0;          
+reg [ (32-1):0] reg_data_live_1;  
+reg use_buf;                                    
+reg [ (32-1):0] reg_data_buf_0;
+reg [ (32-1):0] reg_data_buf_1;
+ 
+
+  
+
+ 
+     
+
+
+wire [ (32-1):0] reg_data_0;               
+wire [ (32-1):0] reg_data_1;               
+reg [ (32-1):0] bypass_data_0;             
+reg [ (32-1):0] bypass_data_1;             
+wire reg_write_enable_q_w;
+
+reg interlock;                                  
+
+wire stall_a;                                   
+wire stall_f;                                   
+wire stall_d;                                   
+wire stall_x;                                   
+wire stall_m;                                   
+
+
+wire adder_op_d;                                
+reg adder_op_x;                                 
+reg adder_op_x_n;                               
+wire [ (32-1):0] adder_result_x;           
+wire adder_overflow_x;                          
+wire adder_carry_n_x;                           
+
+
+wire [ 3:0] logic_op_d;           
+reg [ 3:0] logic_op_x;            
+wire [ (32-1):0] logic_result_x;           
+
+  
+
+
+wire [ (32-1):0] sextb_result_x;           
+wire [ (32-1):0] sexth_result_x;           
+wire [ (32-1):0] sext_result_x;            
+ 
+
+
+
+  
+
+  
+                                   
+                                     
+
+
+wire direction_d;                               
+reg direction_x;                                        
+wire [ (32-1):0] shifter_result_m;         
+ 
+
+  
+                               
+ 
+                              
+ 
+
+
+  
+           
+
+
+
+
+  
+
+wire [ (32-1):0] multiplier_result_w;      
+ 
+
+  
+                                 
+ 
+
+
+
+
+  
+                                   
+ 
+ 
+ 
+                           
+
+
+
+
+  
+                         
+  
+
+
+
+
+  
+
+wire [ (32-1):0] interrupt_csr_read_data_x;
+ 
+
+wire [ (32-1):0] cfg;                      
+wire [ (32-1):0] cfg2;                     
+  
+                          
+
+
+reg [ (32-1):0] csr_read_data_x;           
+
+
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;                       
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;                       
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;                       
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;                       
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;                       
+  
+                          
+
+
+  
+
+wire [ (32-1):0] instruction_f;     
+ 
+
+
+
+wire [ (32-1):0] instruction_d;     
+  
+
+wire iflush;                                    
+wire icache_stall_request;                      
+wire icache_restart_request;                    
+wire icache_refill_request;                     
+wire icache_refilling;                          
+ 
+
+
+
+  
+                                   
+                                     
+                       
+                     
+                      
+                           
+
+
+wire [ (32-1):0] load_data_w;              
+wire stall_wb_load;                             
+
+
+  
+
+  
+
+wire [ (32-1):0] jtx_csr_read_data;        
+wire [ (32-1):0] jrx_csr_read_data;        
+ 
+
+  
+
+wire jtag_csr_write_enable;                     
+wire [ (32-1):0] jtag_csr_write_data;      
+wire [ (5-1):0] jtag_csr;                  
+wire jtag_read_enable;                          
+wire [ 7:0] jtag_read_data;
+wire jtag_write_enable;
+wire [ 7:0] jtag_write_data;
+wire [ (32-1):0] jtag_address;
+wire jtag_access_complete;
+ 
+
+  
+
+wire jtag_break;                                
+ 
+
+ 
+
+
+
+wire raw_x_0;                                   
+wire raw_x_1;                                   
+wire raw_m_0;                                   
+wire raw_m_1;                                   
+wire raw_w_0;                                   
+wire raw_w_1;                                   
+
+
+wire cmp_zero;                                  
+wire cmp_negative;                              
+wire cmp_overflow;                              
+wire cmp_carry_n;                               
+reg condition_met_x;                            
+reg condition_met_m;
+      
+                             
+
+
+wire branch_taken_m;                            
+
+wire kill_f;                                    
+wire kill_d;                                    
+wire kill_x;                                    
+wire kill_m;                                    
+wire kill_w;                                    
+
+reg [ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8] eba;                 
+  
+
+reg [ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8] deba;                
+ 
+
+reg [ (3-1):0] eid_x;                      
+  
+                        
+                        
+
+
+
+  
+
+  
+
+wire dc_ss;                                     
+ 
+
+wire dc_re;                                     
+wire bp_match;
+wire wp_match;
+wire exception_x;                               
+reg exception_m;                                
+wire debug_exception_x;                         
+reg debug_exception_m;
+reg debug_exception_w;
+wire debug_exception_q_w;
+wire non_debug_exception_x;                     
+reg non_debug_exception_m;
+reg non_debug_exception_w;
+wire non_debug_exception_q_w;
+ 
+                                
+ 
+ 
+ 
+
+
+
+  
+
+  
+ 
+wire reset_exception;                           
+ 
+
+  
+                            
+
+
+ 
+
+  
+
+wire interrupt_exception;                       
+ 
+
+  
+
+wire breakpoint_exception;                      
+wire watchpoint_exception;                      
+ 
+
+  
+     
+   
+            
+                   
+
+
+  
+                   
+
+
+wire system_call_exception;                     
+
+  
+                         
+
+
+
+   
+    
+
+
+     
+  
+                          
+   
+            
+   
+                          
+   
+
+    	      
+    	      
+    	      
+    	      
+    	      
+    	      
+   
+   
+
+
+   
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+lm32_instruction_unit_medium_debug #(
+    .eba_reset              (eba_reset),
+    .associativity          (icache_associativity),
+    .sets                   (icache_sets),
+    .bytes_per_line         (icache_bytes_per_line),
+    .base_address           (icache_base_address),
+    .limit                  (icache_limit)
+  ) instruction_unit (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    
+    .stall_a                (stall_a),
+    .stall_f                (stall_f),
+    .stall_d                (stall_d),
+    .stall_x                (stall_x),
+    .stall_m                (stall_m),
+    .valid_f                (valid_f),
+    .valid_d                (valid_d),
+    .kill_f                 (kill_f),
+    .branch_predict_taken_d (branch_predict_taken_d),
+    .branch_predict_address_d (branch_predict_address_d),
+      
+             
+            
+
+
+    .exception_m            (exception_m),
+    .branch_taken_m         (branch_taken_m),
+    .branch_mispredict_taken_m (branch_mispredict_taken_m),
+    .branch_target_m        (branch_target_m),
+  
+
+    .iflush                 (iflush),
+ 
+
+  
+     
+      
+           
+
+        
+  
+
+    
+    .i_dat_i                (I_DAT_I),
+    .i_ack_i                (I_ACK_I),
+    .i_err_i                (I_ERR_I),
+    .i_rty_i                (I_RTY_I),
+ 
+
+  
+
+    .jtag_read_enable       (jtag_read_enable),
+    .jtag_write_enable      (jtag_write_enable),
+    .jtag_write_data        (jtag_write_data),
+    .jtag_address           (jtag_address),
+ 
+
+    
+    
+    .pc_f                   (pc_f),
+    .pc_d                   (pc_d),
+    .pc_x                   (pc_x),
+    .pc_m                   (pc_m),
+    .pc_w                   (pc_w),
+  
+
+    .icache_stall_request   (icache_stall_request),
+    .icache_restart_request (icache_restart_request),
+    .icache_refill_request  (icache_refill_request),
+    .icache_refilling       (icache_refilling),
+ 
+
+  
+
+    
+    .i_dat_o                (I_DAT_O),
+    .i_adr_o                (I_ADR_O),
+    .i_cyc_o                (I_CYC_O),
+    .i_sel_o                (I_SEL_O),
+    .i_stb_o                (I_STB_O),
+    .i_we_o                 (I_WE_O),
+    .i_cti_o                (I_CTI_O),
+    .i_lock_o               (I_LOCK_O),
+    .i_bte_o                (I_BTE_O),
+ 
+ 
+
+  
+    
+    
+    
+
+
+		      	      
+  
+
+    .jtag_read_data         (jtag_read_data),
+    .jtag_access_complete   (jtag_access_complete),
+ 
+
+  
+                
+
+
+  
+
+    .instruction_f          (instruction_f),
+ 
+
+
+		      
+    .instruction_d          (instruction_d)
+
+
+		      
+    );
+
+
+lm32_decoder_medium_debug decoder (
+    
+    .instruction            (instruction_d),
+    
+    .d_result_sel_0         (d_result_sel_0_d),
+    .d_result_sel_1         (d_result_sel_1_d),
+    .x_result_sel_csr       (x_result_sel_csr_d),
+  
+      
+
+
+      
+         
+
+
+  
+
+    .x_result_sel_sext      (x_result_sel_sext_d),
+ 
+    
+    .x_result_sel_logic     (x_result_sel_logic_d),
+  
+          
+
+
+    .x_result_sel_add       (x_result_sel_add_d),
+    .m_result_sel_compare   (m_result_sel_compare_d),
+  
+
+    .m_result_sel_shift     (m_result_sel_shift_d),  
+ 
+    
+    .w_result_sel_load      (w_result_sel_load_d),
+  
+
+    .w_result_sel_mul       (w_result_sel_mul_d),
+ 
+
+    .x_bypass_enable        (x_bypass_enable_d),
+    .m_bypass_enable        (m_bypass_enable_d),
+    .read_enable_0          (read_enable_0_d),
+    .read_idx_0             (read_idx_0_d),
+    .read_enable_1          (read_enable_1_d),
+    .read_idx_1             (read_idx_1_d),
+    .write_enable           (write_enable_d),
+    .write_idx              (write_idx_d),
+    .immediate              (immediate_d),
+    .branch_offset          (branch_offset_d),
+    .load                   (load_d),
+    .store                  (store_d),
+    .size                   (size_d),
+    .sign_extend            (sign_extend_d),
+    .adder_op               (adder_op_d),
+    .logic_op               (logic_op_d),
+  
+
+    .direction              (direction_d),
+ 
+
+  
+                 
+                
+
+
+  
+                   
+
+
+  
+                     
+                    
+
+
+    .branch                 (branch_d),
+    .bi_unconditional       (bi_unconditional),
+    .bi_conditional         (bi_conditional),
+    .branch_reg             (branch_reg_d),
+    .condition              (condition_d),
+  
+
+    .break_opcode           (break_d),
+ 
+
+    .scall                  (scall_d),
+    .eret                   (eret_d),
+  
+
+    .bret                   (bret_d),
+ 
+
+  
+                
+
+
+    .csr_write_enable       (csr_write_enable_d)
+    ); 
+
+
+lm32_load_store_unit_medium_debug #(
+    .associativity          (dcache_associativity),
+    .sets                   (dcache_sets),
+    .bytes_per_line         (dcache_bytes_per_line),
+    .base_address           (dcache_base_address),
+    .limit                  (dcache_limit)
+  ) load_store_unit (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    
+    .stall_a                (stall_a),
+    .stall_x                (stall_x),
+    .stall_m                (stall_m),
+    .kill_x                 (kill_x),
+    .kill_m                 (kill_m),
+    .exception_m            (exception_m),
+    .store_operand_x        (store_operand_x),
+    .load_store_address_x   (adder_result_x),
+    .load_store_address_m   (operand_m),
+    .load_store_address_w   (operand_w[1:0]),
+    .load_x                 (load_x),
+    .store_x                (store_x),
+    .load_q_x               (load_q_x),
+    .store_q_x              (store_q_x),
+    .load_q_m               (load_q_m),
+    .store_q_m              (store_q_m),
+    .sign_extend_x          (sign_extend_x),
+    .size_x                 (size_x),
+  
+                     
+
+
+
+  
+    
+    
+    
+    
+    
+    
+    
+
+
+		     
+    
+    .d_dat_i                (D_DAT_I),
+    .d_ack_i                (D_ACK_I),
+    .d_err_i                (D_ERR_I),
+    .d_rty_i                (D_RTY_I),
+    
+    
+  
+      
+     
+       
+           
+
+    
+    .load_data_w            (load_data_w),
+    .stall_wb_load          (stall_wb_load),
+    
+    .d_dat_o                (D_DAT_O),
+    .d_adr_o                (D_ADR_O),
+    .d_cyc_o                (D_CYC_O),
+    .d_sel_o                (D_SEL_O),
+    .d_stb_o                (D_STB_O),
+    .d_we_o                 (D_WE_O),
+    .d_cti_o                (D_CTI_O),
+    .d_lock_o               (D_LOCK_O),
+    .d_bte_o                (D_BTE_O)
+    );      
+       
+
+lm32_adder adder (
+    
+    .adder_op_x             (adder_op_x),
+    .adder_op_x_n           (adder_op_x_n),
+    .operand_0_x            (operand_0_x),
+    .operand_1_x            (operand_1_x),
+    
+    .adder_result_x         (adder_result_x),
+    .adder_carry_n_x        (adder_carry_n_x),
+    .adder_overflow_x       (adder_overflow_x)
+    );
+
+
+lm32_logic_op logic_op (
+    
+    .logic_op_x             (logic_op_x),
+    .operand_0_x            (operand_0_x),
+
+    .operand_1_x            (operand_1_x),
+    
+    .logic_result_x         (logic_result_x)
+    );
+              
+  
+
+
+lm32_shifter shifter (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    .stall_x                (stall_x),
+    .direction_x            (direction_x),
+    .sign_extend_x          (sign_extend_x),
+    .operand_0_x            (operand_0_x),
+    .operand_1_x            (operand_1_x),
+    
+    .shifter_result_m       (shifter_result_m)
+    );
+ 
+
+
+  
+
+
+lm32_multiplier multiplier (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    .stall_x                (stall_x),
+    .stall_m                (stall_m),
+    .operand_0              (d_result_0),
+    .operand_1              (d_result_1),
+    
+    .result                 (multiplier_result_w)    
+    );
+ 
+
+
+  
+
+  
+    
+                      
+                      
+                    
+                     
+                   
+                   
+                  
+
+         
+                 
+
+ 
+               
+              
+              
+    
+                
+                
+    
+                   
+                   
+           
+
+            
+    
+
+
+              
+  
+
+
+lm32_interrupt_medium_debug interrupt_unit (
+    
+    .clk_i                  (clk_i), 
+    .rst_i                  (rst_i),
+    
+    .interrupt              (interrupt),
+    
+    .stall_x                (stall_x),
+  
+
+    .non_debug_exception    (non_debug_exception_q_w), 
+    .debug_exception        (debug_exception_q_w),
+ 
+                   
+
+
+    .eret_q_x               (eret_q_x),
+  
+
+    .bret_q_x               (bret_q_x),
+ 
+
+    .csr                    (csr_x),
+    .csr_write_data         (operand_1_x),
+    .csr_write_enable       (csr_write_enable_q_x),
+    
+    .interrupt_exception    (interrupt_exception),
+    
+    .csr_read_data          (interrupt_csr_read_data_x)
+    );
+ 
+
+
+  
+      
+      
+        
+   
+
+
+
+
+  
+
+
+lm32_jtag_medium_debug jtag (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    
+    .jtag_clk               (jtag_clk),
+    .jtag_update            (jtag_update),
+    .jtag_reg_q             (jtag_reg_q),
+    .jtag_reg_addr_q        (jtag_reg_addr_q),
+    
+  
+
+    .csr                    (csr_x),
+    .csr_write_data         (operand_1_x),
+    .csr_write_enable       (csr_write_enable_q_x),
+    .stall_x                (stall_x),
+ 
+
+  
+
+    .jtag_read_data         (jtag_read_data),
+    .jtag_access_complete   (jtag_access_complete),
+ 
+
+  
+
+    .exception_q_w          (debug_exception_q_w || non_debug_exception_q_w),
+ 
+    
+    
+    
+  
+
+    .jtx_csr_read_data      (jtx_csr_read_data),
+    .jrx_csr_read_data      (jrx_csr_read_data),
+ 
+
+  
+
+    .jtag_csr_write_enable  (jtag_csr_write_enable),
+    .jtag_csr_write_data    (jtag_csr_write_data),
+    .jtag_csr               (jtag_csr),
+    .jtag_read_enable       (jtag_read_enable),
+    .jtag_write_enable      (jtag_write_enable),
+    .jtag_write_data        (jtag_write_data),
+    .jtag_address           (jtag_address),
+ 
+
+  
+
+    .jtag_break             (jtag_break),
+    .jtag_reset             (reset_exception),
+ 
+
+    
+    .jtag_reg_d             (jtag_reg_d),
+    .jtag_reg_addr_d        (jtag_reg_addr_d)
+    );
+ 
+
+
+  
+
+
+lm32_debug_medium_debug #(
+    .breakpoints            (breakpoints),
+    .watchpoints            (watchpoints)
+  ) hw_debug (
+    
+    .clk_i                  (clk_i), 
+    .rst_i                  (rst_i),
+    .pc_x                   (pc_x),
+    .load_x                 (load_x),
+    .store_x                (store_x),
+    .load_store_address_x   (adder_result_x),
+    .csr_write_enable_x     (csr_write_enable_q_x),
+    .csr_write_data         (operand_1_x),
+    .csr_x                  (csr_x),
+   
+
+	        
+
+    .jtag_csr_write_enable  (jtag_csr_write_enable),
+    .jtag_csr_write_data    (jtag_csr_write_data),
+    .jtag_csr               (jtag_csr),
+	       
+
+	        
+      
+        
+                   
+	      
+
+ 
+
+  
+
+    .eret_q_x               (eret_q_x),
+    .bret_q_x               (bret_q_x),
+    .stall_x                (stall_x),
+    .exception_x            (exception_x),
+    .q_x                    (q_x),
+  
+      
+
+
+ 
+
+    
+  
+
+    .dc_ss                  (dc_ss),
+ 
+
+    .dc_re                  (dc_re),
+    .bp_match               (bp_match),
+    .wp_match               (wp_match)
+    );
+ 
+
+
+
+
+  
+
+   
+           
+            
+          
+            
+
+
+             
+              
+    
+
+   wire [31:0] regfile_data_0, regfile_data_1;
+   reg [31:0]  w_result_d;
+   reg 	       regfile_raw_0, regfile_raw_0_nxt;
+   reg 	       regfile_raw_1, regfile_raw_1_nxt;
+   
+   
+             
+          
+
+   always @(reg_write_enable_q_w or write_idx_w or instruction_f)
+     begin
+	if (reg_write_enable_q_w
+	    && (write_idx_w == instruction_f[25:21]))
+	  regfile_raw_0_nxt = 1'b1;
+	else
+	  regfile_raw_0_nxt = 1'b0;
+	
+	if (reg_write_enable_q_w
+	    && (write_idx_w == instruction_f[20:16]))
+	  regfile_raw_1_nxt = 1'b1;
+	else
+	  regfile_raw_1_nxt = 1'b0;
+     end
+   
+   
+           
+           
+       
+
+   always @(regfile_raw_0 or w_result_d or regfile_data_0)
+     if (regfile_raw_0)
+       reg_data_live_0 = w_result_d;
+     else
+       reg_data_live_0 = regfile_data_0;
+   
+   
+           
+           
+       
+
+   always @(regfile_raw_1 or w_result_d or regfile_data_1)
+     if (regfile_raw_1)
+       reg_data_live_1 = w_result_d;
+     else
+       reg_data_live_1 = regfile_data_1;
+   
+   
+     
+
+   always @(posedge clk_i  )
+     if (rst_i ==  1'b1)
+       begin
+	  regfile_raw_0 <= 1'b0;
+	  regfile_raw_1 <= 1'b0;
+	  w_result_d <= 32'b0;
+       end
+     else
+       begin
+	  regfile_raw_0 <= regfile_raw_0_nxt;
+	  regfile_raw_1 <= regfile_raw_1_nxt;
+	  w_result_d <= w_result;
+       end
+   
+   
+      
+
+   
+   lm32_dp_ram
+     #(
+       
+       .addr_depth(1<<5),
+       .addr_width(5),
+       .data_width(32)
+       )
+   reg_0
+     (
+      
+      .clk_i	(clk_i),
+      .rst_i	(rst_i), 
+      .we_i	(reg_write_enable_q_w),
+      .wdata_i	(w_result),
+      .waddr_i	(write_idx_w),
+      .raddr_i	(instruction_f[25:21]),
+      
+      .rdata_o	(regfile_data_0)
+      );
+
+   lm32_dp_ram
+     #(
+       .addr_depth(1<<5),
+       .addr_width(5),
+       .data_width(32)
+       )
+   reg_1
+     (
+      
+      .clk_i	(clk_i),
+      .rst_i	(rst_i), 
+      .we_i	(reg_write_enable_q_w),
+      .wdata_i	(w_result),
+      .waddr_i	(write_idx_w),
+      .raddr_i	(instruction_f[20:16]),
+      
+      .rdata_o	(regfile_data_1)
+      );
+ 
+
+
+  
+   
+     
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+   
+     
+      
+      
+      
+      
+      
+      
+      
+        
+      
+       
+      
+      
+      
+   
+   
+     
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+   
+     
+      
+      
+      
+      
+      
+      
+      
+        
+      
+       
+      
+      
+      
+
+
+
+
+
+
+
+
+  
+
+
+assign reg_data_0 = use_buf ? reg_data_buf_0 : reg_data_live_0;
+assign reg_data_1 = use_buf ? reg_data_buf_1 : reg_data_live_1;
+ 
+
+  
+
+ 
+
+   
+   
+
+
+
+
+assign raw_x_0 = (write_idx_x == read_idx_0_d) && (write_enable_q_x ==  1'b1);
+assign raw_m_0 = (write_idx_m == read_idx_0_d) && (write_enable_q_m ==  1'b1);
+assign raw_w_0 = (write_idx_w == read_idx_0_d) && (write_enable_q_w ==  1'b1);
+assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x ==  1'b1);
+assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m ==  1'b1);
+assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w ==  1'b1);
+
+
+always @(*)
+begin
+    if (   (   (x_bypass_enable_x ==  1'b0)
+            && (   ((read_enable_0_d ==  1'b1) && (raw_x_0 ==  1'b1))
+                || ((read_enable_1_d ==  1'b1) && (raw_x_1 ==  1'b1))
+               )
+           )
+        || (   (m_bypass_enable_m ==  1'b0)
+            && (   ((read_enable_0_d ==  1'b1) && (raw_m_0 ==  1'b1))
+                || ((read_enable_1_d ==  1'b1) && (raw_m_1 ==  1'b1))
+               )
+           )
+       )
+        interlock =  1'b1;
+    else
+        interlock =  1'b0;
+end
+
+
+always @(*)
+begin
+    if (raw_x_0 ==  1'b1)        
+        bypass_data_0 = x_result;
+    else if (raw_m_0 ==  1'b1)
+        bypass_data_0 = m_result;
+    else if (raw_w_0 ==  1'b1)
+        bypass_data_0 = w_result;
+    else
+        bypass_data_0 = reg_data_0;
+end
+
+
+always @(*)
+begin
+    if (raw_x_1 ==  1'b1)
+        bypass_data_1 = x_result;
+    else if (raw_m_1 ==  1'b1)
+        bypass_data_1 = m_result;
+    else if (raw_w_1 ==  1'b1)
+        bypass_data_1 = w_result;
+    else
+        bypass_data_1 = reg_data_1;
+end
+
+   
+          
+       
+       
+     
+
+   assign branch_predict_d = bi_unconditional | bi_conditional;
+   assign branch_predict_taken_d = bi_unconditional ? 1'b1 : (bi_conditional ? instruction_d[15] : 1'b0);
+   
+   
+   assign branch_target_d = pc_d + branch_offset_d;
+
+   
+   
+   
+   assign branch_predict_address_d = branch_predict_taken_d ? branch_target_d : pc_f;
+
+
+always @(*)
+begin
+    d_result_0 = d_result_sel_0_d[0] ? {pc_f, 2'b00} : bypass_data_0; 
+    case (d_result_sel_1_d)
+     2'b00:      d_result_1 = { 32{1'b0}};
+     2'b01:     d_result_1 = bypass_data_1;
+     2'b10: d_result_1 = immediate_d;
+    default:                        d_result_1 = { 32{1'bx}};
+    endcase
+end
+
+      
+
+   
+   
+
+
+
+  
+
+
+assign sextb_result_x = {{24{operand_0_x[7]}}, operand_0_x[7:0]};
+assign sexth_result_x = {{16{operand_0_x[15]}}, operand_0_x[15:0]};
+assign sext_result_x = size_x ==  2'b00 ? sextb_result_x : sexth_result_x;
+ 
+
+
+  
+
+      
+
+
+
+
+assign cmp_zero = operand_0_x == operand_1_x;
+assign cmp_negative = adder_result_x[ 32-1];
+assign cmp_overflow = adder_overflow_x;
+assign cmp_carry_n = adder_carry_n_x;
+always @(*)
+begin
+    case (condition_x)
+     3'b000:   condition_met_x =  1'b1;
+     3'b110:   condition_met_x =  1'b1;
+     3'b001:    condition_met_x = cmp_zero;
+     3'b111:   condition_met_x = !cmp_zero;
+     3'b010:    condition_met_x = !cmp_zero && (cmp_negative == cmp_overflow);
+     3'b101:   condition_met_x = cmp_carry_n && !cmp_zero;
+     3'b011:   condition_met_x = cmp_negative == cmp_overflow;
+     3'b100:  condition_met_x = cmp_carry_n;
+    default:              condition_met_x = 1'bx;
+    endcase 
+end
+
+
+always @(*)
+begin
+    x_result =   x_result_sel_add_x ? adder_result_x 
+               : x_result_sel_csr_x ? csr_read_data_x
+  
+
+               : x_result_sel_sext_x ? sext_result_x
+ 
+
+  
+                  
+
+
+  
+                  
+
+
+  
+                  
+
+
+               : logic_result_x;
+end
+
+
+always @(*)
+begin
+    m_result =   m_result_sel_compare_m ? {{ 32-1{1'b0}}, condition_met_m}
+  
+
+               : m_result_sel_shift_m ? shifter_result_m
+ 
+
+               : operand_m; 
+end
+
+
+always @(*)
+begin
+    w_result =    w_result_sel_load_w ? load_data_w
+  
+
+                : w_result_sel_mul_w ? multiplier_result_w
+ 
+
+                : operand_w;
+end
+
+      
+
+          
+                                
+                                     
+                                 
+                                 
+                              
+
+
+
+
+assign branch_taken_m =      (stall_m ==  1'b0) 
+                          && (   (   (branch_m ==  1'b1) 
+                                  && (valid_m ==  1'b1)
+                                  && (   (   (condition_met_m ==  1'b1)
+					  && (branch_predict_taken_m ==  1'b0)
+					 )
+				      || (   (condition_met_m ==  1'b0)
+					  && (branch_predict_m ==  1'b1)
+					  && (branch_predict_taken_m ==  1'b1)
+					 )
+				     )
+                                 ) 
+                              || (exception_m ==  1'b1)
+                             );
+
+
+assign branch_mispredict_taken_m =    (condition_met_m ==  1'b0)
+                                   && (branch_predict_m ==  1'b1)
+	   			   && (branch_predict_taken_m ==  1'b1);
+   
+
+assign branch_flushX_m =    (stall_m ==  1'b0)
+                         && (   (   (branch_m ==  1'b1) 
+                                 && (valid_m ==  1'b1)
+			         && (   (condition_met_m ==  1'b1)
+				     || (   (condition_met_m ==  1'b0)
+					 && (branch_predict_m ==  1'b1)
+					 && (branch_predict_taken_m ==  1'b1)
+					)
+				    )
+			        )
+			     || (exception_m ==  1'b1)
+			    );
+
+
+assign kill_f =    (   (valid_d ==  1'b1)
+                    && (branch_predict_taken_d ==  1'b1)
+		   )
+                || (branch_taken_m ==  1'b1) 
+      
+                   
+
+
+  
+
+                || (icache_refill_request ==  1'b1) 
+ 
+
+                  
+                   
+
+
+                ;
+assign kill_d =    (branch_taken_m ==  1'b1) 
+      
+                   
+
+
+  
+
+                || (icache_refill_request ==  1'b1)     
+ 
+                
+                  
+                   
+
+
+                ;
+assign kill_x =    (branch_flushX_m ==  1'b1) 
+                  
+                   
+
+
+                ;
+assign kill_m =     1'b0
+                  
+                   
+
+
+                ;                
+assign kill_w =     1'b0
+                  
+                   
+
+                
+                ;
+
+
+
+  
+
+assign breakpoint_exception =    (   (   (break_x ==  1'b1)
+				      || (bp_match ==  1'b1)
+				     )
+				  && (valid_x ==  1'b1)
+				 )
+  
+
+                              || (jtag_break ==  1'b1)
+ 
+
+                              ;
+ 
+
+
+  
+
+assign watchpoint_exception = wp_match ==  1'b1;
+ 
+
+
+  
+        
+                                             
+                                         
+     
+
+
+
+  
+     
+
+
+
+assign system_call_exception = (   (scall_x ==  1'b1)
+  
+                                   
+
+
+			       );
+
+  
+
+assign debug_exception_x =  (breakpoint_exception ==  1'b1)
+                         || (watchpoint_exception ==  1'b1)
+                         ;
+
+assign non_debug_exception_x = (system_call_exception ==  1'b1)
+  
+
+                            || (reset_exception ==  1'b1)
+ 
+
+  
+                               
+                               
+
+
+  
+                               
+
+
+  
+
+                            || (   (interrupt_exception ==  1'b1)
+  
+
+                                && (dc_ss ==  1'b0)
+ 
+                            
+  
+ 				   
+				   
+
+
+                               )
+ 
+
+                            ;
+
+assign exception_x = (debug_exception_x ==  1'b1) || (non_debug_exception_x ==  1'b1);
+ 
+               
+ 
+                               
+                               
+
+ 
+                               
+
+ 
+                                  
+ 
+                                   
+                            
+ 
+ 				   
+				   
+
+                               
+
+                            
+
+
+
+  
+ 
+
+ 
+  
+      
+   
+      
+
+
+
+
+always @(*)
+begin
+  
+
+  
+
+    if (reset_exception ==  1'b1)
+        eid_x =  3'h0;
+    else
+ 
+     
+  
+            
+          
+    
+
+
+         if (breakpoint_exception ==  1'b1)
+        eid_x =  3'd1;
+    else
+ 
+
+  
+            
+          
+    
+            
+          
+    
+
+
+  
+
+         if (watchpoint_exception ==  1'b1)
+        eid_x =  3'd3;
+    else 
+ 
+
+  
+            
+          
+    
+
+
+  
+
+         if (   (interrupt_exception ==  1'b1)
+  
+
+             && (dc_ss ==  1'b0)
+ 
+                            
+            )
+        eid_x =  3'h6;
+    else
+ 
+
+        eid_x =  3'h7;
+end
+
+
+
+assign stall_a = (stall_f ==  1'b1);
+                
+assign stall_f = (stall_d ==  1'b1);
+                
+assign stall_d =   (stall_x ==  1'b1) 
+                || (   (interlock ==  1'b1)
+                    && (kill_d ==  1'b0)
+                   ) 
+		|| (   (   (eret_d ==  1'b1)
+			|| (scall_d ==  1'b1)
+  
+			   
+
+
+		       )
+		    && (   (load_q_x ==  1'b1)
+			|| (load_q_m ==  1'b1)
+			|| (store_q_x ==  1'b1)
+			|| (store_q_m ==  1'b1)
+			|| (D_CYC_O ==  1'b1)
+		       )
+                    && (kill_d ==  1'b0)
+		   )
+  
+
+		|| (   (   (break_d ==  1'b1)
+			|| (bret_d ==  1'b1)
+		       )
+		    && (   (load_q_x ==  1'b1)
+			|| (store_q_x ==  1'b1)
+			|| (load_q_m ==  1'b1)
+			|| (store_q_m ==  1'b1)
+			|| (D_CYC_O ==  1'b1)
+		       )
+                    && (kill_d ==  1'b0)
+		   )
+ 
+                   
+                || (   (csr_write_enable_d ==  1'b1)
+                    && (load_q_x ==  1'b1)
+                   )                      
+  
+                 
+                 
+                       
+		           
+			 
+			
+		    
+
+	
+                ;
+                
+assign stall_x =    (stall_m ==  1'b1)
+  
+                       
+                        
+                     
+
+
+
+	    
+                 ;
+
+assign stall_m =    (stall_wb_load ==  1'b1)
+  
+                    
+
+
+                 || (   (D_CYC_O ==  1'b1)
+                     && (   (store_m ==  1'b1)
+		         
+          
+          
+
+		  
+	 
+	
+
+          
+           
+          
+       
+
+  
+
+		         || ((store_x ==  1'b1) && (interrupt_exception ==  1'b1))
+ 
+
+                         || (load_m ==  1'b1)
+                         || (load_x ==  1'b1)
+                        ) 
+                    ) 
+ 
+                 
+  
+                         
+
+                                    
+  
+
+                 || (icache_stall_request ==  1'b1)     
+                 || ((I_CYC_O ==  1'b1) && ((branch_m ==  1'b1) || (exception_m ==  1'b1))) 
+ 
+ 
+                                
+
+
+                               
+  
+                                  
+                        
+                    
+
+
+  
+                  
+   
+
+                 ;      
+
+
+
+
+  
+         
+
+
+  
+         
+         
+
+
+  
+         
+
+
+  
+         
+         
+
+
+assign q_x = (valid_x ==  1'b1) && (kill_x ==  1'b0);
+assign csr_write_enable_q_x = (csr_write_enable_x ==  1'b1) && (q_x ==  1'b1);
+assign eret_q_x = (eret_x ==  1'b1) && (q_x ==  1'b1);
+  
+
+assign bret_q_x = (bret_x ==  1'b1) && (q_x ==  1'b1);
+ 
+
+assign load_q_x = (load_x ==  1'b1) 
+               && (q_x ==  1'b1)
+  
+
+               && (bp_match ==  1'b0)
+ 
+
+                  ;
+assign store_q_x = (store_x ==  1'b1) 
+               && (q_x ==  1'b1)
+  
+
+               && (bp_match ==  1'b0)
+ 
+
+                  ;
+  
+         
+
+                              
+assign q_m = (valid_m ==  1'b1) && (kill_m ==  1'b0) && (exception_m ==  1'b0);
+assign load_q_m = (load_m ==  1'b1) && (q_m ==  1'b1);
+assign store_q_m = (store_m ==  1'b1) && (q_m ==  1'b1);
+  
+
+assign debug_exception_q_w = ((debug_exception_w ==  1'b1) && (valid_w ==  1'b1));
+assign non_debug_exception_q_w = ((non_debug_exception_w ==  1'b1) && (valid_w ==  1'b1));        
+ 
+                 
+
+
+
+assign write_enable_q_x = (write_enable_x ==  1'b1) && (valid_x ==  1'b1) && (branch_flushX_m ==  1'b0);
+assign write_enable_q_m = (write_enable_m ==  1'b1) && (valid_m ==  1'b1);
+assign write_enable_q_w = (write_enable_w ==  1'b1) && (valid_w ==  1'b1);
+
+assign reg_write_enable_q_w = (write_enable_w ==  1'b1) && (kill_w ==  1'b0) && (valid_w ==  1'b1);
+
+
+assign cfg = {
+               6'h02,
+              watchpoints[3:0],
+              breakpoints[3:0],
+              interrupts[5:0],
+  
+
+               1'b1,
+ 
+              
+
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+ 
+               1'b1
+ 
+              
+
+
+              };
+
+assign cfg2 = {
+		     30'b0,
+  
+		     
+
+
+		      1'b0,
+ 
+
+  
+		     
+
+
+		      1'b0
+ 
+
+		     };
+   
+
+  
+
+assign iflush = (   (csr_write_enable_d ==  1'b1) 
+                 && (csr_d ==  5'h3)
+                 && (stall_d ==  1'b0)
+                 && (kill_d ==  1'b0)
+                 && (valid_d ==  1'b1))
+
+  
+
+             ||
+                (   (jtag_csr_write_enable ==  1'b1)
+		 && (jtag_csr ==  5'h3))
+ 
+
+		 ;
+ 
+ 
+  
+         
+                      
+
+ 
+               
+                       
+		      
+
+		   
+
+ 
+
+
+assign csr_d = read_idx_0_d[ (5-1):0];
+
+
+always @(*)
+begin
+    case (csr_x)
+  
+
+     5'h0,
+     5'h1,
+     5'h2:   csr_read_data_x = interrupt_csr_read_data_x;  
+ 
+
+  
+         
+
+
+     5'h6:  csr_read_data_x = cfg;
+     5'h7:  csr_read_data_x = {eba, 8'h00};
+  
+
+     5'h9: csr_read_data_x = {deba, 8'h00};
+ 
+
+  
+
+     5'he:  csr_read_data_x = jtx_csr_read_data;  
+     5'hf:  csr_read_data_x = jrx_csr_read_data;
+ 
+
+     5'ha: csr_read_data_x = cfg2;
+     5'hb:  csr_read_data_x = sdb_address;
+  
+        
+
+
+      
+      
+    default:        csr_read_data_x = { 32{1'bx}};
+    endcase
+end
+
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        eba <= eba_reset[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+    else
+    begin
+        if ((csr_write_enable_q_x ==  1'b1) && (csr_x ==  5'h7) && (stall_x ==  1'b0))
+            eba <= operand_1_x[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+  
+
+   
+
+       if ((jtag_csr_write_enable ==  1'b1) && (jtag_csr ==  5'h7))
+         eba <= jtag_csr_write_data[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+  
+
+   
+              
+           
+ 
+	 
+ 
+
+    end
+end
+
+  
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        deba <= deba_reset[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+    else
+    begin
+        if ((csr_write_enable_q_x ==  1'b1) && (csr_x ==  5'h9) && (stall_x ==  1'b0))
+            deba <= operand_1_x[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+   
+
+    
+
+       if ((jtag_csr_write_enable ==  1'b1) && (jtag_csr ==  5'h9))
+         deba <= jtag_csr_write_data[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+   
+
+    
+              
+           
+  
+       
+  
+
+    end
+end
+ 
+
+
+
+  
+   
+
+       
+          
+    
+            
+
+
+
+
+  
+
+   
+
+       
+          
+    
+    
+        
+                
+             
+	     
+	
+        
+               
+              
+    
+
+
+
+ 
+
+
+  
+
+  
+ 
+
+           
+           
+       
+          
+            
+                 
+             
+          
+     
+            
+ 
+
+
+always @(*)
+begin
+    if (icache_refill_request ==  1'b1) 
+        valid_a =  1'b0;
+    else if (icache_restart_request ==  1'b1) 
+        valid_a =  1'b1;
+    else 
+        valid_a = !icache_refilling;
+end 
+ 
+
+ 
+ 
+ 
+
+        
+          
+         
+          
+     
+          
+ 
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        valid_f <=  1'b0;
+        valid_d <=  1'b0;
+        valid_x <=  1'b0;
+        valid_m <=  1'b0;
+        valid_w <=  1'b0;
+    end
+    else
+    begin    
+        if ((kill_f ==  1'b1) || (stall_a ==  1'b0))
+  
+
+            valid_f <= valid_a;    
+ 
+              
+
+            
+        else if (stall_f ==  1'b0)
+            valid_f <=  1'b0;            
+
+        if (kill_d ==  1'b1)
+            valid_d <=  1'b0;
+        else if (stall_f ==  1'b0)
+            valid_d <= valid_f & !kill_f;
+        else if (stall_d ==  1'b0)
+            valid_d <=  1'b0;
+       
+        if (stall_d ==  1'b0)
+            valid_x <= valid_d & !kill_d;
+        else if (kill_x ==  1'b1)
+            valid_x <=  1'b0;
+        else if (stall_x ==  1'b0)
+            valid_x <=  1'b0;
+
+        if (kill_m ==  1'b1)
+            valid_m <=  1'b0;
+        else if (stall_x ==  1'b0)
+            valid_m <= valid_x & !kill_x;
+        else if (stall_m ==  1'b0)
+            valid_m <=  1'b0;
+
+        if (stall_m ==  1'b0)
+            valid_w <= valid_m & !kill_m;
+        else 
+            valid_w <=  1'b0;        
+    end
+end
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+  
+                 
+
+        
+        operand_0_x <= { 32{1'b0}};
+        operand_1_x <= { 32{1'b0}};
+        store_operand_x <= { 32{1'b0}};
+        branch_target_x <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};        
+        x_result_sel_csr_x <=  1'b0;
+  
+          
+
+
+      
+          
+
+
+  
+
+        x_result_sel_sext_x <=  1'b0;
+ 
+    
+  
+          
+
+
+        x_result_sel_add_x <=  1'b0;
+        m_result_sel_compare_x <=  1'b0;
+  
+
+        m_result_sel_shift_x <=  1'b0;
+ 
+    
+        w_result_sel_load_x <=  1'b0;
+  
+
+        w_result_sel_mul_x <=  1'b0;
+ 
+
+        x_bypass_enable_x <=  1'b0;
+        m_bypass_enable_x <=  1'b0;
+        write_enable_x <=  1'b0;
+        write_idx_x <= { 5{1'b0}};
+        csr_x <= { 5{1'b0}};
+        load_x <=  1'b0;
+        store_x <=  1'b0;
+        size_x <= { 2{1'b0}};
+        sign_extend_x <=  1'b0;
+        adder_op_x <=  1'b0;
+        adder_op_x_n <=  1'b0;
+        logic_op_x <= 4'h0;
+  
+
+        direction_x <=  1'b0;
+ 
+
+  
+          
+
+
+
+        branch_x <=  1'b0;
+        branch_predict_x <=  1'b0;
+        branch_predict_taken_x <=  1'b0;
+        condition_x <=  3'b000;
+  
+
+        break_x <=  1'b0;
+ 
+
+        scall_x <=  1'b0;
+        eret_x <=  1'b0;
+  
+
+        bret_x <=  1'b0;
+ 
+
+  
+          
+          
+
+
+        csr_write_enable_x <=  1'b0;
+        operand_m <= { 32{1'b0}};
+        branch_target_m <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+        m_result_sel_compare_m <=  1'b0;
+  
+
+        m_result_sel_shift_m <=  1'b0;
+ 
+    
+        w_result_sel_load_m <=  1'b0;
+  
+
+        w_result_sel_mul_m <=  1'b0;
+ 
+
+        m_bypass_enable_m <=  1'b0;
+        branch_m <=  1'b0;
+        branch_predict_m <=  1'b0;
+	branch_predict_taken_m <=  1'b0;
+        exception_m <=  1'b0;
+        load_m <=  1'b0;
+        store_m <=  1'b0;
+        write_enable_m <=  1'b0;            
+        write_idx_m <= { 5{1'b0}};
+        condition_met_m <=  1'b0;
+  
+          
+
+
+  
+
+        debug_exception_m <=  1'b0;
+        non_debug_exception_m <=  1'b0;        
+ 
+
+        operand_w <= { 32{1'b0}};        
+        w_result_sel_load_w <=  1'b0;
+  
+
+        w_result_sel_mul_w <=  1'b0;
+ 
+
+        write_idx_w <= { 5{1'b0}};        
+        write_enable_w <=  1'b0;
+  
+
+        debug_exception_w <=  1'b0;
+        non_debug_exception_w <=  1'b0;        
+ 
+          
+
+
+  
+          
+
+
+    end
+    else
+    begin
+        
+       
+        if (stall_x ==  1'b0)
+        begin
+  
+                     
+
+        
+            operand_0_x <= d_result_0;
+            operand_1_x <= d_result_1;
+            store_operand_x <= bypass_data_1;
+            branch_target_x <= branch_reg_d ==  1'b1 ? bypass_data_0[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] : branch_target_d;            
+            x_result_sel_csr_x <= x_result_sel_csr_d;
+  
+              
+
+
+      
+              
+
+
+  
+
+            x_result_sel_sext_x <= x_result_sel_sext_d;
+ 
+    
+  
+              
+
+
+            x_result_sel_add_x <= x_result_sel_add_d;
+            m_result_sel_compare_x <= m_result_sel_compare_d;
+  
+
+            m_result_sel_shift_x <= m_result_sel_shift_d;
+ 
+    
+            w_result_sel_load_x <= w_result_sel_load_d;
+  
+
+            w_result_sel_mul_x <= w_result_sel_mul_d;
+ 
+
+            x_bypass_enable_x <= x_bypass_enable_d;
+            m_bypass_enable_x <= m_bypass_enable_d;
+            load_x <= load_d;
+            store_x <= store_d;
+            branch_x <= branch_d;
+	    branch_predict_x <= branch_predict_d;
+	    branch_predict_taken_x <= branch_predict_taken_d;
+	    write_idx_x <= write_idx_d;
+            csr_x <= csr_d;
+            size_x <= size_d;
+            sign_extend_x <= sign_extend_d;
+            adder_op_x <= adder_op_d;
+            adder_op_x_n <= ~adder_op_d;
+            logic_op_x <= logic_op_d;
+  
+
+            direction_x <= direction_d;
+ 
+
+  
+              
+
+
+            condition_x <= condition_d;
+            csr_write_enable_x <= csr_write_enable_d;
+  
+
+            break_x <= break_d;
+ 
+
+            scall_x <= scall_d;
+  
+              
+
+
+            eret_x <= eret_d;
+  
+
+            bret_x <= bret_d; 
+ 
+
+            write_enable_x <= write_enable_d;
+        end
+        
+        
+
+        if (stall_m ==  1'b0)
+        begin
+            operand_m <= x_result;
+            m_result_sel_compare_m <= m_result_sel_compare_x;
+  
+
+            m_result_sel_shift_m <= m_result_sel_shift_x;
+ 
+    
+            if (exception_x ==  1'b1)
+            begin
+                w_result_sel_load_m <=  1'b0;
+  
+
+                w_result_sel_mul_m <=  1'b0;
+ 
+
+            end
+            else
+            begin
+                w_result_sel_load_m <= w_result_sel_load_x;
+  
+
+                w_result_sel_mul_m <= w_result_sel_mul_x;
+ 
+
+            end
+            m_bypass_enable_m <= m_bypass_enable_x;
+            load_m <= load_x;
+            store_m <= store_x;
+      
+                
+
+
+            branch_m <= branch_x;
+	    branch_predict_m <= branch_predict_x;
+	    branch_predict_taken_m <= branch_predict_taken_x;
+ 
+
+  
+
+	   
+	   
+	   
+	   
+	   
+            if (non_debug_exception_x ==  1'b1) 
+                write_idx_m <=  5'd30;
+            else if (debug_exception_x ==  1'b1)
+                write_idx_m <=  5'd31;
+            else 
+                write_idx_m <= write_idx_x;
+ 
+               
+                  
+             
+                  
+
+
+            condition_met_m <= condition_met_x;
+  
+
+	   if (exception_x ==  1'b1)
+	     if ((dc_re ==  1'b1)
+		 || ((debug_exception_x ==  1'b1) 
+		     && (non_debug_exception_x ==  1'b0)))
+	       branch_target_m <= {deba, eid_x, {3{1'b0}}};
+	     else
+	       branch_target_m <= {eba, eid_x, {3{1'b0}}};
+	   else
+	     branch_target_m <= branch_target_x;
+ 
+                      
+
+
+  
+              
+              
+
+
+  
+              
+
+
+  
+ 
+               
+
+
+
+            write_enable_m <= exception_x ==  1'b1 ?  1'b1 : write_enable_x;            
+  
+
+            debug_exception_m <= debug_exception_x;
+            non_debug_exception_m <= non_debug_exception_x;        
+ 
+
+        end
+        
+        
+        if (stall_m ==  1'b0)
+        begin
+            if ((exception_x ==  1'b1) && (q_x ==  1'b1) && (stall_x ==  1'b0))
+                exception_m <=  1'b1;
+            else 
+                exception_m <=  1'b0;
+  
+	           
+ 
+					    
+
+					 
+
+
+	end
+                
+        
+  
+                      
+
+
+        operand_w <= exception_m ==  1'b1 ? {pc_m, 2'b00} : m_result;
+ 
+
+        w_result_sel_load_w <= w_result_sel_load_m;
+  
+
+        w_result_sel_mul_w <= w_result_sel_mul_m;
+ 
+
+        write_idx_w <= write_idx_m;
+  
+          
+          
+ 
+           
+
+
+
+        write_enable_w <= write_enable_m;
+  
+
+        debug_exception_w <= debug_exception_m;
+        non_debug_exception_w <= non_debug_exception_m;
+ 
+          
+
+
+  
+              
+                   
+                   
+               
+	   
+            
+
+
+    end
+end
+
+  
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        use_buf <=  1'b0;
+        reg_data_buf_0 <= { 32{1'b0}};
+        reg_data_buf_1 <= { 32{1'b0}};
+    end
+    else
+    begin
+        if (stall_d ==  1'b0)
+            use_buf <=  1'b0;
+        else if (use_buf ==  1'b0)
+        begin        
+            reg_data_buf_0 <= reg_data_live_0;
+            reg_data_buf_1 <= reg_data_live_1;
+            use_buf <=  1'b1;
+        end        
+        if (reg_write_enable_q_w ==  1'b1)
+        begin
+            if (write_idx_w == read_idx_0_d)
+                reg_data_buf_0 <= w_result;
+            if (write_idx_w == read_idx_1_d)
+                reg_data_buf_1 <= w_result;
+        end
+    end
+end
+ 
+
+
+  
+
+ 
+
+   
+
+        
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+        
+     
+           
+            
+        
+
+
+
+
+  
+
+   
+
+       
+    
+          
+          
+          
+          
+          
+ 
+          
+
+          
+    
+    
+    
+          
+        
+ 
+               
+
+           
+
+                
+              
+              
+              
+              
+        
+        
+              
+        
+             
+        
+            
+                 
+            
+                
+                  
+                  
+            
+            
+              
+            
+              
+ 
+              
+
+        
+        
+        
+              
+ 
+              
+
+        
+    
+
+
+
+      
+
+
+
+
+
+        
+endmodule 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_load_store_unit_medium_debug 
+(
+    
+    clk_i,
+    rst_i,
+ 
+    stall_a,
+    stall_x,
+    stall_m,
+    kill_x,
+    kill_m,
+    exception_m,
+    store_operand_x,
+    load_store_address_x,
+    load_store_address_m,
+    load_store_address_w,
+    load_x,
+    store_x,
+    load_q_x,
+    store_q_x,
+    load_q_m,
+    store_q_m,
+    sign_extend_x,
+    size_x,
+  
+    
+
+
+    
+    d_dat_i,
+    d_ack_i,
+    d_err_i,
+    d_rty_i,
+    
+    
+  
+    
+    
+    
+    
+
+    
+  
+    
+    
+    
+    
+    
+    
+    
+
+			     
+    load_data_w,
+    stall_wb_load,
+    
+    d_dat_o,
+    d_adr_o,
+    d_cyc_o,
+    d_sel_o,
+    d_stb_o,
+    d_we_o,
+    d_cti_o,
+    d_lock_o,
+    d_bte_o
+    );
+
+
+
+
+
+parameter associativity = 1;                            
+parameter sets = 512;                                   
+parameter bytes_per_line = 16;                          
+parameter base_address = 0;                             
+parameter limit = 0;                                    
+
+
+localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
+localparam addr_offset_lsb = 2;
+localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
+
+
+
+
+
+   input clk_i;                                            
+   
+input rst_i;                                            
+
+input stall_a;                                          
+input stall_x;                                          
+input stall_m;                                          
+input kill_x;                                           
+input kill_m;                                           
+input exception_m;                                      
+
+input [ (32-1):0] store_operand_x;                 
+input [ (32-1):0] load_store_address_x;            
+input [ (32-1):0] load_store_address_m;            
+input [1:0] load_store_address_w;                       
+input load_x;                                           
+input store_x;                                          
+input load_q_x;                                         
+input store_q_x;                                        
+input load_q_m;                                         
+input store_q_m;                                        
+input sign_extend_x;                                    
+input [ 1:0] size_x;                          
+
+  
+                                            
+
+
+
+     
+     
+     
+      
+      
+            
+    	 
+   
+
+
+
+   reg 		 [31:0] iram_dat_d0;
+   reg 		 iram_en_d0;
+   wire 	 iram_en;
+   wire [31:0] 	 iram_data;
+   
+   
+   
+input [ (32-1):0] d_dat_i;                         
+input d_ack_i;                                          
+input d_err_i;                                          
+input d_rty_i;                                          
+
+
+
+
+
+  
+                            
+   
+                           
+   
+                             
+   
+ 
+   
+
+
+
+   
+output [ (32-1):0] load_data_w;                    
+reg    [ (32-1):0] load_data_w;
+output stall_wb_load;                                   
+reg    stall_wb_load;
+
+output [ (32-1):0] d_dat_o;                        
+reg    [ (32-1):0] d_dat_o;
+output [ (32-1):0] d_adr_o;                        
+reg    [ (32-1):0] d_adr_o;
+output d_cyc_o;                                         
+reg    d_cyc_o;
+output [ (4-1):0] d_sel_o;                 
+reg    [ (4-1):0] d_sel_o;
+output d_stb_o;                                         
+reg    d_stb_o; 
+output d_we_o;                                          
+reg    d_we_o;
+output [ (3-1):0] d_cti_o;                       
+reg    [ (3-1):0] d_cti_o;
+output d_lock_o;                                        
+reg    d_lock_o;
+output [ (2-1):0] d_bte_o;                       
+wire   [ (2-1):0] d_bte_o;
+
+
+
+
+
+
+reg [ 1:0] size_m;
+reg [ 1:0] size_w;
+reg sign_extend_m;
+reg sign_extend_w;
+reg [ (32-1):0] store_data_x;       
+reg [ (32-1):0] store_data_m;       
+reg [ (4-1):0] byte_enable_x;
+reg [ (4-1):0] byte_enable_m;
+wire [ (32-1):0] data_m;
+reg [ (32-1):0] data_w;
+
+   
+
+  
+                                    
+ 
+                      
+              
+                                 
+                  
+                   
+                                          
+                      
+
+
+  
+                                      
+ 
+                                      
+                    
+                      
+                        
+                  
+
+
+wire wb_select_x;                                       
+  
+                                      
+
+  
+    
+    
+   
+
+
+
+reg wb_select_m;
+reg [ (32-1):0] wb_data_m;                         
+reg wb_load_complete;                                   
+   
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+  
+
+ 
+              
+                       
+             
+               
+                      
+       
+    
+                      
+                            
+                    
+                    
+                    
+                  
+                  
+                     
+                    
+                 
+            
+               
+                
+                     
+    
+              
+            
+             
+             
+                  
+                  
+    
+
+
+
+
+
+
+
+
+  
+            
+                             
+
+
+
+  
+            
+                             
+
+      
+        
+
+    
+       
+
+   
+
+    
+     
+       
+     
+         
+     
+
+          
+    
+   
+   
+
+
+   
+  
+            
+                               
+ 
+                               
+
+ 
+                               
+
+                     
+
+
+	  
+   assign wb_select_x =     1'b1
+  
+                          
+
+
+  
+                         
+
+
+  
+                         
+
+
+                     ;
+
+
+always @(*)
+begin
+    case (size_x)
+     2'b00:  store_data_x = {4{store_operand_x[7:0]}};
+     2'b11: store_data_x = {2{store_operand_x[15:0]}};
+     2'b10:  store_data_x = store_operand_x;    
+    default:          store_data_x = { 32{1'bx}};
+    endcase
+end
+
+
+always @(*)
+begin
+    casez ({size_x, load_store_address_x[1:0]})
+    { 2'b00, 2'b11}:  byte_enable_x = 4'b0001;
+    { 2'b00, 2'b10}:  byte_enable_x = 4'b0010;
+    { 2'b00, 2'b01}:  byte_enable_x = 4'b0100;
+    { 2'b00, 2'b00}:  byte_enable_x = 4'b1000;
+    { 2'b11, 2'b1?}: byte_enable_x = 4'b0011;
+    { 2'b11, 2'b0?}: byte_enable_x = 4'b1100;
+    { 2'b10, 2'b??}:  byte_enable_x = 4'b1111;
+    default:                   byte_enable_x = 4'bxxxx;
+    endcase
+end
+
+  
+      
+            
+
+           
+	                            
+   
+   
+               
+        
+
+
+   
+  
+  
+   
+   
+         
+                    
+                       
+                      
+                        
+                     
+                        
+  
+   
+         
+                    
+                       
+                      
+                      
+  
+ 
+   
+   
+         
+                    
+                       
+                      
+                      
+  
+   
+         
+                     
+                    
+  
+ 
+
+
+   
+   
+   
+         
+                     
+                      
+                      
+                      
+  
+   
+         
+                     
+                    
+  
+ 
+
+    
+   
+         
+                     
+                    
+
+  
+
+   
+   assign data_m = wb_data_m;
+   
+
+  
+
+ 
+
+
+
+always @(*)
+begin
+    casez ({size_w, load_store_address_w[1:0]})
+    { 2'b00, 2'b11}:  load_data_w = {{24{sign_extend_w & data_w[7]}}, data_w[7:0]};
+    { 2'b00, 2'b10}:  load_data_w = {{24{sign_extend_w & data_w[15]}}, data_w[15:8]};
+    { 2'b00, 2'b01}:  load_data_w = {{24{sign_extend_w & data_w[23]}}, data_w[23:16]};
+    { 2'b00, 2'b00}:  load_data_w = {{24{sign_extend_w & data_w[31]}}, data_w[31:24]};
+    { 2'b11, 2'b1?}: load_data_w = {{16{sign_extend_w & data_w[15]}}, data_w[15:0]};
+    { 2'b11, 2'b0?}: load_data_w = {{16{sign_extend_w & data_w[31]}}, data_w[31:16]};
+    { 2'b10, 2'b??}:  load_data_w = data_w;
+    default:                   load_data_w = { 32{1'bx}};
+    endcase
+end
+
+
+assign d_bte_o =  2'b00;
+
+                  
+
+ 
+     
+    
+    
+   
+   
+   
+    
+    
+    
+    
+   
+   
+     
+     
+    
+    
+    
+   
+         
+     
+     
+    
+    
+
+
+
+
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        d_cyc_o <=  1'b0;
+        d_stb_o <=  1'b0;
+        d_dat_o <= { 32{1'b0}};
+        d_adr_o <= { 32{1'b0}};
+        d_sel_o <= { 4{ 1'b0}};
+        d_we_o <=  1'b0;
+        d_cti_o <=  3'b111;
+        d_lock_o <=  1'b0;
+        wb_data_m <= { 32{1'b0}};
+        wb_load_complete <=  1'b0;
+        stall_wb_load <=  1'b0;
+                  
+          
+
+                
+    end
+    else 
+    begin
+   
+        
+          
+
+                
+        
+        if (d_cyc_o ==  1'b1)
+        begin
+            
+            if ((d_ack_i ==  1'b1) || (d_err_i ==  1'b1))
+            begin
+                  
+                     
+                
+                    
+                        
+                
+                
+
+                
+                begin
+                    
+                    d_cyc_o <=  1'b0;
+                    d_stb_o <=  1'b0;
+                    d_lock_o <=  1'b0;
+                end
+      
+                  
+                
+                  
+
+
+                
+                wb_data_m <= d_dat_i;
+                
+                wb_load_complete <= !d_we_o;
+            end
+            
+        end
+        else 
+        begin
+                  
+               
+            
+                
+                  
+                  
+                  
+                                  
+                  
+                  
+                
+            
+             
+
+            
+                 if (   (store_q_m ==  1'b1)
+                     && (stall_m ==  1'b0)
+  
+                        
+
+
+  
+		        
+
+			
+                    )
+            begin
+                
+                d_dat_o <= store_data_m;
+                d_adr_o <= load_store_address_m;
+                d_cyc_o <=  1'b1;
+                d_sel_o <= byte_enable_m;
+                d_stb_o <=  1'b1;
+                d_we_o <=  1'b1;
+                d_cti_o <=  3'b111;
+            end        
+            else if (   (load_q_m ==  1'b1) 
+                     && (wb_select_m ==  1'b1) 
+                     && (wb_load_complete ==  1'b0)
+                     
+                    )
+            begin
+                
+                stall_wb_load <=  1'b0;
+                d_adr_o <= load_store_address_m;
+                d_cyc_o <=  1'b1;
+                d_sel_o <= byte_enable_m;
+                d_stb_o <=  1'b1;
+                d_we_o <=  1'b0;
+                d_cti_o <=  3'b111;
+            end
+        end
+        
+        if (stall_m ==  1'b0)
+            wb_load_complete <=  1'b0;
+        
+        if ((load_q_x ==  1'b1) && (wb_select_x ==  1'b1) && (stall_x ==  1'b0))
+            stall_wb_load <=  1'b1;
+        
+        if ((kill_m ==  1'b1) || (exception_m ==  1'b1))
+            stall_wb_load <=  1'b0;
+    end
+end
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        sign_extend_m <=  1'b0;
+        size_m <= 2'b00;
+        byte_enable_m <=  1'b0;
+        store_data_m <= { 32{1'b0}};
+  
+          
+
+
+  
+          
+
+
+  
+          
+			    
+
+
+        wb_select_m <=  1'b0;        
+    end
+    else
+    begin
+        if (stall_m ==  1'b0)
+        begin
+            sign_extend_m <= sign_extend_x;
+            size_m <= size_x;
+            byte_enable_m <= byte_enable_x;    
+            store_data_m <= store_data_x;
+  
+              
+
+
+  
+              
+
+
+  
+              
+			    
+
+
+            wb_select_m <= wb_select_x;
+        end
+    end
+end
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        size_w <= 2'b00;
+        data_w <= { 32{1'b0}};
+        sign_extend_w <=  1'b0;
+    end
+    else
+    begin
+        size_w <= size_m;
+
+  
+         
+
+
+        data_w <= data_m;
+
+        sign_extend_w <= sign_extend_m;
+    end
+end
+
+
+
+
+
+
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_decoder_medium_debug (
+    
+    instruction,
+    
+    d_result_sel_0,
+    d_result_sel_1,        
+    x_result_sel_csr,
+  
+    
+
+    
+      
+    
+
+
+  
+
+    x_result_sel_sext,
+ 
+    
+    x_result_sel_logic,
+  
+    
+
+
+    x_result_sel_add,
+    m_result_sel_compare,
+  
+
+    m_result_sel_shift,  
+ 
+    
+    w_result_sel_load,
+  
+
+    w_result_sel_mul,
+ 
+
+    x_bypass_enable,
+    m_bypass_enable,
+    read_enable_0,
+    read_idx_0,
+    read_enable_1,
+    read_idx_1,
+    write_enable,
+    write_idx,
+    immediate,
+    branch_offset,
+    load,
+    store,
+    size,
+    sign_extend,
+    adder_op,
+    logic_op,
+  
+
+    direction,
+ 
+
+  
+    
+    
+
+
+  
+    
+
+
+  
+    
+    
+
+
+    branch,
+    branch_reg,
+    condition,
+    bi_conditional,
+    bi_unconditional,
+  
+
+    break_opcode,
+ 
+
+    scall,
+    eret,
+  
+
+    bret,
+ 
+
+  
+    
+
+
+    csr_write_enable
+    );
+
+
+
+
+
+input [ (32-1):0] instruction;       
+
+
+
+
+
+output [ 0:0] d_result_sel_0;
+reg    [ 0:0] d_result_sel_0;
+output [ 1:0] d_result_sel_1;
+reg    [ 1:0] d_result_sel_1;
+output x_result_sel_csr;
+reg    x_result_sel_csr;
+  
+ 
+    
+
+
+      
+ 
+    
+
+
+  
+
+output x_result_sel_sext;
+reg    x_result_sel_sext;
+ 
+
+output x_result_sel_logic;
+reg    x_result_sel_logic;
+  
+ 
+    
+
+
+output x_result_sel_add;
+reg    x_result_sel_add;
+output m_result_sel_compare;
+reg    m_result_sel_compare;
+  
+
+output m_result_sel_shift;
+reg    m_result_sel_shift;
+ 
+
+output w_result_sel_load;
+reg    w_result_sel_load;
+  
+
+output w_result_sel_mul;
+reg    w_result_sel_mul;
+ 
+
+output x_bypass_enable;
+wire   x_bypass_enable;
+output m_bypass_enable;
+wire   m_bypass_enable;
+output read_enable_0;
+wire   read_enable_0;
+output [ (5-1):0] read_idx_0;
+wire   [ (5-1):0] read_idx_0;
+output read_enable_1;
+wire   read_enable_1;
+output [ (5-1):0] read_idx_1;
+wire   [ (5-1):0] read_idx_1;
+output write_enable;
+wire   write_enable;
+output [ (5-1):0] write_idx;
+wire   [ (5-1):0] write_idx;
+output [ (32-1):0] immediate;
+wire   [ (32-1):0] immediate;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset;
+wire   [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset;
+output load;
+wire   load;
+output store;
+wire   store;
+output [ 1:0] size;
+wire   [ 1:0] size;
+output sign_extend;
+wire   sign_extend;
+output adder_op;
+wire   adder_op;
+output [ 3:0] logic_op;
+wire   [ 3:0] logic_op;
+  
+
+output direction;
+wire   direction;
+ 
+
+  
+ 
+   
+ 
+   
+
+
+  
+ 
+   
+
+
+  
+ 
+   
+ 
+   
+
+
+output branch;
+wire   branch;
+output branch_reg;
+wire   branch_reg;
+output [ (3-1):0] condition;
+wire   [ (3-1):0] condition;
+output bi_conditional;
+wire bi_conditional;
+output bi_unconditional;
+wire bi_unconditional;
+  
+
+output break_opcode;
+wire   break_opcode;
+ 
+
+output scall;
+wire   scall;
+output eret;
+wire   eret;
+  
+
+output bret;
+wire   bret;
+ 
+
+  
+  
+    
+
+
+output csr_write_enable;
+wire   csr_write_enable;
+
+
+
+
+
+wire [ (32-1):0] extended_immediate;       
+wire [ (32-1):0] high_immediate;           
+wire [ (32-1):0] call_immediate;           
+wire [ (32-1):0] branch_immediate;         
+wire sign_extend_immediate;                     
+wire select_high_immediate;                     
+wire select_call_immediate;                     
+
+wire op_add;
+wire op_and;
+wire op_andhi;
+wire op_b;
+wire op_bi;
+wire op_be;
+wire op_bg;
+wire op_bge;
+wire op_bgeu;
+wire op_bgu;
+wire op_bne;
+wire op_call;
+wire op_calli;
+wire op_cmpe;
+wire op_cmpg;
+wire op_cmpge;
+wire op_cmpgeu;
+wire op_cmpgu;
+wire op_cmpne;
+  
+ 
+
+
+wire op_lb;
+wire op_lbu;
+wire op_lh;
+wire op_lhu;
+wire op_lw;
+  
+ 
+
+
+  
+
+wire op_mul;
+ 
+
+wire op_nor;
+wire op_or;
+wire op_orhi;
+wire op_raise;
+wire op_rcsr;
+wire op_sb;
+  
+
+wire op_sextb;
+wire op_sexth;
+ 
+
+wire op_sh;
+  
+
+wire op_sl;
+ 
+
+wire op_sr;
+wire op_sru;
+wire op_sub;
+wire op_sw;
+  
+ 
+
+
+wire op_wcsr;
+wire op_xnor;
+wire op_xor;
+
+wire arith;
+wire logical;
+wire cmp;
+wire bra;
+wire call;
+  
+
+wire shift;
+ 
+
+  
+ 
+
+
+  
+
+wire sext;
+ 
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+assign op_add    = instruction[ 30:26] ==  5'b01101;
+assign op_and    = instruction[ 30:26] ==  5'b01000;
+assign op_andhi  = instruction[ 31:26] ==  6'b011000;
+assign op_b      = instruction[ 31:26] ==  6'b110000;
+assign op_bi     = instruction[ 31:26] ==  6'b111000;
+assign op_be     = instruction[ 31:26] ==  6'b010001;
+assign op_bg     = instruction[ 31:26] ==  6'b010010;
+assign op_bge    = instruction[ 31:26] ==  6'b010011;
+assign op_bgeu   = instruction[ 31:26] ==  6'b010100;
+assign op_bgu    = instruction[ 31:26] ==  6'b010101;
+assign op_bne    = instruction[ 31:26] ==  6'b010111;
+assign op_call   = instruction[ 31:26] ==  6'b110110;
+assign op_calli  = instruction[ 31:26] ==  6'b111110;
+assign op_cmpe   = instruction[ 30:26] ==  5'b11001;
+assign op_cmpg   = instruction[ 30:26] ==  5'b11010;
+assign op_cmpge  = instruction[ 30:26] ==  5'b11011;
+assign op_cmpgeu = instruction[ 30:26] ==  5'b11100;
+assign op_cmpgu  = instruction[ 30:26] ==  5'b11101;
+assign op_cmpne  = instruction[ 30:26] ==  5'b11111;
+  
+       
+
+
+assign op_lb     = instruction[ 31:26] ==  6'b000100;
+assign op_lbu    = instruction[ 31:26] ==  6'b010000;
+assign op_lh     = instruction[ 31:26] ==  6'b000111;
+assign op_lhu    = instruction[ 31:26] ==  6'b001011;
+assign op_lw     = instruction[ 31:26] ==  6'b001010;
+  
+       
+
+
+  
+
+assign op_mul    = instruction[ 30:26] ==  5'b00010;
+ 
+
+assign op_nor    = instruction[ 30:26] ==  5'b00001;
+assign op_or     = instruction[ 30:26] ==  5'b01110;
+assign op_orhi   = instruction[ 31:26] ==  6'b011110;
+assign op_raise  = instruction[ 31:26] ==  6'b101011;
+assign op_rcsr   = instruction[ 31:26] ==  6'b100100;
+assign op_sb     = instruction[ 31:26] ==  6'b001100;
+  
+
+assign op_sextb  = instruction[ 31:26] ==  6'b101100;
+assign op_sexth  = instruction[ 31:26] ==  6'b110111;
+ 
+
+assign op_sh     = instruction[ 31:26] ==  6'b000011;
+  
+
+assign op_sl     = instruction[ 30:26] ==  5'b01111;      
+ 
+
+assign op_sr     = instruction[ 30:26] ==  5'b00101;
+assign op_sru    = instruction[ 30:26] ==  5'b00000;
+assign op_sub    = instruction[ 31:26] ==  6'b110010;
+assign op_sw     = instruction[ 31:26] ==  6'b010110;
+  
+       
+
+
+assign op_wcsr   = instruction[ 31:26] ==  6'b110100;
+assign op_xnor   = instruction[ 30:26] ==  5'b01001;
+assign op_xor    = instruction[ 30:26] ==  5'b00110;
+
+
+assign arith = op_add | op_sub;
+assign logical = op_and | op_andhi | op_nor | op_or | op_orhi | op_xor | op_xnor;
+assign cmp = op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne;
+assign bi_conditional = op_be | op_bg | op_bge | op_bgeu  | op_bgu | op_bne;
+assign bi_unconditional = op_bi;
+assign bra = op_b | bi_unconditional | bi_conditional;
+assign call = op_call | op_calli;
+  
+
+assign shift = op_sl | op_sr | op_sru;
+ 
+
+  
+     
+
+
+  
+   
+     
+
+
+  
+
+assign sext = op_sextb | op_sexth;
+ 
+
+  
+   
+
+
+  
+    
+   
+
+
+assign load = op_lb | op_lbu | op_lh | op_lhu | op_lw;
+assign store = op_sb | op_sh | op_sw;
+
+
+always @(*)
+begin
+    
+    if (call) 
+        d_result_sel_0 =  1'b1;
+    else 
+        d_result_sel_0 =  1'b0;
+    if (call) 
+        d_result_sel_1 =  2'b00;         
+    else if ((instruction[31] == 1'b0) && !bra) 
+        d_result_sel_1 =  2'b10;
+    else
+        d_result_sel_1 =  2'b01; 
+    
+    x_result_sel_csr =  1'b0;
+  
+      
+
+
+  
+      
+
+
+  
+
+    x_result_sel_sext =  1'b0;
+ 
+
+    x_result_sel_logic =  1'b0;
+          
+      
+
+
+    x_result_sel_add =  1'b0;
+    if (op_rcsr)
+        x_result_sel_csr =  1'b1;
+      
+ 
+         
+          
+
+ 
+        
+                  
+
+ 
+      
+                      
+
+
+
+  
+      
+                  
+
+
+  
+
+    else if (sext)
+        x_result_sel_sext =  1'b1;
+ 
+        
+    else if (logical) 
+        x_result_sel_logic =  1'b1;
+          
+      
+          
+
+
+    else 
+        x_result_sel_add =  1'b1;        
+    
+    
+
+    m_result_sel_compare = cmp;
+  
+
+    m_result_sel_shift = shift;
+ 
+
+
+    
+    w_result_sel_load = load;
+  
+
+    w_result_sel_mul = op_mul; 
+ 
+
+end
+
+
+assign x_bypass_enable =  arith 
+                        | logical
+  
+                         
+                         
+
+                        
+  
+                         
+
+
+  
+                         
+                         
+
+
+  
+                         
+
+                  
+  
+
+                        | sext 
+ 
+                        
+  
+                         
+
+
+                        | op_rcsr
+                        ;
+
+assign m_bypass_enable = x_bypass_enable 
+  
+
+                        | shift
+ 
+
+                        | cmp
+                        ;
+
+assign read_enable_0 = ~(op_bi | op_calli);
+assign read_idx_0 = instruction[25:21];
+
+assign read_enable_1 = ~(op_bi | op_calli | load);
+assign read_idx_1 = instruction[20:16];
+
+assign write_enable = ~(bra | op_raise | store | op_wcsr);
+assign write_idx = call
+                    ? 5'd29
+                    : instruction[31] == 1'b0 
+                        ? instruction[20:16] 
+                        : instruction[15:11];
+                        
+
+assign size = instruction[27:26];
+
+assign sign_extend = instruction[28];                      
+
+assign adder_op = op_sub | op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne | bra;
+
+assign logic_op = instruction[29:26];
+  
+
+
+assign direction = instruction[29];
+ 
+
+
+assign branch = bra | call;
+assign branch_reg = op_call | op_b;
+assign condition = instruction[28:26];      
+  
+
+assign break_opcode = op_raise & ~instruction[2];
+ 
+
+assign scall = op_raise & instruction[2];
+assign eret = op_b & (instruction[25:21] == 5'd30);
+  
+
+assign bret = op_b & (instruction[25:21] == 5'd31);
+ 
+
+  
+
+   
+
+
+
+assign csr_write_enable = op_wcsr;
+
+
+
+assign sign_extend_immediate = ~(op_and | op_cmpgeu | op_cmpgu | op_nor | op_or | op_xnor | op_xor);
+assign select_high_immediate = op_andhi | op_orhi;
+assign select_call_immediate = instruction[31];
+
+assign high_immediate = {instruction[15:0], 16'h0000};
+assign extended_immediate = {{16{sign_extend_immediate & instruction[15]}}, instruction[15:0]};
+assign call_immediate = {{6{instruction[25]}}, instruction[25:0]};
+assign branch_immediate = {{16{instruction[15]}}, instruction[15:0]};
+
+assign immediate = select_high_immediate ==  1'b1 
+                        ? high_immediate 
+                        : extended_immediate;
+   
+assign branch_offset = select_call_immediate ==  1'b1   
+                        ? (call_immediate[ (clogb2(32'h7fffffff-32'h0)-2)-1:0])
+                        : (branch_immediate[ (clogb2(32'h7fffffff-32'h0)-2)-1:0]);
+    
+endmodule 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+  
+
+
+
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+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
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+ 
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+ 
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+ 
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+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_icache_medium_debug ( 
+    
+    clk_i,
+    rst_i,    
+    stall_a,
+    stall_f,
+    address_a,
+    address_f,
+    read_enable_f,
+    refill_ready,
+    refill_data,
+    iflush,
+  
+    
+
+
+    valid_d,
+    branch_predict_taken_d,
+    
+    stall_request,
+    restart_request,
+    refill_request,
+    refill_address,
+    refilling,
+    inst
+    );
+
+
+
+
+
+parameter associativity = 1;                            
+parameter sets = 512;                                   
+parameter bytes_per_line = 16;                          
+parameter base_address = 0;                             
+parameter limit = 0;                                    
+
+localparam addr_offset_width = clogb2(bytes_per_line)-1-2;
+localparam addr_set_width = clogb2(sets)-1;
+localparam addr_offset_lsb = 2;
+localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
+localparam addr_set_lsb = (addr_offset_msb+1);
+localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
+localparam addr_tag_lsb = (addr_set_msb+1);
+localparam addr_tag_msb = clogb2( 32'h7fffffff- 32'h0)-1;
+localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
+
+
+
+
+
+input clk_i;                                        
+input rst_i;                                        
+
+input stall_a;                                      
+input stall_f;                                      
+
+input valid_d;                                      
+input branch_predict_taken_d;                       
+   
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] address_a;                     
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] address_f;                     
+input read_enable_f;                                
+
+input refill_ready;                                 
+input [ (32-1):0] refill_data;          
+
+input iflush;                                       
+  
+                                      
+
+
+   
+
+
+
+
+output stall_request;                               
+wire   stall_request;
+output restart_request;                             
+reg    restart_request;
+output refill_request;                              
+wire   refill_request;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] refill_address;               
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] refill_address;               
+output refilling;                                   
+reg    refilling;
+output [ (32-1):0] inst;                
+wire   [ (32-1):0] inst;
+
+
+
+
+
+wire enable;
+wire [0:associativity-1] way_mem_we;
+wire [ (32-1):0] way_data[0:associativity-1];
+wire [ ((addr_tag_width+1)-1):1] way_tag[0:associativity-1];
+wire [0:associativity-1] way_valid;
+wire [0:associativity-1] way_match;
+wire miss;
+
+wire [ (addr_set_width-1):0] tmem_read_address;
+wire [ (addr_set_width-1):0] tmem_write_address;
+wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_read_address;
+wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_write_address;
+wire [ ((addr_tag_width+1)-1):0] tmem_write_data;
+
+reg [ 3:0] state;
+wire flushing;
+wire check;
+wire refill;
+
+reg [associativity-1:0] refill_way_select;
+reg [ addr_offset_msb:addr_offset_lsb] refill_offset;
+wire last_refill;
+reg [ (addr_set_width-1):0] flush_set;
+
+genvar i;
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+   generate
+      for (i = 0; i < associativity; i = i + 1)
+	begin : memories
+	   
+	   lm32_ram 
+	     #(
+	       
+	       .data_width                 (32),
+	       .address_width              ( (addr_offset_width+addr_set_width))
+
+) 
+	   way_0_data_ram 
+	     (
+	      
+	      .read_clk                   (clk_i),
+	      .write_clk                  (clk_i),
+	      .reset                      (rst_i),
+	      .read_address               (dmem_read_address),
+	      .enable_read                (enable),
+	      .write_address              (dmem_write_address),
+	      .enable_write               ( 1'b1),
+	      .write_enable               (way_mem_we[i]),
+	      .write_data                 (refill_data),    
+	      
+	      .read_data                  (way_data[i])
+	      );
+	   
+	   lm32_ram 
+	     #(
+	       
+	       .data_width                 ( (addr_tag_width+1)),
+	       .address_width              ( addr_set_width)
+
+	       ) 
+	   way_0_tag_ram 
+	     (
+	      
+	      .read_clk                   (clk_i),
+	      .write_clk                  (clk_i),
+	      .reset                      (rst_i),
+	      .read_address               (tmem_read_address),
+	      .enable_read                (enable),
+	      .write_address              (tmem_write_address),
+	      .enable_write               ( 1'b1),
+	      .write_enable               (way_mem_we[i] | flushing),
+	      .write_data                 (tmem_write_data),
+	      
+	      .read_data                  ({way_tag[i], way_valid[i]})
+	      );
+	   
+	end
+endgenerate
+
+
+
+
+
+
+generate
+    for (i = 0; i < associativity; i = i + 1)
+    begin : match
+assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_f[ addr_tag_msb:addr_tag_lsb],  1'b1});
+    end
+endgenerate
+
+
+generate
+    if (associativity == 1)
+    begin : inst_1
+assign inst = way_match[0] ? way_data[0] : 32'b0;
+    end
+    else if (associativity == 2)
+	 begin : inst_2
+assign inst = way_match[0] ? way_data[0] : (way_match[1] ? way_data[1] : 32'b0);
+    end
+endgenerate
+
+
+generate 
+    if (bytes_per_line > 4)
+assign dmem_write_address = {refill_address[ addr_set_msb:addr_set_lsb], refill_offset};
+    else
+assign dmem_write_address = refill_address[ addr_set_msb:addr_set_lsb];
+endgenerate
+    
+assign dmem_read_address = address_a[ addr_set_msb:addr_offset_lsb];
+
+
+assign tmem_read_address = address_a[ addr_set_msb:addr_set_lsb];
+assign tmem_write_address = flushing 
+                                ? flush_set
+                                : refill_address[ addr_set_msb:addr_set_lsb];
+
+
+generate 
+    if (bytes_per_line > 4)                            
+assign last_refill = refill_offset == {addr_offset_width{1'b1}};
+    else
+assign last_refill =  1'b1;
+endgenerate
+
+
+assign enable = (stall_a ==  1'b0);
+
+
+generate
+    if (associativity == 1) 
+    begin : we_1     
+assign way_mem_we[0] = (refill_ready ==  1'b1);
+    end
+    else
+    begin : we_2
+assign way_mem_we[0] = (refill_ready ==  1'b1) && (refill_way_select[0] ==  1'b1);
+assign way_mem_we[1] = (refill_ready ==  1'b1) && (refill_way_select[1] ==  1'b1);
+    end
+endgenerate                     
+
+
+assign tmem_write_data[ 0] = last_refill & !flushing;
+assign tmem_write_data[ ((addr_tag_width+1)-1):1] = refill_address[ addr_tag_msb:addr_tag_lsb];
+
+
+assign flushing = |state[1:0];
+assign check = state[2];
+assign refill = state[3];
+
+assign miss = (~(|way_match)) && (read_enable_f ==  1'b1) && (stall_f ==  1'b0) && !(valid_d && branch_predict_taken_d);
+assign stall_request = (check ==  1'b0);
+assign refill_request = (refill ==  1'b1);
+                      
+
+
+
+
+
+generate
+    if (associativity >= 2) 
+    begin : way_select      
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
+    else
+    begin        
+        if (miss ==  1'b1)
+            refill_way_select <= {refill_way_select[0], refill_way_select[1]};
+    end
+end
+    end
+endgenerate
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        refilling <=  1'b0;
+    else
+        refilling <= refill;
+end
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        state <=  4'b0001;
+        flush_set <= { addr_set_width{1'b1}};
+        refill_address <= { (clogb2(32'h7fffffff-32'h0)-2){1'bx}};
+        restart_request <=  1'b0;
+    end
+    else 
+    begin
+        case (state)
+
+        
+         4'b0001:
+        begin            
+            if (flush_set == { addr_set_width{1'b0}})
+                state <=  4'b0100;
+            flush_set <= flush_set - 1'b1;
+        end
+
+        
+         4'b0010:
+        begin            
+            if (flush_set == { addr_set_width{1'b0}})
+  
+	       
+                  
+	      
+
+
+		state <=  4'b0100;
+	   
+            flush_set <= flush_set - 1'b1;
+        end
+        
+        
+         4'b0100:
+        begin            
+            if (stall_a ==  1'b0)
+                restart_request <=  1'b0;
+            if (iflush ==  1'b1)
+            begin
+                refill_address <= address_f;
+                state <=  4'b0010;
+            end
+            else if (miss ==  1'b1)
+            begin
+                refill_address <= address_f;
+                state <=  4'b1000;
+            end
+        end
+
+        
+         4'b1000:
+        begin            
+            if (refill_ready ==  1'b1)
+            begin
+                if (last_refill ==  1'b1)
+                begin
+                    restart_request <=  1'b1;
+                    state <=  4'b0100;
+                end
+            end
+        end
+
+        endcase        
+    end
+end
+
+generate 
+    if (bytes_per_line > 4)
+    begin
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        refill_offset <= {addr_offset_width{1'b0}};
+    else 
+    begin
+        case (state)
+        
+        
+         4'b0100:
+        begin            
+            if (iflush ==  1'b1)
+                refill_offset <= {addr_offset_width{1'b0}};
+            else if (miss ==  1'b1)
+                refill_offset <= {addr_offset_width{1'b0}};
+        end
+
+        
+         4'b1000:
+        begin            
+            if (refill_ready ==  1'b1)
+                refill_offset <= refill_offset + 1'b1;
+        end
+
+        endcase        
+    end
+end
+    end
+endgenerate
+   
+endmodule
+
+ 
+
+
+
+
+
+
+
+
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+								 
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+               
+                 
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+                    
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+   
+    
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+                                    
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+     
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+                                   
+                                  
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+                     
+        
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+          
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+                     
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+                           
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+                                              
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+   
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+		    
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+		         
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+           
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+		               
+		    
+		      
+		       
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+                              
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+                                   
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+          
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+    
+     
+    
+         
+
+        
+        
+        
+               
+                  
+                
+        
+        
+        
+        
+        
+               
+                  
+               
+            
+                  
+                  
+                  
+            
+                
+                  
+        
+
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+        
+        
+              
+               
+            
+                   
+                
+                      
+                      
+                
+            
+        
+        
+                
+    
+
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+
+       
+    
+
+   
+
+       
+          
+     
+    
+         
+        
+        
+        
+        
+               
+                  
+        
+
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+        
+               
+                    
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+ 
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+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
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+                
+           
+
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+              
+               
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+ 
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+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_debug_medium_debug (
+    
+    clk_i, 
+    rst_i,
+    pc_x,
+    load_x,
+    store_x,
+    load_store_address_x,
+    csr_write_enable_x,
+    csr_write_data,
+    csr_x,
+  
+
+  
+
+    jtag_csr_write_enable,
+    jtag_csr_write_data,
+    jtag_csr,
+ 
+
+  
+   
+   
+   
+
+
+  
+
+
+		   
+  
+
+    eret_q_x,
+    bret_q_x,
+    stall_x,
+    exception_x,
+    q_x,
+  
+    
+
+
+ 
+
+
+    
+  
+
+    dc_ss,
+ 
+
+    dc_re,
+    bp_match,
+    wp_match
+    );
+    
+
+
+
+
+parameter breakpoints = 0;                      
+parameter watchpoints = 0;                      
+
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;                      
+input load_x;                                   
+input store_x;                                  
+input [ (32-1):0] load_store_address_x;    
+input csr_write_enable_x;                       
+input [ (32-1):0] csr_write_data;          
+input [ (5-1):0] csr_x;                    
+  
+
+  
+
+input jtag_csr_write_enable;                    
+input [ (32-1):0] jtag_csr_write_data;     
+input [ (5-1):0] jtag_csr;                 
+ 
+
+     
+                          
+            
+                          
+
+
+ 
+
+
+
+  
+
+input eret_q_x;                                 
+input bret_q_x;                                 
+input stall_x;                                  
+input exception_x;                              
+input q_x;                                      
+  
+                     
+
+
+ 
+
+
+
+
+
+
+  
+
+output dc_ss;                                   
+reg    dc_ss;
+ 
+
+output dc_re;                                   
+reg    dc_re;
+output bp_match;                                
+wire   bp_match;        
+output wp_match;                                
+wire   wp_match;
+
+
+
+
+
+genvar i;                                       
+
+
+
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] bp_a[0:breakpoints-1];       
+reg bp_e[0:breakpoints-1];                      
+wire [0:breakpoints-1]bp_match_n;               
+
+reg [ 1:0] wpc_c[0:watchpoints-1];   
+reg [ (32-1):0] wp[0:watchpoints-1];       
+wire [0:watchpoints-1]wp_match_n;               
+
+wire debug_csr_write_enable;                    
+wire [ (32-1):0] debug_csr_write_data;     
+wire [ (5-1):0] debug_csr;                 
+
+  
+
+
+reg [ 2:0] state;           
+
+ 
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+generate
+    for (i = 0; i < breakpoints; i = i + 1)
+    begin : bp_comb
+assign bp_match_n[i] = ((bp_a[i] == pc_x) && (bp_e[i] ==  1'b1));
+    end
+endgenerate
+generate 
+  
+
+    if (breakpoints > 0) 
+assign bp_match = (|bp_match_n) || (state ==  3'b011);
+    else
+assign bp_match = state ==  3'b011;
+ 
+        
+   
+    
+   
+
+
+endgenerate    
+               
+
+generate 
+    for (i = 0; i < watchpoints; i = i + 1)
+    begin : wp_comb
+assign wp_match_n[i] = (wp[i] == load_store_address_x) && ((load_x & wpc_c[i][0]) | (store_x & wpc_c[i][1]));
+    end               
+endgenerate
+generate
+    if (watchpoints > 0) 
+assign wp_match = |wp_match_n;                
+    else
+assign wp_match =  1'b0;
+endgenerate
+                
+  
+                
+
+  
+
+assign debug_csr_write_enable = (csr_write_enable_x ==  1'b1) || (jtag_csr_write_enable ==  1'b1);
+assign debug_csr_write_data = jtag_csr_write_enable ==  1'b1 ? jtag_csr_write_data : csr_write_data;
+assign debug_csr = jtag_csr_write_enable ==  1'b1 ? jtag_csr : csr_x;
+ 
+
+   
+  
+         
+         
+         
+
+
+
+   
+ 
+   
+   
+   
+
+
+
+
+
+
+
+
+generate
+    for (i = 0; i < breakpoints; i = i + 1)
+    begin : bp_seq
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        bp_a[i] <= { (clogb2(32'h7fffffff-32'h0)-2){1'bx}};
+        bp_e[i] <=  1'b0;
+    end
+    else
+    begin
+        if ((debug_csr_write_enable ==  1'b1) && (debug_csr ==  5'h10 + i))
+        begin
+            bp_a[i] <= debug_csr_write_data[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2];
+            bp_e[i] <= debug_csr_write_data[0];
+        end
+    end
+end    
+    end
+endgenerate
+
+
+generate
+    for (i = 0; i < watchpoints; i = i + 1)
+    begin : wp_seq
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        wp[i] <= { 32{1'bx}};
+        wpc_c[i] <=  2'b00;
+    end
+    else
+    begin
+        if (debug_csr_write_enable ==  1'b1)
+        begin
+            if (debug_csr ==  5'h8)
+                wpc_c[i] <= debug_csr_write_data[3+i*2:2+i*2];
+            if (debug_csr ==  5'h18 + i)
+                wp[i] <= debug_csr_write_data;
+        end
+    end  
+end
+    end
+endgenerate
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        dc_re <=  1'b0;
+    else
+    begin
+        if ((debug_csr_write_enable ==  1'b1) && (debug_csr ==  5'h8))
+            dc_re <= debug_csr_write_data[1];
+    end
+end    
+
+  
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        state <=  3'b000;
+        dc_ss <=  1'b0;
+    end
+    else
+    begin
+        if ((debug_csr_write_enable ==  1'b1) && (debug_csr ==  5'h8))
+        begin
+            dc_ss <= debug_csr_write_data[0];
+            if (debug_csr_write_data[0] ==  1'b0) 
+                state <=  3'b000;
+            else 
+                state <=  3'b001;
+        end
+        case (state)
+         3'b001:
+        begin
+            
+            if (   (   (eret_q_x ==  1'b1)
+                    || (bret_q_x ==  1'b1)
+                    )
+                && (stall_x ==  1'b0)
+               )
+                state <=  3'b010; 
+        end
+         3'b010:
+        begin
+            
+            if ((q_x ==  1'b1) && (stall_x ==  1'b0))
+                state <=  3'b011;
+        end
+         3'b011:
+        begin
+            
+  
+               
+                  
+             
+
+
+                 if ((exception_x ==  1'b1) && (q_x ==  1'b1) && (stall_x ==  1'b0))
+            begin
+                dc_ss <=  1'b0;
+                state <=  3'b100;
+            end
+        end
+         3'b100:
+        begin
+            
+  
+               
+                  
+             
+
+
+                state <=  3'b000;
+        end
+        endcase
+    end
+end
+ 
+
+
+endmodule
+
+ 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_instruction_unit_medium_debug (
+    
+    clk_i,
+    rst_i,
+    
+    stall_a,
+    stall_f,
+    stall_d,
+    stall_x,
+    stall_m,
+    valid_f,
+    valid_d,
+    kill_f,
+    branch_predict_taken_d,
+    branch_predict_address_d,
+      
+    
+    
+
+
+    exception_m,
+    branch_taken_m,
+    branch_mispredict_taken_m,
+    branch_target_m,
+  
+
+    iflush,
+ 
+
+  
+    
+    
+    
+
+        
+  
+
+    
+    i_dat_i,
+    i_ack_i,
+    i_err_i,
+    i_rty_i,
+ 
+
+  
+
+    jtag_read_enable,
+    jtag_write_enable,
+    jtag_write_data,
+    jtag_address,
+ 
+
+    
+    
+    pc_f,
+    pc_d,
+    pc_x,
+    pc_m,
+    pc_w,
+  
+
+    icache_stall_request,
+    icache_restart_request,
+    icache_refill_request,
+    icache_refilling,
+ 
+
+  
+
+    
+    i_dat_o,
+    i_adr_o,
+    i_cyc_o,
+    i_sel_o,
+    i_stb_o,
+    i_we_o,
+    i_cti_o,
+    i_lock_o,
+    i_bte_o,
+ 
+
+  
+    
+    
+    
+
+
+  
+
+    jtag_read_data,
+    jtag_access_complete,
+ 
+
+  
+    
+
+
+  
+
+    instruction_f,
+ 
+    
+    instruction_d
+    );
+
+
+
+
+
+parameter eba_reset =  32'h00000000;                   
+parameter associativity = 1;                            
+parameter sets = 512;                                   
+parameter bytes_per_line = 16;                          
+parameter base_address = 0;                             
+parameter limit = 0;                                    
+
+
+localparam eba_reset_minus_4 = eba_reset - 4;
+localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
+localparam addr_offset_lsb = 2;
+localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
+
+
+
+
+  
+  
+   
+        
+   
+
+
+
+input clk_i;                                            
+input rst_i;                                            
+
+input stall_a;                                          
+input stall_f;                                          
+input stall_d;                                          
+input stall_x;                                          
+input stall_m;                                          
+input valid_f;                                          
+input valid_d;                                          
+input kill_f;                                           
+
+input branch_predict_taken_d;                           
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d;          
+   
+      
+                                    
+                     
+
+
+input exception_m;
+input branch_taken_m;                                   
+input branch_mispredict_taken_m;                        
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_m;                   
+
+  
+
+input iflush;                                           
+ 
+
+  
+                            
+                             
+ 
+
+        
+
+
+  
+
+input [ (32-1):0] i_dat_i;                         
+input i_ack_i;                                          
+input i_err_i;                                          
+input i_rty_i;                                          
+ 
+
+
+  
+
+input jtag_read_enable;                                 
+input jtag_write_enable;                                
+input [ 7:0] jtag_write_data;                 
+input [ (32-1):0] jtag_address;                    
+ 
+
+
+
+
+
+        
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;                             
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;                             
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;                             
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;                             
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;                             
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;
+
+  
+
+output icache_stall_request;                            
+wire   icache_stall_request;
+output icache_restart_request;                          
+wire   icache_restart_request;
+output icache_refill_request;                           
+wire   icache_refill_request;
+output icache_refilling;                                
+wire   icache_refilling;
+ 
+
+
+  
+
+output [ (32-1):0] i_dat_o;                        
+  
+
+reg    [ (32-1):0] i_dat_o;
+ 
+    
+
+
+output [ (32-1):0] i_adr_o;                        
+reg    [ (32-1):0] i_adr_o;
+output i_cyc_o;                                         
+reg    i_cyc_o; 
+output [ (4-1):0] i_sel_o;                 
+  
+
+reg    [ (4-1):0] i_sel_o;
+ 
+    
+
+
+output i_stb_o;                                         
+reg    i_stb_o;
+output i_we_o;                                          
+  
+
+reg    i_we_o;
+ 
+   
+
+
+output [ (3-1):0] i_cti_o;                       
+reg    [ (3-1):0] i_cti_o;
+output i_lock_o;                                        
+reg    i_lock_o;
+output [ (2-1):0] i_bte_o;                       
+wire   [ (2-1):0] i_bte_o;
+ 
+
+
+  
+
+output [ 7:0] jtag_read_data;                 
+reg    [ 7:0] jtag_read_data;
+output jtag_access_complete;                            
+wire   jtag_access_complete;
+ 
+
+
+  
+                                      
+    
+
+
+  
+
+output [ (32-1):0] instruction_f;           
+wire   [ (32-1):0] instruction_f;
+ 
+
+output [ (32-1):0] instruction_d;           
+reg    [ (32-1):0] instruction_d;
+
+
+
+
+
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_a;                                
+
+  
+
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] restart_address;                     
+ 
+
+
+  
+
+wire icache_read_enable_f;                              
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] icache_refill_address;              
+reg icache_refill_ready;                                
+reg [ (32-1):0] icache_refill_data;         
+wire [ (32-1):0] icache_data_f;             
+wire [ (3-1):0] first_cycle_type;                
+wire [ (3-1):0] next_cycle_type;                 
+wire last_word;                                         
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] first_address;                      
+ 
+ 
+                    
+
+
+
+  
+                                      
+    			     
+   
+
+
+  
+
+ 
+               
+
+
+
+   
+  
+   
+    			               
+ 
+
+
+  
+    		       
+
+
+   
+  
+
+reg jtag_access;                                        
+ 
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+  
+
+
+lm32_icache_medium_debug #(
+    .associativity          (associativity),
+    .sets                   (sets),
+    .bytes_per_line         (bytes_per_line),
+    .base_address           (base_address),
+    .limit                  (limit)
+    ) icache ( 
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),      
+    .stall_a                (stall_a),
+    .stall_f                (stall_f),
+    .branch_predict_taken_d (branch_predict_taken_d),
+    .valid_d                (valid_d),
+    .address_a              (pc_a),
+    .address_f              (pc_f),
+    .read_enable_f          (icache_read_enable_f),
+    .refill_ready           (icache_refill_ready),
+    .refill_data            (icache_refill_data),
+    .iflush                 (iflush),
+    
+    .stall_request          (icache_stall_request),
+    .restart_request        (icache_restart_request),
+    .refill_request         (icache_refill_request),
+    .refill_address         (icache_refill_address),
+    .refilling              (icache_refilling),
+    .inst                   (icache_data_f)
+    );
+ 
+
+
+
+
+
+
+  
+
+   
+   assign icache_read_enable_f =    (valid_f ==  1'b1)
+     && (kill_f ==  1'b0)
+   
+      
+ 
+                         
+    
+				       
+ 
+       
+				    ;
+ 
+ 
+
+
+always @(*)
+begin
+    
+  
+       
+          
+     
+
+    
+      if (branch_taken_m ==  1'b1)
+	if ((branch_mispredict_taken_m ==  1'b1) && (exception_m ==  1'b0))
+	  pc_a = pc_x;
+	else
+          pc_a = branch_target_m;
+      
+          
+          
+
+
+      else
+	if ( (valid_d ==  1'b1) && (branch_predict_taken_d ==  1'b1) )
+	  pc_a = branch_predict_address_d;
+	else
+  
+
+          if (icache_restart_request ==  1'b1)
+            pc_a = restart_address;
+	  else 
+ 
+        
+            pc_a = pc_f + 1'b1;
+end
+
+
+  
+      
+      
+        
+
+
+
+  
+
+     
+    	      
+
+     
+      
+	  
+       
+	  
+	
+	    
+     
+   
+   
+          
+
+
+  
+   
+
+
+                     
+
+  
+
+assign instruction_f = icache_data_f;
+ 
+   
+
+
+
+ 
+ 
+   
+
+  
+
+  
+
+ 
+   
+   
+   
+
+
+assign i_bte_o =  2'b00;
+ 
+
+
+  
+
+
+generate
+    case (bytes_per_line)
+    4:
+    begin
+assign first_cycle_type =  3'b111;
+assign next_cycle_type =  3'b111;
+assign last_word =  1'b1;
+assign first_address = icache_refill_address;
+    end
+    8:
+    begin
+assign first_cycle_type =  3'b010;
+assign next_cycle_type =  3'b111;
+assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 1'b1;
+assign first_address = {icache_refill_address[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
+    end
+    16:
+    begin
+assign first_cycle_type =  3'b010;
+assign next_cycle_type = i_adr_o[addr_offset_msb] == 1'b1 ?  3'b111 :  3'b010;
+assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 2'b11;
+assign first_address = {icache_refill_address[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
+    end
+    endcase
+endgenerate
+ 
+
+                     
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        pc_f <= eba_reset_minus_4[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2];
+        pc_d <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+        pc_x <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+        pc_m <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+        pc_w <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+    end
+    else
+    begin
+        if (stall_f ==  1'b0)
+            pc_f <= pc_a;
+        if (stall_d ==  1'b0)
+            pc_d <= pc_f;
+        if (stall_x ==  1'b0)
+            pc_x <= pc_d;
+        if (stall_m ==  1'b0)
+            pc_m <= pc_x;
+        pc_w <= pc_m;
+    end
+end
+
+  
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        restart_address <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+    else
+    begin
+  
+         
+            
+               
+                  
+                    
+                  
+
+               
+                  
+
+
+
+  
+        
+            if (icache_refill_request ==  1'b1)
+                restart_address <= icache_refill_address;
+ 
+
+ 
+
+    end
+end
+ 
+
+
+
+  
+   
+
+       
+          
+    
+    
+           
+              
+    
+
+
+
+
+  
+
+     
+
+assign jtag_access_complete = (i_cyc_o ==  1'b1) && ((i_ack_i ==  1'b1) || (i_err_i ==  1'b1)) && (jtag_access ==  1'b1);
+always @(*)
+begin
+    case (jtag_address[1:0])
+    2'b00: jtag_read_data = i_dat_i[ 31:24];
+    2'b01: jtag_read_data = i_dat_i[ 23:16];
+    2'b10: jtag_read_data = i_dat_i[ 15:8];
+    2'b11: jtag_read_data = i_dat_i[ 7:0];
+    endcase 
+end
+    
+
+ 
+
+
+  
+
+   
+   
+                
+   always @(posedge clk_i  )
+     begin
+	if (rst_i ==  1'b1)
+	  begin
+             i_cyc_o <=  1'b0;
+             i_stb_o <=  1'b0;
+             i_adr_o <= { 32{1'b0}};
+             i_cti_o <=  3'b111;
+             i_lock_o <=  1'b0;
+             icache_refill_data <= { 32{1'b0}};
+             icache_refill_ready <=  1'b0;
+    
+               
+  
+
+    
+
+             i_we_o <=  1'b0;
+             i_sel_o <= 4'b1111;
+             jtag_access <=  1'b0;
+   
+
+	  end
+	else
+	  begin   
+             icache_refill_ready <=  1'b0;
+             
+             if (i_cyc_o ==  1'b1)
+               begin
+		  
+		  if ((i_ack_i ==  1'b1) || (i_err_i ==  1'b1))
+		    begin
+    
+
+                       if (jtag_access ==  1'b1)
+			 begin
+			    i_cyc_o <=  1'b0;
+			    i_stb_o <=  1'b0;       
+			    i_we_o <=  1'b0;  
+			    jtag_access <=  1'b0;    
+			 end
+                       else
+   
+
+			 begin
+			    if (last_word ==  1'b1)
+			      begin
+				 
+				 i_cyc_o <=  1'b0;
+				 i_stb_o <=  1'b0;
+				 i_lock_o <=  1'b0;
+			      end
+			    
+			    i_adr_o[addr_offset_msb:addr_offset_lsb] <= i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
+			    i_cti_o <= next_cycle_type;
+			    
+			    icache_refill_ready <=  1'b1;
+			    icache_refill_data <= i_dat_i;
+			 end
+		    end
+    
+		   
+		     
+		    
+                         
+                         
+		    
+		  
+  
+
+               end
+             else
+               begin
+		  if ((icache_refill_request ==  1'b1) && (icache_refill_ready ==  1'b0))
+		    begin
+                       
+    
+     
+                       i_sel_o <= 4'b1111;
+   
+
+                       i_adr_o <= {first_address, 2'b00};
+                       i_cyc_o <=  1'b1;
+                       i_stb_o <=  1'b1;                
+                       i_cti_o <= first_cycle_type;
+                       
+    
+                         
+  
+
+		    end
+    
+
+		  else
+		    begin
+                       if ((jtag_read_enable ==  1'b1) || (jtag_write_enable ==  1'b1))
+			 begin
+			    case (jtag_address[1:0])
+			      2'b00: i_sel_o <= 4'b1000;
+			      2'b01: i_sel_o <= 4'b0100;
+			      2'b10: i_sel_o <= 4'b0010;
+			      2'b11: i_sel_o <= 4'b0001;
+			    endcase
+			    i_adr_o <= jtag_address;
+			    i_dat_o <= {4{jtag_write_data}};
+			    i_cyc_o <=  1'b1;
+			    i_stb_o <=  1'b1;
+			    i_we_o <= jtag_write_enable;
+			    i_cti_o <=  3'b111;
+			    jtag_access <=  1'b1;
+			 end
+		    end 
+   
+                    
+    
+		  
+		  
+        
+		     
+                      
+   
+		     
+                      
+  
+
+               end
+	  end
+     end
+  
+      
+     
+	   
+	  
+               
+               
+               
+               
+               
+               
+   
+               
+  
+	  
+	
+	     
+             
+                
+               
+		  
+		        
+		    
+                       
+                         
+                         
+                       
+                         
+		    
+   
+		   
+		     
+		    
+                         
+                         
+		       
+		    
+		  
+  
+               
+             
+               
+		  
+		         
+    
+			    
+         
+			 
+		    
+                       
+        
+                         
+  
+                          
+                         
+                         
+   
+                         
+  
+		    
+		  
+		    
+	                      
+    
+			         
+         
+			      
+			 
+   
+			      
+  
+			 
+		    
+               
+	  
+     
+ 
+
+ 
+ 
+
+   
+   always @(posedge clk_i  )
+     begin
+	if (rst_i ==  1'b1)
+	  begin
+             instruction_d <= { 32{1'b0}};
+  
+               
+
+
+	  end
+	else
+	  begin
+             if (stall_d ==  1'b0)
+               begin
+		  instruction_d <= instruction_f;
+  
+		    
+
+
+               end
+	  end
+     end  
+   
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+  
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
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+ 
+ 
+ 
+ 
+ 
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+ 
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+ 
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+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+  
+
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_jtag_medium_debug (
+    
+    clk_i,
+    rst_i,
+    jtag_clk, 
+    jtag_update,
+    jtag_reg_q,
+    jtag_reg_addr_q,
+  
+
+    csr,
+    csr_write_enable,
+    csr_write_data,
+    stall_x,
+ 
+
+  
+
+    jtag_read_data,
+    jtag_access_complete,
+ 
+
+  
+
+    exception_q_w,
+ 
+
+    
+  
+
+    jtx_csr_read_data,
+    jrx_csr_read_data,
+ 
+
+  
+
+    jtag_csr_write_enable,
+    jtag_csr_write_data,
+    jtag_csr,
+    jtag_read_enable,
+    jtag_write_enable,
+    jtag_write_data,
+    jtag_address,
+ 
+
+  
+
+    jtag_break,
+    jtag_reset,
+ 
+
+    jtag_reg_d,
+    jtag_reg_addr_d
+    );
+
+
+
+
+
+input clk_i;                                            
+input rst_i;                                            
+
+input jtag_clk;                                         
+input jtag_update;                                      
+input [ 7:0] jtag_reg_q;                      
+input [2:0] jtag_reg_addr_q;                            
+
+  
+
+input [ (5-1):0] csr;                              
+input csr_write_enable;                                 
+input [ (32-1):0] csr_write_data;                  
+input stall_x;                                          
+ 
+
+  
+
+input [ 7:0] jtag_read_data;                  
+input jtag_access_complete;                             
+ 
+
+  
+
+input exception_q_w;                                    
+ 
+
+
+
+
+
+       
+  
+
+output [ (32-1):0] jtx_csr_read_data;              
+wire   [ (32-1):0] jtx_csr_read_data;
+output [ (32-1):0] jrx_csr_read_data;              
+wire   [ (32-1):0] jrx_csr_read_data;
+ 
+
+  
+
+output jtag_csr_write_enable;                           
+reg    jtag_csr_write_enable;
+output [ (32-1):0] jtag_csr_write_data;            
+wire   [ (32-1):0] jtag_csr_write_data;
+output [ (5-1):0] jtag_csr;                        
+wire   [ (5-1):0] jtag_csr;
+output jtag_read_enable;                                
+reg    jtag_read_enable;
+output jtag_write_enable;                               
+reg    jtag_write_enable;
+output [ 7:0] jtag_write_data;                
+wire   [ 7:0] jtag_write_data;        
+output [ (32-1):0] jtag_address;                   
+wire   [ (32-1):0] jtag_address;
+ 
+
+  
+
+output jtag_break;                                      
+reg    jtag_break;
+output jtag_reset;                                      
+reg    jtag_reset;
+ 
+
+output [ 7:0] jtag_reg_d;
+reg    [ 7:0] jtag_reg_d;
+output [2:0] jtag_reg_addr_d;
+wire   [2:0] jtag_reg_addr_d;
+             
+
+
+
+
+reg rx_update;                          
+reg rx_update_r;                        
+reg rx_update_r_r;                      
+reg rx_update_r_r_r;                    
+
+
+
+wire [ 7:0] rx_byte;   
+wire [2:0] rx_addr;
+
+  
+                 
+reg [ 7:0] uart_tx_byte;      
+reg uart_tx_valid;                      
+reg [ 7:0] uart_rx_byte;      
+reg uart_rx_valid;                      
+ 
+
+
+reg [ 3:0] command;             
+  
+
+reg [ 7:0] jtag_byte_0;       
+reg [ 7:0] jtag_byte_1;
+reg [ 7:0] jtag_byte_2;
+reg [ 7:0] jtag_byte_3;
+reg [ 7:0] jtag_byte_4;
+reg processing;                         
+ 
+
+
+reg [ 3:0] state;       
+
+
+
+
+
+  
+
+assign jtag_csr_write_data = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
+assign jtag_csr = jtag_byte_4[ (5-1):0];
+assign jtag_address = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
+assign jtag_write_data = jtag_byte_4;
+ 
+
+                 
+
+  
+                 
+assign jtag_reg_addr_d[1:0] = {uart_rx_valid, uart_tx_valid};         
+ 
+   
+
+
+  
+
+assign jtag_reg_addr_d[2] = processing;
+ 
+   
+
+
+
+  
+                 
+assign jtx_csr_read_data = {{ 32-9{1'b0}}, uart_tx_valid, 8'h00};
+assign jrx_csr_read_data = {{ 32-9{1'b0}}, uart_rx_valid, uart_rx_byte};
+ 
+         
+                 
+
+
+
+
+assign rx_byte = jtag_reg_q;
+assign rx_addr = jtag_reg_addr_q;
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        rx_update <= 1'b0;
+        rx_update_r <= 1'b0;
+        rx_update_r_r <= 1'b0;
+        rx_update_r_r_r <= 1'b0;
+    end
+    else
+    begin
+        rx_update <= jtag_update;
+        rx_update_r <= rx_update;
+        rx_update_r_r <= rx_update_r;
+        rx_update_r_r_r <= rx_update_r_r;
+    end
+end
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        state <=  4'h0;
+        command <= 4'b0000;
+        jtag_reg_d <= 8'h00;
+  
+
+        processing <=  1'b0;
+        jtag_csr_write_enable <=  1'b0;
+        jtag_read_enable <=  1'b0;
+        jtag_write_enable <=  1'b0;
+ 
+
+  
+
+        jtag_break <=  1'b0;
+        jtag_reset <=  1'b0;
+ 
+
+  
+                 
+        uart_tx_byte <= 8'h00;
+        uart_tx_valid <=  1'b0;
+        uart_rx_byte <= 8'h00;
+        uart_rx_valid <=  1'b0;
+ 
+
+    end
+    else
+    begin
+  
+                 
+        if ((csr_write_enable ==  1'b1) && (stall_x ==  1'b0))
+        begin
+            case (csr)
+             5'he:
+            begin
+                
+                uart_tx_byte <= csr_write_data[ 7:0];
+                uart_tx_valid <=  1'b1;
+            end
+             5'hf:
+            begin
+                
+                uart_rx_valid <=  1'b0;
+            end
+            endcase
+        end
+ 
+
+  
+
+        
+        if (exception_q_w ==  1'b1)
+        begin
+            jtag_break <=  1'b0;
+            jtag_reset <=  1'b0;
+        end
+ 
+
+        case (state)
+         4'h0:
+        begin
+            
+            if ((~rx_update_r_r_r & rx_update_r_r) ==  1'b1)
+            begin
+                command <= rx_byte[7:4];                
+                case (rx_addr)
+  
+
+                 3'b000:
+                begin
+                    case (rx_byte[7:4])
+  
+
+                     4'b0001:
+                        state <=  4'h1;
+                     4'b0011:
+                    begin
+                        {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
+                        state <=  4'h6;
+                    end
+                     4'b0010:
+                        state <=  4'h1;
+                     4'b0100:
+                    begin
+                        {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
+                        state <= 5;
+                    end
+                     4'b0101:
+                        state <=  4'h1;
+ 
+                    
+                     4'b0110:
+                    begin
+  
+     
+                        uart_rx_valid <=  1'b0;    
+                        uart_tx_valid <=  1'b0;         
+ 
+
+                        jtag_break <=  1'b1;
+                    end
+                     4'b0111:
+                    begin
+  
+     
+                        uart_rx_valid <=  1'b0;    
+                        uart_tx_valid <=  1'b0;         
+ 
+
+                        jtag_reset <=  1'b1;
+                    end
+                    endcase                               
+                end
+ 
+
+  
+                 
+                 3'b001:
+                begin
+                    uart_rx_byte <= rx_byte;
+                    uart_rx_valid <=  1'b1;
+                end                    
+                 3'b010:
+                begin
+                    jtag_reg_d <= uart_tx_byte;
+                    uart_tx_valid <=  1'b0;
+                end
+ 
+
+                default:
+                    ;
+                endcase                
+            end
+        end
+  
+
+         4'h1:
+        begin
+            if ((~rx_update_r_r_r & rx_update_r_r) ==  1'b1)
+            begin
+                jtag_byte_0 <= rx_byte;
+                state <=  4'h2;
+            end
+        end
+         4'h2:
+        begin
+            if ((~rx_update_r_r_r & rx_update_r_r) ==  1'b1)
+            begin
+                jtag_byte_1 <= rx_byte;
+                state <=  4'h3;
+            end
+        end
+         4'h3:
+        begin
+            if ((~rx_update_r_r_r & rx_update_r_r) ==  1'b1)
+            begin
+                jtag_byte_2 <= rx_byte;
+                state <=  4'h4;
+            end
+        end
+         4'h4:
+        begin
+            if ((~rx_update_r_r_r & rx_update_r_r) ==  1'b1)
+            begin
+                jtag_byte_3 <= rx_byte;
+                if (command ==  4'b0001)
+                    state <=  4'h6;
+                else 
+                    state <=  4'h5;
+            end
+        end
+         4'h5:
+        begin
+            if ((~rx_update_r_r_r & rx_update_r_r) ==  1'b1)
+            begin
+                jtag_byte_4 <= rx_byte;
+                state <=  4'h6;
+            end
+        end
+         4'h6:
+        begin
+            case (command)
+             4'b0001,
+             4'b0011:
+            begin
+                jtag_read_enable <=  1'b1;
+                processing <=  1'b1;
+                state <=  4'h7;
+            end
+             4'b0010,
+             4'b0100:
+            begin
+                jtag_write_enable <=  1'b1;
+                processing <=  1'b1;
+                state <=  4'h7;
+            end
+             4'b0101:
+            begin
+                jtag_csr_write_enable <=  1'b1;
+                processing <=  1'b1;
+                state <=  4'h8;
+            end
+            endcase
+        end
+         4'h7:
+        begin
+            if (jtag_access_complete ==  1'b1)
+            begin          
+                jtag_read_enable <=  1'b0;
+                jtag_reg_d <= jtag_read_data;
+                jtag_write_enable <=  1'b0;  
+                processing <=  1'b0;
+                state <=  4'h0;
+            end
+        end    
+         4'h8:
+        begin
+            jtag_csr_write_enable <=  1'b0;
+            processing <=  1'b0;
+            state <=  4'h0;
+        end    
+ 
+
+        endcase
+    end
+end
+  
+endmodule
+
+ 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_interrupt_medium_debug (
+    
+    clk_i, 
+    rst_i,
+    
+    interrupt,
+    
+    stall_x,
+  
+
+    non_debug_exception,
+    debug_exception,
+ 
+    
+
+
+    eret_q_x,
+  
+
+    bret_q_x,
+ 
+
+    csr,
+    csr_write_data,
+    csr_write_enable,
+    
+    interrupt_exception,
+    
+    csr_read_data
+    );
+
+
+
+
+
+parameter interrupts =  32;         
+
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+
+input [interrupts-1:0] interrupt;               
+
+input stall_x;                                  
+
+  
+
+input non_debug_exception;                      
+input debug_exception;                          
+ 
+                                 
+
+
+input eret_q_x;                                 
+  
+
+input bret_q_x;                                 
+ 
+
+
+input [ (5-1):0] csr;                      
+input [ (32-1):0] csr_write_data;          
+input csr_write_enable;                         
+
+
+
+
+
+output interrupt_exception;                     
+wire   interrupt_exception;
+
+output [ (32-1):0] csr_read_data;          
+reg    [ (32-1):0] csr_read_data;
+
+
+
+
+
+wire [interrupts-1:0] asserted;                 
+
+wire [interrupts-1:0] interrupt_n_exception;
+
+
+
+reg ie;                                         
+reg eie;                                        
+  
+
+reg bie;                                        
+ 
+
+reg [interrupts-1:0] ip;                        
+reg [interrupts-1:0] im;                        
+
+
+
+
+
+
+assign interrupt_n_exception = ip & im;
+
+
+assign interrupt_exception = (|interrupt_n_exception) & ie;
+
+
+assign asserted = ip | interrupt;
+       
+generate
+    if (interrupts > 1) 
+    begin
+
+always @(*)
+begin
+    case (csr)
+     5'h0:  csr_read_data = {{ 32-3{1'b0}}, 
+  
+
+                                    bie,
+ 
+                                                                         
+
+
+                                    eie, 
+                                    ie
+                                   };
+     5'h2:  csr_read_data = ip;
+     5'h1:  csr_read_data = im;
+    default:       csr_read_data = { 32{1'bx}};
+    endcase
+end
+    end
+    else
+    begin
+
+always @(*)
+begin
+    case (csr)
+     5'h0:  csr_read_data = {{ 32-3{1'b0}}, 
+  
+
+                                    bie, 
+ 
+                                                                        
+
+
+                                    eie, 
+                                    ie
+                                   };
+     5'h2:  csr_read_data = ip;
+    default:       csr_read_data = { 32{1'bx}};
+      endcase
+end
+    end
+endgenerate
+    
+
+
+
+
+  
+
+   reg [ 10:0] eie_delay  = 0;
+
+   
+generate
+
+   
+    if (interrupts > 1)
+    begin
+
+always @(posedge clk_i  )
+  begin
+    if (rst_i ==  1'b1)
+    begin
+        ie                   <=  1'b0;
+        eie                  <=  1'b0;
+  
+
+        bie                  <=  1'b0;
+ 
+
+        im                   <= {interrupts{1'b0}};
+        ip                   <= {interrupts{1'b0}};
+       eie_delay             <= 0;
+       
+    end
+    else
+    begin
+        
+        ip                   <= asserted;
+  
+
+        if (non_debug_exception ==  1'b1)
+        begin
+            
+            eie              <= ie;
+            ie               <=  1'b0;
+        end
+        else if (debug_exception ==  1'b1)
+        begin
+            
+            bie              <= ie;
+            ie               <=  1'b0;
+        end
+ 
+           
+        
+            
+                           
+                            
+        
+
+
+        else if (stall_x ==  1'b0)
+        begin
+
+           if(eie_delay[0])
+             ie              <= eie;
+           
+           eie_delay         <= {1'b0, eie_delay[ 10:1]};
+
+            if (eret_q_x ==  1'b1) begin
+                
+               eie_delay[ 10] <=  1'b1;
+               eie_delay[ 10-1:0] <= 0;
+            end
+           
+                      
+           
+  
+
+            else if (bret_q_x ==  1'b1)
+                
+                ie      <= bie;
+ 
+
+            else if (csr_write_enable ==  1'b1)
+            begin
+                
+                if (csr ==  5'h0)
+                begin
+                    ie  <= csr_write_data[0];
+                    eie <= csr_write_data[1];
+  
+
+                    bie <= csr_write_data[2];
+ 
+
+                end
+                if (csr ==  5'h1)
+                    im  <= csr_write_data[interrupts-1:0];
+                if (csr ==  5'h2)
+                    ip  <= asserted & ~csr_write_data[interrupts-1:0];
+            end
+        end
+    end
+end
+    end
+else
+    begin
+
+always @(posedge clk_i  )
+  begin
+    if (rst_i ==  1'b1)
+    begin
+        ie              <=  1'b0;
+        eie             <=  1'b0;
+  
+
+        bie             <=  1'b0;
+ 
+
+        ip              <= {interrupts{1'b0}};
+       eie_delay        <= 0;
+    end
+    else
+    begin
+        
+        ip              <= asserted;
+  
+
+        if (non_debug_exception ==  1'b1)
+        begin
+            
+            eie         <= ie;
+            ie          <=  1'b0;
+        end
+        else if (debug_exception ==  1'b1)
+        begin
+            
+            bie         <= ie;
+            ie          <=  1'b0;
+        end
+ 
+           
+        
+            
+                      
+                       
+        
+
+
+        else if (stall_x ==  1'b0)
+          begin
+
+             if(eie_delay[0])
+               ie              <= eie;
+           
+             eie_delay         <= {1'b0, eie_delay[ 10:1]};
+
+             if (eret_q_x ==  1'b1) begin
+                
+                eie_delay[ 10] <=  1'b1;
+                eie_delay[ 10-1:0] <= 0;
+             end
+           
+  
+
+            else if (bret_q_x ==  1'b1)
+                
+                ie      <= bie;
+ 
+
+            else if (csr_write_enable ==  1'b1)
+            begin
+                
+                if (csr ==  5'h0)
+                begin
+                    ie  <= csr_write_data[0];
+                    eie <= csr_write_data[1];
+  
+
+                    bie <= csr_write_data[2];
+ 
+
+                end
+                if (csr ==  5'h2)
+                    ip  <= asserted & ~csr_write_data[interrupts-1:0];
+            end
+        end
+    end
+end
+    end
+endgenerate
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+	 
+	 
+	 
+	 
+	
+
+ 
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+  
+
+
+
+
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+ 
+
+
+
+  
+
+  
+
+ 
+
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+ 
+ 
+                    
+
+  
+                    
+
+
+
+  
+
+
+
+  
+
+  
+
+
+
+  
+
+  
+
+
+
+  
+
+  
+
+
+
+  
+ 
+
+
+  
+ 
+
+
+ 
+
+
+
+  
+ 
+
+
+  
+ 
+
+
+ 
+
+ 
+
+
+
+  
+
+  
+
+  
+ 
+ 
+
+ 
+
+
+ 
+
+
+  
+
+  
+
+ 
+ 
+ 
+
+
+
+
+
+  
+ 
+
+
+  
+ 
+
+
+  
+ 
+
+
+
+
+  
+
+  
+
+ 
+
+  
+ 
+
+
+
+
+  
+
+
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+                   
+                     
+
+
+  
+                   
+                     
+
+
+  
+
+  
+
+ 
+
+ 
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+                      
+                    
+
+
+  
+
+  
+
+  
+
+  
+                     
+                     
+
+
+  
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+
+ 
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+  
+
+  
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+
+  
+
+  
+
+
+
+  
+
+  
+
+ 
+ 
+ 
+
+
+
+
+
+
+
+
+
+  
+
+  
+
+  
+
+
+
+
+
+
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+
+
+  
+
+
+
+
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+ 
+
+
+
+
+
+
+
+
+module lm32_top_medium_icache (
+    
+    clk_i,
+    rst_i,
+    
+
+    interrupt,
+
+    
+  
+    
+    
+
+     
+  
+
+    
+    I_DAT_I,
+    I_ACK_I,
+    I_ERR_I,
+    I_RTY_I,
+ 
+
+    
+    D_DAT_I,
+    D_ACK_I,
+    D_ERR_I,
+    D_RTY_I,
+    
+      
+    
+    
+    
+    
+
+    
+  
+
+    
+    I_DAT_O,
+    I_ADR_O,
+    I_CYC_O,
+    I_SEL_O,
+    I_STB_O,
+    I_WE_O,
+    I_CTI_O,
+    I_LOCK_O,
+    I_BTE_O,
+ 
+
+    
+    D_DAT_O,
+    D_ADR_O,
+    D_CYC_O,
+    D_SEL_O,
+    D_STB_O,
+    D_WE_O,
+    D_CTI_O,
+    D_LOCK_O,
+    D_BTE_O
+    );
+
+parameter eba_reset = 32'h00000000;
+parameter sdb_address = 32'h00000000;
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+
+
+input [ (32-1):0] interrupt;          
+
+
+  
+               
+                             
+
+    
+
+  
+
+input [ (32-1):0] I_DAT_I;                 
+input I_ACK_I;                                  
+input I_ERR_I;                                  
+input I_RTY_I;                                  
+ 
+
+
+input [ (32-1):0] D_DAT_I;                 
+input D_ACK_I;                                  
+input D_ERR_I;                                  
+input D_RTY_I;                                  
+
+
+
+
+
+  
+                               
+   
+       
+     
+           
+    
+           
+    
+
+
+
+  
+
+output [ (32-1):0] I_DAT_O;                
+wire   [ (32-1):0] I_DAT_O;
+output [ (32-1):0] I_ADR_O;                
+wire   [ (32-1):0] I_ADR_O;
+output I_CYC_O;                                 
+wire   I_CYC_O;
+output [ (4-1):0] I_SEL_O;         
+wire   [ (4-1):0] I_SEL_O;
+output I_STB_O;                                 
+wire   I_STB_O;
+output I_WE_O;                                  
+wire   I_WE_O;
+output [ (3-1):0] I_CTI_O;               
+wire   [ (3-1):0] I_CTI_O;
+output I_LOCK_O;                                
+wire   I_LOCK_O;
+output [ (2-1):0] I_BTE_O;               
+wire   [ (2-1):0] I_BTE_O;
+ 
+
+
+output [ (32-1):0] D_DAT_O;                
+wire   [ (32-1):0] D_DAT_O;
+output [ (32-1):0] D_ADR_O;                
+wire   [ (32-1):0] D_ADR_O;
+output D_CYC_O;                                 
+wire   D_CYC_O;
+output [ (4-1):0] D_SEL_O;         
+wire   [ (4-1):0] D_SEL_O;
+output D_STB_O;                                 
+wire   D_STB_O;
+output D_WE_O;                                  
+wire   D_WE_O;
+output [ (3-1):0] D_CTI_O;               
+wire   [ (3-1):0] D_CTI_O;
+output D_LOCK_O;                                
+wire   D_LOCK_O;
+output [ (2-1):0] D_BTE_O;               
+wire   [ (2-1):0] D_BTE_O;
+  
+
+
+
+ 
+  
+
+  
+  
+ 
+  
+  
+ 
+ 
+
+
+
+
+  
+
+                     
+                             
+                            
+                   
+                                 
+ 
+                                 
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+   
+
+lm32_cpu_medium_icache 
+	#(
+		.eba_reset(eba_reset),
+    .sdb_address(sdb_address)
+	) cpu (
+    
+    .clk_i                 (clk_i),
+  
+                   
+
+
+    .rst_i                 (rst_i),
+    
+  
+
+    .interrupt             (interrupt),
+ 
+
+    
+  
+               
+             
+
+     
+  
+    
+                  
+               
+                
+           
+
+
+  
+
+     
+    .I_DAT_I               (I_DAT_I),
+    .I_ACK_I               (I_ACK_I),
+    .I_ERR_I               (I_ERR_I),
+    .I_RTY_I               (I_RTY_I),
+ 
+
+    
+    .D_DAT_I               (D_DAT_I),
+    .D_ACK_I               (D_ACK_I),
+    .D_ERR_I               (D_ERR_I),
+    .D_RTY_I               (D_RTY_I),
+    
+  
+                  
+            
+           
+                 
+                
+ 
+                
+
+
+
+  
+                
+           
+
+
+      
+                
+               
+            
+            
+
+    
+  
+
+    
+    .I_DAT_O               (I_DAT_O),
+    .I_ADR_O               (I_ADR_O),
+    .I_CYC_O               (I_CYC_O),
+    .I_SEL_O               (I_SEL_O),
+    .I_STB_O               (I_STB_O),
+    .I_WE_O                (I_WE_O),
+    .I_CTI_O               (I_CTI_O),
+    .I_LOCK_O              (I_LOCK_O),
+    .I_BTE_O               (I_BTE_O),
+     
+
+    
+    .D_DAT_O               (D_DAT_O),
+    .D_ADR_O               (D_ADR_O),
+    .D_CYC_O               (D_CYC_O),
+    .D_SEL_O               (D_SEL_O),
+    .D_STB_O               (D_STB_O),
+    .D_WE_O                (D_WE_O),
+    .D_CTI_O               (D_CTI_O),
+    .D_LOCK_O              (D_LOCK_O),
+    .D_BTE_O               (D_BTE_O)
+    );
+   
+  		   
+
+  
+    
+                     
+                
+    
+                
+                     
+                
+                      
+                     
+    
+
+        
+   
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+           
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_mc_arithmetic_medium_icache (
+    
+    clk_i,
+    rst_i,
+    stall_d,
+    kill_x,
+  
+    
+    
+
+
+  
+    
+
+
+  
+    
+    
+    
+
+
+    operand_0_d,
+    operand_1_d,
+    
+    result_x,
+  
+    
+
+
+    stall_request_x
+    );
+
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+input stall_d;                                  
+input kill_x;                                   
+  
+                                  
+                                 
+
+
+  
+                                
+
+
+  
+                              
+                             
+                             
+
+
+input [ (32-1):0] operand_0_d;
+input [ (32-1):0] operand_1_d;
+
+
+
+
+
+output [ (32-1):0] result_x;               
+reg    [ (32-1):0] result_x;
+  
+                         
+    
+
+
+output stall_request_x;                         
+wire   stall_request_x;
+
+
+
+
+
+reg [ (32-1):0] p;                         
+reg [ (32-1):0] a;
+reg [ (32-1):0] b;
+  
+  
+
+
+
+reg [ 2:0] state;                 
+reg [5:0] cycles;                               
+
+  
+                               
+                                 
+
+
+
+
+
+
+
+
+assign stall_request_x = state !=  3'b000;
+
+  
+
+      
+
+
+
+  
+
+       
+
+
+
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        cycles <= {6{1'b0}};
+        p <= { 32{1'b0}};
+        a <= { 32{1'b0}};
+        b <= { 32{1'b0}};
+  
+          
+
+
+  
+          
+
+
+        result_x <= { 32{1'b0}};
+        state <=  3'b000;
+    end
+    else
+    begin
+  
+          
+
+
+        case (state)
+         3'b000:
+        begin
+            if (stall_d ==  1'b0)                 
+            begin          
+                cycles <=  32;
+                p <= 32'b0;
+                a <= operand_0_d;
+                b <= operand_1_d;                    
+  
+                   
+                      
+                   
+                      
+
+                    
+  
+                   
+                      
+
+
+  
+                   
+                
+                      
+                      
+                      
+                      
+                      
+                
+                   
+                
+                      
+                      
+                      
+                      
+                      
+                
+
+
+            end            
+        end
+  
+        
+        
+               
+            
+                  
+                   
+            
+             
+            
+                   
+                   
+            
+              
+                   
+            
+                
+                    
+                  
+            
+                
+        
+        
+        
+               
+            
+                  
+                   
+            
+             
+            
+                   
+                   
+            
+              
+                   
+            
+                
+                    
+                  
+            
+                
+        
+
+        
+  
+        
+        
+               
+                    
+               
+               
+              
+                   
+                  
+                
+        
+
+     
+  
+        
+               
+               
+              
+                   
+                  
+                
+        
+        
+               
+               
+              
+                   
+                  
+                
+        
+
+   
+        endcase
+    end
+end 
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
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+ 
+
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+ 
+ 
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+ 
+ 
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+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_cpu_medium_icache (
+    
+    clk_i,
+  
+    
+
+
+    rst_i,
+  
+    
+
+
+  
+   
+   
+   
+   
+   
+   
+
+
+
+    
+  
+
+    interrupt,
+ 
+
+    
+  
+    
+    
+
+     
+  
+    
+    
+     
+    
+    
+
+
+  
+
+    
+    I_DAT_I,
+    I_ACK_I,
+    I_ERR_I,
+    I_RTY_I,
+ 
+
+    
+    D_DAT_I,
+    D_ACK_I,
+    D_ERR_I,
+    D_RTY_I,
+    
+  
+    
+    
+    
+    
+    
+ 
+    
+
+
+
+  
+    
+    
+
+
+      
+    
+    
+    
+    
+
+    
+  
+
+    
+    I_DAT_O,
+    I_ADR_O,
+    I_CYC_O,
+    I_SEL_O,
+    I_STB_O,
+    I_WE_O,
+    I_CTI_O,
+    I_LOCK_O,
+    I_BTE_O,
+ 
+ 
+  
+    
+    
+    
+    
+    
+    
+    
+    
+           
+
+
+		 
+		 
+    
+    D_DAT_O,
+    D_ADR_O,
+    D_CYC_O,
+    D_SEL_O,
+    D_STB_O,
+    D_WE_O,
+    D_CTI_O,
+    D_LOCK_O,
+    D_BTE_O
+
+		 
+    );
+
+
+
+
+
+parameter eba_reset =  32'h00000000;                           
+  
+                            
+
+
+parameter sdb_address =   32'h00000000;
+
+  
+
+parameter icache_associativity =  1;     
+parameter icache_sets =  256;                       
+parameter icache_bytes_per_line =  16;   
+parameter icache_base_address =  32'h0;       
+parameter icache_limit =  32'h7fffffff;                     
+ 
+       
+                         
+     
+         
+                       
+
+
+
+  
+        
+                          
+      
+          
+                        
+
+
+parameter dcache_associativity = 1;    
+parameter dcache_sets = 512;                      
+parameter dcache_bytes_per_line = 16;  
+parameter dcache_base_address = 0;      
+parameter dcache_limit = 0;                    
+ 
+
+
+  
+                          
+
+
+parameter watchpoints = 0;
+ 
+
+  
+                          
+
+
+parameter breakpoints = 0;
+ 
+
+
+  
+
+parameter interrupts =  32;                         
+ 
+   
+
+
+
+
+
+
+
+input clk_i;                                    
+  
+                                   
+
+    
+input rst_i;                                    
+
+  
+
+input [ (32-1):0] interrupt;          
+ 
+
+
+  
+               
+                             
+
+    
+
+   
+                                  
+                               
+                
+  
+
+
+
+  
+
+input [ (32-1):0] I_DAT_I;                 
+input I_ACK_I;                                  
+input I_ERR_I;                                  
+input I_RTY_I;                                  
+ 
+
+
+input [ (32-1):0] D_DAT_I;                 
+input D_ACK_I;                                  
+input D_ERR_I;                                  
+input D_RTY_I;                                  
+
+
+
+
+
+  
+    
+     
+
+
+   
+   
+  
+                   
+     
+                           
+    
+                          
+    
+                 
+     
+                               
+    
+ 
+                               
+    
+
+
+
+
+  
+  
+    
+  
+    
+
+
+
+  
+                               
+   
+       
+     
+           
+    
+           
+    
+
+
+
+  
+
+output [ (32-1):0] I_DAT_O;                
+wire   [ (32-1):0] I_DAT_O;
+output [ (32-1):0] I_ADR_O;                
+wire   [ (32-1):0] I_ADR_O;
+output I_CYC_O;                                 
+wire   I_CYC_O;
+output [ (4-1):0] I_SEL_O;         
+wire   [ (4-1):0] I_SEL_O;
+output I_STB_O;                                 
+wire   I_STB_O;
+output I_WE_O;                                  
+wire   I_WE_O;
+output [ (3-1):0] I_CTI_O;               
+wire   [ (3-1):0] I_CTI_O;
+output I_LOCK_O;                                
+wire   I_LOCK_O;
+output [ (2-1):0] I_BTE_O;               
+wire   [ (2-1):0] I_BTE_O;
+ 
+
+
+output [ (32-1):0] D_DAT_O;                
+wire   [ (32-1):0] D_DAT_O;
+output [ (32-1):0] D_ADR_O;                
+wire   [ (32-1):0] D_ADR_O;
+output D_CYC_O;                                 
+wire   D_CYC_O;
+output [ (4-1):0] D_SEL_O;         
+wire   [ (4-1):0] D_SEL_O;
+output D_STB_O;                                 
+wire   D_STB_O;
+output D_WE_O;                                  
+wire   D_WE_O;
+output [ (3-1):0] D_CTI_O;               
+wire   [ (3-1):0] D_CTI_O;
+output D_LOCK_O;                                
+wire   D_LOCK_O;
+output [ (2-1):0] D_BTE_O;               
+wire   [ (2-1):0] D_BTE_O;
+
+  
+      
+     
+       
+      
+             
+
+
+   
+
+
+
+
+
+
+  
+
+reg valid_a;                                    
+ 
+
+reg valid_f;                                    
+reg valid_d;                                    
+reg valid_x;                                    
+reg valid_m;                                    
+reg valid_w;                                    
+   
+wire q_x;
+wire [ (32-1):0] immediate_d;              
+wire load_d;                                    
+reg load_x;                                     
+reg load_m;
+wire load_q_x;
+wire store_q_x;
+wire q_m;
+wire load_q_m;
+wire store_q_m;
+wire store_d;                                   
+reg store_x;
+reg store_m;
+wire [ 1:0] size_d;                   
+reg [ 1:0] size_x;
+wire branch_d;                                  
+wire branch_predict_d;                          
+wire branch_predict_taken_d;                    
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d;   
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_d;
+wire bi_unconditional;
+wire bi_conditional;
+reg branch_x;                                   
+reg branch_predict_x;
+reg branch_predict_taken_x;
+reg branch_m;
+reg branch_predict_m;
+reg branch_predict_taken_m;
+wire branch_mispredict_taken_m;                 
+wire branch_flushX_m;                           
+wire branch_reg_d;                              
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset_d;            
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_x;             
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_m;
+wire [ 0:0] d_result_sel_0_d; 
+wire [ 1:0] d_result_sel_1_d; 
+
+wire x_result_sel_csr_d;                        
+reg x_result_sel_csr_x;
+  
+ 
+                    
+ 
+
+
+      
+                       
+ 
+
+
+  
+
+wire x_result_sel_sext_d;                       
+reg x_result_sel_sext_x;
+ 
+
+wire x_result_sel_logic_d;                      
+  
+                        
+ 
+
+
+wire x_result_sel_add_d;                        
+reg x_result_sel_add_x;
+wire m_result_sel_compare_d;                    
+reg m_result_sel_compare_x;
+reg m_result_sel_compare_m;
+  
+
+wire m_result_sel_shift_d;                      
+reg m_result_sel_shift_x;
+reg m_result_sel_shift_m;
+ 
+
+wire w_result_sel_load_d;                       
+reg w_result_sel_load_x;
+reg w_result_sel_load_m;
+reg w_result_sel_load_w;
+  
+
+wire w_result_sel_mul_d;                        
+reg w_result_sel_mul_x;
+reg w_result_sel_mul_m;
+reg w_result_sel_mul_w;
+ 
+
+wire x_bypass_enable_d;                         
+reg x_bypass_enable_x;                          
+wire m_bypass_enable_d;                         
+reg m_bypass_enable_x;                          
+reg m_bypass_enable_m;
+wire sign_extend_d;                             
+reg sign_extend_x;
+wire write_enable_d;                            
+reg write_enable_x;
+wire write_enable_q_x;
+reg write_enable_m;
+wire write_enable_q_m;
+reg write_enable_w;
+wire write_enable_q_w;
+wire read_enable_0_d;                           
+wire [ (5-1):0] read_idx_0_d;          
+wire read_enable_1_d;                           
+wire [ (5-1):0] read_idx_1_d;          
+wire [ (5-1):0] write_idx_d;           
+reg [ (5-1):0] write_idx_x;            
+reg [ (5-1):0] write_idx_m;
+reg [ (5-1):0] write_idx_w;
+wire [ (4 -1):0] csr_d;                     
+reg  [ (4 -1):0] csr_x;                  
+wire [ (3-1):0] condition_d;         
+reg [ (3-1):0] condition_x;          
+  
+                                    
+                                     
+
+
+wire scall_d;                                   
+reg scall_x;    
+wire eret_d;                                    
+reg eret_x;
+wire eret_q_x;
+  
+ 
+ 
+
+
+  
+                                     
+ 
+ 
+ 
+ 
+ 
+
+
+
+wire csr_write_enable_d;                        
+reg csr_write_enable_x;
+wire csr_write_enable_q_x;
+  
+       
+
+
+
+  
+                                
+ 
+ 
+  
+
+
+
+reg [ (32-1):0] d_result_0;                
+reg [ (32-1):0] d_result_1;                
+reg [ (32-1):0] x_result;                  
+reg [ (32-1):0] m_result;                  
+reg [ (32-1):0] w_result;                  
+
+reg [ (32-1):0] operand_0_x;               
+reg [ (32-1):0] operand_1_x;               
+reg [ (32-1):0] store_operand_x;           
+reg [ (32-1):0] operand_m;                 
+reg [ (32-1):0] operand_w;                 
+
+
+  
+
+reg [ (32-1):0] reg_data_live_0;          
+reg [ (32-1):0] reg_data_live_1;  
+reg use_buf;                                    
+reg [ (32-1):0] reg_data_buf_0;
+reg [ (32-1):0] reg_data_buf_1;
+ 
+
+  
+
+ 
+     
+
+
+wire [ (32-1):0] reg_data_0;               
+wire [ (32-1):0] reg_data_1;               
+reg [ (32-1):0] bypass_data_0;             
+reg [ (32-1):0] bypass_data_1;             
+wire reg_write_enable_q_w;
+
+reg interlock;                                  
+
+wire stall_a;                                   
+wire stall_f;                                   
+wire stall_d;                                   
+wire stall_x;                                   
+wire stall_m;                                   
+
+
+wire adder_op_d;                                
+reg adder_op_x;                                 
+reg adder_op_x_n;                               
+wire [ (32-1):0] adder_result_x;           
+wire adder_overflow_x;                          
+wire adder_carry_n_x;                           
+
+
+wire [ 3:0] logic_op_d;           
+reg [ 3:0] logic_op_x;            
+wire [ (32-1):0] logic_result_x;           
+
+  
+
+
+wire [ (32-1):0] sextb_result_x;           
+wire [ (32-1):0] sexth_result_x;           
+wire [ (32-1):0] sext_result_x;            
+ 
+
+
+
+  
+
+  
+                                   
+                                     
+
+
+wire direction_d;                               
+reg direction_x;                                        
+wire [ (32-1):0] shifter_result_m;         
+ 
+
+  
+                               
+ 
+                              
+ 
+
+
+  
+           
+
+
+
+
+  
+
+wire [ (32-1):0] multiplier_result_w;      
+ 
+
+  
+                                 
+ 
+
+
+
+
+  
+                                   
+ 
+ 
+ 
+                           
+
+
+
+
+  
+                         
+  
+
+
+
+
+  
+
+wire [ (32-1):0] interrupt_csr_read_data_x;
+ 
+
+wire [ (32-1):0] cfg;                      
+wire [ (32-1):0] cfg2;                     
+  
+                          
+
+
+reg [ (32-1):0] csr_read_data_x;           
+
+
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;                       
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;                       
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;                       
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;                       
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;                       
+  
+                          
+
+
+  
+
+wire [ (32-1):0] instruction_f;     
+ 
+
+
+
+wire [ (32-1):0] instruction_d;     
+  
+
+wire iflush;                                    
+wire icache_stall_request;                      
+wire icache_restart_request;                    
+wire icache_refill_request;                     
+wire icache_refilling;                          
+ 
+
+
+
+  
+                                   
+                                     
+                       
+                     
+                      
+                           
+
+
+wire [ (32-1):0] load_data_w;              
+wire stall_wb_load;                             
+
+
+  
+ 
+          
+          
+
+ 
+                      
+        
+                    
+                           
+  
+ 
+  
+  
+ 
+
+ 
+                                 
+
+
+
+
+
+wire raw_x_0;                                   
+wire raw_x_1;                                   
+wire raw_m_0;                                   
+wire raw_m_1;                                   
+wire raw_w_0;                                   
+wire raw_w_1;                                   
+
+
+wire cmp_zero;                                  
+wire cmp_negative;                              
+wire cmp_overflow;                              
+wire cmp_carry_n;                               
+reg condition_met_x;                            
+reg condition_met_m;
+      
+                             
+
+
+wire branch_taken_m;                            
+
+wire kill_f;                                    
+wire kill_d;                                    
+wire kill_x;                                    
+wire kill_m;                                    
+wire kill_w;                                    
+
+reg [ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8] eba;                 
+  
+                  
+
+
+reg [ (3-1):0] eid_x;                      
+  
+                        
+                        
+
+
+
+  
+ 
+                                      
+
+                                      
+ 
+ 
+                                
+                                 
+                          
+ 
+ 
+ 
+                      
+ 
+ 
+ 
+
+
+wire exception_x;                               
+reg exception_m;
+reg exception_w;
+wire exception_q_w;
+ 
+
+
+  
+  
+                            
+
+ 
+                            
+
+
+
+  
+
+wire interrupt_exception;                       
+ 
+
+  
+                       
+                       
+
+
+  
+     
+   
+            
+                   
+
+
+  
+                   
+
+
+wire system_call_exception;                     
+
+  
+                         
+
+
+
+   
+    
+
+
+     
+  
+                          
+   
+            
+   
+                          
+   
+
+    	      
+    	      
+    	      
+    	      
+    	      
+    	      
+   
+   
+
+
+   
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+lm32_instruction_unit_medium_icache #(
+    .eba_reset              (eba_reset),
+    .associativity          (icache_associativity),
+    .sets                   (icache_sets),
+    .bytes_per_line         (icache_bytes_per_line),
+    .base_address           (icache_base_address),
+    .limit                  (icache_limit)
+  ) instruction_unit (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    
+    .stall_a                (stall_a),
+    .stall_f                (stall_f),
+    .stall_d                (stall_d),
+    .stall_x                (stall_x),
+    .stall_m                (stall_m),
+    .valid_f                (valid_f),
+    .valid_d                (valid_d),
+    .kill_f                 (kill_f),
+    .branch_predict_taken_d (branch_predict_taken_d),
+    .branch_predict_address_d (branch_predict_address_d),
+      
+             
+            
+
+
+    .exception_m            (exception_m),
+    .branch_taken_m         (branch_taken_m),
+    .branch_mispredict_taken_m (branch_mispredict_taken_m),
+    .branch_target_m        (branch_target_m),
+  
+
+    .iflush                 (iflush),
+ 
+
+  
+     
+      
+           
+
+        
+  
+
+    
+    .i_dat_i                (I_DAT_I),
+    .i_ack_i                (I_ACK_I),
+    .i_err_i                (I_ERR_I),
+    .i_rty_i                (I_RTY_I),
+ 
+
+  
+           
+          
+            
+               
+
+
+    
+    
+    .pc_f                   (pc_f),
+    .pc_d                   (pc_d),
+    .pc_x                   (pc_x),
+    .pc_m                   (pc_m),
+    .pc_w                   (pc_w),
+  
+
+    .icache_stall_request   (icache_stall_request),
+    .icache_restart_request (icache_restart_request),
+    .icache_refill_request  (icache_refill_request),
+    .icache_refilling       (icache_refilling),
+ 
+
+  
+
+    
+    .i_dat_o                (I_DAT_O),
+    .i_adr_o                (I_ADR_O),
+    .i_cyc_o                (I_CYC_O),
+    .i_sel_o                (I_SEL_O),
+    .i_stb_o                (I_STB_O),
+    .i_we_o                 (I_WE_O),
+    .i_cti_o                (I_CTI_O),
+    .i_lock_o               (I_LOCK_O),
+    .i_bte_o                (I_BTE_O),
+ 
+ 
+
+  
+    
+    
+    
+
+
+		      	      
+  
+             
+       
+
+
+  
+                
+
+
+  
+
+    .instruction_f          (instruction_f),
+ 
+
+
+		      
+    .instruction_d          (instruction_d)
+
+
+		      
+    );
+
+
+lm32_decoder_medium_icache decoder (
+    
+    .instruction            (instruction_d),
+    
+    .d_result_sel_0         (d_result_sel_0_d),
+    .d_result_sel_1         (d_result_sel_1_d),
+    .x_result_sel_csr       (x_result_sel_csr_d),
+  
+      
+
+
+      
+         
+
+
+  
+
+    .x_result_sel_sext      (x_result_sel_sext_d),
+ 
+    
+    .x_result_sel_logic     (x_result_sel_logic_d),
+  
+          
+
+
+    .x_result_sel_add       (x_result_sel_add_d),
+    .m_result_sel_compare   (m_result_sel_compare_d),
+  
+
+    .m_result_sel_shift     (m_result_sel_shift_d),  
+ 
+    
+    .w_result_sel_load      (w_result_sel_load_d),
+  
+
+    .w_result_sel_mul       (w_result_sel_mul_d),
+ 
+
+    .x_bypass_enable        (x_bypass_enable_d),
+    .m_bypass_enable        (m_bypass_enable_d),
+    .read_enable_0          (read_enable_0_d),
+    .read_idx_0             (read_idx_0_d),
+    .read_enable_1          (read_enable_1_d),
+    .read_idx_1             (read_idx_1_d),
+    .write_enable           (write_enable_d),
+    .write_idx              (write_idx_d),
+    .immediate              (immediate_d),
+    .branch_offset          (branch_offset_d),
+    .load                   (load_d),
+    .store                  (store_d),
+    .size                   (size_d),
+    .sign_extend            (sign_extend_d),
+    .adder_op               (adder_op_d),
+    .logic_op               (logic_op_d),
+  
+
+    .direction              (direction_d),
+ 
+
+  
+                 
+                
+
+
+  
+                   
+
+
+  
+                     
+                    
+
+
+    .branch                 (branch_d),
+    .bi_unconditional       (bi_unconditional),
+    .bi_conditional         (bi_conditional),
+    .branch_reg             (branch_reg_d),
+    .condition              (condition_d),
+  
+               
+
+
+    .scall                  (scall_d),
+    .eret                   (eret_d),
+  
+                       
+
+
+  
+                
+
+
+    .csr_write_enable       (csr_write_enable_d)
+    ); 
+
+
+lm32_load_store_unit_medium_icache #(
+    .associativity          (dcache_associativity),
+    .sets                   (dcache_sets),
+    .bytes_per_line         (dcache_bytes_per_line),
+    .base_address           (dcache_base_address),
+    .limit                  (dcache_limit)
+  ) load_store_unit (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    
+    .stall_a                (stall_a),
+    .stall_x                (stall_x),
+    .stall_m                (stall_m),
+    .kill_x                 (kill_x),
+    .kill_m                 (kill_m),
+    .exception_m            (exception_m),
+    .store_operand_x        (store_operand_x),
+    .load_store_address_x   (adder_result_x),
+    .load_store_address_m   (operand_m),
+    .load_store_address_w   (operand_w[1:0]),
+    .load_x                 (load_x),
+    .store_x                (store_x),
+    .load_q_x               (load_q_x),
+    .store_q_x              (store_q_x),
+    .load_q_m               (load_q_m),
+    .store_q_m              (store_q_m),
+    .sign_extend_x          (sign_extend_x),
+    .size_x                 (size_x),
+  
+                     
+
+
+
+  
+    
+    
+    
+    
+    
+    
+    
+
+
+		     
+    
+    .d_dat_i                (D_DAT_I),
+    .d_ack_i                (D_ACK_I),
+    .d_err_i                (D_ERR_I),
+    .d_rty_i                (D_RTY_I),
+    
+    
+  
+      
+     
+       
+           
+
+    
+    .load_data_w            (load_data_w),
+    .stall_wb_load          (stall_wb_load),
+    
+    .d_dat_o                (D_DAT_O),
+    .d_adr_o                (D_ADR_O),
+    .d_cyc_o                (D_CYC_O),
+    .d_sel_o                (D_SEL_O),
+    .d_stb_o                (D_STB_O),
+    .d_we_o                 (D_WE_O),
+    .d_cti_o                (D_CTI_O),
+    .d_lock_o               (D_LOCK_O),
+    .d_bte_o                (D_BTE_O)
+    );      
+       
+
+lm32_adder adder (
+    
+    .adder_op_x             (adder_op_x),
+    .adder_op_x_n           (adder_op_x_n),
+    .operand_0_x            (operand_0_x),
+    .operand_1_x            (operand_1_x),
+    
+    .adder_result_x         (adder_result_x),
+    .adder_carry_n_x        (adder_carry_n_x),
+    .adder_overflow_x       (adder_overflow_x)
+    );
+
+
+lm32_logic_op logic_op (
+    
+    .logic_op_x             (logic_op_x),
+    .operand_0_x            (operand_0_x),
+
+    .operand_1_x            (operand_1_x),
+    
+    .logic_result_x         (logic_result_x)
+    );
+              
+  
+
+
+lm32_shifter shifter (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    .stall_x                (stall_x),
+    .direction_x            (direction_x),
+    .sign_extend_x          (sign_extend_x),
+    .operand_0_x            (operand_0_x),
+    .operand_1_x            (operand_1_x),
+    
+    .shifter_result_m       (shifter_result_m)
+    );
+ 
+
+
+  
+
+
+lm32_multiplier multiplier (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    .stall_x                (stall_x),
+    .stall_m                (stall_m),
+    .operand_0              (d_result_0),
+    .operand_1              (d_result_1),
+    
+    .result                 (multiplier_result_w)    
+    );
+ 
+
+
+  
+
+  
+    
+                      
+                      
+                    
+                     
+                   
+                   
+                  
+
+         
+                 
+
+ 
+               
+              
+              
+    
+                
+                
+    
+                   
+                   
+           
+
+            
+    
+
+
+              
+  
+
+
+lm32_interrupt_medium_icache interrupt_unit (
+    
+    .clk_i                  (clk_i), 
+    .rst_i                  (rst_i),
+    
+    .interrupt              (interrupt),
+    
+    .stall_x                (stall_x),
+  
+         
+            
+
+
+    .exception              (exception_q_w), 
+ 
+
+    .eret_q_x               (eret_q_x),
+  
+                   
+
+
+    .csr                    (csr_x),
+    .csr_write_data         (operand_1_x),
+    .csr_write_enable       (csr_write_enable_q_x),
+    
+    .interrupt_exception    (interrupt_exception),
+    
+    .csr_read_data          (interrupt_csr_read_data_x)
+    );
+ 
+
+
+  
+      
+      
+        
+   
+
+
+
+
+  
+
+  
+    
+                      
+                      
+    
+                   
+                
+                 
+            
+    
+ 
+                        
+             
+           
+                    
+
+ 
+             
+       
+
+ 
+                
+    
+    
+    
+ 
+          
+          
+
+ 
+      
+        
+                   
+           
+          
+            
+               
+
+ 
+                 
+                 
+
+    
+                 
+            
+    
+
+
+
+  
+
+ 
+                
+                
+    
+    
+                       
+                      
+                       
+                     
+                    
+       
+         
+             
+                      
+  
+	       
+      
+        
+                   
+	      
+	       
+      
+        
+                   
+	      
+
+ 
+                   
+                   
+                    
+                
+                        
+ 
+      
+
+
+    
+ 
+                      
+
+                      
+                   
+                   
+    
+
+
+
+
+
+  
+
+   
+           
+            
+          
+            
+
+
+             
+              
+    
+
+   wire [31:0] regfile_data_0, regfile_data_1;
+   reg [31:0]  w_result_d;
+   reg 	       regfile_raw_0, regfile_raw_0_nxt;
+   reg 	       regfile_raw_1, regfile_raw_1_nxt;
+   
+   
+             
+          
+
+   always @(reg_write_enable_q_w or write_idx_w or instruction_f)
+     begin
+	if (reg_write_enable_q_w
+	    && (write_idx_w == instruction_f[25:21]))
+	  regfile_raw_0_nxt = 1'b1;
+	else
+	  regfile_raw_0_nxt = 1'b0;
+	
+	if (reg_write_enable_q_w
+	    && (write_idx_w == instruction_f[20:16]))
+	  regfile_raw_1_nxt = 1'b1;
+	else
+	  regfile_raw_1_nxt = 1'b0;
+     end
+   
+   
+           
+           
+       
+
+   always @(regfile_raw_0 or w_result_d or regfile_data_0)
+     if (regfile_raw_0)
+       reg_data_live_0 = w_result_d;
+     else
+       reg_data_live_0 = regfile_data_0;
+   
+   
+           
+           
+       
+
+   always @(regfile_raw_1 or w_result_d or regfile_data_1)
+     if (regfile_raw_1)
+       reg_data_live_1 = w_result_d;
+     else
+       reg_data_live_1 = regfile_data_1;
+   
+   
+     
+
+   always @(posedge clk_i  )
+     if (rst_i ==  1'b1)
+       begin
+	  regfile_raw_0 <= 1'b0;
+	  regfile_raw_1 <= 1'b0;
+	  w_result_d <= 32'b0;
+       end
+     else
+       begin
+	  regfile_raw_0 <= regfile_raw_0_nxt;
+	  regfile_raw_1 <= regfile_raw_1_nxt;
+	  w_result_d <= w_result;
+       end
+   
+   
+      
+
+   
+   lm32_dp_ram
+     #(
+       
+       .addr_depth(1<<5),
+       .addr_width(5),
+       .data_width(32)
+       )
+   reg_0
+     (
+      
+      .clk_i	(clk_i),
+      .rst_i	(rst_i), 
+      .we_i	(reg_write_enable_q_w),
+      .wdata_i	(w_result),
+      .waddr_i	(write_idx_w),
+      .raddr_i	(instruction_f[25:21]),
+      
+      .rdata_o	(regfile_data_0)
+      );
+
+   lm32_dp_ram
+     #(
+       .addr_depth(1<<5),
+       .addr_width(5),
+       .data_width(32)
+       )
+   reg_1
+     (
+      
+      .clk_i	(clk_i),
+      .rst_i	(rst_i), 
+      .we_i	(reg_write_enable_q_w),
+      .wdata_i	(w_result),
+      .waddr_i	(write_idx_w),
+      .raddr_i	(instruction_f[20:16]),
+      
+      .rdata_o	(regfile_data_1)
+      );
+ 
+
+
+  
+   
+     
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+   
+     
+      
+      
+      
+      
+      
+      
+      
+        
+      
+       
+      
+      
+      
+   
+   
+     
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+   
+     
+      
+      
+      
+      
+      
+      
+      
+        
+      
+       
+      
+      
+      
+
+
+
+
+
+
+
+
+  
+
+
+assign reg_data_0 = use_buf ? reg_data_buf_0 : reg_data_live_0;
+assign reg_data_1 = use_buf ? reg_data_buf_1 : reg_data_live_1;
+ 
+
+  
+
+ 
+
+   
+   
+
+
+
+
+assign raw_x_0 = (write_idx_x == read_idx_0_d) && (write_enable_q_x ==  1'b1);
+assign raw_m_0 = (write_idx_m == read_idx_0_d) && (write_enable_q_m ==  1'b1);
+assign raw_w_0 = (write_idx_w == read_idx_0_d) && (write_enable_q_w ==  1'b1);
+assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x ==  1'b1);
+assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m ==  1'b1);
+assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w ==  1'b1);
+
+
+always @(*)
+begin
+    if (   (   (x_bypass_enable_x ==  1'b0)
+            && (   ((read_enable_0_d ==  1'b1) && (raw_x_0 ==  1'b1))
+                || ((read_enable_1_d ==  1'b1) && (raw_x_1 ==  1'b1))
+               )
+           )
+        || (   (m_bypass_enable_m ==  1'b0)
+            && (   ((read_enable_0_d ==  1'b1) && (raw_m_0 ==  1'b1))
+                || ((read_enable_1_d ==  1'b1) && (raw_m_1 ==  1'b1))
+               )
+           )
+       )
+        interlock =  1'b1;
+    else
+        interlock =  1'b0;
+end
+
+
+always @(*)
+begin
+    if (raw_x_0 ==  1'b1)        
+        bypass_data_0 = x_result;
+    else if (raw_m_0 ==  1'b1)
+        bypass_data_0 = m_result;
+    else if (raw_w_0 ==  1'b1)
+        bypass_data_0 = w_result;
+    else
+        bypass_data_0 = reg_data_0;
+end
+
+
+always @(*)
+begin
+    if (raw_x_1 ==  1'b1)
+        bypass_data_1 = x_result;
+    else if (raw_m_1 ==  1'b1)
+        bypass_data_1 = m_result;
+    else if (raw_w_1 ==  1'b1)
+        bypass_data_1 = w_result;
+    else
+        bypass_data_1 = reg_data_1;
+end
+
+   
+          
+       
+       
+     
+
+   assign branch_predict_d = bi_unconditional | bi_conditional;
+   assign branch_predict_taken_d = bi_unconditional ? 1'b1 : (bi_conditional ? instruction_d[15] : 1'b0);
+   
+   
+   assign branch_target_d = pc_d + branch_offset_d;
+
+   
+   
+   
+   assign branch_predict_address_d = branch_predict_taken_d ? branch_target_d : pc_f;
+
+
+always @(*)
+begin
+    d_result_0 = d_result_sel_0_d[0] ? {pc_f, 2'b00} : bypass_data_0; 
+    case (d_result_sel_1_d)
+     2'b00:      d_result_1 = { 32{1'b0}};
+     2'b01:     d_result_1 = bypass_data_1;
+     2'b10: d_result_1 = immediate_d;
+    default:                        d_result_1 = { 32{1'bx}};
+    endcase
+end
+
+      
+
+   
+   
+
+
+
+  
+
+
+assign sextb_result_x = {{24{operand_0_x[7]}}, operand_0_x[7:0]};
+assign sexth_result_x = {{16{operand_0_x[15]}}, operand_0_x[15:0]};
+assign sext_result_x = size_x ==  2'b00 ? sextb_result_x : sexth_result_x;
+ 
+
+
+  
+
+      
+
+
+
+
+assign cmp_zero = operand_0_x == operand_1_x;
+assign cmp_negative = adder_result_x[ 32-1];
+assign cmp_overflow = adder_overflow_x;
+assign cmp_carry_n = adder_carry_n_x;
+always @(*)
+begin
+    case (condition_x)
+     3'b000:   condition_met_x =  1'b1;
+     3'b110:   condition_met_x =  1'b1;
+     3'b001:    condition_met_x = cmp_zero;
+     3'b111:   condition_met_x = !cmp_zero;
+     3'b010:    condition_met_x = !cmp_zero && (cmp_negative == cmp_overflow);
+     3'b101:   condition_met_x = cmp_carry_n && !cmp_zero;
+     3'b011:   condition_met_x = cmp_negative == cmp_overflow;
+     3'b100:  condition_met_x = cmp_carry_n;
+    default:              condition_met_x = 1'bx;
+    endcase 
+end
+
+
+always @(*)
+begin
+    x_result =   x_result_sel_add_x ? adder_result_x 
+               : x_result_sel_csr_x ? csr_read_data_x
+  
+
+               : x_result_sel_sext_x ? sext_result_x
+ 
+
+  
+                  
+
+
+  
+                  
+
+
+  
+                  
+
+
+               : logic_result_x;
+end
+
+
+always @(*)
+begin
+    m_result =   m_result_sel_compare_m ? {{ 32-1{1'b0}}, condition_met_m}
+  
+
+               : m_result_sel_shift_m ? shifter_result_m
+ 
+
+               : operand_m; 
+end
+
+
+always @(*)
+begin
+    w_result =    w_result_sel_load_w ? load_data_w
+  
+
+                : w_result_sel_mul_w ? multiplier_result_w
+ 
+
+                : operand_w;
+end
+
+      
+
+          
+                                
+                                     
+                                 
+                                 
+                              
+
+
+
+
+assign branch_taken_m =      (stall_m ==  1'b0) 
+                          && (   (   (branch_m ==  1'b1) 
+                                  && (valid_m ==  1'b1)
+                                  && (   (   (condition_met_m ==  1'b1)
+					  && (branch_predict_taken_m ==  1'b0)
+					 )
+				      || (   (condition_met_m ==  1'b0)
+					  && (branch_predict_m ==  1'b1)
+					  && (branch_predict_taken_m ==  1'b1)
+					 )
+				     )
+                                 ) 
+                              || (exception_m ==  1'b1)
+                             );
+
+
+assign branch_mispredict_taken_m =    (condition_met_m ==  1'b0)
+                                   && (branch_predict_m ==  1'b1)
+	   			   && (branch_predict_taken_m ==  1'b1);
+   
+
+assign branch_flushX_m =    (stall_m ==  1'b0)
+                         && (   (   (branch_m ==  1'b1) 
+                                 && (valid_m ==  1'b1)
+			         && (   (condition_met_m ==  1'b1)
+				     || (   (condition_met_m ==  1'b0)
+					 && (branch_predict_m ==  1'b1)
+					 && (branch_predict_taken_m ==  1'b1)
+					)
+				    )
+			        )
+			     || (exception_m ==  1'b1)
+			    );
+
+
+assign kill_f =    (   (valid_d ==  1'b1)
+                    && (branch_predict_taken_d ==  1'b1)
+		   )
+                || (branch_taken_m ==  1'b1) 
+      
+                   
+
+
+  
+
+                || (icache_refill_request ==  1'b1) 
+ 
+
+                  
+                   
+
+
+                ;
+assign kill_d =    (branch_taken_m ==  1'b1) 
+      
+                   
+
+
+  
+
+                || (icache_refill_request ==  1'b1)     
+ 
+                
+                  
+                   
+
+
+                ;
+assign kill_x =    (branch_flushX_m ==  1'b1) 
+                  
+                   
+
+
+                ;
+assign kill_m =     1'b0
+                  
+                   
+
+
+                ;                
+assign kill_w =     1'b0
+                  
+                   
+
+                
+                ;
+
+
+
+  
+              
+				         
+				     
+				     
+				 
+ 
+                                 
+
+                              
+
+
+
+  
+     
+
+
+
+  
+        
+                                             
+                                         
+     
+
+
+
+  
+     
+
+
+
+assign system_call_exception = (   (scall_x ==  1'b1)
+  
+                                   
+
+
+			       );
+
+  
+      
+                            
+                         
+
+     
+ 
+                               
+
+ 
+                               
+                               
+
+ 
+                               
+
+ 
+                                  
+ 
+                                   
+                            
+ 
+ 				   
+				   
+
+                               
+
+                            
+
+         
+
+
+assign exception_x =           (system_call_exception ==  1'b1)
+  
+                               
+                               
+
+
+  
+                               
+
+
+  
+
+                            || (   (interrupt_exception ==  1'b1)
+  
+                                   
+
+                            
+  
+ 				   
+				   
+
+
+                               )
+ 
+
+                            ;
+ 
+
+
+  
+ 
+
+ 
+  
+      
+   
+      
+
+
+
+
+always @(*)
+begin
+  
+ 
+       
+          
+    
+     
+ 
+            
+          
+    
+
+            
+          
+    
+
+
+  
+            
+          
+    
+            
+          
+    
+
+
+  
+            
+          
+     
+
+
+  
+            
+          
+    
+
+
+  
+
+         if (   (interrupt_exception ==  1'b1)
+  
+                
+
+                            
+            )
+        eid_x =  3'h6;
+    else
+ 
+
+        eid_x =  3'h7;
+end
+
+
+
+assign stall_a = (stall_f ==  1'b1);
+                
+assign stall_f = (stall_d ==  1'b1);
+                
+assign stall_d =   (stall_x ==  1'b1) 
+                || (   (interlock ==  1'b1)
+                    && (kill_d ==  1'b0)
+                   ) 
+		|| (   (   (eret_d ==  1'b1)
+			|| (scall_d ==  1'b1)
+  
+			   
+
+
+		       )
+		    && (   (load_q_x ==  1'b1)
+			|| (load_q_m ==  1'b1)
+			|| (store_q_x ==  1'b1)
+			|| (store_q_m ==  1'b1)
+			|| (D_CYC_O ==  1'b1)
+		       )
+                    && (kill_d ==  1'b0)
+		   )
+  
+		         
+			   
+		       
+		          
+			   
+			   
+			   
+			   
+		       
+                       
+		   
+
+                   
+                || (   (csr_write_enable_d ==  1'b1)
+                    && (load_q_x ==  1'b1)
+                   )                      
+  
+                 
+                 
+                       
+		           
+			 
+			
+		    
+
+	
+                ;
+                
+assign stall_x =    (stall_m ==  1'b1)
+  
+                       
+                        
+                     
+
+
+
+	    
+                 ;
+
+assign stall_m =    (stall_wb_load ==  1'b1)
+  
+                    
+
+
+                 || (   (D_CYC_O ==  1'b1)
+                     && (   (store_m ==  1'b1)
+		         
+          
+          
+
+		  
+	 
+	
+
+          
+           
+          
+       
+
+  
+
+		         || ((store_x ==  1'b1) && (interrupt_exception ==  1'b1))
+ 
+
+                         || (load_m ==  1'b1)
+                         || (load_x ==  1'b1)
+                        ) 
+                    ) 
+ 
+                 
+  
+                         
+
+                                    
+  
+
+                 || (icache_stall_request ==  1'b1)     
+                 || ((I_CYC_O ==  1'b1) && ((branch_m ==  1'b1) || (exception_m ==  1'b1))) 
+ 
+ 
+                                
+
+
+                               
+  
+                                  
+                        
+                    
+
+
+  
+                  
+   
+
+                 ;      
+
+
+
+
+  
+         
+
+
+  
+         
+         
+
+
+  
+         
+
+
+  
+         
+         
+
+
+assign q_x = (valid_x ==  1'b1) && (kill_x ==  1'b0);
+assign csr_write_enable_q_x = (csr_write_enable_x ==  1'b1) && (q_x ==  1'b1);
+assign eret_q_x = (eret_x ==  1'b1) && (q_x ==  1'b1);
+  
+         
+
+
+assign load_q_x = (load_x ==  1'b1) 
+               && (q_x ==  1'b1)
+  
+                  
+
+
+                  ;
+assign store_q_x = (store_x ==  1'b1) 
+               && (q_x ==  1'b1)
+  
+                  
+
+
+                  ;
+  
+         
+
+                              
+assign q_m = (valid_m ==  1'b1) && (kill_m ==  1'b0) && (exception_m ==  1'b0);
+assign load_q_m = (load_m ==  1'b1) && (q_m ==  1'b1);
+assign store_q_m = (store_m ==  1'b1) && (q_m ==  1'b1);
+  
+         
+                 
+
+
+assign exception_q_w = ((exception_w ==  1'b1) && (valid_w ==  1'b1));        
+ 
+
+
+assign write_enable_q_x = (write_enable_x ==  1'b1) && (valid_x ==  1'b1) && (branch_flushX_m ==  1'b0);
+assign write_enable_q_m = (write_enable_m ==  1'b1) && (valid_m ==  1'b1);
+assign write_enable_q_w = (write_enable_w ==  1'b1) && (valid_w ==  1'b1);
+
+assign reg_write_enable_q_w = (write_enable_w ==  1'b1) && (kill_w ==  1'b0) && (valid_w ==  1'b1);
+
+
+assign cfg = {
+               6'h02,
+              watchpoints[3:0],
+              breakpoints[3:0],
+              interrupts[5:0],
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+ 
+               1'b1
+ 
+              
+
+
+              };
+
+assign cfg2 = {
+		     30'b0,
+  
+		     
+
+
+		      1'b0,
+ 
+
+  
+		     
+
+
+		      1'b0
+ 
+
+		     };
+   
+
+  
+
+assign iflush = (   (csr_write_enable_d ==  1'b1) 
+                 && (csr_d ==  4 'h3)
+                 && (stall_d ==  1'b0)
+                 && (kill_d ==  1'b0)
+                 && (valid_d ==  1'b1))
+
+  
+             
+                     
+		    
+
+
+		 ;
+ 
+ 
+  
+         
+                      
+
+ 
+               
+                       
+		      
+
+		   
+
+ 
+
+
+assign csr_d = read_idx_0_d[ (4 -1):0];
+
+
+always @(*)
+begin
+    case (csr_x)
+  
+
+     4 'h0,
+     4 'h1,
+     4 'h2:   csr_read_data_x = interrupt_csr_read_data_x;  
+ 
+
+  
+         
+
+
+     4 'h6:  csr_read_data_x = cfg;
+     4 'h7:  csr_read_data_x = {eba, 8'h00};
+  
+        
+
+
+  
+          
+        
+
+
+     4 'ha: csr_read_data_x = cfg2;
+     4 'hb:  csr_read_data_x = sdb_address;
+  
+        
+
+
+      
+      
+    default:        csr_read_data_x = { 32{1'bx}};
+    endcase
+end
+
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        eba <= eba_reset[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+    else
+    begin
+        if ((csr_write_enable_q_x ==  1'b1) && (csr_x ==  4 'h7) && (stall_x ==  1'b0))
+            eba <= operand_1_x[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+  
+  
+              
+           
+ 
+  
+              
+           
+ 	 
+
+
+    end
+end
+
+  
+
+   
+
+       
+          
+    
+    
+                   
+              
+  
+   
+              
+           
+  
+   
+              
+           
+         
+ 
+    
+
+
+
+
+
+  
+   
+
+       
+          
+    
+            
+
+
+
+
+  
+
+   
+
+       
+          
+    
+    
+        
+                
+             
+	     
+	
+        
+               
+              
+    
+
+
+
+ 
+
+
+  
+
+  
+ 
+
+           
+           
+       
+          
+            
+                 
+             
+          
+     
+            
+ 
+
+
+always @(*)
+begin
+    if (icache_refill_request ==  1'b1) 
+        valid_a =  1'b0;
+    else if (icache_restart_request ==  1'b1) 
+        valid_a =  1'b1;
+    else 
+        valid_a = !icache_refilling;
+end 
+ 
+
+ 
+ 
+ 
+
+        
+          
+         
+          
+     
+          
+ 
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        valid_f <=  1'b0;
+        valid_d <=  1'b0;
+        valid_x <=  1'b0;
+        valid_m <=  1'b0;
+        valid_w <=  1'b0;
+    end
+    else
+    begin    
+        if ((kill_f ==  1'b1) || (stall_a ==  1'b0))
+  
+
+            valid_f <= valid_a;    
+ 
+              
+
+            
+        else if (stall_f ==  1'b0)
+            valid_f <=  1'b0;            
+
+        if (kill_d ==  1'b1)
+            valid_d <=  1'b0;
+        else if (stall_f ==  1'b0)
+            valid_d <= valid_f & !kill_f;
+        else if (stall_d ==  1'b0)
+            valid_d <=  1'b0;
+       
+        if (stall_d ==  1'b0)
+            valid_x <= valid_d & !kill_d;
+        else if (kill_x ==  1'b1)
+            valid_x <=  1'b0;
+        else if (stall_x ==  1'b0)
+            valid_x <=  1'b0;
+
+        if (kill_m ==  1'b1)
+            valid_m <=  1'b0;
+        else if (stall_x ==  1'b0)
+            valid_m <= valid_x & !kill_x;
+        else if (stall_m ==  1'b0)
+            valid_m <=  1'b0;
+
+        if (stall_m ==  1'b0)
+            valid_w <= valid_m & !kill_m;
+        else 
+            valid_w <=  1'b0;        
+    end
+end
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+  
+                 
+
+        
+        operand_0_x <= { 32{1'b0}};
+        operand_1_x <= { 32{1'b0}};
+        store_operand_x <= { 32{1'b0}};
+        branch_target_x <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};        
+        x_result_sel_csr_x <=  1'b0;
+  
+          
+
+
+      
+          
+
+
+  
+
+        x_result_sel_sext_x <=  1'b0;
+ 
+    
+  
+          
+
+
+        x_result_sel_add_x <=  1'b0;
+        m_result_sel_compare_x <=  1'b0;
+  
+
+        m_result_sel_shift_x <=  1'b0;
+ 
+    
+        w_result_sel_load_x <=  1'b0;
+  
+
+        w_result_sel_mul_x <=  1'b0;
+ 
+
+        x_bypass_enable_x <=  1'b0;
+        m_bypass_enable_x <=  1'b0;
+        write_enable_x <=  1'b0;
+        write_idx_x <= { 5{1'b0}};
+        csr_x <= { 4 {1'b0}};
+        load_x <=  1'b0;
+        store_x <=  1'b0;
+        size_x <= { 2{1'b0}};
+        sign_extend_x <=  1'b0;
+        adder_op_x <=  1'b0;
+        adder_op_x_n <=  1'b0;
+        logic_op_x <= 4'h0;
+  
+
+        direction_x <=  1'b0;
+ 
+
+  
+          
+
+
+
+        branch_x <=  1'b0;
+        branch_predict_x <=  1'b0;
+        branch_predict_taken_x <=  1'b0;
+        condition_x <=  3'b000;
+  
+          
+
+
+        scall_x <=  1'b0;
+        eret_x <=  1'b0;
+  
+          
+
+
+  
+          
+          
+
+
+        csr_write_enable_x <=  1'b0;
+        operand_m <= { 32{1'b0}};
+        branch_target_m <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+        m_result_sel_compare_m <=  1'b0;
+  
+
+        m_result_sel_shift_m <=  1'b0;
+ 
+    
+        w_result_sel_load_m <=  1'b0;
+  
+
+        w_result_sel_mul_m <=  1'b0;
+ 
+
+        m_bypass_enable_m <=  1'b0;
+        branch_m <=  1'b0;
+        branch_predict_m <=  1'b0;
+	branch_predict_taken_m <=  1'b0;
+        exception_m <=  1'b0;
+        load_m <=  1'b0;
+        store_m <=  1'b0;
+        write_enable_m <=  1'b0;            
+        write_idx_m <= { 5{1'b0}};
+        condition_met_m <=  1'b0;
+  
+          
+
+
+  
+          
+                  
+
+
+        operand_w <= { 32{1'b0}};        
+        w_result_sel_load_w <=  1'b0;
+  
+
+        w_result_sel_mul_w <=  1'b0;
+ 
+
+        write_idx_w <= { 5{1'b0}};        
+        write_enable_w <=  1'b0;
+  
+          
+                  
+
+
+        exception_w <=  1'b0;
+ 
+
+  
+          
+
+
+    end
+    else
+    begin
+        
+       
+        if (stall_x ==  1'b0)
+        begin
+  
+                     
+
+        
+            operand_0_x <= d_result_0;
+            operand_1_x <= d_result_1;
+            store_operand_x <= bypass_data_1;
+            branch_target_x <= branch_reg_d ==  1'b1 ? bypass_data_0[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] : branch_target_d;            
+            x_result_sel_csr_x <= x_result_sel_csr_d;
+  
+              
+
+
+      
+              
+
+
+  
+
+            x_result_sel_sext_x <= x_result_sel_sext_d;
+ 
+    
+  
+              
+
+
+            x_result_sel_add_x <= x_result_sel_add_d;
+            m_result_sel_compare_x <= m_result_sel_compare_d;
+  
+
+            m_result_sel_shift_x <= m_result_sel_shift_d;
+ 
+    
+            w_result_sel_load_x <= w_result_sel_load_d;
+  
+
+            w_result_sel_mul_x <= w_result_sel_mul_d;
+ 
+
+            x_bypass_enable_x <= x_bypass_enable_d;
+            m_bypass_enable_x <= m_bypass_enable_d;
+            load_x <= load_d;
+            store_x <= store_d;
+            branch_x <= branch_d;
+	    branch_predict_x <= branch_predict_d;
+	    branch_predict_taken_x <= branch_predict_taken_d;
+	    write_idx_x <= write_idx_d;
+            csr_x <= csr_d;
+            size_x <= size_d;
+            sign_extend_x <= sign_extend_d;
+            adder_op_x <= adder_op_d;
+            adder_op_x_n <= ~adder_op_d;
+            logic_op_x <= logic_op_d;
+  
+
+            direction_x <= direction_d;
+ 
+
+  
+              
+
+
+            condition_x <= condition_d;
+            csr_write_enable_x <= csr_write_enable_d;
+  
+              
+
+
+            scall_x <= scall_d;
+  
+              
+
+
+            eret_x <= eret_d;
+  
+               
+
+
+            write_enable_x <= write_enable_d;
+        end
+        
+        
+
+        if (stall_m ==  1'b0)
+        begin
+            operand_m <= x_result;
+            m_result_sel_compare_m <= m_result_sel_compare_x;
+  
+
+            m_result_sel_shift_m <= m_result_sel_shift_x;
+ 
+    
+            if (exception_x ==  1'b1)
+            begin
+                w_result_sel_load_m <=  1'b0;
+  
+
+                w_result_sel_mul_m <=  1'b0;
+ 
+
+            end
+            else
+            begin
+                w_result_sel_load_m <= w_result_sel_load_x;
+  
+
+                w_result_sel_mul_m <= w_result_sel_mul_x;
+ 
+
+            end
+            m_bypass_enable_m <= m_bypass_enable_x;
+            load_m <= load_x;
+            store_m <= store_x;
+      
+                
+
+
+            branch_m <= branch_x;
+	    branch_predict_m <= branch_predict_x;
+	    branch_predict_taken_m <= branch_predict_taken_x;
+ 
+
+  
+	   
+	   
+	   
+	   
+	   
+                
+                  
+                
+                  
+             
+                  
+
+
+            if (exception_x ==  1'b1)
+                write_idx_m <=  5'd30;
+            else 
+                write_idx_m <= write_idx_x;
+ 
+
+            condition_met_m <= condition_met_x;
+  
+	      
+	        
+		     
+		        
+	           
+	     
+	           
+	   
+	       
+
+
+            branch_target_m <= exception_x ==  1'b1 ? {eba, eid_x, {3{1'b0}}} : branch_target_x;
+ 
+
+  
+              
+              
+
+
+  
+              
+
+
+  
+ 
+               
+
+
+
+            write_enable_m <= exception_x ==  1'b1 ?  1'b1 : write_enable_x;            
+  
+              
+                      
+
+
+        end
+        
+        
+        if (stall_m ==  1'b0)
+        begin
+            if ((exception_x ==  1'b1) && (q_x ==  1'b1) && (stall_x ==  1'b0))
+                exception_m <=  1'b1;
+            else 
+                exception_m <=  1'b0;
+  
+	           
+ 
+					    
+
+					 
+
+
+	end
+                
+        
+  
+                      
+
+
+        operand_w <= exception_m ==  1'b1 ? {pc_m, 2'b00} : m_result;
+ 
+
+        w_result_sel_load_w <= w_result_sel_load_m;
+  
+
+        w_result_sel_mul_w <= w_result_sel_mul_m;
+ 
+
+        write_idx_w <= write_idx_m;
+  
+          
+          
+ 
+           
+
+
+
+        write_enable_w <= write_enable_m;
+  
+          
+          
+
+
+        exception_w <= exception_m;
+ 
+
+  
+              
+                   
+                   
+               
+	   
+            
+
+
+    end
+end
+
+  
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        use_buf <=  1'b0;
+        reg_data_buf_0 <= { 32{1'b0}};
+        reg_data_buf_1 <= { 32{1'b0}};
+    end
+    else
+    begin
+        if (stall_d ==  1'b0)
+            use_buf <=  1'b0;
+        else if (use_buf ==  1'b0)
+        begin        
+            reg_data_buf_0 <= reg_data_live_0;
+            reg_data_buf_1 <= reg_data_live_1;
+            use_buf <=  1'b1;
+        end        
+        if (reg_write_enable_q_w ==  1'b1)
+        begin
+            if (write_idx_w == read_idx_0_d)
+                reg_data_buf_0 <= w_result;
+            if (write_idx_w == read_idx_1_d)
+                reg_data_buf_1 <= w_result;
+        end
+    end
+end
+ 
+
+
+  
+
+ 
+
+   
+
+        
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+        
+     
+           
+            
+        
+
+
+
+
+  
+
+   
+
+       
+    
+          
+          
+          
+          
+          
+ 
+          
+
+          
+    
+    
+    
+          
+        
+ 
+               
+
+           
+
+                
+              
+              
+              
+              
+        
+        
+              
+        
+             
+        
+            
+                 
+            
+                
+                  
+                  
+            
+            
+              
+            
+              
+ 
+              
+
+        
+        
+        
+              
+ 
+              
+
+        
+    
+
+
+
+      
+
+
+
+
+
+        
+endmodule 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_load_store_unit_medium_icache 
+(
+    
+    clk_i,
+    rst_i,
+ 
+    stall_a,
+    stall_x,
+    stall_m,
+    kill_x,
+    kill_m,
+    exception_m,
+    store_operand_x,
+    load_store_address_x,
+    load_store_address_m,
+    load_store_address_w,
+    load_x,
+    store_x,
+    load_q_x,
+    store_q_x,
+    load_q_m,
+    store_q_m,
+    sign_extend_x,
+    size_x,
+  
+    
+
+
+    
+    d_dat_i,
+    d_ack_i,
+    d_err_i,
+    d_rty_i,
+    
+    
+  
+    
+    
+    
+    
+
+    
+  
+    
+    
+    
+    
+    
+    
+    
+
+			     
+    load_data_w,
+    stall_wb_load,
+    
+    d_dat_o,
+    d_adr_o,
+    d_cyc_o,
+    d_sel_o,
+    d_stb_o,
+    d_we_o,
+    d_cti_o,
+    d_lock_o,
+    d_bte_o
+    );
+
+
+
+
+
+parameter associativity = 1;                            
+parameter sets = 512;                                   
+parameter bytes_per_line = 16;                          
+parameter base_address = 0;                             
+parameter limit = 0;                                    
+
+
+localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
+localparam addr_offset_lsb = 2;
+localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
+
+
+
+
+
+   input clk_i;                                            
+   
+input rst_i;                                            
+
+input stall_a;                                          
+input stall_x;                                          
+input stall_m;                                          
+input kill_x;                                           
+input kill_m;                                           
+input exception_m;                                      
+
+input [ (32-1):0] store_operand_x;                 
+input [ (32-1):0] load_store_address_x;            
+input [ (32-1):0] load_store_address_m;            
+input [1:0] load_store_address_w;                       
+input load_x;                                           
+input store_x;                                          
+input load_q_x;                                         
+input store_q_x;                                        
+input load_q_m;                                         
+input store_q_m;                                        
+input sign_extend_x;                                    
+input [ 1:0] size_x;                          
+
+  
+                                            
+
+
+
+     
+     
+     
+      
+      
+            
+    	 
+   
+
+
+
+   reg 		 [31:0] iram_dat_d0;
+   reg 		 iram_en_d0;
+   wire 	 iram_en;
+   wire [31:0] 	 iram_data;
+   
+   
+   
+input [ (32-1):0] d_dat_i;                         
+input d_ack_i;                                          
+input d_err_i;                                          
+input d_rty_i;                                          
+
+
+
+
+
+  
+                            
+   
+                           
+   
+                             
+   
+ 
+   
+
+
+
+   
+output [ (32-1):0] load_data_w;                    
+reg    [ (32-1):0] load_data_w;
+output stall_wb_load;                                   
+reg    stall_wb_load;
+
+output [ (32-1):0] d_dat_o;                        
+reg    [ (32-1):0] d_dat_o;
+output [ (32-1):0] d_adr_o;                        
+reg    [ (32-1):0] d_adr_o;
+output d_cyc_o;                                         
+reg    d_cyc_o;
+output [ (4-1):0] d_sel_o;                 
+reg    [ (4-1):0] d_sel_o;
+output d_stb_o;                                         
+reg    d_stb_o; 
+output d_we_o;                                          
+reg    d_we_o;
+output [ (3-1):0] d_cti_o;                       
+reg    [ (3-1):0] d_cti_o;
+output d_lock_o;                                        
+reg    d_lock_o;
+output [ (2-1):0] d_bte_o;                       
+wire   [ (2-1):0] d_bte_o;
+
+
+
+
+
+
+reg [ 1:0] size_m;
+reg [ 1:0] size_w;
+reg sign_extend_m;
+reg sign_extend_w;
+reg [ (32-1):0] store_data_x;       
+reg [ (32-1):0] store_data_m;       
+reg [ (4-1):0] byte_enable_x;
+reg [ (4-1):0] byte_enable_m;
+wire [ (32-1):0] data_m;
+reg [ (32-1):0] data_w;
+
+   
+
+  
+                                    
+ 
+                      
+              
+                                 
+                  
+                   
+                                          
+                      
+
+
+  
+                                      
+ 
+                                      
+                    
+                      
+                        
+                  
+
+
+wire wb_select_x;                                       
+  
+                                      
+
+  
+    
+    
+   
+
+
+
+reg wb_select_m;
+reg [ (32-1):0] wb_data_m;                         
+reg wb_load_complete;                                   
+   
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+  
+
+ 
+              
+                       
+             
+               
+                      
+       
+    
+                      
+                            
+                    
+                    
+                    
+                  
+                  
+                     
+                    
+                 
+            
+               
+                
+                     
+    
+              
+            
+             
+             
+                  
+                  
+    
+
+
+
+
+
+
+
+
+  
+            
+                             
+
+
+
+  
+            
+                             
+
+      
+        
+
+    
+       
+
+   
+
+    
+     
+       
+     
+         
+     
+
+          
+    
+   
+   
+
+
+   
+  
+            
+                               
+ 
+                               
+
+ 
+                               
+
+                     
+
+
+	  
+   assign wb_select_x =     1'b1
+  
+                          
+
+
+  
+                         
+
+
+  
+                         
+
+
+                     ;
+
+
+always @(*)
+begin
+    case (size_x)
+     2'b00:  store_data_x = {4{store_operand_x[7:0]}};
+     2'b11: store_data_x = {2{store_operand_x[15:0]}};
+     2'b10:  store_data_x = store_operand_x;    
+    default:          store_data_x = { 32{1'bx}};
+    endcase
+end
+
+
+always @(*)
+begin
+    casez ({size_x, load_store_address_x[1:0]})
+    { 2'b00, 2'b11}:  byte_enable_x = 4'b0001;
+    { 2'b00, 2'b10}:  byte_enable_x = 4'b0010;
+    { 2'b00, 2'b01}:  byte_enable_x = 4'b0100;
+    { 2'b00, 2'b00}:  byte_enable_x = 4'b1000;
+    { 2'b11, 2'b1?}: byte_enable_x = 4'b0011;
+    { 2'b11, 2'b0?}: byte_enable_x = 4'b1100;
+    { 2'b10, 2'b??}:  byte_enable_x = 4'b1111;
+    default:                   byte_enable_x = 4'bxxxx;
+    endcase
+end
+
+  
+      
+            
+
+           
+	                            
+   
+   
+               
+        
+
+
+   
+  
+  
+   
+   
+         
+                    
+                       
+                      
+                        
+                     
+                        
+  
+   
+         
+                    
+                       
+                      
+                      
+  
+ 
+   
+   
+         
+                    
+                       
+                      
+                      
+  
+   
+         
+                     
+                    
+  
+ 
+
+
+   
+   
+   
+         
+                     
+                      
+                      
+                      
+  
+   
+         
+                     
+                    
+  
+ 
+
+    
+   
+         
+                     
+                    
+
+  
+
+   
+   assign data_m = wb_data_m;
+   
+
+  
+
+ 
+
+
+
+always @(*)
+begin
+    casez ({size_w, load_store_address_w[1:0]})
+    { 2'b00, 2'b11}:  load_data_w = {{24{sign_extend_w & data_w[7]}}, data_w[7:0]};
+    { 2'b00, 2'b10}:  load_data_w = {{24{sign_extend_w & data_w[15]}}, data_w[15:8]};
+    { 2'b00, 2'b01}:  load_data_w = {{24{sign_extend_w & data_w[23]}}, data_w[23:16]};
+    { 2'b00, 2'b00}:  load_data_w = {{24{sign_extend_w & data_w[31]}}, data_w[31:24]};
+    { 2'b11, 2'b1?}: load_data_w = {{16{sign_extend_w & data_w[15]}}, data_w[15:0]};
+    { 2'b11, 2'b0?}: load_data_w = {{16{sign_extend_w & data_w[31]}}, data_w[31:16]};
+    { 2'b10, 2'b??}:  load_data_w = data_w;
+    default:                   load_data_w = { 32{1'bx}};
+    endcase
+end
+
+
+assign d_bte_o =  2'b00;
+
+                  
+
+ 
+     
+    
+    
+   
+   
+   
+    
+    
+    
+    
+   
+   
+     
+     
+    
+    
+    
+   
+         
+     
+     
+    
+    
+
+
+
+
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        d_cyc_o <=  1'b0;
+        d_stb_o <=  1'b0;
+        d_dat_o <= { 32{1'b0}};
+        d_adr_o <= { 32{1'b0}};
+        d_sel_o <= { 4{ 1'b0}};
+        d_we_o <=  1'b0;
+        d_cti_o <=  3'b111;
+        d_lock_o <=  1'b0;
+        wb_data_m <= { 32{1'b0}};
+        wb_load_complete <=  1'b0;
+        stall_wb_load <=  1'b0;
+                  
+          
+
+                
+    end
+    else 
+    begin
+   
+        
+          
+
+                
+        
+        if (d_cyc_o ==  1'b1)
+        begin
+            
+            if ((d_ack_i ==  1'b1) || (d_err_i ==  1'b1))
+            begin
+                  
+                     
+                
+                    
+                        
+                
+                
+
+                
+                begin
+                    
+                    d_cyc_o <=  1'b0;
+                    d_stb_o <=  1'b0;
+                    d_lock_o <=  1'b0;
+                end
+      
+                  
+                
+                  
+
+
+                
+                wb_data_m <= d_dat_i;
+                
+                wb_load_complete <= !d_we_o;
+            end
+            
+        end
+        else 
+        begin
+                  
+               
+            
+                
+                  
+                  
+                  
+                                  
+                  
+                  
+                
+            
+             
+
+            
+                 if (   (store_q_m ==  1'b1)
+                     && (stall_m ==  1'b0)
+  
+                        
+
+
+  
+		        
+
+			
+                    )
+            begin
+                
+                d_dat_o <= store_data_m;
+                d_adr_o <= load_store_address_m;
+                d_cyc_o <=  1'b1;
+                d_sel_o <= byte_enable_m;
+                d_stb_o <=  1'b1;
+                d_we_o <=  1'b1;
+                d_cti_o <=  3'b111;
+            end        
+            else if (   (load_q_m ==  1'b1) 
+                     && (wb_select_m ==  1'b1) 
+                     && (wb_load_complete ==  1'b0)
+                     
+                    )
+            begin
+                
+                stall_wb_load <=  1'b0;
+                d_adr_o <= load_store_address_m;
+                d_cyc_o <=  1'b1;
+                d_sel_o <= byte_enable_m;
+                d_stb_o <=  1'b1;
+                d_we_o <=  1'b0;
+                d_cti_o <=  3'b111;
+            end
+        end
+        
+        if (stall_m ==  1'b0)
+            wb_load_complete <=  1'b0;
+        
+        if ((load_q_x ==  1'b1) && (wb_select_x ==  1'b1) && (stall_x ==  1'b0))
+            stall_wb_load <=  1'b1;
+        
+        if ((kill_m ==  1'b1) || (exception_m ==  1'b1))
+            stall_wb_load <=  1'b0;
+    end
+end
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        sign_extend_m <=  1'b0;
+        size_m <= 2'b00;
+        byte_enable_m <=  1'b0;
+        store_data_m <= { 32{1'b0}};
+  
+          
+
+
+  
+          
+
+
+  
+          
+			    
+
+
+        wb_select_m <=  1'b0;        
+    end
+    else
+    begin
+        if (stall_m ==  1'b0)
+        begin
+            sign_extend_m <= sign_extend_x;
+            size_m <= size_x;
+            byte_enable_m <= byte_enable_x;    
+            store_data_m <= store_data_x;
+  
+              
+
+
+  
+              
+
+
+  
+              
+			    
+
+
+            wb_select_m <= wb_select_x;
+        end
+    end
+end
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        size_w <= 2'b00;
+        data_w <= { 32{1'b0}};
+        sign_extend_w <=  1'b0;
+    end
+    else
+    begin
+        size_w <= size_m;
+
+  
+         
+
+
+        data_w <= data_m;
+
+        sign_extend_w <= sign_extend_m;
+    end
+end
+
+
+
+
+
+
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_decoder_medium_icache (
+    
+    instruction,
+    
+    d_result_sel_0,
+    d_result_sel_1,        
+    x_result_sel_csr,
+  
+    
+
+    
+      
+    
+
+
+  
+
+    x_result_sel_sext,
+ 
+    
+    x_result_sel_logic,
+  
+    
+
+
+    x_result_sel_add,
+    m_result_sel_compare,
+  
+
+    m_result_sel_shift,  
+ 
+    
+    w_result_sel_load,
+  
+
+    w_result_sel_mul,
+ 
+
+    x_bypass_enable,
+    m_bypass_enable,
+    read_enable_0,
+    read_idx_0,
+    read_enable_1,
+    read_idx_1,
+    write_enable,
+    write_idx,
+    immediate,
+    branch_offset,
+    load,
+    store,
+    size,
+    sign_extend,
+    adder_op,
+    logic_op,
+  
+
+    direction,
+ 
+
+  
+    
+    
+
+
+  
+    
+
+
+  
+    
+    
+
+
+    branch,
+    branch_reg,
+    condition,
+    bi_conditional,
+    bi_unconditional,
+  
+    
+
+
+    scall,
+    eret,
+  
+    
+
+
+  
+    
+
+
+    csr_write_enable
+    );
+
+
+
+
+
+input [ (32-1):0] instruction;       
+
+
+
+
+
+output [ 0:0] d_result_sel_0;
+reg    [ 0:0] d_result_sel_0;
+output [ 1:0] d_result_sel_1;
+reg    [ 1:0] d_result_sel_1;
+output x_result_sel_csr;
+reg    x_result_sel_csr;
+  
+ 
+    
+
+
+      
+ 
+    
+
+
+  
+
+output x_result_sel_sext;
+reg    x_result_sel_sext;
+ 
+
+output x_result_sel_logic;
+reg    x_result_sel_logic;
+  
+ 
+    
+
+
+output x_result_sel_add;
+reg    x_result_sel_add;
+output m_result_sel_compare;
+reg    m_result_sel_compare;
+  
+
+output m_result_sel_shift;
+reg    m_result_sel_shift;
+ 
+
+output w_result_sel_load;
+reg    w_result_sel_load;
+  
+
+output w_result_sel_mul;
+reg    w_result_sel_mul;
+ 
+
+output x_bypass_enable;
+wire   x_bypass_enable;
+output m_bypass_enable;
+wire   m_bypass_enable;
+output read_enable_0;
+wire   read_enable_0;
+output [ (5-1):0] read_idx_0;
+wire   [ (5-1):0] read_idx_0;
+output read_enable_1;
+wire   read_enable_1;
+output [ (5-1):0] read_idx_1;
+wire   [ (5-1):0] read_idx_1;
+output write_enable;
+wire   write_enable;
+output [ (5-1):0] write_idx;
+wire   [ (5-1):0] write_idx;
+output [ (32-1):0] immediate;
+wire   [ (32-1):0] immediate;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset;
+wire   [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset;
+output load;
+wire   load;
+output store;
+wire   store;
+output [ 1:0] size;
+wire   [ 1:0] size;
+output sign_extend;
+wire   sign_extend;
+output adder_op;
+wire   adder_op;
+output [ 3:0] logic_op;
+wire   [ 3:0] logic_op;
+  
+
+output direction;
+wire   direction;
+ 
+
+  
+ 
+   
+ 
+   
+
+
+  
+ 
+   
+
+
+  
+ 
+   
+ 
+   
+
+
+output branch;
+wire   branch;
+output branch_reg;
+wire   branch_reg;
+output [ (3-1):0] condition;
+wire   [ (3-1):0] condition;
+output bi_conditional;
+wire bi_conditional;
+output bi_unconditional;
+wire bi_unconditional;
+  
+ 
+   
+
+
+output scall;
+wire   scall;
+output eret;
+wire   eret;
+  
+ 
+   
+
+
+  
+  
+    
+
+
+output csr_write_enable;
+wire   csr_write_enable;
+
+
+
+
+
+wire [ (32-1):0] extended_immediate;       
+wire [ (32-1):0] high_immediate;           
+wire [ (32-1):0] call_immediate;           
+wire [ (32-1):0] branch_immediate;         
+wire sign_extend_immediate;                     
+wire select_high_immediate;                     
+wire select_call_immediate;                     
+
+wire op_add;
+wire op_and;
+wire op_andhi;
+wire op_b;
+wire op_bi;
+wire op_be;
+wire op_bg;
+wire op_bge;
+wire op_bgeu;
+wire op_bgu;
+wire op_bne;
+wire op_call;
+wire op_calli;
+wire op_cmpe;
+wire op_cmpg;
+wire op_cmpge;
+wire op_cmpgeu;
+wire op_cmpgu;
+wire op_cmpne;
+  
+ 
+
+
+wire op_lb;
+wire op_lbu;
+wire op_lh;
+wire op_lhu;
+wire op_lw;
+  
+ 
+
+
+  
+
+wire op_mul;
+ 
+
+wire op_nor;
+wire op_or;
+wire op_orhi;
+wire op_raise;
+wire op_rcsr;
+wire op_sb;
+  
+
+wire op_sextb;
+wire op_sexth;
+ 
+
+wire op_sh;
+  
+
+wire op_sl;
+ 
+
+wire op_sr;
+wire op_sru;
+wire op_sub;
+wire op_sw;
+  
+ 
+
+
+wire op_wcsr;
+wire op_xnor;
+wire op_xor;
+
+wire arith;
+wire logical;
+wire cmp;
+wire bra;
+wire call;
+  
+
+wire shift;
+ 
+
+  
+ 
+
+
+  
+
+wire sext;
+ 
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+assign op_add    = instruction[ 30:26] ==  5'b01101;
+assign op_and    = instruction[ 30:26] ==  5'b01000;
+assign op_andhi  = instruction[ 31:26] ==  6'b011000;
+assign op_b      = instruction[ 31:26] ==  6'b110000;
+assign op_bi     = instruction[ 31:26] ==  6'b111000;
+assign op_be     = instruction[ 31:26] ==  6'b010001;
+assign op_bg     = instruction[ 31:26] ==  6'b010010;
+assign op_bge    = instruction[ 31:26] ==  6'b010011;
+assign op_bgeu   = instruction[ 31:26] ==  6'b010100;
+assign op_bgu    = instruction[ 31:26] ==  6'b010101;
+assign op_bne    = instruction[ 31:26] ==  6'b010111;
+assign op_call   = instruction[ 31:26] ==  6'b110110;
+assign op_calli  = instruction[ 31:26] ==  6'b111110;
+assign op_cmpe   = instruction[ 30:26] ==  5'b11001;
+assign op_cmpg   = instruction[ 30:26] ==  5'b11010;
+assign op_cmpge  = instruction[ 30:26] ==  5'b11011;
+assign op_cmpgeu = instruction[ 30:26] ==  5'b11100;
+assign op_cmpgu  = instruction[ 30:26] ==  5'b11101;
+assign op_cmpne  = instruction[ 30:26] ==  5'b11111;
+  
+       
+
+
+assign op_lb     = instruction[ 31:26] ==  6'b000100;
+assign op_lbu    = instruction[ 31:26] ==  6'b010000;
+assign op_lh     = instruction[ 31:26] ==  6'b000111;
+assign op_lhu    = instruction[ 31:26] ==  6'b001011;
+assign op_lw     = instruction[ 31:26] ==  6'b001010;
+  
+       
+
+
+  
+
+assign op_mul    = instruction[ 30:26] ==  5'b00010;
+ 
+
+assign op_nor    = instruction[ 30:26] ==  5'b00001;
+assign op_or     = instruction[ 30:26] ==  5'b01110;
+assign op_orhi   = instruction[ 31:26] ==  6'b011110;
+assign op_raise  = instruction[ 31:26] ==  6'b101011;
+assign op_rcsr   = instruction[ 31:26] ==  6'b100100;
+assign op_sb     = instruction[ 31:26] ==  6'b001100;
+  
+
+assign op_sextb  = instruction[ 31:26] ==  6'b101100;
+assign op_sexth  = instruction[ 31:26] ==  6'b110111;
+ 
+
+assign op_sh     = instruction[ 31:26] ==  6'b000011;
+  
+
+assign op_sl     = instruction[ 30:26] ==  5'b01111;      
+ 
+
+assign op_sr     = instruction[ 30:26] ==  5'b00101;
+assign op_sru    = instruction[ 30:26] ==  5'b00000;
+assign op_sub    = instruction[ 31:26] ==  6'b110010;
+assign op_sw     = instruction[ 31:26] ==  6'b010110;
+  
+       
+
+
+assign op_wcsr   = instruction[ 31:26] ==  6'b110100;
+assign op_xnor   = instruction[ 30:26] ==  5'b01001;
+assign op_xor    = instruction[ 30:26] ==  5'b00110;
+
+
+assign arith = op_add | op_sub;
+assign logical = op_and | op_andhi | op_nor | op_or | op_orhi | op_xor | op_xnor;
+assign cmp = op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne;
+assign bi_conditional = op_be | op_bg | op_bge | op_bgeu  | op_bgu | op_bne;
+assign bi_unconditional = op_bi;
+assign bra = op_b | bi_unconditional | bi_conditional;
+assign call = op_call | op_calli;
+  
+
+assign shift = op_sl | op_sr | op_sru;
+ 
+
+  
+     
+
+
+  
+   
+     
+
+
+  
+
+assign sext = op_sextb | op_sexth;
+ 
+
+  
+   
+
+
+  
+    
+   
+
+
+assign load = op_lb | op_lbu | op_lh | op_lhu | op_lw;
+assign store = op_sb | op_sh | op_sw;
+
+
+always @(*)
+begin
+    
+    if (call) 
+        d_result_sel_0 =  1'b1;
+    else 
+        d_result_sel_0 =  1'b0;
+    if (call) 
+        d_result_sel_1 =  2'b00;         
+    else if ((instruction[31] == 1'b0) && !bra) 
+        d_result_sel_1 =  2'b10;
+    else
+        d_result_sel_1 =  2'b01; 
+    
+    x_result_sel_csr =  1'b0;
+  
+      
+
+
+  
+      
+
+
+  
+
+    x_result_sel_sext =  1'b0;
+ 
+
+    x_result_sel_logic =  1'b0;
+          
+      
+
+
+    x_result_sel_add =  1'b0;
+    if (op_rcsr)
+        x_result_sel_csr =  1'b1;
+      
+ 
+         
+          
+
+ 
+        
+                  
+
+ 
+      
+                      
+
+
+
+  
+      
+                  
+
+
+  
+
+    else if (sext)
+        x_result_sel_sext =  1'b1;
+ 
+        
+    else if (logical) 
+        x_result_sel_logic =  1'b1;
+          
+      
+          
+
+
+    else 
+        x_result_sel_add =  1'b1;        
+    
+    
+
+    m_result_sel_compare = cmp;
+  
+
+    m_result_sel_shift = shift;
+ 
+
+
+    
+    w_result_sel_load = load;
+  
+
+    w_result_sel_mul = op_mul; 
+ 
+
+end
+
+
+assign x_bypass_enable =  arith 
+                        | logical
+  
+                         
+                         
+
+                        
+  
+                         
+
+
+  
+                         
+                         
+
+
+  
+                         
+
+                  
+  
+
+                        | sext 
+ 
+                        
+  
+                         
+
+
+                        | op_rcsr
+                        ;
+
+assign m_bypass_enable = x_bypass_enable 
+  
+
+                        | shift
+ 
+
+                        | cmp
+                        ;
+
+assign read_enable_0 = ~(op_bi | op_calli);
+assign read_idx_0 = instruction[25:21];
+
+assign read_enable_1 = ~(op_bi | op_calli | load);
+assign read_idx_1 = instruction[20:16];
+
+assign write_enable = ~(bra | op_raise | store | op_wcsr);
+assign write_idx = call
+                    ? 5'd29
+                    : instruction[31] == 1'b0 
+                        ? instruction[20:16] 
+                        : instruction[15:11];
+                        
+
+assign size = instruction[27:26];
+
+assign sign_extend = instruction[28];                      
+
+assign adder_op = op_sub | op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne | bra;
+
+assign logic_op = instruction[29:26];
+  
+
+
+assign direction = instruction[29];
+ 
+
+
+assign branch = bra | call;
+assign branch_reg = op_call | op_b;
+assign condition = instruction[28:26];      
+  
+     
+
+
+assign scall = op_raise & instruction[2];
+assign eret = op_b & (instruction[25:21] == 5'd30);
+  
+       
+
+
+  
+
+   
+
+
+
+assign csr_write_enable = op_wcsr;
+
+
+
+assign sign_extend_immediate = ~(op_and | op_cmpgeu | op_cmpgu | op_nor | op_or | op_xnor | op_xor);
+assign select_high_immediate = op_andhi | op_orhi;
+assign select_call_immediate = instruction[31];
+
+assign high_immediate = {instruction[15:0], 16'h0000};
+assign extended_immediate = {{16{sign_extend_immediate & instruction[15]}}, instruction[15:0]};
+assign call_immediate = {{6{instruction[25]}}, instruction[25:0]};
+assign branch_immediate = {{16{instruction[15]}}, instruction[15:0]};
+
+assign immediate = select_high_immediate ==  1'b1 
+                        ? high_immediate 
+                        : extended_immediate;
+   
+assign branch_offset = select_call_immediate ==  1'b1   
+                        ? (call_immediate[ (clogb2(32'h7fffffff-32'h0)-2)-1:0])
+                        : (branch_immediate[ (clogb2(32'h7fffffff-32'h0)-2)-1:0]);
+    
+endmodule 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_icache_medium_icache ( 
+    
+    clk_i,
+    rst_i,    
+    stall_a,
+    stall_f,
+    address_a,
+    address_f,
+    read_enable_f,
+    refill_ready,
+    refill_data,
+    iflush,
+  
+    
+
+
+    valid_d,
+    branch_predict_taken_d,
+    
+    stall_request,
+    restart_request,
+    refill_request,
+    refill_address,
+    refilling,
+    inst
+    );
+
+
+
+
+
+parameter associativity = 1;                            
+parameter sets = 512;                                   
+parameter bytes_per_line = 16;                          
+parameter base_address = 0;                             
+parameter limit = 0;                                    
+
+localparam addr_offset_width = clogb2(bytes_per_line)-1-2;
+localparam addr_set_width = clogb2(sets)-1;
+localparam addr_offset_lsb = 2;
+localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
+localparam addr_set_lsb = (addr_offset_msb+1);
+localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
+localparam addr_tag_lsb = (addr_set_msb+1);
+localparam addr_tag_msb = clogb2( 32'h7fffffff- 32'h0)-1;
+localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
+
+
+
+
+
+input clk_i;                                        
+input rst_i;                                        
+
+input stall_a;                                      
+input stall_f;                                      
+
+input valid_d;                                      
+input branch_predict_taken_d;                       
+   
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] address_a;                     
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] address_f;                     
+input read_enable_f;                                
+
+input refill_ready;                                 
+input [ (32-1):0] refill_data;          
+
+input iflush;                                       
+  
+                                      
+
+
+   
+
+
+
+
+output stall_request;                               
+wire   stall_request;
+output restart_request;                             
+reg    restart_request;
+output refill_request;                              
+wire   refill_request;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] refill_address;               
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] refill_address;               
+output refilling;                                   
+reg    refilling;
+output [ (32-1):0] inst;                
+wire   [ (32-1):0] inst;
+
+
+
+
+
+wire enable;
+wire [0:associativity-1] way_mem_we;
+wire [ (32-1):0] way_data[0:associativity-1];
+wire [ ((addr_tag_width+1)-1):1] way_tag[0:associativity-1];
+wire [0:associativity-1] way_valid;
+wire [0:associativity-1] way_match;
+wire miss;
+
+wire [ (addr_set_width-1):0] tmem_read_address;
+wire [ (addr_set_width-1):0] tmem_write_address;
+wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_read_address;
+wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_write_address;
+wire [ ((addr_tag_width+1)-1):0] tmem_write_data;
+
+reg [ 3:0] state;
+wire flushing;
+wire check;
+wire refill;
+
+reg [associativity-1:0] refill_way_select;
+reg [ addr_offset_msb:addr_offset_lsb] refill_offset;
+wire last_refill;
+reg [ (addr_set_width-1):0] flush_set;
+
+genvar i;
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+   generate
+      for (i = 0; i < associativity; i = i + 1)
+	begin : memories
+	   
+	   lm32_ram 
+	     #(
+	       
+	       .data_width                 (32),
+	       .address_width              ( (addr_offset_width+addr_set_width))
+
+) 
+	   way_0_data_ram 
+	     (
+	      
+	      .read_clk                   (clk_i),
+	      .write_clk                  (clk_i),
+	      .reset                      (rst_i),
+	      .read_address               (dmem_read_address),
+	      .enable_read                (enable),
+	      .write_address              (dmem_write_address),
+	      .enable_write               ( 1'b1),
+	      .write_enable               (way_mem_we[i]),
+	      .write_data                 (refill_data),    
+	      
+	      .read_data                  (way_data[i])
+	      );
+	   
+	   lm32_ram 
+	     #(
+	       
+	       .data_width                 ( (addr_tag_width+1)),
+	       .address_width              ( addr_set_width)
+
+	       ) 
+	   way_0_tag_ram 
+	     (
+	      
+	      .read_clk                   (clk_i),
+	      .write_clk                  (clk_i),
+	      .reset                      (rst_i),
+	      .read_address               (tmem_read_address),
+	      .enable_read                (enable),
+	      .write_address              (tmem_write_address),
+	      .enable_write               ( 1'b1),
+	      .write_enable               (way_mem_we[i] | flushing),
+	      .write_data                 (tmem_write_data),
+	      
+	      .read_data                  ({way_tag[i], way_valid[i]})
+	      );
+	   
+	end
+endgenerate
+
+
+
+
+
+
+generate
+    for (i = 0; i < associativity; i = i + 1)
+    begin : match
+assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_f[ addr_tag_msb:addr_tag_lsb],  1'b1});
+    end
+endgenerate
+
+
+generate
+    if (associativity == 1)
+    begin : inst_1
+assign inst = way_match[0] ? way_data[0] : 32'b0;
+    end
+    else if (associativity == 2)
+	 begin : inst_2
+assign inst = way_match[0] ? way_data[0] : (way_match[1] ? way_data[1] : 32'b0);
+    end
+endgenerate
+
+
+generate 
+    if (bytes_per_line > 4)
+assign dmem_write_address = {refill_address[ addr_set_msb:addr_set_lsb], refill_offset};
+    else
+assign dmem_write_address = refill_address[ addr_set_msb:addr_set_lsb];
+endgenerate
+    
+assign dmem_read_address = address_a[ addr_set_msb:addr_offset_lsb];
+
+
+assign tmem_read_address = address_a[ addr_set_msb:addr_set_lsb];
+assign tmem_write_address = flushing 
+                                ? flush_set
+                                : refill_address[ addr_set_msb:addr_set_lsb];
+
+
+generate 
+    if (bytes_per_line > 4)                            
+assign last_refill = refill_offset == {addr_offset_width{1'b1}};
+    else
+assign last_refill =  1'b1;
+endgenerate
+
+
+assign enable = (stall_a ==  1'b0);
+
+
+generate
+    if (associativity == 1) 
+    begin : we_1     
+assign way_mem_we[0] = (refill_ready ==  1'b1);
+    end
+    else
+    begin : we_2
+assign way_mem_we[0] = (refill_ready ==  1'b1) && (refill_way_select[0] ==  1'b1);
+assign way_mem_we[1] = (refill_ready ==  1'b1) && (refill_way_select[1] ==  1'b1);
+    end
+endgenerate                     
+
+
+assign tmem_write_data[ 0] = last_refill & !flushing;
+assign tmem_write_data[ ((addr_tag_width+1)-1):1] = refill_address[ addr_tag_msb:addr_tag_lsb];
+
+
+assign flushing = |state[1:0];
+assign check = state[2];
+assign refill = state[3];
+
+assign miss = (~(|way_match)) && (read_enable_f ==  1'b1) && (stall_f ==  1'b0) && !(valid_d && branch_predict_taken_d);
+assign stall_request = (check ==  1'b0);
+assign refill_request = (refill ==  1'b1);
+                      
+
+
+
+
+
+generate
+    if (associativity >= 2) 
+    begin : way_select      
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
+    else
+    begin        
+        if (miss ==  1'b1)
+            refill_way_select <= {refill_way_select[0], refill_way_select[1]};
+    end
+end
+    end
+endgenerate
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        refilling <=  1'b0;
+    else
+        refilling <= refill;
+end
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        state <=  4'b0001;
+        flush_set <= { addr_set_width{1'b1}};
+        refill_address <= { (clogb2(32'h7fffffff-32'h0)-2){1'bx}};
+        restart_request <=  1'b0;
+    end
+    else 
+    begin
+        case (state)
+
+        
+         4'b0001:
+        begin            
+            if (flush_set == { addr_set_width{1'b0}})
+                state <=  4'b0100;
+            flush_set <= flush_set - 1'b1;
+        end
+
+        
+         4'b0010:
+        begin            
+            if (flush_set == { addr_set_width{1'b0}})
+  
+	       
+                  
+	      
+
+
+		state <=  4'b0100;
+	   
+            flush_set <= flush_set - 1'b1;
+        end
+        
+        
+         4'b0100:
+        begin            
+            if (stall_a ==  1'b0)
+                restart_request <=  1'b0;
+            if (iflush ==  1'b1)
+            begin
+                refill_address <= address_f;
+                state <=  4'b0010;
+            end
+            else if (miss ==  1'b1)
+            begin
+                refill_address <= address_f;
+                state <=  4'b1000;
+            end
+        end
+
+        
+         4'b1000:
+        begin            
+            if (refill_ready ==  1'b1)
+            begin
+                if (last_refill ==  1'b1)
+                begin
+                    restart_request <=  1'b1;
+                    state <=  4'b0100;
+                end
+            end
+        end
+
+        endcase        
+    end
+end
+
+generate 
+    if (bytes_per_line > 4)
+    begin
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        refill_offset <= {addr_offset_width{1'b0}};
+    else 
+    begin
+        case (state)
+        
+        
+         4'b0100:
+        begin            
+            if (iflush ==  1'b1)
+                refill_offset <= {addr_offset_width{1'b0}};
+            else if (miss ==  1'b1)
+                refill_offset <= {addr_offset_width{1'b0}};
+        end
+
+        
+         4'b1000:
+        begin            
+            if (refill_ready ==  1'b1)
+                refill_offset <= refill_offset + 1'b1;
+        end
+
+        endcase        
+    end
+end
+    end
+endgenerate
+   
+endmodule
+
+ 
+
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+                    
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+                                             
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+                      
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+ 
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+                     
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+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
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+ 
+ 
+
+ 
+ 
+
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+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
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+ 
+
+
+
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+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_instruction_unit_medium_icache (
+    
+    clk_i,
+    rst_i,
+    
+    stall_a,
+    stall_f,
+    stall_d,
+    stall_x,
+    stall_m,
+    valid_f,
+    valid_d,
+    kill_f,
+    branch_predict_taken_d,
+    branch_predict_address_d,
+      
+    
+    
+
+
+    exception_m,
+    branch_taken_m,
+    branch_mispredict_taken_m,
+    branch_target_m,
+  
+
+    iflush,
+ 
+
+  
+    
+    
+    
+
+        
+  
+
+    
+    i_dat_i,
+    i_ack_i,
+    i_err_i,
+    i_rty_i,
+ 
+
+  
+    
+    
+    
+    
+
+
+    
+    
+    pc_f,
+    pc_d,
+    pc_x,
+    pc_m,
+    pc_w,
+  
+
+    icache_stall_request,
+    icache_restart_request,
+    icache_refill_request,
+    icache_refilling,
+ 
+
+  
+
+    
+    i_dat_o,
+    i_adr_o,
+    i_cyc_o,
+    i_sel_o,
+    i_stb_o,
+    i_we_o,
+    i_cti_o,
+    i_lock_o,
+    i_bte_o,
+ 
+
+  
+    
+    
+    
+
+
+  
+    
+    
+
+
+  
+    
+
+
+  
+
+    instruction_f,
+ 
+    
+    instruction_d
+    );
+
+
+
+
+
+parameter eba_reset =  32'h00000000;                   
+parameter associativity = 1;                            
+parameter sets = 512;                                   
+parameter bytes_per_line = 16;                          
+parameter base_address = 0;                             
+parameter limit = 0;                                    
+
+
+localparam eba_reset_minus_4 = eba_reset - 4;
+localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
+localparam addr_offset_lsb = 2;
+localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
+
+
+
+
+  
+  
+   
+        
+   
+
+
+
+input clk_i;                                            
+input rst_i;                                            
+
+input stall_a;                                          
+input stall_f;                                          
+input stall_d;                                          
+input stall_x;                                          
+input stall_m;                                          
+input valid_f;                                          
+input valid_d;                                          
+input kill_f;                                           
+
+input branch_predict_taken_d;                           
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d;          
+   
+      
+                                    
+                     
+
+
+input exception_m;
+input branch_taken_m;                                   
+input branch_mispredict_taken_m;                        
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_m;                   
+
+  
+
+input iflush;                                           
+ 
+
+  
+                            
+                             
+ 
+
+        
+
+
+  
+
+input [ (32-1):0] i_dat_i;                         
+input i_ack_i;                                          
+input i_err_i;                                          
+input i_rty_i;                                          
+ 
+
+
+  
+                                  
+                                 
+                   
+                      
+
+
+
+
+
+
+        
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;                             
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;                             
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;                             
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;                             
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;                             
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;
+
+  
+
+output icache_stall_request;                            
+wire   icache_stall_request;
+output icache_restart_request;                          
+wire   icache_restart_request;
+output icache_refill_request;                           
+wire   icache_refill_request;
+output icache_refilling;                                
+wire   icache_refilling;
+ 
+
+
+  
+
+output [ (32-1):0] i_dat_o;                        
+  
+     
+
+
+wire   [ (32-1):0] i_dat_o;
+ 
+
+output [ (32-1):0] i_adr_o;                        
+reg    [ (32-1):0] i_adr_o;
+output i_cyc_o;                                         
+reg    i_cyc_o; 
+output [ (4-1):0] i_sel_o;                 
+  
+     
+
+
+wire   [ (4-1):0] i_sel_o;
+ 
+
+output i_stb_o;                                         
+reg    i_stb_o;
+output i_we_o;                                          
+  
+    
+
+
+wire   i_we_o;
+ 
+
+output [ (3-1):0] i_cti_o;                       
+reg    [ (3-1):0] i_cti_o;
+output i_lock_o;                                        
+reg    i_lock_o;
+output [ (2-1):0] i_bte_o;                       
+wire   [ (2-1):0] i_bte_o;
+ 
+
+
+  
+                   
+     
+                             
+   
+
+
+
+  
+                                      
+    
+
+
+  
+
+output [ (32-1):0] instruction_f;           
+wire   [ (32-1):0] instruction_f;
+ 
+
+output [ (32-1):0] instruction_d;           
+reg    [ (32-1):0] instruction_d;
+
+
+
+
+
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_a;                                
+
+  
+
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] restart_address;                     
+ 
+
+
+  
+
+wire icache_read_enable_f;                              
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] icache_refill_address;              
+reg icache_refill_ready;                                
+reg [ (32-1):0] icache_refill_data;         
+wire [ (32-1):0] icache_data_f;             
+wire [ (3-1):0] first_cycle_type;                
+wire [ (3-1):0] next_cycle_type;                 
+wire last_word;                                         
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] first_address;                      
+ 
+ 
+                    
+
+
+
+  
+                                      
+    			     
+   
+
+
+  
+
+ 
+               
+
+
+
+   
+  
+   
+    			               
+ 
+
+
+  
+    		       
+
+
+   
+  
+                                         
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+  
+
+
+lm32_icache_medium_icache #(
+    .associativity          (associativity),
+    .sets                   (sets),
+    .bytes_per_line         (bytes_per_line),
+    .base_address           (base_address),
+    .limit                  (limit)
+    ) icache ( 
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),      
+    .stall_a                (stall_a),
+    .stall_f                (stall_f),
+    .branch_predict_taken_d (branch_predict_taken_d),
+    .valid_d                (valid_d),
+    .address_a              (pc_a),
+    .address_f              (pc_f),
+    .read_enable_f          (icache_read_enable_f),
+    .refill_ready           (icache_refill_ready),
+    .refill_data            (icache_refill_data),
+    .iflush                 (iflush),
+    
+    .stall_request          (icache_stall_request),
+    .restart_request        (icache_restart_request),
+    .refill_request         (icache_refill_request),
+    .refill_address         (icache_refill_address),
+    .refilling              (icache_refilling),
+    .inst                   (icache_data_f)
+    );
+ 
+
+
+
+
+
+
+  
+
+   
+   assign icache_read_enable_f =    (valid_f ==  1'b1)
+     && (kill_f ==  1'b0)
+   
+      
+ 
+                         
+    
+				       
+ 
+       
+				    ;
+ 
+ 
+
+
+always @(*)
+begin
+    
+  
+       
+          
+     
+
+    
+      if (branch_taken_m ==  1'b1)
+	if ((branch_mispredict_taken_m ==  1'b1) && (exception_m ==  1'b0))
+	  pc_a = pc_x;
+	else
+          pc_a = branch_target_m;
+      
+          
+          
+
+
+      else
+	if ( (valid_d ==  1'b1) && (branch_predict_taken_d ==  1'b1) )
+	  pc_a = branch_predict_address_d;
+	else
+  
+
+          if (icache_restart_request ==  1'b1)
+            pc_a = restart_address;
+	  else 
+ 
+        
+            pc_a = pc_f + 1'b1;
+end
+
+
+  
+      
+      
+        
+
+
+
+  
+
+     
+    	      
+
+     
+      
+	  
+       
+	  
+	
+	    
+     
+   
+   
+          
+
+
+  
+   
+
+
+                     
+
+  
+
+assign instruction_f = icache_data_f;
+ 
+   
+
+
+
+ 
+ 
+   
+
+  
+
+  
+
+
+assign i_dat_o = 32'd0;
+assign i_we_o =  1'b0;
+assign i_sel_o = 4'b1111;
+ 
+
+assign i_bte_o =  2'b00;
+ 
+
+
+  
+
+
+generate
+    case (bytes_per_line)
+    4:
+    begin
+assign first_cycle_type =  3'b111;
+assign next_cycle_type =  3'b111;
+assign last_word =  1'b1;
+assign first_address = icache_refill_address;
+    end
+    8:
+    begin
+assign first_cycle_type =  3'b010;
+assign next_cycle_type =  3'b111;
+assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 1'b1;
+assign first_address = {icache_refill_address[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
+    end
+    16:
+    begin
+assign first_cycle_type =  3'b010;
+assign next_cycle_type = i_adr_o[addr_offset_msb] == 1'b1 ?  3'b111 :  3'b010;
+assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 2'b11;
+assign first_address = {icache_refill_address[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
+    end
+    endcase
+endgenerate
+ 
+
+                     
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        pc_f <= eba_reset_minus_4[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2];
+        pc_d <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+        pc_x <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+        pc_m <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+        pc_w <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+    end
+    else
+    begin
+        if (stall_f ==  1'b0)
+            pc_f <= pc_a;
+        if (stall_d ==  1'b0)
+            pc_d <= pc_f;
+        if (stall_x ==  1'b0)
+            pc_x <= pc_d;
+        if (stall_m ==  1'b0)
+            pc_m <= pc_x;
+        pc_w <= pc_m;
+    end
+end
+
+  
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        restart_address <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+    else
+    begin
+  
+         
+            
+               
+                  
+                    
+                  
+
+               
+                  
+
+
+
+  
+        
+            if (icache_refill_request ==  1'b1)
+                restart_address <= icache_refill_address;
+ 
+
+ 
+
+    end
+end
+ 
+
+
+
+  
+   
+
+       
+          
+    
+    
+           
+              
+    
+
+
+
+
+  
+    
+                 
+ 
+
+     
+       
+       
+       
+       
+     
+
+   
+
+
+
+  
+
+   
+   
+                
+   always @(posedge clk_i  )
+     begin
+	if (rst_i ==  1'b1)
+	  begin
+             i_cyc_o <=  1'b0;
+             i_stb_o <=  1'b0;
+             i_adr_o <= { 32{1'b0}};
+             i_cti_o <=  3'b111;
+             i_lock_o <=  1'b0;
+             icache_refill_data <= { 32{1'b0}};
+             icache_refill_ready <=  1'b0;
+    
+               
+  
+
+    
+               
+               
+               
+  
+
+	  end
+	else
+	  begin   
+             icache_refill_ready <=  1'b0;
+             
+             if (i_cyc_o ==  1'b1)
+               begin
+		  
+		  if ((i_ack_i ==  1'b1) || (i_err_i ==  1'b1))
+		    begin
+    
+                          
+			 
+			      
+			             
+			        
+			          
+			 
+                       
+  
+
+			 begin
+			    if (last_word ==  1'b1)
+			      begin
+				 
+				 i_cyc_o <=  1'b0;
+				 i_stb_o <=  1'b0;
+				 i_lock_o <=  1'b0;
+			      end
+			    
+			    i_adr_o[addr_offset_msb:addr_offset_lsb] <= i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
+			    i_cti_o <= next_cycle_type;
+			    
+			    icache_refill_ready <=  1'b1;
+			    icache_refill_data <= i_dat_i;
+			 end
+		    end
+    
+		   
+		     
+		    
+                         
+                         
+		    
+		  
+  
+
+               end
+             else
+               begin
+		  if ((icache_refill_request ==  1'b1) && (icache_refill_ready ==  1'b0))
+		    begin
+                       
+         
+                         
+  
+
+                       i_adr_o <= {first_address, 2'b00};
+                       i_cyc_o <=  1'b1;
+                       i_stb_o <=  1'b1;                
+                       i_cti_o <= first_cycle_type;
+                       
+    
+                         
+  
+
+		    end
+    
+		  
+		    
+                              
+			 
+			     
+			         
+			         
+			         
+			         
+			    
+			      
+			      
+			      
+			      
+			      
+			      
+			      
+			 
+		     
+  
+                    
+    
+		  
+		  
+        
+		     
+                      
+   
+		     
+                      
+  
+
+               end
+	  end
+     end
+  
+      
+     
+	   
+	  
+               
+               
+               
+               
+               
+               
+   
+               
+  
+	  
+	
+	     
+             
+                
+               
+		  
+		        
+		    
+                       
+                         
+                         
+                       
+                         
+		    
+   
+		   
+		     
+		    
+                         
+                         
+		       
+		    
+		  
+  
+               
+             
+               
+		  
+		         
+    
+			    
+         
+			 
+		    
+                       
+        
+                         
+  
+                          
+                         
+                         
+   
+                         
+  
+		    
+		  
+		    
+	                      
+    
+			         
+         
+			      
+			 
+   
+			      
+  
+			 
+		    
+               
+	  
+     
+ 
+
+ 
+ 
+
+   
+   always @(posedge clk_i  )
+     begin
+	if (rst_i ==  1'b1)
+	  begin
+             instruction_d <= { 32{1'b0}};
+  
+               
+
+
+	  end
+	else
+	  begin
+             if (stall_d ==  1'b0)
+               begin
+		  instruction_d <= instruction_f;
+  
+		    
+
+
+               end
+	  end
+     end  
+   
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+  
+
+                              
+                              
+                              
+
+
+                          
+                  
+                 
+              
+             
+                    
+                        
+                        
+
+
+                  
+         
+          
+          
+          
+          
+          
+      
+      
+         
+
+
+
+
+
+  
+    
+    
+    
+     
+    
+    
+    
+ 
+    
+    
+    
+    
+
+ 
+    
+    
+
+ 
+    
+
+    
+ 
+    
+    
+
+ 
+    
+    
+    
+    
+    
+    
+    
+
+ 
+    
+    
+
+    
+    
+    
+
+
+
+
+
+                                             
+                                             
+
+                                          
+                                       
+                        
+                              
+
+ 
+                                
+                                  
+                    
+                                           
+
+ 
+                    
+                              
+
+ 
+                                     
+
+
+
+
+
+       
+ 
+                
+    
+                
+    
+
+ 
+                            
+    
+              
+    
+                          
+    
+                                 
+    
+                                
+    
+                  
+            
+                     
+    
+
+ 
+                                       
+    
+                                       
+    
+
+  
+     
+  
+    
+             
+
+
+
+
+                           
+                         
+                       
+                     
+
+
+
+     
+  
+
+                  
+        
+                       
+        
+                       
+
+
+               
+ 
+         
+  
+  
+  
+  
+                          
+
+
+         
+
+
+
+
+
+ 
+      
+   
+      
+   
+
+                 
+
+                  
+             
+
+   
+
+ 
+   
+
+   
+
+
+                  
+     
+     
+         
+                 
+
+
+
+
+   
+   
+
+
+
+   
+
+       
+    
+          
+          
+          
+          
+    
+    
+    
+          
+          
+          
+          
+    
+
+
+
+   
+
+       
+    
+          
+          
+          
+ 
+          
+          
+          
+          
+
+ 
+          
+          
+
+                  
+          
+          
+          
+          
+
+    
+    
+    
+                  
+               
+        
+             
+            
+            
+                
+                  
+                  
+            
+            
+            
+                
+                  
+            
+            
+        
+
+ 
+        
+           
+        
+              
+              
+        
+
+         
+        
+        
+            
+                 
+            
+                                  
+                 
+ 
+                
+                
+                     
+ 
+                    
+                          
+                    
+                    
+                              
+                          
+                    
+                    
+                          
+                    
+                    
+                              
+                          
+                    
+                    
+                          
+                    
+                    
+                    
+      
+                              
+                                   
+
+                          
+                    
+                    
+                    
+      
+                              
+                                   
+
+                          
+                    
+                                                   
+                
+
+                  
+                
+                
+                      
+                      
+                                    
+                
+                
+                      
+                      
+                
+
+                
+                    
+                                
+            
+        
+ 
+        
+        
+                 
+            
+                  
+                  
+            
+        
+        
+        
+                 
+            
+                  
+                  
+            
+        
+        
+        
+                 
+            
+                  
+                  
+            
+        
+        
+        
+                 
+            
+                  
+                   
+                      
+                 
+                      
+            
+        
+        
+        
+                 
+            
+                  
+                  
+            
+        
+        
+        
+             
+            
+            
+            
+                  
+                  
+                  
+            
+            
+            
+            
+                  
+                  
+                  
+            
+            
+            
+                  
+                  
+                  
+            
+            
+        
+        
+        
+               
+                      
+                  
+                  
+                    
+                  
+                  
+            
+            
+        
+        
+              
+              
+              
+            
+
+        
+    
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_interrupt_medium_icache (
+    
+    clk_i, 
+    rst_i,
+    
+    interrupt,
+    
+    stall_x,
+  
+    
+    
+
+
+    exception,
+ 
+
+    eret_q_x,
+  
+    
+
+
+    csr,
+    csr_write_data,
+    csr_write_enable,
+    
+    interrupt_exception,
+    
+    csr_read_data
+    );
+
+
+
+
+
+parameter interrupts =  32;         
+
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+
+input [interrupts-1:0] interrupt;               
+
+input stall_x;                                  
+
+  
+                       
+                           
+
+
+input exception;                                
+ 
+
+input eret_q_x;                                 
+  
+                                  
+
+
+
+input [ (4 -1):0] csr;                      
+input [ (32-1):0] csr_write_data;          
+input csr_write_enable;                         
+
+
+
+
+
+output interrupt_exception;                     
+wire   interrupt_exception;
+
+output [ (32-1):0] csr_read_data;          
+reg    [ (32-1):0] csr_read_data;
+
+
+
+
+
+wire [interrupts-1:0] asserted;                 
+
+wire [interrupts-1:0] interrupt_n_exception;
+
+
+
+reg ie;                                         
+reg eie;                                        
+  
+                                         
+
+
+reg [interrupts-1:0] ip;                        
+reg [interrupts-1:0] im;                        
+
+
+
+
+
+
+assign interrupt_n_exception = ip & im;
+
+
+assign interrupt_exception = (|interrupt_n_exception) & ie;
+
+
+assign asserted = ip | interrupt;
+       
+generate
+    if (interrupts > 1) 
+    begin
+
+always @(*)
+begin
+    case (csr)
+     4 'h0:  csr_read_data = {{ 32-3{1'b0}}, 
+  
+                                    
+
+
+                                    1'b0,                                     
+ 
+
+                                    eie, 
+                                    ie
+                                   };
+     4 'h2:  csr_read_data = ip;
+     4 'h1:  csr_read_data = im;
+    default:       csr_read_data = { 32{1'bx}};
+    endcase
+end
+    end
+    else
+    begin
+
+always @(*)
+begin
+    case (csr)
+     4 'h0:  csr_read_data = {{ 32-3{1'b0}}, 
+  
+                                     
+
+
+                                    1'b0,                                    
+ 
+
+                                    eie, 
+                                    ie
+                                   };
+     4 'h2:  csr_read_data = ip;
+    default:       csr_read_data = { 32{1'bx}};
+      endcase
+end
+    end
+endgenerate
+    
+
+
+
+
+  
+
+   reg [ 10:0] eie_delay  = 0;
+
+   
+generate
+
+   
+    if (interrupts > 1)
+    begin
+
+always @(posedge clk_i  )
+  begin
+    if (rst_i ==  1'b1)
+    begin
+        ie                   <=  1'b0;
+        eie                  <=  1'b0;
+  
+                           
+
+
+        im                   <= {interrupts{1'b0}};
+        ip                   <= {interrupts{1'b0}};
+       eie_delay             <= 0;
+       
+    end
+    else
+    begin
+        
+        ip                   <= asserted;
+  
+           
+        
+            
+                           
+                            
+        
+            
+        
+            
+                           
+                            
+        
+
+
+        if (exception ==  1'b1)
+        begin
+            
+            eie              <= ie;
+            ie               <=  1'b0;
+        end
+ 
+
+        else if (stall_x ==  1'b0)
+        begin
+
+           if(eie_delay[0])
+             ie              <= eie;
+           
+           eie_delay         <= {1'b0, eie_delay[ 10:1]};
+
+            if (eret_q_x ==  1'b1) begin
+                
+               eie_delay[ 10] <=  1'b1;
+               eie_delay[ 10-1:0] <= 0;
+            end
+           
+                      
+           
+  
+                
+                
+                       
+
+
+            else if (csr_write_enable ==  1'b1)
+            begin
+                
+                if (csr ==  4 'h0)
+                begin
+                    ie  <= csr_write_data[0];
+                    eie <= csr_write_data[1];
+  
+                      
+
+
+                end
+                if (csr ==  4 'h1)
+                    im  <= csr_write_data[interrupts-1:0];
+                if (csr ==  4 'h2)
+                    ip  <= asserted & ~csr_write_data[interrupts-1:0];
+            end
+        end
+    end
+end
+    end
+else
+    begin
+
+always @(posedge clk_i  )
+  begin
+    if (rst_i ==  1'b1)
+    begin
+        ie              <=  1'b0;
+        eie             <=  1'b0;
+  
+                      
+
+
+        ip              <= {interrupts{1'b0}};
+       eie_delay        <= 0;
+    end
+    else
+    begin
+        
+        ip              <= asserted;
+  
+           
+        
+            
+                      
+                       
+        
+            
+        
+            
+                      
+                       
+        
+
+
+        if (exception ==  1'b1)
+        begin
+            
+            eie         <= ie;
+            ie          <=  1'b0;
+        end
+ 
+
+        else if (stall_x ==  1'b0)
+          begin
+
+             if(eie_delay[0])
+               ie              <= eie;
+           
+             eie_delay         <= {1'b0, eie_delay[ 10:1]};
+
+             if (eret_q_x ==  1'b1) begin
+                
+                eie_delay[ 10] <=  1'b1;
+                eie_delay[ 10-1:0] <= 0;
+             end
+           
+  
+                
+                
+                       
+
+
+            else if (csr_write_enable ==  1'b1)
+            begin
+                
+                if (csr ==  4 'h0)
+                begin
+                    ie  <= csr_write_data[0];
+                    eie <= csr_write_data[1];
+  
+                      
+
+
+                end
+                if (csr ==  4 'h2)
+                    ip  <= asserted & ~csr_write_data[interrupts-1:0];
+            end
+        end
+    end
+end
+    end
+endgenerate
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	 
+
+ 
+
+
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+  
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+  
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+  
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+  
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+  
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+  
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+  
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+ 
+
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+  
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+  
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+ 
+
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+  
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+  
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+  
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+  
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+  
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+  
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+  
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+  
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+  
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+  
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+  
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+  
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+  
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+
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+  
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+  
+
+ 
+ 
+                    
+
+  
+                    
+
+
+
+  
+
+
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+  
+
+  
+
+
+
+  
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+  
+
+
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+  
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+  
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+
+
+  
+ 
+
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+  
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+  
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+ 
+
+ 
+
+
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+  
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+  
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+ 
+ 
+ 
+
+
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+
+
+  
+
+  
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+  
+ 
+ 
+
+ 
+
+
+ 
+
+
+  
+
+  
+
+ 
+ 
+ 
+
+
+
+
+
+  
+ 
+
+
+  
+ 
+
+
+  
+ 
+
+
+
+
+  
+
+  
+
+ 
+
+  
+ 
+
+
+
+
+  
+
+
+
+  
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+
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+  
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+  
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+  
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+  
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+  
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+  
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+  
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+  
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+  
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+  
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+
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+  
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+  
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+  
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+  
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+  
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+  
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+
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+  
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+  
+
+  
+
+ 
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
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+  
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+  
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+ 
+
+  
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+  
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+  
+
+  
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+  
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+  
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+ 
+
+  
+
+  
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+  
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+  
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+  
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+  
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+  
+
+  
+
+  
+
+ 
+ 
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+  
+
+  
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+
+  
+
+  
+
+
+
+  
+
+  
+
+ 
+ 
+ 
+
+
+
+
+
+
+
+
+
+  
+
+  
+
+  
+
+
+
+
+
+
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+
+
+  
+
+
+
+
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+ 
+
+
+
+
+
+
+
+
+module lm32_top_medium_icache_debug (
+    
+    clk_i,
+    rst_i,
+    
+
+    interrupt,
+
+    
+  
+    
+    
+
+     
+  
+
+    
+    I_DAT_I,
+    I_ACK_I,
+    I_ERR_I,
+    I_RTY_I,
+ 
+
+    
+    D_DAT_I,
+    D_ACK_I,
+    D_ERR_I,
+    D_RTY_I,
+    
+      
+    
+    
+    
+    
+
+    
+  
+
+    
+    I_DAT_O,
+    I_ADR_O,
+    I_CYC_O,
+    I_SEL_O,
+    I_STB_O,
+    I_WE_O,
+    I_CTI_O,
+    I_LOCK_O,
+    I_BTE_O,
+ 
+
+    
+    D_DAT_O,
+    D_ADR_O,
+    D_CYC_O,
+    D_SEL_O,
+    D_STB_O,
+    D_WE_O,
+    D_CTI_O,
+    D_LOCK_O,
+    D_BTE_O
+    );
+
+parameter eba_reset = 32'h00000000;
+parameter sdb_address = 32'h00000000;
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+
+
+input [ (32-1):0] interrupt;          
+
+
+  
+               
+                             
+
+    
+
+  
+
+input [ (32-1):0] I_DAT_I;                 
+input I_ACK_I;                                  
+input I_ERR_I;                                  
+input I_RTY_I;                                  
+ 
+
+
+input [ (32-1):0] D_DAT_I;                 
+input D_ACK_I;                                  
+input D_ERR_I;                                  
+input D_RTY_I;                                  
+
+
+
+
+
+  
+                               
+   
+       
+     
+           
+    
+           
+    
+
+
+
+  
+
+output [ (32-1):0] I_DAT_O;                
+wire   [ (32-1):0] I_DAT_O;
+output [ (32-1):0] I_ADR_O;                
+wire   [ (32-1):0] I_ADR_O;
+output I_CYC_O;                                 
+wire   I_CYC_O;
+output [ (4-1):0] I_SEL_O;         
+wire   [ (4-1):0] I_SEL_O;
+output I_STB_O;                                 
+wire   I_STB_O;
+output I_WE_O;                                  
+wire   I_WE_O;
+output [ (3-1):0] I_CTI_O;               
+wire   [ (3-1):0] I_CTI_O;
+output I_LOCK_O;                                
+wire   I_LOCK_O;
+output [ (2-1):0] I_BTE_O;               
+wire   [ (2-1):0] I_BTE_O;
+ 
+
+
+output [ (32-1):0] D_DAT_O;                
+wire   [ (32-1):0] D_DAT_O;
+output [ (32-1):0] D_ADR_O;                
+wire   [ (32-1):0] D_ADR_O;
+output D_CYC_O;                                 
+wire   D_CYC_O;
+output [ (4-1):0] D_SEL_O;         
+wire   [ (4-1):0] D_SEL_O;
+output D_STB_O;                                 
+wire   D_STB_O;
+output D_WE_O;                                  
+wire   D_WE_O;
+output [ (3-1):0] D_CTI_O;               
+wire   [ (3-1):0] D_CTI_O;
+output D_LOCK_O;                                
+wire   D_LOCK_O;
+output [ (2-1):0] D_BTE_O;               
+wire   [ (2-1):0] D_BTE_O;
+  
+
+
+
+ 
+  
+
+
+wire [ 7:0] jtag_reg_d;
+wire [ 7:0] jtag_reg_q;
+wire jtag_update;
+wire [2:0] jtag_reg_addr_d;
+wire [2:0] jtag_reg_addr_q;
+wire jtck;
+wire jrstn;
+ 
+
+
+
+  
+
+                     
+                             
+                            
+                   
+                                 
+ 
+                                 
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+   
+
+lm32_cpu_medium_icache_debug 
+	#(
+		.eba_reset(eba_reset),
+    .sdb_address(sdb_address)
+	) cpu (
+    
+    .clk_i                 (clk_i),
+  
+                   
+
+
+    .rst_i                 (rst_i),
+    
+  
+
+    .interrupt             (interrupt),
+ 
+
+    
+  
+               
+             
+
+     
+  
+
+    
+    .jtag_clk              (jtck),
+    .jtag_update           (jtag_update),
+    .jtag_reg_q            (jtag_reg_q),
+    .jtag_reg_addr_q       (jtag_reg_addr_q),
+ 
+
+  
+
+     
+    .I_DAT_I               (I_DAT_I),
+    .I_ACK_I               (I_ACK_I),
+    .I_ERR_I               (I_ERR_I),
+    .I_RTY_I               (I_RTY_I),
+ 
+
+    
+    .D_DAT_I               (D_DAT_I),
+    .D_ACK_I               (D_ACK_I),
+    .D_ERR_I               (D_ERR_I),
+    .D_RTY_I               (D_RTY_I),
+    
+  
+                  
+            
+           
+                 
+                
+ 
+                
+
+
+
+  
+
+    .jtag_reg_d            (jtag_reg_d),
+    .jtag_reg_addr_d       (jtag_reg_addr_d),
+ 
+
+      
+                
+               
+            
+            
+
+    
+  
+
+    
+    .I_DAT_O               (I_DAT_O),
+    .I_ADR_O               (I_ADR_O),
+    .I_CYC_O               (I_CYC_O),
+    .I_SEL_O               (I_SEL_O),
+    .I_STB_O               (I_STB_O),
+    .I_WE_O                (I_WE_O),
+    .I_CTI_O               (I_CTI_O),
+    .I_LOCK_O              (I_LOCK_O),
+    .I_BTE_O               (I_BTE_O),
+     
+
+    
+    .D_DAT_O               (D_DAT_O),
+    .D_ADR_O               (D_ADR_O),
+    .D_CYC_O               (D_CYC_O),
+    .D_SEL_O               (D_SEL_O),
+    .D_STB_O               (D_STB_O),
+    .D_WE_O                (D_WE_O),
+    .D_CTI_O               (D_CTI_O),
+    .D_LOCK_O              (D_LOCK_O),
+    .D_BTE_O               (D_BTE_O)
+    );
+   
+  
+		   
+
+jtag_cores jtag_cores (
+    
+    .reg_d                 (jtag_reg_d),
+    .reg_addr_d            (jtag_reg_addr_d),
+    
+    .reg_update            (jtag_update),
+    .reg_q                 (jtag_reg_q),
+    .reg_addr_q            (jtag_reg_addr_q),
+    .jtck                  (jtck),
+    .jrstn                 (jrstn)
+    );
+ 
+        
+   
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+           
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_mc_arithmetic_medium_icache_debug (
+    
+    clk_i,
+    rst_i,
+    stall_d,
+    kill_x,
+  
+    
+    
+
+
+  
+    
+
+
+  
+    
+    
+    
+
+
+    operand_0_d,
+    operand_1_d,
+    
+    result_x,
+  
+    
+
+
+    stall_request_x
+    );
+
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+input stall_d;                                  
+input kill_x;                                   
+  
+                                  
+                                 
+
+
+  
+                                
+
+
+  
+                              
+                             
+                             
+
+
+input [ (32-1):0] operand_0_d;
+input [ (32-1):0] operand_1_d;
+
+
+
+
+
+output [ (32-1):0] result_x;               
+reg    [ (32-1):0] result_x;
+  
+                         
+    
+
+
+output stall_request_x;                         
+wire   stall_request_x;
+
+
+
+
+
+reg [ (32-1):0] p;                         
+reg [ (32-1):0] a;
+reg [ (32-1):0] b;
+  
+  
+
+
+
+reg [ 2:0] state;                 
+reg [5:0] cycles;                               
+
+  
+                               
+                                 
+
+
+
+
+
+
+
+
+assign stall_request_x = state !=  3'b000;
+
+  
+
+      
+
+
+
+  
+
+       
+
+
+
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        cycles <= {6{1'b0}};
+        p <= { 32{1'b0}};
+        a <= { 32{1'b0}};
+        b <= { 32{1'b0}};
+  
+          
+
+
+  
+          
+
+
+        result_x <= { 32{1'b0}};
+        state <=  3'b000;
+    end
+    else
+    begin
+  
+          
+
+
+        case (state)
+         3'b000:
+        begin
+            if (stall_d ==  1'b0)                 
+            begin          
+                cycles <=  32;
+                p <= 32'b0;
+                a <= operand_0_d;
+                b <= operand_1_d;                    
+  
+                   
+                      
+                   
+                      
+
+                    
+  
+                   
+                      
+
+
+  
+                   
+                
+                      
+                      
+                      
+                      
+                      
+                
+                   
+                
+                      
+                      
+                      
+                      
+                      
+                
+
+
+            end            
+        end
+  
+        
+        
+               
+            
+                  
+                   
+            
+             
+            
+                   
+                   
+            
+              
+                   
+            
+                
+                    
+                  
+            
+                
+        
+        
+        
+               
+            
+                  
+                   
+            
+             
+            
+                   
+                   
+            
+              
+                   
+            
+                
+                    
+                  
+            
+                
+        
+
+        
+  
+        
+        
+               
+                    
+               
+               
+              
+                   
+                  
+                
+        
+
+     
+  
+        
+               
+               
+              
+                   
+                  
+                
+        
+        
+               
+               
+              
+                   
+                  
+                
+        
+
+   
+        endcase
+    end
+end 
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_cpu_medium_icache_debug (
+    
+    clk_i,
+  
+    
+
+
+    rst_i,
+  
+    
+
+
+  
+   
+   
+   
+   
+   
+   
+
+
+
+    
+  
+
+    interrupt,
+ 
+
+    
+  
+    
+    
+
+     
+  
+
+    
+    jtag_clk,
+    jtag_update, 
+    jtag_reg_q,
+    jtag_reg_addr_q,
+ 
+
+  
+
+    
+    I_DAT_I,
+    I_ACK_I,
+    I_ERR_I,
+    I_RTY_I,
+ 
+
+    
+    D_DAT_I,
+    D_ACK_I,
+    D_ERR_I,
+    D_RTY_I,
+    
+  
+    
+    
+    
+    
+    
+ 
+    
+
+
+
+  
+
+    jtag_reg_d,
+    jtag_reg_addr_d,
+ 
+
+      
+    
+    
+    
+    
+
+    
+  
+
+    
+    I_DAT_O,
+    I_ADR_O,
+    I_CYC_O,
+    I_SEL_O,
+    I_STB_O,
+    I_WE_O,
+    I_CTI_O,
+    I_LOCK_O,
+    I_BTE_O,
+ 
+ 
+  
+    
+    
+    
+    
+    
+    
+    
+    
+           
+
+
+		 
+		 
+    
+    D_DAT_O,
+    D_ADR_O,
+    D_CYC_O,
+    D_SEL_O,
+    D_STB_O,
+    D_WE_O,
+    D_CTI_O,
+    D_LOCK_O,
+    D_BTE_O
+
+		 
+    );
+
+
+
+
+
+parameter eba_reset =  32'h00000000;                           
+  
+
+parameter deba_reset =  32'h10000000;                         
+ 
+
+parameter sdb_address =   32'h00000000;
+
+  
+
+parameter icache_associativity =  1;     
+parameter icache_sets =  256;                       
+parameter icache_bytes_per_line =  16;   
+parameter icache_base_address =  32'h0;       
+parameter icache_limit =  32'h7fffffff;                     
+ 
+       
+                         
+     
+         
+                       
+
+
+
+  
+        
+                          
+      
+          
+                        
+
+
+parameter dcache_associativity = 1;    
+parameter dcache_sets = 512;                      
+parameter dcache_bytes_per_line = 16;  
+parameter dcache_base_address = 0;      
+parameter dcache_limit = 0;                    
+ 
+
+
+  
+
+parameter watchpoints =  32'h4;                       
+ 
+   
+
+
+  
+                          
+
+
+parameter breakpoints = 0;
+ 
+
+
+  
+
+parameter interrupts =  32;                         
+ 
+   
+
+
+
+
+
+
+
+input clk_i;                                    
+  
+                                   
+
+    
+input rst_i;                                    
+
+  
+
+input [ (32-1):0] interrupt;          
+ 
+
+
+  
+               
+                             
+
+    
+
+  
+ 
+input jtag_clk;                                 
+input jtag_update;                              
+input [ 7:0] jtag_reg_q;              
+input [2:0] jtag_reg_addr_q;
+ 
+
+
+  
+
+input [ (32-1):0] I_DAT_I;                 
+input I_ACK_I;                                  
+input I_ERR_I;                                  
+input I_RTY_I;                                  
+ 
+
+
+input [ (32-1):0] D_DAT_I;                 
+input D_ACK_I;                                  
+input D_ERR_I;                                  
+input D_RTY_I;                                  
+
+
+
+
+
+  
+    
+     
+
+
+   
+   
+  
+                   
+     
+                           
+    
+                          
+    
+                 
+     
+                               
+    
+ 
+                               
+    
+
+
+
+
+  
+
+output [ 7:0] jtag_reg_d;
+wire   [ 7:0] jtag_reg_d;
+output [2:0] jtag_reg_addr_d;
+wire   [2:0] jtag_reg_addr_d;
+ 
+
+
+  
+                               
+   
+       
+     
+           
+    
+           
+    
+
+
+
+  
+
+output [ (32-1):0] I_DAT_O;                
+wire   [ (32-1):0] I_DAT_O;
+output [ (32-1):0] I_ADR_O;                
+wire   [ (32-1):0] I_ADR_O;
+output I_CYC_O;                                 
+wire   I_CYC_O;
+output [ (4-1):0] I_SEL_O;         
+wire   [ (4-1):0] I_SEL_O;
+output I_STB_O;                                 
+wire   I_STB_O;
+output I_WE_O;                                  
+wire   I_WE_O;
+output [ (3-1):0] I_CTI_O;               
+wire   [ (3-1):0] I_CTI_O;
+output I_LOCK_O;                                
+wire   I_LOCK_O;
+output [ (2-1):0] I_BTE_O;               
+wire   [ (2-1):0] I_BTE_O;
+ 
+
+
+output [ (32-1):0] D_DAT_O;                
+wire   [ (32-1):0] D_DAT_O;
+output [ (32-1):0] D_ADR_O;                
+wire   [ (32-1):0] D_ADR_O;
+output D_CYC_O;                                 
+wire   D_CYC_O;
+output [ (4-1):0] D_SEL_O;         
+wire   [ (4-1):0] D_SEL_O;
+output D_STB_O;                                 
+wire   D_STB_O;
+output D_WE_O;                                  
+wire   D_WE_O;
+output [ (3-1):0] D_CTI_O;               
+wire   [ (3-1):0] D_CTI_O;
+output D_LOCK_O;                                
+wire   D_LOCK_O;
+output [ (2-1):0] D_BTE_O;               
+wire   [ (2-1):0] D_BTE_O;
+
+  
+      
+     
+       
+      
+             
+
+
+   
+
+
+
+
+
+
+  
+
+reg valid_a;                                    
+ 
+
+reg valid_f;                                    
+reg valid_d;                                    
+reg valid_x;                                    
+reg valid_m;                                    
+reg valid_w;                                    
+   
+wire q_x;
+wire [ (32-1):0] immediate_d;              
+wire load_d;                                    
+reg load_x;                                     
+reg load_m;
+wire load_q_x;
+wire store_q_x;
+wire q_m;
+wire load_q_m;
+wire store_q_m;
+wire store_d;                                   
+reg store_x;
+reg store_m;
+wire [ 1:0] size_d;                   
+reg [ 1:0] size_x;
+wire branch_d;                                  
+wire branch_predict_d;                          
+wire branch_predict_taken_d;                    
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d;   
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_d;
+wire bi_unconditional;
+wire bi_conditional;
+reg branch_x;                                   
+reg branch_predict_x;
+reg branch_predict_taken_x;
+reg branch_m;
+reg branch_predict_m;
+reg branch_predict_taken_m;
+wire branch_mispredict_taken_m;                 
+wire branch_flushX_m;                           
+wire branch_reg_d;                              
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset_d;            
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_x;             
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_m;
+wire [ 0:0] d_result_sel_0_d; 
+wire [ 1:0] d_result_sel_1_d; 
+
+wire x_result_sel_csr_d;                        
+reg x_result_sel_csr_x;
+  
+ 
+                    
+ 
+
+
+      
+                       
+ 
+
+
+  
+
+wire x_result_sel_sext_d;                       
+reg x_result_sel_sext_x;
+ 
+
+wire x_result_sel_logic_d;                      
+  
+                        
+ 
+
+
+wire x_result_sel_add_d;                        
+reg x_result_sel_add_x;
+wire m_result_sel_compare_d;                    
+reg m_result_sel_compare_x;
+reg m_result_sel_compare_m;
+  
+
+wire m_result_sel_shift_d;                      
+reg m_result_sel_shift_x;
+reg m_result_sel_shift_m;
+ 
+
+wire w_result_sel_load_d;                       
+reg w_result_sel_load_x;
+reg w_result_sel_load_m;
+reg w_result_sel_load_w;
+  
+
+wire w_result_sel_mul_d;                        
+reg w_result_sel_mul_x;
+reg w_result_sel_mul_m;
+reg w_result_sel_mul_w;
+ 
+
+wire x_bypass_enable_d;                         
+reg x_bypass_enable_x;                          
+wire m_bypass_enable_d;                         
+reg m_bypass_enable_x;                          
+reg m_bypass_enable_m;
+wire sign_extend_d;                             
+reg sign_extend_x;
+wire write_enable_d;                            
+reg write_enable_x;
+wire write_enable_q_x;
+reg write_enable_m;
+wire write_enable_q_m;
+reg write_enable_w;
+wire write_enable_q_w;
+wire read_enable_0_d;                           
+wire [ (5-1):0] read_idx_0_d;          
+wire read_enable_1_d;                           
+wire [ (5-1):0] read_idx_1_d;          
+wire [ (5-1):0] write_idx_d;           
+reg [ (5-1):0] write_idx_x;            
+reg [ (5-1):0] write_idx_m;
+reg [ (5-1):0] write_idx_w;
+wire [ (5-1):0] csr_d;                     
+reg  [ (5-1):0] csr_x;                  
+wire [ (3-1):0] condition_d;         
+reg [ (3-1):0] condition_x;          
+  
+
+wire break_d;                                   
+reg break_x;                                    
+ 
+
+wire scall_d;                                   
+reg scall_x;    
+wire eret_d;                                    
+reg eret_x;
+wire eret_q_x;
+  
+ 
+ 
+
+
+  
+
+wire bret_d;                                    
+reg bret_x;
+wire bret_q_x;
+  
+ 
+ 
+
+
+ 
+
+wire csr_write_enable_d;                        
+reg csr_write_enable_x;
+wire csr_write_enable_q_x;
+  
+       
+
+
+
+  
+                                
+ 
+ 
+  
+
+
+
+reg [ (32-1):0] d_result_0;                
+reg [ (32-1):0] d_result_1;                
+reg [ (32-1):0] x_result;                  
+reg [ (32-1):0] m_result;                  
+reg [ (32-1):0] w_result;                  
+
+reg [ (32-1):0] operand_0_x;               
+reg [ (32-1):0] operand_1_x;               
+reg [ (32-1):0] store_operand_x;           
+reg [ (32-1):0] operand_m;                 
+reg [ (32-1):0] operand_w;                 
+
+
+  
+
+reg [ (32-1):0] reg_data_live_0;          
+reg [ (32-1):0] reg_data_live_1;  
+reg use_buf;                                    
+reg [ (32-1):0] reg_data_buf_0;
+reg [ (32-1):0] reg_data_buf_1;
+ 
+
+  
+
+ 
+     
+
+
+wire [ (32-1):0] reg_data_0;               
+wire [ (32-1):0] reg_data_1;               
+reg [ (32-1):0] bypass_data_0;             
+reg [ (32-1):0] bypass_data_1;             
+wire reg_write_enable_q_w;
+
+reg interlock;                                  
+
+wire stall_a;                                   
+wire stall_f;                                   
+wire stall_d;                                   
+wire stall_x;                                   
+wire stall_m;                                   
+
+
+wire adder_op_d;                                
+reg adder_op_x;                                 
+reg adder_op_x_n;                               
+wire [ (32-1):0] adder_result_x;           
+wire adder_overflow_x;                          
+wire adder_carry_n_x;                           
+
+
+wire [ 3:0] logic_op_d;           
+reg [ 3:0] logic_op_x;            
+wire [ (32-1):0] logic_result_x;           
+
+  
+
+
+wire [ (32-1):0] sextb_result_x;           
+wire [ (32-1):0] sexth_result_x;           
+wire [ (32-1):0] sext_result_x;            
+ 
+
+
+
+  
+
+  
+                                   
+                                     
+
+
+wire direction_d;                               
+reg direction_x;                                        
+wire [ (32-1):0] shifter_result_m;         
+ 
+
+  
+                               
+ 
+                              
+ 
+
+
+  
+           
+
+
+
+
+  
+
+wire [ (32-1):0] multiplier_result_w;      
+ 
+
+  
+                                 
+ 
+
+
+
+
+  
+                                   
+ 
+ 
+ 
+                           
+
+
+
+
+  
+                         
+  
+
+
+
+
+  
+
+wire [ (32-1):0] interrupt_csr_read_data_x;
+ 
+
+wire [ (32-1):0] cfg;                      
+wire [ (32-1):0] cfg2;                     
+  
+                          
+
+
+reg [ (32-1):0] csr_read_data_x;           
+
+
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;                       
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;                       
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;                       
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;                       
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;                       
+  
+                          
+
+
+  
+
+wire [ (32-1):0] instruction_f;     
+ 
+
+
+
+wire [ (32-1):0] instruction_d;     
+  
+
+wire iflush;                                    
+wire icache_stall_request;                      
+wire icache_restart_request;                    
+wire icache_refill_request;                     
+wire icache_refilling;                          
+ 
+
+
+
+  
+                                   
+                                     
+                       
+                     
+                      
+                           
+
+
+wire [ (32-1):0] load_data_w;              
+wire stall_wb_load;                             
+
+
+  
+
+  
+
+wire [ (32-1):0] jtx_csr_read_data;        
+wire [ (32-1):0] jrx_csr_read_data;        
+ 
+
+  
+
+wire jtag_csr_write_enable;                     
+wire [ (32-1):0] jtag_csr_write_data;      
+wire [ (5-1):0] jtag_csr;                  
+wire jtag_read_enable;                          
+wire [ 7:0] jtag_read_data;
+wire jtag_write_enable;
+wire [ 7:0] jtag_write_data;
+wire [ (32-1):0] jtag_address;
+wire jtag_access_complete;
+ 
+
+  
+
+wire jtag_break;                                
+ 
+
+ 
+
+
+
+wire raw_x_0;                                   
+wire raw_x_1;                                   
+wire raw_m_0;                                   
+wire raw_m_1;                                   
+wire raw_w_0;                                   
+wire raw_w_1;                                   
+
+
+wire cmp_zero;                                  
+wire cmp_negative;                              
+wire cmp_overflow;                              
+wire cmp_carry_n;                               
+reg condition_met_x;                            
+reg condition_met_m;
+      
+                             
+
+
+wire branch_taken_m;                            
+
+wire kill_f;                                    
+wire kill_d;                                    
+wire kill_x;                                    
+wire kill_m;                                    
+wire kill_w;                                    
+
+reg [ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8] eba;                 
+  
+
+reg [ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8] deba;                
+ 
+
+reg [ (3-1):0] eid_x;                      
+  
+                        
+                        
+
+
+
+  
+
+  
+
+wire dc_ss;                                     
+ 
+
+wire dc_re;                                     
+wire bp_match;
+wire wp_match;
+wire exception_x;                               
+reg exception_m;                                
+wire debug_exception_x;                         
+reg debug_exception_m;
+reg debug_exception_w;
+wire debug_exception_q_w;
+wire non_debug_exception_x;                     
+reg non_debug_exception_m;
+reg non_debug_exception_w;
+wire non_debug_exception_q_w;
+ 
+                                
+ 
+ 
+ 
+
+
+
+  
+
+  
+ 
+wire reset_exception;                           
+ 
+
+  
+                            
+
+
+ 
+
+  
+
+wire interrupt_exception;                       
+ 
+
+  
+
+wire breakpoint_exception;                      
+wire watchpoint_exception;                      
+ 
+
+  
+     
+   
+            
+                   
+
+
+  
+                   
+
+
+wire system_call_exception;                     
+
+  
+                         
+
+
+
+   
+    
+
+
+     
+  
+                          
+   
+            
+   
+                          
+   
+
+    	      
+    	      
+    	      
+    	      
+    	      
+    	      
+   
+   
+
+
+   
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+lm32_instruction_unit_medium_icache_debug #(
+    .eba_reset              (eba_reset),
+    .associativity          (icache_associativity),
+    .sets                   (icache_sets),
+    .bytes_per_line         (icache_bytes_per_line),
+    .base_address           (icache_base_address),
+    .limit                  (icache_limit)
+  ) instruction_unit (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    
+    .stall_a                (stall_a),
+    .stall_f                (stall_f),
+    .stall_d                (stall_d),
+    .stall_x                (stall_x),
+    .stall_m                (stall_m),
+    .valid_f                (valid_f),
+    .valid_d                (valid_d),
+    .kill_f                 (kill_f),
+    .branch_predict_taken_d (branch_predict_taken_d),
+    .branch_predict_address_d (branch_predict_address_d),
+      
+             
+            
+
+
+    .exception_m            (exception_m),
+    .branch_taken_m         (branch_taken_m),
+    .branch_mispredict_taken_m (branch_mispredict_taken_m),
+    .branch_target_m        (branch_target_m),
+  
+
+    .iflush                 (iflush),
+ 
+
+  
+     
+      
+           
+
+        
+  
+
+    
+    .i_dat_i                (I_DAT_I),
+    .i_ack_i                (I_ACK_I),
+    .i_err_i                (I_ERR_I),
+    .i_rty_i                (I_RTY_I),
+ 
+
+  
+
+    .jtag_read_enable       (jtag_read_enable),
+    .jtag_write_enable      (jtag_write_enable),
+    .jtag_write_data        (jtag_write_data),
+    .jtag_address           (jtag_address),
+ 
+
+    
+    
+    .pc_f                   (pc_f),
+    .pc_d                   (pc_d),
+    .pc_x                   (pc_x),
+    .pc_m                   (pc_m),
+    .pc_w                   (pc_w),
+  
+
+    .icache_stall_request   (icache_stall_request),
+    .icache_restart_request (icache_restart_request),
+    .icache_refill_request  (icache_refill_request),
+    .icache_refilling       (icache_refilling),
+ 
+
+  
+
+    
+    .i_dat_o                (I_DAT_O),
+    .i_adr_o                (I_ADR_O),
+    .i_cyc_o                (I_CYC_O),
+    .i_sel_o                (I_SEL_O),
+    .i_stb_o                (I_STB_O),
+    .i_we_o                 (I_WE_O),
+    .i_cti_o                (I_CTI_O),
+    .i_lock_o               (I_LOCK_O),
+    .i_bte_o                (I_BTE_O),
+ 
+ 
+
+  
+    
+    
+    
+
+
+		      	      
+  
+
+    .jtag_read_data         (jtag_read_data),
+    .jtag_access_complete   (jtag_access_complete),
+ 
+
+  
+                
+
+
+  
+
+    .instruction_f          (instruction_f),
+ 
+
+
+		      
+    .instruction_d          (instruction_d)
+
+
+		      
+    );
+
+
+lm32_decoder_medium_icache_debug decoder (
+    
+    .instruction            (instruction_d),
+    
+    .d_result_sel_0         (d_result_sel_0_d),
+    .d_result_sel_1         (d_result_sel_1_d),
+    .x_result_sel_csr       (x_result_sel_csr_d),
+  
+      
+
+
+      
+         
+
+
+  
+
+    .x_result_sel_sext      (x_result_sel_sext_d),
+ 
+    
+    .x_result_sel_logic     (x_result_sel_logic_d),
+  
+          
+
+
+    .x_result_sel_add       (x_result_sel_add_d),
+    .m_result_sel_compare   (m_result_sel_compare_d),
+  
+
+    .m_result_sel_shift     (m_result_sel_shift_d),  
+ 
+    
+    .w_result_sel_load      (w_result_sel_load_d),
+  
+
+    .w_result_sel_mul       (w_result_sel_mul_d),
+ 
+
+    .x_bypass_enable        (x_bypass_enable_d),
+    .m_bypass_enable        (m_bypass_enable_d),
+    .read_enable_0          (read_enable_0_d),
+    .read_idx_0             (read_idx_0_d),
+    .read_enable_1          (read_enable_1_d),
+    .read_idx_1             (read_idx_1_d),
+    .write_enable           (write_enable_d),
+    .write_idx              (write_idx_d),
+    .immediate              (immediate_d),
+    .branch_offset          (branch_offset_d),
+    .load                   (load_d),
+    .store                  (store_d),
+    .size                   (size_d),
+    .sign_extend            (sign_extend_d),
+    .adder_op               (adder_op_d),
+    .logic_op               (logic_op_d),
+  
+
+    .direction              (direction_d),
+ 
+
+  
+                 
+                
+
+
+  
+                   
+
+
+  
+                     
+                    
+
+
+    .branch                 (branch_d),
+    .bi_unconditional       (bi_unconditional),
+    .bi_conditional         (bi_conditional),
+    .branch_reg             (branch_reg_d),
+    .condition              (condition_d),
+  
+
+    .break_opcode           (break_d),
+ 
+
+    .scall                  (scall_d),
+    .eret                   (eret_d),
+  
+
+    .bret                   (bret_d),
+ 
+
+  
+                
+
+
+    .csr_write_enable       (csr_write_enable_d)
+    ); 
+
+
+lm32_load_store_unit_medium_icache_debug #(
+    .associativity          (dcache_associativity),
+    .sets                   (dcache_sets),
+    .bytes_per_line         (dcache_bytes_per_line),
+    .base_address           (dcache_base_address),
+    .limit                  (dcache_limit)
+  ) load_store_unit (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    
+    .stall_a                (stall_a),
+    .stall_x                (stall_x),
+    .stall_m                (stall_m),
+    .kill_x                 (kill_x),
+    .kill_m                 (kill_m),
+    .exception_m            (exception_m),
+    .store_operand_x        (store_operand_x),
+    .load_store_address_x   (adder_result_x),
+    .load_store_address_m   (operand_m),
+    .load_store_address_w   (operand_w[1:0]),
+    .load_x                 (load_x),
+    .store_x                (store_x),
+    .load_q_x               (load_q_x),
+    .store_q_x              (store_q_x),
+    .load_q_m               (load_q_m),
+    .store_q_m              (store_q_m),
+    .sign_extend_x          (sign_extend_x),
+    .size_x                 (size_x),
+  
+                     
+
+
+
+  
+    
+    
+    
+    
+    
+    
+    
+
+
+		     
+    
+    .d_dat_i                (D_DAT_I),
+    .d_ack_i                (D_ACK_I),
+    .d_err_i                (D_ERR_I),
+    .d_rty_i                (D_RTY_I),
+    
+    
+  
+      
+     
+       
+           
+
+    
+    .load_data_w            (load_data_w),
+    .stall_wb_load          (stall_wb_load),
+    
+    .d_dat_o                (D_DAT_O),
+    .d_adr_o                (D_ADR_O),
+    .d_cyc_o                (D_CYC_O),
+    .d_sel_o                (D_SEL_O),
+    .d_stb_o                (D_STB_O),
+    .d_we_o                 (D_WE_O),
+    .d_cti_o                (D_CTI_O),
+    .d_lock_o               (D_LOCK_O),
+    .d_bte_o                (D_BTE_O)
+    );      
+       
+
+lm32_adder adder (
+    
+    .adder_op_x             (adder_op_x),
+    .adder_op_x_n           (adder_op_x_n),
+    .operand_0_x            (operand_0_x),
+    .operand_1_x            (operand_1_x),
+    
+    .adder_result_x         (adder_result_x),
+    .adder_carry_n_x        (adder_carry_n_x),
+    .adder_overflow_x       (adder_overflow_x)
+    );
+
+
+lm32_logic_op logic_op (
+    
+    .logic_op_x             (logic_op_x),
+    .operand_0_x            (operand_0_x),
+
+    .operand_1_x            (operand_1_x),
+    
+    .logic_result_x         (logic_result_x)
+    );
+              
+  
+
+
+lm32_shifter shifter (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    .stall_x                (stall_x),
+    .direction_x            (direction_x),
+    .sign_extend_x          (sign_extend_x),
+    .operand_0_x            (operand_0_x),
+    .operand_1_x            (operand_1_x),
+    
+    .shifter_result_m       (shifter_result_m)
+    );
+ 
+
+
+  
+
+
+lm32_multiplier multiplier (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    .stall_x                (stall_x),
+    .stall_m                (stall_m),
+    .operand_0              (d_result_0),
+    .operand_1              (d_result_1),
+    
+    .result                 (multiplier_result_w)    
+    );
+ 
+
+
+  
+
+  
+    
+                      
+                      
+                    
+                     
+                   
+                   
+                  
+
+         
+                 
+
+ 
+               
+              
+              
+    
+                
+                
+    
+                   
+                   
+           
+
+            
+    
+
+
+              
+  
+
+
+lm32_interrupt_medium_icache_debug interrupt_unit (
+    
+    .clk_i                  (clk_i), 
+    .rst_i                  (rst_i),
+    
+    .interrupt              (interrupt),
+    
+    .stall_x                (stall_x),
+  
+
+    .non_debug_exception    (non_debug_exception_q_w), 
+    .debug_exception        (debug_exception_q_w),
+ 
+                   
+
+
+    .eret_q_x               (eret_q_x),
+  
+
+    .bret_q_x               (bret_q_x),
+ 
+
+    .csr                    (csr_x),
+    .csr_write_data         (operand_1_x),
+    .csr_write_enable       (csr_write_enable_q_x),
+    
+    .interrupt_exception    (interrupt_exception),
+    
+    .csr_read_data          (interrupt_csr_read_data_x)
+    );
+ 
+
+
+  
+      
+      
+        
+   
+
+
+
+
+  
+
+
+lm32_jtag_medium_icache_debug jtag (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    
+    .jtag_clk               (jtag_clk),
+    .jtag_update            (jtag_update),
+    .jtag_reg_q             (jtag_reg_q),
+    .jtag_reg_addr_q        (jtag_reg_addr_q),
+    
+  
+
+    .csr                    (csr_x),
+    .csr_write_data         (operand_1_x),
+    .csr_write_enable       (csr_write_enable_q_x),
+    .stall_x                (stall_x),
+ 
+
+  
+
+    .jtag_read_data         (jtag_read_data),
+    .jtag_access_complete   (jtag_access_complete),
+ 
+
+  
+
+    .exception_q_w          (debug_exception_q_w || non_debug_exception_q_w),
+ 
+    
+    
+    
+  
+
+    .jtx_csr_read_data      (jtx_csr_read_data),
+    .jrx_csr_read_data      (jrx_csr_read_data),
+ 
+
+  
+
+    .jtag_csr_write_enable  (jtag_csr_write_enable),
+    .jtag_csr_write_data    (jtag_csr_write_data),
+    .jtag_csr               (jtag_csr),
+    .jtag_read_enable       (jtag_read_enable),
+    .jtag_write_enable      (jtag_write_enable),
+    .jtag_write_data        (jtag_write_data),
+    .jtag_address           (jtag_address),
+ 
+
+  
+
+    .jtag_break             (jtag_break),
+    .jtag_reset             (reset_exception),
+ 
+
+    
+    .jtag_reg_d             (jtag_reg_d),
+    .jtag_reg_addr_d        (jtag_reg_addr_d)
+    );
+ 
+
+
+  
+
+
+lm32_debug_medium_icache_debug #(
+    .breakpoints            (breakpoints),
+    .watchpoints            (watchpoints)
+  ) hw_debug (
+    
+    .clk_i                  (clk_i), 
+    .rst_i                  (rst_i),
+    .pc_x                   (pc_x),
+    .load_x                 (load_x),
+    .store_x                (store_x),
+    .load_store_address_x   (adder_result_x),
+    .csr_write_enable_x     (csr_write_enable_q_x),
+    .csr_write_data         (operand_1_x),
+    .csr_x                  (csr_x),
+   
+
+	        
+
+    .jtag_csr_write_enable  (jtag_csr_write_enable),
+    .jtag_csr_write_data    (jtag_csr_write_data),
+    .jtag_csr               (jtag_csr),
+	       
+
+	        
+      
+        
+                   
+	      
+
+ 
+
+  
+
+    .eret_q_x               (eret_q_x),
+    .bret_q_x               (bret_q_x),
+    .stall_x                (stall_x),
+    .exception_x            (exception_x),
+    .q_x                    (q_x),
+  
+      
+
+
+ 
+
+    
+  
+
+    .dc_ss                  (dc_ss),
+ 
+
+    .dc_re                  (dc_re),
+    .bp_match               (bp_match),
+    .wp_match               (wp_match)
+    );
+ 
+
+
+
+
+  
+
+   
+           
+            
+          
+            
+
+
+             
+              
+    
+
+   wire [31:0] regfile_data_0, regfile_data_1;
+   reg [31:0]  w_result_d;
+   reg 	       regfile_raw_0, regfile_raw_0_nxt;
+   reg 	       regfile_raw_1, regfile_raw_1_nxt;
+   
+   
+             
+          
+
+   always @(reg_write_enable_q_w or write_idx_w or instruction_f)
+     begin
+	if (reg_write_enable_q_w
+	    && (write_idx_w == instruction_f[25:21]))
+	  regfile_raw_0_nxt = 1'b1;
+	else
+	  regfile_raw_0_nxt = 1'b0;
+	
+	if (reg_write_enable_q_w
+	    && (write_idx_w == instruction_f[20:16]))
+	  regfile_raw_1_nxt = 1'b1;
+	else
+	  regfile_raw_1_nxt = 1'b0;
+     end
+   
+   
+           
+           
+       
+
+   always @(regfile_raw_0 or w_result_d or regfile_data_0)
+     if (regfile_raw_0)
+       reg_data_live_0 = w_result_d;
+     else
+       reg_data_live_0 = regfile_data_0;
+   
+   
+           
+           
+       
+
+   always @(regfile_raw_1 or w_result_d or regfile_data_1)
+     if (regfile_raw_1)
+       reg_data_live_1 = w_result_d;
+     else
+       reg_data_live_1 = regfile_data_1;
+   
+   
+     
+
+   always @(posedge clk_i  )
+     if (rst_i ==  1'b1)
+       begin
+	  regfile_raw_0 <= 1'b0;
+	  regfile_raw_1 <= 1'b0;
+	  w_result_d <= 32'b0;
+       end
+     else
+       begin
+	  regfile_raw_0 <= regfile_raw_0_nxt;
+	  regfile_raw_1 <= regfile_raw_1_nxt;
+	  w_result_d <= w_result;
+       end
+   
+   
+      
+
+   
+   lm32_dp_ram
+     #(
+       
+       .addr_depth(1<<5),
+       .addr_width(5),
+       .data_width(32)
+       )
+   reg_0
+     (
+      
+      .clk_i	(clk_i),
+      .rst_i	(rst_i), 
+      .we_i	(reg_write_enable_q_w),
+      .wdata_i	(w_result),
+      .waddr_i	(write_idx_w),
+      .raddr_i	(instruction_f[25:21]),
+      
+      .rdata_o	(regfile_data_0)
+      );
+
+   lm32_dp_ram
+     #(
+       .addr_depth(1<<5),
+       .addr_width(5),
+       .data_width(32)
+       )
+   reg_1
+     (
+      
+      .clk_i	(clk_i),
+      .rst_i	(rst_i), 
+      .we_i	(reg_write_enable_q_w),
+      .wdata_i	(w_result),
+      .waddr_i	(write_idx_w),
+      .raddr_i	(instruction_f[20:16]),
+      
+      .rdata_o	(regfile_data_1)
+      );
+ 
+
+
+  
+   
+     
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+   
+     
+      
+      
+      
+      
+      
+      
+      
+        
+      
+       
+      
+      
+      
+   
+   
+     
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+   
+     
+      
+      
+      
+      
+      
+      
+      
+        
+      
+       
+      
+      
+      
+
+
+
+
+
+
+
+
+  
+
+
+assign reg_data_0 = use_buf ? reg_data_buf_0 : reg_data_live_0;
+assign reg_data_1 = use_buf ? reg_data_buf_1 : reg_data_live_1;
+ 
+
+  
+
+ 
+
+   
+   
+
+
+
+
+assign raw_x_0 = (write_idx_x == read_idx_0_d) && (write_enable_q_x ==  1'b1);
+assign raw_m_0 = (write_idx_m == read_idx_0_d) && (write_enable_q_m ==  1'b1);
+assign raw_w_0 = (write_idx_w == read_idx_0_d) && (write_enable_q_w ==  1'b1);
+assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x ==  1'b1);
+assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m ==  1'b1);
+assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w ==  1'b1);
+
+
+always @(*)
+begin
+    if (   (   (x_bypass_enable_x ==  1'b0)
+            && (   ((read_enable_0_d ==  1'b1) && (raw_x_0 ==  1'b1))
+                || ((read_enable_1_d ==  1'b1) && (raw_x_1 ==  1'b1))
+               )
+           )
+        || (   (m_bypass_enable_m ==  1'b0)
+            && (   ((read_enable_0_d ==  1'b1) && (raw_m_0 ==  1'b1))
+                || ((read_enable_1_d ==  1'b1) && (raw_m_1 ==  1'b1))
+               )
+           )
+       )
+        interlock =  1'b1;
+    else
+        interlock =  1'b0;
+end
+
+
+always @(*)
+begin
+    if (raw_x_0 ==  1'b1)        
+        bypass_data_0 = x_result;
+    else if (raw_m_0 ==  1'b1)
+        bypass_data_0 = m_result;
+    else if (raw_w_0 ==  1'b1)
+        bypass_data_0 = w_result;
+    else
+        bypass_data_0 = reg_data_0;
+end
+
+
+always @(*)
+begin
+    if (raw_x_1 ==  1'b1)
+        bypass_data_1 = x_result;
+    else if (raw_m_1 ==  1'b1)
+        bypass_data_1 = m_result;
+    else if (raw_w_1 ==  1'b1)
+        bypass_data_1 = w_result;
+    else
+        bypass_data_1 = reg_data_1;
+end
+
+   
+          
+       
+       
+     
+
+   assign branch_predict_d = bi_unconditional | bi_conditional;
+   assign branch_predict_taken_d = bi_unconditional ? 1'b1 : (bi_conditional ? instruction_d[15] : 1'b0);
+   
+   
+   assign branch_target_d = pc_d + branch_offset_d;
+
+   
+   
+   
+   assign branch_predict_address_d = branch_predict_taken_d ? branch_target_d : pc_f;
+
+
+always @(*)
+begin
+    d_result_0 = d_result_sel_0_d[0] ? {pc_f, 2'b00} : bypass_data_0; 
+    case (d_result_sel_1_d)
+     2'b00:      d_result_1 = { 32{1'b0}};
+     2'b01:     d_result_1 = bypass_data_1;
+     2'b10: d_result_1 = immediate_d;
+    default:                        d_result_1 = { 32{1'bx}};
+    endcase
+end
+
+      
+
+   
+   
+
+
+
+  
+
+
+assign sextb_result_x = {{24{operand_0_x[7]}}, operand_0_x[7:0]};
+assign sexth_result_x = {{16{operand_0_x[15]}}, operand_0_x[15:0]};
+assign sext_result_x = size_x ==  2'b00 ? sextb_result_x : sexth_result_x;
+ 
+
+
+  
+
+      
+
+
+
+
+assign cmp_zero = operand_0_x == operand_1_x;
+assign cmp_negative = adder_result_x[ 32-1];
+assign cmp_overflow = adder_overflow_x;
+assign cmp_carry_n = adder_carry_n_x;
+always @(*)
+begin
+    case (condition_x)
+     3'b000:   condition_met_x =  1'b1;
+     3'b110:   condition_met_x =  1'b1;
+     3'b001:    condition_met_x = cmp_zero;
+     3'b111:   condition_met_x = !cmp_zero;
+     3'b010:    condition_met_x = !cmp_zero && (cmp_negative == cmp_overflow);
+     3'b101:   condition_met_x = cmp_carry_n && !cmp_zero;
+     3'b011:   condition_met_x = cmp_negative == cmp_overflow;
+     3'b100:  condition_met_x = cmp_carry_n;
+    default:              condition_met_x = 1'bx;
+    endcase 
+end
+
+
+always @(*)
+begin
+    x_result =   x_result_sel_add_x ? adder_result_x 
+               : x_result_sel_csr_x ? csr_read_data_x
+  
+
+               : x_result_sel_sext_x ? sext_result_x
+ 
+
+  
+                  
+
+
+  
+                  
+
+
+  
+                  
+
+
+               : logic_result_x;
+end
+
+
+always @(*)
+begin
+    m_result =   m_result_sel_compare_m ? {{ 32-1{1'b0}}, condition_met_m}
+  
+
+               : m_result_sel_shift_m ? shifter_result_m
+ 
+
+               : operand_m; 
+end
+
+
+always @(*)
+begin
+    w_result =    w_result_sel_load_w ? load_data_w
+  
+
+                : w_result_sel_mul_w ? multiplier_result_w
+ 
+
+                : operand_w;
+end
+
+      
+
+          
+                                
+                                     
+                                 
+                                 
+                              
+
+
+
+
+assign branch_taken_m =      (stall_m ==  1'b0) 
+                          && (   (   (branch_m ==  1'b1) 
+                                  && (valid_m ==  1'b1)
+                                  && (   (   (condition_met_m ==  1'b1)
+					  && (branch_predict_taken_m ==  1'b0)
+					 )
+				      || (   (condition_met_m ==  1'b0)
+					  && (branch_predict_m ==  1'b1)
+					  && (branch_predict_taken_m ==  1'b1)
+					 )
+				     )
+                                 ) 
+                              || (exception_m ==  1'b1)
+                             );
+
+
+assign branch_mispredict_taken_m =    (condition_met_m ==  1'b0)
+                                   && (branch_predict_m ==  1'b1)
+	   			   && (branch_predict_taken_m ==  1'b1);
+   
+
+assign branch_flushX_m =    (stall_m ==  1'b0)
+                         && (   (   (branch_m ==  1'b1) 
+                                 && (valid_m ==  1'b1)
+			         && (   (condition_met_m ==  1'b1)
+				     || (   (condition_met_m ==  1'b0)
+					 && (branch_predict_m ==  1'b1)
+					 && (branch_predict_taken_m ==  1'b1)
+					)
+				    )
+			        )
+			     || (exception_m ==  1'b1)
+			    );
+
+
+assign kill_f =    (   (valid_d ==  1'b1)
+                    && (branch_predict_taken_d ==  1'b1)
+		   )
+                || (branch_taken_m ==  1'b1) 
+      
+                   
+
+
+  
+
+                || (icache_refill_request ==  1'b1) 
+ 
+
+                  
+                   
+
+
+                ;
+assign kill_d =    (branch_taken_m ==  1'b1) 
+      
+                   
+
+
+  
+
+                || (icache_refill_request ==  1'b1)     
+ 
+                
+                  
+                   
+
+
+                ;
+assign kill_x =    (branch_flushX_m ==  1'b1) 
+                  
+                   
+
+
+                ;
+assign kill_m =     1'b0
+                  
+                   
+
+
+                ;                
+assign kill_w =     1'b0
+                  
+                   
+
+                
+                ;
+
+
+
+  
+
+assign breakpoint_exception =    (   (   (break_x ==  1'b1)
+				      || (bp_match ==  1'b1)
+				     )
+				  && (valid_x ==  1'b1)
+				 )
+  
+
+                              || (jtag_break ==  1'b1)
+ 
+
+                              ;
+ 
+
+
+  
+
+assign watchpoint_exception = wp_match ==  1'b1;
+ 
+
+
+  
+        
+                                             
+                                         
+     
+
+
+
+  
+     
+
+
+
+assign system_call_exception = (   (scall_x ==  1'b1)
+  
+                                   
+
+
+			       );
+
+  
+
+assign debug_exception_x =  (breakpoint_exception ==  1'b1)
+                         || (watchpoint_exception ==  1'b1)
+                         ;
+
+assign non_debug_exception_x = (system_call_exception ==  1'b1)
+  
+
+                            || (reset_exception ==  1'b1)
+ 
+
+  
+                               
+                               
+
+
+  
+                               
+
+
+  
+
+                            || (   (interrupt_exception ==  1'b1)
+  
+
+                                && (dc_ss ==  1'b0)
+ 
+                            
+  
+ 				   
+				   
+
+
+                               )
+ 
+
+                            ;
+
+assign exception_x = (debug_exception_x ==  1'b1) || (non_debug_exception_x ==  1'b1);
+ 
+               
+ 
+                               
+                               
+
+ 
+                               
+
+ 
+                                  
+ 
+                                   
+                            
+ 
+ 				   
+				   
+
+                               
+
+                            
+
+
+
+  
+ 
+
+ 
+  
+      
+   
+      
+
+
+
+
+always @(*)
+begin
+  
+
+  
+
+    if (reset_exception ==  1'b1)
+        eid_x =  3'h0;
+    else
+ 
+     
+  
+            
+          
+    
+
+
+         if (breakpoint_exception ==  1'b1)
+        eid_x =  3'd1;
+    else
+ 
+
+  
+            
+          
+    
+            
+          
+    
+
+
+  
+
+         if (watchpoint_exception ==  1'b1)
+        eid_x =  3'd3;
+    else 
+ 
+
+  
+            
+          
+    
+
+
+  
+
+         if (   (interrupt_exception ==  1'b1)
+  
+
+             && (dc_ss ==  1'b0)
+ 
+                            
+            )
+        eid_x =  3'h6;
+    else
+ 
+
+        eid_x =  3'h7;
+end
+
+
+
+assign stall_a = (stall_f ==  1'b1);
+                
+assign stall_f = (stall_d ==  1'b1);
+                
+assign stall_d =   (stall_x ==  1'b1) 
+                || (   (interlock ==  1'b1)
+                    && (kill_d ==  1'b0)
+                   ) 
+		|| (   (   (eret_d ==  1'b1)
+			|| (scall_d ==  1'b1)
+  
+			   
+
+
+		       )
+		    && (   (load_q_x ==  1'b1)
+			|| (load_q_m ==  1'b1)
+			|| (store_q_x ==  1'b1)
+			|| (store_q_m ==  1'b1)
+			|| (D_CYC_O ==  1'b1)
+		       )
+                    && (kill_d ==  1'b0)
+		   )
+  
+
+		|| (   (   (break_d ==  1'b1)
+			|| (bret_d ==  1'b1)
+		       )
+		    && (   (load_q_x ==  1'b1)
+			|| (store_q_x ==  1'b1)
+			|| (load_q_m ==  1'b1)
+			|| (store_q_m ==  1'b1)
+			|| (D_CYC_O ==  1'b1)
+		       )
+                    && (kill_d ==  1'b0)
+		   )
+ 
+                   
+                || (   (csr_write_enable_d ==  1'b1)
+                    && (load_q_x ==  1'b1)
+                   )                      
+  
+                 
+                 
+                       
+		           
+			 
+			
+		    
+
+	
+                ;
+                
+assign stall_x =    (stall_m ==  1'b1)
+  
+                       
+                        
+                     
+
+
+
+	    
+                 ;
+
+assign stall_m =    (stall_wb_load ==  1'b1)
+  
+                    
+
+
+                 || (   (D_CYC_O ==  1'b1)
+                     && (   (store_m ==  1'b1)
+		         
+          
+          
+
+		  
+	 
+	
+
+          
+           
+          
+       
+
+  
+
+		         || ((store_x ==  1'b1) && (interrupt_exception ==  1'b1))
+ 
+
+                         || (load_m ==  1'b1)
+                         || (load_x ==  1'b1)
+                        ) 
+                    ) 
+ 
+                 
+  
+                         
+
+                                    
+  
+
+                 || (icache_stall_request ==  1'b1)     
+                 || ((I_CYC_O ==  1'b1) && ((branch_m ==  1'b1) || (exception_m ==  1'b1))) 
+ 
+ 
+                                
+
+
+                               
+  
+                                  
+                        
+                    
+
+
+  
+                  
+   
+
+                 ;      
+
+
+
+
+  
+         
+
+
+  
+         
+         
+
+
+  
+         
+
+
+  
+         
+         
+
+
+assign q_x = (valid_x ==  1'b1) && (kill_x ==  1'b0);
+assign csr_write_enable_q_x = (csr_write_enable_x ==  1'b1) && (q_x ==  1'b1);
+assign eret_q_x = (eret_x ==  1'b1) && (q_x ==  1'b1);
+  
+
+assign bret_q_x = (bret_x ==  1'b1) && (q_x ==  1'b1);
+ 
+
+assign load_q_x = (load_x ==  1'b1) 
+               && (q_x ==  1'b1)
+  
+
+               && (bp_match ==  1'b0)
+ 
+
+                  ;
+assign store_q_x = (store_x ==  1'b1) 
+               && (q_x ==  1'b1)
+  
+
+               && (bp_match ==  1'b0)
+ 
+
+                  ;
+  
+         
+
+                              
+assign q_m = (valid_m ==  1'b1) && (kill_m ==  1'b0) && (exception_m ==  1'b0);
+assign load_q_m = (load_m ==  1'b1) && (q_m ==  1'b1);
+assign store_q_m = (store_m ==  1'b1) && (q_m ==  1'b1);
+  
+
+assign debug_exception_q_w = ((debug_exception_w ==  1'b1) && (valid_w ==  1'b1));
+assign non_debug_exception_q_w = ((non_debug_exception_w ==  1'b1) && (valid_w ==  1'b1));        
+ 
+                 
+
+
+
+assign write_enable_q_x = (write_enable_x ==  1'b1) && (valid_x ==  1'b1) && (branch_flushX_m ==  1'b0);
+assign write_enable_q_m = (write_enable_m ==  1'b1) && (valid_m ==  1'b1);
+assign write_enable_q_w = (write_enable_w ==  1'b1) && (valid_w ==  1'b1);
+
+assign reg_write_enable_q_w = (write_enable_w ==  1'b1) && (kill_w ==  1'b0) && (valid_w ==  1'b1);
+
+
+assign cfg = {
+               6'h02,
+              watchpoints[3:0],
+              breakpoints[3:0],
+              interrupts[5:0],
+  
+
+               1'b1,
+ 
+              
+
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+ 
+               1'b1
+ 
+              
+
+
+              };
+
+assign cfg2 = {
+		     30'b0,
+  
+		     
+
+
+		      1'b0,
+ 
+
+  
+		     
+
+
+		      1'b0
+ 
+
+		     };
+   
+
+  
+
+assign iflush = (   (csr_write_enable_d ==  1'b1) 
+                 && (csr_d ==  5'h3)
+                 && (stall_d ==  1'b0)
+                 && (kill_d ==  1'b0)
+                 && (valid_d ==  1'b1))
+
+  
+
+             ||
+                (   (jtag_csr_write_enable ==  1'b1)
+		 && (jtag_csr ==  5'h3))
+ 
+
+		 ;
+ 
+ 
+  
+         
+                      
+
+ 
+               
+                       
+		      
+
+		   
+
+ 
+
+
+assign csr_d = read_idx_0_d[ (5-1):0];
+
+
+always @(*)
+begin
+    case (csr_x)
+  
+
+     5'h0,
+     5'h1,
+     5'h2:   csr_read_data_x = interrupt_csr_read_data_x;  
+ 
+
+  
+         
+
+
+     5'h6:  csr_read_data_x = cfg;
+     5'h7:  csr_read_data_x = {eba, 8'h00};
+  
+
+     5'h9: csr_read_data_x = {deba, 8'h00};
+ 
+
+  
+
+     5'he:  csr_read_data_x = jtx_csr_read_data;  
+     5'hf:  csr_read_data_x = jrx_csr_read_data;
+ 
+
+     5'ha: csr_read_data_x = cfg2;
+     5'hb:  csr_read_data_x = sdb_address;
+  
+        
+
+
+      
+      
+    default:        csr_read_data_x = { 32{1'bx}};
+    endcase
+end
+
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        eba <= eba_reset[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+    else
+    begin
+        if ((csr_write_enable_q_x ==  1'b1) && (csr_x ==  5'h7) && (stall_x ==  1'b0))
+            eba <= operand_1_x[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+  
+
+   
+
+       if ((jtag_csr_write_enable ==  1'b1) && (jtag_csr ==  5'h7))
+         eba <= jtag_csr_write_data[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+  
+
+   
+              
+           
+ 
+	 
+ 
+
+    end
+end
+
+  
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        deba <= deba_reset[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+    else
+    begin
+        if ((csr_write_enable_q_x ==  1'b1) && (csr_x ==  5'h9) && (stall_x ==  1'b0))
+            deba <= operand_1_x[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+   
+
+    
+
+       if ((jtag_csr_write_enable ==  1'b1) && (jtag_csr ==  5'h9))
+         deba <= jtag_csr_write_data[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+   
+
+    
+              
+           
+  
+       
+  
+
+    end
+end
+ 
+
+
+
+  
+   
+
+       
+          
+    
+            
+
+
+
+
+  
+
+   
+
+       
+          
+    
+    
+        
+                
+             
+	     
+	
+        
+               
+              
+    
+
+
+
+ 
+
+
+  
+
+  
+ 
+
+           
+           
+       
+          
+            
+                 
+             
+          
+     
+            
+ 
+
+
+always @(*)
+begin
+    if (icache_refill_request ==  1'b1) 
+        valid_a =  1'b0;
+    else if (icache_restart_request ==  1'b1) 
+        valid_a =  1'b1;
+    else 
+        valid_a = !icache_refilling;
+end 
+ 
+
+ 
+ 
+ 
+
+        
+          
+         
+          
+     
+          
+ 
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        valid_f <=  1'b0;
+        valid_d <=  1'b0;
+        valid_x <=  1'b0;
+        valid_m <=  1'b0;
+        valid_w <=  1'b0;
+    end
+    else
+    begin    
+        if ((kill_f ==  1'b1) || (stall_a ==  1'b0))
+  
+
+            valid_f <= valid_a;    
+ 
+              
+
+            
+        else if (stall_f ==  1'b0)
+            valid_f <=  1'b0;            
+
+        if (kill_d ==  1'b1)
+            valid_d <=  1'b0;
+        else if (stall_f ==  1'b0)
+            valid_d <= valid_f & !kill_f;
+        else if (stall_d ==  1'b0)
+            valid_d <=  1'b0;
+       
+        if (stall_d ==  1'b0)
+            valid_x <= valid_d & !kill_d;
+        else if (kill_x ==  1'b1)
+            valid_x <=  1'b0;
+        else if (stall_x ==  1'b0)
+            valid_x <=  1'b0;
+
+        if (kill_m ==  1'b1)
+            valid_m <=  1'b0;
+        else if (stall_x ==  1'b0)
+            valid_m <= valid_x & !kill_x;
+        else if (stall_m ==  1'b0)
+            valid_m <=  1'b0;
+
+        if (stall_m ==  1'b0)
+            valid_w <= valid_m & !kill_m;
+        else 
+            valid_w <=  1'b0;        
+    end
+end
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+  
+                 
+
+        
+        operand_0_x <= { 32{1'b0}};
+        operand_1_x <= { 32{1'b0}};
+        store_operand_x <= { 32{1'b0}};
+        branch_target_x <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};        
+        x_result_sel_csr_x <=  1'b0;
+  
+          
+
+
+      
+          
+
+
+  
+
+        x_result_sel_sext_x <=  1'b0;
+ 
+    
+  
+          
+
+
+        x_result_sel_add_x <=  1'b0;
+        m_result_sel_compare_x <=  1'b0;
+  
+
+        m_result_sel_shift_x <=  1'b0;
+ 
+    
+        w_result_sel_load_x <=  1'b0;
+  
+
+        w_result_sel_mul_x <=  1'b0;
+ 
+
+        x_bypass_enable_x <=  1'b0;
+        m_bypass_enable_x <=  1'b0;
+        write_enable_x <=  1'b0;
+        write_idx_x <= { 5{1'b0}};
+        csr_x <= { 5{1'b0}};
+        load_x <=  1'b0;
+        store_x <=  1'b0;
+        size_x <= { 2{1'b0}};
+        sign_extend_x <=  1'b0;
+        adder_op_x <=  1'b0;
+        adder_op_x_n <=  1'b0;
+        logic_op_x <= 4'h0;
+  
+
+        direction_x <=  1'b0;
+ 
+
+  
+          
+
+
+
+        branch_x <=  1'b0;
+        branch_predict_x <=  1'b0;
+        branch_predict_taken_x <=  1'b0;
+        condition_x <=  3'b000;
+  
+
+        break_x <=  1'b0;
+ 
+
+        scall_x <=  1'b0;
+        eret_x <=  1'b0;
+  
+
+        bret_x <=  1'b0;
+ 
+
+  
+          
+          
+
+
+        csr_write_enable_x <=  1'b0;
+        operand_m <= { 32{1'b0}};
+        branch_target_m <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+        m_result_sel_compare_m <=  1'b0;
+  
+
+        m_result_sel_shift_m <=  1'b0;
+ 
+    
+        w_result_sel_load_m <=  1'b0;
+  
+
+        w_result_sel_mul_m <=  1'b0;
+ 
+
+        m_bypass_enable_m <=  1'b0;
+        branch_m <=  1'b0;
+        branch_predict_m <=  1'b0;
+	branch_predict_taken_m <=  1'b0;
+        exception_m <=  1'b0;
+        load_m <=  1'b0;
+        store_m <=  1'b0;
+        write_enable_m <=  1'b0;            
+        write_idx_m <= { 5{1'b0}};
+        condition_met_m <=  1'b0;
+  
+          
+
+
+  
+
+        debug_exception_m <=  1'b0;
+        non_debug_exception_m <=  1'b0;        
+ 
+
+        operand_w <= { 32{1'b0}};        
+        w_result_sel_load_w <=  1'b0;
+  
+
+        w_result_sel_mul_w <=  1'b0;
+ 
+
+        write_idx_w <= { 5{1'b0}};        
+        write_enable_w <=  1'b0;
+  
+
+        debug_exception_w <=  1'b0;
+        non_debug_exception_w <=  1'b0;        
+ 
+          
+
+
+  
+          
+
+
+    end
+    else
+    begin
+        
+       
+        if (stall_x ==  1'b0)
+        begin
+  
+                     
+
+        
+            operand_0_x <= d_result_0;
+            operand_1_x <= d_result_1;
+            store_operand_x <= bypass_data_1;
+            branch_target_x <= branch_reg_d ==  1'b1 ? bypass_data_0[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] : branch_target_d;            
+            x_result_sel_csr_x <= x_result_sel_csr_d;
+  
+              
+
+
+      
+              
+
+
+  
+
+            x_result_sel_sext_x <= x_result_sel_sext_d;
+ 
+    
+  
+              
+
+
+            x_result_sel_add_x <= x_result_sel_add_d;
+            m_result_sel_compare_x <= m_result_sel_compare_d;
+  
+
+            m_result_sel_shift_x <= m_result_sel_shift_d;
+ 
+    
+            w_result_sel_load_x <= w_result_sel_load_d;
+  
+
+            w_result_sel_mul_x <= w_result_sel_mul_d;
+ 
+
+            x_bypass_enable_x <= x_bypass_enable_d;
+            m_bypass_enable_x <= m_bypass_enable_d;
+            load_x <= load_d;
+            store_x <= store_d;
+            branch_x <= branch_d;
+	    branch_predict_x <= branch_predict_d;
+	    branch_predict_taken_x <= branch_predict_taken_d;
+	    write_idx_x <= write_idx_d;
+            csr_x <= csr_d;
+            size_x <= size_d;
+            sign_extend_x <= sign_extend_d;
+            adder_op_x <= adder_op_d;
+            adder_op_x_n <= ~adder_op_d;
+            logic_op_x <= logic_op_d;
+  
+
+            direction_x <= direction_d;
+ 
+
+  
+              
+
+
+            condition_x <= condition_d;
+            csr_write_enable_x <= csr_write_enable_d;
+  
+
+            break_x <= break_d;
+ 
+
+            scall_x <= scall_d;
+  
+              
+
+
+            eret_x <= eret_d;
+  
+
+            bret_x <= bret_d; 
+ 
+
+            write_enable_x <= write_enable_d;
+        end
+        
+        
+
+        if (stall_m ==  1'b0)
+        begin
+            operand_m <= x_result;
+            m_result_sel_compare_m <= m_result_sel_compare_x;
+  
+
+            m_result_sel_shift_m <= m_result_sel_shift_x;
+ 
+    
+            if (exception_x ==  1'b1)
+            begin
+                w_result_sel_load_m <=  1'b0;
+  
+
+                w_result_sel_mul_m <=  1'b0;
+ 
+
+            end
+            else
+            begin
+                w_result_sel_load_m <= w_result_sel_load_x;
+  
+
+                w_result_sel_mul_m <= w_result_sel_mul_x;
+ 
+
+            end
+            m_bypass_enable_m <= m_bypass_enable_x;
+            load_m <= load_x;
+            store_m <= store_x;
+      
+                
+
+
+            branch_m <= branch_x;
+	    branch_predict_m <= branch_predict_x;
+	    branch_predict_taken_m <= branch_predict_taken_x;
+ 
+
+  
+
+	   
+	   
+	   
+	   
+	   
+            if (non_debug_exception_x ==  1'b1) 
+                write_idx_m <=  5'd30;
+            else if (debug_exception_x ==  1'b1)
+                write_idx_m <=  5'd31;
+            else 
+                write_idx_m <= write_idx_x;
+ 
+               
+                  
+             
+                  
+
+
+            condition_met_m <= condition_met_x;
+  
+
+	   if (exception_x ==  1'b1)
+	     if ((dc_re ==  1'b1)
+		 || ((debug_exception_x ==  1'b1) 
+		     && (non_debug_exception_x ==  1'b0)))
+	       branch_target_m <= {deba, eid_x, {3{1'b0}}};
+	     else
+	       branch_target_m <= {eba, eid_x, {3{1'b0}}};
+	   else
+	     branch_target_m <= branch_target_x;
+ 
+                      
+
+
+  
+              
+              
+
+
+  
+              
+
+
+  
+ 
+               
+
+
+
+            write_enable_m <= exception_x ==  1'b1 ?  1'b1 : write_enable_x;            
+  
+
+            debug_exception_m <= debug_exception_x;
+            non_debug_exception_m <= non_debug_exception_x;        
+ 
+
+        end
+        
+        
+        if (stall_m ==  1'b0)
+        begin
+            if ((exception_x ==  1'b1) && (q_x ==  1'b1) && (stall_x ==  1'b0))
+                exception_m <=  1'b1;
+            else 
+                exception_m <=  1'b0;
+  
+	           
+ 
+					    
+
+					 
+
+
+	end
+                
+        
+  
+                      
+
+
+        operand_w <= exception_m ==  1'b1 ? {pc_m, 2'b00} : m_result;
+ 
+
+        w_result_sel_load_w <= w_result_sel_load_m;
+  
+
+        w_result_sel_mul_w <= w_result_sel_mul_m;
+ 
+
+        write_idx_w <= write_idx_m;
+  
+          
+          
+ 
+           
+
+
+
+        write_enable_w <= write_enable_m;
+  
+
+        debug_exception_w <= debug_exception_m;
+        non_debug_exception_w <= non_debug_exception_m;
+ 
+          
+
+
+  
+              
+                   
+                   
+               
+	   
+            
+
+
+    end
+end
+
+  
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        use_buf <=  1'b0;
+        reg_data_buf_0 <= { 32{1'b0}};
+        reg_data_buf_1 <= { 32{1'b0}};
+    end
+    else
+    begin
+        if (stall_d ==  1'b0)
+            use_buf <=  1'b0;
+        else if (use_buf ==  1'b0)
+        begin        
+            reg_data_buf_0 <= reg_data_live_0;
+            reg_data_buf_1 <= reg_data_live_1;
+            use_buf <=  1'b1;
+        end        
+        if (reg_write_enable_q_w ==  1'b1)
+        begin
+            if (write_idx_w == read_idx_0_d)
+                reg_data_buf_0 <= w_result;
+            if (write_idx_w == read_idx_1_d)
+                reg_data_buf_1 <= w_result;
+        end
+    end
+end
+ 
+
+
+  
+
+ 
+
+   
+
+        
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+        
+     
+           
+            
+        
+
+
+
+
+  
+
+   
+
+       
+    
+          
+          
+          
+          
+          
+ 
+          
+
+          
+    
+    
+    
+          
+        
+ 
+               
+
+           
+
+                
+              
+              
+              
+              
+        
+        
+              
+        
+             
+        
+            
+                 
+            
+                
+                  
+                  
+            
+            
+              
+            
+              
+ 
+              
+
+        
+        
+        
+              
+ 
+              
+
+        
+    
+
+
+
+      
+
+
+
+
+
+        
+endmodule 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_load_store_unit_medium_icache_debug 
+(
+    
+    clk_i,
+    rst_i,
+ 
+    stall_a,
+    stall_x,
+    stall_m,
+    kill_x,
+    kill_m,
+    exception_m,
+    store_operand_x,
+    load_store_address_x,
+    load_store_address_m,
+    load_store_address_w,
+    load_x,
+    store_x,
+    load_q_x,
+    store_q_x,
+    load_q_m,
+    store_q_m,
+    sign_extend_x,
+    size_x,
+  
+    
+
+
+    
+    d_dat_i,
+    d_ack_i,
+    d_err_i,
+    d_rty_i,
+    
+    
+  
+    
+    
+    
+    
+
+    
+  
+    
+    
+    
+    
+    
+    
+    
+
+			     
+    load_data_w,
+    stall_wb_load,
+    
+    d_dat_o,
+    d_adr_o,
+    d_cyc_o,
+    d_sel_o,
+    d_stb_o,
+    d_we_o,
+    d_cti_o,
+    d_lock_o,
+    d_bte_o
+    );
+
+
+
+
+
+parameter associativity = 1;                            
+parameter sets = 512;                                   
+parameter bytes_per_line = 16;                          
+parameter base_address = 0;                             
+parameter limit = 0;                                    
+
+
+localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
+localparam addr_offset_lsb = 2;
+localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
+
+
+
+
+
+   input clk_i;                                            
+   
+input rst_i;                                            
+
+input stall_a;                                          
+input stall_x;                                          
+input stall_m;                                          
+input kill_x;                                           
+input kill_m;                                           
+input exception_m;                                      
+
+input [ (32-1):0] store_operand_x;                 
+input [ (32-1):0] load_store_address_x;            
+input [ (32-1):0] load_store_address_m;            
+input [1:0] load_store_address_w;                       
+input load_x;                                           
+input store_x;                                          
+input load_q_x;                                         
+input store_q_x;                                        
+input load_q_m;                                         
+input store_q_m;                                        
+input sign_extend_x;                                    
+input [ 1:0] size_x;                          
+
+  
+                                            
+
+
+
+     
+     
+     
+      
+      
+            
+    	 
+   
+
+
+
+   reg 		 [31:0] iram_dat_d0;
+   reg 		 iram_en_d0;
+   wire 	 iram_en;
+   wire [31:0] 	 iram_data;
+   
+   
+   
+input [ (32-1):0] d_dat_i;                         
+input d_ack_i;                                          
+input d_err_i;                                          
+input d_rty_i;                                          
+
+
+
+
+
+  
+                            
+   
+                           
+   
+                             
+   
+ 
+   
+
+
+
+   
+output [ (32-1):0] load_data_w;                    
+reg    [ (32-1):0] load_data_w;
+output stall_wb_load;                                   
+reg    stall_wb_load;
+
+output [ (32-1):0] d_dat_o;                        
+reg    [ (32-1):0] d_dat_o;
+output [ (32-1):0] d_adr_o;                        
+reg    [ (32-1):0] d_adr_o;
+output d_cyc_o;                                         
+reg    d_cyc_o;
+output [ (4-1):0] d_sel_o;                 
+reg    [ (4-1):0] d_sel_o;
+output d_stb_o;                                         
+reg    d_stb_o; 
+output d_we_o;                                          
+reg    d_we_o;
+output [ (3-1):0] d_cti_o;                       
+reg    [ (3-1):0] d_cti_o;
+output d_lock_o;                                        
+reg    d_lock_o;
+output [ (2-1):0] d_bte_o;                       
+wire   [ (2-1):0] d_bte_o;
+
+
+
+
+
+
+reg [ 1:0] size_m;
+reg [ 1:0] size_w;
+reg sign_extend_m;
+reg sign_extend_w;
+reg [ (32-1):0] store_data_x;       
+reg [ (32-1):0] store_data_m;       
+reg [ (4-1):0] byte_enable_x;
+reg [ (4-1):0] byte_enable_m;
+wire [ (32-1):0] data_m;
+reg [ (32-1):0] data_w;
+
+   
+
+  
+                                    
+ 
+                      
+              
+                                 
+                  
+                   
+                                          
+                      
+
+
+  
+                                      
+ 
+                                      
+                    
+                      
+                        
+                  
+
+
+wire wb_select_x;                                       
+  
+                                      
+
+  
+    
+    
+   
+
+
+
+reg wb_select_m;
+reg [ (32-1):0] wb_data_m;                         
+reg wb_load_complete;                                   
+   
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+  
+
+ 
+              
+                       
+             
+               
+                      
+       
+    
+                      
+                            
+                    
+                    
+                    
+                  
+                  
+                     
+                    
+                 
+            
+               
+                
+                     
+    
+              
+            
+             
+             
+                  
+                  
+    
+
+
+
+
+
+
+
+
+  
+            
+                             
+
+
+
+  
+            
+                             
+
+      
+        
+
+    
+       
+
+   
+
+    
+     
+       
+     
+         
+     
+
+          
+    
+   
+   
+
+
+   
+  
+            
+                               
+ 
+                               
+
+ 
+                               
+
+                     
+
+
+	  
+   assign wb_select_x =     1'b1
+  
+                          
+
+
+  
+                         
+
+
+  
+                         
+
+
+                     ;
+
+
+always @(*)
+begin
+    case (size_x)
+     2'b00:  store_data_x = {4{store_operand_x[7:0]}};
+     2'b11: store_data_x = {2{store_operand_x[15:0]}};
+     2'b10:  store_data_x = store_operand_x;    
+    default:          store_data_x = { 32{1'bx}};
+    endcase
+end
+
+
+always @(*)
+begin
+    casez ({size_x, load_store_address_x[1:0]})
+    { 2'b00, 2'b11}:  byte_enable_x = 4'b0001;
+    { 2'b00, 2'b10}:  byte_enable_x = 4'b0010;
+    { 2'b00, 2'b01}:  byte_enable_x = 4'b0100;
+    { 2'b00, 2'b00}:  byte_enable_x = 4'b1000;
+    { 2'b11, 2'b1?}: byte_enable_x = 4'b0011;
+    { 2'b11, 2'b0?}: byte_enable_x = 4'b1100;
+    { 2'b10, 2'b??}:  byte_enable_x = 4'b1111;
+    default:                   byte_enable_x = 4'bxxxx;
+    endcase
+end
+
+  
+      
+            
+
+           
+	                            
+   
+   
+               
+        
+
+
+   
+  
+  
+   
+   
+         
+                    
+                       
+                      
+                        
+                     
+                        
+  
+   
+         
+                    
+                       
+                      
+                      
+  
+ 
+   
+   
+         
+                    
+                       
+                      
+                      
+  
+   
+         
+                     
+                    
+  
+ 
+
+
+   
+   
+   
+         
+                     
+                      
+                      
+                      
+  
+   
+         
+                     
+                    
+  
+ 
+
+    
+   
+         
+                     
+                    
+
+  
+
+   
+   assign data_m = wb_data_m;
+   
+
+  
+
+ 
+
+
+
+always @(*)
+begin
+    casez ({size_w, load_store_address_w[1:0]})
+    { 2'b00, 2'b11}:  load_data_w = {{24{sign_extend_w & data_w[7]}}, data_w[7:0]};
+    { 2'b00, 2'b10}:  load_data_w = {{24{sign_extend_w & data_w[15]}}, data_w[15:8]};
+    { 2'b00, 2'b01}:  load_data_w = {{24{sign_extend_w & data_w[23]}}, data_w[23:16]};
+    { 2'b00, 2'b00}:  load_data_w = {{24{sign_extend_w & data_w[31]}}, data_w[31:24]};
+    { 2'b11, 2'b1?}: load_data_w = {{16{sign_extend_w & data_w[15]}}, data_w[15:0]};
+    { 2'b11, 2'b0?}: load_data_w = {{16{sign_extend_w & data_w[31]}}, data_w[31:16]};
+    { 2'b10, 2'b??}:  load_data_w = data_w;
+    default:                   load_data_w = { 32{1'bx}};
+    endcase
+end
+
+
+assign d_bte_o =  2'b00;
+
+                  
+
+ 
+     
+    
+    
+   
+   
+   
+    
+    
+    
+    
+   
+   
+     
+     
+    
+    
+    
+   
+         
+     
+     
+    
+    
+
+
+
+
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        d_cyc_o <=  1'b0;
+        d_stb_o <=  1'b0;
+        d_dat_o <= { 32{1'b0}};
+        d_adr_o <= { 32{1'b0}};
+        d_sel_o <= { 4{ 1'b0}};
+        d_we_o <=  1'b0;
+        d_cti_o <=  3'b111;
+        d_lock_o <=  1'b0;
+        wb_data_m <= { 32{1'b0}};
+        wb_load_complete <=  1'b0;
+        stall_wb_load <=  1'b0;
+                  
+          
+
+                
+    end
+    else 
+    begin
+   
+        
+          
+
+                
+        
+        if (d_cyc_o ==  1'b1)
+        begin
+            
+            if ((d_ack_i ==  1'b1) || (d_err_i ==  1'b1))
+            begin
+                  
+                     
+                
+                    
+                        
+                
+                
+
+                
+                begin
+                    
+                    d_cyc_o <=  1'b0;
+                    d_stb_o <=  1'b0;
+                    d_lock_o <=  1'b0;
+                end
+      
+                  
+                
+                  
+
+
+                
+                wb_data_m <= d_dat_i;
+                
+                wb_load_complete <= !d_we_o;
+            end
+            
+        end
+        else 
+        begin
+                  
+               
+            
+                
+                  
+                  
+                  
+                                  
+                  
+                  
+                
+            
+             
+
+            
+                 if (   (store_q_m ==  1'b1)
+                     && (stall_m ==  1'b0)
+  
+                        
+
+
+  
+		        
+
+			
+                    )
+            begin
+                
+                d_dat_o <= store_data_m;
+                d_adr_o <= load_store_address_m;
+                d_cyc_o <=  1'b1;
+                d_sel_o <= byte_enable_m;
+                d_stb_o <=  1'b1;
+                d_we_o <=  1'b1;
+                d_cti_o <=  3'b111;
+            end        
+            else if (   (load_q_m ==  1'b1) 
+                     && (wb_select_m ==  1'b1) 
+                     && (wb_load_complete ==  1'b0)
+                     
+                    )
+            begin
+                
+                stall_wb_load <=  1'b0;
+                d_adr_o <= load_store_address_m;
+                d_cyc_o <=  1'b1;
+                d_sel_o <= byte_enable_m;
+                d_stb_o <=  1'b1;
+                d_we_o <=  1'b0;
+                d_cti_o <=  3'b111;
+            end
+        end
+        
+        if (stall_m ==  1'b0)
+            wb_load_complete <=  1'b0;
+        
+        if ((load_q_x ==  1'b1) && (wb_select_x ==  1'b1) && (stall_x ==  1'b0))
+            stall_wb_load <=  1'b1;
+        
+        if ((kill_m ==  1'b1) || (exception_m ==  1'b1))
+            stall_wb_load <=  1'b0;
+    end
+end
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        sign_extend_m <=  1'b0;
+        size_m <= 2'b00;
+        byte_enable_m <=  1'b0;
+        store_data_m <= { 32{1'b0}};
+  
+          
+
+
+  
+          
+
+
+  
+          
+			    
+
+
+        wb_select_m <=  1'b0;        
+    end
+    else
+    begin
+        if (stall_m ==  1'b0)
+        begin
+            sign_extend_m <= sign_extend_x;
+            size_m <= size_x;
+            byte_enable_m <= byte_enable_x;    
+            store_data_m <= store_data_x;
+  
+              
+
+
+  
+              
+
+
+  
+              
+			    
+
+
+            wb_select_m <= wb_select_x;
+        end
+    end
+end
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        size_w <= 2'b00;
+        data_w <= { 32{1'b0}};
+        sign_extend_w <=  1'b0;
+    end
+    else
+    begin
+        size_w <= size_m;
+
+  
+         
+
+
+        data_w <= data_m;
+
+        sign_extend_w <= sign_extend_m;
+    end
+end
+
+
+
+
+
+
+
+endmodule
+
+
+
+
+
+
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+  
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+     
+    
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+  
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+ 
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+ 
+
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+                  
+                    
+                 
+                   
+           
+             
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+                   
+               
+                 
+
+
+                      
+                      
+                      
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+
+ 
+                    
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+                    
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+  
+                    
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+                      
+
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+           
+             
+
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+                
+           
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+              
+               
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+                    
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+                
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+             
+               
+                 
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+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
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+ 
+                   
+                     
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+                    
+                     
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+                      
+                      
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+                     
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+                      
+                    
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+                    
+                     
+                
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+                     
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+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
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+                   
+             
+               
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+                  
+                    
+                 
+                   
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+                  
+                  
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+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
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+  
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+  
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+  
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+  
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+  
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+  
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+  
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+  
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+  
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+  
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+  
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+  
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+  
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+  
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+  
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+  
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+  
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+  
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+  
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+  
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+  
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+  
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+  
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+  
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+  
+
+  
+
+
+
+
+
+
+module lm32_decoder_medium_icache_debug (
+    
+    instruction,
+    
+    d_result_sel_0,
+    d_result_sel_1,        
+    x_result_sel_csr,
+  
+    
+
+    
+      
+    
+
+
+  
+
+    x_result_sel_sext,
+ 
+    
+    x_result_sel_logic,
+  
+    
+
+
+    x_result_sel_add,
+    m_result_sel_compare,
+  
+
+    m_result_sel_shift,  
+ 
+    
+    w_result_sel_load,
+  
+
+    w_result_sel_mul,
+ 
+
+    x_bypass_enable,
+    m_bypass_enable,
+    read_enable_0,
+    read_idx_0,
+    read_enable_1,
+    read_idx_1,
+    write_enable,
+    write_idx,
+    immediate,
+    branch_offset,
+    load,
+    store,
+    size,
+    sign_extend,
+    adder_op,
+    logic_op,
+  
+
+    direction,
+ 
+
+  
+    
+    
+
+
+  
+    
+
+
+  
+    
+    
+
+
+    branch,
+    branch_reg,
+    condition,
+    bi_conditional,
+    bi_unconditional,
+  
+
+    break_opcode,
+ 
+
+    scall,
+    eret,
+  
+
+    bret,
+ 
+
+  
+    
+
+
+    csr_write_enable
+    );
+
+
+
+
+
+input [ (32-1):0] instruction;       
+
+
+
+
+
+output [ 0:0] d_result_sel_0;
+reg    [ 0:0] d_result_sel_0;
+output [ 1:0] d_result_sel_1;
+reg    [ 1:0] d_result_sel_1;
+output x_result_sel_csr;
+reg    x_result_sel_csr;
+  
+ 
+    
+
+
+      
+ 
+    
+
+
+  
+
+output x_result_sel_sext;
+reg    x_result_sel_sext;
+ 
+
+output x_result_sel_logic;
+reg    x_result_sel_logic;
+  
+ 
+    
+
+
+output x_result_sel_add;
+reg    x_result_sel_add;
+output m_result_sel_compare;
+reg    m_result_sel_compare;
+  
+
+output m_result_sel_shift;
+reg    m_result_sel_shift;
+ 
+
+output w_result_sel_load;
+reg    w_result_sel_load;
+  
+
+output w_result_sel_mul;
+reg    w_result_sel_mul;
+ 
+
+output x_bypass_enable;
+wire   x_bypass_enable;
+output m_bypass_enable;
+wire   m_bypass_enable;
+output read_enable_0;
+wire   read_enable_0;
+output [ (5-1):0] read_idx_0;
+wire   [ (5-1):0] read_idx_0;
+output read_enable_1;
+wire   read_enable_1;
+output [ (5-1):0] read_idx_1;
+wire   [ (5-1):0] read_idx_1;
+output write_enable;
+wire   write_enable;
+output [ (5-1):0] write_idx;
+wire   [ (5-1):0] write_idx;
+output [ (32-1):0] immediate;
+wire   [ (32-1):0] immediate;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset;
+wire   [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset;
+output load;
+wire   load;
+output store;
+wire   store;
+output [ 1:0] size;
+wire   [ 1:0] size;
+output sign_extend;
+wire   sign_extend;
+output adder_op;
+wire   adder_op;
+output [ 3:0] logic_op;
+wire   [ 3:0] logic_op;
+  
+
+output direction;
+wire   direction;
+ 
+
+  
+ 
+   
+ 
+   
+
+
+  
+ 
+   
+
+
+  
+ 
+   
+ 
+   
+
+
+output branch;
+wire   branch;
+output branch_reg;
+wire   branch_reg;
+output [ (3-1):0] condition;
+wire   [ (3-1):0] condition;
+output bi_conditional;
+wire bi_conditional;
+output bi_unconditional;
+wire bi_unconditional;
+  
+
+output break_opcode;
+wire   break_opcode;
+ 
+
+output scall;
+wire   scall;
+output eret;
+wire   eret;
+  
+
+output bret;
+wire   bret;
+ 
+
+  
+  
+    
+
+
+output csr_write_enable;
+wire   csr_write_enable;
+
+
+
+
+
+wire [ (32-1):0] extended_immediate;       
+wire [ (32-1):0] high_immediate;           
+wire [ (32-1):0] call_immediate;           
+wire [ (32-1):0] branch_immediate;         
+wire sign_extend_immediate;                     
+wire select_high_immediate;                     
+wire select_call_immediate;                     
+
+wire op_add;
+wire op_and;
+wire op_andhi;
+wire op_b;
+wire op_bi;
+wire op_be;
+wire op_bg;
+wire op_bge;
+wire op_bgeu;
+wire op_bgu;
+wire op_bne;
+wire op_call;
+wire op_calli;
+wire op_cmpe;
+wire op_cmpg;
+wire op_cmpge;
+wire op_cmpgeu;
+wire op_cmpgu;
+wire op_cmpne;
+  
+ 
+
+
+wire op_lb;
+wire op_lbu;
+wire op_lh;
+wire op_lhu;
+wire op_lw;
+  
+ 
+
+
+  
+
+wire op_mul;
+ 
+
+wire op_nor;
+wire op_or;
+wire op_orhi;
+wire op_raise;
+wire op_rcsr;
+wire op_sb;
+  
+
+wire op_sextb;
+wire op_sexth;
+ 
+
+wire op_sh;
+  
+
+wire op_sl;
+ 
+
+wire op_sr;
+wire op_sru;
+wire op_sub;
+wire op_sw;
+  
+ 
+
+
+wire op_wcsr;
+wire op_xnor;
+wire op_xor;
+
+wire arith;
+wire logical;
+wire cmp;
+wire bra;
+wire call;
+  
+
+wire shift;
+ 
+
+  
+ 
+
+
+  
+
+wire sext;
+ 
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+assign op_add    = instruction[ 30:26] ==  5'b01101;
+assign op_and    = instruction[ 30:26] ==  5'b01000;
+assign op_andhi  = instruction[ 31:26] ==  6'b011000;
+assign op_b      = instruction[ 31:26] ==  6'b110000;
+assign op_bi     = instruction[ 31:26] ==  6'b111000;
+assign op_be     = instruction[ 31:26] ==  6'b010001;
+assign op_bg     = instruction[ 31:26] ==  6'b010010;
+assign op_bge    = instruction[ 31:26] ==  6'b010011;
+assign op_bgeu   = instruction[ 31:26] ==  6'b010100;
+assign op_bgu    = instruction[ 31:26] ==  6'b010101;
+assign op_bne    = instruction[ 31:26] ==  6'b010111;
+assign op_call   = instruction[ 31:26] ==  6'b110110;
+assign op_calli  = instruction[ 31:26] ==  6'b111110;
+assign op_cmpe   = instruction[ 30:26] ==  5'b11001;
+assign op_cmpg   = instruction[ 30:26] ==  5'b11010;
+assign op_cmpge  = instruction[ 30:26] ==  5'b11011;
+assign op_cmpgeu = instruction[ 30:26] ==  5'b11100;
+assign op_cmpgu  = instruction[ 30:26] ==  5'b11101;
+assign op_cmpne  = instruction[ 30:26] ==  5'b11111;
+  
+       
+
+
+assign op_lb     = instruction[ 31:26] ==  6'b000100;
+assign op_lbu    = instruction[ 31:26] ==  6'b010000;
+assign op_lh     = instruction[ 31:26] ==  6'b000111;
+assign op_lhu    = instruction[ 31:26] ==  6'b001011;
+assign op_lw     = instruction[ 31:26] ==  6'b001010;
+  
+       
+
+
+  
+
+assign op_mul    = instruction[ 30:26] ==  5'b00010;
+ 
+
+assign op_nor    = instruction[ 30:26] ==  5'b00001;
+assign op_or     = instruction[ 30:26] ==  5'b01110;
+assign op_orhi   = instruction[ 31:26] ==  6'b011110;
+assign op_raise  = instruction[ 31:26] ==  6'b101011;
+assign op_rcsr   = instruction[ 31:26] ==  6'b100100;
+assign op_sb     = instruction[ 31:26] ==  6'b001100;
+  
+
+assign op_sextb  = instruction[ 31:26] ==  6'b101100;
+assign op_sexth  = instruction[ 31:26] ==  6'b110111;
+ 
+
+assign op_sh     = instruction[ 31:26] ==  6'b000011;
+  
+
+assign op_sl     = instruction[ 30:26] ==  5'b01111;      
+ 
+
+assign op_sr     = instruction[ 30:26] ==  5'b00101;
+assign op_sru    = instruction[ 30:26] ==  5'b00000;
+assign op_sub    = instruction[ 31:26] ==  6'b110010;
+assign op_sw     = instruction[ 31:26] ==  6'b010110;
+  
+       
+
+
+assign op_wcsr   = instruction[ 31:26] ==  6'b110100;
+assign op_xnor   = instruction[ 30:26] ==  5'b01001;
+assign op_xor    = instruction[ 30:26] ==  5'b00110;
+
+
+assign arith = op_add | op_sub;
+assign logical = op_and | op_andhi | op_nor | op_or | op_orhi | op_xor | op_xnor;
+assign cmp = op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne;
+assign bi_conditional = op_be | op_bg | op_bge | op_bgeu  | op_bgu | op_bne;
+assign bi_unconditional = op_bi;
+assign bra = op_b | bi_unconditional | bi_conditional;
+assign call = op_call | op_calli;
+  
+
+assign shift = op_sl | op_sr | op_sru;
+ 
+
+  
+     
+
+
+  
+   
+     
+
+
+  
+
+assign sext = op_sextb | op_sexth;
+ 
+
+  
+   
+
+
+  
+    
+   
+
+
+assign load = op_lb | op_lbu | op_lh | op_lhu | op_lw;
+assign store = op_sb | op_sh | op_sw;
+
+
+always @(*)
+begin
+    
+    if (call) 
+        d_result_sel_0 =  1'b1;
+    else 
+        d_result_sel_0 =  1'b0;
+    if (call) 
+        d_result_sel_1 =  2'b00;         
+    else if ((instruction[31] == 1'b0) && !bra) 
+        d_result_sel_1 =  2'b10;
+    else
+        d_result_sel_1 =  2'b01; 
+    
+    x_result_sel_csr =  1'b0;
+  
+      
+
+
+  
+      
+
+
+  
+
+    x_result_sel_sext =  1'b0;
+ 
+
+    x_result_sel_logic =  1'b0;
+          
+      
+
+
+    x_result_sel_add =  1'b0;
+    if (op_rcsr)
+        x_result_sel_csr =  1'b1;
+      
+ 
+         
+          
+
+ 
+        
+                  
+
+ 
+      
+                      
+
+
+
+  
+      
+                  
+
+
+  
+
+    else if (sext)
+        x_result_sel_sext =  1'b1;
+ 
+        
+    else if (logical) 
+        x_result_sel_logic =  1'b1;
+          
+      
+          
+
+
+    else 
+        x_result_sel_add =  1'b1;        
+    
+    
+
+    m_result_sel_compare = cmp;
+  
+
+    m_result_sel_shift = shift;
+ 
+
+
+    
+    w_result_sel_load = load;
+  
+
+    w_result_sel_mul = op_mul; 
+ 
+
+end
+
+
+assign x_bypass_enable =  arith 
+                        | logical
+  
+                         
+                         
+
+                        
+  
+                         
+
+
+  
+                         
+                         
+
+
+  
+                         
+
+                  
+  
+
+                        | sext 
+ 
+                        
+  
+                         
+
+
+                        | op_rcsr
+                        ;
+
+assign m_bypass_enable = x_bypass_enable 
+  
+
+                        | shift
+ 
+
+                        | cmp
+                        ;
+
+assign read_enable_0 = ~(op_bi | op_calli);
+assign read_idx_0 = instruction[25:21];
+
+assign read_enable_1 = ~(op_bi | op_calli | load);
+assign read_idx_1 = instruction[20:16];
+
+assign write_enable = ~(bra | op_raise | store | op_wcsr);
+assign write_idx = call
+                    ? 5'd29
+                    : instruction[31] == 1'b0 
+                        ? instruction[20:16] 
+                        : instruction[15:11];
+                        
+
+assign size = instruction[27:26];
+
+assign sign_extend = instruction[28];                      
+
+assign adder_op = op_sub | op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne | bra;
+
+assign logic_op = instruction[29:26];
+  
+
+
+assign direction = instruction[29];
+ 
+
+
+assign branch = bra | call;
+assign branch_reg = op_call | op_b;
+assign condition = instruction[28:26];      
+  
+
+assign break_opcode = op_raise & ~instruction[2];
+ 
+
+assign scall = op_raise & instruction[2];
+assign eret = op_b & (instruction[25:21] == 5'd30);
+  
+
+assign bret = op_b & (instruction[25:21] == 5'd31);
+ 
+
+  
+
+   
+
+
+
+assign csr_write_enable = op_wcsr;
+
+
+
+assign sign_extend_immediate = ~(op_and | op_cmpgeu | op_cmpgu | op_nor | op_or | op_xnor | op_xor);
+assign select_high_immediate = op_andhi | op_orhi;
+assign select_call_immediate = instruction[31];
+
+assign high_immediate = {instruction[15:0], 16'h0000};
+assign extended_immediate = {{16{sign_extend_immediate & instruction[15]}}, instruction[15:0]};
+assign call_immediate = {{6{instruction[25]}}, instruction[25:0]};
+assign branch_immediate = {{16{instruction[15]}}, instruction[15:0]};
+
+assign immediate = select_high_immediate ==  1'b1 
+                        ? high_immediate 
+                        : extended_immediate;
+   
+assign branch_offset = select_call_immediate ==  1'b1   
+                        ? (call_immediate[ (clogb2(32'h7fffffff-32'h0)-2)-1:0])
+                        : (branch_immediate[ (clogb2(32'h7fffffff-32'h0)-2)-1:0]);
+    
+endmodule 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+  
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+
+
+
+
+module lm32_icache_medium_icache_debug ( 
+    
+    clk_i,
+    rst_i,    
+    stall_a,
+    stall_f,
+    address_a,
+    address_f,
+    read_enable_f,
+    refill_ready,
+    refill_data,
+    iflush,
+  
+    
+
+
+    valid_d,
+    branch_predict_taken_d,
+    
+    stall_request,
+    restart_request,
+    refill_request,
+    refill_address,
+    refilling,
+    inst
+    );
+
+
+
+
+
+parameter associativity = 1;                            
+parameter sets = 512;                                   
+parameter bytes_per_line = 16;                          
+parameter base_address = 0;                             
+parameter limit = 0;                                    
+
+localparam addr_offset_width = clogb2(bytes_per_line)-1-2;
+localparam addr_set_width = clogb2(sets)-1;
+localparam addr_offset_lsb = 2;
+localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
+localparam addr_set_lsb = (addr_offset_msb+1);
+localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
+localparam addr_tag_lsb = (addr_set_msb+1);
+localparam addr_tag_msb = clogb2( 32'h7fffffff- 32'h0)-1;
+localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
+
+
+
+
+
+input clk_i;                                        
+input rst_i;                                        
+
+input stall_a;                                      
+input stall_f;                                      
+
+input valid_d;                                      
+input branch_predict_taken_d;                       
+   
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] address_a;                     
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] address_f;                     
+input read_enable_f;                                
+
+input refill_ready;                                 
+input [ (32-1):0] refill_data;          
+
+input iflush;                                       
+  
+                                      
+
+
+   
+
+
+
+
+output stall_request;                               
+wire   stall_request;
+output restart_request;                             
+reg    restart_request;
+output refill_request;                              
+wire   refill_request;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] refill_address;               
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] refill_address;               
+output refilling;                                   
+reg    refilling;
+output [ (32-1):0] inst;                
+wire   [ (32-1):0] inst;
+
+
+
+
+
+wire enable;
+wire [0:associativity-1] way_mem_we;
+wire [ (32-1):0] way_data[0:associativity-1];
+wire [ ((addr_tag_width+1)-1):1] way_tag[0:associativity-1];
+wire [0:associativity-1] way_valid;
+wire [0:associativity-1] way_match;
+wire miss;
+
+wire [ (addr_set_width-1):0] tmem_read_address;
+wire [ (addr_set_width-1):0] tmem_write_address;
+wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_read_address;
+wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_write_address;
+wire [ ((addr_tag_width+1)-1):0] tmem_write_data;
+
+reg [ 3:0] state;
+wire flushing;
+wire check;
+wire refill;
+
+reg [associativity-1:0] refill_way_select;
+reg [ addr_offset_msb:addr_offset_lsb] refill_offset;
+wire last_refill;
+reg [ (addr_set_width-1):0] flush_set;
+
+genvar i;
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+   generate
+      for (i = 0; i < associativity; i = i + 1)
+	begin : memories
+	   
+	   lm32_ram 
+	     #(
+	       
+	       .data_width                 (32),
+	       .address_width              ( (addr_offset_width+addr_set_width))
+
+) 
+	   way_0_data_ram 
+	     (
+	      
+	      .read_clk                   (clk_i),
+	      .write_clk                  (clk_i),
+	      .reset                      (rst_i),
+	      .read_address               (dmem_read_address),
+	      .enable_read                (enable),
+	      .write_address              (dmem_write_address),
+	      .enable_write               ( 1'b1),
+	      .write_enable               (way_mem_we[i]),
+	      .write_data                 (refill_data),    
+	      
+	      .read_data                  (way_data[i])
+	      );
+	   
+	   lm32_ram 
+	     #(
+	       
+	       .data_width                 ( (addr_tag_width+1)),
+	       .address_width              ( addr_set_width)
+
+	       ) 
+	   way_0_tag_ram 
+	     (
+	      
+	      .read_clk                   (clk_i),
+	      .write_clk                  (clk_i),
+	      .reset                      (rst_i),
+	      .read_address               (tmem_read_address),
+	      .enable_read                (enable),
+	      .write_address              (tmem_write_address),
+	      .enable_write               ( 1'b1),
+	      .write_enable               (way_mem_we[i] | flushing),
+	      .write_data                 (tmem_write_data),
+	      
+	      .read_data                  ({way_tag[i], way_valid[i]})
+	      );
+	   
+	end
+endgenerate
+
+
+
+
+
+
+generate
+    for (i = 0; i < associativity; i = i + 1)
+    begin : match
+assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_f[ addr_tag_msb:addr_tag_lsb],  1'b1});
+    end
+endgenerate
+
+
+generate
+    if (associativity == 1)
+    begin : inst_1
+assign inst = way_match[0] ? way_data[0] : 32'b0;
+    end
+    else if (associativity == 2)
+	 begin : inst_2
+assign inst = way_match[0] ? way_data[0] : (way_match[1] ? way_data[1] : 32'b0);
+    end
+endgenerate
+
+
+generate 
+    if (bytes_per_line > 4)
+assign dmem_write_address = {refill_address[ addr_set_msb:addr_set_lsb], refill_offset};
+    else
+assign dmem_write_address = refill_address[ addr_set_msb:addr_set_lsb];
+endgenerate
+    
+assign dmem_read_address = address_a[ addr_set_msb:addr_offset_lsb];
+
+
+assign tmem_read_address = address_a[ addr_set_msb:addr_set_lsb];
+assign tmem_write_address = flushing 
+                                ? flush_set
+                                : refill_address[ addr_set_msb:addr_set_lsb];
+
+
+generate 
+    if (bytes_per_line > 4)                            
+assign last_refill = refill_offset == {addr_offset_width{1'b1}};
+    else
+assign last_refill =  1'b1;
+endgenerate
+
+
+assign enable = (stall_a ==  1'b0);
+
+
+generate
+    if (associativity == 1) 
+    begin : we_1     
+assign way_mem_we[0] = (refill_ready ==  1'b1);
+    end
+    else
+    begin : we_2
+assign way_mem_we[0] = (refill_ready ==  1'b1) && (refill_way_select[0] ==  1'b1);
+assign way_mem_we[1] = (refill_ready ==  1'b1) && (refill_way_select[1] ==  1'b1);
+    end
+endgenerate                     
+
+
+assign tmem_write_data[ 0] = last_refill & !flushing;
+assign tmem_write_data[ ((addr_tag_width+1)-1):1] = refill_address[ addr_tag_msb:addr_tag_lsb];
+
+
+assign flushing = |state[1:0];
+assign check = state[2];
+assign refill = state[3];
+
+assign miss = (~(|way_match)) && (read_enable_f ==  1'b1) && (stall_f ==  1'b0) && !(valid_d && branch_predict_taken_d);
+assign stall_request = (check ==  1'b0);
+assign refill_request = (refill ==  1'b1);
+                      
+
+
+
+
+
+generate
+    if (associativity >= 2) 
+    begin : way_select      
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
+    else
+    begin        
+        if (miss ==  1'b1)
+            refill_way_select <= {refill_way_select[0], refill_way_select[1]};
+    end
+end
+    end
+endgenerate
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        refilling <=  1'b0;
+    else
+        refilling <= refill;
+end
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        state <=  4'b0001;
+        flush_set <= { addr_set_width{1'b1}};
+        refill_address <= { (clogb2(32'h7fffffff-32'h0)-2){1'bx}};
+        restart_request <=  1'b0;
+    end
+    else 
+    begin
+        case (state)
+
+        
+         4'b0001:
+        begin            
+            if (flush_set == { addr_set_width{1'b0}})
+                state <=  4'b0100;
+            flush_set <= flush_set - 1'b1;
+        end
+
+        
+         4'b0010:
+        begin            
+            if (flush_set == { addr_set_width{1'b0}})
+  
+	       
+                  
+	      
+
+
+		state <=  4'b0100;
+	   
+            flush_set <= flush_set - 1'b1;
+        end
+        
+        
+         4'b0100:
+        begin            
+            if (stall_a ==  1'b0)
+                restart_request <=  1'b0;
+            if (iflush ==  1'b1)
+            begin
+                refill_address <= address_f;
+                state <=  4'b0010;
+            end
+            else if (miss ==  1'b1)
+            begin
+                refill_address <= address_f;
+                state <=  4'b1000;
+            end
+        end
+
+        
+         4'b1000:
+        begin            
+            if (refill_ready ==  1'b1)
+            begin
+                if (last_refill ==  1'b1)
+                begin
+                    restart_request <=  1'b1;
+                    state <=  4'b0100;
+                end
+            end
+        end
+
+        endcase        
+    end
+end
+
+generate 
+    if (bytes_per_line > 4)
+    begin
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        refill_offset <= {addr_offset_width{1'b0}};
+    else 
+    begin
+        case (state)
+        
+        
+         4'b0100:
+        begin            
+            if (iflush ==  1'b1)
+                refill_offset <= {addr_offset_width{1'b0}};
+            else if (miss ==  1'b1)
+                refill_offset <= {addr_offset_width{1'b0}};
+        end
+
+        
+         4'b1000:
+        begin            
+            if (refill_ready ==  1'b1)
+                refill_offset <= refill_offset + 1'b1;
+        end
+
+        endcase        
+    end
+end
+    end
+endgenerate
+   
+endmodule
+
+ 
+
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+								 
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+ 
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+                  
+                    
+                 
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+           
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+
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+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
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+                    
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+                
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+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
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+              
+                  
+                 
+            
+
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+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
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+         
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+                   
+                
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+           
+             
+
+                
+                  
+              
+            
+
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+               
+               
+              
+
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+
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+   
+    
+    
+        
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
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+
+
+                               
+                                      
+                             
+                                
+                                       
+
+   
+   
+   
+   
+   
+   
+   
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+   
+
+
+
+
+
+                                             
+                                             
+
+                                           
+                                           
+                                           
+
+                         
+                         
+                                          
+                                         
+                        
+          
+
+                                      
+                       
+
+                                            
+
+
+
+
+
+                                    
+   
+                                  
+    
+                                   
+    
+                   
+     
+                                        
+    
+                        
+    
+
+
+
+
+
+                                   
+                                  
+                     
+                     
+        
+  
+                       
+                       
+                                               
+
+          
+         
+          
+         
+                 
+                     
+
+                           
+                                           
+                                              
+                                             
+
+                                        
+                
+             
+                                        
+                   
+
+  
+
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+ 
+
+
+
+
+
+   
+                     
+	  
+	   
+              
+               
+		 
+		  
+		    
+		     
+		     
+
+		      
+		    
+		     
+		      
+		      
+		      
+		      
+		      
+		      
+		      
+		      
+		          
+		     
+		      
+		         
+             
+           
+             
+		               
+		    
+		      
+		       
+			 
+			  
+			  
+
+			   
+			 
+			  
+			   
+			   
+			   
+			   
+			   
+			   
+			   
+			       
+			       
+			  
+			   
+			  
+		  
+             
+	   
+	   
+	    
+	     
+	       
+	        
+	        
+
+	         
+	       
+		
+		 
+		 
+		 
+		 
+		 
+		 
+		 
+		 
+		 
+		
+		  
+		
+	
+      
+   
+
+
+
+
+
+
+
+               
+      
+       
+    
+
+
+
+
+           
+	   
+   
+    
+        
+	   
+        
+    
+
+
+
+       
+    
+
+ 
+
+       
+          
+    
+    
+              
+              
+              
+              
+    
+
+    
+    
+    
+
+ 
+
+       
+          
+    
+          
+
+    
+
+
+
+ 
+        
+      
+                              
+                             
+    
+      
+                             
+                             
+
+   
+
+     
+                             
+                             
+   
+
+
+ 
+                                   
+     
+    
+   
+
+
+
+     
+       
+
+
+         
+
+
+
+        
+           
+             
+         
+     
+     
+      
+                 
+                 
+             
+             
+    
+
+
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+             
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+           
+     
+                      
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+        
+            
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+       
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+    
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+       
+          
+     
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+   
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+       
+    
+          
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+    
+     
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+         
+
+        
+        
+        
+               
+                  
+                
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+        
+        
+        
+               
+                  
+               
+            
+                  
+                  
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+            
+                
+                  
+        
+
+        
+        
+        
+              
+               
+            
+                   
+                
+                      
+                      
+                
+            
+        
+        
+                
+    
+
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+       
+    
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+   
+
+       
+          
+     
+    
+         
+        
+        
+        
+        
+               
+                  
+        
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+        
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+               
+                    
+        
+        
+                
+    
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+                  
+                    
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+                    
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+              
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+                  
+                    
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+                   
+              
+                  
+                 
+            
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+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
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+ 
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+ 
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+                   
+             
+               
+
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+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
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+ 
+
+
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+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
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+
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_debug_medium_icache_debug (
+    
+    clk_i, 
+    rst_i,
+    pc_x,
+    load_x,
+    store_x,
+    load_store_address_x,
+    csr_write_enable_x,
+    csr_write_data,
+    csr_x,
+  
+
+  
+
+    jtag_csr_write_enable,
+    jtag_csr_write_data,
+    jtag_csr,
+ 
+
+  
+   
+   
+   
+
+
+  
+
+
+		   
+  
+
+    eret_q_x,
+    bret_q_x,
+    stall_x,
+    exception_x,
+    q_x,
+  
+    
+
+
+ 
+
+
+    
+  
+
+    dc_ss,
+ 
+
+    dc_re,
+    bp_match,
+    wp_match
+    );
+    
+
+
+
+
+parameter breakpoints = 0;                      
+parameter watchpoints = 0;                      
+
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;                      
+input load_x;                                   
+input store_x;                                  
+input [ (32-1):0] load_store_address_x;    
+input csr_write_enable_x;                       
+input [ (32-1):0] csr_write_data;          
+input [ (5-1):0] csr_x;                    
+  
+
+  
+
+input jtag_csr_write_enable;                    
+input [ (32-1):0] jtag_csr_write_data;     
+input [ (5-1):0] jtag_csr;                 
+ 
+
+     
+                          
+            
+                          
+
+
+ 
+
+
+
+  
+
+input eret_q_x;                                 
+input bret_q_x;                                 
+input stall_x;                                  
+input exception_x;                              
+input q_x;                                      
+  
+                     
+
+
+ 
+
+
+
+
+
+
+  
+
+output dc_ss;                                   
+reg    dc_ss;
+ 
+
+output dc_re;                                   
+reg    dc_re;
+output bp_match;                                
+wire   bp_match;        
+output wp_match;                                
+wire   wp_match;
+
+
+
+
+
+genvar i;                                       
+
+
+
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] bp_a[0:breakpoints-1];       
+reg bp_e[0:breakpoints-1];                      
+wire [0:breakpoints-1]bp_match_n;               
+
+reg [ 1:0] wpc_c[0:watchpoints-1];   
+reg [ (32-1):0] wp[0:watchpoints-1];       
+wire [0:watchpoints-1]wp_match_n;               
+
+wire debug_csr_write_enable;                    
+wire [ (32-1):0] debug_csr_write_data;     
+wire [ (5-1):0] debug_csr;                 
+
+  
+
+
+reg [ 2:0] state;           
+
+ 
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+generate
+    for (i = 0; i < breakpoints; i = i + 1)
+    begin : bp_comb
+assign bp_match_n[i] = ((bp_a[i] == pc_x) && (bp_e[i] ==  1'b1));
+    end
+endgenerate
+generate 
+  
+
+    if (breakpoints > 0) 
+assign bp_match = (|bp_match_n) || (state ==  3'b011);
+    else
+assign bp_match = state ==  3'b011;
+ 
+        
+   
+    
+   
+
+
+endgenerate    
+               
+
+generate 
+    for (i = 0; i < watchpoints; i = i + 1)
+    begin : wp_comb
+assign wp_match_n[i] = (wp[i] == load_store_address_x) && ((load_x & wpc_c[i][0]) | (store_x & wpc_c[i][1]));
+    end               
+endgenerate
+generate
+    if (watchpoints > 0) 
+assign wp_match = |wp_match_n;                
+    else
+assign wp_match =  1'b0;
+endgenerate
+                
+  
+                
+
+  
+
+assign debug_csr_write_enable = (csr_write_enable_x ==  1'b1) || (jtag_csr_write_enable ==  1'b1);
+assign debug_csr_write_data = jtag_csr_write_enable ==  1'b1 ? jtag_csr_write_data : csr_write_data;
+assign debug_csr = jtag_csr_write_enable ==  1'b1 ? jtag_csr : csr_x;
+ 
+
+   
+  
+         
+         
+         
+
+
+
+   
+ 
+   
+   
+   
+
+
+
+
+
+
+
+
+generate
+    for (i = 0; i < breakpoints; i = i + 1)
+    begin : bp_seq
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        bp_a[i] <= { (clogb2(32'h7fffffff-32'h0)-2){1'bx}};
+        bp_e[i] <=  1'b0;
+    end
+    else
+    begin
+        if ((debug_csr_write_enable ==  1'b1) && (debug_csr ==  5'h10 + i))
+        begin
+            bp_a[i] <= debug_csr_write_data[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2];
+            bp_e[i] <= debug_csr_write_data[0];
+        end
+    end
+end    
+    end
+endgenerate
+
+
+generate
+    for (i = 0; i < watchpoints; i = i + 1)
+    begin : wp_seq
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        wp[i] <= { 32{1'bx}};
+        wpc_c[i] <=  2'b00;
+    end
+    else
+    begin
+        if (debug_csr_write_enable ==  1'b1)
+        begin
+            if (debug_csr ==  5'h8)
+                wpc_c[i] <= debug_csr_write_data[3+i*2:2+i*2];
+            if (debug_csr ==  5'h18 + i)
+                wp[i] <= debug_csr_write_data;
+        end
+    end  
+end
+    end
+endgenerate
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        dc_re <=  1'b0;
+    else
+    begin
+        if ((debug_csr_write_enable ==  1'b1) && (debug_csr ==  5'h8))
+            dc_re <= debug_csr_write_data[1];
+    end
+end    
+
+  
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        state <=  3'b000;
+        dc_ss <=  1'b0;
+    end
+    else
+    begin
+        if ((debug_csr_write_enable ==  1'b1) && (debug_csr ==  5'h8))
+        begin
+            dc_ss <= debug_csr_write_data[0];
+            if (debug_csr_write_data[0] ==  1'b0) 
+                state <=  3'b000;
+            else 
+                state <=  3'b001;
+        end
+        case (state)
+         3'b001:
+        begin
+            
+            if (   (   (eret_q_x ==  1'b1)
+                    || (bret_q_x ==  1'b1)
+                    )
+                && (stall_x ==  1'b0)
+               )
+                state <=  3'b010; 
+        end
+         3'b010:
+        begin
+            
+            if ((q_x ==  1'b1) && (stall_x ==  1'b0))
+                state <=  3'b011;
+        end
+         3'b011:
+        begin
+            
+  
+               
+                  
+             
+
+
+                 if ((exception_x ==  1'b1) && (q_x ==  1'b1) && (stall_x ==  1'b0))
+            begin
+                dc_ss <=  1'b0;
+                state <=  3'b100;
+            end
+        end
+         3'b100:
+        begin
+            
+  
+               
+                  
+             
+
+
+                state <=  3'b000;
+        end
+        endcase
+    end
+end
+ 
+
+
+endmodule
+
+ 
+
+
+
+
+
+
+
+
+
+
+
+
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+  
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+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_instruction_unit_medium_icache_debug (
+    
+    clk_i,
+    rst_i,
+    
+    stall_a,
+    stall_f,
+    stall_d,
+    stall_x,
+    stall_m,
+    valid_f,
+    valid_d,
+    kill_f,
+    branch_predict_taken_d,
+    branch_predict_address_d,
+      
+    
+    
+
+
+    exception_m,
+    branch_taken_m,
+    branch_mispredict_taken_m,
+    branch_target_m,
+  
+
+    iflush,
+ 
+
+  
+    
+    
+    
+
+        
+  
+
+    
+    i_dat_i,
+    i_ack_i,
+    i_err_i,
+    i_rty_i,
+ 
+
+  
+
+    jtag_read_enable,
+    jtag_write_enable,
+    jtag_write_data,
+    jtag_address,
+ 
+
+    
+    
+    pc_f,
+    pc_d,
+    pc_x,
+    pc_m,
+    pc_w,
+  
+
+    icache_stall_request,
+    icache_restart_request,
+    icache_refill_request,
+    icache_refilling,
+ 
+
+  
+
+    
+    i_dat_o,
+    i_adr_o,
+    i_cyc_o,
+    i_sel_o,
+    i_stb_o,
+    i_we_o,
+    i_cti_o,
+    i_lock_o,
+    i_bte_o,
+ 
+
+  
+    
+    
+    
+
+
+  
+
+    jtag_read_data,
+    jtag_access_complete,
+ 
+
+  
+    
+
+
+  
+
+    instruction_f,
+ 
+    
+    instruction_d
+    );
+
+
+
+
+
+parameter eba_reset =  32'h00000000;                   
+parameter associativity = 1;                            
+parameter sets = 512;                                   
+parameter bytes_per_line = 16;                          
+parameter base_address = 0;                             
+parameter limit = 0;                                    
+
+
+localparam eba_reset_minus_4 = eba_reset - 4;
+localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
+localparam addr_offset_lsb = 2;
+localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
+
+
+
+
+  
+  
+   
+        
+   
+
+
+
+input clk_i;                                            
+input rst_i;                                            
+
+input stall_a;                                          
+input stall_f;                                          
+input stall_d;                                          
+input stall_x;                                          
+input stall_m;                                          
+input valid_f;                                          
+input valid_d;                                          
+input kill_f;                                           
+
+input branch_predict_taken_d;                           
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d;          
+   
+      
+                                    
+                     
+
+
+input exception_m;
+input branch_taken_m;                                   
+input branch_mispredict_taken_m;                        
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_m;                   
+
+  
+
+input iflush;                                           
+ 
+
+  
+                            
+                             
+ 
+
+        
+
+
+  
+
+input [ (32-1):0] i_dat_i;                         
+input i_ack_i;                                          
+input i_err_i;                                          
+input i_rty_i;                                          
+ 
+
+
+  
+
+input jtag_read_enable;                                 
+input jtag_write_enable;                                
+input [ 7:0] jtag_write_data;                 
+input [ (32-1):0] jtag_address;                    
+ 
+
+
+
+
+
+        
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;                             
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;                             
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;                             
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;                             
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;                             
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;
+
+  
+
+output icache_stall_request;                            
+wire   icache_stall_request;
+output icache_restart_request;                          
+wire   icache_restart_request;
+output icache_refill_request;                           
+wire   icache_refill_request;
+output icache_refilling;                                
+wire   icache_refilling;
+ 
+
+
+  
+
+output [ (32-1):0] i_dat_o;                        
+  
+
+reg    [ (32-1):0] i_dat_o;
+ 
+    
+
+
+output [ (32-1):0] i_adr_o;                        
+reg    [ (32-1):0] i_adr_o;
+output i_cyc_o;                                         
+reg    i_cyc_o; 
+output [ (4-1):0] i_sel_o;                 
+  
+
+reg    [ (4-1):0] i_sel_o;
+ 
+    
+
+
+output i_stb_o;                                         
+reg    i_stb_o;
+output i_we_o;                                          
+  
+
+reg    i_we_o;
+ 
+   
+
+
+output [ (3-1):0] i_cti_o;                       
+reg    [ (3-1):0] i_cti_o;
+output i_lock_o;                                        
+reg    i_lock_o;
+output [ (2-1):0] i_bte_o;                       
+wire   [ (2-1):0] i_bte_o;
+ 
+
+
+  
+
+output [ 7:0] jtag_read_data;                 
+reg    [ 7:0] jtag_read_data;
+output jtag_access_complete;                            
+wire   jtag_access_complete;
+ 
+
+
+  
+                                      
+    
+
+
+  
+
+output [ (32-1):0] instruction_f;           
+wire   [ (32-1):0] instruction_f;
+ 
+
+output [ (32-1):0] instruction_d;           
+reg    [ (32-1):0] instruction_d;
+
+
+
+
+
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_a;                                
+
+  
+
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] restart_address;                     
+ 
+
+
+  
+
+wire icache_read_enable_f;                              
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] icache_refill_address;              
+reg icache_refill_ready;                                
+reg [ (32-1):0] icache_refill_data;         
+wire [ (32-1):0] icache_data_f;             
+wire [ (3-1):0] first_cycle_type;                
+wire [ (3-1):0] next_cycle_type;                 
+wire last_word;                                         
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] first_address;                      
+ 
+ 
+                    
+
+
+
+  
+                                      
+    			     
+   
+
+
+  
+
+ 
+               
+
+
+
+   
+  
+   
+    			               
+ 
+
+
+  
+    		       
+
+
+   
+  
+
+reg jtag_access;                                        
+ 
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+  
+
+
+lm32_icache_medium_icache_debug #(
+    .associativity          (associativity),
+    .sets                   (sets),
+    .bytes_per_line         (bytes_per_line),
+    .base_address           (base_address),
+    .limit                  (limit)
+    ) icache ( 
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),      
+    .stall_a                (stall_a),
+    .stall_f                (stall_f),
+    .branch_predict_taken_d (branch_predict_taken_d),
+    .valid_d                (valid_d),
+    .address_a              (pc_a),
+    .address_f              (pc_f),
+    .read_enable_f          (icache_read_enable_f),
+    .refill_ready           (icache_refill_ready),
+    .refill_data            (icache_refill_data),
+    .iflush                 (iflush),
+    
+    .stall_request          (icache_stall_request),
+    .restart_request        (icache_restart_request),
+    .refill_request         (icache_refill_request),
+    .refill_address         (icache_refill_address),
+    .refilling              (icache_refilling),
+    .inst                   (icache_data_f)
+    );
+ 
+
+
+
+
+
+
+  
+
+   
+   assign icache_read_enable_f =    (valid_f ==  1'b1)
+     && (kill_f ==  1'b0)
+   
+      
+ 
+                         
+    
+				       
+ 
+       
+				    ;
+ 
+ 
+
+
+always @(*)
+begin
+    
+  
+       
+          
+     
+
+    
+      if (branch_taken_m ==  1'b1)
+	if ((branch_mispredict_taken_m ==  1'b1) && (exception_m ==  1'b0))
+	  pc_a = pc_x;
+	else
+          pc_a = branch_target_m;
+      
+          
+          
+
+
+      else
+	if ( (valid_d ==  1'b1) && (branch_predict_taken_d ==  1'b1) )
+	  pc_a = branch_predict_address_d;
+	else
+  
+
+          if (icache_restart_request ==  1'b1)
+            pc_a = restart_address;
+	  else 
+ 
+        
+            pc_a = pc_f + 1'b1;
+end
+
+
+  
+      
+      
+        
+
+
+
+  
+
+     
+    	      
+
+     
+      
+	  
+       
+	  
+	
+	    
+     
+   
+   
+          
+
+
+  
+   
+
+
+                     
+
+  
+
+assign instruction_f = icache_data_f;
+ 
+   
+
+
+
+ 
+ 
+   
+
+  
+
+  
+
+ 
+   
+   
+   
+
+
+assign i_bte_o =  2'b00;
+ 
+
+
+  
+
+
+generate
+    case (bytes_per_line)
+    4:
+    begin
+assign first_cycle_type =  3'b111;
+assign next_cycle_type =  3'b111;
+assign last_word =  1'b1;
+assign first_address = icache_refill_address;
+    end
+    8:
+    begin
+assign first_cycle_type =  3'b010;
+assign next_cycle_type =  3'b111;
+assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 1'b1;
+assign first_address = {icache_refill_address[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
+    end
+    16:
+    begin
+assign first_cycle_type =  3'b010;
+assign next_cycle_type = i_adr_o[addr_offset_msb] == 1'b1 ?  3'b111 :  3'b010;
+assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 2'b11;
+assign first_address = {icache_refill_address[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
+    end
+    endcase
+endgenerate
+ 
+
+                     
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        pc_f <= eba_reset_minus_4[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2];
+        pc_d <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+        pc_x <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+        pc_m <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+        pc_w <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+    end
+    else
+    begin
+        if (stall_f ==  1'b0)
+            pc_f <= pc_a;
+        if (stall_d ==  1'b0)
+            pc_d <= pc_f;
+        if (stall_x ==  1'b0)
+            pc_x <= pc_d;
+        if (stall_m ==  1'b0)
+            pc_m <= pc_x;
+        pc_w <= pc_m;
+    end
+end
+
+  
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        restart_address <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+    else
+    begin
+  
+         
+            
+               
+                  
+                    
+                  
+
+               
+                  
+
+
+
+  
+        
+            if (icache_refill_request ==  1'b1)
+                restart_address <= icache_refill_address;
+ 
+
+ 
+
+    end
+end
+ 
+
+
+
+  
+   
+
+       
+          
+    
+    
+           
+              
+    
+
+
+
+
+  
+
+     
+
+assign jtag_access_complete = (i_cyc_o ==  1'b1) && ((i_ack_i ==  1'b1) || (i_err_i ==  1'b1)) && (jtag_access ==  1'b1);
+always @(*)
+begin
+    case (jtag_address[1:0])
+    2'b00: jtag_read_data = i_dat_i[ 31:24];
+    2'b01: jtag_read_data = i_dat_i[ 23:16];
+    2'b10: jtag_read_data = i_dat_i[ 15:8];
+    2'b11: jtag_read_data = i_dat_i[ 7:0];
+    endcase 
+end
+    
+
+ 
+
+
+  
+
+   
+   
+                
+   always @(posedge clk_i  )
+     begin
+	if (rst_i ==  1'b1)
+	  begin
+             i_cyc_o <=  1'b0;
+             i_stb_o <=  1'b0;
+             i_adr_o <= { 32{1'b0}};
+             i_cti_o <=  3'b111;
+             i_lock_o <=  1'b0;
+             icache_refill_data <= { 32{1'b0}};
+             icache_refill_ready <=  1'b0;
+    
+               
+  
+
+    
+
+             i_we_o <=  1'b0;
+             i_sel_o <= 4'b1111;
+             jtag_access <=  1'b0;
+   
+
+	  end
+	else
+	  begin   
+             icache_refill_ready <=  1'b0;
+             
+             if (i_cyc_o ==  1'b1)
+               begin
+		  
+		  if ((i_ack_i ==  1'b1) || (i_err_i ==  1'b1))
+		    begin
+    
+
+                       if (jtag_access ==  1'b1)
+			 begin
+			    i_cyc_o <=  1'b0;
+			    i_stb_o <=  1'b0;       
+			    i_we_o <=  1'b0;  
+			    jtag_access <=  1'b0;    
+			 end
+                       else
+   
+
+			 begin
+			    if (last_word ==  1'b1)
+			      begin
+				 
+				 i_cyc_o <=  1'b0;
+				 i_stb_o <=  1'b0;
+				 i_lock_o <=  1'b0;
+			      end
+			    
+			    i_adr_o[addr_offset_msb:addr_offset_lsb] <= i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
+			    i_cti_o <= next_cycle_type;
+			    
+			    icache_refill_ready <=  1'b1;
+			    icache_refill_data <= i_dat_i;
+			 end
+		    end
+    
+		   
+		     
+		    
+                         
+                         
+		    
+		  
+  
+
+               end
+             else
+               begin
+		  if ((icache_refill_request ==  1'b1) && (icache_refill_ready ==  1'b0))
+		    begin
+                       
+    
+     
+                       i_sel_o <= 4'b1111;
+   
+
+                       i_adr_o <= {first_address, 2'b00};
+                       i_cyc_o <=  1'b1;
+                       i_stb_o <=  1'b1;                
+                       i_cti_o <= first_cycle_type;
+                       
+    
+                         
+  
+
+		    end
+    
+
+		  else
+		    begin
+                       if ((jtag_read_enable ==  1'b1) || (jtag_write_enable ==  1'b1))
+			 begin
+			    case (jtag_address[1:0])
+			      2'b00: i_sel_o <= 4'b1000;
+			      2'b01: i_sel_o <= 4'b0100;
+			      2'b10: i_sel_o <= 4'b0010;
+			      2'b11: i_sel_o <= 4'b0001;
+			    endcase
+			    i_adr_o <= jtag_address;
+			    i_dat_o <= {4{jtag_write_data}};
+			    i_cyc_o <=  1'b1;
+			    i_stb_o <=  1'b1;
+			    i_we_o <= jtag_write_enable;
+			    i_cti_o <=  3'b111;
+			    jtag_access <=  1'b1;
+			 end
+		    end 
+   
+                    
+    
+		  
+		  
+        
+		     
+                      
+   
+		     
+                      
+  
+
+               end
+	  end
+     end
+  
+      
+     
+	   
+	  
+               
+               
+               
+               
+               
+               
+   
+               
+  
+	  
+	
+	     
+             
+                
+               
+		  
+		        
+		    
+                       
+                         
+                         
+                       
+                         
+		    
+   
+		   
+		     
+		    
+                         
+                         
+		       
+		    
+		  
+  
+               
+             
+               
+		  
+		         
+    
+			    
+         
+			 
+		    
+                       
+        
+                         
+  
+                          
+                         
+                         
+   
+                         
+  
+		    
+		  
+		    
+	                      
+    
+			         
+         
+			      
+			 
+   
+			      
+  
+			 
+		    
+               
+	  
+     
+ 
+
+ 
+ 
+
+   
+   always @(posedge clk_i  )
+     begin
+	if (rst_i ==  1'b1)
+	  begin
+             instruction_d <= { 32{1'b0}};
+  
+               
+
+
+	  end
+	else
+	  begin
+             if (stall_d ==  1'b0)
+               begin
+		  instruction_d <= instruction_f;
+  
+		    
+
+
+               end
+	  end
+     end  
+   
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+  
+
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_jtag_medium_icache_debug (
+    
+    clk_i,
+    rst_i,
+    jtag_clk, 
+    jtag_update,
+    jtag_reg_q,
+    jtag_reg_addr_q,
+  
+
+    csr,
+    csr_write_enable,
+    csr_write_data,
+    stall_x,
+ 
+
+  
+
+    jtag_read_data,
+    jtag_access_complete,
+ 
+
+  
+
+    exception_q_w,
+ 
+
+    
+  
+
+    jtx_csr_read_data,
+    jrx_csr_read_data,
+ 
+
+  
+
+    jtag_csr_write_enable,
+    jtag_csr_write_data,
+    jtag_csr,
+    jtag_read_enable,
+    jtag_write_enable,
+    jtag_write_data,
+    jtag_address,
+ 
+
+  
+
+    jtag_break,
+    jtag_reset,
+ 
+
+    jtag_reg_d,
+    jtag_reg_addr_d
+    );
+
+
+
+
+
+input clk_i;                                            
+input rst_i;                                            
+
+input jtag_clk;                                         
+input jtag_update;                                      
+input [ 7:0] jtag_reg_q;                      
+input [2:0] jtag_reg_addr_q;                            
+
+  
+
+input [ (5-1):0] csr;                              
+input csr_write_enable;                                 
+input [ (32-1):0] csr_write_data;                  
+input stall_x;                                          
+ 
+
+  
+
+input [ 7:0] jtag_read_data;                  
+input jtag_access_complete;                             
+ 
+
+  
+
+input exception_q_w;                                    
+ 
+
+
+
+
+
+       
+  
+
+output [ (32-1):0] jtx_csr_read_data;              
+wire   [ (32-1):0] jtx_csr_read_data;
+output [ (32-1):0] jrx_csr_read_data;              
+wire   [ (32-1):0] jrx_csr_read_data;
+ 
+
+  
+
+output jtag_csr_write_enable;                           
+reg    jtag_csr_write_enable;
+output [ (32-1):0] jtag_csr_write_data;            
+wire   [ (32-1):0] jtag_csr_write_data;
+output [ (5-1):0] jtag_csr;                        
+wire   [ (5-1):0] jtag_csr;
+output jtag_read_enable;                                
+reg    jtag_read_enable;
+output jtag_write_enable;                               
+reg    jtag_write_enable;
+output [ 7:0] jtag_write_data;                
+wire   [ 7:0] jtag_write_data;        
+output [ (32-1):0] jtag_address;                   
+wire   [ (32-1):0] jtag_address;
+ 
+
+  
+
+output jtag_break;                                      
+reg    jtag_break;
+output jtag_reset;                                      
+reg    jtag_reset;
+ 
+
+output [ 7:0] jtag_reg_d;
+reg    [ 7:0] jtag_reg_d;
+output [2:0] jtag_reg_addr_d;
+wire   [2:0] jtag_reg_addr_d;
+             
+
+
+
+
+reg rx_update;                          
+reg rx_update_r;                        
+reg rx_update_r_r;                      
+reg rx_update_r_r_r;                    
+
+
+
+wire [ 7:0] rx_byte;   
+wire [2:0] rx_addr;
+
+  
+                 
+reg [ 7:0] uart_tx_byte;      
+reg uart_tx_valid;                      
+reg [ 7:0] uart_rx_byte;      
+reg uart_rx_valid;                      
+ 
+
+
+reg [ 3:0] command;             
+  
+
+reg [ 7:0] jtag_byte_0;       
+reg [ 7:0] jtag_byte_1;
+reg [ 7:0] jtag_byte_2;
+reg [ 7:0] jtag_byte_3;
+reg [ 7:0] jtag_byte_4;
+reg processing;                         
+ 
+
+
+reg [ 3:0] state;       
+
+
+
+
+
+  
+
+assign jtag_csr_write_data = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
+assign jtag_csr = jtag_byte_4[ (5-1):0];
+assign jtag_address = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
+assign jtag_write_data = jtag_byte_4;
+ 
+
+                 
+
+  
+                 
+assign jtag_reg_addr_d[1:0] = {uart_rx_valid, uart_tx_valid};         
+ 
+   
+
+
+  
+
+assign jtag_reg_addr_d[2] = processing;
+ 
+   
+
+
+
+  
+                 
+assign jtx_csr_read_data = {{ 32-9{1'b0}}, uart_tx_valid, 8'h00};
+assign jrx_csr_read_data = {{ 32-9{1'b0}}, uart_rx_valid, uart_rx_byte};
+ 
+         
+                 
+
+
+
+
+assign rx_byte = jtag_reg_q;
+assign rx_addr = jtag_reg_addr_q;
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        rx_update <= 1'b0;
+        rx_update_r <= 1'b0;
+        rx_update_r_r <= 1'b0;
+        rx_update_r_r_r <= 1'b0;
+    end
+    else
+    begin
+        rx_update <= jtag_update;
+        rx_update_r <= rx_update;
+        rx_update_r_r <= rx_update_r;
+        rx_update_r_r_r <= rx_update_r_r;
+    end
+end
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        state <=  4'h0;
+        command <= 4'b0000;
+        jtag_reg_d <= 8'h00;
+  
+
+        processing <=  1'b0;
+        jtag_csr_write_enable <=  1'b0;
+        jtag_read_enable <=  1'b0;
+        jtag_write_enable <=  1'b0;
+ 
+
+  
+
+        jtag_break <=  1'b0;
+        jtag_reset <=  1'b0;
+ 
+
+  
+                 
+        uart_tx_byte <= 8'h00;
+        uart_tx_valid <=  1'b0;
+        uart_rx_byte <= 8'h00;
+        uart_rx_valid <=  1'b0;
+ 
+
+    end
+    else
+    begin
+  
+                 
+        if ((csr_write_enable ==  1'b1) && (stall_x ==  1'b0))
+        begin
+            case (csr)
+             5'he:
+            begin
+                
+                uart_tx_byte <= csr_write_data[ 7:0];
+                uart_tx_valid <=  1'b1;
+            end
+             5'hf:
+            begin
+                
+                uart_rx_valid <=  1'b0;
+            end
+            endcase
+        end
+ 
+
+  
+
+        
+        if (exception_q_w ==  1'b1)
+        begin
+            jtag_break <=  1'b0;
+            jtag_reset <=  1'b0;
+        end
+ 
+
+        case (state)
+         4'h0:
+        begin
+            
+            if ((~rx_update_r_r_r & rx_update_r_r) ==  1'b1)
+            begin
+                command <= rx_byte[7:4];                
+                case (rx_addr)
+  
+
+                 3'b000:
+                begin
+                    case (rx_byte[7:4])
+  
+
+                     4'b0001:
+                        state <=  4'h1;
+                     4'b0011:
+                    begin
+                        {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
+                        state <=  4'h6;
+                    end
+                     4'b0010:
+                        state <=  4'h1;
+                     4'b0100:
+                    begin
+                        {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
+                        state <= 5;
+                    end
+                     4'b0101:
+                        state <=  4'h1;
+ 
+                    
+                     4'b0110:
+                    begin
+  
+     
+                        uart_rx_valid <=  1'b0;    
+                        uart_tx_valid <=  1'b0;         
+ 
+
+                        jtag_break <=  1'b1;
+                    end
+                     4'b0111:
+                    begin
+  
+     
+                        uart_rx_valid <=  1'b0;    
+                        uart_tx_valid <=  1'b0;         
+ 
+
+                        jtag_reset <=  1'b1;
+                    end
+                    endcase                               
+                end
+ 
+
+  
+                 
+                 3'b001:
+                begin
+                    uart_rx_byte <= rx_byte;
+                    uart_rx_valid <=  1'b1;
+                end                    
+                 3'b010:
+                begin
+                    jtag_reg_d <= uart_tx_byte;
+                    uart_tx_valid <=  1'b0;
+                end
+ 
+
+                default:
+                    ;
+                endcase                
+            end
+        end
+  
+
+         4'h1:
+        begin
+            if ((~rx_update_r_r_r & rx_update_r_r) ==  1'b1)
+            begin
+                jtag_byte_0 <= rx_byte;
+                state <=  4'h2;
+            end
+        end
+         4'h2:
+        begin
+            if ((~rx_update_r_r_r & rx_update_r_r) ==  1'b1)
+            begin
+                jtag_byte_1 <= rx_byte;
+                state <=  4'h3;
+            end
+        end
+         4'h3:
+        begin
+            if ((~rx_update_r_r_r & rx_update_r_r) ==  1'b1)
+            begin
+                jtag_byte_2 <= rx_byte;
+                state <=  4'h4;
+            end
+        end
+         4'h4:
+        begin
+            if ((~rx_update_r_r_r & rx_update_r_r) ==  1'b1)
+            begin
+                jtag_byte_3 <= rx_byte;
+                if (command ==  4'b0001)
+                    state <=  4'h6;
+                else 
+                    state <=  4'h5;
+            end
+        end
+         4'h5:
+        begin
+            if ((~rx_update_r_r_r & rx_update_r_r) ==  1'b1)
+            begin
+                jtag_byte_4 <= rx_byte;
+                state <=  4'h6;
+            end
+        end
+         4'h6:
+        begin
+            case (command)
+             4'b0001,
+             4'b0011:
+            begin
+                jtag_read_enable <=  1'b1;
+                processing <=  1'b1;
+                state <=  4'h7;
+            end
+             4'b0010,
+             4'b0100:
+            begin
+                jtag_write_enable <=  1'b1;
+                processing <=  1'b1;
+                state <=  4'h7;
+            end
+             4'b0101:
+            begin
+                jtag_csr_write_enable <=  1'b1;
+                processing <=  1'b1;
+                state <=  4'h8;
+            end
+            endcase
+        end
+         4'h7:
+        begin
+            if (jtag_access_complete ==  1'b1)
+            begin          
+                jtag_read_enable <=  1'b0;
+                jtag_reg_d <= jtag_read_data;
+                jtag_write_enable <=  1'b0;  
+                processing <=  1'b0;
+                state <=  4'h0;
+            end
+        end    
+         4'h8:
+        begin
+            jtag_csr_write_enable <=  1'b0;
+            processing <=  1'b0;
+            state <=  4'h0;
+        end    
+ 
+
+        endcase
+    end
+end
+  
+endmodule
+
+ 
+
+
+
+
+
+
+
+
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+  
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+ 
+ 
+
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+
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+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
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+ 
+ 
+
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+ 
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+ 
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+ 
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+ 
+ 
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+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_interrupt_medium_icache_debug (
+    
+    clk_i, 
+    rst_i,
+    
+    interrupt,
+    
+    stall_x,
+  
+
+    non_debug_exception,
+    debug_exception,
+ 
+    
+
+
+    eret_q_x,
+  
+
+    bret_q_x,
+ 
+
+    csr,
+    csr_write_data,
+    csr_write_enable,
+    
+    interrupt_exception,
+    
+    csr_read_data
+    );
+
+
+
+
+
+parameter interrupts =  32;         
+
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+
+input [interrupts-1:0] interrupt;               
+
+input stall_x;                                  
+
+  
+
+input non_debug_exception;                      
+input debug_exception;                          
+ 
+                                 
+
+
+input eret_q_x;                                 
+  
+
+input bret_q_x;                                 
+ 
+
+
+input [ (5-1):0] csr;                      
+input [ (32-1):0] csr_write_data;          
+input csr_write_enable;                         
+
+
+
+
+
+output interrupt_exception;                     
+wire   interrupt_exception;
+
+output [ (32-1):0] csr_read_data;          
+reg    [ (32-1):0] csr_read_data;
+
+
+
+
+
+wire [interrupts-1:0] asserted;                 
+
+wire [interrupts-1:0] interrupt_n_exception;
+
+
+
+reg ie;                                         
+reg eie;                                        
+  
+
+reg bie;                                        
+ 
+
+reg [interrupts-1:0] ip;                        
+reg [interrupts-1:0] im;                        
+
+
+
+
+
+
+assign interrupt_n_exception = ip & im;
+
+
+assign interrupt_exception = (|interrupt_n_exception) & ie;
+
+
+assign asserted = ip | interrupt;
+       
+generate
+    if (interrupts > 1) 
+    begin
+
+always @(*)
+begin
+    case (csr)
+     5'h0:  csr_read_data = {{ 32-3{1'b0}}, 
+  
+
+                                    bie,
+ 
+                                                                         
+
+
+                                    eie, 
+                                    ie
+                                   };
+     5'h2:  csr_read_data = ip;
+     5'h1:  csr_read_data = im;
+    default:       csr_read_data = { 32{1'bx}};
+    endcase
+end
+    end
+    else
+    begin
+
+always @(*)
+begin
+    case (csr)
+     5'h0:  csr_read_data = {{ 32-3{1'b0}}, 
+  
+
+                                    bie, 
+ 
+                                                                        
+
+
+                                    eie, 
+                                    ie
+                                   };
+     5'h2:  csr_read_data = ip;
+    default:       csr_read_data = { 32{1'bx}};
+      endcase
+end
+    end
+endgenerate
+    
+
+
+
+
+  
+
+   reg [ 10:0] eie_delay  = 0;
+
+   
+generate
+
+   
+    if (interrupts > 1)
+    begin
+
+always @(posedge clk_i  )
+  begin
+    if (rst_i ==  1'b1)
+    begin
+        ie                   <=  1'b0;
+        eie                  <=  1'b0;
+  
+
+        bie                  <=  1'b0;
+ 
+
+        im                   <= {interrupts{1'b0}};
+        ip                   <= {interrupts{1'b0}};
+       eie_delay             <= 0;
+       
+    end
+    else
+    begin
+        
+        ip                   <= asserted;
+  
+
+        if (non_debug_exception ==  1'b1)
+        begin
+            
+            eie              <= ie;
+            ie               <=  1'b0;
+        end
+        else if (debug_exception ==  1'b1)
+        begin
+            
+            bie              <= ie;
+            ie               <=  1'b0;
+        end
+ 
+           
+        
+            
+                           
+                            
+        
+
+
+        else if (stall_x ==  1'b0)
+        begin
+
+           if(eie_delay[0])
+             ie              <= eie;
+           
+           eie_delay         <= {1'b0, eie_delay[ 10:1]};
+
+            if (eret_q_x ==  1'b1) begin
+                
+               eie_delay[ 10] <=  1'b1;
+               eie_delay[ 10-1:0] <= 0;
+            end
+           
+                      
+           
+  
+
+            else if (bret_q_x ==  1'b1)
+                
+                ie      <= bie;
+ 
+
+            else if (csr_write_enable ==  1'b1)
+            begin
+                
+                if (csr ==  5'h0)
+                begin
+                    ie  <= csr_write_data[0];
+                    eie <= csr_write_data[1];
+  
+
+                    bie <= csr_write_data[2];
+ 
+
+                end
+                if (csr ==  5'h1)
+                    im  <= csr_write_data[interrupts-1:0];
+                if (csr ==  5'h2)
+                    ip  <= asserted & ~csr_write_data[interrupts-1:0];
+            end
+        end
+    end
+end
+    end
+else
+    begin
+
+always @(posedge clk_i  )
+  begin
+    if (rst_i ==  1'b1)
+    begin
+        ie              <=  1'b0;
+        eie             <=  1'b0;
+  
+
+        bie             <=  1'b0;
+ 
+
+        ip              <= {interrupts{1'b0}};
+       eie_delay        <= 0;
+    end
+    else
+    begin
+        
+        ip              <= asserted;
+  
+
+        if (non_debug_exception ==  1'b1)
+        begin
+            
+            eie         <= ie;
+            ie          <=  1'b0;
+        end
+        else if (debug_exception ==  1'b1)
+        begin
+            
+            bie         <= ie;
+            ie          <=  1'b0;
+        end
+ 
+           
+        
+            
+                      
+                       
+        
+
+
+        else if (stall_x ==  1'b0)
+          begin
+
+             if(eie_delay[0])
+               ie              <= eie;
+           
+             eie_delay         <= {1'b0, eie_delay[ 10:1]};
+
+             if (eret_q_x ==  1'b1) begin
+                
+                eie_delay[ 10] <=  1'b1;
+                eie_delay[ 10-1:0] <= 0;
+             end
+           
+  
+
+            else if (bret_q_x ==  1'b1)
+                
+                ie      <= bie;
+ 
+
+            else if (csr_write_enable ==  1'b1)
+            begin
+                
+                if (csr ==  5'h0)
+                begin
+                    ie  <= csr_write_data[0];
+                    eie <= csr_write_data[1];
+  
+
+                    bie <= csr_write_data[2];
+ 
+
+                end
+                if (csr ==  5'h2)
+                    ip  <= asserted & ~csr_write_data[interrupts-1:0];
+            end
+        end
+    end
+end
+    end
+endgenerate
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+  
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+  
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+	  
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+	  
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+	  
+	 
+	 
+	 
+	 
+	
+
+ 
+
+
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+  
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+
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+
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+  
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+  
+
+  
+
+
+
+  
+                    
+
+
+  
+
+  
+
+ 
+  
+                    
+
+
+ 
+
+  
+
+
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+  
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+
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+
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+ 
+
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+ 
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+ 
+
+ 
+
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+  
+ 
+
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+  
+ 
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+  
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+ 
+
+ 
+ 
+
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+  
+ 
+
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+  
+ 
+
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+ 
+
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+  
+ 
+
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+ 
+
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+ 
+
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+  
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+
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+
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+
+  
+                   
+                     
+
+
+  
+                   
+                     
+
+
+  
+
+  
+
+ 
+
+ 
+
+
+
+  
+
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+
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+  
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+  
+
+  
+
+  
+
+  
+                      
+                    
+
+
+  
+
+  
+
+  
+
+  
+                     
+                     
+
+
+  
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+
+ 
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
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+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+  
+
+  
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+
+  
+
+  
+
+
+
+  
+ 
+
+
+  
+ 
+
+
+ 
+
+
+
+
+
+
+
+  
+
+  
+
+  
+
+
+
+
+
+
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+
+
+  
+
+
+
+
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+ 
+
+
+
+
+
+
+
+
+module lm32_top_minimal (
+    
+    clk_i,
+    rst_i,
+    
+
+    interrupt,
+
+    
+  
+    
+    
+
+     
+  
+
+    
+    I_DAT_I,
+    I_ACK_I,
+    I_ERR_I,
+    I_RTY_I,
+ 
+
+    
+    D_DAT_I,
+    D_ACK_I,
+    D_ERR_I,
+    D_RTY_I,
+    
+      
+    
+    
+    
+    
+
+    
+  
+
+    
+    I_DAT_O,
+    I_ADR_O,
+    I_CYC_O,
+    I_SEL_O,
+    I_STB_O,
+    I_WE_O,
+    I_CTI_O,
+    I_LOCK_O,
+    I_BTE_O,
+ 
+
+    
+    D_DAT_O,
+    D_ADR_O,
+    D_CYC_O,
+    D_SEL_O,
+    D_STB_O,
+    D_WE_O,
+    D_CTI_O,
+    D_LOCK_O,
+    D_BTE_O
+    );
+
+parameter eba_reset = 32'h00000000;
+parameter sdb_address = 32'h00000000;
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+
+
+input [ (32-1):0] interrupt;          
+
+
+  
+               
+                             
+
+    
+
+  
+
+input [ (32-1):0] I_DAT_I;                 
+input I_ACK_I;                                  
+input I_ERR_I;                                  
+input I_RTY_I;                                  
+ 
+
+
+input [ (32-1):0] D_DAT_I;                 
+input D_ACK_I;                                  
+input D_ERR_I;                                  
+input D_RTY_I;                                  
+
+
+
+
+
+  
+                               
+   
+       
+     
+           
+    
+           
+    
+
+
+
+  
+
+output [ (32-1):0] I_DAT_O;                
+wire   [ (32-1):0] I_DAT_O;
+output [ (32-1):0] I_ADR_O;                
+wire   [ (32-1):0] I_ADR_O;
+output I_CYC_O;                                 
+wire   I_CYC_O;
+output [ (4-1):0] I_SEL_O;         
+wire   [ (4-1):0] I_SEL_O;
+output I_STB_O;                                 
+wire   I_STB_O;
+output I_WE_O;                                  
+wire   I_WE_O;
+output [ (3-1):0] I_CTI_O;               
+wire   [ (3-1):0] I_CTI_O;
+output I_LOCK_O;                                
+wire   I_LOCK_O;
+output [ (2-1):0] I_BTE_O;               
+wire   [ (2-1):0] I_BTE_O;
+ 
+
+
+output [ (32-1):0] D_DAT_O;                
+wire   [ (32-1):0] D_DAT_O;
+output [ (32-1):0] D_ADR_O;                
+wire   [ (32-1):0] D_ADR_O;
+output D_CYC_O;                                 
+wire   D_CYC_O;
+output [ (4-1):0] D_SEL_O;         
+wire   [ (4-1):0] D_SEL_O;
+output D_STB_O;                                 
+wire   D_STB_O;
+output D_WE_O;                                  
+wire   D_WE_O;
+output [ (3-1):0] D_CTI_O;               
+wire   [ (3-1):0] D_CTI_O;
+output D_LOCK_O;                                
+wire   D_LOCK_O;
+output [ (2-1):0] D_BTE_O;               
+wire   [ (2-1):0] D_BTE_O;
+  
+
+
+
+ 
+  
+
+  
+  
+ 
+  
+  
+ 
+ 
+
+
+
+
+  
+
+                     
+                             
+                            
+                   
+                                 
+ 
+                                 
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+   
+
+lm32_cpu_minimal 
+	#(
+		.eba_reset(eba_reset),
+    .sdb_address(sdb_address)
+	) cpu (
+    
+    .clk_i                 (clk_i),
+  
+                   
+
+
+    .rst_i                 (rst_i),
+    
+  
+
+    .interrupt             (interrupt),
+ 
+
+    
+  
+               
+             
+
+     
+  
+    
+                  
+               
+                
+           
+
+
+  
+
+     
+    .I_DAT_I               (I_DAT_I),
+    .I_ACK_I               (I_ACK_I),
+    .I_ERR_I               (I_ERR_I),
+    .I_RTY_I               (I_RTY_I),
+ 
+
+    
+    .D_DAT_I               (D_DAT_I),
+    .D_ACK_I               (D_ACK_I),
+    .D_ERR_I               (D_ERR_I),
+    .D_RTY_I               (D_RTY_I),
+    
+  
+                  
+            
+           
+                 
+                
+ 
+                
+
+
+
+  
+                
+           
+
+
+      
+                
+               
+            
+            
+
+    
+  
+
+    
+    .I_DAT_O               (I_DAT_O),
+    .I_ADR_O               (I_ADR_O),
+    .I_CYC_O               (I_CYC_O),
+    .I_SEL_O               (I_SEL_O),
+    .I_STB_O               (I_STB_O),
+    .I_WE_O                (I_WE_O),
+    .I_CTI_O               (I_CTI_O),
+    .I_LOCK_O              (I_LOCK_O),
+    .I_BTE_O               (I_BTE_O),
+     
+
+    
+    .D_DAT_O               (D_DAT_O),
+    .D_ADR_O               (D_ADR_O),
+    .D_CYC_O               (D_CYC_O),
+    .D_SEL_O               (D_SEL_O),
+    .D_STB_O               (D_STB_O),
+    .D_WE_O                (D_WE_O),
+    .D_CTI_O               (D_CTI_O),
+    .D_LOCK_O              (D_LOCK_O),
+    .D_BTE_O               (D_BTE_O)
+    );
+   
+  		   
+
+  
+    
+                     
+                
+    
+                
+                     
+                
+                      
+                     
+    
+
+        
+   
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+           
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_mc_arithmetic_minimal (
+    
+    clk_i,
+    rst_i,
+    stall_d,
+    kill_x,
+  
+    
+    
+
+
+  
+    
+
+
+  
+    
+    
+    
+
+
+    operand_0_d,
+    operand_1_d,
+    
+    result_x,
+  
+    
+
+
+    stall_request_x
+    );
+
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+input stall_d;                                  
+input kill_x;                                   
+  
+                                  
+                                 
+
+
+  
+                                
+
+
+  
+                              
+                             
+                             
+
+
+input [ (32-1):0] operand_0_d;
+input [ (32-1):0] operand_1_d;
+
+
+
+
+
+output [ (32-1):0] result_x;               
+reg    [ (32-1):0] result_x;
+  
+                         
+    
+
+
+output stall_request_x;                         
+wire   stall_request_x;
+
+
+
+
+
+reg [ (32-1):0] p;                         
+reg [ (32-1):0] a;
+reg [ (32-1):0] b;
+  
+  
+
+
+
+reg [ 2:0] state;                 
+reg [5:0] cycles;                               
+
+  
+                               
+                                 
+
+
+
+
+
+
+
+
+assign stall_request_x = state !=  3'b000;
+
+  
+
+      
+
+
+
+  
+
+       
+
+
+
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        cycles <= {6{1'b0}};
+        p <= { 32{1'b0}};
+        a <= { 32{1'b0}};
+        b <= { 32{1'b0}};
+  
+          
+
+
+  
+          
+
+
+        result_x <= { 32{1'b0}};
+        state <=  3'b000;
+    end
+    else
+    begin
+  
+          
+
+
+        case (state)
+         3'b000:
+        begin
+            if (stall_d ==  1'b0)                 
+            begin          
+                cycles <=  32;
+                p <= 32'b0;
+                a <= operand_0_d;
+                b <= operand_1_d;                    
+  
+                   
+                      
+                   
+                      
+
+                    
+  
+                   
+                      
+
+
+  
+                   
+                
+                      
+                      
+                      
+                      
+                      
+                
+                   
+                
+                      
+                      
+                      
+                      
+                      
+                
+
+
+            end            
+        end
+  
+        
+        
+               
+            
+                  
+                   
+            
+             
+            
+                   
+                   
+            
+              
+                   
+            
+                
+                    
+                  
+            
+                
+        
+        
+        
+               
+            
+                  
+                   
+            
+             
+            
+                   
+                   
+            
+              
+                   
+            
+                
+                    
+                  
+            
+                
+        
+
+        
+  
+        
+        
+               
+                    
+               
+               
+              
+                   
+                  
+                
+        
+
+     
+  
+        
+               
+               
+              
+                   
+                  
+                
+        
+        
+               
+               
+              
+                   
+                  
+                
+        
+
+   
+        endcase
+    end
+end 
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_cpu_minimal (
+    
+    clk_i,
+  
+    
+
+
+    rst_i,
+  
+    
+
+
+  
+   
+   
+   
+   
+   
+   
+
+
+
+    
+  
+
+    interrupt,
+ 
+
+    
+  
+    
+    
+
+     
+  
+    
+    
+     
+    
+    
+
+
+  
+
+    
+    I_DAT_I,
+    I_ACK_I,
+    I_ERR_I,
+    I_RTY_I,
+ 
+
+    
+    D_DAT_I,
+    D_ACK_I,
+    D_ERR_I,
+    D_RTY_I,
+    
+  
+    
+    
+    
+    
+    
+ 
+    
+
+
+
+  
+    
+    
+
+
+      
+    
+    
+    
+    
+
+    
+  
+
+    
+    I_DAT_O,
+    I_ADR_O,
+    I_CYC_O,
+    I_SEL_O,
+    I_STB_O,
+    I_WE_O,
+    I_CTI_O,
+    I_LOCK_O,
+    I_BTE_O,
+ 
+ 
+  
+    
+    
+    
+    
+    
+    
+    
+    
+           
+
+
+		 
+		 
+    
+    D_DAT_O,
+    D_ADR_O,
+    D_CYC_O,
+    D_SEL_O,
+    D_STB_O,
+    D_WE_O,
+    D_CTI_O,
+    D_LOCK_O,
+    D_BTE_O
+
+		 
+    );
+
+
+
+
+
+parameter eba_reset =  32'h00000000;                           
+  
+                            
+
+
+parameter sdb_address =   32'h00000000;
+
+  
+        
+                          
+      
+          
+                        
+
+
+parameter icache_associativity = 1;    
+parameter icache_sets = 512;                      
+parameter icache_bytes_per_line = 16;  
+parameter icache_base_address = 0;      
+parameter icache_limit = 0;                    
+ 
+
+
+  
+        
+                          
+      
+          
+                        
+
+
+parameter dcache_associativity = 1;    
+parameter dcache_sets = 512;                      
+parameter dcache_bytes_per_line = 16;  
+parameter dcache_base_address = 0;      
+parameter dcache_limit = 0;                    
+ 
+
+
+  
+                          
+
+
+parameter watchpoints = 0;
+ 
+
+  
+                          
+
+
+parameter breakpoints = 0;
+ 
+
+
+  
+
+parameter interrupts =  32;                         
+ 
+   
+
+
+
+
+
+
+
+input clk_i;                                    
+  
+                                   
+
+    
+input rst_i;                                    
+
+  
+
+input [ (32-1):0] interrupt;          
+ 
+
+
+  
+               
+                             
+
+    
+
+   
+                                  
+                               
+                
+  
+
+
+
+  
+
+input [ (32-1):0] I_DAT_I;                 
+input I_ACK_I;                                  
+input I_ERR_I;                                  
+input I_RTY_I;                                  
+ 
+
+
+input [ (32-1):0] D_DAT_I;                 
+input D_ACK_I;                                  
+input D_ERR_I;                                  
+input D_RTY_I;                                  
+
+
+
+
+
+  
+    
+     
+
+
+   
+   
+  
+                   
+     
+                           
+    
+                          
+    
+                 
+     
+                               
+    
+ 
+                               
+    
+
+
+
+
+  
+  
+    
+  
+    
+
+
+
+  
+                               
+   
+       
+     
+           
+    
+           
+    
+
+
+
+  
+
+output [ (32-1):0] I_DAT_O;                
+wire   [ (32-1):0] I_DAT_O;
+output [ (32-1):0] I_ADR_O;                
+wire   [ (32-1):0] I_ADR_O;
+output I_CYC_O;                                 
+wire   I_CYC_O;
+output [ (4-1):0] I_SEL_O;         
+wire   [ (4-1):0] I_SEL_O;
+output I_STB_O;                                 
+wire   I_STB_O;
+output I_WE_O;                                  
+wire   I_WE_O;
+output [ (3-1):0] I_CTI_O;               
+wire   [ (3-1):0] I_CTI_O;
+output I_LOCK_O;                                
+wire   I_LOCK_O;
+output [ (2-1):0] I_BTE_O;               
+wire   [ (2-1):0] I_BTE_O;
+ 
+
+
+output [ (32-1):0] D_DAT_O;                
+wire   [ (32-1):0] D_DAT_O;
+output [ (32-1):0] D_ADR_O;                
+wire   [ (32-1):0] D_ADR_O;
+output D_CYC_O;                                 
+wire   D_CYC_O;
+output [ (4-1):0] D_SEL_O;         
+wire   [ (4-1):0] D_SEL_O;
+output D_STB_O;                                 
+wire   D_STB_O;
+output D_WE_O;                                  
+wire   D_WE_O;
+output [ (3-1):0] D_CTI_O;               
+wire   [ (3-1):0] D_CTI_O;
+output D_LOCK_O;                                
+wire   D_LOCK_O;
+output [ (2-1):0] D_BTE_O;               
+wire   [ (2-1):0] D_BTE_O;
+
+  
+      
+     
+       
+      
+             
+
+
+   
+
+
+
+
+
+
+  
+                                     
+
+
+reg valid_f;                                    
+reg valid_d;                                    
+reg valid_x;                                    
+reg valid_m;                                    
+reg valid_w;                                    
+   
+wire q_x;
+wire [ (32-1):0] immediate_d;              
+wire load_d;                                    
+reg load_x;                                     
+reg load_m;
+wire load_q_x;
+wire store_q_x;
+wire q_m;
+wire load_q_m;
+wire store_q_m;
+wire store_d;                                   
+reg store_x;
+reg store_m;
+wire [ 1:0] size_d;                   
+reg [ 1:0] size_x;
+wire branch_d;                                  
+wire branch_predict_d;                          
+wire branch_predict_taken_d;                    
+wire [ ((32-2)+2-1):2] branch_predict_address_d;   
+wire [ ((32-2)+2-1):2] branch_target_d;
+wire bi_unconditional;
+wire bi_conditional;
+reg branch_x;                                   
+reg branch_predict_x;
+reg branch_predict_taken_x;
+reg branch_m;
+reg branch_predict_m;
+reg branch_predict_taken_m;
+wire branch_mispredict_taken_m;                 
+wire branch_flushX_m;                           
+wire branch_reg_d;                              
+wire [ ((32-2)+2-1):2] branch_offset_d;            
+reg [ ((32-2)+2-1):2] branch_target_x;             
+reg [ ((32-2)+2-1):2] branch_target_m;
+wire [ 0:0] d_result_sel_0_d; 
+wire [ 1:0] d_result_sel_1_d; 
+
+wire x_result_sel_csr_d;                        
+reg x_result_sel_csr_x;
+  
+ 
+                    
+ 
+
+
+  
+    
+wire x_result_sel_shift_d;                      
+reg x_result_sel_shift_x;
+ 
+
+  
+                        
+ 
+
+
+wire x_result_sel_logic_d;                      
+  
+                        
+ 
+
+
+wire x_result_sel_add_d;                        
+reg x_result_sel_add_x;
+wire m_result_sel_compare_d;                    
+reg m_result_sel_compare_x;
+reg m_result_sel_compare_m;
+  
+                       
+ 
+ 
+
+
+wire w_result_sel_load_d;                       
+reg w_result_sel_load_x;
+reg w_result_sel_load_m;
+reg w_result_sel_load_w;
+  
+                         
+ 
+ 
+ 
+
+
+wire x_bypass_enable_d;                         
+reg x_bypass_enable_x;                          
+wire m_bypass_enable_d;                         
+reg m_bypass_enable_x;                          
+reg m_bypass_enable_m;
+wire sign_extend_d;                             
+reg sign_extend_x;
+wire write_enable_d;                            
+reg write_enable_x;
+wire write_enable_q_x;
+reg write_enable_m;
+wire write_enable_q_m;
+reg write_enable_w;
+wire write_enable_q_w;
+wire read_enable_0_d;                           
+wire [ (5-1):0] read_idx_0_d;          
+wire read_enable_1_d;                           
+wire [ (5-1):0] read_idx_1_d;          
+wire [ (5-1):0] write_idx_d;           
+reg [ (5-1):0] write_idx_x;            
+reg [ (5-1):0] write_idx_m;
+reg [ (5-1):0] write_idx_w;
+wire [ (4 -1):0] csr_d;                     
+reg  [ (4 -1):0] csr_x;                  
+wire [ (3-1):0] condition_d;         
+reg [ (3-1):0] condition_x;          
+  
+                                    
+                                     
+
+
+wire scall_d;                                   
+reg scall_x;    
+wire eret_d;                                    
+reg eret_x;
+wire eret_q_x;
+  
+ 
+ 
+
+
+  
+                                     
+ 
+ 
+ 
+ 
+ 
+
+
+
+wire csr_write_enable_d;                        
+reg csr_write_enable_x;
+wire csr_write_enable_q_x;
+  
+       
+
+
+
+  
+                                
+ 
+ 
+  
+
+
+
+reg [ (32-1):0] d_result_0;                
+reg [ (32-1):0] d_result_1;                
+reg [ (32-1):0] x_result;                  
+reg [ (32-1):0] m_result;                  
+reg [ (32-1):0] w_result;                  
+
+reg [ (32-1):0] operand_0_x;               
+reg [ (32-1):0] operand_1_x;               
+reg [ (32-1):0] store_operand_x;           
+reg [ (32-1):0] operand_m;                 
+reg [ (32-1):0] operand_w;                 
+
+
+  
+
+reg [ (32-1):0] reg_data_live_0;          
+reg [ (32-1):0] reg_data_live_1;  
+reg use_buf;                                    
+reg [ (32-1):0] reg_data_buf_0;
+reg [ (32-1):0] reg_data_buf_1;
+ 
+
+  
+
+ 
+     
+
+
+wire [ (32-1):0] reg_data_0;               
+wire [ (32-1):0] reg_data_1;               
+reg [ (32-1):0] bypass_data_0;             
+reg [ (32-1):0] bypass_data_1;             
+wire reg_write_enable_q_w;
+
+reg interlock;                                  
+
+wire stall_a;                                   
+wire stall_f;                                   
+wire stall_d;                                   
+wire stall_x;                                   
+wire stall_m;                                   
+
+
+wire adder_op_d;                                
+reg adder_op_x;                                 
+reg adder_op_x_n;                               
+wire [ (32-1):0] adder_result_x;           
+wire adder_overflow_x;                          
+wire adder_carry_n_x;                           
+
+
+wire [ 3:0] logic_op_d;           
+reg [ 3:0] logic_op_x;            
+wire [ (32-1):0] logic_result_x;           
+
+  
+
+             
+             
+              
+
+
+
+
+  
+ 
+                                   
+                                     
+
+                                
+                                         
+           
+
+
+  
+                               
+ 
+                              
+ 
+
+
+  
+
+wire [ (32-1):0] shifter_result_x;         
+ 
+
+
+
+  
+        
+
+
+  
+                                 
+ 
+
+
+
+
+  
+                                   
+ 
+ 
+ 
+                           
+
+
+
+
+  
+                         
+  
+
+
+
+
+  
+
+wire [ (32-1):0] interrupt_csr_read_data_x;
+ 
+
+wire [ (32-1):0] cfg;                      
+wire [ (32-1):0] cfg2;                     
+  
+                          
+
+
+reg [ (32-1):0] csr_read_data_x;           
+
+
+wire [ ((32-2)+2-1):2] pc_f;                       
+wire [ ((32-2)+2-1):2] pc_d;                       
+wire [ ((32-2)+2-1):2] pc_x;                       
+wire [ ((32-2)+2-1):2] pc_m;                       
+wire [ ((32-2)+2-1):2] pc_w;                       
+  
+                          
+
+
+  
+
+wire [ (32-1):0] instruction_f;     
+ 
+
+
+
+wire [ (32-1):0] instruction_d;     
+  
+                                     
+                       
+                     
+                      
+                           
+
+
+
+
+  
+                                   
+                                     
+                       
+                     
+                      
+                           
+
+
+wire [ (32-1):0] load_data_w;              
+wire stall_wb_load;                             
+
+
+  
+ 
+          
+          
+
+ 
+                      
+        
+                    
+                           
+  
+ 
+  
+  
+ 
+
+ 
+                                 
+
+
+
+
+
+wire raw_x_0;                                   
+wire raw_x_1;                                   
+wire raw_m_0;                                   
+wire raw_m_1;                                   
+wire raw_w_0;                                   
+wire raw_w_1;                                   
+
+
+wire cmp_zero;                                  
+wire cmp_negative;                              
+wire cmp_overflow;                              
+wire cmp_carry_n;                               
+reg condition_met_x;                            
+reg condition_met_m;
+      
+                             
+
+
+wire branch_taken_m;                            
+
+wire kill_f;                                    
+wire kill_d;                                    
+wire kill_x;                                    
+wire kill_m;                                    
+wire kill_w;                                    
+
+reg [ (32-2)+2-1:8] eba;                 
+  
+                  
+
+
+reg [ (3-1):0] eid_x;                      
+  
+                        
+                        
+
+
+
+  
+ 
+                                      
+
+                                      
+ 
+ 
+                                
+                                 
+                          
+ 
+ 
+ 
+                      
+ 
+ 
+ 
+
+
+wire exception_x;                               
+reg exception_m;
+reg exception_w;
+wire exception_q_w;
+ 
+
+
+  
+  
+                            
+
+ 
+                            
+
+
+
+  
+
+wire interrupt_exception;                       
+ 
+
+  
+                       
+                       
+
+
+  
+     
+   
+            
+                   
+
+
+  
+                   
+
+
+wire system_call_exception;                     
+
+  
+                         
+
+
+
+   
+    
+
+
+     
+  
+                          
+   
+            
+   
+                          
+   
+
+    	      
+    	      
+    	      
+    	      
+    	      
+    	      
+   
+   
+
+
+   
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+lm32_instruction_unit_minimal #(
+    .eba_reset              (eba_reset),
+    .associativity          (icache_associativity),
+    .sets                   (icache_sets),
+    .bytes_per_line         (icache_bytes_per_line),
+    .base_address           (icache_base_address),
+    .limit                  (icache_limit)
+  ) instruction_unit (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    
+    .stall_a                (stall_a),
+    .stall_f                (stall_f),
+    .stall_d                (stall_d),
+    .stall_x                (stall_x),
+    .stall_m                (stall_m),
+    .valid_f                (valid_f),
+    .valid_d                (valid_d),
+    .kill_f                 (kill_f),
+    .branch_predict_taken_d (branch_predict_taken_d),
+    .branch_predict_address_d (branch_predict_address_d),
+      
+             
+            
+
+
+    .exception_m            (exception_m),
+    .branch_taken_m         (branch_taken_m),
+    .branch_mispredict_taken_m (branch_mispredict_taken_m),
+    .branch_target_m        (branch_target_m),
+  
+                     
+
+
+  
+     
+      
+           
+
+        
+  
+
+    
+    .i_dat_i                (I_DAT_I),
+    .i_ack_i                (I_ACK_I),
+    .i_err_i                (I_ERR_I),
+    .i_rty_i                (I_RTY_I),
+ 
+
+  
+           
+          
+            
+               
+
+
+    
+    
+    .pc_f                   (pc_f),
+    .pc_d                   (pc_d),
+    .pc_x                   (pc_x),
+    .pc_m                   (pc_m),
+    .pc_w                   (pc_w),
+  
+       
+     
+      
+           
+
+
+  
+
+    
+    .i_dat_o                (I_DAT_O),
+    .i_adr_o                (I_ADR_O),
+    .i_cyc_o                (I_CYC_O),
+    .i_sel_o                (I_SEL_O),
+    .i_stb_o                (I_STB_O),
+    .i_we_o                 (I_WE_O),
+    .i_cti_o                (I_CTI_O),
+    .i_lock_o               (I_LOCK_O),
+    .i_bte_o                (I_BTE_O),
+ 
+ 
+
+  
+    
+    
+    
+
+
+		      	      
+  
+             
+       
+
+
+  
+                
+
+
+  
+
+    .instruction_f          (instruction_f),
+ 
+
+
+		      
+    .instruction_d          (instruction_d)
+
+
+		      
+    );
+
+
+lm32_decoder_minimal decoder (
+    
+    .instruction            (instruction_d),
+    
+    .d_result_sel_0         (d_result_sel_0_d),
+    .d_result_sel_1         (d_result_sel_1_d),
+    .x_result_sel_csr       (x_result_sel_csr_d),
+  
+      
+
+
+  
+    
+    .x_result_sel_shift     (x_result_sel_shift_d),
+ 
+
+  
+          
+
+    
+    .x_result_sel_logic     (x_result_sel_logic_d),
+  
+          
+
+
+    .x_result_sel_add       (x_result_sel_add_d),
+    .m_result_sel_compare   (m_result_sel_compare_d),
+  
+           
+
+    
+    .w_result_sel_load      (w_result_sel_load_d),
+  
+           
+
+
+    .x_bypass_enable        (x_bypass_enable_d),
+    .m_bypass_enable        (m_bypass_enable_d),
+    .read_enable_0          (read_enable_0_d),
+    .read_idx_0             (read_idx_0_d),
+    .read_enable_1          (read_enable_1_d),
+    .read_idx_1             (read_idx_1_d),
+    .write_enable           (write_enable_d),
+    .write_idx              (write_idx_d),
+    .immediate              (immediate_d),
+    .branch_offset          (branch_offset_d),
+    .load                   (load_d),
+    .store                  (store_d),
+    .size                   (size_d),
+    .sign_extend            (sign_extend_d),
+    .adder_op               (adder_op_d),
+    .logic_op               (logic_op_d),
+  
+                  
+
+
+  
+                 
+                
+
+
+  
+                   
+
+
+  
+                     
+                    
+
+
+    .branch                 (branch_d),
+    .bi_unconditional       (bi_unconditional),
+    .bi_conditional         (bi_conditional),
+    .branch_reg             (branch_reg_d),
+    .condition              (condition_d),
+  
+               
+
+
+    .scall                  (scall_d),
+    .eret                   (eret_d),
+  
+                       
+
+
+  
+                
+
+
+    .csr_write_enable       (csr_write_enable_d)
+    ); 
+
+
+lm32_load_store_unit_minimal #(
+    .associativity          (dcache_associativity),
+    .sets                   (dcache_sets),
+    .bytes_per_line         (dcache_bytes_per_line),
+    .base_address           (dcache_base_address),
+    .limit                  (dcache_limit)
+  ) load_store_unit (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    
+    .stall_a                (stall_a),
+    .stall_x                (stall_x),
+    .stall_m                (stall_m),
+    .kill_x                 (kill_x),
+    .kill_m                 (kill_m),
+    .exception_m            (exception_m),
+    .store_operand_x        (store_operand_x),
+    .load_store_address_x   (adder_result_x),
+    .load_store_address_m   (operand_m),
+    .load_store_address_w   (operand_w[1:0]),
+    .load_x                 (load_x),
+    .store_x                (store_x),
+    .load_q_x               (load_q_x),
+    .store_q_x              (store_q_x),
+    .load_q_m               (load_q_m),
+    .store_q_m              (store_q_m),
+    .sign_extend_x          (sign_extend_x),
+    .size_x                 (size_x),
+  
+                     
+
+
+
+  
+    
+    
+    
+    
+    
+    
+    
+
+
+		     
+    
+    .d_dat_i                (D_DAT_I),
+    .d_ack_i                (D_ACK_I),
+    .d_err_i                (D_ERR_I),
+    .d_rty_i                (D_RTY_I),
+    
+    
+  
+      
+     
+       
+           
+
+    
+    .load_data_w            (load_data_w),
+    .stall_wb_load          (stall_wb_load),
+    
+    .d_dat_o                (D_DAT_O),
+    .d_adr_o                (D_ADR_O),
+    .d_cyc_o                (D_CYC_O),
+    .d_sel_o                (D_SEL_O),
+    .d_stb_o                (D_STB_O),
+    .d_we_o                 (D_WE_O),
+    .d_cti_o                (D_CTI_O),
+    .d_lock_o               (D_LOCK_O),
+    .d_bte_o                (D_BTE_O)
+    );      
+       
+
+lm32_adder adder (
+    
+    .adder_op_x             (adder_op_x),
+    .adder_op_x_n           (adder_op_x_n),
+    .operand_0_x            (operand_0_x),
+    .operand_1_x            (operand_1_x),
+    
+    .adder_result_x         (adder_result_x),
+    .adder_carry_n_x        (adder_carry_n_x),
+    .adder_overflow_x       (adder_overflow_x)
+    );
+
+
+lm32_logic_op logic_op (
+    
+    .logic_op_x             (logic_op_x),
+    .operand_0_x            (operand_0_x),
+
+    .operand_1_x            (operand_1_x),
+    
+    .logic_result_x         (logic_result_x)
+    );
+              
+  
+
+  
+    
+                      
+                      
+                    
+                
+              
+                
+                
+    
+           
+    
+
+
+
+  
+
+  
+    
+                      
+                      
+                    
+                    
+                  
+                  
+    
+                         
+    
+
+
+
+  
+
+  
+    
+                      
+                      
+                    
+                     
+                   
+                   
+                  
+
+         
+                 
+
+ 
+               
+              
+              
+    
+                
+                
+    
+                   
+                   
+           
+
+            
+    
+
+
+              
+  
+
+
+lm32_interrupt_minimal interrupt_unit (
+    
+    .clk_i                  (clk_i), 
+    .rst_i                  (rst_i),
+    
+    .interrupt              (interrupt),
+    
+    .stall_x                (stall_x),
+  
+         
+            
+
+
+    .exception              (exception_q_w), 
+ 
+
+    .eret_q_x               (eret_q_x),
+  
+                   
+
+
+    .csr                    (csr_x),
+    .csr_write_data         (operand_1_x),
+    .csr_write_enable       (csr_write_enable_q_x),
+    
+    .interrupt_exception    (interrupt_exception),
+    
+    .csr_read_data          (interrupt_csr_read_data_x)
+    );
+ 
+
+
+  
+      
+      
+        
+   
+
+
+
+
+  
+
+  
+    
+                      
+                      
+    
+                   
+                
+                 
+            
+    
+ 
+                        
+             
+           
+                    
+
+ 
+             
+       
+
+ 
+                
+    
+    
+    
+ 
+          
+          
+
+ 
+      
+        
+                   
+           
+          
+            
+               
+
+ 
+                 
+                 
+
+    
+                 
+            
+    
+
+
+
+  
+
+ 
+                
+                
+    
+    
+                       
+                      
+                       
+                     
+                    
+       
+         
+             
+                      
+  
+	       
+      
+        
+                   
+	      
+	       
+      
+        
+                   
+	      
+
+ 
+                   
+                   
+                    
+                
+                        
+ 
+      
+
+
+    
+ 
+                      
+
+                      
+                   
+                   
+    
+
+
+
+
+
+  
+
+   
+           
+            
+          
+            
+
+
+             
+              
+    
+
+   wire [31:0] regfile_data_0, regfile_data_1;
+   reg [31:0]  w_result_d;
+   reg 	       regfile_raw_0, regfile_raw_0_nxt;
+   reg 	       regfile_raw_1, regfile_raw_1_nxt;
+   
+   
+             
+          
+
+   always @(reg_write_enable_q_w or write_idx_w or instruction_f)
+     begin
+	if (reg_write_enable_q_w
+	    && (write_idx_w == instruction_f[25:21]))
+	  regfile_raw_0_nxt = 1'b1;
+	else
+	  regfile_raw_0_nxt = 1'b0;
+	
+	if (reg_write_enable_q_w
+	    && (write_idx_w == instruction_f[20:16]))
+	  regfile_raw_1_nxt = 1'b1;
+	else
+	  regfile_raw_1_nxt = 1'b0;
+     end
+   
+   
+           
+           
+       
+
+   always @(regfile_raw_0 or w_result_d or regfile_data_0)
+     if (regfile_raw_0)
+       reg_data_live_0 = w_result_d;
+     else
+       reg_data_live_0 = regfile_data_0;
+   
+   
+           
+           
+       
+
+   always @(regfile_raw_1 or w_result_d or regfile_data_1)
+     if (regfile_raw_1)
+       reg_data_live_1 = w_result_d;
+     else
+       reg_data_live_1 = regfile_data_1;
+   
+   
+     
+
+   always @(posedge clk_i  )
+     if (rst_i ==  1'b1)
+       begin
+	  regfile_raw_0 <= 1'b0;
+	  regfile_raw_1 <= 1'b0;
+	  w_result_d <= 32'b0;
+       end
+     else
+       begin
+	  regfile_raw_0 <= regfile_raw_0_nxt;
+	  regfile_raw_1 <= regfile_raw_1_nxt;
+	  w_result_d <= w_result;
+       end
+   
+   
+      
+
+   
+   lm32_dp_ram
+     #(
+       
+       .addr_depth(1<<5),
+       .addr_width(5),
+       .data_width(32)
+       )
+   reg_0
+     (
+      
+      .clk_i	(clk_i),
+      .rst_i	(rst_i), 
+      .we_i	(reg_write_enable_q_w),
+      .wdata_i	(w_result),
+      .waddr_i	(write_idx_w),
+      .raddr_i	(instruction_f[25:21]),
+      
+      .rdata_o	(regfile_data_0)
+      );
+
+   lm32_dp_ram
+     #(
+       .addr_depth(1<<5),
+       .addr_width(5),
+       .data_width(32)
+       )
+   reg_1
+     (
+      
+      .clk_i	(clk_i),
+      .rst_i	(rst_i), 
+      .we_i	(reg_write_enable_q_w),
+      .wdata_i	(w_result),
+      .waddr_i	(write_idx_w),
+      .raddr_i	(instruction_f[20:16]),
+      
+      .rdata_o	(regfile_data_1)
+      );
+ 
+
+
+  
+   
+     
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+   
+     
+      
+      
+      
+      
+      
+      
+      
+        
+      
+       
+      
+      
+      
+   
+   
+     
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+   
+     
+      
+      
+      
+      
+      
+      
+      
+        
+      
+       
+      
+      
+      
+
+
+
+
+
+
+
+
+  
+
+
+assign reg_data_0 = use_buf ? reg_data_buf_0 : reg_data_live_0;
+assign reg_data_1 = use_buf ? reg_data_buf_1 : reg_data_live_1;
+ 
+
+  
+
+ 
+
+   
+   
+
+
+
+
+assign raw_x_0 = (write_idx_x == read_idx_0_d) && (write_enable_q_x ==  1'b1);
+assign raw_m_0 = (write_idx_m == read_idx_0_d) && (write_enable_q_m ==  1'b1);
+assign raw_w_0 = (write_idx_w == read_idx_0_d) && (write_enable_q_w ==  1'b1);
+assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x ==  1'b1);
+assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m ==  1'b1);
+assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w ==  1'b1);
+
+
+always @(*)
+begin
+    if (   (   (x_bypass_enable_x ==  1'b0)
+            && (   ((read_enable_0_d ==  1'b1) && (raw_x_0 ==  1'b1))
+                || ((read_enable_1_d ==  1'b1) && (raw_x_1 ==  1'b1))
+               )
+           )
+        || (   (m_bypass_enable_m ==  1'b0)
+            && (   ((read_enable_0_d ==  1'b1) && (raw_m_0 ==  1'b1))
+                || ((read_enable_1_d ==  1'b1) && (raw_m_1 ==  1'b1))
+               )
+           )
+       )
+        interlock =  1'b1;
+    else
+        interlock =  1'b0;
+end
+
+
+always @(*)
+begin
+    if (raw_x_0 ==  1'b1)        
+        bypass_data_0 = x_result;
+    else if (raw_m_0 ==  1'b1)
+        bypass_data_0 = m_result;
+    else if (raw_w_0 ==  1'b1)
+        bypass_data_0 = w_result;
+    else
+        bypass_data_0 = reg_data_0;
+end
+
+
+always @(*)
+begin
+    if (raw_x_1 ==  1'b1)
+        bypass_data_1 = x_result;
+    else if (raw_m_1 ==  1'b1)
+        bypass_data_1 = m_result;
+    else if (raw_w_1 ==  1'b1)
+        bypass_data_1 = w_result;
+    else
+        bypass_data_1 = reg_data_1;
+end
+
+   
+          
+       
+       
+     
+
+   assign branch_predict_d = bi_unconditional | bi_conditional;
+   assign branch_predict_taken_d = bi_unconditional ? 1'b1 : (bi_conditional ? instruction_d[15] : 1'b0);
+   
+   
+   assign branch_target_d = pc_d + branch_offset_d;
+
+   
+   
+   
+   assign branch_predict_address_d = branch_predict_taken_d ? branch_target_d : pc_f;
+
+
+always @(*)
+begin
+    d_result_0 = d_result_sel_0_d[0] ? {pc_f, 2'b00} : bypass_data_0; 
+    case (d_result_sel_1_d)
+     2'b00:      d_result_1 = { 32{1'b0}};
+     2'b01:     d_result_1 = bypass_data_1;
+     2'b10: d_result_1 = immediate_d;
+    default:                        d_result_1 = { 32{1'bx}};
+    endcase
+end
+
+      
+
+   
+   
+
+
+
+  
+
+    
+    
+         
+
+
+
+  
+
+
+assign shifter_result_x = {operand_0_x[ 32-1] & sign_extend_x, operand_0_x[ 32-1:1]};
+ 
+
+
+
+assign cmp_zero = operand_0_x == operand_1_x;
+assign cmp_negative = adder_result_x[ 32-1];
+assign cmp_overflow = adder_overflow_x;
+assign cmp_carry_n = adder_carry_n_x;
+always @(*)
+begin
+    case (condition_x)
+     3'b000:   condition_met_x =  1'b1;
+     3'b110:   condition_met_x =  1'b1;
+     3'b001:    condition_met_x = cmp_zero;
+     3'b111:   condition_met_x = !cmp_zero;
+     3'b010:    condition_met_x = !cmp_zero && (cmp_negative == cmp_overflow);
+     3'b101:   condition_met_x = cmp_carry_n && !cmp_zero;
+     3'b011:   condition_met_x = cmp_negative == cmp_overflow;
+     3'b100:  condition_met_x = cmp_carry_n;
+    default:              condition_met_x = 1'bx;
+    endcase 
+end
+
+
+always @(*)
+begin
+    x_result =   x_result_sel_add_x ? adder_result_x 
+               : x_result_sel_csr_x ? csr_read_data_x
+  
+                  
+
+
+  
+                  
+
+
+  
+
+               : x_result_sel_shift_x ? shifter_result_x
+ 
+
+  
+                  
+
+
+               : logic_result_x;
+end
+
+
+always @(*)
+begin
+    m_result =   m_result_sel_compare_m ? {{ 32-1{1'b0}}, condition_met_m}
+  
+                  
+
+
+               : operand_m; 
+end
+
+
+always @(*)
+begin
+    w_result =    w_result_sel_load_w ? load_data_w
+  
+                   
+
+
+                : operand_w;
+end
+
+      
+
+          
+                                
+                                     
+                                 
+                                 
+                              
+
+
+
+
+assign branch_taken_m =      (stall_m ==  1'b0) 
+                          && (   (   (branch_m ==  1'b1) 
+                                  && (valid_m ==  1'b1)
+                                  && (   (   (condition_met_m ==  1'b1)
+					  && (branch_predict_taken_m ==  1'b0)
+					 )
+				      || (   (condition_met_m ==  1'b0)
+					  && (branch_predict_m ==  1'b1)
+					  && (branch_predict_taken_m ==  1'b1)
+					 )
+				     )
+                                 ) 
+                              || (exception_m ==  1'b1)
+                             );
+
+
+assign branch_mispredict_taken_m =    (condition_met_m ==  1'b0)
+                                   && (branch_predict_m ==  1'b1)
+	   			   && (branch_predict_taken_m ==  1'b1);
+   
+
+assign branch_flushX_m =    (stall_m ==  1'b0)
+                         && (   (   (branch_m ==  1'b1) 
+                                 && (valid_m ==  1'b1)
+			         && (   (condition_met_m ==  1'b1)
+				     || (   (condition_met_m ==  1'b0)
+					 && (branch_predict_m ==  1'b1)
+					 && (branch_predict_taken_m ==  1'b1)
+					)
+				    )
+			        )
+			     || (exception_m ==  1'b1)
+			    );
+
+
+assign kill_f =    (   (valid_d ==  1'b1)
+                    && (branch_predict_taken_d ==  1'b1)
+		   )
+                || (branch_taken_m ==  1'b1) 
+      
+                   
+
+
+  
+                    
+
+
+                  
+                   
+
+
+                ;
+assign kill_d =    (branch_taken_m ==  1'b1) 
+      
+                   
+
+
+  
+                        
+
+                
+                  
+                   
+
+
+                ;
+assign kill_x =    (branch_flushX_m ==  1'b1) 
+                  
+                   
+
+
+                ;
+assign kill_m =     1'b0
+                  
+                   
+
+
+                ;                
+assign kill_w =     1'b0
+                  
+                   
+
+                
+                ;
+
+
+
+  
+              
+				         
+				     
+				     
+				 
+ 
+                                 
+
+                              
+
+
+
+  
+     
+
+
+
+  
+        
+                                             
+                                         
+     
+
+
+
+  
+     
+
+
+
+assign system_call_exception = (   (scall_x ==  1'b1)
+  
+                                   
+
+
+			       );
+
+  
+      
+                            
+                         
+
+     
+ 
+                               
+
+ 
+                               
+                               
+
+ 
+                               
+
+ 
+                                  
+ 
+                                   
+                            
+ 
+ 				   
+				   
+
+                               
+
+                            
+
+         
+
+
+assign exception_x =           (system_call_exception ==  1'b1)
+  
+                               
+                               
+
+
+  
+                               
+
+
+  
+
+                            || (   (interrupt_exception ==  1'b1)
+  
+                                   
+
+                            
+  
+ 				   
+				   
+
+
+                               )
+ 
+
+                            ;
+ 
+
+
+  
+ 
+
+ 
+  
+      
+   
+      
+
+
+
+
+always @(*)
+begin
+  
+ 
+       
+          
+    
+     
+ 
+            
+          
+    
+
+            
+          
+    
+
+
+  
+            
+          
+    
+            
+          
+    
+
+
+  
+            
+          
+     
+
+
+  
+            
+          
+    
+
+
+  
+
+         if (   (interrupt_exception ==  1'b1)
+  
+                
+
+                            
+            )
+        eid_x =  3'h6;
+    else
+ 
+
+        eid_x =  3'h7;
+end
+
+
+
+assign stall_a = (stall_f ==  1'b1);
+                
+assign stall_f = (stall_d ==  1'b1);
+                
+assign stall_d =   (stall_x ==  1'b1) 
+                || (   (interlock ==  1'b1)
+                    && (kill_d ==  1'b0)
+                   ) 
+		|| (   (   (eret_d ==  1'b1)
+			|| (scall_d ==  1'b1)
+  
+			   
+
+
+		       )
+		    && (   (load_q_x ==  1'b1)
+			|| (load_q_m ==  1'b1)
+			|| (store_q_x ==  1'b1)
+			|| (store_q_m ==  1'b1)
+			|| (D_CYC_O ==  1'b1)
+		       )
+                    && (kill_d ==  1'b0)
+		   )
+  
+		         
+			   
+		       
+		          
+			   
+			   
+			   
+			   
+		       
+                       
+		   
+
+                   
+                || (   (csr_write_enable_d ==  1'b1)
+                    && (load_q_x ==  1'b1)
+                   )                      
+  
+                 
+                 
+                       
+		           
+			 
+			
+		    
+
+	
+                ;
+                
+assign stall_x =    (stall_m ==  1'b1)
+  
+                       
+                        
+                     
+
+
+
+	    
+                 ;
+
+assign stall_m =    (stall_wb_load ==  1'b1)
+  
+                    
+
+
+                 || (   (D_CYC_O ==  1'b1)
+                     && (   (store_m ==  1'b1)
+		         
+          
+          
+
+		  
+	 
+	
+
+          
+           
+          
+       
+
+  
+
+		         || ((store_x ==  1'b1) && (interrupt_exception ==  1'b1))
+ 
+
+                         || (load_m ==  1'b1)
+                         || (load_x ==  1'b1)
+                        ) 
+                    ) 
+ 
+                 
+  
+                         
+
+                                    
+  
+                         
+                             
+
+
+  
+
+                 || (I_CYC_O ==  1'b1)            
+ 
+
+ 
+                               
+  
+                                  
+                        
+                    
+
+
+  
+                  
+   
+
+                 ;      
+
+
+
+
+  
+         
+
+
+  
+         
+         
+
+
+  
+         
+
+
+  
+         
+         
+
+
+assign q_x = (valid_x ==  1'b1) && (kill_x ==  1'b0);
+assign csr_write_enable_q_x = (csr_write_enable_x ==  1'b1) && (q_x ==  1'b1);
+assign eret_q_x = (eret_x ==  1'b1) && (q_x ==  1'b1);
+  
+         
+
+
+assign load_q_x = (load_x ==  1'b1) 
+               && (q_x ==  1'b1)
+  
+                  
+
+
+                  ;
+assign store_q_x = (store_x ==  1'b1) 
+               && (q_x ==  1'b1)
+  
+                  
+
+
+                  ;
+  
+         
+
+                              
+assign q_m = (valid_m ==  1'b1) && (kill_m ==  1'b0) && (exception_m ==  1'b0);
+assign load_q_m = (load_m ==  1'b1) && (q_m ==  1'b1);
+assign store_q_m = (store_m ==  1'b1) && (q_m ==  1'b1);
+  
+         
+                 
+
+
+assign exception_q_w = ((exception_w ==  1'b1) && (valid_w ==  1'b1));        
+ 
+
+
+assign write_enable_q_x = (write_enable_x ==  1'b1) && (valid_x ==  1'b1) && (branch_flushX_m ==  1'b0);
+assign write_enable_q_m = (write_enable_m ==  1'b1) && (valid_m ==  1'b1);
+assign write_enable_q_w = (write_enable_w ==  1'b1) && (valid_w ==  1'b1);
+
+assign reg_write_enable_q_w = (write_enable_w ==  1'b1) && (kill_w ==  1'b0) && (valid_w ==  1'b1);
+
+
+assign cfg = {
+               6'h02,
+              watchpoints[3:0],
+              breakpoints[3:0],
+              interrupts[5:0],
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+   
+              
+
+
+               1'b0
+ 
+
+              };
+
+assign cfg2 = {
+		     30'b0,
+  
+		     
+
+
+		      1'b0,
+ 
+
+  
+		     
+
+
+		      1'b0
+ 
+
+		     };
+   
+
+  
+         
+                    
+                    
+                    
+                    
+
+ 
+             
+                     
+		    
+
+		 
+
+ 
+  
+         
+                      
+
+ 
+               
+                       
+		      
+
+		   
+
+ 
+
+
+assign csr_d = read_idx_0_d[ (4 -1):0];
+
+
+always @(*)
+begin
+    case (csr_x)
+  
+
+     4 'h0,
+     4 'h1,
+     4 'h2:   csr_read_data_x = interrupt_csr_read_data_x;  
+ 
+
+  
+         
+
+
+     4 'h6:  csr_read_data_x = cfg;
+     4 'h7:  csr_read_data_x = {eba, 8'h00};
+  
+        
+
+
+  
+          
+        
+
+
+     4 'ha: csr_read_data_x = cfg2;
+     4 'hb:  csr_read_data_x = sdb_address;
+  
+        
+
+
+      
+      
+    default:        csr_read_data_x = { 32{1'bx}};
+    endcase
+end
+
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        eba <= eba_reset[ (32-2)+2-1:8];
+    else
+    begin
+        if ((csr_write_enable_q_x ==  1'b1) && (csr_x ==  4 'h7) && (stall_x ==  1'b0))
+            eba <= operand_1_x[ (32-2)+2-1:8];
+  
+  
+              
+           
+ 
+  
+              
+           
+ 	 
+
+
+    end
+end
+
+  
+
+   
+
+       
+          
+    
+    
+                   
+              
+  
+   
+              
+           
+  
+   
+              
+           
+         
+ 
+    
+
+
+
+
+
+  
+   
+
+       
+          
+    
+            
+
+
+
+
+  
+
+   
+
+       
+          
+    
+    
+        
+                
+             
+	     
+	
+        
+               
+              
+    
+
+
+
+ 
+
+
+  
+ 
+ 
+
+           
+           
+       
+          
+            
+                 
+             
+          
+     
+            
+ 
+
+ 
+
+        
+          
+         
+          
+     
+          
+ 
+
+
+
+  
+ 
+
+        
+          
+         
+          
+     
+          
+ 
+
+
+ 
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        valid_f <=  1'b0;
+        valid_d <=  1'b0;
+        valid_x <=  1'b0;
+        valid_m <=  1'b0;
+        valid_w <=  1'b0;
+    end
+    else
+    begin    
+        if ((kill_f ==  1'b1) || (stall_a ==  1'b0))
+  
+                  
+
+
+            valid_f <=  1'b1;
+ 
+            
+        else if (stall_f ==  1'b0)
+            valid_f <=  1'b0;            
+
+        if (kill_d ==  1'b1)
+            valid_d <=  1'b0;
+        else if (stall_f ==  1'b0)
+            valid_d <= valid_f & !kill_f;
+        else if (stall_d ==  1'b0)
+            valid_d <=  1'b0;
+       
+        if (stall_d ==  1'b0)
+            valid_x <= valid_d & !kill_d;
+        else if (kill_x ==  1'b1)
+            valid_x <=  1'b0;
+        else if (stall_x ==  1'b0)
+            valid_x <=  1'b0;
+
+        if (kill_m ==  1'b1)
+            valid_m <=  1'b0;
+        else if (stall_x ==  1'b0)
+            valid_m <= valid_x & !kill_x;
+        else if (stall_m ==  1'b0)
+            valid_m <=  1'b0;
+
+        if (stall_m ==  1'b0)
+            valid_w <= valid_m & !kill_m;
+        else 
+            valid_w <=  1'b0;        
+    end
+end
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+  
+                 
+
+        
+        operand_0_x <= { 32{1'b0}};
+        operand_1_x <= { 32{1'b0}};
+        store_operand_x <= { 32{1'b0}};
+        branch_target_x <= { (32-2){1'b0}};        
+        x_result_sel_csr_x <=  1'b0;
+  
+          
+
+
+  
+    
+        x_result_sel_shift_x <=  1'b0;
+ 
+
+  
+          
+
+    
+  
+          
+
+
+        x_result_sel_add_x <=  1'b0;
+        m_result_sel_compare_x <=  1'b0;
+  
+          
+
+    
+        w_result_sel_load_x <=  1'b0;
+  
+          
+
+
+        x_bypass_enable_x <=  1'b0;
+        m_bypass_enable_x <=  1'b0;
+        write_enable_x <=  1'b0;
+        write_idx_x <= { 5{1'b0}};
+        csr_x <= { 4 {1'b0}};
+        load_x <=  1'b0;
+        store_x <=  1'b0;
+        size_x <= { 2{1'b0}};
+        sign_extend_x <=  1'b0;
+        adder_op_x <=  1'b0;
+        adder_op_x_n <=  1'b0;
+        logic_op_x <= 4'h0;
+  
+          
+
+
+  
+          
+
+
+
+        branch_x <=  1'b0;
+        branch_predict_x <=  1'b0;
+        branch_predict_taken_x <=  1'b0;
+        condition_x <=  3'b000;
+  
+          
+
+
+        scall_x <=  1'b0;
+        eret_x <=  1'b0;
+  
+          
+
+
+  
+          
+          
+
+
+        csr_write_enable_x <=  1'b0;
+        operand_m <= { 32{1'b0}};
+        branch_target_m <= { (32-2){1'b0}};
+        m_result_sel_compare_m <=  1'b0;
+  
+          
+
+    
+        w_result_sel_load_m <=  1'b0;
+  
+          
+
+
+        m_bypass_enable_m <=  1'b0;
+        branch_m <=  1'b0;
+        branch_predict_m <=  1'b0;
+	branch_predict_taken_m <=  1'b0;
+        exception_m <=  1'b0;
+        load_m <=  1'b0;
+        store_m <=  1'b0;
+        write_enable_m <=  1'b0;            
+        write_idx_m <= { 5{1'b0}};
+        condition_met_m <=  1'b0;
+  
+          
+
+
+  
+          
+                  
+
+
+        operand_w <= { 32{1'b0}};        
+        w_result_sel_load_w <=  1'b0;
+  
+          
+
+
+        write_idx_w <= { 5{1'b0}};        
+        write_enable_w <=  1'b0;
+  
+          
+                  
+
+
+        exception_w <=  1'b0;
+ 
+
+  
+          
+
+
+    end
+    else
+    begin
+        
+       
+        if (stall_x ==  1'b0)
+        begin
+  
+                     
+
+        
+            operand_0_x <= d_result_0;
+            operand_1_x <= d_result_1;
+            store_operand_x <= bypass_data_1;
+            branch_target_x <= branch_reg_d ==  1'b1 ? bypass_data_0[ ((32-2)+2-1):2] : branch_target_d;            
+            x_result_sel_csr_x <= x_result_sel_csr_d;
+  
+              
+
+
+  
+    
+            x_result_sel_shift_x <= x_result_sel_shift_d;
+ 
+
+  
+              
+
+    
+  
+              
+
+
+            x_result_sel_add_x <= x_result_sel_add_d;
+            m_result_sel_compare_x <= m_result_sel_compare_d;
+  
+              
+
+    
+            w_result_sel_load_x <= w_result_sel_load_d;
+  
+              
+
+
+            x_bypass_enable_x <= x_bypass_enable_d;
+            m_bypass_enable_x <= m_bypass_enable_d;
+            load_x <= load_d;
+            store_x <= store_d;
+            branch_x <= branch_d;
+	    branch_predict_x <= branch_predict_d;
+	    branch_predict_taken_x <= branch_predict_taken_d;
+	    write_idx_x <= write_idx_d;
+            csr_x <= csr_d;
+            size_x <= size_d;
+            sign_extend_x <= sign_extend_d;
+            adder_op_x <= adder_op_d;
+            adder_op_x_n <= ~adder_op_d;
+            logic_op_x <= logic_op_d;
+  
+              
+
+
+  
+              
+
+
+            condition_x <= condition_d;
+            csr_write_enable_x <= csr_write_enable_d;
+  
+              
+
+
+            scall_x <= scall_d;
+  
+              
+
+
+            eret_x <= eret_d;
+  
+               
+
+
+            write_enable_x <= write_enable_d;
+        end
+        
+        
+
+        if (stall_m ==  1'b0)
+        begin
+            operand_m <= x_result;
+            m_result_sel_compare_m <= m_result_sel_compare_x;
+  
+              
+
+    
+            if (exception_x ==  1'b1)
+            begin
+                w_result_sel_load_m <=  1'b0;
+  
+                  
+
+
+            end
+            else
+            begin
+                w_result_sel_load_m <= w_result_sel_load_x;
+  
+                  
+
+
+            end
+            m_bypass_enable_m <= m_bypass_enable_x;
+            load_m <= load_x;
+            store_m <= store_x;
+      
+                
+
+
+            branch_m <= branch_x;
+	    branch_predict_m <= branch_predict_x;
+	    branch_predict_taken_m <= branch_predict_taken_x;
+ 
+
+  
+	   
+	   
+	   
+	   
+	   
+                
+                  
+                
+                  
+             
+                  
+
+
+            if (exception_x ==  1'b1)
+                write_idx_m <=  5'd30;
+            else 
+                write_idx_m <= write_idx_x;
+ 
+
+            condition_met_m <= condition_met_x;
+  
+	      
+	        
+		     
+		        
+	           
+	     
+	           
+	   
+	       
+
+
+            branch_target_m <= exception_x ==  1'b1 ? {eba, eid_x, {3{1'b0}}} : branch_target_x;
+ 
+
+  
+              
+              
+
+
+  
+              
+
+
+  
+ 
+               
+
+
+
+            write_enable_m <= exception_x ==  1'b1 ?  1'b1 : write_enable_x;            
+  
+              
+                      
+
+
+        end
+        
+        
+        if (stall_m ==  1'b0)
+        begin
+            if ((exception_x ==  1'b1) && (q_x ==  1'b1) && (stall_x ==  1'b0))
+                exception_m <=  1'b1;
+            else 
+                exception_m <=  1'b0;
+  
+	           
+ 
+					    
+
+					 
+
+
+	end
+                
+        
+  
+                      
+
+
+        operand_w <= exception_m ==  1'b1 ? {pc_m, 2'b00} : m_result;
+ 
+
+        w_result_sel_load_w <= w_result_sel_load_m;
+  
+          
+
+
+        write_idx_w <= write_idx_m;
+  
+          
+          
+ 
+           
+
+
+
+        write_enable_w <= write_enable_m;
+  
+          
+          
+
+
+        exception_w <= exception_m;
+ 
+
+  
+              
+                   
+                   
+               
+	   
+            
+
+
+    end
+end
+
+  
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        use_buf <=  1'b0;
+        reg_data_buf_0 <= { 32{1'b0}};
+        reg_data_buf_1 <= { 32{1'b0}};
+    end
+    else
+    begin
+        if (stall_d ==  1'b0)
+            use_buf <=  1'b0;
+        else if (use_buf ==  1'b0)
+        begin        
+            reg_data_buf_0 <= reg_data_live_0;
+            reg_data_buf_1 <= reg_data_live_1;
+            use_buf <=  1'b1;
+        end        
+        if (reg_write_enable_q_w ==  1'b1)
+        begin
+            if (write_idx_w == read_idx_0_d)
+                reg_data_buf_0 <= w_result;
+            if (write_idx_w == read_idx_1_d)
+                reg_data_buf_1 <= w_result;
+        end
+    end
+end
+ 
+
+
+  
+
+ 
+
+   
+
+        
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+        
+     
+           
+            
+        
+
+
+
+
+  
+
+   
+
+       
+    
+          
+          
+          
+          
+          
+ 
+          
+
+          
+    
+    
+    
+          
+        
+ 
+               
+
+           
+
+                
+              
+              
+              
+              
+        
+        
+              
+        
+             
+        
+            
+                 
+            
+                
+                  
+                  
+            
+            
+              
+            
+              
+ 
+              
+
+        
+        
+        
+              
+ 
+              
+
+        
+    
+
+
+
+      
+
+
+
+
+
+        
+endmodule 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_load_store_unit_minimal 
+(
+    
+    clk_i,
+    rst_i,
+ 
+    stall_a,
+    stall_x,
+    stall_m,
+    kill_x,
+    kill_m,
+    exception_m,
+    store_operand_x,
+    load_store_address_x,
+    load_store_address_m,
+    load_store_address_w,
+    load_x,
+    store_x,
+    load_q_x,
+    store_q_x,
+    load_q_m,
+    store_q_m,
+    sign_extend_x,
+    size_x,
+  
+    
+
+
+    
+    d_dat_i,
+    d_ack_i,
+    d_err_i,
+    d_rty_i,
+    
+    
+  
+    
+    
+    
+    
+
+    
+  
+    
+    
+    
+    
+    
+    
+    
+
+			     
+    load_data_w,
+    stall_wb_load,
+    
+    d_dat_o,
+    d_adr_o,
+    d_cyc_o,
+    d_sel_o,
+    d_stb_o,
+    d_we_o,
+    d_cti_o,
+    d_lock_o,
+    d_bte_o
+    );
+
+
+
+
+
+parameter associativity = 1;                            
+parameter sets = 512;                                   
+parameter bytes_per_line = 16;                          
+parameter base_address = 0;                             
+parameter limit = 0;                                    
+
+
+localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
+localparam addr_offset_lsb = 2;
+localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
+
+
+
+
+
+   input clk_i;                                            
+   
+input rst_i;                                            
+
+input stall_a;                                          
+input stall_x;                                          
+input stall_m;                                          
+input kill_x;                                           
+input kill_m;                                           
+input exception_m;                                      
+
+input [ (32-1):0] store_operand_x;                 
+input [ (32-1):0] load_store_address_x;            
+input [ (32-1):0] load_store_address_m;            
+input [1:0] load_store_address_w;                       
+input load_x;                                           
+input store_x;                                          
+input load_q_x;                                         
+input store_q_x;                                        
+input load_q_m;                                         
+input store_q_m;                                        
+input sign_extend_x;                                    
+input [ 1:0] size_x;                          
+
+  
+                                            
+
+
+
+     
+     
+     
+      
+      
+            
+    	 
+   
+
+
+
+   reg 		 [31:0] iram_dat_d0;
+   reg 		 iram_en_d0;
+   wire 	 iram_en;
+   wire [31:0] 	 iram_data;
+   
+   
+   
+input [ (32-1):0] d_dat_i;                         
+input d_ack_i;                                          
+input d_err_i;                                          
+input d_rty_i;                                          
+
+
+
+
+
+  
+                            
+   
+                           
+   
+                             
+   
+ 
+   
+
+
+
+   
+output [ (32-1):0] load_data_w;                    
+reg    [ (32-1):0] load_data_w;
+output stall_wb_load;                                   
+reg    stall_wb_load;
+
+output [ (32-1):0] d_dat_o;                        
+reg    [ (32-1):0] d_dat_o;
+output [ (32-1):0] d_adr_o;                        
+reg    [ (32-1):0] d_adr_o;
+output d_cyc_o;                                         
+reg    d_cyc_o;
+output [ (4-1):0] d_sel_o;                 
+reg    [ (4-1):0] d_sel_o;
+output d_stb_o;                                         
+reg    d_stb_o; 
+output d_we_o;                                          
+reg    d_we_o;
+output [ (3-1):0] d_cti_o;                       
+reg    [ (3-1):0] d_cti_o;
+output d_lock_o;                                        
+reg    d_lock_o;
+output [ (2-1):0] d_bte_o;                       
+wire   [ (2-1):0] d_bte_o;
+
+
+
+
+
+
+reg [ 1:0] size_m;
+reg [ 1:0] size_w;
+reg sign_extend_m;
+reg sign_extend_w;
+reg [ (32-1):0] store_data_x;       
+reg [ (32-1):0] store_data_m;       
+reg [ (4-1):0] byte_enable_x;
+reg [ (4-1):0] byte_enable_m;
+wire [ (32-1):0] data_m;
+reg [ (32-1):0] data_w;
+
+   
+
+  
+                                    
+ 
+                      
+              
+                                 
+                  
+                   
+                                          
+                      
+
+
+  
+                                      
+ 
+                                      
+                    
+                      
+                        
+                  
+
+
+wire wb_select_x;                                       
+  
+                                      
+
+  
+    
+    
+   
+
+
+
+reg wb_select_m;
+reg [ (32-1):0] wb_data_m;                         
+reg wb_load_complete;                                   
+   
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+  
+
+ 
+              
+                       
+             
+               
+                      
+       
+    
+                      
+                            
+                    
+                    
+                    
+                  
+                  
+                     
+                    
+                 
+            
+               
+                
+                     
+    
+              
+            
+             
+             
+                  
+                  
+    
+
+
+
+
+
+
+
+
+  
+            
+                             
+
+
+
+  
+            
+                             
+
+      
+        
+
+    
+       
+
+   
+
+    
+     
+       
+     
+         
+     
+
+          
+    
+   
+   
+
+
+   
+  
+            
+                               
+ 
+                               
+
+ 
+                               
+
+                     
+
+
+	  
+   assign wb_select_x =     1'b1
+  
+                          
+
+
+  
+                         
+
+
+  
+                         
+
+
+                     ;
+
+
+always @(*)
+begin
+    case (size_x)
+     2'b00:  store_data_x = {4{store_operand_x[7:0]}};
+     2'b11: store_data_x = {2{store_operand_x[15:0]}};
+     2'b10:  store_data_x = store_operand_x;    
+    default:          store_data_x = { 32{1'bx}};
+    endcase
+end
+
+
+always @(*)
+begin
+    casez ({size_x, load_store_address_x[1:0]})
+    { 2'b00, 2'b11}:  byte_enable_x = 4'b0001;
+    { 2'b00, 2'b10}:  byte_enable_x = 4'b0010;
+    { 2'b00, 2'b01}:  byte_enable_x = 4'b0100;
+    { 2'b00, 2'b00}:  byte_enable_x = 4'b1000;
+    { 2'b11, 2'b1?}: byte_enable_x = 4'b0011;
+    { 2'b11, 2'b0?}: byte_enable_x = 4'b1100;
+    { 2'b10, 2'b??}:  byte_enable_x = 4'b1111;
+    default:                   byte_enable_x = 4'bxxxx;
+    endcase
+end
+
+  
+      
+            
+
+           
+	                            
+   
+   
+               
+        
+
+
+   
+  
+  
+   
+   
+         
+                    
+                       
+                      
+                        
+                     
+                        
+  
+   
+         
+                    
+                       
+                      
+                      
+  
+ 
+   
+   
+         
+                    
+                       
+                      
+                      
+  
+   
+         
+                     
+                    
+  
+ 
+
+
+   
+   
+   
+         
+                     
+                      
+                      
+                      
+  
+   
+         
+                     
+                    
+  
+ 
+
+    
+   
+         
+                     
+                    
+
+  
+
+   
+   assign data_m = wb_data_m;
+   
+
+  
+
+ 
+
+
+
+always @(*)
+begin
+    casez ({size_w, load_store_address_w[1:0]})
+    { 2'b00, 2'b11}:  load_data_w = {{24{sign_extend_w & data_w[7]}}, data_w[7:0]};
+    { 2'b00, 2'b10}:  load_data_w = {{24{sign_extend_w & data_w[15]}}, data_w[15:8]};
+    { 2'b00, 2'b01}:  load_data_w = {{24{sign_extend_w & data_w[23]}}, data_w[23:16]};
+    { 2'b00, 2'b00}:  load_data_w = {{24{sign_extend_w & data_w[31]}}, data_w[31:24]};
+    { 2'b11, 2'b1?}: load_data_w = {{16{sign_extend_w & data_w[15]}}, data_w[15:0]};
+    { 2'b11, 2'b0?}: load_data_w = {{16{sign_extend_w & data_w[31]}}, data_w[31:16]};
+    { 2'b10, 2'b??}:  load_data_w = data_w;
+    default:                   load_data_w = { 32{1'bx}};
+    endcase
+end
+
+
+assign d_bte_o =  2'b00;
+
+                  
+
+ 
+     
+    
+    
+   
+   
+   
+    
+    
+    
+    
+   
+   
+     
+     
+    
+    
+    
+   
+         
+     
+     
+    
+    
+
+
+
+
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        d_cyc_o <=  1'b0;
+        d_stb_o <=  1'b0;
+        d_dat_o <= { 32{1'b0}};
+        d_adr_o <= { 32{1'b0}};
+        d_sel_o <= { 4{ 1'b0}};
+        d_we_o <=  1'b0;
+        d_cti_o <=  3'b111;
+        d_lock_o <=  1'b0;
+        wb_data_m <= { 32{1'b0}};
+        wb_load_complete <=  1'b0;
+        stall_wb_load <=  1'b0;
+                  
+          
+
+                
+    end
+    else 
+    begin
+   
+        
+          
+
+                
+        
+        if (d_cyc_o ==  1'b1)
+        begin
+            
+            if ((d_ack_i ==  1'b1) || (d_err_i ==  1'b1))
+            begin
+                  
+                     
+                
+                    
+                        
+                
+                
+
+                
+                begin
+                    
+                    d_cyc_o <=  1'b0;
+                    d_stb_o <=  1'b0;
+                    d_lock_o <=  1'b0;
+                end
+      
+                  
+                
+                  
+
+
+                
+                wb_data_m <= d_dat_i;
+                
+                wb_load_complete <= !d_we_o;
+            end
+            
+        end
+        else 
+        begin
+                  
+               
+            
+                
+                  
+                  
+                  
+                                  
+                  
+                  
+                
+            
+             
+
+            
+                 if (   (store_q_m ==  1'b1)
+                     && (stall_m ==  1'b0)
+  
+                        
+
+
+  
+		        
+
+			
+                    )
+            begin
+                
+                d_dat_o <= store_data_m;
+                d_adr_o <= load_store_address_m;
+                d_cyc_o <=  1'b1;
+                d_sel_o <= byte_enable_m;
+                d_stb_o <=  1'b1;
+                d_we_o <=  1'b1;
+                d_cti_o <=  3'b111;
+            end        
+            else if (   (load_q_m ==  1'b1) 
+                     && (wb_select_m ==  1'b1) 
+                     && (wb_load_complete ==  1'b0)
+                     
+                    )
+            begin
+                
+                stall_wb_load <=  1'b0;
+                d_adr_o <= load_store_address_m;
+                d_cyc_o <=  1'b1;
+                d_sel_o <= byte_enable_m;
+                d_stb_o <=  1'b1;
+                d_we_o <=  1'b0;
+                d_cti_o <=  3'b111;
+            end
+        end
+        
+        if (stall_m ==  1'b0)
+            wb_load_complete <=  1'b0;
+        
+        if ((load_q_x ==  1'b1) && (wb_select_x ==  1'b1) && (stall_x ==  1'b0))
+            stall_wb_load <=  1'b1;
+        
+        if ((kill_m ==  1'b1) || (exception_m ==  1'b1))
+            stall_wb_load <=  1'b0;
+    end
+end
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        sign_extend_m <=  1'b0;
+        size_m <= 2'b00;
+        byte_enable_m <=  1'b0;
+        store_data_m <= { 32{1'b0}};
+  
+          
+
+
+  
+          
+
+
+  
+          
+			    
+
+
+        wb_select_m <=  1'b0;        
+    end
+    else
+    begin
+        if (stall_m ==  1'b0)
+        begin
+            sign_extend_m <= sign_extend_x;
+            size_m <= size_x;
+            byte_enable_m <= byte_enable_x;    
+            store_data_m <= store_data_x;
+  
+              
+
+
+  
+              
+
+
+  
+              
+			    
+
+
+            wb_select_m <= wb_select_x;
+        end
+    end
+end
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        size_w <= 2'b00;
+        data_w <= { 32{1'b0}};
+        sign_extend_w <=  1'b0;
+    end
+    else
+    begin
+        size_w <= size_m;
+
+  
+         
+
+
+        data_w <= data_m;
+
+        sign_extend_w <= sign_extend_m;
+    end
+end
+
+
+
+
+
+
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_decoder_minimal (
+    
+    instruction,
+    
+    d_result_sel_0,
+    d_result_sel_1,        
+    x_result_sel_csr,
+  
+    
+
+    
+  
+    
+    x_result_sel_shift,
+ 
+
+  
+    
+
+    
+    x_result_sel_logic,
+  
+    
+
+
+    x_result_sel_add,
+    m_result_sel_compare,
+  
+      
+
+    
+    w_result_sel_load,
+  
+    
+
+
+    x_bypass_enable,
+    m_bypass_enable,
+    read_enable_0,
+    read_idx_0,
+    read_enable_1,
+    read_idx_1,
+    write_enable,
+    write_idx,
+    immediate,
+    branch_offset,
+    load,
+    store,
+    size,
+    sign_extend,
+    adder_op,
+    logic_op,
+  
+    
+
+
+  
+    
+    
+
+
+  
+    
+
+
+  
+    
+    
+
+
+    branch,
+    branch_reg,
+    condition,
+    bi_conditional,
+    bi_unconditional,
+  
+    
+
+
+    scall,
+    eret,
+  
+    
+
+
+  
+    
+
+
+    csr_write_enable
+    );
+
+
+
+
+
+input [ (32-1):0] instruction;       
+
+
+
+
+
+output [ 0:0] d_result_sel_0;
+reg    [ 0:0] d_result_sel_0;
+output [ 1:0] d_result_sel_1;
+reg    [ 1:0] d_result_sel_1;
+output x_result_sel_csr;
+reg    x_result_sel_csr;
+  
+ 
+    
+
+
+  
+    
+output x_result_sel_shift;
+reg    x_result_sel_shift;
+ 
+
+  
+ 
+    
+
+
+output x_result_sel_logic;
+reg    x_result_sel_logic;
+  
+ 
+    
+
+
+output x_result_sel_add;
+reg    x_result_sel_add;
+output m_result_sel_compare;
+reg    m_result_sel_compare;
+  
+ 
+    
+
+
+output w_result_sel_load;
+reg    w_result_sel_load;
+  
+ 
+    
+
+
+output x_bypass_enable;
+wire   x_bypass_enable;
+output m_bypass_enable;
+wire   m_bypass_enable;
+output read_enable_0;
+wire   read_enable_0;
+output [ (5-1):0] read_idx_0;
+wire   [ (5-1):0] read_idx_0;
+output read_enable_1;
+wire   read_enable_1;
+output [ (5-1):0] read_idx_1;
+wire   [ (5-1):0] read_idx_1;
+output write_enable;
+wire   write_enable;
+output [ (5-1):0] write_idx;
+wire   [ (5-1):0] write_idx;
+output [ (32-1):0] immediate;
+wire   [ (32-1):0] immediate;
+output [ ((32-2)+2-1):2] branch_offset;
+wire   [ ((32-2)+2-1):2] branch_offset;
+output load;
+wire   load;
+output store;
+wire   store;
+output [ 1:0] size;
+wire   [ 1:0] size;
+output sign_extend;
+wire   sign_extend;
+output adder_op;
+wire   adder_op;
+output [ 3:0] logic_op;
+wire   [ 3:0] logic_op;
+  
+ 
+   
+
+
+  
+ 
+   
+ 
+   
+
+
+  
+ 
+   
+
+
+  
+ 
+   
+ 
+   
+
+
+output branch;
+wire   branch;
+output branch_reg;
+wire   branch_reg;
+output [ (3-1):0] condition;
+wire   [ (3-1):0] condition;
+output bi_conditional;
+wire bi_conditional;
+output bi_unconditional;
+wire bi_unconditional;
+  
+ 
+   
+
+
+output scall;
+wire   scall;
+output eret;
+wire   eret;
+  
+ 
+   
+
+
+  
+  
+    
+
+
+output csr_write_enable;
+wire   csr_write_enable;
+
+
+
+
+
+wire [ (32-1):0] extended_immediate;       
+wire [ (32-1):0] high_immediate;           
+wire [ (32-1):0] call_immediate;           
+wire [ (32-1):0] branch_immediate;         
+wire sign_extend_immediate;                     
+wire select_high_immediate;                     
+wire select_call_immediate;                     
+
+wire op_add;
+wire op_and;
+wire op_andhi;
+wire op_b;
+wire op_bi;
+wire op_be;
+wire op_bg;
+wire op_bge;
+wire op_bgeu;
+wire op_bgu;
+wire op_bne;
+wire op_call;
+wire op_calli;
+wire op_cmpe;
+wire op_cmpg;
+wire op_cmpge;
+wire op_cmpgeu;
+wire op_cmpgu;
+wire op_cmpne;
+  
+ 
+
+
+wire op_lb;
+wire op_lbu;
+wire op_lh;
+wire op_lhu;
+wire op_lw;
+  
+ 
+
+
+  
+ 
+
+
+wire op_nor;
+wire op_or;
+wire op_orhi;
+wire op_raise;
+wire op_rcsr;
+wire op_sb;
+  
+ 
+ 
+
+
+wire op_sh;
+  
+ 
+
+
+wire op_sr;
+wire op_sru;
+wire op_sub;
+wire op_sw;
+  
+ 
+
+
+wire op_wcsr;
+wire op_xnor;
+wire op_xor;
+
+wire arith;
+wire logical;
+wire cmp;
+wire bra;
+wire call;
+  
+ 
+
+
+  
+
+wire shift;
+ 
+
+  
+ 
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+assign op_add    = instruction[ 30:26] ==  5'b01101;
+assign op_and    = instruction[ 30:26] ==  5'b01000;
+assign op_andhi  = instruction[ 31:26] ==  6'b011000;
+assign op_b      = instruction[ 31:26] ==  6'b110000;
+assign op_bi     = instruction[ 31:26] ==  6'b111000;
+assign op_be     = instruction[ 31:26] ==  6'b010001;
+assign op_bg     = instruction[ 31:26] ==  6'b010010;
+assign op_bge    = instruction[ 31:26] ==  6'b010011;
+assign op_bgeu   = instruction[ 31:26] ==  6'b010100;
+assign op_bgu    = instruction[ 31:26] ==  6'b010101;
+assign op_bne    = instruction[ 31:26] ==  6'b010111;
+assign op_call   = instruction[ 31:26] ==  6'b110110;
+assign op_calli  = instruction[ 31:26] ==  6'b111110;
+assign op_cmpe   = instruction[ 30:26] ==  5'b11001;
+assign op_cmpg   = instruction[ 30:26] ==  5'b11010;
+assign op_cmpge  = instruction[ 30:26] ==  5'b11011;
+assign op_cmpgeu = instruction[ 30:26] ==  5'b11100;
+assign op_cmpgu  = instruction[ 30:26] ==  5'b11101;
+assign op_cmpne  = instruction[ 30:26] ==  5'b11111;
+  
+       
+
+
+assign op_lb     = instruction[ 31:26] ==  6'b000100;
+assign op_lbu    = instruction[ 31:26] ==  6'b010000;
+assign op_lh     = instruction[ 31:26] ==  6'b000111;
+assign op_lhu    = instruction[ 31:26] ==  6'b001011;
+assign op_lw     = instruction[ 31:26] ==  6'b001010;
+  
+       
+
+
+  
+        
+
+
+assign op_nor    = instruction[ 30:26] ==  5'b00001;
+assign op_or     = instruction[ 30:26] ==  5'b01110;
+assign op_orhi   = instruction[ 31:26] ==  6'b011110;
+assign op_raise  = instruction[ 31:26] ==  6'b101011;
+assign op_rcsr   = instruction[ 31:26] ==  6'b100100;
+assign op_sb     = instruction[ 31:26] ==  6'b001100;
+  
+      
+      
+
+
+assign op_sh     = instruction[ 31:26] ==  6'b000011;
+  
+               
+
+
+assign op_sr     = instruction[ 30:26] ==  5'b00101;
+assign op_sru    = instruction[ 30:26] ==  5'b00000;
+assign op_sub    = instruction[ 31:26] ==  6'b110010;
+assign op_sw     = instruction[ 31:26] ==  6'b010110;
+  
+       
+
+
+assign op_wcsr   = instruction[ 31:26] ==  6'b110100;
+assign op_xnor   = instruction[ 30:26] ==  5'b01001;
+assign op_xor    = instruction[ 30:26] ==  5'b00110;
+
+
+assign arith = op_add | op_sub;
+assign logical = op_and | op_andhi | op_nor | op_or | op_orhi | op_xor | op_xnor;
+assign cmp = op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne;
+assign bi_conditional = op_be | op_bg | op_bge | op_bgeu  | op_bgu | op_bne;
+assign bi_unconditional = op_bi;
+assign bra = op_b | bi_unconditional | bi_conditional;
+assign call = op_call | op_calli;
+  
+       
+
+
+  
+
+assign shift = op_sr | op_sru;
+ 
+
+  
+   
+     
+
+
+  
+     
+
+
+  
+   
+
+
+  
+    
+   
+
+
+assign load = op_lb | op_lbu | op_lh | op_lhu | op_lw;
+assign store = op_sb | op_sh | op_sw;
+
+
+always @(*)
+begin
+    
+    if (call) 
+        d_result_sel_0 =  1'b1;
+    else 
+        d_result_sel_0 =  1'b0;
+    if (call) 
+        d_result_sel_1 =  2'b00;         
+    else if ((instruction[31] == 1'b0) && !bra) 
+        d_result_sel_1 =  2'b10;
+    else
+        d_result_sel_1 =  2'b01; 
+    
+    x_result_sel_csr =  1'b0;
+  
+      
+
+
+  
+
+    x_result_sel_shift =  1'b0;
+ 
+
+  
+      
+
+
+    x_result_sel_logic =  1'b0;
+          
+      
+
+
+    x_result_sel_add =  1'b0;
+    if (op_rcsr)
+        x_result_sel_csr =  1'b1;
+      
+ 
+         
+          
+
+ 
+        
+                  
+
+ 
+      
+                      
+
+
+
+  
+
+    else if (shift)
+        x_result_sel_shift =  1'b1;        
+ 
+
+  
+      
+          
+
+        
+    else if (logical) 
+        x_result_sel_logic =  1'b1;
+          
+      
+          
+
+
+    else 
+        x_result_sel_add =  1'b1;        
+    
+    
+
+    m_result_sel_compare = cmp;
+  
+      
+
+
+
+    
+    w_result_sel_load = load;
+  
+       
+
+
+end
+
+
+assign x_bypass_enable =  arith 
+                        | logical
+  
+                         
+                         
+
+                        
+  
+                         
+
+
+  
+                         
+                         
+
+
+  
+
+                        | shift
+ 
+                  
+  
+                          
+
+                        
+  
+                         
+
+
+                        | op_rcsr
+                        ;
+
+assign m_bypass_enable = x_bypass_enable 
+  
+                         
+
+
+                        | cmp
+                        ;
+
+assign read_enable_0 = ~(op_bi | op_calli);
+assign read_idx_0 = instruction[25:21];
+
+assign read_enable_1 = ~(op_bi | op_calli | load);
+assign read_idx_1 = instruction[20:16];
+
+assign write_enable = ~(bra | op_raise | store | op_wcsr);
+assign write_idx = call
+                    ? 5'd29
+                    : instruction[31] == 1'b0 
+                        ? instruction[20:16] 
+                        : instruction[15:11];
+                        
+
+assign size = instruction[27:26];
+
+assign sign_extend = instruction[28];                      
+
+assign adder_op = op_sub | op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne | bra;
+
+assign logic_op = instruction[29:26];
+  
+
+   
+
+
+
+assign branch = bra | call;
+assign branch_reg = op_call | op_b;
+assign condition = instruction[28:26];      
+  
+     
+
+
+assign scall = op_raise & instruction[2];
+assign eret = op_b & (instruction[25:21] == 5'd30);
+  
+       
+
+
+  
+
+   
+
+
+
+assign csr_write_enable = op_wcsr;
+
+
+
+assign sign_extend_immediate = ~(op_and | op_cmpgeu | op_cmpgu | op_nor | op_or | op_xnor | op_xor);
+assign select_high_immediate = op_andhi | op_orhi;
+assign select_call_immediate = instruction[31];
+
+assign high_immediate = {instruction[15:0], 16'h0000};
+assign extended_immediate = {{16{sign_extend_immediate & instruction[15]}}, instruction[15:0]};
+assign call_immediate = {{6{instruction[25]}}, instruction[25:0]};
+assign branch_immediate = {{16{instruction[15]}}, instruction[15:0]};
+
+assign immediate = select_high_immediate ==  1'b1 
+                        ? high_immediate 
+                        : extended_immediate;
+   
+assign branch_offset = select_call_immediate ==  1'b1   
+                        ? (call_immediate[ (32-2)-1:0])
+                        : (branch_immediate[ (32-2)-1:0]);
+    
+endmodule 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+  
+
+           
+              
+              
+              
+
+           
+             
+           
+             
+
+                
+                  
+              
+            
+
+                 
+          
+               
+               
+              
+
+
+
+
+
+   
+    
+    
+        
+    
+    
+    
+    
+    
+    
+    
+    
+ 
+    
+
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+
+
+
+
+
+                               
+                                      
+                             
+                                
+                                       
+
+   
+   
+   
+   
+   
+   
+   
+   
+   
+
+
+
+
+
+                                         
+                                         
+
+                                       
+                                       
+
+                                       
+                        
+   
+                       
+                       
+                                 
+
+                                  
+            
+
+                                        
+ 
+                                      
+
+   
+
+
+
+
+                                
+   
+                              
+    
+                               
+   
+                 
+                    
+                                    
+    
+                  
+    
+
+
+
+
+
+ 
+  
+  
+  
+  
+  
+ 
+
+  
+  
+  
+  
+  
+
+  
+ 
+ 
+ 
+
+  
+  
+ 
+  
+
+ 
+
+
+
+
+
+ 
+
+
+
+
+
+   
+                 
+	  
+	   
+	    
+	     
+	       
+	                        
+	                     
+
+ 
+	    
+	     
+	      
+	                         
+	                        
+	                            
+	                     
+	                      
+	                    
+	                     
+	                     
+	                           
+	      
+	                        
+	      
+	   
+	    
+	     
+	       
+	                        
+	                     
+
+	        
+	    
+	     
+	      
+	                         
+	                        
+	                            
+	                     
+	                      
+	                    
+	                     
+	                       
+	                       
+	      
+	                         
+	      
+	   
+	
+
+
+
+
+
+
+
+
+               
+      
+       
+    
+
+
+
+
+       
+      
+       
+    
+        
+	   
+           
+    
+
+
+
+ 
+       
+    
+    
+   
+
+    
+   
+
+
+   
+    
+                                 
+                                 
+
+
+ 
+                                   
+     
+    
+   
+
+
+
+     
+
+
+
+        
+           
+     
+    
+    
+      
+         
+         
+    
+                     
+
+
+     
+   
+
+
+   
+   
+   
+
+               
+     
+     
+                      
+
+
+
+
+
+
+        
+            
+   
+
+       
+           
+    
+            
+           
+               
+    
+
+    
+
+
+
+   
+
+       
+          
+    
+          
+
+
+
+   
+
+       
+    
+          
+          
+          
+          
+    
+     
+    
+         
+
+        
+        
+                    
+               
+                  
+                
+        
+
+        
+        
+                    
+               
+ 
+	       
+                  
+	      
+
+		  
+	   
+                
+        
+        
+        
+        
+                    
+               
+                  
+               
+            
+                  
+                  
+            
+                
+            
+                  
+                  
+            
+        
+
+        
+        
+                    
+               
+            
+                   
+                
+                      
+                      
+                
+            
+        
+
+                
+    
+
+
+ 
+       
+    
+
+   
+
+       
+          
+     
+    
+         
+        
+        
+        
+                    
+               
+                  
+                
+                  
+        
+
+        
+        
+                    
+               
+                    
+        
+
+                
+    
+
+    
+
+   
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+								 
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+  
+
+           
+              
+              
+              
+
+           
+             
+           
+             
+
+                
+                  
+              
+            
+
+                 
+               
+               
+              
+
+
+
+
+
+   
+    
+    
+        
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+
+
+
+
+
+                               
+                                      
+                             
+                                
+                                       
+
+   
+   
+   
+   
+   
+   
+   
+   
+   
+
+
+
+
+
+                                             
+                                             
+
+                                           
+                                           
+                                           
+
+                         
+                         
+                                          
+                                         
+                        
+          
+
+                                      
+                       
+
+                                            
+
+
+
+
+
+                                    
+   
+                                  
+    
+                                   
+    
+                   
+     
+                                        
+    
+                        
+    
+
+
+
+
+
+                                   
+                                  
+                     
+                     
+        
+  
+                       
+                       
+                                               
+
+          
+         
+          
+         
+                 
+                     
+
+                           
+                                           
+                                              
+                                             
+
+                                        
+                
+             
+                                        
+                   
+
+  
+
+
+
+
+
+ 
+
+
+
+
+
+   
+                     
+	  
+	   
+              
+               
+		 
+		  
+		    
+		     
+		     
+
+		      
+		    
+		     
+		      
+		      
+		      
+		      
+		      
+		      
+		      
+		      
+		          
+		     
+		      
+		         
+             
+           
+             
+		               
+		    
+		      
+		       
+			 
+			  
+			  
+
+			   
+			 
+			  
+			   
+			   
+			   
+			   
+			   
+			   
+			   
+			       
+			       
+			  
+			   
+			  
+		  
+             
+	   
+	   
+	    
+	     
+	       
+	        
+	        
+
+	         
+	       
+		
+		 
+		 
+		 
+		 
+		 
+		 
+		 
+		 
+		 
+		
+		  
+		
+	
+      
+   
+
+
+
+
+
+
+
+               
+      
+       
+    
+
+
+
+
+           
+	   
+   
+    
+        
+	   
+        
+    
+
+
+
+       
+    
+
+ 
+
+       
+          
+    
+    
+              
+              
+              
+              
+    
+
+    
+    
+    
+
+ 
+
+       
+          
+    
+          
+
+    
+
+
+
+ 
+        
+      
+                              
+                             
+    
+      
+                             
+                             
+
+   
+
+     
+                             
+                             
+   
+
+
+ 
+                                   
+     
+    
+   
+
+
+
+     
+       
+
+
+         
+
+
+
+        
+           
+             
+         
+     
+     
+      
+                 
+                 
+             
+             
+    
+
+
+
+             
+   
+
+
+   
+   
+   
+
+           
+     
+                      
+
+
+
+
+
+
+        
+            
+   
+
+       
+           
+    
+            
+           
+               
+    
+
+     
+   
+
+
+   
+
+       
+          
+     
+          
+
+
+
+   
+
+       
+    
+          
+          
+          
+          
+          
+    
+     
+    
+         
+
+        
+        
+        
+               
+                  
+                
+        
+        
+        
+        
+        
+               
+                  
+               
+            
+                  
+                  
+                  
+            
+                
+                  
+        
+
+        
+        
+        
+              
+               
+            
+                   
+                
+                      
+                      
+                
+            
+        
+        
+                
+    
+
+
+
+       
+    
+
+   
+
+       
+          
+     
+    
+         
+        
+        
+        
+        
+               
+                  
+        
+
+        
+        
+        
+               
+                    
+        
+        
+                
+    
+
+    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
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+ 
+ 
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+                    
+
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+                
+
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+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
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+ 
+ 
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+ 
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+
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+                   
+             
+               
+
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+
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+                  
+                    
+                 
+                   
+
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+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
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+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+  
+
+
+                  
+                 
+         
+     
+     
+              
+
+
+
+
+
+  
+    
+     
+    
+    
+    
+    
+    
+    
+    
+    
+ 
+ 
+    
+    
+    
+
+ 
+   
+   
+   
+
+ 
+
+		   
+ 
+    
+    
+    
+    
+    
+ 
+    
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+    
+ 
+    
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+    
+    
+    
+    
+    
+
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+
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+                         
+                         
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+
+
+
+
+                                     
+                                     
+
+                        
+                                    
+                                   
+      
+                        
+            
+                      
+ 
+ 
+                     
+       
+                   
+
+    
+                          
+            
+                          
+
+
+
+
+ 
+                                  
+                                  
+                                   
+                               
+                                       
+ 
+                     
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+
+
+
+ 
+                                    
+    
+
+                                    
+    
+                                 
+           
+                                 
+   
+
+
+
+
+
+                                        
+
+
+
+         
+                       
+                
+
+     
+         
+                
+
+                     
+       
+                   
+
+ 
+
+             
+
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+
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+ 
+
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+
+
+
+
+               
+      
+         
+    
+
+ 
+ 
+        
+       
+    
+     
+
+        
+   
+    
+   
+
+    
+               
+
+ 
+               
+      
+             
+                   
+
+
+        
+                   
+    
+   
+
+                
+                 
+
+ 
+         
+         
+         
+
+   
+ 
+         
+         
+         
+
+
+   
+
+   
+   
+   
+
+
+
+
+
+
+
+
+               
+      
+   
+
+       
+    
+          
+          
+    
+    
+    
+                 
+        
+              
+              
+        
+    
+    
+    
+
+
+
+
+               
+      
+   
+
+       
+    
+          
+          
+    
+    
+    
+           
+        
+               
+                  
+                 
+                  
+        
+      
+
+    
+
+
+
+   
+
+       
+          
+    
+    
+               
+              
+    
+    
+
+ 
+
+   
+
+       
+    
+          
+          
+    
+    
+    
+               
+        
+              
+                
+                  
+             
+                  
+        
+         
+        
+        
+            
+                     
+                       
+                    
+                   
+               
+                   
+        
+        
+        
+            
+                   
+                  
+        
+        
+        
+            
+ 
+               
+                  
+             
+
+                            
+            
+                  
+                  
+            
+        
+        
+        
+            
+ 
+               
+                  
+             
+
+                  
+        
+        
+    
+
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+  
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+
+
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+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
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+ 
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+ 
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+ 
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+ 
+ 
+
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+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_instruction_unit_minimal (
+    
+    clk_i,
+    rst_i,
+    
+    stall_a,
+    stall_f,
+    stall_d,
+    stall_x,
+    stall_m,
+    valid_f,
+    valid_d,
+    kill_f,
+    branch_predict_taken_d,
+    branch_predict_address_d,
+      
+    
+    
+
+
+    exception_m,
+    branch_taken_m,
+    branch_mispredict_taken_m,
+    branch_target_m,
+  
+    
+
+
+  
+    
+    
+    
+
+        
+  
+
+    
+    i_dat_i,
+    i_ack_i,
+    i_err_i,
+    i_rty_i,
+ 
+
+  
+    
+    
+    
+    
+
+
+    
+    
+    pc_f,
+    pc_d,
+    pc_x,
+    pc_m,
+    pc_w,
+  
+    
+    
+    
+    
+
+
+  
+
+    
+    i_dat_o,
+    i_adr_o,
+    i_cyc_o,
+    i_sel_o,
+    i_stb_o,
+    i_we_o,
+    i_cti_o,
+    i_lock_o,
+    i_bte_o,
+ 
+
+  
+    
+    
+    
+
+
+  
+    
+    
+
+
+  
+    
+
+
+  
+
+    instruction_f,
+ 
+    
+    instruction_d
+    );
+
+
+
+
+
+parameter eba_reset =  32'h00000000;                   
+parameter associativity = 1;                            
+parameter sets = 512;                                   
+parameter bytes_per_line = 16;                          
+parameter base_address = 0;                             
+parameter limit = 0;                                    
+
+
+localparam eba_reset_minus_4 = eba_reset - 4;
+localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
+localparam addr_offset_lsb = 2;
+localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
+
+
+
+
+  
+  
+   
+        
+   
+
+
+
+input clk_i;                                            
+input rst_i;                                            
+
+input stall_a;                                          
+input stall_f;                                          
+input stall_d;                                          
+input stall_x;                                          
+input stall_m;                                          
+input valid_f;                                          
+input valid_d;                                          
+input kill_f;                                           
+
+input branch_predict_taken_d;                           
+input [ ((32-2)+2-1):2] branch_predict_address_d;          
+   
+      
+                                    
+                     
+
+
+input exception_m;
+input branch_taken_m;                                   
+input branch_mispredict_taken_m;                        
+input [ ((32-2)+2-1):2] branch_target_m;                   
+
+  
+                                            
+
+
+  
+                            
+                             
+ 
+
+        
+
+
+  
+
+input [ (32-1):0] i_dat_i;                         
+input i_ack_i;                                          
+input i_err_i;                                          
+input i_rty_i;                                          
+ 
+
+
+  
+                                  
+                                 
+                   
+                      
+
+
+
+
+
+
+        
+output [ ((32-2)+2-1):2] pc_f;                             
+reg    [ ((32-2)+2-1):2] pc_f;
+output [ ((32-2)+2-1):2] pc_d;                             
+reg    [ ((32-2)+2-1):2] pc_d;
+output [ ((32-2)+2-1):2] pc_x;                             
+reg    [ ((32-2)+2-1):2] pc_x;
+output [ ((32-2)+2-1):2] pc_m;                             
+reg    [ ((32-2)+2-1):2] pc_m;
+output [ ((32-2)+2-1):2] pc_w;                             
+reg    [ ((32-2)+2-1):2] pc_w;
+
+  
+                             
+   
+                           
+   
+                            
+   
+                                 
+   
+
+
+
+  
+
+output [ (32-1):0] i_dat_o;                        
+  
+     
+
+
+wire   [ (32-1):0] i_dat_o;
+ 
+
+output [ (32-1):0] i_adr_o;                        
+reg    [ (32-1):0] i_adr_o;
+output i_cyc_o;                                         
+reg    i_cyc_o; 
+output [ (4-1):0] i_sel_o;                 
+  
+     
+
+
+wire   [ (4-1):0] i_sel_o;
+ 
+
+output i_stb_o;                                         
+reg    i_stb_o;
+output i_we_o;                                          
+  
+    
+
+
+wire   i_we_o;
+ 
+
+output [ (3-1):0] i_cti_o;                       
+reg    [ (3-1):0] i_cti_o;
+output i_lock_o;                                        
+reg    i_lock_o;
+output [ (2-1):0] i_bte_o;                       
+wire   [ (2-1):0] i_bte_o;
+ 
+
+
+  
+                   
+     
+                             
+   
+
+
+
+  
+                                      
+    
+
+
+  
+
+output [ (32-1):0] instruction_f;           
+wire   [ (32-1):0] instruction_f;
+ 
+
+output [ (32-1):0] instruction_d;           
+reg    [ (32-1):0] instruction_d;
+
+
+
+
+
+reg [ ((32-2)+2-1):2] pc_a;                                
+
+  
+                       
+
+
+
+  
+                               
+                
+                                 
+           
+               
+                  
+                   
+                                          
+                        
+
+
+  
+
+reg [ (32-1):0] wb_data_f;                  
+ 
+
+ 
+
+  
+                                      
+    			     
+   
+
+
+  
+
+ 
+               
+
+
+
+   
+  
+   
+    			               
+ 
+
+
+  
+    		       
+
+
+   
+  
+                                         
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+  
+
+ 
+              
+                       
+             
+               
+                      
+       
+    
+                      
+                            
+                    
+                    
+     
+                    
+                  
+                  
+              
+               
+                
+                     
+    
+              
+            
+             
+             
+                  
+                       
+    
+
+
+
+
+
+
+
+  
+   
+           
+        
+  
+      
+                          
+   
+				       
+        
+				    
+
+ 
+
+
+always @(*)
+begin
+    
+  
+       
+          
+     
+
+    
+      if (branch_taken_m ==  1'b1)
+	if ((branch_mispredict_taken_m ==  1'b1) && (exception_m ==  1'b0))
+	  pc_a = pc_x;
+	else
+          pc_a = branch_target_m;
+      
+          
+          
+
+
+      else
+	if ( (valid_d ==  1'b1) && (branch_predict_taken_d ==  1'b1) )
+	  pc_a = branch_predict_address_d;
+	else
+  
+             
+              
+	   
+
+        
+            pc_a = pc_f + 1'b1;
+end
+
+
+  
+      
+      
+        
+
+
+
+  
+
+     
+    	      
+
+     
+      
+	  
+       
+	  
+	
+	    
+     
+   
+   
+          
+
+
+  
+   
+
+
+                     
+
+  
+   
+
+
+assign instruction_f = wb_data_f;
+ 
+
+
+ 
+ 
+   
+
+  
+
+  
+
+
+assign i_dat_o = 32'd0;
+assign i_we_o =  1'b0;
+assign i_sel_o = 4'b1111;
+ 
+
+assign i_bte_o =  2'b00;
+ 
+
+
+  
+
+
+     
+    
+    
+   
+   
+   
+   
+    
+    
+    
+   
+   
+     
+    
+    
+    
+    
+   
+         
+     
+    
+    
+    
+
+
+
+                     
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        pc_f <= eba_reset_minus_4[ ((32-2)+2-1):2];
+        pc_d <= { (32-2){1'b0}};
+        pc_x <= { (32-2){1'b0}};
+        pc_m <= { (32-2){1'b0}};
+        pc_w <= { (32-2){1'b0}};
+    end
+    else
+    begin
+        if (stall_f ==  1'b0)
+            pc_f <= pc_a;
+        if (stall_d ==  1'b0)
+            pc_d <= pc_f;
+        if (stall_x ==  1'b0)
+            pc_x <= pc_d;
+        if (stall_m ==  1'b0)
+            pc_m <= pc_x;
+        pc_w <= pc_m;
+    end
+end
+
+  
+
+   
+
+       
+          
+    
+    
+ 
+         
+            
+               
+                  
+                    
+                  
+
+               
+                  
+
+
+         
+               
+                  
+
+
+    
+
+
+
+
+
+  
+   
+
+       
+          
+    
+    
+           
+              
+    
+
+
+
+
+  
+    
+                 
+ 
+
+     
+       
+       
+       
+       
+     
+
+   
+
+
+
+  
+
+   
+                   
+      
+     
+	   
+	  
+               
+               
+               
+               
+               
+               
+               
+   
+               
+  
+   
+               
+               
+               
+  
+	  
+	
+	     
+               
+             
+                
+               
+		  
+		         
+		    
+   
+                          
+			 
+			      
+			             
+			        
+			          
+			 
+                       
+  
+			 
+			       
+			      
+				 
+				   
+				   
+				   
+			      
+			    
+			        
+			      
+			    
+			      
+			      
+			 
+		    
+   
+		   
+		     
+		    
+                         
+                         
+		    
+		  
+  
+               
+             
+               
+		         
+		    
+                       
+        
+                         
+  
+                          
+                         
+                                         
+                         
+                       
+   
+                         
+  
+		    
+   
+		  
+		    
+                              
+			 
+			     
+			         
+			         
+			         
+			         
+			    
+			      
+			      
+			      
+			      
+			      
+			      
+			      
+			 
+		     
+                      
+   
+		  
+		  
+        
+		     
+                      
+   
+		     
+                      
+  
+               
+	  
+     
+ 
+
+   always @(posedge clk_i  )
+     begin
+	if (rst_i ==  1'b1)
+	  begin
+             i_cyc_o <=  1'b0;
+             i_stb_o <=  1'b0;
+             i_adr_o <= { 32{1'b0}};
+             i_cti_o <=  3'b111;
+             i_lock_o <=  1'b0;
+             wb_data_f <= { 32{1'b0}};
+    
+               
+  
+
+	  end
+	else
+	  begin   
+             
+             if (i_cyc_o ==  1'b1)
+               begin
+		  
+		  if((i_ack_i ==  1'b1) || (i_err_i ==  1'b1))
+		    begin
+                       
+                       i_cyc_o <=  1'b0;
+                       i_stb_o <=  1'b0;
+                       
+                       wb_data_f <= i_dat_i;
+		    end
+    
+		   
+		     
+		    
+                         
+                         
+		       
+		    
+		  
+  
+
+               end
+             else
+               begin
+		  
+		  if (   (stall_a ==  1'b0) 
+     
+			    
+  
+       
+			 )
+		    begin
+                       
+         
+                         
+  
+
+                       i_adr_o <= {pc_a, 2'b00};
+                       i_cyc_o <=  1'b1;
+                       i_stb_o <=  1'b1;
+    
+                         
+  
+
+		    end
+		  else
+		    begin
+	               if (   (stall_a ==  1'b0) 
+     
+			         
+  
+       
+			      )
+			 begin
+    
+			      
+  
+
+			 end
+		    end
+               end
+	  end
+     end
+  
+
+ 
+ 
+
+   
+   always @(posedge clk_i  )
+     begin
+	if (rst_i ==  1'b1)
+	  begin
+             instruction_d <= { 32{1'b0}};
+  
+               
+
+
+	  end
+	else
+	  begin
+             if (stall_d ==  1'b0)
+               begin
+		  instruction_d <= instruction_f;
+  
+		    
+
+
+               end
+	  end
+     end  
+   
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+  
+
+                              
+                              
+                              
+
+
+                          
+                  
+                 
+              
+             
+                    
+                        
+                        
+
+
+                  
+         
+          
+          
+          
+          
+          
+      
+      
+         
+
+
+
+
+
+  
+    
+    
+    
+     
+    
+    
+    
+ 
+    
+    
+    
+    
+
+ 
+    
+    
+
+ 
+    
+
+    
+ 
+    
+    
+
+ 
+    
+    
+    
+    
+    
+    
+    
+
+ 
+    
+    
+
+    
+    
+    
+
+
+
+
+
+                                             
+                                             
+
+                                          
+                                       
+                        
+                              
+
+ 
+                                
+                                  
+                    
+                                           
+
+ 
+                    
+                              
+
+ 
+                                     
+
+
+
+
+
+       
+ 
+                
+    
+                
+    
+
+ 
+                            
+    
+              
+    
+                          
+    
+                                 
+    
+                                
+    
+                  
+            
+                     
+    
+
+ 
+                                       
+    
+                                       
+    
+
+  
+     
+  
+    
+             
+
+
+
+
+                           
+                         
+                       
+                     
+
+
+
+     
+  
+
+                  
+        
+                       
+        
+                       
+
+
+               
+ 
+         
+  
+  
+  
+  
+                          
+
+
+         
+
+
+
+
+
+ 
+      
+   
+      
+   
+
+                 
+
+                  
+             
+
+   
+
+ 
+   
+
+   
+
+
+                  
+     
+     
+         
+                 
+
+
+
+
+   
+   
+
+
+
+   
+
+       
+    
+          
+          
+          
+          
+    
+    
+    
+          
+          
+          
+          
+    
+
+
+
+   
+
+       
+    
+          
+          
+          
+ 
+          
+          
+          
+          
+
+ 
+          
+          
+
+                  
+          
+          
+          
+          
+
+    
+    
+    
+                  
+               
+        
+             
+            
+            
+                
+                  
+                  
+            
+            
+            
+                
+                  
+            
+            
+        
+
+ 
+        
+           
+        
+              
+              
+        
+
+         
+        
+        
+            
+                 
+            
+                                  
+                 
+ 
+                
+                
+                     
+ 
+                    
+                          
+                    
+                    
+                              
+                          
+                    
+                    
+                          
+                    
+                    
+                              
+                          
+                    
+                    
+                          
+                    
+                    
+                    
+      
+                              
+                                   
+
+                          
+                    
+                    
+                    
+      
+                              
+                                   
+
+                          
+                    
+                                                   
+                
+
+                  
+                
+                
+                      
+                      
+                                    
+                
+                
+                      
+                      
+                
+
+                
+                    
+                                
+            
+        
+ 
+        
+        
+                 
+            
+                  
+                  
+            
+        
+        
+        
+                 
+            
+                  
+                  
+            
+        
+        
+        
+                 
+            
+                  
+                  
+            
+        
+        
+        
+                 
+            
+                  
+                   
+                      
+                 
+                      
+            
+        
+        
+        
+                 
+            
+                  
+                  
+            
+        
+        
+        
+             
+            
+            
+            
+                  
+                  
+                  
+            
+            
+            
+            
+                  
+                  
+                  
+            
+            
+            
+                  
+                  
+                  
+            
+            
+        
+        
+        
+               
+                      
+                  
+                  
+                    
+                  
+                  
+            
+            
+        
+        
+              
+              
+              
+            
+
+        
+    
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_interrupt_minimal (
+    
+    clk_i, 
+    rst_i,
+    
+    interrupt,
+    
+    stall_x,
+  
+    
+    
+
+
+    exception,
+ 
+
+    eret_q_x,
+  
+    
+
+
+    csr,
+    csr_write_data,
+    csr_write_enable,
+    
+    interrupt_exception,
+    
+    csr_read_data
+    );
+
+
+
+
+
+parameter interrupts =  32;         
+
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+
+input [interrupts-1:0] interrupt;               
+
+input stall_x;                                  
+
+  
+                       
+                           
+
+
+input exception;                                
+ 
+
+input eret_q_x;                                 
+  
+                                  
+
+
+
+input [ (4 -1):0] csr;                      
+input [ (32-1):0] csr_write_data;          
+input csr_write_enable;                         
+
+
+
+
+
+output interrupt_exception;                     
+wire   interrupt_exception;
+
+output [ (32-1):0] csr_read_data;          
+reg    [ (32-1):0] csr_read_data;
+
+
+
+
+
+wire [interrupts-1:0] asserted;                 
+
+wire [interrupts-1:0] interrupt_n_exception;
+
+
+
+reg ie;                                         
+reg eie;                                        
+  
+                                         
+
+
+reg [interrupts-1:0] ip;                        
+reg [interrupts-1:0] im;                        
+
+
+
+
+
+
+assign interrupt_n_exception = ip & im;
+
+
+assign interrupt_exception = (|interrupt_n_exception) & ie;
+
+
+assign asserted = ip | interrupt;
+       
+generate
+    if (interrupts > 1) 
+    begin
+
+always @(*)
+begin
+    case (csr)
+     4 'h0:  csr_read_data = {{ 32-3{1'b0}}, 
+  
+                                    
+
+
+                                    1'b0,                                     
+ 
+
+                                    eie, 
+                                    ie
+                                   };
+     4 'h2:  csr_read_data = ip;
+     4 'h1:  csr_read_data = im;
+    default:       csr_read_data = { 32{1'bx}};
+    endcase
+end
+    end
+    else
+    begin
+
+always @(*)
+begin
+    case (csr)
+     4 'h0:  csr_read_data = {{ 32-3{1'b0}}, 
+  
+                                     
+
+
+                                    1'b0,                                    
+ 
+
+                                    eie, 
+                                    ie
+                                   };
+     4 'h2:  csr_read_data = ip;
+    default:       csr_read_data = { 32{1'bx}};
+      endcase
+end
+    end
+endgenerate
+    
+
+
+
+
+  
+
+   reg [ 10:0] eie_delay  = 0;
+
+   
+generate
+
+   
+    if (interrupts > 1)
+    begin
+
+always @(posedge clk_i  )
+  begin
+    if (rst_i ==  1'b1)
+    begin
+        ie                   <=  1'b0;
+        eie                  <=  1'b0;
+  
+                           
+
+
+        im                   <= {interrupts{1'b0}};
+        ip                   <= {interrupts{1'b0}};
+       eie_delay             <= 0;
+       
+    end
+    else
+    begin
+        
+        ip                   <= asserted;
+  
+           
+        
+            
+                           
+                            
+        
+            
+        
+            
+                           
+                            
+        
+
+
+        if (exception ==  1'b1)
+        begin
+            
+            eie              <= ie;
+            ie               <=  1'b0;
+        end
+ 
+
+        else if (stall_x ==  1'b0)
+        begin
+
+           if(eie_delay[0])
+             ie              <= eie;
+           
+           eie_delay         <= {1'b0, eie_delay[ 10:1]};
+
+            if (eret_q_x ==  1'b1) begin
+                
+               eie_delay[ 10] <=  1'b1;
+               eie_delay[ 10-1:0] <= 0;
+            end
+           
+                      
+           
+  
+                
+                
+                       
+
+
+            else if (csr_write_enable ==  1'b1)
+            begin
+                
+                if (csr ==  4 'h0)
+                begin
+                    ie  <= csr_write_data[0];
+                    eie <= csr_write_data[1];
+  
+                      
+
+
+                end
+                if (csr ==  4 'h1)
+                    im  <= csr_write_data[interrupts-1:0];
+                if (csr ==  4 'h2)
+                    ip  <= asserted & ~csr_write_data[interrupts-1:0];
+            end
+        end
+    end
+end
+    end
+else
+    begin
+
+always @(posedge clk_i  )
+  begin
+    if (rst_i ==  1'b1)
+    begin
+        ie              <=  1'b0;
+        eie             <=  1'b0;
+  
+                      
+
+
+        ip              <= {interrupts{1'b0}};
+       eie_delay        <= 0;
+    end
+    else
+    begin
+        
+        ip              <= asserted;
+  
+           
+        
+            
+                      
+                       
+        
+            
+        
+            
+                      
+                       
+        
+
+
+        if (exception ==  1'b1)
+        begin
+            
+            eie         <= ie;
+            ie          <=  1'b0;
+        end
+ 
+
+        else if (stall_x ==  1'b0)
+          begin
+
+             if(eie_delay[0])
+               ie              <= eie;
+           
+             eie_delay         <= {1'b0, eie_delay[ 10:1]};
+
+             if (eret_q_x ==  1'b1) begin
+                
+                eie_delay[ 10] <=  1'b1;
+                eie_delay[ 10-1:0] <= 0;
+             end
+           
+  
+                
+                
+                       
+
+
+            else if (csr_write_enable ==  1'b1)
+            begin
+                
+                if (csr ==  4 'h0)
+                begin
+                    ie  <= csr_write_data[0];
+                    eie <= csr_write_data[1];
+  
+                      
+
+
+                end
+                if (csr ==  4 'h2)
+                    ip  <= asserted & ~csr_write_data[interrupts-1:0];
+            end
+        end
+    end
+end
+    end
+endgenerate
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+	 
+	 
+	 
+	 
+	
+
+ 
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+  
+
+
+
+
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+ 
+
+
+
+  
+ 
+
+
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+
+
+  
+                    
+
+
+  
+                    
+
+
+  
+
+  
+
+ 
+
+ 
+
+  
+
+
+
+  
+
+  
+
+
+
+  
+
+  
+
+
+
+  
+
+  
+
+
+
+  
+ 
+
+
+  
+
+  
+
+ 
+
+ 
+
+
+
+  
+ 
+
+
+  
+
+  
+
+ 
+
+
+ 
+
+
+
+  
+
+  
+
+  
+ 
+ 
+
+ 
+
+
+ 
+
+
+  
+
+  
+
+ 
+ 
+ 
+
+
+
+
+
+  
+
+  
+
+ 
+
+  
+ 
+
+
+  
+ 
+
+
+
+
+  
+
+  
+
+ 
+
+  
+ 
+
+
+
+
+  
+
+
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+ 
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+ 
+
+  
+
+  
+
+  
+
+  
+                     
+                     
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+ 
+ 
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+  
+
+  
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+
+  
+
+  
+
+
+
+  
+ 
+
+
+  
+ 
+
+
+ 
+
+
+
+
+
+
+
+  
+
+  
+
+  
+
+
+
+
+
+
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+
+
+  
+
+
+
+
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+ 
+
+
+
+
+
+
+
+
+module lm32_top_wr_node (
+    
+    clk_i,
+    rst_i,
+    
+
+    interrupt,
+
+    
+  
+    
+    
+
+     
+  
+    
+    
+    
+    
+    
+
+
+    
+    D_DAT_I,
+    D_ACK_I,
+    D_ERR_I,
+    D_RTY_I,
+    
+      
+    
+    
+    
+    
+
+    
+  
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+
+
+    
+    D_DAT_O,
+    D_ADR_O,
+    D_CYC_O,
+    D_SEL_O,
+    D_STB_O,
+    D_WE_O,
+    D_CTI_O,
+    D_LOCK_O,
+    D_BTE_O
+    );
+
+parameter eba_reset = 32'h00000000;
+parameter sdb_address = 32'h00000000;
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+
+
+input [ (32-1):0] interrupt;          
+
+
+  
+               
+                             
+
+    
+
+  
+                   
+                                   
+                                   
+                                   
+
+
+
+input [ (32-1):0] D_DAT_I;                 
+input D_ACK_I;                                  
+input D_ERR_I;                                  
+input D_RTY_I;                                  
+
+
+
+
+
+  
+                               
+   
+       
+     
+           
+    
+           
+    
+
+
+
+  
+                  
+    
+                  
+    
+                                  
+   
+           
+    
+                                  
+   
+                                   
+   
+                 
+    
+                                 
+   
+                 
+    
+
+
+
+output [ (32-1):0] D_DAT_O;                
+wire   [ (32-1):0] D_DAT_O;
+output [ (32-1):0] D_ADR_O;                
+wire   [ (32-1):0] D_ADR_O;
+output D_CYC_O;                                 
+wire   D_CYC_O;
+output [ (4-1):0] D_SEL_O;         
+wire   [ (4-1):0] D_SEL_O;
+output D_STB_O;                                 
+wire   D_STB_O;
+output D_WE_O;                                  
+wire   D_WE_O;
+output [ (3-1):0] D_CTI_O;               
+wire   [ (3-1):0] D_CTI_O;
+output D_LOCK_O;                                
+wire   D_LOCK_O;
+output [ (2-1):0] D_BTE_O;               
+wire   [ (2-1):0] D_BTE_O;
+  
+
+
+
+ 
+  
+
+  
+  
+ 
+  
+  
+ 
+ 
+
+
+
+
+  
+
+                     
+                             
+                            
+                   
+                                 
+ 
+                                 
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+   
+
+lm32_cpu_wr_node 
+	#(
+		.eba_reset(eba_reset),
+    .sdb_address(sdb_address)
+	) cpu (
+    
+    .clk_i                 (clk_i),
+  
+                   
+
+
+    .rst_i                 (rst_i),
+    
+  
+
+    .interrupt             (interrupt),
+ 
+
+    
+  
+               
+             
+
+     
+  
+    
+                  
+               
+                
+           
+
+
+  
+     
+                   
+                   
+                   
+                   
+
+
+    
+    .D_DAT_I               (D_DAT_I),
+    .D_ACK_I               (D_ACK_I),
+    .D_ERR_I               (D_ERR_I),
+    .D_RTY_I               (D_RTY_I),
+    
+  
+                  
+            
+           
+                 
+                
+ 
+                
+
+
+
+  
+                
+           
+
+
+      
+                
+               
+            
+            
+
+    
+  
+    
+                   
+                   
+                   
+                   
+                   
+                    
+                   
+                  
+                   
+    
+
+    
+    .D_DAT_O               (D_DAT_O),
+    .D_ADR_O               (D_ADR_O),
+    .D_CYC_O               (D_CYC_O),
+    .D_SEL_O               (D_SEL_O),
+    .D_STB_O               (D_STB_O),
+    .D_WE_O                (D_WE_O),
+    .D_CTI_O               (D_CTI_O),
+    .D_LOCK_O              (D_LOCK_O),
+    .D_BTE_O               (D_BTE_O)
+    );
+   
+  		   
+
+  
+    
+                     
+                
+    
+                
+                     
+                
+                      
+                     
+    
+
+        
+   
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+           
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_mc_arithmetic_wr_node (
+    
+    clk_i,
+    rst_i,
+    stall_d,
+    kill_x,
+  
+
+    divide_d,
+    modulus_d,
+ 
+
+  
+    
+
+
+  
+    
+    
+    
+
+
+    operand_0_d,
+    operand_1_d,
+    
+    result_x,
+  
+
+    divide_by_zero_x,
+ 
+
+    stall_request_x
+    );
+
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+input stall_d;                                  
+input kill_x;                                   
+  
+
+input divide_d;                                 
+input modulus_d;                                
+ 
+
+  
+                                
+
+
+  
+                              
+                             
+                             
+
+
+input [ (32-1):0] operand_0_d;
+input [ (32-1):0] operand_1_d;
+
+
+
+
+
+output [ (32-1):0] result_x;               
+reg    [ (32-1):0] result_x;
+  
+
+output divide_by_zero_x;                        
+reg    divide_by_zero_x;
+ 
+
+output stall_request_x;                         
+wire   stall_request_x;
+
+
+
+
+
+reg [ (32-1):0] p;                         
+reg [ (32-1):0] a;
+reg [ (32-1):0] b;
+  
+
+wire [32:0] t;
+ 
+
+
+reg [ 2:0] state;                 
+reg [5:0] cycles;                               
+
+  
+                               
+                                 
+
+
+
+
+
+
+
+
+assign stall_request_x = state !=  3'b000;
+
+  
+
+
+assign t = {p[ 32-2:0], a[ 32-1]} - b;
+ 
+
+
+  
+
+       
+
+
+
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        cycles <= {6{1'b0}};
+        p <= { 32{1'b0}};
+        a <= { 32{1'b0}};
+        b <= { 32{1'b0}};
+  
+          
+
+
+  
+
+        divide_by_zero_x <=  1'b0;
+ 
+
+        result_x <= { 32{1'b0}};
+        state <=  3'b000;
+    end
+    else
+    begin
+  
+
+        divide_by_zero_x <=  1'b0;
+ 
+
+        case (state)
+         3'b000:
+        begin
+            if (stall_d ==  1'b0)                 
+            begin          
+                cycles <=  32;
+                p <= 32'b0;
+                a <= operand_0_d;
+                b <= operand_1_d;                    
+  
+
+                if (divide_d ==  1'b1)
+                    state <=  3'b011 ;
+                if (modulus_d ==  1'b1)
+                    state <=  3'b010   ;
+ 
+                    
+  
+                   
+                      
+
+
+  
+                   
+                
+                      
+                      
+                      
+                      
+                      
+                
+                   
+                
+                      
+                      
+                      
+                      
+                      
+                
+
+
+            end            
+        end
+  
+
+         3'b011 :
+        begin
+            if (t[32] == 1'b0)
+            begin
+                p <= t[31:0];
+                a <= {a[ 32-2:0], 1'b1};
+            end
+            else 
+            begin
+                p <= {p[ 32-2:0], a[ 32-1]};
+                a <= {a[ 32-2:0], 1'b0};
+            end
+            result_x <= a;
+            if ((cycles ==  32'd0) || (kill_x ==  1'b1))
+            begin
+                
+                divide_by_zero_x <= b == { 32{1'b0}};
+                state <=  3'b000;
+            end
+            cycles <= cycles - 1'b1;
+        end
+         3'b010   :
+        begin
+            if (t[32] == 1'b0)
+            begin
+                p <= t[31:0];
+                a <= {a[ 32-2:0], 1'b1};
+            end
+            else 
+            begin
+                p <= {p[ 32-2:0], a[ 32-1]};
+                a <= {a[ 32-2:0], 1'b0};
+            end
+            result_x <= p;
+            if ((cycles ==  32'd0) || (kill_x ==  1'b1))
+            begin
+                
+                divide_by_zero_x <= b == { 32{1'b0}};
+                state <=  3'b000;
+            end
+            cycles <= cycles - 1'b1;
+        end
+ 
+        
+  
+        
+        
+               
+                    
+               
+               
+              
+                   
+                  
+                
+        
+
+     
+  
+        
+               
+               
+              
+                   
+                  
+                
+        
+        
+               
+               
+              
+                   
+                  
+                
+        
+
+   
+        endcase
+    end
+end 
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_cpu_wr_node (
+    
+    clk_i,
+  
+    
+
+
+    rst_i,
+  
+
+    enable_i,
+ 
+
+  
+
+   dbg_exception_o,
+   dbg_csr_write_enable_i,
+   dbg_csr_write_data_i,
+   dbg_csr_addr_i,
+   dbg_break_i,
+   dbg_reset_i,
+ 
+
+
+    
+  
+
+    interrupt,
+ 
+
+    
+  
+    
+    
+
+     
+  
+    
+    
+     
+    
+    
+
+
+  
+    
+    
+    
+    
+    
+
+
+    
+    D_DAT_I,
+    D_ACK_I,
+    D_ERR_I,
+    D_RTY_I,
+    
+  
+    
+    
+    
+    
+    
+ 
+    
+
+
+
+  
+    
+    
+
+
+      
+    
+    
+    
+    
+
+    
+  
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+
+ 
+  
+
+    iram_i_adr_o,
+    iram_i_dat_i,
+    iram_i_en_o,
+    iram_d_adr_o,
+    iram_d_dat_o,
+    iram_d_dat_i,
+    iram_d_sel_o,
+    iram_d_we_o,
+    iram_d_en_o,       
+ 
+
+		 
+		 
+    
+    D_DAT_O,
+    D_ADR_O,
+    D_CYC_O,
+    D_SEL_O,
+    D_STB_O,
+    D_WE_O,
+    D_CTI_O,
+    D_LOCK_O,
+    D_BTE_O
+
+		 
+    );
+
+
+
+
+
+parameter eba_reset =  32'h00000000;                           
+  
+
+parameter deba_reset =  32'h10000000;                         
+ 
+
+parameter sdb_address =   32'h00000000;
+
+  
+        
+                          
+      
+          
+                        
+
+
+parameter icache_associativity = 1;    
+parameter icache_sets = 512;                      
+parameter icache_bytes_per_line = 16;  
+parameter icache_base_address = 0;      
+parameter icache_limit = 0;                    
+ 
+
+
+  
+        
+                          
+      
+          
+                        
+
+
+parameter dcache_associativity = 1;    
+parameter dcache_sets = 512;                      
+parameter dcache_bytes_per_line = 16;  
+parameter dcache_base_address = 0;      
+parameter dcache_limit = 0;                    
+ 
+
+
+  
+
+parameter watchpoints =  32'h4;                       
+ 
+   
+
+
+  
+                          
+
+
+parameter breakpoints = 0;
+ 
+
+
+  
+
+parameter interrupts =  32;                         
+ 
+   
+
+
+
+
+
+
+
+input clk_i;                                    
+  
+                                   
+
+    
+input rst_i;                                    
+
+  
+
+input [ (32-1):0] interrupt;          
+ 
+
+
+  
+               
+                             
+
+    
+
+   
+                                  
+                               
+                
+  
+
+
+
+  
+                   
+                                   
+                                   
+                                   
+
+
+
+input [ (32-1):0] D_DAT_I;                 
+input D_ACK_I;                                  
+input D_ERR_I;                                  
+input D_RTY_I;                                  
+
+
+
+
+
+  
+
+   input enable_i;
+   wire  enable_i;
+ 
+
+   
+   
+  
+                   
+     
+                           
+    
+                          
+    
+                 
+     
+                               
+    
+ 
+                               
+    
+
+
+
+
+  
+  
+    
+  
+    
+
+
+
+  
+                               
+   
+       
+     
+           
+    
+           
+    
+
+
+
+  
+                  
+    
+                  
+    
+                                  
+   
+           
+    
+                                  
+   
+                                   
+   
+                 
+    
+                                 
+   
+                 
+    
+
+
+
+output [ (32-1):0] D_DAT_O;                
+wire   [ (32-1):0] D_DAT_O;
+output [ (32-1):0] D_ADR_O;                
+wire   [ (32-1):0] D_ADR_O;
+output D_CYC_O;                                 
+wire   D_CYC_O;
+output [ (4-1):0] D_SEL_O;         
+wire   [ (4-1):0] D_SEL_O;
+output D_STB_O;                                 
+wire   D_STB_O;
+output D_WE_O;                                  
+wire   D_WE_O;
+output [ (3-1):0] D_CTI_O;               
+wire   [ (3-1):0] D_CTI_O;
+output D_LOCK_O;                                
+wire   D_LOCK_O;
+output [ (2-1):0] D_BTE_O;               
+wire   [ (2-1):0] D_BTE_O;
+
+  
+
+   output [31:0] iram_i_adr_o, iram_d_adr_o;
+   output [31:0] iram_d_dat_o;
+   input [31:0]  iram_i_dat_i, iram_d_dat_i;
+   output [3:0]  iram_d_sel_o;
+   output        iram_d_en_o, iram_i_en_o, iram_d_we_o;
+ 
+
+   
+
+
+
+
+
+
+  
+                                     
+
+
+reg valid_f;                                    
+reg valid_d;                                    
+reg valid_x;                                    
+reg valid_m;                                    
+reg valid_w;                                    
+   
+wire q_x;
+wire [ (32-1):0] immediate_d;              
+wire load_d;                                    
+reg load_x;                                     
+reg load_m;
+wire load_q_x;
+wire store_q_x;
+wire q_m;
+wire load_q_m;
+wire store_q_m;
+wire store_d;                                   
+reg store_x;
+reg store_m;
+wire [ 1:0] size_d;                   
+reg [ 1:0] size_x;
+wire branch_d;                                  
+wire branch_predict_d;                          
+wire branch_predict_taken_d;                    
+wire [ ((32-2)+2-1):2] branch_predict_address_d;   
+wire [ ((32-2)+2-1):2] branch_target_d;
+wire bi_unconditional;
+wire bi_conditional;
+reg branch_x;                                   
+reg branch_predict_x;
+reg branch_predict_taken_x;
+reg branch_m;
+reg branch_predict_m;
+reg branch_predict_taken_m;
+wire branch_mispredict_taken_m;                 
+wire branch_flushX_m;                           
+wire branch_reg_d;                              
+wire [ ((32-2)+2-1):2] branch_offset_d;            
+reg [ ((32-2)+2-1):2] branch_target_x;             
+reg [ ((32-2)+2-1):2] branch_target_m;
+wire [ 0:0] d_result_sel_0_d; 
+wire [ 1:0] d_result_sel_1_d; 
+
+wire x_result_sel_csr_d;                        
+reg x_result_sel_csr_x;
+  
+
+wire q_d;
+wire x_result_sel_mc_arith_d;                   
+reg x_result_sel_mc_arith_x;
+ 
+
+      
+                       
+ 
+
+
+  
+
+wire x_result_sel_sext_d;                       
+reg x_result_sel_sext_x;
+ 
+
+wire x_result_sel_logic_d;                      
+  
+                        
+ 
+
+
+wire x_result_sel_add_d;                        
+reg x_result_sel_add_x;
+wire m_result_sel_compare_d;                    
+reg m_result_sel_compare_x;
+reg m_result_sel_compare_m;
+  
+
+wire m_result_sel_shift_d;                      
+reg m_result_sel_shift_x;
+reg m_result_sel_shift_m;
+ 
+
+wire w_result_sel_load_d;                       
+reg w_result_sel_load_x;
+reg w_result_sel_load_m;
+reg w_result_sel_load_w;
+  
+
+wire w_result_sel_mul_d;                        
+reg w_result_sel_mul_x;
+reg w_result_sel_mul_m;
+reg w_result_sel_mul_w;
+ 
+
+wire x_bypass_enable_d;                         
+reg x_bypass_enable_x;                          
+wire m_bypass_enable_d;                         
+reg m_bypass_enable_x;                          
+reg m_bypass_enable_m;
+wire sign_extend_d;                             
+reg sign_extend_x;
+wire write_enable_d;                            
+reg write_enable_x;
+wire write_enable_q_x;
+reg write_enable_m;
+wire write_enable_q_m;
+reg write_enable_w;
+wire write_enable_q_w;
+wire read_enable_0_d;                           
+wire [ (5-1):0] read_idx_0_d;          
+wire read_enable_1_d;                           
+wire [ (5-1):0] read_idx_1_d;          
+wire [ (5-1):0] write_idx_d;           
+reg [ (5-1):0] write_idx_x;            
+reg [ (5-1):0] write_idx_m;
+reg [ (5-1):0] write_idx_w;
+wire [ (5-1):0] csr_d;                     
+reg  [ (5-1):0] csr_x;                  
+wire [ (3-1):0] condition_d;         
+reg [ (3-1):0] condition_x;          
+  
+
+wire break_d;                                   
+reg break_x;                                    
+ 
+
+wire scall_d;                                   
+reg scall_x;    
+wire eret_d;                                    
+reg eret_x;
+wire eret_q_x;
+  
+ 
+ 
+
+
+  
+
+wire bret_d;                                    
+reg bret_x;
+wire bret_q_x;
+  
+ 
+ 
+
+
+ 
+
+wire csr_write_enable_d;                        
+reg csr_write_enable_x;
+wire csr_write_enable_q_x;
+  
+       
+
+
+
+  
+
+wire bus_error_d;                               
+reg bus_error_x;
+reg data_bus_error_exception_m;
+reg [ ((32-2)+2-1):2] memop_pc_w;
+ 
+
+
+reg [ (32-1):0] d_result_0;                
+reg [ (32-1):0] d_result_1;                
+reg [ (32-1):0] x_result;                  
+reg [ (32-1):0] m_result;                  
+reg [ (32-1):0] w_result;                  
+
+reg [ (32-1):0] operand_0_x;               
+reg [ (32-1):0] operand_1_x;               
+reg [ (32-1):0] store_operand_x;           
+reg [ (32-1):0] operand_m;                 
+reg [ (32-1):0] operand_w;                 
+
+
+  
+
+reg [ (32-1):0] reg_data_live_0;          
+reg [ (32-1):0] reg_data_live_1;  
+reg use_buf;                                    
+reg [ (32-1):0] reg_data_buf_0;
+reg [ (32-1):0] reg_data_buf_1;
+ 
+
+  
+
+ 
+     
+
+
+wire [ (32-1):0] reg_data_0;               
+wire [ (32-1):0] reg_data_1;               
+reg [ (32-1):0] bypass_data_0;             
+reg [ (32-1):0] bypass_data_1;             
+wire reg_write_enable_q_w;
+
+reg interlock;                                  
+
+wire stall_a;                                   
+wire stall_f;                                   
+wire stall_d;                                   
+wire stall_x;                                   
+wire stall_m;                                   
+
+
+wire adder_op_d;                                
+reg adder_op_x;                                 
+reg adder_op_x_n;                               
+wire [ (32-1):0] adder_result_x;           
+wire adder_overflow_x;                          
+wire adder_carry_n_x;                           
+
+
+wire [ 3:0] logic_op_d;           
+reg [ 3:0] logic_op_x;            
+wire [ (32-1):0] logic_result_x;           
+
+  
+
+
+wire [ (32-1):0] sextb_result_x;           
+wire [ (32-1):0] sexth_result_x;           
+wire [ (32-1):0] sext_result_x;            
+ 
+
+
+
+  
+
+  
+                                   
+                                     
+
+
+wire direction_d;                               
+reg direction_x;                                        
+wire [ (32-1):0] shifter_result_m;         
+ 
+
+  
+                               
+ 
+                              
+ 
+
+
+  
+           
+
+
+
+
+  
+
+wire [ (32-1):0] multiplier_result_w;      
+ 
+
+  
+                                 
+ 
+
+
+
+
+  
+
+wire divide_d;                                  
+wire divide_q_d;
+wire modulus_d;
+wire modulus_q_d;
+wire divide_by_zero_x;                          
+ 
+
+
+
+  
+
+wire mc_stall_request_x;                        
+wire [ (32-1):0] mc_result_x;
+ 
+
+
+
+  
+
+wire [ (32-1):0] interrupt_csr_read_data_x;
+ 
+
+wire [ (32-1):0] cfg;                      
+wire [ (32-1):0] cfg2;                     
+  
+                          
+
+
+reg [ (32-1):0] csr_read_data_x;           
+
+
+wire [ ((32-2)+2-1):2] pc_f;                       
+wire [ ((32-2)+2-1):2] pc_d;                       
+wire [ ((32-2)+2-1):2] pc_x;                       
+wire [ ((32-2)+2-1):2] pc_m;                       
+wire [ ((32-2)+2-1):2] pc_w;                       
+  
+                          
+
+
+  
+
+wire [ (32-1):0] instruction_f;     
+ 
+
+
+
+wire [ (32-1):0] instruction_d;     
+  
+                                     
+                       
+                     
+                      
+                           
+
+
+
+
+  
+                                   
+                                     
+                       
+                     
+                      
+                           
+
+
+wire [ (32-1):0] load_data_w;              
+wire stall_wb_load;                             
+
+
+  
+ 
+          
+          
+
+ 
+                      
+        
+                    
+                           
+  
+ 
+  
+  
+ 
+
+ 
+                                 
+
+
+
+
+
+wire raw_x_0;                                   
+wire raw_x_1;                                   
+wire raw_m_0;                                   
+wire raw_m_1;                                   
+wire raw_w_0;                                   
+wire raw_w_1;                                   
+
+
+wire cmp_zero;                                  
+wire cmp_negative;                              
+wire cmp_overflow;                              
+wire cmp_carry_n;                               
+reg condition_met_x;                            
+reg condition_met_m;
+      
+                             
+
+
+wire branch_taken_m;                            
+
+wire kill_f;                                    
+wire kill_d;                                    
+wire kill_x;                                    
+wire kill_m;                                    
+wire kill_w;                                    
+
+reg [ (32-2)+2-1:8] eba;                 
+  
+
+reg [ (32-2)+2-1:8] deba;                
+ 
+
+reg [ (3-1):0] eid_x;                      
+  
+                        
+                        
+
+
+
+  
+
+  
+
+wire dc_ss;                                     
+ 
+
+wire dc_re;                                     
+wire bp_match;
+wire wp_match;
+wire exception_x;                               
+reg exception_m;                                
+wire debug_exception_x;                         
+reg debug_exception_m;
+reg debug_exception_w;
+wire debug_exception_q_w;
+wire non_debug_exception_x;                     
+reg non_debug_exception_m;
+reg non_debug_exception_w;
+wire non_debug_exception_q_w;
+ 
+                                
+ 
+ 
+ 
+
+
+
+  
+
+   
+                            
+
+
+  
+
+wire reset_exception;                           
+ 
+
+ 
+
+  
+
+wire interrupt_exception;                       
+ 
+
+  
+
+wire breakpoint_exception;                      
+wire watchpoint_exception;                      
+ 
+
+  
+
+   reg [ (32-1):0] data_bus_error_addr;
+   
+wire instruction_bus_error_exception;           
+wire data_bus_error_exception;                  
+ 
+
+  
+
+wire divide_by_zero_exception;                  
+ 
+
+wire system_call_exception;                     
+
+  
+
+reg data_bus_error_seen;                        
+ 
+
+
+   
+
+   wire iram_stall_request_x;
+ 
+
+     
+  
+
+input dbg_csr_write_enable_i;                         
+wire   dbg_csr_write_enable_i;
+input [ (32-1):0] dbg_csr_write_data_i;          
+wire  [ (32-1):0] dbg_csr_write_data_i;
+input [ (5-1):0] dbg_csr_addr_i;                        
+wire  [ (5-1):0] dbg_csr_addr_i;
+
+   output 	      dbg_exception_o;
+   wire 	      dbg_exception_o;
+   input 	      dbg_reset_i;
+   wire 	      dbg_reset_i;
+   input 	      dbg_break_i;
+   wire 	      dbg_break_i;
+   
+   
+ 
+
+   
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+lm32_instruction_unit_wr_node #(
+    .eba_reset              (eba_reset),
+    .associativity          (icache_associativity),
+    .sets                   (icache_sets),
+    .bytes_per_line         (icache_bytes_per_line),
+    .base_address           (icache_base_address),
+    .limit                  (icache_limit)
+  ) instruction_unit (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    
+    .stall_a                (stall_a),
+    .stall_f                (stall_f),
+    .stall_d                (stall_d),
+    .stall_x                (stall_x),
+    .stall_m                (stall_m),
+    .valid_f                (valid_f),
+    .valid_d                (valid_d),
+    .kill_f                 (kill_f),
+    .branch_predict_taken_d (branch_predict_taken_d),
+    .branch_predict_address_d (branch_predict_address_d),
+      
+             
+            
+
+
+    .exception_m            (exception_m),
+    .branch_taken_m         (branch_taken_m),
+    .branch_mispredict_taken_m (branch_mispredict_taken_m),
+    .branch_target_m        (branch_target_m),
+  
+                     
+
+
+  
+     
+      
+           
+
+        
+  
+    
+                    
+                    
+                    
+                    
+
+
+  
+
+    .jtag_read_enable       (jtag_read_enable),
+    .jtag_write_enable      (jtag_write_enable),
+    .jtag_write_data        (jtag_write_data),
+    .jtag_address           (jtag_address),
+ 
+
+    
+    
+    .pc_f                   (pc_f),
+    .pc_d                   (pc_d),
+    .pc_x                   (pc_x),
+    .pc_m                   (pc_m),
+    .pc_w                   (pc_w),
+  
+       
+     
+      
+           
+
+
+  
+    
+                    
+                    
+                    
+                    
+                    
+                     
+                    
+                   
+                    
+
+ 
+
+  
+
+    .iram_i_adr_o(iram_i_adr_o),
+    .iram_i_dat_i(iram_i_dat_i),
+    .iram_i_en_o(iram_i_en_o),
+ 
+
+		      	      
+  
+
+    .jtag_read_data         (jtag_read_data),
+    .jtag_access_complete   (jtag_access_complete),
+ 
+
+  
+
+    .bus_error_d            (bus_error_d),
+ 
+
+  
+
+    .instruction_f          (instruction_f),
+ 
+
+
+		      
+    .instruction_d          (instruction_d)
+
+
+		      
+    );
+
+
+lm32_decoder_wr_node decoder (
+    
+    .instruction            (instruction_d),
+    
+    .d_result_sel_0         (d_result_sel_0_d),
+    .d_result_sel_1         (d_result_sel_1_d),
+    .x_result_sel_csr       (x_result_sel_csr_d),
+  
+
+    .x_result_sel_mc_arith  (x_result_sel_mc_arith_d),
+ 
+
+      
+         
+
+
+  
+
+    .x_result_sel_sext      (x_result_sel_sext_d),
+ 
+    
+    .x_result_sel_logic     (x_result_sel_logic_d),
+  
+          
+
+
+    .x_result_sel_add       (x_result_sel_add_d),
+    .m_result_sel_compare   (m_result_sel_compare_d),
+  
+
+    .m_result_sel_shift     (m_result_sel_shift_d),  
+ 
+    
+    .w_result_sel_load      (w_result_sel_load_d),
+  
+
+    .w_result_sel_mul       (w_result_sel_mul_d),
+ 
+
+    .x_bypass_enable        (x_bypass_enable_d),
+    .m_bypass_enable        (m_bypass_enable_d),
+    .read_enable_0          (read_enable_0_d),
+    .read_idx_0             (read_idx_0_d),
+    .read_enable_1          (read_enable_1_d),
+    .read_idx_1             (read_idx_1_d),
+    .write_enable           (write_enable_d),
+    .write_idx              (write_idx_d),
+    .immediate              (immediate_d),
+    .branch_offset          (branch_offset_d),
+    .load                   (load_d),
+    .store                  (store_d),
+    .size                   (size_d),
+    .sign_extend            (sign_extend_d),
+    .adder_op               (adder_op_d),
+    .logic_op               (logic_op_d),
+  
+
+    .direction              (direction_d),
+ 
+
+  
+                 
+                
+
+
+  
+                   
+
+
+  
+
+    .divide                 (divide_d),
+    .modulus                (modulus_d),
+ 
+
+    .branch                 (branch_d),
+    .bi_unconditional       (bi_unconditional),
+    .bi_conditional         (bi_conditional),
+    .branch_reg             (branch_reg_d),
+    .condition              (condition_d),
+  
+
+    .break_opcode           (break_d),
+ 
+
+    .scall                  (scall_d),
+    .eret                   (eret_d),
+  
+
+    .bret                   (bret_d),
+ 
+
+  
+                
+
+
+    .csr_write_enable       (csr_write_enable_d)
+    ); 
+
+
+lm32_load_store_unit_wr_node #(
+    .associativity          (dcache_associativity),
+    .sets                   (dcache_sets),
+    .bytes_per_line         (dcache_bytes_per_line),
+    .base_address           (dcache_base_address),
+    .limit                  (dcache_limit)
+  ) load_store_unit (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    
+    .stall_a                (stall_a),
+    .stall_x                (stall_x),
+    .stall_m                (stall_m),
+    .kill_x                 (kill_x),
+    .kill_m                 (kill_m),
+    .exception_m            (exception_m),
+    .store_operand_x        (store_operand_x),
+    .load_store_address_x   (adder_result_x),
+    .load_store_address_m   (operand_m),
+    .load_store_address_w   (operand_w[1:0]),
+    .load_x                 (load_x),
+    .store_x                (store_x),
+    .load_q_x               (load_q_x),
+    .store_q_x              (store_q_x),
+    .load_q_m               (load_q_m),
+    .store_q_m              (store_q_m),
+    .sign_extend_x          (sign_extend_x),
+    .size_x                 (size_x),
+  
+                     
+
+
+
+  
+
+    .iram_d_adr_o(iram_d_adr_o),
+    .iram_d_dat_o(iram_d_dat_o),
+    .iram_d_dat_i(iram_d_dat_i),
+    .iram_d_sel_o(iram_d_sel_o),
+    .iram_d_we_o(iram_d_we_o),
+    .iram_d_en_o(iram_d_en_o),
+    .iram_stall_request_x(iram_stall_request_x),
+ 
+
+		     
+    
+    .d_dat_i                (D_DAT_I),
+    .d_ack_i                (D_ACK_I),
+    .d_err_i                (D_ERR_I),
+    .d_rty_i                (D_RTY_I),
+    
+    
+  
+      
+     
+       
+           
+
+    
+    .load_data_w            (load_data_w),
+    .stall_wb_load          (stall_wb_load),
+    
+    .d_dat_o                (D_DAT_O),
+    .d_adr_o                (D_ADR_O),
+    .d_cyc_o                (D_CYC_O),
+    .d_sel_o                (D_SEL_O),
+    .d_stb_o                (D_STB_O),
+    .d_we_o                 (D_WE_O),
+    .d_cti_o                (D_CTI_O),
+    .d_lock_o               (D_LOCK_O),
+    .d_bte_o                (D_BTE_O)
+    );      
+       
+
+lm32_adder adder (
+    
+    .adder_op_x             (adder_op_x),
+    .adder_op_x_n           (adder_op_x_n),
+    .operand_0_x            (operand_0_x),
+    .operand_1_x            (operand_1_x),
+    
+    .adder_result_x         (adder_result_x),
+    .adder_carry_n_x        (adder_carry_n_x),
+    .adder_overflow_x       (adder_overflow_x)
+    );
+
+
+lm32_logic_op logic_op (
+    
+    .logic_op_x             (logic_op_x),
+    .operand_0_x            (operand_0_x),
+
+    .operand_1_x            (operand_1_x),
+    
+    .logic_result_x         (logic_result_x)
+    );
+              
+  
+
+
+lm32_shifter shifter (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    .stall_x                (stall_x),
+    .direction_x            (direction_x),
+    .sign_extend_x          (sign_extend_x),
+    .operand_0_x            (operand_0_x),
+    .operand_1_x            (operand_1_x),
+    
+    .shifter_result_m       (shifter_result_m)
+    );
+ 
+
+
+  
+
+
+lm32_multiplier multiplier (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    .stall_x                (stall_x),
+    .stall_m                (stall_m),
+    .operand_0              (d_result_0),
+    .operand_1              (d_result_1),
+    
+    .result                 (multiplier_result_w)    
+    );
+ 
+
+
+  
+
+
+lm32_mc_arithmetic_wr_node mc_arithmetic (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    .stall_d                (stall_d),
+    .kill_x                 (kill_x),
+  
+                  
+    .divide_d               (divide_q_d),
+    .modulus_d              (modulus_q_d),
+ 
+
+          
+                 
+
+
+  
+               
+              
+              
+
+    
+    .operand_0_d            (d_result_0),
+    .operand_1_d            (d_result_1),
+    
+    .result_x               (mc_result_x),
+  
+                  
+    .divide_by_zero_x       (divide_by_zero_x),
+ 
+
+    .stall_request_x        (mc_stall_request_x)
+    );
+ 
+
+              
+  
+
+
+lm32_interrupt_wr_node interrupt_unit (
+    
+    .clk_i                  (clk_i), 
+    .rst_i                  (rst_i),
+    
+    .interrupt              (interrupt),
+    
+    .stall_x                (stall_x),
+  
+
+    .non_debug_exception    (non_debug_exception_q_w), 
+    .debug_exception        (debug_exception_q_w),
+ 
+                   
+
+
+    .eret_q_x               (eret_q_x),
+  
+
+    .bret_q_x               (bret_q_x),
+ 
+
+    .csr                    (csr_x),
+    .csr_write_data         (operand_1_x),
+    .csr_write_enable       (csr_write_enable_q_x),
+    
+    .interrupt_exception    (interrupt_exception),
+    
+    .csr_read_data          (interrupt_csr_read_data_x)
+    );
+ 
+
+
+  
+
+   assign jtag_break = dbg_break_i;
+   assign reset_exception = dbg_reset_i;
+   assign dbg_exception_o = debug_exception_q_w || non_debug_exception_q_w;
+   
+ 
+
+
+
+  
+
+  
+    
+                      
+                      
+    
+                   
+                
+                 
+            
+    
+ 
+                        
+             
+           
+                    
+
+ 
+             
+       
+
+ 
+                
+    
+    
+    
+ 
+          
+          
+
+ 
+      
+        
+                   
+           
+          
+            
+               
+
+ 
+                 
+                 
+
+    
+                 
+            
+    
+
+
+
+  
+
+
+lm32_debug_wr_node #(
+    .breakpoints            (breakpoints),
+    .watchpoints            (watchpoints)
+  ) hw_debug (
+    
+    .clk_i                  (clk_i), 
+    .rst_i                  (rst_i),
+    .pc_x                   (pc_x),
+    .load_x                 (load_x),
+    .store_x                (store_x),
+    .load_store_address_x   (adder_result_x),
+    .csr_write_enable_x     (csr_write_enable_q_x),
+    .csr_write_data         (operand_1_x),
+    .csr_x                  (csr_x),
+   
+
+	        
+      
+        
+                   
+	      
+
+	        
+
+    .dbg_csr_write_enable_i  (dbg_csr_write_enable_i),
+    .dbg_csr_write_data_i    (dbg_csr_write_data_i),
+    .dbg_csr_addr_i               (dbg_csr_addr_i),
+	       
+
+ 
+
+  
+
+    .eret_q_x               (eret_q_x),
+    .bret_q_x               (bret_q_x),
+    .stall_x                (stall_x),
+    .exception_x            (exception_x),
+    .q_x                    (q_x),
+  
+      
+
+
+ 
+
+    
+  
+
+    .dc_ss                  (dc_ss),
+ 
+
+    .dc_re                  (dc_re),
+    .bp_match               (bp_match),
+    .wp_match               (wp_match)
+    );
+ 
+
+
+
+
+  
+
+   
+           
+            
+          
+            
+
+
+             
+              
+    
+
+   wire [31:0] regfile_data_0, regfile_data_1;
+   reg [31:0]  w_result_d;
+   reg 	       regfile_raw_0, regfile_raw_0_nxt;
+   reg 	       regfile_raw_1, regfile_raw_1_nxt;
+   
+   
+             
+          
+
+   always @(reg_write_enable_q_w or write_idx_w or instruction_f)
+     begin
+	if (reg_write_enable_q_w
+	    && (write_idx_w == instruction_f[25:21]))
+	  regfile_raw_0_nxt = 1'b1;
+	else
+	  regfile_raw_0_nxt = 1'b0;
+	
+	if (reg_write_enable_q_w
+	    && (write_idx_w == instruction_f[20:16]))
+	  regfile_raw_1_nxt = 1'b1;
+	else
+	  regfile_raw_1_nxt = 1'b0;
+     end
+   
+   
+           
+           
+       
+
+   always @(regfile_raw_0 or w_result_d or regfile_data_0)
+     if (regfile_raw_0)
+       reg_data_live_0 = w_result_d;
+     else
+       reg_data_live_0 = regfile_data_0;
+   
+   
+           
+           
+       
+
+   always @(regfile_raw_1 or w_result_d or regfile_data_1)
+     if (regfile_raw_1)
+       reg_data_live_1 = w_result_d;
+     else
+       reg_data_live_1 = regfile_data_1;
+   
+   
+     
+
+   always @(posedge clk_i  )
+     if (rst_i ==  1'b1)
+       begin
+	  regfile_raw_0 <= 1'b0;
+	  regfile_raw_1 <= 1'b0;
+	  w_result_d <= 32'b0;
+       end
+     else
+       begin
+	  regfile_raw_0 <= regfile_raw_0_nxt;
+	  regfile_raw_1 <= regfile_raw_1_nxt;
+	  w_result_d <= w_result;
+       end
+   
+   
+      
+
+   
+   lm32_dp_ram
+     #(
+       
+       .addr_depth(1<<5),
+       .addr_width(5),
+       .data_width(32)
+       )
+   reg_0
+     (
+      
+      .clk_i	(clk_i),
+      .rst_i	(rst_i), 
+      .we_i	(reg_write_enable_q_w),
+      .wdata_i	(w_result),
+      .waddr_i	(write_idx_w),
+      .raddr_i	(instruction_f[25:21]),
+      
+      .rdata_o	(regfile_data_0)
+      );
+
+   lm32_dp_ram
+     #(
+       .addr_depth(1<<5),
+       .addr_width(5),
+       .data_width(32)
+       )
+   reg_1
+     (
+      
+      .clk_i	(clk_i),
+      .rst_i	(rst_i), 
+      .we_i	(reg_write_enable_q_w),
+      .wdata_i	(w_result),
+      .waddr_i	(write_idx_w),
+      .raddr_i	(instruction_f[20:16]),
+      
+      .rdata_o	(regfile_data_1)
+      );
+ 
+
+
+  
+   
+     
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+   
+     
+      
+      
+      
+      
+      
+      
+      
+        
+      
+       
+      
+      
+      
+   
+   
+     
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+   
+     
+      
+      
+      
+      
+      
+      
+      
+        
+      
+       
+      
+      
+      
+
+
+
+
+
+
+
+
+  
+
+
+assign reg_data_0 = use_buf ? reg_data_buf_0 : reg_data_live_0;
+assign reg_data_1 = use_buf ? reg_data_buf_1 : reg_data_live_1;
+ 
+
+  
+
+ 
+
+   
+   
+
+
+
+
+assign raw_x_0 = (write_idx_x == read_idx_0_d) && (write_enable_q_x ==  1'b1);
+assign raw_m_0 = (write_idx_m == read_idx_0_d) && (write_enable_q_m ==  1'b1);
+assign raw_w_0 = (write_idx_w == read_idx_0_d) && (write_enable_q_w ==  1'b1);
+assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x ==  1'b1);
+assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m ==  1'b1);
+assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w ==  1'b1);
+
+
+always @(*)
+begin
+    if (   (   (x_bypass_enable_x ==  1'b0)
+            && (   ((read_enable_0_d ==  1'b1) && (raw_x_0 ==  1'b1))
+                || ((read_enable_1_d ==  1'b1) && (raw_x_1 ==  1'b1))
+               )
+           )
+        || (   (m_bypass_enable_m ==  1'b0)
+            && (   ((read_enable_0_d ==  1'b1) && (raw_m_0 ==  1'b1))
+                || ((read_enable_1_d ==  1'b1) && (raw_m_1 ==  1'b1))
+               )
+           )
+       )
+        interlock =  1'b1;
+    else
+        interlock =  1'b0;
+end
+
+
+always @(*)
+begin
+    if (raw_x_0 ==  1'b1)        
+        bypass_data_0 = x_result;
+    else if (raw_m_0 ==  1'b1)
+        bypass_data_0 = m_result;
+    else if (raw_w_0 ==  1'b1)
+        bypass_data_0 = w_result;
+    else
+        bypass_data_0 = reg_data_0;
+end
+
+
+always @(*)
+begin
+    if (raw_x_1 ==  1'b1)
+        bypass_data_1 = x_result;
+    else if (raw_m_1 ==  1'b1)
+        bypass_data_1 = m_result;
+    else if (raw_w_1 ==  1'b1)
+        bypass_data_1 = w_result;
+    else
+        bypass_data_1 = reg_data_1;
+end
+
+   
+          
+       
+       
+     
+
+   assign branch_predict_d = bi_unconditional | bi_conditional;
+   assign branch_predict_taken_d = bi_unconditional ? 1'b1 : (bi_conditional ? instruction_d[15] : 1'b0);
+   
+   
+   assign branch_target_d = pc_d + branch_offset_d;
+
+   
+   
+   
+   assign branch_predict_address_d = branch_predict_taken_d ? branch_target_d : pc_f;
+
+
+always @(*)
+begin
+    d_result_0 = d_result_sel_0_d[0] ? {pc_f, 2'b00} : bypass_data_0; 
+    case (d_result_sel_1_d)
+     2'b00:      d_result_1 = { 32{1'b0}};
+     2'b01:     d_result_1 = bypass_data_1;
+     2'b10: d_result_1 = immediate_d;
+    default:                        d_result_1 = { 32{1'bx}};
+    endcase
+end
+
+      
+
+   
+   
+
+
+
+  
+
+
+assign sextb_result_x = {{24{operand_0_x[7]}}, operand_0_x[7:0]};
+assign sexth_result_x = {{16{operand_0_x[15]}}, operand_0_x[15:0]};
+assign sext_result_x = size_x ==  2'b00 ? sextb_result_x : sexth_result_x;
+ 
+
+
+  
+
+      
+
+
+
+
+assign cmp_zero = operand_0_x == operand_1_x;
+assign cmp_negative = adder_result_x[ 32-1];
+assign cmp_overflow = adder_overflow_x;
+assign cmp_carry_n = adder_carry_n_x;
+always @(*)
+begin
+    case (condition_x)
+     3'b000:   condition_met_x =  1'b1;
+     3'b110:   condition_met_x =  1'b1;
+     3'b001:    condition_met_x = cmp_zero;
+     3'b111:   condition_met_x = !cmp_zero;
+     3'b010:    condition_met_x = !cmp_zero && (cmp_negative == cmp_overflow);
+     3'b101:   condition_met_x = cmp_carry_n && !cmp_zero;
+     3'b011:   condition_met_x = cmp_negative == cmp_overflow;
+     3'b100:  condition_met_x = cmp_carry_n;
+    default:              condition_met_x = 1'bx;
+    endcase 
+end
+
+
+always @(*)
+begin
+    x_result =   x_result_sel_add_x ? adder_result_x 
+               : x_result_sel_csr_x ? csr_read_data_x
+  
+
+               : x_result_sel_sext_x ? sext_result_x
+ 
+
+  
+                  
+
+
+  
+                  
+
+
+  
+
+               : x_result_sel_mc_arith_x ? mc_result_x
+ 
+
+               : logic_result_x;
+end
+
+
+always @(*)
+begin
+    m_result =   m_result_sel_compare_m ? {{ 32-1{1'b0}}, condition_met_m}
+  
+
+               : m_result_sel_shift_m ? shifter_result_m
+ 
+
+               : operand_m; 
+end
+
+
+always @(*)
+begin
+    w_result =    w_result_sel_load_w ? load_data_w
+  
+
+                : w_result_sel_mul_w ? multiplier_result_w
+ 
+
+                : operand_w;
+end
+
+      
+
+          
+                                
+                                     
+                                 
+                                 
+                              
+
+
+
+
+assign branch_taken_m =      (stall_m ==  1'b0) 
+                          && (   (   (branch_m ==  1'b1) 
+                                  && (valid_m ==  1'b1)
+                                  && (   (   (condition_met_m ==  1'b1)
+					  && (branch_predict_taken_m ==  1'b0)
+					 )
+				      || (   (condition_met_m ==  1'b0)
+					  && (branch_predict_m ==  1'b1)
+					  && (branch_predict_taken_m ==  1'b1)
+					 )
+				     )
+                                 ) 
+                              || (exception_m ==  1'b1)
+                             );
+
+
+assign branch_mispredict_taken_m =    (condition_met_m ==  1'b0)
+                                   && (branch_predict_m ==  1'b1)
+	   			   && (branch_predict_taken_m ==  1'b1);
+   
+
+assign branch_flushX_m =    (stall_m ==  1'b0)
+                         && (   (   (branch_m ==  1'b1) 
+                                 && (valid_m ==  1'b1)
+			         && (   (condition_met_m ==  1'b1)
+				     || (   (condition_met_m ==  1'b0)
+					 && (branch_predict_m ==  1'b1)
+					 && (branch_predict_taken_m ==  1'b1)
+					)
+				    )
+			        )
+			     || (exception_m ==  1'b1)
+			    );
+
+
+assign kill_f =    (   (valid_d ==  1'b1)
+                    && (branch_predict_taken_d ==  1'b1)
+		   )
+                || (branch_taken_m ==  1'b1) 
+      
+                   
+
+
+  
+                    
+
+
+                  
+                   
+
+
+                ;
+assign kill_d =    (branch_taken_m ==  1'b1) 
+      
+                   
+
+
+  
+                        
+
+                
+                  
+                   
+
+
+                ;
+assign kill_x =    (branch_flushX_m ==  1'b1) 
+                  
+                   
+
+
+                ;
+assign kill_m =     1'b0
+                  
+                   
+
+
+                ;                
+assign kill_w =     1'b0
+                  
+                   
+
+                
+                ;
+
+
+
+  
+
+assign breakpoint_exception =    (   (   (break_x ==  1'b1)
+				      || (bp_match ==  1'b1)
+				     )
+				  && (valid_x ==  1'b1)
+				 )
+  
+                                 
+
+
+                              ;
+ 
+
+
+  
+
+assign watchpoint_exception = wp_match ==  1'b1;
+ 
+
+
+  
+
+assign instruction_bus_error_exception = (   (bus_error_x ==  1'b1)
+                                          && (valid_x ==  1'b1)
+                                         );
+assign data_bus_error_exception = data_bus_error_seen ==  1'b1;
+ 
+
+
+  
+
+assign divide_by_zero_exception = divide_by_zero_x ==  1'b1;
+ 
+
+
+assign system_call_exception = (   (scall_x ==  1'b1)
+  
+
+                                && (valid_x ==  1'b1)
+ 
+
+			       );
+
+  
+
+assign debug_exception_x =  (breakpoint_exception ==  1'b1)
+                         || (watchpoint_exception ==  1'b1)
+                         ;
+
+assign non_debug_exception_x = (system_call_exception ==  1'b1)
+  
+                               
+
+
+  
+
+                            || (instruction_bus_error_exception ==  1'b1)
+                            || (data_bus_error_exception ==  1'b1)
+ 
+
+  
+
+                            || (divide_by_zero_exception ==  1'b1)
+ 
+
+  
+
+                            || (   (interrupt_exception ==  1'b1)
+  
+
+                                && (dc_ss ==  1'b0)
+ 
+                            
+  
+
+ 				&& (store_q_m ==  1'b0)
+				&& (D_CYC_O ==  1'b0)
+ 
+
+                               )
+ 
+
+                            ;
+
+assign exception_x = (debug_exception_x ==  1'b1) || (non_debug_exception_x ==  1'b1);
+ 
+               
+ 
+                               
+                               
+
+ 
+                               
+
+ 
+                                  
+ 
+                                   
+                            
+ 
+ 				   
+				   
+
+                               
+
+                            
+
+
+
+  
+
+reg user_stall;
+
+always@(posedge clk_i)
+  if(rst_i)
+    user_stall <= 0;
+  else if(!D_CYC_O)
+    user_stall <= ~enable_i;
+ 
+
+
+
+always @(*)
+begin
+  
+
+  
+       
+          
+    
+
+     
+  
+
+         if (data_bus_error_exception ==  1'b1)
+        eid_x =  3'h4;
+    else
+ 
+
+         if (breakpoint_exception ==  1'b1)
+        eid_x =  3'd1;
+    else
+ 
+
+  
+
+         if (data_bus_error_exception ==  1'b1)
+        eid_x =  3'h4;
+    else
+         if (instruction_bus_error_exception ==  1'b1)
+        eid_x =  3'h2;
+    else
+ 
+
+  
+
+         if (watchpoint_exception ==  1'b1)
+        eid_x =  3'd3;
+    else 
+ 
+
+  
+
+         if (divide_by_zero_exception ==  1'b1)
+        eid_x =  3'h5;
+    else
+ 
+
+  
+
+         if (   (interrupt_exception ==  1'b1)
+  
+
+             && (dc_ss ==  1'b0)
+ 
+                            
+            )
+        eid_x =  3'h6;
+    else
+ 
+
+        eid_x =  3'h7;
+end
+
+
+
+assign stall_a = (stall_f ==  1'b1);
+                
+assign stall_f = (stall_d ==  1'b1);
+                
+assign stall_d =   (stall_x ==  1'b1) 
+                || (   (interlock ==  1'b1)
+                    && (kill_d ==  1'b0)
+                   ) 
+		|| (   (   (eret_d ==  1'b1)
+			|| (scall_d ==  1'b1)
+  
+
+			|| (bus_error_d ==  1'b1)
+ 
+
+		       )
+		    && (   (load_q_x ==  1'b1)
+			|| (load_q_m ==  1'b1)
+			|| (store_q_x ==  1'b1)
+			|| (store_q_m ==  1'b1)
+			|| (D_CYC_O ==  1'b1)
+		       )
+                    && (kill_d ==  1'b0)
+		   )
+  
+
+		|| (   (   (break_d ==  1'b1)
+			|| (bret_d ==  1'b1)
+		       )
+		    && (   (load_q_x ==  1'b1)
+			|| (store_q_x ==  1'b1)
+			|| (load_q_m ==  1'b1)
+			|| (store_q_m ==  1'b1)
+			|| (D_CYC_O ==  1'b1)
+		       )
+                    && (kill_d ==  1'b0)
+		   )
+ 
+                   
+                || (   (csr_write_enable_d ==  1'b1)
+                    && (load_q_x ==  1'b1)
+                   )                      
+  
+
+                 
+                 
+                 || (   (iram_stall_request_x ==  1'b1)
+		     && (   (load_d ==  1'b1)
+			 
+			)
+		    )
+ 
+	
+                ;
+                
+assign stall_x =    (stall_m ==  1'b1)
+  
+
+                 || (   (mc_stall_request_x ==  1'b1)
+                     && (kill_x ==  1'b0)
+                    ) 
+ 
+
+
+	    
+                 ;
+
+assign stall_m =    (stall_wb_load ==  1'b1)
+  
+                    
+
+
+                 || (   (D_CYC_O ==  1'b1)
+                     && (   (store_m ==  1'b1)
+		         
+          
+          
+
+		  
+	 
+	
+
+          
+           
+          
+       
+
+  
+
+		         || ((store_x ==  1'b1) && (interrupt_exception ==  1'b1))
+ 
+
+                         || (load_m ==  1'b1)
+                         || (load_x ==  1'b1)
+                        ) 
+                    ) 
+ 
+                 
+  
+                         
+
+                                    
+  
+                         
+                             
+
+
+  
+                                
+
+
+ 
+                               
+  
+                                  
+                        
+                    
+
+
+  
+
+                 || (user_stall)
+    
+
+                 ;      
+
+
+
+
+  
+
+assign q_d = (valid_d ==  1'b1) && (kill_d ==  1'b0);
+ 
+
+  
+         
+         
+
+
+  
+         
+
+
+  
+
+assign divide_q_d = (divide_d ==  1'b1) && (q_d ==  1'b1);
+assign modulus_q_d = (modulus_d ==  1'b1) && (q_d ==  1'b1);
+ 
+
+assign q_x = (valid_x ==  1'b1) && (kill_x ==  1'b0);
+assign csr_write_enable_q_x = (csr_write_enable_x ==  1'b1) && (q_x ==  1'b1);
+assign eret_q_x = (eret_x ==  1'b1) && (q_x ==  1'b1);
+  
+
+assign bret_q_x = (bret_x ==  1'b1) && (q_x ==  1'b1);
+ 
+
+assign load_q_x = (load_x ==  1'b1) 
+               && (q_x ==  1'b1)
+  
+
+               && (bp_match ==  1'b0)
+ 
+
+                  ;
+assign store_q_x = (store_x ==  1'b1) 
+               && (q_x ==  1'b1)
+  
+
+               && (bp_match ==  1'b0)
+ 
+
+                  ;
+  
+         
+
+                              
+assign q_m = (valid_m ==  1'b1) && (kill_m ==  1'b0) && (exception_m ==  1'b0);
+assign load_q_m = (load_m ==  1'b1) && (q_m ==  1'b1);
+assign store_q_m = (store_m ==  1'b1) && (q_m ==  1'b1);
+  
+
+assign debug_exception_q_w = ((debug_exception_w ==  1'b1) && (valid_w ==  1'b1));
+assign non_debug_exception_q_w = ((non_debug_exception_w ==  1'b1) && (valid_w ==  1'b1));        
+ 
+                 
+
+
+
+assign write_enable_q_x = (write_enable_x ==  1'b1) && (valid_x ==  1'b1) && (branch_flushX_m ==  1'b0);
+assign write_enable_q_m = (write_enable_m ==  1'b1) && (valid_m ==  1'b1);
+assign write_enable_q_w = (write_enable_w ==  1'b1) && (valid_w ==  1'b1);
+
+assign reg_write_enable_q_w = (write_enable_w ==  1'b1) && (kill_w ==  1'b0) && (valid_w ==  1'b1);
+
+
+assign cfg = {
+               6'h02,
+              watchpoints[3:0],
+              breakpoints[3:0],
+              interrupts[5:0],
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+ 
+               1'b1
+ 
+              
+
+
+              };
+
+assign cfg2 = {
+		     30'b0,
+  
+
+		      1'b1,
+ 
+		     
+
+
+  
+		     
+
+
+		      1'b0
+ 
+
+		     };
+   
+
+  
+         
+                    
+                    
+                    
+                    
+
+ 
+             
+                     
+		    
+
+		 
+
+ 
+  
+         
+                      
+
+ 
+               
+                       
+		      
+
+		   
+
+ 
+
+
+assign csr_d = read_idx_0_d[ (5-1):0];
+
+
+always @(*)
+begin
+    case (csr_x)
+  
+
+     5'h0,
+     5'h1,
+     5'h2:   csr_read_data_x = interrupt_csr_read_data_x;  
+ 
+
+  
+         
+
+
+     5'h6:  csr_read_data_x = cfg;
+     5'h7:  csr_read_data_x = {eba, 8'h00};
+  
+
+     5'h9: csr_read_data_x = {deba, 8'h00};
+ 
+
+  
+          
+        
+
+
+     5'ha: csr_read_data_x = cfg2;
+     5'hb:  csr_read_data_x = sdb_address;
+  
+
+     5'hc:  csr_read_data_x = data_bus_error_addr;
+ 
+
+      
+      
+    default:        csr_read_data_x = { 32{1'bx}};
+    endcase
+end
+
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        eba <= eba_reset[ (32-2)+2-1:8];
+    else
+    begin
+        if ((csr_write_enable_q_x ==  1'b1) && (csr_x ==  5'h7) && (stall_x ==  1'b0))
+            eba <= operand_1_x[ (32-2)+2-1:8];
+  
+
+   
+              
+           
+ 
+
+   
+
+       if ((dbg_csr_write_enable_i ==  1'b1) && (dbg_csr_addr_i ==  5'h7))
+         eba <= dbg_csr_write_data_i[ (32-2)+2-1:8];
+  
+	 
+ 
+
+    end
+end
+
+  
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        deba <= deba_reset[ (32-2)+2-1:8];
+    else
+    begin
+        if ((csr_write_enable_q_x ==  1'b1) && (csr_x ==  5'h9) && (stall_x ==  1'b0))
+            deba <= operand_1_x[ (32-2)+2-1:8];
+   
+
+    
+              
+           
+  
+
+    
+
+       if ((dbg_csr_write_enable_i ==  1'b1) && (dbg_csr_addr_i ==  5'h9))
+         deba <= dbg_csr_write_data_i[ (32-2)+2-1:8];
+   
+       
+  
+
+    end
+end
+ 
+
+
+
+  
+   
+
+       
+          
+    
+            
+
+
+
+
+  
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        data_bus_error_seen <=  1'b0;
+    else
+    begin
+        
+        if ((D_ERR_I ==  1'b1) && (D_CYC_O ==  1'b1)) begin
+           data_bus_error_seen <=  1'b1;
+	   data_bus_error_addr <= D_ADR_O;
+	end
+        
+        if ((exception_m ==  1'b1) && (kill_m ==  1'b0))
+            data_bus_error_seen <=  1'b0;
+    end
+end
+ 
+
+ 
+
+
+  
+ 
+ 
+
+           
+           
+       
+          
+            
+                 
+             
+          
+     
+            
+ 
+
+ 
+
+        
+          
+         
+          
+     
+          
+ 
+
+
+
+  
+ 
+
+        
+          
+         
+          
+     
+          
+ 
+
+
+ 
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        valid_f <=  1'b0;
+        valid_d <=  1'b0;
+        valid_x <=  1'b0;
+        valid_m <=  1'b0;
+        valid_w <=  1'b0;
+    end
+    else
+    begin    
+        if ((kill_f ==  1'b1) || (stall_a ==  1'b0))
+  
+                  
+
+
+            valid_f <=  1'b1;
+ 
+            
+        else if (stall_f ==  1'b0)
+            valid_f <=  1'b0;            
+
+        if (kill_d ==  1'b1)
+            valid_d <=  1'b0;
+        else if (stall_f ==  1'b0)
+            valid_d <= valid_f & !kill_f;
+        else if (stall_d ==  1'b0)
+            valid_d <=  1'b0;
+       
+        if (stall_d ==  1'b0)
+            valid_x <= valid_d & !kill_d;
+        else if (kill_x ==  1'b1)
+            valid_x <=  1'b0;
+        else if (stall_x ==  1'b0)
+            valid_x <=  1'b0;
+
+        if (kill_m ==  1'b1)
+            valid_m <=  1'b0;
+        else if (stall_x ==  1'b0)
+            valid_m <= valid_x & !kill_x;
+        else if (stall_m ==  1'b0)
+            valid_m <=  1'b0;
+
+        if (stall_m ==  1'b0)
+            valid_w <= valid_m & !kill_m;
+        else 
+            valid_w <=  1'b0;        
+    end
+end
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+  
+                 
+
+        
+        operand_0_x <= { 32{1'b0}};
+        operand_1_x <= { 32{1'b0}};
+        store_operand_x <= { 32{1'b0}};
+        branch_target_x <= { (32-2){1'b0}};        
+        x_result_sel_csr_x <=  1'b0;
+  
+
+        x_result_sel_mc_arith_x <=  1'b0;
+ 
+
+      
+          
+
+
+  
+
+        x_result_sel_sext_x <=  1'b0;
+ 
+    
+  
+          
+
+
+        x_result_sel_add_x <=  1'b0;
+        m_result_sel_compare_x <=  1'b0;
+  
+
+        m_result_sel_shift_x <=  1'b0;
+ 
+    
+        w_result_sel_load_x <=  1'b0;
+  
+
+        w_result_sel_mul_x <=  1'b0;
+ 
+
+        x_bypass_enable_x <=  1'b0;
+        m_bypass_enable_x <=  1'b0;
+        write_enable_x <=  1'b0;
+        write_idx_x <= { 5{1'b0}};
+        csr_x <= { 5{1'b0}};
+        load_x <=  1'b0;
+        store_x <=  1'b0;
+        size_x <= { 2{1'b0}};
+        sign_extend_x <=  1'b0;
+        adder_op_x <=  1'b0;
+        adder_op_x_n <=  1'b0;
+        logic_op_x <= 4'h0;
+  
+
+        direction_x <=  1'b0;
+ 
+
+  
+          
+
+
+
+        branch_x <=  1'b0;
+        branch_predict_x <=  1'b0;
+        branch_predict_taken_x <=  1'b0;
+        condition_x <=  3'b000;
+  
+
+        break_x <=  1'b0;
+ 
+
+        scall_x <=  1'b0;
+        eret_x <=  1'b0;
+  
+
+        bret_x <=  1'b0;
+ 
+
+  
+
+        bus_error_x <=  1'b0;
+        data_bus_error_exception_m <=  1'b0;
+ 
+
+        csr_write_enable_x <=  1'b0;
+        operand_m <= { 32{1'b0}};
+        branch_target_m <= { (32-2){1'b0}};
+        m_result_sel_compare_m <=  1'b0;
+  
+
+        m_result_sel_shift_m <=  1'b0;
+ 
+    
+        w_result_sel_load_m <=  1'b0;
+  
+
+        w_result_sel_mul_m <=  1'b0;
+ 
+
+        m_bypass_enable_m <=  1'b0;
+        branch_m <=  1'b0;
+        branch_predict_m <=  1'b0;
+	branch_predict_taken_m <=  1'b0;
+        exception_m <=  1'b0;
+        load_m <=  1'b0;
+        store_m <=  1'b0;
+        write_enable_m <=  1'b0;            
+        write_idx_m <= { 5{1'b0}};
+        condition_met_m <=  1'b0;
+  
+          
+
+
+  
+
+        debug_exception_m <=  1'b0;
+        non_debug_exception_m <=  1'b0;        
+ 
+
+        operand_w <= { 32{1'b0}};        
+        w_result_sel_load_w <=  1'b0;
+  
+
+        w_result_sel_mul_w <=  1'b0;
+ 
+
+        write_idx_w <= { 5{1'b0}};        
+        write_enable_w <=  1'b0;
+  
+
+        debug_exception_w <=  1'b0;
+        non_debug_exception_w <=  1'b0;        
+ 
+          
+
+
+  
+
+        memop_pc_w <= { (32-2){1'b0}};
+ 
+
+    end
+    else
+    begin
+        
+       
+        if (stall_x ==  1'b0)
+        begin
+  
+                     
+
+        
+            operand_0_x <= d_result_0;
+            operand_1_x <= d_result_1;
+            store_operand_x <= bypass_data_1;
+            branch_target_x <= branch_reg_d ==  1'b1 ? bypass_data_0[ ((32-2)+2-1):2] : branch_target_d;            
+            x_result_sel_csr_x <= x_result_sel_csr_d;
+  
+
+            x_result_sel_mc_arith_x <= x_result_sel_mc_arith_d;
+ 
+
+      
+              
+
+
+  
+
+            x_result_sel_sext_x <= x_result_sel_sext_d;
+ 
+    
+  
+              
+
+
+            x_result_sel_add_x <= x_result_sel_add_d;
+            m_result_sel_compare_x <= m_result_sel_compare_d;
+  
+
+            m_result_sel_shift_x <= m_result_sel_shift_d;
+ 
+    
+            w_result_sel_load_x <= w_result_sel_load_d;
+  
+
+            w_result_sel_mul_x <= w_result_sel_mul_d;
+ 
+
+            x_bypass_enable_x <= x_bypass_enable_d;
+            m_bypass_enable_x <= m_bypass_enable_d;
+            load_x <= load_d;
+            store_x <= store_d;
+            branch_x <= branch_d;
+	    branch_predict_x <= branch_predict_d;
+	    branch_predict_taken_x <= branch_predict_taken_d;
+	    write_idx_x <= write_idx_d;
+            csr_x <= csr_d;
+            size_x <= size_d;
+            sign_extend_x <= sign_extend_d;
+            adder_op_x <= adder_op_d;
+            adder_op_x_n <= ~adder_op_d;
+            logic_op_x <= logic_op_d;
+  
+
+            direction_x <= direction_d;
+ 
+
+  
+              
+
+
+            condition_x <= condition_d;
+            csr_write_enable_x <= csr_write_enable_d;
+  
+
+            break_x <= break_d;
+ 
+
+            scall_x <= scall_d;
+  
+
+            bus_error_x <= bus_error_d;
+ 
+
+            eret_x <= eret_d;
+  
+
+            bret_x <= bret_d; 
+ 
+
+            write_enable_x <= write_enable_d;
+        end
+        
+        
+
+        if (stall_m ==  1'b0)
+        begin
+            operand_m <= x_result;
+            m_result_sel_compare_m <= m_result_sel_compare_x;
+  
+
+            m_result_sel_shift_m <= m_result_sel_shift_x;
+ 
+    
+            if (exception_x ==  1'b1)
+            begin
+                w_result_sel_load_m <=  1'b0;
+  
+
+                w_result_sel_mul_m <=  1'b0;
+ 
+
+            end
+            else
+            begin
+                w_result_sel_load_m <= w_result_sel_load_x;
+  
+
+                w_result_sel_mul_m <= w_result_sel_mul_x;
+ 
+
+            end
+            m_bypass_enable_m <= m_bypass_enable_x;
+            load_m <= load_x;
+            store_m <= store_x;
+      
+                
+
+
+            branch_m <= branch_x;
+	    branch_predict_m <= branch_predict_x;
+	    branch_predict_taken_m <= branch_predict_taken_x;
+ 
+
+  
+
+	   
+	   
+	   
+	   
+	   
+            if (non_debug_exception_x ==  1'b1) 
+                write_idx_m <=  5'd30;
+            else if (debug_exception_x ==  1'b1)
+                write_idx_m <=  5'd31;
+            else 
+                write_idx_m <= write_idx_x;
+ 
+               
+                  
+             
+                  
+
+
+            condition_met_m <= condition_met_x;
+  
+
+	   if (exception_x ==  1'b1)
+	     if ((dc_re ==  1'b1)
+		 || ((debug_exception_x ==  1'b1) 
+		     && (non_debug_exception_x ==  1'b0)))
+	       branch_target_m <= {deba, eid_x, {3{1'b0}}};
+	     else
+	       branch_target_m <= {eba, eid_x, {3{1'b0}}};
+	   else
+	     branch_target_m <= branch_target_x;
+ 
+                      
+
+
+  
+              
+              
+
+
+  
+              
+
+
+  
+ 
+               
+
+
+
+            write_enable_m <= exception_x ==  1'b1 ?  1'b1 : write_enable_x;            
+  
+
+            debug_exception_m <= debug_exception_x;
+            non_debug_exception_m <= non_debug_exception_x;        
+ 
+
+        end
+        
+        
+        if (stall_m ==  1'b0)
+        begin
+            if ((exception_x ==  1'b1) && (q_x ==  1'b1) && (stall_x ==  1'b0))
+                exception_m <=  1'b1;
+            else 
+                exception_m <=  1'b0;
+  
+
+	   data_bus_error_exception_m <=    (data_bus_error_exception ==  1'b1) 
+  
+
+					 && (reset_exception ==  1'b0)
+ 
+
+					 ;
+ 
+
+	end
+                
+        
+  
+
+        operand_w <= exception_m ==  1'b1 ? (data_bus_error_exception_m ? {memop_pc_w, 2'b00} : {pc_m, 2'b00}) : m_result;
+ 
+                 
+
+
+        w_result_sel_load_w <= w_result_sel_load_m;
+  
+
+        w_result_sel_mul_w <= w_result_sel_mul_m;
+ 
+
+        write_idx_w <= write_idx_m;
+  
+          
+          
+ 
+           
+
+
+
+        write_enable_w <= write_enable_m;
+  
+
+        debug_exception_w <= debug_exception_m;
+        non_debug_exception_w <= non_debug_exception_m;
+ 
+          
+
+
+  
+
+        if (   (stall_m ==  1'b0)
+            && (   (load_q_m ==  1'b1) 
+                || (store_q_m ==  1'b1)
+               )
+	   )
+          memop_pc_w <= pc_m;
+ 
+
+    end
+end
+
+  
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        use_buf <=  1'b0;
+        reg_data_buf_0 <= { 32{1'b0}};
+        reg_data_buf_1 <= { 32{1'b0}};
+    end
+    else
+    begin
+        if (stall_d ==  1'b0)
+            use_buf <=  1'b0;
+        else if (use_buf ==  1'b0)
+        begin        
+            reg_data_buf_0 <= reg_data_live_0;
+            reg_data_buf_1 <= reg_data_live_1;
+            use_buf <=  1'b1;
+        end        
+        if (reg_write_enable_q_w ==  1'b1)
+        begin
+            if (write_idx_w == read_idx_0_d)
+                reg_data_buf_0 <= w_result;
+            if (write_idx_w == read_idx_1_d)
+                reg_data_buf_1 <= w_result;
+        end
+    end
+end
+ 
+
+
+  
+
+ 
+
+   
+
+        
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+        
+     
+           
+            
+        
+
+
+
+
+  
+
+   
+
+       
+    
+          
+          
+          
+          
+          
+ 
+          
+
+          
+    
+    
+    
+          
+        
+ 
+               
+
+           
+
+                
+              
+              
+              
+              
+        
+        
+              
+        
+             
+        
+            
+                 
+            
+                
+                  
+                  
+            
+            
+              
+            
+              
+ 
+              
+
+        
+        
+        
+              
+ 
+              
+
+        
+    
+
+
+
+      
+
+
+
+
+
+        
+endmodule 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_load_store_unit_wr_node 
+(
+    
+    clk_i,
+    rst_i,
+ 
+    stall_a,
+    stall_x,
+    stall_m,
+    kill_x,
+    kill_m,
+    exception_m,
+    store_operand_x,
+    load_store_address_x,
+    load_store_address_m,
+    load_store_address_w,
+    load_x,
+    store_x,
+    load_q_x,
+    store_q_x,
+    load_q_m,
+    store_q_m,
+    sign_extend_x,
+    size_x,
+  
+    
+
+
+    
+    d_dat_i,
+    d_ack_i,
+    d_err_i,
+    d_rty_i,
+    
+    
+  
+    
+    
+    
+    
+
+    
+  
+
+    iram_d_adr_o,
+    iram_d_dat_o,
+    iram_d_dat_i,
+    iram_d_sel_o,
+    iram_d_we_o,
+    iram_d_en_o,
+    iram_stall_request_x,
+ 
+			     
+    load_data_w,
+    stall_wb_load,
+    
+    d_dat_o,
+    d_adr_o,
+    d_cyc_o,
+    d_sel_o,
+    d_stb_o,
+    d_we_o,
+    d_cti_o,
+    d_lock_o,
+    d_bte_o
+    );
+
+
+
+
+
+parameter associativity = 1;                            
+parameter sets = 512;                                   
+parameter bytes_per_line = 16;                          
+parameter base_address = 0;                             
+parameter limit = 0;                                    
+
+
+localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
+localparam addr_offset_lsb = 2;
+localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
+
+
+
+
+
+   input clk_i;                                            
+   
+input rst_i;                                            
+
+input stall_a;                                          
+input stall_x;                                          
+input stall_m;                                          
+input kill_x;                                           
+input kill_m;                                           
+input exception_m;                                      
+
+input [ (32-1):0] store_operand_x;                 
+input [ (32-1):0] load_store_address_x;            
+input [ (32-1):0] load_store_address_m;            
+input [1:0] load_store_address_w;                       
+input load_x;                                           
+input store_x;                                          
+input load_q_x;                                         
+input store_q_x;                                        
+input load_q_m;                                         
+input store_q_m;                                        
+input sign_extend_x;                                    
+input [ 1:0] size_x;                          
+
+  
+                                            
+
+
+
+  
+   
+   output [31:0] iram_d_adr_o;
+   output [31:0] iram_d_dat_o;
+   input [31:0]  iram_d_dat_i;
+   output [3:0]  iram_d_sel_o;
+   output        iram_d_en_o, iram_d_we_o;
+   output 	 iram_stall_request_x;
+   
+ 
+
+
+   reg 		 [31:0] iram_dat_d0;
+   reg 		 iram_en_d0;
+   wire 	 iram_en;
+   wire [31:0] 	 iram_data;
+   
+   
+   
+input [ (32-1):0] d_dat_i;                         
+input d_ack_i;                                          
+input d_err_i;                                          
+input d_rty_i;                                          
+
+
+
+
+
+  
+                            
+   
+                           
+   
+                             
+   
+ 
+   
+
+
+
+   
+output [ (32-1):0] load_data_w;                    
+reg    [ (32-1):0] load_data_w;
+output stall_wb_load;                                   
+reg    stall_wb_load;
+
+output [ (32-1):0] d_dat_o;                        
+reg    [ (32-1):0] d_dat_o;
+output [ (32-1):0] d_adr_o;                        
+reg    [ (32-1):0] d_adr_o;
+output d_cyc_o;                                         
+reg    d_cyc_o;
+output [ (4-1):0] d_sel_o;                 
+reg    [ (4-1):0] d_sel_o;
+output d_stb_o;                                         
+reg    d_stb_o; 
+output d_we_o;                                          
+reg    d_we_o;
+output [ (3-1):0] d_cti_o;                       
+reg    [ (3-1):0] d_cti_o;
+output d_lock_o;                                        
+reg    d_lock_o;
+output [ (2-1):0] d_bte_o;                       
+wire   [ (2-1):0] d_bte_o;
+
+
+
+
+
+
+reg [ 1:0] size_m;
+reg [ 1:0] size_w;
+reg sign_extend_m;
+reg sign_extend_w;
+reg [ (32-1):0] store_data_x;       
+reg [ (32-1):0] store_data_m;       
+reg [ (4-1):0] byte_enable_x;
+reg [ (4-1):0] byte_enable_m;
+wire [ (32-1):0] data_m;
+reg [ (32-1):0] data_w;
+
+   
+
+  
+                                    
+ 
+                      
+              
+                                 
+                  
+                   
+                                          
+                      
+
+
+  
+                                      
+ 
+                                      
+                    
+                      
+                        
+                  
+
+
+wire wb_select_x;                                       
+  
+
+wire iram_select_x;                                     
+
+reg  iram_enable_m;
+   reg iram_select_m;
+   reg iram_d_en_d0;
+   
+
+ 
+
+reg wb_select_m;
+reg [ (32-1):0] wb_data_m;                         
+reg wb_load_complete;                                   
+   
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+  
+
+ 
+              
+                       
+             
+               
+                      
+       
+    
+                      
+                            
+                    
+                    
+                    
+                  
+                  
+                     
+                    
+                 
+            
+               
+                
+                     
+    
+              
+            
+             
+             
+                  
+                  
+    
+
+
+
+
+
+
+
+
+  
+            
+                             
+
+
+
+  
+
+   assign iram_select_x =    (load_store_address_x >=  0) 
+                          && (load_store_address_x <=  32'h000fffff);
+
+   assign iram_d_sel_o = byte_enable_m;
+   assign iram_en = !stall_x || !stall_m;
+
+   always@(posedge clk_i)
+     iram_en_d0 <= iram_en;
+
+  
+
+ 
+
+  
+
+  
+
+
+       
+   
+   
+   
+ 
+
+   
+  
+            
+                               
+ 
+                               
+
+ 
+                               
+
+                     
+
+
+	  
+   assign wb_select_x =     1'b1
+  
+                          
+
+
+  
+                         
+
+
+  
+
+                        && !iram_select_x
+ 
+
+                     ;
+
+
+always @(*)
+begin
+    case (size_x)
+     2'b00:  store_data_x = {4{store_operand_x[7:0]}};
+     2'b11: store_data_x = {2{store_operand_x[15:0]}};
+     2'b10:  store_data_x = store_operand_x;    
+    default:          store_data_x = { 32{1'bx}};
+    endcase
+end
+
+
+always @(*)
+begin
+    casez ({size_x, load_store_address_x[1:0]})
+    { 2'b00, 2'b11}:  byte_enable_x = 4'b0001;
+    { 2'b00, 2'b10}:  byte_enable_x = 4'b0010;
+    { 2'b00, 2'b01}:  byte_enable_x = 4'b0100;
+    { 2'b00, 2'b00}:  byte_enable_x = 4'b1000;
+    { 2'b11, 2'b1?}: byte_enable_x = 4'b0011;
+    { 2'b11, 2'b0?}: byte_enable_x = 4'b1100;
+    { 2'b10, 2'b??}:  byte_enable_x = 4'b1111;
+    default:                   byte_enable_x = 4'bxxxx;
+    endcase
+end
+
+  
+
+   assign iram_d_dat_o = store_data_m;
+   assign iram_d_adr_o = (iram_enable_m && store_q_m) ? load_store_address_m : load_store_address_x;
+
+   assign iram_stall_request_x =    (iram_select_x ==  1'b1)
+	                         && (store_q_x ==  1'b1);
+   
+   
+   assign iram_d_we_o =    (iram_enable_m ==  1'b1) && (store_q_m ==  1'b1);
+   assign iram_d_en_o = !stall_m || !stall_x;
+ 
+
+   
+  
+  
+   
+   
+         
+                    
+                       
+                      
+                        
+                     
+                        
+  
+   
+         
+                    
+                       
+                      
+                      
+  
+ 
+   
+   
+         
+                    
+                       
+                      
+                      
+  
+   
+         
+                     
+                    
+  
+ 
+
+
+   
+   
+   
+         
+                     
+                      
+                      
+                      
+  
+   
+         
+                     
+                    
+  
+ 
+
+    
+
+   
+   assign data_m = wb_select_m ==  1'b1 
+                   ? wb_data_m 
+                   : iram_d_dat_i;
+
+   
+   
+      
+  
+
+  
+
+ 
+
+
+
+always @(*)
+begin
+    casez ({size_w, load_store_address_w[1:0]})
+    { 2'b00, 2'b11}:  load_data_w = {{24{sign_extend_w & data_w[7]}}, data_w[7:0]};
+    { 2'b00, 2'b10}:  load_data_w = {{24{sign_extend_w & data_w[15]}}, data_w[15:8]};
+    { 2'b00, 2'b01}:  load_data_w = {{24{sign_extend_w & data_w[23]}}, data_w[23:16]};
+    { 2'b00, 2'b00}:  load_data_w = {{24{sign_extend_w & data_w[31]}}, data_w[31:24]};
+    { 2'b11, 2'b1?}: load_data_w = {{16{sign_extend_w & data_w[15]}}, data_w[15:0]};
+    { 2'b11, 2'b0?}: load_data_w = {{16{sign_extend_w & data_w[31]}}, data_w[31:16]};
+    { 2'b10, 2'b??}:  load_data_w = data_w;
+    default:                   load_data_w = { 32{1'bx}};
+    endcase
+end
+
+
+assign d_bte_o =  2'b00;
+
+                  
+
+ 
+     
+    
+    
+   
+   
+   
+    
+    
+    
+    
+   
+   
+     
+     
+    
+    
+    
+   
+         
+     
+     
+    
+    
+
+
+
+
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        d_cyc_o <=  1'b0;
+        d_stb_o <=  1'b0;
+        d_dat_o <= { 32{1'b0}};
+        d_adr_o <= { 32{1'b0}};
+        d_sel_o <= { 4{ 1'b0}};
+        d_we_o <=  1'b0;
+        d_cti_o <=  3'b111;
+        d_lock_o <=  1'b0;
+        wb_data_m <= { 32{1'b0}};
+        wb_load_complete <=  1'b0;
+        stall_wb_load <=  1'b0;
+                  
+          
+
+                
+    end
+    else 
+    begin
+   
+        
+          
+
+                
+        
+        if (d_cyc_o ==  1'b1)
+        begin
+            
+            if ((d_ack_i ==  1'b1) || (d_err_i ==  1'b1))
+            begin
+                  
+                     
+                
+                    
+                        
+                
+                
+
+                
+                begin
+                    
+                    d_cyc_o <=  1'b0;
+                    d_stb_o <=  1'b0;
+                    d_lock_o <=  1'b0;
+                end
+      
+                  
+                
+                  
+
+
+                
+                wb_data_m <= d_dat_i;
+                
+                wb_load_complete <= !d_we_o;
+            end
+            
+        end
+        else 
+        begin
+                  
+               
+            
+                
+                  
+                  
+                  
+                                  
+                  
+                  
+                
+            
+             
+
+            
+                 if (   (store_q_m ==  1'b1)
+                     && (stall_m ==  1'b0)
+  
+                        
+
+
+  
+
+		     && (iram_enable_m ==  1'b0)
+ 
+			
+                    )
+            begin
+                
+                d_dat_o <= store_data_m;
+                d_adr_o <= load_store_address_m;
+                d_cyc_o <=  1'b1;
+                d_sel_o <= byte_enable_m;
+                d_stb_o <=  1'b1;
+                d_we_o <=  1'b1;
+                d_cti_o <=  3'b111;
+            end        
+            else if (   (load_q_m ==  1'b1) 
+                     && (wb_select_m ==  1'b1) 
+                     && (wb_load_complete ==  1'b0)
+                     
+                    )
+            begin
+                
+                stall_wb_load <=  1'b0;
+                d_adr_o <= load_store_address_m;
+                d_cyc_o <=  1'b1;
+                d_sel_o <= byte_enable_m;
+                d_stb_o <=  1'b1;
+                d_we_o <=  1'b0;
+                d_cti_o <=  3'b111;
+            end
+        end
+        
+        if (stall_m ==  1'b0)
+            wb_load_complete <=  1'b0;
+        
+        if ((load_q_x ==  1'b1) && (wb_select_x ==  1'b1) && (stall_x ==  1'b0))
+            stall_wb_load <=  1'b1;
+        
+        if ((kill_m ==  1'b1) || (exception_m ==  1'b1))
+            stall_wb_load <=  1'b0;
+    end
+end
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        sign_extend_m <=  1'b0;
+        size_m <= 2'b00;
+        byte_enable_m <=  1'b0;
+        store_data_m <= { 32{1'b0}};
+  
+          
+
+
+  
+          
+
+
+  
+
+        iram_enable_m <=  1'b0;
+			  iram_select_m <=  1'b0;
+ 
+
+        wb_select_m <=  1'b0;        
+    end
+    else
+    begin
+        if (stall_m ==  1'b0)
+        begin
+            sign_extend_m <= sign_extend_x;
+            size_m <= size_x;
+            byte_enable_m <= byte_enable_x;    
+            store_data_m <= store_data_x;
+  
+              
+
+
+  
+              
+
+
+  
+
+            iram_enable_m <= iram_select_x;
+			  iram_select_m <= iram_select_x;
+ 
+
+            wb_select_m <= wb_select_x;
+        end
+    end
+end
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        size_w <= 2'b00;
+        data_w <= { 32{1'b0}};
+        sign_extend_w <=  1'b0;
+    end
+    else
+    begin
+        size_w <= size_m;
+
+  
+
+       if(!iram_select_m || iram_en_d0)
+ 
+
+        data_w <= data_m;
+
+        sign_extend_w <= sign_extend_m;
+    end
+end
+
+
+
+
+
+
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
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+ 
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+ 
+ 
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+ 
+ 
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+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_decoder_wr_node (
+    
+    instruction,
+    
+    d_result_sel_0,
+    d_result_sel_1,        
+    x_result_sel_csr,
+  
+
+    x_result_sel_mc_arith,
+ 
+    
+      
+    
+
+
+  
+
+    x_result_sel_sext,
+ 
+    
+    x_result_sel_logic,
+  
+    
+
+
+    x_result_sel_add,
+    m_result_sel_compare,
+  
+
+    m_result_sel_shift,  
+ 
+    
+    w_result_sel_load,
+  
+
+    w_result_sel_mul,
+ 
+
+    x_bypass_enable,
+    m_bypass_enable,
+    read_enable_0,
+    read_idx_0,
+    read_enable_1,
+    read_idx_1,
+    write_enable,
+    write_idx,
+    immediate,
+    branch_offset,
+    load,
+    store,
+    size,
+    sign_extend,
+    adder_op,
+    logic_op,
+  
+
+    direction,
+ 
+
+  
+    
+    
+
+
+  
+    
+
+
+  
+
+    divide,
+    modulus,
+ 
+
+    branch,
+    branch_reg,
+    condition,
+    bi_conditional,
+    bi_unconditional,
+  
+
+    break_opcode,
+ 
+
+    scall,
+    eret,
+  
+
+    bret,
+ 
+
+  
+    
+
+
+    csr_write_enable
+    );
+
+
+
+
+
+input [ (32-1):0] instruction;       
+
+
+
+
+
+output [ 0:0] d_result_sel_0;
+reg    [ 0:0] d_result_sel_0;
+output [ 1:0] d_result_sel_1;
+reg    [ 1:0] d_result_sel_1;
+output x_result_sel_csr;
+reg    x_result_sel_csr;
+  
+
+output x_result_sel_mc_arith;
+reg    x_result_sel_mc_arith;
+ 
+
+      
+ 
+    
+
+
+  
+
+output x_result_sel_sext;
+reg    x_result_sel_sext;
+ 
+
+output x_result_sel_logic;
+reg    x_result_sel_logic;
+  
+ 
+    
+
+
+output x_result_sel_add;
+reg    x_result_sel_add;
+output m_result_sel_compare;
+reg    m_result_sel_compare;
+  
+
+output m_result_sel_shift;
+reg    m_result_sel_shift;
+ 
+
+output w_result_sel_load;
+reg    w_result_sel_load;
+  
+
+output w_result_sel_mul;
+reg    w_result_sel_mul;
+ 
+
+output x_bypass_enable;
+wire   x_bypass_enable;
+output m_bypass_enable;
+wire   m_bypass_enable;
+output read_enable_0;
+wire   read_enable_0;
+output [ (5-1):0] read_idx_0;
+wire   [ (5-1):0] read_idx_0;
+output read_enable_1;
+wire   read_enable_1;
+output [ (5-1):0] read_idx_1;
+wire   [ (5-1):0] read_idx_1;
+output write_enable;
+wire   write_enable;
+output [ (5-1):0] write_idx;
+wire   [ (5-1):0] write_idx;
+output [ (32-1):0] immediate;
+wire   [ (32-1):0] immediate;
+output [ ((32-2)+2-1):2] branch_offset;
+wire   [ ((32-2)+2-1):2] branch_offset;
+output load;
+wire   load;
+output store;
+wire   store;
+output [ 1:0] size;
+wire   [ 1:0] size;
+output sign_extend;
+wire   sign_extend;
+output adder_op;
+wire   adder_op;
+output [ 3:0] logic_op;
+wire   [ 3:0] logic_op;
+  
+
+output direction;
+wire   direction;
+ 
+
+  
+ 
+   
+ 
+   
+
+
+  
+ 
+   
+
+
+  
+
+output divide;
+wire   divide;
+output modulus;
+wire   modulus;
+ 
+
+output branch;
+wire   branch;
+output branch_reg;
+wire   branch_reg;
+output [ (3-1):0] condition;
+wire   [ (3-1):0] condition;
+output bi_conditional;
+wire bi_conditional;
+output bi_unconditional;
+wire bi_unconditional;
+  
+
+output break_opcode;
+wire   break_opcode;
+ 
+
+output scall;
+wire   scall;
+output eret;
+wire   eret;
+  
+
+output bret;
+wire   bret;
+ 
+
+  
+  
+    
+
+
+output csr_write_enable;
+wire   csr_write_enable;
+
+
+
+
+
+wire [ (32-1):0] extended_immediate;       
+wire [ (32-1):0] high_immediate;           
+wire [ (32-1):0] call_immediate;           
+wire [ (32-1):0] branch_immediate;         
+wire sign_extend_immediate;                     
+wire select_high_immediate;                     
+wire select_call_immediate;                     
+
+wire op_add;
+wire op_and;
+wire op_andhi;
+wire op_b;
+wire op_bi;
+wire op_be;
+wire op_bg;
+wire op_bge;
+wire op_bgeu;
+wire op_bgu;
+wire op_bne;
+wire op_call;
+wire op_calli;
+wire op_cmpe;
+wire op_cmpg;
+wire op_cmpge;
+wire op_cmpgeu;
+wire op_cmpgu;
+wire op_cmpne;
+  
+
+wire op_divu;
+ 
+
+wire op_lb;
+wire op_lbu;
+wire op_lh;
+wire op_lhu;
+wire op_lw;
+  
+
+wire op_modu;
+ 
+
+  
+
+wire op_mul;
+ 
+
+wire op_nor;
+wire op_or;
+wire op_orhi;
+wire op_raise;
+wire op_rcsr;
+wire op_sb;
+  
+
+wire op_sextb;
+wire op_sexth;
+ 
+
+wire op_sh;
+  
+
+wire op_sl;
+ 
+
+wire op_sr;
+wire op_sru;
+wire op_sub;
+wire op_sw;
+  
+ 
+
+
+wire op_wcsr;
+wire op_xnor;
+wire op_xor;
+
+wire arith;
+wire logical;
+wire cmp;
+wire bra;
+wire call;
+  
+
+wire shift;
+ 
+
+  
+ 
+
+
+  
+
+wire sext;
+ 
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+assign op_add    = instruction[ 30:26] ==  5'b01101;
+assign op_and    = instruction[ 30:26] ==  5'b01000;
+assign op_andhi  = instruction[ 31:26] ==  6'b011000;
+assign op_b      = instruction[ 31:26] ==  6'b110000;
+assign op_bi     = instruction[ 31:26] ==  6'b111000;
+assign op_be     = instruction[ 31:26] ==  6'b010001;
+assign op_bg     = instruction[ 31:26] ==  6'b010010;
+assign op_bge    = instruction[ 31:26] ==  6'b010011;
+assign op_bgeu   = instruction[ 31:26] ==  6'b010100;
+assign op_bgu    = instruction[ 31:26] ==  6'b010101;
+assign op_bne    = instruction[ 31:26] ==  6'b010111;
+assign op_call   = instruction[ 31:26] ==  6'b110110;
+assign op_calli  = instruction[ 31:26] ==  6'b111110;
+assign op_cmpe   = instruction[ 30:26] ==  5'b11001;
+assign op_cmpg   = instruction[ 30:26] ==  5'b11010;
+assign op_cmpge  = instruction[ 30:26] ==  5'b11011;
+assign op_cmpgeu = instruction[ 30:26] ==  5'b11100;
+assign op_cmpgu  = instruction[ 30:26] ==  5'b11101;
+assign op_cmpne  = instruction[ 30:26] ==  5'b11111;
+  
+
+assign op_divu   = instruction[ 31:26] ==  6'b100011;
+ 
+
+assign op_lb     = instruction[ 31:26] ==  6'b000100;
+assign op_lbu    = instruction[ 31:26] ==  6'b010000;
+assign op_lh     = instruction[ 31:26] ==  6'b000111;
+assign op_lhu    = instruction[ 31:26] ==  6'b001011;
+assign op_lw     = instruction[ 31:26] ==  6'b001010;
+  
+
+assign op_modu   = instruction[ 31:26] ==  6'b110001;
+ 
+
+  
+
+assign op_mul    = instruction[ 30:26] ==  5'b00010;
+ 
+
+assign op_nor    = instruction[ 30:26] ==  5'b00001;
+assign op_or     = instruction[ 30:26] ==  5'b01110;
+assign op_orhi   = instruction[ 31:26] ==  6'b011110;
+assign op_raise  = instruction[ 31:26] ==  6'b101011;
+assign op_rcsr   = instruction[ 31:26] ==  6'b100100;
+assign op_sb     = instruction[ 31:26] ==  6'b001100;
+  
+
+assign op_sextb  = instruction[ 31:26] ==  6'b101100;
+assign op_sexth  = instruction[ 31:26] ==  6'b110111;
+ 
+
+assign op_sh     = instruction[ 31:26] ==  6'b000011;
+  
+
+assign op_sl     = instruction[ 30:26] ==  5'b01111;      
+ 
+
+assign op_sr     = instruction[ 30:26] ==  5'b00101;
+assign op_sru    = instruction[ 30:26] ==  5'b00000;
+assign op_sub    = instruction[ 31:26] ==  6'b110010;
+assign op_sw     = instruction[ 31:26] ==  6'b010110;
+  
+       
+
+
+assign op_wcsr   = instruction[ 31:26] ==  6'b110100;
+assign op_xnor   = instruction[ 30:26] ==  5'b01001;
+assign op_xor    = instruction[ 30:26] ==  5'b00110;
+
+
+assign arith = op_add | op_sub;
+assign logical = op_and | op_andhi | op_nor | op_or | op_orhi | op_xor | op_xnor;
+assign cmp = op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne;
+assign bi_conditional = op_be | op_bg | op_bge | op_bgeu  | op_bgu | op_bne;
+assign bi_unconditional = op_bi;
+assign bra = op_b | bi_unconditional | bi_conditional;
+assign call = op_call | op_calli;
+  
+
+assign shift = op_sl | op_sr | op_sru;
+ 
+
+  
+     
+
+
+  
+   
+     
+
+
+  
+
+assign sext = op_sextb | op_sexth;
+ 
+
+  
+   
+
+
+  
+
+assign divide = op_divu; 
+assign modulus = op_modu;
+ 
+
+assign load = op_lb | op_lbu | op_lh | op_lhu | op_lw;
+assign store = op_sb | op_sh | op_sw;
+
+
+always @(*)
+begin
+    
+    if (call) 
+        d_result_sel_0 =  1'b1;
+    else 
+        d_result_sel_0 =  1'b0;
+    if (call) 
+        d_result_sel_1 =  2'b00;         
+    else if ((instruction[31] == 1'b0) && !bra) 
+        d_result_sel_1 =  2'b10;
+    else
+        d_result_sel_1 =  2'b01; 
+    
+    x_result_sel_csr =  1'b0;
+  
+
+    x_result_sel_mc_arith =  1'b0;
+ 
+
+  
+      
+
+
+  
+
+    x_result_sel_sext =  1'b0;
+ 
+
+    x_result_sel_logic =  1'b0;
+          
+      
+
+
+    x_result_sel_add =  1'b0;
+    if (op_rcsr)
+        x_result_sel_csr =  1'b1;
+  
+    
+  
+         
+          
+
+
+  
+
+    else if (divide | modulus)
+        x_result_sel_mc_arith =  1'b1;        
+ 
+
+  
+      
+                      
+
+
+ 
+
+  
+      
+                  
+
+
+  
+
+    else if (sext)
+        x_result_sel_sext =  1'b1;
+ 
+        
+    else if (logical) 
+        x_result_sel_logic =  1'b1;
+          
+      
+          
+
+
+    else 
+        x_result_sel_add =  1'b1;        
+    
+    
+
+    m_result_sel_compare = cmp;
+  
+
+    m_result_sel_shift = shift;
+ 
+
+
+    
+    w_result_sel_load = load;
+  
+
+    w_result_sel_mul = op_mul; 
+ 
+
+end
+
+
+assign x_bypass_enable =  arith 
+                        | logical
+  
+                         
+                         
+
+                        
+  
+                         
+
+
+  
+
+                        | divide
+                        | modulus
+ 
+
+  
+                         
+
+                  
+  
+
+                        | sext 
+ 
+                        
+  
+                         
+
+
+                        | op_rcsr
+                        ;
+
+assign m_bypass_enable = x_bypass_enable 
+  
+
+                        | shift
+ 
+
+                        | cmp
+                        ;
+
+assign read_enable_0 = ~(op_bi | op_calli);
+assign read_idx_0 = instruction[25:21];
+
+assign read_enable_1 = ~(op_bi | op_calli | load);
+assign read_idx_1 = instruction[20:16];
+
+assign write_enable = ~(bra | op_raise | store | op_wcsr);
+assign write_idx = call
+                    ? 5'd29
+                    : instruction[31] == 1'b0 
+                        ? instruction[20:16] 
+                        : instruction[15:11];
+                        
+
+assign size = instruction[27:26];
+
+assign sign_extend = instruction[28];                      
+
+assign adder_op = op_sub | op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne | bra;
+
+assign logic_op = instruction[29:26];
+  
+
+
+assign direction = instruction[29];
+ 
+
+
+assign branch = bra | call;
+assign branch_reg = op_call | op_b;
+assign condition = instruction[28:26];      
+  
+
+assign break_opcode = op_raise & ~instruction[2];
+ 
+
+assign scall = op_raise & instruction[2];
+assign eret = op_b & (instruction[25:21] == 5'd30);
+  
+
+assign bret = op_b & (instruction[25:21] == 5'd31);
+ 
+
+  
+
+   
+
+
+
+assign csr_write_enable = op_wcsr;
+
+
+
+assign sign_extend_immediate = ~(op_and | op_cmpgeu | op_cmpgu | op_nor | op_or | op_xnor | op_xor);
+assign select_high_immediate = op_andhi | op_orhi;
+assign select_call_immediate = instruction[31];
+
+assign high_immediate = {instruction[15:0], 16'h0000};
+assign extended_immediate = {{16{sign_extend_immediate & instruction[15]}}, instruction[15:0]};
+assign call_immediate = {{6{instruction[25]}}, instruction[25:0]};
+assign branch_immediate = {{16{instruction[15]}}, instruction[15:0]};
+
+assign immediate = select_high_immediate ==  1'b1 
+                        ? high_immediate 
+                        : extended_immediate;
+   
+assign branch_offset = select_call_immediate ==  1'b1   
+                        ? (call_immediate[ (32-2)-1:0])
+                        : (branch_immediate[ (32-2)-1:0]);
+    
+endmodule 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
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+   
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+        
+            
+   
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+           
+    
+            
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+    
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+          
+     
+          
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+   
+
+       
+    
+          
+          
+          
+          
+          
+    
+     
+    
+         
+
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+        
+        
+               
+                  
+                
+        
+        
+        
+        
+        
+               
+                  
+               
+            
+                  
+                  
+                  
+            
+                
+                  
+        
+
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+        
+        
+              
+               
+            
+                   
+                
+                      
+                      
+                
+            
+        
+        
+                
+    
+
+
+
+       
+    
+
+   
+
+       
+          
+     
+    
+         
+        
+        
+        
+        
+               
+                  
+        
+
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+        
+               
+                    
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+                    
+                 
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+           
+             
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+               
+                 
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+                      
+                      
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+ 
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+  
+                    
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+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
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+                    
+                   
+                  
+                   
+          
+
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+ 
+                   
+                     
+
+ 
+                   
+                     
+
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+                     
+
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+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
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+ 
+
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+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_debug_wr_node (
+    
+    clk_i, 
+    rst_i,
+    pc_x,
+    load_x,
+    store_x,
+    load_store_address_x,
+    csr_write_enable_x,
+    csr_write_data,
+    csr_x,
+  
+
+  
+    
+    
+    
+
+
+  
+
+   dbg_csr_write_enable_i,
+   dbg_csr_write_data_i,
+   dbg_csr_addr_i,
+ 
+
+  
+
+
+		   
+  
+
+    eret_q_x,
+    bret_q_x,
+    stall_x,
+    exception_x,
+    q_x,
+  
+    
+
+
+ 
+
+
+    
+  
+
+    dc_ss,
+ 
+
+    dc_re,
+    bp_match,
+    wp_match
+    );
+    
+
+
+
+
+parameter breakpoints = 0;                      
+parameter watchpoints = 0;                      
+
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+
+input [ ((32-2)+2-1):2] pc_x;                      
+input load_x;                                   
+input store_x;                                  
+input [ (32-1):0] load_store_address_x;    
+input csr_write_enable_x;                       
+input [ (32-1):0] csr_write_data;          
+input [ (5-1):0] csr_x;                    
+  
+
+  
+                     
+       
+                   
+
+
+     
+
+input dbg_csr_write_enable_i;                         
+input [ (32-1):0] dbg_csr_write_data_i;          
+input [ (5-1):0] dbg_csr_addr_i;                        
+ 
+
+ 
+
+
+
+  
+
+input eret_q_x;                                 
+input bret_q_x;                                 
+input stall_x;                                  
+input exception_x;                              
+input q_x;                                      
+  
+                     
+
+
+ 
+
+
+
+
+
+
+  
+
+output dc_ss;                                   
+reg    dc_ss;
+ 
+
+output dc_re;                                   
+reg    dc_re;
+output bp_match;                                
+wire   bp_match;        
+output wp_match;                                
+wire   wp_match;
+
+
+
+
+
+genvar i;                                       
+
+
+
+reg [ ((32-2)+2-1):2] bp_a[0:breakpoints-1];       
+reg bp_e[0:breakpoints-1];                      
+wire [0:breakpoints-1]bp_match_n;               
+
+reg [ 1:0] wpc_c[0:watchpoints-1];   
+reg [ (32-1):0] wp[0:watchpoints-1];       
+wire [0:watchpoints-1]wp_match_n;               
+
+wire debug_csr_write_enable;                    
+wire [ (32-1):0] debug_csr_write_data;     
+wire [ (5-1):0] debug_csr;                 
+
+  
+
+
+reg [ 2:0] state;           
+
+ 
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+generate
+    for (i = 0; i < breakpoints; i = i + 1)
+    begin : bp_comb
+assign bp_match_n[i] = ((bp_a[i] == pc_x) && (bp_e[i] ==  1'b1));
+    end
+endgenerate
+generate 
+  
+
+    if (breakpoints > 0) 
+assign bp_match = (|bp_match_n) || (state ==  3'b011);
+    else
+assign bp_match = state ==  3'b011;
+ 
+        
+   
+    
+   
+
+
+endgenerate    
+               
+
+generate 
+    for (i = 0; i < watchpoints; i = i + 1)
+    begin : wp_comb
+assign wp_match_n[i] = (wp[i] == load_store_address_x) && ((load_x & wpc_c[i][0]) | (store_x & wpc_c[i][1]));
+    end               
+endgenerate
+generate
+    if (watchpoints > 0) 
+assign wp_match = |wp_match_n;                
+    else
+assign wp_match =  1'b0;
+endgenerate
+                
+  
+                
+
+  
+         
+         
+         
+
+
+   
+  
+
+assign debug_csr_write_enable = (csr_write_enable_x ==  1'b1) || (dbg_csr_write_enable_i ==  1'b1);
+assign debug_csr_write_data = dbg_csr_write_data_i ==  1'b1 ? dbg_csr_write_data_i : csr_write_data;
+assign debug_csr = dbg_csr_write_enable_i ==  1'b1 ? dbg_csr_addr_i : csr_x;
+
+ 
+
+   
+ 
+   
+   
+   
+
+
+
+
+
+
+
+
+generate
+    for (i = 0; i < breakpoints; i = i + 1)
+    begin : bp_seq
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        bp_a[i] <= { (32-2){1'bx}};
+        bp_e[i] <=  1'b0;
+    end
+    else
+    begin
+        if ((debug_csr_write_enable ==  1'b1) && (debug_csr ==  5'h10 + i))
+        begin
+            bp_a[i] <= debug_csr_write_data[ ((32-2)+2-1):2];
+            bp_e[i] <= debug_csr_write_data[0];
+        end
+    end
+end    
+    end
+endgenerate
+
+
+generate
+    for (i = 0; i < watchpoints; i = i + 1)
+    begin : wp_seq
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        wp[i] <= { 32{1'bx}};
+        wpc_c[i] <=  2'b00;
+    end
+    else
+    begin
+        if (debug_csr_write_enable ==  1'b1)
+        begin
+            if (debug_csr ==  5'h8)
+                wpc_c[i] <= debug_csr_write_data[3+i*2:2+i*2];
+            if (debug_csr ==  5'h18 + i)
+                wp[i] <= debug_csr_write_data;
+        end
+    end  
+end
+    end
+endgenerate
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        dc_re <=  1'b0;
+    else
+    begin
+        if ((debug_csr_write_enable ==  1'b1) && (debug_csr ==  5'h8))
+            dc_re <= debug_csr_write_data[1];
+    end
+end    
+
+  
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        state <=  3'b000;
+        dc_ss <=  1'b0;
+    end
+    else
+    begin
+        if ((debug_csr_write_enable ==  1'b1) && (debug_csr ==  5'h8))
+        begin
+            dc_ss <= debug_csr_write_data[0];
+            if (debug_csr_write_data[0] ==  1'b0) 
+                state <=  3'b000;
+            else 
+                state <=  3'b001;
+        end
+        case (state)
+         3'b001:
+        begin
+            
+            if (   (   (eret_q_x ==  1'b1)
+                    || (bret_q_x ==  1'b1)
+                    )
+                && (stall_x ==  1'b0)
+               )
+                state <=  3'b010; 
+        end
+         3'b010:
+        begin
+            
+            if ((q_x ==  1'b1) && (stall_x ==  1'b0))
+                state <=  3'b011;
+        end
+         3'b011:
+        begin
+            
+  
+               
+                  
+             
+
+
+                 if ((exception_x ==  1'b1) && (q_x ==  1'b1) && (stall_x ==  1'b0))
+            begin
+                dc_ss <=  1'b0;
+                state <=  3'b100;
+            end
+        end
+         3'b100:
+        begin
+            
+  
+               
+                  
+             
+
+
+                state <=  3'b000;
+        end
+        endcase
+    end
+end
+ 
+
+
+endmodule
+
+ 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_instruction_unit_wr_node (
+    
+    clk_i,
+    rst_i,
+    
+    stall_a,
+    stall_f,
+    stall_d,
+    stall_x,
+    stall_m,
+    valid_f,
+    valid_d,
+    kill_f,
+    branch_predict_taken_d,
+    branch_predict_address_d,
+      
+    
+    
+
+
+    exception_m,
+    branch_taken_m,
+    branch_mispredict_taken_m,
+    branch_target_m,
+  
+    
+
+
+  
+    
+    
+    
+
+        
+  
+    
+    
+    
+    
+    
+
+
+  
+
+    jtag_read_enable,
+    jtag_write_enable,
+    jtag_write_data,
+    jtag_address,
+ 
+
+    
+    
+    pc_f,
+    pc_d,
+    pc_x,
+    pc_m,
+    pc_w,
+  
+    
+    
+    
+    
+
+
+  
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+
+
+  
+
+    iram_i_adr_o,
+    iram_i_dat_i,
+    iram_i_en_o,
+ 
+
+  
+
+    jtag_read_data,
+    jtag_access_complete,
+ 
+
+  
+
+    bus_error_d,
+ 
+
+  
+
+    instruction_f,
+ 
+    
+    instruction_d
+    );
+
+
+
+
+
+parameter eba_reset =  32'h00000000;                   
+parameter associativity = 1;                            
+parameter sets = 512;                                   
+parameter bytes_per_line = 16;                          
+parameter base_address = 0;                             
+parameter limit = 0;                                    
+
+
+localparam eba_reset_minus_4 = eba_reset - 4;
+localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
+localparam addr_offset_lsb = 2;
+localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
+
+
+
+
+  
+
+output [31:0] iram_i_adr_o;
+input [31:0]  iram_i_dat_i;
+   output     iram_i_en_o;
+   
+ 
+
+
+input clk_i;                                            
+input rst_i;                                            
+
+input stall_a;                                          
+input stall_f;                                          
+input stall_d;                                          
+input stall_x;                                          
+input stall_m;                                          
+input valid_f;                                          
+input valid_d;                                          
+input kill_f;                                           
+
+input branch_predict_taken_d;                           
+input [ ((32-2)+2-1):2] branch_predict_address_d;          
+   
+      
+                                    
+                     
+
+
+input exception_m;
+input branch_taken_m;                                   
+input branch_mispredict_taken_m;                        
+input [ ((32-2)+2-1):2] branch_target_m;                   
+
+  
+                                            
+
+
+  
+                            
+                             
+ 
+
+        
+
+
+  
+                           
+                                           
+                                           
+                                           
+
+
+
+  
+
+input jtag_read_enable;                                 
+input jtag_write_enable;                                
+input [ 7:0] jtag_write_data;                 
+input [ (32-1):0] jtag_address;                    
+ 
+
+
+
+
+
+        
+output [ ((32-2)+2-1):2] pc_f;                             
+reg    [ ((32-2)+2-1):2] pc_f;
+output [ ((32-2)+2-1):2] pc_d;                             
+reg    [ ((32-2)+2-1):2] pc_d;
+output [ ((32-2)+2-1):2] pc_x;                             
+reg    [ ((32-2)+2-1):2] pc_x;
+output [ ((32-2)+2-1):2] pc_m;                             
+reg    [ ((32-2)+2-1):2] pc_m;
+output [ ((32-2)+2-1):2] pc_w;                             
+reg    [ ((32-2)+2-1):2] pc_w;
+
+  
+                             
+   
+                           
+   
+                            
+   
+                                 
+   
+
+
+
+  
+                          
+ 
+     
+
+    
+
+                          
+     
+                                          
+     
+                   
+ 
+     
+
+    
+
+                                          
+    
+                                           
+ 
+    
+
+   
+
+                         
+     
+                                         
+    
+                         
+    
+
+
+
+  
+
+output [ 7:0] jtag_read_data;                 
+reg    [ 7:0] jtag_read_data;
+output jtag_access_complete;                            
+wire   jtag_access_complete;
+ 
+
+
+  
+
+output bus_error_d;                                     
+reg    bus_error_d;
+ 
+
+  
+
+output [ (32-1):0] instruction_f;           
+wire   [ (32-1):0] instruction_f;
+ 
+
+output [ (32-1):0] instruction_d;           
+reg    [ (32-1):0] instruction_d;
+
+
+
+
+
+reg [ ((32-2)+2-1):2] pc_a;                                
+
+  
+                       
+
+
+
+  
+                               
+                
+                                 
+           
+               
+                  
+                   
+                                          
+                        
+
+
+  
+                    
+
+
+ 
+
+  
+
+wire iram_select_a;                                     
+   reg 			     iram_select_f;
+   
+ 
+
+  
+
+ 
+               
+
+
+
+  
+ 
+   
+   
+    			               
+ 
+
+ 
+
+  
+
+   wire 		     bus_error_f = 0;
+ 
+
+   
+  
+
+reg jtag_access;                                        
+ 
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+  
+
+ 
+              
+                       
+             
+               
+                      
+       
+    
+                      
+                            
+                    
+                    
+     
+                    
+                  
+                  
+              
+               
+                
+                     
+    
+              
+            
+             
+             
+                  
+                       
+    
+
+
+
+
+
+
+
+  
+   
+           
+        
+  
+      
+                          
+   
+				       
+        
+				    
+
+ 
+
+
+always @(*)
+begin
+    
+  
+       
+          
+     
+
+    
+      if (branch_taken_m ==  1'b1)
+	if ((branch_mispredict_taken_m ==  1'b1) && (exception_m ==  1'b0))
+	  pc_a = pc_x;
+	else
+          pc_a = branch_target_m;
+      
+          
+          
+
+
+      else
+	if ( (valid_d ==  1'b1) && (branch_predict_taken_d ==  1'b1) )
+	  pc_a = branch_predict_address_d;
+	else
+  
+             
+              
+	   
+
+        
+            pc_a = pc_f + 1'b1;
+end
+
+
+  
+
+   assign iram_select_a = 1'b1;
+   assign iram_i_en_o = !stall_a;
+   assign iram_i_adr_o = {pc_a, 2'b00}; 
+ 
+
+
+  
+
+
+   reg [31:0] prev_instruction_f;
+   reg 	      iram_i_en_d0;
+
+   always@(posedge clk_i) 
+     if(rst_i) begin
+	iram_i_en_d0 <= 0;
+     end else begin
+	iram_i_en_d0 <= !stall_a;
+	if(iram_i_en_d0)
+	  prev_instruction_f <= iram_i_dat_i;
+     end
+   
+   
+   assign instruction_f = (!iram_i_en_d0) ? prev_instruction_f : iram_i_dat_i;
+
+
+  
+   
+ 
+                     
+
+ 
+   
+
+   
+
+
+
+ 
+   
+
+  
+ 
+
+   
+   
+   
+
+   
+
+
+
+  
+
+
+     
+    
+    
+   
+   
+   
+   
+    
+    
+    
+   
+   
+     
+    
+    
+    
+    
+   
+         
+     
+    
+    
+    
+
+
+
+                     
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        pc_f <= eba_reset_minus_4[ ((32-2)+2-1):2];
+        pc_d <= { (32-2){1'b0}};
+        pc_x <= { (32-2){1'b0}};
+        pc_m <= { (32-2){1'b0}};
+        pc_w <= { (32-2){1'b0}};
+    end
+    else
+    begin
+        if (stall_f ==  1'b0)
+            pc_f <= pc_a;
+        if (stall_d ==  1'b0)
+            pc_d <= pc_f;
+        if (stall_x ==  1'b0)
+            pc_x <= pc_d;
+        if (stall_m ==  1'b0)
+            pc_m <= pc_x;
+        pc_w <= pc_m;
+    end
+end
+
+  
+
+   
+
+       
+          
+    
+    
+ 
+         
+            
+               
+                  
+                    
+                  
+
+               
+                  
+
+
+         
+               
+                  
+
+
+    
+
+
+
+
+
+  
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        iram_select_f <=  1'b0;
+    else
+    begin
+        if (stall_f ==  1'b0)
+            iram_select_f <= iram_select_a;
+    end
+end
+ 
+
+
+  
+
+     
+                 
+ 
+
+     
+       
+       
+       
+       
+     
+
+   
+
+ 
+
+
+  
+   
+                  
+      
+     
+	   
+	  
+               
+               
+               
+               
+               
+               
+               
+   
+               
+  
+   
+               
+               
+               
+  
+	  
+	
+	     
+               
+             
+                
+               
+		  
+		         
+		    
+   
+                          
+			 
+			      
+			             
+			        
+			          
+			 
+                       
+  
+			 
+			       
+			      
+				 
+				   
+				   
+				   
+			      
+			    
+			        
+			      
+			    
+			      
+			      
+			 
+		    
+   
+		   
+		     
+		    
+                         
+                         
+		    
+		  
+  
+               
+             
+               
+		         
+		    
+                       
+        
+                         
+  
+                          
+                         
+                                         
+                         
+                       
+   
+                         
+  
+		    
+   
+		  
+		    
+                              
+			 
+			     
+			         
+			         
+			         
+			         
+			    
+			      
+			      
+			      
+			      
+			      
+			      
+			      
+			 
+		     
+                      
+   
+		  
+		  
+        
+		     
+                      
+   
+		     
+                      
+  
+               
+	  
+     
+ 
+      
+     
+	   
+	  
+               
+               
+               
+               
+               
+               
+   
+               
+  
+	  
+	
+	     
+             
+                
+               
+		  
+		        
+		    
+                       
+                         
+                         
+                       
+                         
+		    
+   
+		   
+		     
+		    
+                         
+                         
+		       
+		    
+		  
+  
+               
+             
+               
+		  
+		         
+    
+			    
+         
+			 
+		    
+                       
+        
+                         
+  
+                          
+                         
+                         
+   
+                         
+  
+		    
+		  
+		    
+	                      
+    
+			         
+         
+			      
+			 
+   
+			      
+  
+			 
+		    
+               
+	  
+     
+ 
+
+ 
+
+   
+   always @(posedge clk_i  )
+     begin
+	if (rst_i ==  1'b1)
+	  begin
+             instruction_d <= { 32{1'b0}};
+  
+
+             bus_error_d <=  1'b0;
+ 
+
+	  end
+	else
+	  begin
+             if (stall_d ==  1'b0)
+               begin
+		  instruction_d <= instruction_f;
+  
+
+		  bus_error_d <= bus_error_f;
+ 
+
+               end
+	  end
+     end  
+   
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
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+                    
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+                    
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+                  
+         
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+          
+          
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+          
+      
+      
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+ 
+                    
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+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
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+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
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+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_interrupt_wr_node (
+    
+    clk_i, 
+    rst_i,
+    
+    interrupt,
+    
+    stall_x,
+  
+
+    non_debug_exception,
+    debug_exception,
+ 
+    
+
+
+    eret_q_x,
+  
+
+    bret_q_x,
+ 
+
+    csr,
+    csr_write_data,
+    csr_write_enable,
+    
+    interrupt_exception,
+    
+    csr_read_data
+    );
+
+
+
+
+
+parameter interrupts =  32;         
+
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+
+input [interrupts-1:0] interrupt;               
+
+input stall_x;                                  
+
+  
+
+input non_debug_exception;                      
+input debug_exception;                          
+ 
+                                 
+
+
+input eret_q_x;                                 
+  
+
+input bret_q_x;                                 
+ 
+
+
+input [ (5-1):0] csr;                      
+input [ (32-1):0] csr_write_data;          
+input csr_write_enable;                         
+
+
+
+
+
+output interrupt_exception;                     
+wire   interrupt_exception;
+
+output [ (32-1):0] csr_read_data;          
+reg    [ (32-1):0] csr_read_data;
+
+
+
+
+
+wire [interrupts-1:0] asserted;                 
+
+wire [interrupts-1:0] interrupt_n_exception;
+
+
+
+reg ie;                                         
+reg eie;                                        
+  
+
+reg bie;                                        
+ 
+
+reg [interrupts-1:0] ip;                        
+reg [interrupts-1:0] im;                        
+
+
+
+
+
+
+assign interrupt_n_exception = ip & im;
+
+
+assign interrupt_exception = (|interrupt_n_exception) & ie;
+
+
+assign asserted = ip | interrupt;
+       
+generate
+    if (interrupts > 1) 
+    begin
+
+always @(*)
+begin
+    case (csr)
+     5'h0:  csr_read_data = {{ 32-3{1'b0}}, 
+  
+
+                                    bie,
+ 
+                                                                         
+
+
+                                    eie, 
+                                    ie
+                                   };
+     5'h2:  csr_read_data = ip;
+     5'h1:  csr_read_data = im;
+    default:       csr_read_data = { 32{1'bx}};
+    endcase
+end
+    end
+    else
+    begin
+
+always @(*)
+begin
+    case (csr)
+     5'h0:  csr_read_data = {{ 32-3{1'b0}}, 
+  
+
+                                    bie, 
+ 
+                                                                        
+
+
+                                    eie, 
+                                    ie
+                                   };
+     5'h2:  csr_read_data = ip;
+    default:       csr_read_data = { 32{1'bx}};
+      endcase
+end
+    end
+endgenerate
+    
+
+
+
+
+  
+
+   reg [ 10:0] eie_delay  = 0;
+
+   
+generate
+
+   
+    if (interrupts > 1)
+    begin
+
+always @(posedge clk_i  )
+  begin
+    if (rst_i ==  1'b1)
+    begin
+        ie                   <=  1'b0;
+        eie                  <=  1'b0;
+  
+
+        bie                  <=  1'b0;
+ 
+
+        im                   <= {interrupts{1'b0}};
+        ip                   <= {interrupts{1'b0}};
+       eie_delay             <= 0;
+       
+    end
+    else
+    begin
+        
+        ip                   <= asserted;
+  
+
+        if (non_debug_exception ==  1'b1)
+        begin
+            
+            eie              <= ie;
+            ie               <=  1'b0;
+        end
+        else if (debug_exception ==  1'b1)
+        begin
+            
+            bie              <= ie;
+            ie               <=  1'b0;
+        end
+ 
+           
+        
+            
+                           
+                            
+        
+
+
+        else if (stall_x ==  1'b0)
+        begin
+
+           if(eie_delay[0])
+             ie              <= eie;
+           
+           eie_delay         <= {1'b0, eie_delay[ 10:1]};
+
+            if (eret_q_x ==  1'b1) begin
+                
+               eie_delay[ 10] <=  1'b1;
+               eie_delay[ 10-1:0] <= 0;
+            end
+           
+                      
+           
+  
+
+            else if (bret_q_x ==  1'b1)
+                
+                ie      <= bie;
+ 
+
+            else if (csr_write_enable ==  1'b1)
+            begin
+                
+                if (csr ==  5'h0)
+                begin
+                    ie  <= csr_write_data[0];
+                    eie <= csr_write_data[1];
+  
+
+                    bie <= csr_write_data[2];
+ 
+
+                end
+                if (csr ==  5'h1)
+                    im  <= csr_write_data[interrupts-1:0];
+                if (csr ==  5'h2)
+                    ip  <= asserted & ~csr_write_data[interrupts-1:0];
+            end
+        end
+    end
+end
+    end
+else
+    begin
+
+always @(posedge clk_i  )
+  begin
+    if (rst_i ==  1'b1)
+    begin
+        ie              <=  1'b0;
+        eie             <=  1'b0;
+  
+
+        bie             <=  1'b0;
+ 
+
+        ip              <= {interrupts{1'b0}};
+       eie_delay        <= 0;
+    end
+    else
+    begin
+        
+        ip              <= asserted;
+  
+
+        if (non_debug_exception ==  1'b1)
+        begin
+            
+            eie         <= ie;
+            ie          <=  1'b0;
+        end
+        else if (debug_exception ==  1'b1)
+        begin
+            
+            bie         <= ie;
+            ie          <=  1'b0;
+        end
+ 
+           
+        
+            
+                      
+                       
+        
+
+
+        else if (stall_x ==  1'b0)
+          begin
+
+             if(eie_delay[0])
+               ie              <= eie;
+           
+             eie_delay         <= {1'b0, eie_delay[ 10:1]};
+
+             if (eret_q_x ==  1'b1) begin
+                
+                eie_delay[ 10] <=  1'b1;
+                eie_delay[ 10-1:0] <= 0;
+             end
+           
+  
+
+            else if (bret_q_x ==  1'b1)
+                
+                ie      <= bie;
+ 
+
+            else if (csr_write_enable ==  1'b1)
+            begin
+                
+                if (csr ==  5'h0)
+                begin
+                    ie  <= csr_write_data[0];
+                    eie <= csr_write_data[1];
+  
+
+                    bie <= csr_write_data[2];
+ 
+
+                end
+                if (csr ==  5'h2)
+                    ip  <= asserted & ~csr_write_data[interrupts-1:0];
+            end
+        end
+    end
+end
+    end
+endgenerate
+
+endmodule
+
+
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd
new file mode 100644
index 000000000..d57c9b7ab
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd
@@ -0,0 +1,825 @@
+--auto-generated by gen_lmcores.py. Don't hand-edit please
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.wishbone_pkg.all;
+entity xwb_lm32 is
+generic(g_profile: string;
+g_reset_vector: std_logic_vector(31 downto 0) := x"00000000";
+g_sdb_address: std_logic_vector(31 downto 0) := x"00000000");
+port(
+clk_sys_i : in  std_logic;
+rst_n_i : in  std_logic;
+irq_i : in  std_logic_vector(31 downto 0);
+dwb_o  : out t_wishbone_master_out;
+dwb_i  : in  t_wishbone_master_in;
+iwb_o  : out t_wishbone_master_out;
+iwb_i  : in  t_wishbone_master_in);
+end xwb_lm32;
+architecture rtl of xwb_lm32 is 
+function f_eval_i_burst_length(profile_name:string) return natural is
+begin
+if profile_name = "minimal" then return 1; end if; 
+if profile_name = "medium" then return 1; end if; 
+if profile_name = "medium_icache" then return 4; end if; 
+if profile_name = "medium_debug" then return 4; end if; 
+if profile_name = "medium_icache_debug" then return 4; end if; 
+if profile_name = "full" then return 4; end if; 
+if profile_name = "full_debug" then return 4; end if; 
+if profile_name = "wr_node" then return 1; end if; 
+return 0;
+end function;
+function f_eval_d_burst_length(profile_name:string) return natural is
+begin
+if profile_name = "minimal" then return 1; end if; 
+if profile_name = "medium" then return 1; end if; 
+if profile_name = "medium_icache" then return 1; end if; 
+if profile_name = "medium_debug" then return 1; end if; 
+if profile_name = "medium_icache_debug" then return 1; end if; 
+if profile_name = "full" then return 4; end if; 
+if profile_name = "full_debug" then return 4; end if; 
+if profile_name = "wr_node" then return 1; end if; 
+return 0;
+end function;
+component lm32_top_minimal is 
+generic ( eba_reset: std_logic_vector(31 downto 0);
+          sdb_address: std_logic_vector(31 downto 0));
+port (
+ 
+  clk_i    : in  std_logic;
+  rst_i    : in  std_logic;
+  interrupt  : in  std_logic_vector(31 downto 0);
+  I_DAT_I  : in  std_logic_vector(31 downto 0);
+  I_ACK_I  : in  std_logic;
+  I_ERR_I  : in  std_logic;
+  I_RTY_I  : in  std_logic;
+   D_DAT_I  : in  std_logic_vector(31 downto 0);
+   D_ACK_I  : in  std_logic;
+   D_ERR_I  : in  std_logic;
+   D_RTY_I  : in  std_logic;
+   I_DAT_O  : out std_logic_vector(31 downto 0);
+   I_ADR_O  : out std_logic_vector(31 downto 0);
+   I_CYC_O  : out std_logic;
+   I_SEL_O  : out std_logic_vector(3 downto 0);
+   I_STB_O  : out std_logic;
+   I_WE_O   : out std_logic;
+   I_CTI_O  : out std_logic_vector(2 downto 0);
+   I_LOCK_O : out std_logic;
+   I_BTE_O  : out std_logic_vector(1 downto 0);
+   D_DAT_O  : out std_logic_vector(31 downto 0);
+   D_ADR_O  : out std_logic_vector(31 downto 0);
+   D_CYC_O  : out std_logic;
+   D_SEL_O  : out std_logic_vector(3 downto 0);
+   D_STB_O  : out std_logic;
+   D_WE_O   : out std_logic;
+   D_CTI_O  : out std_logic_vector(2 downto 0);
+   D_LOCK_O : out std_logic;
+   D_BTE_O  : out std_logic_vector(1 downto 0));
+end component;
+component lm32_top_medium is 
+generic ( eba_reset: std_logic_vector(31 downto 0);
+          sdb_address: std_logic_vector(31 downto 0));
+port (
+ 
+  clk_i    : in  std_logic;
+  rst_i    : in  std_logic;
+  interrupt  : in  std_logic_vector(31 downto 0);
+  I_DAT_I  : in  std_logic_vector(31 downto 0);
+  I_ACK_I  : in  std_logic;
+  I_ERR_I  : in  std_logic;
+  I_RTY_I  : in  std_logic;
+   D_DAT_I  : in  std_logic_vector(31 downto 0);
+   D_ACK_I  : in  std_logic;
+   D_ERR_I  : in  std_logic;
+   D_RTY_I  : in  std_logic;
+   I_DAT_O  : out std_logic_vector(31 downto 0);
+   I_ADR_O  : out std_logic_vector(31 downto 0);
+   I_CYC_O  : out std_logic;
+   I_SEL_O  : out std_logic_vector(3 downto 0);
+   I_STB_O  : out std_logic;
+   I_WE_O   : out std_logic;
+   I_CTI_O  : out std_logic_vector(2 downto 0);
+   I_LOCK_O : out std_logic;
+   I_BTE_O  : out std_logic_vector(1 downto 0);
+   D_DAT_O  : out std_logic_vector(31 downto 0);
+   D_ADR_O  : out std_logic_vector(31 downto 0);
+   D_CYC_O  : out std_logic;
+   D_SEL_O  : out std_logic_vector(3 downto 0);
+   D_STB_O  : out std_logic;
+   D_WE_O   : out std_logic;
+   D_CTI_O  : out std_logic_vector(2 downto 0);
+   D_LOCK_O : out std_logic;
+   D_BTE_O  : out std_logic_vector(1 downto 0));
+end component;
+component lm32_top_medium_icache is 
+generic ( eba_reset: std_logic_vector(31 downto 0);
+          sdb_address: std_logic_vector(31 downto 0));
+port (
+ 
+  clk_i    : in  std_logic;
+  rst_i    : in  std_logic;
+  interrupt  : in  std_logic_vector(31 downto 0);
+  I_DAT_I  : in  std_logic_vector(31 downto 0);
+  I_ACK_I  : in  std_logic;
+  I_ERR_I  : in  std_logic;
+  I_RTY_I  : in  std_logic;
+   D_DAT_I  : in  std_logic_vector(31 downto 0);
+   D_ACK_I  : in  std_logic;
+   D_ERR_I  : in  std_logic;
+   D_RTY_I  : in  std_logic;
+   I_DAT_O  : out std_logic_vector(31 downto 0);
+   I_ADR_O  : out std_logic_vector(31 downto 0);
+   I_CYC_O  : out std_logic;
+   I_SEL_O  : out std_logic_vector(3 downto 0);
+   I_STB_O  : out std_logic;
+   I_WE_O   : out std_logic;
+   I_CTI_O  : out std_logic_vector(2 downto 0);
+   I_LOCK_O : out std_logic;
+   I_BTE_O  : out std_logic_vector(1 downto 0);
+   D_DAT_O  : out std_logic_vector(31 downto 0);
+   D_ADR_O  : out std_logic_vector(31 downto 0);
+   D_CYC_O  : out std_logic;
+   D_SEL_O  : out std_logic_vector(3 downto 0);
+   D_STB_O  : out std_logic;
+   D_WE_O   : out std_logic;
+   D_CTI_O  : out std_logic_vector(2 downto 0);
+   D_LOCK_O : out std_logic;
+   D_BTE_O  : out std_logic_vector(1 downto 0));
+end component;
+component lm32_top_medium_debug is 
+generic ( eba_reset: std_logic_vector(31 downto 0);
+          sdb_address: std_logic_vector(31 downto 0));
+port (
+ 
+  clk_i    : in  std_logic;
+  rst_i    : in  std_logic;
+  interrupt  : in  std_logic_vector(31 downto 0);
+  I_DAT_I  : in  std_logic_vector(31 downto 0);
+  I_ACK_I  : in  std_logic;
+  I_ERR_I  : in  std_logic;
+  I_RTY_I  : in  std_logic;
+   D_DAT_I  : in  std_logic_vector(31 downto 0);
+   D_ACK_I  : in  std_logic;
+   D_ERR_I  : in  std_logic;
+   D_RTY_I  : in  std_logic;
+   I_DAT_O  : out std_logic_vector(31 downto 0);
+   I_ADR_O  : out std_logic_vector(31 downto 0);
+   I_CYC_O  : out std_logic;
+   I_SEL_O  : out std_logic_vector(3 downto 0);
+   I_STB_O  : out std_logic;
+   I_WE_O   : out std_logic;
+   I_CTI_O  : out std_logic_vector(2 downto 0);
+   I_LOCK_O : out std_logic;
+   I_BTE_O  : out std_logic_vector(1 downto 0);
+   D_DAT_O  : out std_logic_vector(31 downto 0);
+   D_ADR_O  : out std_logic_vector(31 downto 0);
+   D_CYC_O  : out std_logic;
+   D_SEL_O  : out std_logic_vector(3 downto 0);
+   D_STB_O  : out std_logic;
+   D_WE_O   : out std_logic;
+   D_CTI_O  : out std_logic_vector(2 downto 0);
+   D_LOCK_O : out std_logic;
+   D_BTE_O  : out std_logic_vector(1 downto 0));
+end component;
+component lm32_top_medium_icache_debug is 
+generic ( eba_reset: std_logic_vector(31 downto 0);
+          sdb_address: std_logic_vector(31 downto 0));
+port (
+ 
+  clk_i    : in  std_logic;
+  rst_i    : in  std_logic;
+  interrupt  : in  std_logic_vector(31 downto 0);
+  I_DAT_I  : in  std_logic_vector(31 downto 0);
+  I_ACK_I  : in  std_logic;
+  I_ERR_I  : in  std_logic;
+  I_RTY_I  : in  std_logic;
+   D_DAT_I  : in  std_logic_vector(31 downto 0);
+   D_ACK_I  : in  std_logic;
+   D_ERR_I  : in  std_logic;
+   D_RTY_I  : in  std_logic;
+   I_DAT_O  : out std_logic_vector(31 downto 0);
+   I_ADR_O  : out std_logic_vector(31 downto 0);
+   I_CYC_O  : out std_logic;
+   I_SEL_O  : out std_logic_vector(3 downto 0);
+   I_STB_O  : out std_logic;
+   I_WE_O   : out std_logic;
+   I_CTI_O  : out std_logic_vector(2 downto 0);
+   I_LOCK_O : out std_logic;
+   I_BTE_O  : out std_logic_vector(1 downto 0);
+   D_DAT_O  : out std_logic_vector(31 downto 0);
+   D_ADR_O  : out std_logic_vector(31 downto 0);
+   D_CYC_O  : out std_logic;
+   D_SEL_O  : out std_logic_vector(3 downto 0);
+   D_STB_O  : out std_logic;
+   D_WE_O   : out std_logic;
+   D_CTI_O  : out std_logic_vector(2 downto 0);
+   D_LOCK_O : out std_logic;
+   D_BTE_O  : out std_logic_vector(1 downto 0));
+end component;
+component lm32_top_full is 
+generic ( eba_reset: std_logic_vector(31 downto 0);
+          sdb_address: std_logic_vector(31 downto 0));
+port (
+ 
+  clk_i    : in  std_logic;
+  rst_i    : in  std_logic;
+  interrupt  : in  std_logic_vector(31 downto 0);
+  I_DAT_I  : in  std_logic_vector(31 downto 0);
+  I_ACK_I  : in  std_logic;
+  I_ERR_I  : in  std_logic;
+  I_RTY_I  : in  std_logic;
+   D_DAT_I  : in  std_logic_vector(31 downto 0);
+   D_ACK_I  : in  std_logic;
+   D_ERR_I  : in  std_logic;
+   D_RTY_I  : in  std_logic;
+   I_DAT_O  : out std_logic_vector(31 downto 0);
+   I_ADR_O  : out std_logic_vector(31 downto 0);
+   I_CYC_O  : out std_logic;
+   I_SEL_O  : out std_logic_vector(3 downto 0);
+   I_STB_O  : out std_logic;
+   I_WE_O   : out std_logic;
+   I_CTI_O  : out std_logic_vector(2 downto 0);
+   I_LOCK_O : out std_logic;
+   I_BTE_O  : out std_logic_vector(1 downto 0);
+   D_DAT_O  : out std_logic_vector(31 downto 0);
+   D_ADR_O  : out std_logic_vector(31 downto 0);
+   D_CYC_O  : out std_logic;
+   D_SEL_O  : out std_logic_vector(3 downto 0);
+   D_STB_O  : out std_logic;
+   D_WE_O   : out std_logic;
+   D_CTI_O  : out std_logic_vector(2 downto 0);
+   D_LOCK_O : out std_logic;
+   D_BTE_O  : out std_logic_vector(1 downto 0));
+end component;
+component lm32_top_full_debug is 
+generic ( eba_reset: std_logic_vector(31 downto 0);
+          sdb_address: std_logic_vector(31 downto 0));
+port (
+ 
+  clk_i    : in  std_logic;
+  rst_i    : in  std_logic;
+  interrupt  : in  std_logic_vector(31 downto 0);
+  I_DAT_I  : in  std_logic_vector(31 downto 0);
+  I_ACK_I  : in  std_logic;
+  I_ERR_I  : in  std_logic;
+  I_RTY_I  : in  std_logic;
+   D_DAT_I  : in  std_logic_vector(31 downto 0);
+   D_ACK_I  : in  std_logic;
+   D_ERR_I  : in  std_logic;
+   D_RTY_I  : in  std_logic;
+   I_DAT_O  : out std_logic_vector(31 downto 0);
+   I_ADR_O  : out std_logic_vector(31 downto 0);
+   I_CYC_O  : out std_logic;
+   I_SEL_O  : out std_logic_vector(3 downto 0);
+   I_STB_O  : out std_logic;
+   I_WE_O   : out std_logic;
+   I_CTI_O  : out std_logic_vector(2 downto 0);
+   I_LOCK_O : out std_logic;
+   I_BTE_O  : out std_logic_vector(1 downto 0);
+   D_DAT_O  : out std_logic_vector(31 downto 0);
+   D_ADR_O  : out std_logic_vector(31 downto 0);
+   D_CYC_O  : out std_logic;
+   D_SEL_O  : out std_logic_vector(3 downto 0);
+   D_STB_O  : out std_logic;
+   D_WE_O   : out std_logic;
+   D_CTI_O  : out std_logic_vector(2 downto 0);
+   D_LOCK_O : out std_logic;
+   D_BTE_O  : out std_logic_vector(1 downto 0));
+end component;
+component lm32_top_wr_node is 
+generic ( eba_reset: std_logic_vector(31 downto 0);
+          sdb_address: std_logic_vector(31 downto 0));
+port (
+ 
+  clk_i    : in  std_logic;
+  rst_i    : in  std_logic;
+  interrupt  : in  std_logic_vector(31 downto 0);
+  I_DAT_I  : in  std_logic_vector(31 downto 0);
+  I_ACK_I  : in  std_logic;
+  I_ERR_I  : in  std_logic;
+  I_RTY_I  : in  std_logic;
+   D_DAT_I  : in  std_logic_vector(31 downto 0);
+   D_ACK_I  : in  std_logic;
+   D_ERR_I  : in  std_logic;
+   D_RTY_I  : in  std_logic;
+   I_DAT_O  : out std_logic_vector(31 downto 0);
+   I_ADR_O  : out std_logic_vector(31 downto 0);
+   I_CYC_O  : out std_logic;
+   I_SEL_O  : out std_logic_vector(3 downto 0);
+   I_STB_O  : out std_logic;
+   I_WE_O   : out std_logic;
+   I_CTI_O  : out std_logic_vector(2 downto 0);
+   I_LOCK_O : out std_logic;
+   I_BTE_O  : out std_logic_vector(1 downto 0);
+   D_DAT_O  : out std_logic_vector(31 downto 0);
+   D_ADR_O  : out std_logic_vector(31 downto 0);
+   D_CYC_O  : out std_logic;
+   D_SEL_O  : out std_logic_vector(3 downto 0);
+   D_STB_O  : out std_logic;
+   D_WE_O   : out std_logic;
+   D_CTI_O  : out std_logic_vector(2 downto 0);
+   D_LOCK_O : out std_logic;
+   D_BTE_O  : out std_logic_vector(1 downto 0));
+end component;
+
+  function pick(first : boolean;
+                 a, b  : t_wishbone_address)
+      return t_wishbone_address is
+   begin
+      if first then
+         return a;
+      else
+         return b;
+      end if;
+   end pick;
+   
+   function b2l(val : boolean)
+      return std_logic is
+   begin
+      if val then 
+         return '1';
+      else
+         return '0';
+      end if;
+   end b2l;
+
+ function strip_undefined
+    (x           : std_logic_vector) return std_logic_vector is
+    variable tmp : std_logic_vector(x'left downto 0);
+  begin
+    for i  in 0 to x'left loop
+      if(x(i)='1') then
+        tmp(i) := '1';
+      else
+        tmp(i) := '0';
+      end if;
+    end loop;  -- i
+    return tmp;
+  end strip_undefined;
+   
+   constant dcache_burst_length : natural := f_eval_d_burst_length(g_profile);
+   constant icache_burst_length : natural := f_eval_i_burst_length(g_profile);
+   
+   -- Control pins from the LM32
+   signal I_ADR : t_wishbone_address;
+   signal D_ADR : t_wishbone_address;
+   signal I_CYC : std_logic;
+   signal D_CYC : std_logic;
+   signal I_CTI : t_wishbone_cycle_type;
+   signal D_CTI : t_wishbone_cycle_type;
+   -- We also watch the STALL lines from the v4 slaves
+   
+   -- Registered logic:
+   signal inst_was_busy : std_logic;
+   signal data_was_busy : std_logic;
+   signal inst_addr_reg : t_wishbone_address;
+   signal data_addr_reg : t_wishbone_address;
+   signal inst_remaining : natural range 0 to icache_burst_length;
+   signal data_remaining : natural range 0 to dcache_burst_length;
+   
+   -- Asynchronous logic:
+   signal I_STB_O : std_logic;
+   signal D_STB_O : std_logic;
+   signal rst:std_logic;
+begin
+		rst <= not rst_n_i;
+gen_profile_minimal: if (g_profile = "minimal") generate
+U_Wrapped_LM32: lm32_top_minimal
+
+generic map (
+			eba_reset => g_reset_vector,
+                        sdb_address => g_sdb_address)
+port map(
+      clk_i	=> clk_sys_i,
+      rst_i	=> rst,
+      interrupt	=> irq_i,
+      -- Pass slave responses through unmodified
+      I_DAT_I	=> strip_undefined(iwb_i.DAT),
+      I_ACK_I	=> iwb_i.ACK,
+      I_ERR_I	=> iwb_i.ERR,
+      I_RTY_I	=> iwb_i.RTY,
+      D_DAT_I	=> strip_undefined(dwb_i.DAT),
+      D_ACK_I	=> dwb_i.ACK,
+      D_ERR_I	=> dwb_i.ERR,
+      D_RTY_I	=> dwb_i.RTY,
+      -- Writes can only happen as a single cycle
+      I_DAT_O	=> iwb_o.DAT,
+      D_DAT_O	=> dwb_o.DAT,
+      I_WE_O	=> iwb_o.WE,
+      D_WE_O	=> dwb_o.WE,
+      -- SEL /= 1111 only for single cycles
+      I_SEL_O	=> iwb_o.SEL,
+      D_SEL_O	=> dwb_o.SEL,
+      -- We can ignore BTE as we know it's always linear burst mode
+      I_BTE_O	=> open,
+      D_BTE_O	=> open,
+      -- Lock is never flagged by LM32. Besides, WBv4 locks intercon on CYC.
+      I_LOCK_O	=> open,
+      D_LOCK_O	=> open,
+      -- The LM32 has STB=CYC always
+      I_STB_O	=> open,
+      D_STB_O	=> open,
+      -- We monitor these pins to direct the adapter's logic
+      I_ADR_O	=> I_ADR,
+      I_CYC_O	=> I_CYC,
+      I_CTI_O	=> I_CTI,
+      D_ADR_O	=> D_ADR,
+      D_CYC_O	=> D_CYC,
+      D_CTI_O	=> D_CTI);
+end generate gen_profile_minimal;
+gen_profile_medium: if (g_profile = "medium") generate
+U_Wrapped_LM32: lm32_top_medium
+
+generic map (
+			eba_reset => g_reset_vector,
+                        sdb_address => g_sdb_address)
+port map(
+      clk_i	=> clk_sys_i,
+      rst_i	=> rst,
+      interrupt	=> irq_i,
+      -- Pass slave responses through unmodified
+      I_DAT_I	=> strip_undefined(iwb_i.DAT),
+      I_ACK_I	=> iwb_i.ACK,
+      I_ERR_I	=> iwb_i.ERR,
+      I_RTY_I	=> iwb_i.RTY,
+      D_DAT_I	=> strip_undefined(dwb_i.DAT),
+      D_ACK_I	=> dwb_i.ACK,
+      D_ERR_I	=> dwb_i.ERR,
+      D_RTY_I	=> dwb_i.RTY,
+      -- Writes can only happen as a single cycle
+      I_DAT_O	=> iwb_o.DAT,
+      D_DAT_O	=> dwb_o.DAT,
+      I_WE_O	=> iwb_o.WE,
+      D_WE_O	=> dwb_o.WE,
+      -- SEL /= 1111 only for single cycles
+      I_SEL_O	=> iwb_o.SEL,
+      D_SEL_O	=> dwb_o.SEL,
+      -- We can ignore BTE as we know it's always linear burst mode
+      I_BTE_O	=> open,
+      D_BTE_O	=> open,
+      -- Lock is never flagged by LM32. Besides, WBv4 locks intercon on CYC.
+      I_LOCK_O	=> open,
+      D_LOCK_O	=> open,
+      -- The LM32 has STB=CYC always
+      I_STB_O	=> open,
+      D_STB_O	=> open,
+      -- We monitor these pins to direct the adapter's logic
+      I_ADR_O	=> I_ADR,
+      I_CYC_O	=> I_CYC,
+      I_CTI_O	=> I_CTI,
+      D_ADR_O	=> D_ADR,
+      D_CYC_O	=> D_CYC,
+      D_CTI_O	=> D_CTI);
+end generate gen_profile_medium;
+gen_profile_medium_icache: if (g_profile = "medium_icache") generate
+U_Wrapped_LM32: lm32_top_medium_icache
+
+generic map (
+			eba_reset => g_reset_vector,
+                        sdb_address => g_sdb_address)
+port map(
+      clk_i	=> clk_sys_i,
+      rst_i	=> rst,
+      interrupt	=> irq_i,
+      -- Pass slave responses through unmodified
+      I_DAT_I	=> strip_undefined(iwb_i.DAT),
+      I_ACK_I	=> iwb_i.ACK,
+      I_ERR_I	=> iwb_i.ERR,
+      I_RTY_I	=> iwb_i.RTY,
+      D_DAT_I	=> strip_undefined(dwb_i.DAT),
+      D_ACK_I	=> dwb_i.ACK,
+      D_ERR_I	=> dwb_i.ERR,
+      D_RTY_I	=> dwb_i.RTY,
+      -- Writes can only happen as a single cycle
+      I_DAT_O	=> iwb_o.DAT,
+      D_DAT_O	=> dwb_o.DAT,
+      I_WE_O	=> iwb_o.WE,
+      D_WE_O	=> dwb_o.WE,
+      -- SEL /= 1111 only for single cycles
+      I_SEL_O	=> iwb_o.SEL,
+      D_SEL_O	=> dwb_o.SEL,
+      -- We can ignore BTE as we know it's always linear burst mode
+      I_BTE_O	=> open,
+      D_BTE_O	=> open,
+      -- Lock is never flagged by LM32. Besides, WBv4 locks intercon on CYC.
+      I_LOCK_O	=> open,
+      D_LOCK_O	=> open,
+      -- The LM32 has STB=CYC always
+      I_STB_O	=> open,
+      D_STB_O	=> open,
+      -- We monitor these pins to direct the adapter's logic
+      I_ADR_O	=> I_ADR,
+      I_CYC_O	=> I_CYC,
+      I_CTI_O	=> I_CTI,
+      D_ADR_O	=> D_ADR,
+      D_CYC_O	=> D_CYC,
+      D_CTI_O	=> D_CTI);
+end generate gen_profile_medium_icache;
+gen_profile_medium_debug: if (g_profile = "medium_debug") generate
+U_Wrapped_LM32: lm32_top_medium_debug
+
+generic map (
+			eba_reset => g_reset_vector,
+                        sdb_address => g_sdb_address)
+port map(
+      clk_i	=> clk_sys_i,
+      rst_i	=> rst,
+      interrupt	=> irq_i,
+      -- Pass slave responses through unmodified
+      I_DAT_I	=> strip_undefined(iwb_i.DAT),
+      I_ACK_I	=> iwb_i.ACK,
+      I_ERR_I	=> iwb_i.ERR,
+      I_RTY_I	=> iwb_i.RTY,
+      D_DAT_I	=> strip_undefined(dwb_i.DAT),
+      D_ACK_I	=> dwb_i.ACK,
+      D_ERR_I	=> dwb_i.ERR,
+      D_RTY_I	=> dwb_i.RTY,
+      -- Writes can only happen as a single cycle
+      I_DAT_O	=> iwb_o.DAT,
+      D_DAT_O	=> dwb_o.DAT,
+      I_WE_O	=> iwb_o.WE,
+      D_WE_O	=> dwb_o.WE,
+      -- SEL /= 1111 only for single cycles
+      I_SEL_O	=> iwb_o.SEL,
+      D_SEL_O	=> dwb_o.SEL,
+      -- We can ignore BTE as we know it's always linear burst mode
+      I_BTE_O	=> open,
+      D_BTE_O	=> open,
+      -- Lock is never flagged by LM32. Besides, WBv4 locks intercon on CYC.
+      I_LOCK_O	=> open,
+      D_LOCK_O	=> open,
+      -- The LM32 has STB=CYC always
+      I_STB_O	=> open,
+      D_STB_O	=> open,
+      -- We monitor these pins to direct the adapter's logic
+      I_ADR_O	=> I_ADR,
+      I_CYC_O	=> I_CYC,
+      I_CTI_O	=> I_CTI,
+      D_ADR_O	=> D_ADR,
+      D_CYC_O	=> D_CYC,
+      D_CTI_O	=> D_CTI);
+end generate gen_profile_medium_debug;
+gen_profile_medium_icache_debug: if (g_profile = "medium_icache_debug") generate
+U_Wrapped_LM32: lm32_top_medium_icache_debug
+
+generic map (
+			eba_reset => g_reset_vector,
+                        sdb_address => g_sdb_address)
+port map(
+      clk_i	=> clk_sys_i,
+      rst_i	=> rst,
+      interrupt	=> irq_i,
+      -- Pass slave responses through unmodified
+      I_DAT_I	=> strip_undefined(iwb_i.DAT),
+      I_ACK_I	=> iwb_i.ACK,
+      I_ERR_I	=> iwb_i.ERR,
+      I_RTY_I	=> iwb_i.RTY,
+      D_DAT_I	=> strip_undefined(dwb_i.DAT),
+      D_ACK_I	=> dwb_i.ACK,
+      D_ERR_I	=> dwb_i.ERR,
+      D_RTY_I	=> dwb_i.RTY,
+      -- Writes can only happen as a single cycle
+      I_DAT_O	=> iwb_o.DAT,
+      D_DAT_O	=> dwb_o.DAT,
+      I_WE_O	=> iwb_o.WE,
+      D_WE_O	=> dwb_o.WE,
+      -- SEL /= 1111 only for single cycles
+      I_SEL_O	=> iwb_o.SEL,
+      D_SEL_O	=> dwb_o.SEL,
+      -- We can ignore BTE as we know it's always linear burst mode
+      I_BTE_O	=> open,
+      D_BTE_O	=> open,
+      -- Lock is never flagged by LM32. Besides, WBv4 locks intercon on CYC.
+      I_LOCK_O	=> open,
+      D_LOCK_O	=> open,
+      -- The LM32 has STB=CYC always
+      I_STB_O	=> open,
+      D_STB_O	=> open,
+      -- We monitor these pins to direct the adapter's logic
+      I_ADR_O	=> I_ADR,
+      I_CYC_O	=> I_CYC,
+      I_CTI_O	=> I_CTI,
+      D_ADR_O	=> D_ADR,
+      D_CYC_O	=> D_CYC,
+      D_CTI_O	=> D_CTI);
+end generate gen_profile_medium_icache_debug;
+gen_profile_full: if (g_profile = "full") generate
+U_Wrapped_LM32: lm32_top_full
+
+generic map (
+			eba_reset => g_reset_vector,
+                        sdb_address => g_sdb_address)
+port map(
+      clk_i	=> clk_sys_i,
+      rst_i	=> rst,
+      interrupt	=> irq_i,
+      -- Pass slave responses through unmodified
+      I_DAT_I	=> strip_undefined(iwb_i.DAT),
+      I_ACK_I	=> iwb_i.ACK,
+      I_ERR_I	=> iwb_i.ERR,
+      I_RTY_I	=> iwb_i.RTY,
+      D_DAT_I	=> strip_undefined(dwb_i.DAT),
+      D_ACK_I	=> dwb_i.ACK,
+      D_ERR_I	=> dwb_i.ERR,
+      D_RTY_I	=> dwb_i.RTY,
+      -- Writes can only happen as a single cycle
+      I_DAT_O	=> iwb_o.DAT,
+      D_DAT_O	=> dwb_o.DAT,
+      I_WE_O	=> iwb_o.WE,
+      D_WE_O	=> dwb_o.WE,
+      -- SEL /= 1111 only for single cycles
+      I_SEL_O	=> iwb_o.SEL,
+      D_SEL_O	=> dwb_o.SEL,
+      -- We can ignore BTE as we know it's always linear burst mode
+      I_BTE_O	=> open,
+      D_BTE_O	=> open,
+      -- Lock is never flagged by LM32. Besides, WBv4 locks intercon on CYC.
+      I_LOCK_O	=> open,
+      D_LOCK_O	=> open,
+      -- The LM32 has STB=CYC always
+      I_STB_O	=> open,
+      D_STB_O	=> open,
+      -- We monitor these pins to direct the adapter's logic
+      I_ADR_O	=> I_ADR,
+      I_CYC_O	=> I_CYC,
+      I_CTI_O	=> I_CTI,
+      D_ADR_O	=> D_ADR,
+      D_CYC_O	=> D_CYC,
+      D_CTI_O	=> D_CTI);
+end generate gen_profile_full;
+gen_profile_full_debug: if (g_profile = "full_debug") generate
+U_Wrapped_LM32: lm32_top_full_debug
+
+generic map (
+			eba_reset => g_reset_vector,
+                        sdb_address => g_sdb_address)
+port map(
+      clk_i	=> clk_sys_i,
+      rst_i	=> rst,
+      interrupt	=> irq_i,
+      -- Pass slave responses through unmodified
+      I_DAT_I	=> strip_undefined(iwb_i.DAT),
+      I_ACK_I	=> iwb_i.ACK,
+      I_ERR_I	=> iwb_i.ERR,
+      I_RTY_I	=> iwb_i.RTY,
+      D_DAT_I	=> strip_undefined(dwb_i.DAT),
+      D_ACK_I	=> dwb_i.ACK,
+      D_ERR_I	=> dwb_i.ERR,
+      D_RTY_I	=> dwb_i.RTY,
+      -- Writes can only happen as a single cycle
+      I_DAT_O	=> iwb_o.DAT,
+      D_DAT_O	=> dwb_o.DAT,
+      I_WE_O	=> iwb_o.WE,
+      D_WE_O	=> dwb_o.WE,
+      -- SEL /= 1111 only for single cycles
+      I_SEL_O	=> iwb_o.SEL,
+      D_SEL_O	=> dwb_o.SEL,
+      -- We can ignore BTE as we know it's always linear burst mode
+      I_BTE_O	=> open,
+      D_BTE_O	=> open,
+      -- Lock is never flagged by LM32. Besides, WBv4 locks intercon on CYC.
+      I_LOCK_O	=> open,
+      D_LOCK_O	=> open,
+      -- The LM32 has STB=CYC always
+      I_STB_O	=> open,
+      D_STB_O	=> open,
+      -- We monitor these pins to direct the adapter's logic
+      I_ADR_O	=> I_ADR,
+      I_CYC_O	=> I_CYC,
+      I_CTI_O	=> I_CTI,
+      D_ADR_O	=> D_ADR,
+      D_CYC_O	=> D_CYC,
+      D_CTI_O	=> D_CTI);
+end generate gen_profile_full_debug;
+gen_profile_wr_node: if (g_profile = "wr_node") generate
+U_Wrapped_LM32: lm32_top_wr_node
+
+generic map (
+			eba_reset => g_reset_vector,
+                        sdb_address => g_sdb_address)
+port map(
+      clk_i	=> clk_sys_i,
+      rst_i	=> rst,
+      interrupt	=> irq_i,
+      -- Pass slave responses through unmodified
+      I_DAT_I	=> strip_undefined(iwb_i.DAT),
+      I_ACK_I	=> iwb_i.ACK,
+      I_ERR_I	=> iwb_i.ERR,
+      I_RTY_I	=> iwb_i.RTY,
+      D_DAT_I	=> strip_undefined(dwb_i.DAT),
+      D_ACK_I	=> dwb_i.ACK,
+      D_ERR_I	=> dwb_i.ERR,
+      D_RTY_I	=> dwb_i.RTY,
+      -- Writes can only happen as a single cycle
+      I_DAT_O	=> iwb_o.DAT,
+      D_DAT_O	=> dwb_o.DAT,
+      I_WE_O	=> iwb_o.WE,
+      D_WE_O	=> dwb_o.WE,
+      -- SEL /= 1111 only for single cycles
+      I_SEL_O	=> iwb_o.SEL,
+      D_SEL_O	=> dwb_o.SEL,
+      -- We can ignore BTE as we know it's always linear burst mode
+      I_BTE_O	=> open,
+      D_BTE_O	=> open,
+      -- Lock is never flagged by LM32. Besides, WBv4 locks intercon on CYC.
+      I_LOCK_O	=> open,
+      D_LOCK_O	=> open,
+      -- The LM32 has STB=CYC always
+      I_STB_O	=> open,
+      D_STB_O	=> open,
+      -- We monitor these pins to direct the adapter's logic
+      I_ADR_O	=> I_ADR,
+      I_CYC_O	=> I_CYC,
+      I_CTI_O	=> I_CTI,
+      D_ADR_O	=> D_ADR,
+      D_CYC_O	=> D_CYC,
+      D_CTI_O	=> D_CTI);
+end generate gen_profile_wr_node;
+
+   -- Cycle durations always match in our adapter
+   iwb_o.CYC <= I_CYC;
+   dwb_o.CYC <= D_CYC;
+   
+   iwb_o.STB <= I_STB_O;
+   dwb_o.STB <= D_STB_O;
+   
+   I_STB_O <= (I_CYC and not inst_was_busy) or b2l(inst_remaining /= 0);
+   inst : process(clk_sys_i)
+      variable inst_addr : t_wishbone_address;
+      variable inst_length : natural;
+   begin
+      if rising_edge(clk_sys_i) then
+         if rst = '1' then
+            inst_was_busy <= '0';
+            inst_remaining <= 0;
+            inst_addr_reg <= (others => '0');
+         else
+            inst_was_busy <= I_CYC;
+            
+            -- Is this the start of a new WB cycle?
+            if I_CYC = '1' and inst_was_busy = '0' then
+               inst_addr := I_ADR;
+               if I_CTI = "010" then
+                  inst_length := icache_burst_length;
+               else
+                  inst_length := 1;
+               end if;
+            else
+               inst_addr := inst_addr_reg;
+               inst_length := inst_remaining;
+            end if;
+            
+            -- When stalled, we cannot advance the address
+            if iwb_i.STALL = '0' and I_STB_O = '1' then
+               inst_addr_reg  <= std_logic_vector(unsigned(inst_addr) + 4);
+               inst_remaining <= inst_length - 1;
+            else
+               inst_addr_reg  <= inst_addr;
+               inst_remaining <= inst_length;
+            end if;
+         end if;
+      end if;
+   end process;
+   
+   D_STB_O <= (D_CYC and not data_was_busy) or b2l(data_remaining /= 0);
+   data : process(clk_sys_i)
+      variable data_addr : t_wishbone_address;
+      variable data_length : natural;
+   begin
+      if rising_edge(clk_sys_i) then
+         if rst = '1' then
+            data_was_busy <= '0';
+            data_remaining <= 0;
+            data_addr_reg <= (others => '0');
+         else
+            data_was_busy <= D_CYC;
+            
+            -- Is this the start of a new WB cycle?
+            if D_CYC = '1' and data_was_busy = '0' then
+               data_addr := D_ADR;
+               if D_CTI = "010" then
+                  data_length := dcache_burst_length;
+               else
+                  data_length := 1;
+               end if;
+            else
+               data_addr := data_addr_reg;
+               data_length := data_remaining;
+            end if;
+            
+            -- When stalled, we cannot advance the address
+            if dwb_i.STALL = '0' and D_STB_O = '1' then
+               data_addr_reg  <= std_logic_vector(unsigned(data_addr) + 4);
+               data_remaining <= data_length - 1;
+            else
+               data_addr_reg  <= data_addr;
+               data_remaining <= data_length;
+            end if;
+         end if;
+      end if;
+   end process;
+   
+   -- The first request uses the WBv3 address, thereafter an incrementing one.
+   dwb_o.ADR <= pick(data_was_busy = '0', D_ADR, data_addr_reg);
+   iwb_o.ADR <= pick(inst_was_busy = '0', I_ADR, inst_addr_reg);
+	end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v
new file mode 100644
index 000000000..1821c3f6d
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v
@@ -0,0 +1,20 @@
+module jtag_tap(
+  output tck,
+  output tdi,
+  input tdo,
+  output capture,
+  output shift,
+  output e1dr,
+  output update,
+  output reset
+);
+
+	assign tck = 1;
+	assign tdi = 1;
+	assign capture = 0;
+	assign shift = 0;
+	assign e1dr = 0;
+	assign update = 0;
+	assign reset = 0;
+
+endmodule
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v
new file mode 100644
index 000000000..ea3e0cb0d
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v
@@ -0,0 +1,119 @@
+// =============================================================================
+//                           COPYRIGHT NOTICE
+// Copyright 2006 (c) Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// This confidential and proprietary software may be used only as authorised by
+// a licensing agreement from Lattice Semiconductor Corporation.
+// The entire notice above must be reproduced on all authorized copies and
+// copies may only be made to the extent permitted by a licensing agreement from
+// Lattice Semiconductor Corporation.
+//
+// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
+// 5555 NE Moore Court                            408-826-6000 (other locations)
+// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
+// U.S.A                                   email: techsupport@latticesemi.com
+// =============================================================================/
+//                         FILE DETAILS
+// Project          : LatticeMico32
+// File             : lm32_multiplier.v
+// Title            : Pipelined multiplier.
+// Dependencies     : lm32_include.v
+// Version          : 6.1.17
+//                  : Initial Release
+// Version          : 7.0SP2, 3.0
+//                  : No Change
+// Version          : 3.1
+//                  : No Change
+// =============================================================================
+                  
+`include "../../src/lm32_include.v"
+
+/////////////////////////////////////////////////////
+// Module interface
+/////////////////////////////////////////////////////
+
+module lm32_multiplier (
+    // ----- Inputs -----
+    clk_i,
+    rst_i,
+    stall_x,
+    stall_m,
+    operand_0,
+    operand_1,
+    // ----- Ouputs -----
+    result
+    );
+
+/////////////////////////////////////////////////////
+// Inputs
+/////////////////////////////////////////////////////
+
+input clk_i;                            // Clock 
+input rst_i;                            // Reset
+input stall_x;                          // Stall instruction in X stage
+input stall_m;                          // Stall instruction in M stage
+input [`LM32_WORD_RNG] operand_0;     	// Muliplicand
+input [`LM32_WORD_RNG] operand_1;     	// Multiplier
+
+/////////////////////////////////////////////////////
+// Outputs
+/////////////////////////////////////////////////////
+
+output [`LM32_WORD_RNG] result;       	// Product of multiplication
+wire   [`LM32_WORD_RNG] result;
+
+/////////////////////////////////////////////////////
+// Internal nets and registers 
+/////////////////////////////////////////////////////
+
+// Divide multiplicands into high and low
+`define HALF_WORD_WIDTH (`LM32_WORD_WIDTH/2)
+`define HALF_WORD_RNG (`HALF_WORD_WIDTH-1):0
+
+// Result = c+d+e = a*b
+reg [`HALF_WORD_RNG] a0, a1, b0, b1;
+reg [`HALF_WORD_RNG] c0, c1;
+reg [`HALF_WORD_RNG] d1, e1;
+reg [`HALF_WORD_RNG] result0, result1;
+
+assign result = {result1, result0};
+
+/////////////////////////////////////////////////////
+// Sequential logic
+/////////////////////////////////////////////////////
+
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+    if (rst_i == `TRUE)
+    begin
+        a0 <= {`HALF_WORD_WIDTH{1'b0}};
+        a1 <= {`HALF_WORD_WIDTH{1'b0}};
+        b0 <= {`HALF_WORD_WIDTH{1'b0}};
+        b1 <= {`HALF_WORD_WIDTH{1'b0}};
+		  c0 <= {`HALF_WORD_WIDTH{1'b0}};
+		  c1 <= {`HALF_WORD_WIDTH{1'b0}};
+		  d1 <= {`HALF_WORD_WIDTH{1'b0}};
+		  e1 <= {`HALF_WORD_WIDTH{1'b0}};
+        result0 <= {`HALF_WORD_WIDTH{1'b0}};
+        result1 <= {`HALF_WORD_WIDTH{1'b0}};
+    end
+    else
+    begin
+        if (stall_x == `FALSE)
+        begin    
+            {a1, a0} <= operand_0;
+            {b1, b0} <= operand_1;
+        end
+        if (stall_m == `FALSE)
+		  begin
+            {c1, c0} <= a0 * b0;
+				d1 <= a0 * b1;
+				e1 <= a1 * b0;
+		  end
+		  
+        result0 <= c0;
+		  result1 <= c1 + d1 + e1;
+    end
+end
+
+endmodule
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v
new file mode 100644
index 000000000..78dbf0293
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v
@@ -0,0 +1,66 @@
+// Modified by GSI to use simple positive edge clocking and the JTAG capture state
+
+module jtag_cores (
+    input [7:0] reg_d,
+    input [2:0] reg_addr_d,
+    output reg_update,
+    output [7:0] reg_q,
+    output [2:0] reg_addr_q,
+    output jtck,
+    output jrstn
+);
+
+wire tck;
+wire tdi;
+wire tdo;
+wire capture;
+wire shift;
+wire update;
+wire e1dr;
+wire reset;
+
+jtag_tap jtag_tap (
+	.tck(tck),
+	.tdi(tdi),
+	.tdo(tdo),
+	.capture(capture),
+	.shift(shift),
+	.e1dr(e1dr),
+	.update(update),
+	.reset(reset)
+);
+
+reg [10:0] jtag_shift;
+reg [10:0] jtag_latched;
+
+always @(posedge tck)
+begin
+	if(reset)
+		jtag_shift <= 11'b0;
+	else begin
+		if (shift)
+			jtag_shift <= {tdi, jtag_shift[10:1]};
+		else if (capture)
+			jtag_shift <= {reg_d, reg_addr_d};
+	end
+end
+
+assign tdo = jtag_shift[0];
+
+always @(posedge tck)
+begin
+	if(reset)
+		jtag_latched <= 11'b0;
+	else begin
+	   if (e1dr)
+		   jtag_latched <= jtag_shift;
+	end
+end
+
+assign reg_update = update;
+assign reg_q = jtag_latched[10:3];
+assign reg_addr_q = jtag_latched[2:0];
+assign jtck = tck;
+assign jrstn = ~reset;
+
+endmodule
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v
new file mode 100644
index 000000000..b0d2d79ce
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v
@@ -0,0 +1,115 @@
+// =============================================================================
+//                           COPYRIGHT NOTICE
+// Copyright 2006 (c) Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// This confidential and proprietary software may be used only as authorised by
+// a licensing agreement from Lattice Semiconductor Corporation.
+// The entire notice above must be reproduced on all authorized copies and
+// copies may only be made to the extent permitted by a licensing agreement from
+// Lattice Semiconductor Corporation.
+//
+// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
+// 5555 NE Moore Court                            408-826-6000 (other locations)
+// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
+// U.S.A                                   email: techsupport@latticesemi.com
+// ============================================================================/
+//                         FILE DETAILS
+// Project          : LatticeMico32
+// File             : lm32_adder.v
+// Title            : Integer adder / subtractor with comparison flag generation 
+// Dependencies     : lm32_include.v
+// Version          : 6.1.17
+//                  : Initial Release
+// Version          : 7.0SP2, 3.0
+//                  : No Change
+// Version          : 3.1
+//                  : No Change
+// =============================================================================
+
+`include "lm32_include.v"
+
+/////////////////////////////////////////////////////
+// Module interface
+/////////////////////////////////////////////////////
+
+module lm32_adder (
+    // ----- Inputs -------
+    adder_op_x,
+    adder_op_x_n,
+    operand_0_x,
+    operand_1_x,
+    // ----- Outputs -------
+    adder_result_x,
+    adder_carry_n_x,
+    adder_overflow_x
+    );
+
+/////////////////////////////////////////////////////
+// Inputs
+/////////////////////////////////////////////////////
+
+input adder_op_x;                                       // Operating to perform, 0 for addition, 1 for subtraction
+input adder_op_x_n;                                     // Inverted version of adder_op_x
+input [`LM32_WORD_RNG] operand_0_x;                     // Operand to add, or subtract from
+input [`LM32_WORD_RNG] operand_1_x;                     // Opearnd to add, or subtract by
+
+/////////////////////////////////////////////////////
+// Outputs
+/////////////////////////////////////////////////////
+
+output [`LM32_WORD_RNG] adder_result_x;                 // Result of addition or subtraction
+wire   [`LM32_WORD_RNG] adder_result_x;
+output adder_carry_n_x;                                 // Inverted carry
+wire   adder_carry_n_x;
+output adder_overflow_x;                                // Indicates if overflow occured, only valid for subtractions
+reg    adder_overflow_x;
+    
+/////////////////////////////////////////////////////
+// Internal nets and registers 
+/////////////////////////////////////////////////////
+
+wire a_sign;                                            // Sign (i.e. positive or negative) of operand 0
+wire b_sign;                                            // Sign of operand 1
+wire result_sign;                                       // Sign of result
+
+/////////////////////////////////////////////////////
+// Instantiations 
+/////////////////////////////////////////////////////
+
+lm32_addsub addsub (
+    // ----- Inputs -----
+    .DataA          (operand_0_x), 
+    .DataB          (operand_1_x), 
+    .Cin            (adder_op_x), 
+    .Add_Sub        (adder_op_x_n), 
+    // ----- Ouputs -----
+    .Result         (adder_result_x), 
+    .Cout           (adder_carry_n_x)
+    );
+
+/////////////////////////////////////////////////////
+// Combinational Logic
+/////////////////////////////////////////////////////
+
+// Extract signs of operands and result
+
+assign a_sign = operand_0_x[`LM32_WORD_WIDTH-1];
+assign b_sign = operand_1_x[`LM32_WORD_WIDTH-1];
+assign result_sign = adder_result_x[`LM32_WORD_WIDTH-1];
+
+// Determine whether an overflow occured when performing a subtraction
+
+always @(*)
+begin    
+    //  +ve - -ve = -ve -> overflow
+    //  -ve - +ve = +ve -> overflow
+    if  (   (!a_sign & b_sign & result_sign)
+         || (a_sign & !b_sign & !result_sign)
+        )
+        adder_overflow_x = `TRUE;
+    else
+        adder_overflow_x = `FALSE;
+end
+    
+endmodule
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v
new file mode 100644
index 000000000..8861cbe2d
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v
@@ -0,0 +1,74 @@
+// =============================================================================
+//                           COPYRIGHT NOTICE
+// Copyright 2006 (c) Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// This confidential and proprietary software may be used only as authorised by
+// a licensing agreement from Lattice Semiconductor Corporation.
+// The entire notice above must be reproduced on all authorized copies and
+// copies may only be made to the extent permitted by a licensing agreement from
+// Lattice Semiconductor Corporation.
+//
+// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
+// 5555 NE Moore Court                            408-826-6000 (other locations)
+// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
+// U.S.A                                   email: techsupport@latticesemi.com
+// =============================================================================/
+//                         FILE DETAILS
+// Project          : LatticeMico32
+// File             : lm32_addsub.v
+// Title            : PMI adder/subtractor.
+// Version          : 6.1.17
+//                  : Initial Release
+// Version          : 7.0SP2, 3.0
+//                  : No Change
+// Version          : 3.1
+//                  : No Change
+// =============================================================================
+
+`include "lm32_include.v"
+
+/////////////////////////////////////////////////////
+// Module interface
+/////////////////////////////////////////////////////
+
+module lm32_addsub (
+    // ----- Inputs -------
+    DataA, 
+    DataB, 
+    Cin, 
+    Add_Sub, 
+    // ----- Outputs -------
+    Result, 
+    Cout
+    );
+
+/////////////////////////////////////////////////////
+// Inputs
+/////////////////////////////////////////////////////
+
+input [31:0] DataA;
+input [31:0] DataB;
+input Cin;
+input Add_Sub;
+
+/////////////////////////////////////////////////////
+// Outputs
+/////////////////////////////////////////////////////
+
+output [31:0] Result;
+wire   [31:0] Result;
+output Cout;
+wire   Cout;
+
+/////////////////////////////////////////////////////
+// Instantiations
+///////////////////////////////////////////////////// 
+
+// Modified for Milkymist: removed non-portable instantiated block
+	     wire [32:0] tmp_addResult = DataA + DataB + Cin;
+	     wire [32:0] tmp_subResult = DataA - DataB - !Cin;   
+   
+	     assign  Result = (Add_Sub == 1) ? tmp_addResult[31:0] : tmp_subResult[31:0];
+	     assign  Cout = (Add_Sub == 1) ? tmp_addResult[32] : !tmp_subResult[32];
+
+endmodule
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd
new file mode 100644
index 000000000..7f416bb95
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd
@@ -0,0 +1,46 @@
+-- Work-alike to lm32_dp_ram.v, but using generic_simple_dpram
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.genram_pkg.all;
+
+entity lm32_dp_ram is
+  generic(
+    addr_width : natural := 32;
+    addr_depth : natural := 1024;
+    data_width : natural := 8);
+  port(
+    clk_i   : in std_logic;
+    rst_i   : in std_logic;
+    we_i    : in std_logic;
+    waddr_i : in  std_logic_vector(addr_width-1 downto 0);
+    wdata_i : in  std_logic_vector(data_width-1 downto 0);
+    raddr_i : in  std_logic_vector(addr_width-1 downto 0);
+    rdata_o : out std_logic_vector(data_width-1 downto 0));
+end lm32_dp_ram;
+
+architecture syn of lm32_dp_ram is
+
+  constant c_addr_width : natural := f_log2_size(addr_depth);
+
+begin
+
+  ram : generic_simple_dpram
+    generic map(
+      g_data_width               => data_width,
+      g_size                     => addr_depth,
+      g_with_byte_enable         => false,
+      g_addr_conflict_resolution => "write_first",
+      g_dual_clock               => false)
+    port map(
+      clka_i => clk_i,
+      wea_i  => we_i,
+      aa_i   => waddr_i(c_addr_width-1 downto 0),
+      da_i   => wdata_i,
+      clkb_i => clk_i,
+      ab_i   => raddr_i(c_addr_width-1 downto 0),
+      qb_o   => rdata_o);
+  
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
new file mode 100644
index 000000000..5adff9d86
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
@@ -0,0 +1,320 @@
+// =============================================================================
+//                           COPYRIGHT NOTICE
+// Copyright 2006 (c) Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// This confidential and proprietary software may be used only as authorised by
+// a licensing agreement from Lattice Semiconductor Corporation.
+// The entire notice above must be reproduced on all authorized copies and
+// copies may only be made to the extent permitted by a licensing agreement from
+// Lattice Semiconductor Corporation.
+//
+// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
+// 5555 NE Moore Court                            408-826-6000 (other locations)
+// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
+// U.S.A                                   email: techsupport@latticesemi.com
+// =============================================================================/
+//                         FILE DETAILS
+// Project          : LatticeMico32
+// File             : lm32_include.v
+// Title            : CPU global macros
+// Version          : 6.1.17
+//                  : Initial Release
+// Version          : 7.0SP2, 3.0
+//                  : No Change
+// Version          : 3.1
+//                  : No Change
+// Version          : 3.2
+//                  : No Change
+// Version          : 3.3
+//                  : Support for extended configuration register
+// =============================================================================
+
+`ifdef LM32_INCLUDE_V
+`else
+`define LM32_INCLUDE_V
+
+// Configuration options
+//`include "system_conf.v"
+
+`ifdef TRUE
+`else
+`define TRUE    1'b1
+`define FALSE   1'b0
+`define TRUE_N  1'b0
+`define FALSE_N 1'b1
+`endif
+
+// Wishbone configuration
+`ifndef CFG_IRAM_ENABLED
+`define CFG_IWB_ENABLED
+`endif
+
+`define CFG_DWB_ENABLED
+
+// Data-path width
+`define LM32_WORD_WIDTH                 32
+`define LM32_WORD_RNG                   (`LM32_WORD_WIDTH-1):0
+`define LM32_SHIFT_WIDTH                5
+`define LM32_SHIFT_RNG                  (`LM32_SHIFT_WIDTH-1):0
+`define LM32_BYTE_SELECT_WIDTH          4
+`define LM32_BYTE_SELECT_RNG            (`LM32_BYTE_SELECT_WIDTH-1):0
+
+// Register file size
+`define LM32_REGISTERS                  32
+`define LM32_REG_IDX_WIDTH              5
+`define LM32_REG_IDX_RNG                (`LM32_REG_IDX_WIDTH-1):0
+
+// Standard register numbers
+`define LM32_RA_REG                     `LM32_REG_IDX_WIDTH'd29
+`define LM32_EA_REG                     `LM32_REG_IDX_WIDTH'd30
+`define LM32_BA_REG                     `LM32_REG_IDX_WIDTH'd31
+
+// Range of Program Counter. Two LSBs are always 0. 
+`ifdef CFG_ICACHE_ENABLED
+`define LM32_PC_WIDTH                   (clogb2(`CFG_ICACHE_LIMIT-`CFG_ICACHE_BASE_ADDRESS)-2)
+`else
+`ifdef CFG_IWB_ENABLED
+`define LM32_PC_WIDTH                   (`LM32_WORD_WIDTH-2)
+`else
+`define LM32_IRAM_ADDRESS_WIDTH 32
+`define LM32_PC_WIDTH                   (`LM32_IRAM_ADDRESS_WIDTH-2)
+`endif
+`endif
+`define LM32_PC_RNG                     (`LM32_PC_WIDTH+2-1):2
+
+// Range of an instruction
+`define LM32_INSTRUCTION_WIDTH          32
+`define LM32_INSTRUCTION_RNG            (`LM32_INSTRUCTION_WIDTH-1):0
+
+// Adder operation
+`define LM32_ADDER_OP_ADD               1'b0
+`define LM32_ADDER_OP_SUBTRACT          1'b1
+
+// Shift direction
+`define LM32_SHIFT_OP_RIGHT             1'b0
+`define LM32_SHIFT_OP_LEFT              1'b1
+
+// Derive macro that indicates whether we have single-stepping or not
+`ifdef CFG_ROM_DEBUG_ENABLED
+`define LM32_SINGLE_STEP_ENABLED
+`else
+`ifdef CFG_HW_DEBUG_ENABLED
+`define LM32_SINGLE_STEP_ENABLED
+`endif
+`endif
+
+// Derive macro that indicates whether JTAG interface is required
+`ifdef CFG_JTAG_UART_ENABLED
+`define LM32_JTAG_ENABLED
+`else
+`ifdef CFG_DEBUG_ENABLED
+`define LM32_JTAG_ENABLED
+`else
+`endif
+`endif
+
+// Derive macro that indicates whether we have a barrel-shifter or not
+`ifdef CFG_PL_BARREL_SHIFT_ENABLED
+`define LM32_BARREL_SHIFT_ENABLED
+`else // CFG_PL_BARREL_SHIFT_ENABLED
+`ifdef CFG_MC_BARREL_SHIFT_ENABLED
+`define LM32_BARREL_SHIFT_ENABLED
+`else
+`define LM32_NO_BARREL_SHIFT
+`endif
+`endif // CFG_PL_BARREL_SHIFT_ENABLED
+
+// Derive macro that indicates whether we have a multiplier or not
+`ifdef CFG_PL_MULTIPLY_ENABLED
+`define LM32_MULTIPLY_ENABLED
+`else
+`ifdef CFG_MC_MULTIPLY_ENABLED
+`define LM32_MULTIPLY_ENABLED
+`endif
+`endif
+
+// Derive a macro that indicates whether or not the multi-cycle arithmetic unit is required
+`ifdef CFG_MC_DIVIDE_ENABLED
+`define LM32_MC_ARITHMETIC_ENABLED
+`endif
+`ifdef CFG_MC_MULTIPLY_ENABLED
+`define LM32_MC_ARITHMETIC_ENABLED
+`endif
+`ifdef CFG_MC_BARREL_SHIFT_ENABLED
+`define LM32_MC_ARITHMETIC_ENABLED
+`endif
+
+// Derive macro that indicates if we are using an EBR register file
+`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
+`define LM32_EBR_REGISTER_FILE
+`endif
+`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
+`define LM32_EBR_REGISTER_FILE
+`endif
+
+// Revision number
+`define LM32_REVISION                   6'h02
+
+// Logical operations - Function encoded directly in instruction
+`define LM32_LOGIC_OP_RNG               3:0
+
+// Conditions for conditional branches
+`define LM32_CONDITION_WIDTH            3
+`define LM32_CONDITION_RNG              (`LM32_CONDITION_WIDTH-1):0
+`define LM32_CONDITION_E                3'b001
+`define LM32_CONDITION_G                3'b010
+`define LM32_CONDITION_GE               3'b011
+`define LM32_CONDITION_GEU              3'b100
+`define LM32_CONDITION_GU               3'b101
+`define LM32_CONDITION_NE               3'b111
+`define LM32_CONDITION_U1               3'b000
+`define LM32_CONDITION_U2               3'b110
+
+// Size of load or store instruction - Encoding corresponds to opcode
+`define LM32_SIZE_WIDTH                 2
+`define LM32_SIZE_RNG                   1:0
+`define LM32_SIZE_BYTE                  2'b00
+`define LM32_SIZE_HWORD                 2'b11
+`define LM32_SIZE_WORD                  2'b10
+`define LM32_ADDRESS_LSBS_WIDTH         2
+
+// Width and range of a CSR index
+`ifdef CFG_DEBUG_ENABLED
+`define LM32_CSR_WIDTH                  5
+`define LM32_CSR_RNG                    (`LM32_CSR_WIDTH-1):0
+`else
+`ifdef CFG_JTAG_ENABLED
+`define LM32_CSR_WIDTH                  4
+`define LM32_CSR_RNG                    (`LM32_CSR_WIDTH-1):0
+`else
+`define LM32_CSR_WIDTH                  4 // CFG2 is "a"
+`define LM32_CSR_RNG                    (`LM32_CSR_WIDTH-1):0
+`endif
+`endif
+
+// CSR indices
+`define LM32_CSR_IE                     `LM32_CSR_WIDTH'h0
+`define LM32_CSR_IM                     `LM32_CSR_WIDTH'h1
+`define LM32_CSR_IP                     `LM32_CSR_WIDTH'h2
+`define LM32_CSR_ICC                    `LM32_CSR_WIDTH'h3
+`define LM32_CSR_DCC                    `LM32_CSR_WIDTH'h4
+`define LM32_CSR_CC                     `LM32_CSR_WIDTH'h5
+`define LM32_CSR_CFG                    `LM32_CSR_WIDTH'h6
+`define LM32_CSR_EBA                    `LM32_CSR_WIDTH'h7
+`ifdef CFG_DEBUG_ENABLED
+`define LM32_CSR_DC                     `LM32_CSR_WIDTH'h8
+`define LM32_CSR_DEBA                   `LM32_CSR_WIDTH'h9
+`endif
+`define LM32_CSR_CFG2                   `LM32_CSR_WIDTH'ha
+`define LM32_CSR_SDB                    `LM32_CSR_WIDTH'hb
+`define LM32_CSR_ERR_ADDR               `LM32_CSR_WIDTH'hc
+`ifdef CFG_JTAG_ENABLED
+`define LM32_CSR_JTX                    `LM32_CSR_WIDTH'he
+`define LM32_CSR_JRX                    `LM32_CSR_WIDTH'hf
+`endif
+`ifdef CFG_DEBUG_ENABLED
+`define LM32_CSR_BP0                    `LM32_CSR_WIDTH'h10
+`define LM32_CSR_BP1                    `LM32_CSR_WIDTH'h11
+`define LM32_CSR_BP2                    `LM32_CSR_WIDTH'h12
+`define LM32_CSR_BP3                    `LM32_CSR_WIDTH'h13
+`define LM32_CSR_WP0                    `LM32_CSR_WIDTH'h18
+`define LM32_CSR_WP1                    `LM32_CSR_WIDTH'h19
+`define LM32_CSR_WP2                    `LM32_CSR_WIDTH'h1a
+`define LM32_CSR_WP3                    `LM32_CSR_WIDTH'h1b
+`endif 
+
+// Values for WPC CSR
+`define LM32_WPC_C_RNG                  1:0
+`define LM32_WPC_C_DISABLED             2'b00
+`define LM32_WPC_C_READ                 2'b01
+`define LM32_WPC_C_WRITE                2'b10
+`define LM32_WPC_C_READ_WRITE           2'b11
+
+// Exception IDs
+`define LM32_EID_WIDTH                  3
+`define LM32_EID_RNG                    (`LM32_EID_WIDTH-1):0
+`define LM32_EID_RESET                  3'h0
+`define LM32_EID_BREAKPOINT             3'd1
+`define LM32_EID_INST_BUS_ERROR         3'h2
+`define LM32_EID_WATCHPOINT             3'd3
+`define LM32_EID_DATA_BUS_ERROR         3'h4
+`define LM32_EID_DIVIDE_BY_ZERO         3'h5
+`define LM32_EID_INTERRUPT              3'h6
+`define LM32_EID_SCALL                  3'h7
+
+// Pipeline result selection mux controls
+
+`define LM32_D_RESULT_SEL_0_RNG          0:0
+`define LM32_D_RESULT_SEL_0_REG_0        1'b0
+`define LM32_D_RESULT_SEL_0_NEXT_PC      1'b1
+
+`define LM32_D_RESULT_SEL_1_RNG          1:0
+`define LM32_D_RESULT_SEL_1_ZERO         2'b00
+`define LM32_D_RESULT_SEL_1_REG_1        2'b01
+`define LM32_D_RESULT_SEL_1_IMMEDIATE    2'b10
+
+`define LM32_USER_OPCODE_WIDTH           11
+`define LM32_USER_OPCODE_RNG             (`LM32_USER_OPCODE_WIDTH-1):0
+
+// Derive a macro to indicate if either of the caches are implemented
+`ifdef CFG_ICACHE_ENABLED
+`define LM32_CACHE_ENABLED
+`else
+`ifdef CFG_DCACHE_ENABLED
+`define LM32_CACHE_ENABLED
+`endif
+`endif
+
+/////////////////////////////////////////////////////
+// Interrupts
+/////////////////////////////////////////////////////
+
+// Currently this is fixed to 32 and should not be changed
+`define CFG_INTERRUPTS                  32
+`define LM32_INTERRUPT_WIDTH            `CFG_INTERRUPTS
+`define LM32_INTERRUPT_RNG              (`LM32_INTERRUPT_WIDTH-1):0
+
+/////////////////////////////////////////////////////
+// General
+/////////////////////////////////////////////////////
+
+// Sub-word range types
+`define LM32_BYTE_WIDTH                 8
+`define LM32_BYTE_RNG                   7:0
+`define LM32_HWORD_WIDTH                16
+`define LM32_HWORD_RNG                  15:0
+
+// Word sub-byte indicies
+`define LM32_BYTE_0_RNG                  7:0
+`define LM32_BYTE_1_RNG                  15:8
+`define LM32_BYTE_2_RNG                  23:16
+`define LM32_BYTE_3_RNG                  31:24
+
+// Word sub-halfword indices
+`define LM32_HWORD_0_RNG                 15:0
+`define LM32_HWORD_1_RNG                 31:16
+
+// Use a synchronous reset
+`define CFG_RESET_SENSITIVITY
+
+// Wishbone defines 
+// Refer to Wishbone System-on-Chip Interconnection Architecture
+// These should probably be moved to a Wishbone common file
+
+// Wishbone cycle types
+`define LM32_CTYPE_WIDTH                3
+`define LM32_CTYPE_RNG                  (`LM32_CTYPE_WIDTH-1):0
+`define LM32_CTYPE_CLASSIC              3'b000
+`define LM32_CTYPE_CONSTANT             3'b001
+`define LM32_CTYPE_INCREMENTING         3'b010
+`define LM32_CTYPE_END                  3'b111
+
+// Wishbone burst types
+`define LM32_BTYPE_WIDTH                2
+`define LM32_BTYPE_RNG                  (`LM32_BTYPE_WIDTH-1):0
+`define LM32_BTYPE_LINEAR               2'b00
+`define LM32_BTYPE_4_BEAT               2'b01
+`define LM32_BTYPE_8_BEAT               2'b10
+`define LM32_BTYPE_16_BEAT              2'b11
+
+`endif
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v
new file mode 100644
index 000000000..af1b752be
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v
@@ -0,0 +1,76 @@
+// =============================================================================
+//                           COPYRIGHT NOTICE
+// Copyright 2006 (c) Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// This confidential and proprietary software may be used only as authorised by
+// a licensing agreement from Lattice Semiconductor Corporation.
+// The entire notice above must be reproduced on all authorized copies and
+// copies may only be made to the extent permitted by a licensing agreement from
+// Lattice Semiconductor Corporation.
+//
+// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
+// 5555 NE Moore Court                            408-826-6000 (other locations)
+// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
+// U.S.A                                   email: techsupport@latticesemi.com
+// =============================================================================/
+//                         FILE DETAILS
+// Project          : LatticeMico32
+// File             : lm32_logic_op.v
+// Title            : Logic operations (and / or / not etc)
+// Dependencies     : lm32_include.v
+// Version          : 6.1.17
+//                  : Initial Release
+// Version          : 7.0SP2, 3.0
+//                  : No Change
+// Version          : 3.1
+//                  : No Change
+// =============================================================================
+
+`include "lm32_include.v"
+
+/////////////////////////////////////////////////////
+// Module interface
+/////////////////////////////////////////////////////
+
+module lm32_logic_op (
+    // ----- Inputs -------
+    logic_op_x,
+    operand_0_x,
+    operand_1_x,
+    // ----- Outputs -------
+    logic_result_x
+    );
+
+/////////////////////////////////////////////////////
+// Inputs
+/////////////////////////////////////////////////////
+
+input [`LM32_LOGIC_OP_RNG] logic_op_x;
+input [`LM32_WORD_RNG] operand_0_x;
+input [`LM32_WORD_RNG] operand_1_x;
+
+/////////////////////////////////////////////////////
+// Outputs
+/////////////////////////////////////////////////////
+
+output [`LM32_WORD_RNG] logic_result_x;
+reg    [`LM32_WORD_RNG] logic_result_x;
+    
+/////////////////////////////////////////////////////
+// Internal nets and registers 
+/////////////////////////////////////////////////////
+
+integer logic_idx;
+
+/////////////////////////////////////////////////////
+// Combinational Logic
+/////////////////////////////////////////////////////
+
+always @(*)
+begin
+    for(logic_idx = 0; logic_idx < `LM32_WORD_WIDTH; logic_idx = logic_idx + 1)
+        logic_result_x[logic_idx] = logic_op_x[{operand_1_x[logic_idx], operand_0_x[logic_idx]}];
+end
+    
+endmodule
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd
new file mode 100644
index 000000000..e39dbb999
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd
@@ -0,0 +1,66 @@
+-- Work-alike to lm32_ram.v, but using generic_simple_dpram
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.genram_pkg.all;
+
+entity lm32_ram is
+  generic(
+    data_width    : natural := 1;
+    address_width : natural := 1);
+  port(
+    read_clk      : in  std_logic;
+    write_clk     : in  std_logic;
+    reset         : in  std_logic;
+    enable_read   : in  std_logic;
+    read_address  : in  std_logic_vector(address_width-1 downto 0);
+    enable_write  : in  std_logic;
+    write_address : in  std_logic_vector(address_width-1 downto 0);
+    write_data    : in  std_logic_vector(data_width   -1 downto 0);
+    write_enable  : in  std_logic;
+    read_data     : out std_logic_vector(data_width   -1 downto 0));
+end lm32_ram;
+
+architecture syn of lm32_ram is
+  
+  signal wea : std_logic;
+  signal reb : std_logic;
+  
+  -- Emulate read-enable using another bypass
+  signal old_data : std_logic_vector(data_width-1 downto 0);
+  signal new_data : std_logic_vector(data_width-1 downto 0);
+  signal data     : std_logic_vector(data_width-1 downto 0);
+
+begin
+  
+  wea <= enable_write and write_enable;
+  ram : generic_simple_dpram
+    generic map(
+      g_data_width               => data_width,
+      g_size                     => 2**address_width,
+      g_with_byte_enable         => false,
+      g_addr_conflict_resolution => "write_first",
+      g_dual_clock               => false) -- read_clk always = write_clk in LM32
+    port map(
+      clka_i => read_clk,
+      wea_i  => wea,
+      aa_i   => write_address,
+      da_i   => write_data,
+      clkb_i => write_clk,
+      ab_i   => read_address,
+      qb_o   => new_data);
+  
+  data <= old_data when reb='0' else new_data;
+  read_data <= data;
+  
+  main : process(read_clk) is
+  begin
+    if rising_edge(read_clk) then
+      old_data <= data;
+      reb <= enable_read;
+    end if;
+  end process;
+  
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v
new file mode 100644
index 000000000..a9f0892b9
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v
@@ -0,0 +1,138 @@
+// =============================================================================
+//                           COPYRIGHT NOTICE
+// Copyright 2006 (c) Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// This confidential and proprietary software may be used only as authorised by
+// a licensing agreement from Lattice Semiconductor Corporation.
+// The entire notice above must be reproduced on all authorized copies and
+// copies may only be made to the extent permitted by a licensing agreement from
+// Lattice Semiconductor Corporation.
+//
+// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
+// 5555 NE Moore Court                            408-826-6000 (other locations)
+// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
+// U.S.A                                   email: techsupport@latticesemi.com
+// =============================================================================/
+//                         FILE DETAILS
+// Project          : LatticeMico32
+// File             : lm32_shifter.v
+// Title            : Barrel shifter
+// Dependencies     : lm32_include.v
+// Version          : 6.1.17
+//                  : Initial Release
+// Version          : 7.0SP2, 3.0
+//                  : No Change
+// Version          : 3.1
+//                  : No Change
+// =============================================================================
+
+`include "lm32_include.v"
+
+/////////////////////////////////////////////////////
+// Module interface
+/////////////////////////////////////////////////////
+
+module lm32_shifter (
+    // ----- Inputs -------
+    clk_i,
+    rst_i,
+    stall_x,
+    direction_x,
+    sign_extend_x,
+    operand_0_x,
+    operand_1_x,
+    // ----- Outputs -------
+    shifter_result_m
+    );
+
+/////////////////////////////////////////////////////
+// Inputs
+/////////////////////////////////////////////////////
+
+input clk_i;                                // Clock
+input rst_i;                                // Reset
+input stall_x;                              // Stall instruction in X stage
+input direction_x;                          // Direction to shift
+input sign_extend_x;                        // Whether shift is arithmetic (1'b1) or logical (1'b0)
+input [`LM32_WORD_RNG] operand_0_x;         // Operand to shift
+input [`LM32_WORD_RNG] operand_1_x;         // Operand that specifies how many bits to shift by
+
+/////////////////////////////////////////////////////
+// Outputs
+/////////////////////////////////////////////////////
+
+output [`LM32_WORD_RNG] shifter_result_m;   // Result of shift
+wire   [`LM32_WORD_RNG] shifter_result_m;
+
+/////////////////////////////////////////////////////
+// Internal nets and registers 
+/////////////////////////////////////////////////////
+
+reg direction_m;
+wire [`LM32_WORD_WIDTH*2-1:0] right_shift_result_x;
+reg [`LM32_WORD_RNG] left_shift_result;
+reg [`LM32_WORD_RNG] right_shift_result_m;
+reg [`LM32_WORD_RNG] left_shift_operand;
+wire [`LM32_WORD_RNG] right_shift_operand;
+wire fill_value;
+wire [`LM32_WORD_RNG] right_shift_in;
+
+integer shift_idx_0;
+integer shift_idx_1;
+
+/////////////////////////////////////////////////////
+// Combinational Logic
+/////////////////////////////////////////////////////
+    
+// Select operands - To perform a left shift, we reverse the bits and perform a right shift
+always @(*)
+begin
+    for (shift_idx_0 = 0; shift_idx_0 < `LM32_WORD_WIDTH; shift_idx_0 = shift_idx_0 + 1)
+        left_shift_operand[`LM32_WORD_WIDTH-1-shift_idx_0] = operand_0_x[shift_idx_0];
+end
+assign right_shift_operand = direction_x == `LM32_SHIFT_OP_LEFT ? left_shift_operand : operand_0_x;
+
+// Determine fill value for right shift - Sign bit for arithmetic shift, or zero for logical shift
+assign fill_value = (sign_extend_x == `TRUE) && (direction_x == `LM32_SHIFT_OP_RIGHT) 
+                      ? operand_0_x[`LM32_WORD_WIDTH-1] 
+                      : 1'b0;
+
+// Determine bits to shift in for right shift or rotate
+assign right_shift_in = {`LM32_WORD_WIDTH{fill_value}};
+
+// Determine the result of the shifter
+assign right_shift_result_x = {right_shift_in, right_shift_operand} >> operand_1_x[`LM32_SHIFT_RNG];
+
+// Reverse bits to get left shift result
+always @(*)
+begin
+    for (shift_idx_1 = 0; shift_idx_1 < `LM32_WORD_WIDTH; shift_idx_1 = shift_idx_1 + 1)
+        left_shift_result[`LM32_WORD_WIDTH-1-shift_idx_1] = right_shift_result_m[shift_idx_1];
+end
+
+// Select result 
+assign shifter_result_m = direction_m == `LM32_SHIFT_OP_LEFT ? left_shift_result : right_shift_result_m;
+    
+/////////////////////////////////////////////////////
+// Sequential Logic
+/////////////////////////////////////////////////////
+
+// Perform right shift
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+    if (rst_i == `TRUE)
+    begin
+        right_shift_result_m <= {`LM32_WORD_WIDTH{1'b0}};
+        direction_m <= `FALSE;
+    end
+    else
+    begin
+        if (stall_x == `FALSE)
+        begin
+            right_shift_result_m <= right_shift_result_x[`LM32_WORD_RNG];
+            direction_m <= direction_x;
+        end
+    end
+end 
+    
+endmodule
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v
new file mode 100644
index 000000000..b7d0abba9
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v
@@ -0,0 +1,432 @@
+//////////////////////////////////////////////////////////////////////////////
+//                                                                          //
+//  Minimalistic 1-wire (onewire) master with Avalon MM bus interface       //
+//                                                                          //
+//  Copyright (C) 2010  Iztok Jeras                                         //
+//                                                                          //
+//////////////////////////////////////////////////////////////////////////////
+//                                                                          //
+//  This RTL is free hardware: you can redistribute it and/or modify        //
+//  it under the terms of the GNU Lesser General Public License             //
+//  as published by the Free Software Foundation, either                    //
+//  version 3 of the License, or (at your option) any later version.        //
+//                                                                          //
+//  This RTL is distributed in the hope that it will be useful,             //
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of          //
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the           //
+//  GNU General Public License for more details.                            //
+//                                                                          //
+//  You should have received a copy of the GNU General Public License       //
+//  along with this program.  If not, see <http://www.gnu.org/licenses/>.   //
+//                                                                          //
+//////////////////////////////////////////////////////////////////////////////
+
+//////////////////////////////////////////////////////////////////////////////
+//  Modifications:
+//      2016-08-24: by Jan Pospisil (j.pospisil@cern.ch)
+//          * added default values; typos
+//////////////////////////////////////////////////////////////////////////////
+
+//////////////////////////////////////////////////////////////////////////////
+//                                                                          //
+// The clock divider parameter is computed with the next formula:           //
+//                                                                          //
+// CDR_N = f_CLK * BTP_N - 1  (example: CDR_N = 1MHz * 5.0us - 1 = 5-1)     //
+// CDR_O = f_CLK * BTP_O - 1  (example: CDR_O = 1MHz * 1.0us - 1 = 1-1)     //
+//                                                                          //
+// If the dividing factor is not a round integer, than the timing of the    //
+// controller will be slightly off, and would support only a subset of      //
+// 1-wire devices with timing closer to the typical 30us slot.              //
+//                                                                          //
+// Base time periods BTP_N = "5.0" and BTP_O = "1.0" are optimized for      //
+// onewire timing. The default timing restricts the range of available      //
+// frequences to multiples of 1MHz.                                         //
+//                                                                          //
+// If even this restrictions are too strict use timing BTP_N = "6.0" and    //
+// BTP_O = "0.5", where the actual periods can be in the range:             //
+// 6.0us <= BTP_N <= 7.5us                                                  //
+// 0.5us <= BTP_O <= 0.66us                                                 //
+//                                                                          //
+// A third timing option is available for normal mode BTP_N = "7.5", this   //
+// option is optimized for logic size.                                      //
+//                                                                          //
+//////////////////////////////////////////////////////////////////////////////
+
+module sockit_owm #(
+  // enable implementation of optional functionality
+  parameter OVD_E =    1,  // overdrive functionality is implemented by default
+  parameter CDR_E =    1,  // clock divider register is implemented by default
+  // interface parameters
+  parameter BDW   =   32,  // bus data width
+  parameter OWN   =    1,  // number of 1-wire ports
+  // computed bus address port width
+`ifdef __ICARUS__
+  parameter BAW   = (BDW==32) ? 1 : 2,
+`else
+  parameter BAW   = 1,  // TODO, the above is correct, but does not work well with Altera SOPC Builder
+`endif
+  // base time period
+  parameter BTP_N = "5.0", // normal    mode (5.0us, options are "7.5", "5.0" and "6.0")
+  parameter BTP_O = "0.5", // overdrive mode (1.0us, options are "1.0",       and "0.5")
+  // normal mode timing
+  parameter T_RSTH_N = (BTP_N == "7.5") ?  64 : (BTP_N == "5.0") ?  96 :  80,  // reset high
+  parameter T_RSTL_N = (BTP_N == "7.5") ?  64 : (BTP_N == "5.0") ?  96 :  80,  // reset low
+  parameter T_RSTP_N = (BTP_N == "7.5") ?  10 : (BTP_N == "5.0") ?  15 :  10,  // reset presence pulse
+  parameter T_DAT0_N = (BTP_N == "7.5") ?   8 : (BTP_N == "5.0") ?  12 :  10,  // bit 0 low
+  parameter T_DAT1_N = (BTP_N == "7.5") ?   1 : (BTP_N == "5.0") ?   1 :   1,  // bit 1 low
+  parameter T_BITS_N = (BTP_N == "7.5") ?   2 : (BTP_N == "5.0") ?   3 :   2,  // bit sample
+  parameter T_RCVR_N = (BTP_N == "7.5") ?   1 : (BTP_N == "5.0") ?   1 :   1,  // recovery
+  parameter T_IDLE_N = (BTP_N == "7.5") ? 128 : (BTP_N == "5.0") ? 200 : 160,  // idle timer
+  // overdrive mode timing
+  parameter T_RSTH_O = (BTP_O == "1.0") ?  48 :  96,  // reset high
+  parameter T_RSTL_O = (BTP_O == "1.0") ?  48 :  96,  // reset low
+  parameter T_RSTP_O = (BTP_O == "1.0") ?  10 :  15,  // reset presence pulse
+  parameter T_DAT0_O = (BTP_O == "1.0") ?   6 :  12,  // bit 0 low
+  parameter T_DAT1_O = (BTP_O == "1.0") ?   1 :   2,  // bit 1 low
+  parameter T_BITS_O = (BTP_O == "1.0") ?   2 :   3,  // bit sample
+  parameter T_RCVR_O = (BTP_O == "1.0") ?   2 :   4,  // recovery
+  parameter T_IDLE_O = (BTP_O == "1.0") ?  96 : 192,  // idle timer
+  // clock divider ratios (defaults are for a 1MHz clock)
+  parameter CDR_N = 5-1,  // normal    mode
+  parameter CDR_O = 1-1   // overdrive mode
+)(
+  // system signals
+  input            clk,
+  input            rst,
+  // CPU bus interface
+  input            bus_ren,  // read  enable
+  input            bus_wen,  // write enable
+  input  [BAW-1:0] bus_adr,  // address
+  input  [BDW-1:0] bus_wdt,  // write data
+  output [BDW-1:0] bus_rdt,  // read  data
+  output           bus_irq,  // interrupt request
+  // 1-wire interface
+  output [OWN-1:0] owr_p,    // output power enable
+  output [OWN-1:0] owr_e,    // output pull down enable
+  input  [OWN-1:0] owr_i     // input from bidirectional wire
+);
+
+//////////////////////////////////////////////////////////////////////////////
+// local parameters
+//////////////////////////////////////////////////////////////////////////////
+
+function integer clogb2;               
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+     value = value >> 1;
+end
+endfunction
+
+// size of combined power and select registers
+localparam PDW = (BDW==32) ? 24 : 8;
+
+// size of boudrate generator counter (divider for normal mode is largest)
+localparam CDW = CDR_E ? ((BDW==32) ? 16 : 8) : clogb2(CDR_N);
+
+// size of port select signal
+localparam SDW = clogb2(OWN);
+
+// size of cycle timing counter
+localparam TDW =       (T_RSTH_O+T_RSTL_O) >       (T_RSTH_N+T_RSTL_N)
+               ? clogb2(T_RSTH_O+T_RSTL_O) : clogb2(T_RSTH_N+T_RSTL_N);
+
+//////////////////////////////////////////////////////////////////////////////
+// local signals
+//////////////////////////////////////////////////////////////////////////////
+
+// address dependent write enable
+wire bus_ren_ctl_sts;
+wire bus_wen_ctl_sts;
+wire bus_wen_pwr_sel;
+wire bus_wen_cdr_n;
+wire bus_wen_cdr_o;
+
+// read data bus segments
+wire     [7:0] bus_rdt_ctl_sts;
+wire [PDW-1:0] bus_rdt_pwr_sel;
+
+// clock divider
+reg  [CDW-1:0] div;
+reg  [CDW-1:0] cdr_n = CDR_N[CDW-1:0];
+reg  [CDW-1:0] cdr_o = CDR_O[CDW-1:0];
+wire           pls;
+
+// cycle control and status
+reg            owr_cyc;  // cycle status
+reg  [TDW-1:0] cnt;      // cycle counter
+
+// port select
+//generate if (OWN>1) begin : sel_declaration
+reg  [SDW-1:0] owr_sel;
+//end endgenerate
+
+// modified input data for overdrive
+wire           req_ovd;
+
+// onewire signals
+reg  [OWN-1:0] owr_pwr;  // power
+reg            owr_ovd;  // overdrive
+reg            owr_rst;  // reset
+reg            owr_dat;  // data bit
+reg            owr_smp;  // sample bit
+
+reg            owr_oen;  // output enable
+wire           owr_iln;  // input line
+
+// interrupt signals
+reg            irq_ena;  // interrupt enable
+reg            irq_sts;  // interrupt status
+
+// timing signals
+wire [TDW-1:0] t_idl ;   // idle                 cycle    time
+wire [TDW-1:0] t_rst ;   // reset                cycle    time
+wire [TDW-1:0] t_bit ;   // data bit             cycle    time
+wire [TDW-1:0] t_rstp;   // reset presence pulse sampling time
+wire [TDW-1:0] t_rsth;   // reset                release  time
+wire [TDW-1:0] t_dat0;   // data bit 0           release  time
+wire [TDW-1:0] t_dat1;   // data bit 1           release  time
+wire [TDW-1:0] t_bits;   // data bit             sampling time
+wire [TDW-1:0] t_zero;   // end of               cycle    time
+
+//////////////////////////////////////////////////////////////////////////////
+// cycle timing
+//////////////////////////////////////////////////////////////////////////////
+
+// idle time
+assign t_idl  = req_ovd ? T_IDLE_O[TDW-1:0]                         : T_IDLE_N[TDW-1:0];
+// reset cycle time (reset low + reset hight)
+assign t_rst  = req_ovd ? T_RSTL_O[TDW-1:0] + T_RSTH_O[TDW-1:0]     : T_RSTL_N[TDW-1:0] + T_RSTH_N[TDW-1:0];
+// data bit cycle time (write 0 + recovery)
+assign t_bit  = req_ovd ? T_DAT0_O[TDW-1:0] + T_RCVR_O[TDW-1:0]     : T_DAT0_N[TDW-1:0] + T_RCVR_N[TDW-1:0];
+
+// reset presence pulse sampling time (reset high - reset presence)
+assign t_rstp = owr_ovd ? T_RSTH_O[TDW-1:0] - T_RSTP_O[TDW-1:0]     : T_RSTH_N[TDW-1:0] - T_RSTP_N[TDW-1:0];
+// reset      release time (reset high)
+assign t_rsth = owr_ovd ? T_RSTH_O[TDW-1:0]                         : T_RSTH_N[TDW-1:0];
+
+// data bit 0 release time (write bit 0 - write bit 0 + recovery)
+assign t_dat0 = owr_ovd ? T_DAT0_O[TDW-1:0] - T_DAT0_O[TDW-1:0] + T_RCVR_O[TDW-1:0] : T_DAT0_N[TDW-1:0] - T_DAT0_N[TDW-1:0] + T_RCVR_N[TDW-1:0];
+// data bit 1 release time (write bit 0 - write bit 1 + recovery)
+assign t_dat1 = owr_ovd ? T_DAT0_O[TDW-1:0] - T_DAT1_O[TDW-1:0] + T_RCVR_O[TDW-1:0] : T_DAT0_N[TDW-1:0] - T_DAT1_N[TDW-1:0] + T_RCVR_N[TDW-1:0];
+// data bit sampling time (write bit 0 - write bit 1 + recovery)
+assign t_bits = owr_ovd ? T_DAT0_O[TDW-1:0] - T_BITS_O[TDW-1:0] + T_RCVR_O[TDW-1:0] : T_DAT0_N[TDW-1:0] - T_BITS_N[TDW-1:0] + T_RCVR_N[TDW-1:0];
+
+// end of cycle time
+assign t_zero = 'd0;
+
+//////////////////////////////////////////////////////////////////////////////
+// bus read
+//////////////////////////////////////////////////////////////////////////////
+
+// bus segnemt - controll/status register
+assign bus_rdt_ctl_sts = {irq_ena, irq_sts, 1'b0, owr_pwr[0], owr_cyc, owr_ovd, owr_rst, owr_dat};
+
+// bus segnemt - power and select register
+generate
+  if (BDW==32) begin
+    if (OWN>1) begin
+      assign bus_rdt_pwr_sel = {{16-OWN{1'b0}}, owr_pwr, 4'h0, {4-SDW{1'b0}}, owr_sel};
+    end else begin
+      assign bus_rdt_pwr_sel = 24'h0000_00;
+    end
+  end else if (BDW==8) begin
+    if (OWN>1) begin
+      assign bus_rdt_pwr_sel = {{ 4-OWN{1'b0}}, owr_pwr,       {4-SDW{1'b0}}, owr_sel};
+    end else begin
+      assign bus_rdt_pwr_sel = 8'hxx;
+    end
+  end
+endgenerate
+
+// bus read data
+generate if (BDW==32) begin
+  assign bus_rdt = (bus_adr[0]==1'b0) ? {bus_rdt_pwr_sel, bus_rdt_ctl_sts} : (cdr_o << 16 | cdr_n);
+end else if (BDW==8) begin
+  assign bus_rdt = (bus_adr[1]==1'b0) ? ((bus_adr[0]==1'b0) ? bus_rdt_ctl_sts
+                                                            : bus_rdt_pwr_sel)
+                                      : ((bus_adr[0]==1'b0) ? cdr_n
+                                                            : cdr_o          );
+end endgenerate
+
+//////////////////////////////////////////////////////////////////////////////
+// bus write
+//////////////////////////////////////////////////////////////////////////////
+
+// combined write/read enable and address decoder
+generate if (BDW==32) begin
+  assign bus_ren_ctl_sts = bus_ren & bus_adr[0] == 1'b0;
+  assign bus_wen_ctl_sts = bus_wen & bus_adr[0] == 1'b0;
+  assign bus_wen_pwr_sel = bus_wen & bus_adr[0] == 1'b0;
+  assign bus_wen_cdr_n   = bus_wen & bus_adr[0] == 1'b1;
+  assign bus_wen_cdr_o   = bus_wen & bus_adr[0] == 1'b1;
+end else if (BDW==8) begin
+  assign bus_ren_ctl_sts = bus_ren & bus_adr[1:0] == 2'b00;
+  assign bus_wen_ctl_sts = bus_wen & bus_adr[1:0] == 2'b00;
+  assign bus_wen_pwr_sel = bus_wen & bus_adr[1:0] == 2'b01;
+  assign bus_wen_cdr_n   = bus_wen & bus_adr[1:0] == 2'b10;
+  assign bus_wen_cdr_o   = bus_wen & bus_adr[1:0] == 2'b11;
+end endgenerate
+
+//////////////////////////////////////////////////////////////////////////////
+// clock divider
+//////////////////////////////////////////////////////////////////////////////
+
+// clock divider ratio registers
+generate
+  if (CDR_E) begin
+    if (BDW==32) begin
+      always @ (posedge clk, posedge rst)
+      if (rst) begin
+        cdr_n <= CDR_N[CDW-1:0];
+        cdr_o <= CDR_O[CDW-1:0];
+      end else begin
+        if (bus_wen_cdr_n)  cdr_n <= bus_wdt[15: 0];
+        if (bus_wen_cdr_o)  cdr_o <= bus_wdt[31:16];
+      end
+    end else if (BDW==8) begin
+      always @ (posedge clk, posedge rst)
+      if (rst) begin
+        cdr_n <= CDR_N[CDW-1:0];
+        cdr_o <= CDR_O[CDW-1:0];
+      end else begin
+        if (bus_wen_cdr_n)  cdr_n <= bus_wdt;
+        if (bus_wen_cdr_o)  cdr_o <= bus_wdt;
+      end
+    end
+  end else begin
+    initial begin
+      cdr_n = CDR_N[CDW-1:0];
+      cdr_o = CDR_O[CDW-1:0];
+    end
+  end
+endgenerate
+
+// clock divider
+always @ (posedge clk, posedge rst)
+if (rst)        div <= {CDW{1'd0}};
+else begin
+  if (bus_wen)  div <= {CDW{1'd0}};
+  else          div <= pls ? {CDW{1'd0}} : div + owr_cyc;
+end
+
+// divided clock pulse
+assign pls = (div == (owr_ovd ? cdr_o : cdr_n));
+
+//////////////////////////////////////////////////////////////////////////////
+// power and select register
+//////////////////////////////////////////////////////////////////////////////
+
+// select and power register implementation
+generate if (OWN>1) begin : sel_implementation
+  // port select
+  always @ (posedge clk, posedge rst)
+  if (rst)                   owr_sel <= {SDW{1'b0}};
+  else if (bus_wen_pwr_sel)  owr_sel <= bus_wdt[(BDW==32 ?  8 : 0)+:SDW];
+  
+  // power delivery
+  always @ (posedge clk, posedge rst)
+  if (rst)                   owr_pwr <= {OWN{1'b0}};
+  else if (bus_wen_pwr_sel)  owr_pwr <= bus_wdt[(BDW==32 ? 16 : 4)+:OWN];
+end else begin
+  // port select
+  initial                    owr_sel <= 'd0; 
+  // power delivery
+  always @ (posedge clk, posedge rst)
+  if (rst)                   owr_pwr <= 1'b0;
+  else if (bus_wen_ctl_sts)  owr_pwr <= bus_wdt[4];
+end endgenerate
+
+//////////////////////////////////////////////////////////////////////////////
+// interrupt logic
+//////////////////////////////////////////////////////////////////////////////
+
+// bus interrupt
+assign bus_irq = irq_ena & irq_sts;
+
+// interrupt enable
+always @ (posedge clk, posedge rst)
+if (rst)                   irq_ena <= 1'b0;     
+else if (bus_wen_ctl_sts)  irq_ena <= bus_wdt[7]; 
+
+// transmit status (active after onewire cycle ends)
+always @ (posedge clk, posedge rst)
+if (rst)                           irq_sts <= 1'b0;
+else begin
+  if (bus_wen_ctl_sts)             irq_sts <= 1'b0;
+  else if (pls & (cnt == t_zero))  irq_sts <= 1'b1;
+  else if (bus_ren_ctl_sts)        irq_sts <= 1'b0;
+end
+
+//////////////////////////////////////////////////////////////////////////////
+// onewire state machine
+//////////////////////////////////////////////////////////////////////////////
+
+assign req_ovd = OVD_E ? bus_wen_ctl_sts & bus_wdt[2] : 1'b0; 
+
+// overdrive
+always @ (posedge clk, posedge rst)
+if (rst)                   owr_ovd <= 1'b0;
+else if (bus_wen_ctl_sts)  owr_ovd <= req_ovd;
+
+// reset
+always @ (posedge clk, posedge rst)
+if (rst)                   owr_rst <= 1'b0;
+else if (bus_wen_ctl_sts)  owr_rst <= bus_wdt[1];
+
+// transmit data, reset, overdrive
+always @ (posedge clk, posedge rst)
+if (rst)                           owr_dat <= 1'b0;
+else begin
+  if (bus_wen_ctl_sts)             owr_dat <= bus_wdt[0];
+  else if (pls & (cnt == t_zero))  owr_dat <= owr_smp;
+end
+
+// onewire cycle status
+always @ (posedge clk, posedge rst)
+if (rst)                           owr_cyc <= 1'b0;
+else begin
+  if (bus_wen_ctl_sts)             owr_cyc <= bus_wdt[3] & ~&bus_wdt[2:0];
+  else if (pls & (cnt == t_zero))  owr_cyc <= 1'b0;
+end
+
+// state counter (initial value depends whether the cycle is reset or data)
+always @ (posedge clk, posedge rst)
+if (rst)                 cnt <= 0;
+else begin
+  if (bus_wen_ctl_sts)   cnt <= (&bus_wdt[1:0] ? t_idl : bus_wdt[1] ? t_rst : t_bit) - 1'd1;
+  else if (pls)          cnt <= cnt - 1'd1;
+end
+
+// receive data (sampling point depends whether the cycle is reset or data)
+always @ (posedge clk)
+if (pls) begin
+  if      ( owr_rst & (cnt == t_rstp))  owr_smp <= owr_iln;  // presence detect
+  else if (~owr_rst & (cnt == t_bits))  owr_smp <= owr_iln;  // read data bit
+end
+
+// output register (switch point depends whether the cycle is reset or data)
+always @ (posedge clk, posedge rst)
+if (rst)                                owr_oen <= 1'b0;
+else begin
+  if (bus_wen_ctl_sts)                  owr_oen <= ~&bus_wdt[1:0];
+  else if (pls) begin
+    if      (owr_rst & (cnt == t_rsth)) owr_oen <= 1'b0;  // reset
+    else if (owr_dat & (cnt == t_dat1)) owr_oen <= 1'b0;  // write 1, read
+    else if (          (cnt == t_dat0)) owr_oen <= 1'b0;  // write 0
+  end
+end
+
+//////////////////////////////////////////////////////////////////////////////
+// IO
+//////////////////////////////////////////////////////////////////////////////
+
+// only one 1-wire line can be accessed at the same time
+assign owr_e   = owr_oen << owr_sel;
+// all 1-wire lines can be powered independently
+assign owr_p   = owr_pwr;
+
+// 1-wire line status read multiplexer
+assign owr_iln = owr_i [owr_sel];
+
+endmodule
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
new file mode 100644
index 000000000..b1f5d60b7
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
@@ -0,0 +1,184 @@
+------------------------------------------------------------------------------
+-- Title      : Wishbone 1-Wire Master
+-- Project    : General Cores Library (gencores)
+------------------------------------------------------------------------------
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-Co-HT
+-- Created    : 2010-05-18
+-- Last update: 2012-02-23
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Wishbone Dallas/Maxim Semiconductor 1-Wire master.
+-------------------------------------------------------------------------------
+-- 
+-- Based on sockit_owm project Copyright (c) 2010 Iztok Jeras.
+-- http://opencores.org/project,sockit_owm
+--
+-- sockit_owm RTL is licensed under LGPL 3.
+
+-- wb_onewire_master.vhd copyright (c) 2011 CERN
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2011-09-18  1.0      twlostow        Created
+-- 2016-08-24  1.1      jpospisi        propagated CDR_N/O generics up the
+--                                        hierarchy; added assignments to (new)
+--                                        unspecified WB signals
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.STD_LOGIC_1164.all;
+
+use work.gencores_pkg.all;
+use work.wishbone_pkg.all;
+
+entity wb_onewire_master is
+
+  generic(
+    g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
+    g_address_granularity : t_wishbone_address_granularity := WORD;
+    g_num_ports           : integer                        := 1;
+    g_ow_btp_normal       : string                         := "5.0";
+    g_ow_btp_overdrive    : string                         := "1.0";
+    g_CDR_N               : integer                        := 4; -- normal    mode
+    g_CDR_O               : integer                        := 0  -- overdrive mode
+    );  
+
+  port (
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    wb_cyc_i   : in  std_logic;
+    wb_sel_i   : in  std_logic_vector(c_wishbone_data_width/8-1 downto 0);
+    wb_stb_i   : in  std_logic;
+    wb_we_i    : in  std_logic;
+    wb_adr_i   : in  std_logic_vector(2 downto 0);
+    wb_dat_i   : in  std_logic_vector(c_wishbone_data_width-1 downto 0);
+    wb_dat_o   : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+    wb_ack_o   : out std_logic;
+    wb_int_o   : out std_logic;
+    wb_stall_o : out std_logic;
+
+    owr_pwren_o : out std_logic_vector(g_num_ports -1 downto 0);
+    owr_en_o    : out std_logic_vector(g_num_ports -1 downto 0);
+    owr_i       : in  std_logic_vector(g_num_ports -1 downto 0)
+    );
+
+end wb_onewire_master;
+
+
+architecture rtl of wb_onewire_master is
+
+  component sockit_owm
+    generic(
+      BTP_N : string;
+      BTP_O : string;
+      OWN   : integer;
+      CDR_N : integer;
+      CDR_O : integer);
+
+    port(
+      clk     : in  std_logic;
+      rst     : in  std_logic;
+      bus_ren : in  std_logic;
+      bus_wen : in  std_logic;
+      bus_adr : in  std_logic_vector(0 downto 0);
+      bus_wdt : in  std_logic_vector(31 downto 0);
+      bus_rdt : out std_logic_vector(31 downto 0);
+      bus_irq : out std_logic;
+      owr_p   : out std_logic_vector(OWN-1 downto 0);
+      owr_e   : out std_logic_vector(OWN-1 downto 0);
+      owr_i   : in  std_logic_vector(OWN-1 downto 0)
+      );
+  end component;
+
+  signal bus_wen : std_logic;
+  signal bus_ren : std_logic;
+  signal rst     : std_logic;
+
+  signal slave_in  : t_wishbone_slave_in;
+  signal slave_out : t_wishbone_slave_out;
+
+  signal adp_out : t_wishbone_master_out;
+  signal adp_in  : t_wishbone_master_in;
+
+  signal rdat_int : std_logic_vector(31 downto 0);
+  
+begin  -- rtl
+
+  slave_in.adr(2 downto 0)                          <= wb_adr_i;
+  slave_in.adr(c_wishbone_address_width-1 downto 3) <= (others => '0');
+  slave_in.cyc                                      <= wb_cyc_i;
+  slave_in.stb                                      <= wb_stb_i;
+  slave_in.sel                                      <= wb_sel_i;
+  slave_in.dat                                      <= wb_dat_i;
+  slave_in.we                                       <= wb_we_i;
+
+  wb_int_o   <= slave_out.int;
+  wb_dat_o   <= slave_out.dat;
+  wb_stall_o <= slave_out.stall;
+  wb_ack_o   <= slave_out.ack;
+
+
+  U_Slave_adapter : wb_slave_adapter
+    generic map (
+      g_master_use_struct  => true,
+      g_master_mode        => CLASSIC,
+      g_master_granularity => WORD,
+      g_slave_use_struct   => true,
+      g_slave_mode         => g_interface_mode,
+      g_slave_granularity  => g_address_granularity)
+    port map (
+      clk_sys_i => clk_sys_i,
+      rst_n_i   => rst_n_i,
+
+      slave_i  => slave_in,
+      slave_o  => slave_out,
+      master_i => adp_in,
+      master_o => adp_out);
+
+  
+  bus_wen <= adp_out.cyc and adp_out.stb and adp_out.we and not adp_in.ack;
+  bus_ren <= adp_out.cyc and adp_out.stb and not (adp_out.we or adp_in.ack);
+
+  process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        adp_in.ack <= '0';
+      else
+        adp_in.ack <= adp_out.stb and adp_out.cyc and not adp_in.ack;
+        adp_in.dat <= rdat_int;
+      end if;
+    end if;
+  end process;
+
+  rst <= not rst_n_i;
+
+  Wrapped_1wire : sockit_owm
+    generic map (
+      BTP_N => g_ow_btp_normal,
+      BTP_O => g_ow_btp_overdrive,
+      OWN   => g_num_ports,
+      CDR_N => g_CDR_N,
+      CDR_O => g_CDR_O)
+    port map (
+      clk     => clk_sys_i,
+      rst     => rst,
+      bus_ren => bus_ren,
+      bus_wen => bus_wen,
+      bus_adr => adp_out.adr(0 downto 0),
+      bus_wdt => adp_out.dat,
+      bus_rdt => rdat_int,
+      bus_irq => adp_in.int,
+      owr_p   => owr_pwren_o,
+      owr_e   => owr_en_o,
+      owr_i   => owr_i);
+
+  adp_in.err <= '0';
+  adp_in.rty <= '0';
+  adp_in.stall <= '0';
+
+end rtl;
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd
new file mode 100644
index 000000000..3920efd20
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd
@@ -0,0 +1,105 @@
+--------------------------------------------------------------------------------
+--  Modifications:
+--      2016-08-24: by Jan Pospisil (j.pospisil@cern.ch)
+--          * propagated CDR_N/O generics up the hierarchy; added assignments
+--            to (new) unspecified WB signals
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.wishbone_pkg.all;
+
+entity xwb_onewire_master is
+  generic(
+    g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
+    g_address_granularity : t_wishbone_address_granularity := WORD;
+    g_num_ports           : integer                        := 1;
+    g_ow_btp_normal       : string                         := "5.0";
+    g_ow_btp_overdrive    : string                         := "1.0";
+    g_CDR_N               : integer                        := 4; -- normal    mode
+    g_CDR_O               : integer                        := 0  -- overdrive mode
+    );
+
+  port(
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    -- Wishbone
+    slave_i : in  t_wishbone_slave_in;
+    slave_o : out t_wishbone_slave_out;
+    desc_o  : out t_wishbone_device_descriptor;
+
+    owr_pwren_o : out std_logic_vector(g_num_ports -1 downto 0);
+    owr_en_o    : out std_logic_vector(g_num_ports -1 downto 0);
+    owr_i       : in  std_logic_vector(g_num_ports -1 downto 0)
+
+    );
+
+end xwb_onewire_master;
+
+architecture rtl of xwb_onewire_master is
+
+  component wb_onewire_master
+    generic (
+      g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
+      g_address_granularity : t_wishbone_address_granularity := WORD;
+      g_num_ports           : integer;
+      g_ow_btp_normal       : string;
+      g_ow_btp_overdrive    : string;
+      g_CDR_N               : integer;
+      g_CDR_O               : integer);
+    port (
+      clk_sys_i   : in  std_logic;
+      rst_n_i     : in  std_logic;
+      
+      wb_cyc_i    : in  std_logic;
+      wb_sel_i    : in  std_logic_vector(c_wishbone_data_width/8-1 downto 0);
+      wb_stb_i    : in  std_logic;
+      wb_we_i     : in  std_logic;
+      wb_adr_i    : in  std_logic_vector(2 downto 0);
+      wb_dat_i    : in  std_logic_vector(c_wishbone_data_width-1 downto 0);
+      wb_dat_o    : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+      wb_ack_o    : out std_logic;
+      wb_int_o    : out std_logic;
+      wb_stall_o  : out std_logic;
+      
+      owr_pwren_o : out std_logic_vector(g_num_ports -1 downto 0);
+      owr_en_o    : out std_logic_vector(g_num_ports -1 downto 0);
+      owr_i       : in  std_logic_vector(g_num_ports -1 downto 0));
+  end component;
+  
+begin  -- rtl
+
+  U_Wrapped_1W : wb_onewire_master
+    generic map (
+      g_interface_mode      => g_interface_mode,
+      g_address_granularity => g_address_granularity,
+      g_num_ports           => g_num_ports,
+      g_ow_btp_normal       => g_ow_btp_normal,
+      g_ow_btp_overdrive    => g_ow_btp_overdrive,
+      g_CDR_N               => g_CDR_N,
+      g_CDR_O               => g_CDR_O)
+    port map (
+      clk_sys_i   => clk_sys_i,
+      rst_n_i     => rst_n_i,
+      wb_cyc_i    => slave_i.cyc,
+      wb_sel_i    => slave_i.sel,
+      wb_stb_i    => slave_i.stb,
+      wb_we_i     => slave_i.we,
+      wb_adr_i    => slave_i.adr(2 downto 0),
+      wb_dat_i    => slave_i.dat,
+      wb_dat_o    => slave_o.dat,
+      wb_ack_o    => slave_o.ack,
+      wb_int_o    => slave_o.int,
+      wb_stall_o  => slave_o.stall,
+      owr_pwren_o => owr_pwren_o,
+      owr_en_o    => owr_en_o,
+      owr_i       => owr_i);
+
+  slave_o.err <= '0';
+  slave_o.rty <= '0';
+
+  desc_o <= (others => '0');
+  
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
new file mode 100644
index 000000000..193fc3dc3
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
@@ -0,0 +1,232 @@
+-------------------------------------------------------------------------------
+-- Title      : Wishbone Slave Adapter
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : wb_slave_adapter.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Description:
+--
+-- universal "adapter"
+-- pipelined <> classic
+-- word-aligned/byte-aligned address
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011-2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.wishbone_pkg.all;
+
+entity wb_slave_adapter is
+
+  generic (
+    g_master_use_struct  : boolean;
+    g_master_mode        : t_wishbone_interface_mode;
+    g_master_granularity : t_wishbone_address_granularity;
+    g_slave_use_struct   : boolean;
+    g_slave_mode         : t_wishbone_interface_mode;
+    g_slave_granularity  : t_wishbone_address_granularity
+    );
+
+  port (
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+-- slave port (i.e. wb_slave_adapter is slave)
+    sl_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0);
+    sl_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
+    sl_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
+    sl_cyc_i : in std_logic;
+    sl_stb_i : in std_logic;
+    sl_we_i  : in std_logic;
+
+
+    sl_dat_o   : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+    sl_err_o   : out std_logic;
+    sl_rty_o   : out std_logic;
+    sl_ack_o   : out std_logic;
+    sl_stall_o : out std_logic;
+    sl_int_o   : out std_logic;
+
+    slave_i : in  t_wishbone_slave_in;
+    slave_o : out t_wishbone_slave_out;
+
+-- master port (i.e. wb_slave_adapter is master)
+    ma_adr_o : out std_logic_vector(c_wishbone_address_width-1 downto 0);
+    ma_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+    ma_sel_o : out std_logic_vector(c_wishbone_data_width/8-1 downto 0);
+    ma_cyc_o : out std_logic;
+    ma_stb_o : out std_logic;
+    ma_we_o  : out std_logic;
+
+    ma_dat_i   : in std_logic_vector(c_wishbone_data_width-1 downto 0);
+    ma_err_i   : in std_logic;
+    ma_rty_i   : in std_logic;
+    ma_ack_i   : in std_logic;
+    ma_stall_i : in std_logic;
+    ma_int_i   : in std_logic;
+
+    master_i : in  t_wishbone_master_in;
+    master_o : out t_wishbone_master_out
+    );
+end wb_slave_adapter;
+
+architecture rtl of wb_slave_adapter is
+
+  function f_num_byte_address_bits
+    return integer is
+  begin
+    case c_wishbone_data_width is
+      when 8      => return 0;
+      when 16     => return 1;
+      when 32     => return 2;
+      when 64     => return 3;
+      when others =>
+        report "wb_slave_adapter: invalid c_wishbone_data_width (we support 8, 16, 32 and 64)" severity failure;
+    end case;
+    return 0;
+  end f_num_byte_address_bits;
+
+  function f_zeros(size : integer)
+    return std_logic_vector is
+  begin
+    return std_logic_vector(to_unsigned(0, size));
+  end f_zeros;
+
+  type t_fsm_state is (IDLE, WAIT4ACK);
+
+  signal fsm_state : t_fsm_state := IDLE;
+
+  signal master_in  : t_wishbone_master_in;
+  signal master_out : t_wishbone_master_out;
+  signal slave_in   : t_wishbone_slave_in;
+  signal slave_out  : t_wishbone_slave_out;
+  signal stored_we  : std_logic;
+  
+begin  -- rtl
+
+  gen_slave_use_struct : if (g_slave_use_struct) generate
+    slave_in <= slave_i;
+  end generate gen_slave_use_struct;
+
+  gen_slave_use_slv : if (not g_slave_use_struct) generate
+    slave_in.cyc <= sl_cyc_i;
+    slave_in.stb <= sl_stb_i;
+    slave_in.we  <= sl_we_i;
+    slave_in.dat <= sl_dat_i;
+    slave_in.sel <= sl_sel_i;
+    slave_in.adr <= sl_adr_i;
+  end generate gen_slave_use_slv;
+
+  slave_o    <= slave_out;
+  sl_ack_o   <= slave_out.ack;
+  sl_rty_o   <= slave_out.rty;
+  sl_err_o   <= slave_out.err;
+  sl_stall_o <= slave_out.stall;
+  sl_dat_o   <= slave_out.dat;
+  sl_int_o   <= slave_out.int;
+  
+
+  gen_master_use_struct : if (g_master_use_struct) generate
+    master_in <= master_i;
+  end generate gen_master_use_struct;
+
+  gen_master_use_slv : if (not g_master_use_struct) generate
+    master_in <= (
+      ack   => ma_ack_i,
+      rty   => ma_rty_i,
+      err   => ma_err_i,
+      dat   => ma_dat_i,
+      stall => ma_stall_i,
+      int   => ma_int_i);
+  end generate gen_master_use_slv;
+
+  master_o <= master_out;
+  ma_adr_o <= master_out.adr;
+  ma_dat_o <= master_out.dat;
+  ma_sel_o <= master_out.sel;
+  ma_cyc_o <= master_out.cyc;
+  ma_stb_o <= master_out.stb;
+  ma_we_o  <= master_out.we;
+
+  p_gen_address : process(slave_in, master_out)
+  begin
+    if(g_master_granularity = g_slave_granularity) then
+      master_out.adr <= slave_in.adr;
+    elsif(g_master_granularity = BYTE) then  -- byte->word
+      master_out.adr <= slave_in.adr(c_wishbone_address_width-f_num_byte_address_bits-1 downto 0)
+                        & f_zeros(f_num_byte_address_bits);
+    else
+      master_out.adr <= f_zeros(f_num_byte_address_bits)
+                        & slave_in.adr(c_wishbone_address_width-1 downto f_num_byte_address_bits);
+    end if;
+  end process;
+  
+  P2C : if (g_slave_mode = PIPELINED and g_master_mode = CLASSIC)   generate
+    master_out.stb  <= slave_in.stb;
+    slave_out.stall <= not master_in.ack;
+  end generate;
+  
+  C2P : if (g_slave_mode = CLASSIC   and g_master_mode = PIPELINED) generate
+    master_out.stb  <= slave_in.stb when fsm_state=IDLE else '0';
+    slave_out.stall <= '0'; -- classic will ignore this anyway
+    
+    state_machine : process(clk_sys_i) is
+    begin
+      if rising_edge(clk_sys_i) then
+        if rst_n_i = '0' then
+          fsm_state <= IDLE;
+        else
+          case fsm_state is
+            when IDLE => 
+              if slave_in.stb ='1' and slave_in.cyc = '1' and master_in.stall='0' and master_in.ack='0' then
+                fsm_state <= WAIT4ACK;
+              end if;
+            when WAIT4ACK => 
+              if (slave_in.stb = '0' and slave_in.cyc = '0') or master_in.ack='1' or master_in.err='1' then 
+                fsm_state <= IDLE;
+              end if;
+          end case;
+        end if;
+      end if;
+    end process;
+  end generate;
+  
+  X2X : if (g_slave_mode = g_master_mode) generate
+    master_out.stb  <= slave_in.stb;
+    slave_out.stall <= master_in.stall;
+  end generate;
+  
+  master_out.dat <= slave_in.dat;
+  master_out.cyc <= slave_in.cyc;
+  master_out.sel <= slave_in.sel;
+  master_out.we  <= slave_in.we;
+
+  slave_out.ack <= master_in.ack;
+  slave_out.err <= master_in.err;
+  slave_out.rty <= master_in.rty;
+  slave_out.dat <= master_in.dat;
+  slave_out.int <= master_in.int;
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v
new file mode 100644
index 000000000..f9afa0f47
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v
@@ -0,0 +1,167 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  spi_define.v                                                ////
+////                                                              ////
+////  This file is part of the SPI IP core project                ////
+////  http://www.opencores.org/projects/spi/                      ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Simon Srot (simons@opencores.org)                     ////
+////                                                              ////
+////  All additional information is avaliable in the Readme.txt   ////
+////  file.                                                       ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2002 Authors                                   ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+//////////////////////////////////////////////////////////////////////
+//
+//  Modified to use parameters in spi_top instead of constants in this
+//  file for divider length, max char length and number of slaves,
+//  G.Daniluk, CERN 2013
+//
+//////////////////////////////////////////////////////////////////////
+
+//
+// Number of bits used for devider register. If used in system with
+// low frequency of system clock this can be reduced.
+// Use SPI_DIVIDER_LEN for fine tuning theexact number.
+//
+//`define SPI_DIVIDER_LEN_8
+//`define SPI_DIVIDER_LEN_16
+//`define SPI_DIVIDER_LEN_24
+//`define SPI_DIVIDER_LEN_32
+//
+//`ifdef SPI_DIVIDER_LEN_8
+//  `define SPI_DIVIDER_LEN       8    // Can be set from 1 to 8
+//`endif                                                          
+//`ifdef SPI_DIVIDER_LEN_16                                       
+//  `define SPI_DIVIDER_LEN       16   // Can be set from 9 to 16
+//`endif                                                          
+//`ifdef SPI_DIVIDER_LEN_24                                       
+//  `define SPI_DIVIDER_LEN       24   // Can be set from 17 to 24
+//`endif                                                          
+//`ifdef SPI_DIVIDER_LEN_32                                       
+//  `define SPI_DIVIDER_LEN       32   // Can be set from 25 to 32 
+//`endif
+
+//
+// Maximum nuber of bits that can be send/received at once. 
+// Use SPI_MAX_CHAR for fine tuning the exact number, when using
+// SPI_MAX_CHAR_32, SPI_MAX_CHAR_24, SPI_MAX_CHAR_16, SPI_MAX_CHAR_8.
+//
+//`define SPI_MAX_CHAR_128
+//`define SPI_MAX_CHAR_64
+//`define SPI_MAX_CHAR_32
+//`define SPI_MAX_CHAR_24
+//`define SPI_MAX_CHAR_16
+//`define SPI_MAX_CHAR_8
+//
+//`ifdef SPI_MAX_CHAR_128
+//  `define SPI_MAX_CHAR          128  // Can only be set to 128 
+//  `define SPI_CHAR_LEN_BITS     7
+//`endif
+//`ifdef SPI_MAX_CHAR_64
+//  `define SPI_MAX_CHAR          64   // Can only be set to 64 
+//  `define SPI_CHAR_LEN_BITS     6
+//`endif
+//`ifdef SPI_MAX_CHAR_32
+//  `define SPI_MAX_CHAR          32   // Can be set from 25 to 32 
+//  `define SPI_CHAR_LEN_BITS     5
+//`endif
+//`ifdef SPI_MAX_CHAR_24
+//  `define SPI_MAX_CHAR          24   // Can be set from 17 to 24 
+//  `define SPI_CHAR_LEN_BITS     5
+//`endif
+//`ifdef SPI_MAX_CHAR_16
+//  `define SPI_MAX_CHAR          16   // Can be set from 9 to 16 
+//  `define SPI_CHAR_LEN_BITS     4
+//`endif
+//`ifdef SPI_MAX_CHAR_8
+//  `define SPI_MAX_CHAR          8    // Can be set from 1 to 8 
+//  `define SPI_CHAR_LEN_BITS     3
+//`endif
+
+//
+// Number of device select signals. Use SPI_SS_NB for fine tuning the 
+// exact number.
+//
+//`define SPI_SS_NB_8
+//`define SPI_SS_NB_16
+//`define SPI_SS_NB_24
+//`define SPI_SS_NB_32
+//
+//`ifdef SPI_SS_NB_8
+//  `define SPI_SS_NB             8    // Can be set from 1 to 8
+//`endif
+//`ifdef SPI_SS_NB_16
+//  `define SPI_SS_NB             16   // Can be set from 9 to 16
+//`endif
+//`ifdef SPI_SS_NB_24
+//  `define SPI_SS_NB             24   // Can be set from 17 to 24
+//`endif
+//`ifdef SPI_SS_NB_32
+//  `define SPI_SS_NB             32   // Can be set from 25 to 32
+//`endif
+
+//
+// Bits of WISHBONE address used for partial decoding of SPI registers.
+//
+`define SPI_OFS_BITS	          4:2
+
+//
+// Register offset
+//
+`define SPI_RX_0                0
+`define SPI_RX_1                1
+`define SPI_RX_2                2
+`define SPI_RX_3                3
+`define SPI_TX_0                0
+`define SPI_TX_1                1
+`define SPI_TX_2                2
+`define SPI_TX_3                3
+`define SPI_CTRL                4
+`define SPI_DEVIDE              5
+`define SPI_SS                  6
+
+//
+// Number of bits in ctrl register
+//
+`define SPI_CTRL_BIT_NB         14
+
+//
+// Control register bit position
+//
+`define SPI_CTRL_ASS            13
+`define SPI_CTRL_IE             12
+`define SPI_CTRL_LSB            11
+`define SPI_CTRL_TX_NEGEDGE     10
+`define SPI_CTRL_RX_NEGEDGE     9
+`define SPI_CTRL_GO             8
+`define SPI_CTRL_RES_1          7
+`define SPI_CTRL_CHAR_LEN       6:0
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v
new file mode 100644
index 000000000..60d4ecbd1
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v
@@ -0,0 +1,2 @@
+`timescale 1ns / 10ps
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd
new file mode 100644
index 000000000..c2bb19ea4
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd
@@ -0,0 +1,99 @@
+---------------------------------------------------------------------------------------
+-- Title          : Wishbone slave core for Simple Wishbone UART
+---------------------------------------------------------------------------------------
+-- File           : simple_uart_pkg.vhd
+-- Author         : auto-generated by wbgen2 from simple_uart_wb.wb
+-- Created        : Tue Aug 15 10:16:30 2017
+-- Standard       : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE simple_uart_wb.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package uart_wbgen2_pkg is
+  
+  
+  -- Input registers (user design -> WB slave)
+  
+  type t_uart_in_registers is record
+    sr_tx_busy_i                             : std_logic;
+    sr_rx_rdy_i                              : std_logic;
+    rdr_rx_data_i                            : std_logic_vector(7 downto 0);
+    host_tdr_rdy_i                           : std_logic;
+    host_rdr_data_i                          : std_logic_vector(7 downto 0);
+    host_rdr_rdy_i                           : std_logic;
+    host_rdr_count_i                         : std_logic_vector(15 downto 0);
+    end record;
+  
+  constant c_uart_in_registers_init_value: t_uart_in_registers := (
+    sr_tx_busy_i => '0',
+    sr_rx_rdy_i => '0',
+    rdr_rx_data_i => (others => '0'),
+    host_tdr_rdy_i => '0',
+    host_rdr_data_i => (others => '0'),
+    host_rdr_rdy_i => '0',
+    host_rdr_count_i => (others => '0')
+    );
+    
+    -- Output registers (WB slave -> user design)
+    
+    type t_uart_out_registers is record
+      bcr_o                                    : std_logic_vector(31 downto 0);
+      bcr_wr_o                                 : std_logic;
+      tdr_tx_data_o                            : std_logic_vector(7 downto 0);
+      tdr_tx_data_wr_o                         : std_logic;
+      host_tdr_data_o                          : std_logic_vector(7 downto 0);
+      host_tdr_data_wr_o                       : std_logic;
+      end record;
+    
+    constant c_uart_out_registers_init_value: t_uart_out_registers := (
+      bcr_o => (others => '0'),
+      bcr_wr_o => '0',
+      tdr_tx_data_o => (others => '0'),
+      tdr_tx_data_wr_o => '0',
+      host_tdr_data_o => (others => '0'),
+      host_tdr_data_wr_o => '0'
+      );
+    function "or" (left, right: t_uart_in_registers) return t_uart_in_registers;
+    function f_x_to_zero (x:std_logic) return std_logic;
+    function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
+end package;
+
+package body uart_wbgen2_pkg is
+function f_x_to_zero (x:std_logic) return std_logic is
+begin
+if x = '1' then
+return '1';
+else
+return '0';
+end if;
+end function;
+function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
+variable tmp: std_logic_vector(x'length-1 downto 0);
+begin
+for i in 0 to x'length-1 loop
+if x(i) = '1' then
+tmp(i):= '1';
+else
+tmp(i):= '0';
+end if; 
+end loop; 
+return tmp;
+end function;
+function "or" (left, right: t_uart_in_registers) return t_uart_in_registers is
+variable tmp: t_uart_in_registers;
+begin
+tmp.sr_tx_busy_i := f_x_to_zero(left.sr_tx_busy_i) or f_x_to_zero(right.sr_tx_busy_i);
+tmp.sr_rx_rdy_i := f_x_to_zero(left.sr_rx_rdy_i) or f_x_to_zero(right.sr_rx_rdy_i);
+tmp.rdr_rx_data_i := f_x_to_zero(left.rdr_rx_data_i) or f_x_to_zero(right.rdr_rx_data_i);
+tmp.host_tdr_rdy_i := f_x_to_zero(left.host_tdr_rdy_i) or f_x_to_zero(right.host_tdr_rdy_i);
+tmp.host_rdr_data_i := f_x_to_zero(left.host_rdr_data_i) or f_x_to_zero(right.host_rdr_data_i);
+tmp.host_rdr_rdy_i := f_x_to_zero(left.host_rdr_rdy_i) or f_x_to_zero(right.host_rdr_rdy_i);
+tmp.host_rdr_count_i := f_x_to_zero(left.host_rdr_count_i) or f_x_to_zero(right.host_rdr_count_i);
+return tmp;
+end function;
+end package body;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd
new file mode 100644
index 000000000..62d09a5c1
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd
@@ -0,0 +1,315 @@
+---------------------------------------------------------------------------------------
+-- Title          : Wishbone slave core for Simple Wishbone UART
+---------------------------------------------------------------------------------------
+-- File           : simple_uart_wb.vhd
+-- Author         : auto-generated by wbgen2 from simple_uart_wb.wb
+-- Created        : Tue Aug 15 10:16:30 2017
+-- Standard       : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE simple_uart_wb.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.uart_wbgen2_pkg.all;
+
+
+entity simple_uart_wb is
+  port (
+    rst_n_i                                  : in     std_logic;
+    clk_sys_i                                : in     std_logic;
+    wb_adr_i                                 : in     std_logic_vector(2 downto 0);
+    wb_dat_i                                 : in     std_logic_vector(31 downto 0);
+    wb_dat_o                                 : out    std_logic_vector(31 downto 0);
+    wb_cyc_i                                 : in     std_logic;
+    wb_sel_i                                 : in     std_logic_vector(3 downto 0);
+    wb_stb_i                                 : in     std_logic;
+    wb_we_i                                  : in     std_logic;
+    wb_ack_o                                 : out    std_logic;
+    wb_stall_o                               : out    std_logic;
+    rdr_rack_o                               : out    std_logic;
+    host_rack_o                              : out    std_logic;
+    regs_i                                   : in     t_uart_in_registers;
+    regs_o                                   : out    t_uart_out_registers
+  );
+end simple_uart_wb;
+
+architecture syn of simple_uart_wb is
+
+signal ack_sreg                                 : std_logic_vector(9 downto 0);
+signal rddata_reg                               : std_logic_vector(31 downto 0);
+signal wrdata_reg                               : std_logic_vector(31 downto 0);
+signal rwaddr_reg                               : std_logic_vector(2 downto 0);
+signal ack_in_progress                          : std_logic      ;
+
+begin
+-- Some internal signals assignments
+  wrdata_reg <= wb_dat_i;
+-- 
+-- Main register bank access process.
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ack_sreg <= "0000000000";
+      ack_in_progress <= '0';
+      rddata_reg <= "00000000000000000000000000000000";
+      regs_o.bcr_wr_o <= '0';
+      regs_o.tdr_tx_data_wr_o <= '0';
+      rdr_rack_o <= '0';
+      regs_o.host_tdr_data_wr_o <= '0';
+      host_rack_o <= '0';
+    elsif rising_edge(clk_sys_i) then
+-- advance the ACK generator shift register
+      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
+      ack_sreg(9) <= '0';
+      if (ack_in_progress = '1') then
+        if (ack_sreg(0) = '1') then
+          regs_o.bcr_wr_o <= '0';
+          regs_o.tdr_tx_data_wr_o <= '0';
+          rdr_rack_o <= '0';
+          regs_o.host_tdr_data_wr_o <= '0';
+          host_rack_o <= '0';
+          ack_in_progress <= '0';
+        else
+          regs_o.bcr_wr_o <= '0';
+          regs_o.tdr_tx_data_wr_o <= '0';
+          regs_o.host_tdr_data_wr_o <= '0';
+        end if;
+      else
+        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
+          case rwaddr_reg(2 downto 0) is
+          when "000" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(0) <= regs_i.sr_tx_busy_i;
+            rddata_reg(1) <= regs_i.sr_rx_rdy_i;
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "001" => 
+            if (wb_we_i = '1') then
+              regs_o.bcr_wr_o <= '1';
+            end if;
+            rddata_reg(0) <= 'X';
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "010" => 
+            if (wb_we_i = '1') then
+              regs_o.tdr_tx_data_wr_o <= '1';
+            end if;
+            rddata_reg(0) <= 'X';
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "011" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(7 downto 0) <= regs_i.rdr_rx_data_i;
+            rdr_rack_o <= '1';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "100" => 
+            if (wb_we_i = '1') then
+              regs_o.host_tdr_data_wr_o <= '1';
+            end if;
+            rddata_reg(8) <= regs_i.host_tdr_rdy_i;
+            rddata_reg(0) <= 'X';
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "101" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(7 downto 0) <= regs_i.host_rdr_data_i;
+            host_rack_o <= '1';
+            rddata_reg(8) <= regs_i.host_rdr_rdy_i;
+            rddata_reg(24 downto 9) <= regs_i.host_rdr_count_i;
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when others =>
+-- prevent the slave from hanging the bus on invalid address
+            ack_in_progress <= '1';
+            ack_sreg(0) <= '1';
+          end case;
+        end if;
+      end if;
+    end if;
+  end process;
+  
+  
+-- Drive the data output bus
+  wb_dat_o <= rddata_reg;
+-- TX busy
+-- RX ready
+-- Baudrate divider setting
+-- pass-through field: Baudrate divider setting in register: Baudrate control register
+  regs_o.bcr_o <= wrdata_reg(31 downto 0);
+-- Transmit data
+-- pass-through field: Transmit data in register: Transmit data regsiter
+  regs_o.tdr_tx_data_o <= wrdata_reg(7 downto 0);
+-- Received data
+-- TX Data
+-- pass-through field: TX Data in register: Host VUART Tx register
+  regs_o.host_tdr_data_o <= wrdata_reg(7 downto 0);
+-- TX Ready
+-- RX Data
+-- RX Ready
+-- RX FIFO Count
+  rwaddr_reg <= wb_adr_i;
+  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
+-- ACK signal generation. Just pass the LSB of ACK counter.
+  wb_ack_o <= ack_sreg(0);
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd
new file mode 100644
index 000000000..ea996e08e
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd
@@ -0,0 +1,229 @@
+------------------------------------------------------------------------------
+-- Title      : Simple Wishbone UART - receiver
+-- Project    : General Cores Collection (gencores) library
+------------------------------------------------------------------------------
+-- File       : uart_async_rx.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2010 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity uart_async_rx is
+
+
+  port (
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    baud8_tick_i: in std_logic;
+
+    rxd_i      : in  std_logic;
+    rx_ready_o : out std_logic;
+    rx_error_o : out std_logic;
+    rx_data_o  : out std_logic_vector(7 downto 0)
+
+    );
+
+end uart_async_rx;
+
+
+architecture behavioral of uart_async_rx is
+
+  signal Baud8Tick : std_logic;
+  
+  signal RxD_sync_inv      : std_logic_vector(1 downto 0);
+  signal RxD_cnt_inv       : unsigned(1 downto 0);
+  signal RxD_bit_inv       : std_logic;
+
+  signal state       : std_logic_vector(3 downto 0);
+  signal bit_spacing : std_logic_vector(3 downto 0);
+  signal next_bit    : std_logic;
+
+  signal RxD_data       : std_logic_vector(7 downto 0);
+  signal RxD_data_ready : std_logic;
+  signal RxD_data_error : std_logic;
+
+  
+
+begin  -- behavioral
+
+  Baud8Tick <= baud8_tick_i;
+               
+
+  process(clk_sys_i, rst_n_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        RxD_sync_inv <= (others => '0');
+      else
+        if(Baud8Tick = '1') then
+          RxD_sync_inv <= RxD_sync_inv(0) & (not rxd_i);
+        end if;
+      end if;
+    end if;
+  end process;
+
+  process(clk_sys_i, rst_n_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        RxD_bit_inv <= '0';
+        RxD_cnt_inv <= (others => '0');
+      else
+        if(Baud8Tick = '1') then
+          if(RxD_sync_inv(1) = '1' and RxD_cnt_inv /= "11") then
+            RxD_cnt_inv <= RxD_cnt_inv + 1;
+          elsif (RxD_sync_inv(1) = '0' and RxD_cnt_inv /= "00") then
+            RxD_cnt_inv <= RxD_cnt_inv - 1;
+          end if;
+
+          if(RxD_cnt_inv = "00") then
+            RxD_bit_inv <= '0';
+          elsif(RxD_cnt_inv = "11") then
+            RxD_bit_inv <= '1';
+          end if;
+        end if;
+      end if;
+    end if;
+  end process;
+
+
+  next_bit <= '1' when (bit_spacing = x"a") else '0';
+
+  process(clk_sys_i, rst_n_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        bit_spacing <= (others => '0');
+      else
+        if(state = x"0") then
+          bit_spacing <= "0000";
+        elsif(Baud8Tick = '1') then
+--          bit_spacing <= std_logic_vector(resize((unsigned(bit_spacing(2 downto 0)) + 1), 4))
+          bit_spacing <= std_logic_vector(unsigned('0' & bit_spacing(2 downto 0)) + 1)
+                         or (bit_spacing(3) & "000");
+        end if;
+      end if;
+    end if;
+  end process;
+
+  process(clk_sys_i, rst_n_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        state <= (others => '0');
+      else
+        if(Baud8Tick = '1') then
+          case state is
+            when "0000" =>
+              if(RxD_bit_inv = '1') then  -- start bit
+                state <= "1000";
+              end if;
+            when "1000" =>
+              if(next_bit = '1') then
+                state <= "1001";          -- bit 0
+              end if;
+            when "1001" =>
+              if(next_bit = '1') then
+                state <= "1010";          -- bit 1
+              end if;
+            when "1010" =>
+              if(next_bit = '1') then
+                state <= "1011";          -- bit 2
+              end if;
+            when "1011" =>
+              if(next_bit = '1') then
+                state <= "1100";          -- bit 3
+              end if;
+            when "1100" =>
+              if(next_bit = '1') then
+                state <= "1101";          -- bit 4
+              end if;
+            when "1101" =>
+              if(next_bit = '1') then
+                state <= "1110";          -- bit 5
+              end if;
+            when "1110" =>
+              if(next_bit = '1') then
+                state <= "1111";          -- bit 6
+              end if;
+            when "1111" =>
+              if(next_bit = '1') then
+                state <= "0001";          -- bit 7
+              end if;
+            when "0001" =>
+              if(next_bit = '1') then
+                state <= "0000";          -- bit stop
+              end if;
+            when others => state <= "0000";
+          end case;
+        end if;
+      end if;
+    end if;
+  end process;
+
+
+  process(clk_sys_i, rst_n_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        RxD_data <= (others => '0');
+      else
+        if(Baud8Tick = '1' and next_bit = '1' and state(3) = '1') then
+          RxD_data <= (not RxD_bit_inv) & RxD_data(7 downto 1);
+        end if;
+      end if;
+    end if;
+  end process;
+
+  process(clk_sys_i, rst_n_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        RxD_data_error <= '0';
+        RxD_data_ready <= '0';
+      else
+        if(Baud8Tick = '1' and next_bit = '1' and state = "0001" and RxD_bit_inv = '0') then
+          RxD_data_ready <= '1';
+        else
+          RxD_data_ready <= '0';
+        end if;
+
+        if(Baud8Tick = '1' and next_bit = '1' and state = "0001" and RxD_bit_inv = '1') then
+          RxD_data_error <= '1';
+        else
+          RxD_data_error <= '0';
+        end if;
+      end if;
+    end if;
+  end process;
+
+  rx_data_o <= RxD_data;
+  rx_ready_o  <= RxD_data_ready;
+  rx_error_o <= RxD_data_error;
+  
+
+end behavioral;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd
new file mode 100644
index 000000000..d0a743f39
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd
@@ -0,0 +1,190 @@
+------------------------------------------------------------------------------
+-- Title      : Simple Wishbone UART - tranmitter
+-- Project    : General Cores Collection (gencores) library
+------------------------------------------------------------------------------
+-- File       : uart_async_tx.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2010 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity uart_async_tx is
+  
+  port (
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    baud_tick_i: in std_logic;
+    
+    txd_o        : out std_logic;
+    tx_start_p_i : in  std_logic;
+    tx_data_i    : in  std_logic_vector(7 downto 0);
+    tx_busy_o    : out std_logic
+
+    );
+
+end uart_async_tx;
+
+architecture behavioral of uart_async_tx is
+
+signal BaudTick : std_logic;
+  signal TxD_busy         : std_logic;
+  signal TxD_ready        : std_logic;
+  signal state            : std_logic_vector(3 downto 0);
+
+  signal TxD_dataReg : std_logic_vector(7 downto 0);
+  signal TxD_dataD   : std_logic_vector(7 downto 0);
+  signal muxbit      : std_logic;
+  signal TxD         : std_logic;
+
+begin  -- behavioral
+
+
+
+
+  TxD_ready <= '1' when state = "0000" else '0';
+  TxD_busy  <= not TxD_ready;
+  BaudTick  <= baud_tick_i;
+  
+
+  process(clk_sys_i, rst_n_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        TxD_dataReg <= (others => '0');
+      elsif TxD_ready = '1' and tx_start_p_i = '1' then
+        TxD_dataReg <= tx_data_i;
+      end if;
+    end if;
+  end process;
+
+  TxD_dataD <= TxD_dataReg;
+
+  process(clk_sys_i, rst_n_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        state <= "0000";
+      else
+        case state is
+          when "0000" =>
+            if (tx_start_p_i = '1') then
+              state <= "0001";
+            end if;
+
+          when "0001" =>
+            if (BaudTick = '1') then
+              state <= "0100";
+            end if;
+          when "0100" =>
+            if (BaudTick = '1') then
+              state <= "1000";
+            end if;
+          when "1000" =>
+            if (BaudTick = '1') then
+              state <= "1001";
+            end if;
+          when "1001" =>
+            if (BaudTick = '1') then
+              state <= "1010";
+            end if;
+
+          when "1010" =>
+            if (BaudTick = '1') then
+              state <= "1011";
+            end if;
+          when "1011" =>
+            if (BaudTick = '1') then
+              state <= "1100";
+            end if;
+          when "1100" =>
+            if (BaudTick = '1') then
+              state <= "1101";
+            end if;
+          when "1101" =>
+            if (BaudTick = '1') then
+              state <= "1110";
+            end if;
+          when "1110" =>
+            if (BaudTick = '1') then
+              state <= "1111";
+            end if;
+
+          when "1111" =>
+            if (BaudTick = '1') then
+              state <= "0010";
+            end if;
+          when "0010" =>
+            if (BaudTick = '1') then
+              state <= "0011";
+            end if;
+
+          when "0011" =>
+            if (BaudTick = '1') then
+              state <= "0000";
+            end if;
+          when others =>
+            state <= "0000";
+        end case;
+      end if;
+    end if;
+  end process;
+
+
+  process(TxD_dataD, state)
+  begin
+    case state(2 downto 0) is
+      when "000"      => muxbit <= TxD_dataD(0);
+      when "001"      => muxbit <= TxD_dataD(1);
+      when "010"      => muxbit <= TxD_dataD(2);
+      when "011"      => muxbit <= TxD_dataD(3);
+      when "100"      => muxbit <= TxD_dataD(4);
+      when "101"      => muxbit <= TxD_dataD(5);
+      when "110"      => muxbit <= TxD_dataD(6);
+      when "111"      => muxbit <= TxD_dataD(7);
+      when others => null;
+    end case;
+  end process;
+
+  process(clk_sys_i, rst_n_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        TxD <= '1';
+      else
+        if(unsigned(state) < to_unsigned(4, state'length) or (state(3) = '1' and muxbit = '1')) then
+          TxD <= '1';
+        else
+          TxD <= '0';
+        end if;
+      end if;
+    end if;
+  end process;
+
+  txd_o      <= TxD;
+  tx_busy_o <= TxD_busy;
+
+end behavioral;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd
new file mode 100644
index 000000000..a565c5c20
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd
@@ -0,0 +1,89 @@
+------------------------------------------------------------------------------
+-- Title      : Simple Wishbone UART - baud generator
+-- Project    : General Cores Collection (gencores) library
+------------------------------------------------------------------------------
+-- File       : uart_baud_gen.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2010 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity uart_baud_gen is
+  
+  generic (
+    g_baud_acc_width : integer := 16);
+
+  port (
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    baudrate_i : in std_logic_vector(g_baud_acc_width  downto 0);
+
+    baud_tick_o  : out std_logic;
+    baud8_tick_o : out std_logic);
+
+end uart_baud_gen;
+
+architecture behavioral of uart_baud_gen is
+
+  signal Baud8GeneratorInc : unsigned(g_baud_acc_width downto 0);
+  signal Baud8GeneratorAcc : unsigned(g_baud_acc_width downto 0);
+  signal Baud8Tick         : std_logic;
+  signal Baud_sreg         : std_logic_vector(7 downto 0) := "10000000";
+  
+  
+begin  -- behavioral
+
+  Baud8GeneratorInc <= unsigned(baudrate_i);
+
+  process(clk_sys_i, rst_n_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        Baud8GeneratorAcc <= (others => '0');
+      else
+        Baud8GeneratorAcc <= ('0' & Baud8GeneratorAcc(Baud8GeneratorAcc'high-1 downto 0)) + Baud8GeneratorInc;
+      end if;
+    end if;
+  end process;
+
+  Baud8Tick <= std_logic(Baud8GeneratorAcc(g_baud_acc_width));
+
+  process(clk_sys_i, rst_n_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        Baud_sreg <= "10000000";
+      elsif Baud8Tick = '1' then
+        Baud_sreg <= Baud_sreg(0) & Baud_sreg(7 downto 1);
+      end if;
+    end if;
+  end process;
+
+  baud_tick_o  <= Baud_sreg(0) and Baud8Tick;
+  baud8_tick_o <= Baud8Tick;
+
+end behavioral;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd
new file mode 100644
index 000000000..75379bf69
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd
@@ -0,0 +1,323 @@
+-------------------------------------------------------------------------------
+-- Title      : Simple Wishbone UART
+-- Project    : General Cores Collection (gencores) library
+-------------------------------------------------------------------------------
+-- File       : wb_simple_uart.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-Co-HT
+-- Created    : 2011-02-21
+-- Last update: 2017-02-03
+-- Platform   : FPGA-generics
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: A simple UART controller, providing two modes of operation
+-- (both can be used simultenously):
+-- - physical UART (encoding fixed to 8 data bits, no parity and one stop bit)
+-- - virtual UART: TXed data is passed via a FIFO to the Wishbone host (and
+--   vice versa).
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2011-02-21  1.0      twlostow        Created
+-- 2011-10-04  1.1      twlostow        merged with VUART, added adapter
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.genram_pkg.all;
+use work.wishbone_pkg.all;
+use work.UART_wbgen2_pkg.all;
+
+entity wb_simple_uart is
+  generic(
+    g_with_virtual_uart   : boolean;
+    g_with_physical_uart  : boolean;
+    g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
+    g_address_granularity : t_wishbone_address_granularity := WORD;
+    g_vuart_fifo_size     : integer := 1024
+    );
+  port (
+
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    wb_adr_i   : in  std_logic_vector(4 downto 0);
+    wb_dat_i   : in  std_logic_vector(31 downto 0);
+    wb_dat_o   : out std_logic_vector(31 downto 0);
+    wb_cyc_i   : in  std_logic;
+    wb_sel_i   : in  std_logic_vector(3 downto 0);
+    wb_stb_i   : in  std_logic;
+    wb_we_i    : in  std_logic;
+    wb_ack_o   : out std_logic;
+    wb_stall_o : out std_logic;
+
+    uart_rxd_i : in  std_logic;
+    uart_txd_o : out std_logic
+    );
+end wb_simple_uart;
+
+architecture syn of wb_simple_uart is
+
+  constant c_baud_acc_width  : integer := 16;
+
+  component uart_baud_gen
+    generic (
+      g_baud_acc_width : integer);
+    port (
+      clk_sys_i    : in  std_logic;
+      rst_n_i      : in  std_logic;
+      baudrate_i   : in  std_logic_vector(g_baud_acc_width downto 0);
+      baud_tick_o  : out std_logic;
+      baud8_tick_o : out std_logic);
+  end component;
+
+  component uart_async_rx
+    port (
+      clk_sys_i    : in  std_logic;
+      rst_n_i      : in  std_logic;
+      baud8_tick_i : in  std_logic;
+      rxd_i        : in  std_logic;
+      rx_ready_o   : out std_logic;
+      rx_error_o   : out std_logic;
+      rx_data_o    : out std_logic_vector(7 downto 0));
+  end component;
+
+  component uart_async_tx
+    port (
+      clk_sys_i    : in  std_logic;
+      rst_n_i      : in  std_logic;
+      baud_tick_i  : in  std_logic;
+      txd_o        : out std_logic;
+      tx_start_p_i : in  std_logic;
+      tx_data_i    : in  std_logic_vector(7 downto 0);
+      tx_busy_o    : out std_logic);
+  end component;
+
+  component simple_uart_wb
+    port (
+      rst_n_i     : in  std_logic;
+      clk_sys_i   : in  std_logic;
+      wb_adr_i    : in  std_logic_vector(2 downto 0);
+      wb_dat_i    : in  std_logic_vector(31 downto 0);
+      wb_dat_o    : out std_logic_vector(31 downto 0);
+      wb_cyc_i    : in  std_logic;
+      wb_sel_i    : in  std_logic_vector(3 downto 0);
+      wb_stb_i    : in  std_logic;
+      wb_we_i     : in  std_logic;
+      wb_ack_o    : out std_logic;
+      wb_stall_o  : out std_logic;
+      rdr_rack_o  : out std_logic;
+      host_rack_o : out std_logic;
+      regs_i      : in  t_uart_in_registers;
+      regs_o      : out t_uart_out_registers
+    );
+  end component;
+
+  signal rx_ready_reg    : std_logic;
+  signal rx_ready        : std_logic;
+  signal uart_bcr        : std_logic_vector(31 downto 0);
+
+  signal rdr_rack         : std_logic;
+  signal host_rack : std_logic;
+
+  signal baud_tick  : std_logic;
+  signal baud_tick8 : std_logic;
+
+  signal resized_addr : std_logic_vector(c_wishbone_address_width-1 downto 0);
+
+  signal wb_in  : t_wishbone_slave_in;
+  signal wb_out : t_wishbone_slave_out;
+
+  signal regs_in  : t_UART_in_registers;
+  signal regs_out : t_UART_out_registers;
+
+  signal fifo_empty, fifo_full, fifo_rd, fifo_wr : std_logic;
+  signal fifo_count                              : std_logic_vector(f_log2_size(g_vuart_fifo_size)-1 downto 0);
+
+  signal phys_rx_ready, phys_tx_busy : std_logic;
+  
+  signal phys_rx_data : std_logic_vector(7 downto 0);
+  
+  
+begin  -- syn
+
+  gen_check_generics : if(not g_with_physical_uart and not g_with_virtual_uart) generate
+    assert false report "wb_simple_uart: dummy configuration (use virtual, physical or both uarts)" severity failure;
+  end generate gen_check_generics;
+
+  resized_addr(4 downto 0)                          <= wb_adr_i;
+  resized_addr(c_wishbone_address_width-1 downto 5) <= (others => '0');
+
+  U_Adapter : wb_slave_adapter
+    generic map (
+      g_master_use_struct  => true,
+      g_master_mode        => CLASSIC,
+      g_master_granularity => WORD,
+      g_slave_use_struct   => false,
+      g_slave_mode         => g_interface_mode,
+      g_slave_granularity  => g_address_granularity)
+    port map (
+      clk_sys_i  => clk_sys_i,
+      rst_n_i    => rst_n_i,
+      master_i   => wb_out,
+      master_o   => wb_in,
+      sl_adr_i   => resized_addr,
+      sl_dat_i   => wb_dat_i,
+      sl_sel_i   => wb_sel_i,
+      sl_cyc_i   => wb_cyc_i,
+      sl_stb_i   => wb_stb_i,
+      sl_we_i    => wb_we_i,
+      sl_dat_o   => wb_dat_o,
+      sl_ack_o   => wb_ack_o,
+      sl_stall_o => wb_stall_o);
+
+  U_WB_SLAVE : simple_uart_wb
+    port map (
+      rst_n_i    => rst_n_i,
+      clk_sys_i  => clk_sys_i,
+      wb_adr_i   => wb_in.adr(2 downto 0),
+      wb_dat_i   => wb_in.dat,
+      wb_dat_o   => wb_out.dat,
+      wb_cyc_i   => wb_in.cyc,
+      wb_sel_i   => wb_in.sel,
+      wb_stb_i   => wb_in.stb,
+      wb_we_i    => wb_in.we,
+      wb_ack_o   => wb_out.ack,
+      wb_stall_o => wb_out.stall,
+
+      rdr_rack_o  => rdr_rack,
+      host_rack_o => host_rack,
+      regs_o      => regs_out,
+      regs_i      => regs_in);
+
+  wb_out.err <= '0';
+  wb_out.rty <= '0';
+  wb_out.int <= '0';
+
+  gen_phys_uart : if(g_with_physical_uart) generate
+
+    p_bcr_reg : process(clk_sys_i)
+    begin
+      if rising_edge(clk_sys_i) then
+        if rst_n_i = '0' then
+          uart_bcr <= (others => '0');
+        elsif(regs_out.bcr_wr_o = '1')then
+          uart_bcr <= regs_out.bcr_o;
+        end if;
+      end if;
+    end process;
+
+    U_BAUD_GEN : uart_baud_gen
+      generic map (
+        g_baud_acc_width => c_baud_acc_width)
+      port map (
+        clk_sys_i    => clk_sys_i,
+        rst_n_i      => rst_n_i,
+        baudrate_i   => uart_bcr(c_baud_acc_width downto 0),
+        baud_tick_o  => baud_tick,
+        baud8_tick_o => baud_tick8);
+
+    U_TX : uart_async_tx
+      port map (
+        clk_sys_i    => clk_sys_i,
+        rst_n_i      => rst_n_i,
+        baud_tick_i  => baud_tick,
+        txd_o        => uart_txd_o,
+        tx_start_p_i => regs_out.tdr_tx_data_wr_o,
+        tx_data_i    => regs_out.tdr_tx_data_o,
+        tx_busy_o    => phys_tx_busy);
+
+    U_RX : uart_async_rx
+      port map (
+        clk_sys_i    => clk_sys_i,
+        rst_n_i      => rst_n_i,
+        baud8_tick_i => baud_tick8,
+        rxd_i        => uart_rxd_i,
+        rx_ready_o   => phys_rx_ready,
+        rx_error_o   => open,
+        rx_data_o    => phys_rx_data);
+
+  end generate gen_phys_uart;
+  
+  gen_vuart : if(g_with_virtual_uart) generate
+
+    fifo_wr <= not fifo_full and regs_out.tdr_tx_data_wr_o;
+    fifo_rd <= not fifo_empty and not regs_in.host_rdr_rdy_i;
+
+    U_VUART_FIFO : generic_sync_fifo
+      generic map (
+        g_data_width => 8,
+        g_size       => g_vuart_fifo_size,
+        g_with_count => true)
+      port map (
+        rst_n_i => rst_n_i,
+        clk_i   => clk_sys_i,
+        d_i     => regs_out.tdr_tx_data_o,
+        we_i    => fifo_wr,
+        q_o     => regs_in.host_rdr_data_i,
+        rd_i    => fifo_rd,
+        empty_o => fifo_empty,
+        full_o  => fifo_full,
+        count_o => fifo_count);
+
+    regs_in.host_rdr_count_i(fifo_count'left downto 0)    <= fifo_count;
+    regs_in.host_rdr_count_i(15 downto fifo_count'length) <= (others => '0');
+
+    p_vuart_rx_ready : process(clk_sys_i)
+    begin
+      if rising_edge(clk_sys_i) then
+        if rst_n_i = '0' then
+          regs_in.host_rdr_rdy_i <= '0';
+        elsif(fifo_rd = '1') then
+          regs_in.host_rdr_rdy_i <= '1';
+        elsif(host_rack = '1') then
+          regs_in.host_rdr_rdy_i <= '0';
+        end if;
+      end if;
+    end process;
+
+  end generate gen_vuart;
+
+  p_drive_rx_ready : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        regs_in.sr_rx_rdy_i   <= '0';
+        regs_in.rdr_rx_data_i <= (others => '0');
+      else
+        if(rdr_rack = '1' and phys_rx_ready = '0' and regs_out.host_tdr_data_wr_o = '0') then
+          regs_in.sr_rx_rdy_i <= '0';
+        elsif(phys_rx_ready = '1' and g_with_physical_uart) then
+          regs_in.sr_rx_rdy_i   <= '1';
+          regs_in.rdr_rx_data_i <= phys_rx_data;
+        elsif(regs_out.host_tdr_data_wr_o = '1' and g_with_virtual_uart) then
+          regs_in.sr_rx_rdy_i   <= '1';
+          regs_in.rdr_rx_data_i <= regs_out.host_tdr_data_o;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  regs_in.sr_tx_busy_i <= phys_tx_busy when (g_with_physical_uart) else '0';
+  regs_in.host_tdr_rdy_i <= not regs_in.sr_rx_rdy_i;
+  
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd
new file mode 100644
index 000000000..5914773d2
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd
@@ -0,0 +1,129 @@
+------------------------------------------------------------------------------
+-- Title      : Simple Wishbone UART
+-- Project    : General Cores Collection (gencores) library
+------------------------------------------------------------------------------
+-- File       : xwb_simple_uart.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-Co-HT
+-- Created    : 2010-05-18
+-- Last update: 2017-02-03
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: A simple UART controller, providing two modes of operation
+-- (both can be used simultenously):
+-- - physical UART (encoding fixed to 8 data bits, no parity and one stop bit)
+-- - virtual UART: TXed data is passed via a FIFO to the Wishbone host (and
+--   vice versa).
+-------------------------------------------------------------------------------
+-- Copyright (c) 2010 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2010-05-18  1.0      twlostow        Created
+-- 2011-10-04  1.1      twlostow        xwb module
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.wishbone_pkg.all;
+
+entity xwb_simple_uart is
+  generic(
+    g_with_virtual_uart   : boolean := true;
+    g_with_physical_uart  : boolean := true;
+    g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
+    g_address_granularity : t_wishbone_address_granularity := WORD;
+    g_vuart_fifo_size     : integer := 1024
+    );
+
+  port(
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    -- Wishbone
+    slave_i : in  t_wishbone_slave_in;
+    slave_o : out t_wishbone_slave_out;
+    desc_o  : out t_wishbone_device_descriptor;
+
+    uart_rxd_i: in std_logic;
+    uart_txd_o: out std_logic
+
+    );
+
+end xwb_simple_uart;
+
+architecture rtl of xwb_simple_uart is
+
+  component wb_simple_uart
+    generic (
+      g_with_virtual_uart   : boolean;
+      g_with_physical_uart  : boolean;
+      g_interface_mode      : t_wishbone_interface_mode;
+      g_address_granularity : t_wishbone_address_granularity;
+      g_vuart_fifo_size     : integer);
+    port (
+      clk_sys_i  : in  std_logic;
+      rst_n_i    : in  std_logic;
+      wb_adr_i   : in  std_logic_vector(4 downto 0);
+      wb_dat_i   : in  std_logic_vector(31 downto 0);
+      wb_dat_o   : out std_logic_vector(31 downto 0);
+      wb_cyc_i   : in  std_logic;
+      wb_sel_i   : in  std_logic_vector(3 downto 0);
+      wb_stb_i   : in  std_logic;
+      wb_we_i    : in  std_logic;
+      wb_ack_o   : out std_logic;
+      wb_stall_o : out std_logic;
+      uart_rxd_i : in  std_logic;
+      uart_txd_o : out std_logic);
+  end component;
+  
+begin  -- rtl
+
+  U_Wrapped_UART: wb_simple_uart
+    generic map (
+      g_with_virtual_uart   => g_with_virtual_uart,
+      g_with_physical_uart  => g_with_physical_uart,
+      g_interface_mode      => g_interface_mode,
+      g_address_granularity => g_address_granularity,
+      g_vuart_fifo_size     => g_vuart_fifo_size)
+    port map (
+      clk_sys_i  => clk_sys_i,
+      rst_n_i    => rst_n_i,
+      wb_adr_i   => slave_i.adr(4 downto 0),
+      wb_dat_i   => slave_i.dat,
+      wb_dat_o   => slave_o.dat,
+      wb_cyc_i   => slave_i.cyc,
+      wb_sel_i   => slave_i.sel,
+      wb_stb_i   => slave_i.stb,
+      wb_we_i    => slave_i.we,
+      wb_ack_o   => slave_o.ack,
+      wb_stall_o => slave_o.stall,
+      uart_rxd_i => uart_rxd_i,
+      uart_txd_o => uart_txd_o);
+
+  slave_o.err <= '0';
+  slave_o.rty <= '0';
+  slave_o.int <='0';
+
+  desc_o <= (others => '0');
+  
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd
new file mode 100644
index 000000000..7962e6b6f
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd
@@ -0,0 +1,241 @@
+-------------------------------------------------------------------------------
+-- Title      : WBGEN components
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : wbgen2_eic.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+use work.wbgen2_pkg.all;
+
+entity wbgen2_eic is
+  
+  generic (
+    g_num_interrupts : natural := 1;
+
+    g_irq00_mode : integer := 0;
+    g_irq01_mode : integer := 0;
+    g_irq02_mode : integer := 0;
+    g_irq03_mode : integer := 0;
+    g_irq04_mode : integer := 0;
+    g_irq05_mode : integer := 0;
+    g_irq06_mode : integer := 0;
+    g_irq07_mode : integer := 0;
+    g_irq08_mode : integer := 0;
+    g_irq09_mode : integer := 0;
+    g_irq0a_mode : integer := 0;
+    g_irq0b_mode : integer := 0;
+    g_irq0c_mode : integer := 0;
+    g_irq0d_mode : integer := 0;
+    g_irq0e_mode : integer := 0;
+    g_irq0f_mode : integer := 0;
+    g_irq10_mode : integer := 0;
+    g_irq11_mode : integer := 0;
+    g_irq12_mode : integer := 0;
+    g_irq13_mode : integer := 0;
+    g_irq14_mode : integer := 0;
+    g_irq15_mode : integer := 0;
+    g_irq16_mode : integer := 0;
+    g_irq17_mode : integer := 0;
+    g_irq18_mode : integer := 0;
+    g_irq19_mode : integer := 0;
+    g_irq1a_mode : integer := 0;
+    g_irq1b_mode : integer := 0;
+    g_irq1c_mode : integer := 0;
+    g_irq1d_mode : integer := 0;
+    g_irq1e_mode : integer := 0;
+    g_irq1f_mode : integer := 0
+    );
+  port(
+    rst_n_i : in std_logic;             -- reset & system clock, as always :)
+    clk_i   : in std_logic;
+
+    -- raw interrupt inputs
+    irq_i : in std_logic_vector(g_num_interrupts-1 downto 0);  
+
+    -- interrupt acknowledge signal, used for level-active interrupts to
+    -- indicate that the interrupt has been handled
+    irq_ack_o: out std_logic_vector(g_num_interrupts-1 downto 0);  
+
+-- interrupt mask regsiter (slv/bus read-only)
+    reg_imr_o : out std_logic_vector(g_num_interrupts-1 downto 0);
+
+-- interrupt enable/disable registers (slv/bus pass-through)
+    reg_ier_i        : in std_logic_vector(g_num_interrupts-1 downto 0);
+    reg_ier_wr_stb_i : in std_logic;
+
+    reg_idr_i        : in std_logic_vector(g_num_interrupts-1 downto 0);
+    reg_idr_wr_stb_i : in std_logic;
+
+-- interrupt status register (slv/bus write with LOAD_EXT)
+    reg_isr_o        : out std_logic_vector(g_num_interrupts-1 downto 0);
+    reg_isr_i        : in  std_logic_vector(g_num_interrupts-1 downto 0);
+    reg_isr_wr_stb_i : in  std_logic;
+
+-- multiplexed wishbone irq output
+    wb_irq_o : out std_logic
+
+    );
+
+end wbgen2_eic;
+
+architecture syn of wbgen2_eic is
+
+  subtype t_irq_mode is integer;
+  type t_irq_mode_vec is array (0 to 31) of t_irq_mode;
+
+  constant c_IRQ_MODE_RISING_EDGE  : t_irq_mode := 0;
+  constant c_IRQ_MODE_FALLING_EDGE : t_irq_mode := 1;
+  constant c_IRQ_MODE_LEVEL_0      : t_irq_mode := 2;
+  constant c_IRQ_MODE_LEVEL_1      : t_irq_mode := 3;
+
+
+  signal irq_mode : t_irq_mode_vec;
+
+  signal irq_mask    : std_logic_vector(g_num_interrupts-1 downto 0);
+  signal irq_pending : std_logic_vector(g_num_interrupts-1 downto 0);
+
+  signal irq_i_d0 : std_logic_vector(g_num_interrupts-1 downto 0);
+  signal irq_i_d1 : std_logic_vector(g_num_interrupts-1 downto 0);
+  signal irq_i_d2 : std_logic_vector(g_num_interrupts-1 downto 0);
+  
+begin  -- syn
+
+  irq_mode(0)  <= g_irq00_mode;
+  irq_mode(1)  <= g_irq01_mode;
+  irq_mode(2)  <= g_irq02_mode;
+  irq_mode(3)  <= g_irq03_mode;
+  irq_mode(4)  <= g_irq04_mode;
+  irq_mode(5)  <= g_irq05_mode;
+  irq_mode(6)  <= g_irq06_mode;
+  irq_mode(7)  <= g_irq07_mode;
+  irq_mode(8)  <= g_irq08_mode;
+  irq_mode(9)  <= g_irq09_mode;
+  irq_mode(10) <= g_irq0a_mode;
+  irq_mode(11) <= g_irq0b_mode;
+  irq_mode(12) <= g_irq0c_mode;
+  irq_mode(13) <= g_irq0d_mode;
+  irq_mode(14) <= g_irq0e_mode;
+  irq_mode(15) <= g_irq0f_mode;
+  irq_mode(16) <= g_irq10_mode;
+  irq_mode(17) <= g_irq11_mode;
+  irq_mode(18) <= g_irq12_mode;
+  irq_mode(19) <= g_irq13_mode;
+  irq_mode(20) <= g_irq14_mode;
+  irq_mode(21) <= g_irq15_mode;
+  irq_mode(22) <= g_irq16_mode;
+  irq_mode(23) <= g_irq17_mode;
+  irq_mode(24) <= g_irq18_mode;
+  irq_mode(25) <= g_irq19_mode;
+  irq_mode(26) <= g_irq1a_mode;
+  irq_mode(27) <= g_irq1b_mode;
+  irq_mode(28) <= g_irq1c_mode;
+  irq_mode(29) <= g_irq1d_mode;
+  irq_mode(30) <= g_irq1e_mode;
+  irq_mode(31) <= g_irq1f_mode;
+
+
+  process(clk_i, rst_n_i)
+  begin
+    if(rst_n_i = '0') then
+      irq_i_d0    <= (others => '0');
+      irq_i_d1    <= (others => '0');
+      irq_i_d1    <= (others => '0');
+      irq_pending <= (others => '0');
+      irq_mask    <= (others => '0');
+      
+    elsif rising_edge(clk_i) then
+
+      for i in 0 to g_num_interrupts-1 loop
+        
+        irq_i_d0(i) <= irq_i(i);
+        irq_i_d1(i) <= irq_i_d0(i);
+        irq_i_d2(i) <= irq_i_d1(i);
+
+
+        if((reg_isr_i(i) = '1' and reg_isr_wr_stb_i = '1') or irq_mask(i) = '0') then
+          irq_pending(i) <= '0';
+          irq_i_d0(i) <= '0';
+          irq_i_d1(i) <= '0';
+          irq_i_d2(i) <= '0';
+        
+        else
+          
+          case irq_mode(i) is
+            when c_IRQ_MODE_LEVEL_0      => irq_pending(i) <= not irq_i_d2(i);
+            when c_IRQ_MODE_LEVEL_1      => irq_pending(i) <= irq_i_d2(i);
+            when c_IRQ_MODE_RISING_EDGE  => irq_pending(i) <= irq_pending(i) or ((not irq_i_d2(i)) and irq_i_d1(i));
+            when c_IRQ_MODE_FALLING_EDGE => irq_pending(i) <= irq_pending(i) or ((not irq_i_d1(i)) and irq_i_d2(i));
+            when others                  => null;
+          end case;
+        end if;
+      end loop;  -- i
+
+      if(reg_ier_wr_stb_i = '1') then
+        for i in 0 to g_num_interrupts-1 loop
+          if(reg_ier_i(i) = '1') then
+            irq_mask(i) <= '1';
+          end if;
+        end loop;
+      end if;
+
+      if(reg_idr_wr_stb_i = '1') then
+        for i in 0 to g_num_interrupts-1 loop
+          if(reg_idr_i(i) = '1') then
+            irq_mask(i) <= '0';
+          end if;
+        end loop;
+      end if;
+    end if;
+  end process;
+
+  -- generation of wb_irq_o
+
+  process(clk_i, rst_n_i)
+  begin
+    if(rst_n_i = '0') then
+      wb_irq_o <= '0';
+    elsif rising_edge(clk_i) then
+      if(irq_pending = std_logic_vector(to_unsigned(0, g_num_interrupts))) then
+        wb_irq_o <= '0';
+      else
+        wb_irq_o <= '1';
+      end if;
+      
+    end if;
+  end process;
+
+  gen_irq_ack: for i in 0 to g_num_interrupts-1 generate
+    irq_ack_o(i) <= '1' when (reg_isr_wr_stb_i = '1' and reg_isr_i(i) = '1') else '0';
+  end generate gen_irq_ack;
+
+  reg_imr_o <= irq_mask;
+  reg_isr_o <= irq_pending;
+
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd
new file mode 100644
index 000000000..8905cc9dc
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd
@@ -0,0 +1,144 @@
+-------------------------------------------------------------------------------
+-- Title      : WBGEN components
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : wbgen2_fifo_sync.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.wbgen2_pkg.all;
+
+
+entity wbgen2_fifo_sync is
+  generic (
+    g_width      : integer;
+    g_size       : integer;
+    g_usedw_size : integer);
+
+  port
+    (
+
+      clk_i     : in std_logic;
+      rst_n_i : in std_logic := '1';
+
+      wr_data_i : in std_logic_vector(g_width-1 downto 0);
+      wr_req_i  : in std_logic;
+
+      rd_data_o : out std_logic_vector(g_width-1 downto 0);
+      rd_req_i  : in  std_logic;
+
+      wr_empty_o : out std_logic;
+      wr_full_o  : out std_logic;
+      wr_usedw_o : out std_logic_vector(g_usedw_size -1 downto 0);
+
+      rd_empty_o : out std_logic;
+      rd_full_o  : out std_logic;
+      rd_usedw_o : out std_logic_vector(g_usedw_size -1 downto 0)
+
+      );
+end wbgen2_fifo_sync;
+
+
+architecture rtl of wbgen2_fifo_sync is
+
+
+  function f_log2_size (A : natural) return natural is
+  begin
+    for I in 1 to 64 loop               -- Works for up to 64 bits
+      if (2**I > A) then
+        return(I-1);
+      end if;
+    end loop;
+    return(63);
+  end function f_log2_size;
+
+  component generic_sync_fifo
+    generic (
+      g_data_width             : natural;
+      g_size                   : natural;
+      g_show_ahead             : boolean;
+      g_with_empty             : boolean;
+      g_with_full              : boolean;
+      g_with_almost_empty      : boolean;
+      g_with_almost_full       : boolean;
+      g_with_count             : boolean;
+      g_almost_empty_threshold : integer := 0;
+      g_almost_full_threshold  : integer := 0);
+    port (
+      rst_n_i        : in  std_logic := '1';
+      clk_i          : in  std_logic;
+      d_i            : in  std_logic_vector(g_data_width-1 downto 0);
+      we_i           : in  std_logic;
+      q_o            : out std_logic_vector(g_data_width-1 downto 0);
+      rd_i           : in  std_logic;
+      empty_o        : out std_logic;
+      full_o         : out std_logic;
+      almost_empty_o : out std_logic;
+      almost_full_o  : out std_logic;
+      count_o        : out std_logic_vector(f_log2_size(g_size)-1 downto 0));
+  end component;
+  
+  signal empty_int : std_logic;
+  signal full_int : std_logic;
+  signal usedw_int : std_logic_vector(g_usedw_size-1 downto 0);
+  
+begin
+
+  wrapped_fifo: generic_sync_fifo
+    generic map (
+      g_data_width             => g_width,
+      g_size                   => g_size,
+      g_show_ahead             => false,
+      g_with_empty             => true,
+      g_with_full              => true,
+      g_with_almost_empty      => false,
+      g_with_almost_full       => false,
+      g_with_count             => true)
+    port map (
+      rst_n_i        => rst_n_i,
+      clk_i          => clk_i,
+      d_i            => wr_data_i,
+      we_i           => wr_req_i,
+      q_o            => rd_data_o,
+      rd_i           => rd_req_i,
+      empty_o        => empty_int,
+      full_o         => full_int,
+      almost_empty_o => open,
+      almost_full_o  => open,
+      count_o        => usedw_int);
+  
+
+  rd_empty_o <= empty_int;
+  rd_full_o <= full_int;
+  rd_usedw_o <= usedw_int;
+
+  wr_empty_o <= empty_int;
+  wr_full_o <= full_int;
+  wr_usedw_o <= usedw_int;
+  
+  
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd
new file mode 100644
index 000000000..aabce15a7
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd
@@ -0,0 +1,154 @@
+-------------------------------------------------------------------------------
+-- Title      : WBGEN components
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : wbgen2_pkg.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011-2012 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+package wbgen2_pkg is
+
+  
+  component wbgen2_dpssram
+    generic (
+      g_data_width : natural;
+      g_size       : natural;
+      g_addr_width : natural;
+      g_dual_clock : boolean;
+      g_use_bwsel  : boolean);
+    port (
+      clk_a_i   : in  std_logic;
+      clk_b_i   : in  std_logic;
+      addr_a_i  : in  std_logic_vector(g_addr_width-1 downto 0);
+      addr_b_i  : in  std_logic_vector(g_addr_width-1 downto 0);
+      data_a_i  : in  std_logic_vector(g_data_width-1 downto 0);
+      data_b_i  : in  std_logic_vector(g_data_width-1 downto 0);
+      data_a_o  : out std_logic_vector(g_data_width-1 downto 0);
+      data_b_o  : out std_logic_vector(g_data_width-1 downto 0);
+      bwsel_a_i : in  std_logic_vector((g_data_width+7)/8-1 downto 0);
+      bwsel_b_i : in  std_logic_vector((g_data_width+7)/8-1 downto 0);
+      rd_a_i    : in  std_logic;
+      rd_b_i    : in  std_logic;
+      wr_a_i    : in  std_logic;
+      wr_b_i    : in  std_logic);
+  end component;
+
+
+  component wbgen2_eic
+    generic (
+      g_num_interrupts : natural;
+      g_irq00_mode     : integer;
+      g_irq01_mode     : integer;
+      g_irq02_mode     : integer;
+      g_irq03_mode     : integer;
+      g_irq04_mode     : integer;
+      g_irq05_mode     : integer;
+      g_irq06_mode     : integer;
+      g_irq07_mode     : integer;
+      g_irq08_mode     : integer;
+      g_irq09_mode     : integer;
+      g_irq0a_mode     : integer;
+      g_irq0b_mode     : integer;
+      g_irq0c_mode     : integer;
+      g_irq0d_mode     : integer;
+      g_irq0e_mode     : integer;
+      g_irq0f_mode     : integer;
+      g_irq10_mode     : integer;
+      g_irq11_mode     : integer;
+      g_irq12_mode     : integer;
+      g_irq13_mode     : integer;
+      g_irq14_mode     : integer;
+      g_irq15_mode     : integer;
+      g_irq16_mode     : integer;
+      g_irq17_mode     : integer;
+      g_irq18_mode     : integer;
+      g_irq19_mode     : integer;
+      g_irq1a_mode     : integer;
+      g_irq1b_mode     : integer;
+      g_irq1c_mode     : integer;
+      g_irq1d_mode     : integer;
+      g_irq1e_mode     : integer;
+      g_irq1f_mode     : integer);
+    port (
+      rst_n_i          : in  std_logic;
+      clk_i            : in  std_logic;
+      irq_i            : in  std_logic_vector(g_num_interrupts-1 downto 0);
+      irq_ack_o        : out std_logic_vector(g_num_interrupts-1 downto 0);
+      reg_imr_o        : out std_logic_vector(g_num_interrupts-1 downto 0);
+      reg_ier_i        : in  std_logic_vector(g_num_interrupts-1 downto 0);
+      reg_ier_wr_stb_i : in  std_logic;
+      reg_idr_i        : in  std_logic_vector(g_num_interrupts-1 downto 0);
+      reg_idr_wr_stb_i : in  std_logic;
+      reg_isr_o        : out std_logic_vector(g_num_interrupts-1 downto 0);
+      reg_isr_i        : in  std_logic_vector(g_num_interrupts-1 downto 0);
+      reg_isr_wr_stb_i : in  std_logic;
+      wb_irq_o         : out std_logic);
+  end component;
+
+  component wbgen2_fifo_async
+    generic (
+      g_size       : integer;
+      g_width      : integer;
+      g_usedw_size : integer);
+    port (
+      rst_n_i    : in  std_logic := '1';
+      rd_clk_i   : in  std_logic;
+      rd_req_i   : in  std_logic;
+      rd_data_o  : out std_logic_vector(g_width-1 downto 0);
+      rd_empty_o : out std_logic;
+      rd_full_o  : out std_logic;
+      rd_usedw_o : out std_logic_vector(g_usedw_size -1 downto 0);
+      wr_clk_i   : in  std_logic;
+      wr_req_i   : in  std_logic;
+      wr_data_i  : in  std_logic_vector(g_width-1 downto 0);
+      wr_empty_o : out std_logic;
+      wr_full_o  : out std_logic;
+      wr_usedw_o : out std_logic_vector(g_usedw_size -1 downto 0));
+  end component;
+
+
+  component wbgen2_fifo_sync
+    generic (
+      g_width      : integer;
+      g_size       : integer;
+      g_usedw_size : integer);
+    port (
+      clk_i      : in  std_logic;
+      rst_n_i    : in  std_logic := '1';
+      wr_data_i  : in  std_logic_vector(g_width-1 downto 0);
+      wr_req_i   : in  std_logic;
+      rd_data_o  : out std_logic_vector(g_width-1 downto 0);
+      rd_req_i   : in  std_logic;
+      wr_empty_o : out std_logic;
+      wr_full_o  : out std_logic;
+      wr_usedw_o : out std_logic_vector(g_usedw_size -1 downto 0);
+      rd_empty_o : out std_logic;
+      rd_full_o  : out std_logic;
+      rd_usedw_o : out std_logic_vector(g_usedw_size -1 downto 0));
+  end component;
+  
+end wbgen2_pkg;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd
new file mode 100644
index 000000000..b7dfdfafc
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd
@@ -0,0 +1,2130 @@
+-------------------------------------------------------------------------------
+-- Title      : Wishbone package
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : wishbone_pkg.vhd
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011-2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.genram_pkg.all;
+
+package wishbone_pkg is
+
+  constant c_wishbone_address_width : integer := 32;
+  constant c_wishbone_data_width    : integer := 32;
+
+  subtype t_wishbone_address is
+    std_logic_vector(c_wishbone_address_width-1 downto 0);
+  subtype t_wishbone_data is
+    std_logic_vector(c_wishbone_data_width-1 downto 0);
+  subtype t_wishbone_byte_select is
+    std_logic_vector((c_wishbone_address_width/8)-1 downto 0);
+  subtype t_wishbone_cycle_type is
+    std_logic_vector(2 downto 0);
+  subtype t_wishbone_burst_type is
+    std_logic_vector(1 downto 0);
+
+  type t_wishbone_interface_mode is (CLASSIC, PIPELINED);
+  type t_wishbone_address_granularity is (BYTE, WORD);
+
+  type t_wishbone_master_out is record
+    cyc : std_logic;
+    stb : std_logic;
+    adr : t_wishbone_address;
+    sel : t_wishbone_byte_select;
+    we  : std_logic;
+    dat : t_wishbone_data;
+  end record t_wishbone_master_out;
+
+  subtype t_wishbone_slave_in is t_wishbone_master_out;
+
+  type t_wishbone_slave_out is record
+    ack   : std_logic;
+    err   : std_logic;
+    rty   : std_logic;
+    stall : std_logic;
+    int   : std_logic;
+    dat   : t_wishbone_data;
+  end record t_wishbone_slave_out;
+  subtype t_wishbone_master_in is t_wishbone_slave_out;
+
+  subtype t_wishbone_device_descriptor is std_logic_vector(255 downto 0);
+
+  type t_wishbone_byte_select_array is array(natural range <>) of t_wishbone_byte_select; 
+  type t_wishbone_data_array is array(natural range <>) of t_wishbone_data; 
+  type t_wishbone_address_array is array(natural range <>) of t_wishbone_address;
+  type t_wishbone_master_out_array is array (natural range <>) of t_wishbone_master_out;
+  --type t_wishbone_slave_in_array is array (natural range <>) of t_wishbone_slave_in;
+  subtype t_wishbone_slave_in_array is t_wishbone_master_out_array;
+  type t_wishbone_slave_out_array is array (natural range <>) of t_wishbone_slave_out;
+  --type t_wishbone_master_in_array is array (natural range <>) of t_wishbone_master_in;
+  subtype t_wishbone_master_in_array is t_wishbone_slave_out_array;
+
+  constant cc_dummy_address : std_logic_vector(c_wishbone_address_width-1 downto 0) :=
+    (others => 'X');
+  constant cc_dummy_data : std_logic_vector(c_wishbone_data_width-1 downto 0) :=
+    (others => 'X');
+  constant cc_dummy_sel : std_logic_vector(c_wishbone_data_width/8-1 downto 0) :=
+    (others => 'X');
+  constant cc_dummy_slave_in : t_wishbone_slave_in :=
+    ('0', '0', cc_dummy_address, cc_dummy_sel, 'X', cc_dummy_data);
+  constant cc_dummy_master_out : t_wishbone_master_out := cc_dummy_slave_in;
+
+  -- Dangerous! Will stall a bus.
+  constant cc_dummy_slave_out : t_wishbone_slave_out :=
+    ('X', 'X', 'X', 'X', 'X', cc_dummy_data);
+  constant cc_dummy_master_in : t_wishbone_master_in := cc_dummy_slave_out;
+
+  constant cc_dummy_address_array : t_wishbone_address_array(0 downto 0) := (0 => cc_dummy_address);
+
+  -- A generally useful function.
+  function f_ceil_log2(x   : natural) return natural;
+  function f_bits2string(s : std_logic_vector) return string;
+
+  function f_string2bits(s : string) return std_logic_vector;
+  function f_string2svl (s : string) return std_logic_vector;
+  function f_slv2string (slv : std_logic_vector) return string;
+
+  function f_string_fix_len( s : string; ret_len : natural := 10; fill_char : character := '0'; justify_right : boolean := true ) return string;
+  function f_hot_to_bin(x : std_logic_vector) return natural;
+  
+  -- *** Wishbone slave interface functions ***
+  -- f_wb_wr:
+  -- processes an incoming write reqest to a register while honoring the select lines
+  -- valid modes are overwrite "owr", set "set" (bits are or'ed) and clear "clr" (bits are nand'ed)
+  function f_wb_wr(pval : std_logic_vector; ival : std_logic_vector; sel : std_logic_vector; mode : string := "owr") return std_logic_vector;
+------------------------------------------------------------------------------
+-- SDB declaration
+------------------------------------------------------------------------------
+
+  constant c_sdb_device_length : natural := 512;  -- bits
+  subtype  t_sdb_record is std_logic_vector(c_sdb_device_length-1 downto 0);
+  type     t_sdb_record_array is array(natural range <>) of t_sdb_record;
+  
+  type t_sdb_product is record
+    vendor_id : std_logic_vector(63 downto 0);
+    device_id : std_logic_vector(31 downto 0);
+    version   : std_logic_vector(31 downto 0);
+    date      : std_logic_vector(31 downto 0);
+    name      : string(1 to 19);
+  end record t_sdb_product;
+
+  type t_sdb_component is record
+    addr_first : std_logic_vector(63 downto 0);
+    addr_last  : std_logic_vector(63 downto 0);
+    product    : t_sdb_product;
+  end record t_sdb_component;
+
+  constant c_sdb_endian_big    : std_logic := '0';
+  constant c_sdb_endian_little : std_logic := '1';
+  type     t_sdb_device is record
+    abi_class     : std_logic_vector(15 downto 0);
+    abi_ver_major : std_logic_vector(7 downto 0);
+    abi_ver_minor : std_logic_vector(7 downto 0);
+    wbd_endian    : std_logic;          -- 0 = big, 1 = little
+    wbd_width     : std_logic_vector(3 downto 0);  -- 3=64-bit, 2=32-bit, 1=16-bit, 0=8-bit
+    sdb_component : t_sdb_component;
+  end record t_sdb_device;
+
+  type t_sdb_msi is record
+    wbd_endian    : std_logic;          -- 0 = big, 1 = little
+    wbd_width     : std_logic_vector(3 downto 0);  -- 3=64-bit, 2=32-bit, 1=16-bit, 0=8-bit
+    sdb_component : t_sdb_component;
+  end record t_sdb_msi;
+
+  type t_sdb_bridge is record
+    sdb_child     : std_logic_vector(63 downto 0);
+    sdb_component : t_sdb_component;
+  end record t_sdb_bridge;
+
+  type t_sdb_integration is record
+    product : t_sdb_product;
+  end record t_sdb_integration;
+
+  type t_sdb_repo_url is record
+    repo_url : string(1 to 63);
+  end record t_sdb_repo_url;
+
+  type t_sdb_synthesis is record
+    syn_module_name  : string(1 to 16);
+    syn_commit_id    : string(1 to 32);
+    syn_tool_name    : string(1 to 8);
+    syn_tool_version : std_logic_vector(31 downto 0);
+    syn_date         : std_logic_vector(31 downto 0);
+    syn_username     : string(1 to 15);
+  end record t_sdb_synthesis;
+  
+  -- If you have a Wishbone master that does not receive MSI,
+  -- list it in the layout as 'f_sdb_auto_msi(c_null_msi, false)'
+  constant c_null_msi : t_sdb_msi := (
+   wbd_endian    => c_sdb_endian_big,
+   wbd_width     => x"0",
+   sdb_component => (
+   addr_first    => x"0000000000000000",
+   addr_last     => x"0000000000000000",
+   product => (
+   vendor_id     => x"0000000000000000",
+   device_id     => x"00000000",
+   version       => x"00000000",
+   date          => x"00000000",
+   name          => "                   ")));  
+
+  -- general crossbar building functions
+  function f_sdb_create_array(g_enum_dev_id  : boolean := false;
+                              g_dev_id_offs    : natural := 0;
+                              g_enum_dev_name  : boolean := false;
+                              g_dev_name_offs  : natural := 0;       
+                              device           : t_sdb_device; 
+                              instances        : natural := 1) return t_sdb_record_array;  
+  function f_sdb_join_arrays(a : t_sdb_record_array; b : t_sdb_record_array) return t_sdb_record_array;
+  function f_sdb_extract_base_addr(sdb_record : t_sdb_record) return std_logic_vector;
+  function f_sdb_extract_end_addr(sdb_record : t_sdb_record)  return std_logic_vector;
+  function f_sdb_automap_array(sdb_array : t_sdb_record_array; start_offset : t_wishbone_address := (others => '0')) return t_sdb_record_array;  
+  function f_align_addr_offset(offs : unsigned; this_rng : unsigned; prev_rng : unsigned) return unsigned; 
+  function f_sdb_create_rom_addr(sdb_array : t_sdb_record_array) return t_wishbone_address;
+
+
+  -- Used to configure a device at a certain address
+  function f_sdb_embed_device(device : t_sdb_device; address : t_wishbone_address) return t_sdb_record;
+  function f_sdb_embed_bridge(bridge : t_sdb_bridge; address : t_wishbone_address) return t_sdb_record;
+  function f_sdb_embed_msi(msi : t_sdb_msi; address : t_wishbone_address) return t_sdb_record;
+  function f_sdb_embed_integration(integr : t_sdb_integration) return t_sdb_record;
+  function f_sdb_embed_repo_url(url : t_sdb_repo_url) return t_sdb_record;
+  function f_sdb_embed_synthesis(syn : t_sdb_synthesis) return t_sdb_record;
+
+  function f_sdb_extract_device(sdb_record : t_sdb_record) return t_sdb_device;
+  function f_sdb_extract_bridge(sdb_record : t_sdb_record) return t_sdb_bridge;
+  function f_sdb_extract_msi(sdb_record : t_sdb_record) return t_sdb_msi;
+  function f_sdb_extract_integration(sdb_record : t_sdb_record) return t_sdb_integration;
+  function f_sdb_extract_repo_url(sdb_record : t_sdb_record) return t_sdb_repo_url;
+  function f_sdb_extract_synthesis(sdb_record : t_sdb_record) return t_sdb_synthesis;
+
+  -- Automatic crossbar mapping functions
+  function f_sdb_auto_device(device : t_sdb_device; enable : boolean := true; name: string := "") return t_sdb_record;
+  function f_sdb_auto_bridge(bridge : t_sdb_bridge; enable : boolean := true; name: string := "") return t_sdb_record;
+  function f_sdb_auto_msi   (msi    : t_sdb_msi;    enable : boolean := true) return t_sdb_record;
+  function f_sdb_auto_layout(records: t_sdb_record_array)                               return t_sdb_record_array;
+  function f_sdb_auto_layout(slaves : t_sdb_record_array; masters : t_sdb_record_array) return t_sdb_record_array;
+  function f_sdb_auto_sdb   (records: t_sdb_record_array)                               return t_wishbone_address;
+  function f_sdb_auto_sdb   (slaves : t_sdb_record_array; masters : t_sdb_record_array) return t_wishbone_address;
+  
+  -- For internal use by the crossbar
+  function f_sdb_bus_end(g_wraparound : boolean; g_layout : t_sdb_record_array; g_sdb_addr : t_wishbone_address; msi : boolean) return unsigned;
+  function f_sdb_embed_product(product         : t_sdb_product) return std_logic_vector;  -- (319 downto 8)
+  function f_sdb_embed_component(sdb_component : t_sdb_component; address : t_wishbone_address) return std_logic_vector;  -- (447 downto 8)
+  function f_sdb_extract_product(sdb_record    : std_logic_vector(319 downto 8)) return t_sdb_product;
+  function f_sdb_extract_component(sdb_record  : std_logic_vector(447 downto 8)) return t_sdb_component;
+
+------------------------------------------------------------------------------
+-- Components declaration
+-------------------------------------------------------------------------------
+
+  component wb_slave_adapter
+    generic (
+      g_master_use_struct  : boolean;
+      g_master_mode        : t_wishbone_interface_mode;
+      g_master_granularity : t_wishbone_address_granularity;
+      g_slave_use_struct   : boolean;
+      g_slave_mode         : t_wishbone_interface_mode;
+      g_slave_granularity  : t_wishbone_address_granularity);
+    port (
+      clk_sys_i  : in  std_logic;
+      rst_n_i    : in  std_logic;
+      sl_adr_i   : in  std_logic_vector(c_wishbone_address_width-1 downto 0) := cc_dummy_address;
+      sl_dat_i   : in  std_logic_vector(c_wishbone_data_width-1 downto 0)    := cc_dummy_data;
+      sl_sel_i   : in  std_logic_vector(c_wishbone_data_width/8-1 downto 0)  := cc_dummy_sel;
+      sl_cyc_i   : in  std_logic                                             := '0';
+      sl_stb_i   : in  std_logic                                             := '0';
+      sl_we_i    : in  std_logic                                             := '0';
+      sl_dat_o   : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+      sl_err_o   : out std_logic;
+      sl_rty_o   : out std_logic;
+      sl_ack_o   : out std_logic;
+      sl_stall_o : out std_logic;
+      sl_int_o   : out std_logic;
+      slave_i    : in  t_wishbone_slave_in                                   := cc_dummy_slave_in;
+      slave_o    : out t_wishbone_slave_out;
+      ma_adr_o   : out std_logic_vector(c_wishbone_address_width-1 downto 0);
+      ma_dat_o   : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+      ma_sel_o   : out std_logic_vector(c_wishbone_data_width/8-1 downto 0);
+      ma_cyc_o   : out std_logic;
+      ma_stb_o   : out std_logic;
+      ma_we_o    : out std_logic;
+      ma_dat_i   : in  std_logic_vector(c_wishbone_data_width-1 downto 0)    := cc_dummy_data;
+      ma_err_i   : in  std_logic                                             := '0';
+      ma_rty_i   : in  std_logic                                             := '0';
+      ma_ack_i   : in  std_logic                                             := '0';
+      ma_stall_i : in  std_logic                                             := '0';
+      ma_int_i   : in  std_logic                                             := '0';
+      master_i   : in  t_wishbone_master_in                                  := cc_dummy_slave_out;
+      master_o   : out t_wishbone_master_out);
+  end component;
+
+  component wb_async_bridge
+    generic (
+      g_simulation          : integer;
+      g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
+      g_address_granularity : t_wishbone_address_granularity := WORD;
+      g_cpu_address_width   : integer);
+    port (
+      rst_n_i     : in    std_logic;
+      clk_sys_i   : in    std_logic;
+      cpu_cs_n_i  : in    std_logic;
+      cpu_wr_n_i  : in    std_logic;
+      cpu_rd_n_i  : in    std_logic;
+      cpu_bs_n_i  : in    std_logic_vector(3 downto 0);
+      cpu_addr_i  : in    std_logic_vector(g_cpu_address_width-1 downto 0);
+      cpu_data_b  : inout std_logic_vector(31 downto 0);
+      cpu_nwait_o : out   std_logic;
+      wb_adr_o    : out   std_logic_vector(c_wishbone_address_width - 1 downto 0);
+      wb_dat_o    : out   std_logic_vector(31 downto 0);
+      wb_stb_o    : out   std_logic;
+      wb_we_o     : out   std_logic;
+      wb_sel_o    : out   std_logic_vector(3 downto 0);
+      wb_cyc_o    : out   std_logic;
+      wb_dat_i    : in    std_logic_vector (c_wishbone_data_width-1 downto 0);
+      wb_ack_i    : in    std_logic;
+      wb_stall_i  : in    std_logic := '0');
+  end component;
+
+  component xwb_async_bridge
+    generic (
+      g_simulation          : integer;
+      g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
+      g_address_granularity : t_wishbone_address_granularity := WORD;
+      g_cpu_address_width   : integer);
+    port (
+      rst_n_i     : in    std_logic;
+      clk_sys_i   : in    std_logic;
+      cpu_cs_n_i  : in    std_logic;
+      cpu_wr_n_i  : in    std_logic;
+      cpu_rd_n_i  : in    std_logic;
+      cpu_bs_n_i  : in    std_logic_vector(3 downto 0);
+      cpu_addr_i  : in    std_logic_vector(g_cpu_address_width-1 downto 0);
+      cpu_data_b  : inout std_logic_vector(31 downto 0);
+      cpu_nwait_o : out   std_logic;
+      master_o    : out   t_wishbone_master_out;
+      master_i    : in    t_wishbone_master_in);
+  end component;
+
+  component xwb_bus_fanout
+    generic (
+      g_num_outputs          : natural;
+      g_bits_per_slave       : integer;
+      g_address_granularity  : t_wishbone_address_granularity := WORD;
+      g_slave_interface_mode : t_wishbone_interface_mode      := CLASSIC);
+    port (
+      clk_sys_i : in  std_logic;
+      rst_n_i   : in  std_logic;
+      slave_i   : in  t_wishbone_slave_in;
+      slave_o   : out t_wishbone_slave_out;
+      master_i  : in  t_wishbone_master_in_array(0 to g_num_outputs-1);
+      master_o  : out t_wishbone_master_out_array(0 to g_num_outputs-1));
+  end component;
+
+  component xwb_crossbar
+    generic (
+      g_num_masters : integer;
+      g_num_slaves  : integer;
+      g_registered  : boolean;
+      g_address     : t_wishbone_address_array;
+      g_mask        : t_wishbone_address_array);
+    port (
+      clk_sys_i : in  std_logic;
+      rst_n_i   : in  std_logic;
+      slave_i   : in  t_wishbone_slave_in_array(g_num_masters-1 downto 0);
+      slave_o   : out t_wishbone_slave_out_array(g_num_masters-1 downto 0);
+      master_i  : in  t_wishbone_master_in_array(g_num_slaves-1 downto 0);
+      master_o  : out t_wishbone_master_out_array(g_num_slaves-1 downto 0);
+      sdb_sel_o : out std_logic_vector(g_num_masters-1 downto 0)); -- leave open!
+  end component;
+
+  -- Use the f_xwb_bridge_*_sdb to bridge a crossbar to another
+  function f_xwb_bridge_manual_sdb(     -- take a manual bus size
+    g_size     : t_wishbone_address;
+    g_sdb_addr : t_wishbone_address) return t_sdb_bridge;
+
+  function f_xwb_bridge_layout_sdb(     -- determine bus size from layout
+    g_wraparound : boolean := true;
+    g_layout     : t_sdb_record_array;
+    g_sdb_addr   : t_wishbone_address) return t_sdb_bridge;
+
+  function f_xwb_msi_manual_sdb(        -- take a manual bus size
+    g_size     : t_wishbone_address) return t_sdb_msi;
+
+  function f_xwb_msi_layout_sdb(     -- determine MSI size from layout
+    g_layout     : t_sdb_record_array) return t_sdb_msi;
+
+  component xwb_sdb_crossbar
+    generic (
+      g_num_masters : integer;
+      g_num_slaves  : integer;
+      g_registered  : boolean := false;
+      g_wraparound  : boolean := true;
+      g_layout      : t_sdb_record_array;
+      g_sdb_addr    : t_wishbone_address;
+      g_sdb_name    : string := "WB4-Crossbar-GSI   ");
+    port (
+      clk_sys_i     : in  std_logic;
+      rst_n_i       : in  std_logic;
+      slave_i       : in  t_wishbone_slave_in_array  (g_num_masters-1 downto 0);
+      slave_o       : out t_wishbone_slave_out_array (g_num_masters-1 downto 0);
+      msi_master_i  : in  t_wishbone_master_in_array (g_num_masters-1 downto 0) := (others => cc_dummy_master_in);
+      msi_master_o  : out t_wishbone_master_out_array(g_num_masters-1 downto 0);
+      master_i      : in  t_wishbone_master_in_array (g_num_slaves -1 downto 0);
+      master_o      : out t_wishbone_master_out_array(g_num_slaves -1 downto 0);
+      msi_slave_i   : in  t_wishbone_slave_in_array  (g_num_slaves -1 downto 0) := (others => cc_dummy_slave_in);
+      msi_slave_o   : out t_wishbone_slave_out_array (g_num_slaves -1 downto 0));
+  end component;
+  
+  component xwb_register_link -- puts a register of delay between crossbars
+    port(
+      clk_sys_i : in  std_logic;
+      rst_n_i   : in  std_logic;
+      slave_i   : in  t_wishbone_slave_in;
+      slave_o   : out t_wishbone_slave_out;
+      master_i  : in  t_wishbone_master_in;
+      master_o  : out t_wishbone_master_out);
+  end component;
+
+  -- skidpad. acts like a fifo in wb flow control, but costs less
+  component wb_skidpad is
+  generic(
+     g_adrbits   : natural   := 32
+  );
+  Port(
+     clk_i        : std_logic;
+     rst_n_i      : std_logic;
+
+     push_i       : in  std_logic;
+     pop_i        : in  std_logic;
+     full_o       : out std_logic;
+     empty_o      : out std_logic;
+
+     adr_i        : in  std_logic_vector(g_adrbits-1 downto 0);
+     dat_i        : in  std_logic_vector(32-1 downto 0);
+     sel_i        : in  std_logic_vector(4-1 downto 0);
+     we_i         : in  std_logic;
+
+     adr_o        : out std_logic_vector(g_adrbits-1 downto 0);
+     dat_o        : out std_logic_vector(32-1 downto 0);
+     sel_o        : out std_logic_vector(4-1 downto 0);
+     we_o         : out std_logic
+  );
+  end component;
+
+  component sdb_rom is
+    generic(
+      g_layout  : t_sdb_record_array;
+      g_masters : natural;
+      g_bus_end : unsigned(63 downto 0);
+      g_sdb_name    : string := "WB4-Crossbar-GSI   ");
+    port(
+      clk_sys_i : in  std_logic;
+      master_i  : in  std_logic_vector(g_masters-1 downto 0);
+      slave_i   : in  t_wishbone_slave_in;
+      slave_o   : out t_wishbone_slave_out);
+  end component;
+  
+  constant c_xwb_dma_sdb : t_sdb_device := (
+    abi_class     => x"0000",              -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"00",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"7",                 -- 8/16/32-bit port granularity
+    sdb_component => (
+      addr_first  => x"0000000000000000",
+      addr_last   => x"000000000000001f",
+      product     => (
+        vendor_id => x"0000000000000651",  -- GSI
+        device_id => x"cababa56",
+        version   => x"00000001",
+        date      => x"20120518",
+        name      => "WB4-Streaming-DMA_0")));
+  component xwb_dma is
+    generic(
+      -- Value 0 cannot stream
+      -- Value 1 only slaves with async ACK can stream
+      -- Value 2 only slaves with combined latency <= 2 can stream
+      -- Value 3 only slaves with combined latency <= 6 can stream
+      -- Value 4 only slaves with combined latency <= 14 can stream
+      -- ....
+      logRingLen : integer := 4
+      );
+    port(
+      -- Common wishbone signals
+      clk_i       : in  std_logic;
+      rst_n_i     : in  std_logic;
+      slave_i     : in  t_wishbone_slave_in;
+      slave_o     : out t_wishbone_slave_out;
+      -- Master reader port
+      r_master_i  : in  t_wishbone_master_in;
+      r_master_o  : out t_wishbone_master_out;
+      -- Master writer port
+      w_master_i  : in  t_wishbone_master_in;
+      w_master_o  : out t_wishbone_master_out;
+      -- Pulsed high completion signal
+      interrupt_o : out std_logic
+      );
+  end component;
+
+  -- If you reset one clock domain, you must reset BOTH!
+  -- Release of the reset lines may be arbitrarily out-of-phase
+  component xwb_clock_crossing is
+    generic(
+      g_size : natural := 16);
+    port(
+      -- Slave control port
+      slave_clk_i    : in  std_logic;
+      slave_rst_n_i  : in  std_logic;
+      slave_i        : in  t_wishbone_slave_in;
+      slave_o        : out t_wishbone_slave_out;
+      -- Master reader port
+      master_clk_i   : in  std_logic;
+      master_rst_n_i : in  std_logic;
+      master_i       : in  t_wishbone_master_in;
+      master_o       : out t_wishbone_master_out;
+      -- Flow control back-channel for acks
+      slave_ready_o : out std_logic;
+      slave_stall_i : in  std_logic := '0');
+  end component;
+
+  -- g_size is in words
+  function f_xwb_dpram(g_size : natural) return t_sdb_device;
+  component xwb_dpram
+    generic (
+      g_size                  : natural;
+      g_init_file             : string                         := "";
+      g_must_have_init_file   : boolean                        := true;
+      g_slave1_interface_mode : t_wishbone_interface_mode      := CLASSIC;
+      g_slave2_interface_mode : t_wishbone_interface_mode      := CLASSIC;
+      g_slave1_granularity    : t_wishbone_address_granularity := WORD;
+      g_slave2_granularity    : t_wishbone_address_granularity := WORD);
+    port (
+      clk_sys_i : in  std_logic;
+      rst_n_i   : in  std_logic;
+      slave1_i  : in  t_wishbone_slave_in;
+      slave1_o  : out t_wishbone_slave_out;
+      slave2_i  : in  t_wishbone_slave_in;
+      slave2_o  : out t_wishbone_slave_out);
+  end component;
+
+  component xwb_dpram_mixed
+  generic(
+    g_size                  : natural := 16384;
+    g_init_file             : string  := "";
+    g_must_have_init_file   : boolean := true;
+    g_swap_word_endianness  : boolean := true;
+    g_slave1_interface_mode : t_wishbone_interface_mode;
+    g_slave2_interface_mode : t_wishbone_interface_mode;
+    g_dpram_port_a_width    : integer := 16;
+    g_dpram_port_b_width    : integer := 32;
+    g_slave1_granularity    : t_wishbone_address_granularity;
+    g_slave2_granularity    : t_wishbone_address_granularity);
+  port(
+    clk_slave1_i  : in std_logic;
+    clk_slave2_i  : in std_logic;
+    rst_n_i       : in std_logic;
+
+    slave1_i      : in  t_wishbone_slave_in;
+    slave1_o      : out t_wishbone_slave_out;
+    slave2_i      : in  t_wishbone_slave_in;
+    slave2_o      : out t_wishbone_slave_out);
+  end component;
+  
+  -- Just like the DMA controller, but constantly at address 0
+  component xwb_streamer is
+    generic(
+      -- Value 0 cannot stream
+      -- Value 1 only slaves with async ACK can stream
+      -- Value 2 only slaves with combined latency = 2 can stream
+      -- Value 3 only slaves with combined latency = 6 can stream
+      -- Value 4 only slaves with combined latency = 14 can stream
+      -- ....
+      logRingLen : integer := 4
+    );
+    port(
+      -- Common wishbone signals
+      clk_i       : in  std_logic;
+      rst_n_i     : in  std_logic;
+      -- Master reader port
+      r_master_i  : in  t_wishbone_master_in;
+      r_master_o  : out t_wishbone_master_out;
+      -- Master writer port
+      w_master_i  : in  t_wishbone_master_in;
+      w_master_o  : out t_wishbone_master_out);
+  end component;
+
+
+  constant c_xwb_gpio_port_sdb : t_sdb_device := (
+    abi_class     => x"0000",              -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"01",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"7",                 -- 8/16/32-bit port granularity
+    sdb_component => (
+      addr_first  => x"0000000000000000",
+      addr_last   => x"00000000000000ff",
+      product     => (
+        vendor_id => x"000000000000CE42",  -- CERN
+        device_id => x"441c5143",
+        version   => x"00000001",
+        date      => x"20121129",
+        name      => "WB-GPIO-Port       ")));
+
+
+  component wb_gpio_port
+    generic (
+      g_interface_mode         : t_wishbone_interface_mode      := CLASSIC;
+      g_address_granularity    : t_wishbone_address_granularity := WORD;
+      g_num_pins               : natural range 1 to 256;
+      g_with_builtin_tristates : boolean                        := false);
+    port (
+      clk_sys_i  : in    std_logic;
+      rst_n_i    : in    std_logic;
+      wb_sel_i   : in    std_logic_vector(c_wishbone_data_width/8-1 downto 0);
+      wb_cyc_i   : in    std_logic;
+      wb_stb_i   : in    std_logic;
+      wb_we_i    : in    std_logic;
+      wb_adr_i   : in    std_logic_vector(7 downto 0);
+      wb_dat_i   : in    std_logic_vector(c_wishbone_data_width-1 downto 0);
+      wb_dat_o   : out   std_logic_vector(c_wishbone_data_width-1 downto 0);
+      wb_ack_o   : out   std_logic;
+      wb_stall_o : out   std_logic;
+      gpio_b     : inout std_logic_vector(g_num_pins-1 downto 0);
+      gpio_out_o : out   std_logic_vector(g_num_pins-1 downto 0);
+      gpio_in_i  : in    std_logic_vector(g_num_pins-1 downto 0);
+      gpio_oen_o : out   std_logic_vector(g_num_pins-1 downto 0));
+  end component;
+
+  component xwb_gpio_port
+    generic (
+      g_interface_mode         : t_wishbone_interface_mode      := CLASSIC;
+      g_address_granularity    : t_wishbone_address_granularity := WORD;
+      g_num_pins               : natural range 1 to 256;
+      g_with_builtin_tristates : boolean);
+    port (
+      clk_sys_i  : in    std_logic;
+      rst_n_i    : in    std_logic;
+      slave_i    : in    t_wishbone_slave_in;
+      slave_o    : out   t_wishbone_slave_out;
+      desc_o     : out   t_wishbone_device_descriptor;
+      gpio_b     : inout std_logic_vector(g_num_pins-1 downto 0);
+      gpio_out_o : out   std_logic_vector(g_num_pins-1 downto 0);
+      gpio_in_i  : in    std_logic_vector(g_num_pins-1 downto 0);
+      gpio_oen_o : out   std_logic_vector(g_num_pins-1 downto 0));
+  end component;
+
+  constant c_xwb_i2c_master_sdb : t_sdb_device := (
+    abi_class     => x"0000",              -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"01",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"7",                 -- 8/16/32-bit port granularity
+    sdb_component => (
+      addr_first  => x"0000000000000000",
+      addr_last   => x"00000000000000ff",
+      product     => (
+        vendor_id => x"000000000000CE42",  -- CERN
+        device_id => x"123c5443",
+        version   => x"00000001",
+        date      => x"20121129",
+        name      => "WB-I2C-Master      ")));
+
+
+  component wb_i2c_master
+    generic (
+      g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
+      g_address_granularity : t_wishbone_address_granularity := WORD;
+      g_num_interfaces      : integer := 1);
+    port (
+      clk_sys_i    : in  std_logic;
+      rst_n_i      : in  std_logic;
+      wb_adr_i     : in  std_logic_vector(4 downto 0);
+      wb_dat_i     : in  std_logic_vector(31 downto 0);
+      wb_dat_o     : out std_logic_vector(31 downto 0);
+      wb_sel_i     : in  std_logic_vector(3 downto 0);
+      wb_stb_i     : in  std_logic;
+      wb_cyc_i     : in  std_logic;
+      wb_we_i      : in  std_logic;
+      wb_ack_o     : out std_logic;
+      wb_int_o     : out std_logic;
+      wb_stall_o   : out std_logic;
+      scl_pad_i    : in  std_logic_vector(g_num_interfaces-1 downto 0);
+      scl_pad_o    : out std_logic_vector(g_num_interfaces-1 downto 0);
+      scl_padoen_o : out std_logic_vector(g_num_interfaces-1 downto 0);
+      sda_pad_i    : in  std_logic_vector(g_num_interfaces-1 downto 0);
+      sda_pad_o    : out std_logic_vector(g_num_interfaces-1 downto 0);
+      sda_padoen_o : out std_logic_vector(g_num_interfaces-1 downto 0));
+  end component;
+
+  component xwb_i2c_master
+    generic (
+      g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
+      g_address_granularity : t_wishbone_address_granularity := WORD;
+      g_num_interfaces      : integer := 1);
+    port (
+      clk_sys_i    : in  std_logic;
+      rst_n_i      : in  std_logic;
+      slave_i      : in  t_wishbone_slave_in;
+      slave_o      : out t_wishbone_slave_out;
+      desc_o       : out t_wishbone_device_descriptor;
+      scl_pad_i    : in  std_logic_vector(g_num_interfaces-1 downto 0);
+      scl_pad_o    : out std_logic_vector(g_num_interfaces-1 downto 0);
+      scl_padoen_o : out std_logic_vector(g_num_interfaces-1 downto 0);
+      sda_pad_i    : in  std_logic_vector(g_num_interfaces-1 downto 0);
+      sda_pad_o    : out std_logic_vector(g_num_interfaces-1 downto 0);
+      sda_padoen_o : out std_logic_vector(g_num_interfaces-1 downto 0));
+  end component;
+
+  component xwb_lm32
+    generic (
+      g_profile : string;
+      g_reset_vector : std_logic_vector(31 downto 0) := x"00000000";
+      g_sdb_address  : std_logic_vector(31 downto 0) := x"00000000");
+    port (
+      clk_sys_i : in  std_logic;
+      rst_n_i   : in  std_logic;
+      irq_i     : in  std_logic_vector(31 downto 0);
+      dwb_o     : out t_wishbone_master_out;
+      dwb_i     : in  t_wishbone_master_in;
+      iwb_o     : out t_wishbone_master_out;
+      iwb_i     : in  t_wishbone_master_in);
+  end component;
+
+  constant c_xwb_onewire_master_sdb : t_sdb_device := (
+    abi_class     => x"0000",              -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"01",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"7",                 -- 8/16/32-bit port granularity
+    sdb_component => (
+      addr_first  => x"0000000000000000",
+      addr_last   => x"00000000000000ff",
+      product     => (
+        vendor_id => x"000000000000CE42",  -- CERN
+        device_id => x"779c5443",
+        version   => x"00000001",
+        date      => x"20121129",
+        name      => "WB-OneWire-Master  ")));
+
+  component wb_onewire_master
+    generic (
+      g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
+      g_address_granularity : t_wishbone_address_granularity := WORD;
+      g_num_ports           : integer;
+      g_ow_btp_normal       : string                         := "1.0";
+      g_ow_btp_overdrive    : string                         := "5.0");
+    port (
+      clk_sys_i   : in  std_logic;
+      rst_n_i     : in  std_logic;
+      wb_cyc_i    : in  std_logic;
+      wb_sel_i    : in  std_logic_vector(c_wishbone_data_width/8-1 downto 0);
+      wb_stb_i    : in  std_logic;
+      wb_we_i     : in  std_logic;
+      wb_adr_i    : in  std_logic_vector(2 downto 0);
+      wb_dat_i    : in  std_logic_vector(c_wishbone_data_width-1 downto 0);
+      wb_dat_o    : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+      wb_ack_o    : out std_logic;
+      wb_int_o    : out std_logic;
+      wb_stall_o  : out std_logic;
+      owr_pwren_o : out std_logic_vector(g_num_ports -1 downto 0);
+      owr_en_o    : out std_logic_vector(g_num_ports -1 downto 0);
+      owr_i       : in  std_logic_vector(g_num_ports -1 downto 0));
+  end component;
+
+  component xwb_onewire_master
+    generic (
+      g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
+      g_address_granularity : t_wishbone_address_granularity := WORD;
+      g_num_ports           : integer;
+      g_ow_btp_normal       : string                         := "5.0";
+      g_ow_btp_overdrive    : string                         := "1.0");
+    port (
+      clk_sys_i   : in  std_logic;
+      rst_n_i     : in  std_logic;
+      slave_i     : in  t_wishbone_slave_in;
+      slave_o     : out t_wishbone_slave_out;
+      desc_o      : out t_wishbone_device_descriptor;
+      owr_pwren_o : out std_logic_vector(g_num_ports -1 downto 0);
+      owr_en_o    : out std_logic_vector(g_num_ports -1 downto 0);
+      owr_i       : in  std_logic_vector(g_num_ports -1 downto 0));
+  end component;
+
+  constant c_xwb_spi_sdb : t_sdb_device := (
+    abi_class     => x"0000",              -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"01",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"7",                 -- 8/16/32-bit port granularity
+    sdb_component => (
+      addr_first  => x"0000000000000000",
+      addr_last   => x"000000000000001F",
+      product     => (
+        vendor_id => x"000000000000CE42",  -- CERN
+        device_id => x"e503947e",       -- echo "WB-SPI.Control     " | md5sum | cut -c1-8
+        version   => x"00000001",
+        date      => x"20121116",
+        name      => "WB-SPI.Control     ")));
+
+  component wb_spi
+    generic (
+      g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
+      g_address_granularity : t_wishbone_address_granularity := WORD;
+      g_divider_len         : integer := 16;
+      g_max_char_len        : integer := 128;
+      g_num_slaves          : integer := 8);
+    port (
+      clk_sys_i  : in  std_logic;
+      rst_n_i    : in  std_logic;
+      wb_adr_i   : in  std_logic_vector(4 downto 0);
+      wb_dat_i   : in  std_logic_vector(31 downto 0);
+      wb_dat_o   : out std_logic_vector(31 downto 0);
+      wb_sel_i   : in  std_logic_vector(3 downto 0);
+      wb_stb_i   : in  std_logic;
+      wb_cyc_i   : in  std_logic;
+      wb_we_i    : in  std_logic;
+      wb_ack_o   : out std_logic;
+      wb_err_o   : out std_logic;
+      wb_int_o   : out std_logic;
+      wb_stall_o : out std_logic;
+      pad_cs_o   : out std_logic_vector(g_num_slaves-1 downto 0);
+      pad_sclk_o : out std_logic;
+      pad_mosi_o : out std_logic;
+      pad_miso_i : in  std_logic);
+  end component;
+
+  component xwb_spi
+    generic (
+      g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
+      g_address_granularity : t_wishbone_address_granularity := WORD;
+      g_divider_len         : integer := 16;
+      g_max_char_len        : integer := 128;
+      g_num_slaves          : integer := 8);
+    port (
+      clk_sys_i  : in  std_logic;
+      rst_n_i    : in  std_logic;
+      slave_i    : in  t_wishbone_slave_in;
+      slave_o    : out t_wishbone_slave_out;
+      desc_o     : out t_wishbone_device_descriptor;
+      pad_cs_o   : out std_logic_vector(g_num_slaves-1 downto 0);
+      pad_sclk_o : out std_logic;
+      pad_mosi_o : out std_logic;
+      pad_miso_i : in  std_logic);
+  end component;
+
+  component wb_simple_uart
+    generic (
+      g_with_virtual_uart   : boolean                        := false;
+      g_with_physical_uart  : boolean                        := true;
+      g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
+      g_address_granularity : t_wishbone_address_granularity := WORD;
+      g_vuart_fifo_size     : integer := 1024);
+    port (
+      clk_sys_i  : in  std_logic;
+      rst_n_i    : in  std_logic;
+      wb_adr_i   : in  std_logic_vector(4 downto 0);
+      wb_dat_i   : in  std_logic_vector(31 downto 0);
+      wb_dat_o   : out std_logic_vector(31 downto 0);
+      wb_cyc_i   : in  std_logic;
+      wb_sel_i   : in  std_logic_vector(3 downto 0);
+      wb_stb_i   : in  std_logic;
+      wb_we_i    : in  std_logic;
+      wb_ack_o   : out std_logic;
+      wb_stall_o : out std_logic;
+      uart_rxd_i : in  std_logic := '1';
+      uart_txd_o : out std_logic);
+  end component;
+
+  component xwb_simple_uart
+    generic (
+      g_with_virtual_uart   : boolean                        := false;
+      g_with_physical_uart  : boolean                        := true;
+      g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
+      g_address_granularity : t_wishbone_address_granularity := WORD;
+      g_vuart_fifo_size     : integer := 1024);
+    port (
+      clk_sys_i  : in  std_logic;
+      rst_n_i    : in  std_logic;
+      slave_i    : in  t_wishbone_slave_in;
+      slave_o    : out t_wishbone_slave_out;
+      desc_o     : out t_wishbone_device_descriptor;
+      uart_rxd_i : in  std_logic := '1';
+      uart_txd_o : out std_logic);
+  end component;
+
+  component wb_simple_pwm
+    generic (
+      g_num_channels        : integer range 1 to 8;
+      g_regs_size           : integer range 1 to 16 := 16;
+      g_default_period      : integer range 0 to 255 := 0;
+      g_default_presc       : integer range 0 to 255 := 0;
+      g_default_val         : integer range 0 to 255 := 0;
+      g_interface_mode      : t_wishbone_interface_mode      := PIPELINED;
+      g_address_granularity : t_wishbone_address_granularity := BYTE);
+    port (
+      clk_sys_i  : in  std_logic;
+      rst_n_i    : in  std_logic;
+      wb_adr_i   : in  std_logic_vector(5 downto 0);
+      wb_dat_i   : in  std_logic_vector(31 downto 0);
+      wb_dat_o   : out std_logic_vector(31 downto 0);
+      wb_cyc_i   : in  std_logic;
+      wb_sel_i   : in  std_logic_vector(3 downto 0);
+      wb_stb_i   : in  std_logic;
+      wb_we_i    : in  std_logic;
+      wb_ack_o   : out std_logic;
+      wb_stall_o : out std_logic;
+      pwm_o      : out std_logic_vector(g_num_channels-1 downto 0));
+  end component;
+
+  component xwb_simple_pwm
+    generic (
+      g_num_channels        : integer range 1 to 8;
+      g_regs_size           : integer range 1 to 16 := 16;
+      g_default_period      : integer range 0 to 255 := 0;
+      g_default_presc       : integer range 0 to 255 := 0;
+      g_default_val         : integer range 0 to 255 := 0;
+      g_interface_mode      : t_wishbone_interface_mode      := PIPELINED;
+      g_address_granularity : t_wishbone_address_granularity := BYTE);
+    port (
+      clk_sys_i : in  std_logic;
+      rst_n_i   : in  std_logic;
+      slave_i   : in  t_wishbone_slave_in;
+      slave_o   : out t_wishbone_slave_out;
+      pwm_o     : out std_logic_vector(g_num_channels-1 downto 0));
+  end component;
+
+  component wb_tics
+    generic (
+      g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
+      g_address_granularity : t_wishbone_address_granularity := WORD;
+      g_period              : integer);
+    port (
+      rst_n_i    : in  std_logic;
+      clk_sys_i  : in  std_logic;
+      wb_adr_i   : in  std_logic_vector(3 downto 0);
+      wb_dat_i   : in  std_logic_vector(c_wishbone_data_width-1 downto 0);
+      wb_dat_o   : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+      wb_cyc_i   : in  std_logic;
+      wb_sel_i   : in  std_logic_vector(c_wishbone_data_width/8-1 downto 0);
+      wb_stb_i   : in  std_logic;
+      wb_we_i    : in  std_logic;
+      wb_ack_o   : out std_logic;
+      wb_stall_o : out std_logic);
+  end component;
+
+  component xwb_tics
+    generic (
+      g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
+      g_address_granularity : t_wishbone_address_granularity := WORD;
+      g_period              : integer);
+    port (
+      clk_sys_i : in  std_logic;
+      rst_n_i   : in  std_logic;
+      slave_i   : in  t_wishbone_slave_in;
+      slave_o   : out t_wishbone_slave_out;
+      desc_o    : out t_wishbone_device_descriptor);
+  end component;
+
+  component wb_vic
+    generic (
+      g_interface_mode      : t_wishbone_interface_mode;
+      g_address_granularity : t_wishbone_address_granularity;
+      g_num_interrupts      : natural;
+      g_init_vectors        : t_wishbone_address_array := cc_dummy_address_array;
+      g_retry_timeout : integer := 0
+      );
+    port (
+      clk_sys_i    : in  std_logic;
+      rst_n_i      : in  std_logic;
+      wb_adr_i     : in  std_logic_vector(c_wishbone_address_width-1 downto 0);
+      wb_dat_i     : in  std_logic_vector(c_wishbone_data_width-1 downto 0);
+      wb_dat_o     : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+      wb_cyc_i     : in  std_logic;
+      wb_sel_i     : in  std_logic_vector(c_wishbone_data_width/8-1 downto 0);
+      wb_stb_i     : in  std_logic;
+      wb_we_i      : in  std_logic;
+      wb_ack_o     : out std_logic;
+      wb_stall_o   : out std_logic;
+      irqs_i       : in  std_logic_vector(g_num_interrupts-1 downto 0);
+      irq_master_o : out std_logic);
+  end component;
+
+  constant c_xwb_vic_sdb : t_sdb_device := (
+    abi_class     => x"0000",              -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"01",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"7",                 -- 8/16/32-bit port granularity
+    sdb_component => (
+      addr_first  => x"0000000000000000",
+      addr_last   => x"00000000000000ff",
+      product     => (
+        vendor_id => x"000000000000CE42",  -- CERN
+        device_id => x"00000013",
+        version   => x"00000002",
+        date      => x"20120113",
+        name      => "WB-VIC-Int.Control ")));   
+
+  component xwb_vic
+    generic (
+      g_interface_mode      : t_wishbone_interface_mode;
+      g_address_granularity : t_wishbone_address_granularity;
+      g_num_interrupts      : natural;
+      g_init_vectors        : t_wishbone_address_array := cc_dummy_address_array;
+    g_retry_timeout : integer := 0);
+
+    port (
+      clk_sys_i    : in  std_logic;
+      rst_n_i      : in  std_logic;
+      slave_i      : in  t_wishbone_slave_in;
+      slave_o      : out t_wishbone_slave_out;
+      irqs_i       : in  std_logic_vector(g_num_interrupts-1 downto 0);
+      irq_master_o : out std_logic);
+  end component;
+
+  constant c_wb_serial_lcd_sdb : t_sdb_device := (
+    abi_class     => x"0000", -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"00",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"7", -- 8/16/32-bit port granularity
+    sdb_component => (
+    addr_first    => x"0000000000000000",
+    addr_last     => x"00000000000000ff",
+    product => (
+    vendor_id     => x"0000000000000651", -- GSI
+    device_id     => x"b77a5045",
+    version       => x"00000001",
+    date          => x"20130222",
+    name          => "SERIAL-LCD-DISPLAY ")));
+  component wb_serial_lcd
+    generic(
+      g_cols : natural := 40;
+      g_rows : natural := 24;
+      g_hold : natural := 15; -- How many times to repeat a line  (for sharpness)
+      g_wait : natural := 1); -- How many cycles per state change (for 20MHz timing)
+    port(
+      slave_clk_i  : in  std_logic;
+      slave_rstn_i : in  std_logic;
+      slave_i      : in  t_wishbone_slave_in;
+      slave_o      : out t_wishbone_slave_out;
+      di_clk_i     : in  std_logic;
+      di_scp_o     : out std_logic;
+      di_lp_o      : out std_logic;
+      di_flm_o     : out std_logic;
+      di_dat_o     : out std_logic);
+  end component;
+
+  function f_wb_spi_flash_sdb(g_bits : natural) return t_sdb_device;
+  component wb_spi_flash is
+    generic(
+      g_port_width             : natural   := 1;  -- 1 for EPCS, 4 for EPCQ
+      g_addr_width             : natural   := 24; -- log of memory (24=16MB)
+      g_idle_time              : natural   := 3;
+      g_dummy_time             : natural   := 8;
+      -- leave these at defaults if you have:
+      --   a) slow clock, b) valid constraints, or c) registered in/outputs
+      g_input_latch_edge       : std_logic := '1'; -- rising
+      g_output_latch_edge      : std_logic := '0'; -- falling
+      g_input_to_output_cycles : natural   := 1);  -- between 1 and 8
+    port(
+      clk_i     : in  std_logic;
+      rstn_i    : in  std_logic;
+      slave_i   : in  t_wishbone_slave_in;
+      slave_o   : out t_wishbone_slave_out;
+      
+      -- For properly constrained designs, set clk_out_i = clk_in_i.
+      clk_out_i : in  std_logic;
+      clk_in_i  : in  std_logic;
+      ncs_o     : out std_logic;
+      oe_o      : out std_logic_vector(g_port_width-1 downto 0);
+      asdi_o    : out std_logic_vector(g_port_width-1 downto 0);
+      data_i    : in  std_logic_vector(g_port_width-1 downto 0);
+      
+      external_request_i : in  std_logic := '0'; -- JTAG wants to use SPI?
+      external_granted_o : out std_logic);
+  end component;
+
+  -----------------------------------------------------------------------------
+  -- I2C to Wishbone bridge, following protocol defined with ELMA
+  -----------------------------------------------------------------------------
+  component wb_i2c_bridge is
+    generic
+    (
+      -- FSM watchdog timeout, see Appendix A in the component documentation for
+      -- an example of setting this generic
+      g_fsm_wdt : positive
+    );
+    port
+    (
+      -- Clock, reset
+      clk_i      : in  std_logic;
+      rst_n_i    : in  std_logic;
+
+      -- I2C lines
+      scl_i      : in  std_logic;
+      scl_o      : out std_logic;
+      scl_en_o   : out std_logic;
+      sda_i      : in  std_logic;
+      sda_o      : out std_logic;
+      sda_en_o   : out std_logic;
+
+      -- I2C address
+      i2c_addr_i : in  std_logic_vector(6 downto 0);
+
+      -- Status outputs
+      -- TIP  : Transfer In Progress
+      --        '1' when the I2C slave detects a matching I2C address, thus a
+      --            transfer is in progress
+      --        '0' when idle
+      -- ERR  : Error
+      --       '1' when the SysMon attempts to access an invalid WB slave
+      --       '0' when idle
+      -- WDTO : Watchdog timeout (single clock cycle pulse)
+      --        '1' -- timeout of watchdog occured
+      --        '0' -- when idle
+      tip_o      : out std_logic;
+      err_p_o    : out std_logic;
+      wdto_p_o   : out std_logic;
+
+      -- Wishbone master signals
+      wbm_stb_o  : out std_logic;
+      wbm_cyc_o  : out std_logic;
+      wbm_sel_o  : out std_logic_vector(3 downto 0);
+      wbm_we_o   : out std_logic;
+      wbm_dat_i  : in  std_logic_vector(31 downto 0);
+      wbm_dat_o  : out std_logic_vector(31 downto 0);
+      wbm_adr_o  : out std_logic_vector(31 downto 0);
+      wbm_ack_i  : in  std_logic;
+      wbm_rty_i  : in  std_logic;
+      wbm_err_i  : in  std_logic
+    );
+  end component wb_i2c_bridge;
+
+  ------------------------------------------------------------------------------
+  -- MultiBoot component
+  ------------------------------------------------------------------------------
+  component xwb_xil_multiboot is
+    port
+    (
+      -- Clock and reset input ports
+      clk_i   : in  std_logic;
+      rst_n_i : in  std_logic;
+
+      -- Wishbone ports
+      wbs_i   : in  t_wishbone_slave_in;
+      wbs_o   : out t_wishbone_slave_out;
+
+      -- SPI ports
+      spi_cs_n_o : out std_logic;
+      spi_sclk_o : out std_logic;
+      spi_mosi_o : out std_logic;
+      spi_miso_i : in  std_logic
+    );
+  end component xwb_xil_multiboot;
+
+  constant c_xwb_xil_multiboot_sdb : t_sdb_device := (
+    abi_class     => x"0000",              -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"00",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"7",                 -- 8/16/32-bit port granularity
+    sdb_component => (
+      addr_first  => x"0000000000000000",
+      addr_last   => x"000000000000001f",
+      product     => (
+        vendor_id => x"000000000000CE42",  -- CERN
+        device_id => x"11da333d",          -- echo "WB-Xilinx-MultiBoot" | md5sum | cut -c1-8
+        version   => x"00000001",
+        date      => x"20140313",
+        name      => "WB-Xilinx-MultiBoot")));
+
+  constant cc_dummy_sdb_device : t_sdb_device := (
+    abi_class     => x"0000",              -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"01",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"7",                 -- 8/16/32-bit port granularity
+    sdb_component => (
+      addr_first  => x"0000000000000000",
+      addr_last   => x"00000000000000ff",
+      product     => (
+        vendor_id => x"000000000000CE42",  -- CERN
+        device_id => x"ffffffff",
+        version   => x"00000001",
+        date      => x"20150722",
+        name      => "Unused-Device      ")));
+
+  
+end wishbone_pkg;
+
+package body wishbone_pkg is
+   -- f_wb_wr: processes a write reqest to a slave register with select lines. valid modes are "owr", "set" and "clr"
+   function f_wb_wr(pval : std_logic_vector; ival : std_logic_vector; sel : std_logic_vector; mode : string := "owr") return std_logic_vector is
+      variable n_sel     : std_logic_vector(pval'range);
+      variable n_val     : std_logic_vector(pval'range);
+      variable result 	 : std_logic_vector(pval'range);   
+   begin
+     for i in pval'range loop 
+      n_sel(i) := sel((i-pval'low) / 8); -- subtract the low index for when register width > wishbone data width
+      n_val(i) := ival(i-pval'low);
+     end loop;
+
+     if(mode = "set") then  
+      result := pval or (n_val and n_sel);
+     elsif (mode = "clr") then
+      result := pval and not (n_val and n_sel); 
+     else
+      result := (pval and not n_sel) or (n_val and n_sel);    
+     end if;  
+     
+     return result;
+   end f_wb_wr;
+  
+  function f_ceil_log2(x : natural) return natural is
+  begin
+    if x <= 1
+    then return 0;
+    else return f_ceil_log2((x+1)/2) +1;
+    end if;
+  end f_ceil_log2;
+
+  function f_sdb_embed_product(product : t_sdb_product)
+    return std_logic_vector             -- (319 downto 8)
+  is
+    variable result : std_logic_vector(319 downto 8);
+  begin
+    result(319 downto 256) := product.vendor_id;
+    result(255 downto 224) := product.device_id;
+    result(223 downto 192) := product.version;
+    result(191 downto 160) := product.date;
+    for i in 0 to 18 loop               -- string to ascii
+      result(159-i*8 downto 152-i*8) :=
+        std_logic_vector(to_unsigned(character'pos(product.name(i+1)), 8));
+    end loop;
+    return result;
+  end;
+
+  function f_sdb_extract_product(sdb_record : std_logic_vector(319 downto 8))
+    return t_sdb_product
+  is
+    variable result : t_sdb_product;
+  begin
+    result.vendor_id := sdb_record(319 downto 256);
+    result.device_id := sdb_record(255 downto 224);
+    result.version   := sdb_record(223 downto 192);
+    result.date      := sdb_record(191 downto 160);
+    for i in 0 to 18 loop               -- ascii to string
+      result.name(i+1) := character'val(to_integer(unsigned(sdb_record(159-i*8 downto 152-i*8))));
+    end loop;
+    return result;
+  end;
+
+  function f_sdb_embed_component(sdb_component : t_sdb_component; address : t_wishbone_address)
+    return std_logic_vector             -- (447 downto 8)
+  is
+    variable result : std_logic_vector(447 downto 8);
+
+    constant first : unsigned(63 downto 0) := unsigned(sdb_component.addr_first);
+    constant last  : unsigned(63 downto 0) := unsigned(sdb_component.addr_last);
+    variable base  : unsigned(63 downto 0) := (others => '0');
+  begin
+    base(address'length-1 downto 0) := unsigned(address);
+
+    result(447 downto 384) := std_logic_vector(base);
+    result(383 downto 320) := std_logic_vector(base + last - first);
+    result(319 downto 8)   := f_sdb_embed_product(sdb_component.product);
+    return result;
+  end;
+
+  function f_sdb_extract_component(sdb_record : std_logic_vector(447 downto 8))
+    return t_sdb_component
+  is
+    variable result : t_sdb_component;
+  begin
+    result.addr_first := sdb_record(447 downto 384);
+    result.addr_last  := sdb_record(383 downto 320);
+    result.product    := f_sdb_extract_product(sdb_record(319 downto 8));
+    return result;
+  end;
+
+  function f_sdb_embed_device(device : t_sdb_device; address : t_wishbone_address)
+    return t_sdb_record
+  is
+    variable result : t_sdb_record;
+  begin
+    result(511 downto 496) := device.abi_class;
+    result(495 downto 488) := device.abi_ver_major;
+    result(487 downto 480) := device.abi_ver_minor;
+    result(479 downto 456) := (others => '0');
+    result(455)            := device.wbd_endian;
+    result(454 downto 452) := (others => '0');
+    result(451 downto 448) := device.wbd_width;
+    result(447 downto 8)   := f_sdb_embed_component(device.sdb_component, address);
+    result(7 downto 0)     := x"01";    -- device
+    return result;
+  end;
+
+  function f_sdb_extract_device(sdb_record : t_sdb_record)
+    return t_sdb_device
+  is
+    variable result : t_sdb_device;
+  begin
+    result.abi_class     := sdb_record(511 downto 496);
+    result.abi_ver_major := sdb_record(495 downto 488);
+    result.abi_ver_minor := sdb_record(487 downto 480);
+    result.wbd_endian    := sdb_record(452);
+    result.wbd_width     := sdb_record(451 downto 448);
+    result.sdb_component := f_sdb_extract_component(sdb_record(447 downto 8));
+
+    assert sdb_record(7 downto 0) = x"01"
+      report "Cannot extract t_sdb_device from record of type " & integer'image(to_integer(unsigned(sdb_record(7 downto 0)))) & "."
+      severity failure;
+    
+    return result;
+  end;
+
+  function f_sdb_embed_msi(msi : t_sdb_msi; address : t_wishbone_address)
+    return t_sdb_record
+  is
+    variable result : t_sdb_record;
+  begin
+    result(511 downto 456) := (others => '0');
+    result(455)            := msi.wbd_endian;
+    result(454 downto 452) := (others => '0');
+    result(451 downto 448) := msi.wbd_width;
+    result(447 downto 8)   := f_sdb_embed_component(msi.sdb_component, address);
+    result(7 downto 0)     := x"03";    -- msi
+    return result;
+  end;
+
+  function f_sdb_extract_msi(sdb_record : t_sdb_record)
+    return t_sdb_msi
+  is
+    variable result : t_sdb_msi;
+  begin
+    result.wbd_endian    := sdb_record(452);
+    result.wbd_width     := sdb_record(451 downto 448);
+    result.sdb_component := f_sdb_extract_component(sdb_record(447 downto 8));
+
+    assert sdb_record(7 downto 0) = x"03"
+      report "Cannot extract t_sdb_msi from record of type " & integer'image(to_integer(unsigned(sdb_record(7 downto 0)))) & "."
+      severity failure;
+    
+    return result;
+  end;
+
+  function f_sdb_embed_integration(integr : t_sdb_integration)
+    return t_sdb_record
+  is
+    variable result : t_sdb_record;
+  begin
+    result(511 downto 320) := (others => '0');
+    result(319 downto 8)   := f_sdb_embed_product(integr.product);
+    result(7 downto 0)     := x"80"; -- integration record
+    return result;
+  end f_sdb_embed_integration;
+
+  function f_sdb_extract_integration(sdb_record : t_sdb_record)
+    return t_sdb_integration
+  is
+    variable result : t_sdb_integration;
+  begin
+    result.product := f_sdb_extract_product(sdb_record(319 downto 8));
+
+    assert sdb_record(7 downto 0) = x"80"
+    report "Cannot extract t_sdb_integration from record of type " & Integer'image(to_integer(unsigned(sdb_record(7 downto 0)))) & "."
+    severity Failure;
+
+    return result;
+  end f_sdb_extract_integration;
+
+  function f_sdb_embed_repo_url(url : t_sdb_repo_url)
+    return t_sdb_record
+  is
+    variable result : t_sdb_record;
+  begin
+    result(511 downto 8) := f_string2svl(url.repo_url);
+    result(  7 downto 0) := x"81"; -- repo_url record
+    return result;
+  end;
+
+  function f_sdb_extract_repo_url(sdb_record : t_sdb_record)
+    return t_sdb_repo_url
+  is
+    variable result : t_sdb_repo_url;
+  begin
+    result.repo_url     := f_slv2string(sdb_record(511 downto 8));
+
+    assert sdb_record(7 downto 0) = x"81"
+    report "Cannot extract t_sdb_repo_url from record of type " & Integer'image(to_integer(unsigned(sdb_record(7 downto 0)))) & "."
+    severity Failure;
+
+    return result;
+  end;
+
+  function f_sdb_embed_synthesis(syn : t_sdb_synthesis)
+    return t_sdb_record
+  is
+    variable result : t_sdb_record;
+  begin
+    result(511 downto 384) := f_string2svl(syn.syn_module_name);
+    result(383 downto 256) := f_string2bits(syn.syn_commit_id);
+    result(255 downto 192) := f_string2svl(syn.syn_tool_name);
+    result(191 downto 160) := syn.syn_tool_version;
+    result(159 downto 128) := syn.syn_date;
+    result(127 downto   8) := f_string2svl(syn.syn_username);
+    result(  7 downto   0) := x"82"; -- synthesis record
+    return result;
+  end;
+
+  function f_sdb_extract_synthesis(sdb_record : t_sdb_record)
+    return t_sdb_synthesis
+  is
+    variable result : t_sdb_synthesis;
+  begin
+    result.syn_module_name  := f_slv2string(sdb_record(511 downto 384));
+    result.syn_commit_id    := f_bits2string(sdb_record(383 downto 256));
+    result.syn_tool_name    := f_slv2string(sdb_record(255 downto 192));
+    result.syn_tool_version := sdb_record(191 downto 160);
+    result.syn_date         := sdb_record(159 downto 128);
+    result.syn_username     := f_slv2string(sdb_record(127 downto   8));
+
+    assert sdb_record(7 downto 0) = x"82"
+    report "Cannot extract t_sdb_repo_url from record of type " & Integer'image(to_integer(unsigned(sdb_record(7 downto 0)))) & "."
+    severity Failure;
+
+    return result;
+  end;
+
+  function f_sdb_embed_bridge(bridge : t_sdb_bridge; address : t_wishbone_address)
+    return t_sdb_record
+  is
+    variable result : t_sdb_record;
+
+    constant first : unsigned(63 downto 0) := unsigned(bridge.sdb_component.addr_first);
+    constant child : unsigned(63 downto 0) := unsigned(bridge.sdb_child);
+    variable base  : unsigned(63 downto 0) := (others => '0');
+  begin
+    base(address'length-1 downto 0) := unsigned(address);
+
+    result(511 downto 448) := std_logic_vector(base + child - first);
+    result(447 downto 8)   := f_sdb_embed_component(bridge.sdb_component, address);
+    result(7 downto 0)     := x"02";    -- bridge
+    return result;
+  end;
+
+  function f_sdb_extract_bridge(sdb_record : t_sdb_record)
+    return t_sdb_bridge
+  is
+    variable result : t_sdb_bridge;
+  begin
+    result.sdb_child     := sdb_record(511 downto 448);
+    result.sdb_component := f_sdb_extract_component(sdb_record(447 downto 8));
+
+    assert sdb_record(7 downto 0) = x"02"
+      report "Cannot extract t_sdb_bridge from record of type " & integer'image(to_integer(unsigned(sdb_record(7 downto 0)))) & "."
+      severity failure;
+    
+    return result;
+  end;
+  
+  function f_sdb_auto_device(device : t_sdb_device; enable : boolean := true; name: string := "")
+    return t_sdb_record
+  is
+    constant c_zero  : t_wishbone_address := (others => '0');
+    variable v_device: t_sdb_device := device;
+    variable v_empty : t_sdb_record := (others => '0');
+  begin
+    v_empty(7 downto 0) := x"f1";
+    if name /= "" then
+      v_device.sdb_component.product.name := f_string_fix_len(name , 19, ' ', false);
+    end if;
+    if enable then
+      v_empty := f_sdb_embed_device(v_device, c_zero);
+    end if;
+    return v_empty;
+  end f_sdb_auto_device;
+  
+  function f_sdb_auto_bridge(bridge : t_sdb_bridge; enable : boolean := true; name: string := "")
+    return t_sdb_record
+  is
+    constant c_zero  : t_wishbone_address := (others => '0');
+    variable v_bridge: t_sdb_bridge := bridge;
+    variable v_empty : t_sdb_record := (others => '0');
+  begin
+    v_empty(7 downto 0) := x"f2";
+    if name /= "" then
+      v_bridge.sdb_component.product.name := f_string_fix_len(name , 19, ' ', false);
+    end if;
+    if enable then
+      v_empty := f_sdb_embed_bridge(v_bridge, c_zero);
+    end if;
+    return v_empty;
+  end f_sdb_auto_bridge;
+  
+  function f_sdb_auto_msi(msi : t_sdb_msi; enable : boolean := true)
+    return t_sdb_record
+  is
+    constant c_zero  : t_wishbone_address := (others => '0');
+    variable v_empty : t_sdb_record := (others => '0');
+  begin
+    v_empty(7 downto 0) := x"f3";
+    if enable then
+      return f_sdb_embed_msi(msi, c_zero);
+    else
+      return v_empty;
+    end if;
+  end f_sdb_auto_msi;
+  
+  subtype t_usdb_address is unsigned(63 downto 0);
+  type t_usdb_address_array is array(natural range <>) of t_usdb_address;
+  
+  -- We map devices by placing the smallest ones first.
+  -- This is guaranteed to pack the maximum number of devices in the smallest space.
+  -- If a device has an address != 0, we leave it alone and let the crossbar confirm
+  -- that the address does not cause a conflict.
+  function f_sdb_auto_layout_helper(records : t_sdb_record_array)
+    return t_usdb_address_array
+  is
+    alias c_records : t_sdb_record_array(records'length-1 downto 0) is records;
+    constant c_zero : t_usdb_address := (others => '0');
+    
+    constant c_used_entries : natural := c_records'length + 1;
+    constant c_rom_entries  : natural := 2**f_ceil_log2(c_used_entries);
+    constant c_rom_bytes    : natural := c_rom_entries * c_sdb_device_length / 8;
+        
+    variable v_component : t_sdb_component;
+    variable v_sizes     : t_usdb_address_array(c_records'length downto 0);
+    variable v_address   : t_usdb_address_array(c_records'length downto 0);
+    variable v_bus_map   : std_logic_vector(c_records'length downto 0) := (others => '0');
+    variable v_bus_cursor: unsigned(63 downto 0) := (others => '0');
+    variable v_msi_map   : std_logic_vector(c_records'length downto 0) := (others => '0');
+    variable v_msi_cursor: unsigned(63 downto 0) := (others => '0');
+    variable v_increment : unsigned(63 downto 0) := (others => '0');
+    variable v_type      : std_logic_vector(7 downto 0);
+  begin
+    -- First, extract the length of the devices, ignoring those not to be mapped
+    for i in c_records'range loop
+      v_component := f_sdb_extract_component(c_records(i)(447 downto 8));
+      v_sizes(i)   := unsigned(v_component.addr_last);
+      v_address(i) := unsigned(v_component.addr_first);
+      
+      -- Silently round up to a power of two; the crossbar will give a warning for us
+      for j in 62 downto 0 loop
+        v_sizes(i)(j) := v_sizes(i)(j+1) or v_sizes(i)(j);
+      end loop;
+      
+      -- Only map devices/bridges at address zero
+      if v_address(i) = c_zero then
+        v_type := c_records(i)(7 downto 0);
+        case v_type is
+          when x"01" => v_bus_map(i) := '1';
+          when x"02" => v_bus_map(i) := '1';
+          when x"03" => v_msi_map(i) := '1';
+          when others => null;
+        end case;
+      end if;
+    end loop;
+    
+    -- Assign the SDB record a spot as well
+    v_address(c_records'length) := (others => '0');
+    v_sizes(c_records'length) := to_unsigned(c_rom_bytes-1, 64);
+    v_bus_map(c_records'length) := '1';
+    
+    -- Start assigning addresses
+    for j in 0 to 63 loop
+      v_increment := (others => '0');
+      v_increment(j) := '1';
+      
+      for i in 0 to c_records'length loop
+        if v_bus_map(i) = '1' and v_sizes(i)(j) = '0' then
+          v_bus_map(i) := '0';
+          v_address(i) := v_bus_cursor;
+          v_bus_cursor := v_bus_cursor + v_increment;
+        end if;
+        if v_msi_map(i) = '1' and v_sizes(i)(j) = '0' then
+          v_msi_map(i) := '0';
+          v_address(i) := v_msi_cursor;
+          v_msi_cursor := v_msi_cursor + v_increment;
+        end if;
+      end loop;
+      
+      -- Round up to the next required alignment
+      if v_bus_cursor(j) = '1' then
+        v_bus_cursor := v_bus_cursor + v_increment;
+      end if;
+      if v_msi_cursor(j) = '1' then
+        v_msi_cursor := v_msi_cursor + v_increment;
+      end if;
+    end loop;
+    
+    return v_address;
+  end f_sdb_auto_layout_helper;
+  
+  function f_sdb_auto_layout(records : t_sdb_record_array)
+    return t_sdb_record_array
+  is
+    alias    c_records : t_sdb_record_array(records'length-1 downto 0) is records;
+    variable v_typ     : std_logic_vector(7 downto 0);
+    variable v_result  : t_sdb_record_array(c_records'range) := c_records;
+    constant c_address : t_usdb_address_array := f_sdb_auto_layout_helper(c_records);
+    variable v_address : t_wishbone_address;
+  begin
+    -- Put the addresses into the mapping
+    for i in v_result'range loop
+      v_typ     := c_records(i)(7 downto 0);
+      v_address := std_logic_vector(c_address(i)(t_wishbone_address'range));
+
+      case v_typ is
+        when x"01" => v_result(i) := f_sdb_embed_device(f_sdb_extract_device(v_result(i)), v_address);
+        when x"02" => v_result(i) := f_sdb_embed_bridge(f_sdb_extract_bridge(v_result(i)), v_address);
+        when x"03" => v_result(i) := f_sdb_embed_msi   (f_sdb_extract_msi   (v_result(i)), v_address);
+        when others => null;
+      end case;
+    end loop;
+    
+    return v_result;
+  end f_sdb_auto_layout;
+  
+  function f_sdb_auto_layout(slaves : t_sdb_record_array; masters : t_sdb_record_array)
+    return t_sdb_record_array
+  is begin
+    return f_sdb_auto_layout(masters & slaves);
+  end f_sdb_auto_layout;
+  
+  function f_sdb_auto_sdb(records : t_sdb_record_array)
+    return t_wishbone_address
+  is
+    alias    c_records : t_sdb_record_array(records'length-1 downto 0) is records;
+    constant c_address : t_usdb_address_array(c_records'length downto 0) := f_sdb_auto_layout_helper(c_records);
+  begin
+    return std_logic_vector(c_address(c_records'length)(t_wishbone_address'range));
+  end f_sdb_auto_sdb;
+  
+  function f_sdb_auto_sdb(slaves : t_sdb_record_array; masters : t_sdb_record_array)
+    return t_wishbone_address
+  is begin
+    return f_sdb_auto_sdb(masters & slaves);
+  end f_sdb_auto_sdb;
+
+--**************************************************************************************************************************--
+-- START MAT's NEW FUNCTIONS FROM 18th Oct 2013
+------------------------------------------------------------------------------------------------------------------------------
+
+
+   function f_sdb_create_array(g_enum_dev_id    : boolean := false;
+                            g_dev_id_offs    : natural := 0;
+                            g_enum_dev_name  : boolean := false;
+                            g_dev_name_offs  : natural := 0;       
+                            device           : t_sdb_device; 
+                            instances        : natural := 1) 
+   return t_sdb_record_array is
+      variable result   : t_sdb_record_array(instances-1 downto 0);  
+      variable i,j, pos : natural;
+      variable dev, newdev      : t_sdb_device;
+      variable serial_no : string(1 to 3);
+      variable text_possible : boolean := false; 
+   begin
+      dev := device;
+             
+      report "### Creating " & integer'image(instances) & " x " & dev.sdb_component.product.name
+      severity note;       
+      for i in 0 to instances-1 loop
+         newdev := dev;        
+         if(g_enum_dev_id) then         
+            dev.sdb_component.product.device_id :=  
+            std_logic_vector( unsigned(dev.sdb_component.product.device_id) 
+                              + to_unsigned(i+g_dev_id_offs, dev.sdb_component.product.device_id'length));        
+         end if;
+         if(g_enum_dev_name) then         
+         -- find end of name
+            
+            for j in dev.sdb_component.product.name'length downto 1 loop
+               if(dev.sdb_component.product.name(j) /= ' ') then               
+                  pos := j;                  
+                  exit;
+               end if;
+            end loop;
+         -- convert i+g_dev_name_offs to string
+            serial_no := f_string_fix_len(integer'image(i+g_dev_name_offs), serial_no'length);
+            report "### Now: " & serial_no & " of " & dev.sdb_component.product.name severity note;
+         -- check if space is sufficient
+            assert (serial_no'length+1 <= dev.sdb_component.product.name'length - pos)
+            report "Not enough space in namestring of sdb_device " & dev.sdb_component.product.name
+            & " to add serial number " & serial_no & ". Space available " & 
+            integer'image(dev.sdb_component.product.name'length-pos-1) & ", required " 
+            & integer'image(serial_no'length+1)    
+            severity Failure;
+         end if;
+         if(g_enum_dev_name) then
+            newdev.sdb_component.product.name(pos+1) := '_'; 
+            for j in 1 to serial_no'length loop
+               newdev.sdb_component.product.name(pos+1+j) := serial_no(j);
+            end loop;            
+         end if;
+          
+      -- insert
+         report "### to: " & newdev.sdb_component.product.name severity note;
+         result(i) := f_sdb_embed_device(newdev, (others=>'0'));
+      end loop;
+      return result;
+   end f_sdb_create_array;
+
+   function f_sdb_join_arrays(a : t_sdb_record_array; b : t_sdb_record_array) return t_sdb_record_array is
+      variable result   : t_sdb_record_array(a'length+b'length-1 downto 0);  
+      variable i : natural;
+   begin
+      for i in 0 to a'left loop
+         result(i) := a(i);
+      end loop;
+      for i in 0 to b'left loop
+         result(i+a'length) := b(i);
+      end loop;
+      return result;
+   end f_sdb_join_arrays;
+
+
+   function f_sdb_extract_base_addr(sdb_record : t_sdb_record) return std_logic_vector is
+   begin
+      return sdb_record(447 downto 384);
+   end f_sdb_extract_base_addr;
+
+   function f_sdb_extract_end_addr(sdb_record : t_sdb_record) return std_logic_vector is
+   begin
+      return sdb_record(383 downto 320);
+   end f_sdb_extract_end_addr;
+
+
+   function f_align_addr_offset(offs : unsigned; this_rng : unsigned; prev_rng : unsigned)
+   return unsigned is
+      variable this_pow, prev_pow   : natural;  
+      variable start, env, result : unsigned(63 downto 0) := (others => '0');
+   begin
+      start(offs'left downto 0) := offs;   
+      --calculate address envelopes (next power of 2) for previous and this component and choose the larger one
+      this_pow := f_hot_to_bin(std_logic_vector(this_rng)); 
+      prev_pow := f_hot_to_bin(std_logic_vector(prev_rng));    
+      -- no max(). thank you very much, std_numeric :-/   
+      if(this_pow >= prev_pow) then
+         env(this_pow) := '1';
+      else
+         env(prev_pow) := '1';
+      end if;
+      --round up to the next multiple of the envelope...
+      if(prev_rng /= 0) then   
+         result := start + env - (start mod env);
+      else
+         result := start;   --...except for first element, result is start. 
+      end if;
+      return result;
+   end f_align_addr_offset;
+
+
+ -- generates aligned address map for an sdb_record_array, accepts optional start offset 
+   function f_sdb_automap_array(sdb_array : t_sdb_record_array; start_offset : t_wishbone_address := (others => '0'))
+   return t_sdb_record_array is
+      constant len         : natural := sdb_array'length;
+      variable this_rng    : unsigned(63 downto 0) := (others => '0');   
+      variable prev_rng    : unsigned(63 downto 0) := (others => '0');   
+      variable prev_offs   : unsigned(63 downto 0) := (others => '0');   
+      variable this_offs   : unsigned(63 downto 0) := (others => '0');   
+      variable device      : t_sdb_device;
+      variable bridge      : t_sdb_bridge;  
+      variable sdb_type    : std_logic_vector(7 downto 0);
+      variable i           : natural;
+      variable result      : t_sdb_record_array(sdb_array'length-1 downto 0); -- last 
+   begin
+   
+      prev_offs(start_offset'left downto 0) := unsigned(start_offset);
+      --traverse the array   
+      for i in 0 to len-1 loop
+         -- find the fitting extraction function by evaling the type byte. 
+         -- could also use the component, but it's safer to use Wes' embed and extract functions.      
+         sdb_type := sdb_array(i)(7 downto 0);
+         case sdb_type is
+            --device         
+            when x"01"  => device      := f_sdb_extract_device(sdb_array(i));
+                           this_rng    := unsigned(device.sdb_component.addr_last) - unsigned(device.sdb_component.addr_first);                      
+                           this_offs   := f_align_addr_offset(prev_offs, this_rng, prev_rng);
+                           result(i)   := f_sdb_embed_device(device, std_logic_vector(this_offs(31 downto 0)));
+            --bridge
+            when x"02"  => bridge      := f_sdb_extract_bridge(sdb_array(i));
+                           this_rng    := unsigned(bridge.sdb_component.addr_last) - unsigned(bridge.sdb_component.addr_first);
+                           this_offs   := f_align_addr_offset(prev_offs, this_rng, prev_rng);
+                           result(i)   := f_sdb_embed_bridge(bridge, std_logic_vector(this_offs(31 downto 0)) );
+            --other
+            when others => result(i) := sdb_array(i);   
+         end case;
+         -- doesnt hurt because this_* doesnt change if its not a device or bridge
+         prev_rng    := this_rng;
+         prev_offs   := this_offs;
+      end loop;
+      report "##* " & integer'image(sdb_array'length) & " Elements, last address: " & f_bits2string(std_logic_vector(this_offs+this_rng)) severity Note;
+      return result;
+   end f_sdb_automap_array;
+
+
+  -- find place for sdb rom on crossbar and return address. try to put it in an address gap.
+   function f_sdb_create_rom_addr(sdb_array : t_sdb_record_array) return t_wishbone_address is
+      constant len                  : natural := sdb_array'length;
+      constant rom_bytes            : natural := (2**f_ceil_log2(sdb_array'length + 1)) * (c_sdb_device_length / 8);
+      variable result               : t_wishbone_address  := (others => '0');
+      variable this_base, this_end  : unsigned(63 downto 0)          := (others => '0');    
+      variable prev_base, prev_end  : unsigned(63 downto 0)          := (others => '0');
+      variable rom_base             : unsigned(63 downto 0)          := (others => '0');
+      variable sdb_type             : std_logic_vector(7 downto 0);     
+   begin
+      --traverse the array   
+      for i in 0 to len-1 loop     
+         sdb_type := sdb_array(i)(7 downto 0);
+         if(sdb_type = x"01" or sdb_type = x"02") then
+            -- get         
+            this_base := unsigned(f_sdb_extract_base_addr(sdb_array(i)));
+            this_end  := unsigned(f_sdb_extract_end_addr(sdb_array(i)));
+            if(unsigned(result) = 0) then
+               rom_base := f_align_addr_offset(prev_base, to_unsigned(rom_bytes-1, 64), (prev_end-prev_base));
+               if(rom_base + to_unsigned(rom_bytes, 64) <= this_base) then
+                  result := std_logic_vector(rom_base(t_wishbone_address'left downto 0));
+               end if;   
+            end if;
+            prev_base := this_base;
+            prev_end  := this_end;      
+         end if;
+      end loop;   
+      -- if there was no gap to fit the sdb rom, place it at the end   
+      if(unsigned(result) = 0) then
+            result := std_logic_vector(f_align_addr_offset(this_base, to_unsigned(rom_bytes-1, 64), 
+                                       this_end-this_base)(t_wishbone_address'left downto 0));   
+      end if;      
+      return result;
+   end f_sdb_create_rom_addr; 
+------------------------------------------------------------------------------------------------------------------------------
+-- END MAT's NEW FUNCTIONS FROM  18th Oct 2013
+------------------------------------------------------------------------------------------------------------------------------
+
+  function f_sdb_bus_end(
+    g_wraparound : boolean;
+    g_layout     : t_sdb_record_array;
+    g_sdb_addr   : t_wishbone_address;
+    msi          : boolean) return unsigned
+  is
+    alias c_layout : t_sdb_record_array(g_layout'length-1 downto 0) is g_layout;
+
+    -- How much space does the ROM need?
+    constant c_used_entries : natural := c_layout'length + 1;
+    constant c_rom_entries  : natural := 2**f_ceil_log2(c_used_entries);  -- next power of 2
+    constant c_sdb_bytes    : natural := c_sdb_device_length / 8;
+    constant c_rom_bytes    : natural := c_rom_entries * c_sdb_bytes;
+    
+    variable result : unsigned(63 downto 0) := (others => '0');
+    variable typ    : std_logic_vector(7 downto 0);
+    variable last   : unsigned(63 downto 0);
+  begin
+    if not msi then
+      -- The ROM will be an addressed slave as well
+      result := (others => '0');
+      result(g_sdb_addr'range) := unsigned(g_sdb_addr);
+      result := result + to_unsigned(c_rom_bytes, 64) - 1;
+    end if;
+    
+    for i in c_layout'range loop
+      typ  := c_layout(i)(7 downto 0);
+      last := unsigned(f_sdb_extract_component(c_layout(i)(447 downto 8)).addr_last);
+      case typ is
+        when x"01" => if not msi and last > result then result := last; end if;
+        when x"02" => if not msi and last > result then result := last; end if;
+        when x"03" => if     msi and last > result then result := last; end if;
+        when others => null;
+      end case;
+    end loop;
+    
+    -- round result up to a power of two -1
+    for i in 62 downto 0 loop
+      result(i) := result(i) or result(i+1);
+    end loop;
+    
+    if not g_wraparound then
+      result := (others => '0');
+      for i in 0 to c_wishbone_address_width-1 loop
+        result(i) := '1';
+      end loop;
+    end if;
+    
+    return result;
+  end f_sdb_bus_end;
+
+  function f_xwb_bridge_manual_sdb(
+    g_size     : t_wishbone_address;
+    g_sdb_addr : t_wishbone_address) return t_sdb_bridge
+  is
+    variable result : t_sdb_bridge;
+  begin
+    result.sdb_child                                      := (others => '0');
+    result.sdb_child(c_wishbone_address_width-1 downto 0) := g_sdb_addr;
+
+    result.sdb_component.addr_first                                     := (others => '0');
+    result.sdb_component.addr_last                                      := (others => '0');
+    result.sdb_component.addr_last(c_wishbone_address_width-1 downto 0) := g_size;
+
+    result.sdb_component.product.vendor_id := x"0000000000000651";  -- GSI
+    result.sdb_component.product.device_id := x"eef0b198";
+    result.sdb_component.product.version   := x"00000001";
+    result.sdb_component.product.date      := x"20120511";
+    result.sdb_component.product.name      := "WB4-Bridge-GSI     ";
+
+    return result;
+  end f_xwb_bridge_manual_sdb;
+  
+  function f_xwb_bridge_layout_sdb(     -- determine bus size from layout
+    g_wraparound : boolean := true;
+    g_layout     : t_sdb_record_array;
+    g_sdb_addr   : t_wishbone_address) return t_sdb_bridge
+  is
+    variable address : t_wishbone_address;
+  begin
+    address := std_logic_vector(f_sdb_bus_end(g_wraparound, g_layout, g_sdb_addr, false)(address'range));
+    return f_xwb_bridge_manual_sdb(address, g_sdb_addr);
+  end f_xwb_bridge_layout_sdb;
+
+  function f_xwb_msi_manual_sdb(
+    g_size     : t_wishbone_address) return t_sdb_msi
+  is
+    variable result : t_sdb_msi;
+  begin
+    result.wbd_endian := '0';
+    result.wbd_width  := x"7";
+
+    result.sdb_component.addr_first                                     := (others => '0');
+    result.sdb_component.addr_last                                      := (others => '0');
+    result.sdb_component.addr_last(c_wishbone_address_width-1 downto 0) := g_size;
+
+    result.sdb_component.product.vendor_id := x"0000000000000651";  -- GSI
+    result.sdb_component.product.device_id := x"aa7bfb3c";
+    result.sdb_component.product.version   := x"00000001";
+    result.sdb_component.product.date      := x"20160422";
+    result.sdb_component.product.name      := "WB4-MSI-Bridge-GSI ";
+
+    return result;
+  end f_xwb_msi_manual_sdb;
+  
+  function f_xwb_msi_layout_sdb(     -- determine MSI size from layout
+    g_layout     : t_sdb_record_array) return t_sdb_msi
+  is
+    constant zero : t_wishbone_address := (others => '0');
+    variable address : t_wishbone_address;
+  begin
+    address := std_logic_vector(f_sdb_bus_end(true, g_layout, zero, true)(address'range));
+    return f_xwb_msi_manual_sdb(address);
+  end f_xwb_msi_layout_sdb;
+  
+  function f_xwb_dpram(g_size : natural) return t_sdb_device
+  is
+    variable result : t_sdb_device;
+  begin
+    result.abi_class     := x"0001";    -- RAM device
+    result.abi_ver_major := x"01";
+    result.abi_ver_minor := x"00";
+    result.wbd_width     := x"7";       -- 32/16/8-bit supported
+    result.wbd_endian    := c_sdb_endian_big;
+
+    result.sdb_component.addr_first := (others => '0');
+    result.sdb_component.addr_last  := std_logic_vector(to_unsigned(g_size*4-1, 64));
+
+    result.sdb_component.product.vendor_id := x"000000000000CE42";  -- CERN
+    result.sdb_component.product.device_id := x"66cfeb52";
+    result.sdb_component.product.version   := x"00000001";
+    result.sdb_component.product.date      := x"20120305";
+    result.sdb_component.product.name      := "WB4-BlockRAM       ";
+
+    return result;
+  end f_xwb_dpram;
+
+  function f_bits2string(s : std_logic_vector) return string is
+    --- extend length to full hex nibble
+    variable result : string((s'length+7)/4 downto 1);
+    variable s_norm : std_logic_vector(result'length*4-1 downto 0) := (others=>'0');
+    variable cut : natural;
+    variable nibble: std_logic_vector(3 downto 0);
+    constant len : natural := result'length;
+  begin
+    s_norm(s'length-1 downto 0) := s;
+    for i in len-1 downto 0 loop
+      nibble := s_norm(i*4+3 downto i*4);
+      case nibble is
+        when "0000" => result(i+1) := '0';
+        when "0001" => result(i+1) := '1';
+        when "0010" => result(i+1) := '2';
+        when "0011" => result(i+1) := '3';
+        when "0100" => result(i+1) := '4';
+        when "0101" => result(i+1) := '5';
+        when "0110" => result(i+1) := '6';
+        when "0111" => result(i+1) := '7';
+        when "1000" => result(i+1) := '8';
+        when "1001" => result(i+1) := '9';
+        when "1010" => result(i+1) := 'a';
+        when "1011" => result(i+1) := 'b';
+        when "1100" => result(i+1) := 'c';
+        when "1101" => result(i+1) := 'd';
+        when "1110" => result(i+1) := 'e';
+        when "1111" => result(i+1) := 'f';
+        when others => result(i+1) := 'X';
+      end case;
+    end loop;
+
+    -- trim leading 0s
+    strip : for i in result'length downto 1 loop
+      cut := i;
+      exit strip when result(i) /= '0';
+    end loop;
+
+    return "0x" & result(cut downto 1);
+  end f_bits2string;
+
+  -- Converts string (hex number, without leading 0x) to std_logic_vector
+  function f_string2bits(s : string) return std_logic_vector is
+    constant len : natural := s'length;
+    variable slv : std_logic_vector(s'length*4-1 downto 0);
+    variable nibble : std_logic_vector(3 downto 0);
+  begin
+    for i in 0 to len-1 loop
+      case s(i+1) is
+        when '0' => nibble := X"0";
+        when '1' => nibble := X"1";
+        when '2' => nibble := X"2";
+        when '3' => nibble := X"3";
+        when '4' => nibble := X"4";
+        when '5' => nibble := X"5";
+        when '6' => nibble := X"6";
+        when '7' => nibble := X"7";
+        when '8' => nibble := X"8";
+        when '9' => nibble := X"9";
+        when 'a' => nibble := X"A";
+        when 'A' => nibble := X"A";
+        when 'b' => nibble := X"B";
+        when 'B' => nibble := X"B";
+        when 'c' => nibble := X"C";
+        when 'C' => nibble := X"C";
+        when 'd' => nibble := X"D";
+        when 'D' => nibble := X"D";
+        when 'e' => nibble := X"E";
+        when 'E' => nibble := X"E";
+        when 'f' => nibble := X"F";
+        when 'F' => nibble := X"F";
+        when others => nibble := "XXXX";
+      end case;
+      if s'ascending then
+        slv(slv'length-(i*4)-1 downto slv'length-(i+1)*4) := nibble;
+      else
+        slv(((i+1)*4)-1 downto i*4) := nibble;
+      end if;
+    end loop;
+    return slv;
+  end f_string2bits;
+
+  -- Converts string to ascii (std_logic_vector)
+  function f_string2svl (s : string) return std_logic_vector is
+    constant len : natural := s'length;
+    variable slv : std_logic_vector((s'length * 8) - 1 downto 0);
+  begin
+    for i in 0 to len-1 loop
+      slv(slv'high-i*8 downto (slv'high-7)-i*8) :=
+        std_logic_vector(to_unsigned(character'pos(s(i+1)), 8));
+    end loop;
+    return slv;
+  end f_string2svl;
+
+  -- Converts ascii (std_logic_vector) to string
+  function f_slv2string (slv : std_logic_vector) return string is
+    constant len : natural := slv'length;
+    variable s : string(1 to slv'length/8);
+  begin
+    for i in 0 to (len/8)-1 loop
+      s(i+1) := character'val(to_integer(unsigned(slv(slv'high-i*8 downto (slv'high-7)-i*8))));
+    end loop;
+    return s;
+  end f_slv2string;
+
+    -- pads a string of unknown length to a given length (useful for integer'image)
+  function f_string_fix_len ( s : string; ret_len : natural := 10; fill_char : character := '0'; justify_right : boolean := true ) return string is
+      variable ret_v : string (1 to ret_len);
+      constant pad_len : integer := ret_len - s'length ;
+      variable pad_v : string (1 to abs(pad_len));
+   begin
+      if pad_len < 1 then
+         ret_v := s(ret_v'range);
+      else
+         pad_v := (others => fill_char);
+         if justify_right then
+           ret_v := pad_v & s;
+         else
+           ret_v := s & pad_v ;
+         end if;
+      end if;
+      return ret_v;
+   end f_string_fix_len;
+
+   -- do not synthesize
+   function f_hot_to_bin(x : std_logic_vector) return natural is
+      variable rv : natural;
+   begin
+      rv := 0;
+      -- if there are few ones set in _x_ then the most significant will be
+      -- translated to bin
+      for i in 0 to x'left loop
+         if x(i) = '1' then
+           rv := i+1;
+         end if;
+      end loop;
+      return rv;
+  end function;  
+
+  function f_wb_spi_flash_sdb(g_bits : natural) return t_sdb_device is
+    variable result : t_sdb_device := (
+      abi_class     => x"0000", -- undocumented device
+      abi_ver_major => x"01",
+      abi_ver_minor => x"02",
+      wbd_endian    => c_sdb_endian_big,
+      wbd_width     => x"7", -- 8/16/32-bit port granularity
+      sdb_component => (
+      addr_first    => x"0000000000000000",
+      addr_last     => x"0000000000ffffff",
+      product => (
+      vendor_id     => x"0000000000000651", -- GSI
+      device_id     => x"5cf12a1c",
+      version       => x"00000002",
+      date          => x"20140417",
+      name          => "SPI-FLASH-16M-MMAP ")));
+  begin
+    result.sdb_component.addr_last := std_logic_vector(to_unsigned(2**g_bits-1, 64));
+    return result;
+  end f_wb_spi_flash_sdb;
+  
+end wishbone_pkg;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/fabric/wr_fabric_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/fabric/wr_fabric_pkg.vhd
new file mode 100644
index 000000000..3e15d94cc
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/fabric/wr_fabric_pkg.vhd
@@ -0,0 +1,220 @@
+-------------------------------------------------------------------------------
+-- Title      : Wishbone Packet Fabric package
+-- Project    : WR Cores Collection
+-------------------------------------------------------------------------------
+-- File       : wr_fabric_pkg.vhd
+-- Author     : Grzegorz Daniluk
+-- Company    : CERN BE-CO-HT
+-- Platform   : 
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012-2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.wishbone_pkg.all;
+
+
+package wr_fabric_pkg is
+
+  constant c_WRF_DATA   : std_logic_vector(1 downto 0) := "00";
+  constant c_WRF_OOB    : std_logic_vector(1 downto 0) := "01";
+  constant c_WRF_STATUS : std_logic_vector(1 downto 0) := "10";
+  constant c_WRF_USER   : std_logic_vector(1 downto 0) := "11";
+
+  constant c_WRF_OOB_TYPE_RX : std_logic_vector(3 downto 0) := "0000";
+  constant c_WRF_OOB_TYPE_TX : std_logic_vector(3 downto 0) := "0001";
+
+  type t_wrf_mux_class is array (natural range <>) of std_logic_vector(7 downto 0);
+
+  type t_wrf_status_reg is record
+    is_hp       : std_logic;
+    has_smac    : std_logic;
+    has_crc     : std_logic;
+    error       : std_logic;
+    tag_me      : std_logic;
+    match_class : std_logic_vector(7 downto 0);
+  end record;
+
+  type t_wrf_source_out is record
+    adr : std_logic_vector(1 downto 0);
+    dat : std_logic_vector(15 downto 0);
+    cyc : std_logic;
+    stb : std_logic;
+    we  : std_logic;
+    sel : std_logic_vector(1 downto 0);
+  end record;
+
+  type t_wrf_source_in is record
+    ack   : std_logic;
+    stall : std_logic;
+    err   : std_logic;
+    rty   : std_logic;
+  end record;
+
+
+  type t_wrf_oob is record
+    valid: std_logic;
+    oob_type : std_logic_vector(3 downto 0);
+    ts_r     : std_logic_vector(27 downto 0);
+    ts_f     : std_logic_vector(3 downto 0);
+    frame_id : std_logic_vector(15 downto 0);
+    port_id  : std_logic_vector(5 downto 0);
+  end record;
+
+  subtype t_wrf_sink_in is t_wrf_source_out;
+  subtype t_wrf_sink_out is t_wrf_source_in;
+
+  type t_wrf_source_in_array is array (natural range <>) of t_wrf_source_in;
+  type t_wrf_source_out_array is array (natural range <>) of t_wrf_source_out;
+
+  subtype t_wrf_sink_in_array is t_wrf_source_out_array;
+  subtype t_wrf_sink_out_array is t_wrf_source_in_array;
+
+  function f_marshall_wrf_status (stat  : t_wrf_status_reg) return std_logic_vector;
+  function f_unmarshall_wrf_status(stat : std_logic_vector) return t_wrf_status_reg;
+
+  constant c_wrf_status_init_value : t_wrf_status_reg :=
+    ('0', '0', '0', '0', '0', (others => '0'));
+
+  constant c_dummy_src_in : t_wrf_source_in :=
+    ('0', '0', '0', '0');
+  constant c_dummy_snk_in : t_wrf_sink_in :=
+    ("XX", "XXXXXXXXXXXXXXXX", '0', '0', '0', "XX");
+
+
+  -----------------------------------------------------------------------------
+  -- WRF MUX
+  -----------------------------------------------------------------------------
+  component xwrf_mux is
+    generic(
+      g_muxed_ports	:	integer := 2);
+    port(
+      clk_sys_i	: in std_logic;
+      rst_n_i		: in std_logic;
+      --ENDPOINT
+      ep_src_o	:	out t_wrf_source_out;
+      ep_src_i	: in  t_wrf_source_in;
+      ep_snk_o	: out t_wrf_sink_out;
+      ep_snk_i  : in  t_wrf_sink_in;
+      --Muxed ports
+      mux_src_o : out t_wrf_source_out_array(g_muxed_ports-1 downto 0);
+      mux_src_i : in  t_wrf_source_in_array(g_muxed_ports-1 downto 0);
+      mux_snk_o : out t_wrf_sink_out_array(g_muxed_ports-1 downto 0);
+      mux_snk_i : in  t_wrf_sink_in_array(g_muxed_ports-1 downto 0);
+      --
+      mux_class_i : in t_wrf_mux_class(g_muxed_ports-1 downto 0)
+    );
+  end component;
+
+  component xwrf_reg is
+    generic(
+      g_adr_width : integer := 2;
+      g_dat_width : integer :=16);
+    port(
+      rst_n_i	:	in std_logic;
+      clk_i   : in std_logic;
+      snk_i		: in  t_wrf_sink_in;
+      snk_o		:	out t_wrf_sink_out;
+      src_i		:	in 	t_wrf_source_in;
+      src_o		:	out t_wrf_source_out);
+  end component;
+
+  component xwrf_loopback
+    generic(
+      g_interface_mode        : t_wishbone_interface_mode      := CLASSIC;
+      g_address_granularity   : t_wishbone_address_granularity := WORD);
+    port(
+      clk_sys_i : in  std_logic;
+      rst_n_i   : in  std_logic;
+  
+      wrf_snk_i : in  t_wrf_sink_in;
+      wrf_snk_o : out t_wrf_sink_out;
+      wrf_src_o : out t_wrf_source_out;
+      wrf_src_i : in  t_wrf_source_in;
+  
+      wb_i : in  t_wishbone_slave_in;
+      wb_o : out t_wishbone_slave_out);
+  end component;
+
+  component xwb_fabric_sink
+    port (
+      clk_i     : in  std_logic;
+      rst_n_i   : in  std_logic;
+      snk_i     : in  t_wrf_sink_in;
+      snk_o     : out t_wrf_sink_out;
+      addr_o    : out std_logic_vector(1 downto 0);
+      data_o    : out std_logic_vector(15 downto 0);
+      dvalid_o  : out std_logic;
+      sof_o     : out std_logic;
+      eof_o     : out std_logic;
+      error_o   : out std_logic;
+      bytesel_o : out std_logic;
+      dreq_i    : in  std_logic);
+  end component;
+
+  component xwb_fabric_source
+    port (
+      clk_i     : in  std_logic;
+      rst_n_i   : in  std_logic;
+      src_i     : in  t_wrf_source_in;
+      src_o     : out t_wrf_source_out;
+      addr_i    : in  std_logic_vector(1 downto 0);
+      data_i    : in  std_logic_vector(15 downto 0);
+      dvalid_i  : in  std_logic;
+      sof_i     : in  std_logic;
+      eof_i     : in  std_logic;
+      error_i   : in  std_logic;
+      bytesel_i : in  std_logic;
+      dreq_o    : out std_logic);
+  end component;
+
+end wr_fabric_pkg;
+
+package body wr_fabric_pkg is
+
+  function f_marshall_wrf_status(stat : t_wrf_status_reg)
+    return std_logic_vector is
+    variable tmp : std_logic_vector(15 downto 0);
+  begin
+    tmp(0)           := stat.is_hp;
+    tmp(1)           := stat.error;
+    tmp(2)           := stat.has_smac;
+    tmp(3)           := stat.has_crc;
+    tmp(15 downto 8) := stat.match_class;
+    return tmp;
+  end function;
+
+  function f_unmarshall_wrf_status(stat : std_logic_vector) return t_wrf_status_reg is
+    variable tmp : t_wrf_status_reg;
+  begin
+    tmp.is_hp       := stat(0);
+    tmp.error       := stat(1);
+    tmp.has_smac    := stat(2);
+    tmp.has_crc     := stat(3);
+    tmp.match_class := stat(15 downto 8);
+    return tmp;
+    
+  end function;
+
+
+end wr_fabric_pkg;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/fabric/xwb_fabric_sink.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/fabric/xwb_fabric_sink.vhd
new file mode 100644
index 000000000..978516c38
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/fabric/xwb_fabric_sink.vhd
@@ -0,0 +1,265 @@
+-------------------------------------------------------------------------------
+-- Title      : Wishbone Packet Fabric buffered packet sink
+-- Project    : WR Cores Collection
+-------------------------------------------------------------------------------
+-- File       : xwb_fabric_sink.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2012-01-16
+-- Last update: 2012-01-22
+-- Platform   : 
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: A simple WB packet streaming sink with builtin FIFO buffer.
+-- Outputs a trivial interface (start-of-packet, end-of-packet, data-valid)
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2011 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2011-01-16  1.0      twlostow        Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.genram_pkg.all;
+use work.wr_fabric_pkg.all;
+
+entity xwb_fabric_sink is
+  
+  port (
+    clk_i   : in std_logic;
+    rst_n_i : in std_logic;
+
+    -- Wishbone Fabric Interface I/O
+    snk_i : in  t_wrf_sink_in;
+    snk_o : out t_wrf_sink_out;
+
+    -- Decoded & buffered fabric
+    addr_o    : out std_logic_vector(1 downto 0);
+    data_o    : out std_logic_vector(15 downto 0);
+    dvalid_o  : out std_logic;
+    sof_o     : out std_logic;
+    eof_o     : out std_logic;
+    error_o   : out std_logic;
+    bytesel_o : out std_logic;
+    dreq_i    : in  std_logic
+    );
+
+end xwb_fabric_sink;
+
+architecture rtl of xwb_fabric_sink is
+
+  constant c_fifo_width : integer := 16 + 2 + 4;
+
+  signal q_valid, full, we, rd : std_logic;
+  signal fin, fout, fout_reg   : std_logic_vector(c_fifo_width-1 downto 0);
+  signal cyc_d0, rd_d0         : std_logic;
+
+  signal pre_sof, pre_eof, pre_bytesel, pre_dvalid : std_logic;
+  signal post_sof, post_dvalid                     : std_logic;
+  signal post_addr                                 : std_logic_vector(1 downto 0);
+  signal post_data                                 : std_logic_vector(15 downto 0);
+
+  signal snk_out : t_wrf_sink_out;
+  
+begin  -- rtl
+
+
+  p_delay_cyc_and_rd : process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        cyc_d0 <= '0';
+        rd_d0  <= '0';
+      else
+        if(full = '0') then
+          cyc_d0 <= snk_i.cyc;
+        end if;
+
+        rd_d0 <= rd;
+      end if;
+    end if;
+  end process;
+
+
+  pre_sof     <= snk_i.cyc and not cyc_d0;  -- sof
+  pre_eof     <= not snk_i.cyc and cyc_d0;  -- eof
+  pre_bytesel <= not snk_i.sel(0);      -- bytesel
+  pre_dvalid  <= snk_i.stb and snk_i.we and snk_i.cyc and not snk_out.stall;  -- data valid
+
+  fin(15 downto 0)  <= snk_i.dat;
+  fin(17 downto 16) <= snk_i.adr;
+  fin(21 downto 18) <= pre_sof & pre_eof & pre_bytesel & pre_dvalid;
+
+
+  snk_out.stall <= full or (snk_i.cyc and not cyc_d0);
+  snk_out.err   <= '0';
+  snk_out.rty   <= '0';
+
+  p_gen_ack : process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        snk_out.ack <= '0';
+      else
+        snk_out.ack <= snk_i.cyc and snk_i.stb and snk_i.we and not snk_out.stall;
+      end if;
+    end if;
+  end process;
+
+  snk_o <= snk_out;
+
+  we <= '1' when fin(21 downto 18) /= "0000" and full = '0' else '0';
+  rd <= q_valid and dreq_i and not post_sof;
+
+  U_FIFO : generic_shiftreg_fifo
+    generic map (
+      g_data_width => c_fifo_width,
+      g_size       => 16)
+    port map (
+      rst_n_i       => rst_n_i,
+      clk_i         => clk_i,
+      d_i           => fin,
+      we_i          => we,
+      q_o           => fout,
+      rd_i          => rd,
+      almost_full_o => full,
+      q_valid_o     => q_valid);
+
+  p_fout_reg : process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        fout_reg <= (others => '0');
+      elsif(rd = '1') then
+        fout_reg <= fout;
+      end if;
+    end if;
+  end process;
+
+
+  post_data <= fout_reg(15 downto 0);
+  post_addr <= fout_reg(17 downto 16);
+  post_sof  <= fout_reg(21) and rd_d0; --and q_valid;
+
+  post_dvalid <= fout_reg(18);
+
+  sof_o     <= post_sof and rd_d0;
+  dvalid_o  <= post_dvalid and rd_d0;
+  error_o   <= '1' when rd_d0 = '1' and (post_addr = c_WRF_STATUS) and (f_unmarshall_wrf_status(post_data).error = '1') else '0';
+  eof_o     <= fout_reg(20) and rd_d0;
+  bytesel_o <= fout_reg(19);
+  data_o    <= post_data;
+  addr_o    <= post_addr;
+
+  
+end rtl;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.genram_pkg.all;
+use work.wr_fabric_pkg.all;
+
+
+entity wb_fabric_sink is
+
+  port (
+    clk_i   : in std_logic;
+    rst_n_i : in std_logic;
+
+    snk_dat_i   : in  std_logic_vector(15 downto 0);
+    snk_adr_i   : in  std_logic_vector(1 downto 0);
+    snk_sel_i   : in  std_logic_vector(1 downto 0);
+    snk_cyc_i   : in  std_logic;
+    snk_stb_i   : in  std_logic;
+    snk_we_i    : in  std_logic;
+    snk_stall_o : out std_logic;
+    snk_ack_o   : out std_logic;
+    snk_err_o   : out std_logic;
+    snk_rty_o   : out std_logic;
+
+    -- Decoded & buffered fabric
+    addr_o    : out std_logic_vector(1 downto 0);
+    data_o    : out std_logic_vector(15 downto 0);
+    dvalid_o  : out std_logic;
+    sof_o     : out std_logic;
+    eof_o     : out std_logic;
+    error_o   : out std_logic;
+    bytesel_o : out std_logic;
+    dreq_i    : in  std_logic
+    );
+
+end wb_fabric_sink;
+
+architecture wrapper of wb_fabric_sink is
+
+  component xwb_fabric_sink
+    port (
+      clk_i     : in  std_logic;
+      rst_n_i   : in  std_logic;
+      snk_i     : in  t_wrf_sink_in;
+      snk_o     : out t_wrf_sink_out;
+      addr_o    : out std_logic_vector(1 downto 0);
+      data_o    : out std_logic_vector(15 downto 0);
+      dvalid_o  : out std_logic;
+      sof_o     : out std_logic;
+      eof_o     : out std_logic;
+      error_o   : out std_logic;
+      bytesel_o : out std_logic;
+      dreq_i    : in  std_logic);
+  end component;
+
+  signal snk_in  : t_wrf_sink_in;
+  signal snk_out : t_wrf_sink_out;
+  
+begin  -- wrapper
+
+  U_Wrapped_Sink : xwb_fabric_sink
+    port map (
+      clk_i     => clk_i,
+      rst_n_i   => rst_n_i,
+      snk_i     => snk_in,
+      snk_o     => snk_out,
+      addr_o    => addr_o,
+      data_o    => data_o,
+      dvalid_o  => dvalid_o,
+      sof_o     => sof_o,
+      eof_o     => eof_o,
+      error_o   => error_o,
+      bytesel_o => bytesel_o,
+      dreq_i    => dreq_i);
+
+  snk_in.adr <= snk_adr_i;
+  snk_in.dat <= snk_dat_i;
+  snk_in.stb <= snk_stb_i;
+  snk_in.we  <= snk_we_i;
+  snk_in.cyc <= snk_cyc_i;
+  snk_in.sel <= snk_sel_i;
+
+  snk_stall_o <= snk_out.stall;
+  snk_ack_o   <= snk_out.ack;
+  snk_err_o   <= snk_out.err;
+  snk_rty_o   <= snk_out.rty;
+  
+end wrapper;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/fabric/xwb_fabric_source.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/fabric/xwb_fabric_source.vhd
new file mode 100644
index 000000000..ec79fb316
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/fabric/xwb_fabric_source.vhd
@@ -0,0 +1,229 @@
+-------------------------------------------------------------------------------
+-- Title      : Wishbone Packet Fabric buffered packet source
+-- Project    : WR Cores Collection
+-------------------------------------------------------------------------------
+-- File       : xwb_fabric_source.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2012-01-16
+-- Last update: 2012-01-22
+-- Platform   : 
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2011 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.genram_pkg.all;
+use work.wr_fabric_pkg.all;
+
+entity xwb_fabric_source is
+  
+  port (
+    clk_i   : in std_logic;
+    rst_n_i : in std_logic;
+
+    -- Wishbone Fabric Interface I/O
+    src_i : in  t_wrf_source_in;
+    src_o : out t_wrf_source_out;
+
+    -- Decoded & buffered fabric
+    addr_i    : in  std_logic_vector(1 downto 0);
+    data_i    : in  std_logic_vector(15 downto 0);
+    dvalid_i  : in  std_logic;
+    sof_i     : in  std_logic;
+    eof_i     : in  std_logic;
+    error_i   : in  std_logic;
+    bytesel_i : in  std_logic;
+    dreq_o    : out std_logic
+    );
+
+end xwb_fabric_source;
+
+architecture rtl of xwb_fabric_source is
+
+  constant c_fifo_width : integer := 16 + 2 + 4;
+
+  signal q_valid, full, we, rd, rd_d0 : std_logic;
+  signal fin, fout                    : std_logic_vector(c_fifo_width-1 downto 0);
+
+  signal pre_dvalid : std_logic;
+  signal pre_eof    : std_logic;
+  signal pre_data   : std_logic_vector(15 downto 0);
+  signal pre_addr   : std_logic_vector(1 downto 0);
+
+  signal post_dvalid, post_eof, post_bytesel, post_sof : std_logic;
+
+  signal err_status : t_wrf_status_reg;
+  signal cyc_int    : std_logic;
+  
+begin  -- rtl
+
+  err_status.error <= '1';
+
+  dreq_o <= not full;
+
+  rd <= not src_i.stall;
+  we <= sof_i or eof_i or error_i or dvalid_i;
+
+  pre_dvalid <= dvalid_i or error_i;
+  pre_data   <= data_i when (error_i = '0') else f_marshall_wrf_status(err_status);
+  pre_addr   <= addr_i when (error_i = '0') else c_WRF_STATUS;
+  pre_eof    <= error_i or eof_i;
+
+  fin <= sof_i & pre_eof & bytesel_i & pre_dvalid & pre_addr & pre_data;
+
+  U_FIFO : generic_shiftreg_fifo
+    generic map (
+      g_data_width => c_fifo_width,
+      g_size       => 16)
+    port map (
+      rst_n_i       => rst_n_i,
+      clk_i         => clk_i,
+      d_i           => fin,
+      we_i          => we,
+      q_o           => fout,
+      rd_i          => rd,
+      almost_full_o => full,
+      q_valid_o     => q_valid);
+
+  post_sof    <= fout(21);
+  post_eof    <= fout(20);
+  post_dvalid <= fout(18);
+
+  p_gen_cyc : process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        cyc_int <= '0';
+      else
+        if( q_valid = '1') then
+          if(post_sof = '1')then
+            cyc_int <= '1';
+          elsif(post_eof = '1') then
+            cyc_int <= '0';
+          end if;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  src_o.cyc <= cyc_int;
+  src_o.we  <= '1';
+  src_o.stb <= post_dvalid and q_valid;
+  src_o.sel <= '1' & not fout(19);
+  src_o.dat <= fout(15 downto 0);
+  src_o.adr <= fout(17 downto 16);
+  
+end rtl;
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.wr_fabric_pkg.all;
+
+entity wb_fabric_source is
+  
+  port (
+    clk_i   : in std_logic;
+    rst_n_i : in std_logic;
+
+    -- Wishbone Fabric Interface I/O
+
+    src_dat_o   : out std_logic_vector(15 downto 0);
+    src_adr_o   : out std_logic_vector(1 downto 0);
+    src_sel_o   : out std_logic_vector(1 downto 0);
+    src_cyc_o   : out std_logic;
+    src_stb_o   : out std_logic;
+    src_we_o    : out std_logic;
+    src_stall_i : in  std_logic;
+    src_ack_i   : in  std_logic;
+    src_err_i   : in  std_logic;
+
+    -- Decoded & buffered fabric
+    addr_i    : in  std_logic_vector(1 downto 0);
+    data_i    : in  std_logic_vector(15 downto 0);
+    dvalid_i  : in  std_logic;
+    sof_i     : in  std_logic;
+    eof_i     : in  std_logic;
+    error_i   : in  std_logic;
+    bytesel_i : in  std_logic;
+    dreq_o    : out std_logic
+    );
+
+end wb_fabric_source;
+
+architecture wrapper of wb_fabric_source is
+  component xwb_fabric_source
+    port (
+      clk_i     : in  std_logic;
+      rst_n_i   : in  std_logic;
+      src_i     : in  t_wrf_source_in;
+      src_o     : out t_wrf_source_out;
+      addr_i    : in  std_logic_vector(1 downto 0);
+      data_i    : in  std_logic_vector(15 downto 0);
+      dvalid_i  : in  std_logic;
+      sof_i     : in  std_logic;
+      eof_i     : in  std_logic;
+      error_i   : in  std_logic;
+      bytesel_i : in  std_logic;
+      dreq_o    : out std_logic);
+  end component;
+
+  signal src_in  : t_wrf_source_in;
+  signal src_out : t_wrf_source_out;
+  
+begin  -- wrapper
+
+  
+  U_Wrapped_Source : xwb_fabric_source
+    port map (
+      clk_i     => clk_i,
+      rst_n_i   => rst_n_i,
+      src_i     => src_in,
+      src_o     => src_out,
+      addr_i    => addr_i,
+      data_i    => data_i,
+      dvalid_i  => dvalid_i,
+      sof_i     => sof_i,
+      eof_i     => eof_i,
+      error_i   => error_i,
+      bytesel_i => bytesel_i,
+      dreq_o    => dreq_o);
+
+  src_cyc_o <= src_out.cyc;
+  src_stb_o <= src_out.stb;
+  src_we_o  <= src_out.we;
+  src_sel_o <= src_out.sel;
+  src_adr_o <= src_out.adr;
+  src_dat_o <= src_out.dat;
+
+  src_in.rty   <= '0';
+  src_in.err   <= src_err_i;
+  src_in.ack   <= src_ack_i;
+  src_in.stall <= src_stall_i;
+
+  
+end wrapper;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/fabric/xwrf_mux.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/fabric/xwrf_mux.vhd
new file mode 100644
index 000000000..5ff1594e1
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/fabric/xwrf_mux.vhd
@@ -0,0 +1,307 @@
+-------------------------------------------------------------------------------
+-- Title      : Simple Pipelined Wishbone MUX/DEMUX for WRPC
+-- Project    : WhiteRabbit
+-------------------------------------------------------------------------------
+-- File       : xwrf_mux.vhd
+-- Author     : Grzegorz Daniluk
+-- Company    : CERN BE-CO-HT
+-- Created    : 2011-08-11
+-- Last update: 2017-02-03
+-- Platform   : FPGA-generics
+-- Standard   : VHDL
+-------------------------------------------------------------------------------
+-- Description:
+-- This is the simple multiplexer/demultiplexer for WR Fabric interface 
+-- (Pipelined Wishbone interface). It forwards ethernet frames between 
+-- WR endpoint, Mini-NIC and external Fabric interface in both directions. 
+-- In the direction 'from' WR endpoint it also decides whether the packet 
+-- has to be forwarded to Mini-NIC (if it is the PTP message) or to the 
+-- external interface (others).
+-------------------------------------------------------------------------------
+-- Copyright (c) 2012-2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2011-08-11  1.0      greg.d          Created
+-- 2012-10-16  2.0      greg.d          generic number of ports
+-------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_misc.all;
+
+use ieee.numeric_std.all;
+
+library work;
+use work.wr_fabric_pkg.all;
+use work.genram_pkg.all;
+
+entity xwrf_mux is
+  generic(
+    g_muxed_ports : integer := 2);
+  port(
+    clk_sys_i   : in  std_logic;
+    rst_n_i     : in  std_logic;
+    --ENDPOINT
+    ep_src_o    : out t_wrf_source_out;
+    ep_src_i    : in  t_wrf_source_in;
+    ep_snk_o    : out t_wrf_sink_out;
+    ep_snk_i    : in  t_wrf_sink_in;
+    --Muxed ports
+    mux_src_o   : out t_wrf_source_out_array(g_muxed_ports-1 downto 0);
+    mux_src_i   : in  t_wrf_source_in_array(g_muxed_ports-1 downto 0);
+    mux_snk_o   : out t_wrf_sink_out_array(g_muxed_ports-1 downto 0);
+    mux_snk_i   : in  t_wrf_sink_in_array(g_muxed_ports-1 downto 0);
+    --
+    mux_class_i : in  t_wrf_mux_class(g_muxed_ports-1 downto 0)
+    );
+end xwrf_mux;
+
+architecture behaviour of xwrf_mux is
+
+  function f_hot_to_bin(x : std_logic_vector(g_muxed_ports-1 downto 0))
+    return integer is
+    variable rv : integer;
+  begin
+    rv := 0;
+    -- if there are few ones set in _x_ then the least significant will be
+    -- translated to bin
+    for i in g_muxed_ports-1 downto 0 loop
+      if x(i) = '1' then
+        rv := i;
+      end if;
+    end loop;
+    return rv;
+  end function;
+
+  function f_match_class(port_mask, pkt_mask : std_logic_vector(7 downto 0)) return std_logic is
+    variable ret : std_logic;
+  begin
+    if((port_mask and pkt_mask) /= x"00") then
+      return '1';
+    else
+      return '0';
+    end if;
+  end function;
+
+  --==================================--
+  --  Masters to Endpoint mux signals --
+  --==================================--
+  type   t_mux is (MUX_SEL, MUX_TRANSFER);
+  signal mux        : t_mux;
+  signal mux_cycs   : std_logic_vector(g_muxed_ports-1 downto 0);
+  signal mux_rrobin : std_logic_vector(g_muxed_ports-1 downto 0);
+  signal mux_select : std_logic_vector(g_muxed_ports-1 downto 0);
+
+  --==================================--
+  -- Endpoint to Slaves demux signals --
+  --==================================--
+  type   t_demux is (DMUX_WAIT, DMUX_STATUS, DMUX_PAYLOAD);
+  signal demux            : t_demux;
+  signal dmux_sel         : std_logic_vector(g_muxed_ports-1 downto 0);
+  signal dmux_status_reg  : std_logic_vector(15 downto 0);
+  signal dmux_select      : std_logic_vector(g_muxed_ports-1 downto 0);
+  signal dmux_others      : std_logic_vector(g_muxed_ports-1 downto 0);
+  signal dmux_sel_zero    : std_logic;
+  signal dmux_snd_stat    : std_logic_vector(g_muxed_ports-1 downto 0);
+  signal ep_stall_mask    : std_logic;
+  signal ep_snk_out_stall : std_logic;
+
+begin
+
+  --=============================================--
+  --                                             --
+  --   Many Fabric Masters talking to ENDPOINT   --
+  --                                             --
+  --=============================================--
+  GEN_MUX_CYCS_REG : for I in 0 to g_muxed_ports-1 generate
+    mux_cycs(I) <= mux_snk_i(I).cyc;
+  end generate;
+
+  p_mux : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if (rst_n_i = '0') then
+        mux_rrobin(0)                        <= '1';
+        mux_rrobin(g_muxed_ports-1 downto 1) <= (others => '0');
+        mux                                  <= MUX_SEL;
+      else
+        case mux is
+          when MUX_SEL =>
+            if (unsigned(mux_cycs and mux_rrobin) /= 0)then
+              mux_select <= mux_cycs and mux_rrobin;
+              mux        <= MUX_TRANSFER;
+            else
+              mux_select <= (others => '0');
+              mux_rrobin <= mux_rrobin(0) & mux_rrobin(g_muxed_ports-1 downto 1);
+            end if;
+
+          when MUX_TRANSFER =>
+            if(unsigned(mux_cycs and mux_select) = 0) then  --cycle end
+              mux_rrobin <= mux_rrobin(0) & mux_rrobin(g_muxed_ports-1 downto 1);
+              mux        <= MUX_SEL;
+            end if;
+        end case;
+
+      end if;
+    end if;
+  end process;
+
+
+  GEN_MUX_CONNS : for J in 0 to g_muxed_ports-1 generate
+    mux_snk_o(J).ack <= ep_src_i.ack when(mux /= MUX_SEL and mux_select(J) = '1') else
+                        '0';
+    mux_snk_o(J).stall <= ep_src_i.stall when(mux /= MUX_SEL and mux_select(J) = '1') else
+                          '1';
+    mux_snk_o(J).err <= ep_src_i.err when(mux /= MUX_SEL and mux_select(J) = '1') else
+                        '0';
+    mux_snk_o(J).rty <= '0';
+  end generate;
+
+  ep_src_o.cyc <= mux_snk_i(f_hot_to_bin(mux_select)).cyc when(mux /= MUX_SEL) else
+                  '0';
+  ep_src_o.stb <= mux_snk_i(f_hot_to_bin(mux_select)).stb when(mux /= MUX_SEL) else
+                  '0';
+  ep_src_o.adr <= mux_snk_i(f_hot_to_bin(mux_select)).adr;
+  ep_src_o.dat <= mux_snk_i(f_hot_to_bin(mux_select)).dat;
+  ep_src_o.sel <= mux_snk_i(f_hot_to_bin(mux_select)).sel;
+  ep_src_o.we  <= '1';
+
+
+  --=============================================--
+  --                                             --
+  --    ENDPOINT talking to many Fabric Slaves   --
+  --                                             --
+  --=============================================--
+
+  CLASS_MATCH : for I in 0 to g_muxed_ports-1 generate
+    dmux_sel(I) <= f_match_class(mux_class_i(I), f_unmarshall_wrf_status(dmux_status_reg).match_class);
+  end generate;
+
+  DMUX_FSM : process(clk_sys_i)
+    variable sel : integer range 0 to g_muxed_ports-1;
+  begin
+    if rising_edge(clk_sys_i) then
+      if(rst_n_i = '0') then
+        dmux_select     <= (others => '0');
+        dmux_snd_stat   <= (others => '0');
+        dmux_status_reg <= (others => '0');
+        ep_stall_mask   <= '0';
+        demux           <= DMUX_WAIT;
+      else
+        case demux is
+                                        ---------------------------------------------------------------
+                                        --State DMUX_WAIT: Wait for the WRF cycle to start and then
+                                        --                 wait for the STATUS word
+                                        ---------------------------------------------------------------
+          when DMUX_WAIT =>
+            dmux_select     <= (others => '0');
+            dmux_snd_stat   <= (others => '0');
+            dmux_status_reg <= (others => '0');
+            ep_stall_mask   <= '0';
+            if(ep_snk_i.cyc = '1' and ep_snk_i.stb = '1' and ep_snk_i.adr = c_WRF_STATUS) then
+              ep_stall_mask   <= '1';
+              dmux_status_reg <= ep_snk_i.dat;
+              demux           <= DMUX_STATUS;
+            end if;
+
+                                        ---------------------------------------------------------------
+                                        --State DMUX_STATUS: Send Status word to appropriate interface
+                                        ---------------------------------------------------------------
+          when DMUX_STATUS =>
+            ep_stall_mask <= '1';
+
+            if(to_integer(unsigned(dmux_sel)) = 0) then  --class not matched to anything, pass pkt to last port
+              dmux_select(g_muxed_ports-1)   <= '1';
+              dmux_snd_stat(g_muxed_ports-1) <= '1';
+              sel                            := g_muxed_ports-1;
+            else
+              dmux_select   <= dmux_sel;
+              dmux_snd_stat <= dmux_sel;
+              sel           := f_hot_to_bin(dmux_sel);
+            end if;
+            if(mux_src_i(sel).stall = '0') then
+              demux <= DMUX_PAYLOAD;
+            end if;
+
+                                        ---------------------------------------------------------------
+                                        --State DMUX_PAYLOAD: Just wait here till the end of the
+                                        --                    current transfer
+                                        ---------------------------------------------------------------
+          when DMUX_PAYLOAD =>
+            dmux_snd_stat <= (others => '0');
+            ep_stall_mask <= '0';
+
+            if(ep_snk_i.cyc = '0') then
+              demux <= DMUX_WAIT;
+            end if;
+
+          when others =>
+            demux <= DMUX_WAIT;
+        end case;
+      end if;
+    end if;
+  end process;
+
+  dmux_sel_zero <= '1' when(to_integer(unsigned(dmux_select)) = 0) else
+                   '0';
+
+  -- dmux_others signal says for given interface I if any other interface was
+  -- also matched to packet class
+  dmux_others(0) <= '0';
+  GEN_DMUX_OTHERS : for I in 1 to g_muxed_ports-1 generate
+    dmux_others(I) <= or_reduce(dmux_select(I-1 downto 0));
+  end generate;
+
+
+  GEN_DMUX_CONN : for I in 0 to g_muxed_ports-1 generate
+    mux_src_o(I).cyc <= ep_snk_i.cyc when(dmux_select(I) = '1' and dmux_others(I) = '0') else
+                        '0';
+    mux_src_o(I).stb <= '1' when(dmux_snd_stat(I) = '1' and dmux_others(I) = '0') else
+                        ep_snk_i.stb when(dmux_select(I) = '1' and dmux_others(I) = '0') else
+                        '0';
+    mux_src_o(I).adr <= c_WRF_STATUS when(dmux_snd_stat(I) = '1' and dmux_others(I) = '0') else
+                        ep_snk_i.adr when(dmux_select(I) = '1' and dmux_others(I) = '0') else
+                        (others => '0');
+    mux_src_o(I).dat <= dmux_status_reg when(dmux_snd_stat(I) = '1' and dmux_others(I) = '0') else
+                        ep_snk_i.dat when(dmux_select(I) = '1' and dmux_others(I) = '0') else
+                        (others => '0');
+    mux_src_o(I).sel <= (others => '1') when(dmux_snd_stat(I) = '1' and dmux_others(I) = '0') else
+                        ep_snk_i.sel when(dmux_select(I) = '1' and dmux_others(I) = '0') else
+                        (others => '1');
+    mux_src_o(I).we <= '1';
+  end generate;
+
+
+  ep_snk_o.ack <= ep_snk_i.cyc and ep_snk_i.stb and not ep_snk_out_stall when(dmux_sel_zero = '1') else
+                  mux_src_i(f_hot_to_bin(dmux_select)).ack;
+
+  ep_snk_o.err <= '0' when(dmux_sel_zero = '1') else
+                  mux_src_i(f_hot_to_bin(dmux_select)).err;
+
+  ep_snk_out_stall <= '1' when(ep_stall_mask = '1') else
+                      '0' when(dmux_sel_zero = '1') else
+                      mux_src_i(f_hot_to_bin(dmux_select)).stall;
+
+  ep_snk_o.stall <= ep_snk_out_stall;
+
+  ep_snk_o.rty <= '0';
+
+end behaviour;
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/timing/dmtd_phase_meas.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/timing/dmtd_phase_meas.vhd
new file mode 100644
index 000000000..2cabc4426
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/timing/dmtd_phase_meas.vhd
@@ -0,0 +1,290 @@
+-------------------------------------------------------------------------------
+-- Title      : Digital DMTD Phase Measurement Unit
+-- Project    : White Rabbit
+-------------------------------------------------------------------------------
+-- File       : dmtd_phase_meas.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-Co-HT
+-- Created    : 2010-02-25
+-- Last update: 2017-02-20
+-- Platform   : FPGA-generic
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Description: Module measures phase shift between the two input clocks
+-- using a DDMTD phase detector. The raw measurement can be further averaged to
+-- increase the accuracy.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2009 - 2017 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2010-02-25  1.0      twlostow        Created
+-- 2011-04-18  1.1      twlostow        Added comments and header
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.NUMERIC_STD.all;
+
+library work;
+use work.gencores_pkg.all;
+
+entity dmtd_phase_meas is
+  generic (
+-- DDMTD deglitcher threshold (in clk_dmtd_i) clock cycles
+    g_deglitcher_threshold: integer;
+-- Phase tag counter size (see dmtd_with_deglitcher.vhd for explanation)
+    g_counter_bits        : integer := 14);
+
+  port (
+-- resets
+    rst_sys_n_i  : in std_logic;
+    rst_dmtd_n_i : in std_logic;
+
+-- system clock 
+    clk_sys_i  : in std_logic;
+-- Input clocks
+    clk_a_i    : in std_logic;
+    clk_b_i    : in std_logic;
+    clk_dmtd_i : in std_logic;
+
+
+    en_i : in std_logic;
+
+    navg_i         : in  std_logic_vector(11 downto 0);
+    phase_meas_o   : out std_logic_vector(31 downto 0);
+    phase_meas_p_o : out std_logic
+    );
+
+end dmtd_phase_meas;
+
+architecture syn of dmtd_phase_meas is
+
+  component dmtd_with_deglitcher
+    generic (
+      g_counter_bits : natural);
+    port (
+      rst_n_dmtdclk_i      : in  std_logic;
+      rst_n_sysclk_i       : in  std_logic;
+      clk_in_i             : in  std_logic;
+      clk_dmtd_i           : in  std_logic;
+      clk_sys_i            : in  std_logic;
+      shift_en_i           : in  std_logic;
+      shift_dir_i          : in  std_logic;
+      deglitch_threshold_i : in  std_logic_vector(15 downto 0);
+      dbg_dmtdout_o        : out std_logic;
+      tag_o                : out std_logic_vector(g_counter_bits-1 downto 0);
+      tag_stb_p1_o         : out std_logic);
+  end component;
+
+  type t_pd_state is (PD_WAIT_TAG, PD_WAIT_A, PD_WAIT_B);
+
+  signal tag_a : std_logic_vector(g_counter_bits-1 downto 0);
+  signal tag_b : std_logic_vector(g_counter_bits-1 downto 0);
+
+  signal tag_a_p : std_logic;
+  signal tag_b_p : std_logic;
+
+  signal acc     : unsigned(31 downto 0);
+  signal avg_cnt : unsigned(11 downto 0);
+
+  signal phase_raw_p : std_logic;
+  signal phase_raw   : unsigned(g_counter_bits-1 downto 0);
+  signal pd_state    : t_pd_state;
+
+  signal phase_hi, phase_lo : std_logic;
+  signal ph_acq_valid       : std_logic;
+
+
+  signal stored_sign   : std_logic;
+  signal preserve_sign : std_logic;
+  
+begin  -- syn
+
+  DMTD_A : dmtd_with_deglitcher
+    generic map (
+      g_counter_bits => g_counter_bits)
+    port map (
+      rst_n_dmtdclk_i       => rst_dmtd_n_i,
+      rst_n_sysclk_i        => rst_sys_n_i,
+      clk_dmtd_i            => clk_dmtd_i,
+      clk_sys_i             => clk_sys_i,
+      clk_in_i              => clk_a_i,
+      tag_o                 => tag_a,
+      tag_stb_p1_o           => tag_a_p,
+      shift_en_i            => '0',
+      shift_dir_i           => '0',
+      deglitch_threshold_i => std_logic_vector(to_unsigned(g_deglitcher_threshold, 16)),
+      dbg_dmtdout_o         => open);
+
+  DMTD_B : dmtd_with_deglitcher
+    generic map (
+      g_counter_bits => g_counter_bits)
+    port map (
+      rst_n_dmtdclk_i       => rst_dmtd_n_i,
+      rst_n_sysclk_i        => rst_sys_n_i,
+      clk_dmtd_i            => clk_dmtd_i,
+      clk_sys_i             => clk_sys_i,
+      clk_in_i              => clk_b_i,
+      tag_o                 => tag_b,
+      tag_stb_p1_o           => tag_b_p,
+      shift_en_i            => '0',
+      shift_dir_i           => '0',
+      deglitch_threshold_i => std_logic_vector(to_unsigned(g_deglitcher_threshold, 16)),
+      dbg_dmtdout_o         => open);
+
+
+  collect_tags : process (clk_sys_i)
+  begin  -- process   
+    if rising_edge(clk_sys_i) then
+      if(rst_sys_n_i = '0' or en_i = '0') then
+        phase_raw    <= (others => '0');
+        phase_raw_p  <= '0';
+        ph_acq_valid <= '0';
+        pd_state     <= PD_WAIT_TAG;
+
+      else
+
+        case pd_state is
+          when PD_WAIT_TAG =>
+
+            if(tag_a_p = '1' and tag_b_p = '1') then
+              phase_raw   <= unsigned(tag_b) - unsigned(tag_a);
+              phase_raw_p <= '1';
+            elsif(tag_a_p = '1') then
+              phase_raw   <= unsigned(tag_a);
+              phase_raw_p <= '0';
+              pd_state    <= PD_WAIT_B;
+            elsif (tag_b_p = '1') then
+              phase_raw   <= (not unsigned(tag_b)) + 1;
+              phase_raw_p <= '0';
+              pd_state    <= PD_WAIT_A;
+            else
+              phase_raw_p <= '0';
+            end if;
+            
+          when PD_WAIT_A =>
+            if(tag_a_p = '1') then
+              phase_raw   <= phase_raw + unsigned(tag_a);
+              phase_raw_p <= '1';
+              pd_state    <= PD_WAIT_TAG;
+            end if;
+
+          when PD_WAIT_B =>
+            if(tag_b_p = '1') then
+              phase_raw   <= phase_raw - unsigned(tag_b);
+              phase_raw_p <= '1';
+              pd_state    <= PD_WAIT_TAG;
+            end if;
+
+            
+          when others => null;
+        end case;
+
+        --if(tag_a_p = '1' and tag_b_p = '1') then
+        --  phase_raw <= unsigned(tag_b) - unsigned(tag_a);
+        --  phase_raw_p <= '1';
+        --  ph_acq_valid <= '0';
+        --elsif(tag_a_p = '1' and tag_b_p = '0' and ph_acq_valid  ='1') then
+        --  phase_raw   <= phase_raw - unsigned(tag_a); 
+        --  phase_raw_p <= '1';
+        --  ph_acq_valid <= '0';
+        --elsif(tag_a_p = '0' and tag_b_p = '1') then
+        --  phase_raw_p <= '0';
+        --  phase_raw <= unsigned(tag_b);
+        --  ph_acq_valid <= '1';
+        --else
+        --  phase_raw_p <= '0';
+        --end if;
+
+
+      end if;
+    end if;
+  end process;
+
+
+  phase_hi <= '1' when phase_raw(phase_raw'high downto phase_raw'high-1) = "11" else '0';
+  phase_lo <= '1' when phase_raw(phase_raw'high downto phase_raw'high-1) = "00" else '0';
+
+
+  calc_error : process (clk_sys_i)
+  begin  -- process calc_error
+    if rising_edge(clk_sys_i) then
+      if(rst_sys_n_i = '0' or en_i = '0') then
+        acc            <= (others => '0');
+        avg_cnt        <= (others => '0');
+        phase_meas_p_o <= '0';
+        phase_meas_o   <= (others => '0');
+        stored_sign    <= '0';
+      else
+        
+
+        if(phase_raw_p = '1') then
+          if(avg_cnt = to_unsigned(0, avg_cnt'length)) then
+            acc <= resize(phase_raw, acc'length);
+
+            if(phase_lo = '1') then
+              preserve_sign <= '1';
+              stored_sign   <= '0';
+            elsif(phase_hi = '1') then
+              preserve_sign <= '1';
+              stored_sign   <= '1';
+            else
+              preserve_sign <= '0';
+            end if;
+
+            avg_cnt        <= avg_cnt + 1;
+            phase_meas_p_o <= '0';
+          elsif (avg_cnt = unsigned(navg_i)) then
+            avg_cnt        <= (others => '0');
+            phase_meas_o   <= std_logic_vector(acc);
+            phase_meas_p_o <= '1';
+          else
+            avg_cnt        <= avg_cnt + 1;
+            phase_meas_p_o <= '0';
+
+
+
+            if(preserve_sign = '1') then
+              if(phase_lo = '1' and stored_sign = '1') then
+                --       report "preserve_sign1";
+                acc <= acc + resize(phase_raw, acc'length) + to_unsigned(2**g_counter_bits, acc'length);
+              elsif (phase_hi = '1' and stored_sign = '0') then
+
+                --report "preserve_sign0";
+                acc <= acc + resize(phase_raw, acc'length) - to_unsigned(2**g_counter_bits, acc'length);
+              else
+                acc <= acc + resize(phase_raw, acc'length);
+              end if;
+            else
+              acc <= acc + resize(phase_raw, acc'length);
+            end if;
+          end if;
+        else
+          phase_meas_p_o <= '0';
+        end if;
+      end if;
+    end if;
+  end process calc_error;
+
+
+end syn;
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/timing/dmtd_with_deglitcher.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/timing/dmtd_with_deglitcher.vhd
new file mode 100644
index 000000000..e1f4528db
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/timing/dmtd_with_deglitcher.vhd
@@ -0,0 +1,353 @@
+-------------------------------------------------------------------------------
+-- Title      : Digital DMTD Edge Tagger
+-- Project    : White Rabbit
+-------------------------------------------------------------------------------
+-- File       : dmtd_with_deglitcher.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-Co-HT
+-- Created    : 2010-02-25
+-- Last update: 2014-07-15
+-- Platform   : FPGA-generic
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Description: Single-channel DDMTD phase tagger with integrated bit-median
+-- deglitcher. Contains a DDMTD detector, which output signal is deglitched and
+-- tagged with a counter running in DMTD offset clock domain. Phase tags are
+-- generated for each rising edge in DDMTD output with an internal counter
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2009 - 2011 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2009-01-24  1.0      twlostow        Created
+-- 2011-18-04  1.1      twlostow        Bit-median type deglitcher, comments
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.NUMERIC_STD.all;
+
+library work;
+use work.gencores_pkg.all;
+
+entity dmtd_with_deglitcher is
+  generic (
+    -- Size of the phase tag counter. Must be big enough to cover at least one
+    -- full period of the DDMTD detector output. Given the frequencies of clk_in_i
+    -- and clk_dmtd_i are respectively f_in an f_dmtd, it can be calculated with
+    -- the following formula:
+    -- g_counter_bits = log2(f_in / abs(f_in - f_dmtd)) + 1
+    g_counter_bits : natural := 17;
+    g_chipscope    : boolean := false;
+
+    -- Divides the inputs by 2 (effectively passing the clock through a flip flop)
+    -- before it gets to the DMTD, effectively removing Place&Route warnings
+    -- (at the cost of detector bandwidth)
+    g_divide_input_by_2 : boolean := false;
+
+    -- reversed mode: samples clk_dmtd with clk_in.
+    g_reverse : boolean := false
+    );
+  port (
+    -- resets for different clock domains
+    rst_n_dmtdclk_i : in std_logic;
+    rst_n_sysclk_i  : in std_logic;
+
+    -- input clock
+    clk_in_i : in std_logic;
+
+    -- DMTD sampling clock
+    clk_dmtd_i : in std_logic;
+
+    -- system clock
+    clk_sys_i : in std_logic;
+
+    -- async counter resync input: resets only the DDMTD state machine and free
+    -- running counter, synchronized to clk_dmtd_i
+    resync_p_a_i : in std_logic := '0';
+
+    -- [clk_dmtd_i] counter resync output, pulses when free_cntr == 0
+    resync_p_o : out std_logic;
+
+    -- [clk_sys_i] starts resynchronization
+    resync_start_p_i : in std_logic := '0';
+
+    -- [clk_sys_i] 1: resynchonization done
+    resync_done_o : out std_logic;
+
+    -- [clk_dmtd_i] phase shifter enable, HI level shifts the internal counter
+    -- forward/backward by 1 clk_dmtd_i cycle, effectively shifting the tag
+    -- value by +-1.
+    shift_en_i : in std_logic := '0';
+
+    -- [clk_dmtd_i] phase shift direction: 1 - forward, 0 - backward
+    shift_dir_i : in std_logic := '0';
+
+    -- DMTD clock enable, active high. Can be used to reduce the DMTD sampling
+    -- frequency - for example, two 10 MHz signals cannot be sampled directly
+    -- with a 125 MHz clock, but it's possible with a 5 MHz reference, obtained
+    -- by asserting clk_dmtd_en_i every 25 clk_dmtd_i cycles.
+
+    clk_dmtd_en_i : in std_logic := '1';
+
+    -- [clk_dmtd_i] deglitcher threshold
+    deglitch_threshold_i : in std_logic_vector(15 downto 0);
+
+    -- [clk_dmtd_i] raw DDMTD output (for debugging purposes)
+    dbg_dmtdout_o : out std_logic;
+
+    -- [clk_sys_i] deglitched edge tag value
+    tag_o : out std_logic_vector(g_counter_bits-1 downto 0);
+
+    -- [clk_sys_i] pulse indicates new phase tag on tag_o
+    tag_stb_p1_o : out std_logic;
+    dbg_clk_d3_o : out std_logic
+    );
+
+end dmtd_with_deglitcher;
+
+architecture rtl of dmtd_with_deglitcher is
+
+  type t_state is (WAIT_STABLE_0, WAIT_EDGE, GOT_EDGE);
+
+  signal state : t_state;
+
+  signal stab_cntr : unsigned(15 downto 0);
+  signal free_cntr : unsigned(g_counter_bits-1 downto 0);
+
+  signal s_one        : std_logic;
+
+  signal clk_in                                           : std_logic;
+  signal clk_i_d0, clk_i_d1, clk_i_d2, clk_i_d3, clk_i_dx : std_logic;
+
+  attribute keep             : string;
+  attribute keep of clk_in   : signal is "true";
+  attribute keep of clk_i_d0 : signal is "true";
+  attribute keep of clk_i_d1 : signal is "true";
+  attribute keep of clk_i_d2 : signal is "true";
+  attribute keep of clk_i_d3 : signal is "true";
+
+  signal new_edge_sreg : std_logic_vector(5 downto 0);
+  signal new_edge_p    : std_logic;
+
+  signal tag_int       : unsigned(g_counter_bits-1 downto 0);
+  signal resync_p_dmtd : std_logic;
+
+  signal resync_start_p_dmtd, resync_done_dmtd, resync_p_int : std_logic;
+  
+begin  -- rtl
+
+  U_Sync_Resync_Pulse : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_dmtd_i,
+      rst_n_i  => rst_n_dmtdclk_i,
+      data_i   => resync_p_a_i,
+      synced_o => resync_p_dmtd);
+
+  U_Sync_Start_Pulse : gc_pulse_synchronizer
+    port map (
+      clk_in_i  => clk_sys_i,
+      clk_out_i => clk_dmtd_i,
+      rst_n_i   => rst_n_dmtdclk_i,
+      d_ready_o => open,
+      d_p_i     => resync_start_p_i,
+      q_p_o     => resync_start_p_dmtd);
+
+  U_Sync_Resync_Done : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_sys_i,
+      rst_n_i  => rst_n_sysclk_i,
+      data_i   => resync_done_dmtd,
+      synced_o => resync_done_o);
+
+
+  gen_straight : if(g_reverse = false) generate
+    
+    gen_input_div2 : if(g_divide_input_by_2 = true) generate
+      p_divide_input_clock : process(clk_in_i, rst_n_sysclk_i)
+      begin
+        if rst_n_sysclk_i = '0' then
+          clk_in <= '0';
+        elsif rising_edge(clk_in_i) then
+          clk_in <= not clk_in;
+        end if;
+      end process;
+    end generate gen_input_div2;
+
+    gen_input_straight : if(g_divide_input_by_2 = false) generate
+      clk_in <= clk_in_i;
+    end generate gen_input_straight;
+
+    p_the_dmtd_itself : process(clk_dmtd_i)
+    begin
+      if rising_edge(clk_dmtd_i) then
+        clk_i_d0 <= clk_in;
+        clk_i_d1 <= clk_i_d0;
+        clk_i_d2 <= clk_i_d1;
+        clk_i_d3 <= clk_i_d2;
+      end if;
+    end process;
+
+  end generate gen_straight;
+
+  gen_reverse : if(g_reverse = true) generate
+
+    assert (not g_divide_input_by_2) report "dmtd_with_deglitcher: g_reverse implies g_divide_input_by_2 == false" severity failure;
+
+    clk_in <= clk_in_i;
+
+    p_the_dmtd_itself : process(clk_in)
+    begin
+      if rising_edge(clk_in) then
+        clk_i_d0 <= clk_dmtd_i;
+        clk_i_d1 <= clk_i_d0;
+      end if;
+    end process;
+
+    p_sync : process(clk_dmtd_i)
+    begin
+      if rising_edge(clk_dmtd_i) then
+        clk_i_dx <= clk_i_d1;
+        clk_i_d2 <= not clk_i_dx;
+        clk_i_d3 <= clk_i_d2;
+      end if;
+    end process;
+
+  end generate gen_reverse;
+
+-- glitchproof DMTD output edge detection
+  p_deglitch : process (clk_dmtd_i)
+  begin  -- process deglitch
+
+    if rising_edge(clk_dmtd_i) then     -- rising clock edge
+
+      if (rst_n_dmtdclk_i = '0' or (resync_p_dmtd = '1' and resync_done_dmtd = '0')) then  -- synchronous reset (active low)
+        stab_cntr     <= (others => '0');
+        state         <= WAIT_STABLE_0;
+        free_cntr     <= (others => '0');
+        new_edge_sreg <= (others => '0');
+      elsif(clk_dmtd_en_i = '1') then
+        
+        if (shift_en_i = '0') then      -- phase shifter
+          free_cntr <= free_cntr + 1;
+        elsif (shift_dir_i = '1') then
+          free_cntr <= free_cntr + 2;
+        end if;
+
+        case state is
+          when WAIT_STABLE_0 =>         -- out-of-sync
+            new_edge_sreg <= '0' & new_edge_sreg(new_edge_sreg'length-1 downto 1);
+
+            if clk_i_d3 /= '0' then
+              stab_cntr <= (others => '0');
+            else
+              stab_cntr <= stab_cntr + 1;
+            end if;
+
+            -- DMTD output stable counter hit the LOW level threshold?
+            if stab_cntr = unsigned(deglitch_threshold_i) then
+              state <= WAIT_EDGE;
+            end if;
+
+          when WAIT_EDGE =>
+            if (clk_i_d3 /= '0') then   -- got a glitch?
+              state     <= GOT_EDGE;
+              tag_int   <= free_cntr;
+              stab_cntr <= (others => '0');
+            end if;
+
+          when GOT_EDGE =>
+            if (clk_i_d3 = '0') then
+              tag_int <= tag_int + 1;
+            end if;
+
+            if stab_cntr = unsigned(deglitch_threshold_i) then
+              state         <= WAIT_STABLE_0;
+              tag_o         <= std_logic_vector(tag_int);
+              new_edge_sreg <= (others => '1');
+              stab_cntr     <= (others => '0');
+            elsif (clk_i_d3 = '0') then
+              stab_cntr <= (others => '0');
+            else
+              stab_cntr <= stab_cntr + 1;
+            end if;
+
+            
+        end case;
+      end if;
+    end if;
+  end process p_deglitch;
+
+  p_resync_pulse_output : process(clk_dmtd_i)
+  begin
+    if rising_edge(clk_dmtd_i) then
+      if(unsigned(free_cntr(free_cntr'length-1 downto 3)) = 0) then
+        resync_p_o <= '1';
+      else
+        resync_p_o <= '0';
+      end if;
+    end if;
+  end process;
+
+  p_resync_pulse_trigger : process(clk_dmtd_i)
+  begin
+    if rising_edge(clk_dmtd_i) then
+      if rst_n_dmtdclk_i = '0' then
+        resync_done_dmtd <= '1';
+      else
+        if(resync_start_p_dmtd = '1') then
+          resync_done_dmtd <= '0';
+        elsif(resync_p_dmtd = '1') then
+          resync_done_dmtd <= '1';
+        end if;
+      end if;
+    end if;
+  end process;
+
+  U_sync_tag_strobe : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_sys_i,
+      rst_n_i  => rst_n_sysclk_i,
+      data_i   => new_edge_sreg(0),
+      synced_o => open,
+      npulse_o => open,
+      ppulse_o => new_edge_p);
+
+  tag_stb_p1_o <= new_edge_p;
+
+  U_Extend_Debug_Pulses : gc_extend_pulse
+    generic map (
+      g_width => 3000)
+    port map (
+      clk_i      => clk_sys_i,
+      rst_n_i    => rst_n_sysclk_i,
+      pulse_i    => new_edge_p,
+      extended_o => dbg_dmtdout_o);
+
+	dbg_clk_d3_o <= clk_i_d3;
+
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/timing/pulse_stamper.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/timing/pulse_stamper.vhd
new file mode 100644
index 000000000..fb55da00c
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/timing/pulse_stamper.vhd
@@ -0,0 +1,161 @@
+-------------------------------------------------------------------------------
+-- Entity: pulse_stamper
+-- File: pulse_stamper.vhd
+-- Description: a time-tagger which associates a time-tag with an asyncrhonous
+-- input pulse.
+-- Author: Javier Serrano (Javier.Serrano@cern.ch)
+-- Date: 24 January 2012
+-- Version: 0.01
+-- Todo: Factor out syncrhonizer in a separate reusable block.
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--               GNU LESSER GENERAL PUBLIC LICENSE                             
+--              -----------------------------------                            
+-- This source file is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU Lesser General Public License as published by the
+-- Free Software Foundation; either version 2.1 of the License, or (at your
+-- option) any later version.                           
+-- This source is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
+-- for more details. You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it from
+-- http://www.gnu.org/licenses/lgpl-2.1.html                  
+-------------------------------------------------------------------------------
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity pulse_stamper is
+  
+  generic (
+    -- reference clock frequency
+    g_ref_clk_rate : integer := 125000000);
+
+  port(
+    clk_ref_i : in std_logic;           -- timing reference clock
+    clk_sys_i : in std_logic;           -- data output reference clock
+    rst_n_i   : in std_logic;           -- system reset
+
+    pulse_a_i : in std_logic;           -- pulses to be stamped
+
+    -------------------------------------------------------------------------------
+    -- Timing input (from WRPC), clk_ref_i domain
+    ------------------------------------------------------------------------------
+
+    -- 1: time given on tm_utc_i and tm_cycles_i is valid (otherwise, don't timestamp)
+    tm_time_valid_i : in std_logic;
+    -- number of seconds
+    tm_tai_i        : in std_logic_vector(39 downto 0);
+    -- number of clk_ref_i cycles
+    tm_cycles_i     : in std_logic_vector(27 downto 0);
+
+
+    ---------------------------------------------------------------------------
+    -- Time tag output (clk_sys_i domain)
+    ---------------------------------------------------------------------------
+    tag_tai_o      : out std_logic_vector(39 downto 0);
+    tag_cycles_o   : out std_logic_vector(27 downto 0);
+    -- single-cycle pulse: strobe tag on tag_utc_o and tag_cycles_o
+    tag_valid_o : out std_logic
+    );
+
+  
+end pulse_stamper;
+
+architecture rtl of pulse_stamper is
+
+ -- Signals for input anti-metastability ffs
+ signal pulse_ref : std_logic_vector(2 downto 0);
+ signal pulse_ref_p1 : std_logic;
+ signal pulse_ref_p1_d1 : std_logic;
+ 
+ -- Time tagger signals
+ signal tag_utc_ref : std_logic_vector(39 downto 0);
+ signal tag_cycles_ref : std_logic_vector(27 downto 0);
+
+ -- Signals for synchronizer
+ signal rst_from_sync : std_logic;
+ signal pulse_ref_d2 : std_logic;
+ signal pulse_sys : std_logic_vector(2 downto 0);
+ signal pulse_sys_p1 : std_logic;
+ signal pulse_back : std_logic_vector(2 downto 0);
+ 
+begin  -- architecture rtl
+
+ -- Synchronization of external pulse into the clk_ref_i clock domain
+ sync_ext_pulse: process (clk_ref_i)
+ begin
+  if clk_ref_i'event and clk_ref_i='1' then
+    pulse_ref <= pulse_ref(1 downto 0) & pulse_a_i;
+    pulse_ref_p1 <= pulse_ref(1) and not pulse_ref(2);
+    pulse_ref_p1_d1 <= pulse_ref_p1 and tm_time_valid_i;
+  end if;
+ end process sync_ext_pulse;
+
+ -- Time tagging of the pulse, still in the clk_ref_i domain
+ tagger: process (clk_ref_i)
+ begin
+  if clk_ref_i'event and clk_ref_i='1' then
+    if pulse_ref_p1='1' and tm_time_valid_i='1' then
+      tag_utc_ref <= tm_tai_i;
+      tag_cycles_ref <= tm_cycles_i;
+    end if;
+  end if;
+ end process tagger;
+
+ -- Synchronizer to pass UTC register data to the system clock domain
+ -- This synchronizer is made with the following three processes
+
+ -- First one FF with async reset, still in the clk_ref_i domain
+ sync_first_ff: process (clk_ref_i, rst_n_i, rst_from_sync)
+ begin
+  if rst_n_i='0' or rst_from_sync='1' then
+    pulse_ref_d2 <= '0';
+  elsif clk_ref_i'event and clk_ref_i='1' then
+    if pulse_ref_p1_d1='1' then
+      pulse_ref_d2 <= '1';
+    end if;
+  end if;
+ end process sync_first_ff;
+
+ -- Then three FFs to take the strobe safely into the clk_sys_i domain
+ sync_sys: process (clk_sys_i)
+ begin
+  if clk_sys_i'event and clk_sys_i='1' then
+   pulse_sys <= pulse_sys(1 downto 0) & pulse_ref_d2;
+   pulse_sys_p1 <= pulse_sys(1) and not pulse_sys(2);
+  end if;
+ end process sync_sys;
+
+ -- And then back into the clk_ref_i domain
+ sync_ref: process (clk_ref_i)
+ begin
+  if clk_ref_i'event and clk_ref_i='1' then
+    pulse_back <= pulse_back(1 downto 0) & pulse_sys(2);
+    rst_from_sync <= pulse_back(2);
+  end if;
+ end process sync_ref;
+
+ -- Now we can take the time tags into the clk_sys_i domain
+ sys_tags: process (clk_sys_i)
+ begin
+  if clk_sys_i'event and clk_sys_i='1' then
+    if rst_n_i='0' then
+     tag_tai_o <= (others=>'0');
+     tag_cycles_o <= (others=>'0');
+     tag_valid_o <= '0';
+    elsif pulse_sys_p1='1' then
+     tag_tai_o <= tag_utc_ref;
+     tag_cycles_o <= tag_cycles_ref;
+     tag_valid_o <= '1';
+    else
+     tag_valid_o <='0';
+    end if;
+  end if;
+ end process sys_tags;
+ 
+end architecture rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_dacs/spec_serial_dac.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_dacs/spec_serial_dac.vhd
new file mode 100644
index 000000000..c28410f68
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_dacs/spec_serial_dac.vhd
@@ -0,0 +1,209 @@
+-------------------------------------------------------------------------------
+-- Title      : Serial DAC interface
+-- Project    : White Rabbit
+-------------------------------------------------------------------------------
+-- File       : spec_serial_dac.vhd
+-- Author     : paas, slayer
+-- Company    : CERN BE-Co-HT
+-- Created    : 2010-02-25
+-- Last update: 2011-05-10
+-- Platform   : fpga-generic
+-- Standard   : VHDL'87
+-------------------------------------------------------------------------------
+-- Description: The dac unit provides an interface to a 16 bit serial Digital
+-- to Analogue converter (max5441, SPI?/QSPI?/MICROWIRE? compatible) 
+--
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2010 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :1
+-- Date        Version  Author  Description
+-- 2009-01-24  1.0      paas    Created
+-- 2010-02-25  1.1      slayer  Modified for rev 1.1 switch
+-------------------------------------------------------------------------------
+
+
+library IEEE;
+
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+
+entity spec_serial_dac is
+
+  generic (
+    g_num_data_bits  : integer := 16;
+    g_num_extra_bits : integer := 8;
+    g_num_cs_select  : integer := 2
+    );
+
+  port (
+-- clock & reset
+    clk_i   : in std_logic;
+    rst_n_i : in std_logic;
+
+-- channel 1 value and value load strobe
+    value_i  : in std_logic_vector(g_num_data_bits-1 downto 0);
+    cs_sel_i : in std_logic_vector(g_num_cs_select-1 downto 0);
+    load_i   : in std_logic;
+
+-- SCLK divider: 000 = clk_i/8 ... 111 = clk_i/1024
+    sclk_divsel_i : in std_logic_vector(2 downto 0);
+
+-- DAC I/F
+    dac_cs_n_o  : out std_logic_vector(g_num_cs_select-1 downto 0);
+    dac_sclk_o  : out std_logic;
+    dac_sdata_o : out std_logic;
+
+    xdone_o : out std_logic
+    );
+end spec_serial_dac;
+
+
+architecture syn of spec_serial_dac is
+
+  signal divider        : unsigned(11 downto 0);
+  signal dataSh         : std_logic_vector(g_num_data_bits + g_num_extra_bits-1 downto 0);
+  signal bitCounter     : std_logic_vector(g_num_data_bits + g_num_extra_bits+1 downto 0);
+  signal endSendingData : std_logic;
+  signal sendingData    : std_logic;
+  signal iDacClk        : std_logic;
+  signal iValidValue    : std_logic;
+
+  signal divider_muxed : std_logic;
+
+  signal cs_sel_reg : std_logic_vector(g_num_cs_select-1 downto 0);
+  
+begin
+
+  select_divider : process (divider, sclk_divsel_i)
+  begin  -- process
+    case sclk_divsel_i is
+      when "000"  => divider_muxed <= divider(1);  -- sclk = clk_i/8
+      when "001"  => divider_muxed <= divider(2);  -- sclk = clk_i/16
+      when "010"  => divider_muxed <= divider(3);  -- sclk = clk_i/32
+      when "011"  => divider_muxed <= divider(4);  -- sclk = clk_i/64
+      when "100"  => divider_muxed <= divider(5);  -- sclk = clk_i/128
+      when "101"  => divider_muxed <= divider(6);  -- sclk = clk_i/256
+      when "110"  => divider_muxed <= divider(7);  -- sclk = clk_i/512
+      when "111"  => divider_muxed <= divider(8);  -- sclk = clk_i/1024
+      when others => null;
+    end case;
+  end process;
+
+
+  iValidValue <= load_i;
+
+  process(clk_i, rst_n_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        sendingData <= '0';
+      else
+        if iValidValue = '1' and sendingData = '0' then
+          sendingData <= '1';
+        elsif endSendingData = '1' then
+          sendingData <= '0';
+        end if;
+      end if;
+    end if;
+  end process;
+
+  process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if iValidValue = '1' then
+        divider <= (others => '0');
+      elsif sendingData = '1' then
+        if(divider_muxed = '1') then
+          divider <= (others => '0');
+        else
+          divider <= divider + 1;
+        end if;
+      elsif endSendingData = '1' then
+        divider <= (others => '0');
+      end if;
+    end if;
+  end process;
+
+
+  process(clk_i, rst_n_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        iDacClk <= '1';                 -- 0
+      else
+        if iValidValue = '1' then
+          iDacClk <= '1';               -- 0
+        elsif divider_muxed = '1' then
+          iDacClk <= not(iDacClk);
+        elsif endSendingData = '1' then
+          iDacClk <= '1';               -- 0
+        end if;
+      end if;
+    end if;
+  end process;
+
+  process(clk_i, rst_n_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        dataSh <= (others => '0');
+      else
+        if iValidValue = '1' and sendingData = '0' then
+          cs_sel_reg <= cs_sel_i;
+          dataSh(g_num_data_bits-1 downto 0)     <= value_i;
+          dataSh(dataSh'left downto g_num_data_bits) <= (others => '0');
+        elsif sendingData = '1' and divider_muxed = '1' and iDacClk = '0' then
+          dataSh(0)                    <= dataSh(dataSh'left);
+          dataSh(dataSh'left downto 1) <= dataSh(dataSh'left - 1 downto 0);
+        end if;
+      end if;
+    end if;
+  end process;
+
+  process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if iValidValue = '1' and sendingData = '0' then
+        bitCounter(0)                        <= '1';
+        bitCounter(bitCounter'left downto 1) <= (others => '0');
+      elsif sendingData = '1' and to_integer(divider) = 0 and iDacClk = '1' then
+        bitCounter(0)                        <= '0';
+        bitCounter(bitCounter'left downto 1) <= bitCounter(bitCounter'left - 1 downto 0);
+      end if;
+    end if;
+  end process;
+
+  endSendingData <= bitCounter(bitCounter'left);
+
+  xdone_o <= not SendingData;
+
+  dac_sdata_o <= dataSh(dataSh'left);
+
+  gen_cs_out : for i in 0 to g_num_cs_select-1 generate
+    dac_cs_n_o(i) <= not(sendingData) or (not cs_sel_reg(i));
+  end generate gen_cs_out;
+
+  dac_sclk_o <= iDacClk;
+
+
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_dacs/spec_serial_dac_arb.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_dacs/spec_serial_dac_arb.vhd
new file mode 100644
index 000000000..511bb27b7
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_dacs/spec_serial_dac_arb.vhd
@@ -0,0 +1,187 @@
+-------------------------------------------------------------------------------
+-- Title      : SPEC serial DAC interface with arbiter
+-- Project    : White Rabbit
+-------------------------------------------------------------------------------
+-- File       : spec_serial_dac.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-Co-HT
+-- Platform   : fpga-generic
+-- Standard   : VHDL'87
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2011 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+entity spec_serial_dac_arb is
+  generic(
+    g_invert_sclk    : boolean;
+    g_num_extra_bits : integer
+    );
+  port(
+    clk_i   : in std_logic;
+    rst_n_i : in std_logic;
+
+    val1_i  : in std_logic_vector(15 downto 0);
+    load1_i : in std_logic;
+    val2_i  : in std_logic_vector(15 downto 0);
+    load2_i : in std_logic;
+
+    dac_cs_n_o  : out std_logic_vector(1 downto 0);
+    dac_clr_n_o : out std_logic;
+    dac_sclk_o  : out std_logic;
+    dac_din_o   : out std_logic);
+
+end spec_serial_dac_arb;
+
+architecture behavioral of spec_serial_dac_arb is
+
+  component spec_serial_dac
+    generic (
+      g_num_data_bits  : integer;
+      g_num_extra_bits : integer;
+      g_num_cs_select  : integer);
+    port (
+      clk_i         : in  std_logic;
+      rst_n_i       : in  std_logic;
+      value_i       : in  std_logic_vector(g_num_data_bits-1 downto 0);
+      cs_sel_i      : in  std_logic_vector(g_num_cs_select-1 downto 0);
+      load_i        : in  std_logic;
+      sclk_divsel_i : in  std_logic_vector(2 downto 0);
+      dac_cs_n_o    : out std_logic_vector(g_num_cs_select-1 downto 0);
+      dac_sclk_o    : out std_logic;
+      dac_sdata_o   : out std_logic;
+      xdone_o       : out std_logic);
+  end component;
+
+  signal d1, d2             : std_logic_vector(15 downto 0);
+  signal d1_ready, d2_ready : std_logic;
+
+
+  signal dac_data     : std_logic_vector(15 downto 0);
+  signal dac_load     : std_logic;
+  signal dac_cs_sel   : std_logic_vector(1 downto 0);
+  signal dac_done     : std_logic;
+  signal dac_sclk_int : std_logic;
+
+  type t_state is (WAIT_DONE, LOAD_DAC, WAIT_DATA);
+
+  signal state : t_state;
+
+  signal trig0    : std_logic_vector(31 downto 0);
+  signal trig1    : std_logic_vector(31 downto 0);
+  signal trig2    : std_logic_vector(31 downto 0);
+  signal trig3    : std_logic_vector(31 downto 0);
+  signal CONTROL0 : std_logic_vector(35 downto 0);
+
+begin  -- behavioral
+
+  dac_clr_n_o <= '1';
+
+  U_DAC : spec_serial_dac
+    generic map (
+      g_num_data_bits  => 16,
+      g_num_extra_bits => g_num_extra_bits,
+      g_num_cs_select  => 2)
+    port map (
+      clk_i         => clk_i,
+      rst_n_i       => rst_n_i,
+      value_i       => dac_data,
+      cs_sel_i      => dac_cs_sel,
+      load_i        => dac_load,
+      sclk_divsel_i => "001",
+      dac_cs_n_o    => dac_cs_n_o,
+      dac_sclk_o    => dac_sclk_int,
+      dac_sdata_o   => dac_din_o,
+      xdone_o       => dac_done);
+
+
+  p_drive_sclk: process(dac_sclk_int)
+    begin
+      if(g_invert_sclk) then
+        dac_sclk_o <= not dac_sclk_int;
+       else
+        dac_sclk_o <= dac_sclk_int;
+       end if;
+      end process;
+
+  process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        d1         <= (others => '0');
+        d1_ready   <= '0';
+        d2         <= (others => '0');
+        d2_ready   <= '0';
+        dac_load   <= '0';
+        dac_cs_sel <= (others => '0');
+        state      <= WAIT_DATA;
+      else
+
+        if(load1_i = '1' or load2_i = '1') then
+          
+          if(load1_i = '1') then
+            d1_ready <= '1';
+            d1       <= val1_i;
+          end if;
+
+          if(load2_i = '1') then
+            d2_ready <= '1';
+            d2       <= val2_i;
+          end if;
+        else
+          case state is
+            when WAIT_DATA =>
+              if(d1_ready = '1') then
+                dac_cs_sel <= "01";
+                dac_data   <= d1;
+                dac_load   <= '1';
+                d1_ready   <= '0';
+                state      <= LOAD_DAC;
+              elsif(d2_ready = '1') then
+                dac_cs_sel <= "10";
+                dac_data   <= d2;
+                dac_load   <= '1';
+                d2_ready   <= '0';
+                state      <= LOAD_DAC;
+              end if;
+
+            when LOAD_DAC=>
+              dac_load <= '0';
+              state    <= WAIT_DONE;
+
+            when WAIT_DONE =>
+              if(dac_done = '1') then
+                state <= WAIT_DATA;
+              end if;
+            when others => null;
+          end case;
+        end if;
+      end if;
+    end if;
+  end process;
+  
+
+  
+  
+end behavioral;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/endpoint_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/endpoint_pkg.vhd
new file mode 100644
index 000000000..5d1a794ad
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/endpoint_pkg.vhd
@@ -0,0 +1,469 @@
+-------------------------------------------------------------------------------
+-- Title      : 1000base-X MAC/Endpoint
+-- Project    : White Rabbit 
+-------------------------------------------------------------------------------
+-- File       : endpoint_pkg.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2010-04-26
+-- Last update: 2017-02-20
+-- Platform   : FPGA-generic
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Description: Public package for the WR Endpoint. Contains public data
+-- structures and component declarations.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2011-2017 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.wishbone_pkg.all;
+use work.wr_fabric_pkg.all;
+
+package endpoint_pkg is
+
+  function f_pcs_data_width(pcs_16 : boolean) return integer;
+  function f_pcs_k_width(pcs_16 : boolean) return integer;
+  function f_pcs_bts_width(pcs_16 : boolean) return integer;
+  function f_pcs_clock_rate(pcs_16 : boolean) return integer;
+
+  type t_txtsu_timestamp is record
+    stb       : std_logic;
+    tsval     : std_logic_vector(31 downto 0);
+    port_id   : std_logic_vector(5 downto 0);
+    frame_id  : std_logic_vector(15 downto 0);
+    incorrect : std_logic;
+  end record;
+
+  type t_txtsu_timestamp_array is array(integer range <>) of t_txtsu_timestamp;
+
+  -- Endpoint's internal fabric used to connect the submodules with each other.
+  -- Easier to handle than pipelined Wishbone.
+  type t_ep_internal_fabric is record
+    sof                : std_logic;
+    eof                : std_logic;
+    error              : std_logic;
+    dvalid             : std_logic;
+    bytesel            : std_logic;
+    has_rx_timestamp   : std_logic;
+    rx_timestamp_valid : std_logic;
+    data               : std_logic_vector(15 downto 0);
+    addr               : std_logic_vector(1 downto 0);
+  end record;
+  type t_fab_pipe is array(integer range <>) of t_ep_internal_fabric;
+
+  -----------------------------
+  -- Phy i/f types
+  -----------------------------
+  -- 8-bit Serdes
+  type t_phy_8bits_to_wrc is record
+    ref_clk        : std_logic;
+    tx_disparity   : std_logic;
+    tx_enc_err     : std_logic;
+    rx_data        : std_logic_vector(7 downto 0);
+    rx_clk         : std_logic;
+    rx_k           : std_logic_vector(0 downto 0);
+    rx_enc_err     : std_logic;
+    rx_bitslide    : std_logic_vector(3 downto 0);
+    rdy            : std_logic;
+    sfp_tx_fault   : std_logic;
+    sfp_los        : std_logic;
+  end record;
+  type t_phy_8bits_from_wrc is record
+    rst            : std_logic;
+    loopen         : std_logic;
+    tx_data        : std_logic_vector(7 downto 0);
+    tx_k           : std_logic_vector(0 downto 0);
+    loopen_vec     : std_logic_vector(2 downto 0);
+    tx_prbs_sel    : std_logic_vector(2 downto 0);
+    sfp_tx_disable : std_logic;
+  end record;
+
+  constant c_dummy_phy8_to_wrc : t_phy_8bits_to_wrc :=
+    ('0', '0', '0', (others=>'0'), '0', (others=>'0'), '0',
+    (others=>'0'), '0', '0', '0');
+  constant c_dummy_phy8_from_wrc : t_phy_8bits_from_wrc :=
+    ('0', '0', (others=>'0'), (others=>'0'), (others=>'0'),
+    (others=>'0'), '0');
+
+  -- 16-bit Serdes
+  type t_phy_16bits_to_wrc is record
+    ref_clk        : std_logic;
+    tx_disparity   : std_logic;
+    tx_enc_err     : std_logic;
+    rx_data        : std_logic_vector(15 downto 0);
+    rx_clk         : std_logic;
+    rx_k           : std_logic_vector(1 downto 0);
+    rx_enc_err     : std_logic;
+    rx_bitslide    : std_logic_vector(4 downto 0);
+    rdy            : std_logic;
+    sfp_tx_fault   : std_logic;
+    sfp_los        : std_logic;
+  end record;
+  type t_phy_16bits_from_wrc is record
+    rst            : std_logic;
+    loopen         : std_logic;
+    tx_data        : std_logic_vector(15 downto 0);
+    tx_k           : std_logic_vector(1 downto 0);
+    loopen_vec     : std_logic_vector(2 downto 0);
+    tx_prbs_sel    : std_logic_vector(2 downto 0);
+    sfp_tx_disable : std_logic;
+  end record;
+
+  constant c_dummy_phy16_to_wrc : t_phy_16bits_to_wrc :=
+    ('0', '0', '0', (others=>'0'), '0', (others=>'0'), '0',
+    (others=>'0'), '0', '0', '0');
+  constant c_dummy_phy16_from_wrc : t_phy_16bits_from_wrc :=
+    ('0', '0', (others=>'0'), (others=>'0'), (others=>'0'),
+    (others=>'0'), '0');
+
+
+  -- debug CS types
+  type t_dbg_ep_rxpcs is record
+    fsm : std_logic_vector(2 downto 0);
+  end record;
+
+  type t_dbg_ep_pcs is record
+    rx : t_dbg_ep_rxpcs;
+  end record;
+
+  type t_dbg_ep_rxpath is record
+    fab_pipe  : t_fab_pipe(9 downto 0);
+    dreq_pipe : std_logic_vector(9 downto 0);
+    pcs_fifo_afull : std_logic;
+    pcs_fifo_empty : std_logic;
+    pcs_fifo_full  : std_logic;
+    rxbuf_full     : std_logic;
+  end record;
+
+  type t_dbg_ep is record
+    pcs    : t_dbg_ep_pcs;
+    rxpath : t_dbg_ep_rxpath;
+  end record;
+  ------------------------------------
+
+  constant c_epevents_sz  : integer := 29;  --how many events the endpoint generates
+
+  component xwr_endpoint
+    generic (
+      g_interface_mode        : t_wishbone_interface_mode      := CLASSIC;
+      g_address_granularity   : t_wishbone_address_granularity := WORD;
+      g_simulation            : boolean                        := false;
+      g_pcs_16bit             : boolean                        := false;
+      g_records_for_phy       : boolean                        := false;
+      g_tx_force_gap_length   : integer                        := 0;
+      g_tx_runt_padding       : boolean                        := false;
+      g_rx_buffer_size        : integer                        := 1024;
+      g_with_rx_buffer        : boolean                        := true;
+      g_with_flow_control     : boolean                        := true;
+      g_with_timestamper      : boolean                        := true;
+      g_with_dpi_classifier   : boolean                        := false;
+      g_with_vlans            : boolean                        := false;
+      g_with_rtu              : boolean                        := false;
+      g_with_leds             : boolean                        := false;
+      g_with_dmtd             : boolean                        := false;
+      g_with_packet_injection : boolean                        := false;
+      g_use_new_rxcrc         :	boolean                        := false;
+      g_use_new_txcrc         :	boolean                        := false;
+      g_with_stop_traffic     : boolean                        := false);
+    port (
+      clk_ref_i            : in  std_logic;
+      clk_sys_i            : in  std_logic;
+      clk_dmtd_i           : in  std_logic                     := '0';
+      rst_sys_n_i          : in  std_logic;
+      rst_ref_n_i          : in  std_logic;
+      rst_dmtd_n_i         : in  std_logic;
+      rst_txclk_n_i        : in  std_logic;
+      rst_rxclk_n_i        : in  std_logic;
+      pps_csync_p1_i       : in  std_logic                     := '0';
+      pps_valid_i          : in  std_logic                     := '1';
+      phy_rst_o            : out std_logic;
+      phy_loopen_o         : out std_logic;
+      phy_loopen_vec_o     : out std_logic_vector(2 downto 0);
+      phy_tx_prbs_sel_o    : out std_logic_vector(2 downto 0);
+      phy_sfp_tx_fault_i   : in  std_logic                     := '0';
+      phy_sfp_los_i        : in  std_logic                     := '0';
+      phy_sfp_tx_disable_o : out std_logic;
+      phy_rdy_i            : in  std_logic;
+      phy_ref_clk_i        : in  std_logic                     := '0';
+      phy_tx_data_o        : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
+      phy_tx_k_o           : out std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
+      phy_tx_disparity_i   : in  std_logic                     := '0';
+      phy_tx_enc_err_i     : in  std_logic                     := '0';
+      phy_rx_data_i        : in  std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
+      phy_rx_clk_i         : in  std_logic                     := '0';
+      phy_rx_k_i           : in  std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
+      phy_rx_enc_err_i     : in  std_logic                     := '0';
+      phy_rx_bitslide_i    : in  std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
+      phy8_o               : out t_phy_8bits_from_wrc;
+      phy8_i               : in  t_phy_8bits_to_wrc  := c_dummy_phy8_to_wrc;
+      phy16_o              : out t_phy_16bits_from_wrc;
+      phy16_i              : in  t_phy_16bits_to_wrc := c_dummy_phy16_to_wrc;
+      gmii_tx_clk_i        : in  std_logic                     := '0';
+      gmii_txd_o           : out std_logic_vector(7 downto 0);
+      gmii_tx_en_o         : out std_logic;
+      gmii_tx_er_o         : out std_logic;
+      gmii_rx_clk_i        : in  std_logic                     := '0';
+      gmii_rxd_i           : in  std_logic_vector(7 downto 0)  := x"00";
+      gmii_rx_er_i         : in  std_logic                     := '0';
+      gmii_rx_dv_i         : in  std_logic                     := '0';
+      src_o                : out t_wrf_source_out;
+      src_i                : in  t_wrf_source_in;
+      snk_o                : out t_wrf_sink_out;
+      snk_i                : in  t_wrf_sink_in;
+      txtsu_port_id_o      : out std_logic_vector(4 downto 0);
+      txtsu_frame_id_o     : out std_logic_vector(16 -1 downto 0);
+      txtsu_ts_value_o     : out std_logic_vector(28 + 4 - 1 downto 0);
+      txtsu_ts_incorrect_o : out std_logic;
+      txtsu_stb_o          : out std_logic;
+      txtsu_ack_i          : in  std_logic                     := '1';
+      rtu_full_i           : in  std_logic                     := '0';
+      rtu_almost_full_i    : in  std_logic                     := '0';
+      rtu_rq_strobe_p1_o   : out std_logic;
+      rtu_rq_abort_o       : out std_logic;
+      rtu_rq_smac_o        : out std_logic_vector(48 - 1 downto 0);
+      rtu_rq_dmac_o        : out std_logic_vector(48 - 1 downto 0);
+      rtu_rq_vid_o         : out std_logic_vector(12 - 1 downto 0);
+      rtu_rq_has_vid_o     : out std_logic;
+      rtu_rq_prio_o        : out std_logic_vector(3 - 1 downto 0);
+      rtu_rq_has_prio_o    : out std_logic;
+      wb_i                 : in  t_wishbone_slave_in;
+      wb_o                 : out t_wishbone_slave_out;
+      pfilter_pclass_o     : out   std_logic_vector(7 downto 0);
+      pfilter_drop_o       : out   std_logic;
+      pfilter_done_o       : out   std_logic;
+      fc_tx_pause_req_i    : in std_logic := '0';
+      fc_tx_pause_delay_i  : in std_logic_vector(15 downto 0) := x"0000";
+      fc_tx_pause_ready_o  : out std_logic;
+      fc_rx_pause_start_p_o     : out std_logic;
+      fc_rx_pause_quanta_o      : out std_logic_vector(15 downto 0);
+      fc_rx_pause_prio_mask_o   : out std_logic_vector(7 downto 0);      
+      fc_rx_buffer_occupation_o : out std_logic_vector(7 downto 0);
+      inject_req_i         : in  std_logic                     := '0';
+      inject_ready_o       : out std_logic;
+      inject_packet_sel_i  : in  std_logic_vector(2 downto 0)  := "000";
+      inject_user_value_i  : in  std_logic_vector(15 downto 0) := x"0000";
+      rmon_events_o        : out std_logic_vector(c_epevents_sz-1 downto 0);
+      txts_o               : out std_logic; 		-- 2013-Nov-28 peterj added for debugging/calibration
+      rxts_o               : out std_logic; 		-- 2013-Nov-28 peterj added for debugging/calibration
+      led_link_o           : out std_logic;
+      led_act_o            : out std_logic;
+      link_kill_i          : in  std_logic                     := '0';
+      link_up_o            : out std_logic;
+      stop_traffic_i       : in std_logic := '0';
+      dbg_tx_pcs_wr_count_o     : out std_logic_vector(5+4 downto 0);
+      dbg_tx_pcs_rd_count_o     : out std_logic_vector(5+4 downto 0);
+      nice_dbg_o  : out t_dbg_ep);
+  end component;
+
+  component wr_endpoint
+    generic (
+      g_interface_mode        : t_wishbone_interface_mode      := CLASSIC;
+      g_address_granularity   : t_wishbone_address_granularity := WORD;
+      g_tx_force_gap_length   : integer                        := 0;
+      g_tx_runt_padding       : boolean                        := false;
+      g_simulation            : boolean                        := false;
+      g_pcs_16bit             : boolean                        := true;
+      g_rx_buffer_size        : integer                        := 1024;
+      g_with_rx_buffer        : boolean                        := true;
+      g_with_flow_control     : boolean                        := true;
+      g_with_timestamper      : boolean                        := true;
+      g_with_dpi_classifier   : boolean                        := false;
+      g_with_vlans            : boolean                        := true;
+      g_with_rtu              : boolean                        := true;
+      g_with_leds             : boolean                        := true;
+      g_with_dmtd             : boolean                        := false;
+      g_with_packet_injection : boolean                        := false;
+      g_use_new_rxcrc         : boolean                        := false;
+      g_use_new_txcrc         : boolean                        := false;
+      g_with_stop_traffic     : boolean                        := false);
+    port (
+      clk_ref_i            : in  std_logic;
+      clk_sys_i            : in  std_logic;
+      clk_dmtd_i           : in  std_logic;
+      rst_sys_n_i          : in  std_logic;
+      rst_ref_n_i          : in  std_logic;
+      rst_dmtd_n_i         : in  std_logic;
+      rst_txclk_n_i        : in  std_logic;
+      rst_rxclk_n_i        : in  std_logic;
+      pps_csync_p1_i       : in  std_logic;
+      pps_valid_i          : in  std_logic                     := '1';
+      phy_rst_o            : out std_logic;
+      phy_loopen_o         : out std_logic;
+      phy_loopen_vec_o     : out std_logic_vector(2 downto 0);
+      phy_tx_prbs_sel_o    : out std_logic_vector(2 downto 0);
+      phy_sfp_tx_fault_i   : in  std_logic                     := '0';
+      phy_sfp_los_i        : in  std_logic                     := '0';
+      phy_sfp_tx_disable_o : out std_logic;
+      phy_rdy_i            : in  std_logic;
+      phy_ref_clk_i        : in  std_logic;
+      phy_tx_data_o        : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
+      phy_tx_k_o           : out std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
+      phy_tx_disparity_i   : in  std_logic;
+      phy_tx_enc_err_i     : in  std_logic;
+      phy_rx_data_i        : in  std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
+      phy_rx_clk_i         : in  std_logic;
+      phy_rx_k_i           : in  std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
+      phy_rx_enc_err_i     : in  std_logic;
+      phy_rx_bitslide_i    : in  std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
+      gmii_tx_clk_i        : in  std_logic	 									 := '0';
+      gmii_txd_o           : out std_logic_vector(7 downto 0)  := x"00";
+      gmii_tx_en_o         : out std_logic                     := '0';
+      gmii_tx_er_o         : out std_logic                     := '0';
+      gmii_rx_clk_i        : in  std_logic										 := '0';
+      gmii_rxd_i           : in  std_logic_vector(7 downto 0)  := x"00";
+      gmii_rx_er_i         : in  std_logic := '0';
+      gmii_rx_dv_i         : in  std_logic := '0';
+      src_dat_o            : out std_logic_vector(15 downto 0);
+      src_adr_o            : out std_logic_vector(1 downto 0);
+      src_sel_o            : out std_logic_vector(1 downto 0);
+      src_cyc_o            : out std_logic;
+      src_stb_o            : out std_logic;
+      src_we_o             : out std_logic;
+      src_stall_i          : in  std_logic;
+      src_ack_i            : in  std_logic;
+      src_err_i            : in  std_logic;
+      snk_dat_i            : in  std_logic_vector(15 downto 0);
+      snk_adr_i            : in  std_logic_vector(1 downto 0);
+      snk_sel_i            : in  std_logic_vector(1 downto 0);
+      snk_cyc_i            : in  std_logic;
+      snk_stb_i            : in  std_logic;
+      snk_we_i             : in  std_logic;
+      snk_stall_o          : out std_logic;
+      snk_ack_o            : out std_logic;
+      snk_err_o            : out std_logic;
+      snk_rty_o            : out std_logic;
+      txtsu_port_id_o      : out std_logic_vector(4 downto 0);
+      txtsu_frame_id_o     : out std_logic_vector(16 -1 downto 0);
+      txtsu_ts_value_o     : out std_logic_vector(28 + 4 - 1 downto 0);
+      txtsu_ts_incorrect_o : out std_logic;
+      txtsu_stb_o          : out std_logic;
+      txtsu_ack_i          : in  std_logic;
+      rtu_full_i           : in  std_logic;
+      rtu_almost_full_i    : in  std_logic;
+      rtu_rq_strobe_p1_o   : out std_logic;
+      rtu_rq_abort_o       : out std_logic;
+      rtu_rq_smac_o        : out std_logic_vector(48 - 1 downto 0);
+      rtu_rq_dmac_o        : out std_logic_vector(48 - 1 downto 0);
+      rtu_rq_vid_o         : out std_logic_vector(12 - 1 downto 0);
+      rtu_rq_has_vid_o     : out std_logic;
+      rtu_rq_prio_o        : out std_logic_vector(3 - 1 downto 0);
+      rtu_rq_has_prio_o    : out std_logic;
+      wb_cyc_i             : in  std_logic;
+      wb_stb_i             : in  std_logic;
+      wb_we_i              : in  std_logic;
+      wb_sel_i             : in  std_logic_vector(3 downto 0);
+      wb_adr_i             : in  std_logic_vector(7 downto 0);
+      wb_dat_i             : in  std_logic_vector(31 downto 0);
+      wb_dat_o             : out std_logic_vector(31 downto 0);
+      wb_ack_o             : out std_logic;
+      wb_stall_o           : out std_logic;
+      pfilter_pclass_o     : out   std_logic_vector(7 downto 0);
+      pfilter_drop_o       : out   std_logic;
+      pfilter_done_o       : out   std_logic;
+      fc_tx_pause_req_i    : in std_logic := '0';
+      fc_tx_pause_delay_i  : in std_logic_vector(15 downto 0) := x"0000";
+      fc_tx_pause_ready_o  : out std_logic;
+      fc_rx_pause_start_p_o     : out std_logic;
+      fc_rx_pause_quanta_o      : out std_logic_vector(15 downto 0);
+      fc_rx_pause_prio_mask_o   : out std_logic_vector(7 downto 0);     
+      fc_rx_buffer_occupation_o : out std_logic_vector(7 downto 0);
+      inject_req_i         : in  std_logic                     := '0';
+      inject_ready_o       : out std_logic;
+      inject_packet_sel_i  : in  std_logic_vector(2 downto 0)  := "000";
+      inject_user_value_i  : in  std_logic_vector(15 downto 0) := x"0000";
+      rmon_events_o        : out std_logic_vector(c_epevents_sz-1 downto 0);
+      txts_o               : out std_logic; 		-- 2013-Nov-28 peterj added for debugging/calibration
+      rxts_o               : out std_logic; 		-- 2013-Nov-28 peterj added for debugging/calibration
+      led_link_o           : out std_logic;
+      led_act_o            : out std_logic;
+      link_kill_i          : in  std_logic                     := '0';
+      link_up_o            : out std_logic;
+      stop_traffic_i       : in std_logic := '0';
+      dbg_tx_pcs_wr_count_o     : out std_logic_vector(5+4 downto 0);
+      dbg_tx_pcs_rd_count_o     : out std_logic_vector(5+4 downto 0);
+      nice_dbg_o  : out t_dbg_ep);
+  end component;
+  
+  constant c_xwr_endpoint_sdb : t_sdb_device := (
+    abi_class     => x"0000",              -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"01",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"7",                 -- 8/16/32-bit port granularity
+    sdb_component => (
+      addr_first  => x"0000000000000000",
+      addr_last   => x"00000000000000ff",
+      product     => (
+        vendor_id => x"000000000000CE42",  -- CERN
+        device_id => x"650c2d4f",
+        version   => x"00000002",
+        date      => x"20121116",
+        name      => "WR-Endpoint        ")));
+
+end endpoint_pkg;
+
+package body endpoint_pkg is
+
+  function f_pcs_data_width(pcs_16 : boolean)
+    return integer is
+  begin
+    if (pcs_16) then
+      return 16;
+    else
+      return 8;
+    end if;
+  end function;
+
+  function f_pcs_k_width(pcs_16 : boolean)
+    return integer is
+  begin
+    if (pcs_16) then
+      return 2;
+    else
+      return 1;
+    end if;
+  end function;
+
+  function f_pcs_bts_width(pcs_16 : boolean)
+    return integer is
+  begin
+    if (pcs_16) then
+      return 5;
+    else
+      return 4;
+    end if;
+  end function;
+
+  function f_pcs_clock_rate(pcs_16 : boolean)
+    return integer is
+  begin
+    if (pcs_16) then
+      return 62500000;
+    else
+      return 125000000;
+    end if;
+  end function;
+
+end package body endpoint_pkg;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/endpoint_private_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/endpoint_private_pkg.vhd
new file mode 100644
index 000000000..3191e71cb
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/endpoint_private_pkg.vhd
@@ -0,0 +1,930 @@
+-------------------------------------------------------------------------------
+-- Title      : Private constants/types/functions package
+-- Project    : White Rabbit MAC/Endpoint
+-------------------------------------------------------------------------------
+-- File       : endpoint_private_pkg.vhd
+-- Author     : Tomasz Włostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2010-11-18
+-- Last update: 2017-02-20
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Endpoint private definitions:
+-- - 8B10B codes
+-- - VLAN control registers
+-- - Data types: internal fabric, RMON, RTU
+-- - 18-bit FIFO fabric packing/unpacking functions
+-- - Endpoint subcomponents declarations
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2009-2011 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.ep_wbgen2_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.endpoint_pkg.all;
+use work.genram_pkg.all;
+
+package endpoint_private_pkg is
+
+  -- special/control characters
+  constant c_k28_5 : std_logic_vector(7 downto 0) := "10111100";  -- bc
+  constant c_k23_7 : std_logic_vector(7 downto 0) := "11110111";  -- f7
+  constant c_k27_7 : std_logic_vector(7 downto 0) := "11111011";  -- fb
+  constant c_k29_7 : std_logic_vector(7 downto 0) := "11111101";  -- fd
+  constant c_k30_7 : std_logic_vector(7 downto 0) := "11111110";  -- fe
+  constant c_k28_7 : std_logic_vector(7 downto 0) := "11111100";  -- fc
+  constant c_d21_5 : std_logic_vector(7 downto 0) := "10110101";  -- b5
+
+  constant c_d2_2          : std_logic_vector(7 downto 0) := "01000010";  -- 42
+  constant c_d5_6          : std_logic_vector(7 downto 0) := "11000101";  -- c5
+  constant c_d16_2         : std_logic_vector(7 downto 0) := "01010000";  -- 50
+  constant c_preamble_char : std_logic_vector(7 downto 0) := "01010101";
+  constant c_preamble_sfd  : std_logic_vector(7 downto 0) := "11010101";
+
+  constant c_QMODE_PORT_ACCESS        : std_logic_vector(1 downto 0) := "00";
+  constant c_QMODE_PORT_TRUNK         : std_logic_vector(1 downto 0) := "01";
+  constant c_QMODE_PORT_UNQUALIFIED   : std_logic_vector(1 downto 0) := "11";
+  constant c_QMODE_PORT_VLAN_DISABLED : std_logic_vector(1 downto 0) := "10";
+
+  -- fixme: remove these along with the non-WB version of the endpoint
+  constant c_wrsw_ctrl_none      : std_logic_vector(4 - 1 downto 0) := x"0";
+  constant c_wrsw_ctrl_dst_mac   : std_logic_vector(4 - 1 downto 0) := x"1";
+  constant c_wrsw_ctrl_src_mac   : std_logic_vector(4 - 1 downto 0) := x"2";
+  constant c_wrsw_ctrl_ethertype : std_logic_vector(4 - 1 downto 0) := x"3";
+  constant c_wrsw_ctrl_vid_prio  : std_logic_vector(4 - 1 downto 0) := x"4";
+  constant c_wrsw_ctrl_tx_oob    : std_logic_vector(4 - 1 downto 0) := x"5";
+  constant c_wrsw_ctrl_rx_oob    : std_logic_vector(4 - 1 downto 0) := x"6";
+  constant c_wrsw_ctrl_payload   : std_logic_vector(4 - 1 downto 0) := x"7";
+  constant c_wrsw_ctrl_fcs       : std_logic_vector(4 - 1 downto 0) := x"8";
+
+  type t_ep_internal_rtu_request is record
+    smac     : std_logic_vector(47 downto 0);
+    dmac     : std_logic_vector(47 downto 0);
+    vid      : std_logic_vector(11 downto 0);
+    prio     : std_logic_vector(2 downto 0);
+    has_vid  : std_logic;
+    has_prio : std_logic;
+    hash     : std_logic_vector(15 downto 0);
+  end record;
+
+  type t_rmon_triggers is record
+    rx_sync_lost           : std_logic;
+    rx_invalid_code        : std_logic;
+    rx_overrun             : std_logic;
+    rx_crc_err             : std_logic;
+    rx_ok                  : std_logic;
+    rx_pfilter_drop        : std_logic;
+    rx_runt                : std_logic;
+    rx_giant               : std_logic;
+    rx_pause               : std_logic;
+    rx_pcs_err             : std_logic;
+    rx_buffer_overrun      : std_logic;
+    rx_rtu_overrun         : std_logic;
+    rx_path_timing_failure : std_logic;
+    tx_pause               : std_logic;
+    tx_underrun            : std_logic;
+    rx_pclass              : std_logic_vector(7 downto 0); -- packet class (from filter)
+    rx_tclass              : std_logic_vector(7 downto 0); -- traffic class (priority)
+    tx_frame               : std_logic;
+    rx_frame               : std_logic;
+    rx_drop_at_rtu_full    : std_logic;
+  end record;
+
+  component ep_1000basex_pcs
+    generic (
+      g_simulation : boolean;
+      g_16bit      : boolean);
+    port (
+      rst_sys_n_i                   : in  std_logic;
+      rst_txclk_n_i                 : in  std_logic;
+      rst_rxclk_n_i                 : in  std_logic;
+      clk_sys_i                     : in  std_logic;
+      rxpcs_fab_o                   : out t_ep_internal_fabric;
+      rxpcs_fifo_almostfull_i       : in  std_logic;
+      rxpcs_busy_o                  : out std_logic;
+      rxpcs_timestamp_trigger_p_a_o : out std_logic;
+      rxpcs_timestamp_i             : in  std_logic_vector(31 downto 0);
+      rxpcs_timestamp_stb_i         : in  std_logic;
+      rxpcs_timestamp_valid_i       : in  std_logic;
+      txpcs_fab_i                   : in  t_ep_internal_fabric;
+      txpcs_error_o                 : out std_logic;
+      txpcs_busy_o                  : out std_logic;
+      txpcs_dreq_o                  : out std_logic;
+      txpcs_timestamp_trigger_p_a_o : out std_logic;
+      link_ok_o                     : out std_logic;
+      link_ctr_i                    : in  std_logic := '1';
+      serdes_rst_o                  : out std_logic;
+      serdes_loopen_o               : out std_logic;
+      serdes_loopen_vec_o           : out std_logic_vector(2 downto 0);
+      serdes_tx_prbs_sel_o          : out std_logic_vector(2 downto 0);
+      serdes_sfp_tx_fault_i         : in  std_logic;
+      serdes_sfp_los_i              : in  std_logic;
+      serdes_sfp_tx_disable_o       : out std_logic;
+      serdes_rdy_i                  : in  std_logic;
+      serdes_tx_clk_i               : in  std_logic;
+      serdes_tx_data_o              : out std_logic_vector(f_pcs_data_width(g_16bit)-1 downto 0);
+      serdes_tx_k_o                 : out std_logic_vector(f_pcs_k_width(g_16bit)-1 downto 0);
+      serdes_tx_disparity_i         : in  std_logic;
+      serdes_tx_enc_err_i           : in  std_logic;
+      serdes_rx_clk_i               : in  std_logic;
+      serdes_rx_data_i              : in  std_logic_vector(f_pcs_data_width(g_16bit)-1 downto 0);
+      serdes_rx_k_i                 : in  std_logic_vector(f_pcs_k_width(g_16bit)-1 downto 0);
+      serdes_rx_enc_err_i           : in  std_logic;
+      serdes_rx_bitslide_i          : in  std_logic_vector(f_pcs_bts_width(g_16bit)-1 downto 0);
+      rmon_o                        : out t_rmon_triggers;
+      mdio_addr_i                   : in  std_logic_vector(15 downto 0);
+      mdio_data_i                   : in  std_logic_vector(15 downto 0);
+      mdio_data_o                   : out std_logic_vector(15 downto 0);
+      mdio_stb_i                    : in  std_logic;
+      mdio_rw_i                     : in  std_logic;
+      mdio_ready_o                  : out std_logic;
+      dbg_tx_pcs_wr_count_o     : out std_logic_vector(5+4 downto 0);
+      dbg_tx_pcs_rd_count_o     : out std_logic_vector(5+4 downto 0);
+      nice_dbg_o  : out t_dbg_ep_pcs);
+  end component;
+
+  component ep_tx_pcs_8bit
+    port (
+      rst_n_i                 : in  std_logic;
+      rst_txclk_n_i           : in  std_logic;
+      clk_sys_i               : in  std_logic;
+      pcs_fab_i               : in  t_ep_internal_fabric;
+      pcs_error_o             : out std_logic;
+      pcs_busy_o              : out std_logic;
+      pcs_dreq_o              : out std_logic;
+      mdio_mcr_reset_i        : in  std_logic;
+      mdio_mcr_pdown_i        : in  std_logic;
+      mdio_wr_spec_tx_cal_i   : in  std_logic;
+      an_tx_en_i              : in  std_logic;
+      an_tx_val_i             : in  std_logic_vector(15 downto 0);
+      timestamp_trigger_p_a_o : out std_logic;
+      rmon_tx_underrun        : out std_logic;
+      phy_tx_clk_i            : in  std_logic;
+      phy_tx_data_o           : out std_logic_vector(7 downto 0);
+      phy_tx_k_o              : out std_logic;
+      phy_tx_disparity_i      : in  std_logic;
+      phy_tx_enc_err_i        : in  std_logic);
+  end component;
+
+  component ep_tx_pcs_16bit
+    port (
+      rst_n_i                 : in  std_logic;
+      rst_txclk_n_i           : in  std_logic;
+      clk_sys_i               : in  std_logic;
+      pcs_fab_i               : in  t_ep_internal_fabric;
+      pcs_error_o             : out std_logic;
+      pcs_busy_o              : out std_logic;
+      pcs_dreq_o              : out std_logic;
+      mdio_mcr_reset_i        : in  std_logic;
+      mdio_mcr_pdown_i        : in  std_logic;
+      mdio_wr_spec_tx_cal_i   : in  std_logic;
+      an_tx_en_i              : in  std_logic;
+      an_tx_val_i             : in  std_logic_vector(15 downto 0);
+      timestamp_trigger_p_a_o : out std_logic;
+      rmon_tx_underrun        : out std_logic;
+      phy_tx_clk_i            : in  std_logic;
+      phy_tx_data_o           : out std_logic_vector(15 downto 0);
+      phy_tx_k_o              : out std_logic_vector(1 downto 0);
+      phy_tx_disparity_i      : in  std_logic;
+      phy_tx_enc_err_i        : in  std_logic;
+      dbg_wr_count_o     : out std_logic_vector(5+4 downto 0);
+      dbg_rd_count_o     : out std_logic_vector(5+4 downto 0));
+  end component;
+
+  component ep_rx_pcs_8bit
+    generic (
+      g_simulation : boolean);
+    port (
+      clk_sys_i                  : in  std_logic;
+      rst_n_i                    : in  std_logic;
+      rst_rxclk_n_i              : in  std_logic;
+      pcs_fifo_almostfull_i      : in  std_logic;
+      pcs_busy_o                 : out std_logic;
+      pcs_fab_o                  : out t_ep_internal_fabric;
+      timestamp_trigger_p_a_o    : out std_logic;  -- strobe for RX timestamping
+      timestamp_i                : in  std_logic_vector(31 downto 0);
+      timestamp_stb_i            : in  std_logic;
+      timestamp_valid_i          : in  std_logic;
+      phy_rdy_i                  : in  std_logic;
+      phy_rx_clk_i               : in  std_logic;
+      phy_rx_data_i              : in  std_logic_vector(7 downto 0);
+      phy_rx_k_i                 : in  std_logic;
+      phy_rx_enc_err_i           : in  std_logic;
+      mdio_mcr_reset_i           : in  std_logic;
+      mdio_mcr_pdown_i           : in  std_logic;
+      mdio_wr_spec_cal_crst_i    : in  std_logic;
+      mdio_wr_spec_rx_cal_stat_o : out std_logic;
+      synced_o                   : out std_logic;
+      sync_lost_o                : out std_logic;
+      an_rx_en_i                 : in  std_logic;
+      an_rx_val_o                : out std_logic_vector(15 downto 0);
+      an_rx_valid_o              : out std_logic;
+      an_idle_match_o            : out std_logic;
+      rmon_rx_overrun            : out std_logic;
+      rmon_rx_inv_code           : out std_logic;
+      rmon_rx_sync_lost          : out std_logic);
+  end component;
+
+  component ep_rx_pcs_16bit
+    generic (
+      g_simulation : boolean);
+    port (
+      clk_sys_i                  : in  std_logic;
+      rst_n_i                    : in  std_logic;
+      rst_rxclk_n_i              : in  std_logic;
+      pcs_fifo_almostfull_i      : in  std_logic;
+      pcs_busy_o                 : out std_logic;
+      pcs_fab_o                  : out t_ep_internal_fabric;
+      timestamp_trigger_p_a_o    : out std_logic;  -- strobe for RX timestamping
+      timestamp_i                : in  std_logic_vector(31 downto 0);
+      timestamp_stb_i            : in  std_logic;
+      timestamp_valid_i          : in  std_logic;
+      phy_rdy_i                  : in  std_logic;
+      phy_rx_clk_i               : in  std_logic;
+      phy_rx_data_i              : in  std_logic_vector(15 downto 0);
+      phy_rx_k_i                 : in  std_logic_vector(1 downto 0);
+      phy_rx_enc_err_i           : in  std_logic;
+      mdio_mcr_reset_i           : in  std_logic;
+      mdio_mcr_pdown_i           : in  std_logic;
+      mdio_wr_spec_cal_crst_i    : in  std_logic;
+      mdio_wr_spec_rx_cal_stat_o : out std_logic;
+      synced_o                   : out std_logic;
+      sync_lost_o                : out std_logic;
+      an_rx_en_i                 : in  std_logic;
+      an_rx_val_o                : out std_logic_vector(15 downto 0);
+      an_rx_valid_o              : out std_logic;
+      an_idle_match_o            : out std_logic;
+      rmon_rx_overrun            : out std_logic;
+      rmon_rx_inv_code           : out std_logic;
+      rmon_rx_sync_lost          : out std_logic;
+      nice_dbg_o                 : out t_dbg_ep_rxpcs);
+  end component;
+
+  component ep_autonegotiation
+    generic (
+      g_simulation : boolean);
+    port (
+      clk_sys_i               : in  std_logic;
+      rst_n_i                 : in  std_logic;
+      pcs_synced_i            : in  std_logic;
+      pcs_los_i               : in  std_logic;
+      pcs_link_ok_o           : out std_logic;
+      an_idle_match_i         : in  std_logic;
+      an_rx_en_o              : out std_logic;
+      an_rx_val_i             : in  std_logic_vector(15 downto 0);
+      an_rx_valid_i           : in  std_logic;
+      an_tx_en_o              : out std_logic;
+      an_tx_val_o             : out std_logic_vector(15 downto 0);
+      mdio_mcr_anrestart_i    : in  std_logic;
+      mdio_mcr_anenable_i     : in  std_logic;
+      mdio_msr_anegcomplete_o : out std_logic;
+      mdio_advertise_pause_i  : in  std_logic_vector(1 downto 0);
+      mdio_advertise_rfault_i : in  std_logic_vector(1 downto 0);
+      mdio_lpa_full_o         : out std_logic;
+      mdio_lpa_half_o         : out std_logic;
+      mdio_lpa_pause_o        : out std_logic_vector(1 downto 0);
+      mdio_lpa_rfault_o       : out std_logic_vector(1 downto 0);
+      mdio_lpa_lpack_o        : out std_logic;
+      mdio_lpa_npage_o        : out std_logic);
+  end component;
+
+  component ep_pcs_tbi_mdio_wb
+    port (
+      rst_n_i                    : in  std_logic;
+      clk_sys_i                  : in  std_logic;
+      wb_adr_i                   : in  std_logic_vector(4 downto 0);
+      wb_dat_i                   : in  std_logic_vector(31 downto 0);
+      wb_dat_o                   : out std_logic_vector(31 downto 0);
+      wb_cyc_i                   : in  std_logic;
+      wb_sel_i                   : in  std_logic_vector(3 downto 0);
+      wb_stb_i                   : in  std_logic;
+      wb_we_i                    : in  std_logic;
+      wb_ack_o                   : out std_logic;
+      wb_stall_o                 : out std_logic;
+      tx_clk_i                   : in  std_logic;
+      rx_clk_i                   : in  std_logic;
+      mdio_mcr_uni_en_o          : out std_logic;
+      mdio_mcr_anrestart_o       : out std_logic;
+      mdio_mcr_pdown_o           : out std_logic;
+      mdio_mcr_anenable_o        : out std_logic;
+      mdio_mcr_reset_o           : out std_logic;
+      mdio_mcr_loopback_o        : out std_logic;
+      mdio_msr_lstatus_i         : in  std_logic;
+      lstat_read_notify_o        : out std_logic;
+      mdio_msr_rfault_i          : in  std_logic;
+      mdio_msr_anegcomplete_i    : in  std_logic;
+      mdio_advertise_pause_o     : out std_logic_vector(1 downto 0);
+      mdio_advertise_rfault_o    : out std_logic_vector(1 downto 0);
+      mdio_lpa_full_i            : in  std_logic;
+      mdio_lpa_half_i            : in  std_logic;
+      mdio_lpa_pause_i           : in  std_logic_vector(1 downto 0);
+      mdio_lpa_rfault_i          : in  std_logic_vector(1 downto 0);
+      mdio_lpa_lpack_i           : in  std_logic;
+      mdio_lpa_npage_i           : in  std_logic;
+      mdio_wr_spec_tx_cal_o      : out std_logic;
+      mdio_wr_spec_rx_cal_stat_i : in  std_logic;
+      mdio_wr_spec_cal_crst_o    : out std_logic;
+      mdio_wr_spec_bslide_i      : in  std_logic_vector(4 downto 0);
+      mdio_ectrl_lpbck_vec_o       : out std_logic_vector(2 downto 0);
+      mdio_ectrl_sfp_tx_fault_i    : in  std_logic;
+      mdio_ectrl_sfp_loss_i        : in  std_logic;
+      mdio_ectrl_sfp_tx_disable_o  : out std_logic;
+      mdio_ectrl_tx_prbs_sel_o     : out std_logic_vector(2 downto 0));
+  end component;
+
+  component ep_tx_header_processor
+    generic (
+      g_with_packet_injection : boolean;
+      g_with_timestamper      : boolean;
+      g_force_gap_length      : integer;
+      g_runt_padding          : boolean);
+    port (
+      clk_sys_i              : in  std_logic;
+      rst_n_i                : in  std_logic;
+      src_fab_o              : out t_ep_internal_fabric;
+      src_dreq_i             : in  std_logic;
+      pcs_busy_i             : in  std_logic;
+      pcs_error_i            : in  std_logic;
+      wb_snk_i               : in  t_wrf_sink_in;
+      wb_snk_o               : out t_wrf_sink_out;
+      fc_pause_req_i         : in  std_logic;
+      fc_pause_delay_i       : in  std_logic_vector(15 downto 0);
+      fc_pause_ready_o       : out std_logic;
+      fc_flow_enable_i       : in  std_logic;
+      txtsu_port_id_o        : out std_logic_vector(4 downto 0);
+      txtsu_fid_o            : out std_logic_vector(16 -1 downto 0);
+      txtsu_ts_value_o       : out std_logic_vector(28 + 4 - 1 downto 0);
+      txtsu_ts_incorrect_o   : out std_logic;
+      txtsu_stb_o            : out std_logic;
+      txtsu_ack_i            : in  std_logic;
+      txts_timestamp_i       : in  std_logic_vector(31 downto 0);
+      txts_timestamp_valid_i : in  std_logic;
+      ep_ctrl_i              : in std_logic;
+      regs_i                 : in  t_ep_out_registers);
+  end component;
+
+  component ep_tx_vlan_unit
+    port (
+      clk_sys_i         : in  std_logic;
+      rst_n_i           : in  std_logic;
+      snk_fab_i         : in  t_ep_internal_fabric;
+      snk_dreq_o        : out std_logic;
+      src_fab_o         : out t_ep_internal_fabric;
+      src_dreq_i        : in  std_logic;
+      inject_mem_addr_i : in  std_logic_vector(9 downto 0);
+      inject_mem_data_o : out std_logic_vector(17 downto 0);
+      uram_offset_wr_i  : in  std_logic;
+      uram_offset_i     : in  std_logic_vector(9 downto 0);
+      uram_data_i       : in  std_logic_vector(17 downto 0));
+  end component;
+  
+  component ep_timestamping_unit
+    generic (
+      g_timestamp_bits_r : natural;
+      g_timestamp_bits_f : natural;
+      g_ref_clock_rate   : integer);
+    port (
+      clk_ref_i                  : in  std_logic;
+      clk_sys_i                  : in  std_logic;
+      clk_rx_i                   : in  std_logic;
+      rst_n_rx_i                 : in  std_logic;
+      rst_n_ref_i                : in  std_logic;
+      rst_n_sys_i                : in  std_logic;
+      pps_csync_p1_i             : in  std_logic;
+      pps_valid_i                : in  std_logic;
+      tx_timestamp_trigger_p_a_i : in  std_logic;
+      rx_timestamp_trigger_p_a_i : in  std_logic;
+      rxts_timestamp_o           : out std_logic_vector(31 downto 0);
+      rxts_timestamp_stb_o       : out std_logic;
+      rxts_timestamp_valid_o     : out std_logic;
+      txts_timestamp_o           : out std_logic_vector(31 downto 0);
+      txts_timestamp_stb_o       : out std_logic;
+      txts_timestamp_valid_o     : out std_logic;
+      txts_o                     : out std_logic; 		-- 2013-Nov-28 peterj added for debugging/calibration
+      rxts_o                     : out std_logic; 		-- 2013-Nov-28 peterj added for debugging/calibration
+      regs_i                     : in  t_ep_out_registers;
+      regs_o                     : out t_ep_in_registers);
+  end component;
+
+  component ep_flow_control
+    port (
+      clk_sys_i          : in  std_logic;
+      rst_n_i            : in  std_logic;
+      rx_pause_p1_i      : in  std_logic;
+      rx_pause_delay_i   : in  std_logic_vector(15 downto 0);
+      tx_pause_o         : out std_logic;
+      tx_pause_delay_o   : out std_logic_vector(15 downto 0);
+      tx_pause_ack_i     : in  std_logic;
+      tx_flow_enable_o   : out std_logic;
+      rx_buffer_used_i   : in  std_logic_vector(7 downto 0);
+      ep_fcr_txpause_i   : in  std_logic;
+      ep_fcr_rxpause_i   : in  std_logic;
+      ep_fcr_tx_thr_i    : in  std_logic_vector(7 downto 0);
+      ep_fcr_tx_quanta_i : in  std_logic_vector(15 downto 0);
+      rmon_rcvd_pause_o  : out std_logic;
+      rmon_sent_pause_o  : out std_logic);
+  end component;
+
+  component ep_wishbone_controller
+    port (
+      rst_n_i            : in  std_logic;
+      clk_sys_i          : in  std_logic;
+      wb_adr_i          : in  std_logic_vector(4 downto 0);
+      wb_dat_i          : in  std_logic_vector(31 downto 0);
+      wb_dat_o          : out std_logic_vector(31 downto 0);
+      wb_cyc_i           : in  std_logic;
+      wb_sel_i           : in  std_logic_vector(3 downto 0);
+      wb_stb_i           : in  std_logic;
+      wb_we_i            : in  std_logic;
+      wb_ack_o           : out std_logic;
+      wb_stall_o         : out std_logic;
+      tx_clk_i           : in  std_logic;
+      rx_clk_i           : in  std_logic;
+      regs_o             : out t_ep_out_registers;
+      regs_i             : in  t_ep_in_registers);
+  end component;
+
+  component ep_leds_controller
+    generic (
+      g_blink_period_log2 : integer);
+    port (
+      clk_sys_i   : in  std_logic;
+      rst_n_i     : in  std_logic;
+      dvalid_tx_i : in  std_logic;
+      dvalid_rx_i : in  std_logic;
+      link_ok_i   : in  std_logic;
+      led_link_o  : out std_logic;
+      led_act_o   : out std_logic);
+  end component;
+
+  component ep_tx_packet_injection
+    port (
+      clk_sys_i           : in  std_logic;
+      rst_n_i             : in  std_logic;
+      snk_fab_i           : in  t_ep_internal_fabric;
+      snk_dreq_o          : out std_logic;
+      src_fab_o           : out t_ep_internal_fabric;
+      src_dreq_i          : in  std_logic;
+      inject_req_i        : in  std_logic;
+      inject_ready_o      : out std_logic;
+      inject_packet_sel_i : in  std_logic_vector(2 downto 0);
+      inject_user_value_i : in  std_logic_vector(15 downto 0);
+      inject_mode_i       : in  std_logic_vector(1 downto 0);
+      mem_addr_o          : out std_logic_vector(9 downto 0);
+      mem_data_i          : in  std_logic_vector(17 downto 0));
+  end component;
+
+  component ep_rtu_header_extract
+    generic (
+      g_with_rtu : boolean);
+    port (
+      clk_sys_i        : in  std_logic;
+      rst_n_i          : in  std_logic;
+      snk_fab_i        : in  t_ep_internal_fabric;
+      snk_dreq_o       : out std_logic;
+      src_fab_o        : out t_ep_internal_fabric;
+      src_dreq_i       : in  std_logic;
+      mbuf_is_pause_i  : in  std_logic;
+      vlan_class_i     : in  std_logic_vector(2 downto 0);
+      vlan_vid_i       : in  std_logic_vector(11 downto 0);
+      vlan_tag_done_i  : in  std_logic;
+      vlan_is_tagged_i : in  std_logic;
+      rmon_drp_at_rtu_full_o: out std_logic;
+      rtu_rq_o         : out t_ep_internal_rtu_request;
+      rtu_full_i       : in  std_logic;
+      rtu_rq_abort_o   : out std_logic;
+      rtu_rq_valid_o   : out std_logic;
+      rxbuf_full_i     : in  std_logic);
+  end component;
+
+  component ep_rx_early_address_match
+    port (
+      clk_sys_i               : in  std_logic;
+      clk_rx_i                : in  std_logic;
+      rst_n_sys_i             : in  std_logic;
+      rst_n_rx_i              : in  std_logic;
+      snk_fab_i               : in  t_ep_internal_fabric;
+      src_fab_o               : out t_ep_internal_fabric;
+      match_done_o            : out std_logic;
+      match_is_hp_o           : out std_logic;
+      match_is_pause_o        : out std_logic;
+      match_pause_quanta_o    : out std_logic_vector(15 downto 0);
+      match_pause_prio_mask_o : out std_logic_vector(7 downto 0);
+      match_pause_p_o         : out std_logic;
+      regs_i                  : in  t_ep_out_registers);
+  end component;
+
+  component ep_clock_alignment_fifo
+    generic (
+      g_size                 : integer;
+      g_almostfull_threshold : integer);
+    port (
+      rst_n_rd_i       : in  std_logic;
+      rst_n_wr_i       : in std_logic;
+      clk_wr_i         : in  std_logic;
+      clk_rd_i         : in  std_logic;
+      dreq_i           : in  std_logic;
+      fab_i            : in  t_ep_internal_fabric;
+      fab_o            : out t_ep_internal_fabric;
+      full_o           : out std_logic;
+      empty_o          : out std_logic;
+      almostfull_o     : out std_logic;
+      pass_threshold_i : in  std_logic_vector(f_log2_size(g_size)-1 downto 0));
+  end component;
+
+  component ep_packet_filter
+    port (
+      clk_rx_i    : in  std_logic;
+      clk_sys_i   : in  std_logic;
+      rst_n_rx_i  : in  std_logic;
+      rst_n_sys_i : in  std_logic;
+      snk_fab_i   : in  t_ep_internal_fabric;
+      src_fab_o   : out t_ep_internal_fabric;
+      done_o      : out std_logic;
+      pclass_o    : out std_logic_vector(7 downto 0);
+      drop_o      : out std_logic;
+      regs_i      : in  t_ep_out_registers);
+  end component;
+
+  component ep_rx_vlan_unit
+    port (
+      clk_sys_i   : in    std_logic;
+      rst_n_i     : in    std_logic;
+      snk_fab_i   : in    t_ep_internal_fabric;
+      snk_dreq_o  : out   std_logic;
+      src_fab_o   : out   t_ep_internal_fabric;
+      src_dreq_i  : in    std_logic;
+      tclass_o    : out   std_logic_vector(2 downto 0);
+      vid_o       : out   std_logic_vector(11 downto 0);
+      tag_done_o  : out   std_logic;
+      is_tagged_o : out   std_logic;
+      regs_i      : in    t_ep_out_registers;
+      regs_o      : out   t_ep_in_registers);
+  end component;
+
+  component ep_rx_oob_insert
+    port (
+      clk_sys_i  : in  std_logic;
+      rst_n_i    : in  std_logic;
+      snk_fab_i  : in  t_ep_internal_fabric;
+      snk_dreq_o : out std_logic;
+      src_fab_o  : out t_ep_internal_fabric;
+      src_dreq_i : in  std_logic;
+      regs_i     : in  t_ep_out_registers);
+  end component;
+
+  component ep_rx_crc_size_check
+  	generic (
+      g_use_new_crc : boolean := false);
+    port (
+      clk_sys_i      : in  std_logic;
+      rst_n_i        : in  std_logic;
+      snk_fab_i      : in  t_ep_internal_fabric;
+      snk_dreq_o     : out std_logic;
+      src_fab_o      : out t_ep_internal_fabric;
+      src_dreq_i     : in  std_logic;
+      regs_i         : in  t_ep_out_registers;
+      rmon_pcs_err_o : out std_logic;
+      rmon_giant_o   : out std_logic;
+      rmon_runt_o    : out std_logic;
+      rmon_crc_err_o : out std_logic);
+  end component;
+
+  component ep_rx_wb_master
+    generic (
+      g_ignore_ack   : boolean;
+      g_cyc_on_stall : boolean := false);
+    port (
+      clk_sys_i  : in  std_logic;
+      rst_n_i    : in  std_logic;
+      snk_fab_i  : in  t_ep_internal_fabric;
+      snk_dreq_o : out std_logic;
+      src_wb_i   : in  t_wrf_source_in;
+      src_wb_o   : out t_wrf_source_out);
+  end component;
+
+  component ep_rx_status_reg_insert
+    port (
+      clk_sys_i           : in  std_logic;
+      rst_n_i             : in  std_logic;
+      snk_fab_i           : in  t_ep_internal_fabric;
+      snk_dreq_o          : out std_logic;
+      src_fab_o           : out t_ep_internal_fabric;
+      src_dreq_i          : in  std_logic;
+      mbuf_valid_i        : in  std_logic;
+      mbuf_ack_o          : out std_logic;
+      mbuf_drop_i         : in  std_logic;
+      mbuf_pclass_i       : in  std_logic_vector(7 downto 0);
+      mbuf_is_hp_i        : in  std_logic;
+      mbuf_is_pause_i     : in  std_logic;
+      rmon_pfilter_drop_o : out std_logic);
+  end component;
+
+  component ep_rx_buffer
+    generic (
+      g_size : integer;
+      g_with_fc : boolean := false);
+    port (
+      clk_sys_i  : in  std_logic;
+      rst_n_i    : in  std_logic;
+      snk_fab_i  : in  t_ep_internal_fabric;
+      snk_dreq_o : out std_logic;
+      src_fab_o  : out t_ep_internal_fabric;
+      src_dreq_i : in  std_logic;
+      level_o    : out std_logic_vector(7 downto 0);
+      full_o     : out std_logic;
+      drop_req_i : in std_logic;
+      dropped_o  : out std_logic;
+      regs_i     : in  t_ep_out_registers);
+  end component;
+
+
+  component ep_rx_path
+    generic (
+      g_with_vlans          : boolean;
+      g_with_dpi_classifier : boolean;
+      g_with_rtu            : boolean;
+      g_with_rx_buffer      : boolean;
+      g_rx_buffer_size      : integer;
+      g_use_new_crc         :	boolean);
+    port (
+      clk_sys_i              : in  std_logic;
+      clk_rx_i               : in  std_logic;
+      rst_n_sys_i            : in  std_logic;
+      rst_n_rx_i             : in  std_logic;
+      pcs_fab_i              : in  t_ep_internal_fabric;
+      pcs_fifo_almostfull_o  : out std_logic;
+      pcs_busy_i             : in  std_logic;
+      src_wb_o               : out t_wrf_source_out;
+      src_wb_i               : in  t_wrf_source_in;
+      fc_pause_p_o           : out std_logic;
+      fc_pause_quanta_o      : out std_logic_vector(15 downto 0);
+      fc_pause_prio_mask_o   : out std_logic_vector(7 downto 0);
+      fc_buffer_occupation_o : out std_logic_vector(7 downto 0);
+      rmon_o                 : out t_rmon_triggers;
+      regs_i                 : in  t_ep_out_registers;
+      regs_o                 : out t_ep_in_registers;
+      pfilter_pclass_o       : out std_logic_vector(7 downto 0);
+      pfilter_drop_o         : out std_logic;
+      pfilter_done_o         : out std_logic;
+      rtu_rq_o               : out t_ep_internal_rtu_request;
+      rtu_full_i             : in  std_logic;
+      rtu_rq_valid_o         : out std_logic;
+      rtu_rq_abort_o         : out std_logic;
+      nice_dbg_o             : out t_dbg_ep_rxpath);
+  end component;
+
+  component ep_tx_path
+    generic (
+      g_with_vlans            : boolean;
+      g_with_timestamper      : boolean;
+      g_with_packet_injection : boolean;
+      g_force_gap_length      : integer;
+      g_runt_padding          : boolean;
+      g_use_new_crc           :	boolean := false);
+    port (
+      clk_sys_i              : in  std_logic;
+      rst_n_i                : in  std_logic;
+      pcs_fab_o              : out t_ep_internal_fabric;
+      pcs_error_i            : in  std_logic;
+      pcs_busy_i             : in  std_logic;
+      pcs_dreq_i             : in  std_logic;
+      snk_i                  : in  t_wrf_sink_in;
+      snk_o                  : out t_wrf_sink_out;
+      fc_pause_req_i         : in  std_logic;
+      fc_pause_delay_i       : in  std_logic_vector(15 downto 0);
+      fc_pause_ready_o       : out std_logic;
+      fc_flow_enable_i       : in  std_logic;
+      txtsu_port_id_o        : out std_logic_vector(4 downto 0);
+      txtsu_fid_o            : out std_logic_vector(16 -1 downto 0);
+      txtsu_ts_value_o       : out std_logic_vector(28 + 4 - 1 downto 0);
+      txtsu_ts_incorrect_o   : out std_logic;
+      txtsu_stb_o            : out std_logic;
+      txtsu_ack_i            : in  std_logic;
+      txts_timestamp_i       : in  std_logic_vector(31 downto 0);
+      txts_timestamp_valid_i : in  std_logic;
+      inject_req_i           : in  std_logic                     := '0';
+      inject_ready_o         : out std_logic;
+      inject_packet_sel_i    : in  std_logic_vector(2 downto 0)  := "000";
+      inject_user_value_i    : in  std_logic_vector(15 downto 0) := x"0000";
+      ep_ctrl_i              : in  std_logic                     := '1';
+      regs_i                 : in  t_ep_out_registers;
+      regs_o                 : out t_ep_in_registers;
+      dbg_o                  : out std_logic_vector(33 downto 0));
+  end component;
+
+  component ep_tx_crc_inserter
+    generic(
+      g_use_new_crc	: boolean := false);
+    port (
+      clk_sys_i  : in  std_logic;
+      rst_n_i    : in  std_logic;
+      snk_fab_i  : in  t_ep_internal_fabric;
+      snk_dreq_o : out std_logic;
+      src_fab_o  : out t_ep_internal_fabric;
+      src_dreq_i : in  std_logic;
+      dbg_o      : out std_logic_vector(2 downto 0));
+  end component;
+  
+  component ep_tx_inject_ctrl
+    generic(
+      g_min_if_gap_length     : integer
+      );
+    port (
+      clk_sys_i             : in  std_logic;
+      rst_n_i               : in  std_logic;
+      snk_fab_i             : in  t_ep_internal_fabric;
+      snk_dreq_o            : out std_logic;
+      src_fab_o             : out t_ep_internal_fabric;
+      src_dreq_i            : in  std_logic;
+      inject_req_o          : out std_logic;
+      inject_ready_i        : in  std_logic;
+      inject_packet_sel_o   : out std_logic_vector(2 downto 0);
+      inject_user_value_o   : out std_logic_vector(15 downto 0);
+      inject_ctr_ena_o      : out std_logic;
+      inject_ctr_mode_o     : out std_logic_vector(1 downto 0);
+      regs_i                : in  t_ep_out_registers;
+      regs_o                : out t_ep_in_registers);
+  end component;
+
+
+  procedure f_pack_fifo_contents (
+    signal fab        : in  t_ep_internal_fabric;
+    signal dout       : out std_logic_vector;
+    signal dout_valid : out std_logic;
+    early_eof         :     boolean := false);
+
+
+  procedure f_unpack_fifo_contents (
+    signal din         : in  std_logic_vector;
+    constant din_valid : in  std_logic;
+    signal fab         : out t_ep_internal_fabric;
+    early_eof          : boolean := false);
+
+
+  procedure f_pack_rmon_triggers (
+      signal trig_in  : in t_rmon_triggers;
+      signal trig_out : out std_logic_vector(c_epevents_sz-1 downto 0));
+
+end endpoint_private_pkg;
+
+-------------------------------------------------------------------------------
+
+package body endpoint_private_pkg is
+
+  procedure f_pack_fifo_contents
+    (
+      signal fab        : in  t_ep_internal_fabric;
+      signal dout       : out std_logic_vector;
+      signal dout_valid : out std_logic;
+      early_eof         :     boolean := false) is
+  begin
+    -- the encodings are slightly different:
+    -- - if early_eof == 1, the target needs the EOF information along with the last data word.
+    --   This is the case for ep_tx_pcs.
+    -- - if early_eof == 0, EOF is an independent transfer
+    if(early_eof) then
+      if(fab.sof = '1' or fab.error = '1') then
+        -- tag = 01
+        dout(17 downto 16) <= "01";
+        dout(15)           <= fab.sof;
+        dout(14)           <= 'X';
+        dout(13)           <= fab.error;
+        dout(12 downto 0)  <= (others => 'X');
+        dout_valid         <= '1';
+      elsif(fab.eof = '1' and 
+         fab.dvalid = '1') then -- ML: it happened that the last word was "stalled" by PCS (dreq_i LOW)
+                                -- at the EOF... CRC indiated that this word is not valid (dvalid LOW)
+                                -- but this information was ignored... and tx was hanging the tree
+        -- tag = 1x
+        dout(17)          <= '1';
+        dout(16)          <= fab.bytesel;
+        dout(15 downto 0) <= fab.data;
+        dout_valid        <= '1';
+      elsif(fab.dvalid = '1') then
+        -- tag = 00
+        dout(17)          <= '0';
+        dout(16)          <= '0';
+        dout(15 downto 0) <= fab.data;
+        dout_valid        <= '1';
+      else
+        dout(17 downto 0) <= (others => 'X');
+        dout_valid        <= '0';
+      end if;
+    else
+      if(fab.sof = '1' or fab.error = '1' or fab.eof = '1' or fab.has_rx_timestamp = '1') then
+        -- tag = 01
+        dout(17)          <= 'X';
+        dout(16)          <= '1';
+        dout(15)          <= fab.sof;
+        dout(14)          <= fab.eof;
+        dout(13)          <= fab.error;
+        dout(12)          <= fab.has_rx_timestamp;
+        dout(11)          <= fab.rx_timestamp_valid;
+        dout(10 downto 0) <= (others => 'X');
+        dout_valid        <= '1';
+      elsif(fab.dvalid = '1') then
+        dout(17)          <= fab.bytesel;
+        dout(16)          <= '0';
+        dout(15 downto 0) <= fab.data;
+        dout_valid        <= '1';
+      else
+        dout(17 downto 0) <= (others => 'X');
+        dout_valid        <= '0';
+      end if;
+
+    end if;
+  end f_pack_fifo_contents;
+
+  procedure f_unpack_fifo_contents
+    (
+      signal din         : in  std_logic_vector;
+      constant din_valid : in  std_logic;
+      signal fab         : out t_ep_internal_fabric;
+      early_eof          : boolean := false) is
+  begin
+
+    fab.data <= din(15 downto 0);
+    fab.addr <= (others => '0');
+    if(din_valid = '1') then
+      if(early_eof) then
+        fab.dvalid             <= not (not din(17) and din(16));
+        fab.sof                <= not din(17) and din(16) and din(15);
+        fab.eof                <= din(17);
+        fab.error              <= not din(17) and din(16) and din(13);
+        fab.has_rx_timestamp   <= '0';
+        fab.rx_timestamp_valid <= '0';
+        fab.bytesel            <= din(17) and din(16);
+
+      else
+        fab.dvalid             <= not din(16);
+        fab.sof                <= din(16) and din(15);
+        fab.eof                <= din(16) and din(14);
+        fab.error              <= din(16) and din(13);
+        fab.has_rx_timestamp   <= din(16) and din(12);
+        fab.rx_timestamp_valid <= din(16) and din(11);
+        fab.bytesel            <= (not din(16)) and din(17);
+      end if;
+    else
+      fab.bytesel            <= 'X';
+      fab.dvalid             <= '0';
+      fab.sof                <= '0';
+      fab.eof                <= '0';
+      fab.error              <= '0';
+      fab.has_rx_timestamp   <= '0';
+      fab.rx_timestamp_valid <= '0';
+      fab.data               <= (others => 'X');
+    end if;
+  end f_unpack_fifo_contents;
+
+
+  procedure f_pack_rmon_triggers
+    (
+      signal trig_in  : in t_rmon_triggers;
+      signal trig_out : out std_logic_vector(c_epevents_sz-1 downto 0)) is
+  begin
+    --from 1000base pcs
+    trig_out(0) <= trig_in.tx_underrun;
+    trig_out(1) <= trig_in.rx_overrun;
+    trig_out(2) <= trig_in.rx_invalid_code;
+    trig_out(3) <= trig_in.rx_sync_lost;
+    trig_out(4) <= trig_in.rx_pause;
+    trig_out(5) <= trig_in.rx_pfilter_drop;
+    trig_out(6) <= trig_in.rx_pcs_err;
+    trig_out(7) <= trig_in.rx_giant;
+    trig_out(8) <= trig_in.rx_runt;
+    trig_out(9) <= trig_in.rx_crc_err;
+    trig_out(17 downto 10) <= trig_in.rx_pclass(7 downto 0);
+    trig_out(18)<= trig_in.tx_frame;
+    trig_out(19)<= trig_in.rx_frame;
+    trig_out(20)<= trig_in.rx_drop_at_rtu_full;
+    trig_out(28 downto 21) <= trig_in.rx_tclass(7 downto 0);
+  end f_pack_rmon_triggers;
+
+
+end endpoint_private_pkg;
+
+-------------------------------------------------------------------------------
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_1000basex_pcs.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_1000basex_pcs.vhd
new file mode 100644
index 000000000..900726f69
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_1000basex_pcs.vhd
@@ -0,0 +1,635 @@
+-------------------------------------------------------------------------------
+-- Title      : 1000Base-X Physical Coding Sublayer (PCS)
+-- Project    : White Rabbit MAC/Endpoint
+-------------------------------------------------------------------------------
+-- File       : ep_1000basex_pcs.vhd
+-- Author     : Tomasz Włostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2010-11-18
+-- Last update: 2017-02-20
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Module implements the top level of a 1000Base-X compliant PCS
+-- (Physical Coding Sublayer) with precise RX/TX timestamping. The PCS module
+-- incorporates:
+-- - configurable 8/16-bit RX/TX data paths,
+-- - TX clock alignment FIFO,
+-- - 802.3 autonegotiation.
+-- - White Rabbit serdes-specific features (calibration patterns & bitslide)
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2009-2017 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author    Description
+-- 2010-11-18  0.4      twlostow  Created (separeted from wrsw_endpoint)
+-- 2011-02-07  0.5      twlostow  Tested on Spartan6 GTP
+-- 2011-10-18  0.6      twlostow  Virtex-6 GTX port
+-- 2012-01-24  0.7      twlostow  Redone TX timestamping
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.endpoint_private_pkg.all;
+use work.endpoint_pkg.all;
+use work.gencores_pkg.all;
+
+entity ep_1000basex_pcs is
+
+  generic (
+    -- simulation mode: when true, all internal timeouts are reduced by few orders of
+    -- magnitude to speed up simulations.
+    g_simulation : boolean;
+    -- PCS datapath width selection: true = 16-bit (Virtex-6), false = 8-bit
+    -- (Spartan-6 or TBI).
+    g_16bit      : boolean);
+
+  port (
+
+    ---------------------------------------------------------------------------
+    -- System clock & resets (system + rx/tx)
+    ---------------------------------------------------------------------------
+
+    rst_sys_n_i   : in std_logic;
+    rst_txclk_n_i : in std_logic;
+    rst_rxclk_n_i : in std_logic;
+    clk_sys_i     : in std_logic;
+
+    ---------------------------------------------------------------------------
+    -- PCS <-> MAC Interface
+    ---------------------------------------------------------------------------
+
+    -- Internal data output (incoming data).
+    rxpcs_fab_o : out t_ep_internal_fabric;
+
+    -- 1: RX FIFO is almost full (drop the packet).
+    rxpcs_fifo_almostfull_i : in std_logic;
+
+    -- 1: RX PCS is busy receiving a packet or waiting for its' timestamp.
+    rxpcs_busy_o : out std_logic;
+
+    -- 1-pulse: RX timestamp trigger (to timestamping unit).
+    rxpcs_timestamp_trigger_p_a_o : out std_logic;
+
+    -- RX timestamp value (4 falling : 28 rising edge bits).
+    rxpcs_timestamp_i : in std_logic_vector(31 downto 0);
+
+    rxpcs_timestamp_stb_i : in std_logic;
+
+    -- 1: timestamp on rxpcs_timestamp_i is valid).
+    rxpcs_timestamp_valid_i : in std_logic;
+
+    -- Internal data input (data to be TXed).
+    txpcs_fab_i : in t_ep_internal_fabric;
+
+    -- 1: TX error occured.
+    txpcs_error_o : out std_logic;
+
+    -- 1: TX PCS is busy transmitting a packet.
+    txpcs_busy_o : out std_logic;
+
+    -- 1: TX PCS requests another transfer on txpcs_fab_i.
+    txpcs_dreq_o : out std_logic;
+
+    -- 1-pulse: TX timestamp trigger (to timestamping unit).
+    txpcs_timestamp_trigger_p_a_o : out std_logic;
+
+    link_ok_o : out std_logic;
+    link_ctr_i : in std_logic;
+    -----------------------------------------------------------------------------
+    -- GTP/GTX/TBI Serdes interface
+    ---------------------------------------------------------------------------
+
+    -- 1: serdes is reset, 0: serdes is operating normally.
+    serdes_rst_o : out std_logic;
+
+    -- 1: serdes near-end PMA loopback is enabled.
+    serdes_loopen_o         : out std_logic;
+
+    -- 000: loopback vector "normal operation" (see Serdes User Guide)
+    serdes_loopen_vec_o     : out std_logic_vector(2 downto 0);
+
+    -- 000: "normal operation" (see Serdes User Guide)
+    serdes_tx_prbs_sel_o    : out   std_logic_vector(2 downto 0);
+    
+    -- 1: indicates laser fault
+    serdes_sfp_tx_fault_i   : in  std_logic;
+
+    -- 1: indicates Loss Of Signal
+    serdes_sfp_los_i        : in  std_logic;
+    
+    -- 1: Disables the transmitter
+    serdes_sfp_tx_disable_o : out std_logic;
+
+    -- 1: serdes is locked and aligned
+    serdes_rdy_i    : in  std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Serdes TX path (all synchronous to serdes_tx_clk_i)
+    ---------------------------------------------------------------------------
+
+    -- Transmit path clock:
+    -- 62.5 MHz in 16-bit mode, 125 MHz in 8-bit mode.
+    serdes_tx_clk_i : in std_logic;
+
+    -- TX Code group. In 16-bit mode, the MSB is TXed first (tx_data_o[15:8],
+    -- then tx_data_o[7:0]). In 8-bit mode only bits [7:0] are used.
+    serdes_tx_data_o : out std_logic_vector(f_pcs_data_width(g_16bit)-1 downto 0);
+
+    -- TX Control Code: When 1, a K-character is transmitted. In 16-bit mode,
+    -- bit 1 goes first, in 8-bit mode only bit 0 is used.
+    serdes_tx_k_o : out std_logic_vector(f_pcs_k_width(g_16bit)-1 downto 0);
+
+    -- TX Disparity input: 1 = last transmitted code group ended with negative
+    -- running disparity, 0 = positive RD.
+    serdes_tx_disparity_i : in std_logic;
+
+    -- TX Encoding Error: 1 = PHY encountered a transmission error, drop the current
+    -- packet.
+    serdes_tx_enc_err_i : in std_logic;
+
+    -------------------------------------------------------------------------------
+    -- Serdes RX path (all synchronous to serdes_rx_clk_i)
+    -------------------------------------------------------------------------------
+
+    -- RX recovered clock. MUST be synchronous to incoming serial data stream
+    -- for proper PTP/SyncE operation. 62.5 MHz in 16-bit mode, 125 MHz in 8-bit mode.
+    serdes_rx_clk_i      : in std_logic;
+    serdes_rx_data_i     : in std_logic_vector(f_pcs_data_width(g_16bit)-1 downto 0);
+    serdes_rx_k_i        : in std_logic_vector(f_pcs_k_width(g_16bit)-1 downto 0);
+    serdes_rx_enc_err_i  : in std_logic;
+    serdes_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_16bit)-1 downto 0);
+
+    -- RMON events, aligned to clk_sys
+    rmon_o : out t_rmon_triggers;
+
+    --  MDIO interface
+
+    mdio_addr_i  : in  std_logic_vector(15 downto 0);
+    mdio_data_i  : in  std_logic_vector(15 downto 0);
+    mdio_data_o  : out std_logic_vector(15 downto 0);
+    mdio_stb_i   : in  std_logic;
+    mdio_rw_i    : in  std_logic;
+    mdio_ready_o : out std_logic;
+    
+    dbg_tx_pcs_wr_count_o     : out std_logic_vector(5+4 downto 0);
+    dbg_tx_pcs_rd_count_o     : out std_logic_vector(5+4 downto 0);
+    nice_dbg_o                : out t_dbg_ep_pcs);
+
+end ep_1000basex_pcs;
+
+architecture rtl of ep_1000basex_pcs is
+
+  alias rst_n_i : std_logic is rst_sys_n_i;
+
+  signal mdio_mcr_anrestart       : std_logic;
+  signal mdio_mcr_pdown           : std_logic;
+  signal mdio_mcr_pdown_cpu       : std_logic;
+  signal mdio_mcr_anenable        : std_logic;
+  signal mdio_mcr_reset           : std_logic;
+  signal mdio_msr_lstatus         : std_logic;
+  signal mdio_msr_rfault          : std_logic;
+  signal mdio_msr_anegcomplete    : std_logic;
+  signal mdio_advertise_pause     : std_logic_vector(1 downto 0);
+  signal mdio_advertise_rfault    : std_logic_vector(1 downto 0);
+  signal mdio_lpa_full            : std_logic;
+  signal mdio_lpa_half            : std_logic;
+  signal mdio_lpa_pause           : std_logic_vector(1 downto 0);
+  signal mdio_lpa_rfault          : std_logic_vector(1 downto 0);
+  signal mdio_lpa_lpack           : std_logic;
+  signal mdio_lpa_npage           : std_logic;
+  signal mdio_wr_spec_tx_cal      : std_logic;
+  signal mdio_wr_spec_rx_cal_stat : std_logic;
+  signal mdio_wr_spec_cal_crst    : std_logic;
+  signal mdio_wr_spec_bslide      : std_logic_vector(4 downto 0);
+  signal mdio_data_in             : std_logic_vector(31 downto 0);
+  signal mdio_data_out            : std_logic_vector(31 downto 0);
+
+  signal lstat_read_notify : std_logic;
+
+-------------------------------------------------------------------------------
+-- Autonegotiation signals
+-------------------------------------------------------------------------------
+
+  signal an_tx_en      : std_logic;
+  signal an_rx_en      : std_logic;
+  signal an_tx_val     : std_logic_vector(15 downto 0);
+  signal an_rx_val     : std_logic_vector(15 downto 0);
+  signal an_rx_valid   : std_logic;
+  signal an_idle_match : std_logic;
+
+  signal pcs_enable        : std_logic;
+  signal synced, sync_lost : std_logic;
+  signal synced_d1         : std_logic;
+
+  signal txpcs_busy_int : std_logic;
+  signal link_ok        : std_logic;
+
+  signal pcs_reset_n : std_logic;
+
+  signal wb_stb, wb_ack : std_logic;
+
+  signal tx_clk, rx_clk : std_logic;
+
+  --RMON events
+  signal rmon_tx_underrun : std_logic;
+  signal rmon_rx_overrun  : std_logic;
+  signal rmon_rx_inv_code : std_logic;
+  signal rmon_rx_sync_lost: std_logic;
+  
+begin  -- rtl
+
+  pcs_reset_n <= '0' when (mdio_mcr_reset = '1' or rst_n_i = '0') else '1';
+
+  gen_16bit : if(g_16bit) generate
+    U_TX_PCS : ep_tx_pcs_16bit
+      port map (
+        rst_n_i   => pcs_reset_n,
+        clk_sys_i => clk_sys_i,
+
+        rst_txclk_n_i => rst_txclk_n_i,
+
+        pcs_fab_i   => txpcs_fab_i,
+        pcs_error_o => txpcs_error_o,
+        pcs_busy_o  => txpcs_busy_int,
+        pcs_dreq_o  => txpcs_dreq_o,
+
+        mdio_mcr_reset_i      => mdio_mcr_reset,
+        mdio_mcr_pdown_i      => mdio_mcr_pdown,
+        mdio_wr_spec_tx_cal_i => mdio_wr_spec_tx_cal,
+
+        an_tx_en_i              => an_tx_en,
+        an_tx_val_i             => an_tx_val,
+        timestamp_trigger_p_a_o => txpcs_timestamp_trigger_p_a_o,
+        rmon_tx_underrun        => rmon_tx_underrun,
+
+        phy_tx_clk_i       => serdes_tx_clk_i,
+        phy_tx_data_o      => serdes_tx_data_o,
+        phy_tx_k_o         => serdes_tx_k_o,
+        phy_tx_disparity_i => serdes_tx_disparity_i,
+        phy_tx_enc_err_i   => serdes_tx_enc_err_i,
+        dbg_wr_count_o     => dbg_tx_pcs_wr_count_o,
+        dbg_rd_count_o     => dbg_tx_pcs_rd_count_o     
+        );
+
+    U_RX_PCS : ep_rx_pcs_16bit
+      generic map (
+        g_simulation => g_simulation)
+      port map (
+        clk_sys_i => clk_sys_i,
+        rst_n_i   => pcs_reset_n,
+
+        rst_rxclk_n_i => rst_rxclk_n_i,
+
+        pcs_busy_o            => rxpcs_busy_o,
+        pcs_fab_o             => rxpcs_fab_o,
+        pcs_fifo_almostfull_i => rxpcs_fifo_almostfull_i,
+
+        timestamp_trigger_p_a_o => rxpcs_timestamp_trigger_p_a_o,
+        timestamp_i             => rxpcs_timestamp_i,
+        timestamp_valid_i       => rxpcs_timestamp_valid_i,
+        timestamp_stb_i         => rxpcs_timestamp_stb_i,
+
+        mdio_mcr_reset_i           => mdio_mcr_reset,
+        mdio_mcr_pdown_i           => mdio_mcr_pdown,
+        mdio_wr_spec_cal_crst_i    => mdio_wr_spec_cal_crst,
+        mdio_wr_spec_rx_cal_stat_o => mdio_wr_spec_rx_cal_stat,
+
+        synced_o        => synced,
+        sync_lost_o     => sync_lost,
+        an_rx_en_i      => an_rx_en,
+        an_rx_val_o     => an_rx_val,
+        an_rx_valid_o   => an_rx_valid,
+        an_idle_match_o => an_idle_match,
+
+        rmon_rx_overrun  => rmon_rx_overrun,
+        rmon_rx_inv_code => rmon_rx_inv_code,
+        rmon_rx_sync_lost=> rmon_rx_sync_lost,
+
+        phy_rdy_i        => serdes_rdy_i,
+        phy_rx_clk_i     => serdes_rx_clk_i,
+        phy_rx_data_i    => serdes_rx_data_i,
+        phy_rx_k_i       => serdes_rx_k_i,
+        phy_rx_enc_err_i => serdes_rx_enc_err_i,
+
+        nice_dbg_o => nice_dbg_o.rx
+        );
+
+    mdio_wr_spec_bslide <= serdes_rx_bitslide_i(4 downto 0);
+    
+  end generate gen_16bit;
+
+  gen_8bit : if(not g_16bit) generate
+    U_TX_PCS : ep_tx_pcs_8bit
+      port map (
+        rst_n_i   => pcs_reset_n,
+        clk_sys_i => clk_sys_i,
+
+        rst_txclk_n_i => rst_txclk_n_i,
+
+        pcs_fab_i   => txpcs_fab_i,
+        pcs_error_o => txpcs_error_o,
+        pcs_busy_o  => txpcs_busy_int,
+        pcs_dreq_o  => txpcs_dreq_o,
+
+        mdio_mcr_reset_i      => mdio_mcr_reset,
+        mdio_mcr_pdown_i      => mdio_mcr_pdown,
+        mdio_wr_spec_tx_cal_i => mdio_wr_spec_tx_cal,
+
+        an_tx_en_i              => an_tx_en,
+        an_tx_val_i             => an_tx_val,
+        timestamp_trigger_p_a_o => txpcs_timestamp_trigger_p_a_o,
+        rmon_tx_underrun        => rmon_tx_underrun,
+
+        phy_tx_clk_i       => serdes_tx_clk_i,
+        phy_tx_data_o      => serdes_tx_data_o(7 downto 0),
+        phy_tx_k_o         => serdes_tx_k_o(0),
+        phy_tx_disparity_i => serdes_tx_disparity_i,
+        phy_tx_enc_err_i   => serdes_tx_enc_err_i
+        );
+
+    U_RX_PCS : ep_rx_pcs_8bit
+      generic map (
+        g_simulation => g_simulation)
+      port map (
+        clk_sys_i => clk_sys_i,
+        rst_n_i   => pcs_reset_n,
+
+        rst_rxclk_n_i => rst_rxclk_n_i,
+
+        pcs_busy_o            => rxpcs_busy_o,
+        pcs_fab_o             => rxpcs_fab_o,
+        pcs_fifo_almostfull_i => rxpcs_fifo_almostfull_i,
+
+        timestamp_trigger_p_a_o => rxpcs_timestamp_trigger_p_a_o,
+        timestamp_i             => rxpcs_timestamp_i,
+        timestamp_valid_i       => rxpcs_timestamp_valid_i,
+        timestamp_stb_i         => rxpcs_timestamp_stb_i,
+
+        mdio_mcr_reset_i           => mdio_mcr_reset,
+        mdio_mcr_pdown_i           => mdio_mcr_pdown,
+        mdio_wr_spec_cal_crst_i    => mdio_wr_spec_cal_crst,
+        mdio_wr_spec_rx_cal_stat_o => mdio_wr_spec_rx_cal_stat,
+
+        synced_o        => synced,
+        sync_lost_o     => sync_lost,
+        an_rx_en_i      => an_rx_en,
+        an_rx_val_o     => an_rx_val,
+        an_rx_valid_o   => an_rx_valid,
+        an_idle_match_o => an_idle_match,
+
+        rmon_rx_overrun  => rmon_rx_overrun,
+        rmon_rx_inv_code => rmon_rx_inv_code,
+        rmon_rx_sync_lost=> rmon_rx_sync_lost,
+
+        phy_rdy_i        => serdes_rdy_i,
+        phy_rx_clk_i     => serdes_rx_clk_i,
+        phy_rx_data_i    => serdes_rx_data_i(7 downto 0),
+        phy_rx_k_i       => serdes_rx_k_i(0),
+        phy_rx_enc_err_i => serdes_rx_enc_err_i
+        );
+
+    mdio_wr_spec_bslide <= '0' & serdes_rx_bitslide_i(3 downto 0);
+
+    dbg_tx_pcs_rd_count_o <= (others => '0');
+    dbg_tx_pcs_wr_count_o <= (others => '0');
+    nice_dbg_o.rx.fsm     <= (others => '0');
+
+  end generate gen_8bit;
+
+  txpcs_busy_o <= txpcs_busy_int;
+
+  -- to enable killing of link (by ML)
+  mdio_mcr_pdown <= mdio_mcr_pdown_cpu or (not link_ctr_i);
+
+  -- keep PHY reset also when SFP reports LOS (DL)
+  serdes_rst_o <= (not pcs_reset_n) or mdio_mcr_pdown or serdes_sfp_los_i;
+
+  U_MDIO_WB : ep_pcs_tbi_mdio_wb
+    port map (
+      rst_n_i   => rst_n_i,
+      clk_sys_i => clk_sys_i,
+      wb_adr_i  => mdio_addr_i(4 downto 0),
+      wb_dat_i  => mdio_data_in,
+      wb_dat_o  => mdio_data_out,
+
+      wb_cyc_i   => wb_stb,
+      wb_sel_i   => "1111",
+      wb_stb_i   => wb_stb,
+      wb_we_i    => mdio_rw_i,
+      wb_ack_o   => wb_ack,
+      wb_stall_o => open,
+      tx_clk_i   => serdes_tx_clk_i,
+      rx_clk_i   => serdes_rx_clk_i,
+
+      mdio_mcr_uni_en_o          => open,
+      mdio_mcr_anrestart_o       => mdio_mcr_anrestart,
+      mdio_mcr_pdown_o           => mdio_mcr_pdown_cpu,
+      mdio_mcr_anenable_o        => mdio_mcr_anenable,
+      mdio_mcr_reset_o           => mdio_mcr_reset,
+      mdio_mcr_loopback_o        => serdes_loopen_o,
+      mdio_msr_lstatus_i         => mdio_msr_lstatus,
+      mdio_msr_rfault_i          => mdio_msr_rfault,
+      mdio_msr_anegcomplete_i    => mdio_msr_anegcomplete,
+      mdio_advertise_pause_o     => mdio_advertise_pause,
+      mdio_advertise_rfault_o    => mdio_advertise_rfault,
+      mdio_lpa_full_i            => mdio_lpa_full,
+      mdio_lpa_half_i            => mdio_lpa_half,
+      mdio_lpa_pause_i           => mdio_lpa_pause,
+      mdio_lpa_rfault_i          => mdio_lpa_rfault,
+      mdio_lpa_lpack_i           => mdio_lpa_lpack,
+      mdio_lpa_npage_i           => mdio_lpa_npage,
+      mdio_wr_spec_tx_cal_o      => mdio_wr_spec_tx_cal,
+      mdio_wr_spec_rx_cal_stat_i => mdio_wr_spec_rx_cal_stat,
+      mdio_wr_spec_cal_crst_o    => mdio_wr_spec_cal_crst,
+      mdio_wr_spec_bslide_i      => mdio_wr_spec_bslide,
+      mdio_ectrl_lpbck_vec_o       => serdes_loopen_vec_o,
+      mdio_ectrl_sfp_tx_fault_i    => serdes_sfp_tx_fault_i,
+      mdio_ectrl_sfp_loss_i        => serdes_sfp_los_i,
+      mdio_ectrl_sfp_tx_disable_o  => serdes_sfp_tx_disable_o,
+      mdio_ectrl_tx_prbs_sel_o     => serdes_tx_prbs_sel_o,
+
+      lstat_read_notify_o => lstat_read_notify
+      );
+
+
+  mdio_data_in <= X"0000" & mdio_data_i;
+  mdio_data_o  <= mdio_data_out(15 downto 0);
+
+  mdio_msr_rfault <= '0';
+
+  U_AUTONEGOTIATION : ep_autonegotiation
+    generic map (
+      g_simulation => g_simulation)
+
+    port map (
+      clk_sys_i => clk_sys_i,
+      rst_n_i   => pcs_reset_n,
+
+      pcs_synced_i  => synced,
+      pcs_los_i     => sync_lost,
+      pcs_link_ok_o => link_ok,
+
+      an_idle_match_i         => an_idle_match,
+      an_rx_en_o              => an_rx_en,
+      an_rx_val_i             => an_rx_val,
+      an_rx_valid_i           => an_rx_valid,
+      an_tx_en_o              => an_tx_en,
+      an_tx_val_o             => an_tx_val,
+      mdio_mcr_anrestart_i    => mdio_mcr_anrestart,
+      mdio_mcr_anenable_i     => mdio_mcr_anenable,
+      mdio_msr_anegcomplete_o => mdio_msr_anegcomplete,
+      mdio_advertise_pause_i  => mdio_advertise_pause,
+      mdio_advertise_rfault_i => mdio_advertise_rfault,
+      mdio_lpa_full_o         => mdio_lpa_full,
+      mdio_lpa_half_o         => mdio_lpa_half,
+      mdio_lpa_pause_o        => mdio_lpa_pause,
+      mdio_lpa_rfault_o       => mdio_lpa_rfault,
+      mdio_lpa_lpack_o        => mdio_lpa_lpack,
+      mdio_lpa_npage_o        => mdio_lpa_npage
+      );
+
+  -- process: translates the MDIO reads/writes into Wishbone read/writes
+  -- inputs: mdio_stb_i, wb_ack
+  -- ouputs: mdio_ready_o, wb_stb
+  p_translate_mdio_wb : process(clk_sys_i, rst_n_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if (rst_n_i = '0') then
+        wb_stb       <= '0';
+        mdio_ready_o <= '1';
+      else
+        if(mdio_stb_i = '1' and wb_stb = '0') then
+          wb_stb       <= '1';
+          mdio_ready_o <= '0';
+        elsif(wb_stb = '1' and wb_ack = '1') then
+          mdio_ready_o <= '1';
+          wb_stb       <= '0';
+        end if;
+      end if;
+    end if;
+  end process;
+
+  -- process: handles the LSTATUS bit in MSR register
+  -- inputs: sync_lost, synced, lstat_read_notify
+  -- outputs: mdio_msr_lstatus
+  p_gen_link_status : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if(pcs_reset_n = '0') then
+        mdio_msr_lstatus <= '0';
+      else
+        if(sync_lost = '1') then
+          mdio_msr_lstatus <= '0';
+        elsif(lstat_read_notify = '1') then
+          mdio_msr_lstatus <= synced and link_ok;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  -- The process delays by 1 cyc synced signal. This delayed synced, called synced_d1
+  -- is then used to produce link_ok_o (below he process).
+  -- This is done to avoid 1-cycle glitches of link_ok_o. Such glitch happened after
+  -- the autonegotation FSM was in pseudo AN_ENABLED state caused by synced=LOW (in
+  -- this state, link_ok is HIGH). When synced goes HIGH, the FSM enters "proper" 
+  -- AN_ENABLED state, it drives link_ok LOW.s All in all, this glitch is avoided
+  -- when we use delayed synced_d1 to produce the final link_ok_o
+  p_delay_synced: process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if(pcs_reset_n = '0') then
+        synced_d1 <= '0';
+      else
+        synced_d1 <= synced;
+      end if;
+    end if;
+  end process;
+
+  link_ok_o <= link_ok and synced_d1;
+
+  --RMON events
+  U_sync_tx_underrun: gc_sync_ffs
+  generic map (
+    g_sync_edge => "positive")
+  port map (
+    clk_i    => clk_sys_i,
+    rst_n_i  => rst_n_i,
+    data_i   => rmon_tx_underrun,
+    synced_o => open,
+    npulse_o => open,
+    ppulse_o => rmon_o.tx_underrun);
+
+  U_sync_rx_overrun: gc_sync_ffs
+  generic map (
+    g_sync_edge => "positive")
+  port map (
+    clk_i    => clk_sys_i,
+    rst_n_i  => rst_n_i,
+    data_i   => rmon_rx_overrun,
+    synced_o => open,
+    npulse_o => open,
+    ppulse_o => rmon_o.rx_overrun);
+
+  U_sync_rx_inv_code: gc_sync_ffs
+  generic map (
+    g_sync_edge => "positive")
+  port map (
+    clk_i    => clk_sys_i,
+    rst_n_i  => rst_n_i,
+    data_i   => rmon_rx_inv_code,
+    synced_o => open,
+    npulse_o => open,
+    ppulse_o => rmon_o.rx_invalid_code);
+
+  U_sync_rx_sync_lost: gc_sync_ffs
+  generic map (
+    g_sync_edge => "positive")
+  port map (
+    clk_i    => clk_sys_i,
+    rst_n_i  => rst_n_i,
+    data_i   => rmon_rx_sync_lost,
+    synced_o => open,
+    npulse_o => open,
+    ppulse_o => rmon_o.rx_sync_lost);
+
+  -- drive unused outputs
+  rmon_o.rx_crc_err             <= '0';
+  rmon_o.rx_ok                  <= '0';
+  rmon_o.rx_pfilter_drop        <= '0';
+  rmon_o.rx_runt                <= '0';
+  rmon_o.rx_giant               <= '0';
+  rmon_o.rx_pause               <= '0';
+  rmon_o.rx_pcs_err             <= '0';
+  rmon_o.rx_buffer_overrun      <= '0';
+  rmon_o.rx_rtu_overrun         <= '0';
+  rmon_o.rx_path_timing_failure <= '0';
+  rmon_o.tx_pause               <= '0';
+  rmon_o.rx_pclass              <= (others => '0');
+  rmon_o.rx_tclass              <= (others => '0');
+  rmon_o.tx_frame               <= '0';
+  rmon_o.rx_frame               <= '0';
+  rmon_o.rx_drop_at_rtu_full    <= '0';
+
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_autonegotiation.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_autonegotiation.vhd
new file mode 100644
index 000000000..69dbe4c06
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_autonegotiation.vhd
@@ -0,0 +1,281 @@
+-------------------------------------------------------------------------------
+-- Title      : 1000Base-X Autonegotiation 
+-- Project    : White Rabbit MAC/Endpoint
+-------------------------------------------------------------------------------
+-- File       : ep_autonegotiation.vhd
+-- Author     : Tomasz Włostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2010-11-18
+-- Last update: 2017-02-21
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Module implements the 1000Base-X autonegotiation engine as
+-- defined in IEEE802.3.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2009 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1l.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author    Description
+-- 2010-11-18  0.4      twlostow  Initial release
+-- 2011-02-07  0.5      twlostow  Tested on Spartan6 GTP
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.endpoint_private_pkg.all;
+
+entity ep_autonegotiation is
+  generic (
+    g_simulation : boolean);
+  port (
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    -- RX PCS signals
+    pcs_synced_i  : in  std_logic;
+    pcs_los_i     : in  std_logic;
+    pcs_link_ok_o : out std_logic;
+
+    an_idle_match_i : in  std_logic;
+    an_rx_en_o      : out std_logic;
+    an_rx_val_i     : in  std_logic_vector(15 downto 0);
+    an_rx_valid_i   : in  std_logic;
+
+    -- TX PCS signals
+    an_tx_en_o  : out std_logic;
+    an_tx_val_o : out std_logic_vector(15 downto 0);
+
+    mdio_mcr_anrestart_i    : in  std_logic;
+    mdio_mcr_anenable_i     : in  std_logic;
+    mdio_msr_anegcomplete_o : out std_logic;
+
+    mdio_advertise_pause_i  : in std_logic_vector(1 downto 0);
+    mdio_advertise_rfault_i : in std_logic_vector(1 downto 0);
+
+    mdio_lpa_full_o   : out std_logic;
+    mdio_lpa_half_o   : out std_logic;
+    mdio_lpa_pause_o  : out std_logic_vector(1 downto 0);
+    mdio_lpa_rfault_o : out std_logic_vector(1 downto 0);
+    mdio_lpa_lpack_o  : out std_logic;
+    mdio_lpa_npage_o  : out std_logic
+    );
+
+end ep_autonegotiation;
+
+architecture syn of ep_autonegotiation is
+
+  type t_autoneg_state is (AN_ENABLE, AN_RESTART, AN_ABILITY_DETECT, AN_DISABLE_LINK_OK, AN_ACKNOWLEDGE_DETECT, AN_COMPLETE_ACKNOWLEDGE, AN_IDLE_DETECT, AN_LINK_OK);
+
+  signal state : t_autoneg_state;
+
+
+  function f_eval_link_timer_size
+    return integer is
+  begin  -- f_eval_link_timer_size
+    if(g_simulation = false) then
+      return 20;
+      else
+        return 11;
+      end if;
+  end f_eval_link_timer_size;
+
+  constant c_link_timer_bits : integer := f_eval_link_timer_size;
+  
+  signal link_timer : unsigned(c_link_timer_bits downto 0);  -- 23 for normal operation
+
+
+  signal link_timer_restart : std_logic;
+  signal link_timer_expired : std_logic;
+
+  signal an_enable_changed, an_enable_d0 : std_logic;
+  signal toggle_tx, toggle_rx            : std_logic;
+
+  signal rx_config_reg : std_logic_vector(15 downto 0);
+
+  signal acknowledge_match : std_logic;
+  signal ability_match     : std_logic;
+  signal consistency_match : std_logic;
+  
+  
+  
+begin  -- syn
+
+
+  -- process: link timer (counts until MSB of link_timer == 1).
+  -- inputs: link_timer_restart
+  -- outputs: link_timer_expired
+  p_link_timer : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' or link_timer_restart ='1'  then
+        link_timer <= (others => '0');
+      else
+        if(link_timer_expired = '0') then
+          link_timer <= link_timer + 1;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  link_timer_expired <= std_logic(link_timer(link_timer'high)) and (not link_timer_restart);
+
+
+  -- process: detects the changes of Autonegotiation Enable bit.
+  -- inputs: mdio_mcr_anenable_i
+  -- outputs: an_enable_changed
+  p_detect_enable_changed : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      an_enable_d0      <= mdio_mcr_anenable_i;
+      an_enable_changed <= an_enable_d0 xor mdio_mcr_anenable_i;
+    end if;
+  end process;
+
+
+  -- generate some FSM conditions combinatorially outside the FSM process to
+  -- make the code more readable
+  ability_match     <= an_rx_valid_i;
+  acknowledge_match <= an_rx_valid_i and an_rx_val_i(14);
+  consistency_match <= '1' when (an_rx_valid_i = '1' and rx_config_reg (15) = an_rx_val_i(15) and rx_config_reg(13 downto 0) = an_rx_val_i(13 downto 0));
+
+
+-- process: main auto-negotiation state machine. More or less compatible with
+-- IEEE 802.3.
+  p_autonegotation_fsm : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        link_timer_restart <= '0';
+        state              <= AN_ENABLE;
+        pcs_link_ok_o      <= '0';
+
+        an_tx_en_o  <= '0';
+        an_rx_en_o  <= '1';
+        an_tx_val_o <= (others => '0');
+
+        mdio_lpa_lpack_o        <= '0';
+        mdio_msr_anegcomplete_o <= '0';
+        rx_config_reg           <= (others => '0');
+      else
+
+        if(mdio_mcr_anrestart_i = '1' or an_enable_changed = '1' or pcs_synced_i = '0') then
+          state <= AN_ENABLE;
+        else
+          
+          case state is
+            when AN_ENABLE =>
+              mdio_msr_anegcomplete_o <= '0';
+              pcs_link_ok_o <= '0';
+
+              if mdio_mcr_anenable_i = '1' then
+                an_tx_val_o        <= (others => '0');  -- send breaklink
+                an_tx_en_o         <= '1';
+                link_timer_restart <= '1';
+                state              <= AN_RESTART;
+              else
+                state <= AN_DISABLE_LINK_OK;
+              end if;
+
+            when AN_DISABLE_LINK_OK =>
+              an_tx_en_o    <= '0';
+              pcs_link_ok_o <= '1';
+              
+            when AN_RESTART =>
+              link_timer_restart <= '0';
+              if(link_timer_expired = '1') then
+                state <= AN_ABILITY_DETECT;
+              end if;
+
+
+            when AN_ABILITY_DETECT =>
+--              toggle_tx <= mr_adv_ability<12> -- ???
+              an_rx_en_o                 <= '1';
+              an_tx_en_o                 <= '1';
+              an_tx_val_o (15)           <= '0';
+              an_tx_val_o (14)           <= '0';
+              an_tx_val_o (13 downto 12) <= mdio_advertise_rfault_i;
+              an_tx_val_o (11 downto 9)  <= (others => '0');
+              an_tx_val_o (8 downto 7)   <= mdio_advertise_pause_i;
+              an_tx_val_o (6)            <= '0';  -- hdx not supported
+              an_tx_val_o (5)            <= '1';  -- fdx supported
+              an_tx_val_o (4 downto 0)   <= (others => '0');
+
+              if(an_rx_valid_i = '1' and an_rx_val_i /= x"0000") then  -- ability_match=true
+                state         <= AN_ACKNOWLEDGE_DETECT;
+                rx_config_reg <= an_rx_val_i;
+              end if;
+
+            when AN_ACKNOWLEDGE_DETECT =>
+              an_tx_val_o(14) <= '1';
+              if(acknowledge_match = '1' and consistency_match = '0')
+                or (ability_match = '1' and an_rx_val_i = x"0000") then
+                state <= AN_ENABLE;
+              elsif(acknowledge_match = '1' and consistency_match = '1') then
+                state              <= AN_COMPLETE_ACKNOWLEDGE;
+                link_timer_restart <= '1';
+              end if;
+
+            when AN_COMPLETE_ACKNOWLEDGE =>
+              link_timer_restart <= '0';
+
+              mdio_lpa_npage_o  <= an_rx_val_i(15);
+              mdio_lpa_lpack_o  <= an_rx_val_i(14);
+              mdio_lpa_rfault_o <= an_rx_val_i(13 downto 12);
+              mdio_lpa_pause_o  <= an_rx_val_i (8 downto 7);
+              mdio_lpa_half_o   <= an_rx_val_i(6);
+              mdio_lpa_full_o   <= an_rx_val_i(5);
+
+
+              if(ability_match = '1' and an_rx_val_i = x"0000")then
+                state <= AN_ENABLE;
+              elsif(link_timer_expired = '1' and (ability_match = '0' or an_rx_val_i /= x"0000")) then
+                link_timer_restart <= '1';
+                state              <= AN_IDLE_DETECT;
+              end if;
+
+            when AN_IDLE_DETECT =>
+              link_timer_restart <= '0';
+              an_tx_en_o         <= '0';
+              if(ability_match = '1' and an_rx_val_i = x"0000") then
+                state <= AN_ENABLE;
+              elsif (an_idle_match_i = '1' and link_timer_expired = '1') then
+                state <= AN_LINK_OK;
+              end if;
+
+
+            when AN_LINK_OK =>
+              mdio_msr_anegcomplete_o <= '1';
+              pcs_link_ok_o           <= '1';
+              if(ability_match = '1') then
+                state <= AN_ENABLE;
+              end if;
+              
+            when others => null;
+          end case;
+        end if;
+      end if;
+    end if;
+  end process;
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_clock_alignment_fifo.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_clock_alignment_fifo.vhd
new file mode 100644
index 000000000..09a214467
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_clock_alignment_fifo.vhd
@@ -0,0 +1,127 @@
+-------------------------------------------------------------------------------
+-- Title      : RX Clock Alignment FIFO
+-- Project    : White Rabbit MAC/Endpoint
+-------------------------------------------------------------------------------
+-- File       : ep_clock_alignment_fifo.vhd
+-- Author     : Tomasz Włostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2010-11-18
+-- Last update: 2012-08-28
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Asynchronous FIFO with internal fabric (t_ep_internal_fabric)
+-- interface used to pass packet data between the RX clock->system clock
+-- domains. 
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2009-2011 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.genram_pkg.all;
+use work.endpoint_private_pkg.all;
+use work.endpoint_pkg.all;
+
+entity ep_clock_alignment_fifo is
+
+  generic(
+    g_size                 : integer := 64;
+    g_almostfull_threshold : integer := 56);
+
+  port(
+    rst_n_rd_i : in std_logic;
+    rst_n_wr_i : in std_logic;
+    clk_wr_i   : in std_logic;
+    clk_rd_i   : in std_logic;
+
+    dreq_i : in  std_logic;
+    fab_i  : in  t_ep_internal_fabric;
+    fab_o  : out t_ep_internal_fabric;
+
+    full_o       : out std_logic;
+    empty_o      : out std_logic;
+    almostfull_o : out std_logic;
+
+    -- number of data words which enables the output. Used
+    -- to control the minimum latency
+    pass_threshold_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0)
+    );
+end ep_clock_alignment_fifo;
+
+architecture structural of ep_clock_alignment_fifo is
+  signal fifo_in   : std_logic_vector(17 downto 0);
+  signal fifo_out  : std_logic_vector(17 downto 0);
+  signal rx_rdreq  : std_logic;
+  signal empty_int : std_logic;
+  signal valid_int : std_logic;
+
+
+  signal fab_int      : t_ep_internal_fabric;
+  signal fifo_we      : std_logic;
+begin
+
+  f_pack_fifo_contents (fab_i, fifo_in, fifo_we, false);
+
+-- Clock adjustment FIFO
+  U_FIFO : generic_async_fifo
+    generic map (
+      g_data_width             => 18,
+      g_size                   => g_size,
+      g_with_wr_almost_full    => true,
+      g_almost_full_threshold  => g_almostfull_threshold
+      )
+    port map (
+      rst_n_i           => rst_n_wr_i,
+      clk_wr_i          => clk_wr_i,
+      d_i               => fifo_in,
+      we_i              => fifo_we,
+      wr_full_o         => full_o,
+      wr_almost_full_o  => almostfull_o,
+      clk_rd_i          => clk_rd_i,
+      q_o               => fifo_out,
+      rd_i              => rx_rdreq,
+      rd_empty_o        => empty_int);
+  
+
+  rx_rdreq <= (not empty_int) and dreq_i; -- and dreq_mask;
+
+
+  p_readout : process (clk_rd_i)
+  begin
+    if rising_edge(clk_rd_i) then
+      if(rst_n_rd_i = '0') then
+        valid_int <= '0';
+      else
+        valid_int <= rx_rdreq;
+      end if;
+    end if;
+  end process;
+
+  -- FIFO output data formatting
+  f_unpack_fifo_contents(fifo_out, valid_int, fab_int, false);
+
+  fab_o   <= fab_int;
+  empty_o <= empty_int;
+  
+end structural;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_crc32_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_crc32_pkg.vhd
new file mode 100644
index 000000000..c51f95827
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_crc32_pkg.vhd
@@ -0,0 +1,128 @@
+-------------------------------------------------------------------------------
+-- Title      : CRC32 package
+-- Project    : White Rabbit 
+-------------------------------------------------------------------------------
+-- File       : ep_crc32_pkg.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Platform   : FPGA-generic
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012-2013 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+package ep_crc32_pkg is
+
+
+  constant c_CRC32_RESIDUE_FULL : std_logic_vector(31 downto 0) := x"1cdf4421";
+  constant c_CRC32_RESIDUE_HALF : std_logic_vector(31 downto 0) := x"1df722c6";
+  constant c_CRC32_INIT_VALUE   : std_logic_vector(31 downto 0) := x"00000000";
+
+  function f_update_crc32_d16(d : std_logic_vector; data_in : std_logic_vector) return std_logic_vector;
+  function f_update_crc32_d8(d  : std_logic_vector(31 downto 0); data_in : std_logic_vector(7 downto 0)) return std_logic_vector;
+  
+end ep_crc32_pkg;
+
+package body ep_crc32_pkg is
+
+
+  function f_update_crc32_d16(d : std_logic_vector; data_in : std_logic_vector) return std_logic_vector is
+    variable q : std_logic_vector(d'length-1 downto 0);
+  begin
+    q(7)  := not ((not d(23)) xor (not d(17)) xor (not d(30)) xor (not d(29)) xor (not d(27)) xor data_in(7) xor data_in(1) xor data_in(14) xor data_in(13) xor data_in(11));
+    q(6)  := not ((not d(23)) xor (not d(22)) xor (not d(17)) xor (not d(16)) xor (not d(30)) xor (not d(28)) xor (not d(27)) xor (not d(26)) xor data_in(7) xor data_in(6) xor data_in(1) xor data_in(0) xor data_in(14) xor data_in(12) xor data_in(11) xor data_in(10));
+    q(5)  := not ((not d(23)) xor (not d(22)) xor (not d(21)) xor (not d(17)) xor (not d(16)) xor (not d(31)) xor (not d(30)) xor (not d(26)) xor (not d(25)) xor data_in(7) xor data_in(6) xor data_in(5) xor data_in(1) xor data_in(0) xor data_in(15) xor data_in(14) xor data_in(10) xor data_in(9));
+    q(4)  := not ((not d(22)) xor (not d(21)) xor (not d(20)) xor (not d(16)) xor (not d(31)) xor (not d(30)) xor (not d(29)) xor (not d(25)) xor (not d(24)) xor data_in(6) xor data_in(5) xor data_in(4) xor data_in(0) xor data_in(15) xor data_in(14) xor data_in(13) xor data_in(9) xor data_in(8));
+    q(3)  := not ((not d(23)) xor (not d(21)) xor (not d(20)) xor (not d(19)) xor (not d(17)) xor (not d(31)) xor (not d(28)) xor (not d(27)) xor (not d(24)) xor data_in(7) xor data_in(5) xor data_in(4) xor data_in(3) xor data_in(1) xor data_in(15) xor data_in(12) xor data_in(11) xor data_in(8));
+    q(2)  := not ((not d(23)) xor (not d(22)) xor (not d(20)) xor (not d(19)) xor (not d(18)) xor (not d(17)) xor (not d(16)) xor (not d(29)) xor (not d(26)) xor data_in(7) xor data_in(6) xor data_in(4) xor data_in(3) xor data_in(2) xor data_in(1) xor data_in(0) xor data_in(13) xor data_in(10));
+    q(1)  := not ((not d(22)) xor (not d(21)) xor (not d(19)) xor (not d(18)) xor (not d(17)) xor (not d(16)) xor (not d(31)) xor (not d(28)) xor (not d(25)) xor data_in(6) xor data_in(5) xor data_in(3) xor data_in(2) xor data_in(1) xor data_in(0) xor data_in(15) xor data_in(12) xor data_in(9));
+    q(0)  := not ((not d(23)) xor (not d(21)) xor (not d(20)) xor (not d(18)) xor (not d(16)) xor (not d(31)) xor (not d(29)) xor (not d(24)) xor data_in(7) xor data_in(5) xor data_in(4) xor data_in(2) xor data_in(0) xor data_in(15) xor data_in(13) xor data_in(8));
+    q(15) := not ((not d(23)) xor (not d(22)) xor (not d(20)) xor (not d(19)) xor (not d(31)) xor (not d(29)) xor (not d(28)) xor (not d(27)) xor data_in(7) xor data_in(6) xor data_in(4) xor data_in(3) xor data_in(15) xor data_in(13) xor data_in(12) xor data_in(11));
+    q(14) := not ((not d(22)) xor (not d(21)) xor (not d(19)) xor (not d(18)) xor (not d(30)) xor (not d(28)) xor (not d(27)) xor (not d(26)) xor data_in(6) xor data_in(5) xor data_in(3) xor data_in(2) xor data_in(14) xor data_in(12) xor data_in(11) xor data_in(10));
+    q(13) := not ((not d(23)) xor (not d(21)) xor (not d(20)) xor (not d(18)) xor (not d(30)) xor (not d(26)) xor (not d(25)) xor data_in(7) xor data_in(5) xor data_in(4) xor data_in(2) xor data_in(14) xor data_in(10) xor data_in(9));
+    q(12) := not ((not d(23)) xor (not d(22)) xor (not d(20)) xor (not d(19)) xor (not d(30)) xor (not d(27)) xor (not d(25)) xor (not d(24)) xor data_in(7) xor data_in(6) xor data_in(4) xor data_in(3) xor data_in(14) xor data_in(11) xor data_in(9) xor data_in(8));
+    q(11) := not ((not d(23)) xor (not d(22)) xor (not d(21)) xor (not d(19)) xor (not d(18)) xor (not d(17)) xor (not d(30)) xor (not d(27)) xor (not d(26)) xor (not d(24)) xor data_in(7) xor data_in(6) xor data_in(5) xor data_in(3) xor data_in(2) xor data_in(1) xor data_in(14) xor data_in(11) xor data_in(10) xor data_in(8));
+    q(10) := not ((not d(22)) xor (not d(21)) xor (not d(20)) xor (not d(18)) xor (not d(17)) xor (not d(16)) xor (not d(29)) xor (not d(26)) xor (not d(25)) xor data_in(6) xor data_in(5) xor data_in(4) xor data_in(2) xor data_in(1) xor data_in(0) xor data_in(13) xor data_in(10) xor data_in(9));
+    q(9)  := not ((not d(21)) xor (not d(20)) xor (not d(19)) xor (not d(17)) xor (not d(16)) xor (not d(31)) xor (not d(28)) xor (not d(25)) xor (not d(24)) xor data_in(5) xor data_in(4) xor data_in(3) xor data_in(1) xor data_in(0) xor data_in(15) xor data_in(12) xor data_in(9) xor data_in(8));
+    q(8)  := not ((not d(20)) xor (not d(19)) xor (not d(18)) xor (not d(16)) xor (not d(31)) xor (not d(30)) xor (not d(27)) xor (not d(24)) xor data_in(4) xor data_in(3) xor data_in(2) xor data_in(0) xor data_in(15) xor data_in(14) xor data_in(11) xor data_in(8));
+    q(23) := not ((not d(7)) xor (not d(23)) xor (not d(19)) xor (not d(18)) xor (not d(31)) xor (not d(27)) xor (not d(26)) xor data_in(7) xor data_in(3) xor data_in(2) xor data_in(15) xor data_in(11) xor data_in(10));
+    q(22) := not ((not d(6)) xor (not d(22)) xor (not d(18)) xor (not d(17)) xor (not d(30)) xor (not d(26)) xor (not d(25)) xor data_in(6) xor data_in(2) xor data_in(1) xor data_in(14) xor data_in(10) xor data_in(9));
+    q(21) := not ((not d(5)) xor (not d(21)) xor (not d(17)) xor (not d(16)) xor (not d(29)) xor (not d(25)) xor (not d(24)) xor data_in(5) xor data_in(1) xor data_in(0) xor data_in(13) xor data_in(9) xor data_in(8));
+    q(20) := not ((not d(4)) xor (not d(20)) xor (not d(16)) xor (not d(31)) xor (not d(28)) xor (not d(24)) xor data_in(4) xor data_in(0) xor data_in(15) xor data_in(12) xor data_in(8));
+    q(19) := not ((not d(3)) xor (not d(19)) xor (not d(31)) xor (not d(30)) xor (not d(27)) xor data_in(3) xor data_in(15) xor data_in(14) xor data_in(11));
+    q(18) := not ((not d(2)) xor (not d(18)) xor (not d(30)) xor (not d(29)) xor (not d(26)) xor data_in(2) xor data_in(14) xor data_in(13) xor data_in(10));
+    q(17) := not ((not d(1)) xor (not d(23)) xor (not d(30)) xor (not d(28)) xor (not d(27)) xor (not d(25)) xor data_in(7) xor data_in(14) xor data_in(12) xor data_in(11) xor data_in(9));
+    q(16) := not ((not d(0)) xor (not d(23)) xor (not d(22)) xor (not d(17)) xor (not d(30)) xor (not d(26)) xor (not d(24)) xor data_in(7) xor data_in(6) xor data_in(1) xor data_in(14) xor data_in(10) xor data_in(8));
+    q(31) := not ((not d(15)) xor (not d(22)) xor (not d(21)) xor (not d(16)) xor (not d(29)) xor (not d(25)) xor data_in(6) xor data_in(5) xor data_in(0) xor data_in(13) xor data_in(9));
+    q(30) := not ((not d(14)) xor (not d(21)) xor (not d(20)) xor (not d(31)) xor (not d(28)) xor (not d(24)) xor data_in(5) xor data_in(4) xor data_in(15) xor data_in(12) xor data_in(8));
+    q(29) := not ((not d(13)) xor (not d(23)) xor (not d(20)) xor (not d(19)) xor (not d(17)) xor (not d(29)) xor data_in(7) xor data_in(4) xor data_in(3) xor data_in(1) xor data_in(13));
+    q(28) := not ((not d(12)) xor (not d(22)) xor (not d(19)) xor (not d(18)) xor (not d(16)) xor (not d(28)) xor data_in(6) xor data_in(3) xor data_in(2) xor data_in(0) xor data_in(12));
+    q(27) := not ((not d(11)) xor (not d(21)) xor (not d(18)) xor (not d(17)) xor (not d(31)) xor (not d(27)) xor data_in(5) xor data_in(2) xor data_in(1) xor data_in(15) xor data_in(11));
+    q(26) := not ((not d(10)) xor (not d(20)) xor (not d(17)) xor (not d(16)) xor (not d(30)) xor (not d(26)) xor data_in(4) xor data_in(1) xor data_in(0) xor data_in(14) xor data_in(10));
+    q(25) := not ((not d(9)) xor (not d(19)) xor (not d(16)) xor (not d(31)) xor (not d(29)) xor (not d(25)) xor data_in(3) xor data_in(0) xor data_in(15) xor data_in(13) xor data_in(9));
+    q(24) := not ((not d(8)) xor (not d(18)) xor (not d(31)) xor (not d(30)) xor (not d(28)) xor (not d(24)) xor data_in(2) xor data_in(15) xor data_in(14) xor data_in(12) xor data_in(8));
+
+    return q;
+  end f_update_crc32_d16;
+
+
+  function f_update_crc32_d8(d : std_logic_vector(31 downto 0); data_in : std_logic_vector(7 downto 0)) return std_logic_vector is
+    variable q : std_logic_vector(31 downto 0);
+  begin
+    q(7)  := not ((not d(31)) xor (not d(25)) xor data_in(7) xor data_in(1));
+    q(6)  := not ((not d(31)) xor (not d(30)) xor (not d(25)) xor (not d(24)) xor data_in(7) xor data_in(6) xor data_in(1) xor data_in(0));
+    q(5)  := not ((not d(31)) xor (not d(30)) xor (not d(29)) xor (not d(25)) xor (not d(24)) xor data_in(7) xor data_in(6) xor data_in(5) xor data_in(1) xor data_in(0));
+    q(4)  := not ((not d(30)) xor (not d(29)) xor (not d(28)) xor (not d(24)) xor data_in(6) xor data_in(5) xor data_in(4) xor data_in(0));
+    q(3)  := not ((not d(31)) xor (not d(29)) xor (not d(28)) xor (not d(27)) xor (not d(25)) xor data_in(7) xor data_in(5) xor data_in(4) xor data_in(3) xor data_in(1));
+    q(2)  := not ((not d(31)) xor (not d(30)) xor (not d(28)) xor (not d(27)) xor (not d(26)) xor (not d(25)) xor (not d(24)) xor data_in(7) xor data_in(6) xor data_in(4) xor data_in(3) xor data_in(2) xor data_in(1) xor data_in(0));
+    q(1)  := not ((not d(30)) xor (not d(29)) xor (not d(27)) xor (not d(26)) xor (not d(25)) xor (not d(24)) xor data_in(6) xor data_in(5) xor data_in(3) xor data_in(2) xor data_in(1) xor data_in(0));
+    q(0)  := not ((not d(31)) xor (not d(29)) xor (not d(28)) xor (not d(26)) xor (not d(24)) xor data_in(7) xor data_in(5) xor data_in(4) xor data_in(2) xor data_in(0));
+    q(15) := not ((not d(7)) xor (not d(31)) xor (not d(30)) xor (not d(28)) xor (not d(27)) xor data_in(7) xor data_in(6) xor data_in(4) xor data_in(3));
+    q(14) := not ((not d(6)) xor (not d(30)) xor (not d(29)) xor (not d(27)) xor (not d(26)) xor data_in(6) xor data_in(5) xor data_in(3) xor data_in(2));
+    q(13) := not ((not d(5)) xor (not d(31)) xor (not d(29)) xor (not d(28)) xor (not d(26)) xor data_in(7) xor data_in(5) xor data_in(4) xor data_in(2));
+    q(12) := not ((not d(4)) xor (not d(31)) xor (not d(30)) xor (not d(28)) xor (not d(27)) xor data_in(7) xor data_in(6) xor data_in(4) xor data_in(3));
+    q(11) := not ((not d(3)) xor (not d(31)) xor (not d(30)) xor (not d(29)) xor (not d(27)) xor (not d(26)) xor (not d(25)) xor data_in(7) xor data_in(6) xor data_in(5) xor data_in(3) xor data_in(2) xor data_in(1));
+    q(10) := not ((not d(2)) xor (not d(30)) xor (not d(29)) xor (not d(28)) xor (not d(26)) xor (not d(25)) xor (not d(24)) xor data_in(6) xor data_in(5) xor data_in(4) xor data_in(2) xor data_in(1) xor data_in(0));
+    q(9)  := not ((not d(1)) xor (not d(29)) xor (not d(28)) xor (not d(27)) xor (not d(25)) xor (not d(24)) xor data_in(5) xor data_in(4) xor data_in(3) xor data_in(1) xor data_in(0));
+    q(8)  := not ((not d(0)) xor (not d(28)) xor (not d(27)) xor (not d(26)) xor (not d(24)) xor data_in(4) xor data_in(3) xor data_in(2) xor data_in(0));
+    q(23) := not ((not d(15)) xor (not d(31)) xor (not d(27)) xor (not d(26)) xor data_in(7) xor data_in(3) xor data_in(2));
+    q(22) := not ((not d(14)) xor (not d(30)) xor (not d(26)) xor (not d(25)) xor data_in(6) xor data_in(2) xor data_in(1));
+    q(21) := not ((not d(13)) xor (not d(29)) xor (not d(25)) xor (not d(24)) xor data_in(5) xor data_in(1) xor data_in(0));
+    q(20) := not ((not d(12)) xor (not d(28)) xor (not d(24)) xor data_in(4) xor data_in(0));
+    q(19) := not ((not d(11)) xor (not d(27)) xor data_in(3));
+    q(18) := not ((not d(10)) xor (not d(26)) xor data_in(2));
+    q(17) := not ((not d(9)) xor (not d(31)) xor data_in(7));
+    q(16) := not ((not d(8)) xor (not d(31)) xor (not d(30)) xor (not d(25)) xor data_in(7) xor data_in(6) xor data_in(1));
+    q(31) := not ((not d(23)) xor (not d(30)) xor (not d(29)) xor (not d(24)) xor data_in(6) xor data_in(5) xor data_in(0));
+    q(30) := not ((not d(22)) xor (not d(29)) xor (not d(28)) xor data_in(5) xor data_in(4));
+    q(29) := not ((not d(21)) xor (not d(31)) xor (not d(28)) xor (not d(27)) xor (not d(25)) xor data_in(7) xor data_in(4) xor data_in(3) xor data_in(1));
+    q(28) := not ((not d(20)) xor (not d(30)) xor (not d(27)) xor (not d(26)) xor (not d(24)) xor data_in(6) xor data_in(3) xor data_in(2) xor data_in(0));
+    q(27) := not ((not d(19)) xor (not d(29)) xor (not d(26)) xor (not d(25)) xor data_in(5) xor data_in(2) xor data_in(1));
+    q(26) := not ((not d(18)) xor (not d(28)) xor (not d(25)) xor (not d(24)) xor data_in(4) xor data_in(1) xor data_in(0));
+    q(25) := not ((not d(17)) xor (not d(27)) xor (not d(24)) xor data_in(3) xor data_in(0));
+    q(24) := not ((not d(16)) xor (not d(26)) xor data_in(2));
+    return q;
+  end f_update_crc32_d8;
+end ep_crc32_pkg;
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_leds_controller.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_leds_controller.vhd
new file mode 100644
index 000000000..28582fb52
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_leds_controller.vhd
@@ -0,0 +1,129 @@
+-------------------------------------------------------------------------------
+-- Title      : Endpoint LEDs controller
+-- Project    : White Rabbit 
+-------------------------------------------------------------------------------
+-- File       : ep_leds_controller.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Platform   : FPGA-generic
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012 - 2017 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.endpoint_private_pkg.all;
+use work.gencores_pkg.all;
+
+entity ep_leds_controller is
+  
+  generic (
+    g_blink_period_log2 : integer := 21);
+
+  port (
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    -- data valid (from PCS <> framers)
+    dvalid_tx_i : in std_logic;
+    dvalid_rx_i : in std_logic;
+
+    link_ok_i : in std_logic;
+
+    led_link_o : out std_logic;
+    led_act_o  : out std_logic
+    );  
+
+end ep_leds_controller;
+
+architecture rtl of ep_leds_controller is
+
+  type t_state is (INACTIVE, BLINKING);
+
+  signal cnt                    : unsigned(g_blink_period_log2-1 downto 0);
+  signal cnt_reset, cnt_expired : std_logic;
+  signal state                  : t_state;
+  signal led_act                : std_logic;
+  signal last_cycle_act         : std_logic;
+  signal txrx                   : std_logic;
+begin  -- rtl
+
+  led_link_o <= link_ok_i;
+
+  txrx <= dvalid_rx_i or dvalid_tx_i;
+
+  p_counter : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      
+      if(rst_n_i = '0' or cnt_reset = '1')then
+        cnt <= (others => '0');
+      else
+        cnt <= cnt + 1;
+        if((not cnt) = 0) then
+          cnt_expired <= '1';
+        else
+          cnt_expired <= '0';
+        end if;
+      end if;
+    end if;
+  end process;
+
+  p_gen_act_led : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        state     <= INACTIVE;
+        led_act   <= '0';
+        cnt_reset <= '0';
+      else
+        case state is
+          when INACTIVE =>
+            if(txrx = '1') then
+              state     <= BLINKING;
+              led_act   <= '1';
+              cnt_reset <= '1';
+            end if;
+          when BLINKING =>
+            cnt_reset <= '0';
+            if(cnt_expired = '1') then
+              led_act <= not led_act;
+              if(last_cycle_act = '0') then
+                led_act <= '0';
+                state   <= INACTIVE;
+              end if;
+              last_cycle_act <= '0';
+            else
+              if(txrx = '1') then
+                last_cycle_act <= '1';
+              end if;
+            end if;
+        end case;
+      end if;
+    end if;
+  end process;
+
+  led_act_o <= led_act;
+  
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_packet_filter.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_packet_filter.vhd
new file mode 100644
index 000000000..79b4c4cbd
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_packet_filter.vhd
@@ -0,0 +1,371 @@
+-------------------------------------------------------------------------------
+-- Title      : Programmable Packet Filter/Inspector
+-- Project    : White Rabbit MAC/Endpoint
+-------------------------------------------------------------------------------
+-- File       : ep_packet_filter.vhd
+-- Author     : Tomasz Włostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2010-11-18
+-- Last update: 2017-02-02
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: A simple packet inspection CPU, capable of classifying incoming
+-- packets to 8 different packet classes. The microcode format and programming
+-- constaints are described in detail in the Endpoint's manual.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2011-2017 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1l.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.gencores_pkg.all;
+use work.genram_pkg.all;
+use work.endpoint_private_pkg.all;
+use work.endpoint_pkg.all;
+use work.ep_wbgen2_pkg.all;
+
+entity ep_packet_filter is
+
+  port (
+    clk_rx_i    : in std_logic;
+    clk_sys_i   : in std_logic;
+    rst_n_rx_i  : in std_logic;
+    rst_n_sys_i : in std_logic;
+
+    snk_fab_i : in  t_ep_internal_fabric;
+    src_fab_o : out t_ep_internal_fabric;
+
+    done_o   : out std_logic;
+    pclass_o : out std_logic_vector(7 downto 0);
+    drop_o   : out std_logic;
+
+    regs_i : in t_ep_out_registers
+    );
+
+end ep_packet_filter;
+
+architecture behavioral of ep_packet_filter is
+
+  constant c_PC_SIZE : integer := 6;
+
+  constant c_MODE_LOGIC   : std_logic := '1';
+  constant c_MODE_COMPARE : std_logic := '0';
+
+  type t_microcode_instruction is record
+    fin       : std_logic;
+    mode      : std_logic;
+    cmp_bit   : std_logic;
+    cmp_mask  : std_logic_vector(3 downto 0);
+    cmp_value : std_logic_vector(15 downto 0);
+    offset    : std_logic_vector(5 downto 0);
+    op        : std_logic_vector(2 downto 0);
+    op2       : std_logic_vector(2 downto 0);
+
+    rd : std_logic_vector(4 downto 0);
+    ra : std_logic_vector(4 downto 0);
+    rb : std_logic_vector(4 downto 0);
+    rc : std_logic_vector(4 downto 0);
+  end record;
+
+  function f_decode_insn
+    (ir           : std_logic_vector) return t_microcode_instruction is
+    variable insn : t_microcode_instruction;
+  begin
+    insn.fin            := ir(35);
+    insn.mode           := ir(34);
+    insn.cmp_bit        := ir(33);
+    insn.cmp_mask       := ir(32 downto 29);
+    insn.cmp_value      := ir(28 downto 13);
+    insn.offset         := ir(12 downto 7);
+    insn.rd(3 downto 0) := ir(6 downto 3);
+    insn.op             := ir(2 downto 0);
+    insn.rd(4)          := ir(34) and ir(7);
+    insn.ra             := ir(12 downto 8);
+    insn.rb             := ir(17 downto 13);
+    insn.rc             := ir(22 downto 18);
+    insn.op2            := ir(25 downto 23);
+    return insn;
+  end f_decode_insn;
+
+  function f_eval
+    (
+      a, b : std_logic;
+      op   : std_logic_vector
+      ) return std_logic is
+    variable r    : std_logic;
+    variable op_t : std_logic_vector(2 downto 0);
+  begin
+    op_t := op;
+    case op_t is
+      when "000"  => r := a and b;
+      when "100"  => r := a nand b;
+      when "001"  => r := a or b;
+      when "101"  => r := a nor b;
+      when "010"  => r := a xor b;
+      when "110"  => r := a xnor b;
+      when "011"  => r := a;
+      when "111"  => r := not a;
+      when others => null;
+    end case;
+    return r;
+  end f_eval;
+
+  function f_pick_reg(regs : std_logic_vector; index : std_logic_vector)return std_logic is
+    variable idx_int : integer;
+  begin
+    idx_int := to_integer(unsigned(index));
+    return regs(idx_int);
+  end f_pick_reg;
+
+
+
+  signal pc              : unsigned(c_PC_SIZE-1 downto 0);
+  signal ir, ir_d        : std_logic_vector(35 downto 0);
+  signal insn, insn_d    : t_microcode_instruction;
+  signal insn_predecoded : t_microcode_instruction;
+
+  signal done_int : std_logic;
+  signal regs     : std_logic_vector(31 downto 0);
+
+  signal result_cmp : std_logic;
+  signal mask       : std_logic_vector(15 downto 0);
+
+  signal ra, rb, rc, result1, result2, rd : std_logic;
+
+  signal pmem_rdata : std_logic_vector(15 downto 0);
+
+  signal mm_write           : std_logic;
+  signal mm_rdata, mm_wdata : std_logic_vector(35 downto 0);
+
+  type t_state is (WAIT_FRAME, PROCESS_FRAME, GEN_OUTPUT);
+
+  signal stage1, stage2, stage3 : std_logic;
+  signal r_pfcr1_mm_data_lsb : std_logic_vector(11 downto 0);
+
+  signal pfcr0_enable_rxclk : std_logic;
+
+begin  -- behavioral
+
+  U_sync_pfcr0_enable : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_rx_i,
+      rst_n_i  => '1',
+      data_i   => regs_i.pfcr0_enable_o,
+      synced_o => pfcr0_enable_rxclk,
+      npulse_o => open,
+      ppulse_o => open);
+
+  process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if(regs_i.pfcr1_mm_data_lsb_wr_o = '1') then
+        r_pfcr1_mm_data_lsb <= regs_i.pfcr1_mm_data_lsb_o;
+      end if;
+    end if;
+  end process;
+
+
+  mm_write <= not regs_i.pfcr0_enable_o and regs_i.pfcr0_mm_write_o and regs_i.pfcr0_mm_write_wr_o;
+  mm_wdata <= regs_i.pfcr0_mm_data_msb_o & r_pfcr1_mm_data_lsb;
+
+  U_microcode_ram : generic_dpram
+    generic map (
+      g_data_width => 36,
+      g_size       => 2**c_PC_SIZE,
+      g_dual_clock => true)
+    port map (
+      rst_n_i => rst_n_sys_i,
+      clka_i  => clk_rx_i,
+      bwea_i  => "00000",
+      wea_i   => '0',
+      aa_i    => std_logic_vector(pc),
+      da_i    => x"000000000",
+      qa_o    => mm_rdata,
+      clkb_i  => clk_sys_i,
+      bweb_i  => "11111",
+      web_i   => mm_write,
+      ab_i    => regs_i.pfcr0_mm_addr_o,
+      db_i    => mm_wdata
+      );
+
+
+
+  U_backlog_ram : generic_dpram
+    generic map (
+      g_data_width       => 16,
+      g_size             => 2**c_PC_SIZE,
+      g_with_byte_enable => false,
+      g_dual_clock       => false)
+    port map (
+      rst_n_i => rst_n_rx_i,
+      clka_i  => clk_rx_i,
+      bwea_i  => "11",
+      wea_i   => snk_fab_i.dvalid,
+      aa_i    => std_logic_vector(pc),
+      da_i    => snk_fab_i.data,
+      qa_o    => open,
+      clkb_i  => clk_rx_i,
+      bweb_i  => "00",
+      web_i   => '0',
+      ab_i    => insn_predecoded.offset,
+      db_i    => x"0000",
+      qb_o    => pmem_rdata);
+
+  insn_predecoded <= f_decode_insn(mm_rdata);
+
+  src_fab_o <= snk_fab_i;
+
+  p_pc_counter : process(clk_rx_i)
+  begin
+    if rising_edge(clk_rx_i) then
+      if rst_n_rx_i = '0' or snk_fab_i.eof = '1' or snk_fab_i.error = '1' or done_int = '1' then
+        pc     <= (others => '0');
+        stage1 <= '0';
+      elsif(snk_fab_i.dvalid = '1') then
+        pc     <= pc + 1;
+        stage1 <= '1';
+      else
+        stage1 <= '0';
+      end if;
+    end if;
+  end process;
+
+  p_stage2 : process(clk_rx_i)
+  begin
+    if rising_edge(clk_rx_i) then
+      if rst_n_rx_i = '0' or done_int = '1' or snk_fab_i.error = '1' then
+        stage2 <= '0';
+        ir     <= (others => '0');
+      else
+        stage2 <= stage1;
+        ir     <= mm_rdata;
+      end if;
+    end if;
+  end process;
+
+  p_gen_mask : process(insn)
+  begin
+    if(insn.cmp_bit = '0') then
+      mask <= (3 downto 0   => insn.cmp_mask(0),
+               7 downto 4   => insn.cmp_mask(1),
+               11 downto 8  => insn.cmp_mask(2),
+               15 downto 12 => insn.cmp_mask(3));
+    else
+      case insn.cmp_mask is
+        when x"0"   => mask <= x"0001";
+        when x"1"   => mask <= x"0002";
+        when x"2"   => mask <= x"0004";
+        when x"3"   => mask <= x"0008";
+        when x"4"   => mask <= x"0010";
+        when x"5"   => mask <= x"0020";
+        when x"6"   => mask <= x"0040";
+        when x"7"   => mask <= x"0080";
+        when x"8"   => mask <= x"0100";
+        when x"9"   => mask <= x"0200";
+        when x"a"   => mask <= x"0400";
+        when x"b"   => mask <= x"0800";
+        when x"c"   => mask <= x"1000";
+        when x"d"   => mask <= x"2000";
+        when x"e"   => mask <= x"4000";
+        when x"f"   => mask <= x"8000";
+        when others => mask <= (others => 'X');
+      end case;
+    end if;
+  end process;
+
+  p_compare : process(clk_rx_i)
+  begin
+    if rising_edge(clk_rx_i) then
+      if stage2 = '1' then
+        stage3 <= '1';
+        ir_d   <= ir;
+        if (((pmem_rdata and mask) = insn.cmp_value)) then
+          result_cmp <= '1';
+        else
+          result_cmp <= '0';
+        end if;
+
+      else
+        stage3 <= '0';
+      end if;
+    end if;
+  end process;
+
+  insn <= f_decode_insn(ir);
+  insn_d <= f_decode_insn(ir_d);
+  ra     <= f_pick_reg(regs, insn_d.ra) when insn_d.mode = c_MODE_LOGIC else result_cmp;
+  rb     <= f_pick_reg(regs, insn_d.rb) when insn_d.mode = c_MODE_LOGIC else f_pick_reg(regs, insn_d.rd);
+  rc     <= f_pick_reg(regs, insn_d.rc);
+
+  result1 <= f_eval(ra, rb, insn_d.op);
+  result2 <= f_eval(result1, rc, insn_d.op2);
+
+  rd <= result2 when insn_d.mode = c_MODE_LOGIC else result1;
+
+
+  p_execute : process(clk_rx_i)
+  begin
+    if rising_edge(clk_rx_i) then
+      if rst_n_rx_i = '0' or snk_fab_i.eof = '1' or snk_fab_i.error = '1' or done_int = '1' then
+        regs <= (others => '0');
+      else
+        if(stage3 = '1') then
+          regs(to_integer(unsigned(insn_d.rd))) <= rd;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  p_gen_status : process(clk_rx_i)
+  begin
+    if rising_edge(clk_rx_i) then
+      if (rst_n_rx_i = '0' or snk_fab_i.sof = '1') then
+        done_int <= '0';
+        drop_o   <= '0';
+      else
+        if(pfcr0_enable_rxclk = '0') then
+          done_int <= '0';
+          drop_o   <= '0';
+          pclass_o <= (others => '0');
+        elsif( (stage3 = '1' and insn_d.fin = '1') or
+               ((snk_fab_i.error = '1' or snk_fab_i.eof = '1') and done_int = '0') ) then
+          done_int <= '1';
+          pclass_o <= regs(31 downto 24);
+          drop_o   <= regs(23);
+        end if;
+      end if;
+    end if;
+  end process;
+
+  U_Sync_Done : gc_pulse_synchronizer
+    port map (
+      clk_in_i  => clk_rx_i,
+      clk_out_i => clk_sys_i,
+      rst_n_i   => rst_n_rx_i,
+      d_p_i     => done_int,
+      q_p_o     => done_o);
+
+end behavioral;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd
new file mode 100644
index 000000000..f94b29b11
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd
@@ -0,0 +1,627 @@
+---------------------------------------------------------------------------------------
+-- Title          : Wishbone slave core for WR Endpoint 1000base-X TBI PCS register block
+---------------------------------------------------------------------------------------
+-- File           : ep_pcs_tbi_mdio_wb.vhd
+-- Author         : auto-generated by wbgen2 from pcs_regs.wb
+-- Created        : Wed Aug 16 22:43:42 2017
+-- Standard       : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pcs_regs.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity ep_pcs_tbi_mdio_wb is
+  port (
+    rst_n_i                                  : in     std_logic;
+    clk_sys_i                                : in     std_logic;
+    wb_adr_i                                 : in     std_logic_vector(4 downto 0);
+    wb_dat_i                                 : in     std_logic_vector(31 downto 0);
+    wb_dat_o                                 : out    std_logic_vector(31 downto 0);
+    wb_cyc_i                                 : in     std_logic;
+    wb_sel_i                                 : in     std_logic_vector(3 downto 0);
+    wb_stb_i                                 : in     std_logic;
+    wb_we_i                                  : in     std_logic;
+    wb_ack_o                                 : out    std_logic;
+    wb_stall_o                               : out    std_logic;
+    tx_clk_i                                 : in     std_logic;
+    rx_clk_i                                 : in     std_logic;
+-- Port for BIT field: 'Unidirectional Enable' in reg: 'MDIO Control Register'
+    mdio_mcr_uni_en_o                        : out    std_logic;
+-- Port for MONOSTABLE field: 'Restart Auto-Negotiation' in reg: 'MDIO Control Register'
+    mdio_mcr_anrestart_o                     : out    std_logic;
+-- Port for BIT field: 'Power Down' in reg: 'MDIO Control Register'
+    mdio_mcr_pdown_o                         : out    std_logic;
+-- Port for BIT field: 'Auto-Negotiation Enable' in reg: 'MDIO Control Register'
+    mdio_mcr_anenable_o                      : out    std_logic;
+-- Port for BIT field: 'Loopback' in reg: 'MDIO Control Register'
+    mdio_mcr_loopback_o                      : out    std_logic;
+-- Port for MONOSTABLE field: 'Reset' in reg: 'MDIO Control Register'
+    mdio_mcr_reset_o                         : out    std_logic;
+-- Port for BIT field: 'Link Status' in reg: 'MDIO Status Register'
+    mdio_msr_lstatus_i                       : in     std_logic;
+    lstat_read_notify_o                      : out    std_logic;
+-- Port for BIT field: 'Remote Fault' in reg: 'MDIO Status Register'
+    mdio_msr_rfault_i                        : in     std_logic;
+-- Port for BIT field: 'Auto-Negotiation Complete' in reg: 'MDIO Status Register'
+    mdio_msr_anegcomplete_i                  : in     std_logic;
+-- Port for std_logic_vector field: 'Pause' in reg: 'MDIO Auto-Negotiation Advertisement Register'
+    mdio_advertise_pause_o                   : out    std_logic_vector(1 downto 0);
+-- Port for std_logic_vector field: 'Remote Fault' in reg: 'MDIO Auto-Negotiation Advertisement Register'
+    mdio_advertise_rfault_o                  : out    std_logic_vector(1 downto 0);
+-- Port for BIT field: 'Full Duplex' in reg: 'MDIO Auto-Negotiation Link Partner Ability Register'
+    mdio_lpa_full_i                          : in     std_logic;
+-- Port for BIT field: 'Half Duplex' in reg: 'MDIO Auto-Negotiation Link Partner Ability Register'
+    mdio_lpa_half_i                          : in     std_logic;
+-- Port for std_logic_vector field: 'Pause' in reg: 'MDIO Auto-Negotiation Link Partner Ability Register'
+    mdio_lpa_pause_i                         : in     std_logic_vector(1 downto 0);
+-- Port for std_logic_vector field: 'Remote Fault' in reg: 'MDIO Auto-Negotiation Link Partner Ability Register'
+    mdio_lpa_rfault_i                        : in     std_logic_vector(1 downto 0);
+-- Port for BIT field: 'Acknowledge' in reg: 'MDIO Auto-Negotiation Link Partner Ability Register'
+    mdio_lpa_lpack_i                         : in     std_logic;
+-- Port for BIT field: 'Next Page' in reg: 'MDIO Auto-Negotiation Link Partner Ability Register'
+    mdio_lpa_npage_i                         : in     std_logic;
+-- Port for asynchronous (clock: tx_clk_i) BIT field: 'TX Calibration Pattern' in reg: 'WhiteRabbit-specific Configuration Register'
+    mdio_wr_spec_tx_cal_o                    : out    std_logic;
+-- Port for asynchronous (clock: rx_clk_i) BIT field: 'Calibration Pattern RX Status' in reg: 'WhiteRabbit-specific Configuration Register'
+    mdio_wr_spec_rx_cal_stat_i               : in     std_logic;
+-- Port for asynchronous (clock: rx_clk_i) MONOSTABLE field: 'Reset calibration counter' in reg: 'WhiteRabbit-specific Configuration Register'
+    mdio_wr_spec_cal_crst_o                  : out    std_logic;
+-- Port for asynchronous (clock: rx_clk_i) std_logic_vector field: 'GTP RX Bitslide' in reg: 'WhiteRabbit-specific Configuration Register'
+    mdio_wr_spec_bslide_i                    : in     std_logic_vector(4 downto 0);
+-- Port for std_logic_vector field: 'Loopback - detailed' in reg: 'MDIO Extended Control Register'
+    mdio_ectrl_lpbck_vec_o                   : out    std_logic_vector(2 downto 0);
+-- Port for BIT field: 'SFP TX Fault Status' in reg: 'MDIO Extended Control Register'
+    mdio_ectrl_sfp_tx_fault_i                : in     std_logic;
+-- Port for BIT field: 'SFP LOS' in reg: 'MDIO Extended Control Register'
+    mdio_ectrl_sfp_loss_i                    : in     std_logic;
+-- Port for BIT field: 'SFP TX Disable' in reg: 'MDIO Extended Control Register'
+    mdio_ectrl_sfp_tx_disable_o              : out    std_logic;
+-- Port for std_logic_vector field: 'tx_prbs_sel' in reg: 'MDIO Extended Control Register'
+    mdio_ectrl_tx_prbs_sel_o                 : out    std_logic_vector(2 downto 0)
+  );
+end ep_pcs_tbi_mdio_wb;
+
+architecture syn of ep_pcs_tbi_mdio_wb is
+
+signal mdio_mcr_uni_en_int                      : std_logic      ;
+signal mdio_mcr_anrestart_dly0                  : std_logic      ;
+signal mdio_mcr_anrestart_int                   : std_logic      ;
+signal mdio_mcr_pdown_int                       : std_logic      ;
+signal mdio_mcr_anenable_int                    : std_logic      ;
+signal mdio_mcr_loopback_int                    : std_logic      ;
+signal mdio_mcr_reset_dly0                      : std_logic      ;
+signal mdio_mcr_reset_int                       : std_logic      ;
+signal mdio_advertise_pause_int                 : std_logic_vector(1 downto 0);
+signal mdio_advertise_rfault_int                : std_logic_vector(1 downto 0);
+signal mdio_wr_spec_tx_cal_int                  : std_logic      ;
+signal mdio_wr_spec_tx_cal_sync0                : std_logic      ;
+signal mdio_wr_spec_tx_cal_sync1                : std_logic      ;
+signal mdio_wr_spec_rx_cal_stat_sync0           : std_logic      ;
+signal mdio_wr_spec_rx_cal_stat_sync1           : std_logic      ;
+signal mdio_wr_spec_cal_crst_int                : std_logic      ;
+signal mdio_wr_spec_cal_crst_int_delay          : std_logic      ;
+signal mdio_wr_spec_cal_crst_sync0              : std_logic      ;
+signal mdio_wr_spec_cal_crst_sync1              : std_logic      ;
+signal mdio_wr_spec_cal_crst_sync2              : std_logic      ;
+signal mdio_wr_spec_bslide_int                  : std_logic_vector(4 downto 0);
+signal mdio_wr_spec_bslide_lwb                  : std_logic      ;
+signal mdio_wr_spec_bslide_lwb_delay            : std_logic      ;
+signal mdio_wr_spec_bslide_lwb_in_progress      : std_logic      ;
+signal mdio_wr_spec_bslide_lwb_s0               : std_logic      ;
+signal mdio_wr_spec_bslide_lwb_s1               : std_logic      ;
+signal mdio_wr_spec_bslide_lwb_s2               : std_logic      ;
+signal mdio_ectrl_lpbck_vec_int                 : std_logic_vector(2 downto 0);
+signal mdio_ectrl_sfp_tx_disable_int            : std_logic      ;
+signal mdio_ectrl_tx_prbs_sel_int               : std_logic_vector(2 downto 0);
+signal ack_sreg                                 : std_logic_vector(9 downto 0);
+signal rddata_reg                               : std_logic_vector(31 downto 0);
+signal wrdata_reg                               : std_logic_vector(31 downto 0);
+signal rwaddr_reg                               : std_logic_vector(4 downto 0);
+signal ack_in_progress                          : std_logic      ;
+
+begin
+-- Some internal signals assignments
+  wrdata_reg <= wb_dat_i;
+-- 
+-- Main register bank access process.
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ack_sreg <= "0000000000";
+      ack_in_progress <= '0';
+      rddata_reg <= "00000000000000000000000000000000";
+      mdio_mcr_uni_en_int <= '0';
+      mdio_mcr_anrestart_int <= '0';
+      mdio_mcr_pdown_int <= '0';
+      mdio_mcr_anenable_int <= '0';
+      mdio_mcr_loopback_int <= '0';
+      mdio_mcr_reset_int <= '0';
+      lstat_read_notify_o <= '0';
+      mdio_advertise_pause_int <= "00";
+      mdio_advertise_rfault_int <= "00";
+      mdio_wr_spec_tx_cal_int <= '0';
+      mdio_wr_spec_cal_crst_int <= '0';
+      mdio_wr_spec_cal_crst_int_delay <= '0';
+      mdio_wr_spec_bslide_lwb <= '0';
+      mdio_wr_spec_bslide_lwb_delay <= '0';
+      mdio_wr_spec_bslide_lwb_in_progress <= '0';
+      mdio_ectrl_lpbck_vec_int <= "000";
+      mdio_ectrl_sfp_tx_disable_int <= '0';
+      mdio_ectrl_tx_prbs_sel_int <= "000";
+    elsif rising_edge(clk_sys_i) then
+-- advance the ACK generator shift register
+      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
+      ack_sreg(9) <= '0';
+      if (ack_in_progress = '1') then
+        if (ack_sreg(0) = '1') then
+          mdio_mcr_anrestart_int <= '0';
+          mdio_mcr_reset_int <= '0';
+          lstat_read_notify_o <= '0';
+          ack_in_progress <= '0';
+        else
+          mdio_wr_spec_cal_crst_int <= mdio_wr_spec_cal_crst_int_delay;
+          mdio_wr_spec_cal_crst_int_delay <= '0';
+          mdio_wr_spec_bslide_lwb <= mdio_wr_spec_bslide_lwb_delay;
+          mdio_wr_spec_bslide_lwb_delay <= '0';
+          if ((ack_sreg(1) = '1') and (mdio_wr_spec_bslide_lwb_in_progress = '1')) then
+            rddata_reg(8 downto 4) <= mdio_wr_spec_bslide_int;
+            mdio_wr_spec_bslide_lwb_in_progress <= '0';
+          end if;
+        end if;
+      else
+        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
+          case rwaddr_reg(4 downto 0) is
+          when "00000" => 
+            if (wb_we_i = '1') then
+              mdio_mcr_uni_en_int <= wrdata_reg(5);
+              mdio_mcr_anrestart_int <= wrdata_reg(9);
+              mdio_mcr_pdown_int <= wrdata_reg(11);
+              mdio_mcr_anenable_int <= wrdata_reg(12);
+              mdio_mcr_loopback_int <= wrdata_reg(14);
+              mdio_mcr_reset_int <= wrdata_reg(15);
+            end if;
+            rddata_reg(4 downto 0) <= "00000";
+            rddata_reg(5) <= mdio_mcr_uni_en_int;
+            rddata_reg(6) <= '1';
+            rddata_reg(7) <= '0';
+            rddata_reg(8) <= '1';
+            rddata_reg(9) <= '0';
+            rddata_reg(10) <= '0';
+            rddata_reg(11) <= mdio_mcr_pdown_int;
+            rddata_reg(12) <= mdio_mcr_anenable_int;
+            rddata_reg(13) <= '0';
+            rddata_reg(14) <= mdio_mcr_loopback_int;
+            rddata_reg(15) <= '0';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(2) <= '1';
+            ack_in_progress <= '1';
+          when "00001" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(0) <= '0';
+            rddata_reg(1) <= '0';
+            rddata_reg(2) <= mdio_msr_lstatus_i;
+            lstat_read_notify_o <= '1';
+            rddata_reg(3) <= '1';
+            rddata_reg(4) <= mdio_msr_rfault_i;
+            rddata_reg(5) <= mdio_msr_anegcomplete_i;
+            rddata_reg(6) <= '0';
+            rddata_reg(7) <= '1';
+            rddata_reg(8) <= '1';
+            rddata_reg(9) <= '0';
+            rddata_reg(10) <= '0';
+            rddata_reg(11) <= '0';
+            rddata_reg(12) <= '0';
+            rddata_reg(13) <= '0';
+            rddata_reg(14) <= '0';
+            rddata_reg(15) <= '0';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00010" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(15 downto 0) <= "0000000000000000";
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00011" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(3 downto 0) <= "0000";
+            rddata_reg(9 downto 4) <= "000000";
+            rddata_reg(15 downto 10) <= "000000";
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00100" => 
+            if (wb_we_i = '1') then
+              mdio_advertise_pause_int <= wrdata_reg(8 downto 7);
+              mdio_advertise_rfault_int <= wrdata_reg(13 downto 12);
+            end if;
+            rddata_reg(4 downto 0) <= "00000";
+            rddata_reg(5) <= '1';
+            rddata_reg(6) <= '0';
+            rddata_reg(8 downto 7) <= mdio_advertise_pause_int;
+            rddata_reg(11 downto 9) <= "000";
+            rddata_reg(13 downto 12) <= mdio_advertise_rfault_int;
+            rddata_reg(14) <= '0';
+            rddata_reg(15) <= '0';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00101" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(4 downto 0) <= "00000";
+            rddata_reg(5) <= mdio_lpa_full_i;
+            rddata_reg(6) <= mdio_lpa_half_i;
+            rddata_reg(8 downto 7) <= mdio_lpa_pause_i;
+            rddata_reg(11 downto 9) <= "000";
+            rddata_reg(13 downto 12) <= mdio_lpa_rfault_i;
+            rddata_reg(14) <= mdio_lpa_lpack_i;
+            rddata_reg(15) <= mdio_lpa_npage_i;
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00110" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(0) <= '0';
+            rddata_reg(1) <= '0';
+            rddata_reg(2) <= '0';
+            rddata_reg(15 downto 3) <= "0000000000000";
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01111" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(11 downto 0) <= "000000000000";
+            rddata_reg(12) <= '0';
+            rddata_reg(13) <= '0';
+            rddata_reg(14) <= '0';
+            rddata_reg(15) <= '1';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "10000" => 
+            if (wb_we_i = '1') then
+              mdio_wr_spec_tx_cal_int <= wrdata_reg(0);
+              mdio_wr_spec_cal_crst_int <= wrdata_reg(2);
+              mdio_wr_spec_cal_crst_int_delay <= wrdata_reg(2);
+            end if;
+            rddata_reg(0) <= mdio_wr_spec_tx_cal_int;
+            rddata_reg(1) <= mdio_wr_spec_rx_cal_stat_sync1;
+            rddata_reg(2) <= '0';
+            if (wb_we_i = '0') then
+              mdio_wr_spec_bslide_lwb <= '1';
+              mdio_wr_spec_bslide_lwb_delay <= '1';
+              mdio_wr_spec_bslide_lwb_in_progress <= '1';
+            end if;
+            rddata_reg(3) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(5) <= '1';
+            ack_in_progress <= '1';
+          when "10001" => 
+            if (wb_we_i = '1') then
+              mdio_ectrl_lpbck_vec_int <= wrdata_reg(2 downto 0);
+              mdio_ectrl_sfp_tx_disable_int <= wrdata_reg(5);
+              mdio_ectrl_tx_prbs_sel_int <= wrdata_reg(10 downto 8);
+            end if;
+            rddata_reg(2 downto 0) <= mdio_ectrl_lpbck_vec_int;
+            rddata_reg(3) <= mdio_ectrl_sfp_tx_fault_i;
+            rddata_reg(4) <= mdio_ectrl_sfp_loss_i;
+            rddata_reg(5) <= mdio_ectrl_sfp_tx_disable_int;
+            rddata_reg(10 downto 8) <= mdio_ectrl_tx_prbs_sel_int;
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when others =>
+-- prevent the slave from hanging the bus on invalid address
+            ack_in_progress <= '1';
+            ack_sreg(0) <= '1';
+          end case;
+        end if;
+      end if;
+    end if;
+  end process;
+  
+  
+-- Drive the data output bus
+  wb_dat_o <= rddata_reg;
+-- Unidirectional Enable
+  mdio_mcr_uni_en_o <= mdio_mcr_uni_en_int;
+-- Restart Auto-Negotiation
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      mdio_mcr_anrestart_dly0 <= '0';
+      mdio_mcr_anrestart_o <= '0';
+    elsif rising_edge(clk_sys_i) then
+      mdio_mcr_anrestart_dly0 <= mdio_mcr_anrestart_int;
+      mdio_mcr_anrestart_o <= mdio_mcr_anrestart_int and (not mdio_mcr_anrestart_dly0);
+    end if;
+  end process;
+  
+  
+-- Power Down
+  mdio_mcr_pdown_o <= mdio_mcr_pdown_int;
+-- Auto-Negotiation Enable
+  mdio_mcr_anenable_o <= mdio_mcr_anenable_int;
+-- Loopback
+  mdio_mcr_loopback_o <= mdio_mcr_loopback_int;
+-- Reset
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      mdio_mcr_reset_dly0 <= '0';
+      mdio_mcr_reset_o <= '0';
+    elsif rising_edge(clk_sys_i) then
+      mdio_mcr_reset_dly0 <= mdio_mcr_reset_int;
+      mdio_mcr_reset_o <= mdio_mcr_reset_int and (not mdio_mcr_reset_dly0);
+    end if;
+  end process;
+  
+  
+-- Link Status
+-- Remote Fault
+-- Auto-Negotiation Complete
+-- Pause
+  mdio_advertise_pause_o <= mdio_advertise_pause_int;
+-- Remote Fault
+  mdio_advertise_rfault_o <= mdio_advertise_rfault_int;
+-- Full Duplex
+-- Half Duplex
+-- Pause
+-- Remote Fault
+-- Acknowledge
+-- Next Page
+-- TX Calibration Pattern
+-- synchronizer chain for field : TX Calibration Pattern (type RW/RO, clk_sys_i <-> tx_clk_i)
+  process (tx_clk_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      mdio_wr_spec_tx_cal_o <= '0';
+      mdio_wr_spec_tx_cal_sync0 <= '0';
+      mdio_wr_spec_tx_cal_sync1 <= '0';
+    elsif rising_edge(tx_clk_i) then
+      mdio_wr_spec_tx_cal_sync0 <= mdio_wr_spec_tx_cal_int;
+      mdio_wr_spec_tx_cal_sync1 <= mdio_wr_spec_tx_cal_sync0;
+      mdio_wr_spec_tx_cal_o <= mdio_wr_spec_tx_cal_sync1;
+    end if;
+  end process;
+  
+  
+-- Calibration Pattern RX Status
+-- synchronizer chain for field : Calibration Pattern RX Status (type RO/WO, rx_clk_i -> clk_sys_i)
+  process (rx_clk_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      mdio_wr_spec_rx_cal_stat_sync0 <= '0';
+      mdio_wr_spec_rx_cal_stat_sync1 <= '0';
+    elsif rising_edge(rx_clk_i) then
+      mdio_wr_spec_rx_cal_stat_sync0 <= mdio_wr_spec_rx_cal_stat_i;
+      mdio_wr_spec_rx_cal_stat_sync1 <= mdio_wr_spec_rx_cal_stat_sync0;
+    end if;
+  end process;
+  
+  
+-- Reset calibration counter
+  process (rx_clk_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      mdio_wr_spec_cal_crst_o <= '0';
+      mdio_wr_spec_cal_crst_sync0 <= '0';
+      mdio_wr_spec_cal_crst_sync1 <= '0';
+      mdio_wr_spec_cal_crst_sync2 <= '0';
+    elsif rising_edge(rx_clk_i) then
+      mdio_wr_spec_cal_crst_sync0 <= mdio_wr_spec_cal_crst_int;
+      mdio_wr_spec_cal_crst_sync1 <= mdio_wr_spec_cal_crst_sync0;
+      mdio_wr_spec_cal_crst_sync2 <= mdio_wr_spec_cal_crst_sync1;
+      mdio_wr_spec_cal_crst_o <= mdio_wr_spec_cal_crst_sync2 and (not mdio_wr_spec_cal_crst_sync1);
+    end if;
+  end process;
+  
+  
+-- GTP RX Bitslide
+-- asynchronous std_logic_vector register : GTP RX Bitslide (type RO/WO, rx_clk_i <-> clk_sys_i)
+  process (rx_clk_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      mdio_wr_spec_bslide_lwb_s0 <= '0';
+      mdio_wr_spec_bslide_lwb_s1 <= '0';
+      mdio_wr_spec_bslide_lwb_s2 <= '0';
+      mdio_wr_spec_bslide_int <= "00000";
+    elsif rising_edge(rx_clk_i) then
+      mdio_wr_spec_bslide_lwb_s0 <= mdio_wr_spec_bslide_lwb;
+      mdio_wr_spec_bslide_lwb_s1 <= mdio_wr_spec_bslide_lwb_s0;
+      mdio_wr_spec_bslide_lwb_s2 <= mdio_wr_spec_bslide_lwb_s1;
+      if ((mdio_wr_spec_bslide_lwb_s1 = '1') and (mdio_wr_spec_bslide_lwb_s2 = '0')) then
+        mdio_wr_spec_bslide_int <= mdio_wr_spec_bslide_i;
+      end if;
+    end if;
+  end process;
+  
+  
+-- Loopback - detailed
+  mdio_ectrl_lpbck_vec_o <= mdio_ectrl_lpbck_vec_int;
+-- SFP TX Fault Status
+-- SFP LOS
+-- SFP TX Disable
+  mdio_ectrl_sfp_tx_disable_o <= mdio_ectrl_sfp_tx_disable_int;
+-- tx_prbs_sel
+  mdio_ectrl_tx_prbs_sel_o <= mdio_ectrl_tx_prbs_sel_int;
+  rwaddr_reg <= wb_adr_i;
+  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
+-- ACK signal generation. Just pass the LSB of ACK counter.
+  wb_ack_o <= ack_sreg(0);
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_registers_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_registers_pkg.vhd
new file mode 100644
index 000000000..9f5983d51
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_registers_pkg.vhd
@@ -0,0 +1,261 @@
+---------------------------------------------------------------------------------------
+-- Title          : Wishbone slave core for WR switch endpoint controller
+---------------------------------------------------------------------------------------
+-- File           : ep_registers_pkg.vhd
+-- Author         : auto-generated by wbgen2 from ep_wishbone_controller.wb
+-- Created        : Wed Aug 16 22:43:41 2017
+-- Standard       : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ep_wishbone_controller.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package ep_wbgen2_pkg is
+  
+  
+  -- Input registers (user design -> WB slave)
+  
+  type t_ep_in_registers is record
+    ecr_feat_vlan_i                          : std_logic;
+    ecr_feat_dmtd_i                          : std_logic;
+    ecr_feat_ptp_i                           : std_logic;
+    ecr_feat_dpi_i                           : std_logic;
+    tscr_cs_done_i                           : std_logic;
+    tscr_rx_cal_result_i                     : std_logic;
+    tcar_pcp_map_i                           : std_logic_vector(23 downto 0);
+    mdio_asr_rdata_i                         : std_logic_vector(15 downto 0);
+    mdio_asr_ready_i                         : std_logic;
+    dsr_lstatus_i                            : std_logic;
+    dsr_lact_i                               : std_logic;
+    dmcr_en_i                                : std_logic;
+    dmcr_n_avg_i                             : std_logic_vector(11 downto 0);
+    dmsr_ps_val_i                            : std_logic_vector(23 downto 0);
+    dmsr_ps_rdy_i                            : std_logic;
+    inj_ctrl_pic_conf_ifg_i                  : std_logic_vector(15 downto 0);
+    inj_ctrl_pic_conf_sel_i                  : std_logic_vector(2 downto 0);
+    inj_ctrl_pic_conf_valid_i                : std_logic;
+    inj_ctrl_pic_mode_id_i                   : std_logic_vector(2 downto 0);
+    inj_ctrl_pic_mode_valid_i                : std_logic;
+    inj_ctrl_pic_ena_i                       : std_logic;
+    end record;
+  
+  constant c_ep_in_registers_init_value: t_ep_in_registers := (
+    ecr_feat_vlan_i => '0',
+    ecr_feat_dmtd_i => '0',
+    ecr_feat_ptp_i => '0',
+    ecr_feat_dpi_i => '0',
+    tscr_cs_done_i => '0',
+    tscr_rx_cal_result_i => '0',
+    tcar_pcp_map_i => (others => '0'),
+    mdio_asr_rdata_i => (others => '0'),
+    mdio_asr_ready_i => '0',
+    dsr_lstatus_i => '0',
+    dsr_lact_i => '0',
+    dmcr_en_i => '0',
+    dmcr_n_avg_i => (others => '0'),
+    dmsr_ps_val_i => (others => '0'),
+    dmsr_ps_rdy_i => '0',
+    inj_ctrl_pic_conf_ifg_i => (others => '0'),
+    inj_ctrl_pic_conf_sel_i => (others => '0'),
+    inj_ctrl_pic_conf_valid_i => '0',
+    inj_ctrl_pic_mode_id_i => (others => '0'),
+    inj_ctrl_pic_mode_valid_i => '0',
+    inj_ctrl_pic_ena_i => '0'
+    );
+    
+    -- Output registers (WB slave -> user design)
+    
+    type t_ep_out_registers is record
+      ecr_portid_o                             : std_logic_vector(4 downto 0);
+      ecr_rst_cnt_o                            : std_logic;
+      ecr_tx_en_o                              : std_logic;
+      ecr_rx_en_o                              : std_logic;
+      tscr_en_txts_o                           : std_logic;
+      tscr_en_rxts_o                           : std_logic;
+      tscr_cs_start_o                          : std_logic;
+      tscr_rx_cal_start_o                      : std_logic;
+      rfcr_a_runt_o                            : std_logic;
+      rfcr_a_giant_o                           : std_logic;
+      rfcr_a_hp_o                              : std_logic;
+      rfcr_keep_crc_o                          : std_logic;
+      rfcr_hpap_o                              : std_logic_vector(7 downto 0);
+      rfcr_mru_o                               : std_logic_vector(13 downto 0);
+      vcr0_qmode_o                             : std_logic_vector(1 downto 0);
+      vcr0_fix_prio_o                          : std_logic;
+      vcr0_prio_val_o                          : std_logic_vector(2 downto 0);
+      vcr0_pvid_o                              : std_logic_vector(11 downto 0);
+      vcr1_offset_o                            : std_logic_vector(9 downto 0);
+      vcr1_offset_wr_o                         : std_logic;
+      vcr1_data_o                              : std_logic_vector(17 downto 0);
+      vcr1_data_wr_o                           : std_logic;
+      pfcr0_mm_addr_o                          : std_logic_vector(5 downto 0);
+      pfcr0_mm_addr_wr_o                       : std_logic;
+      pfcr0_mm_write_o                         : std_logic;
+      pfcr0_mm_write_wr_o                      : std_logic;
+      pfcr0_enable_o                           : std_logic;
+      pfcr0_mm_data_msb_o                      : std_logic_vector(23 downto 0);
+      pfcr0_mm_data_msb_wr_o                   : std_logic;
+      pfcr1_mm_data_lsb_o                      : std_logic_vector(11 downto 0);
+      pfcr1_mm_data_lsb_wr_o                   : std_logic;
+      tcar_pcp_map_o                           : std_logic_vector(23 downto 0);
+      tcar_pcp_map_load_o                      : std_logic;
+      fcr_rxpause_o                            : std_logic;
+      fcr_txpause_o                            : std_logic;
+      fcr_rxpause_802_1q_o                     : std_logic;
+      fcr_txpause_802_1q_o                     : std_logic;
+      fcr_tx_thr_o                             : std_logic_vector(7 downto 0);
+      fcr_tx_quanta_o                          : std_logic_vector(15 downto 0);
+      mach_o                                   : std_logic_vector(15 downto 0);
+      macl_o                                   : std_logic_vector(31 downto 0);
+      mdio_cr_data_o                           : std_logic_vector(15 downto 0);
+      mdio_cr_data_wr_o                        : std_logic;
+      mdio_cr_addr_o                           : std_logic_vector(7 downto 0);
+      mdio_cr_rw_o                             : std_logic;
+      mdio_asr_phyad_o                         : std_logic_vector(7 downto 0);
+      dsr_lact_o                               : std_logic;
+      dsr_lact_load_o                          : std_logic;
+      dmcr_en_o                                : std_logic;
+      dmcr_en_load_o                           : std_logic;
+      dmcr_n_avg_o                             : std_logic_vector(11 downto 0);
+      dmcr_n_avg_load_o                        : std_logic;
+      dmsr_ps_rdy_o                            : std_logic;
+      dmsr_ps_rdy_load_o                       : std_logic;
+      inj_ctrl_pic_conf_ifg_o                  : std_logic_vector(15 downto 0);
+      inj_ctrl_pic_conf_ifg_load_o             : std_logic;
+      inj_ctrl_pic_conf_sel_o                  : std_logic_vector(2 downto 0);
+      inj_ctrl_pic_conf_sel_load_o             : std_logic;
+      inj_ctrl_pic_conf_valid_o                : std_logic;
+      inj_ctrl_pic_conf_valid_load_o           : std_logic;
+      inj_ctrl_pic_mode_id_o                   : std_logic_vector(2 downto 0);
+      inj_ctrl_pic_mode_id_load_o              : std_logic;
+      inj_ctrl_pic_mode_valid_o                : std_logic;
+      inj_ctrl_pic_mode_valid_load_o           : std_logic;
+      inj_ctrl_pic_ena_o                       : std_logic;
+      inj_ctrl_pic_ena_load_o                  : std_logic;
+      end record;
+    
+    constant c_ep_out_registers_init_value: t_ep_out_registers := (
+      ecr_portid_o => (others => '0'),
+      ecr_rst_cnt_o => '0',
+      ecr_tx_en_o => '0',
+      ecr_rx_en_o => '0',
+      tscr_en_txts_o => '0',
+      tscr_en_rxts_o => '0',
+      tscr_cs_start_o => '0',
+      tscr_rx_cal_start_o => '0',
+      rfcr_a_runt_o => '0',
+      rfcr_a_giant_o => '0',
+      rfcr_a_hp_o => '0',
+      rfcr_keep_crc_o => '0',
+      rfcr_hpap_o => (others => '0'),
+      rfcr_mru_o => (others => '0'),
+      vcr0_qmode_o => (others => '0'),
+      vcr0_fix_prio_o => '0',
+      vcr0_prio_val_o => (others => '0'),
+      vcr0_pvid_o => (others => '0'),
+      vcr1_offset_o => (others => '0'),
+      vcr1_offset_wr_o => '0',
+      vcr1_data_o => (others => '0'),
+      vcr1_data_wr_o => '0',
+      pfcr0_mm_addr_o => (others => '0'),
+      pfcr0_mm_addr_wr_o => '0',
+      pfcr0_mm_write_o => '0',
+      pfcr0_mm_write_wr_o => '0',
+      pfcr0_enable_o => '0',
+      pfcr0_mm_data_msb_o => (others => '0'),
+      pfcr0_mm_data_msb_wr_o => '0',
+      pfcr1_mm_data_lsb_o => (others => '0'),
+      pfcr1_mm_data_lsb_wr_o => '0',
+      tcar_pcp_map_o => (others => '0'),
+      tcar_pcp_map_load_o => '0',
+      fcr_rxpause_o => '0',
+      fcr_txpause_o => '0',
+      fcr_rxpause_802_1q_o => '0',
+      fcr_txpause_802_1q_o => '0',
+      fcr_tx_thr_o => (others => '0'),
+      fcr_tx_quanta_o => (others => '0'),
+      mach_o => (others => '0'),
+      macl_o => (others => '0'),
+      mdio_cr_data_o => (others => '0'),
+      mdio_cr_data_wr_o => '0',
+      mdio_cr_addr_o => (others => '0'),
+      mdio_cr_rw_o => '0',
+      mdio_asr_phyad_o => (others => '0'),
+      dsr_lact_o => '0',
+      dsr_lact_load_o => '0',
+      dmcr_en_o => '0',
+      dmcr_en_load_o => '0',
+      dmcr_n_avg_o => (others => '0'),
+      dmcr_n_avg_load_o => '0',
+      dmsr_ps_rdy_o => '0',
+      dmsr_ps_rdy_load_o => '0',
+      inj_ctrl_pic_conf_ifg_o => (others => '0'),
+      inj_ctrl_pic_conf_ifg_load_o => '0',
+      inj_ctrl_pic_conf_sel_o => (others => '0'),
+      inj_ctrl_pic_conf_sel_load_o => '0',
+      inj_ctrl_pic_conf_valid_o => '0',
+      inj_ctrl_pic_conf_valid_load_o => '0',
+      inj_ctrl_pic_mode_id_o => (others => '0'),
+      inj_ctrl_pic_mode_id_load_o => '0',
+      inj_ctrl_pic_mode_valid_o => '0',
+      inj_ctrl_pic_mode_valid_load_o => '0',
+      inj_ctrl_pic_ena_o => '0',
+      inj_ctrl_pic_ena_load_o => '0'
+      );
+    function "or" (left, right: t_ep_in_registers) return t_ep_in_registers;
+    function f_x_to_zero (x:std_logic) return std_logic;
+    function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
+end package;
+
+package body ep_wbgen2_pkg is
+function f_x_to_zero (x:std_logic) return std_logic is
+begin
+if x = '1' then
+return '1';
+else
+return '0';
+end if;
+end function;
+function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
+variable tmp: std_logic_vector(x'length-1 downto 0);
+begin
+for i in 0 to x'length-1 loop
+if x(i) = '1' then
+tmp(i):= '1';
+else
+tmp(i):= '0';
+end if; 
+end loop; 
+return tmp;
+end function;
+function "or" (left, right: t_ep_in_registers) return t_ep_in_registers is
+variable tmp: t_ep_in_registers;
+begin
+tmp.ecr_feat_vlan_i := f_x_to_zero(left.ecr_feat_vlan_i) or f_x_to_zero(right.ecr_feat_vlan_i);
+tmp.ecr_feat_dmtd_i := f_x_to_zero(left.ecr_feat_dmtd_i) or f_x_to_zero(right.ecr_feat_dmtd_i);
+tmp.ecr_feat_ptp_i := f_x_to_zero(left.ecr_feat_ptp_i) or f_x_to_zero(right.ecr_feat_ptp_i);
+tmp.ecr_feat_dpi_i := f_x_to_zero(left.ecr_feat_dpi_i) or f_x_to_zero(right.ecr_feat_dpi_i);
+tmp.tscr_cs_done_i := f_x_to_zero(left.tscr_cs_done_i) or f_x_to_zero(right.tscr_cs_done_i);
+tmp.tscr_rx_cal_result_i := f_x_to_zero(left.tscr_rx_cal_result_i) or f_x_to_zero(right.tscr_rx_cal_result_i);
+tmp.tcar_pcp_map_i := f_x_to_zero(left.tcar_pcp_map_i) or f_x_to_zero(right.tcar_pcp_map_i);
+tmp.mdio_asr_rdata_i := f_x_to_zero(left.mdio_asr_rdata_i) or f_x_to_zero(right.mdio_asr_rdata_i);
+tmp.mdio_asr_ready_i := f_x_to_zero(left.mdio_asr_ready_i) or f_x_to_zero(right.mdio_asr_ready_i);
+tmp.dsr_lstatus_i := f_x_to_zero(left.dsr_lstatus_i) or f_x_to_zero(right.dsr_lstatus_i);
+tmp.dsr_lact_i := f_x_to_zero(left.dsr_lact_i) or f_x_to_zero(right.dsr_lact_i);
+tmp.dmcr_en_i := f_x_to_zero(left.dmcr_en_i) or f_x_to_zero(right.dmcr_en_i);
+tmp.dmcr_n_avg_i := f_x_to_zero(left.dmcr_n_avg_i) or f_x_to_zero(right.dmcr_n_avg_i);
+tmp.dmsr_ps_val_i := f_x_to_zero(left.dmsr_ps_val_i) or f_x_to_zero(right.dmsr_ps_val_i);
+tmp.dmsr_ps_rdy_i := f_x_to_zero(left.dmsr_ps_rdy_i) or f_x_to_zero(right.dmsr_ps_rdy_i);
+tmp.inj_ctrl_pic_conf_ifg_i := f_x_to_zero(left.inj_ctrl_pic_conf_ifg_i) or f_x_to_zero(right.inj_ctrl_pic_conf_ifg_i);
+tmp.inj_ctrl_pic_conf_sel_i := f_x_to_zero(left.inj_ctrl_pic_conf_sel_i) or f_x_to_zero(right.inj_ctrl_pic_conf_sel_i);
+tmp.inj_ctrl_pic_conf_valid_i := f_x_to_zero(left.inj_ctrl_pic_conf_valid_i) or f_x_to_zero(right.inj_ctrl_pic_conf_valid_i);
+tmp.inj_ctrl_pic_mode_id_i := f_x_to_zero(left.inj_ctrl_pic_mode_id_i) or f_x_to_zero(right.inj_ctrl_pic_mode_id_i);
+tmp.inj_ctrl_pic_mode_valid_i := f_x_to_zero(left.inj_ctrl_pic_mode_valid_i) or f_x_to_zero(right.inj_ctrl_pic_mode_valid_i);
+tmp.inj_ctrl_pic_ena_i := f_x_to_zero(left.inj_ctrl_pic_ena_i) or f_x_to_zero(right.inj_ctrl_pic_ena_i);
+return tmp;
+end function;
+end package body;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rtu_header_extract.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rtu_header_extract.vhd
new file mode 100644
index 000000000..a071bdd3a
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rtu_header_extract.vhd
@@ -0,0 +1,205 @@
+-------------------------------------------------------------------------------
+-- Title      : RTU header extract
+-- Project    : White Rabbit 
+-------------------------------------------------------------------------------
+-- File       : ep_rtu_header_extract.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Platform   : FPGA-generic
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012 - 2017 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.endpoint_private_pkg.all;
+use work.endpoint_pkg.all;
+
+
+entity ep_rtu_header_extract is
+  generic(
+    g_with_rtu : boolean);
+  port(
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    snk_fab_i  : in  t_ep_internal_fabric;
+    snk_dreq_o : out std_logic;
+
+    src_fab_o  : out t_ep_internal_fabric;
+    src_dreq_i : in  std_logic;
+
+    mbuf_is_pause_i : in std_logic; 
+
+    vlan_class_i   : in std_logic_vector(2 downto 0);
+    vlan_vid_i      : in std_logic_vector(11 downto 0);
+    vlan_tag_done_i : in std_logic;
+    vlan_is_tagged_i: in std_logic;
+     
+    rmon_drp_at_rtu_full_o: out std_logic;
+    
+    rtu_rq_o       : out t_ep_internal_rtu_request;
+    rtu_full_i     : in  std_logic;
+    rtu_rq_abort_o : out std_logic;
+    rtu_rq_valid_o : out std_logic;
+    rxbuf_full_i   : in  std_logic
+    );
+
+end ep_rtu_header_extract;
+
+architecture rtl of ep_rtu_header_extract is
+
+  signal hdr_offset : std_logic_vector(11 downto 0);
+  signal in_packet  : std_logic;
+  signal in_header     : std_logic;
+  signal rtu_rq_valid_basic   : std_logic;
+  signal rtu_rq_valid_tagged   : std_logic;
+  signal rtu_rq_valid_out   : std_logic;
+  signal rtu_rq_abort       : std_logic;
+  
+
+  procedure f_extract_rtu(signal q         : out std_logic_vector;
+                          signal fab       :     t_ep_internal_fabric;
+                          signal at_offset :     std_logic) is
+  begin
+    if(at_offset = '1' and fab.dvalid = '1') then
+      q <= fab.data;
+    end if;
+  end f_extract_rtu;
+
+begin  -- rtl
+
+  gen_with_rtu : if(g_with_rtu) generate
+    
+    p_hdr_offset_sreg : process(clk_sys_i)
+    begin
+      if rising_edge(clk_sys_i) then
+        if (rst_n_i = '0' or snk_fab_i.sof = '1') then
+          hdr_offset(hdr_offset'left downto 1) <= (others => '0');
+          hdr_offset(0)                        <= '1';
+        elsif(snk_fab_i.dvalid = '1') then
+          hdr_offset <= hdr_offset(hdr_offset'left-1 downto 0) & '0';
+        end if;
+      end if;
+    end process;
+
+    p_gen_rtu_request : process(clk_sys_i)
+    begin
+      if rising_edge(clk_sys_i) then
+        if rst_n_i = '0' then
+          rtu_rq_o.smac     <= (others => '0');
+          rtu_rq_o.dmac     <= (others => '0');
+          in_packet         <= '0';
+          rtu_rq_valid_basic<= '0';
+          rmon_drp_at_rtu_full_o <='0';
+          rtu_rq_abort     <= '0';
+          in_header        <= '0';
+        else
+          rmon_drp_at_rtu_full_o <='0';
+
+          if(snk_fab_i.sof = '1' and rtu_full_i = '0' and rxbuf_full_i = '0') then
+            in_packet <= '1';
+            in_header <= '1';
+          elsif(snk_fab_i.sof = '1' and rtu_full_i = '1') then
+            rmon_drp_at_rtu_full_o <='1';
+          end if;
+
+          if((snk_fab_i.eof   = '1' and snk_fab_i.sof = '0') or -- in case both (sof & eof) are HIGH
+              snk_fab_i.error = '1') then
+            in_packet <= '0';
+          end if;
+          
+          if(snk_fab_i.error = '1' or rtu_rq_valid_out = '1') then
+            in_header <= '0';
+          end if;
+          
+          
+          f_extract_rtu(rtu_rq_o.dmac(47 downto 32), snk_fab_i, hdr_offset(0));
+          f_extract_rtu(rtu_rq_o.dmac(31 downto 16), snk_fab_i, hdr_offset(1));
+          f_extract_rtu(rtu_rq_o.dmac(15 downto 0), snk_fab_i, hdr_offset(2));
+          f_extract_rtu(rtu_rq_o.smac(47 downto 32), snk_fab_i, hdr_offset(3));
+          f_extract_rtu(rtu_rq_o.smac(31 downto 16), snk_fab_i, hdr_offset(4));
+          f_extract_rtu(rtu_rq_o.smac(15 downto 0), snk_fab_i, hdr_offset(5));
+          
+          if(snk_fab_i.dvalid = '1'  and hdr_offset(6) = '1' and in_packet = '1') then
+            rtu_rq_valid_basic <='1';
+          elsif(rtu_rq_valid_out = '1' or   -- reset after making request or
+                snk_fab_i.error = '1') then -- when there is error in the header, so we don't 
+                                            -- make request for invalid frame which will be dumped
+                                            -- in the SWcore (which reads error status).
+                                            -- the special case when error occurs when the request
+                                            -- is made, we do end with the output of error (below, end of file)
+            rtu_rq_valid_basic     <= '0';
+          end if;
+          
+          if(in_packet       = '1' and in_header    = '0' and -- if we have packet and the header is already processed
+             snk_fab_i.error = '1' and rtu_rq_abort = '0') then 
+            rtu_rq_abort <= '1';
+          else
+            rtu_rq_abort <= '0';
+          end if;
+          
+        end if;
+      end if;
+    end process;
+ 
+    rtu_rq_abort_o <= rtu_rq_abort;
+    src_fab_o.sof <= snk_fab_i.sof and not rtu_full_i; -- null dev
+    
+    rtu_rq_valid_tagged <= rtu_rq_valid_basic and vlan_tag_done_i;
+    
+    -- the request is not done for PAUSE frames as they never go outside of Endpoint 
+    -- (they are dropped inside Endpoint)
+    rtu_rq_valid_out <= (rtu_rq_valid_tagged and (not mbuf_is_pause_i))when (vlan_is_tagged_i = '1') else
+                        (rtu_rq_valid_basic  and (not mbuf_is_pause_i));
+                        
+
+  end generate gen_with_rtu;
+
+  gen_without_rtu : if (not g_with_rtu) generate
+    src_fab_o.sof          <= snk_fab_i.sof;
+    rtu_rq_valid_out       <= '0';
+    rtu_rq_o.smac          <= (others => '0');
+    rtu_rq_o.dmac          <= (others => '0');
+    rtu_rq_abort_o         <= '0';
+    rmon_drp_at_rtu_full_o <= '0';
+  end generate gen_without_rtu;
+
+  snk_dreq_o <= src_dreq_i;
+
+  src_fab_o.eof                <= snk_fab_i.eof;
+  src_fab_o.dvalid             <= snk_fab_i.dvalid;
+  src_fab_o.error              <= snk_fab_i.error;
+  src_fab_o.bytesel            <= snk_fab_i.bytesel;
+  src_fab_o.data               <= snk_fab_i.data;
+  src_fab_o.addr               <= snk_fab_i.addr;
+  src_fab_o.has_rx_timestamp   <= snk_fab_i.has_rx_timestamp;
+  src_fab_o.rx_timestamp_valid <= snk_fab_i.rx_timestamp_valid;
+
+  rtu_rq_o.vid      <= vlan_vid_i;
+  rtu_rq_o.has_vid  <= vlan_is_tagged_i;
+  rtu_rq_o.prio     <= vlan_class_i;
+  rtu_rq_o.has_prio <= vlan_is_tagged_i;
+  rtu_rq_valid_o    <= rtu_rq_valid_out and not snk_fab_i.ERROR;
+  rtu_rq_o.hash     <= (others => '0');
+  
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_buffer.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_buffer.vhd
new file mode 100644
index 000000000..8295fac4b
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_buffer.vhd
@@ -0,0 +1,321 @@
+-------------------------------------------------------------------------------
+-- Title      : RX Packet Buffer
+-- Project    : White Rabbit MAC/Endpoint
+-------------------------------------------------------------------------------
+-- File       : ep_rx_buffer.vhd
+-- Author     : Tomasz Włostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2010-11-18
+-- Last update: 2017-02-02
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: A simple RX packet buffer, optimized for 18-bit Block RAM-based
+-- FIFOs.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2011 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1l.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+
+use work.genram_pkg.all;
+use work.endpoint_private_pkg.all;
+use work.endpoint_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.ep_wbgen2_pkg.all;
+
+entity ep_rx_buffer is
+  generic (
+    g_size    : integer := 1024;
+    g_with_fc : boolean := false
+    );
+  port(
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    snk_fab_i  : in  t_ep_internal_fabric;
+    snk_dreq_o : out std_logic;
+    src_fab_o  : out t_ep_internal_fabric;
+    src_dreq_i : in  std_logic;
+
+    level_o    : out std_logic_vector(7 downto 0);
+    full_o     : out std_logic;
+    drop_req_i : in  std_logic;
+    dropped_o  : out std_logic;
+    regs_i     : in  t_ep_out_registers
+    );
+
+end ep_rx_buffer;
+
+architecture behavioral of ep_rx_buffer is
+
+  constant c_drop_threshold    : integer := g_size - 3;
+  constant c_release_threshold : integer := g_size * 7 / 8;
+
+  type t_write_state is(WAIT_FRAME, DATA);
+
+  procedure f_pack_rbuf_contents
+    (
+      signal st         : in  t_write_state;
+      signal fab        : in  t_ep_internal_fabric;
+      signal prev_addr  : in  std_logic_vector;
+      signal dout       : out std_logic_vector;
+      signal dout_valid : out std_logic) is
+    variable valid_tmp : std_logic;
+  begin
+    if(fab.sof = '1' or fab.error = '1' or fab.eof = '1') then
+      -- tag = 11
+      dout(17)          <= '1';
+      dout(16)          <= '1';
+      dout(15)          <= fab.sof;
+      dout(14)          <= fab.eof;
+      dout(13)          <= fab.error;
+      dout(12 downto 0) <= (others => '0');
+      valid_tmp         := '1';
+--      dout_valid        <= '1';
+    elsif(fab.dvalid = '1') then
+
+      if(prev_addr /= fab.addr) then
+        dout(17 downto 16) <= "10";     -- reg-change
+      else
+        dout(17 downto 16) <= '0' & fab.bytesel;
+      end if;
+
+      dout(15 downto 0) <= fab.data;
+      valid_tmp         := '1';
+    else
+      dout(17 downto 0) <= (others => '0');
+      valid_tmp         := '0';
+    end if;
+
+    if(fab.sof = '1') then
+      dout_valid <= valid_tmp;
+    elsif(st = DATA) then
+      dout_valid <= valid_tmp;
+    else
+      dout_valid <= '0';
+    end if;
+  end f_pack_rbuf_contents;
+
+  procedure f_unpack_rbuf_contents
+    (
+      signal din       : in  std_logic_vector;
+      signal cur_addr  : in  std_logic_vector;
+      signal din_valid : in  std_logic;
+      signal fab       : out t_ep_internal_fabric;
+      early_eof        :     boolean := false) is
+  begin
+
+    fab.data <= din(15 downto 0);
+    if(din_valid = '1') then
+
+      if(din(17 downto 16) = "10") then  -- some fancy encoding is necessary here
+        case cur_addr(1 downto 0) is
+          when c_WRF_DATA =>
+            fab.addr <= c_WRF_OOB after 1 ns;
+          when c_WRF_STATUS =>
+            fab.addr <= c_WRF_DATA after 1 ns;
+          when others => fab.addr <= c_WRF_DATA after 1 ns;
+        end case;
+
+      else
+        fab.addr <= cur_addr after 1 ns;
+      end if;
+
+      fab.dvalid  <= not din(17) or (din(17) and not din(16));
+      fab.sof     <= din(15) and din(17) and din(16);
+      fab.eof     <= din(14) and din(17) and din(16);
+      fab.error   <= din(13) and din(17) and din(16);
+      fab.bytesel <= not din(17) and din(16);
+
+    else
+      fab.bytesel <= '0';
+      fab.addr    <= cur_addr after 1 ns;
+      fab.dvalid  <= '0';
+      fab.sof     <= '0';
+      fab.eof     <= '0';
+      fab.error   <= '0';
+      fab.data    <= (others => '0');
+    end if;
+    fab.has_rx_timestamp   <= '0';
+    fab.rx_timestamp_valid <= '0';
+  end f_unpack_rbuf_contents;
+
+
+  signal q_in, q_out             : std_logic_vector(17 downto 0);
+  signal q_usedw                 : std_logic_vector(f_log2_size(g_size)-1 downto 0);
+  signal q_empty                 : std_logic;
+  signal q_reset                 : std_logic;
+  signal q_rd                    : std_logic;
+  signal q_drop                  : std_logic;
+  signal q_in_valid, q_out_valid : std_logic;
+  signal q_aempty, q_afull       : std_logic;
+
+
+  signal state         : t_write_state;
+  signal fab_to_encode : t_ep_internal_fabric;
+  signal src_fab_int   : t_ep_internal_fabric;
+
+  signal in_prev_addr : std_logic_vector(1 downto 0);
+  signal out_cur_addr : std_logic_vector(1 downto 0);
+  
+begin
+
+  full_o <= q_drop;
+ 
+  p_fifo_write : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        q_drop       <= '0';
+        state        <= WAIT_FRAME;
+        in_prev_addr <= (others => '0');
+        dropped_o    <= '0';
+      else
+
+        if(snk_fab_i.dvalid = '1') then
+          in_prev_addr <= snk_fab_i.addr;
+        end if;
+
+        if(q_afull = '1') then
+          q_drop <= '1';
+        elsif(q_aempty = '1') then
+          q_drop <= '0';
+        end if;
+
+        case state is
+          when WAIT_FRAME =>
+            in_prev_addr <= c_WRF_STATUS;
+
+            if(snk_fab_i.sof = '1' and q_drop = '0' and drop_req_i = '0') then
+              state <= DATA;
+              dropped_o <= '0';
+            elsif(snk_fab_i.sof = '1' and (q_drop = '1' or drop_req_i = '1')) then
+              dropped_o <= '1';
+            end if;
+
+          when DATA =>
+            if(q_drop = '1' or snk_fab_i.eof = '1' or snk_fab_i.error = '1') then
+              state <= WAIT_FRAME;
+            end if;
+            
+          when others => null;
+        end case;
+      end if;
+    end if;
+  end process;
+
+  p_pack_rbuf : process(state, fab_to_encode, in_prev_addr, q_in, q_in_valid)
+  begin
+    f_pack_rbuf_contents(state, fab_to_encode, in_prev_addr, q_in, q_in_valid);
+  end process;
+
+
+  p_encode_fifo_in : process(drop_req_i, q_drop, snk_fab_i, state)
+    variable fab_pre_encode : t_ep_internal_fabric;
+    
+  begin
+    fab_pre_encode := snk_fab_i;
+
+    if(fab_pre_encode.sof = '1' and (q_drop = '1' or drop_req_i = '1')) then
+      fab_pre_encode.sof := '0';
+    end if;
+
+    if(state = DATA and q_drop = '1') then
+      fab_pre_encode.dvalid := '0';
+      fab_pre_encode.error  := '1';
+    end if;
+
+    fab_to_encode <= fab_pre_encode;
+  end process;
+
+  q_reset <= rst_n_i and regs_i.ecr_rx_en_o;
+
+  BUF_FIFO : generic_sync_fifo
+    generic map (
+      g_data_width => 18,
+      g_size       => g_size,
+      g_with_almost_empty => true,
+      g_with_almost_full  => true,
+      g_almost_empty_threshold  => c_release_threshold,
+      g_almost_full_threshold   => c_drop_threshold,
+      g_with_count              => g_with_fc)
+    port map (
+      rst_n_i        => q_reset,
+      clk_i          => clk_sys_i,
+      d_i            => q_in,
+      we_i           => q_in_valid,
+      q_o            => q_out,
+      rd_i           => q_rd,
+      empty_o        => q_empty,
+      full_o         => open,
+      almost_empty_o => q_aempty,
+      almost_full_o  => q_afull,
+      count_o        => q_usedw);
+
+  
+  
+  q_rd <= (not q_empty) and src_dreq_i;
+
+  rd_valid_gen : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if(rst_n_i = '0') then
+        q_out_valid  <= '0';
+        out_cur_addr <= c_WRF_STATUS;
+      else
+        q_out_valid <= q_rd;
+
+        if(src_fab_int.sof = '1' or src_fab_int.eof = '1' or src_fab_int.error = '1')then
+          out_cur_addr <= c_WRF_STATUS;
+        else
+          out_cur_addr <= src_fab_int.addr;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  p_unpack : process(q_out, out_cur_addr, q_out_valid,src_fab_int)
+  begin
+    f_unpack_rbuf_contents(q_out, out_cur_addr, q_out_valid, src_fab_int);
+  end process;
+
+  src_fab_o  <= src_fab_int;
+  snk_dreq_o <= '1';
+
+  GEN_FC: if g_with_fc = true generate
+    GEN_LEV_BIG : if f_log2_size(g_size)-1 > level_o'left generate
+      level_o <= q_usedw(q_usedw'left downto q_usedw'left - 7);
+    end generate;
+    GEN_LEV_SML : if f_log2_size(g_size)-1 < level_o'left+1 generate
+      level_o(q_usedw'left downto 0) <= q_usedw;
+    end generate;
+  end generate;
+
+  GEN_NOFC: if g_with_fc = false generate
+    level_o <= (others=>'X');
+  end generate;
+
+end behavioral;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_crc_size_check.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_crc_size_check.vhd
new file mode 100644
index 000000000..23230b849
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_crc_size_check.vhd
@@ -0,0 +1,404 @@
+-------------------------------------------------------------------------------
+-- Title      : Rx CRC checker
+-- Project    : White Rabbit 
+-------------------------------------------------------------------------------
+-- File       : ep_rx_crc_size_check.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Platform   : FPGA-generic
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2011 - 2017 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.gencores_pkg.all;              -- for gc_crc_gen
+use work.endpoint_private_pkg.all;
+use work.endpoint_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.ep_wbgen2_pkg.all;
+use work.ep_crc32_pkg.all;
+
+-- 1st deframing pipeline stage - CRC/PCS error/Size checker
+
+entity ep_rx_crc_size_check is
+  generic
+    (
+      g_use_new_crc : boolean := false);
+  port(
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    snk_fab_i  : in  t_ep_internal_fabric;
+    snk_dreq_o : out std_logic;
+
+    src_fab_o  : out t_ep_internal_fabric;
+    src_dreq_i : in  std_logic;
+
+    regs_i         : in  t_ep_out_registers;
+    rmon_pcs_err_o : out std_logic;
+    rmon_giant_o   : out std_logic;
+    rmon_runt_o    : out std_logic;
+    rmon_crc_err_o : out std_logic
+    );
+
+end ep_rx_crc_size_check;
+
+architecture behavioral of ep_rx_crc_size_check is
+
+  constant c_MIN_FRAME_SIZE : integer := 64;
+
+  component ep_rx_bypass_queue
+    generic (
+      g_size  : integer;
+      g_width : integer);
+    port (
+      rst_n_i : in  std_logic;
+      clk_i   : in  std_logic;
+      d_i     : in  std_logic_vector(g_width-1 downto 0);
+      valid_i : in  std_logic;
+      dreq_o  : out std_logic;
+      q_o     : out std_logic_vector(g_width-1 downto 0);
+      valid_o : out std_logic;
+      dreq_i  : in  std_logic;
+      flush_i : in  std_logic;
+      purge_i : in  std_logic;
+      empty_o : out std_logic);
+  end component;
+
+
+  type t_state is (ST_WAIT_FRAME, ST_DATA, ST_OOB);
+
+  signal crc_gen_enable        : std_logic;
+  signal crc_gen_reset         : std_logic;
+  signal crc_match, crc_match2 : std_logic;
+
+  signal crc_cur         : std_logic_vector(31 downto 0);
+  signal crc_in_data     : std_logic_vector(15 downto 0);
+  signal crc_last_is_odd : std_logic;
+
+  signal byte_cntr     : unsigned(13 downto 0);
+  signal is_runt       : std_logic;
+  signal is_giant      : std_logic;
+  signal size_check_ok : std_logic;
+
+  signal state : t_state;
+
+  signal q_flush, q_empty : std_logic;
+  signal q_purge          : std_logic;
+  signal q_in, q_out      : std_logic_vector(17 downto 0);
+  signal q_bytesel        : std_logic;
+  signal q_dvalid_in      : std_logic;
+  signal q_dvalid_out     : std_logic;
+  signal q_dreq_out       : std_logic;
+  
+  -- bypass_queue stuff comes here
+  constant c_crc_size    : integer := 2;
+  constant c_dat_width   : integer := 18;
+
+  type t_queue_array is array(0 to c_crc_size-1) of std_logic_vector(c_dat_width-1 downto 0);
+
+  signal q_data           : t_queue_array;
+  signal q_valid          : std_logic_vector(c_crc_size-1 downto 0);
+
+  signal qempty, qfull    : std_logic;
+  signal sreg_enable      : std_logic;
+  signal oob_in           : std_logic;
+  signal dat_in           : std_logic;
+  signal valid_mask       : std_logic;
+  signal err_on_giant     : std_logic;
+
+  function f_queue_occupation(q : std_logic_vector; check_empty : std_logic) return std_logic is
+    variable i : integer;
+  begin
+    for i in 0 to q'length-1 loop
+      if(q(i) = check_empty) then
+        return '0';
+      end if;
+    end loop;  -- i
+    return '1';
+  end function;
+
+begin  -- behavioral
+
+  crc_gen_reset  <= snk_fab_i.sof or (not rst_n_i);
+  crc_gen_enable <= '1' when (snk_fab_i.addr = c_WRF_DATA and snk_fab_i.dvalid = '1') else '0';
+
+  gen_old_crc : if(g_use_new_crc = false) generate
+    U_rx_crc_generator : gc_crc_gen
+      generic map (
+        g_polynomial              => x"04C11DB7",
+        g_init_value              => x"ffffffff",
+        g_residue                 => x"1cdf4421",
+        g_data_width              => 16,
+        g_half_width              => 8,
+        g_sync_reset              => 1,
+        g_dual_width              => 1,
+        g_registered_match_output => false)
+      port map (
+        clk_i   => clk_sys_i,
+        rst_i   => crc_gen_reset,
+        en_i    => crc_gen_enable,
+        half_i  => snk_fab_i.bytesel,
+        data_i  => snk_fab_i.data(15 downto 0),
+        match_o => crc_match,
+        crc_o   => open);
+  end generate gen_old_crc;
+
+  gen_new_crc : if(g_use_new_crc = true) generate
+
+    crc_in_data(15 downto 8) <= snk_fab_i.data(15 downto 8);
+    crc_in_data(7 downto 0)  <= x"00" when snk_fab_i.bytesel = '1' else snk_fab_i.data(7 downto 0);
+
+    p_check_crc : process(clk_sys_i)
+    begin
+      if rising_edge(clk_sys_i) then
+        if crc_gen_reset = '1' then
+          crc_cur <= c_CRC32_INIT_VALUE;
+        elsif(crc_gen_enable = '1') then
+          crc_cur         <= f_update_crc32_d16(crc_cur, crc_in_data);
+          crc_last_is_odd <= snk_fab_i.bytesel;
+        end if;
+      end if;
+    end process;
+
+    crc_match <= '1' when (crc_last_is_odd = '0' and crc_cur = c_CRC32_RESIDUE_FULL)
+                 or (crc_last_is_odd = '1' and crc_cur = c_CRC32_RESIDUE_HALF) else '0';
+
+  end generate gen_new_crc;
+
+--   U_bypass_queue : ep_rx_bypass_queue
+--     generic map (
+--       g_size  => 3,
+--       g_width => 18)
+--     port map (
+--       rst_n_i => rst_n_i,
+--       clk_i   => clk_sys_i,
+--       d_i     => q_in,
+--       valid_i => q_dvalid_in,
+--       dreq_o  => q_dreq_out,
+--       q_o     => q_out,
+--       valid_o => q_dvalid_out,
+--       dreq_i  => src_dreq_i,
+--       flush_i => '0',
+--       purge_i => q_purge,
+--       empty_o => q_empty);
+
+  snk_dreq_o <= q_dreq_out and not (snk_fab_i.eof or snk_fab_i.error);
+
+
+  p_count_bytes : process (clk_sys_i, rst_n_i)
+  begin  -- process
+    if rising_edge(clk_sys_i) then
+      if (rst_n_i = '0' or regs_i.ecr_rx_en_o = '0') then
+        byte_cntr <= (others => '0');
+        is_runt   <= '0';
+        is_giant  <= '0';
+      else
+        if(snk_fab_i.sof = '1') then
+          byte_cntr <= (others => '0');
+          is_runt   <= '1';
+        end if;
+
+        if(snk_fab_i.dvalid = '1') then
+          if(snk_fab_i.bytesel = '1') then
+            byte_cntr <= byte_cntr + 1;
+          else
+            byte_cntr <= byte_cntr + 2;
+          end if;
+        end if;
+
+        if(byte_cntr = to_unsigned(c_MIN_FRAME_SIZE - 2, byte_cntr'length) and snk_fab_i.dvalid = '1' and snk_fab_i.bytesel = '0') then
+          is_runt <= '0';
+        end if;
+
+        if(byte_cntr > unsigned(regs_i.rfcr_mru_o) and snk_fab_i.sof = '0') then
+          is_giant <= '1';
+        else
+          is_giant <= '0';
+        end if;
+        
+      end if;
+    end if;
+  end process;
+
+  size_check_ok <= '0' when (is_runt = '1' and regs_i.rfcr_a_runt_o = '0') or
+                   (is_giant = '1' and regs_i.rfcr_a_giant_o = '0') else '1';
+  err_on_giant  <= '1' when (is_giant = '1' and regs_i.rfcr_a_giant_o = '0') else '0';
+
+  p_gen_output : process(clk_sys_i, rst_n_i)
+  begin
+    if rising_edge(clk_sys_i) then
+
+      if rst_n_i = '0' or regs_i.ecr_rx_en_o = '0' then
+
+        q_purge   <= '0';
+        q_bytesel <= '0';
+
+        state <= ST_WAIT_FRAME;
+
+        rmon_pcs_err_o <= '0';
+        rmon_giant_o   <= '0';
+        rmon_runt_o    <= '0';
+        rmon_crc_err_o <= '0';
+
+        src_fab_o.sof <= '0';
+
+      else
+        case state is
+          when ST_WAIT_FRAME =>
+            q_purge         <= '0';
+            rmon_pcs_err_o  <= '0';
+            rmon_giant_o    <= '0';
+            rmon_runt_o     <= '0';
+            rmon_crc_err_o  <= '0';
+            q_bytesel       <= '0';
+            src_fab_o.error <= '0';
+            src_fab_o.sof   <= '0';
+
+            if(snk_fab_i.sof = '1') then
+              state         <= ST_DATA;
+              src_fab_o.sof <= '1';
+            end if;
+
+          when ST_DATA =>
+
+            src_fab_o.sof <= '0';
+
+            if(snk_fab_i.dvalid = '1' and snk_fab_i.addr = c_WRF_DATA) then
+              q_bytesel <= snk_fab_i.bytesel;
+            end if;
+
+            if(snk_fab_i.error = '1' or    -- an error from the source?
+               (q_bytesel = '1' and oob_in = '0' and snk_fab_i.dvalid = '1')) then -- we expect bytesel at the last byte of data
+
+              src_fab_o.error <= '1';
+              rmon_pcs_err_o  <= '1';
+              state           <= ST_WAIT_FRAME;
+              q_purge         <= '1';
+
+--             elsif(snk_fab_i.eof = '1' or oob_in = '1') then 
+            elsif(snk_fab_i.eof = '1' or oob_in = '1' or err_on_giant = '1') then
+              if(size_check_ok = '0' or crc_match = '0') then  -- bad frame?
+                state           <= ST_WAIT_FRAME;
+                src_fab_o.error <= '1';
+                q_purge         <= '1';
+              elsif(snk_fab_i.eof = '1') then
+                state         <= ST_WAIT_FRAME;
+              else
+                state       <= ST_OOB;
+              end if;
+
+              rmon_runt_o    <= is_runt and (not regs_i.rfcr_a_runt_o);
+              rmon_giant_o   <= is_giant and (not regs_i.rfcr_a_giant_o);
+              rmon_crc_err_o <= not crc_match;
+            end if;
+
+            
+          when ST_OOB =>
+            rmon_runt_o    <= '0';
+            rmon_giant_o   <= '0';
+            rmon_crc_err_o <= '0';
+           
+            if(src_dreq_i = '1' and snk_fab_i.eof='1') then
+              state         <= ST_WAIT_FRAME;
+            end if;
+            
+        end case;
+      end if;
+    end if;
+  end process;
+
+  --
+  q_in(15 downto 0)  <= snk_fab_i.data;
+  q_in(17 downto 16) <= snk_fab_i.addr;
+  q_dvalid_in        <= '1' when snk_fab_i.dvalid = '1' and (state = ST_DATA or state = ST_OOB) else '0';
+
+  --ML optimized queue_bypass so can remove masks tuff
+  src_fab_o.dvalid  <= q_dvalid_out;
+  src_fab_o.data    <= q_in(15 downto 0)  when (oob_in = '1') else q_out(15 downto 0);
+  src_fab_o.addr    <= q_in(17 downto 16) when (oob_in = '1') else q_out(17 downto 16) ;
+  src_fab_o.bytesel <= snk_fab_i.bytesel  when (dat_in = '1') else '0';
+  src_fab_o.eof     <= snk_fab_i.eof;
+
+  src_fab_o.has_rx_timestamp   <= snk_fab_i.has_rx_timestamp;
+  src_fab_o.rx_timestamp_valid <= snk_fab_i.rx_timestamp_valid;
+
+  --------------------- the whole of bypass_queue is here ------------------------------------
+  -- it was put inside as the optimization made it far from "universal" and apparently this
+  -- was the cause of doing the bypass_queue a separate module
+  --------------------------------------------------------------------------------------------
+  qempty       <= f_queue_occupation(q_valid, '1') ;
+  qfull        <= f_queue_occupation(q_valid, '0');
+
+  q_dvalid_out <= (qfull and q_dvalid_in) or (oob_in and valid_mask);
+  q_dreq_out   <= (src_dreq_i or not qfull);
+  oob_in       <= '1' when (snk_fab_i.addr = c_WRF_OOB  and q_dvalid_in = '1') else '0';
+  dat_in       <= '1' when (snk_fab_i.addr = c_WRF_DATA and q_dvalid_in = '1') else '0';
+  
+
+  sreg_enable  <= '1' when ((q_dvalid_in = '1') or (qempty = '0' and q_dvalid_out = '1')) else '0';
+  
+  q_out        <= q_data(0);
+
+  p_fifo: process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if(sreg_enable = '1') then
+        q_data(c_crc_size-1)  <= q_in;
+        L0: for i in 0 to c_crc_size-2 loop
+            q_data(i)       <= q_data(i+1);
+        end loop L0;        
+      end if;
+    end if;
+  end process; 
+
+  p_queue : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' or q_purge = '1' then
+        valid_mask <= '0';
+        q_valid    <= (others => '0');
+      else
+
+        valid_mask <= src_dreq_i;
+
+        if sreg_enable = '1' then
+          q_valid(0)                           <= q_dvalid_in;
+          if(oob_in = '1' ) then -- flashing CRC
+            q_valid                            <=(others => '0');
+          else
+            q_valid(q_valid'length-1 downto 1) <= q_valid(q_valid'length-2 downto 0);
+          end if;
+        end if;
+      end if;
+    end if;
+  end process;
+
+end behavioral;
+
+
+
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_early_address_match.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_early_address_match.vhd
new file mode 100644
index 000000000..427b5d322
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_early_address_match.vhd
@@ -0,0 +1,271 @@
+-------------------------------------------------------------------------------
+-- Title      : Rx Early Address Match
+-- Project    : White Rabbit 
+-------------------------------------------------------------------------------
+-- File       : ep_rx_early_address_match.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Platform   : FPGA-generic
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2011 - 2015 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.gencores_pkg.all;              -- for gc_crc_gen
+use work.endpoint_private_pkg.all;
+use work.endpoint_pkg.all;
+use work.ep_wbgen2_pkg.all;
+
+-- 1st stage in the RX pipeline: early address matching/header parsing
+-- to filter out pause and HP frames in advance.
+
+entity ep_rx_early_address_match is
+  generic
+    (
+      g_early_hp_detection : boolean := false);
+  port(
+    clk_sys_i : in std_logic;
+    clk_rx_i  : in std_logic;
+
+    rst_n_sys_i : in std_logic;
+    rst_n_rx_i  : in std_logic;
+
+    snk_fab_i : in  t_ep_internal_fabric;
+    src_fab_o : out t_ep_internal_fabric;
+
+    match_done_o         : out std_logic;
+    match_is_hp_o        : out std_logic;
+    
+    -- indicate that pause was detected
+    match_is_pause_o     : out std_logic;
+    
+    -- tell quanta (for prio-based pause it is the greatest of all prios)
+    match_pause_quanta_o : out std_logic_vector(15 downto 0);
+    
+    -- mask with priorities which shall be PAUSEd
+    match_pause_prio_mask_o : out std_logic_vector(7 downto 0);
+   
+    -- once the PAUSE frame is decoded, it requests pausing from SWcore
+    match_pause_p_o      : out std_logic; 
+  
+    regs_i : in t_ep_out_registers
+    );
+
+end ep_rx_early_address_match;
+
+architecture behavioral of ep_rx_early_address_match is
+
+  signal hdr_offset : std_logic_vector(16 downto 0);
+
+  signal at_ethertype    : std_logic;
+  signal at_vid          : std_logic;
+  signal is_tagged       : std_logic;
+  signal pause_match_int : std_logic_vector(7 downto 0);
+
+  signal comb_pcp_matches_hp : std_logic;
+  signal done_int            : std_logic;
+
+  signal pause_prio_mask      : std_logic_vector(7 downto 0);
+  signal match_pause_req     : std_logic;
+  signal match_is_pause      : std_logic;
+  signal is_perprio_pause    : std_logic;
+  signal match_pause_quanta  : std_logic_vector(15 downto 0);
+
+  function f_compare_slv (a : std_logic_vector; b : std_logic_vector) return std_logic is
+  begin
+    if(a = b) then
+      return '1';
+    else
+      return '0';
+    end if;
+  end f_compare_slv;
+
+ 
+  
+begin  -- behavioral
+
+  at_ethertype <= hdr_offset(5) and snk_fab_i.dvalid;
+  at_vid       <= hdr_offset(7) and snk_fab_i.dvalid and is_tagged;
+
+  src_fab_o <= snk_fab_i;
+
+  p_hdr_offset_sreg : process(clk_rx_i)
+  begin
+    if rising_edge(clk_rx_i) then
+      if (rst_n_rx_i = '0' or snk_fab_i.sof = '1') then
+        hdr_offset(hdr_offset'left downto 1) <= (others => '0');
+        hdr_offset(0)                        <= '1';
+      elsif(snk_fab_i.dvalid = '1') then
+        hdr_offset <= hdr_offset(hdr_offset'left-1 downto 0) & '0';
+      end if;
+    end if;
+  end process;
+
+  p_match_pause : process(clk_rx_i)
+  begin
+    if rising_edge(clk_rx_i) then
+      if rst_n_rx_i = '0' or snk_fab_i.sof = '1' then
+        pause_match_int      <= (others => '0');
+        match_pause_quanta   <= (others => '0');
+        match_is_pause       <= '0';
+        pause_prio_mask      <= (others => '0');
+        match_pause_req      <= '0';
+        is_perprio_pause     <= '0';
+      else
+        if(snk_fab_i.dvalid = '1') then
+          if(hdr_offset(0) = '1') then
+            pause_match_int (0) <= f_compare_slv(snk_fab_i.data, x"0180");
+          end if;
+          if(hdr_offset(1) = '1') then
+            pause_match_int (1) <= f_compare_slv(snk_fab_i.data, x"c200");
+          end if;
+          if(hdr_offset(2) = '1') then
+            pause_match_int (2) <= f_compare_slv(snk_fab_i.data, x"0001");
+          end if;
+--           if(hdr_offset(3) = '1') then
+--             pause_match_int (3) <= f_compare_slv(snk_fab_i.data, regs_i.mach_o);
+--           end if;
+--           if(hdr_offset(4) = '1') then
+--             pause_match_int (4) <= f_compare_slv(snk_fab_i.data, regs_i.macl_o(31 downto 16));
+--           end if;
+--           if(hdr_offset(5) = '1') then
+--             pause_match_int (5) <= f_compare_slv(snk_fab_i.data, regs_i.macl_o(15 downto 0));
+--           end if;
+          if(hdr_offset(6) = '1') then
+            pause_match_int (3) <= f_compare_slv(snk_fab_i.data, x"8808");
+          end if;
+          if(hdr_offset(7) = '1') then
+            pause_match_int (4) <= f_compare_slv(snk_fab_i.data, x"0001"); -- 802.3 PAUSE
+            pause_match_int (5) <= f_compare_slv(snk_fab_i.data, x"0101"); -- 802.1Q PAUSE (per-prio)
+          end if;
+          if(hdr_offset(8) = '1') then
+            if(f_compare_slv(pause_match_int, b"0001_1111") = '1') then  -- 802.3 PAUSE
+
+              match_is_pause            <= '1'; -- to indicate that frame shall be dropped
+
+              if(regs_i.fcr_rxpause_o = '1') then
+                match_pause_req         <= '1';
+                match_pause_quanta      <= snk_fab_i.data;  
+                pause_prio_mask         <= (others => '1');
+              end if;
+
+            elsif(f_compare_slv(pause_match_int, b"0010_1111") = '1') then  -- 802.1Q PAUSE (per-prio)
+
+              match_is_pause          <= '1'; -- to indicate that frame shall be dropped
+
+              if(regs_i.fcr_rxpause_802_1q_o = '1') then
+                pause_prio_mask       <=  snk_fab_i.data(7 downto 0);
+                is_perprio_pause      <= '1';
+              end if;
+  
+            end if;
+          end if;
+          if (is_perprio_pause ='1' and ((hdr_offset(16 downto 9) and pause_prio_mask) /= b"0000_0000")) then
+            if(snk_fab_i.data > match_pause_quanta) then
+              match_pause_quanta <= snk_fab_i.data;
+            end if;  
+          end if;
+          if(hdr_offset(16) = '1' and is_perprio_pause = '1') then
+            match_pause_req           <= '1';
+          end if;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  match_is_pause_o        <= match_is_pause;
+  match_pause_prio_mask_o <= pause_prio_mask;
+  match_pause_quanta_o    <= match_pause_quanta;
+
+  gen_with_early_hp_det: if(g_early_hp_detection) generate
+  -- ML: the p_match_hp is not used, instead identification of HP is done in RTU 
+  p_match_hp : process(clk_rx_i)
+    variable index : integer;
+  begin
+    
+    if rising_edge(clk_rx_i) then
+      index := to_integer(unsigned(snk_fab_i.data(15 downto 13)));
+
+      if rst_n_rx_i = '0' or snk_fab_i.sof = '1' then
+        is_tagged     <= '0';
+        match_is_hp_o <= '0';
+      else
+        if(at_ethertype = '1') then
+          is_tagged <= f_compare_slv(snk_fab_i.data, x"8100");
+        end if;
+
+        if (at_vid = '1') then
+          if(regs_i.rfcr_a_hp_o = '1' and regs_i.rfcr_hpap_o(index) = '1' and is_tagged = '1') then
+            match_is_hp_o <= '1';
+          else
+            match_is_hp_o <= '0';
+          end if;
+        end if;
+      end if;
+    end if;
+  end process;
+  end generate gen_with_early_hp_det;
+  
+  gen_without_early_hp_det: if(not g_early_hp_detection) generate
+    match_is_hp_o <='0';
+  end generate gen_without_early_hp_det;
+
+  p_gen_done : process(clk_rx_i)
+  begin
+    if rising_edge(clk_rx_i) then
+      if rst_n_rx_i = '0' or snk_fab_i.sof = '1' then
+        done_int <= '0';
+      else
+        if hdr_offset(8) = '1' or snk_fab_i.error = '1' then
+          done_int <= '1';
+        end if;
+      end if;
+    end if;
+  end process;
+
+  U_sync_done : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_sys_i,
+      rst_n_i  => rst_n_sys_i,
+      data_i   => done_int,
+      ppulse_o => match_done_o);
+
+  U_sync_pause : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_sys_i,
+      rst_n_i  => rst_n_sys_i,
+      data_i   => match_pause_req,
+      ppulse_o => match_pause_p_o);
+
+end behavioral;
+
+
+
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_oob_insert.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_oob_insert.vhd
new file mode 100644
index 000000000..4fbaf7596
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_oob_insert.vhd
@@ -0,0 +1,171 @@
+-------------------------------------------------------------------------------
+-- Title      : RX OOB inserter
+-- Project    : White Rabbit 
+-------------------------------------------------------------------------------
+-- File       : ep_rx_oob_insert.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Platform   : FPGA-generic
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2011 - 2017 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.gencores_pkg.all;              -- for gc_crc_gen
+use work.endpoint_private_pkg.all;
+use work.endpoint_pkg.all;
+use work.ep_wbgen2_pkg.all;
+use work.wr_fabric_pkg.all;
+
+
+entity ep_rx_oob_insert is
+  port(clk_sys_i : in std_logic;
+       rst_n_i   : in std_logic;
+
+       snk_fab_i  : in  t_ep_internal_fabric;
+       snk_dreq_o : out std_logic;
+
+       src_fab_o  : out t_ep_internal_fabric;
+       src_dreq_i : in  std_logic;
+
+       regs_i : in t_ep_out_registers
+       );
+
+end ep_rx_oob_insert;
+
+architecture behavioral of ep_rx_oob_insert is
+
+  type t_state is (WAIT_OOB, OOB);
+  signal state : t_state;
+
+  signal src_dreq_d0 : std_logic;
+
+  --component chipscope_ila
+  --  port (
+  --    CONTROL : inout std_logic_vector(35 downto 0);
+  --    CLK     : in    std_logic;
+  --    TRIG0   : in    std_logic_vector(31 downto 0);
+  --    TRIG1   : in    std_logic_vector(31 downto 0);
+  --    TRIG2   : in    std_logic_vector(31 downto 0);
+  --    TRIG3   : in    std_logic_vector(31 downto 0));
+  --end component;
+
+  --component chipscope_icon
+  --  port (
+  --    CONTROL0 : inout std_logic_vector (35 downto 0));
+  --end component;
+  
+  --signal CONTROL : std_logic_vector(35 downto 0);
+  --signal CLK     : std_logic;
+  --signal TRIG0   : std_logic_vector(31 downto 0);
+  --signal TRIG1   : std_logic_vector(31 downto 0);
+  --signal TRIG2   : std_logic_vector(31 downto 0);
+  --signal TRIG3   : std_logic_vector(31 downto 0);
+  
+begin
+  --chipscope_ila_1 : chipscope_ila
+  --  port map (
+  --    CONTROL => CONTROL,
+  --    CLK     => clk_sys_i,
+  --    TRIG0   => TRIG0,
+  --    TRIG1   => TRIG1,
+  --    TRIG2   => TRIG2,
+  --    TRIG3   => TRIG3);
+
+  --chipscope_icon_1 : chipscope_icon
+  --  port map (
+  --    CONTROL0 => CONTROL);
+
+  --TRIG0(15 downto 0) <= snk_fab_i.data;
+  --trig0(16) <= snk_fab_i.sof;
+  --trig0(17) <= snk_fab_i.eof;
+  --trig0(18) <= snk_fab_i.error;
+  --trig0(19) <= snk_fab_i.bytesel;
+  --trig0(20) <= snk_fab_i.has_rx_timestamp;
+  --trig0(21) <= snk_fab_i.dvalid;
+  --trig0(22) <= '1' when state = WAIT_OOB else '0';
+  --trig0(24 downto 23) <= snk_fab_i.addr;
+
+  snk_dreq_o                   <= src_dreq_i;
+  src_fab_o.sof                <= snk_fab_i.sof;
+  src_fab_o.eof                <= snk_fab_i.eof;
+  src_fab_o.ERROR              <= snk_fab_i.ERROR;
+  src_fab_o.bytesel            <= snk_fab_i.bytesel;
+  src_fab_o.has_rx_timestamp   <= snk_fab_i.has_rx_timestamp;
+  src_fab_o.rx_timestamp_valid <= snk_fab_i.rx_timestamp_valid;
+  
+  p_comb_src : process (state, snk_fab_i, src_dreq_i, regs_i)
+  begin
+
+    if(snk_fab_i.has_rx_timestamp = '1')then
+      src_fab_o.data   <= c_WRF_OOB_TYPE_RX & (not snk_fab_i.rx_timestamp_valid) & "000000" & regs_i.ecr_portid_o;
+      src_fab_o.dvalid <= '1';
+      src_fab_o.addr   <= c_WRF_OOB;
+    else
+      if(state = WAIT_OOB) then
+        src_fab_o.addr <= c_WRF_DATA;
+      else
+        src_fab_o.addr <= c_WRF_OOB;
+      end if;
+      src_fab_o.data   <= snk_fab_i.data;
+      src_fab_o.dvalid <= snk_fab_i.dvalid;
+    end if;
+  end process;
+
+  p_fsm : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' or regs_i.ecr_rx_en_o = '0' then
+        state <= WAIT_OOB;
+      else
+
+        if(snk_fab_i.error = '1' or snk_fab_i.sof = '1') then
+          state <= WAIT_OOB;
+        else
+
+          case state is
+            when WAIT_OOB =>
+              if(snk_fab_i.has_rx_timestamp = '1') then
+                state <= OOB;
+              end if;
+
+            when OOB =>
+              if(snk_fab_i.eof = '1') then
+                state <= WAIT_OOB;
+              end if;
+              
+          end case;
+        end if;
+      end if;
+    end if;
+  end process;
+
+
+end behavioral;
+
+
+
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_path.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_path.vhd
new file mode 100644
index 000000000..7398828f2
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_path.vhd
@@ -0,0 +1,515 @@
+-------------------------------------------------------------------------------
+-- Title      : Gigabit Ethernet reception pipeline
+-- Project    : White Rabbit MAC/Endpoint
+-------------------------------------------------------------------------------
+-- File       : ep_rx_path.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2009-06-22
+-- Last update: 2017-02-02
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: RX path unit:
+-- - provides elastic buffering between RX and system clock
+-- - checks frame CRC and size
+-- - inserts/removes 802.1q headers when necessary 
+-- - parses packet headers and generates RTU requests
+-- - performs programmable packet inspection and classifying
+-- - distinguishes between HP and non-HP frames
+-- - issues RTU requests
+-- - embeds RX OOB block with timestamp information
+-- 
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2009-2011 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2009-06-22  0.1      twlostow        Created
+-- 2011-10-18  0.5      twlostow        WB rev B4 - compatible data path
+------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.gencores_pkg.all;
+use work.genram_pkg.all;
+use work.endpoint_private_pkg.all;
+use work.endpoint_pkg.all;
+use work.ep_wbgen2_pkg.all;
+use work.wr_fabric_pkg.all;
+
+entity ep_rx_path is
+  generic (
+    g_with_vlans          : boolean := true;
+    g_with_dpi_classifier : boolean := true;
+    g_with_rtu            : boolean := true;
+    g_with_rx_buffer      : boolean := true;
+    g_with_early_match    : boolean := false;
+    g_rx_buffer_size      : integer := 1024;
+    g_use_new_crc         :	boolean := false);
+  port (
+    clk_sys_i   : in std_logic;
+    clk_rx_i    : in std_logic;
+    rst_n_sys_i : in std_logic;
+    rst_n_rx_i  : in std_logic;
+
+-- physical coding sublayer (PCS) interface
+    pcs_fab_i             : in  t_ep_internal_fabric;
+    pcs_fifo_almostfull_o : out std_logic;
+    pcs_busy_i            : in  std_logic;
+
+-- Wishbone I/O
+    src_wb_o : out t_wrf_source_out;
+    src_wb_i : in  t_wrf_source_in;
+
+-- flow control signals
+    fc_pause_p_o           : out std_logic;
+    fc_pause_quanta_o      : out std_logic_vector(15 downto 0);
+    fc_pause_prio_mask_o   : out std_logic_vector(7 downto 0);
+    fc_buffer_occupation_o : out std_logic_vector(7 downto 0);
+
+-- RMON/statistic counters signals
+    rmon_o : out t_rmon_triggers;
+    regs_i : in  t_ep_out_registers;
+    regs_o : out t_ep_in_registers;
+
+-- info for TRU module
+    pfilter_pclass_o : out std_logic_vector(7 downto 0);
+    pfilter_drop_o   : out std_logic;
+    pfilter_done_o   : out std_logic;
+
+-------------------------------------------------------------------------------
+-- RTU interface
+-------------------------------------------------------------------------------
+
+    rtu_rq_o       : out t_ep_internal_rtu_request;
+    rtu_full_i     : in  std_logic;
+    rtu_rq_valid_o : out std_logic;
+    rtu_rq_abort_o : out std_logic;
+
+    nice_dbg_o     : out t_dbg_ep_rxpath
+    );
+end ep_rx_path;
+
+architecture behavioral of ep_rx_path is
+
+  type t_rx_deframer_state is (RXF_IDLE, RXF_DATA, RXF_FLUSH_STALL, RXF_FINISH_CYCLE, RXF_THROW_ERROR);
+
+  signal state : t_rx_deframer_state;
+
+  signal gap_cntr : unsigned(3 downto 0);
+
+  -- new sigs
+  signal counter : unsigned(7 downto 0);
+
+  signal rxdata_saved : std_logic_vector(15 downto 0);
+  signal next_hdr     : std_logic;
+  signal is_pause     : std_logic;
+
+  signal data_firstword : std_logic;
+
+
+  signal flush_stall : std_logic;
+  signal stb_int     : std_logic;
+
+  signal fab_int  : t_ep_internal_fabric;
+  signal dreq_int : std_logic;
+
+  signal ack_count   : unsigned(7 downto 0);
+  signal src_out_int : t_wrf_source_out;
+
+  signal tmp_sel : std_logic;
+  signal tmp_dat : std_logic_vector(15 downto 0);
+
+
+  signal fab_pipe  : t_fab_pipe(0 to 9);
+  signal dreq_pipe : std_logic_vector(9 downto 0);
+
+  signal ematch_done     : std_logic;
+  signal ematch_is_hp    : std_logic;
+  signal ematch_is_pause : std_logic;
+  signal fc_pause_p      : std_logic;
+
+  signal pfilter_pclass : std_logic_vector(7 downto 0);
+  signal pfilter_drop   : std_logic;
+  signal pfilter_done   : std_logic;
+
+  signal vlan_tclass    : std_logic_vector(2 downto 0);
+  signal vlan_vid       : std_logic_vector(11 downto 0);
+  signal vlan_tag_done  : std_logic;
+  signal vlan_is_tagged : std_logic;
+
+  signal pcs_fifo_almostfull                                    : std_logic;
+  signal mbuf_rd, mbuf_valid, mbuf_we, mbuf_pf_drop, mbuf_is_hp : std_logic;
+  signal mbuf_is_pause, mbuf_full : std_logic;
+  signal mbuf_pf_class            : std_logic_vector(7 downto 0);
+  signal rtu_rq_valid         : std_logic;
+  signal stat_reg_mbuf_valid  : std_logic;
+
+  signal rxbuf_full       : std_logic;
+  signal rxbuf_dropped    : std_logic;
+
+  signal src_wb_out : t_wrf_source_out;
+  signal src_wb_cyc_d0 : std_logic;
+  
+  signal rst_n_rx_match_buff : std_logic;
+
+begin  -- behavioral
+
+  fab_pipe(0) <= pcs_fab_i;
+
+  fc_pause_p_o    <= fc_pause_p;
+  gen_with_early_match : if(g_with_early_match) generate
+    U_early_addr_match : ep_rx_early_address_match
+      port map (
+        clk_sys_i               => clk_sys_i,
+        clk_rx_i                => clk_rx_i,
+        rst_n_sys_i             => rst_n_sys_i,
+        rst_n_rx_i              => rst_n_rx_i,
+        snk_fab_i               => fab_pipe(0),
+        src_fab_o               => fab_pipe(1),
+        match_done_o            => ematch_done,
+        match_is_hp_o           => ematch_is_hp,
+        match_is_pause_o        => ematch_is_pause,
+        match_pause_quanta_o    => fc_pause_quanta_o,
+        match_pause_prio_mask_o => fc_pause_prio_mask_o,
+        match_pause_p_o         => fc_pause_p,
+        regs_i                  => regs_i);
+  end generate gen_with_early_match;
+
+  gen_without_early_match : if(not g_with_early_match) generate
+    fab_pipe(1)          <= fab_pipe(0);
+    ematch_done          <= '0';
+    ematch_is_hp         <= '0';
+    ematch_is_pause      <= '0';
+    fc_pause_quanta_o    <= (others =>'0');
+    fc_pause_prio_mask_o <= (others =>'0');
+    fc_pause_p           <= '0';
+  end generate gen_without_early_match;
+
+  gen_with_packet_filter : if(g_with_dpi_classifier) generate
+    U_packet_filter : ep_packet_filter
+      port map (
+        clk_sys_i   => clk_sys_i,
+        clk_rx_i    => clk_rx_i,
+        rst_n_sys_i => rst_n_sys_i,
+        rst_n_rx_i  => rst_n_rx_i,
+
+        snk_fab_i => fab_pipe(1),
+        src_fab_o => fab_pipe(2),
+        done_o    => pfilter_done,
+        pclass_o  => pfilter_pclass,
+        drop_o    => pfilter_drop,
+        regs_i    => regs_i);
+  end generate gen_with_packet_filter;
+
+  gen_without_packet_filter : if(not g_with_dpi_classifier) generate
+    fab_pipe(2)    <= fab_pipe(1);
+    pfilter_drop   <= '0';
+    pfilter_done   <= '1';
+    pfilter_pclass <= (others => '0');
+  end generate gen_without_packet_filter;
+
+  process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if (rst_n_sys_i = '0') then
+        mbuf_we <= '0';
+      -- if rx_buffer has dropped a frame (e.g. because it was full) we
+      -- shouldn't store pfilter decision in the mbuf as well
+      elsif( ((ematch_done='1' and g_with_early_match) or
+              (pfilter_done='1' and g_with_dpi_classifier)) and
+              rxbuf_dropped='0') then
+        mbuf_we <= '1';
+      elsif(mbuf_rd = '1' or mbuf_full = '0') then
+        mbuf_we <= '0';
+      end if;
+    end if;
+  end process;
+
+  gen_with_match_buff: if( g_with_early_match or g_with_dpi_classifier) generate
+    U_Sync_Rst_match_buff : gc_sync_ffs
+      port map (
+        clk_i    => clk_sys_i,
+        rst_n_i  => '1',
+        data_i   => rst_n_rx_i,
+        synced_o => rst_n_rx_match_buff);
+
+    U_match_buffer : generic_shiftreg_fifo
+      generic map (
+        g_data_width => 8 + 1 + 1 + 1,
+        g_size       => 16)
+      port map (
+        rst_n_i           => rst_n_rx_match_buff,
+        clk_i             => clk_sys_i,
+        d_i (0)           => ematch_is_hp,
+        d_i (1)           => ematch_is_pause,
+        d_i (2)           => pfilter_drop,
+        d_i (10 downto 3) => pfilter_pclass,
+
+        we_i              => mbuf_we,
+        q_o (0)           => mbuf_is_hp,
+        q_o (1)           => mbuf_is_pause,
+        q_o (2)           => mbuf_pf_drop,
+        q_o (10 downto 3) => mbuf_pf_class,
+
+        rd_i      => mbuf_rd,
+        full_o    => mbuf_full,
+        q_valid_o => mbuf_valid);
+  end generate;
+
+  gen_without_match_buf: if(not (g_with_early_match or g_with_dpi_classifier)) generate
+    mbuf_is_hp    <= '0';
+    mbuf_is_pause <= '0';
+    mbuf_pf_drop  <= '0';
+    mbuf_pf_class <= (others=>'0');
+    mbuf_full     <= '0';
+    mbuf_valid    <= '1';
+  end generate;
+
+  -- don't block ep_rx_status_reg_insert when pfilter is disabled and early
+  -- match is not used
+  stat_reg_mbuf_valid <= '1' when (not g_with_early_match and g_with_dpi_classifier
+                                   and regs_i.pfcr0_enable_o='0') else
+                         mbuf_valid;
+
+  U_Rx_Clock_Align_FIFO : ep_clock_alignment_fifo
+    generic map (
+      g_size                 => 128,
+      g_almostfull_threshold => 112)
+    port map (
+      rst_n_rd_i       => rst_n_sys_i,
+      rst_n_wr_i       => rst_n_rx_i,
+      clk_wr_i         => clk_rx_i,
+      clk_rd_i         => clk_sys_i,
+      dreq_i           => dreq_pipe(3),
+      fab_i            => fab_pipe(2),
+      fab_o            => fab_pipe(3),
+      full_o           => nice_dbg_o.pcs_fifo_full,
+      empty_o          => nice_dbg_o.pcs_fifo_empty,
+      almostfull_o     => pcs_fifo_almostfull,
+      pass_threshold_i => std_logic_vector(to_unsigned(32, 7)));  -- fixme: add
+                                                                  -- register
+  pcs_fifo_almostfull_o <= pcs_fifo_almostfull;
+
+  U_Insert_OOB : ep_rx_oob_insert
+    port map (
+      clk_sys_i  => clk_sys_i,
+      rst_n_i    => rst_n_sys_i,
+      snk_fab_i  => fab_pipe(3),
+      snk_dreq_o => dreq_pipe(3),
+      src_dreq_i => dreq_pipe(4),
+      src_fab_o  => fab_pipe(4),
+      regs_i     => regs_i);
+
+  U_crc_size_checker : ep_rx_crc_size_check
+    generic map (
+      g_use_new_crc	 => g_use_new_crc)
+    port map (
+      clk_sys_i      => clk_sys_i,
+      rst_n_i        => rst_n_sys_i,
+      snk_fab_i      => fab_pipe(4),
+      snk_dreq_o     => dreq_pipe(4),
+      src_dreq_i     => dreq_pipe(5),
+      src_fab_o      => fab_pipe(5),
+      regs_i         => regs_i,
+      rmon_pcs_err_o => rmon_o.rx_pcs_err,
+      rmon_giant_o   => rmon_o.rx_giant,
+      rmon_runt_o    => rmon_o.rx_runt,
+      rmon_crc_err_o => rmon_o.rx_crc_err);
+
+  gen_with_vlan_unit : if(g_with_vlans) generate
+    U_vlan_unit : ep_rx_vlan_unit
+      port map (
+        clk_sys_i   => clk_sys_i,
+        rst_n_i     => rst_n_sys_i,
+        snk_fab_i   => fab_pipe(5),
+        snk_dreq_o  => dreq_pipe(5),
+        src_fab_o   => fab_pipe(6),
+        src_dreq_i  => dreq_pipe(6),
+        tclass_o    => vlan_tclass,
+        vid_o       => vlan_vid,
+        tag_done_o  => vlan_tag_done,
+        is_tagged_o => vlan_is_tagged,
+        regs_i      => regs_i,
+        regs_o      => regs_o);
+  end generate gen_with_vlan_unit;
+
+
+  gen_without_vlan_unit : if(not g_with_vlans) generate
+    fab_pipe(6)    <= fab_pipe(5);
+    dreq_pipe(5)   <= dreq_pipe(6);
+    vlan_tclass    <= (others => '0');
+    vlan_vid       <= (others => '0');
+    vlan_tag_done  <= '0';
+    vlan_is_tagged <= '0';
+    regs_o         <= c_ep_in_registers_init_value;
+  end generate gen_without_vlan_unit;
+
+  U_RTU_Header_Extract : ep_rtu_header_extract
+    generic map (
+      g_with_rtu => g_with_rtu)
+    port map (
+      clk_sys_i        => clk_sys_i,
+      rst_n_i          => rst_n_sys_i,
+      snk_fab_i        => fab_pipe(6),
+      snk_dreq_o       => dreq_pipe(6),
+      src_fab_o        => fab_pipe(7),
+      src_dreq_i       => dreq_pipe(7),
+      mbuf_is_pause_i  => mbuf_is_pause,  -- this module is in the pipe before ep_rx_status_reg_insert,
+                                          -- however, we know that mbuf_is_pause is valid when it 
+                                          -- is used by this module -- this is because blocks the pipe
+                                          -- untill mbuf_valid is HIGH, and rtu_rq_valid_o is inserted HIGH
+                                          -- at the end of the header... (clear ??:)
+      vlan_class_i     => vlan_tclass,
+      vlan_vid_i       => vlan_vid,
+      vlan_tag_done_i  => vlan_tag_done,
+      vlan_is_tagged_i => vlan_is_tagged,
+      
+      rmon_drp_at_rtu_full_o => rmon_o.rx_drop_at_rtu_full,
+      
+      rtu_rq_o         => rtu_rq_o,
+      rtu_full_i       => rtu_full_i,
+      rtu_rq_abort_o   => rtu_rq_abort_o,
+      rtu_rq_valid_o   => rtu_rq_valid,
+      rxbuf_full_i     => rxbuf_full);
+
+  gen_with_rx_buffer : if g_with_rx_buffer generate
+    U_Rx_Buffer : ep_rx_buffer
+      generic map (
+        g_size    => g_rx_buffer_size,
+        g_with_fc => false)
+      port map (
+        clk_sys_i  => clk_sys_i,
+        rst_n_i    => rst_n_sys_i,
+        snk_fab_i  => fab_pipe(7),
+        snk_dreq_o => dreq_pipe(7),
+        src_fab_o  => fab_pipe(8),
+        src_dreq_i => dreq_pipe(8),
+        level_o    => fc_buffer_occupation_o,
+        full_o     => rxbuf_full,
+        drop_req_i => mbuf_we,  -- if mbuf_we is high that means it waits to be
+                                -- stored in mbuf => mbuf is probably full so we
+                                -- should drop this frame
+        dropped_o  => rxbuf_dropped,
+        regs_i     => regs_i);
+  end generate gen_with_rx_buffer;
+
+  gen_without_rx_buffer : if (not g_with_rx_buffer) generate
+    fab_pipe(8)  <= fab_pipe(7);
+    dreq_pipe(7) <= dreq_pipe(8);
+    rxbuf_full  <= '0';
+  end generate gen_without_rx_buffer;
+
+  U_Gen_Status : ep_rx_status_reg_insert
+    port map (
+      clk_sys_i           => clk_sys_i,
+      rst_n_i             => rst_n_sys_i,
+      snk_fab_i           => fab_pipe(8),
+      snk_dreq_o          => dreq_pipe(8),
+      src_fab_o           => fab_pipe(9),
+      src_dreq_i          => dreq_pipe(9),
+      mbuf_valid_i        => stat_reg_mbuf_valid,
+      mbuf_ack_o          => mbuf_rd,
+      mbuf_drop_i         => mbuf_pf_drop,
+      mbuf_pclass_i       => mbuf_pf_class,
+      mbuf_is_hp_i        => mbuf_is_hp,
+      mbuf_is_pause_i     => mbuf_is_pause,
+      rmon_pfilter_drop_o => rmon_o.rx_pfilter_drop);
+
+  U_RX_Wishbone_Master : ep_rx_wb_master
+    generic map (
+      g_ignore_ack => true)
+    port map (
+      clk_sys_i  => clk_sys_i,
+      rst_n_i    => rst_n_sys_i,
+      snk_fab_i  => fab_pipe(9),
+      snk_dreq_o => dreq_pipe(9),
+      src_wb_i   => src_wb_i,
+      src_wb_o   => src_wb_out
+      );
+
+  src_wb_o <= src_wb_out;
+
+  -- direct output of packet filter data (for TRU)
+  pfilter_pclass_o <= pfilter_pclass;
+  pfilter_drop_o   <= pfilter_drop;
+  pfilter_done_o   <= pfilter_done;
+
+  rtu_rq_valid_o   <= rtu_rq_valid;
+  -----------------------------------------
+  -- RMON events
+  -----------------------------------------
+  rmon_o.rx_pause <= fc_pause_p;
+  GEN_PCLASS_EVT: for i in 0 to 7 generate
+    rmon_o.rx_pclass(i) <= pfilter_pclass(i) and pfilter_done;
+  end generate;
+
+  rmon_o.rx_tclass(0) <= rtu_rq_valid when (vlan_tclass = "000" and vlan_is_tagged = '1') else '0';
+  rmon_o.rx_tclass(1) <= rtu_rq_valid when (vlan_tclass = "001" and vlan_is_tagged = '1') else '0';
+  rmon_o.rx_tclass(2) <= rtu_rq_valid when (vlan_tclass = "010" and vlan_is_tagged = '1') else '0';
+  rmon_o.rx_tclass(3) <= rtu_rq_valid when (vlan_tclass = "011" and vlan_is_tagged = '1') else '0';
+  rmon_o.rx_tclass(4) <= rtu_rq_valid when (vlan_tclass = "100" and vlan_is_tagged = '1') else '0';
+  rmon_o.rx_tclass(5) <= rtu_rq_valid when (vlan_tclass = "101" and vlan_is_tagged = '1') else '0';
+  rmon_o.rx_tclass(6) <= rtu_rq_valid when (vlan_tclass = "110" and vlan_is_tagged = '1') else '0';
+  rmon_o.rx_tclass(7) <= rtu_rq_valid when (vlan_tclass = "111" and vlan_is_tagged = '1') else '0';
+
+  GEN_DBG: for i in 0 to 9 generate
+    nice_dbg_o.fab_pipe(i) <= fab_pipe(i);
+    nice_dbg_o.dreq_pipe(i)<= dreq_pipe(i);
+  end generate GEN_DBG;
+
+  nice_dbg_o.pcs_fifo_afull <= pcs_fifo_almostfull;
+  nice_dbg_o.rxbuf_full <= rxbuf_full;
+
+  process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if (rst_n_sys_i = '0') then
+        src_wb_cyc_d0 <= '0';
+      else
+        src_wb_cyc_d0 <= src_wb_out.cyc;
+      end if;
+    end if;
+  end process;
+
+  rmon_o.rx_frame <= '1' when (src_wb_out.cyc = '1' and src_wb_cyc_d0 = '0') else
+                     '0';
+
+  -- drive unused signals and outputs
+  dreq_pipe(2 downto 0)         <= (others => '0');
+  rmon_o.rx_sync_lost           <= '0';
+  rmon_o.rx_invalid_code        <= '0';
+  rmon_o.rx_overrun             <= '0';
+  rmon_o.rx_ok                  <= '0';
+  rmon_o.rx_buffer_overrun      <= '0';
+  rmon_o.rx_rtu_overrun         <= '0';
+  rmon_o.rx_path_timing_failure <= '0';
+  rmon_o.tx_pause               <= '0';
+  rmon_o.tx_underrun            <= '0';
+  rmon_o.tx_frame               <= '0';
+
+end behavioral;
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_pcs_16bit.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_pcs_16bit.vhd
new file mode 100644
index 000000000..ea0fd8818
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_pcs_16bit.vhd
@@ -0,0 +1,765 @@
+-------------------------------------------------------------------------------
+-- Title      : 1000BaseT/X MAC Endpoint - receive path PCS for 1000BaseX
+-- Project    : White Rabbit Switch
+-------------------------------------------------------------------------------
+-- File       : ep_rx_pcs_16bit.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2009-06-16
+-- Last update: 2017-02-20
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Module implements the reception path for 1000BaseX PCS
+-- (Physical Coding Sublayer) with native 16-bit datapath.
+-- It provides synchronization between the PHY RX clock and system reference clock,
+-- elastic buffering, preamble, SFD and other 8b10b patterns recognition.
+-- It also generates deterministic timestamping pulses for RXed packets.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2011-2017 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author    Description
+-- 2011-10-17  0.2      twlostow  Virtex6 port
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.gencores_pkg.all;
+use work.endpoint_private_pkg.all;
+use work.endpoint_pkg.all;
+
+entity ep_rx_pcs_16bit is
+  generic (
+    g_simulation : boolean);
+  port (
+-- 62.5 MHz refclk divided by 2
+    clk_sys_i : in std_logic;
+
+-- reset (refclk2-synchronous)
+    rst_n_i : in std_logic;
+
+-- reset (phy_rx_clk_i sync)
+    rst_rxclk_n_i : in std_logic;
+
+    pcs_fifo_almostfull_i : in  std_logic;
+-- RX path busy indicator (active HI).
+-- When asserted, the receiver is in the middle of reception of a frame
+    pcs_busy_o            : out std_logic;
+-- data FIFO output
+    pcs_fab_o             : out t_ep_internal_fabric;
+
+
+    timestamp_trigger_p_a_o : out std_logic;  -- strobe for RX timestamping
+    timestamp_i       : in  std_logic_vector(31 downto 0);
+    timestamp_stb_i: in std_logic;
+    timestamp_valid_i : in  std_logic;
+
+-------------------------------------------------------------------------------
+-- PHY interface
+-------------------------------------------------------------------------------    
+
+    phy_rdy_i        : in std_logic;
+    phy_rx_clk_i     : in std_logic;
+    phy_rx_data_i    : in std_logic_vector(15 downto 0);
+    phy_rx_k_i       : in std_logic_vector(1 downto 0);
+    phy_rx_enc_err_i : in std_logic;
+
+-------------------------------------------------------------------------------
+-- Wishbone registers
+-------------------------------------------------------------------------------    
+
+    -- Receive control regsiter
+    mdio_mcr_reset_i           : in  std_logic;
+    mdio_mcr_pdown_i           : in  std_logic;
+    mdio_wr_spec_cal_crst_i    : in  std_logic;
+    mdio_wr_spec_rx_cal_stat_o : out std_logic;
+
+    synced_o    : out std_logic;
+    sync_lost_o : out std_logic;
+
+    -- autonegotiation signals
+    an_rx_en_i      : in  std_logic;
+    an_rx_val_o     : out std_logic_vector(15 downto 0);
+    an_rx_valid_o   : out std_logic;
+    an_idle_match_o : out std_logic;
+
+    -- RMON events
+    rmon_rx_overrun   : out std_logic;
+    rmon_rx_inv_code  : out std_logic;
+    rmon_rx_sync_lost : out std_logic;
+     
+    nice_dbg_o  : out t_dbg_ep_rxpcs
+    );
+
+end ep_rx_pcs_16bit;
+
+architecture behavioral of ep_rx_pcs_16bit is
+
+-- RX state machine definitions
+  type t_tbif_rx_state is (RX_NOFRAME, RX_CR, RX_SPD_PREAMBLE, RX_PAYLOAD, RX_EXTEND);
+
+-- size of the calibrration pattern detection counter. It counts up every time
+-- a valid calibration pattern character is received and resets upon detecion
+-- of non-calibration character. The pattern is validated when the counter
+-- overflows (after 2**c_cal_pattern_counter_bits counts)
+
+  function f_calc_pattern_counter_bits
+    return integer is
+  begin  -- f_calc_pattern_counter_bits
+    if(g_simulation) then
+      return 8;                         -- use smaller calibration counter to
+                                        -- speed up the simulation
+    else
+      return 17;
+    end if;
+  end f_calc_pattern_counter_bits;
+
+  function f_to_sl(x : boolean) return std_logic is
+  begin
+    if(x) then
+      return '1';
+    else
+      return '0';
+    end if;
+  end f_to_sl;
+
+
+  constant c_cal_pattern_counter_bits : integer := f_calc_pattern_counter_bits;
+
+  component ep_sync_detect_16bit
+    port (
+      rst_n_i  : in  std_logic;
+      rbclk_i  : in  std_logic;
+      en_i     : in  std_logic;
+      data_i   : in  std_logic_vector(15 downto 0);
+      k_i      : in  std_logic_vector(1 downto 0);
+      err_i    : in  std_logic;
+      synced_o : out std_logic;
+      cal_i    : in  std_logic);
+  end component;
+
+  signal rst_n_rx : std_logic;
+
+  signal rx_state         : t_tbif_rx_state;
+  signal preamble_cntr    : unsigned(2 downto 0);
+  signal rx_busy          : std_logic;
+  signal rx_enable_synced : std_logic;
+  signal rx_rdreq         : std_logic;
+
+  -- 8b10b decoding and postprocessing signals
+  signal d_data                                 : std_logic_vector(15 downto 0);
+  signal d_err, d_is_idle, d_is_spd_preamble    : std_logic;
+  signal d_is_eof_extend, d_is_eof, d_is_extend : std_logic;
+  signal d_is_preamble, d_is_preamble_sfd       : std_logic;
+  signal d_is_k                                 : std_logic_vector(1 downto 0);
+  signal d_is_lcr                               : std_logic;
+  signal d_is_cal                               : std_logic;
+
+-- Synchronization detection FSM signals
+  signal rx_synced      : std_logic;
+  signal rx_sync_lost_p : std_logic;
+  signal rx_sync_status : std_logic;
+  signal rx_sync_enable : std_logic;
+
+-- Autonegotiation control signals
+  signal an_rx_en_synced : std_logic;
+
+  signal lcr_ready         : std_logic;
+  signal lcr_prev_val      : std_logic_vector(15 downto 0);
+  signal lcr_cur_val       : std_logic_vector(15 downto 0);
+  signal lcr_final_val     : std_logic_vector(15 downto 0);
+  signal lcr_validity_cntr : unsigned(1 downto 0);
+
+  signal an_idle_cntr      : unsigned(1 downto 0);
+  signal an_idle_match_int : std_logic;
+
+-- RMON counter pulses
+  signal rmon_rx_overrun_p_int   : std_logic;
+  signal rmon_syncloss_p_int     : std_logic;
+  signal rmon_invalid_code_p_int : std_logic;
+
+-- Misc. signals
+  signal cal_pattern_cntr      : unsigned(c_cal_pattern_counter_bits-1 downto 0);
+  signal mdio_mcr_reset_synced : std_logic;
+  signal mdio_mcr_pdown_synced : std_logic;
+
+
+  signal pcs_valid_int     : std_logic;
+  signal timestamp_pending : std_logic_vector(2 downto 0) := "000";
+  
+begin
+-------------------------------------------------------------------------------
+-- synchronizer chains for Wishbone-accessible control signals
+-------------------------------------------------------------------------------
+
+  U_sync_pcs_busy : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_sys_i,
+      rst_n_i  => '1',
+      data_i   => rx_busy,
+      synced_o => pcs_busy_o,
+      npulse_o => open,
+      ppulse_o => open);
+
+  U_sync_an_rx_enable : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => phy_rx_clk_i,
+      rst_n_i  => rst_n_rx,
+      data_i   => an_rx_en_i,
+      synced_o => an_rx_en_synced,
+      npulse_o => open,
+      ppulse_o => open);
+
+  U_sync_mcr_reset : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => phy_rx_clk_i,
+      rst_n_i  => '1',
+      data_i   => mdio_mcr_reset_i,
+      synced_o => mdio_mcr_reset_synced,
+      npulse_o => open,
+      ppulse_o => open);
+
+  U_sync_power_down : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => phy_rx_clk_i,
+      rst_n_i  => '1',
+      data_i   => mdio_mcr_pdown_i,
+      synced_o => mdio_mcr_pdown_synced,
+      npulse_o => open,
+      ppulse_o => open);
+
+  rx_sync_enable <= not mdio_mcr_pdown_synced;
+  rst_n_rx  <= rst_rxclk_n_i and not mdio_mcr_reset_synced and phy_rdy_i;
+
+-------------------------------------------------------------------------------
+-- 802.3z Link Synchronization State Machine
+-------------------------------------------------------------------------------
+
+  U_SYNC_DET : ep_sync_detect_16bit
+    port map (
+      rst_n_i  => rst_n_rx,
+      rbclk_i  => phy_rx_clk_i,
+      en_i     => rx_sync_enable,
+      data_i   => phy_rx_data_i,
+      k_i      => phy_rx_k_i,
+      err_i    => phy_rx_enc_err_i,
+      synced_o => rx_synced,
+      cal_i    => d_is_cal);
+
+  -- synchronizer chain for rx_synced signal, also serving as a loss-of-sync detector
+  U_sync_los : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_sys_i,
+      rst_n_i  => '1',
+      data_i   => rx_synced,
+      synced_o => rx_sync_status,
+      npulse_o => rx_sync_lost_p,
+      ppulse_o => open);
+
+  synced_o    <= rx_sync_status;        -- drive the PCS outputs
+  sync_lost_o <= rx_sync_lost_p;
+
+-------------------------------------------------------------------------------
+-- Calibration pattern logic
+-------------------------------------------------------------------------------
+
+  -- process checks the presence of valid calibtaion pattern and controls the
+  -- state of CAL_STA bit in Receive Control Register.
+  --
+  -- reads: phy_rx_data_i, mdio_wr_spec_cal_crst_i
+  -- writes: mdio_wr_spec_rx_cal_stat_o
+  --
+  p_detect_cal : process(phy_rx_clk_i)
+  begin
+    if rising_edge(phy_rx_clk_i) then
+      if rst_n_rx = '0' then
+        cal_pattern_cntr <= (others => '0');
+        d_is_cal         <= '0';
+      else
+
+        d_is_cal <= f_to_sl(phy_rx_data_i = (c_k28_7 & c_k28_7) and phy_rx_k_i = "11");
+
+        if(d_is_cal = '1' and mdio_wr_spec_cal_crst_i = '0') then
+
+-- we've got c_cal_pattern_threshold valid calibration characters - indicate
+-- that we're receiving a valid calibration pattern
+          if(cal_pattern_cntr(cal_pattern_cntr'high) = '1') then
+            mdio_wr_spec_rx_cal_stat_o <= '1';
+          else
+            mdio_wr_spec_rx_cal_stat_o <= '0';
+            cal_pattern_cntr           <= cal_pattern_cntr + 1;
+          end if;
+-- we've got a non-calibration character or the pattern detection has been reset
+        else
+          mdio_wr_spec_rx_cal_stat_o <= '0';
+          cal_pattern_cntr           <= (others => '0');
+        end if;
+      end if;
+    end if;
+  end process;
+
+
+-------------------------------------------------------------------------------
+-- Clock adjustment FIFO
+-------------------------------------------------------------------------------  
+
+
+  -- process postprocesses the raw 8b10b decoder output (phy_rx_data_i, phy_rx_k_i, phy_rx_enc_err_ior)
+  -- providing 1-bit signals indicating various 8b10b control patterns
+  p_8b10b_postprocess : process(phy_rx_clk_i)
+  begin
+    if rising_edge(phy_rx_clk_i) then
+      
+      if(rst_n_rx = '0' or rx_synced = '0') then
+        d_data            <= (others => '0');
+        d_is_idle         <= '0';
+        d_is_k            <= "00";
+        d_is_spd_preamble <= '0';
+        d_is_preamble_sfd <= '0';
+        d_is_preamble     <= '0';
+        d_is_eof          <= '0';
+        d_is_extend       <= '0';
+        d_is_eof_extend   <= '0';
+        d_is_lcr          <= '0';
+        d_err             <= '0';
+      else
+
+        d_data <= phy_rx_data_i;
+        d_is_k <= phy_rx_k_i;
+
+        if(phy_rx_enc_err_i = '0') then
+          d_err <= '0';
+
+          
+          d_is_idle <= f_to_sl(phy_rx_data_i(15 downto 8) = c_K28_5
+                               and (phy_rx_data_i(7 downto 0) = c_d16_2
+                                    or phy_rx_data_i(7 downto 0) = c_d5_6)
+                               and phy_rx_k_i = "10");
+
+
+          d_is_spd_preamble <= f_to_sl(
+            phy_rx_data_i(15 downto 8) = c_k27_7
+            and phy_rx_data_i(7 downto 0) = c_preamble_char
+            and phy_rx_k_i = "10");
+
+          d_is_preamble <= f_to_sl(
+            phy_rx_data_i = c_preamble_char & c_preamble_char
+            and phy_rx_k_i = "00");
+
+          d_is_preamble_sfd <= f_to_sl(
+            phy_rx_data_i = c_preamble_char & c_preamble_sfd
+            and phy_rx_k_i = "00");
+
+-- data + EPD
+          d_is_eof <= f_to_sl(
+            phy_rx_data_i(7 downto 0) = c_K29_7
+            and phy_rx_k_i = "01");
+
+          -- EPD + extend
+          d_is_eof_extend <= f_to_sl(
+            phy_rx_data_i(15 downto 8) = c_K29_7
+            and phy_rx_data_i(7 downto 0) = c_k23_7
+            and phy_rx_k_i = "11");
+
+          d_is_extend <= f_to_sl(
+            phy_rx_data_i = c_K23_7 & c_K23_7
+            and phy_rx_k_i = "11");
+
+          d_is_lcr <= f_to_sl(
+            phy_rx_data_i(15 downto 8) = c_K28_5
+            and (phy_rx_data_i(7 downto 0) = c_d21_5
+                 or phy_rx_data_i(7 downto 0) = c_d2_2)
+            and phy_rx_k_i = "10");
+
+
+-- invalid code received?
+        else
+          d_err             <= '1';
+          d_is_idle         <= 'X';
+          d_is_spd_preamble <= 'X';
+          d_is_preamble_sfd <= 'X';
+          d_is_preamble     <= 'X';
+          d_is_eof          <= 'X';
+          d_is_extend       <= 'X';
+          d_is_eof_extend   <= 'X';
+          d_is_lcr          <= 'X';
+        end if;
+      end if;
+    end if;
+  end process;
+
+-- process: RBCLK-driven RX state machine. Implements the receive logic od 802.3z compliant
+-- 1000BaseX PCS.
+-- reads: almost everything
+-- writes: almost everything
+
+  
+  rx_fsm : process (phy_rx_clk_i)
+  begin
+    if rising_edge(phy_rx_clk_i) then
+      -- reset or PCS disabled
+      if(rst_n_rx = '0' or mdio_mcr_pdown_synced = '1') then
+        rx_state <= RX_NOFRAME;
+        rx_busy  <= '0';
+
+        pcs_fab_o.sof    <= '0';
+        pcs_fab_o.eof    <= '0';
+        pcs_fab_o.error  <= '0';
+        pcs_fab_o.dvalid <= '0';
+        pcs_fab_o.bytesel <= '0';
+        pcs_fab_o.has_rx_timestamp <= '0';
+        pcs_fab_o.data <= (others => 'X');
+
+        lcr_ready         <= '0';
+        lcr_cur_val       <= (others => '0');
+        lcr_prev_val      <= (others => '0');
+        -- lcr_final_val ===> DO NOT CLEAR on reset
+        lcr_validity_cntr <= (others => '0');
+        an_idle_cntr      <= (others => '0');
+        an_idle_match_int <= '0';
+
+        rmon_rx_overrun_p_int   <= '0';
+        rmon_invalid_code_p_int <= '0';
+        timestamp_trigger_p_a_o <= '0';
+        timestamp_pending       <= "000";
+      else                              -- normal PCS operation
+
+        -- clear the autogotiation variables if the autonegotiation is disabled
+        if(an_rx_en_synced = '0') then
+          lcr_ready         <= '0';
+          lcr_validity_cntr <= (others => '0');
+          lcr_prev_val      <= (others => '0');
+          an_idle_cntr      <= (others => '0');
+          an_idle_match_int <= '0';
+        end if;
+
+-------------------------------------------------------------------------------
+-- Main RX PCS state machine
+-------------------------------------------------------------------------------          
+        case rx_state is
+
+-------------------------------------------------------------------------------
+-- State NOFRAME: receiver is receiving IDLE pattern
+-------------------------------------------------------------------------------            
+          when RX_NOFRAME =>
+
+            preamble_cntr <= "011";
+            pcs_fab_o.eof   <= '0';
+            pcs_fab_o.error <= '0';
+            pcs_fab_o.bytesel <= '0';
+            pcs_fab_o.has_rx_timestamp <= '0';
+
+            rx_busy           <= '0';
+            timestamp_trigger_p_a_o <= '0';
+
+            -- insert the RX timestamp into the FIFO
+            if(timestamp_pending /= "000") then
+              pcs_fab_o.dvalid <= '1';
+            else
+              pcs_fab_o.dvalid <= '0';
+            end if;
+
+            if(timestamp_pending(0) = '1')then
+              pcs_fab_o.data <= timestamp_i(31 downto 16);
+              pcs_fab_o.eof  <= '0';
+            elsif(timestamp_pending(1) = '1')then
+              pcs_fab_o.data <= timestamp_i(15 downto 0);
+              pcs_fab_o.eof  <= '0';
+            elsif(timestamp_pending(2) = '1')then
+              pcs_fab_o.data <= (others => 'X');
+              pcs_fab_o.eof  <= '1';
+            end if;
+
+            timestamp_pending <= timestamp_pending(1 downto 0) & '0';
+
+            if (rx_synced = '0') then  -- PCS is not synced: stay in NOFRAME state and ignore the incoming codes.
+              rx_state <= RX_NOFRAME;
+            else
+
+              if(d_is_spd_preamble = '1') then  -- we've got a Start-of-Packet Delimeter
+                if(pcs_fifo_almostfull_i = '0') then
+                  rx_state <= RX_SPD_PREAMBLE;
+                else
+                  rx_state              <= RX_NOFRAME;
+                  rmon_rx_overrun_p_int <= '1';
+                end if;
+              end if;
+
+              if (d_is_lcr = '1') then
+                rx_state          <= RX_CR;
+                an_idle_match_int <= '0';
+                an_idle_cntr      <= (others => '0');
+                rx_busy           <= '1';
+              end if;
+
+              if(d_is_idle = '1') then
+                lcr_ready         <= '0';
+                an_idle_match_int <= '0';
+                an_idle_cntr      <= (others => '0');
+                lcr_validity_cntr <= (others => '0');
+
+                if(an_idle_cntr = "11") then
+                  an_idle_match_int <= '1';
+                else
+                  an_idle_cntr <= an_idle_cntr + 1;
+                end if;
+                rx_busy <= '0';
+              end if;
+            end if;
+
+-- produce a pulse at every invalid 8b10b code.
+            rmon_invalid_code_p_int <= d_err;
+
+-------------------------------------------------------------------------------
+-- States CR3/CR4: reception of LCR register value.
+-------------------------------------------------------------------------------              
+          when RX_CR =>  -- receives the 1st byte of Config_Reg and
+            -- checks if the subsequent Config_Reg
+            -- values are identical.
+
+-- an error? - abort the reception and go to NOFRAME state.
+            if(d_err = '1' or d_is_k /= "00" or rx_synced = '0') then
+              rx_state                <= RX_NOFRAME;
+              rmon_invalid_code_p_int <= d_err;
+
+              -- reset the Config_Reg value and mark it as invalid
+              lcr_ready         <= '0';
+              lcr_validity_cntr <= (others => '0');
+
+-- check if the autonegotiation unit has enabled the reception of LCR
+            elsif (an_rx_en_synced = '1') then
+              lcr_prev_val <= lcr_cur_val;
+
+-- check for 3 subsequent Configuration sequences with identical Config_Reg value
+              if(lcr_cur_val = lcr_prev_val) then
+                if(lcr_validity_cntr = "10") then
+-- we've got 3? Indicate that we have received valid Config_Reg.
+                  lcr_ready <= '1';
+                  lcr_final_val <= lcr_cur_val;
+                else
+                  lcr_validity_cntr <= lcr_validity_cntr + 1;
+                  lcr_ready         <= '0';
+                end if;
+              else
+-- the subsequent values of Config_Reg are different?
+                lcr_validity_cntr <= (others => '0');
+                lcr_ready         <= '0';
+              end if;
+
+              lcr_cur_val <= d_data(7 downto 0) & d_data(15 downto 8);
+            end if;
+
+            rx_state <= RX_NOFRAME;
+
+-------------------------------------------------------------------------------
+-- State SPD_PREAMBLE: we've received an Start-Of-Packet delimeter. Check for
+-- the valid preamble.
+-------------------------------------------------------------------------------                            
+          when RX_SPD_PREAMBLE =>
+
+            rx_busy <= '1';
+
+            if(d_err = '1' or rx_synced = '0') then  -- check for encoding errors.
+              rx_state                <= RX_NOFRAME;
+              rmon_invalid_code_p_int <= d_err;
+            else
+
+              -- keep looking for Ethernet SFD char (0xd5). If it occurs on
+              -- the right position, start receiving the frame payload
+              if d_is_preamble_sfd = '1' then
+-- generate the RX timestamp pulse
+                timestamp_trigger_p_a_o <= '1';
+
+-- we've got an SFD at proper offset from the beginning of the preamble
+                if (preamble_cntr = "010") or (preamble_cntr = "001") then
+
+-- indicate a start-of-packet condition in the RX FIFO and enable writing to
+-- the FIFO.
+                  pcs_fab_o.sof <= '1';
+                  rx_state      <= RX_PAYLOAD;
+                end if;
+                
+              elsif (d_is_preamble = '1') then
+                preamble_cntr <= preamble_cntr - 1;
+              -- got duplicated SPD code?
+              elsif (d_is_spd_preamble = '1') then
+                preamble_cntr <= "111";
+              else
+                rx_state                <= RX_NOFRAME;  -- not a preamble sequence?
+                rmon_invalid_code_p_int <= '1';
+              end if;
+
+              if(preamble_cntr = "000") then  -- too long preamble - abort reception
+                rx_state <= RX_NOFRAME;
+              end if;
+            end if;
+
+-------------------------------------------------------------------------------
+-- State PAYLOAD: receives the full frame payload (including the MAC header and
+-- the CRC)
+-------------------------------------------------------------------------------
+
+          when RX_PAYLOAD =>
+
+            pcs_fab_o.sof <= '0';
+            pcs_fab_o.eof <= '0';
+            pcs_fab_o.has_rx_timestamp <= '0';
+            pcs_fab_o.data <= d_data;
+
+            -- check for errors.
+            if (d_err = '1' or rx_synced = '0' or pcs_fifo_almostfull_i = '1'
+                or (d_is_k /= "00" and d_is_eof_extend = '0' and d_is_eof = '0')) then
+
+              -- indicate an errorneous termination of the current frame in the
+              -- RX FIFO
+              pcs_fab_o.error <= '1';
+              pcs_fab_o.dvalid <= '0';
+              pcs_fab_o.bytesel <= 'X';
+              
+              rmon_invalid_code_p_int <= d_err;
+              rmon_rx_overrun_p_int   <= pcs_fifo_almostfull_i;
+
+              rx_state <= RX_NOFRAME;
+            elsif d_is_eof = '1' or d_is_eof_extend = '1' then
+
+              pcs_fab_o.error <= '0';
+
+              if d_is_eof = '1' then    -- got EPD at even position
+                pcs_fab_o.bytesel <= '1';
+                pcs_fab_o.dvalid  <= '1';
+                rx_state          <= RX_EXTEND;
+              else
+                pcs_fab_o.bytesel <= '0';
+                pcs_fab_o.dvalid  <= '0';
+                rx_state          <= RX_EXTEND;
+              end if;
+              
+            else
+              pcs_fab_o.bytesel <= '0';
+              pcs_fab_o.error  <= '0';
+              pcs_fab_o.dvalid <= '1';
+            end if;
+
+
+-------------------------------------------------------------------------------
+-- State EXTEND: receive carrier extension
+-------------------------------------------------------------------------------
+
+          when RX_EXTEND =>
+
+            timestamp_trigger_p_a_o <= '0';
+            pcs_fab_o.dvalid  <= '0';
+
+            if d_is_extend = '1' then   -- got carrier extend. Just keep
+                                        -- receiving it.
+              rx_state        <= RX_EXTEND;
+              pcs_fab_o.eof   <= '0';
+              pcs_fab_o.error <= '0';
+            elsif d_is_idle = '1' then  -- got comma, real end-of-frame
+              -- indicate the correct ending of the current frame in the RX FIFO
+              pcs_fab_o.eof              <= not timestamp_stb_i;
+              pcs_fab_o.error            <= '0';
+              pcs_fab_o.has_rx_timestamp <= timestamp_stb_i;
+              timestamp_pending          <= (others => timestamp_stb_i);
+
+              rx_state <= RX_NOFRAME;
+            else
+              -- got anything else than comma (for example, the /V/ code):
+              pcs_fab_o.error         <= '1';
+              rmon_invalid_code_p_int <= '1';
+              rx_state                <= RX_NOFRAME;
+            end if;
+        end case;
+      end if;
+    end if;     
+  end process;
+
+  an_rx_val_o <= lcr_final_val;
+
+  U_sync_an_rx_ready : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_sys_i,
+      rst_n_i  => rst_n_i,
+      data_i   => lcr_ready,
+      synced_o => an_rx_valid_o,
+      npulse_o => open,
+      ppulse_o => open);
+
+  U_sync_an_idle_match : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_sys_i,
+      rst_n_i  => rst_n_i,
+      data_i   => an_idle_match_int,
+      synced_o => an_idle_match_o,
+      npulse_o => open,
+      ppulse_o => open);
+
+  U_ext_rmon_1 : gc_extend_pulse
+    generic map (
+      g_width => 3)
+    port map (
+      clk_i      => phy_rx_clk_i,
+      rst_n_i    => rst_n_rx,
+      pulse_i    => rmon_invalid_code_p_int,
+      extended_o => rmon_rx_inv_code);
+
+  U_ext_rmon_2 : gc_extend_pulse
+    generic map (
+      g_width => 3)
+    port map (
+      clk_i      => phy_rx_clk_i,
+      rst_n_i    => rst_n_rx,
+      pulse_i    => rmon_rx_overrun_p_int,
+      extended_o => rmon_rx_overrun);
+
+-- drive the "RX PCS Sync Lost" event counter
+  rmon_rx_sync_lost <= rx_sync_lost_p and (not mdio_mcr_pdown_i);
+
+  pcs_fab_o.rx_timestamp_valid <= timestamp_valid_i;
+
+  nice_dbg_o.fsm <= "000" when (rx_state = RX_NOFRAME) else
+                    "001" when (rx_state = RX_CR) else
+                    "010" when (rx_state = RX_SPD_PREAMBLE) else
+                    "011" when (rx_state = RX_PAYLOAD) else
+                    "100" when (rx_state = RX_EXTEND) else
+                    "111";
+
+end behavioral;
+
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_pcs_8bit.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_pcs_8bit.vhd
new file mode 100644
index 000000000..9310cf36a
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_pcs_8bit.vhd
@@ -0,0 +1,858 @@
+-------------------------------------------------------------------------------
+-- Title      : 1000BaseT/X MAC Endpoint - receive path PCS for 1000BaseX
+-- Project    : White Rabbit Switch
+-------------------------------------------------------------------------------
+-- File       : ep_rx_pcs_tbi.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2009-06-16
+-- Last update: 2017-02-20
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Module implements the reception path for 1000BaseX PCS
+-- (Physical Coding Sublayer). It provides synchronization between the PHY RX
+-- clock and system reference clock, elastic buffering, preamble, SFD and other
+-- 8b10b patterns recognition. It also generates deterministic timestamping
+-- pulses for RXed packets.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2009-2017 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author    Description
+-- 2009-06-16  0.1      twlostow  Created (no error propagation supported yet)
+-- 2010-10-25  0.2      twlostow  Names updated to comply with the coding,
+--                                added some comments
+-- 2010-11-18  0.4      twlostow  Added support for Xilinx GTP transceivers.
+-- 2011-02-07  0.5      twlostow  Tested on Spartan6 GTP
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.gencores_pkg.all;
+use work.genram_pkg.all;
+use work.endpoint_private_pkg.all;
+use work.endpoint_pkg.all;
+
+entity ep_rx_pcs_8bit is
+  generic (
+    g_simulation : boolean);
+  port (
+-- 62.5 MHz refclk divided by 2
+    clk_sys_i : in std_logic;
+
+-- reset (refclk2-synchronous)
+    rst_n_i : in std_logic;
+
+-- reset (phy_rx_clk_i sync)
+    rst_rxclk_n_i : in std_logic;
+
+    pcs_fifo_almostfull_i : in  std_logic;
+-- RX path busy indicator (active HI).
+-- When asserted, the receiver is in the middle of reception of a frame
+    pcs_busy_o            : out std_logic;
+-- data FIFO output
+    pcs_fab_o             : out t_ep_internal_fabric;
+
+
+    timestamp_trigger_p_a_o : out std_logic;  -- strobe for RX timestamping
+
+    timestamp_i           : in  std_logic_vector(31 downto 0);
+    timestamp_stb_i       : in  std_logic;
+    timestamp_valid_i     : in  std_logic;
+
+-------------------------------------------------------------------------------
+-- PHY interface
+-------------------------------------------------------------------------------    
+
+    phy_rdy_i        : in std_logic;
+    phy_rx_clk_i     : in std_logic;
+    phy_rx_data_i    : in std_logic_vector(7 downto 0);
+    phy_rx_k_i       : in std_logic;
+    phy_rx_enc_err_i : in std_logic;
+
+-------------------------------------------------------------------------------
+-- Wishbone registers
+-------------------------------------------------------------------------------    
+
+    -- Receive control regsiter
+    mdio_mcr_reset_i           : in  std_logic;
+    mdio_mcr_pdown_i           : in  std_logic;
+    mdio_wr_spec_cal_crst_i    : in  std_logic;
+    mdio_wr_spec_rx_cal_stat_o : out std_logic;
+
+    synced_o    : out std_logic;
+    sync_lost_o : out std_logic;
+
+    -- autonegotiation signals
+    an_rx_en_i      : in  std_logic;
+    an_rx_val_o     : out std_logic_vector(15 downto 0);
+    an_rx_valid_o   : out std_logic;
+    an_idle_match_o : out std_logic;
+
+    -- RMON events
+    rmon_rx_overrun   : out std_logic;
+    rmon_rx_inv_code  : out std_logic;
+    rmon_rx_sync_lost : out std_logic
+    );
+
+end ep_rx_pcs_8bit;
+
+architecture behavioral of ep_rx_pcs_8bit is
+
+-- RX state machine definitions
+  type t_tbif_rx_state is (RX_NOFRAME, RX_COMMA, RX_CR3, RX_CR4, RX_SPD_PREAMBLE, RX_PAYLOAD, RX_EXTEND);
+
+-- size of the calibrration pattern detection counter. It counts up every time
+-- a valid calibration pattern character is received and resets upon detecion
+-- of non-calibration character. The pattern is validated when the counter
+-- overflows (after 2**c_cal_pattern_counter_bits counts)
+
+
+  function f_calc_pattern_counter_bits
+    return integer is
+  begin  -- f_calc_pattern_counter_bits
+    if(g_simulation) then
+      return 8;                         -- use smaller calibration counter to
+                                        -- speed up the simulation
+    else
+      return 17;
+    end if;
+  end f_calc_pattern_counter_bits;
+
+  constant c_cal_pattern_counter_bits : integer := f_calc_pattern_counter_bits;
+
+  component ep_sync_detect
+    port (
+      rst_n_i  : in  std_logic;
+      rbclk_i  : in  std_logic;
+      en_i     : in  std_logic;
+      data_i   : in  std_logic_vector(7 downto 0);
+      k_i      : in  std_logic;
+      err_i    : in  std_logic;
+      synced_o : out std_logic;
+      even_o   : out std_logic;
+      cal_i    : in  std_logic);
+  end component;
+
+  signal rst_n_rx : std_logic;
+
+  signal rx_state             : t_tbif_rx_state;
+  signal preamble_cntr        : unsigned(2 downto 0);
+  signal rx_busy              : std_logic;
+  signal rx_enable_synced     : std_logic;
+  signal rx_rdreq, fifo_wrreq : std_logic;
+
+  -- 8b10b decoding and postprocessing signals
+  signal d_is_k, d_err, d_is_comma, d_is_epd        : std_logic;
+  signal d_is_spd, d_is_extend, d_is_idle, d_is_lcr : std_logic;
+  signal d_is_sfd_char, d_is_preamble_char          : std_logic;
+  signal d_data                                     : std_logic_vector(7 downto 0);
+  signal d_is_even                                  : std_logic;
+  signal d_is_cal                                   : std_logic;
+
+  -- Clock alignment FIFO signals
+  signal fifo_wr_toggle     : std_logic;
+  signal fifo_rx_data       : std_logic_vector(15 downto 0);
+  signal fifo_mask_write    : std_logic;
+  signal fifo_bytesel       : std_logic;
+  signal fifo_sof, fifo_eof : std_logic;
+  signal fifo_error         : std_logic;
+  signal fifo_almostfull    : std_logic;
+  signal fifo_clear_n       : std_logic;
+  signal fifo_with_rx_ts    : std_logic;
+  signal fifo_ts_valid    : std_logic;
+
+-- Synchronization detection FSM signals
+  signal rx_synced, rx_even : std_logic;
+  signal rx_sync_lost_p     : std_logic;
+  signal rx_sync_status     : std_logic;
+  signal rx_sync_enable     : std_logic;
+
+-- Autonegotiation control signals
+  signal an_rx_en_synced : std_logic;
+
+  signal lcr_ready         : std_logic;
+  signal lcr_prev_val      : std_logic_vector(15 downto 0);
+  signal lcr_cur_val       : std_logic_vector(15 downto 0);
+  signal lcr_final_val     : std_logic_vector(15 downto 0);
+  signal lcr_validity_cntr : unsigned(1 downto 0);
+
+  signal an_idle_cntr      : unsigned(1 downto 0);
+  signal an_idle_match_int : std_logic;
+
+-- RMON counter pulses
+  signal rmon_rx_overrun_p_int   : std_logic;
+  signal rmon_invalid_code_p_int : std_logic;
+
+-- Misc. signals
+  signal cal_pattern_cntr      : unsigned(c_cal_pattern_counter_bits-1 downto 0);
+  signal mdio_mcr_reset_synced : std_logic;
+  signal mdio_mcr_pdown_synced : std_logic;
+
+
+  signal pcs_valid_int     : std_logic;
+  signal timestamp_pending : std_logic_vector(2 downto 0);
+  
+begin
+-------------------------------------------------------------------------------
+-- synchronizer chains for Wishbone-accessible control signals
+-------------------------------------------------------------------------------
+
+  U_sync_pcs_busy : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_sys_i,
+      rst_n_i  => '1',
+      data_i   => rx_busy,
+      synced_o => pcs_busy_o,
+      npulse_o => open,
+      ppulse_o => open);
+
+  U_sync_an_rx_enable : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => phy_rx_clk_i,
+      rst_n_i  => rst_n_rx,
+      data_i   => an_rx_en_i,
+      synced_o => an_rx_en_synced,
+      npulse_o => open,
+      ppulse_o => open);
+
+  U_sync_mcr_reset : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => phy_rx_clk_i,
+      rst_n_i  => '1',
+      data_i   => mdio_mcr_reset_i,
+      synced_o => mdio_mcr_reset_synced,
+      npulse_o => open,
+      ppulse_o => open);
+
+  U_sync_power_down : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => phy_rx_clk_i,
+      rst_n_i  => '1',
+      data_i   => mdio_mcr_pdown_i,
+      synced_o => mdio_mcr_pdown_synced,
+      npulse_o => open,
+      ppulse_o => open);
+
+  rx_sync_enable <= not mdio_mcr_pdown_synced;
+  rst_n_rx  <= rst_rxclk_n_i and not mdio_mcr_reset_synced and phy_rdy_i;
+
+-------------------------------------------------------------------------------
+-- 802.3z Link Synchronization State Machine
+-------------------------------------------------------------------------------
+
+  U_SYNC_DET : ep_sync_detect
+    port map (
+      rst_n_i  => rst_n_rx,
+      rbclk_i  => phy_rx_clk_i,
+      en_i     => rx_sync_enable,
+      data_i   => phy_rx_data_i,
+      k_i      => phy_rx_k_i,
+      err_i    => phy_rx_enc_err_i,
+      synced_o => rx_synced,
+      even_o   => rx_even,
+      cal_i    => d_is_cal);
+
+  -- synchronizer chain for rx_synced signal, also serving as a loss-of-sync detector
+  U_sync_los : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_sys_i,
+      rst_n_i  => '1',
+      data_i   => rx_synced,
+      synced_o => rx_sync_status,
+      npulse_o => rx_sync_lost_p,
+      ppulse_o => open);
+
+  synced_o    <= rx_sync_status;        -- drive the PCS outputs
+  sync_lost_o <= rx_sync_lost_p;
+
+-------------------------------------------------------------------------------
+-- Calibration pattern logic
+-------------------------------------------------------------------------------
+
+  -- process checks the presence of valid calibtaion pattern and controls the
+  -- state of CAL_STA bit in Receive Control Register.
+  --
+  -- reads: phy_rx_data_i, mdio_wr_spec_cal_crst_i
+  -- writes: mdio_wr_spec_rx_cal_stat_o
+  --
+  p_detect_cal : process(phy_rx_clk_i)
+  begin
+    if rising_edge(phy_rx_clk_i) then
+      if rst_n_rx = '0' then
+        cal_pattern_cntr <= (others => '0');
+        d_is_cal         <= '0';
+      else
+        
+        if(phy_rx_data_i = c_k28_7 and phy_rx_k_i = '1') then
+          d_is_cal <= '1';
+        else
+          d_is_cal <= '0';
+        end if;
+
+        if(d_is_cal = '1' and mdio_wr_spec_cal_crst_i = '0') then
+
+-- we've got c_cal_pattern_threshold valid calibration characters - indicate
+-- that we're receiving a valid calibration pattern
+          if(cal_pattern_cntr(cal_pattern_cntr'high) = '1') then
+            mdio_wr_spec_rx_cal_stat_o <= '1';
+          else
+            mdio_wr_spec_rx_cal_stat_o <= '0';
+            cal_pattern_cntr           <= cal_pattern_cntr + 1;
+          end if;
+-- we've got a non-calibration character or the pattern detection has been reset
+        else
+          mdio_wr_spec_rx_cal_stat_o <= '0';
+          cal_pattern_cntr           <= (others => '0');
+        end if;
+      end if;
+    end if;
+  end process;
+
+
+-------------------------------------------------------------------------------
+-- Clock adjustment FIFO
+-------------------------------------------------------------------------------  
+
+  -- FIFO input data formatting
+  fifo_wrreq <= fifo_wr_toggle and fifo_mask_write;
+
+  pcs_fab_o.data             <= fifo_rx_data;
+  pcs_fab_o.addr             <= (others => '0');
+  pcs_fab_o.sof              <= fifo_sof and fifo_wrreq;
+  pcs_fab_o.eof              <= fifo_eof and fifo_wrreq;
+  pcs_fab_o.bytesel          <= fifo_bytesel;
+  pcs_fab_o.error            <= fifo_error and fifo_wrreq;
+  pcs_fab_o.has_rx_timestamp <= fifo_with_rx_ts;
+  pcs_fab_o.rx_timestamp_valid <= timestamp_valid_i;
+  pcs_fab_o.dvalid           <= not (fifo_sof or fifo_eof or fifo_error) and fifo_wrreq;
+
+  fifo_almostfull <= pcs_fifo_almostfull_i;
+
+  -- process postprocesses the raw 8b10b decoder output (phy_rx_data_i, phy_rx_k_i, phy_rx_enc_err_ior)
+  -- providing 1-bit signals indicating various 8b10b control patterns
+  p_8b10b_postprocess : process(phy_rx_clk_i)
+  begin
+    if rising_edge(phy_rx_clk_i) then
+      
+      if(rst_n_rx = '0') then
+        d_data             <= (others => '0');
+        d_is_comma         <= '0';
+        d_is_spd           <= '0';
+        d_is_extend        <= '0';
+        d_is_lcr           <= '0';
+        d_is_epd           <= '0';
+        d_is_idle          <= '0';
+        d_is_k             <= '0';
+        d_err              <= '0';
+        d_is_sfd_char      <= '0';
+        d_is_preamble_char <= '0';
+        d_err              <= '0';
+      else
+
+        -- store the odd/even field information from sync detection unit (U_SYNC_DET)
+        d_is_even <= rx_even;
+        d_data    <= phy_rx_data_i;
+        d_is_k    <= phy_rx_k_i;
+
+        if(phy_rx_enc_err_i = '0') then
+          d_err <= '0';
+
+-- decode commas and other control characters....
+          if(phy_rx_data_i = c_K28_5 and phy_rx_k_i = '1') then
+            d_is_comma <= '1';
+          else
+            d_is_comma <= '0';
+          end if;
+
+          if(phy_rx_data_i = c_k23_7 and phy_rx_k_i = '1') then
+            d_is_extend <= '1';
+          else
+            d_is_extend <= '0';
+          end if;
+
+          if(phy_rx_data_i = c_k27_7 and phy_rx_k_i = '1') then
+            d_is_spd <= '1';
+          else
+            d_is_spd <= '0';
+          end if;
+
+          if(phy_rx_data_i = c_K29_7 and phy_rx_k_i = '1') then
+            d_is_epd <= '1';
+          else
+            d_is_epd <= '0';
+          end if;
+
+          if((phy_rx_data_i = c_d21_5 or phy_rx_data_i = c_d2_2) and phy_rx_k_i = '0') then
+            d_is_lcr <= '1';
+          else
+            d_is_lcr <= '0';
+          end if;
+
+          if((phy_rx_data_i = c_d5_6 or phy_rx_data_i = c_d16_2) and phy_rx_k_i = '0') then
+            d_is_idle <= '1';
+          else
+            d_is_idle <= '0';
+          end if;
+
+          if(phy_rx_data_i = c_preamble_sfd and phy_rx_k_i = '0') then
+            d_is_sfd_char <= '1';
+          else
+            d_is_sfd_char <= '0';
+          end if;
+
+          if(phy_rx_data_i = c_preamble_char and phy_rx_k_i = '0') then
+            d_is_preamble_char <= '1';
+          else
+            d_is_preamble_char <= '0';
+          end if;
+
+-- invalid code received?
+        else
+          d_err              <= '1';
+          d_is_sfd_char      <= '0';
+          d_is_preamble_char <= '0';
+          d_is_comma         <= '0';
+          d_is_spd           <= '0';
+          d_is_extend        <= '0';
+          d_is_lcr           <= '0';
+          d_is_epd           <= '0';
+          d_is_idle          <= '0';
+          d_is_k             <= '0';
+        end if;
+      end if;
+    end if;
+  end process;
+
+
+-- process: RBCLK-driven RX state machine. Implements the receive logic od 802.3z compliant
+-- 1000BaseX PCS.
+-- reads: almost everything
+-- writes: almost everything
+
+  rx_fsm : process (phy_rx_clk_i)
+  begin
+    if rising_edge(phy_rx_clk_i) then
+      -- reset or PCS disabled
+      if(rst_n_rx = '0' or mdio_mcr_pdown_synced = '1') then
+        rx_state <= RX_NOFRAME;
+        rx_busy  <= '0';
+
+        fifo_sof        <= '0';
+        fifo_eof        <= '0';
+        fifo_error      <= '0';
+        fifo_wr_toggle  <= '0';
+        fifo_mask_write <= '0';
+        fifo_with_rx_ts <= '0';
+
+        lcr_ready         <= '0';
+        lcr_cur_val       <= (others => '0');
+        lcr_prev_val      <= (others => '0');
+        -- lcr_final_val ===> DO NOT CLEAR on reset
+        lcr_validity_cntr <= (others => '0');
+        an_idle_cntr      <= (others => '0');
+        an_idle_match_int <= '0';
+
+        rmon_rx_overrun_p_int   <= '0';
+        rmon_invalid_code_p_int <= '0';
+
+        timestamp_trigger_p_a_o <= '0';
+        timestamp_pending <= "000";
+      else                              -- normal PCS operation
+
+        -- clear the autogotiation variables if the autonegotiation is disabled
+        if(an_rx_en_synced = '0') then
+          lcr_ready         <= '0';
+          lcr_validity_cntr <= (others => '0');
+          lcr_prev_val      <= (others => '0');
+          an_idle_cntr      <= (others => '0');
+          an_idle_match_int <= '0';
+        end if;
+
+-------------------------------------------------------------------------------
+-- Main RX PCS state machine
+-------------------------------------------------------------------------------          
+        case rx_state is
+
+-------------------------------------------------------------------------------
+-- State NOFRAME: receiver is receiving IDLE pattern
+-------------------------------------------------------------------------------            
+          when RX_NOFRAME =>
+
+            
+            fifo_sof     <= '0';
+            fifo_eof     <= '0';
+            fifo_error   <= '0';
+            fifo_bytesel <= '0';
+
+            rx_busy           <= '0';
+            timestamp_trigger_p_a_o <= '0';
+
+            -- insert the RX timestamp into the FIFO
+            if(timestamp_pending /= "000") then
+              fifo_mask_write <= '1';
+              fifo_wr_toggle  <= '1';
+            else
+              fifo_mask_write <= '0';
+              fifo_wr_toggle  <= '0';
+            end if;
+
+            if(timestamp_pending(0) = '1')then
+              fifo_rx_data <= timestamp_i(31 downto 16);
+            elsif(timestamp_pending(1) = '1')then
+              fifo_rx_data <= timestamp_i(15 downto 0);
+            elsif(timestamp_pending(2) = '1')then
+              fifo_eof <= '1';
+            end if;
+
+            timestamp_pending <= timestamp_pending(1 downto 0) & '0';
+
+            if (rx_synced = '0') then
+-- PCS is not synced: stay in NOFRAME state and ignore the incoming codes.
+              rx_state <= RX_NOFRAME;
+
+            elsif(d_is_comma = '1') then
+-- we've got a comma character: it's probably an idle sequence or a Config_Reg value,
+-- check the next code.
+              rx_state <= RX_COMMA;
+            elsif (d_is_spd = '1') then
+-- we've got a Start-of-Packet Delimeter
+
+              if(d_is_even = '1' and fifo_almostfull = '0') then
+                preamble_cntr <= "111";
+                rx_state      <= RX_SPD_PREAMBLE;
+              elsif (fifo_almostfull = '1') then
+                rmon_rx_overrun_p_int <= '1';
+              end if;
+              
+            end if;
+
+
+-- produce a pulse at every invalid 8b10b code.
+            rmon_invalid_code_p_int <= d_err;
+
+-------------------------------------------------------------------------------
+-- State COMMA: we've received a comma character followed by something else.
+-- Determine what's "something else"
+-------------------------------------------------------------------------------                            
+
+          when RX_COMMA =>
+-- received a code with error (or a control code group) or a misaligned code:
+-- go to the initial NOFRAME state and account the error.
+
+            fifo_mask_write <= '0';
+            fifo_wr_toggle  <= '0';
+            fifo_with_rx_ts <= '0';
+
+            if (d_err = '1' or d_is_k = '1' or d_is_even = '1' or rx_synced = '0') then
+              rmon_invalid_code_p_int <= d_err;
+              rx_state                <= RX_NOFRAME;
+
+              lcr_ready         <= '0';
+              an_idle_match_int <= '0';
+              an_idle_cntr      <= (others => '0');
+            else
+
+-- don't write anything to the PCS FIFO, it's a control character
+              fifo_mask_write <= '0';
+
+-- received D5.6 or D16.2 - it's an idle pattern. Simply ignore it.
+              if(d_is_idle = '1') then
+                rx_state  <= RX_NOFRAME;
+                lcr_ready <= '0';
+
+
+                if(an_idle_cntr = "11") then
+                  an_idle_match_int <= '1';
+                else
+                  an_idle_cntr <= an_idle_cntr + 1;
+                end if;
+
+
+-- received D21.5 or D2.2 - it's a 802.3x autonegotiation Config_Reg (802.3 p.
+-- 36.2.4.10). Begin the reception of its value.
+              elsif(d_is_lcr = '1') then
+                an_idle_match_int <= '0';
+                an_idle_cntr      <= (others => '0');
+                rx_busy           <= '1';
+                rx_state          <= RX_CR3;
+              else
+                lcr_ready         <= '0';
+                an_idle_match_int <= '0';
+                an_idle_cntr      <= (others => '0');
+                lcr_validity_cntr <= (others => '0');
+              end if;
+            end if;
+
+-------------------------------------------------------------------------------
+-- States CR3/CR4: reception of LCR register value.
+-------------------------------------------------------------------------------              
+          when RX_CR3 =>  -- receives the 1st byte of Config_Reg and
+            -- checks if the subsequent Config_Reg
+            -- values are identical.
+
+-- an error? - abort the reception and go to NOFRAME state.
+            if(d_err = '1' or d_is_k = '1' or d_is_even = '0' or rx_synced = '0') then
+              rx_state                <= RX_NOFRAME;
+              rmon_invalid_code_p_int <= d_err;
+
+              -- reset the Config_Reg value and mark it as invalid
+              lcr_ready         <= '0';
+              lcr_validity_cntr <= (others => '0');
+
+-- check if the autonegotiation unit has enabled the reception of LCR
+            elsif (an_rx_en_synced = '1') then
+              lcr_prev_val <= lcr_cur_val;
+
+-- check for 3 subsequent Configuration sequences with identical Config_Reg value
+              if(lcr_cur_val = lcr_prev_val) then
+                if(lcr_validity_cntr = "10") then
+-- we've got 3? Indicate that we have received valid Config_Reg.
+                  lcr_ready <= '1';
+                  lcr_final_val <= lcr_cur_val; -- only latched here, not even on reset
+                else
+                  lcr_validity_cntr <= lcr_validity_cntr + 1;
+                  lcr_ready         <= '0';
+                end if;
+              else
+-- the subsequent values of Config_Reg are different?
+                lcr_validity_cntr <= (others => '0');
+                lcr_ready         <= '0';
+              end if;
+
+              lcr_cur_val (7 downto 0) <= d_data;
+            end if;
+
+            rx_state <= RX_CR4;
+
+          when RX_CR4 =>                -- receives the 2nd byte of LCR
+
+            if(d_err = '1' or d_is_k = '1' or d_is_even = '1' or rx_synced = '0') then
+              -- in case of an error
+              rx_state                <= RX_NOFRAME;
+              rmon_invalid_code_p_int <= d_err;
+            elsif (an_rx_en_synced = '1') then
+              -- store the value of the LSB of the Config_Reg
+              lcr_cur_val (15 downto 8) <= d_data;
+            end if;
+
+            rx_state <= RX_NOFRAME;
+
+-------------------------------------------------------------------------------
+-- State SPD_PREAMBLE: we've received an Start-Of-Packet delimeter. Check for
+-- the valid preamble.
+-------------------------------------------------------------------------------                            
+          when RX_SPD_PREAMBLE =>
+
+            rx_busy <= '1';
+
+            if(d_err = '1' or rx_synced = '0') then  -- check for encoding errors.
+              rx_state                <= RX_NOFRAME;
+              rmon_invalid_code_p_int <= d_err;
+            else
+
+              -- keep looking for Ethernet SFD char (0xd5). If it occurs on
+              -- the right position, start receiving the frame payload
+              if d_is_sfd_char = '1' then
+-- generate the RX timestamp pulse
+                timestamp_trigger_p_a_o <= '1';
+
+-- we've got an SFD at proper offset from the beginning of the preamble
+                if (preamble_cntr = "010") or (preamble_cntr = "001") then
+
+-- indicate a start-of-packet condition in the RX FIFO and enable writing to
+-- the FIFO.
+                  fifo_sof        <= '1';
+                  fifo_mask_write <= '1';
+                  fifo_wr_toggle  <= '1';
+                  rx_state        <= RX_PAYLOAD;
+                end if;
+                
+              elsif (d_is_preamble_char = '1') then
+                preamble_cntr <= preamble_cntr - 1;
+                -- got duplicated SPD code?
+              elsif (d_is_spd = '1') then
+                preamble_cntr <= "111";
+              end if;
+
+              if(preamble_cntr = "000") then  -- too long preamble - abort reception
+                rx_state <= RX_NOFRAME;
+              end if;
+            end if;
+
+-------------------------------------------------------------------------------
+-- State PAYLOAD: receives the full frame payload (including the MAC header and
+-- the CRC)
+-------------------------------------------------------------------------------
+
+          when RX_PAYLOAD =>
+
+            fifo_sof <= '0';
+
+            -- check for errors.
+            if (d_err = '1' or rx_synced = '0' or fifo_almostfull = '1') then
+              rmon_invalid_code_p_int <= d_err;
+              rmon_rx_overrun_p_int   <= fifo_almostfull;
+
+              rx_state <= RX_NOFRAME;
+
+              -- indicate an errorneous termination of the current frame in the
+              -- RX FIFO
+              fifo_error     <= '1';
+              fifo_wr_toggle <= '1';
+              
+            elsif d_is_k = '1' then
+              if d_is_epd = '1' then    -- got an EPD (End-of-packet delimeter)
+
+                fifo_bytesel   <= not fifo_wr_toggle;
+                fifo_wr_toggle <= not fifo_wr_toggle;
+
+                rx_state <= RX_EXTEND;
+
+              else
+                -- any other K-character in the middle of frame (premature
+                -- end)? - terminate the frame and indicate an error in the
+                -- RX FIFO.
+
+                if d_is_comma = '1' then  -- got link idle inside frame
+                  rx_state <= RX_COMMA;
+                else
+                  rx_state <= RX_NOFRAME;
+                end if;
+
+                fifo_error     <= '1';
+                fifo_wr_toggle <= '1';
+              end if;
+            else
+              -- got a data character. Every 2 characters, write them to the
+              -- 16-bit FIFO.
+
+              fifo_wr_toggle <= not fifo_wr_toggle;
+
+              if fifo_wr_toggle = '1' then
+                fifo_rx_data(15 downto 8) <= d_data;
+              else
+                fifo_rx_data(7 downto 0) <= d_data;
+              end if;
+            end if;
+
+-------------------------------------------------------------------------------
+-- State EXTEND: receive carrier extension
+-------------------------------------------------------------------------------
+
+          when RX_EXTEND =>
+
+            timestamp_trigger_p_a_o <= '0';
+
+            if d_is_extend = '1' then    -- got carrier extend. Just keep
+                                         -- receiving it.
+              fifo_mask_write <= '0';
+              rx_state        <= RX_EXTEND;
+            elsif d_is_comma = '1' then  -- got comma, real end-of-frame
+              -- indicate the correct ending of the current frame in the RX FIFO
+              fifo_eof          <= not timestamp_stb_i;
+              fifo_with_rx_ts   <= timestamp_stb_i;
+              fifo_mask_write   <= '1';
+              fifo_wr_toggle    <= '1';
+              timestamp_pending <= (others => timestamp_stb_i);
+
+
+              rx_state <= RX_COMMA;
+              
+            else
+              -- got anything else than comma (for example, the /V/ code):
+
+              rmon_invalid_code_p_int <= '1';
+              fifo_error              <= '1';
+              fifo_mask_write         <= '1';
+              fifo_wr_toggle          <= '1';
+
+              rx_state <= RX_NOFRAME;
+            end if;
+
+          when others => null;
+        end case;
+      end if;
+    end if;
+  end process;
+
+  an_rx_val_o <= lcr_final_val;
+
+  U_sync_an_rx_ready : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_sys_i,
+      rst_n_i  => rst_n_i,
+      data_i   => lcr_ready,
+      synced_o => an_rx_valid_o,
+      npulse_o => open,
+      ppulse_o => open);
+
+  U_sync_an_idle_match : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_sys_i,
+      rst_n_i  => rst_n_i,
+      data_i   => an_idle_match_int,
+      synced_o => an_idle_match_o,
+      npulse_o => open,
+      ppulse_o => open);
+
+  U_ext_rmon_1 : gc_extend_pulse
+    generic map (
+      g_width => 3)
+    port map (
+      clk_i      => phy_rx_clk_i,
+      rst_n_i    => rst_n_rx,
+      pulse_i    => rmon_invalid_code_p_int,
+      extended_o => rmon_rx_inv_code);
+
+  U_ext_rmon_2 : gc_extend_pulse
+    generic map (
+      g_width => 3)
+    port map (
+      clk_i      => phy_rx_clk_i,
+      rst_n_i    => rst_n_rx,
+      pulse_i    => rmon_rx_overrun_p_int,
+      extended_o => rmon_rx_overrun);
+
+-- drive the "RX PCS Sync Lost" event counter
+  rmon_rx_sync_lost <= rx_sync_lost_p and (not mdio_mcr_pdown_i);
+
+end behavioral;
+
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_status_reg_insert.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_status_reg_insert.vhd
new file mode 100644
index 000000000..974c2659b
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_status_reg_insert.vhd
@@ -0,0 +1,153 @@
+-------------------------------------------------------------------------------
+-- Title      : RX Status Register Inserter
+-- Project    : White Rabbit 
+-------------------------------------------------------------------------------
+-- File       : ep_rx_status_reg_insert.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Platform   : FPGA-generic
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2011 - 2017 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.endpoint_private_pkg.all;
+use work.endpoint_pkg.all;
+use work.wr_fabric_pkg.all;
+
+entity ep_rx_status_reg_insert is
+  
+  port (
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    snk_fab_i  : in  t_ep_internal_fabric;
+    snk_dreq_o : out std_logic;
+
+    src_fab_o  : out t_ep_internal_fabric;
+    src_dreq_i : in  std_logic;
+
+    mbuf_valid_i    : in  std_logic;
+    mbuf_ack_o      : out std_logic;
+    mbuf_drop_i     : in  std_logic;
+    mbuf_pclass_i   : in  std_logic_vector(7 downto 0);
+    mbuf_is_hp_i    : in  std_logic;
+    mbuf_is_pause_i : in  std_logic;
+
+    rmon_pfilter_drop_o : out std_logic
+    );
+
+end ep_rx_status_reg_insert;
+
+architecture rtl of ep_rx_status_reg_insert is
+
+  type t_state is (WAIT_FRAME, WAIT_MBUF, GEN_STATUS);
+
+  signal dreq_mask    : std_logic;
+  signal embed_status : std_logic;
+  signal sreg         : t_wrf_status_reg;
+  signal state        : t_state;
+  signal src_fab_out  : t_ep_internal_fabric;
+
+  signal sof_mask : std_logic;
+  
+begin  -- rtl
+  
+  embed_status     <= '1'                         when (state = GEN_STATUS) else '0';
+  src_fab_out.data <= f_marshall_wrf_status(sreg) when (embed_status = '1') else snk_fab_i.data;
+  src_fab_out.addr <= c_WRF_STATUS                when (embed_status = '1') else snk_fab_i.addr;
+
+  src_fab_out.eof     <= snk_fab_i.eof;
+  src_fab_out.error   <= snk_fab_i.error;
+  src_fab_out.bytesel <= snk_fab_i.bytesel;
+  src_fab_out.dvalid  <= snk_fab_i.dvalid or (embed_status and src_dreq_i);
+
+  src_fab_out.has_rx_timestamp   <= snk_fab_i.has_rx_timestamp;
+  src_fab_out.rx_timestamp_valid <= snk_fab_i.rx_timestamp_valid;
+
+  src_fab_o <= src_fab_out;
+
+  src_fab_out.sof <= '1' when (mbuf_valid_i = '1' and state = WAIT_MBUF and mbuf_drop_i = '0' and mbuf_is_pause_i = '0') else '0';
+  mbuf_ack_o      <= '1' when (mbuf_valid_i = '1' and state = WAIT_MBUF)                                                 else '0';
+
+  snk_dreq_o <= src_dreq_i and dreq_mask and not snk_fab_i.sof;
+--   snk_dreq_o <= src_dreq_i and not snk_fab_i.sof;
+
+  p_gen_status : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        rmon_pfilter_drop_o <= '0';
+        state     <= WAIT_FRAME;
+        dreq_mask <= '1';
+        sreg.match_class <= (others =>'0');
+        sreg.is_hp       <= '0';
+        sreg.has_crc     <= '0';
+        sreg.has_smac    <= '0';
+        sreg.error       <= '0';        
+      else
+        case state is
+          when WAIT_FRAME =>
+            rmon_pfilter_drop_o <= '0';
+            if(snk_fab_i.sof = '1') then
+              state     <= WAIT_MBUF;
+              dreq_mask <= '0';
+            end if;
+            
+          when WAIT_MBUF =>
+            if(mbuf_valid_i = '1') then
+                rmon_pfilter_drop_o <= mbuf_drop_i;
+
+                if(mbuf_drop_i = '0' and mbuf_is_pause_i = '0') then
+                  state <= GEN_STATUS;
+                  dreq_mask <= '1';
+                else
+                  state <= WAIT_FRAME;
+                  dreq_mask <= '1';
+                end if;
+
+                sreg.match_class <= mbuf_pclass_i;
+                sreg.is_hp       <= mbuf_is_hp_i;
+                sreg.has_crc     <= '0';
+                sreg.has_smac    <= '1';
+                sreg.error       <= '0';
+            else
+              rmon_pfilter_drop_o <= '0';
+              --rmon_o.rx_path_timing_failure <= '0';
+            end if;
+            
+          when GEN_STATUS =>
+            rmon_pfilter_drop_o <= '0';
+            if(src_dreq_i = '1') then
+              state     <= WAIT_FRAME;
+              dreq_mask <= '1';
+            end if;
+        end case;
+      end if;
+    end if;
+  end process;
+
+
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_vlan_unit.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_vlan_unit.vhd
new file mode 100644
index 000000000..ed027d6dc
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_vlan_unit.vhd
@@ -0,0 +1,449 @@
+-------------------------------------------------------------------------------
+-- Title      : RX VLAN unit
+-- Project    : White Rabbit 
+-------------------------------------------------------------------------------
+-- File       : ep_rx_vlan_unit.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Platform   : FPGA-generic
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2011-2015 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.endpoint_private_pkg.all;
+use work.endpoint_pkg.all;
+use work.ep_wbgen2_pkg.all;
+use work.wr_fabric_pkg.all;
+
+
+-- 3rd deframing pipeline stage - VLAN Unit
+
+entity ep_rx_vlan_unit is
+  port(clk_sys_i : in std_logic;
+       rst_n_i   : in std_logic;
+
+       snk_fab_i  : in  t_ep_internal_fabric;
+       snk_dreq_o : out std_logic;
+
+       src_fab_o  : out t_ep_internal_fabric;
+       src_dreq_i : in  std_logic;
+
+       tclass_o   : out std_logic_vector(2 downto 0);
+       vid_o      : out std_logic_vector(11 downto 0);
+       tag_done_o : out std_logic;
+       is_tagged_o: out std_logic;
+
+       regs_i : in    t_ep_out_registers;
+       regs_o : out   t_ep_in_registers
+       );
+
+end ep_rx_vlan_unit;
+
+architecture behavioral of ep_rx_vlan_unit is
+
+  
+  type t_tag_type is (NONE, PRIO, VLAN, NULL_VLAN);
+  type t_state is (WAIT_FRAME, DATA, FLUSH_STALL, DISCARD_FRAME, INSERT_TAG, END_FRAME);
+
+  signal dreq_mask  : std_logic;
+  signal hdr_offset : std_logic_vector(11 downto 0);
+
+  signal comb_tag_type : t_tag_type;
+
+  signal tag_type : t_tag_type;
+  signal state    : t_state;
+
+  signal at_ethertype     : std_logic;
+  signal at_vid           : std_logic;
+  signal at_tpid          : std_logic;
+  signal is_tagged        : std_logic;
+  signal stored_ethertype : std_logic_vector(15 downto 0);
+  signal stored_fab       : t_ep_internal_fabric;
+
+  signal prio_int     : std_logic_vector(2 downto 0);
+  signal force_dvalid : std_logic;
+
+  signal r_tcar_pcp_map : std_logic_vector(23 downto 0);
+  signal is_tag_inserted: std_logic;
+
+  procedure f_vlan_decision
+    (tag_type       :     t_tag_type;
+     qmode          : in  std_logic_vector(1 downto 0);
+     admit          : out std_logic;
+     use_pvid       : out std_logic;
+     use_fixed_prio : out std_logic) is
+  begin
+
+    use_pvid       := 'X';
+    use_fixed_prio := 'X';
+    admit          := '0';
+
+    -- From Jose's table. Thanks a lot!
+    case (qmode) is
+      when c_QMODE_PORT_ACCESS =>
+        case tag_type is
+          when NONE =>
+            admit := '1'; use_pvid := '1'; use_fixed_prio := '1';
+          when PRIO =>
+            admit := '1'; use_pvid := '1'; use_fixed_prio := '0';
+          when VLAN =>
+            admit := '0'; use_pvid := '0';
+          when NULL_VLAN =>
+            admit := '0';
+        end case;
+
+      when c_QMODE_PORT_TRUNK =>
+        case tag_type is
+          when NONE =>
+            admit := '0';
+          when PRIO =>
+            admit := '0';
+          when VLAN =>
+            admit          := '1';
+            use_pvid       := '0';
+            use_fixed_prio := '0';
+          when NULL_VLAN =>
+            admit := '0';
+        end case;
+
+      when c_QMODE_PORT_UNQUALIFIED =>
+        
+        case tag_type is
+          when NONE =>
+            admit    := '1';
+            use_pvid := '1'; use_fixed_prio := '1';
+          when PRIO =>
+            admit    := '1';
+            use_pvid := '1'; use_fixed_prio := '0';
+          when VLAN =>
+            admit    := '1';
+            use_pvid := '0'; use_fixed_prio := '0';
+          when NULL_VLAN =>
+            admit := '0';
+        end case;
+
+      when c_QMODE_PORT_VLAN_DISABLED =>
+        case tag_type is
+          when NONE =>
+            admit          := '1';
+            use_pvid       := '0';
+            use_fixed_prio := '1';
+          when PRIO =>
+            admit          := '1';
+            use_pvid       := '0';
+            use_fixed_prio := '0';
+          when VLAN =>
+            admit          := '1';
+            use_pvid       := '0';
+            use_fixed_prio := '0';
+          when NULL_VLAN =>
+            admit          := '1';
+            use_pvid       := '0';
+            use_fixed_prio := '0';
+        end case;
+      when others => null;
+    end case;
+  end procedure;
+
+  
+begin  -- behavioral
+
+  at_ethertype <= hdr_offset(6) and snk_fab_i.dvalid;
+  at_tpid      <= hdr_offset(6) and snk_fab_i.dvalid and is_tagged;--unused 
+  at_vid       <= hdr_offset(7) and snk_fab_i.dvalid and is_tagged;
+
+  snk_dreq_o <= src_dreq_i and dreq_mask;-- and not at_ethertype;
+
+  p_decode_tag_type : process(snk_fab_i, is_tagged)
+  begin
+    if(is_tagged = '0') then
+      comb_tag_type <= NONE;
+    else
+      case snk_fab_i.data(11 downto 0) is
+        when x"000" => comb_tag_type <= PRIO;
+        when x"fff" => comb_tag_type <= NULL_VLAN;
+        when others => comb_tag_type <= VLAN;
+      end case;
+    end if;
+  end process;
+
+  p_tag_untag : process(clk_sys_i)
+    variable admit, use_pvid, use_fixed_prio : std_logic;
+    variable v_dreq_mask                     : std_logic;
+    variable v_stored_fab                    : t_ep_internal_fabric;
+    variable v_src_fab                       : t_ep_internal_fabric;
+    variable v_next_state                    : t_state;
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' or regs_i.ecr_rx_en_o = '0' then
+        hdr_offset(hdr_offset'left downto 1) <= (others => '0');
+        hdr_offset(0)    <= '1';
+        state            <= WAIT_FRAME;
+        dreq_mask        <= '0';
+        vid_o            <= (others =>'0');
+        is_tag_inserted  <= '0';
+        is_tagged        <= '0';
+        src_fab_o.eof    <= '0';
+        src_fab_o.error  <= '0';
+        src_fab_o.dvalid <= '0';
+        
+      else
+        if(snk_fab_i.error = '1') then
+          state <= DISCARD_FRAME;
+        else
+
+          case state is
+            when WAIT_FRAME =>
+              dreq_mask       <= '1';
+              src_fab_o.eof   <= '0';
+              src_fab_o.error <= '0';
+              is_tagged       <= '0';
+              is_tag_inserted <= '0';
+              prio_int        <= regs_i.vcr0_prio_val_o;
+              vid_o           <= (others =>'0');
+
+              if(snk_fab_i.sof = '1') then
+                hdr_offset(hdr_offset'left downto 1) <= (others => '0');
+                hdr_offset(0)                        <= '1';
+                state                                <= DATA;
+              end if;
+
+            when DATA =>
+
+              v_dreq_mask     := '1';
+              v_src_fab.eof   := '0';
+              v_src_fab.error := '0';
+              v_next_state    := DATA;
+
+              if (snk_fab_i.dvalid = '1' and src_dreq_i = '0') then
+                v_stored_fab.bytesel := snk_fab_i.bytesel;
+                v_stored_fab.data    := snk_fab_i.data;
+                v_stored_fab.addr    := snk_fab_i.addr;
+                v_stored_fab.dvalid  := '1';
+                v_next_state         := FLUSH_STALL;
+              else
+                v_src_fab.addr    := snk_fab_i.addr;
+                v_src_fab.data    := snk_fab_i.data;
+                v_src_fab.dvalid  := src_dreq_i and snk_fab_i.dvalid;
+                v_src_fab.bytesel := snk_fab_i.bytesel;
+              end if;
+
+              if(at_ethertype = '1') then
+                stored_ethertype <= snk_fab_i.data;
+
+                if(snk_fab_i.data = x"8100") then  -- got a 802.1q tagged frame
+                  is_tagged <= '1';
+                else
+                  if (regs_i.vcr0_qmode_o = c_QMODE_PORT_ACCESS) then
+                    prio_int <= regs_i.vcr0_prio_val_o;
+                    is_tag_inserted  <= '1';
+                    v_src_fab.dvalid := '0';
+                    v_next_state     := INSERT_TAG;
+                    v_dreq_mask      := '0';
+                  elsif (regs_i.vcr0_qmode_o = c_QMODE_PORT_TRUNK) then
+                    v_src_fab.dvalid := '0';
+                    v_next_state     := DISCARD_FRAME;
+                  end if;
+                  is_tagged <= '0';
+                end if;
+              end if;
+
+              if(snk_fab_i.eof = '1') then
+                if(src_dreq_i = '1') then
+                  v_src_fab.eof := '1';
+                  v_next_state  := WAIT_FRAME;
+                else
+                  v_next_state := END_FRAME;
+                end if;
+              end if;
+
+              if(at_vid = '1') then
+
+                -- decide what to do with the frame, basing on the port mode
+                -- (ACCESS, TRUNK, UNQUALIFIED), and whether the frame is tagged
+                -- or not.
+                f_vlan_decision(comb_tag_type, regs_i.vcr0_qmode_o, admit, use_pvid, use_fixed_prio);
+
+                -- assign the VID
+                if(admit = '0') then    -- oops...
+                  v_next_state := DISCARD_FRAME;
+                end if;
+
+                if(use_pvid = '1')then
+                  v_stored_fab.data(11 downto 0) := regs_i.vcr0_pvid_o;
+                  v_src_fab.data(11 downto 0)    := regs_i.vcr0_pvid_o;
+                end if;
+                vid_o   <= v_src_fab.data(11 downto 0);
+                -- assign the priority 
+                if(regs_i.vcr0_fix_prio_o = '1' or use_fixed_prio = '1') then
+                  -- Forced priority (or a non-priority tagged frame)? Take the priority
+                  -- value from VCR0 register
+                  prio_int <= regs_i.vcr0_prio_val_o;
+                else
+                  -- Got a priority tag - use the value from the VLAN tag
+                  prio_int <= snk_fab_i.data(15 downto 13);
+                end if;
+              end if;
+
+              if(snk_fab_i.dvalid = '1') then
+                hdr_offset <= hdr_offset(hdr_offset'left-1 downto 0) & '0';
+              end if;
+
+              if(v_next_state = INSERT_TAG) then
+                src_fab_o.eof     <= '0';              
+                src_fab_o.dvalid  <= '1';
+                src_fab_o.error   <= '0';
+                src_fab_o.addr    <= c_WRF_DATA;
+                src_fab_o.data    <= x"8100";
+                src_fab_o.bytesel <= '0';
+              else
+                src_fab_o.eof     <= v_src_fab.eof;              
+                src_fab_o.dvalid  <= v_src_fab.dvalid;
+                src_fab_o.error   <= v_src_fab.error;
+                src_fab_o.addr    <= v_src_fab.addr;
+                src_fab_o.data    <= v_src_fab.data;
+                src_fab_o.bytesel <= v_src_fab.bytesel;
+              end if;
+
+              dreq_mask  <= v_dreq_mask;
+              stored_fab <= v_stored_fab;
+              state      <= v_next_state;
+              
+            when END_FRAME =>
+              if(src_dreq_i = '1')then
+                src_fab_o.eof    <= '1';
+                src_fab_o.dvalid <= '0';
+                state            <= WAIT_FRAME;
+              end if;
+              
+            when DISCARD_FRAME =>
+              if(src_dreq_i = '1') then
+                src_fab_o.error  <= '1';
+                src_fab_o.dvalid <= '0';
+                state            <= WAIT_FRAME;
+              end if;
+
+            when FLUSH_STALL =>
+              if(src_dreq_i = '1')then
+                src_fab_o.addr    <= stored_fab.addr;
+                src_fab_o.data    <= stored_fab.data;
+                src_fab_o.dvalid  <= stored_fab.dvalid;
+                src_fab_o.bytesel <= stored_fab.bytesel;
+                state             <= DATA;
+              else
+                src_fab_o.DATA   <= (others => 'X');
+                src_fab_o.dvalid <= '0';
+              end if;
+
+            when INSERT_TAG =>
+              src_fab_o.dvalid <= '0';
+
+              if(src_dreq_i = '1') then
+-- we are at 7th word from the beginning of the frame, but the sink reception
+-- is disabled, so we can insert the original ethertype as the TPID
+
+                if(hdr_offset(7) = '1') then
+                  src_fab_o.addr   <= c_WRF_DATA;
+                  src_fab_o.data   <= regs_i.vcr0_prio_val_o & '0' & regs_i.vcr0_pvid_o;
+                  src_fab_o.dvalid <= '1';
+                  vid_o            <= regs_i.vcr0_pvid_o; -- use the inserted PVID
+                  dreq_mask        <= '0';
+                  stored_fab.bytesel <= snk_fab_i.bytesel;
+                  stored_fab.data    <= snk_fab_i.data;
+                  stored_fab.addr    <= snk_fab_i.addr;
+                  stored_fab.dvalid  <= snk_fab_i.dvalid;
+
+                end if;
+
+                if(hdr_offset(8) = '1') then
+                  src_fab_o.addr   <= c_WRF_DATA;
+                  src_fab_o.data   <= stored_ethertype;
+                  src_fab_o.dvalid <= '1';
+                  dreq_mask        <= '1';
+                end if;
+
+                if(hdr_offset(9) = '1') then
+                  src_fab_o.addr    <= stored_fab.addr;
+                  src_fab_o.data    <= stored_fab.data;
+                  src_fab_o.dvalid  <= stored_fab.dvalid;
+                  src_fab_o.bytesel <= stored_fab.bytesel;
+                  dreq_mask        <= '1';
+                  state            <= DATA;                  
+                end if;
+
+                hdr_offset <= hdr_offset(hdr_offset'left-1 downto 0) & '0';
+              else
+                src_fab_o.dvalid <= '0';
+              end if;
+          end case;
+        end if;
+      end if;
+    end if;
+  end process;
+
+
+-- Process: p_map_prio_to_tc
+-- Maps the PCP value from the 802.1q header into a traffic class for further
+-- processing. The mapping table is stored in TCAR register.
+
+  regs_o.tcar_pcp_map_i <= r_tcar_pcp_map;
+
+  p_map_prio_to_tc : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+
+      if(regs_i.tcar_pcp_map_load_o = '1') then
+        r_tcar_pcp_map <= regs_i.tcar_pcp_map_o;
+      end if;
+
+      if(rst_n_i = '0' or regs_i.ecr_rx_en_o = '0' or snk_fab_i.sof = '1')then
+        tag_done_o <= '0';
+        tclass_o   <= "000";
+      elsif(hdr_offset(9) = '1') then
+        -- we're already after the headers, so prio_int is
+        -- certainly valid
+        tag_done_o <= '1';
+        case prio_int is
+          when "000"  => tclass_o <= r_tcar_pcp_map(2 downto 0);
+          when "001"  => tclass_o <= r_tcar_pcp_map(5 downto 3);
+          when "010"  => tclass_o <= r_tcar_pcp_map(8 downto 6);
+          when "011"  => tclass_o <= r_tcar_pcp_map(11 downto 9);
+          when "100"  => tclass_o <= r_tcar_pcp_map(14 downto 12);
+          when "101"  => tclass_o <= r_tcar_pcp_map(17 downto 15);
+          when "110"  => tclass_o <= r_tcar_pcp_map(20 downto 18);
+          when "111"  => tclass_o <= r_tcar_pcp_map(23 downto 21);
+          when others => tclass_o <= "000";--"XXX";  -- packet probably contains porn
+        end case;
+      end if;
+    end if;
+  end process;
+
+  src_fab_o.sof <= regs_i.ecr_rx_en_o and snk_fab_i.sof;
+  is_tagged_o   <= is_tagged or is_tag_inserted;
+  
+end behavioral;
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_wb_master.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_wb_master.vhd
new file mode 100644
index 000000000..b496ee3b7
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_wb_master.vhd
@@ -0,0 +1,226 @@
+-------------------------------------------------------------------------------
+-- Title      : White Rabbit MAC/Endpoint 
+-- Project    : White Rabbit Switch 
+-------------------------------------------------------------------------------
+-- File       : ep_rx_wb_master
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2009-06-22
+-- Last update: 2017-02-02
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: RX Wishbone Master. Converts the internal fabric (DREQ-VALID
+-- throttling) to Pipelined Wishbone (b4)
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2011-2017 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author  Description
+-- 2011-08-22  0.1      twlostow  Created
+------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.endpoint_private_pkg.all;
+use work.endpoint_pkg.all;
+use work.wr_fabric_pkg.all;
+
+entity ep_rx_wb_master is
+  generic(
+    g_ignore_ack   : boolean := true;
+    g_cyc_on_stall : boolean := false);
+  port (
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+-- physical coding sublayer (PCS) interface
+    snk_fab_i  : in  t_ep_internal_fabric;
+    snk_dreq_o : out std_logic;
+
+-- Wishbone I/O (master)
+    src_wb_i : in  t_wrf_source_in;
+    src_wb_o : out t_wrf_source_out
+    );
+
+end ep_rx_wb_master;
+
+architecture behavioral of ep_rx_wb_master is
+
+  type t_state is (IDLE, DATA, FLUSH_STALL, FINISH_CYCLE, THROW_ERROR);
+
+  signal state       : t_state;
+  signal ack_count   : unsigned(3 downto 0);
+  signal src_out_int : t_wrf_source_out;
+
+  signal tmp_sel : std_logic;
+  signal tmp_dat : std_logic_vector(15 downto 0);
+  signal tmp_adr : std_logic_vector(1 downto 0);
+  signal enter_idle : std_logic;
+  signal sof_reg  : std_logic;
+
+begin  -- behavioral
+  
+  gen_cyc_on_stall: if g_cyc_on_stall = true generate
+    snk_dreq_o <= '1' when ((src_wb_i.stall = '0' and state /= FINISH_CYCLE and
+                  state /= THROW_ERROR and snk_fab_i.eof = '0' and snk_fab_i.error = '0' and snk_fab_i.sof = '0' and enter_idle = '0') or state = IDLE) else '0';
+  end generate;
+
+  gen_nocyc_on_stall: if g_cyc_on_stall = false generate
+--     snk_dreq_o <= '1' when (src_wb_i.stall = '0' and state /= FINISH_CYCLE and snk_fab_i.eof = '0' and snk_fab_i.error = '0' and snk_fab_i.sof = '0' and enter_idle = '0') else '0';
+--     snk_dreq_o <= '1' when (src_wb_i.stall = '0' and state /= FINISH_CYCLE and snk_fab_i.eof = '0' and snk_fab_i.error = '0' and enter_idle = '0') else '0';
+    snk_dreq_o <= '1' when (src_wb_i.stall = '0' and state /= FINISH_CYCLE and
+                  state /= THROW_ERROR and snk_fab_i.eof = '0' and snk_fab_i.error = '0') else '0';
+  end generate;
+
+  p_count_acks : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' or src_out_int.cyc = '0' then
+        ack_count <= (others => '0');
+      else
+        if(src_out_int.stb = '1' and src_wb_i.stall = '0' and src_wb_i.ack = '0') then
+          ack_count <= ack_count + 1;
+        elsif(src_wb_i.ack = '1' and not(src_out_int.stb = '1' and src_wb_i.stall = '0')) then
+          ack_count <= ack_count - 1;
+        end if;
+        
+      end if;
+    end if;
+  end process;
+
+  process(clk_sys_i)
+    variable stat : t_wrf_status_reg := c_wrf_status_init_value;
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        state           <= IDLE;
+        src_out_int.stb <= '0';
+        src_out_int.we  <= '1';
+        src_out_int.adr <= c_WRF_DATA;
+        src_out_int.cyc <= '0';
+        enter_idle <= '1';
+        sof_reg    <= '0';
+      else
+        case state is
+          when IDLE =>
+            enter_idle <= '0';
+            src_out_int.adr <= snk_fab_i.addr;
+            src_out_int.dat <= snk_fab_i.data;
+
+            if((snk_fab_i.sof='1' or sof_reg='1') and src_wb_i.err = '0') then
+              src_out_int.cyc <= '1';
+              state           <= DATA;
+            end if;
+            
+          when DATA =>
+            sof_reg <= '0';
+            if(src_wb_i.stall = '0') then
+              src_out_int.adr <= snk_fab_i.addr;
+              src_out_int.dat    <= snk_fab_i.data;
+              src_out_int.stb    <= snk_fab_i.dvalid;
+              src_out_int.sel(1) <= '1';
+              src_out_int.sel(0) <= not snk_fab_i.bytesel;
+            end if;
+
+
+            if(src_wb_i.err = '1') then
+              state <= IDLE;
+              enter_idle <= '1';
+              src_out_int.cyc <= '0';
+              src_out_int.stb <= '0';
+            elsif(snk_fab_i.error = '1') then
+              state <= THROW_ERROR;
+            elsif(src_wb_i.stall = '1' and snk_fab_i.dvalid = '1') then
+              state <= FLUSH_STALL;
+            end if;
+
+            if(snk_fab_i.eof = '1')then
+              state <= FINISH_CYCLE;
+            end if;
+
+            
+            
+            tmp_adr <= snk_fab_i.addr;
+            tmp_dat <= snk_fab_i.data;
+            tmp_sel <= snk_fab_i.bytesel;
+
+          when FLUSH_STALL =>
+            if(src_wb_i.err = '1') then
+              state <= IDLE;
+              enter_idle <= '1';
+              src_out_int.cyc <= '0';
+              src_out_int.stb <= '0';
+            elsif(src_wb_i.stall = '0') then
+              src_out_int.dat    <= tmp_dat;
+              src_out_int.adr    <= tmp_adr;
+              src_out_int.stb    <= '1';
+              src_out_int.sel(1) <= '1';
+              src_out_int.sel(0) <= not tmp_sel;
+              state              <= DATA;
+            end if;
+
+          when THROW_ERROR =>
+            if(snk_fab_i.sof='1') then
+              sof_reg <= '1';
+            end if;
+            if(src_wb_i.err = '1') then
+              enter_idle <= '1';
+              state <= IDLE;
+              src_out_int.cyc <= '0';
+              src_out_int.stb <= '0';
+            elsif(src_wb_i.stall = '0') then
+              stat.error      := '1';
+              src_out_int.adr <= c_WRF_STATUS;
+              src_out_int.dat <= f_marshall_wrf_status(stat);
+              src_out_int.stb <= '1';
+              state           <= FINISH_CYCLE;
+            end if;
+              
+            
+          when FINISH_CYCLE =>
+            if(snk_fab_i.sof='1') then
+              sof_reg <= '1';
+            end if;
+            if(src_wb_i.stall = '0') then
+              src_out_int.stb <= '0';
+            end if;
+
+            if(((ack_count = 0) or g_ignore_ack) and src_out_int.stb = '0') then
+              src_out_int.cyc <= '0';
+              enter_idle <= '1';
+              state           <= IDLE;
+            end if;
+          when others => null;
+        end case;
+      end if;
+    end if;
+  end process;
+
+
+  src_wb_o <= src_out_int;
+  
+end behavioral;
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_sync_detect.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_sync_detect.vhd
new file mode 100644
index 000000000..cf0be4e9a
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_sync_detect.vhd
@@ -0,0 +1,280 @@
+-------------------------------------------------------------------------------
+-- Title      : 802.3x 1000base-X compatible synchronization detect unit
+-- Project    : WhiteRabbit Switch
+-------------------------------------------------------------------------------
+-- File       : ep_sync_detect.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-Co-HT
+-- Created    : 2010-05-28
+-- Last update: 2012-04-27
+-- Platform   : FPGA-generics
+-- Standard   : VHDL
+-------------------------------------------------------------------------------
+-- Description: Module implements a link synchronization detect state machine
+-- compatible with 802.3x spec.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2010 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2010-05-28  1.0      twlostow        Created
+-------------------------------------------------------------------------------
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.endpoint_private_pkg.all;
+
+entity ep_sync_detect is
+  
+  port (
+-- reset, synchronous to rbclk_i, active LOW
+    rst_n_i  : in  std_logic;
+-- recovered byte clock
+    rbclk_i  : in  std_logic;
+-- enable, active HI
+    en_i     : in  std_logic;
+-- decoded data input, active HI
+    data_i   : in  std_logic_vector(7 downto 0);
+-- decoded K signal, active HI
+    k_i      : in  std_logic;
+-- 8b10b coding error indication, active HI
+    err_i    : in  std_logic;
+-- sync detect output, active HI
+    synced_o : out std_logic;
+-- odd/even field indicator (HI = even field)
+    even_o   : out std_logic;
+
+    cal_i: in std_logic
+    );
+
+end ep_sync_detect;
+
+architecture behavioral of ep_sync_detect is
+
+  type t_sync_fsm_state is (LOSS_OF_SYNC, COMMA_DETECT_1, ACQUIRE_SYNC_1, COMMA_DETECT_2, ACQUIRE_SYNC_2, COMMA_DETECT_3, SYNC_ACQUIRED_1, SYNC_ACQUIRED_2, SYNC_ACQUIRED_3, SYNC_ACQUIRED_4, SYNC_ACQUIRED_2A, SYNC_ACQUIRED_3A, SYNC_ACQUIRED_4A);
+
+  signal state      : t_sync_fsm_state;
+  signal cggood     : std_logic;
+  signal cgbad      : std_logic;
+  signal comma      : std_logic;
+  signal rx_even    : std_logic;
+  signal is_d       : std_logic;
+  signal is_k       : std_logic;
+  signal is_k28_5   : std_logic;
+  signal good_cgs   : unsigned(2 downto 0);
+  
+  
+begin  -- behavioral
+
+
+  is_k28_5 <= '1' when data_i = c_k28_5 else '0';
+  is_d     <= (not k_i);
+
+  comma <= is_k28_5;
+
+--  cgbad <= err_i or (k_i and comma and rx_even);
+
+  cgbad  <= err_i or (k_i and comma and (not rx_even));
+  cggood <= not (err_i or (k_i and comma and (not rx_even)));
+
+  even_o <= rx_even;
+
+-- fixme!
+
+  -- 1000base-x sync detect state machine
+  -- as defined in 802.3-2008, figure 36-9.
+
+
+  sync_fsm : process (rbclk_i, rst_n_i)
+  begin  -- process sync_fsm
+    if rising_edge(rbclk_i) then
+      if(rst_n_i = '0') then
+        state      <= LOSS_OF_SYNC;
+        synced_o   <= '0';
+        rx_even    <= '0';
+        good_cgs   <= (others => '0');
+      else
+        if(en_i = '0') then
+          state      <= LOSS_OF_SYNC;
+          synced_o   <= '0';
+          rx_even    <= '0';
+          good_cgs   <= (others => '0');
+        else
+
+          -- prevents from 
+          if(cal_i = '0') then  
+            
+            case state is
+              when LOSS_OF_SYNC =>
+                synced_o <= '0';
+                if(comma = '1') then
+                  rx_even <= '0';
+                  state <= COMMA_DETECT_1;
+                else
+                  rx_even  <= not rx_even;
+                end if;
+
+              when COMMA_DETECT_1 =>
+                rx_even <= not rx_even;
+                if(is_d = '1') then     -- got data
+                  state <= ACQUIRE_SYNC_1;
+                else
+                  state <= LOSS_OF_SYNC;
+                end if;
+
+              when ACQUIRE_SYNC_1 =>
+                if(cgbad = '1') then
+                  state <= LOSS_OF_SYNC;
+                  rx_even <= not rx_even;
+                elsif (rx_even = '1' and comma = '1') then
+                  rx_even <= '0';         -- was 1
+                  state <= COMMA_DETECT_2;
+                else
+                  rx_even <= not rx_even;
+                end if;
+
+              when COMMA_DETECT_2 =>
+                rx_even <= not rx_even;
+                if(is_d = '1') then
+                  state <= ACQUIRE_SYNC_2;
+                else
+                  state <= LOSS_OF_SYNC;
+                end if;
+
+              when ACQUIRE_SYNC_2 =>
+                if(cgbad = '1') then
+                  rx_even <= not rx_even;
+                  state <= LOSS_OF_SYNC;
+                elsif (rx_even = '1' and comma = '1') then
+                  state <= COMMA_DETECT_3;
+                  rx_even <= '0';
+                else
+                  rx_even <= not rx_even;
+                end if;
+
+              when COMMA_DETECT_3 =>
+                rx_even <= not rx_even;
+                if(is_d = '1') then
+                  state <= SYNC_ACQUIRED_1;
+                else
+                  state <= LOSS_OF_SYNC;
+                end if;
+
+              when SYNC_ACQUIRED_1 =>
+                synced_o <= '1';
+                rx_even  <= not rx_even;
+
+                if(cggood = '1') then
+                  state <= SYNC_ACQUIRED_1;
+                end if;
+
+                if (cgbad = '1') then
+                  state <= SYNC_ACQUIRED_2;
+                end if;
+
+              when SYNC_ACQUIRED_2 =>
+                rx_even  <= not rx_even;
+                good_cgs <= (others => '0');
+
+                if(cggood = '1') then
+                  state <= SYNC_ACQUIRED_2A;
+                end if;
+
+                if(cgbad = '1') then
+                  state <= SYNC_ACQUIRED_3;
+                end if;
+
+              when SYNC_ACQUIRED_2A =>
+                rx_even  <= not rx_even;
+                good_cgs <= good_cgs + 1;
+
+                if(good_cgs = "011" and cggood = '1') then
+                  state <= SYNC_ACQUIRED_1;
+                end if;
+
+                if(cgbad = '1') then
+                  state <= SYNC_ACQUIRED_3;
+                end if;
+
+              when SYNC_ACQUIRED_3 =>
+                rx_even  <= not rx_even;
+                good_cgs <= (others => '0');
+
+                if(cggood = '1') then
+                  state <= SYNC_ACQUIRED_3A;
+                end if;
+
+                if(cgbad = '1') then
+                  state <= SYNC_ACQUIRED_4;
+                end if;
+                
+              when SYNC_ACQUIRED_3A =>
+                rx_even  <= not rx_even;
+                good_cgs <= good_cgs + 1;
+
+                if(good_cgs = "011" and cggood = '1') then
+                  state <= SYNC_ACQUIRED_2;
+                end if;
+
+                if(cgbad = '1') then
+                  state <= SYNC_ACQUIRED_4;
+                end if;
+
+              when SYNC_ACQUIRED_4 =>
+                rx_even  <= not rx_even;
+                good_cgs <= (others => '0');
+
+                if(cggood = '1') then
+                  state <= SYNC_ACQUIRED_4A;
+                end if;
+
+                if(cgbad = '1') then
+                  state <= LOSS_OF_SYNC;
+                end if;
+
+              when SYNC_ACQUIRED_4A =>
+                rx_even  <= not rx_even;
+                good_cgs <= good_cgs + 1;
+
+                if(good_cgs = "011" and cggood = '1') then
+                  state <= SYNC_ACQUIRED_3;
+                end if;
+
+                if (cgbad = '1') then
+                  state <= LOSS_OF_SYNC;
+                end if;
+              when others => null;
+            end case;
+          end if;
+        end if;
+      end if;
+    end if;
+  end process;
+  
+
+  
+
+end behavioral;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_sync_detect_16bit.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_sync_detect_16bit.vhd
new file mode 100644
index 000000000..c49209499
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_sync_detect_16bit.vhd
@@ -0,0 +1,193 @@
+-------------------------------------------------------------------------------
+-- Title      : 802.3x 1000base-X compatible synchronization detect unit
+-- Project    : WhiteRabbit Switch
+-------------------------------------------------------------------------------
+-- File       : ep_sync_detect.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-Co-HT
+-- Created    : 2010-05-28
+-- Last update: 2012-01-18
+-- Platform   : FPGA-generics
+-- Standard   : VHDL
+-------------------------------------------------------------------------------
+-- Description: Module implements a link synchronization detect state machine
+-- compatible with 802.3x spec.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2010 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2010-05-28  1.0      twlostow        Created
+-------------------------------------------------------------------------------
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.endpoint_private_pkg.all;
+
+entity ep_sync_detect_16bit is
+  
+  port (
+-- reset, synchronous to rbclk_i, active LOW
+    rst_n_i  : in  std_logic;
+-- recovered byte clock
+    rbclk_i  : in  std_logic;
+-- enable, active HI
+    en_i     : in  std_logic;
+-- decoded data input, active HI
+    data_i   : in  std_logic_vector(15 downto 0);
+-- decoded K signal, active HI
+    k_i      : in  std_logic_vector(1 downto 0);
+-- 8b10b coding error indication, active HI
+    err_i    : in  std_logic;
+-- sync detect output, active HI
+    synced_o : out std_logic;
+
+    cal_i : in std_logic
+    );
+
+end ep_sync_detect_16bit;
+
+architecture behavioral of ep_sync_detect_16bit is
+
+  type t_sync_fsm_state is (LOSS_OF_SYNC, CD_ACQ_1, CD_ACQ_2, CD_ACQ_3, SYNC_ACQUIRED_1, SYNC_ACQUIRED_2, SYNC_ACQUIRED_3, SYNC_ACQUIRED_4, SYNC_ACQUIRED_2A, SYNC_ACQUIRED_3A, SYNC_ACQUIRED_4A);
+
+  
+  function f_pick(sel : std_logic;
+                  w1  : t_sync_fsm_state;
+                  w0  : t_sync_fsm_state) return t_sync_fsm_state is
+
+  begin
+    if(sel = '1') then
+      return w1;
+    else
+      return w0;
+    end if;
+  end f_pick;
+
+
+
+  signal state    : t_sync_fsm_state;
+  signal good_cgs : unsigned(2 downto 0);
+
+  signal valid_idle   : std_logic;
+  signal invalid_code : std_logic;
+  signal valid_data   : std_logic;
+  
+begin  -- behavioral
+
+  valid_idle   <= '1' when (k_i = "10" and data_i(15 downto 8) = c_k28_5 and err_i = '0')   else '0';
+  valid_data   <= '1' when (k_i = "00" and err_i = '0')                                     else '0';
+  invalid_code <= '1' when (err_i = '1' or (k_i(0) = '1' and data_i(7 downto 0) = c_k28_5)) else '0';
+
+
+  sync_fsm : process (rbclk_i, rst_n_i)
+  begin  -- process sync_fsm
+    if rising_edge(rbclk_i) then
+      if(rst_n_i = '0') then
+        state    <= LOSS_OF_SYNC;
+        synced_o <= '0';
+        good_cgs <= (others => '0');
+      else
+        if(en_i = '0') then
+          state    <= LOSS_OF_SYNC;
+          synced_o <= '0';
+          good_cgs <= (others => '0');
+        else
+
+          -- prevents from 
+          if(cal_i = '0') then
+            
+            case state is
+              when LOSS_OF_SYNC =>
+                synced_o <= '0';
+                state    <= f_pick(valid_idle, CD_ACQ_1, LOSS_OF_SYNC);
+              when CD_ACQ_1 =>
+                state <= f_pick(valid_idle or valid_data, CD_ACQ_2, LOSS_OF_SYNC);
+              when CD_ACQ_2 =>
+                state <= f_pick(valid_idle, CD_ACQ_3, LOSS_OF_SYNC);
+              when CD_ACQ_3 =>
+                state <= f_pick(valid_idle or valid_data, SYNC_ACQUIRED_1, LOSS_OF_SYNC);
+                
+              when SYNC_ACQUIRED_1 =>
+                synced_o <= '1';
+                state    <= f_pick(invalid_code, SYNC_ACQUIRED_2, SYNC_ACQUIRED_1);
+
+              when SYNC_ACQUIRED_2 =>
+                good_cgs <= (others => '0');
+                state    <= f_pick(invalid_code, SYNC_ACQUIRED_3, SYNC_ACQUIRED_2A);
+
+              when SYNC_ACQUIRED_2A =>
+                good_cgs <= good_cgs + 1;
+
+                if(good_cgs = "011" and invalid_code = '0') then
+                  state <= SYNC_ACQUIRED_1;
+                end if;
+
+                if(invalid_code = '1') then
+                  state <= SYNC_ACQUIRED_3;
+                end if;
+
+              when SYNC_ACQUIRED_3 =>
+                good_cgs <= (others => '0');
+                state    <= f_pick(invalid_code, SYNC_ACQUIRED_4, SYNC_ACQUIRED_3A);
+
+                
+              when SYNC_ACQUIRED_3A =>
+                good_cgs <= good_cgs + 1;
+
+                if(good_cgs = "011" and invalid_code = '0') then
+                  state <= SYNC_ACQUIRED_2;
+                end if;
+
+                if(invalid_code = '1') then
+                  state <= SYNC_ACQUIRED_4;
+                end if;
+
+              when SYNC_ACQUIRED_4 =>
+                good_cgs <= (others => '0');
+                state    <= f_pick(invalid_code, LOSS_OF_SYNC, SYNC_ACQUIRED_4A);
+                
+              when SYNC_ACQUIRED_4A =>
+                good_cgs <= good_cgs + 1;
+
+                if(good_cgs = "011" and invalid_code = '0') then
+                  state <= SYNC_ACQUIRED_3;
+                end if;
+
+                if (invalid_code = '1') then
+                  state <= LOSS_OF_SYNC;
+                end if;
+            end case;
+          end if;
+        end if;
+      end if;
+    end if;
+  end process;
+
+
+
+
+end behavioral;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_timestamping_unit.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_timestamping_unit.vhd
new file mode 100644
index 000000000..0ea2cfd2b
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_timestamping_unit.vhd
@@ -0,0 +1,424 @@
+-------------------------------------------------------------------------------
+-- Title      : Optical 1000base-X endpoint - IEEE1588/WhiteRabbit
+--              timestamping unit
+-- Project    : White Rabbit 
+-------------------------------------------------------------------------------
+-- File       : ep_timestamping_unit.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2009-06-22
+-- Last update: 2017-02-03
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'87
+-------------------------------------------------------------------------------
+-- Description: Timestamping unit. Takes both TX and RX timestamps upon
+-- detection of rising edge on asynchronous timestamp strobe inputs.
+-- There are 2 timestamps taken:
+-- - rising edge timestamp (28 bits by default) - the main timestamp value
+-- - falling edge timestamp (4 least significant bits of the TS counter) which
+--   are used to detect metastabilities and setup/hold violations which may
+--   occur during sampling asynchronous timestamp strobes.
+-- Both timestamps are taken using refclk_i.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2009 - 2012 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2009-06-22  0.1      twlostow        Created
+-------------------------------------------------------------------------------
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.gencores_pkg.all;
+use work.endpoint_private_pkg.all;
+use work.ep_wbgen2_pkg.all;
+
+entity ep_timestamping_unit is
+  generic (
+-- size of rising edge timestamp
+    g_timestamp_bits_r : natural := 28;
+-- size of falling edge timestamp
+    g_timestamp_bits_f : natural := 4;
+    g_ref_clock_rate   : integer := 125000000
+    );
+
+  port (
+-- reference clock (for the timestamping counters)
+    clk_ref_i : in std_logic;
+
+-- reference / 2 (bus-side logic)
+    clk_sys_i : in std_logic;
+
+-- RX clock
+    clk_rx_i : in std_logic;
+
+    -- resets
+    rst_n_rx_i  : in std_logic;
+    rst_n_ref_i : in std_logic;
+    rst_n_sys_i : in std_logic;
+
+-- PPS pulse input (active HI for 1 clk_ref_i cycle) for internal TS counter synchronization
+    pps_csync_p1_i : in std_logic;
+
+    pps_valid_i : in std_logic;
+
+-- asynchronous TX/RX timestamp triggers (from PCS)
+    tx_timestamp_trigger_p_a_i : in std_logic;
+    rx_timestamp_trigger_p_a_i : in std_logic;
+
+-------------------------------------------------------------------------------
+-- RX Timestamp output (clk_rx_i clock domain)
+-------------------------------------------------------------------------------
+
+    -- RX timestamp (to RX deframer)
+    rxts_timestamp_o : out std_logic_vector(31 downto 0);
+
+    -- RX timestamp strobe (back to the PCSr). When HI,
+    -- rxts_timestamp_o and rxts_timestamp_valid_o contain information about
+    -- the RX timestamp and its validity
+    rxts_timestamp_stb_o : out std_logic;
+
+    -- RX timestamp valid (to RX deframer)
+    rxts_timestamp_valid_o : out std_logic;
+
+-------------------------------------------------------------------------------
+-- TX Timestamp output (clk_ref_i clock domain)
+-------------------------------------------------------------------------------    
+
+    -- TX timestamp output (to TXTSU/Framer)
+    txts_timestamp_o : out std_logic_vector(31 downto 0);
+
+    -- TX timestamp strobe (to TXTSU/Framer). When HI,
+    -- txts_timestamp_o and txts_timestamp_valid_o contain information about
+    -- the TX timestamp and its validity
+    txts_timestamp_stb_o : out std_logic;
+
+    -- TX timestamp valid (to TXTSU/Framer)
+    txts_timestamp_valid_o : out std_logic;
+
+    txts_o                 : out std_logic; 		-- 2013-Nov-28 peterj added for debugging/calibration
+    rxts_o                 : out std_logic; 		-- 2013-Nov-28 peterj added for debugging/calibration
+
+-------------------------------------------------------------------------------
+-- Wishbone regs
+-------------------------------------------------------------------------------
+
+    regs_i : in  t_ep_out_registers;
+    regs_o : out t_ep_in_registers
+    );
+
+end ep_timestamping_unit;
+
+
+
+architecture syn of ep_timestamping_unit is
+
+
+  component ep_ts_counter
+    generic (
+      g_num_bits_r : natural;
+      g_num_bits_f : natural;
+      g_init_value : natural;
+      g_max_value  : natural);
+    port (
+      clk_i          : in  std_logic;
+      rst_n_i        : in  std_logic;
+      overflow_o     : out std_logic := '0';
+      value_r_o      : out std_logic_vector(g_num_bits_r-1 downto 0);
+      value_f_o      : out std_logic_vector(g_num_bits_f-1 downto 0);
+      pps_p_i        : in  std_logic;
+      sync_start_p_i : in  std_logic;
+      sync_done_o    : out std_logic);
+  end component;
+
+  signal cntr_rx_r : std_logic_vector(g_timestamp_bits_r-1 downto 0);
+  signal cntr_rx_f : std_logic_vector(g_timestamp_bits_f-1 downto 0);
+  signal cntr_tx_r : std_logic_vector(g_timestamp_bits_r-1 downto 0);
+  signal cntr_tx_f : std_logic_vector(g_timestamp_bits_f-1 downto 0);
+
+  signal cntr_r : std_logic_vector(g_timestamp_bits_r-1 downto 0);
+  signal cntr_f : std_logic_vector(g_timestamp_bits_f-1 downto 0);
+
+  signal take_tx_synced_p, take_rx_synced_p             : std_logic;
+  signal take_tx_synced_p_fedge, take_rx_synced_p_fedge : std_logic;
+
+  signal tx_sync_delay : std_logic_vector(4 downto 0);
+  signal rx_sync_delay : std_logic_vector(4 downto 0);
+  signal rx_ts_done    : std_logic;
+  signal tx_ts_done    : std_logic;
+
+  signal got_tx_oob : std_logic;
+  signal tx_oob_reg : std_logic_vector(15 downto 0);
+
+
+  signal rx_oob_reg : std_logic_vector(47 downto 0);
+  signal fid_valid  : std_logic;
+
+  signal txts_valid : std_logic;
+
+  signal valid_rx, valid_tx : std_logic;
+
+
+  signal cal_count                                   : unsigned(5 downto 0);
+  signal rx_trigger_mask, rx_trigger_a, rx_cal_pulse_a : std_logic;
+
+  signal regs_o_tscr_cs_done       : std_logic;
+  signal regs_o_tscr_rx_cal_result : std_logic;
+  
+begin  -- syn
+
+  -- Instatniation of the timestamping counter
+  U_counter : ep_ts_counter
+    generic map (
+      g_num_bits_r => g_timestamp_bits_r,
+      g_num_bits_f => g_timestamp_bits_f,
+      g_init_value => 0,
+      g_max_value  => g_ref_clock_rate-1)
+    port map (
+
+      clk_i          => clk_ref_i,
+      rst_n_i        => rst_n_ref_i,
+      pps_p_i        => pps_csync_p1_i,
+      overflow_o     => open,
+      value_r_o      => cntr_r,
+      value_f_o      => cntr_f,
+      sync_start_p_i => regs_i.tscr_cs_start_o,
+      sync_done_o    => regs_o_tscr_cs_done
+      );
+
+
+  p_gen_regs_o: process (regs_o_tscr_cs_done, regs_o_tscr_rx_cal_result) is
+  begin
+    -- initial values
+    regs_o <= c_ep_in_registers_init_value;
+
+    -- override initial values
+    regs_o.tscr_cs_done_i       <= regs_o_tscr_cs_done;
+    regs_o.tscr_rx_cal_result_i <= regs_o_tscr_rx_cal_result;
+
+  end process p_gen_regs_o;
+
+  p_rx_timestamper_calibration : process(clk_rx_i)
+  begin
+    if rising_edge(clk_rx_i) then
+      if rst_n_rx_i = '0' then
+        cal_count       <= (others => '0');
+        rx_cal_pulse_a  <= '0';
+        rx_trigger_mask <= '1';
+        
+      elsif(regs_i.tscr_rx_cal_start_o = '1') then
+        cal_count       <= to_unsigned(1, 6);
+        rx_trigger_mask <= '0';
+      elsif(cal_count /= 0) then
+        cal_count <= cal_count + 1;
+
+        if(rx_ts_done = '1') then
+          if(cntr_rx_f /= cntr_rx_r(g_timestamp_bits_f-1 downto 0)) then
+            regs_o_tscr_rx_cal_result <= '1';
+          else
+            regs_o_tscr_rx_cal_result <= '0';
+          end if;
+        end if;
+
+      else
+        
+        rx_trigger_mask <= '1';
+      end if;
+
+      if(cal_count (5 downto 4) = x"01") then
+        rx_cal_pulse_a <= '1';
+      else
+        rx_cal_pulse_a <= '0';
+      end if;
+      
+    end if;
+  end process;
+
+
+  rx_trigger_a       <= (rx_timestamp_trigger_p_a_i and rx_trigger_mask) or rx_cal_pulse_a;
+  -- Sync chains for timestamp strobes: 4 combinations - (TX-RX) -> (rising/falling)
+  sync_ffs_tx_r : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_ref_i,
+      rst_n_i  => rst_n_ref_i,
+      data_i   => tx_timestamp_trigger_p_a_i,
+      synced_o => open,
+      npulse_o => open,
+      ppulse_o => take_tx_synced_p);
+
+
+  
+  sync_ffs_rx_r : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_ref_i,
+      rst_n_i  => rst_n_ref_i,
+      data_i   => rx_trigger_a,
+      synced_o => open,
+      npulse_o => open,
+      ppulse_o => take_rx_synced_p);
+
+
+  sync_ffs_tx_f : gc_sync_ffs
+    generic map (
+      g_sync_edge => "negative")
+    port map (
+      clk_i    => clk_ref_i,
+      rst_n_i  => rst_n_ref_i,
+      data_i   => tx_timestamp_trigger_p_a_i,
+      synced_o => open,
+      npulse_o => open,
+      ppulse_o => take_tx_synced_p_fedge);
+
+  sync_ffs_rx_f : gc_sync_ffs
+    generic map (
+      g_sync_edge => "negative")
+    port map (
+      clk_i    => clk_ref_i,
+      rst_n_i  => rst_n_ref_i,
+      data_i   => rx_trigger_a,
+      synced_o => open,
+      npulse_o => open,
+      ppulse_o => take_rx_synced_p_fedge);
+
+  
+
+  take_r : process(clk_ref_i)
+  begin
+    if rising_edge(clk_ref_i) then
+      if(rst_n_ref_i = '0') then
+        cntr_rx_r <= (others => '0');
+        cntr_tx_r <= (others => '0');
+
+        rx_sync_delay <= (others => '0');
+        tx_sync_delay <= (others => '0');
+      else
+        -- shift reg
+
+        if take_rx_synced_p = '1' then
+          cntr_rx_r                                                           <= cntr_r;
+          valid_rx                                                            <= pps_valid_i;
+          rx_sync_delay(rx_sync_delay'length-1 downto rx_sync_delay'length-4) <= (others => '1');
+        else
+          rx_sync_delay <= '0' & rx_sync_delay(rx_sync_delay'length-1 downto 1);
+        end if;
+
+        if take_tx_synced_p = '1' then
+          cntr_tx_r                                                           <= cntr_r;
+          valid_tx                                                            <= pps_valid_i;
+          tx_sync_delay(tx_sync_delay'length-1 downto tx_sync_delay'length-4) <= (others => '1');
+        else
+          tx_sync_delay <= '0' & tx_sync_delay(tx_sync_delay'length-1 downto 1);
+        end if;
+        
+      end if;
+    end if;
+  end process;
+
+  take_f : process(clk_ref_i)
+  begin
+    if falling_edge(clk_ref_i) then
+      if rst_n_ref_i = '0' then
+        cntr_rx_f <= (others => '0');
+        cntr_tx_f <= (others => '0');
+      else
+        if take_rx_synced_p_fedge = '1' then
+          cntr_rx_f <= cntr_f;
+        end if;
+        if take_tx_synced_p_fedge = '1' then
+          cntr_tx_f <= cntr_f;
+        end if;
+      end if;
+    end if;
+  end process;
+
+
+  -- timestamping "done" signals sync chains (clk_ref -> clk_sys)
+  tx_done_gen : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_sys_i,
+      rst_n_i  => rst_n_sys_i,
+      data_i   => tx_sync_delay(0),
+      synced_o => open,
+      npulse_o => tx_ts_done,
+      ppulse_o => open);
+
+  -- timestamping "done" signals sync chains (clk_rx -> clk_sys)
+  rx_done_gen : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_rx_i,
+      rst_n_i  => rst_n_rx_i,
+      data_i   => rx_sync_delay(0),
+      synced_o => open,
+      npulse_o => rx_ts_done,
+      ppulse_o => open);
+
+  txts_o <= tx_ts_done; 		-- 2013-Nov-28 peterj added for debugging/calibration
+  rxts_o <= rx_ts_done; 		-- 2013-Nov-28 peterj added for debugging/calibration
+
+  p_output_rx_ts : process (clk_rx_i)
+  begin
+    if rising_edge(clk_rx_i) then
+      if(rst_n_rx_i = '0') then
+        rxts_timestamp_stb_o   <= '0';
+        rxts_timestamp_o       <= (others => '0');
+        rxts_timestamp_valid_o <= '0';
+      else
+        if(regs_i. tscr_en_rxts_o = '0') then
+          rxts_timestamp_stb_o <= '0';
+        elsif(rx_ts_done = '1' and regs_i.tscr_en_rxts_o = '1') then
+          rxts_timestamp_stb_o   <= '1';
+          rxts_timestamp_valid_o <= valid_rx;
+          rxts_timestamp_o       <= cntr_rx_f & cntr_rx_r;
+        end if;
+      end if;
+    end if;
+  end process;
+
+
+  p_output_tx_ts : process (clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if(rst_n_sys_i = '0') then
+        txts_timestamp_o       <= (others => '0');
+        txts_timestamp_stb_o   <= '0';
+        txts_timestamp_valid_o <= '0';
+      elsif(tx_ts_done = '1' and regs_i.tscr_en_txts_o = '1') then
+        txts_timestamp_o       <= cntr_tx_f & cntr_tx_r;
+        txts_timestamp_stb_o   <= '1';
+        txts_timestamp_valid_o <= valid_tx;
+      end if;
+    end if;
+  end process;
+
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_ts_counter.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_ts_counter.vhd
new file mode 100644
index 000000000..2b9589f5a
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_ts_counter.vhd
@@ -0,0 +1,152 @@
+-------------------------------------------------------------------------------
+-- Title      : Optical 1000base-X endpoint - IEEE1588 timestamping counter
+-- Project    : White Rabbit Switch
+-------------------------------------------------------------------------------
+-- File       : ep_ts_counter.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2009-06-22
+-- Last update: 2017-02-03
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'87
+-------------------------------------------------------------------------------
+-- Description: Implementation of dual-edge synchronous counter for
+-- PTP timestamping purposes. Falling edge counter always follows the value of
+-- rising edge counter. For space reasons only some LSBs of falling edge
+-- counter are outputted.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2009 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author    Description
+-- 2009-06-22  1.0      twlostow  Created
+-- 2010-09-01  1.0      twlostow  Added PPS sync
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.endpoint_private_pkg.all;
+
+entity ep_ts_counter is
+
+  generic (
+-- number of bits for rising edge counter
+    g_num_bits_r : natural := 27;
+-- number of bits to copy for falling edge counter
+    g_num_bits_f : natural := 5;
+-- initial value of the counter (after reset)
+    g_init_value : natural := 124999990;
+-- max value of the counter after reaching which it goes back to 0
+    g_max_value  : natural := 124999999
+    );
+
+  port (
+    -- counter clock 
+    clk_i      : in  std_logic;
+    -- synchronous reset, active LOW
+    rst_n_i    : in  std_logic;
+-- overflow indicator, active HI when counter value = g_max_value
+    overflow_o : out std_logic := '0';
+-- counter values (rising and falling edge)
+    value_r_o  : out std_logic_vector(g_num_bits_r-1 downto 0);
+    value_f_o  : out std_logic_vector(g_num_bits_f-1 downto 0);
+
+-- PPS pulse input, active HI, synchronous to clk_i. Resets the counter when
+-- synchronization is enabled
+    pps_p_i : in std_logic;
+
+-- Synchronization enable: a HI pulse on this line will cause the counter to be
+-- synced to next incoming PPS pulse. After then, sync_done_o will become HI.
+    sync_start_p_i : in std_logic;
+
+-- Synchronization done: HI indicates that we've got a PPS pulse we've been waiting for
+-- and now the counter value equals 0 when PPS pulse is active.
+    sync_done_o : out std_logic
+    );
+
+end ep_ts_counter;
+
+architecture syn of ep_ts_counter is
+
+  signal cntr_r           : unsigned(g_num_bits_r-1 downto 0) := (others => '0');
+  signal cntr_f           : unsigned (g_num_bits_f-1 downto 0);
+  
+begin  -- syn
+
+
+  -- the main TS counter counts on rising clock edge.
+  rising_ctr : process (clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if(rst_n_i = '0') then
+        cntr_r           <= to_unsigned(g_init_value, g_num_bits_r);
+        sync_done_o      <= '1';
+      else
+
+-- we've got a synchronization request
+        --if(sync_start_p_i = '1') then
+        --  sync_in_progress <= '1';
+        --  sync_done_o      <= '0';
+-- so wait for the next PPS pulse, and then set the PPS counter to 1 (so it
+-- equals to 0 when PPS input is active)
+        --elsif(sync_in_progress = '1' and pps_p_i = '1') then
+        --  sync_in_progress <= '0';
+        --  sync_done_o      <= '1';
+        --  cntr_r           <= to_unsigned(1, g_num_bits_r);
+        --else
+
+
+        -- increment the counter, reset on overflow
+        if(cntr_r = to_unsigned(g_max_value, g_num_bits_r) or pps_p_i = '1') then
+          cntr_r <= (others => '0');
+        else
+          cntr_r <= cntr_r + 1;
+        end if;
+      end if;
+
+      -- generate overflow output
+      if(cntr_r = to_unsigned(0, g_num_bits_r)) then
+        overflow_o <= '1';
+      else
+        overflow_o <= '0';
+      end if;
+--      end if;
+    end if;
+  end process;
+
+
+-- the falling edge counter just copies the rising edge counter half a clock
+-- cycle after.
+  falling_ctr : process(clk_i)
+  begin
+    if falling_edge(clk_i)then
+      cntr_f <= cntr_r(g_num_bits_f-1 downto 0);
+    end if;
+  end process;
+
+  -- stupid VHDL type conversion mumbo-jumbo
+  value_r_o <= std_logic_vector(cntr_r);
+  value_f_o <= std_logic_vector(cntr_f);
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_crc_inserter.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_crc_inserter.vhd
new file mode 100644
index 000000000..a560f06e6
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_crc_inserter.vhd
@@ -0,0 +1,267 @@
+-------------------------------------------------------------------------------
+-- Title      : 1000base-X MAC/Endpoint
+-- Project    : White Rabbit 
+-------------------------------------------------------------------------------
+-- File       : ep_tx_crc_inserter.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2009-06-22
+-- Last update: 2017-02-02
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Calculates and embeds the CRC into the transmitted frame.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2009-2012 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+
+use work.gencores_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.endpoint_private_pkg.all;
+use work.endpoint_pkg.all;
+use work.ep_wbgen2_pkg.all;
+use work.ep_crc32_pkg.all;
+
+entity ep_tx_crc_inserter is
+  generic(
+    g_use_new_crc	: boolean := false);
+  port (
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    snk_fab_i  : in  t_ep_internal_fabric;
+    snk_dreq_o : out std_logic;
+
+    src_fab_o  : out t_ep_internal_fabric;
+    src_dreq_i : in  std_logic;
+    dbg_o      : out std_logic_vector(2 downto 0)
+    );
+end ep_tx_crc_inserter;
+
+architecture behavioral of ep_tx_crc_inserter is
+
+  type t_state is (IDLE, WAIT_CRC, EMBED_1, EMBED_2, EMBED_3);
+
+-- general signals
+  signal state : t_state;
+
+-- CRC generator signals
+  signal crc_gen_reset  : std_logic;
+  signal crc_gen_enable : std_logic;
+  signal crc_value      : std_logic_vector(31 downto 0);
+
+  signal odd_length : std_logic;
+
+  signal embed_valid : std_logic;
+
+  signal stored_msb : std_logic_vector(7 downto 0);
+  signal in_payload : std_logic;
+  signal src_dreq_d0 : std_logic;
+
+  signal crc_p_value, crc_n_value : std_logic_vector(31 downto 0);
+  --signal crc_next, crc_new	:	std_logic_vector(31 downto 0);
+  
+begin  -- behavioral
+
+  dbg_o          <= "111" when (state = IDLE) else
+                    "110" when (state = WAIT_CRC) else
+                    "101" when (state = EMBED_1) else
+                    "100" when (state = EMBED_2) else
+                    "011" when (state = EMBED_3) else
+                    "000";
+
+  in_payload     <= '1' when (state = IDLE or state = WAIT_CRC) else '0';
+-- ML: potential optimization (if desperate)
+-- in_payload     <= '1' when (state = IDLE or state = WAIT_CRC) or (src_dreq_d0 = '1' and odd_length = '0' and state = EMBED_2)) else '0';
+  crc_gen_reset  <= '1' when rst_n_i = '0' or snk_fab_i.sof = '1'                                         else '0';
+  crc_gen_enable <= '1' when (snk_fab_i.dvalid = '1' and in_payload = '1') else '0';
+
+	gen_old_crc: if(g_use_new_crc = false) generate
+  	U_tx_crc_generator : gc_crc_gen
+  	  generic map (
+  	    g_polynomial              => x"04C11DB7",
+  	    g_init_value              => x"ffffffff",
+  	    g_residue                 => x"38fb2284",
+  	    g_data_width              => 16,
+  	    g_half_width              => 8,
+  	    g_sync_reset              => 1,
+  	    g_dual_width              => 1,
+  	    g_registered_match_output => false,
+  	    g_registered_crc_output   => true)
+  	  port map (
+  	    clk_i   => clk_sys_i,
+  	    rst_i   => crc_gen_reset,
+  	    en_i    => crc_gen_enable,
+  	    half_i  => snk_fab_i.bytesel,
+  	    data_i  => snk_fab_i.data,
+  	    match_o => open,
+  	    crc_o   => crc_value);
+	end generate;
+
+	gen_new_crc: if(g_use_new_crc = true) generate
+		p_check_crc_p: process(clk_sys_i)
+		begin
+			if falling_edge(clk_sys_i) then
+				if(crc_gen_reset = '1')then
+					crc_n_value <= c_CRC32_INIT_VALUE;
+				elsif(crc_gen_enable = '1') then
+					crc_n_value <= f_update_crc32_d8(crc_p_value, snk_fab_i.data(15 downto 8));
+				end if;
+			end if;
+		end process;
+
+		p_check_crc_n: process(clk_sys_i)
+		begin
+			if rising_edge(clk_sys_i) then
+				if(crc_gen_reset = '1') then
+					crc_p_value <= c_CRC32_INIT_VALUE;
+				elsif(crc_gen_enable = '1' and snk_fab_i.bytesel = '0') then
+					crc_p_value <= f_update_crc32_d8(crc_n_value, snk_fab_i.data(7 downto 0));
+				end if;
+			end if;
+		end process;
+
+		crc_value <= crc_p_value when odd_length = '0' else
+								 crc_n_value;
+
+	end generate;
+
+  p_delay_dreq: process(clk_sys_i)
+    begin
+      if rising_edge(clk_sys_i) then
+        src_dreq_d0 <= src_dreq_i;
+      end if;
+    end process;
+  
+  p_crc_fsm : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if(rst_n_i = '0' or snk_fab_i.error = '1') then
+        state     <= IDLE;
+      else
+        case state is
+          when IDLE =>
+            odd_length <= '0';
+
+            if(snk_fab_i.sof = '1') then
+              state <= WAIT_CRC;
+            end if;
+            
+          when WAIT_CRC =>
+            if(snk_fab_i.bytesel = '1') then
+              odd_length <= '1';
+              stored_msb <= snk_fab_i.data(15 downto 8);
+            end if;
+
+            if(snk_fab_i.eof = '1' or snk_fab_i.addr = c_WRF_OOB) then
+              state <= EMBED_1;
+            end if;
+
+          when EMBED_1 =>
+            if(src_dreq_d0 = '1') then
+              state <= EMBED_2;
+            end if;
+
+          when EMBED_2 =>
+            if(src_dreq_d0 = '1') then
+              if(odd_length = '1') then
+                state <= EMBED_3;
+              else
+                state     <= IDLE;
+              end if;
+            end if;
+            
+          when EMBED_3 =>
+            if(src_dreq_d0 = '1') then
+              state     <= IDLE;
+            end if;
+        end case;
+      end if;
+    end if;
+  end process;
+
+  p_drive_data_addr : process(state, crc_value, odd_length, stored_msb, snk_fab_i, src_dreq_d0)
+  begin
+
+    case state is
+      when EMBED_1 =>
+        if(odd_length = '1') then
+          src_fab_o.data    <= stored_msb & crc_value(31 downto 24);
+          src_fab_o.addr    <= c_WRF_DATA;
+          src_fab_o.bytesel <= '0';
+          src_fab_o.dvalid <= src_dreq_d0;
+          src_fab_o.eof <= '0';
+        else
+          src_fab_o.data    <= crc_value(31 downto 16);
+          src_fab_o.addr    <= c_WRF_DATA;
+          src_fab_o.bytesel <= '0';
+          src_fab_o.dvalid <= src_dreq_d0;
+          src_fab_o.eof <= '0';
+        end if;
+
+      when EMBED_2 =>
+        if(odd_length = '1') then
+          src_fab_o.data    <= crc_value(23 downto 8);
+          src_fab_o.addr    <= c_WRF_DATA;
+          src_fab_o.bytesel <= '0';
+          src_fab_o.dvalid <= src_dreq_d0;
+          src_fab_o.eof <= '0';
+        else
+          src_fab_o.data    <= crc_value(15 downto 0);
+          src_fab_o.addr    <= c_WRF_DATA;
+          src_fab_o.bytesel <= '0';
+          src_fab_o.dvalid <= src_dreq_d0;
+          src_fab_o.eof <= '1';
+        end if;
+        
+      when EMBED_3 =>
+        src_fab_o.data    <= crc_value(7 downto 0) & "XXXXXXXX";
+        src_fab_o.addr    <= c_WRF_DATA;
+        src_fab_o.bytesel <= '1';
+        src_fab_o.dvalid <= src_dreq_d0;
+        src_fab_o.eof <= '1';
+
+      when others =>
+        src_fab_o.data    <= snk_fab_i.data;
+        src_fab_o.addr    <= snk_fab_i.addr;
+        src_fab_o.bytesel <= '0';
+        src_fab_o.dvalid <= snk_fab_i.dvalid and not snk_fab_i.bytesel;
+        src_fab_o.eof <= '0';
+  
+    end case;
+
+    src_fab_o.addr <= c_WRF_DATA;
+  end process;
+
+  snk_dreq_o                   <= src_dreq_i and in_payload;
+  src_fab_o.sof                <= snk_fab_i.sof;
+  src_fab_o.error              <= snk_fab_i.error;
+  src_fab_o.has_rx_timestamp   <= snk_fab_i.has_rx_timestamp;
+  src_fab_o.rx_timestamp_valid <= snk_fab_i.rx_timestamp_valid;
+
+end behavioral;
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_header_processor.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_header_processor.vhd
new file mode 100644
index 000000000..233f0b130
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_header_processor.vhd
@@ -0,0 +1,723 @@
+-------------------------------------------------------------------------------
+-- Title      : 1000base-X MAC/Endpoint - TX packet header processing unit
+-- Project    : White Rabbit
+-------------------------------------------------------------------------------
+-- File       : ep_tx_header_processor.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2009-06-22
+-- Last update: 2017-02-02
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Processes headers and OOBs of the packets to be transmitted.
+-- - provides a Wishbone-B4 interface to the host
+-- - embeds source MAC addresses if they aren't defined by the host
+-- - decodes TX OOB data and passes it to the timestamping unit
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2009 - 2017 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.gencores_pkg.all;
+use work.genram_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.endpoint_private_pkg.all;
+use work.endpoint_pkg.all;
+use work.ep_wbgen2_pkg.all;
+
+entity ep_tx_header_processor is
+  generic(
+    g_with_packet_injection : boolean;
+    g_with_timestamper      : boolean;
+    g_force_gap_length      : integer;
+    g_runt_padding          : boolean
+    );
+
+  port (
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+------------------------------------------------------------------------------
+-- Physical Coding Sublayer (PCS) interface
+------------------------------------------------------------------------------
+
+    src_fab_o  : out t_ep_internal_fabric;
+    src_dreq_i : in  std_logic;
+
+    pcs_busy_i  : in std_logic;
+    pcs_error_i : in std_logic;
+
+-------------------------------------------------------------------------------
+-- WRF Sink (see WRF specification for the details)
+-------------------------------------------------------------------------------    
+
+    wb_snk_i : in  t_wrf_sink_in;
+    wb_snk_o : out t_wrf_sink_out;
+
+-------------------------------------------------------------------------------
+-- Flow Control Unit signals
+-------------------------------------------------------------------------------    
+
+-- TX send pause frame - when active, the framer will send a PAUSE frame
+-- as soon as possible. The pause quanta must be provided on tx_pause_delay_i input.
+    fc_pause_req_i   : in std_logic;
+    fc_pause_delay_i : in std_logic_vector(15 downto 0);
+
+-- TX send pause acknowledge - active after the current pause send request has
+-- been completed
+    fc_pause_ready_o : out std_logic;
+
+-- When active, the framer will allow for packet transmission.
+    fc_flow_enable_i : in std_logic;
+
+-------------------------------------------------------------------------------
+-- OOB/TSU signals
+-------------------------------------------------------------------------------    
+
+-- Port ID value
+    txtsu_port_id_o      : out std_logic_vector(4 downto 0);
+-- Frame ID value
+    txtsu_fid_o          : out std_logic_vector(16 -1 downto 0);
+-- Encoded timestamps
+    txtsu_ts_value_o     : out std_logic_vector(28 + 4 - 1 downto 0);
+    txtsu_ts_incorrect_o : out std_logic;
+
+-- TX timestamp strobe: HI tells the TX timestamping unit that a timestamp is
+-- available on txtsu_ts_value_o, txtsu_fid_o andd txtsu_port_id_o. The correctness
+-- of the timestamping is indiacted on txtsu_ts_incorrect_o. Line remains HI
+-- until assertion of txtsu_ack_i.
+    txtsu_stb_o : out std_logic;
+
+-- TX timestamp acknowledge: HI indicates that TXTSU has successfully received
+-- the timestamp
+    txtsu_ack_i : in std_logic;
+
+---------------------------------------------------------------------------
+-- Timestamp input from the timestamping unit
+---------------------------------------------------------------------------
+    txts_timestamp_i       : in std_logic_vector(31 downto 0);
+    txts_timestamp_valid_i : in std_logic;
+
+-------------------------------------------------------------------------------
+-- Control registers
+-------------------------------------------------------------------------------
+    ep_ctrl_i           : in std_logic;
+    regs_i : in t_ep_out_registers
+
+    );
+
+
+end ep_tx_header_processor;
+
+architecture behavioral of ep_tx_header_processor is
+
+  constant c_IFG_LENGTH : integer := g_force_gap_length ;--0;
+  constant c_MIN_FRAME_THR  : integer := 30;
+  constant c_MIN_QFRAME_THR : integer := 32; -- we need to pad more 802.1q
+                                             -- tagged frame if it's going to be
+                                             -- untagged later in the tx_path
+
+  type t_tx_framer_state is (TXF_IDLE, TXF_DELAYED_SOF, TXF_ADDR, TXF_DATA, TXF_GAP, TXF_PAD, TXF_ABORT, TXF_STORE_TSTAMP);
+
+-- general signals
+  signal state   : t_tx_framer_state;
+  signal counter : unsigned(13 downto 0);
+
+-- Flow Control-related signals
+  signal tx_pause_mode  : std_logic;
+
+  signal snk_valid : std_logic;
+
+  signal sof_p1, eof_p1, abort_p1, error_p1 : std_logic;
+  signal snk_cyc_d0                         : std_logic;
+
+  signal stored_status : t_wrf_status_reg;
+
+  type t_oob_fsm_state is (OOB_IDLE, OOB_1, OOB_2);
+
+  signal oob_state : t_oob_fsm_state;
+  signal oob       : t_wrf_oob;
+
+  signal wb_out         : t_wrf_sink_out;
+  signal decoded_status : t_wrf_status_reg;
+
+  signal abort_now : std_logic;
+  signal stall_int : std_logic;
+  signal tx_en        : std_logic;
+  signal ep_ctrl     : std_logic;
+  signal bitsel_d    : std_logic;
+  signal needs_padding  : std_logic;
+  signal to_be_untagged : std_logic;
+  signal sof_reg     : std_logic;
+
+  function b2s (x : boolean)
+    return std_logic is
+  begin
+    if(x) then
+      return '1';
+    else
+      return '0';
+    end if;
+  end function;
+
+  function f_pick (cond : boolean; when_1 : std_logic_vector; when_0 : std_logic_vector)
+    return std_logic_vector is
+  begin
+    if(cond) then
+      return when_1;
+    else
+      return when_0;
+    end if;
+  end function;
+
+  function f_pick (cond : std_logic; when_1 : std_logic_vector; when_0 : std_logic_vector)
+    return std_logic_vector is
+  begin
+    if(cond = '1') then
+      return when_1;
+    else
+      return when_0;
+    end if;
+  end function;
+
+  function f_pick (cond : boolean; when_1 : std_logic ; when_0 : std_logic)
+    return std_logic is
+  begin
+    if(cond) then
+      return when_1;
+    else
+      return when_0;
+    end if;
+  end function;
+  
+  function f_fabric_2_slv (
+    in_i : t_wrf_sink_in;
+    in_o : t_wrf_sink_out) return std_logic_vector is
+    variable tmp : std_logic_vector(31 downto 0);
+  begin
+    tmp(15 downto 0)  := in_i.dat;
+    tmp(17 downto 16) := in_i.adr;
+    tmp(19 downto 18) := in_i.sel;
+    tmp(20)           := in_i.cyc;
+    tmp(21)           := in_i.stb;
+    tmp(22)           := in_i.we;
+    tmp(23)           := in_o.ack;
+    tmp(24)           := in_o.stall;
+    tmp(25)           := in_o.err;
+    tmp(26)           := in_o.rty;
+    return tmp;
+  end f_fabric_2_slv;
+  
+begin  -- behavioral
+  
+  p_detect_frame : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        snk_cyc_d0 <= '0';
+      else
+        snk_cyc_d0 <= wb_snk_i.cyc;
+      end if;
+    end if;
+  end process;
+
+  sof_p1 <= not snk_cyc_d0 and wb_snk_i.cyc;
+  eof_p1 <= snk_cyc_d0 and not wb_snk_i.cyc;
+
+  snk_valid <= (wb_snk_i.cyc and wb_snk_i.stb and wb_snk_i.we) and not wb_out.stall;
+
+  decoded_status <= f_unmarshall_wrf_status(wb_snk_i.dat);
+
+  error_p1 <= snk_valid and b2s(wb_snk_i.adr = c_WRF_STATUS) and decoded_status.error;
+
+-- abort_now <= '1' when (state /= TXF_IDLE and state /= TXF_GAP) and (regs_i.ecr_tx_en_o = '0' or error_p1 = '1') else '0';
+ abort_now <= '1' when (state /= TXF_IDLE and state /= TXF_GAP) and (tx_en = '0' or error_p1 = '1') else
+              '1' when (state = TXF_ABORT and wb_snk_i.cyc = '1' ) else 
+              '0'; -- ML
+
+  GEN_PADDING: if(g_runt_padding) generate
+    needs_padding <= '1' when( (to_be_untagged = '1' and counter < c_MIN_QFRAME_THR) or
+                                counter < c_MIN_FRAME_THR) else
+                     '0';
+  end generate;
+  GEN_NOPADDING: if( not g_runt_padding) generate
+    -- even if padding is disabled, we still need to pad short 802.1q frames
+    -- that will be untagged
+    needs_padding <= '1' when (to_be_untagged = '1' and counter < c_MIN_QFRAME_THR) else
+                     '0';
+  end generate;
+
+  process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if(rst_n_i='0') then
+        sof_reg <= '0';
+      elsif(sof_p1='1') then
+        sof_reg <= '1';
+      elsif(state = TXF_ADDR) then
+        sof_reg <= '0';
+      end if;
+    end if;
+  end process;
+
+  p_store_status : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      
+      if rst_n_i = '0' or tx_pause_mode = '1' then
+        stored_status.has_smac <= '0';
+        stored_status.is_hp    <= '0';
+        stored_status.has_crc  <= '0';
+      else
+        if(snk_valid = '1' and wb_snk_i.adr = c_WRF_STATUS) then
+          stored_status <= f_unmarshall_wrf_status(wb_snk_i.dat);
+        end if;
+      end if;
+    end if;
+  end process;
+
+  -----------------------------------------------------------------------------
+  -- Out-of-band handling state machine. When a packet comes with OOB info
+  -- (frame ID), it is registered here. Then the main FSM waits until the TX
+  -- FIFO of the endpoint is completely empty and pushes the last timestamp 
+  -- from the PCS to the TX Timestamping Unit
+  -----------------------------------------------------------------------------
+  gen_ts_supported : if(g_with_timestamper) generate
+    p_oob_fsm : process(clk_sys_i)
+    begin
+      if rising_edge(clk_sys_i) then
+        if (rst_n_i = '0' or state = TXF_ADDR) then
+          oob_state    <= OOB_1;
+          oob.valid    <= '0';
+          oob.oob_type <= (others => '0');
+        else
+          
+          case oob_state is
+            when OOB_1 =>
+              if(snk_valid = '1' and wb_snk_i.adr = c_WRF_OOB) then
+                oob.oob_type <= wb_snk_i.dat(15 downto 12);
+                oob_state    <= OOB_2;
+                oob.valid    <= '0';
+              end if;
+              
+            when OOB_2 =>
+              if(snk_valid = '1' and wb_snk_i.adr = c_WRF_OOB and oob.oob_type = c_WRF_OOB_TYPE_TX) then
+                oob.frame_id <= wb_snk_i.dat(15 downto 0);
+                oob_state    <= OOB_IDLE;
+                oob.valid    <= '1';
+              end if;
+              
+            when OOB_IDLE =>
+              oob_state <= OOB_IDLE;
+          end case;
+        end if;
+      end if;
+    end process;
+  end generate gen_ts_supported;
+
+  p_tx_fsm : process (clk_sys_i)
+  begin  -- process
+    if rising_edge(clk_sys_i) then
+      if(rst_n_i = '0') then
+        state <= TXF_IDLE;
+
+        src_fab_o.has_rx_timestamp   <= '0';
+        src_fab_o.rx_timestamp_valid <= '0';
+        src_fab_o.dvalid             <= '0';
+        src_fab_o.ERROR              <= '0';
+        src_fab_o.sof                <= '0';
+        src_fab_o.eof                <= '0';
+        src_fab_o.bytesel            <= '0';
+
+        wb_out.err <= '0';
+        wb_out.rty <= '0';
+
+        tx_pause_mode <= '0';
+
+        fc_pause_ready_o <= '1';
+
+        txtsu_stb_o <= '0';
+        bitsel_d  <= '0';
+        to_be_untagged <= '0';
+
+      else
+
+        -- we are in the middle of the frame and the framer has got suddenly
+        -- disabled or we've received an ABORT command or an error occured in the PCS:
+
+        if(pcs_error_i = '1') then
+          state      <= TXF_IDLE;
+          wb_out.rty <= '1';
+          ----------------------------------------------------------------------------------
+          src_fab_o.error  <= '1'; -- nasty-bug-fix: it might happen that PCS throws error
+                                   -- to a previous frame, but we already start sending
+                                   -- the next one, in this case the frame is stopped being
+                                   -- sent but PCS does not know why... in the end we see
+                                   -- two SOFs in PACs
+          ----------------------------------------------------------------------------------                         
+        elsif(abort_now = '1') then
+          -- abort the current frame
+          state            <= TXF_ABORT;
+          src_fab_o.sof    <= '0';
+          src_fab_o.dvalid <= '0';
+
+        else
+
+          case state is
+
+-------------------------------------------------------------------------------
+-- TX FSM state IDLE: awaits incoming TX frames
+-------------------------------------------------------------------------------
+
+            when TXF_IDLE =>            -- idle state - wait for the next frame
+
+              wb_out.err <= '0';
+              wb_out.rty <= '0';
+
+              txtsu_stb_o <= '0';
+              bitsel_d    <= '0';
+
+              src_fab_o.error  <= '0';
+              src_fab_o.eof    <= '0';
+              src_fab_o.dvalid <= '0';
+              src_fab_o.bytesel <= '0';
+              to_be_untagged    <= '0';
+
+              -- Check start-of-frame and send-pause signals and eventually
+              -- commence frame transmission
+
+--             if(src_dreq_i = '1' and (sof_p1 = '1' or fc_pause_req_i = '1') and tx_en = '1') then --ML:removed
+--            EXPLANATION: removed src_dreq_i = '1' as the cycle can start on stall HIGH (dreq_i LOW), 
+--            it means that if we wait for dreq to be high.... we can miss SOF and thus entire frame. 
+--            New state added to include a case where SOF (start of cycle) starts when dreq is LOW.
+--            (we cannot just go to TXF_ADDR... it is because the PCS needs the minimal gap to add CRC)
+              if((sof_p1 = '1' or sof_reg='1' or fc_pause_req_i = '1') and tx_en = '1') then --ML
+
+                fc_pause_ready_o <= '0';
+                tx_pause_mode    <= fc_pause_req_i;
+
+                counter       <= (others => '0');
+                
+                if(src_dreq_i = '1') then
+                  state         <= TXF_ADDR;
+                  src_fab_o.sof <= '1';
+                end if;
+                
+              else
+                src_fab_o.sof <= '0';
+              end if;
+
+-------------------------------------------------------------------------------
+-- TX FSM (ML-added): this state takes into accunt the rare case where SOF happens 
+-- when dreq is LOW (PCS not ready). So we wait for dreq HIGH and STALL in the 
+-- meanttime (see process at the end)
+-------------------------------------------------------------------------------
+            when TXF_DELAYED_SOF =>
+             
+              if(src_dreq_i = '1') then
+                state         <= TXF_ADDR;
+                src_fab_o.sof <= '1';
+             end if;              
+-------------------------------------------------------------------------------
+-- TX FSM state HEADER: processes the frame header, send pause frames
+-- if compiled without packet injection support.
+-------------------------------------------------------------------------------
+
+            when TXF_ADDR =>
+              src_fab_o.sof <= '0';
+              
+              if (src_dreq_i = '1' and ((snk_valid = '1' and wb_snk_i.adr = c_WRF_DATA) or (tx_pause_mode = '1' and not g_with_packet_injection))) then
+
+                counter          <= counter + 1;
+                src_fab_o.dvalid <= '1';
+
+                case counter(3 downto 0) is
+                  when x"0" =>
+                    src_fab_o.data <= f_pick(tx_pause_mode = '1' and not g_with_packet_injection, x"0180", wb_snk_i.dat);
+                  when x"1" =>
+                    src_fab_o.data <= f_pick(tx_pause_mode = '1' and not g_with_packet_injection, x"c200", wb_snk_i.dat);
+                  when x"2" =>
+                    src_fab_o.data <= f_pick(tx_pause_mode = '1' and not g_with_packet_injection, x"0001", wb_snk_i.dat);
+                  when x"3" =>
+                    src_fab_o.data <= f_pick(stored_status.has_smac, wb_snk_i.dat, regs_i.mach_o);
+                  when x"4" =>
+                    src_fab_o.data <= f_pick(stored_status.has_smac, wb_snk_i.dat, regs_i.macl_o(31 downto 16));
+                  when x"5" =>
+                    src_fab_o.data <= f_pick(stored_status.has_smac, wb_snk_i.dat, regs_i.macl_o(15 downto 0));
+                    if(tx_pause_mode = '0' or g_with_packet_injection) then
+                      state <= TXF_DATA;
+                    end if;
+                  when x"6" =>
+                    src_fab_o.data <= f_pick(g_with_packet_injection, "XXXXXXXXXXXXXXXX", x"8808");
+                    to_be_untagged <= f_pick(wb_snk_i.dat = x"8100" and
+                                             regs_i.vcr0_qmode_o = c_QMODE_PORT_ACCESS, '1', '0');
+                  when x"7" =>
+                    src_fab_o.data <= f_pick(g_with_packet_injection, "XXXXXXXXXXXXXXXX", x"0001"); -- peterj: IEEE 802.3 Table 31A-1 MAC control codes PAUSE (Annex 31B)
+                  when x"8" =>
+                    src_fab_o.data <= f_pick(g_with_packet_injection, "XXXXXXXXXXXXXXXX", fc_pause_delay_i); -- ML: bug ??? (forget optcode: 0x0001)
+                    state          <= TXF_PAD;
+                  when others =>
+                    state <= TXF_PAD;
+                end case;
+                
+                src_fab_o.addr   <= c_WRF_DATA;
+                
+              else
+                src_fab_o.dvalid <= '0';
+                src_fab_o.data   <= (others => 'X');
+                src_fab_o.addr   <= (others => 'X');
+              end if;
+
+-------------------------------------------------------------------------------
+-- TX FSM state PAD: pads a pause frame to 64 bytes.
+-------------------------------------------------------------------------------
+
+            when TXF_PAD =>
+              
+              if(src_dreq_i = '1') then
+                counter <= counter + 1;
+
+                src_fab_o.data   <= (others => '0');
+                src_fab_o.dvalid <= '1';
+                src_fab_o.addr   <= (others => '0');
+
+                if( (to_be_untagged = '1' and counter = c_MIN_QFRAME_THR-1) or
+                    (to_be_untagged = '0' and counter = c_MIN_FRAME_THR-1) ) then
+                  state <= TXF_GAP;
+                  src_fab_o.eof    <= '1';
+                end if;
+                
+              else
+                src_fab_o.data   <= (others => '0');
+                src_fab_o.dvalid <= '0';
+                src_fab_o.addr   <= (others => '0');
+              end if;
+
+-------------------------------------------------------------------------------
+-- TX FSM state DATA: trasmits frame payload
+-------------------------------------------------------------------------------
+
+            when TXF_DATA =>
+
+              -- ML: added this EOF force LOW to make sure that EOF is single cycle, withouth
+              -- this, it might have happened that we had eof_p1 but PCS was busy, so we set
+              -- src_fab_o.eof to HIGH but actually did not exit the TXF_DATA state... this
+              -- caused EOF to be longer than one cycle
+              src_fab_o.eof   <= '0'; 
+
+              if (counter = x"6") then
+                to_be_untagged <= f_pick(wb_snk_i.dat = x"8100" and
+                                         regs_i.vcr0_qmode_o = c_QMODE_PORT_ACCESS, '1', '0');
+              end if;
+              
+              if((wb_snk_i.adr = c_WRF_OOB or eof_p1='1') and needs_padding='1') then
+                state <= TXF_PAD;
+              elsif(eof_p1 = '1' and needs_padding='0') then
+                src_fab_o.eof <= '1';
+                counter       <= (others => '0');
+    
+                if(g_force_gap_length = 0 and bitsel_d = '1') then -- only for odd
+
+                  -- Submit the TX timestamp to the TXTSU queue
+                  if(oob.valid = '1' and oob.oob_type = c_WRF_OOB_TYPE_TX) then
+                    if(pcs_busy_i = '0') then
+                      txtsu_stb_o          <= '1';
+                      txtsu_ts_incorrect_o <= not txts_timestamp_valid_i;
+                      txtsu_ts_value_o     <= txts_timestamp_i;
+                      txtsu_port_id_o      <= regs_i.ecr_portid_o;
+                      txtsu_fid_o          <= oob.frame_id;
+                      state                <= TXF_STORE_TSTAMP;
+                    else
+                       -- wait in the GAP state for pcs_busy_i LOW
+                      state                <= TXF_GAP;
+                    end if;                                      ---if(pcs_busy_i = '0') then
+                  else
+                    -- dont need timestamp, don't need GAP, just go to IDLE
+                    state <= TXF_IDLE;
+                  end if;                                        -- if(oob.valid = '1' and oob.oob_type = c_WRF_OOB_TYPE_TX) then
+                else -- need some GAP
+                  state         <= TXF_GAP;
+                end if;                                          -- f(g_force_gap_length = 0 and bitsel_d = '1') then      
+              end if;                                            -- if(eof_p1 = '1') then
+
+              if(snk_valid = '1' and wb_snk_i.adr = c_WRF_DATA) then
+                src_fab_o.data    <= wb_snk_i.dat;
+                src_fab_o.dvalid  <= '1';
+                src_fab_o.bytesel <= (not wb_snk_i.sel(0)) and (not needs_padding);
+                counter <= counter + 1;
+              else
+                src_fab_o.dvalid  <= '0';
+                src_fab_o.data    <= (others => 'X');
+                src_fab_o.bytesel <= '0';
+              end if;
+              
+              if(wb_snk_i.sel(0) = '0') then
+                bitsel_d <='1';
+              end if;  
+
+              if(needs_padding='1') then
+                src_fab_o.addr  <= (others=>'0');
+              else
+                src_fab_o.addr    <= wb_snk_i.adr;
+              end if;
+
+-------------------------------------------------------------------------------
+-- TX FSM states: WAIT_CRC, EMBED_CRC: dealing with frame checksum field
+-------------------------------------------------------------------------------            
+
+            when TXF_GAP =>
+              src_fab_o.eof    <= '0';
+              src_fab_o.error  <= '0';
+              src_fab_o.dvalid <= '0';
+              wb_out.err       <= '0';
+              wb_out.rty       <= '0';
+              src_fab_o.bytesel <= '0';
+
+              if(counter >= c_IFG_LENGTH or g_force_gap_length = 0) then
+
+                -- Submit the TX timestamp to the TXTSU queue
+                if(oob.valid = '1' and oob.oob_type = c_WRF_OOB_TYPE_TX) then
+                  if(pcs_busy_i = '0') then
+                    txtsu_stb_o          <= '1';
+                    txtsu_ts_incorrect_o <= not txts_timestamp_valid_i;
+                    txtsu_ts_value_o     <= txts_timestamp_i;
+                    txtsu_port_id_o      <= regs_i.ecr_portid_o;
+                    txtsu_fid_o          <= oob.frame_id;
+                    state                <= TXF_STORE_TSTAMP;
+                  end if;
+                else
+                  state <= TXF_IDLE;
+                end if;
+
+              else
+                counter <= counter + 1;
+              end if;
+
+            when TXF_STORE_TSTAMP =>  -- to slow ??? anyway, we can finish the frame
+              
+              src_fab_o.eof    <= '0';
+              src_fab_o.error  <= '0';
+              src_fab_o.dvalid <= '0';
+              wb_out.err       <= '0';
+              wb_out.rty       <= '0';
+              src_fab_o.bytesel<= '0';
+
+              if(txtsu_ack_i = '1') then
+                txtsu_stb_o <= '0';
+                state       <= TXF_IDLE;
+              end if;
+
+-------------------------------------------------------------------------------
+-- TX FSM state ABORT: signalize underlying PCS block to abort the frame
+-- immediately, corrupting its contents
+-------------------------------------------------------------------------------            
+            when TXF_ABORT =>
+              src_fab_o.sof    <= '0';
+              src_fab_o.dvalid <= '1';
+              src_fab_o.error  <= '1';
+
+              counter <= (others => '0');
+              state   <= TXF_IDLE;
+
+          end case;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  tx_en <= regs_i.ecr_tx_en_o and ep_ctrl and ep_ctrl_i; 
+
+  --p_gen_stall : process(src_dreq_i, state, regs_i, wb_snk_i, snk_cyc_d0, tx_en)
+  p_gen_stall : process(src_dreq_i, state, tx_en, wb_snk_i, eof_p1)
+  begin
+    --if(regs_i.ecr_tx_en_o = '0') then
+    if(tx_en = '0') then --ML
+      wb_out.stall <= '0';              -- /dev/null if TX disabled
+--     elsif((wb_snk_i.cyc xor snk_cyc_d0) = '1') then
+--    elsif(wb_snk_i.cyc = '1' and snk_cyc_d0 = '0') then -- ML: do it only at the SOF, not EOF
+--      wb_out.stall <= '1';              -- /block for 1 cycle right upon
+                                        -- detection of a packet, so the FSM
+                                        -- has time to catch up
+    
+    -- stall at EOF - the SWcore should not send anything, but just in case, not to miss
+    -- SOF... the next cycle will be TXF_GAP (also stalling) or TXF_IDLE (can accept new frames)
+    elsif(eof_p1 = '1') then -- accept OOB as is      
+      wb_out.stall <= '1';
+      
+    -- when data is flowing (TXF_DATA) or we expect data (TXF_IDLE) stall only when no dreq_i 
+    -- from other modules
+---------------------------------------------------------------------------------------------
+-- ML: when error at the very end of the frame (e.g. due to jambo frame), stall happenend
+-- at the last cycle before cyc DOWN, subsequently, cycle did not finish and switch hanged
+---------------------------------------------------------------------------------------------
+--     elsif(src_dreq_i = '1' and state /= TXF_GAP and state /= TXF_ABORT and state /= TXF_DELAYED_SOF and state /= TXF_STORE_TSTAMP) then
+---------------------------------------------------------------------------------------------
+    elsif(src_dreq_i = '1' and state /= TXF_PAD and state /= TXF_GAP  and state /= TXF_DELAYED_SOF and state /= TXF_STORE_TSTAMP) then
+      wb_out.stall <= '0';              -- during data/header phase - whenever
+                                        -- the sink is ready to accept data
+    
+    -- when we receive OOB, there we have always resources/possibilties to accept it
+    -- since it is dumped in here, so we prevent dreq_i going LOW from stopping
+    -- to receive OOB
+    elsif(wb_snk_i.adr = c_WRF_OOB and wb_snk_i.cyc = '1') then -- accept OOB as is
+      wb_out.stall <= '0';              
+
+    -- one other option renderds stall 
+    else
+      wb_out.stall <= '1';
+    end if;
+  end process;
+
+  p_gen_ack : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      wb_out.ack <= snk_valid;
+    end if;
+  end process;
+
+  -- in theory, this should not happen: we don't send frames to ports which are DOWN, but..
+  -- we make sure that we don't start sending frames on the PHY in the middle of the frame...
+  -- the TX is enabled only when we don't receive any frames from SWcore
+  p_ctrl: process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if(rst_n_i = '0') then
+        ep_ctrl  <= '1';
+      else
+        if(ep_ctrl_i = '0') then
+          ep_ctrl <= '0';
+        elsif(ep_ctrl_i = '1' and wb_snk_i.cyc = '0') then
+          ep_ctrl <= '1';
+        end if; --ep_ctr
+      end if;-- rst
+    end if;  -- clk   
+  end process;
+
+  wb_snk_o <= wb_out;
+
+end behavioral;
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_inject_ctrl.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_inject_ctrl.vhd
new file mode 100644
index 000000000..766de7613
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_inject_ctrl.vhd
@@ -0,0 +1,235 @@
+-------------------------------------------------------------------------------
+-- Title      : Controller of
+-- Project    : White Rabbit MAC/Endpoint
+-------------------------------------------------------------------------------
+-- File       : ep_tx_inject_ctrl.vhd
+-- Author     : Maciej Lipinski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2014-01-16
+-- Last update: 2014-01-16
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: this module enables to control HW packet injection in order
+-- to turn the Endpoint into simple traffic generator for testing purposes
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2014 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.wr_fabric_pkg.all;
+use work.endpoint_private_pkg.all;
+use work.endpoint_pkg.all;
+use work.ep_wbgen2_pkg.all;
+
+entity ep_tx_inject_ctrl is
+
+  generic(
+    g_min_if_gap_length     : integer
+    );
+
+  port (
+    clk_sys_i             : in  std_logic;
+    rst_n_i               : in  std_logic;
+
+    snk_fab_i             : in  t_ep_internal_fabric;
+    snk_dreq_o            : out std_logic;
+
+    src_fab_o             : out t_ep_internal_fabric;
+    src_dreq_i            : in  std_logic;
+
+    inject_req_o          : out std_logic;
+    inject_ready_i        : in  std_logic;
+    inject_packet_sel_o   : out std_logic_vector(2 downto 0);
+    inject_user_value_o   : out std_logic_vector(15 downto 0);
+    inject_ctr_ena_o      : out std_logic;
+    inject_ctr_mode_o     : out std_logic_vector(1 downto 0);
+
+    regs_i                : in  t_ep_out_registers;
+    regs_o                : out t_ep_in_registers
+    );
+end ep_tx_inject_ctrl;
+
+architecture rtl of ep_tx_inject_ctrl is
+
+  -- there a lag between setting inject_req and SOF, this nees to be included
+  constant if_gap_offset : unsigned(15 downto 0) := x"0000"; -- unused
+  constant src_fab_null  : t_ep_internal_fabric := (
+    sof                => '0',
+    eof                => '0',
+    error              => '0',
+    dvalid             => '0',
+    bytesel            => '0',
+    has_rx_timestamp   => '0',
+    rx_timestamp_valid => '0',
+    data               => (others => '0'),
+    addr               => (others => '0'));
+  type t_state is (IDLE, INJECT_REQ, INJECT, IFG, END_GEN);
+  
+  -- Wishbone settings
+  signal if_gap_value  : unsigned(15 downto 0);
+  signal pck_sel       : std_logic_vector(2  downto 0);
+  signal gen_ena       : std_logic;
+  signal inj_mode      : std_logic_vector(1 downto 0);
+
+  signal if_gap_cnt    : unsigned(15 downto 0);
+  signal frame_id_cnt  : unsigned(15 downto 0);
+  signal within_packet : std_logic;
+  signal state         : t_state;
+
+  -- translation betwen if_gap_value and real IFG:
+  -- | ----------------------------------------- |
+  -- | if_gap_value | gap in words | gap in time |
+  -- |   0          |     7        |   112 ns    | disallowed 
+  -- | ......................................... |
+  -- |   5          |     12       |   192 ns    | minimal leagal
+  -- |   6          |     13       |   208 ns    | 
+  -- | ......................................... |
+  -- |   65536      |     65546    |   1.048ms   | maximum allowed due to register size (16 bits)
+  -- | ----------------------------------------- |
+begin  -- rtl
+
+  p_detect_within : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        within_packet <= '0';
+      else
+        if(snk_fab_i.sof = '1')then
+          within_packet <= '1';
+        elsif(snk_fab_i.eof = '1' or snk_fab_i.error = '1') then
+          within_packet <= '0';
+        end if;
+      end if;
+    end if;
+  end process;
+
+  p_config_reg: process(clk_sys_i)
+  begin
+   if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+          if_gap_value <= (others=>'0');
+          pck_sel      <= (others=>'0');
+          gen_ena      <= '0';
+          inj_mode     <= (others=>'0');
+      else
+        if(regs_i.inj_ctrl_pic_ena_load_o = '1') then  -- writing the register
+          if (regs_i.inj_ctrl_pic_conf_valid_o  = '1') then
+            if_gap_value <= unsigned(regs_i.inj_ctrl_pic_conf_ifg_o);
+            pck_sel      <= regs_i.inj_ctrl_pic_conf_sel_o;
+          end if;
+          if(regs_i.inj_ctrl_pic_mode_valid_o = '1') then
+            inj_mode     <= regs_i.inj_ctrl_pic_mode_id_o(1 downto 0);
+          end if;
+          gen_ena        <= regs_i.inj_ctrl_pic_ena_o;
+        end if;
+      end if;
+    end if;
+  end process;  
+
+  p_ctrl_fsm : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        state           <= IDLE;
+        inject_req_o    <= '0';
+        if_gap_cnt      <= (others => '0');
+        frame_id_cnt    <= (others => '0');
+      else
+        case state is
+          when IDLE =>
+            
+            --  start when 
+            --  1) inject enabled, and 
+            --  2) no packet being received from SWcore and 
+            --  3) no packet being just started (otherwise, we could have two SOFs
+            if(gen_ena = '1' and within_packet = '0' and snk_fab_i.sof = '0') then 
+              inject_req_o   <= '1';                                
+              if_gap_cnt     <= if_gap_offset;
+              frame_id_cnt   <= (others => '0');
+              state          <= INJECT_REQ;
+            end if;
+            
+          when INJECT_REQ =>
+            
+            inject_req_o <= '0';
+            state        <= INJECT;
+            
+          when INJECT =>
+          
+            if(inject_ready_i = '1') then
+              frame_id_cnt <= frame_id_cnt + 1;
+              state        <= IFG;
+            end if;
+          
+          when IFG =>
+            
+            if(gen_ena = '0' ) then --gen disabled
+              if_gap_cnt      <= (others => '0');
+              frame_id_cnt    <= (others => '0');             
+              if(within_packet = '0') then  -- if there is no frame being currently dumped
+                state           <= IDLE;    -- go to idle state          
+              else                          -- if there is a frame being dumped, 
+                state           <= END_GEN; -- wait until it finishes
+              end if;
+            elsif(if_gap_cnt < if_gap_value) then
+              if_gap_cnt <= if_gap_cnt + 1;
+            else
+              inject_req_o   <= '1';
+              if_gap_cnt     <= if_gap_offset;
+              state          <= INJECT_REQ;          
+            end if;
+            
+          when END_GEN =>
+          
+            if(within_packet = '0') then -- now we can gracefully come back to normal functing
+              state           <= IDLE; 
+            end if;
+          
+          when others =>
+
+            state           <= IDLE;
+            if_gap_cnt      <= (others => '0');
+            frame_id_cnt    <= (others => '0');              
+
+        end case;
+      end if;
+    end if;
+  end process;
+
+  inject_user_value_o            <= std_logic_vector(frame_id_cnt);
+  inject_packet_sel_o            <= pck_sel;
+  inject_ctr_ena_o               <= gen_ena;
+  inject_ctr_mode_o              <= inj_mode;
+  snk_dreq_o                     <= src_dreq_i when (state = IDLE) else '1';         -- dev/null if gen
+  src_fab_o                      <= snk_fab_i  when (state = IDLE) else src_fab_null;-- dev/null if gen
+  regs_o.inj_ctrl_pic_conf_ifg_i <= std_logic_vector(if_gap_value);
+  regs_o.inj_ctrl_pic_conf_sel_i <= pck_sel;
+  regs_o.inj_ctrl_pic_conf_valid_i  <= '0';
+  regs_o.inj_ctrl_pic_ena_i      <= gen_ena;
+  regs_o.inj_ctrl_pic_mode_id_i  <= '0' & inj_mode;
+
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_packet_injection.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_packet_injection.vhd
new file mode 100644
index 000000000..08e40970c
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_packet_injection.vhd
@@ -0,0 +1,251 @@
+-------------------------------------------------------------------------------
+-- Title      : 1000base-X MAC/Endpoint - TX packet injection unit
+-- Project    : White Rabbit
+-------------------------------------------------------------------------------
+-- File       : ep_tx_packet_injection.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2012-11-01
+-- Last update: 2013-03-12
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Asynchronously sends pre-defined packets upon a hardware request.
+-- Packet contents are defined in a buffer accessible via Wishbone. The buffer
+-- is shared with the TX VLAN unit and can contain templates of up to 8 packets
+-- of up to 128 bytes of size. It is possible to replace a selected 16-bit word
+-- within each template with a user-provided value.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2012-11-01  1.0      twlostow          Created
+-- 2013-03-12  1.1      mlipinsk          added empty-template protaciton 
+--                                        prepared signals for RMON
+-------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.endpoint_private_pkg.all;
+use work.endpoint_pkg.all;
+
+entity ep_tx_packet_injection is
+
+  port
+    (
+      clk_sys_i : in std_logic;
+      rst_n_i   : in std_logic;
+
+      snk_fab_i  : in  t_ep_internal_fabric;
+      snk_dreq_o : out std_logic;
+
+      src_fab_o  : out t_ep_internal_fabric;
+      src_dreq_i : in  std_logic;
+
+      inject_req_i        : in  std_logic;
+      inject_ready_o      : out std_logic;
+      inject_packet_sel_i : in  std_logic_vector(2 downto 0);
+      inject_user_value_i : in  std_logic_vector(15 downto 0);
+      inject_mode_i       : in  std_logic_vector(1 downto 0);
+      -- 0 : default
+      -- 1 : corrupt
+      -- 2 : unused
+      -- 3 : unused
+
+      mem_addr_o : out std_logic_vector(9 downto 0);
+      mem_data_i : in  std_logic_vector(17 downto 0)
+      );
+
+end ep_tx_packet_injection;
+
+architecture rtl of ep_tx_packet_injection is
+
+  type t_state is (WAIT_IDLE, SOF, DO_INJECT, EOF);
+
+  alias template_last  : std_logic is mem_data_i(16);
+  alias template_first : std_logic is mem_data_i(16);
+  alias template_user  : std_logic is mem_data_i(17);
+
+  signal state   : t_state;
+  signal counter : unsigned(8 downto 0);
+
+  signal within_packet : std_logic;
+  signal select_inject : std_logic;
+
+  signal inj_src            : t_ep_internal_fabric;
+  signal inject_req_latched : std_logic;
+  signal first_word         : std_logic; -- ML: used for masking the first word (we use the 
+                                         --     same bit for SOF and EOF
+  -- ML: singals for RMON counters
+  signal no_template_error  : std_logic; -- ML: indicates that injection was attempted with no valid template
+  signal inject_done        : std_logic; -- ML: indicates that requrested injection was successful
+  
+begin  -- rtl
+
+  snk_dreq_o  <= '0' when (state = DO_INJECT) else src_dreq_i;
+  inject_done <= '1' when (state = EOF and src_dreq_i = '1') else '0';
+  
+  p_detect_within : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        within_packet <= '0';
+      else
+        if(snk_fab_i.sof = '1')then
+          within_packet <= '1';
+        end if;
+
+        if(snk_fab_i.eof = '1' or snk_fab_i.error = '1') then
+          within_packet <= '0';
+        end if;
+      end if;
+    end if;
+  end process;
+
+  p_injection_request_ready : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        inject_ready_o     <= '1';
+        inject_req_latched <= '0';
+      else
+        if(inject_req_i = '1') then
+          inject_ready_o     <= '0';
+          inject_req_latched <= '1';
+        elsif(state = EOF and src_dreq_i = '1' ) then                     
+          inject_ready_o     <= '1';
+          inject_req_latched <= '0';
+        elsif(no_template_error = '1') then
+          inject_ready_o     <= '1';
+          inject_req_latched <= '0';        
+        end if;
+      end if;
+    end if;
+  end process;
+
+  p_injection_fsm : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        state             <= WAIT_IDLE;
+        select_inject     <= '0';
+        no_template_error <= '0';
+        inj_src.sof       <= '0';
+        inj_src.eof       <= '0';
+        inj_src.dvalid    <= '0'; 
+        inj_src.error     <= '0';
+        first_word        <= '0';    
+      else
+        case state is
+          when WAIT_IDLE =>
+            inj_src.sof       <= '0';
+            inj_src.eof       <= '0';
+            inj_src.dvalid    <= '0';
+            inj_src.error     <= '0';
+            no_template_error <= '0';
+            first_word        <= '0';
+
+            if(inject_req_i = '1') then --ML: we make sure that we remember the packet_sel_i 
+                                        --    only when req_i HIGH
+              counter(8 downto 6) <= unsigned(inject_packet_sel_i);
+              counter(5 downto 0) <= (others => '0');
+            end if;
+
+            if(within_packet = '0' and inject_req_latched = '1' and no_template_error = '0') then
+              state         <= SOF;
+              select_inject <= '1';
+            else
+              select_inject <= '0';
+            end if;
+            
+          when SOF =>
+            if(template_first = '0') then  -- ML: check that the first word is valid, abort if error
+              state             <= WAIT_IDLE;
+              no_template_error <= '1';
+            elsif(src_dreq_i = '1') then
+              first_word  <= '1';  -- since the same bit is for SOF and EOF, we need to mask SOF
+                                   -- during first word
+              inj_src.sof <= '1';
+              state       <= DO_INJECT;
+            end if;
+
+          when DO_INJECT =>
+            inj_src.sof <= '0';
+
+            if(src_dreq_i = '1') then
+
+              inj_src.dvalid <= '1';
+              counter        <= counter + 1;
+
+            else
+              inj_src.dvalid <= '0';
+            end if;
+            
+            if(first_word = '1' and template_first = '0') then -- ML: first word read
+              first_word <= '0';
+            end if;
+            
+            if(template_last = '1' and inj_src.dvalid = '1' and first_word = '0' and src_dreq_i = '1') then
+              inj_src.dvalid    <= '0';       
+              state             <= EOF;
+              if(inject_mode_i = "01") then
+                inj_src.error     <= '1';    
+              else
+                inj_src.eof       <= '1';
+              end if;
+            end if;
+            
+          when EOF =>
+            inj_src.eof       <= '0';
+            inj_src.error     <= '0';
+            if(src_dreq_i = '1') then
+              state         <= WAIT_IDLE;
+              select_inject <= '0'; 
+            end if;
+        end case;
+      end if;
+    end if;
+  end process;
+
+--   inj_src.bytesel <= '0';
+  -- the last word cannot be user-defined as we use the user bit to indicate  odd size
+  inj_src.bytesel <= template_user when (template_last = '1' and first_word = '0') else '0';
+--   inj_src.error   <= '0';
+
+  p_inj_src_data : process(template_user, inject_user_value_i, mem_data_i,template_last,first_word)
+  begin
+    if(template_user = '1' and template_last = '0' and first_word = '0') then
+      inj_src.data <= inject_user_value_i;
+    else
+      inj_src.data <= mem_data_i(15 downto 0);
+    end if;
+  end process;
+
+  src_fab_o <= inj_src when select_inject = '1' else snk_fab_i;
+
+
+  mem_addr_o <= '1' & std_logic_vector(counter);
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_path.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_path.vhd
new file mode 100644
index 000000000..ceba9c0a2
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_path.vhd
@@ -0,0 +1,352 @@
+-------------------------------------------------------------------------------
+-- Title      : Complete Transmit Path
+-- Project    : White Rabbit MAC/Endpoint
+-------------------------------------------------------------------------------
+-- File       : ep_tx_path.vhd
+-- Author     : Tomasz Włostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2012-11-01
+-- Last update: 2017-02-03
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Full transmit path of the endpoint (excluding the PCS).
+-- Chains the wishbone interface and header processor, followed by the VLAN unit
+-- (optional), packet injector (optional) and CRC inserter.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2009 - 2012 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.wr_fabric_pkg.all;
+use work.endpoint_private_pkg.all;
+use work.endpoint_pkg.all;
+use work.ep_wbgen2_pkg.all;
+
+entity ep_tx_path is
+
+  generic(
+    g_with_vlans            : boolean;
+    g_with_timestamper      : boolean;
+    g_with_packet_injection : boolean;
+    g_with_inj_ctrl         : boolean := true;
+    g_force_gap_length      : integer;
+    g_runt_padding          : boolean;
+    g_use_new_crc           :	boolean
+    );
+
+  port (
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+------------------------------------------------------------------------------
+-- Physical Coding Sublayer (PCS) interface
+------------------------------------------------------------------------------
+
+    pcs_fab_o   : out t_ep_internal_fabric;
+    pcs_error_i : in  std_logic;
+    pcs_busy_i  : in  std_logic;
+    pcs_dreq_i  : in  std_logic;
+
+-------------------------------------------------------------------------------
+-- WRF Sink (see WRF specification for the details)
+-------------------------------------------------------------------------------    
+
+    snk_i : in  t_wrf_sink_in;
+    snk_o : out t_wrf_sink_out;
+
+-------------------------------------------------------------------------------
+-- Flow Control Unit signals
+-------------------------------------------------------------------------------    
+
+-- TX send pause frame - when active, the framer will send a PAUSE frame
+-- as soon as possible. The pause quanta must be provided on tx_pause_delay_i input.
+    fc_pause_req_i   : in std_logic;
+    fc_pause_delay_i : in std_logic_vector(15 downto 0);
+
+-- TX send pause acknowledge - active after the current pause send request has
+-- been completed
+    fc_pause_ready_o : out std_logic;
+
+-- When active, the framer will allow for packet transmission.
+    fc_flow_enable_i : in std_logic;
+
+-------------------------------------------------------------------------------
+-- OOB/TSU signals
+-------------------------------------------------------------------------------    
+
+-- Port ID value
+    txtsu_port_id_o      : out std_logic_vector(4 downto 0);
+-- Frame ID value
+    txtsu_fid_o          : out std_logic_vector(16 -1 downto 0);
+-- Encoded timestamps
+    txtsu_ts_value_o     : out std_logic_vector(28 + 4 - 1 downto 0);
+    txtsu_ts_incorrect_o : out std_logic;
+
+-- TX timestamp strobe: HI tells the TX timestamping unit that a timestamp is
+-- available on txtsu_ts_value_o, txtsu_fid_o andd txtsu_port_id_o. The correctness
+-- of the timestamping is indiacted on txtsu_ts_incorrect_o. Line remains HI
+-- until assertion of txtsu_ack_i.
+    txtsu_stb_o : out std_logic;
+
+-- TX timestamp acknowledge: HI indicates that TXTSU has successfully received
+-- the timestamp
+    txtsu_ack_i : in std_logic;
+
+------------------------------------------------------------------------------
+-- Timestamp input from the timestamping unit
+------------------------------------------------------------------------------
+    txts_timestamp_i       : in std_logic_vector(31 downto 0);
+    txts_timestamp_valid_i : in std_logic;
+
+------------------------------------------------------------------------------
+-- Packet Injector (for TRU & HW-RSTP)
+------------------------------------------------------------------------------
+
+    inject_req_i        : in  std_logic                     := '0';
+    inject_ready_o      : out std_logic;
+    inject_packet_sel_i : in  std_logic_vector(2 downto 0)  := "000";
+    inject_user_value_i : in  std_logic_vector(15 downto 0) := x"0000";
+
+
+-------------------------------------------------------------------------------
+-- Control registers
+-------------------------------------------------------------------------------
+    ep_ctrl_i           : in std_logic :='1';
+    regs_i : in t_ep_out_registers;
+    regs_o : out t_ep_in_registers;
+    dbg_o          : out std_logic_vector(33 downto 0)
+    );
+
+
+end ep_tx_path;
+
+architecture rtl of ep_tx_path is
+
+  type t_fab_pipe is array(integer range <>) of t_ep_internal_fabric;
+
+  signal fab_pipe  : t_fab_pipe(4 downto 0);
+  signal dreq_pipe : std_logic_vector(4 downto 0);
+
+  signal vlan_mem_addr : std_logic_vector(9 downto 0);
+  signal vlan_mem_data : std_logic_vector(17 downto 0);
+  
+  signal txtsu_stb     : std_logic;
+
+  signal inject_req            : std_logic;
+  signal inject_ready          : std_logic;
+  signal inject_packet_sel     : std_logic_vector(2 downto 0);
+  signal inject_user_value     : std_logic_vector(15 downto 0);
+  signal inject_mode           : std_logic_vector( 1 downto 0);
+
+  signal inj_ctr_req            : std_logic;
+  signal inj_ctr_packet_sel     : std_logic_vector(2 downto 0);
+  signal inj_ctr_user_value     : std_logic_vector(15 downto 0);
+  signal inj_ctr_ena            : std_logic;
+  signal inj_ctr_mode           : std_logic_vector( 1 downto 0);
+
+
+begin  -- rtl
+
+  U_Header_Processor : ep_tx_header_processor
+    generic map (
+      g_with_packet_injection => g_with_packet_injection,
+      g_with_timestamper      => g_with_timestamper,
+      g_force_gap_length      => g_force_gap_length,
+      g_runt_padding          => g_runt_padding)
+    port map (
+      clk_sys_i              => clk_sys_i,
+      rst_n_i                => rst_n_i,
+      src_fab_o              => fab_pipe(0),
+      src_dreq_i             => dreq_pipe(0),
+      pcs_busy_i             => pcs_busy_i,
+      pcs_error_i            => pcs_error_i,
+      wb_snk_i               => snk_i,
+      wb_snk_o               => snk_o,
+      fc_pause_req_i         => fc_pause_req_i,
+      fc_pause_delay_i       => fc_pause_delay_i,
+      fc_pause_ready_o       => fc_pause_ready_o,
+      fc_flow_enable_i       => fc_flow_enable_i,
+      txtsu_port_id_o        => txtsu_port_id_o,
+      txtsu_fid_o            => txtsu_fid_o,
+      txtsu_ts_value_o       => txtsu_ts_value_o,
+      txtsu_ts_incorrect_o   => txtsu_ts_incorrect_o,
+      txtsu_stb_o            => txtsu_stb, --txtsu_stb_o,
+      txtsu_ack_i            => txtsu_ack_i,
+      txts_timestamp_i       => txts_timestamp_i,
+      txts_timestamp_valid_i => txts_timestamp_valid_i,
+      ep_ctrl_i              => ep_ctrl_i,
+      regs_i                 => regs_i);
+
+  txtsu_stb_o <= txtsu_stb;
+
+  assert not (g_with_packet_injection and not g_with_vlans)
+    report "wr_endpoint: packet injection requires VLAN support to be enabled" severity failure;
+
+  gen_with_inj_ctrl: if(g_with_inj_ctrl and g_with_packet_injection) generate
+    -- the injector control has two main purposes:
+    -- 1) control ep_tx_packet_injector so that it continuously generatres frames with
+    --    desired interframe gap
+    -- 2) block the possible traffic coming from SWcore 
+    --    - so that it does not disturb generation which is done only between frames from SWcore
+    --    - each frame coming from SWcore is "scanned" by Ethertype in the RAM which is used
+    --      for generation -> if ep_tx_vlan_unit is used (if dev/null was done after this module)
+    --      when ep_tx_packet_injection is used to genrate frame... we have problem cause two
+    --      modules read from the same RAM
+    U_Injector_ctr: ep_tx_inject_ctrl
+      generic map (
+        g_min_if_gap_length   => 5)
+      port map (
+        clk_sys_i             => clk_sys_i,
+        rst_n_i               => rst_n_i,
+        snk_fab_i             => fab_pipe(0),
+        snk_dreq_o            => dreq_pipe(0),
+        src_fab_o             => fab_pipe(1),
+        src_dreq_i            => dreq_pipe(1),
+        inject_req_o          => inj_ctr_req,
+        inject_ready_i        => inject_ready,
+        inject_packet_sel_o   => inj_ctr_packet_sel,
+        inject_user_value_o   => inj_ctr_user_value,
+        inject_ctr_ena_o      => inj_ctr_ena,
+        inject_ctr_mode_o     => inj_ctr_mode,
+        regs_i                => regs_i,
+        regs_o                => regs_o);
+  end generate gen_with_inj_ctrl;
+
+  inject_req        <= inj_ctr_req        when (inj_ctr_ena ='1') else inject_req_i;
+  inject_packet_sel <= inj_ctr_packet_sel when (inj_ctr_ena ='1') else inject_packet_sel_i;
+  inject_ready_o    <= inject_ready;
+
+  gen_without_inj_ctrl: if((not g_with_inj_ctrl) or (not g_with_packet_injection)) generate
+    fab_pipe(1)        <= fab_pipe(0);
+    dreq_pipe(0)       <= dreq_pipe(1);   
+    inj_ctr_req        <= '0';
+    inj_ctr_mode       <= (others => '0');
+    inj_ctr_packet_sel <= (others => '0');
+    inj_ctr_user_value <= (others => '0');
+    inj_ctr_ena        <= '0';
+    regs_o             <= c_ep_in_registers_init_value;
+  end generate gen_without_inj_ctrl;
+
+  gen_with_vlan_unit : if(g_with_vlans) generate
+    U_VLAN_Unit : ep_tx_vlan_unit
+      port map (
+        clk_sys_i         => clk_sys_i,
+        rst_n_i           => rst_n_i,
+        snk_fab_i         => fab_pipe(1),
+        snk_dreq_o        => dreq_pipe(1),
+        src_fab_o         => fab_pipe(2),
+        src_dreq_i        => dreq_pipe(2),
+        inject_mem_addr_i => vlan_mem_addr,
+        inject_mem_data_o => vlan_mem_data,
+        uram_offset_wr_i  => regs_i.vcr1_offset_wr_o,
+        uram_offset_i     => regs_i.vcr1_offset_o,
+        uram_data_i       => regs_i.vcr1_data_o);
+  end generate gen_with_vlan_unit;
+
+  gen_without_vlan_unit : if(not g_with_vlans) generate
+    fab_pipe(2)  <= fab_pipe(1);
+    dreq_pipe(1) <= dreq_pipe(2);
+  end generate gen_without_vlan_unit;
+
+  gen_with_injection : if(g_with_packet_injection) generate
+
+    inject_user_value <= inj_ctr_user_value when (inj_ctr_ena ='1') else inject_user_value_i;
+    inject_mode       <= inj_ctr_mode       when (inj_ctr_ena ='1') else "00";
+
+    U_Injector : ep_tx_packet_injection
+      port map (
+        clk_sys_i           => clk_sys_i,
+        rst_n_i             => rst_n_i,
+        snk_fab_i           => fab_pipe(2),
+        snk_dreq_o          => dreq_pipe(2),
+        src_fab_o           => fab_pipe(3),
+        src_dreq_i          => dreq_pipe(3),
+        inject_req_i        => inject_req,
+        inject_ready_o      => inject_ready,
+        inject_packet_sel_i => inject_packet_sel,
+        inject_user_value_i => inject_user_value,
+        inject_mode_i       => inject_mode,
+        mem_addr_o          => vlan_mem_addr,
+        mem_data_i          => vlan_mem_data);
+  end generate gen_with_injection;
+
+  gen_without_injection : if (not g_with_packet_injection) generate
+    fab_pipe(3)  <= fab_pipe(2);
+    dreq_pipe(2) <= dreq_pipe(3);
+    inject_ready <= '0';
+  end generate gen_without_injection;
+
+  U_Insert_CRC : ep_tx_crc_inserter
+    generic map(
+      g_use_new_crc => g_use_new_crc)
+    port map (
+      clk_sys_i  => clk_sys_i,
+      rst_n_i    => rst_n_i,
+      snk_fab_i  => fab_pipe(3),
+      snk_dreq_o => dreq_pipe(3),
+      src_fab_o  => fab_pipe(4),
+      src_dreq_i => dreq_pipe(4),
+      dbg_o      => dbg_o(33 downto 31));
+
+  pcs_fab_o    <= fab_pipe(4);
+  dreq_pipe(4) <= pcs_dreq_i;
+
+--   GEN_DBG: for i in 0 to 3 generate
+--     dbg_o(i)    <= fab_pipe(i).sof;
+--     dbg_o(i+4)  <= fab_pipe(i).eof;
+--   end generate GEN_DBG;
+
+    dbg_o(0)    <= fab_pipe(0).sof;             -- 64
+    dbg_o(1)    <= fab_pipe(2).sof;             -- 65
+    dbg_o(2)    <= fab_pipe(3).sof;             -- 66
+    dbg_o(3)    <= fab_pipe(4).sof;             -- 67
+    dbg_o(4)    <= fab_pipe(0).eof;             -- 68
+    dbg_o(5)    <= fab_pipe(2).eof;             -- 69
+    dbg_o(6)    <= fab_pipe(3).eof;             -- 70
+    dbg_o(7)    <= fab_pipe(4).eof;             -- 71
+
+    dbg_o(8)    <= dreq_pipe(0);                -- 72
+    dbg_o(9)    <= dreq_pipe(2);                -- 73
+    dbg_o(10)   <= dreq_pipe(3);                -- 74 
+    dbg_o(11)   <= fab_pipe(0).dvalid;          -- 75
+    dbg_o(12)   <= fab_pipe(4).dvalid;          -- 32
+    -- new 4 bits
+    dbg_o(13)   <= dreq_pipe(4);                -- 33
+    dbg_o(14)   <= txtsu_stb;                   -- 34
+    dbg_o(15)   <= txtsu_ack_i;                 -- 35
+    dbg_o(16)   <= fab_pipe(2).dvalid;          -- 36
+--     dbg_o(28 downto 13) <= fab_pipe(2).data;
+    dbg_o(17)   <= inj_ctr_req;                 -- 37    
+    dbg_o(18)   <= inject_req;                  -- 38
+    dbg_o(19)   <= inject_ready;                -- 39                inj_ctr_user_value;
+    dbg_o(20)   <= inj_ctr_ena;                 -- 40
+    dbg_o(23 downto 21) <= inject_packet_sel;   -- 41-43
+    dbg_o(24)   <= inject_req_i;                -- 43
+    dbg_o(28 downto 25) <= fab_pipe(3).data(3 downto 0);
+--     dbg_o(28 downto 17) <= fab_pipe(3).data(11 downto 0);
+    dbg_o(30 downto 29) <= fab_pipe(3).addr;
+    
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_pcs_16bit.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_pcs_16bit.vhd
new file mode 100644
index 000000000..0bc801ee2
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_pcs_16bit.vhd
@@ -0,0 +1,546 @@
+-------------------------------------------------------------------------------
+-- Title      : 16-bit transmit path for 1000Base-X PCS
+-- Project    : White Rabbit MAC/Endpoint
+-------------------------------------------------------------------------------
+-- File       : ep_tx_pcs_16bit.vhd
+-- Author     : Tomasz Włostowski
+-- Company    : CERN BE-CO-HT section
+-- Created    : 2009-06-16
+-- Last update: 2017-02-20
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Module implements a 16-bit transmit path for 802.3z 1000BaseX PCS.
+-- This block interfaces the Ethernet framer to TX PMA (Physical Medium Attachment).
+-- It performs preamble generation, insertion of idle patterns, all the low-level
+-- signalling. Strobing signal for taking TX timestamps is also generated.
+--
+-- Module uses two separate clocks: 62.5 MHz phy_tx_clk_i
+-- (Transmit clock for PHY) which clocks 8b10b signalling layer, and an async
+-- (clk_sys_i) which is used for data exchange with the rest of MAC data path. Data
+-- exchange between these clock domains is done using an async FIFO.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2011-2017 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author   Description
+-- 2011-10-15  0.2      twlostow 16-bit version for Virtex 6 GTX
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.gencores_pkg.all;
+use work.genram_pkg.all;
+use work.endpoint_private_pkg.all;
+use work.endpoint_pkg.all;
+
+
+entity ep_tx_pcs_16bit is
+
+  port (
+-- reset (synchronous to clk_sys_i, active LO)
+    rst_n_i : in std_logic;
+
+-- system clock (faster than reference)
+    clk_sys_i : in std_logic;
+
+-- reset (phy_tx_clk_i sync)
+    rst_txclk_n_i : in std_logic;
+
+-------------------------------------------------------------------------------
+-- TX Framer inteface
+-------------------------------------------------------------------------------    
+
+-- TX Fabric input
+    pcs_fab_i : in t_ep_internal_fabric;
+
+-- HI pulse indicates an error during transmission of a frame (buffer underrun)
+    pcs_error_o : out std_logic;
+
+-- HI indicates that the PCS is busy (transmitting a frame or during autonegotiation)
+    pcs_busy_o : out std_logic;
+
+-- HI indicates that PCS FIFO is almost full.
+    pcs_dreq_o : out std_logic;
+
+-------------------------------------------------------------------------------
+-- WB controller control signals
+-------------------------------------------------------------------------------
+
+    mdio_mcr_reset_i      : in std_logic;
+-- Transmit Control Register, EN_PCS field
+    mdio_mcr_pdown_i      : in std_logic;
+-- Transmit Control Register, TX_CAL field
+    mdio_wr_spec_tx_cal_i : in std_logic;
+
+-- autonegotiation control
+    an_tx_en_i  : in std_logic;
+    an_tx_val_i : in std_logic_vector(15 downto 0);
+
+-- Timestamp strobe
+    timestamp_trigger_p_a_o : out std_logic;
+
+-- RMON events
+    rmon_tx_underrun : out std_logic;
+
+-------------------------------------------------------------------------------
+-- PHY Interface
+-------------------------------------------------------------------------------
+
+    phy_tx_clk_i       : in  std_logic;
+    phy_tx_data_o      : out std_logic_vector(15 downto 0);
+    phy_tx_k_o         : out std_logic_vector(1 downto 0);
+    phy_tx_disparity_i : in  std_logic;
+    phy_tx_enc_err_i   : in  std_logic;
+    
+    dbg_wr_count_o     : out std_logic_vector(5+4 downto 0);
+    dbg_rd_count_o     : out std_logic_vector(5+4 downto 0)
+    );
+
+end ep_tx_pcs_16bit;
+
+
+architecture behavioral of ep_tx_pcs_16bit is
+
+-- TX state machine definitions
+  type t_tbif_tx_state is (TX_COMMA_IDLE, TX_CAL, TX_CR12, TX_CR34, TX_SPD_PREAMBLE, TX_DATA, TX_PREAMBLE, TX_SFD, TX_EPD, TX_EXTEND, TX_GEN_ERROR);
+
+-- TX state machine signals
+
+  signal tx_is_k            : std_logic_vector(1 downto 0);
+  signal tx_odata_reg       : std_logic_vector(15 downto 0);
+  signal tx_catch_disparity : std_logic;
+  signal tx_state           : t_tbif_tx_state;
+  signal tx_cntr            : unsigned(3 downto 0);
+  signal tx_cr_alternate    : std_logic;
+
+-- TX clock alignment FIFO signals
+  signal fifo_packed_in, fifo_packed_out : std_logic_vector(17 downto 0);
+  signal fifo_empty                      : std_logic;
+  signal fifo_almost_empty               : std_logic;
+  signal fifo_almost_full                : std_logic;
+  signal fifo_enough_data                : std_logic;
+  signal fifo_wr                         : std_logic;
+  signal fifo_rd                         : std_logic := '0';
+  signal fifo_ready                      : std_logic;
+  signal fifo_clear_n, fifo_clear_n_d0, fifo_clear_n_d1, fifo_clear_n_d2, fifo_clear_n_d3, fifo_clear_n_d4 : std_logic;
+  signal fifo_read_int                   : std_logic;
+  signal fifo_fab                        : t_ep_internal_fabric;
+
+  signal tx_busy  : std_logic;
+  signal tx_error : std_logic;
+  signal rst_n_tx : std_logic;
+
+  signal mdio_mcr_reset_synced : std_logic;
+  signal mdio_mcr_pdown_synced : std_logic;
+
+  signal an_tx_en_synced : std_logic;
+  signal wr_count       :  std_logic_vector(6 downto 0);
+  signal rd_count       :  std_logic_vector(6 downto 0);
+  
+  constant tx_interframe_gap: unsigned(3 downto 0) := x"2"; --ML changed from "1000" to 0010
+  -- effectively it is 6 cycles for IFG:
+  -- last data (CRC) of the previous frame
+  -- -----------------------------------------
+  -- 3 cycles for count down (2 downto 0)
+  -- 1 cycle fifo_rd
+  -- 1 read SOF from FIFO
+  -- 1 cycle in TX_SPD_PREAMBLE
+  -- -----------------------------------------
+  -- just now we send Preamble
+  -- 
+begin
+
+  U_sync_pcs_busy_o : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_sys_i,
+      rst_n_i  => rst_n_i,
+      data_i   => tx_busy,
+      synced_o => pcs_busy_o);
+
+  U_sync_pcs_error_o : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_sys_i,
+      rst_n_i  => rst_n_i,
+      data_i   => tx_error,
+      ppulse_o => pcs_error_o);
+
+  U_sync_an_tx_en : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => phy_tx_clk_i,
+      rst_n_i  => rst_n_i,
+      data_i   => an_tx_en_i,
+      synced_o => an_tx_en_synced);
+
+  U_sync_mcr_reset : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => phy_tx_clk_i,
+      rst_n_i  => '1',
+      data_i   => mdio_mcr_reset_i,
+      synced_o => mdio_mcr_reset_synced,
+      npulse_o => open,
+      ppulse_o => open);
+
+  U_sync_power_down : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => phy_tx_clk_i,
+      rst_n_i  => '1',
+      data_i   => mdio_mcr_pdown_i,
+      synced_o => mdio_mcr_pdown_synced);
+
+  phy_tx_data_o <= tx_odata_reg;
+  phy_tx_k_o    <= tx_is_k;
+
+  rst_n_tx <= rst_txclk_n_i and not mdio_mcr_reset_synced;
+
+-------------------------------------------------------------------------------
+-- Clock alignment FIFO
+-------------------------------------------------------------------------------  
+
+
+ -------------------------------------------------------------------------------------------
+ -- some hacks to make pdown (in particular killing the link) work with Xilix native FIFOs
+ -- (the rst signal can be set (LOW) only after 4 cycles after rd_i is "unset" (LOW)
+ -------------------------------------------------------------------------------------------
+ fifo_clear_n_d0 <= '0' when (rst_n_i = '0') or (mdio_mcr_pdown_synced = '1') else '1';
+ p_fifo_clean : process(phy_tx_clk_i)
+  begin
+    if rising_edge(phy_tx_clk_i) then
+      fifo_clear_n_d1 <= fifo_clear_n_d0;
+      fifo_clear_n_d2 <= fifo_clear_n_d1;
+      fifo_clear_n_d3 <= fifo_clear_n_d2;
+      fifo_clear_n_d4 <= fifo_clear_n_d3;
+     end if;
+  end process;
+
+  fifo_clear_n <= fifo_clear_n_d4 when (fifo_clear_n_d0 = '0') else
+                  fifo_clear_n_d0;
+  fifo_read_int <= fifo_rd and not (fifo_fab.eof or fifo_fab.error or fifo_fab.sof) and
+                   fifo_clear_n_d0;
+  -------------------------------------------------------------------------------------------
+  f_pack_fifo_contents(pcs_fab_i, fifo_packed_in, fifo_wr, true);
+
+
+
+  U_TX_FIFO : generic_async_fifo
+    generic map (
+      g_data_width             => 18,
+      g_size                   => 128,--64,
+      g_with_rd_empty          => true,
+      g_with_rd_almost_empty   => true,
+      g_with_wr_almost_full    => true,
+      g_almost_empty_threshold => 20, -- must be not more/equal then mini-frame size (so 64/2), 
+                                      -- therwise frames get stuck in PCS 40,
+
+      -- ML this is a hack: we have a problem, the native FIFO that was used here
+      --    is not working ocrrectly (probably something with full/empty/etc signals
+      --    If this flags here are defined, another fifo (v6_hwfifo) is used, it is
+      --    not the best for resources... but works. We tried increaseing the size
+      --    of the FIFO, changing thresholds... not works very well. 
+      --    The native FIFO works somehow better with the following parameters
+      --        g_size = 1000
+      --        g_almost_full_threshold = 900
+      --     but it is still not good enough to use it
+      --     
+      g_with_rd_count          => true, -- ML debug
+      g_with_wr_count          => true, -- ML debug
+      
+      g_almost_full_threshold  => 100) -- fixme: make this a generic (or WB register)
+    port map (
+      rst_n_i           => fifo_clear_n,
+      clk_wr_i          => clk_sys_i,
+      d_i               => fifo_packed_in,
+      we_i              => fifo_wr,
+      wr_empty_o        => dbg_wr_count_o(0), --open,
+      wr_full_o         => dbg_wr_count_o(1), --open,
+      wr_almost_empty_o => dbg_wr_count_o(2), --open,
+      wr_almost_full_o  => fifo_almost_full,
+      wr_count_o        => wr_count,
+      clk_rd_i          => phy_tx_clk_i,
+      q_o               => fifo_packed_out,
+      rd_i              => fifo_read_int,
+      rd_empty_o        => fifo_empty,
+      rd_full_o         => dbg_rd_count_o(1) ,--open,
+      rd_almost_empty_o => fifo_almost_empty,
+      rd_almost_full_o  => dbg_rd_count_o(3),
+      rd_count_o        => rd_count); --rd_count);--dbg_rd_count_o); --open);
+
+      dbg_wr_count_o(3) <= fifo_almost_full;
+      dbg_rd_count_o(0) <= fifo_empty;
+      dbg_rd_count_o(2) <= fifo_almost_empty;
+      
+      dbg_wr_count_o(9 downto 4) <= wr_count(5 downto 0);
+      dbg_rd_count_o(9 downto 4) <= rd_count(5 downto 0);
+
+  fifo_enough_data <= not fifo_almost_empty;
+
+  p_gen_fifo_ready_flag : process(phy_tx_clk_i)
+  begin
+    if rising_edge(phy_tx_clk_i) then
+      fifo_ready <= fifo_read_int;
+    end if;
+  end process;
+
+  f_unpack_fifo_contents(fifo_packed_out, fifo_ready, fifo_fab, true);
+
+  -----------------------------------------------------------------------------
+  -- TX PCS state machine
+  -----------------------------------------------------------------------------
+  p_tx_fsm : process (phy_tx_clk_i)
+  begin
+    
+    if rising_edge(phy_tx_clk_i) then
+
+-- The PCS is reset or disabled
+      if(rst_n_tx = '0' or mdio_mcr_pdown_synced = '1') then
+        tx_state                <= TX_COMMA_IDLE;
+        timestamp_trigger_p_a_o <= '0';
+        fifo_rd                 <= '0';
+        tx_error                <= '0';
+        tx_odata_reg            <= (others => '0');
+        tx_is_k                 <= "00";
+        tx_cr_alternate         <= '0';
+        tx_catch_disparity      <= '0';
+        tx_cntr                 <= (others => '0');
+        rmon_tx_underrun        <= '0';
+      else
+        case tx_state is
+-------------------------------------------------------------------------------
+-- State COMMA: sends the /I/ sequence (K28.5 + D5.6/D16.2)
+-------------------------------------------------------------------------------            
+          when TX_COMMA_IDLE =>
+
+            -- clear the RMON/error pulse after 2 cycles (DATA->COMMA->IDLE) to
+            -- make sure is't long enough to trigger the event counter
+            rmon_tx_underrun <= '0';
+            tx_error         <= '0';
+
+            tx_is_k                   <= "10";
+            tx_odata_reg(15 downto 8) <= c_K28_5;
+
+            if (phy_tx_disparity_i = '1' and tx_catch_disparity = '1') then
+              tx_odata_reg(7 downto 0) <= c_d5_6;
+            else
+              tx_odata_reg(7 downto 0) <= c_d16_2;
+            end if;
+
+
+-- endpoint wants to send Config_Reg
+            if(an_tx_en_synced = '1') then
+              tx_state        <= TX_CR12;
+              tx_cr_alternate <= '0';
+              fifo_rd         <= '0';
+
+-- we've got a new frame in the FIFO
+            elsif (fifo_fab.sof = '1' and fifo_ready = '1' and tx_cntr = "0000")then
+              fifo_rd  <= '0';
+              tx_state <= TX_SPD_PREAMBLE;
+              tx_cntr  <= "0001";
+
+-- host requested a calibration pattern
+            elsif(mdio_wr_spec_tx_cal_i = '1') then
+              tx_state        <= TX_CAL;
+              fifo_rd         <= '0';
+              tx_cr_alternate <= '0';
+            else
+-- continue sending idle sequences and checking if something has arrived in the
+-- FIFO
+              if(tx_cntr /= "0000") then
+                fifo_rd <= '0';
+              else
+                fifo_rd <= (not fifo_empty) and fifo_enough_data;
+              end if;
+              tx_state <= TX_COMMA_IDLE;
+            end if;
+
+            tx_catch_disparity <= '0';
+
+            if(tx_cntr /= "0000") then
+              tx_cntr <= tx_cntr - 1;
+            end if;
+-------------------------------------------------------------------------------
+-- State: CAL: transmit the calibration sequence
+-------------------------------------------------------------------------------
+
+          when TX_CAL =>
+            tx_is_k         <= "11";
+            tx_odata_reg    <= c_k28_7 & c_k28_7;
+            tx_cr_alternate <= '1';
+            if(mdio_wr_spec_tx_cal_i = '0' and tx_cr_alternate = '1') then
+              tx_state <= TX_COMMA_IDLE;
+            end if;
+
+-------------------------------------------------------------------------------
+-- States: CR1, CR2, CR3, CR4: send the /C/ Configuration code set
+-------------------------------------------------------------------------------
+
+          when TX_CR12 =>
+            fifo_rd <= not fifo_empty;
+
+            tx_is_k                   <= "10";
+            tx_odata_reg(15 downto 8) <= c_k28_5;
+
+            if (tx_cr_alternate = '1') then
+              tx_odata_reg(7 downto 0) <= c_d21_5;
+            else
+              tx_odata_reg(7 downto 0) <= c_d2_2;
+            end if;
+
+            tx_cr_alternate <= not tx_cr_alternate;
+            tx_state        <= TX_CR34;
+
+          when TX_CR34 =>
+            fifo_rd <= not fifo_empty;
+
+            tx_is_k                   <= "00";
+            tx_odata_reg(15 downto 8) <= an_tx_val_i(7 downto 0);
+            tx_odata_reg(7 downto 0)  <= an_tx_val_i(15 downto 8);
+
+            if(an_tx_en_synced = '1') then
+              tx_state <= TX_CR12;
+            else
+              tx_state <= TX_COMMA_IDLE;
+            end if;
+
+
+-------------------------------------------------------------------------------
+-- State SPD: sends a start-of-packet delimeter
+-------------------------------------------------------------------------------
+          when TX_SPD_PREAMBLE =>
+            fifo_rd      <= '0';
+            tx_is_k      <= "10";
+            tx_odata_reg <= c_k27_7 & c_preamble_char;
+            tx_state     <= TX_PREAMBLE;
+
+-------------------------------------------------------------------------------
+-- State PREAMBLE: produces an Ethernet preamble
+-------------------------------------------------------------------------------
+          when TX_PREAMBLE =>
+            tx_is_k      <= "00";
+            tx_odata_reg <= c_preamble_char & c_preamble_char;
+
+            if (tx_cntr = "0000") then
+              tx_state <= TX_SFD;
+              fifo_rd  <= '1';
+            end if;
+
+            tx_cntr <= tx_cntr - 1;
+
+-------------------------------------------------------------------------------
+-- State SFD: outputs the start-of-frame delimeter (last byte of the preamble)
+-------------------------------------------------------------------------------            
+          when TX_SFD =>
+            tx_is_k                 <= "00";
+            tx_odata_reg            <= c_preamble_char & c_preamble_sfd;
+            timestamp_trigger_p_a_o <= '1';
+            tx_state                <= TX_DATA;
+
+          when TX_DATA =>
+
+            if((fifo_empty = '1' or fifo_fab.error = '1') and fifo_fab.eof = '0') then  -- FIFO underrun?
+              tx_odata_reg     <= c_k30_7 & c_k23_7;  -- emit error propagation code
+              tx_is_k          <= "11";
+              tx_state         <= TX_GEN_ERROR;
+              tx_error         <= not fifo_fab.error;
+              rmon_tx_underrun <= '1';
+              fifo_rd          <= '0';
+            else
+
+              if(fifo_fab.bytesel = '1') then
+                tx_odata_reg <= fifo_fab.DATA(15 downto 8) & c_k29_7;
+                tx_is_k      <= "01";
+              else
+                tx_odata_reg <= fifo_fab.DATA;
+                tx_is_k      <= "00";
+              end if;
+
+              if (fifo_fab.eof = '1') then
+                if(fifo_fab.bytesel = '1') then
+                  tx_state <= TX_EXTEND;
+                else
+                  tx_state <= TX_EPD;
+                end if;
+                fifo_rd <= '0';
+              end if;
+            end if;
+
+-------------------------------------------------------------------------------
+-- State EPD: send End-of-frame delimeter
+-------------------------------------------------------------------------------
+          when TX_EPD =>
+            timestamp_trigger_p_a_o <= '0';
+            tx_is_k                 <= "11";
+            tx_odata_reg            <= c_k29_7 & c_k23_7;
+            tx_catch_disparity      <= '1';
+            tx_cntr                 <= tx_interframe_gap;
+            tx_state                <= TX_COMMA_IDLE;
+
+--------------------------------------------------------------------------------
+-- State EXTEND: send the carrier extension
+-------------------------------------------------------------------------------
+          when TX_EXTEND =>
+            timestamp_trigger_p_a_o <= '0';
+            tx_is_k                 <= "11";
+            tx_odata_reg            <= c_k23_7 & c_k23_7;
+            tx_catch_disparity      <= '1';
+            tx_cntr                 <= tx_interframe_gap-1;--"0100";
+            tx_state                <= TX_COMMA_IDLE;
+
+-------------------------------------------------------------------------------
+-- State GEN_ERROR: entered when an error occured. Just terminates the frame.
+-------------------------------------------------------------------------------            
+          when TX_GEN_ERROR =>
+            tx_state <= TX_EPD;
+
+        end case;
+      end if;
+    end if;
+  end process;
+
+  process(phy_tx_clk_i)
+  begin
+    if rising_edge(phy_tx_clk_i) then
+      if fifo_empty = '0' or (tx_state /= TX_CR12 and tx_state /= TX_CR34 and tx_state /= TX_COMMA_IDLE) then
+        tx_busy <= '1';
+      else
+        tx_busy <= '0';
+      end if;
+    end if;
+  end process;
+
+  pcs_dreq_o <= not fifo_almost_full;
+  
+end behavioral;
+
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_pcs_8bit.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_pcs_8bit.vhd
new file mode 100644
index 000000000..db19a419a
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_pcs_8bit.vhd
@@ -0,0 +1,514 @@
+-------------------------------------------------------------------------------
+-- Title      : 1000BaseT/X MAC Endpoint - receive path PCS for 1000BaseX
+-- Project    : White Rabbit Switch
+-------------------------------------------------------------------------------
+-- File       : ep_tx_pcs_tbi.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2009-06-16
+-- Last update: 2017-02-20
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Module implements the transmit path for 802.3z 1000BaseX PCS.
+-- This block interfaces the Ethernet framer to TX PMA (Physical Medium Attachment).
+-- It performs preamble generation, insertion of idle patterns, all the low-level
+-- signalling (including 8b10b coding). Strobing signal for taking TX timestamps
+-- is also generated.
+--
+-- Module uses two separate clocks: 125 MHz tbi_tx_clk (or gtp_tx_clk)
+-- (Transmit clock for PHY) which clocks 8b10b signalling layer, and 62.5 MHz
+-- (clk_sys_i) which is used for data exchange with the rest of switch. Data
+-- exchange between these clock domains  is done using an async FIFO.
+--
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2009-2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author   Description
+-- 2009-06-16  0.1      twlostow Created (no error propagation supported yet)
+-- 2010-04-06  0.2      twlostow Cleanup, new timestamping/LCR scheme
+-- 2010-07-30  0.2      twlostow Fixed preamble length bug
+-- 2010-11-18  0.4      twlostow Added support for Xilinx GTP transceivers.
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+library work;
+use work.gencores_pkg.all;
+use work.genram_pkg.all;
+use work.endpoint_private_pkg.all;
+use work.endpoint_pkg.all;
+
+
+entity ep_tx_pcs_8bit is
+
+  port (
+-- reset (synchronous to refclk2, active LO)
+    rst_n_i : in std_logic;
+
+-- 62.5 MHz clock (refclk/2)
+    clk_sys_i : in std_logic;
+
+-- reset (phy_tx_clk_i sync)
+    rst_txclk_n_i : in std_logic;
+
+-------------------------------------------------------------------------------
+-- TX Framer inteface
+-------------------------------------------------------------------------------
+
+-- TX Fabric input
+    pcs_fab_i : in t_ep_internal_fabric;
+
+-- HI pulse indicates an error during transmission of a frame (buffer underrun)
+    pcs_error_o : out std_logic;
+
+-- HI indicates that the PCS is busy (transmitting a frame or during autonegotiation)
+    pcs_busy_o : out std_logic;
+
+-- HI indicates that PCS FIFO is almost full.
+    pcs_dreq_o : out std_logic;
+
+-------------------------------------------------------------------------------
+-- WB controller control signals
+-------------------------------------------------------------------------------
+
+    mdio_mcr_reset_i      : in std_logic;
+-- Transmit Control Register, EN_PCS field
+    mdio_mcr_pdown_i      : in std_logic;
+-- Transmit Control Register, TX_CAL field
+    mdio_wr_spec_tx_cal_i : in std_logic;
+
+-- autonegotiation control
+    an_tx_en_i  : in std_logic;
+    an_tx_val_i : in std_logic_vector(15 downto 0);
+
+-- Timestamp strobe
+    timestamp_trigger_p_a_o : out std_logic;
+
+-- RMON events
+    rmon_tx_underrun : out std_logic;
+
+-------------------------------------------------------------------------------
+-- PHY Interface
+-------------------------------------------------------------------------------
+
+    phy_tx_clk_i       : in  std_logic;
+    phy_tx_data_o      : out std_logic_vector(7 downto 0);
+    phy_tx_k_o         : out std_logic;
+    phy_tx_disparity_i : in  std_logic;
+    phy_tx_enc_err_i   : in  std_logic
+    );
+
+end ep_tx_pcs_8bit;
+
+
+architecture behavioral of ep_tx_pcs_8bit is
+
+-- TX state machine definitions
+  type t_tbif_tx_state is (TX_COMMA, TX_CAL, TX_CR1, TX_CR2, TX_CR3, TX_CR4, TX_SPD, TX_IDLE, TX_DATA, TX_PREAMBLE, TX_SFD, TX_EPD, TX_EXTEND, TX_GOTO_COMMA, TX_GEN_ERROR);
+
+-- TX state machine signals
+
+  signal tx_is_k            : std_logic;
+  signal tx_catch_disparity : std_logic;
+  signal tx_odata_reg       : std_logic_vector(7 downto 0);
+  signal tx_state           : t_tbif_tx_state;
+  signal tx_cntr            : unsigned(3 downto 0);
+  signal tx_cr_alternate    : std_logic;
+
+-- TX clock alignment FIFO signals
+  signal fifo_packed_in, fifo_packed_out : std_logic_vector(17 downto 0);
+  signal fifo_empty                      : std_logic;
+  signal fifo_almost_empty               : std_logic;
+  signal fifo_almost_full                : std_logic;
+  signal fifo_enough_data                : std_logic;
+  signal fifo_wr                         : std_logic;
+  signal fifo_rd                         : std_logic;
+  signal fifo_ready                      : std_logic;
+  signal fifo_clear_n                    : std_logic;
+  signal fifo_fab                        : t_ep_internal_fabric;
+
+  signal tx_rdreq_toggle : std_logic;
+  signal tx_odd_length   : std_logic;
+
+  signal tx_busy  : std_logic;
+  signal tx_error : std_logic;
+  signal rst_n_tx : std_logic;
+
+  signal mdio_mcr_reset_synced : std_logic;
+  signal mdio_mcr_pdown_synced : std_logic;
+  signal an_tx_en_synced       : std_logic;
+
+begin
+
+  U_sync_pcs_busy_o : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_sys_i,
+      rst_n_i  => rst_n_i,
+      data_i   => tx_busy,
+      synced_o => pcs_busy_o);
+
+  U_sync_pcs_error_o : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_sys_i,
+      rst_n_i  => rst_n_i,
+      data_i   => tx_error,
+      ppulse_o => pcs_error_o);
+
+  U_sync_an_tx_en : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => phy_tx_clk_i,
+      rst_n_i  => '1',
+      data_i   => an_tx_en_i,
+      synced_o => an_tx_en_synced);
+
+  U_sync_mcr_reset : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => phy_tx_clk_i,
+      rst_n_i  => '1',
+      data_i   => mdio_mcr_reset_i,
+      synced_o => mdio_mcr_reset_synced,
+      npulse_o => open,
+      ppulse_o => open);
+
+  U_sync_power_down : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => phy_tx_clk_i,
+      rst_n_i  => '1',
+      data_i   => mdio_mcr_pdown_i,
+      synced_o => mdio_mcr_pdown_synced);
+
+  phy_tx_data_o <= tx_odata_reg;
+  phy_tx_k_o    <= tx_is_k;
+
+  rst_n_tx <= rst_txclk_n_i and not mdio_mcr_reset_synced;
+
+-------------------------------------------------------------------------------
+-- Clock alignment FIFO
+-------------------------------------------------------------------------------
+
+  fifo_clear_n <= '0' when (rst_n_i = '0') or (mdio_mcr_pdown_synced = '1') else '1';
+
+  f_pack_fifo_contents(pcs_fab_i, fifo_packed_in, fifo_wr, true);
+
+  U_TX_FIFO : generic_async_fifo
+    generic map (
+      g_data_width             => 18,
+      g_size                   => 64,
+      g_with_rd_empty          => true,
+      g_with_rd_almost_empty   => true,
+      g_with_rd_count          => true,
+      g_with_wr_almost_full    => true,
+      g_almost_empty_threshold => 16,
+      g_almost_full_threshold  => 56)  -- fixme: make this a generic (or WB register)
+    port map (
+      rst_n_i           => fifo_clear_n,
+      clk_wr_i          => clk_sys_i,
+      d_i               => fifo_packed_in,
+      we_i              => fifo_wr,
+      wr_empty_o        => open,
+      wr_full_o         => open,
+      wr_almost_empty_o => open,
+      wr_almost_full_o  => fifo_almost_full,
+      wr_count_o        => open,
+      clk_rd_i          => phy_tx_clk_i,
+      q_o               => fifo_packed_out,
+      rd_i              => fifo_rd,
+      rd_empty_o        => fifo_empty,
+      rd_full_o         => open,
+      rd_almost_empty_o => fifo_almost_empty,
+      rd_almost_full_o  => open,
+      rd_count_o        => open);
+
+  fifo_enough_data <= not fifo_almost_empty;
+
+  f_unpack_fifo_contents(fifo_packed_out, '1', fifo_fab, true);
+
+  -----------------------------------------------------------------------------
+  -- TX PCS state machine
+  -----------------------------------------------------------------------------
+
+  p_tx_fsm : process (phy_tx_clk_i)
+  begin
+
+    if rising_edge(phy_tx_clk_i) then
+
+-- The PCS is reset or disabled
+      if(rst_n_tx = '0' or mdio_mcr_pdown_synced = '1') then
+        tx_state                <= TX_COMMA;
+        timestamp_trigger_p_a_o <= '0';
+        fifo_rd                 <= '0';
+        tx_error                <= '0';
+        tx_odata_reg            <= (others => '0');
+        tx_is_k                 <= '0';
+        tx_cr_alternate         <= '0';
+        tx_catch_disparity      <= '0';
+        tx_cntr                 <= (others => '0');
+        tx_odd_length           <= '0';
+        tx_rdreq_toggle         <= '0';
+        rmon_tx_underrun        <= '0';
+
+      else
+
+        case tx_state is
+
+-------------------------------------------------------------------------------
+-- State COMMA: sends K28.5 comma character (first byte of /I/ sequence)
+-------------------------------------------------------------------------------
+          when TX_COMMA =>
+            tx_is_k      <= '1';
+            tx_odata_reg <= c_K28_5;
+            tx_state     <= TX_IDLE;
+            fifo_rd      <= '0';
+            fifo_ready   <= fifo_rd;
+
+-------------------------------------------------------------------------------
+-- State IDLE: sends the second code of the /I/ sequence with proper disparity\
+-------------------------------------------------------------------------------
+          when TX_IDLE =>
+
+            -- clear the RMON/error pulse after 2 cycles (DATA->COMMA->IDLE) to
+            -- make sure is't long enough to trigger the event counter
+            rmon_tx_underrun <= '0';
+            tx_error         <= '0';
+
+-- endpoint wants to send Config_Reg
+            if(an_tx_en_synced = '1') then
+              tx_state        <= TX_CR1;
+              tx_cr_alternate <= '0';
+              fifo_rd         <= '0';
+
+-- we've got a new frame in the FIFO
+            elsif (fifo_fab.sof = '1' and fifo_ready = '1' and tx_cntr = "0000")then
+              fifo_rd  <= '1';
+              tx_state <= TX_SPD;
+              tx_cntr  <= "0101";
+
+-- host requested a calibration pattern
+            elsif(mdio_wr_spec_tx_cal_i = '1') then
+              tx_state        <= TX_CAL;
+              fifo_rd         <= '0';
+              tx_cr_alternate <= '0';
+            else
+-- continue sending idle sequences and checking if something has arrived in the
+-- FIFO
+              if(tx_cntr /= "0000") then
+                fifo_rd <= '0';
+              else
+                fifo_rd <= (not fifo_empty) and fifo_enough_data;
+              end if;
+              tx_state <= TX_COMMA;
+            end if;
+
+            tx_is_k <= '0';
+
+-- check the disparity of the previously emitted code and choose whether to send
+-- /I1/ or /I2/
+            if (phy_tx_disparity_i = '1' and tx_catch_disparity = '1') then
+              tx_odata_reg <= c_d5_6;
+            else
+              tx_odata_reg <= c_d16_2;
+            end if;
+
+            tx_catch_disparity <= '0';
+
+            if(tx_cntr /= "0000") then
+              tx_cntr <= tx_cntr - 1;
+            end if;
+-------------------------------------------------------------------------------
+-- State: CAL: transmit the calibration sequence
+-------------------------------------------------------------------------------
+
+          when TX_CAL =>
+            tx_odata_reg <= c_k28_7;
+            tx_is_k      <= '1';
+            if(mdio_wr_spec_tx_cal_i = '0' and tx_cr_alternate = '1') then
+              tx_state <= TX_COMMA;
+            end if;
+
+            tx_cr_alternate <= not tx_cr_alternate;
+
+-------------------------------------------------------------------------------
+-- States: CR1, CR2, CR3, CR4: send the /C/ Configuration code set
+-------------------------------------------------------------------------------
+
+          when TX_CR1 =>
+            tx_is_k      <= '1';
+            tx_odata_reg <= c_k28_5;
+            tx_state     <= TX_CR2;
+
+          when TX_CR2 =>
+            tx_is_k <= '0';
+            if (tx_cr_alternate = '1') then
+              tx_odata_reg <= c_d21_5;
+            else
+              tx_odata_reg <= c_d2_2;
+            end if;
+            tx_cr_alternate <= not tx_cr_alternate;
+            tx_state        <= TX_CR3;
+
+          when TX_CR3 =>
+            tx_odata_reg <= an_tx_val_i(7 downto 0);
+            tx_state     <= TX_CR4;
+
+          when TX_CR4 =>
+            tx_odata_reg <= an_tx_val_i(15 downto 8);
+
+-- check if the autonegotiation control still wants the Config_Reg to be sent
+            if(an_tx_en_synced = '1') then
+              tx_state <= TX_CR1;
+            else
+              tx_state <= TX_COMMA;
+            end if;
+
+-------------------------------------------------------------------------------
+-- State SPD: sends a start-of-packet delimeter
+-------------------------------------------------------------------------------
+          when TX_SPD =>
+            fifo_rd      <= '0';
+            tx_is_k      <= '1';
+            tx_odata_reg <= c_k27_7;
+            tx_state     <= TX_PREAMBLE;
+
+-------------------------------------------------------------------------------
+-- State PREAMBLE: produces an Ethernet preamble
+-------------------------------------------------------------------------------
+          when TX_PREAMBLE =>
+            tx_is_k      <= '0';
+            tx_odata_reg <= c_preamble_char;
+
+            if (tx_cntr = "0000") then
+              tx_state        <= TX_SFD;
+              tx_rdreq_toggle <= '1';
+            end if;
+
+            tx_cntr <= tx_cntr - 1;
+
+
+-------------------------------------------------------------------------------
+-- State SFD: outputs the start-of-frame delimeter (last byte of the preamble)
+-------------------------------------------------------------------------------
+          when TX_SFD =>
+
+            tx_odata_reg            <= c_preamble_sfd;
+            tx_rdreq_toggle         <= '1';
+            tx_state                <= TX_DATA;
+            timestamp_trigger_p_a_o <= '1';
+
+          when TX_DATA =>
+
+
+            -- toggle the TX FIFO request line, so we read a 16-bit word
+            -- every 2 phy_tx_clk_i periods
+
+            fifo_rd <= tx_rdreq_toggle and not (fifo_empty or fifo_fab.eof);
+
+            if((fifo_empty = '1' or fifo_fab.error = '1') and fifo_fab.eof = '0') then  --
+              -- FIFO underrun?
+              tx_odata_reg     <= c_k30_7;  -- emit error propagation code
+              tx_is_k          <= '1';
+              tx_state         <= TX_GEN_ERROR;
+              tx_error         <= not fifo_fab.error;
+              rmon_tx_underrun <= '1';
+            else
+
+              if tx_rdreq_toggle = '1' then  -- send 16-bit word MSB or LSB
+                tx_odata_reg <= fifo_fab.data(15 downto 8);
+              else
+                tx_odata_reg <= fifo_fab.data(7 downto 0);
+              end if;
+
+              tx_rdreq_toggle <= not tx_rdreq_toggle;
+
+              -- handle the end of frame both for even- and odd-length frames
+              tx_odd_length <= fifo_fab.bytesel;
+
+              if (fifo_fab.eof = '1' and (tx_rdreq_toggle = '0' or (tx_rdreq_toggle = '1' and fifo_fab.bytesel = '1'))) then
+                tx_state <= TX_EPD;
+                fifo_rd  <= '0';
+              end if;
+            end if;
+
+-------------------------------------------------------------------------------
+-- State EPD: send End-of-frame delimeter
+-------------------------------------------------------------------------------
+          when TX_EPD =>
+            timestamp_trigger_p_a_o <= '0';
+
+            tx_is_k      <= '1';
+            tx_odata_reg <= c_k29_7;
+            tx_state     <= TX_EXTEND;
+
+--------------------------------------------------------------------------------
+-- State EXTEND: send the carrier extension
+-------------------------------------------------------------------------------
+          when TX_EXTEND =>
+            tx_odata_reg <= c_k23_7;
+            if(tx_odd_length = '0')then
+              tx_state           <= TX_COMMA;
+              tx_catch_disparity <= '1';
+            else
+              tx_odd_length <= '0';
+            end if;
+
+            tx_cntr <= "1000";
+
+-------------------------------------------------------------------------------
+-- State GEN_ERROR: entered when an error occured. Just terminates the frame.
+-------------------------------------------------------------------------------
+          when TX_GEN_ERROR =>
+            tx_state <= TX_EPD;
+
+          when others => null;
+        end case;
+      end if;
+    end if;
+  end process;
+
+  process(phy_tx_clk_i)
+  begin
+    if rising_edge(phy_tx_clk_i) then
+      if fifo_empty = '0' or (tx_state /= TX_IDLE and tx_state /= TX_COMMA) then
+        tx_busy <= '1';
+      else
+        tx_busy <= '0';
+      end if;
+    end if;
+  end process;
+
+  pcs_dreq_o <= not fifo_almost_full;
+
+end behavioral;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_vlan_unit.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_vlan_unit.vhd
new file mode 100644
index 000000000..97e1355ea
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_vlan_unit.vhd
@@ -0,0 +1,305 @@
+-------------------------------------------------------------------------------
+-- Title      : 1000base-X MAC/Endpoint - TX VLAN unit
+-- Project    : White Rabbit
+-------------------------------------------------------------------------------
+-- File       : ep_tx_vlan_unit.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2012-11-01
+-- Last update: 2012-11-16
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Performs VLAN untagging, if the VID of the egress packet is in
+-- the VLAN untagged set.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- FIXME: redo ram split between VLAN/PCK_INJ to use the unused 256 words and
+--        enable storing full-size frame (now max is 1024 bits, if we add 2x256
+--        bytes it will be exactly what we need) -> this requires chagnes in 
+--        HDL+SW+SV 
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2012-11-01  1.0      twlostow	    Created
+-- 2013-04-24  1.1      mlipinsk	    corrected VLAN untagging
+-- 2013-09-02  1.2      mlipinsk	    optimized by 1-cycle
+-- 2014-02-14  1.3      greg.d        Bufixed to use in WRSW NIC
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.gencores_pkg.all;
+use work.genram_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.endpoint_private_pkg.all;
+use work.endpoint_pkg.all;
+use work.ep_wbgen2_pkg.all;
+
+entity ep_tx_vlan_unit is
+
+  port (
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    snk_fab_i  : in  t_ep_internal_fabric;
+    snk_dreq_o : out std_logic;
+
+    src_fab_o  : out t_ep_internal_fabric;
+    src_dreq_i : in  std_logic;
+
+-- Shared buffer interface to the packet injection unit
+    inject_mem_addr_i : in  std_logic_vector(9 downto 0);
+    inject_mem_data_o : out std_logic_vector(17 downto 0);
+
+    uram_offset_wr_i  : in std_logic;
+    uram_offset_i     : in std_logic_vector(9 downto 0);
+    uram_data_i       : in std_logic_vector(17 downto 0)
+    );
+
+
+end ep_tx_vlan_unit;
+
+architecture behavioral of ep_tx_vlan_unit is
+
+
+  type t_state is (IDLE, CHECK_ETHERTYPE, PUSH_QHEADER_1, POP_QHEADER_2, POP_QHEADER_3, POP_ETHERTYPE);
+
+-- general signals
+  signal state   : t_state;
+  signal counter : unsigned(2 downto 0);
+
+  signal vut_rd_vid : std_logic_vector(11 downto 0);
+  signal vut_wr_vid : std_logic_vector(11 downto 0);
+  signal vut_untag, vut_untag_reg  : std_logic;
+
+  signal vut_stored_tag       : std_logic_vector(15 downto 0);
+  signal vut_stored_ethertype : std_logic_vector(15 downto 0);
+  signal flush_ethertype : std_logic;
+  signal flushed         : std_logic;
+
+  signal mem_addr_muxed : std_logic_vector(9 downto 0);
+  signal mem_rdata      : std_logic_vector(17 downto 0);
+  signal src_dreq_d0    : std_logic;
+
+begin  -- behavioral
+
+  vut_rd_vid <= snk_fab_i.data(11 downto 0);
+
+  -- FIXME:
+  -- ML: currently 256 words of the ram are not used and we don't have space to store 
+  --     max size frame (max tempalte is 512x2bytes = 1024 bytes)
+  --     we can use the unused bytes, just that some changes to sw+hw are needed
+  mem_addr_muxed <= ("00" & vut_rd_vid(11 downto 4)) when state /= IDLE else inject_mem_addr_i;
+
+  U_Untagged_Set_RAM : generic_dpram
+    generic map (
+      g_data_width => 18,
+      g_size       => 1024,
+      g_dual_clock => false)
+    port map (
+      rst_n_i => rst_n_i,
+      clka_i  => clk_sys_i,
+      clkb_i  => '0',
+      wea_i   => '0',
+      aa_i    => mem_addr_muxed,
+      qa_o    => mem_rdata,
+      web_i   => uram_offset_wr_i,
+      ab_i    => uram_offset_i,
+      db_i    => uram_data_i);
+
+  inject_mem_data_o <= mem_rdata;
+
+  vut_untag <= mem_rdata(to_integer(unsigned(vut_stored_tag(3 downto 0))));
+
+  p_delay_signals : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      src_dreq_d0 <= src_dreq_i;
+      
+    end if;
+  end process;
+
+  p_main_fsm : process (clk_sys_i)
+  begin  -- process
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        state <= IDLE;
+      else
+        case state is
+          when IDLE =>
+            flushed <= '0';
+            if(snk_fab_i.sof = '1') then
+              counter <= (others => '0');
+            end if;
+            if(snk_fab_i.dvalid = '1' and snk_fab_i.addr = c_WRF_DATA and counter /= 6) then
+              counter <= counter + 1;
+            end if;
+            if(src_dreq_i='1') then
+              flush_ethertype <= '0';
+            end if;
+
+            if(snk_fab_i.dvalid = '1' and counter = 5) then
+              state <= CHECK_ETHERTYPE;
+            end if;
+
+          when CHECK_ETHERTYPE =>
+            vut_stored_ethertype <= snk_fab_i.data;
+
+            if(snk_fab_i.dvalid = '1') then
+
+              if(snk_fab_i.data = x"8100") then
+                state <= PUSH_QHEADER_1;
+              else
+                state <= IDLE;
+              end if;
+            end if;
+
+          when PUSH_QHEADER_1 =>
+            vut_untag_reg <= '0';
+
+            if(snk_fab_i.dvalid = '1') then
+              vut_stored_tag <= snk_fab_i.data;
+              state          <= POP_ETHERTYPE;
+            end if;
+
+          when POP_ETHERTYPE =>
+            if(vut_untag = '1') then
+              vut_untag_reg <= '1';
+            end if;
+            if(snk_fab_i.dvalid = '1') then
+              vut_stored_ethertype <= snk_fab_i.data; 
+            end if;
+            -- if dreq is '1' in POP_ETHERTYPE, that means we have passed
+            -- ethertype to src_fab_o and we don't need to do it after going to
+            -- IDLE.
+            if(src_dreq_d0 = '1') then
+              flush_ethertype <= '0';
+            elsif(src_dreq_i = '0' and flushed = '0') then
+              flush_ethertype <= '1';
+            end if;
+            if(src_dreq_d0 = '1') then
+              flushed <= '1';
+            end if;
+            if( (vut_untag = '1' or vut_untag_reg = '1') and src_dreq_i = '1') then
+              state <= IDLE; 
+            end if;
+            if(vut_untag='0' and vut_untag_reg='0' and src_dreq_d0='1') then
+              state <= POP_QHEADER_2;
+            end if;
+
+          when POP_QHEADER_2 =>
+            if(src_dreq_d0 = '1') then
+              state <= POP_QHEADER_3;
+            end if;
+
+          when POP_QHEADER_3 =>
+            if(src_dreq_d0 = '1') then
+              state <= IDLE;
+            end if;
+
+        end case;
+      end if;
+    end if;
+  end process;
+
+
+--   p_main_fsm_comb : process(snk_fab_i, src_dreq_d0, state, vut_stored_tag, vut_stored_ethertype, counter,vut_untag)
+  p_main_fsm_comb : process(snk_fab_i,src_dreq_i, src_dreq_d0, state, vut_stored_tag, vut_stored_ethertype, counter,vut_untag, flush_ethertype)
+  begin
+
+    case state is
+      when IDLE =>
+        src_fab_o.sof     <= snk_fab_i.sof;
+        src_fab_o.eof     <= snk_fab_i.eof;
+        src_fab_o.error   <= snk_fab_i.error;
+        src_fab_o.bytesel <= snk_fab_i.bytesel;
+      when others =>
+        src_fab_o.sof     <= '0';
+        src_fab_o.eof     <= '0';
+        src_fab_o.error   <= '0';
+        src_fab_o.bytesel <= '0';
+    end case;
+
+    case state is
+      when IDLE =>
+        snk_dreq_o       <= src_dreq_i;
+        -- validate Ethertype from POP_ETHERTYPE state if dreq was high
+        src_fab_o.dvalid <= snk_fab_i.dvalid or flush_ethertype;
+        src_fab_o.addr   <= snk_fab_i.addr;
+        if(flush_ethertype = '1') then
+          src_fab_o.data   <= vut_stored_ethertype;
+        else
+          src_fab_o.data   <= snk_fab_i.data;
+        end if;
+
+      when CHECK_ETHERTYPE =>
+        snk_dreq_o <= src_dreq_i;
+        if(snk_fab_i.data /= x"8100") then
+          src_fab_o.dvalid <= snk_fab_i.dvalid;
+        else
+          src_fab_o.dvalid <= '0';
+        end if;
+        src_fab_o.data <= snk_fab_i.data;
+        src_fab_o.addr <= snk_fab_i.addr;
+        
+      when PUSH_QHEADER_1 =>
+        snk_dreq_o       <= '1';
+        src_fab_o.dvalid <= '0';
+        src_fab_o.data   <= (others => 'X');
+        src_fab_o.addr   <= c_WRF_DATA;
+--       when CHECK_UNTAG =>
+--         snk_dreq_o       <= '0';
+--         src_fab_o.dvalid <= '0';
+--         src_fab_o.data   <= (others => 'X');
+        
+      when POP_ETHERTYPE =>
+        if(vut_untag = '1') then
+          snk_dreq_o       <= src_dreq_i       and src_dreq_d0;
+          src_fab_o.dvalid <= snk_fab_i.dvalid and src_dreq_d0;
+          src_fab_o.data   <= snk_fab_i.data;
+        else
+          src_fab_o.data   <= x"8100";
+          snk_dreq_o       <= '0';
+          src_fab_o.dvalid <= src_dreq_d0;          
+        end if;
+        src_fab_o.addr   <= c_WRF_DATA;
+
+      when POP_QHEADER_2 =>
+        snk_dreq_o       <= '0';
+        src_fab_o.dvalid <= src_dreq_d0;
+        src_fab_o.data   <= vut_stored_tag;--vut_stored_ethertype;
+        src_fab_o.addr   <= c_WRF_DATA;
+
+      when POP_QHEADER_3 =>
+        snk_dreq_o       <= src_dreq_i and src_dreq_d0;
+        src_fab_o.dvalid <= src_dreq_d0;
+        src_fab_o.data   <= vut_stored_ethertype; --vut_stored_tag;
+        src_fab_o.addr   <= c_WRF_DATA;
+    end case;
+  end process;
+  
+end behavioral;
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_wishbone_controller.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_wishbone_controller.vhd
new file mode 100644
index 000000000..b58e0cfdc
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_wishbone_controller.vhd
@@ -0,0 +1,861 @@
+---------------------------------------------------------------------------------------
+-- Title          : Wishbone slave core for WR switch endpoint controller
+---------------------------------------------------------------------------------------
+-- File           : ep_wishbone_controller.vhd
+-- Author         : auto-generated by wbgen2 from ep_wishbone_controller.wb
+-- Created        : Wed Aug 16 22:43:41 2017
+-- Standard       : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ep_wishbone_controller.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.ep_wbgen2_pkg.all;
+
+
+entity ep_wishbone_controller is
+  port (
+    rst_n_i                                  : in     std_logic;
+    clk_sys_i                                : in     std_logic;
+    wb_adr_i                                 : in     std_logic_vector(4 downto 0);
+    wb_dat_i                                 : in     std_logic_vector(31 downto 0);
+    wb_dat_o                                 : out    std_logic_vector(31 downto 0);
+    wb_cyc_i                                 : in     std_logic;
+    wb_sel_i                                 : in     std_logic_vector(3 downto 0);
+    wb_stb_i                                 : in     std_logic;
+    wb_we_i                                  : in     std_logic;
+    wb_ack_o                                 : out    std_logic;
+    wb_stall_o                               : out    std_logic;
+    tx_clk_i                                 : in     std_logic;
+    rx_clk_i                                 : in     std_logic;
+    regs_i                                   : in     t_ep_in_registers;
+    regs_o                                   : out    t_ep_out_registers
+  );
+end ep_wishbone_controller;
+
+architecture syn of ep_wishbone_controller is
+
+signal ep_ecr_portid_int                        : std_logic_vector(4 downto 0);
+signal ep_ecr_rst_cnt_dly0                      : std_logic      ;
+signal ep_ecr_rst_cnt_int                       : std_logic      ;
+signal ep_ecr_tx_en_int                         : std_logic      ;
+signal ep_ecr_rx_en_int                         : std_logic      ;
+signal ep_tscr_en_txts_int                      : std_logic      ;
+signal ep_tscr_en_rxts_int                      : std_logic      ;
+signal ep_tscr_cs_start_int                     : std_logic      ;
+signal ep_tscr_cs_start_int_delay               : std_logic      ;
+signal ep_tscr_cs_start_sync0                   : std_logic      ;
+signal ep_tscr_cs_start_sync1                   : std_logic      ;
+signal ep_tscr_cs_start_sync2                   : std_logic      ;
+signal ep_tscr_cs_done_sync0                    : std_logic      ;
+signal ep_tscr_cs_done_sync1                    : std_logic      ;
+signal ep_tscr_rx_cal_start_int                 : std_logic      ;
+signal ep_tscr_rx_cal_start_int_delay           : std_logic      ;
+signal ep_tscr_rx_cal_start_sync0               : std_logic      ;
+signal ep_tscr_rx_cal_start_sync1               : std_logic      ;
+signal ep_tscr_rx_cal_start_sync2               : std_logic      ;
+signal ep_rfcr_a_runt_int                       : std_logic      ;
+signal ep_rfcr_a_giant_int                      : std_logic      ;
+signal ep_rfcr_a_hp_int                         : std_logic      ;
+signal ep_rfcr_keep_crc_int                     : std_logic      ;
+signal ep_rfcr_hpap_int                         : std_logic_vector(7 downto 0);
+signal ep_rfcr_mru_int                          : std_logic_vector(13 downto 0);
+signal ep_vcr0_qmode_int                        : std_logic_vector(1 downto 0);
+signal ep_vcr0_fix_prio_int                     : std_logic      ;
+signal ep_vcr0_prio_val_int                     : std_logic_vector(2 downto 0);
+signal ep_vcr0_pvid_int                         : std_logic_vector(11 downto 0);
+signal ep_pfcr0_enable_int                      : std_logic      ;
+signal ep_fcr_rxpause_int                       : std_logic      ;
+signal ep_fcr_txpause_int                       : std_logic      ;
+signal ep_fcr_rxpause_802_1q_int                : std_logic      ;
+signal ep_fcr_txpause_802_1q_int                : std_logic      ;
+signal ep_fcr_tx_thr_int                        : std_logic_vector(7 downto 0);
+signal ep_fcr_tx_quanta_int                     : std_logic_vector(15 downto 0);
+signal ep_mach_int                              : std_logic_vector(15 downto 0);
+signal ep_macl_int                              : std_logic_vector(31 downto 0);
+signal ep_mdio_cr_addr_int                      : std_logic_vector(7 downto 0);
+signal ep_mdio_cr_rw_int                        : std_logic      ;
+signal ep_mdio_asr_phyad_int                    : std_logic_vector(7 downto 0);
+signal ack_sreg                                 : std_logic_vector(9 downto 0);
+signal rddata_reg                               : std_logic_vector(31 downto 0);
+signal wrdata_reg                               : std_logic_vector(31 downto 0);
+signal rwaddr_reg                               : std_logic_vector(4 downto 0);
+signal ack_in_progress                          : std_logic      ;
+
+begin
+-- Some internal signals assignments
+  wrdata_reg <= wb_dat_i;
+-- 
+-- Main register bank access process.
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ack_sreg <= "0000000000";
+      ack_in_progress <= '0';
+      rddata_reg <= "00000000000000000000000000000000";
+      ep_ecr_portid_int <= "00000";
+      ep_ecr_rst_cnt_int <= '0';
+      ep_ecr_tx_en_int <= '0';
+      ep_ecr_rx_en_int <= '0';
+      ep_tscr_en_txts_int <= '0';
+      ep_tscr_en_rxts_int <= '0';
+      ep_tscr_cs_start_int <= '0';
+      ep_tscr_cs_start_int_delay <= '0';
+      ep_tscr_rx_cal_start_int <= '0';
+      ep_tscr_rx_cal_start_int_delay <= '0';
+      ep_rfcr_a_runt_int <= '0';
+      ep_rfcr_a_giant_int <= '0';
+      ep_rfcr_a_hp_int <= '0';
+      ep_rfcr_keep_crc_int <= '0';
+      ep_rfcr_hpap_int <= "00000000";
+      ep_rfcr_mru_int <= "00000000000000";
+      ep_vcr0_qmode_int <= "00";
+      ep_vcr0_fix_prio_int <= '0';
+      ep_vcr0_prio_val_int <= "000";
+      ep_vcr0_pvid_int <= "000000000000";
+      regs_o.vcr1_offset_wr_o <= '0';
+      regs_o.vcr1_data_wr_o <= '0';
+      regs_o.pfcr0_mm_addr_wr_o <= '0';
+      regs_o.pfcr0_mm_write_wr_o <= '0';
+      ep_pfcr0_enable_int <= '0';
+      regs_o.pfcr0_mm_data_msb_wr_o <= '0';
+      regs_o.pfcr1_mm_data_lsb_wr_o <= '0';
+      regs_o.tcar_pcp_map_load_o <= '0';
+      ep_fcr_rxpause_int <= '0';
+      ep_fcr_txpause_int <= '0';
+      ep_fcr_rxpause_802_1q_int <= '0';
+      ep_fcr_txpause_802_1q_int <= '0';
+      ep_fcr_tx_thr_int <= "00000000";
+      ep_fcr_tx_quanta_int <= "0000000000000000";
+      ep_mach_int <= "0000000000000000";
+      ep_macl_int <= "00000000000000000000000000000000";
+      regs_o.mdio_cr_data_wr_o <= '0';
+      ep_mdio_cr_addr_int <= "00000000";
+      ep_mdio_cr_rw_int <= '0';
+      ep_mdio_asr_phyad_int <= "00000000";
+      regs_o.dsr_lact_load_o <= '0';
+      regs_o.dmcr_en_load_o <= '0';
+      regs_o.dmcr_n_avg_load_o <= '0';
+      regs_o.dmsr_ps_rdy_load_o <= '0';
+      regs_o.inj_ctrl_pic_conf_ifg_load_o <= '0';
+      regs_o.inj_ctrl_pic_conf_sel_load_o <= '0';
+      regs_o.inj_ctrl_pic_conf_valid_load_o <= '0';
+      regs_o.inj_ctrl_pic_mode_id_load_o <= '0';
+      regs_o.inj_ctrl_pic_mode_valid_load_o <= '0';
+      regs_o.inj_ctrl_pic_ena_load_o <= '0';
+    elsif rising_edge(clk_sys_i) then
+-- advance the ACK generator shift register
+      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
+      ack_sreg(9) <= '0';
+      if (ack_in_progress = '1') then
+        if (ack_sreg(0) = '1') then
+          ep_ecr_rst_cnt_int <= '0';
+          regs_o.vcr1_offset_wr_o <= '0';
+          regs_o.vcr1_data_wr_o <= '0';
+          regs_o.pfcr0_mm_addr_wr_o <= '0';
+          regs_o.pfcr0_mm_write_wr_o <= '0';
+          regs_o.pfcr0_mm_data_msb_wr_o <= '0';
+          regs_o.pfcr1_mm_data_lsb_wr_o <= '0';
+          regs_o.tcar_pcp_map_load_o <= '0';
+          regs_o.mdio_cr_data_wr_o <= '0';
+          regs_o.dsr_lact_load_o <= '0';
+          regs_o.dmcr_en_load_o <= '0';
+          regs_o.dmcr_n_avg_load_o <= '0';
+          regs_o.dmsr_ps_rdy_load_o <= '0';
+          regs_o.inj_ctrl_pic_conf_ifg_load_o <= '0';
+          regs_o.inj_ctrl_pic_conf_sel_load_o <= '0';
+          regs_o.inj_ctrl_pic_conf_valid_load_o <= '0';
+          regs_o.inj_ctrl_pic_mode_id_load_o <= '0';
+          regs_o.inj_ctrl_pic_mode_valid_load_o <= '0';
+          regs_o.inj_ctrl_pic_ena_load_o <= '0';
+          ack_in_progress <= '0';
+        else
+          ep_tscr_cs_start_int <= ep_tscr_cs_start_int_delay;
+          ep_tscr_cs_start_int_delay <= '0';
+          ep_tscr_rx_cal_start_int <= ep_tscr_rx_cal_start_int_delay;
+          ep_tscr_rx_cal_start_int_delay <= '0';
+          regs_o.vcr1_offset_wr_o <= '0';
+          regs_o.vcr1_data_wr_o <= '0';
+          regs_o.pfcr0_mm_addr_wr_o <= '0';
+          regs_o.pfcr0_mm_write_wr_o <= '0';
+          regs_o.pfcr0_mm_data_msb_wr_o <= '0';
+          regs_o.pfcr1_mm_data_lsb_wr_o <= '0';
+          regs_o.tcar_pcp_map_load_o <= '0';
+          regs_o.mdio_cr_data_wr_o <= '0';
+          regs_o.dsr_lact_load_o <= '0';
+          regs_o.dmcr_en_load_o <= '0';
+          regs_o.dmcr_n_avg_load_o <= '0';
+          regs_o.dmsr_ps_rdy_load_o <= '0';
+          regs_o.inj_ctrl_pic_conf_ifg_load_o <= '0';
+          regs_o.inj_ctrl_pic_conf_sel_load_o <= '0';
+          regs_o.inj_ctrl_pic_conf_valid_load_o <= '0';
+          regs_o.inj_ctrl_pic_mode_id_load_o <= '0';
+          regs_o.inj_ctrl_pic_mode_valid_load_o <= '0';
+          regs_o.inj_ctrl_pic_ena_load_o <= '0';
+        end if;
+      else
+        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
+          case rwaddr_reg(4 downto 0) is
+          when "00000" => 
+            if (wb_we_i = '1') then
+              ep_ecr_portid_int <= wrdata_reg(4 downto 0);
+              ep_ecr_rst_cnt_int <= wrdata_reg(5);
+              ep_ecr_tx_en_int <= wrdata_reg(6);
+              ep_ecr_rx_en_int <= wrdata_reg(7);
+            end if;
+            rddata_reg(4 downto 0) <= ep_ecr_portid_int;
+            rddata_reg(5) <= '0';
+            rddata_reg(6) <= ep_ecr_tx_en_int;
+            rddata_reg(7) <= ep_ecr_rx_en_int;
+            rddata_reg(24) <= regs_i.ecr_feat_vlan_i;
+            rddata_reg(25) <= regs_i.ecr_feat_dmtd_i;
+            rddata_reg(26) <= regs_i.ecr_feat_ptp_i;
+            rddata_reg(27) <= regs_i.ecr_feat_dpi_i;
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(2) <= '1';
+            ack_in_progress <= '1';
+          when "00001" => 
+            if (wb_we_i = '1') then
+              ep_tscr_en_txts_int <= wrdata_reg(0);
+              ep_tscr_en_rxts_int <= wrdata_reg(1);
+              ep_tscr_cs_start_int <= wrdata_reg(2);
+              ep_tscr_cs_start_int_delay <= wrdata_reg(2);
+              ep_tscr_rx_cal_start_int <= wrdata_reg(4);
+              ep_tscr_rx_cal_start_int_delay <= wrdata_reg(4);
+            end if;
+            rddata_reg(0) <= ep_tscr_en_txts_int;
+            rddata_reg(1) <= ep_tscr_en_rxts_int;
+            rddata_reg(2) <= '0';
+            rddata_reg(3) <= ep_tscr_cs_done_sync1;
+            rddata_reg(4) <= '0';
+            rddata_reg(5) <= regs_i.tscr_rx_cal_result_i;
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(4) <= '1';
+            ack_in_progress <= '1';
+          when "00010" => 
+            if (wb_we_i = '1') then
+              ep_rfcr_a_runt_int <= wrdata_reg(0);
+              ep_rfcr_a_giant_int <= wrdata_reg(1);
+              ep_rfcr_a_hp_int <= wrdata_reg(2);
+              ep_rfcr_keep_crc_int <= wrdata_reg(3);
+              ep_rfcr_hpap_int <= wrdata_reg(11 downto 4);
+              ep_rfcr_mru_int <= wrdata_reg(25 downto 12);
+            end if;
+            rddata_reg(0) <= ep_rfcr_a_runt_int;
+            rddata_reg(1) <= ep_rfcr_a_giant_int;
+            rddata_reg(2) <= ep_rfcr_a_hp_int;
+            rddata_reg(3) <= ep_rfcr_keep_crc_int;
+            rddata_reg(11 downto 4) <= ep_rfcr_hpap_int;
+            rddata_reg(25 downto 12) <= ep_rfcr_mru_int;
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00011" => 
+            if (wb_we_i = '1') then
+              ep_vcr0_qmode_int <= wrdata_reg(1 downto 0);
+              ep_vcr0_fix_prio_int <= wrdata_reg(2);
+              ep_vcr0_prio_val_int <= wrdata_reg(6 downto 4);
+              ep_vcr0_pvid_int <= wrdata_reg(27 downto 16);
+            end if;
+            rddata_reg(1 downto 0) <= ep_vcr0_qmode_int;
+            rddata_reg(2) <= ep_vcr0_fix_prio_int;
+            rddata_reg(6 downto 4) <= ep_vcr0_prio_val_int;
+            rddata_reg(27 downto 16) <= ep_vcr0_pvid_int;
+            rddata_reg(3) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00100" => 
+            if (wb_we_i = '1') then
+              regs_o.vcr1_offset_wr_o <= '1';
+              regs_o.vcr1_data_wr_o <= '1';
+            end if;
+            rddata_reg(0) <= 'X';
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00101" => 
+            if (wb_we_i = '1') then
+              regs_o.pfcr0_mm_addr_wr_o <= '1';
+              regs_o.pfcr0_mm_write_wr_o <= '1';
+              ep_pfcr0_enable_int <= wrdata_reg(7);
+              regs_o.pfcr0_mm_data_msb_wr_o <= '1';
+            end if;
+            rddata_reg(7) <= ep_pfcr0_enable_int;
+            rddata_reg(0) <= 'X';
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00110" => 
+            if (wb_we_i = '1') then
+              regs_o.pfcr1_mm_data_lsb_wr_o <= '1';
+            end if;
+            rddata_reg(0) <= 'X';
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00111" => 
+            if (wb_we_i = '1') then
+              regs_o.tcar_pcp_map_load_o <= '1';
+            end if;
+            rddata_reg(23 downto 0) <= regs_i.tcar_pcp_map_i;
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01000" => 
+            if (wb_we_i = '1') then
+              ep_fcr_rxpause_int <= wrdata_reg(0);
+              ep_fcr_txpause_int <= wrdata_reg(1);
+              ep_fcr_rxpause_802_1q_int <= wrdata_reg(2);
+              ep_fcr_txpause_802_1q_int <= wrdata_reg(3);
+              ep_fcr_tx_thr_int <= wrdata_reg(15 downto 8);
+              ep_fcr_tx_quanta_int <= wrdata_reg(31 downto 16);
+            end if;
+            rddata_reg(0) <= ep_fcr_rxpause_int;
+            rddata_reg(1) <= ep_fcr_txpause_int;
+            rddata_reg(2) <= ep_fcr_rxpause_802_1q_int;
+            rddata_reg(3) <= ep_fcr_txpause_802_1q_int;
+            rddata_reg(15 downto 8) <= ep_fcr_tx_thr_int;
+            rddata_reg(31 downto 16) <= ep_fcr_tx_quanta_int;
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01001" => 
+            if (wb_we_i = '1') then
+              ep_mach_int <= wrdata_reg(15 downto 0);
+            end if;
+            rddata_reg(15 downto 0) <= ep_mach_int;
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01010" => 
+            if (wb_we_i = '1') then
+              ep_macl_int <= wrdata_reg(31 downto 0);
+            end if;
+            rddata_reg(31 downto 0) <= ep_macl_int;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01011" => 
+            if (wb_we_i = '1') then
+              regs_o.mdio_cr_data_wr_o <= '1';
+              ep_mdio_cr_addr_int <= wrdata_reg(23 downto 16);
+              ep_mdio_cr_rw_int <= wrdata_reg(31);
+            end if;
+            rddata_reg(23 downto 16) <= ep_mdio_cr_addr_int;
+            rddata_reg(31) <= ep_mdio_cr_rw_int;
+            rddata_reg(0) <= 'X';
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01100" => 
+            if (wb_we_i = '1') then
+              ep_mdio_asr_phyad_int <= wrdata_reg(23 downto 16);
+            end if;
+            rddata_reg(15 downto 0) <= regs_i.mdio_asr_rdata_i;
+            rddata_reg(23 downto 16) <= ep_mdio_asr_phyad_int;
+            rddata_reg(31) <= regs_i.mdio_asr_ready_i;
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01101" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= "11001010111111101011101010111110";
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01110" => 
+            if (wb_we_i = '1') then
+              regs_o.dsr_lact_load_o <= '1';
+            end if;
+            rddata_reg(0) <= regs_i.dsr_lstatus_i;
+            rddata_reg(1) <= regs_i.dsr_lact_i;
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01111" => 
+            if (wb_we_i = '1') then
+              regs_o.dmcr_en_load_o <= '1';
+              regs_o.dmcr_n_avg_load_o <= '1';
+            end if;
+            rddata_reg(0) <= regs_i.dmcr_en_i;
+            rddata_reg(27 downto 16) <= regs_i.dmcr_n_avg_i;
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "10000" => 
+            if (wb_we_i = '1') then
+              regs_o.dmsr_ps_rdy_load_o <= '1';
+            end if;
+            rddata_reg(23 downto 0) <= regs_i.dmsr_ps_val_i;
+            rddata_reg(24) <= regs_i.dmsr_ps_rdy_i;
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "10001" => 
+            if (wb_we_i = '1') then
+              regs_o.inj_ctrl_pic_conf_ifg_load_o <= '1';
+              regs_o.inj_ctrl_pic_conf_sel_load_o <= '1';
+              regs_o.inj_ctrl_pic_conf_valid_load_o <= '1';
+              regs_o.inj_ctrl_pic_mode_id_load_o <= '1';
+              regs_o.inj_ctrl_pic_mode_valid_load_o <= '1';
+              regs_o.inj_ctrl_pic_ena_load_o <= '1';
+            end if;
+            rddata_reg(15 downto 0) <= regs_i.inj_ctrl_pic_conf_ifg_i;
+            rddata_reg(18 downto 16) <= regs_i.inj_ctrl_pic_conf_sel_i;
+            rddata_reg(19) <= regs_i.inj_ctrl_pic_conf_valid_i;
+            rddata_reg(22 downto 20) <= regs_i.inj_ctrl_pic_mode_id_i;
+            rddata_reg(23) <= regs_i.inj_ctrl_pic_mode_valid_i;
+            rddata_reg(24) <= regs_i.inj_ctrl_pic_ena_i;
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when others =>
+-- prevent the slave from hanging the bus on invalid address
+            ack_in_progress <= '1';
+            ack_sreg(0) <= '1';
+          end case;
+        end if;
+      end if;
+    end if;
+  end process;
+  
+  
+-- Drive the data output bus
+  wb_dat_o <= rddata_reg;
+-- Port identifier
+  regs_o.ecr_portid_o <= ep_ecr_portid_int;
+-- Reset event counters
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ep_ecr_rst_cnt_dly0 <= '0';
+      regs_o.ecr_rst_cnt_o <= '0';
+    elsif rising_edge(clk_sys_i) then
+      ep_ecr_rst_cnt_dly0 <= ep_ecr_rst_cnt_int;
+      regs_o.ecr_rst_cnt_o <= ep_ecr_rst_cnt_int and (not ep_ecr_rst_cnt_dly0);
+    end if;
+  end process;
+  
+  
+-- Transmit path enable
+  regs_o.ecr_tx_en_o <= ep_ecr_tx_en_int;
+-- Receive path enable
+  regs_o.ecr_rx_en_o <= ep_ecr_rx_en_int;
+-- Feature present: VLAN tagging
+-- Feature present: DDMTD phase measurement
+-- Feature present: IEEE1588 timestamper
+-- Feature present: DPI packet classifier
+-- Transmit timestamping enable
+  regs_o.tscr_en_txts_o <= ep_tscr_en_txts_int;
+-- Receive timestamping enable
+  regs_o.tscr_en_rxts_o <= ep_tscr_en_rxts_int;
+-- Timestamping counter synchronization start
+  process (tx_clk_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      regs_o.tscr_cs_start_o <= '0';
+      ep_tscr_cs_start_sync0 <= '0';
+      ep_tscr_cs_start_sync1 <= '0';
+      ep_tscr_cs_start_sync2 <= '0';
+    elsif rising_edge(tx_clk_i) then
+      ep_tscr_cs_start_sync0 <= ep_tscr_cs_start_int;
+      ep_tscr_cs_start_sync1 <= ep_tscr_cs_start_sync0;
+      ep_tscr_cs_start_sync2 <= ep_tscr_cs_start_sync1;
+      regs_o.tscr_cs_start_o <= ep_tscr_cs_start_sync2 and (not ep_tscr_cs_start_sync1);
+    end if;
+  end process;
+  
+  
+-- Timestamping counter synchronization done
+-- synchronizer chain for field : Timestamping counter synchronization done (type RO/WO, tx_clk_i -> clk_sys_i)
+  process (tx_clk_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ep_tscr_cs_done_sync0 <= '0';
+      ep_tscr_cs_done_sync1 <= '0';
+    elsif rising_edge(tx_clk_i) then
+      ep_tscr_cs_done_sync0 <= regs_i.tscr_cs_done_i;
+      ep_tscr_cs_done_sync1 <= ep_tscr_cs_done_sync0;
+    end if;
+  end process;
+  
+  
+-- Start calibration of RX timestamper
+  process (rx_clk_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      regs_o.tscr_rx_cal_start_o <= '0';
+      ep_tscr_rx_cal_start_sync0 <= '0';
+      ep_tscr_rx_cal_start_sync1 <= '0';
+      ep_tscr_rx_cal_start_sync2 <= '0';
+    elsif rising_edge(rx_clk_i) then
+      ep_tscr_rx_cal_start_sync0 <= ep_tscr_rx_cal_start_int;
+      ep_tscr_rx_cal_start_sync1 <= ep_tscr_rx_cal_start_sync0;
+      ep_tscr_rx_cal_start_sync2 <= ep_tscr_rx_cal_start_sync1;
+      regs_o.tscr_rx_cal_start_o <= ep_tscr_rx_cal_start_sync2 and (not ep_tscr_rx_cal_start_sync1);
+    end if;
+  end process;
+  
+  
+-- RX timestamper calibration result flag
+-- RX accept runts
+  regs_o.rfcr_a_runt_o <= ep_rfcr_a_runt_int;
+-- RX accept giants
+  regs_o.rfcr_a_giant_o <= ep_rfcr_a_giant_int;
+-- RX accept HP
+  regs_o.rfcr_a_hp_o <= ep_rfcr_a_hp_int;
+-- RX keep CRC
+  regs_o.rfcr_keep_crc_o <= ep_rfcr_keep_crc_int;
+-- RX Fiter HP Priorities
+  regs_o.rfcr_hpap_o <= ep_rfcr_hpap_int;
+-- Maximum receive unit (MRU)
+  regs_o.rfcr_mru_o <= ep_rfcr_mru_int;
+-- RX 802.1q port mode
+  regs_o.vcr0_qmode_o <= ep_vcr0_qmode_int;
+-- Force 802.1q priority
+  regs_o.vcr0_fix_prio_o <= ep_vcr0_fix_prio_int;
+-- Port-assigned 802.1q priority
+  regs_o.vcr0_prio_val_o <= ep_vcr0_prio_val_int;
+-- Port-assigned VID
+  regs_o.vcr0_pvid_o <= ep_vcr0_pvid_int;
+-- VLAN Untagged Set/Injection Buffer offset
+-- pass-through field: VLAN Untagged Set/Injection Buffer offset in register: VLAN Control Register 1
+  regs_o.vcr1_offset_o <= wrdata_reg(9 downto 0);
+-- VLAN Untagged Set/Injection Buffer value
+-- pass-through field: VLAN Untagged Set/Injection Buffer value in register: VLAN Control Register 1
+  regs_o.vcr1_data_o <= wrdata_reg(27 downto 10);
+-- Microcode Memory Address
+-- pass-through field: Microcode Memory Address in register: Packet Filter Control Register 0
+  regs_o.pfcr0_mm_addr_o <= wrdata_reg(5 downto 0);
+-- Microcode Memory Write Enable
+-- pass-through field: Microcode Memory Write Enable in register: Packet Filter Control Register 0
+  regs_o.pfcr0_mm_write_o <= wrdata_reg(6);
+-- Packet Filter Enable
+  regs_o.pfcr0_enable_o <= ep_pfcr0_enable_int;
+-- Microcode Memory Data (24 MSBs)
+-- pass-through field: Microcode Memory Data (24 MSBs) in register: Packet Filter Control Register 0
+  regs_o.pfcr0_mm_data_msb_o <= wrdata_reg(31 downto 8);
+-- Microcode Memory Data (12 LSBs)
+-- pass-through field: Microcode Memory Data (12 LSBs) in register: Packet Filter Control Register 1
+  regs_o.pfcr1_mm_data_lsb_o <= wrdata_reg(11 downto 0);
+-- 802.1Q priority tag to Traffic Class map
+  regs_o.tcar_pcp_map_o <= wrdata_reg(23 downto 0);
+-- RX Pause 802.3 enable
+  regs_o.fcr_rxpause_o <= ep_fcr_rxpause_int;
+-- TX Pause 802.3 enable
+  regs_o.fcr_txpause_o <= ep_fcr_txpause_int;
+-- Rx Pause 802.1Q enable
+  regs_o.fcr_rxpause_802_1q_o <= ep_fcr_rxpause_802_1q_int;
+-- Tx Pause 802.1Q enable (not implemented)
+  regs_o.fcr_txpause_802_1q_o <= ep_fcr_txpause_802_1q_int;
+-- TX pause threshold
+  regs_o.fcr_tx_thr_o <= ep_fcr_tx_thr_int;
+-- TX pause quanta
+  regs_o.fcr_tx_quanta_o <= ep_fcr_tx_quanta_int;
+-- MAC Address
+  regs_o.mach_o <= ep_mach_int;
+-- MAC Address
+  regs_o.macl_o <= ep_macl_int;
+-- MDIO Register Value
+-- pass-through field: MDIO Register Value in register: MDIO Control Register
+  regs_o.mdio_cr_data_o <= wrdata_reg(15 downto 0);
+-- MDIO Register Address
+  regs_o.mdio_cr_addr_o <= ep_mdio_cr_addr_int;
+-- MDIO Read/Write select
+  regs_o.mdio_cr_rw_o <= ep_mdio_cr_rw_int;
+-- MDIO Read Value
+-- MDIO PHY Address
+  regs_o.mdio_asr_phyad_o <= ep_mdio_asr_phyad_int;
+-- MDIO Ready
+-- Link status
+-- Link activity
+  regs_o.dsr_lact_o <= wrdata_reg(1);
+-- DMTD Phase measurement enable
+  regs_o.dmcr_en_o <= wrdata_reg(0);
+-- DMTD averaging samples
+  regs_o.dmcr_n_avg_o <= wrdata_reg(27 downto 16);
+-- DMTD Phase shift value
+-- DMTD Phase shift value ready
+  regs_o.dmsr_ps_rdy_o <= wrdata_reg(24);
+-- Config: Interframe GAP
+  regs_o.inj_ctrl_pic_conf_ifg_o <= wrdata_reg(15 downto 0);
+-- Config: packet pattern sel id
+  regs_o.inj_ctrl_pic_conf_sel_o <= wrdata_reg(18 downto 16);
+-- Config: valid
+  regs_o.inj_ctrl_pic_conf_valid_o <= wrdata_reg(19);
+-- Mode: packet generate mode
+  regs_o.inj_ctrl_pic_mode_id_o <= wrdata_reg(22 downto 20);
+-- Mode: valid
+  regs_o.inj_ctrl_pic_mode_valid_o <= wrdata_reg(23);
+-- Frame Generation Enabled
+  regs_o.inj_ctrl_pic_ena_o <= wrdata_reg(24);
+  rwaddr_reg <= wb_adr_i;
+  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
+-- ACK signal generation. Just pass the LSB of ACK counter.
+  wb_ack_o <= ack_sreg(0);
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/wr_endpoint.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/wr_endpoint.vhd
new file mode 100644
index 000000000..f014eab9f
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/wr_endpoint.vhd
@@ -0,0 +1,1001 @@
+-------------------------------------------------------------------------------
+-- Title      : 1000base-X MAC/Endpoint
+-- Project    : White Rabbit
+-------------------------------------------------------------------------------
+-- File       : wr_endpoint.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2010-04-26
+-- Last update: 2017-02-20
+-- Platform   : FPGA-generics
+-- Standard   : VHDL
+-------------------------------------------------------------------------------
+-- Description: Module implements the top level for the White Rabbit Endpoint
+-- It's basically an extended Ethernet MAC providing extra timing/switch-specific
+-- features such as:
+-- - VLANs: inserting/removing tags (for ACCESS/TRUNK port support)
+-- - RX/TX precise timestaping
+-- - full PCS for optical Gigabit Ethernet 
+-- - decodes MAC addresses, VIDs and priorities and passes them to the RTU.
+-- Refer to the manual for more details.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2011 - 2017 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+
+use work.gencores_pkg.all;
+use work.endpoint_private_pkg.all;
+use work.endpoint_pkg.all;
+use work.ep_wbgen2_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.wishbone_pkg.all;
+
+entity wr_endpoint is
+  
+  generic (
+    g_interface_mode        : t_wishbone_interface_mode      := CLASSIC;
+    g_address_granularity   : t_wishbone_address_granularity := WORD;
+    g_tx_force_gap_length   : integer                        := 0;
+    g_tx_runt_padding       : boolean                        := true;
+    g_simulation            : boolean                        := false;
+    g_pcs_16bit             : boolean                        := true;
+    g_rx_buffer_size        : integer                        := 1024;
+    g_with_rx_buffer        : boolean                        := true;
+    g_with_flow_control     : boolean                        := true;
+    g_with_timestamper      : boolean                        := true;
+    g_with_dpi_classifier   : boolean                        := false;
+    g_with_vlans            : boolean                        := true;
+    g_with_rtu              : boolean                        := true;
+    g_with_leds             : boolean                        := true;
+    g_with_dmtd             : boolean                        := false;
+    g_with_packet_injection : boolean                        := false;
+    g_use_new_rxcrc         : boolean                        := false;
+    g_use_new_txcrc         : boolean                        := false;
+    g_with_stop_traffic     : boolean                        := false
+    );
+  port (
+
+-------------------------------------------------------------------------------
+-- Clocks
+-------------------------------------------------------------------------------
+
+-- Endpoint transmit reference clock. Must be 125 MHz +- 100 ppm
+    clk_ref_i : in std_logic;
+
+-- reference clock / 2 (62.5 MHz, in-phase with refclk)
+    clk_sys_i : in std_logic;
+
+-- DMTD offset clock for phase tracking - used only if g_with_dmtd == true
+    clk_dmtd_i : in std_logic;
+
+-- resets for various clock domains
+    rst_sys_n_i   : in std_logic;
+    rst_ref_n_i   : in std_logic;
+    rst_dmtd_n_i  : in std_logic;
+    rst_txclk_n_i : in std_logic;
+    rst_rxclk_n_i : in std_logic;
+
+-- PPS input (1 clk_ref_i cycle HI) for synchronizing timestamp counter
+    pps_csync_p1_i : in std_logic;
+
+-- PPS valid input (clk_ref_i domain), when 1, the external PPS generator/servo
+-- is not adjusting the time scale, so we can safely timestamp.
+    pps_valid_i : in std_logic := '1';
+
+-------------------------------------------------------------------------------
+-- PHY Interace (8/16 bit PCS)
+-------------------------------------------------------------------------------    
+
+    phy_rst_o            : out std_logic;
+    phy_loopen_o         : out std_logic;
+    phy_loopen_vec_o     : out std_logic_vector(2 downto 0);
+    phy_tx_prbs_sel_o    : out std_logic_vector(2 downto 0);
+    phy_sfp_tx_fault_i   : in  std_logic;
+    phy_sfp_los_i        : in  std_logic;
+    phy_sfp_tx_disable_o : out std_logic;
+    phy_rdy_i            : in  std_logic;
+
+    phy_ref_clk_i      : in  std_logic;
+    phy_tx_data_o      : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
+    phy_tx_k_o         : out std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
+    phy_tx_disparity_i : in  std_logic;
+    phy_tx_enc_err_i   : in  std_logic;
+
+    phy_rx_data_i     : in std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
+    phy_rx_clk_i      : in std_logic;
+    phy_rx_k_i        : in std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
+    phy_rx_enc_err_i  : in std_logic;
+    phy_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0);
+
+-------------------------------------------------------------------------------
+-- GMII Interface (8-bit)
+-------------------------------------------------------------------------------
+
+    gmii_tx_clk_i : in  std_logic := '0';
+    gmii_txd_o    : out std_logic_vector(7 downto 0);
+    gmii_tx_en_o  : out std_logic;
+    gmii_tx_er_o  : out std_logic;
+
+    gmii_rx_clk_i : in std_logic                    := '0';
+    gmii_rxd_i    : in std_logic_vector(7 downto 0) := x"00";
+    gmii_rx_er_i  : in std_logic                    := '0';
+    gmii_rx_dv_i  : in std_logic                    := '0';
+
+    ---------------------------------------------------------------------------
+    -- Wishbone I/O
+    ---------------------------------------------------------------------------
+
+    src_dat_o   : out std_logic_vector(15 downto 0);
+    src_adr_o   : out std_logic_vector(1 downto 0);
+    src_sel_o   : out std_logic_vector(1 downto 0);
+    src_cyc_o   : out std_logic;
+    src_stb_o   : out std_logic;
+    src_we_o    : out std_logic;
+    src_stall_i : in  std_logic;
+    src_ack_i   : in  std_logic;
+    src_err_i   : in  std_logic;
+
+    snk_dat_i   : in  std_logic_vector(15 downto 0);
+    snk_adr_i   : in  std_logic_vector(1 downto 0);
+    snk_sel_i   : in  std_logic_vector(1 downto 0);
+    snk_cyc_i   : in  std_logic;
+    snk_stb_i   : in  std_logic;
+    snk_we_i    : in  std_logic;
+    snk_stall_o : out std_logic;
+    snk_ack_o   : out std_logic;
+    snk_err_o   : out std_logic;
+    snk_rty_o   : out std_logic;
+
+-------------------------------------------------------------------------------
+-- TX timestamping unit interface
+-------------------------------------------------------------------------------  
+
+-- Port ID value
+    txtsu_port_id_o  : out std_logic_vector(4 downto 0);
+-- Frame ID value
+    txtsu_frame_id_o : out std_logic_vector(16 -1 downto 0);
+
+-- TX Timestamp and correctness info
+    txtsu_ts_value_o     : out std_logic_vector(28 + 4 - 1 downto 0);
+    txtsu_ts_incorrect_o : out std_logic;
+
+-- TX timestamp strobe: HI tells the TX timestamping unit that a timestamp is
+-- available on txtsu_ts_value_o, txtsu_fid_o andd txtsu_port_id_o. The correctness
+-- of the timestamping is indiacted on txtsu_ts_incorrect_o. Line remains HI
+-- until assertion of txtsu_ack_i.
+    txtsu_stb_o : out std_logic;
+
+-- TX timestamp acknowledge: HI indicates that TXTSU has successfully received
+-- the timestamp
+    txtsu_ack_i : in std_logic;
+
+-------------------------------------------------------------------------------
+-- RTU interface
+-------------------------------------------------------------------------------
+
+-- 1 indicates that coresponding RTU port is full.
+    rtu_full_i : in std_logic;
+
+-- 1 indicates that coresponding RTU port is almost full.
+    rtu_almost_full_i : in std_logic;
+
+-- request strobe, single HI pulse begins evaluation of the request. 
+    rtu_rq_strobe_p1_o : out std_logic;
+    
+    rtu_rq_abort_o : out std_logic;
+
+-- source and destination MAC addresses extracted from the packet header
+    rtu_rq_smac_o : out std_logic_vector(48 - 1 downto 0);
+    rtu_rq_dmac_o : out std_logic_vector(48 - 1 downto 0);
+
+-- VLAN id (extracted from the header for TRUNK ports and assigned by the port
+-- for ACCESS ports)
+    rtu_rq_vid_o : out std_logic_vector(12 - 1 downto 0);
+
+-- HI means that packet has valid assigned a valid VID (low - packet is untagged)
+    rtu_rq_has_vid_o : out std_logic;
+
+-- packet priority (either extracted from the header or assigned per port).
+    rtu_rq_prio_o : out std_logic_vector(3 - 1 downto 0);
+
+-- HI indicates that packet has assigned priority.
+    rtu_rq_has_prio_o : out std_logic;
+
+-------------------------------------------------------------------------------   
+-- Wishbone bus
+-------------------------------------------------------------------------------
+
+    wb_cyc_i   : in  std_logic;
+    wb_stb_i   : in  std_logic;
+    wb_we_i    : in  std_logic;
+    wb_sel_i   : in  std_logic_vector(3 downto 0);
+    wb_adr_i   : in  std_logic_vector(7 downto 0);
+    wb_dat_i   : in  std_logic_vector(31 downto 0);
+    wb_dat_o   : out std_logic_vector(31 downto 0);
+    wb_ack_o   : out std_logic;
+    wb_stall_o : out std_logic;
+
+-------------------------------------------------------------------------------
+-- direct output of packet filter  (for TRU/HW-RSTP)
+-------------------------------------------------------------------------------
+
+   pfilter_pclass_o : out std_logic_vector(7 downto 0);
+   pfilter_drop_o   : out std_logic;
+   pfilter_done_o   : out std_logic;
+
+-------------------------------------------------------------------------------
+-- control of PAUSE sending (ML: not used and not tested... TRU uses packet injection) -- 
+-------------------------------------------------------------------------------
+
+   fc_tx_pause_req_i   : in  std_logic                     := '0';
+   fc_tx_pause_delay_i : in  std_logic_vector(15 downto 0) := x"0000";
+   fc_tx_pause_ready_o : out std_logic;
+
+-------------------------------------------------------------------------------
+-- information about received PAUSE (for SWcore)
+-------------------------------------------------------------------------------
+
+   fc_rx_pause_start_p_o   : out std_logic;
+   fc_rx_pause_quanta_o    : out std_logic_vector(15 downto 0);
+   fc_rx_pause_prio_mask_o : out std_logic_vector(7 downto 0);
+   fc_rx_buffer_occupation_o : out std_logic_vector(7 downto 0);
+-------------------------------------------------------------------------------
+-- Packet Injection Interface (for TRU/HW-RSTP)
+-------------------------------------------------------------------------------
+
+-- injection request: triggers transmission of the packet to be injected,
+-- allowed when inject_ready = 1
+    inject_req_i : in std_logic := '0';
+
+-- injection ready flag: when true, user application can request asynchronous
+-- injection of a predefined packet
+    inject_ready_o : out std_logic;
+
+-- injection template selection (8 available)
+    inject_packet_sel_i : in std_logic_vector(2 downto 0) := "000";
+
+-- user-defined value to be embedded in the injected packet at a predefined
+-- location
+    inject_user_value_i : in std_logic_vector(15 downto 0) := x"0000";
+
+-------------------------------------------------------------------------------
+-- Misc stuff
+-------------------------------------------------------------------------------
+    rmon_events_o : out std_logic_vector(c_epevents_sz-1 downto 0);
+
+    txts_o     : out std_logic; 		                -- 2013-Nov-28 peterj added for debugging/calibration
+    rxts_o     : out std_logic; 		                -- 2013-Nov-28 peterj added for debugging/calibration
+
+    led_link_o : out std_logic;
+    led_act_o  : out std_logic;
+
+-- HI physically kills the link (turn of laser)
+    link_kill_i : in std_logic := '0';
+
+-- HI indicates that link is up (so cable connected), LOW indicates that link is faulty 
+-- (e.g.: cable disconnected)
+    link_up_o : out std_logic;
+
+    stop_traffic_i : in std_logic := '0';
+
+    dbg_tx_pcs_wr_count_o     : out std_logic_vector(5+4 downto 0);
+    dbg_tx_pcs_rd_count_o     : out std_logic_vector(5+4 downto 0);
+    nice_dbg_o  : out t_dbg_ep
+    );
+
+end wr_endpoint;
+
+architecture syn of wr_endpoint is
+
+  constant c_zeros : std_logic_vector(63 downto 0) := (others => '0');
+  constant c_ones  : std_logic_vector(63 downto 0) := (others => '0');
+
+-------------------------------------------------------------------------------
+  component dmtd_phase_meas
+    generic (
+      g_deglitcher_threshold : integer;
+      g_counter_bits         : integer);
+    port (
+      rst_sys_n_i    : in  std_logic;
+      rst_dmtd_n_i   : in  std_logic;
+      clk_sys_i      : in  std_logic;
+      clk_a_i        : in  std_logic;
+      clk_b_i        : in  std_logic;
+      clk_dmtd_i     : in  std_logic;
+      en_i           : in  std_logic;
+      navg_i         : in  std_logic_vector(11 downto 0);
+      phase_meas_o   : out std_logic_vector(31 downto 0);
+      phase_meas_p_o : out std_logic);
+  end component;
+
+-------------------------------------------------------------------------------
+-- TX FRAMER -> TX PCS signals
+-------------------------------------------------------------------------------
+
+  signal txpcs_fab   : t_ep_internal_fabric;
+  signal txpcs_dreq  : std_logic;
+  signal txpcs_error : std_logic;
+  signal txpcs_busy  : std_logic;
+
+-------------------------------------------------------------------------------
+-- Timestamping/OOB signals
+-------------------------------------------------------------------------------
+
+  signal txoob_fid_value : std_logic_vector(15 downto 0);
+  signal txoob_fid_stb   : std_logic;
+
+  signal txpcs_timestamp_trigger_p_a : std_logic;
+
+  signal txts_timestamp_stb   : std_logic;
+  signal txts_timestamp_valid : std_logic;
+  signal txts_timestamp_value : std_logic_vector(31 downto 0);
+
+
+  signal rxpcs_timestamp_stb         : std_logic;
+  signal rxpcs_timestamp_trigger_p_a : std_logic;
+  signal rxpcs_timestamp_valid       : std_logic;
+  signal rxpcs_timestamp_value       : std_logic_vector(31 downto 0);
+
+
+-------------------------------------------------------------------------------
+-- RX PCS -> RX DEFRAMER signals
+-------------------------------------------------------------------------------
+
+  signal rxpcs_fab             : t_ep_internal_fabric;
+  signal rxpath_fab            : t_ep_internal_fabric;
+  signal rxpcs_busy            : std_logic;
+  signal rxpcs_fifo_almostfull : std_logic;
+
+-------------------------------------------------------------------------------
+-- WB slave signals
+-------------------------------------------------------------------------------
+
+  signal regs_fromwb     : t_ep_out_registers;
+  signal regs_towb       : t_ep_in_registers;
+  signal regs_towb_ep    : t_ep_in_registers;
+  signal regs_towb_tsu   : t_ep_in_registers;
+  signal regs_towb_rpath : t_ep_in_registers;
+  signal regs_towb_tpath : t_ep_in_registers;
+  signal regs_towb_dmtd  : t_ep_in_registers;
+
+-------------------------------------------------------------------------------
+-- flow control signals
+-------------------------------------------------------------------------------
+
+  signal txfra_flow_enable : std_logic;
+  signal rxfra_pause_p     : std_logic;
+  signal rxfra_pause_delay : std_logic_vector(15 downto 0);
+
+  signal txfra_pause_req   : std_logic;
+  signal txfra_pause_ready : std_logic;
+  signal txfra_pause_delay : std_logic_vector(15 downto 0);
+
+  signal link_ok : std_logic;
+
+  signal txfra_enable : std_logic;
+  signal mdio_addr    : std_logic_vector(15 downto 0);
+
+  signal sink_in  : t_wrf_sink_in;
+  signal sink_out : t_wrf_sink_out;
+
+  signal src_in  : t_wrf_source_in;
+  signal src_out : t_wrf_source_out;
+
+  signal rst_n_rx : std_logic;
+
+  signal wb_in  : t_wishbone_slave_in;
+  signal wb_out : t_wishbone_slave_out;
+
+  signal extended_ADDR : std_logic_vector(c_wishbone_address_width-1 downto 0);
+
+  signal phase_meas    : std_logic_vector(31 downto 0);
+  signal phase_meas_p  : std_logic;
+  signal validity_cntr : unsigned(1 downto 0);
+  signal r_dmcr_en     : std_logic;
+  signal r_dmcr_n_avg  : std_logic_vector(11 downto 0);
+
+
+  signal rtu_rq               : t_ep_internal_rtu_request;
+  signal dvalid_tx, dvalid_rx : std_logic;
+
+-------------------------------------------------------------------------------
+-- TRU stuff
+-------------------------------------------------------------------------------
+  signal ep_ctrl        : std_logic;
+  signal pfilter_pclass : std_logic_vector(7 downto 0);
+  signal pfilter_drop   : std_logic;
+  signal pfilter_done   : std_logic;
+  signal tx_pclass      : std_logic_vector(7 downto 0);
+
+-------------------------------------------------------------------------------
+-- RMON signals
+-------------------------------------------------------------------------------
+  signal pcs_rmon     : t_rmon_triggers;
+  signal rx_path_rmon : t_rmon_triggers;
+  signal rmon         : t_rmon_triggers;
+ 
+-------------------------------------------------------------------------------
+-- chipscope (for desperates)
+-------------------------------------------------------------------------------
+  signal CONTROL0                   : std_logic_vector(35 downto 0);
+  signal TRIG0, TRIG1, TRIG2, TRIG3 : std_logic_vector(31 downto 0);
+
+  component chipscope_icon
+    port (
+      CONTROL0 : inout std_logic_vector(35 downto 0));
+  end component;
+
+  component chipscope_ila
+    port (
+      CONTROL : inout std_logic_vector(35 downto 0);
+      CLK     : in    std_logic;
+      TRIG0   : in    std_logic_vector(31 downto 0);
+      TRIG1   : in    std_logic_vector(31 downto 0);
+      TRIG2   : in    std_logic_vector(31 downto 0);
+      TRIG3   : in    std_logic_vector(31 downto 0));
+  end component;
+
+begin
+
+  rst_n_rx  <= rst_rxclk_n_i and phy_rdy_i;
+
+-------------------------------------------------------------------------------
+-- 1000Base-X PCS
+-------------------------------------------------------------------------------
+
+  mdio_addr <= regs_fromwb.mdio_asr_phyad_o & regs_fromwb.mdio_cr_addr_o;
+
+  U_PCS_1000BASEX : ep_1000basex_pcs
+    generic map (
+      g_simulation => g_simulation,
+      g_16bit      => g_pcs_16bit)
+    port map (
+      rst_sys_n_i   => rst_sys_n_i,
+      rst_rxclk_n_i => rst_rxclk_n_i,
+      rst_txclk_n_i => rst_txclk_n_i,
+      clk_sys_i     => clk_sys_i,
+
+      rxpcs_fab_o             => rxpcs_fab,
+      rxpcs_busy_o            => rxpcs_busy,
+      rxpcs_fifo_almostfull_i => rxpcs_fifo_almostfull,
+
+      rxpcs_timestamp_trigger_p_a_o => rxpcs_timestamp_trigger_p_a,
+      rxpcs_timestamp_i             => rxpcs_timestamp_value,
+      rxpcs_timestamp_stb_i         => rxpcs_timestamp_stb,
+      rxpcs_timestamp_valid_i       => rxpcs_timestamp_valid,
+
+      txpcs_fab_i   => txpcs_fab,
+      txpcs_busy_o  => txpcs_busy,
+      txpcs_dreq_o  => txpcs_dreq,
+      txpcs_error_o => txpcs_error,
+
+      txpcs_timestamp_trigger_p_a_o => txpcs_timestamp_trigger_p_a,
+
+      link_ok_o  => link_ok,
+      link_ctr_i => ep_ctrl,
+
+      serdes_rst_o             => phy_rst_o,
+      serdes_loopen_o          => phy_loopen_o,
+      serdes_loopen_vec_o      => phy_loopen_vec_o,
+      serdes_tx_prbs_sel_o     => phy_tx_prbs_sel_o,
+      serdes_sfp_tx_fault_i    => phy_sfp_tx_fault_i,
+      serdes_sfp_los_i         => phy_sfp_los_i,
+      serdes_sfp_tx_disable_o  => phy_sfp_tx_disable_o,
+      serdes_rdy_i             => phy_rdy_i,
+
+      serdes_tx_clk_i       => phy_ref_clk_i,
+      serdes_tx_data_o      => phy_tx_data_o,
+      serdes_tx_k_o         => phy_tx_k_o,
+      serdes_tx_disparity_i => phy_tx_disparity_i,
+      serdes_tx_enc_err_i   => phy_tx_enc_err_i,
+      serdes_rx_data_i      => phy_rx_data_i,
+      serdes_rx_clk_i       => phy_rx_clk_i,
+      serdes_rx_k_i         => phy_rx_k_i,
+      serdes_rx_enc_err_i   => phy_rx_enc_err_i,
+      serdes_rx_bitslide_i  => phy_rx_bitslide_i,
+
+      rmon_o => pcs_rmon,
+
+      mdio_addr_i  => mdio_addr,
+      mdio_data_i  => regs_fromwb.mdio_cr_data_o,
+      mdio_data_o  => regs_towb_ep.mdio_asr_rdata_i,
+      mdio_stb_i   => regs_fromwb.mdio_cr_data_wr_o,
+      mdio_rw_i    => regs_fromwb.mdio_cr_rw_o,
+      mdio_ready_o => regs_towb_ep.mdio_asr_ready_i,
+      dbg_tx_pcs_wr_count_o => dbg_tx_pcs_wr_count_o,
+      dbg_tx_pcs_rd_count_o => dbg_tx_pcs_rd_count_o,
+      nice_dbg_o   => nice_dbg_o.pcs);
+
+
+-------------------------------------------------------------------------------
+-- TX FRAMER
+-------------------------------------------------------------------------------
+
+--  txfra_enable <= link_ok and regs_fromwb.ecr_tx_en_o;
+
+--   txfra_pause_req <= '0';
+
+  U_Tx_Path : ep_tx_path
+    generic map (
+      g_with_packet_injection => g_with_packet_injection,
+      g_with_vlans            => g_with_vlans,
+      g_with_timestamper      => g_with_timestamper,
+      g_force_gap_length      => g_tx_force_gap_length,
+      g_runt_padding          => g_tx_runt_padding,
+      g_use_new_crc           => g_use_new_txcrc)
+    port map (
+      clk_sys_i        => clk_sys_i,
+      rst_n_i          => rst_sys_n_i,
+      pcs_error_i      => txpcs_error,
+      pcs_busy_i       => txpcs_busy,
+      pcs_fab_o        => txpcs_fab,
+      pcs_dreq_i       => txpcs_dreq,
+      snk_i            => sink_in,
+      snk_o            => sink_out,
+      fc_pause_req_i   => txfra_pause_req,
+      fc_pause_ready_o => txfra_pause_ready,
+      fc_pause_delay_i => txfra_pause_delay,
+      fc_flow_enable_i => txfra_flow_enable,
+      ep_ctrl_i        => ep_ctrl,
+      regs_i           => regs_fromwb,
+      regs_o           => regs_towb_tpath,
+
+      txts_timestamp_i       => txts_timestamp_value,
+      txts_timestamp_valid_i => txts_timestamp_valid,
+
+      txtsu_port_id_o      => txtsu_port_id_o,
+      txtsu_fid_o          => txtsu_frame_id_o,
+      txtsu_ts_value_o     => txtsu_ts_value_o,
+      txtsu_ts_incorrect_o => txtsu_ts_incorrect_o,
+      txtsu_stb_o          => txtsu_stb_o,
+      txtsu_ack_i          => txtsu_ack_i,
+
+      inject_req_i        => inject_req_i,
+      inject_user_value_i => inject_user_value_i,
+      inject_packet_sel_i => inject_packet_sel_i,
+      inject_ready_o      => inject_ready_o);
+
+
+  txfra_flow_enable <= '1';
+
+  sink_in.dat <= snk_dat_i;
+  sink_in.adr <= snk_adr_i;
+  sink_in.sel <= snk_sel_i;
+  sink_in.cyc <= snk_cyc_i;
+  sink_in.stb <= snk_stb_i;
+  sink_in.we  <= snk_we_i;
+  snk_stall_o <= sink_out.stall;
+  snk_ack_o   <= sink_out.ack;
+  snk_err_o   <= sink_out.err;
+  snk_rty_o   <= sink_out.rty;
+
+
+-------------------------------------------------------------------------------
+-- RX deframer
+-------------------------------------------------------------------------------
+
+  U_Rx_Path : ep_rx_path
+    generic map (
+      g_with_vlans          => g_with_vlans,
+      g_with_dpi_classifier => g_with_dpi_classifier,
+      g_with_rtu            => g_with_rtu,
+      g_with_rx_buffer      => g_with_rx_buffer,
+      g_rx_buffer_size      => g_rx_buffer_size,
+      g_use_new_crc         => g_use_new_rxcrc)
+    port map (
+      clk_sys_i => clk_sys_i,
+      clk_rx_i  => phy_rx_clk_i,
+
+      rst_n_sys_i => rst_sys_n_i,
+      rst_n_rx_i  => rst_n_rx,
+
+      pcs_fab_i             => rxpath_fab,
+      pcs_fifo_almostfull_o => rxpcs_fifo_almostfull,
+      pcs_busy_i            => rxpcs_busy,
+
+      fc_pause_p_o         => fc_rx_pause_start_p_o,  --rxfra_pause_p,
+      fc_pause_quanta_o    => fc_rx_pause_quanta_o,   --rxfra_pause_delay,
+      fc_pause_prio_mask_o => fc_rx_pause_prio_mask_o,
+      fc_buffer_occupation_o => fc_rx_buffer_occupation_o,
+
+      rmon_o => rx_path_rmon,
+      regs_i => regs_fromwb,
+      regs_o => regs_towb_rpath,
+
+      pfilter_pclass_o => pfilter_pclass,
+      pfilter_drop_o   => pfilter_drop,
+      pfilter_done_o   => pfilter_done,
+
+      rtu_full_i     => rtu_full_i,
+      rtu_rq_o       => rtu_rq,
+      rtu_rq_valid_o => rtu_rq_strobe_p1_o,
+      rtu_rq_abort_o => rtu_rq_abort_o,
+      src_wb_o       => src_out,
+      src_wb_i       => src_in,
+      nice_dbg_o     => nice_dbg_o.rxpath);
+
+
+  rtu_rq_smac_o     <= rtu_rq.smac;
+  rtu_rq_dmac_o     <= rtu_rq.dmac;
+  rtu_rq_vid_o      <= rtu_rq.vid;
+  rtu_rq_prio_o     <= rtu_rq.prio;
+  rtu_rq_has_vid_o  <= rtu_rq.has_vid;
+  rtu_rq_has_prio_o <= rtu_rq.has_prio;
+
+  src_dat_o    <= src_out.dat;
+  src_adr_o    <= src_out.adr;
+  src_sel_o    <= src_out.sel;
+  src_cyc_o    <= src_out.cyc;
+  src_stb_o    <= src_out.stb;
+  src_we_o     <= src_out.we;
+  src_in.stall <= src_stall_i;
+  src_in.ack   <= src_ack_i;
+  src_in.err   <= src_err_i;
+  src_in.rty   <= '0';
+
+-------------------------------------------------------------------------------
+-- Flow control unit
+-------------------------------------------------------------------------------
+
+  --U_FLOW_CTL : ep_flow_control
+  --  port map (
+  --    clk_sys_i => clk_sys_i,
+  --    rst_n_i   => rst_n_i,
+
+  --    rx_pause_p1_i    => rxfra_pause_p,
+  --    rx_pause_delay_i => rxfra_pause_delay,
+
+  --    tx_pause_o       => txfra_pause,
+  --    tx_pause_delay_o => txfra_pause_delay,
+  --    tx_pause_ack_i   => txfra_pause_ack,
+
+  --    tx_flow_enable_o => txfra_flow_enable,
+
+  --    rx_buffer_used_i => rx_buffer_used,
+
+  --    ep_fcr_txpause_i   => regs.fcr_txpause_o,
+  --    ep_fcr_rxpause_i   => regs.fcr_rxpause_o,
+  --    ep_fcr_tx_thr_i    => regs.fcr_tx_thr_o,
+  --    ep_fcr_tx_quanta_i => regs.fcr_tx_quanta_o,
+  --    rmon_rcvd_pause_o  => rmon.rx_pause,
+  --    rmon_sent_pause_o  => rmon.tx_pause
+  --    );
+
+-------------------------------------------------------------------------------
+-- Timestamping unit
+-------------------------------------------------------------------------------
+
+  U_EP_TSU : ep_timestamping_unit
+    generic map (
+      g_timestamp_bits_r => 28,
+      g_timestamp_bits_f => 4,
+      g_ref_clock_rate   => f_pcs_clock_rate(g_pcs_16bit))
+    port map (
+      clk_ref_i      => clk_ref_i,
+      clk_rx_i       => phy_rx_clk_i,
+      clk_sys_i      => clk_sys_i,
+      rst_n_rx_i     => rst_rxclk_n_i,
+      rst_n_sys_i    => rst_sys_n_i,
+      rst_n_ref_i    => rst_ref_n_i,
+      pps_csync_p1_i => pps_csync_p1_i,
+      pps_valid_i    => pps_valid_i,
+
+      tx_timestamp_trigger_p_a_i => txpcs_timestamp_trigger_p_a,
+      rx_timestamp_trigger_p_a_i => rxpcs_timestamp_trigger_p_a,
+
+      rxts_timestamp_o       => rxpcs_timestamp_value,
+      rxts_timestamp_valid_o => rxpcs_timestamp_valid,
+      rxts_timestamp_stb_o   => rxpcs_timestamp_stb,
+
+      txts_timestamp_o       => txts_timestamp_value,
+      txts_timestamp_valid_o => txts_timestamp_valid,
+
+      txts_o                 => txts_o,                   -- 2013-Nov-28 peterj added for debugging/calibration
+      rxts_o                 => rxts_o, 		              -- 2013-Nov-28 peterj added for debugging/calibration
+
+      regs_i => regs_fromwb,
+      regs_o => regs_towb_tsu);
+
+
+-------------------------------------------------------------------------------
+-- Wishbone controller & IO registers
+-------------------------------------------------------------------------------
+
+  extended_ADDR <= std_logic_vector(resize(unsigned(wb_adr_i), c_wishbone_address_width));
+
+  U_Slave_adapter : wb_slave_adapter
+    generic map (
+      g_master_use_struct  => true,
+      g_master_mode        => CLASSIC,
+      g_master_granularity => WORD,
+      g_slave_use_struct   => false,
+      g_slave_mode         => g_interface_mode,
+      g_slave_granularity  => g_address_granularity)
+    port map (
+      clk_sys_i  => clk_sys_i,
+      rst_n_i    => rst_sys_n_i,
+      sl_adr_i   => extended_ADDR,
+      sl_dat_i   => wb_dat_i,
+      sl_sel_i   => wb_sel_i,
+      sl_cyc_i   => wb_cyc_i,
+      sl_stb_i   => wb_stb_i,
+      sl_we_i    => wb_we_i,
+      sl_dat_o   => wb_dat_o,
+      sl_ack_o   => wb_ack_o,
+      sl_stall_o => wb_stall_o,
+      master_i   => wb_out,
+      master_o   => wb_in);
+
+  U_WB_SLAVE : ep_wishbone_controller
+    port map (
+      rst_n_i    => rst_sys_n_i,
+      clk_sys_i  => clk_sys_i,
+      wb_adr_i   => wb_in.adr(4 downto 0),
+      wb_dat_i   => wb_in.dat,
+      wb_dat_o   => wb_out.dat,
+      wb_cyc_i   => wb_in.cyc,
+      wb_sel_i   => wb_in.sel,
+      wb_stb_i   => wb_in.stb,
+      wb_we_i    => wb_in.we,
+      wb_ack_o   => wb_out.ack,
+      wb_stall_o => open,
+
+      tx_clk_i => clk_ref_i,
+      rx_clk_i => phy_rx_clk_i,
+
+      regs_o => regs_fromwb,
+      regs_i => regs_towb
+      );     
+
+  wb_out.stall <= '0';
+  wb_out.rty   <= '0';
+  wb_out.err   <= '0';
+  wb_out.int   <= '0';
+
+  regs_towb <= regs_towb_ep or regs_towb_tsu or regs_towb_rpath or regs_towb_tpath or regs_towb_dmtd;
+
+
+  p_link_activity : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+
+      if(rst_sys_n_i = '0') or
+        (regs_fromwb.dsr_lact_o = '1' and regs_fromwb.dsr_lact_load_o = '1') then
+        regs_towb_ep.dsr_lact_i <= '0';
+      else
+        regs_towb_ep.dsr_lact_i <= dvalid_rx or dvalid_tx;
+      end if;
+    end if;
+  end process;
+
+  -- drive unused regs_towb_ep signals
+  regs_towb_ep.ecr_feat_vlan_i           <= '0';
+  regs_towb_ep.ecr_feat_dmtd_i           <= '0';
+  regs_towb_ep.ecr_feat_ptp_i            <= '0';
+  regs_towb_ep.ecr_feat_dpi_i            <= '0';
+  regs_towb_ep.tscr_cs_done_i            <= '0';
+  regs_towb_ep.tscr_rx_cal_result_i      <= '0';
+  regs_towb_ep.tcar_pcp_map_i            <= (others => '0');
+  regs_towb_ep.dsr_lstatus_i             <= '0';
+  regs_towb_ep.dmcr_en_i                 <= '0';
+  regs_towb_ep.dmcr_n_avg_i              <= (others => '0');
+  regs_towb_ep.inj_ctrl_pic_conf_ifg_i   <= (others => '0');
+  regs_towb_ep.inj_ctrl_pic_conf_sel_i   <= (others => '0');
+  regs_towb_ep.inj_ctrl_pic_conf_valid_i <= '0';
+  regs_towb_ep.inj_ctrl_pic_mode_id_i    <= (others => '0');
+  regs_towb_ep.inj_ctrl_pic_mode_valid_i <= '0';
+  regs_towb_ep.inj_ctrl_pic_ena_i        <= '0';
+
+-------------------------------------------------------------------------------
+-- DMTD phase meter
+------------------------------------------------------------------------------  
+
+  gen_with_dmtd : if(g_with_dmtd) generate
+    U_DMTD : dmtd_phase_meas
+      generic map (
+        g_counter_bits         => 14,
+        g_deglitcher_threshold => 1000)
+      port map (
+        clk_sys_i => clk_sys_i,
+
+        clk_a_i    => phy_ref_clk_i,
+        clk_b_i    => phy_rx_clk_i,
+        clk_dmtd_i => clk_dmtd_i,
+
+        rst_sys_n_i  => rst_sys_n_i,
+        rst_dmtd_n_i => rst_dmtd_n_i,
+
+        en_i           => r_dmcr_en,
+        navg_i         => r_dmcr_n_avg,
+        phase_meas_o   => phase_meas,
+        phase_meas_p_o => phase_meas_p);
+
+
+
+    regs_towb_dmtd.dmcr_en_i    <= r_dmcr_en;
+    regs_towb_dmtd.dmcr_n_avg_i <= r_dmcr_n_avg;
+
+    p_dmtd_update : process(clk_sys_i)
+    begin
+      if rising_edge(clk_sys_i) then
+        if rst_sys_n_i = '0' then
+          validity_cntr              <= (others => '0');
+          regs_towb_ep.dmsr_ps_rdy_i <= '0';
+        else
+
+          if(regs_fromwb.dmcr_en_load_o = '1') then
+            r_dmcr_en    <= regs_fromwb.dmcr_en_o;
+            r_dmcr_n_avg <= regs_fromwb.dmcr_n_avg_o;
+          end if;
+
+          if(r_dmcr_en = '0') then
+            validity_cntr              <= (others => '0');
+            regs_towb_ep.dmsr_ps_rdy_i <= '0';
+          elsif(regs_fromwb.dmsr_ps_rdy_o = '1' and regs_fromwb.dmsr_ps_rdy_load_o = '1') then
+            regs_towb_ep.dmsr_ps_rdy_i <= '0';
+          elsif(phase_meas_p = '1') then
+
+            if(validity_cntr = "11") then
+              regs_towb_ep.dmsr_ps_rdy_i <= '1';
+              regs_towb_ep.dmsr_ps_val_i <= phase_meas(23 downto 0);  -- discard few
+            else
+              regs_towb_ep.dmsr_ps_rdy_i <= '0';
+              validity_cntr              <= validity_cntr + 1;
+            end if;
+          end if;
+        end if;
+      end if;
+    end process;
+
+  end generate gen_with_dmtd;
+
+  gen_without_dmtd : if(not g_with_dmtd) generate
+    regs_towb_ep.dmsr_ps_rdy_i <= '0';
+    regs_towb_ep.dmsr_ps_val_i <= (others => 'X');
+    regs_towb_dmtd             <= c_ep_in_registers_init_value;
+  end generate gen_without_dmtd;
+
+  dvalid_tx <= snk_cyc_i and snk_stb_i and link_ok;
+  dvalid_rx <= src_out.cyc and src_out.stb and link_ok;
+
+  gen_leds : if g_with_leds generate
+    U_Led_Ctrl : ep_leds_controller
+      generic map (
+        g_blink_period_log2 => 22)
+      port map (
+        clk_sys_i   => clk_sys_i,
+        rst_n_i     => rst_sys_n_i,
+        dvalid_tx_i => dvalid_tx,
+        dvalid_rx_i => dvalid_rx,
+        link_ok_i   => link_ok,
+        led_link_o  => led_link_o,
+        led_act_o   => led_act_o);
+  end generate gen_leds;
+
+  -------------------------- TRU stuff -----------------------------------
+  link_up_o <= link_ok;                 -- indicates that link is UP
+
+  pfilter_pclass_o <= pfilter_pclass;
+  pfilter_done_o   <= pfilter_done;
+  pfilter_drop_o   <= pfilter_drop;
+
+  txfra_pause_req     <= fc_tx_pause_req_i;
+  fc_tx_pause_ready_o <= txfra_pause_ready;
+  txfra_pause_delay   <= fc_tx_pause_delay_i;
+
+  -- TRU needs to be able to share the control of ouput path, i.e. turn off the laser
+  p_ep_ctrl : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_sys_n_i = '0' then
+        ep_ctrl <= '1';
+      else
+        ep_ctrl <= not link_kill_i;
+      end if;
+    end if;
+  end process;
+
+  GEN_STOP: if(g_with_stop_traffic) generate
+    rxpath_fab.sof    <= rxpcs_fab.sof    when(stop_traffic_i='0') else '0';
+    rxpath_fab.dvalid <= rxpcs_fab.dvalid when(stop_traffic_i='0') else '0';
+    rxpath_fab.eof   <= rxpcs_fab.eof;
+    rxpath_fab.error <= rxpcs_fab.error;
+    rxpath_fab.bytesel <= rxpcs_fab.bytesel;
+    rxpath_fab.has_rx_timestamp <= rxpcs_fab.has_rx_timestamp;
+    rxpath_fab.rx_timestamp_valid <= rxpcs_fab.rx_timestamp_valid;
+    rxpath_fab.data <= rxpcs_fab.data;
+    rxpath_fab.addr <= rxpcs_fab.addr;
+  end generate;
+
+  GEN_NO_STOP: if(not g_with_stop_traffic) generate
+    rxpath_fab <= rxpcs_fab;
+  end generate;
+
+  -------------------------- RMON events -----------------------------------
+  rmon.rx_pcs_err      <= rx_path_rmon.rx_pcs_err;  --from ep_rx_path
+  rmon.rx_giant        <= rx_path_rmon.rx_giant;
+  rmon.rx_runt         <= rx_path_rmon.rx_runt;
+  rmon.rx_crc_err      <= rx_path_rmon.rx_crc_err;
+  rmon.rx_pause        <= rx_path_rmon.rx_pause;
+  rmon.rx_pfilter_drop <= rx_path_rmon.rx_pfilter_drop;
+  rmon.rx_pclass       <= rx_path_rmon.rx_pclass;
+  rmon.rx_tclass       <= rx_path_rmon.rx_tclass;
+  rmon.rx_drop_at_rtu_full <= rx_path_rmon.rx_drop_at_rtu_full;
+  rmon.tx_underrun     <= pcs_rmon.tx_underrun;
+  rmon.rx_overrun      <= pcs_rmon.rx_overrun;
+  rmon.rx_invalid_code <= pcs_rmon.rx_invalid_code;
+  rmon.rx_sync_lost    <= pcs_rmon.rx_sync_lost;
+
+
+  rmon_event_tx : gc_sync_ffs
+    generic map(
+      g_sync_edge => "negative")
+    port map (
+      clk_i    => clk_sys_i,
+      rst_n_i  => rst_sys_n_i,
+      data_i   => txpcs_timestamp_trigger_p_a,
+      synced_o => open,
+      npulse_o => open,
+      ppulse_o => rmon.tx_frame);
+
+  rmon_event_rx : gc_sync_ffs
+    generic map(
+      g_sync_edge => "negative")
+    port map (
+      clk_i    => clk_sys_i,
+      rst_n_i  => rst_sys_n_i,
+      data_i   => rxpcs_timestamp_trigger_p_a,
+      synced_o => open,
+      npulse_o => open,
+      ppulse_o => rmon.rx_frame);
+
+  f_pack_rmon_triggers(rmon, rmon_events_o(c_epevents_sz-1 downto 0));
+
+--   CS_ICON : chipscope_icon
+--    port map (
+--     CONTROL0 => CONTROL0);
+--   CS_ILA : chipscope_ila
+--    port map (
+--      CONTROL => CONTROL0,
+--      CLK     => phy_ref_clk_i,
+--      TRIG0   => TRIG0,
+--      TRIG1   => TRIG1,
+--      TRIG2   => TRIG2,
+--      TRIG3   => TRIG3);
+-- 
+--   TRIG0(15    downto   0) <= phy_rx_data_i;
+--   TRIG0(17    downto  16) <= phy_rx_k_i;
+--   TRIG0(              18) <= phy_rx_enc_err_i;
+--   TRIG0(23    downto  19) <= phy_rx_bitslide_i;
+
+  -- Drive unsued GMII outputs
+  gmii_txd_o   <= (others => '0');
+  gmii_tx_en_o <= '0';
+  gmii_tx_er_o <= '0';
+
+end syn;
+
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/xwr_endpoint.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/xwr_endpoint.vhd
new file mode 100644
index 000000000..b5d64008a
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/xwr_endpoint.vhd
@@ -0,0 +1,533 @@
+-------------------------------------------------------------------------------
+-- Title      : 1000base-X MAC/Endpoint - top level
+-- Project    : White Rabbit
+-------------------------------------------------------------------------------
+-- File       : xwr_endpoint.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2010-04-26
+-- Last update: 2017-02-20
+-- Platform   : FPGA-generic
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Description: Struct-ized wrapper for WR Endpoint.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2011 - 2012 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+
+use work.endpoint_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.wishbone_pkg.all;
+
+entity xwr_endpoint is
+  
+  generic (
+    g_interface_mode        : t_wishbone_interface_mode      := CLASSIC;
+    g_address_granularity   : t_wishbone_address_granularity := WORD;
+    g_simulation            : boolean                        := false;
+    g_tx_force_gap_length   : integer                        := 0;
+    g_tx_runt_padding       : boolean                        := false;
+    g_pcs_16bit             : boolean                        := false;
+    g_records_for_phy       : boolean                        := false;
+    g_rx_buffer_size        : integer                        := 1024;
+    g_with_rx_buffer        : boolean                        := true;
+    g_with_flow_control     : boolean                        := true;
+    g_with_timestamper      : boolean                        := true;
+    g_with_dpi_classifier   : boolean                        := true;
+    g_with_vlans            : boolean                        := true;
+    g_with_rtu              : boolean                        := true;
+    g_with_leds             : boolean                        := true;
+    g_with_dmtd             : boolean                        := true;
+    g_with_packet_injection : boolean                        := false;
+    g_use_new_rxcrc         : boolean                        := false;
+    g_use_new_txcrc         : boolean                        := false;
+    g_with_stop_traffic     : boolean                        := false
+    );
+  port (
+
+-------------------------------------------------------------------------------
+-- Clocks
+-------------------------------------------------------------------------------
+
+-- Endpoint transmit reference clock. Must be 125 MHz +- 100 ppm
+    clk_ref_i : in std_logic;
+
+-- reference clock / 2 (62.5 MHz, in-phase with refclk)
+    clk_sys_i : in std_logic;
+
+    clk_dmtd_i : in std_logic := '0';
+
+-- resets for various clock domains
+    rst_sys_n_i   : in std_logic;
+    rst_ref_n_i   : in std_logic;
+    rst_dmtd_n_i  : in std_logic;
+    rst_txclk_n_i : in std_logic;
+    rst_rxclk_n_i : in std_logic;
+
+-- PPS input (1 clk_ref_i cycle HI) for synchronizing timestamp counter
+    pps_csync_p1_i : in std_logic := '0';
+
+-- PPS valid input (clk_ref_i domain), when 1, the external PPS generator/servo
+-- is not adjusting the time scale, so we can safely timestamp.
+    pps_valid_i : in std_logic := '1';
+
+-------------------------------------------------------------------------------
+-- PHY Interace (8/16 bit PCS)
+-------------------------------------------------------------------------------    
+
+    -- 1st option is to use std_logic based I/Os
+    phy_rst_o            : out std_logic;
+    phy_loopen_o         : out std_logic;
+    phy_loopen_vec_o     : out std_logic_vector(2 downto 0);
+    phy_tx_prbs_sel_o    : out std_logic_vector(2 downto 0);
+    phy_sfp_tx_fault_i   : in std_logic;
+    phy_sfp_los_i        : in std_logic;
+    phy_sfp_tx_disable_o : out std_logic;
+    phy_rdy_i            : in  std_logic;
+
+    phy_ref_clk_i      : in  std_logic := '0';
+    phy_tx_data_o      : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
+    phy_tx_k_o         : out std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
+    phy_tx_disparity_i : in  std_logic := '0';
+    phy_tx_enc_err_i   : in  std_logic := '0';
+
+    phy_rx_data_i     : in std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
+    phy_rx_clk_i      : in std_logic                     := '0';
+    phy_rx_k_i        : in std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
+    phy_rx_enc_err_i  : in std_logic                     := '0';
+    phy_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
+
+    -- 2nd option is to use record-based I/Os
+    phy8_o            : out t_phy_8bits_from_wrc;
+    phy8_i            : in  t_phy_8bits_to_wrc;
+    phy16_o           : out t_phy_16bits_from_wrc;
+    phy16_i           : in  t_phy_16bits_to_wrc;
+
+-------------------------------------------------------------------------------
+-- GMII Interface (8-bit)
+-------------------------------------------------------------------------------
+
+    gmii_tx_clk_i : in  std_logic := '0';
+    gmii_txd_o    : out std_logic_vector(7 downto 0);
+    gmii_tx_en_o  : out std_logic;
+    gmii_tx_er_o  : out std_logic;
+
+    gmii_rx_clk_i : in std_logic                    := '0';
+    gmii_rxd_i    : in std_logic_vector(7 downto 0) := x"00";
+    gmii_rx_er_i  : in std_logic                    := '0';
+    gmii_rx_dv_i  : in std_logic                    := '0';
+
+    ---------------------------------------------------------------------------
+    -- Wishbone I/O
+    ---------------------------------------------------------------------------
+
+    src_o : out t_wrf_source_out;
+    src_i : in  t_wrf_source_in;
+
+    snk_o : out t_wrf_sink_out;
+    snk_i : in  t_wrf_sink_in;
+
+-------------------------------------------------------------------------------
+-- TX timestamping unit interface
+-------------------------------------------------------------------------------  
+
+-- Port ID value
+    txtsu_port_id_o  : out std_logic_vector(4 downto 0);
+-- Frame ID value
+    txtsu_frame_id_o : out std_logic_vector(16 -1 downto 0);
+
+-- TX Timestamp and correctness info
+    txtsu_ts_value_o     : out std_logic_vector(28 + 4 - 1 downto 0);
+    txtsu_ts_incorrect_o : out std_logic;
+
+-- TX timestamp strobe: HI tells the TX timestamping unit that a timestamp is
+-- available on txtsu_ts_value_o, txtsu_fid_o andd txtsu_port_id_o. The correctness
+-- of the timestamping is indiacted on txtsu_ts_incorrect_o. Line remains HI
+-- until assertion of txtsu_ack_i.
+    txtsu_stb_o : out std_logic;
+
+-- TX timestamp acknowledge: HI indicates that TXTSU has successfully received
+-- the timestamp
+    txtsu_ack_i : in std_logic := '1';
+
+-------------------------------------------------------------------------------
+-- RTU interface
+-------------------------------------------------------------------------------
+
+-- 1 indicates that coresponding RTU port is full.
+    rtu_full_i : in std_logic := '0';
+
+-- 1 indicates that coresponding RTU port is almost full.
+    rtu_almost_full_i : in std_logic := '0';
+
+-- request strobe, single HI pulse begins evaluation of the request. 
+    rtu_rq_strobe_p1_o : out std_logic;
+    rtu_rq_abort_o         : out std_logic;
+
+-- source and destination MAC addresses extracted from the packet header
+    rtu_rq_smac_o : out std_logic_vector(48 - 1 downto 0);
+    rtu_rq_dmac_o : out std_logic_vector(48 - 1 downto 0);
+
+-- VLAN id (extracted from the header for TRUNK ports and assigned by the port
+-- for ACCESS ports)
+    rtu_rq_vid_o : out std_logic_vector(12 - 1 downto 0);
+
+-- HI means that packet has valid assigned a valid VID (low - packet is untagged)
+    rtu_rq_has_vid_o : out std_logic;
+
+-- packet priority (either extracted from the header or assigned per port).
+    rtu_rq_prio_o : out std_logic_vector(3 - 1 downto 0);
+
+-- HI indicates that packet has assigned priority.
+    rtu_rq_has_prio_o : out std_logic;
+
+-------------------------------------------------------------------------------   
+-- Wishbone bus
+-------------------------------------------------------------------------------
+
+    wb_i : in  t_wishbone_slave_in;
+    wb_o : out t_wishbone_slave_out;
+
+-------------------------------------------------------------------------------
+-- direct output of packet filter  (for TRU/HW-RSTP)
+-------------------------------------------------------------------------------
+   
+   pfilter_pclass_o       : out   std_logic_vector(7 downto 0);
+   pfilter_drop_o         : out   std_logic;
+   pfilter_done_o         : out   std_logic;
+
+-------------------------------------------------------------------------------
+-- control of PAUSE sending (ML: not used and not tested... TRU uses packet injection) -- 
+-------------------------------------------------------------------------------
+   
+   fc_tx_pause_req_i   : in std_logic := '0';
+   fc_tx_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000";
+   fc_tx_pause_ready_o : out std_logic;
+
+-------------------------------------------------------------------------------
+-- information about received PAUSE (for SWcore)
+-------------------------------------------------------------------------------
+
+   fc_rx_pause_start_p_o     : out std_logic;
+   fc_rx_pause_quanta_o      : out std_logic_vector(15 downto 0);
+   fc_rx_pause_prio_mask_o   : out std_logic_vector(7 downto 0);
+   fc_rx_buffer_occupation_o : out std_logic_vector(7 downto 0);
+-------------------------------------------------------------------------------
+-- Packet Injection Interface (for TRU/HW-RSTP)
+-------------------------------------------------------------------------------
+
+-- injection request: triggers transmission of the packet to be injected,
+-- allowed when inject_ready = 1
+    inject_req_i : in std_logic := '0';
+
+-- injection ready flag: when true, user application can request asynchronous
+-- injection of a predefined packet
+    inject_ready_o : out std_logic;
+
+-- injection template selection (8 available)
+    inject_packet_sel_i : in std_logic_vector(2 downto 0) := "000";
+
+-- user-defined value to be embedded in the injected packet at a predefined
+-- location
+    inject_user_value_i : in std_logic_vector(15 downto 0) := x"0000";
+
+-------------------------------------------------------------------------------
+-- Misc stuff
+-------------------------------------------------------------------------------
+    rmon_events_o        : out std_logic_vector(c_epevents_sz-1 downto 0);
+
+    txts_o     : out std_logic; 		-- 2013-Nov-28 peterj added for debugging/calibration
+    rxts_o     : out std_logic; 		-- 2013-Nov-28 peterj added for debugging/calibration
+
+    led_link_o : out std_logic;
+    led_act_o  : out std_logic;
+
+    link_kill_i : in  std_logic := '0';
+    link_up_o   : out std_logic;
+    stop_traffic_i : in std_logic := '0';
+    dbg_tx_pcs_wr_count_o     : out std_logic_vector(5+4 downto 0);
+    dbg_tx_pcs_rd_count_o     : out std_logic_vector(5+4 downto 0);
+    nice_dbg_o  : out t_dbg_ep);
+
+end xwr_endpoint;
+
+architecture syn of xwr_endpoint is
+
+  signal phy_rst          : std_logic;
+  signal phy_loopen       : std_logic;
+  signal phy_loopen_vec   : std_logic_vector(2 downto 0);
+  signal phy_tx_data      : std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
+  signal phy_tx_k         : std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
+  signal phy_tx_prbs_sel  : std_logic_vector(2 downto 0);
+  signal sfp_tx_disable   : std_logic;
+  signal phy_tx_clk       : std_logic;
+
+  signal phy_tx_disparity : std_logic;
+  signal phy_tx_enc_err   : std_logic;
+  signal phy_rx_data      : std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
+  signal phy_rx_clk       : std_logic;
+  signal phy_rx_k         : std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
+  signal phy_rx_enc_err   : std_logic;
+  signal phy_rx_bts       : std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0);
+  signal phy_rdy          : std_logic;
+  signal sfp_tx_fault     : std_logic;
+  signal sfp_los          : std_logic;
+
+begin
+
+  U_Wrapped_Endpoint : wr_endpoint
+    generic map (
+      g_interface_mode      => g_interface_mode,
+      g_address_granularity => g_address_granularity,
+      g_tx_force_gap_length => g_tx_force_gap_length,
+      g_tx_runt_padding     => g_tx_runt_padding,
+      g_simulation            => g_simulation,
+      g_pcs_16bit             => g_pcs_16bit,
+      g_rx_buffer_size        => g_rx_buffer_size,
+      g_with_rx_buffer        => g_with_rx_buffer,
+      g_with_flow_control     => g_with_flow_control,
+      g_with_timestamper      => g_with_timestamper,
+      g_with_dpi_classifier   => g_with_dpi_classifier,
+      g_with_vlans            => g_with_vlans,
+      g_with_rtu              => g_with_rtu,
+      g_with_leds             => g_with_leds,
+      g_with_dmtd             => g_with_dmtd,
+      g_with_packet_injection => g_with_packet_injection,
+      g_use_new_rxcrc         => g_use_new_rxcrc,
+      g_use_new_txcrc         => g_use_new_txcrc,
+      g_with_stop_traffic     => g_with_stop_traffic)
+    port map (
+      clk_ref_i            => clk_ref_i,
+      clk_sys_i            => clk_sys_i,
+      clk_dmtd_i           => clk_dmtd_i,
+      rst_sys_n_i          => rst_sys_n_i,
+      rst_ref_n_i          => rst_ref_n_i,
+      rst_dmtd_n_i         => rst_dmtd_n_i,
+      rst_txclk_n_i        => rst_txclk_n_i,
+      rst_rxclk_n_i        => rst_rxclk_n_i,
+      pps_csync_p1_i       => pps_csync_p1_i,
+      pps_valid_i          => pps_valid_i,
+
+      phy_rst_o            => phy_rst,
+      phy_loopen_o         => phy_loopen,
+      phy_loopen_vec_o     => phy_loopen_vec,
+      phy_tx_prbs_sel_o    => phy_tx_prbs_sel,
+      phy_rdy_i            => phy_rdy,
+
+      phy_sfp_tx_fault_i   => sfp_tx_fault,
+      phy_sfp_los_i        => sfp_los,
+      phy_sfp_tx_disable_o => sfp_tx_disable,
+
+      phy_ref_clk_i        => phy_tx_clk,
+      phy_tx_data_o        => phy_tx_data,
+      phy_tx_k_o           => phy_tx_k,
+      phy_tx_disparity_i   => phy_tx_disparity,
+      phy_tx_enc_err_i     => phy_tx_enc_err,
+      phy_rx_data_i        => phy_rx_data,
+      phy_rx_clk_i         => phy_rx_clk,
+      phy_rx_k_i           => phy_rx_k,
+      phy_rx_enc_err_i     => phy_rx_enc_err,
+      phy_rx_bitslide_i    => phy_rx_bts,
+
+      gmii_tx_clk_i        => gmii_tx_clk_i,
+      gmii_txd_o           => gmii_txd_o,
+      gmii_tx_en_o         => gmii_tx_en_o,
+      gmii_tx_er_o         => gmii_tx_er_o,
+      gmii_rx_clk_i        => gmii_rx_clk_i,
+      gmii_rxd_i           => gmii_rxd_i,
+      gmii_rx_er_i         => gmii_rx_er_i,
+      gmii_rx_dv_i         => gmii_rx_dv_i,
+      src_dat_o            => src_o.dat,
+      src_adr_o            => src_o.adr,
+      src_sel_o            => src_o.sel,
+      src_cyc_o            => src_o.cyc,
+      src_stb_o            => src_o.stb,
+      src_we_o             => src_o.we,
+      src_stall_i          => src_i.stall,
+      src_ack_i            => src_i.ack,
+      src_err_i            => src_i.err,
+      snk_dat_i            => snk_i.dat,
+      snk_adr_i            => snk_i.adr,
+      snk_sel_i            => snk_i.sel,
+      snk_cyc_i            => snk_i.cyc,
+      snk_stb_i            => snk_i.stb,
+      snk_we_i             => snk_i.we,
+      snk_stall_o          => snk_o.stall,
+      snk_ack_o            => snk_o.ack,
+      snk_err_o            => snk_o.err,
+      snk_rty_o            => snk_o.rty,
+      txtsu_port_id_o      => txtsu_port_id_o,
+      txtsu_frame_id_o     => txtsu_frame_id_o,
+      txtsu_ts_value_o     => txtsu_ts_value_o,
+      txtsu_ts_incorrect_o => txtsu_ts_incorrect_o,
+      txtsu_stb_o          => txtsu_stb_o,
+      txtsu_ack_i          => txtsu_ack_i,
+      rtu_full_i           => rtu_full_i,
+      rtu_almost_full_i    => rtu_almost_full_i,
+      rtu_rq_strobe_p1_o   => rtu_rq_strobe_p1_o,
+      rtu_rq_abort_o       => rtu_rq_abort_o,
+      rtu_rq_smac_o        => rtu_rq_smac_o,
+      rtu_rq_dmac_o        => rtu_rq_dmac_o,
+      rtu_rq_vid_o         => rtu_rq_vid_o,
+      rtu_rq_has_vid_o     => rtu_rq_has_vid_o,
+      rtu_rq_prio_o        => rtu_rq_prio_o,
+      rtu_rq_has_prio_o    => rtu_rq_has_prio_o,
+      wb_cyc_i             => wb_i.cyc,
+      wb_stb_i             => wb_i.stb,
+      wb_we_i              => wb_i.we,
+      wb_sel_i             => wb_i.sel,
+      wb_adr_i             => wb_i.adr(7 downto 0),
+      wb_dat_i             => wb_i.dat,
+      wb_dat_o             => wb_o.dat,
+      wb_ack_o             => wb_o.ack,
+      wb_stall_o           => wb_o.stall,
+      rmon_events_o        => rmon_events_o,
+      txts_o               => txts_o, 		-- 2013-Nov-28 peterj added for debugging/calibration
+      rxts_o               => rxts_o, 		-- 2013-Nov-28 peterj added for debugging/calibration
+      led_link_o           => led_link_o,
+      led_act_o            => led_act_o,
+      link_up_o            => link_up_o,
+      link_kill_i          => link_kill_i,
+      pfilter_pclass_o     => pfilter_pclass_o,
+      pfilter_drop_o       => pfilter_drop_o,
+      pfilter_done_o       => pfilter_done_o,
+      fc_tx_pause_req_i    => fc_tx_pause_req_i,
+      fc_tx_pause_delay_i  => fc_tx_pause_delay_i,
+      fc_tx_pause_ready_o  => fc_tx_pause_ready_o,
+      fc_rx_pause_start_p_o   => fc_rx_pause_start_p_o,
+      fc_rx_pause_quanta_o    => fc_rx_pause_quanta_o,
+      fc_rx_pause_prio_mask_o => fc_rx_pause_prio_mask_o,
+      fc_rx_buffer_occupation_o =>fc_rx_buffer_occupation_o,
+      inject_req_i         => inject_req_i,
+      inject_user_value_i  => inject_user_value_i,
+      inject_packet_sel_i  => inject_packet_sel_i,
+      inject_ready_o       => inject_ready_o,
+      stop_traffic_i       => stop_traffic_i,
+      dbg_tx_pcs_wr_count_o=>dbg_tx_pcs_wr_count_o,
+      dbg_tx_pcs_rd_count_o=>dbg_tx_pcs_rd_count_o,
+      nice_dbg_o           => nice_dbg_o);
+
+  wb_o.err <= '0';
+  wb_o.rty <= '0';
+  wb_o.int <= '0';
+
+
+  -- Record-based PHY connections, depending on 8/16-bit PCS
+  GEN_16BIT_IF: if g_pcs_16bit and g_records_for_phy generate
+    phy16_o.rst            <= phy_rst;
+    phy16_o.loopen         <= phy_loopen;
+    phy16_o.loopen_vec     <= phy_loopen_vec;
+    phy16_o.tx_data        <= phy_tx_data;
+    phy16_o.tx_k           <= phy_tx_k;
+    phy16_o.tx_prbs_sel    <= phy_tx_prbs_sel;
+    phy16_o.sfp_tx_disable <= sfp_tx_disable;
+
+    phy_tx_clk       <= phy16_i.ref_clk;
+    phy_tx_disparity <= phy16_i.tx_disparity;
+    phy_tx_enc_err   <= phy16_i.tx_enc_err;
+    phy_rx_data      <= phy16_i.rx_data;
+    phy_rx_clk       <= phy16_i.rx_clk;
+    phy_rx_k         <= phy16_i.rx_k;
+    phy_rx_enc_err   <= phy16_i.rx_enc_err;
+    phy_rx_bts       <= phy16_i.rx_bitslide;
+    phy_rdy          <= phy16_i.rdy;
+    sfp_tx_fault     <= phy16_i.sfp_tx_fault;
+    sfp_los          <= phy16_i.sfp_los;
+
+    -- drive unused ports with dummy values
+    phy8_o               <= c_dummy_phy8_from_wrc;
+    phy_rst_o            <= '0';
+    phy_loopen_o         <= '0';
+    phy_tx_data_o        <= (others => '0');
+    phy_tx_k_o           <= (others => '0');
+    phy_loopen_vec_o     <= (others => '0');
+    phy_tx_prbs_sel_o    <= (others => '0');
+    phy_sfp_tx_disable_o <= '0';
+  end generate;
+
+  GEN_8BIT_IF: if not g_pcs_16bit and g_records_for_phy generate
+    phy8_o.rst            <= phy_rst;
+    phy8_o.loopen         <= phy_loopen;
+    phy8_o.loopen_vec     <= phy_loopen_vec;
+    phy8_o.tx_data        <= phy_tx_data;
+    phy8_o.tx_k           <= phy_tx_k;
+    phy8_o.tx_prbs_sel    <= phy_tx_prbs_sel;
+    phy8_o.sfp_tx_disable <= sfp_tx_disable;
+
+    phy_tx_clk       <= phy8_i.ref_clk;
+    phy_tx_disparity <= phy8_i.tx_disparity;
+    phy_tx_enc_err   <= phy8_i.tx_enc_err;
+    phy_rx_data      <= phy8_i.rx_data;
+    phy_rx_clk       <= phy8_i.rx_clk;
+    phy_rx_k         <= phy8_i.rx_k;
+    phy_rx_enc_err   <= phy8_i.rx_enc_err;
+    phy_rx_bts       <= phy8_i.rx_bitslide;
+    phy_rdy          <= phy8_i.rdy;
+    sfp_tx_fault     <= phy8_i.sfp_tx_fault;
+    sfp_los          <= phy8_i.sfp_los;
+
+    -- drive unused ports with dummy values
+    phy16_o              <= c_dummy_phy16_from_wrc;
+    phy_rst_o            <= '0';
+    phy_loopen_o         <= '0';
+    phy_tx_data_o        <= (others => '0');
+    phy_tx_k_o           <= (others => '0');
+    phy_loopen_vec_o     <= (others => '0');
+    phy_tx_prbs_sel_o    <= (others => '0');
+    phy_sfp_tx_disable_o <= '0';
+  end generate;
+
+  -- backwards compatibility
+  GEN_STD_IF: if not g_records_for_phy generate
+    phy_rst_o            <= phy_rst;
+    phy_loopen_o         <= phy_loopen;
+    phy_loopen_vec_o     <= phy_loopen_vec;
+    phy_tx_data_o        <= phy_tx_data;
+    phy_tx_k_o           <= phy_tx_k;
+    phy_tx_prbs_sel_o    <= phy_tx_prbs_sel;
+    phy_sfp_tx_disable_o <= sfp_tx_disable;
+
+    phy_tx_clk       <= phy_ref_clk_i;
+    phy_tx_disparity <= phy_tx_disparity_i;
+    phy_tx_enc_err   <= phy_tx_enc_err_i;
+    phy_rx_data      <= phy_rx_data_i;
+    phy_rx_clk       <= phy_rx_clk_i;
+    phy_rx_k         <= phy_rx_k_i;
+    phy_rx_enc_err   <= phy_rx_enc_err_i;
+    phy_rx_bts       <= phy_rx_bitslide_i;
+    phy_rdy          <= phy_rdy_i;
+    sfp_tx_fault     <= phy_sfp_tx_fault_i;
+    sfp_los          <= phy_sfp_los_i;
+
+    -- drive unused ports with dummy values
+    phy8_o  <= c_dummy_phy8_from_wrc;
+    phy16_o <= c_dummy_phy16_from_wrc;
+  end generate;
+  
+end syn;
+
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_mini_nic/minic_wb_slave.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_mini_nic/minic_wb_slave.vhd
new file mode 100644
index 000000000..1a2db96a2
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_mini_nic/minic_wb_slave.vhd
@@ -0,0 +1,602 @@
+---------------------------------------------------------------------------------------
+-- Title          : Wishbone slave core for Mini NIC for WhiteRabbit
+---------------------------------------------------------------------------------------
+-- File           : minic_wb_slave.vhd
+-- Author         : auto-generated by wbgen2 from mini_nic.wb
+-- Created        : Wed Aug 16 22:41:57 2017
+-- Standard       : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE mini_nic.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.wbgen2_pkg.all;
+
+use work.minic_wbgen2_pkg.all;
+
+
+entity minic_wb_slave is
+  port (
+    rst_n_i                                  : in     std_logic;
+    clk_sys_i                                : in     std_logic;
+    wb_adr_i                                 : in     std_logic_vector(4 downto 0);
+    wb_dat_i                                 : in     std_logic_vector(31 downto 0);
+    wb_dat_o                                 : out    std_logic_vector(31 downto 0);
+    wb_cyc_i                                 : in     std_logic;
+    wb_sel_i                                 : in     std_logic_vector(3 downto 0);
+    wb_stb_i                                 : in     std_logic;
+    wb_we_i                                  : in     std_logic;
+    wb_ack_o                                 : out    std_logic;
+    wb_stall_o                               : out    std_logic;
+    wb_int_o                                 : out    std_logic;
+    tx_ts_read_ack_o                         : out    std_logic;
+    irq_tx_i                                 : in     std_logic;
+    irq_tx_ack_o                             : out    std_logic;
+    irq_tx_mask_o                            : out    std_logic;
+    irq_rx_i                                 : in     std_logic;
+    irq_rx_ack_o                             : out    std_logic;
+    irq_txts_i                               : in     std_logic;
+    regs_i                                   : in     t_minic_in_registers;
+    regs_o                                   : out    t_minic_out_registers
+  );
+end minic_wb_slave;
+
+architecture syn of minic_wb_slave is
+
+signal minic_mcr_tx_start_dly0                  : std_logic      ;
+signal minic_mcr_tx_start_int                   : std_logic      ;
+signal minic_mcr_rx_en_int                      : std_logic      ;
+signal minic_mcr_rx_class_int                   : std_logic_vector(7 downto 0);
+signal minic_mprot_lo_int                       : std_logic_vector(15 downto 0);
+signal minic_mprot_hi_int                       : std_logic_vector(15 downto 0);
+signal eic_idr_int                              : std_logic_vector(2 downto 0);
+signal eic_idr_write_int                        : std_logic      ;
+signal eic_ier_int                              : std_logic_vector(2 downto 0);
+signal eic_ier_write_int                        : std_logic      ;
+signal eic_imr_int                              : std_logic_vector(2 downto 0);
+signal eic_isr_clear_int                        : std_logic_vector(2 downto 0);
+signal eic_isr_status_int                       : std_logic_vector(2 downto 0);
+signal eic_irq_ack_int                          : std_logic_vector(2 downto 0);
+signal eic_isr_write_int                        : std_logic      ;
+signal irq_inputs_vector_int                    : std_logic_vector(2 downto 0);
+signal ack_sreg                                 : std_logic_vector(9 downto 0);
+signal rddata_reg                               : std_logic_vector(31 downto 0);
+signal wrdata_reg                               : std_logic_vector(31 downto 0);
+signal rwaddr_reg                               : std_logic_vector(4 downto 0);
+signal ack_in_progress                          : std_logic      ;
+
+begin
+-- Some internal signals assignments
+  wrdata_reg <= wb_dat_i;
+-- 
+-- Main register bank access process.
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ack_sreg <= "0000000000";
+      ack_in_progress <= '0';
+      rddata_reg <= "00000000000000000000000000000000";
+      minic_mcr_tx_start_int <= '0';
+      minic_mcr_rx_en_int <= '0';
+      minic_mcr_rx_class_int <= "00000000";
+      regs_o.tx_fifo_dat_wr_o <= '0';
+      regs_o.tx_fifo_type_wr_o <= '0';
+      tx_ts_read_ack_o <= '0';
+      minic_mprot_lo_int <= "0000000000000000";
+      minic_mprot_hi_int <= "0000000000000000";
+      eic_idr_write_int <= '0';
+      eic_ier_write_int <= '0';
+      eic_isr_write_int <= '0';
+    elsif rising_edge(clk_sys_i) then
+-- advance the ACK generator shift register
+      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
+      ack_sreg(9) <= '0';
+      if (ack_in_progress = '1') then
+        if (ack_sreg(0) = '1') then
+          minic_mcr_tx_start_int <= '0';
+          regs_o.tx_fifo_dat_wr_o <= '0';
+          regs_o.tx_fifo_type_wr_o <= '0';
+          tx_ts_read_ack_o <= '0';
+          eic_idr_write_int <= '0';
+          eic_ier_write_int <= '0';
+          eic_isr_write_int <= '0';
+          ack_in_progress <= '0';
+        else
+          regs_o.tx_fifo_dat_wr_o <= '0';
+          regs_o.tx_fifo_type_wr_o <= '0';
+        end if;
+      else
+        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
+          case rwaddr_reg(4 downto 0) is
+          when "00000" => 
+            if (wb_we_i = '1') then
+              minic_mcr_tx_start_int <= wrdata_reg(0);
+              minic_mcr_rx_en_int <= wrdata_reg(10);
+              minic_mcr_rx_class_int <= wrdata_reg(23 downto 16);
+            end if;
+            rddata_reg(0) <= '0';
+            rddata_reg(1) <= regs_i.mcr_tx_idle_i;
+            rddata_reg(2) <= regs_i.mcr_tx_error_i;
+            rddata_reg(3) <= regs_i.mcr_tx_empty_i;
+            rddata_reg(4) <= regs_i.mcr_tx_full_i;
+            rddata_reg(8) <= regs_i.mcr_rx_ready_i;
+            rddata_reg(9) <= regs_i.mcr_rx_error_i;
+            rddata_reg(10) <= minic_mcr_rx_en_int;
+            rddata_reg(11) <= regs_i.mcr_tx_ts_ready_i;
+            rddata_reg(12) <= regs_i.mcr_rx_empty_i;
+            rddata_reg(13) <= regs_i.mcr_rx_full_i;
+            rddata_reg(23 downto 16) <= minic_mcr_rx_class_int;
+            rddata_reg(27 downto 24) <= regs_i.mcr_ver_i;
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(2) <= '1';
+            ack_in_progress <= '1';
+          when "00001" => 
+            if (wb_we_i = '1') then
+              regs_o.tx_fifo_dat_wr_o <= '1';
+              regs_o.tx_fifo_type_wr_o <= '1';
+            end if;
+            rddata_reg(0) <= 'X';
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00010" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(15 downto 0) <= regs_i.rx_fifo_dat_i;
+            rddata_reg(17 downto 16) <= regs_i.rx_fifo_type_i;
+            rddata_reg(30) <= regs_i.rx_fifo_empty_i;
+            rddata_reg(31) <= regs_i.rx_fifo_full_i;
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00011" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(0) <= 'X';
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00100" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(0) <= 'X';
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00101" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(0) <= regs_i.tsr0_valid_i;
+            rddata_reg(5 downto 1) <= regs_i.tsr0_pid_i;
+            rddata_reg(21 downto 6) <= regs_i.tsr0_fid_i;
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00110" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.tsr1_tsval_i;
+            tx_ts_read_ack_o <= '1';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00111" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(23 downto 0) <= regs_i.dbgr_irq_cnt_i;
+            rddata_reg(24) <= regs_i.dbgr_wb_irq_val_i;
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01000" => 
+            if (wb_we_i = '1') then
+              minic_mprot_lo_int <= wrdata_reg(15 downto 0);
+              minic_mprot_hi_int <= wrdata_reg(31 downto 16);
+            end if;
+            rddata_reg(15 downto 0) <= minic_mprot_lo_int;
+            rddata_reg(31 downto 16) <= minic_mprot_hi_int;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "10000" => 
+            if (wb_we_i = '1') then
+              eic_idr_write_int <= '1';
+            end if;
+            rddata_reg(0) <= 'X';
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "10001" => 
+            if (wb_we_i = '1') then
+              eic_ier_write_int <= '1';
+            end if;
+            rddata_reg(0) <= 'X';
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "10010" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(2 downto 0) <= eic_imr_int(2 downto 0);
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "10011" => 
+            if (wb_we_i = '1') then
+              eic_isr_write_int <= '1';
+            end if;
+            rddata_reg(2 downto 0) <= eic_isr_status_int(2 downto 0);
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when others =>
+-- prevent the slave from hanging the bus on invalid address
+            ack_in_progress <= '1';
+            ack_sreg(0) <= '1';
+          end case;
+        end if;
+      end if;
+    end if;
+  end process;
+  
+  
+-- Drive the data output bus
+  wb_dat_o <= rddata_reg;
+-- TX DMA start
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      minic_mcr_tx_start_dly0 <= '0';
+      regs_o.mcr_tx_start_o <= '0';
+    elsif rising_edge(clk_sys_i) then
+      minic_mcr_tx_start_dly0 <= minic_mcr_tx_start_int;
+      regs_o.mcr_tx_start_o <= minic_mcr_tx_start_int and (not minic_mcr_tx_start_dly0);
+    end if;
+  end process;
+  
+  
+-- TX DMA idle
+-- TX DMA error
+-- TX_FIFO_EMPTY
+-- TX_FIFO_FULL
+-- RX DMA ready
+-- RX DMA error
+-- RX DMA enable
+  regs_o.mcr_rx_en_o <= minic_mcr_rx_en_int;
+-- TX TS ready
+-- RX_FIFO_EMPTY
+-- RX_FIFO_FULL
+-- RX Accepted Packet Classes
+  regs_o.mcr_rx_class_o <= minic_mcr_rx_class_int;
+-- Regs map version
+-- Data to send
+-- pass-through field: Data to send in register: TX FIFO Register
+  regs_o.tx_fifo_dat_o <= wrdata_reg(15 downto 0);
+-- Data type
+-- pass-through field: Data type in register: TX FIFO Register
+  regs_o.tx_fifo_type_o <= wrdata_reg(17 downto 16);
+-- Data to send
+-- Data type
+-- RX_FIFO_EMPTY
+-- RX_FIFO_FULL
+-- Timestamp valid
+-- Port ID
+-- Frame ID
+-- Timestamp value
+-- interrupt counter
+-- status of wb_irq_o line
+-- address range lo
+  regs_o.mprot_lo_o <= minic_mprot_lo_int;
+-- address range hi
+  regs_o.mprot_hi_o <= minic_mprot_hi_int;
+-- extra code for reg/fifo/mem: Interrupt disable register
+  eic_idr_int(2 downto 0) <= wrdata_reg(2 downto 0);
+-- extra code for reg/fifo/mem: Interrupt enable register
+  eic_ier_int(2 downto 0) <= wrdata_reg(2 downto 0);
+-- extra code for reg/fifo/mem: Interrupt status register
+  eic_isr_clear_int(2 downto 0) <= wrdata_reg(2 downto 0);
+-- extra code for reg/fifo/mem: IRQ_CONTROLLER
+  eic_irq_controller_inst : wbgen2_eic
+    generic map (
+      g_num_interrupts     => 3,
+      g_irq00_mode         => 3,
+      g_irq01_mode         => 3,
+      g_irq02_mode         => 3,
+      g_irq03_mode         => 0,
+      g_irq04_mode         => 0,
+      g_irq05_mode         => 0,
+      g_irq06_mode         => 0,
+      g_irq07_mode         => 0,
+      g_irq08_mode         => 0,
+      g_irq09_mode         => 0,
+      g_irq0a_mode         => 0,
+      g_irq0b_mode         => 0,
+      g_irq0c_mode         => 0,
+      g_irq0d_mode         => 0,
+      g_irq0e_mode         => 0,
+      g_irq0f_mode         => 0,
+      g_irq10_mode         => 0,
+      g_irq11_mode         => 0,
+      g_irq12_mode         => 0,
+      g_irq13_mode         => 0,
+      g_irq14_mode         => 0,
+      g_irq15_mode         => 0,
+      g_irq16_mode         => 0,
+      g_irq17_mode         => 0,
+      g_irq18_mode         => 0,
+      g_irq19_mode         => 0,
+      g_irq1a_mode         => 0,
+      g_irq1b_mode         => 0,
+      g_irq1c_mode         => 0,
+      g_irq1d_mode         => 0,
+      g_irq1e_mode         => 0,
+      g_irq1f_mode         => 0
+    )
+    port map (
+      clk_i                => clk_sys_i,
+      rst_n_i              => rst_n_i,
+      irq_i                => irq_inputs_vector_int,
+      irq_ack_o            => eic_irq_ack_int,
+      reg_imr_o            => eic_imr_int,
+      reg_ier_i            => eic_ier_int,
+      reg_ier_wr_stb_i     => eic_ier_write_int,
+      reg_idr_i            => eic_idr_int,
+      reg_idr_wr_stb_i     => eic_idr_write_int,
+      reg_isr_o            => eic_isr_status_int,
+      reg_isr_i            => eic_isr_clear_int,
+      reg_isr_wr_stb_i     => eic_isr_write_int,
+      wb_irq_o             => wb_int_o
+    );
+  
+  irq_inputs_vector_int(0) <= irq_tx_i;
+  irq_tx_ack_o <= eic_irq_ack_int(0);
+  irq_tx_mask_o <= eic_imr_int(0);
+  irq_inputs_vector_int(1) <= irq_rx_i;
+  irq_rx_ack_o <= eic_irq_ack_int(1);
+  irq_inputs_vector_int(2) <= irq_txts_i;
+  rwaddr_reg <= wb_adr_i;
+  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
+-- ACK signal generation. Just pass the LSB of ACK counter.
+  wb_ack_o <= ack_sreg(0);
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_mini_nic/minic_wbgen2_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_mini_nic/minic_wbgen2_pkg.vhd
new file mode 100644
index 000000000..585a0513d
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_mini_nic/minic_wbgen2_pkg.vhd
@@ -0,0 +1,145 @@
+---------------------------------------------------------------------------------------
+-- Title          : Wishbone slave core for Mini NIC for WhiteRabbit
+---------------------------------------------------------------------------------------
+-- File           : minic_wbgen2_pkg.vhd
+-- Author         : auto-generated by wbgen2 from mini_nic.wb
+-- Created        : Wed Aug 16 22:41:57 2017
+-- Standard       : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE mini_nic.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.wbgen2_pkg.all;
+
+package minic_wbgen2_pkg is
+  
+  
+  -- Input registers (user design -> WB slave)
+  
+  type t_minic_in_registers is record
+    mcr_tx_idle_i                            : std_logic;
+    mcr_tx_error_i                           : std_logic;
+    mcr_tx_empty_i                           : std_logic;
+    mcr_tx_full_i                            : std_logic;
+    mcr_rx_ready_i                           : std_logic;
+    mcr_rx_error_i                           : std_logic;
+    mcr_tx_ts_ready_i                        : std_logic;
+    mcr_rx_empty_i                           : std_logic;
+    mcr_rx_full_i                            : std_logic;
+    mcr_ver_i                                : std_logic_vector(3 downto 0);
+    rx_fifo_dat_i                            : std_logic_vector(15 downto 0);
+    rx_fifo_type_i                           : std_logic_vector(1 downto 0);
+    rx_fifo_empty_i                          : std_logic;
+    rx_fifo_full_i                           : std_logic;
+    tsr0_valid_i                             : std_logic;
+    tsr0_pid_i                               : std_logic_vector(4 downto 0);
+    tsr0_fid_i                               : std_logic_vector(15 downto 0);
+    tsr1_tsval_i                             : std_logic_vector(31 downto 0);
+    dbgr_irq_cnt_i                           : std_logic_vector(23 downto 0);
+    dbgr_wb_irq_val_i                        : std_logic;
+    end record;
+  
+  constant c_minic_in_registers_init_value: t_minic_in_registers := (
+    mcr_tx_idle_i => '0',
+    mcr_tx_error_i => '0',
+    mcr_tx_empty_i => '0',
+    mcr_tx_full_i => '0',
+    mcr_rx_ready_i => '0',
+    mcr_rx_error_i => '0',
+    mcr_tx_ts_ready_i => '0',
+    mcr_rx_empty_i => '0',
+    mcr_rx_full_i => '0',
+    mcr_ver_i => (others => '0'),
+    rx_fifo_dat_i => (others => '0'),
+    rx_fifo_type_i => (others => '0'),
+    rx_fifo_empty_i => '0',
+    rx_fifo_full_i => '0',
+    tsr0_valid_i => '0',
+    tsr0_pid_i => (others => '0'),
+    tsr0_fid_i => (others => '0'),
+    tsr1_tsval_i => (others => '0'),
+    dbgr_irq_cnt_i => (others => '0'),
+    dbgr_wb_irq_val_i => '0'
+    );
+    
+    -- Output registers (WB slave -> user design)
+    
+    type t_minic_out_registers is record
+      mcr_tx_start_o                           : std_logic;
+      mcr_rx_en_o                              : std_logic;
+      mcr_rx_class_o                           : std_logic_vector(7 downto 0);
+      tx_fifo_dat_o                            : std_logic_vector(15 downto 0);
+      tx_fifo_dat_wr_o                         : std_logic;
+      tx_fifo_type_o                           : std_logic_vector(1 downto 0);
+      tx_fifo_type_wr_o                        : std_logic;
+      mprot_lo_o                               : std_logic_vector(15 downto 0);
+      mprot_hi_o                               : std_logic_vector(15 downto 0);
+      end record;
+    
+    constant c_minic_out_registers_init_value: t_minic_out_registers := (
+      mcr_tx_start_o => '0',
+      mcr_rx_en_o => '0',
+      mcr_rx_class_o => (others => '0'),
+      tx_fifo_dat_o => (others => '0'),
+      tx_fifo_dat_wr_o => '0',
+      tx_fifo_type_o => (others => '0'),
+      tx_fifo_type_wr_o => '0',
+      mprot_lo_o => (others => '0'),
+      mprot_hi_o => (others => '0')
+      );
+    function "or" (left, right: t_minic_in_registers) return t_minic_in_registers;
+    function f_x_to_zero (x:std_logic) return std_logic;
+    function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
+end package;
+
+package body minic_wbgen2_pkg is
+function f_x_to_zero (x:std_logic) return std_logic is
+begin
+if x = '1' then
+return '1';
+else
+return '0';
+end if;
+end function;
+function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
+variable tmp: std_logic_vector(x'length-1 downto 0);
+begin
+for i in 0 to x'length-1 loop
+if x(i) = '1' then
+tmp(i):= '1';
+else
+tmp(i):= '0';
+end if; 
+end loop; 
+return tmp;
+end function;
+function "or" (left, right: t_minic_in_registers) return t_minic_in_registers is
+variable tmp: t_minic_in_registers;
+begin
+tmp.mcr_tx_idle_i := f_x_to_zero(left.mcr_tx_idle_i) or f_x_to_zero(right.mcr_tx_idle_i);
+tmp.mcr_tx_error_i := f_x_to_zero(left.mcr_tx_error_i) or f_x_to_zero(right.mcr_tx_error_i);
+tmp.mcr_tx_empty_i := f_x_to_zero(left.mcr_tx_empty_i) or f_x_to_zero(right.mcr_tx_empty_i);
+tmp.mcr_tx_full_i := f_x_to_zero(left.mcr_tx_full_i) or f_x_to_zero(right.mcr_tx_full_i);
+tmp.mcr_rx_ready_i := f_x_to_zero(left.mcr_rx_ready_i) or f_x_to_zero(right.mcr_rx_ready_i);
+tmp.mcr_rx_error_i := f_x_to_zero(left.mcr_rx_error_i) or f_x_to_zero(right.mcr_rx_error_i);
+tmp.mcr_tx_ts_ready_i := f_x_to_zero(left.mcr_tx_ts_ready_i) or f_x_to_zero(right.mcr_tx_ts_ready_i);
+tmp.mcr_rx_empty_i := f_x_to_zero(left.mcr_rx_empty_i) or f_x_to_zero(right.mcr_rx_empty_i);
+tmp.mcr_rx_full_i := f_x_to_zero(left.mcr_rx_full_i) or f_x_to_zero(right.mcr_rx_full_i);
+tmp.mcr_ver_i := f_x_to_zero(left.mcr_ver_i) or f_x_to_zero(right.mcr_ver_i);
+tmp.rx_fifo_dat_i := f_x_to_zero(left.rx_fifo_dat_i) or f_x_to_zero(right.rx_fifo_dat_i);
+tmp.rx_fifo_type_i := f_x_to_zero(left.rx_fifo_type_i) or f_x_to_zero(right.rx_fifo_type_i);
+tmp.rx_fifo_empty_i := f_x_to_zero(left.rx_fifo_empty_i) or f_x_to_zero(right.rx_fifo_empty_i);
+tmp.rx_fifo_full_i := f_x_to_zero(left.rx_fifo_full_i) or f_x_to_zero(right.rx_fifo_full_i);
+tmp.tsr0_valid_i := f_x_to_zero(left.tsr0_valid_i) or f_x_to_zero(right.tsr0_valid_i);
+tmp.tsr0_pid_i := f_x_to_zero(left.tsr0_pid_i) or f_x_to_zero(right.tsr0_pid_i);
+tmp.tsr0_fid_i := f_x_to_zero(left.tsr0_fid_i) or f_x_to_zero(right.tsr0_fid_i);
+tmp.tsr1_tsval_i := f_x_to_zero(left.tsr1_tsval_i) or f_x_to_zero(right.tsr1_tsval_i);
+tmp.dbgr_irq_cnt_i := f_x_to_zero(left.dbgr_irq_cnt_i) or f_x_to_zero(right.dbgr_irq_cnt_i);
+tmp.dbgr_wb_irq_val_i := f_x_to_zero(left.dbgr_wb_irq_val_i) or f_x_to_zero(right.dbgr_wb_irq_val_i);
+return tmp;
+end function;
+end package body;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_mini_nic/wr_mini_nic.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_mini_nic/wr_mini_nic.vhd
new file mode 100644
index 000000000..3ca72931f
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_mini_nic/wr_mini_nic.vhd
@@ -0,0 +1,817 @@
+-------------------------------------------------------------------------------
+-- Title      : Mini Embedded DMA Network Interface Controller
+-- Project    : WhiteRabbit Core
+-------------------------------------------------------------------------------
+-- File       : wrsw_mini_nic.vhd
+-- Author     : Grzegorz Daniluk, Tomasz Wlostowski
+-- Company    : CERN BE-Co-HT
+-- Created    : 2010-07-26
+-- Last update: 2017-02-03
+-- Platform   : FPGA-generic
+-- Standard   : VHDL
+-------------------------------------------------------------------------------
+-- Description: Module implements a simple NIC with DMA controller. It
+-- sends/receives the packets using WR switch fabric interface (see the
+-- wrsw_endpoint.vhd for the details). Packets are stored and read from the
+-- system memory via simple memory bus. WR endpoint-compatible TX timestamping
+-- unit is also included.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2010-2016 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2010-07-26  1.0      twlostow        Created
+-- 2010-08-16  1.0      twlostow        Bugfixes, linux compatibility added
+-- 2011-08-03  2.0      greg.d          rewritten to use pipelined Wishbone
+-- 2011-10-45  2.1      twlostow        bugfixes...
+-- 2016-10-27  3.0      greg.d          rewritten with Tx/Rx FIFOs
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.wr_fabric_pkg.all;
+use work.wishbone_pkg.all;
+use work.genram_pkg.all;
+use work.minic_wbgen2_pkg.all;
+
+
+entity wr_mini_nic is
+
+  generic (
+    g_interface_mode       : t_wishbone_interface_mode      := CLASSIC;
+    g_address_granularity  : t_wishbone_address_granularity := WORD;
+    g_tx_fifo_size         : integer                        := 1024;
+    g_rx_fifo_size         : integer                        := 2048;
+    g_buffer_little_endian : boolean                        := false);
+
+  port (
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+-------------------------------------------------------------------------------
+-- Pipelined Wishbone interface
+-------------------------------------------------------------------------------
+
+    -- WBP Master (TX)
+    src_dat_o   : out std_logic_vector(15 downto 0);
+    src_adr_o   : out std_logic_vector(1 downto 0);
+    src_sel_o   : out std_logic_vector(1 downto 0);
+    src_cyc_o   : out std_logic;
+    src_stb_o   : out std_logic;
+    src_we_o    : out std_logic;
+    src_stall_i : in  std_logic;
+    src_err_i   : in  std_logic;
+    src_ack_i   : in  std_logic;
+
+    -- WBP Slave (RX)
+    snk_dat_i   : in  std_logic_vector(15 downto 0);
+    snk_adr_i   : in  std_logic_vector(1 downto 0);
+    snk_sel_i   : in  std_logic_vector(1 downto 0);
+    snk_cyc_i   : in  std_logic;
+    snk_stb_i   : in  std_logic;
+    snk_we_i    : in  std_logic;
+    snk_stall_o : out std_logic;
+    snk_err_o   : out std_logic;
+    snk_ack_o   : out std_logic;
+
+-------------------------------------------------------------------------------
+-- TXTSU i/f
+-------------------------------------------------------------------------------
+
+    txtsu_port_id_i     : in  std_logic_vector(4 downto 0);
+    txtsu_frame_id_i    : in  std_logic_vector(16 - 1 downto 0);
+    txtsu_tsval_i       : in  std_logic_vector(28 + 4 - 1 downto 0);
+    txtsu_tsincorrect_i : in  std_logic;
+    txtsu_stb_i         : in  std_logic;
+    txtsu_ack_o         : out std_logic;
+
+-------------------------------------------------------------------------------
+-- Wishbone slave
+-------------------------------------------------------------------------------    
+
+    wb_cyc_i   : in  std_logic;
+    wb_stb_i   : in  std_logic;
+    wb_we_i    : in  std_logic;
+    wb_sel_i   : in  std_logic_vector(c_wishbone_data_width/8-1 downto 0);
+    wb_adr_i   : in  std_logic_vector(c_wishbone_address_width-1 downto 0);
+    wb_dat_i   : in  std_logic_vector(c_wishbone_data_width-1 downto 0);
+    wb_dat_o   : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+    wb_ack_o   : out std_logic;
+    wb_stall_o : out std_logic;
+    wb_int_o   : out std_logic
+    );
+end wr_mini_nic;
+
+architecture behavioral of wr_mini_nic is
+
+  constant c_NTX_TIMEOUT : integer := 100;
+  constant c_WRF_BYTESEL : std_logic_vector(1 downto 0) := "11";
+
+  component minic_wb_slave
+    port (
+      rst_n_i          : in  std_logic;
+      clk_sys_i        : in  std_logic;
+      wb_adr_i         : in  std_logic_vector(4 downto 0);
+      wb_dat_i         : in  std_logic_vector(31 downto 0);
+      wb_dat_o         : out std_logic_vector(31 downto 0);
+      wb_cyc_i         : in  std_logic;
+      wb_sel_i         : in  std_logic_vector(3 downto 0);
+      wb_stb_i         : in  std_logic;
+      wb_we_i          : in  std_logic;
+      wb_ack_o         : out std_logic;
+      wb_stall_o       : out std_logic;
+      wb_int_o         : out std_logic;
+      tx_ts_read_ack_o : out std_logic;
+      irq_tx_i         : in  std_logic;
+      irq_tx_ack_o     : out std_logic;
+      irq_tx_mask_o    : out std_logic;
+      irq_rx_i         : in  std_logic;
+      irq_rx_ack_o     : out std_logic;
+      irq_txts_i       : in  std_logic;
+      regs_i           : in  t_minic_in_registers;
+      regs_o           : out t_minic_out_registers
+    );
+  end component;
+
+  function f_swap_endian_16
+    (
+      data : std_logic_vector(15 downto 0)
+      ) return std_logic_vector is
+  begin
+    if(g_buffer_little_endian = true) then
+      return data(7 downto 0) & data(15 downto 8);
+    else
+      return data;
+    end if;
+  end function f_swap_endian_16;
+
+
+  signal src_cyc_int   : std_logic;
+  signal src_stb_int   : std_logic;
+  signal snk_stall_int : std_logic;
+
+
+-----------------------------------------------------------------------------
+-- FIFO interface signals
+-----------------------------------------------------------------------------
+
+  signal tx_fifo_d : std_logic_vector(17 downto 0);
+  signal tx_fifo_q : std_logic_vector(17 downto 0);
+  alias  txf_type is tx_fifo_q(17 downto 16);
+  alias  txf_data is tx_fifo_q(15 downto 0);
+  signal tx_fifo_we, tx_fifo_rd : std_logic;
+  signal tx_fifo_empty, tx_fifo_full : std_logic;
+  signal rx_fifo_d : std_logic_vector(17 downto 0);
+  signal rx_fifo_q : std_logic_vector(17 downto 0);
+  signal rx_fifo_we, rx_fifo_rd : std_logic;
+  signal rx_fifo_empty, rx_fifo_full : std_logic;
+  signal rx_fifo_afull : std_logic;
+
+  signal txf_ferror : std_logic;
+  signal txf_fnew   : std_logic;
+  signal tx_status_word : t_wrf_status_reg;
+
+
+-------------------------------------------------------------------------------
+-- TX FSM stuff
+-------------------------------------------------------------------------------
+
+  type t_tx_fsm_state is (TX_IDLE, TX_STATUS, TX_PACKET, TX_FLUSH, TX_END_PACKET);
+
+  signal ntx_timeout_is_zero : std_logic;
+  signal ntx_timeout         : unsigned(7 downto 0);
+
+  signal ntx_ack_count     : unsigned(2 downto 0);
+
+  signal ntx_state         : t_tx_fsm_state;
+  signal ntx_rst_ts_ready  : std_logic;
+
+  signal ntx_stored_dat : std_logic_vector(15 downto 0);
+  signal ntx_stored_type : std_logic_vector(1 downto 0);
+  signal ntx_flush_last  : std_logic;
+
+-------------------------------------------------------------------------------
+-- RX FSM stuff
+-------------------------------------------------------------------------------  
+
+  signal snk_cyc_d0 : std_logic;
+  signal nrx_sof : std_logic;
+  signal nrx_eof : std_logic;
+  alias rxf_type is rx_fifo_d(17 downto 16);
+  alias rxf_data is rx_fifo_d(15 downto 0);
+
+  type t_rx_fsm_state is (RX_WAIT_FRAME, RX_FRAME, RX_FULL);
+  signal nrx_state    : t_rx_fsm_state;
+
+-------------------------------------------------------------------------------
+-- Classic Wishbone slave signals
+-------------------------------------------------------------------------------  
+
+  signal regs_in  : t_minic_in_registers;
+  signal regs_out : t_minic_out_registers;
+
+  signal wb_in  : t_wishbone_master_in;
+  signal wb_out : t_wishbone_master_out;
+
+  signal irq_tx     : std_logic;
+  signal irq_rx_ack : std_logic;
+  signal irq_rx     : std_logic;
+
+  signal nrx_newpacket, nrx_newpacket_d0 : std_logic;
+  signal ntx_newpacket, ntx_newpacket_d0 : std_logic;
+
+  signal irq_txts    : std_logic;
+  signal irq_tx_ack  : std_logic;
+  signal irq_tx_mask : std_logic;
+
+
+  --component chipscope_ila
+  --  port (
+  --    CONTROL : inout std_logic_vector(35 downto 0);
+  --    CLK     : in    std_logic;
+  --    TRIG0   : in    std_logic_vector(31 downto 0);
+  --    TRIG1   : in    std_logic_vector(31 downto 0);
+  --    TRIG2   : in    std_logic_vector(31 downto 0);
+  --    TRIG3   : in    std_logic_vector(31 downto 0));
+  --end component;
+
+  --signal CONTROL : std_logic_vector(35 downto 0);
+  --signal CLK     : std_logic;
+  --signal TRIG0   : std_logic_vector(31 downto 0);
+  --signal TRIG1   : std_logic_vector(31 downto 0);
+  --signal TRIG2   : std_logic_vector(31 downto 0);
+  --signal TRIG3   : std_logic_vector(31 downto 0);
+
+  --component chipscope_icon
+  --  port (
+  --    CONTROL0 : inout std_logic_vector (35 downto 0));
+  --end component;
+
+begin  -- behavioral
+
+  --chipscope_ila_1 : chipscope_ila
+  --  port map (
+  --    CONTROL => CONTROL,
+  --    CLK     => clk_sys_i,
+  --    TRIG0   => TRIG0,
+  --    TRIG1   => TRIG1,
+  --    TRIG2   => TRIG2,
+  --    TRIG3   => TRIG3);
+
+  --chipscope_icon_1 : chipscope_icon
+  --  port map (
+  --    CONTROL0 => CONTROL);
+
+  regs_in.mcr_ver_i         <= x"1";
+  regs_in.dbgr_irq_cnt_i    <= (others => '0');
+  regs_in.dbgr_wb_irq_val_i <= '0';
+
+-------------------------------------------------------------------------------
+-- Tx / Rx FIFO
+-----------------------------------------------------------------------------
+  TX_FIFO: generic_sync_fifo
+    generic map(
+      g_data_width => 18, 
+      g_size       => g_tx_fifo_size,
+      g_with_almost_empty => false,
+      g_with_almost_full  => false,
+      g_with_count        => false,
+      g_show_ahead        => true)
+    port map (
+      rst_n_i => rst_n_i,
+      clk_i   => clk_sys_i,
+      d_i     => tx_fifo_d,
+      we_i    => tx_fifo_we,
+      q_o     => tx_fifo_q,
+      rd_i    => tx_fifo_rd,
+      empty_o => tx_fifo_empty,
+      full_o  => tx_fifo_full);
+
+  RX_FIFO: generic_sync_fifo
+    generic map(
+      g_data_width => 18, 
+      g_size       => g_rx_fifo_size,
+      g_with_almost_empty => false,
+      g_with_almost_full  => true,
+      g_with_count        => false,
+      g_almost_full_threshold => g_rx_fifo_size/2,
+      g_show_ahead        => true)
+    port map (
+      rst_n_i => rst_n_i,
+      clk_i   => clk_sys_i,
+      d_i     => rx_fifo_d,
+      we_i    => rx_fifo_we,
+      q_o     => rx_fifo_q,
+      rd_i    => rx_fifo_rd,
+      empty_o => rx_fifo_empty,
+      full_o  => rx_fifo_full,
+      almost_full_o => rx_fifo_afull);
+
+  tx_fifo_d  <= regs_out.tx_fifo_type_o & regs_out.tx_fifo_dat_o;
+  tx_fifo_we <= regs_out.tx_fifo_dat_wr_o and regs_out.tx_fifo_type_wr_o;
+  regs_in.mcr_tx_empty_i <= tx_fifo_empty;
+  regs_in.mcr_tx_full_i  <= tx_fifo_full;
+
+  regs_in.mcr_rx_empty_i  <= rx_fifo_empty;
+  regs_in.rx_fifo_empty_i <= rx_fifo_empty;
+  regs_in.mcr_rx_full_i   <= rx_fifo_full;
+  regs_in.rx_fifo_full_i  <= rx_fifo_full;
+  regs_in.rx_fifo_type_i  <= rx_fifo_q(17 downto 16);
+  regs_in.rx_fifo_dat_i   <= rx_fifo_q(15 downto 0);
+
+  -- sniff wb access to generate rx_fifo_rd every time the RX_FIFO register is
+  -- read
+  rx_fifo_rd <= '1' when(wb_out.cyc='1' and wb_out.stb='1' and wb_out.adr(7 downto 0)=x"02" and wb_in.ack='1') else
+                '0';
+
+-------------------------------------------------------------------------------
+-- TX Path  (Host -> Fabric)
+-------------------------------------------------------------------------------  
+
+-- helper signals to avoid big IF conditions in the FSM
+  ntx_timeout_is_zero <= '1' when (ntx_timeout = to_unsigned(0, ntx_timeout'length)) else '0';
+
+  p_count_acks : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' or src_cyc_int = '0' or src_err_i = '1' then
+        ntx_ack_count <= (others => '0');
+      else
+        if(src_stb_int = '1' and src_stall_i = '0' and src_ack_i = '0') then
+          ntx_ack_count <= ntx_ack_count + 1;
+        elsif(src_ack_i = '1' and not(src_stb_int = '1' and src_stall_i = '0')) then
+          ntx_ack_count <= ntx_ack_count - 1;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  tx_status_word <= f_unmarshall_wrf_status(tx_fifo_q(15 downto 0));
+  -- signals error in transmitted frame (set by software
+  -- by writing again status register to TX Fifo
+  txf_ferror <= '1' when (tx_fifo_empty = '0' and txf_type = c_WRF_STATUS and tx_status_word.error = '1') else
+                '0';
+  txf_fnew   <= '1' when (tx_fifo_empty = '0' and txf_type = c_WRF_STATUS and tx_status_word.error = '0') else
+                '0';
+
+  p_tx_fsm: process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if (rst_n_i = '0') then
+        src_cyc_int <= '0';
+        src_stb_int <= '0';
+        src_sel_o   <= "11";
+        src_adr_o   <= c_WRF_DATA;
+        tx_fifo_rd  <= '0';
+        ntx_rst_ts_ready <= '0';
+        ntx_state   <= TX_IDLE;
+        ntx_stored_dat <= (others=>'0');
+        ntx_stored_type <= (others=>'0');
+        ntx_flush_last <= '0';
+        ntx_newpacket  <= '0';
+      else
+        case ntx_state is
+          when TX_IDLE =>
+            regs_in.mcr_tx_error_i <= '0';
+            src_cyc_int <= '0';
+            src_stb_int <= '0';
+            src_sel_o   <= "11";
+            src_adr_o   <= txf_type;
+            ntx_timeout <= to_unsigned(c_NTX_TIMEOUT, ntx_timeout'length);
+            ntx_flush_last <= '0';
+            ntx_newpacket  <= '0';
+            if (tx_fifo_empty = '0' and txf_fnew = '0') then
+              -- if there is something in the fifo but it's not a status word,
+              -- we read until we find a valid status. In this case we indicate
+              -- that Minic is busy by driving wbreg bit tx_idle to 0.
+              tx_fifo_rd <= '1';
+              ntx_rst_ts_ready <= '0';
+              regs_in.mcr_tx_idle_i  <= '0';
+            elsif (tx_fifo_empty = '0' and txf_fnew = '1' and regs_out.mcr_tx_start_o = '1') then
+              -- we have a new frame to be sent, proceed..
+              src_cyc_int <= '1';
+              tx_fifo_rd <= '1';
+              ntx_rst_ts_ready <= '1';
+              regs_in.mcr_tx_idle_i  <= '0';
+              ntx_state  <= TX_STATUS;
+            else
+              -- wait quietly for something to be written to FIFO
+              tx_fifo_rd <= '0';
+              ntx_rst_ts_ready <= '0';
+              regs_in.mcr_tx_idle_i  <= '1';
+            end if;
+
+          when TX_STATUS =>
+            -- read first word of the frame from fifo and start transmission
+            regs_in.mcr_tx_idle_i <= '0';
+            ntx_rst_ts_ready      <= '0';
+            src_cyc_int <= '1';
+            src_stb_int <= '1';
+            src_sel_o   <= "11";
+            src_adr_o   <= c_WRF_STATUS;
+            src_dat_o   <= f_swap_endian_16(txf_data);
+            tx_fifo_rd <= '1';
+            ntx_flush_last <= '0';
+            ntx_newpacket  <= '0';
+            ntx_state <= TX_PACKET;
+
+          when TX_PACKET =>
+            regs_in.mcr_tx_idle_i <= '0';
+            ntx_rst_ts_ready      <= '0';
+            src_cyc_int <= '1';
+            ntx_newpacket  <= '0';
+            if (tx_fifo_empty = '0' and src_stall_i = '0' and txf_ferror = '0' and txf_type = c_WRF_DATA) then
+              -- normal situation, we send the payload of a frame
+              src_adr_o   <= c_WRF_DATA;
+              src_dat_o   <= f_swap_endian_16(txf_data);
+              src_sel_o   <= "11";
+              src_stb_int <= '1';
+              tx_fifo_rd  <= '1';
+              ntx_flush_last <= '0';
+            elsif (tx_fifo_empty = '0' and src_stall_i = '0' and txf_ferror = '0' and txf_type = c_WRF_BYTESEL) then
+              -- almost normal situation, only one byte of data is valid
+              src_adr_o   <= c_WRF_DATA;
+              src_dat_o   <= f_swap_endian_16(txf_data);
+              src_sel_o   <= "10";
+              src_stb_int <= '1';
+              tx_fifo_rd  <= '1';
+              ntx_flush_last <= '0';
+            elsif (tx_fifo_empty = '0' and src_stall_i = '0' and txf_ferror = '0' and txf_type = c_WRF_OOB) then
+              -- we got OOB in TXed frame, let's send it
+              src_adr_o   <= c_WRF_OOB;
+              src_dat_o   <= f_swap_endian_16(txf_data);
+              src_sel_o   <= "11";
+              src_stb_int <= '1';
+              tx_fifo_rd  <= '1';
+              ntx_flush_last <= '0';
+            elsif ((tx_fifo_empty = '1' or txf_fnew = '1') and src_stall_i = '0') then
+              -- we done with this frame
+              src_adr_o   <= c_WRF_DATA;
+              src_dat_o   <= f_swap_endian_16(txf_data);
+              src_stb_int <= '0';
+              src_sel_o   <= "11";
+              tx_fifo_rd  <= '0';
+              ntx_flush_last <= '0';
+              ntx_state   <= TX_END_PACKET;
+            else
+              -- e.g. snk is stalling, we wait
+              tx_fifo_rd  <= '0';
+              src_stb_int <= '1';
+              ntx_stored_dat <= txf_data;
+              ntx_stored_type <= txf_type;
+              if (tx_fifo_empty = '1') then
+                ntx_flush_last <= '1';
+              else
+                ntx_flush_last <= '0';
+              end if;
+              ntx_state   <= TX_FLUSH;
+            end if;
+
+          when TX_FLUSH =>
+            regs_in.mcr_tx_idle_i <= '0';
+            ntx_rst_ts_ready      <= '0';
+            src_cyc_int <= '1';
+            ntx_newpacket  <= '0';
+            if (src_stall_i = '0' and (ntx_stored_type = c_WRF_DATA or ntx_stored_type = c_WRF_OOB)) then
+              src_adr_o   <= ntx_stored_type;
+              src_dat_o   <= f_swap_endian_16(ntx_stored_dat);
+              src_sel_o   <= "11";
+            elsif (src_stall_i = '0' and ntx_stored_type = c_WRF_BYTESEL) then
+              src_adr_o   <= c_WRF_DATA;
+              src_dat_o   <= f_swap_endian_16(ntx_stored_dat);
+              src_sel_o   <= "10";
+            else
+              src_stb_int <= '1';
+              tx_fifo_rd  <= '0';
+            end if;
+
+            if (ntx_flush_last = '0' and src_stall_i = '0') then
+              src_stb_int <= '1';
+              tx_fifo_rd  <= '1';
+              ntx_state   <= TX_PACKET;
+            elsif (ntx_flush_last = '1' and src_stall_i = '0') then
+              src_stb_int <= '0';
+              tx_fifo_rd  <= '0';
+              ntx_state   <= TX_END_PACKET;
+            else
+              src_stb_int <= '1';
+              tx_fifo_rd  <= '0';
+              ntx_state   <= TX_FLUSH;
+            end if;
+
+          when TX_END_PACKET =>
+            regs_in.mcr_tx_idle_i <= '0';
+            ntx_rst_ts_ready      <= '0';
+            src_stb_int <= '0';
+            -- timeout counter in case we never get all ACKs.
+            ntx_timeout <= ntx_timeout - 1;
+            if (ntx_ack_count = 0 or ntx_timeout_is_zero = '1') then
+              regs_in.mcr_tx_error_i <= ntx_timeout_is_zero;
+              src_cyc_int <= '0';
+              src_sel_o   <= "11";
+              tx_fifo_rd  <= '0';
+              ntx_newpacket <= '1';
+              ntx_state   <= TX_IDLE;
+            end if;
+        end case;
+      end if;
+    end if;
+  end process;
+
+-- these are never used:
+  src_we_o  <= '1';
+  src_stb_o <= src_stb_int;
+  src_cyc_o <= src_cyc_int;
+
+-------------------------------------------------------------------------------
+-- RX Path (Fabric ->  Host)
+-------------------------------------------------------------------------------  
+
+  p_rx_gen_ack : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        snk_ack_o <= '0';
+      else
+        if(snk_cyc_i = '1' and snk_stb_i = '1' and snk_stall_int = '0') then
+          snk_ack_o <= '1';
+        else
+          snk_ack_o <= '0';
+        end if;
+      end if;
+    end if;
+
+  end process;
+
+  nrx_sof <= '1' when(snk_cyc_d0 = '0' and snk_cyc_i = '1') else
+             '0';
+  nrx_eof <= '1' when(snk_cyc_d0 = '1' and snk_cyc_i = '0') else
+             '0';
+
+  process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if (rst_n_i = '0') then
+        snk_cyc_d0 <= '0';
+        rx_fifo_we <= '0';
+        rxf_type   <= (others=>'0');
+        rxf_data   <= (others=>'0');
+        snk_stall_int <= '0';
+        regs_in.mcr_rx_ready_i <= '0';
+        nrx_newpacket <= '0';
+        nrx_state  <= RX_WAIT_FRAME;
+
+      else
+        snk_cyc_d0 <= snk_cyc_i;
+
+        case nrx_state is
+          when RX_WAIT_FRAME =>
+            rx_fifo_we <= '0';
+            rxf_type   <= (others=>'0');
+            rxf_data   <= (others=>'0');
+            regs_in.mcr_rx_error_i  <= '0';
+            nrx_newpacket <= '0';
+            if (regs_out.mcr_rx_en_o = '1') then
+              snk_stall_int <= not nrx_sof;
+            else
+              -- RX path is disabled, don't stall any traffic
+              snk_stall_int <= '0';
+            end if;
+
+            -- wait for software to enable RX path and a start of new frame
+            if (regs_out.mcr_rx_en_o = '1' and nrx_sof = '1' and rx_fifo_full = '0') then
+              nrx_state <= RX_FRAME;
+            end if;
+
+          when RX_FRAME =>
+            snk_stall_int <= '0';
+            -- receive frame, write it to FIFO
+            if (snk_stb_i = '1' and snk_sel_i = "11") then
+              rxf_type   <= snk_adr_i;
+              rxf_data   <= f_swap_endian_16(snk_dat_i);
+              rx_fifo_we <= '1';
+            elsif (snk_stb_i = '1' and snk_sel_i = "10") then
+              rxf_type   <= c_WRF_BYTESEL;
+              rxf_data   <= f_swap_endian_16(snk_dat_i);
+              rx_fifo_we <= '1';
+            else
+              rxf_type   <= (others=>'0');
+              rxf_data   <= (others=>'0');
+              rx_fifo_we <= '0';
+            end if;
+
+            if ((regs_out.mcr_rx_en_o = '0' or nrx_eof = '1') and rx_fifo_full = '0') then
+              -- stop writing FIFO if sw disables RX path
+              -- or if we're done with current frame
+              regs_in.mcr_rx_ready_i <= '1';
+              regs_in.mcr_rx_error_i  <= '0';
+              nrx_newpacket <= '1';
+              nrx_state              <= RX_WAIT_FRAME;
+            elsif ((regs_out.mcr_rx_en_o = '0' or nrx_eof = '1') and rx_fifo_full = '1') then
+              -- the difference with the previous condition is that if the fifo
+              -- is full on the last word, we don't set rx_error, because the
+              -- frame was not cut (it fits in the FIFO). Besides that, we have
+              -- to go to RX_FULL state to wait for the FIFO to be half-empty
+              -- and receive more frames.
+              regs_in.mcr_rx_ready_i <= '1';
+              regs_in.mcr_rx_error_i  <= '0';
+              nrx_newpacket <= '1';
+              nrx_state              <= RX_FULL;
+            elsif (rx_fifo_full = '1') then
+              -- error if fifo gets full needs to be recovered
+              regs_in.mcr_rx_ready_i <= '1';
+              regs_in.mcr_rx_error_i  <= '1';
+              nrx_newpacket <= '1';
+              nrx_state <= RX_FULL;
+            else
+              regs_in.mcr_rx_ready_i <= '0';
+              regs_in.mcr_rx_error_i  <= '0';
+              nrx_newpacket <= '0';
+
+            end if;
+
+          when RX_FULL =>
+            snk_stall_int <= '0';
+            rx_fifo_we <= '0';
+            rxf_type   <= (others=>'0');
+            rxf_data   <= (others=>'0');
+            nrx_newpacket <= '0';
+
+            -- recovering means disabling RX path and reading everything from
+            -- the FIFO
+            --if (regs_out.mcr_rx_en_o = '0' and rx_fifo_empty = '1') then
+            --  nrx_state <= RX_WAIT_FRAME;
+            --end if;
+            if (snk_cyc_i = '0' and rx_fifo_afull = '0') then
+              nrx_state <= RX_WAIT_FRAME;
+            end if;
+        end case;
+      end if;
+    end if;
+  end process;
+
+
+  snk_stall_o <= snk_stall_int;
+  snk_err_o   <= '0';
+
+-------------------------------------------------------------------------------
+-- TX Timestamping unit
+-------------------------------------------------------------------------------  
+  tsu_fsm : process(clk_sys_i, rst_n_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if(rst_n_i = '0') then
+        regs_in.mcr_tx_ts_ready_i <= '0';
+        regs_in.tsr0_valid_i <= '0';
+        regs_in.tsr0_pid_i   <= (others => '0');
+        regs_in.tsr0_fid_i   <= (others => '0');
+        regs_in.tsr1_tsval_i <= (others => '0');
+        txtsu_ack_o          <= '0';
+      else
+        -- Make sure the timestamp is written to the FIFO only once.
+
+        if(ntx_rst_ts_ready = '1') then
+          regs_in.mcr_tx_ts_ready_i <= '0';
+        elsif(txtsu_stb_i = '1') then
+          regs_in.mcr_tx_ts_ready_i <= '1';
+          regs_in.tsr0_valid_i <= not txtsu_tsincorrect_i;
+          regs_in.tsr0_fid_i   <= txtsu_frame_id_i;
+          regs_in.tsr0_pid_i   <= txtsu_port_id_i;
+          regs_in.tsr1_tsval_i <= txtsu_tsval_i;
+          txtsu_ack_o          <= '1';
+        else
+          txtsu_ack_o <= '0';
+        end if;
+      end if;
+    end if;
+  end process;
+
+  handle_irqs: process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        irq_tx           <= '0';
+        irq_rx           <= '0';
+        ntx_newpacket_d0 <= '0';
+        nrx_newpacket_d0 <= '0';
+      else
+        ntx_newpacket_d0 <= ntx_newpacket;
+        nrx_newpacket_d0 <= nrx_newpacket;
+
+        if (ntx_newpacket_d0 = '0' and ntx_newpacket = '1' and irq_tx_mask = '1') then
+          irq_tx <= '1';
+        elsif (irq_tx_mask = '0' or irq_tx_ack = '1') then
+          irq_tx <= '0';
+        end if;
+
+        if (nrx_newpacket_d0 = '0' and nrx_newpacket = '1') then
+          irq_rx <= '1';
+        elsif (irq_rx_ack = '1') then
+          irq_rx <= '0';
+        end if;
+      end if;
+    end if;
+  end process;
+
+  irq_txts <= '0';
+
+  U_Slave_Adapter : wb_slave_adapter
+    generic map (
+      g_master_use_struct  => true,
+      g_master_mode        => CLASSIC,
+      g_master_granularity => WORD,
+      g_slave_use_struct   => false,
+      g_slave_mode         => g_interface_mode,
+      g_slave_granularity  => g_address_granularity)
+    port map (
+      clk_sys_i  => clk_sys_i,
+      rst_n_i    => rst_n_i,
+      sl_adr_i   => wb_adr_i,
+      sl_dat_i   => wb_dat_i,
+      sl_sel_i   => wb_sel_i,
+      sl_cyc_i   => wb_cyc_i,
+      sl_stb_i   => wb_stb_i,
+      sl_we_i    => wb_we_i,
+      sl_dat_o   => wb_dat_o,
+      sl_ack_o   => wb_ack_o,
+      sl_stall_o => wb_stall_o,
+      master_i   => wb_in,
+      master_o   => wb_out);
+
+  U_WB_Slave : minic_wb_slave
+    port map (
+      rst_n_i          => rst_n_i,
+      clk_sys_i        => clk_sys_i,
+      wb_adr_i         => wb_out.adr(4 downto 0),
+      wb_dat_i         => wb_out.dat,
+      wb_dat_o         => wb_in.dat,
+      wb_cyc_i         => wb_out.cyc,
+      wb_sel_i         => wb_out.sel,
+      wb_stb_i         => wb_out.stb,
+      wb_we_i          => wb_out.we,
+      wb_ack_o         => wb_in.ack,
+      wb_stall_o       => wb_in.stall,
+      wb_int_o         => wb_int_o,
+      regs_i           => regs_in,
+      regs_o           => regs_out,
+      tx_ts_read_ack_o => open,
+      irq_tx_i         => irq_tx,
+      irq_tx_ack_o     => irq_tx_ack,
+      irq_tx_mask_o    => irq_tx_mask,
+      irq_rx_i         => irq_rx,
+      irq_rx_ack_o     => irq_rx_ack,
+      irq_txts_i       => irq_txts);
+
+  wb_in.err <= '0';
+  wb_in.rty <= '0';
+  wb_in.int <= '0';
+
+  --TRIG0(0) <= regs_out.mcr_rx_en_o;
+  --TRIG0(1) <= rx_fifo_empty;
+  --TRIG0(2) <= rx_fifo_full;
+  --TRIG0(3) <= rx_fifo_rd;
+  --TRIG0(4) <= rx_fifo_we;
+  --TRIG0(6 downto 5)  <= rx_fifo_q(17 downto 16);
+  --TRIG0(22 downto 7) <= rx_fifo_q(15 downto 0);
+  --TRIG0(24 downto 23) <= "00" when(nrx_state = RX_WAIT_FRAME) else
+  --                       "01" when(nrx_state = RX_FRAME) else
+  --                       "10" when(nrx_state = RX_FULL) else
+  --                       "11";
+  --TRIG0(25) <= nrx_sof;
+  --TRIG0(26) <= nrx_eof;
+  --TRIG0(27) <= snk_cyc_i;
+  --TRIG0(28) <= snk_stb_i;
+  --TRIG0(29) <= snk_stall_int;
+  --TRIG0(31 downto 30) <= snk_adr_i;
+
+  --TRIG1(15 downto 0) <= snk_dat_i;
+  --TRIG1(16) <= rx_fifo_afull;
+  --TRIG1(17) <= wb_out.cyc;
+  --TRIG1(18) <= wb_out.stb;
+  --TRIG1(19) <= wb_in.ack;
+  --TRIG1(20) <= irq_rx;
+
+  --TRIG2(31 downto 0) <= wb_out.adr;
+
+end behavioral;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_mini_nic/xwr_mini_nic.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_mini_nic/xwr_mini_nic.vhd
new file mode 100644
index 000000000..1cbbe9dfe
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_mini_nic/xwr_mini_nic.vhd
@@ -0,0 +1,186 @@
+-------------------------------------------------------------------------------
+-- Title      : Mini Embedded DMA Network Interface Controller
+-- Project    : WhiteRabbit Core
+-------------------------------------------------------------------------------
+-- File       : xwrsw_mini_nic.vhd
+-- Author     : Grzegorz Daniluk, Tomasz Wlostowski
+-- Company    : CERN BE-Co-HT
+-- Created    : 2010-07-26
+-- Last update: 2017-02-03
+-- Platform   : FPGA-generic
+-- Standard   : VHDL
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2010-2016 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.wr_fabric_pkg.all;
+use work.wishbone_pkg.all;
+
+entity xwr_mini_nic is
+
+  generic (
+    g_interface_mode       : t_wishbone_interface_mode      := CLASSIC;
+    g_address_granularity  : t_wishbone_address_granularity := WORD;
+    g_tx_fifo_size         : integer                        := 1024;
+    g_rx_fifo_size         : integer                        := 2048;
+    g_buffer_little_endian : boolean                        := false);
+
+  port (
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+-------------------------------------------------------------------------------
+-- Pipelined Wishbone interface
+-------------------------------------------------------------------------------
+
+    -- WBP Master (TX)
+    src_o : out t_wrf_source_out;
+    src_i : in  t_wrf_source_in;
+
+    -- WBP Slave (RX)
+    snk_o : out t_wrf_sink_out;
+    snk_i : in  t_wrf_sink_in;
+
+-------------------------------------------------------------------------------
+-- TXTSU i/f
+-------------------------------------------------------------------------------
+
+    txtsu_port_id_i     : in  std_logic_vector(4 downto 0);
+    txtsu_frame_id_i    : in  std_logic_vector(16 - 1 downto 0);
+    txtsu_tsval_i       : in  std_logic_vector(28 + 4 - 1 downto 0);
+    txtsu_tsincorrect_i : in  std_logic;
+    txtsu_stb_i         : in  std_logic;
+    txtsu_ack_o         : out std_logic;
+
+-------------------------------------------------------------------------------
+-- Wishbone slave
+-------------------------------------------------------------------------------    
+
+  wb_i : in  t_wishbone_slave_in;
+  wb_o : out t_wishbone_slave_out
+    );
+end xwr_mini_nic;
+
+architecture wrapper of xwr_mini_nic is
+
+  component wr_mini_nic
+    generic (
+      g_interface_mode       : t_wishbone_interface_mode;
+      g_address_granularity  : t_wishbone_address_granularity;
+      g_tx_fifo_size         : integer;
+      g_rx_fifo_size         : integer;
+      g_buffer_little_endian : boolean);
+    port (
+      clk_sys_i           : in  std_logic;
+      rst_n_i             : in  std_logic;
+      src_dat_o           : out std_logic_vector(15 downto 0);
+      src_adr_o           : out std_logic_vector(1 downto 0);
+      src_sel_o           : out std_logic_vector(1 downto 0);
+      src_cyc_o           : out std_logic;
+      src_stb_o           : out std_logic;
+      src_we_o            : out std_logic;
+      src_stall_i         : in  std_logic;
+      src_err_i           : in  std_logic;
+      src_ack_i           : in  std_logic;
+      snk_dat_i           : in  std_logic_vector(15 downto 0);
+      snk_adr_i           : in  std_logic_vector(1 downto 0);
+      snk_sel_i           : in  std_logic_vector(1 downto 0);
+      snk_cyc_i           : in  std_logic;
+      snk_stb_i           : in  std_logic;
+      snk_we_i            : in  std_logic;
+      snk_stall_o         : out std_logic;
+      snk_err_o           : out std_logic;
+      snk_ack_o           : out std_logic;
+      txtsu_port_id_i     : in  std_logic_vector(4 downto 0);
+      txtsu_frame_id_i    : in  std_logic_vector(16 - 1 downto 0);
+      txtsu_tsval_i       : in  std_logic_vector(28 + 4 - 1 downto 0);
+      txtsu_tsincorrect_i : in  std_logic;
+      txtsu_stb_i         : in  std_logic;
+      txtsu_ack_o         : out std_logic;
+      wb_cyc_i            : in  std_logic;
+      wb_stb_i            : in  std_logic;
+      wb_we_i             : in  std_logic;
+      wb_sel_i            : in  std_logic_vector(c_wishbone_data_width/8-1 downto 0);
+      wb_adr_i            : in  std_logic_vector(c_wishbone_address_width-1 downto 0);
+      wb_dat_i            : in  std_logic_vector(c_wishbone_data_width-1 downto 0);
+      wb_dat_o            : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+      wb_ack_o            : out std_logic;
+      wb_stall_o          : out std_logic;
+      wb_int_o            : out std_logic);
+  end component;
+  
+begin  -- wrapper
+
+  U_Wrapped_Minic : wr_mini_nic
+    generic map (
+      g_interface_mode       => g_interface_mode,
+      g_address_granularity  => g_address_granularity,
+      g_tx_fifo_size         => g_tx_fifo_size,
+      g_rx_fifo_size         => g_rx_fifo_size,
+      g_buffer_little_endian => g_buffer_little_endian)
+    port map (
+      clk_sys_i           => clk_sys_i,
+      rst_n_i             => rst_n_i,
+      src_dat_o           => src_o.dat,
+      src_adr_o           => src_o.adr,
+      src_sel_o           => src_o.sel,
+      src_cyc_o           => src_o.cyc,
+      src_stb_o           => src_o.stb,
+      src_we_o            => src_o.we,
+      src_stall_i         => src_i.stall,
+      src_err_i           => src_i.err,
+      src_ack_i           => src_i.ack,
+      snk_dat_i           => snk_i.dat,
+      snk_adr_i           => snk_i.adr,
+      snk_sel_i           => snk_i.sel,
+      snk_cyc_i           => snk_i.cyc,
+      snk_stb_i           => snk_i.stb,
+      snk_we_i            => snk_i.we,
+      snk_stall_o         => snk_o.stall,
+      snk_err_o           => snk_o.err,
+      snk_ack_o           => snk_o.ack,
+      txtsu_port_id_i     => txtsu_port_id_i,
+      txtsu_frame_id_i    => txtsu_frame_id_i,
+      txtsu_tsval_i       => txtsu_tsval_i,
+      txtsu_tsincorrect_i => txtsu_tsincorrect_i,
+      txtsu_stb_i         => txtsu_stb_i,
+      txtsu_ack_o         => txtsu_ack_o,
+      wb_cyc_i            => wb_i.cyc,
+      wb_stb_i            => wb_i.stb,
+      wb_we_i             => wb_i.we,
+      wb_sel_i            => wb_i.sel,
+      wb_adr_i            => wb_i.adr,
+      wb_dat_i            => wb_i.dat,
+      wb_dat_o            => wb_o.dat,
+      wb_ack_o            => wb_o.ack,
+      wb_stall_o          => wb_o.stall,
+      wb_int_o            => wb_o.int);
+
+
+  wb_o.err <= '0';
+  wb_o.rty <= '0';
+  
+  snk_o.rty <= '0';
+
+end wrapper;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_pps_gen/pps_gen_wb.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_pps_gen/pps_gen_wb.vhd
new file mode 100644
index 000000000..d9866aeab
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_pps_gen/pps_gen_wb.vhd
@@ -0,0 +1,820 @@
+---------------------------------------------------------------------------------------
+-- Title          : Wishbone slave core for WR Switch PPS generator and RTC
+---------------------------------------------------------------------------------------
+-- File           : pps_gen_wb.vhd
+-- Author         : auto-generated by wbgen2 from pps_gen_wb.wb
+-- Created        : Wed Aug 16 22:41:09 2017
+-- Standard       : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pps_gen_wb.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity pps_gen_wb is
+  port (
+    rst_n_i                                  : in     std_logic;
+    clk_sys_i                                : in     std_logic;
+    wb_adr_i                                 : in     std_logic_vector(2 downto 0);
+    wb_dat_i                                 : in     std_logic_vector(31 downto 0);
+    wb_dat_o                                 : out    std_logic_vector(31 downto 0);
+    wb_cyc_i                                 : in     std_logic;
+    wb_sel_i                                 : in     std_logic_vector(3 downto 0);
+    wb_stb_i                                 : in     std_logic;
+    wb_we_i                                  : in     std_logic;
+    wb_ack_o                                 : out    std_logic;
+    wb_stall_o                               : out    std_logic;
+    refclk_i                                 : in     std_logic;
+-- Port for asynchronous (clock: refclk_i) MONOSTABLE field: 'Reset counter' in reg: 'Control Register'
+    ppsg_cr_cnt_rst_o                        : out    std_logic;
+-- Port for asynchronous (clock: refclk_i) BIT field: 'Enable counter' in reg: 'Control Register'
+    ppsg_cr_cnt_en_o                         : out    std_logic;
+-- Ports for asynchronous (clock: refclk_i) RW/RW BIT field: 'Adjust offset' in reg: 'Control Register'
+    ppsg_cr_cnt_adj_o                        : out    std_logic;
+    ppsg_cr_cnt_adj_i                        : in     std_logic;
+    ppsg_cr_cnt_adj_load_o                   : out    std_logic;
+-- Port for asynchronous (clock: refclk_i) MONOSTABLE field: 'Set time' in reg: 'Control Register'
+    ppsg_cr_cnt_set_o                        : out    std_logic;
+-- Port for asynchronous (clock: refclk_i) std_logic_vector field: 'PPS Pulse width' in reg: 'Control Register'
+    ppsg_cr_pwidth_o                         : out    std_logic_vector(27 downto 0);
+-- Port for asynchronous (clock: refclk_i) std_logic_vector field: 'Nanosecond counter' in reg: 'Nanosecond counter register'
+    ppsg_cntr_nsec_i                         : in     std_logic_vector(27 downto 0);
+-- Port for asynchronous (clock: refclk_i) std_logic_vector field: 'UTC Counter' in reg: 'UTC Counter register (least-significant part)'
+    ppsg_cntr_utclo_i                        : in     std_logic_vector(31 downto 0);
+-- Port for asynchronous (clock: refclk_i) std_logic_vector field: 'UTC Counter' in reg: 'UTC Counter register (most-significant part)'
+    ppsg_cntr_utchi_i                        : in     std_logic_vector(7 downto 0);
+-- Ports for PASS_THROUGH field: 'Nanosecond adjustment' in reg: 'Nanosecond adjustment register'
+    ppsg_adj_nsec_o                          : out    std_logic_vector(27 downto 0);
+    ppsg_adj_nsec_wr_o                       : out    std_logic;
+-- Ports for PASS_THROUGH field: 'UTC Counter adjustment' in reg: 'UTC Adjustment register (least-significant part)'
+    ppsg_adj_utclo_o                         : out    std_logic_vector(31 downto 0);
+    ppsg_adj_utclo_wr_o                      : out    std_logic;
+-- Ports for PASS_THROUGH field: 'UTC Counter adjustment' in reg: 'UTC Adjustment register (most-significant part)'
+    ppsg_adj_utchi_o                         : out    std_logic_vector(7 downto 0);
+    ppsg_adj_utchi_wr_o                      : out    std_logic;
+-- Ports for asynchronous (clock: refclk_i) RW/RW BIT field: 'Sync to external PPS input' in reg: 'External sync control register'
+    ppsg_escr_sync_o                         : out    std_logic;
+    ppsg_escr_sync_i                         : in     std_logic;
+    ppsg_escr_sync_load_o                    : out    std_logic;
+-- Port for asynchronous (clock: refclk_i) BIT field: 'PPS unmask output' in reg: 'External sync control register'
+    ppsg_escr_pps_unmask_o                   : out    std_logic;
+-- Port for asynchronous (clock: refclk_i) BIT field: 'PPS output valid' in reg: 'External sync control register'
+    ppsg_escr_pps_valid_o                    : out    std_logic;
+-- Port for asynchronous (clock: refclk_i) BIT field: 'Timecode output(UTC+cycles) valid' in reg: 'External sync control register'
+    ppsg_escr_tm_valid_o                     : out    std_logic;
+-- Port for asynchronous (clock: refclk_i) MONOSTABLE field: 'Set seconds counter' in reg: 'External sync control register'
+    ppsg_escr_sec_set_o                      : out    std_logic;
+-- Port for asynchronous (clock: refclk_i) MONOSTABLE field: 'Set nanoseconds counter' in reg: 'External sync control register'
+    ppsg_escr_nsec_set_o                     : out    std_logic
+  );
+end pps_gen_wb;
+
+architecture syn of pps_gen_wb is
+
+signal ppsg_cr_cnt_rst_int                      : std_logic      ;
+signal ppsg_cr_cnt_rst_int_delay                : std_logic      ;
+signal ppsg_cr_cnt_rst_sync0                    : std_logic      ;
+signal ppsg_cr_cnt_rst_sync1                    : std_logic      ;
+signal ppsg_cr_cnt_rst_sync2                    : std_logic      ;
+signal ppsg_cr_cnt_en_int                       : std_logic      ;
+signal ppsg_cr_cnt_en_sync0                     : std_logic      ;
+signal ppsg_cr_cnt_en_sync1                     : std_logic      ;
+signal ppsg_cr_cnt_adj_int_read                 : std_logic      ;
+signal ppsg_cr_cnt_adj_int_write                : std_logic      ;
+signal ppsg_cr_cnt_adj_lw                       : std_logic      ;
+signal ppsg_cr_cnt_adj_lw_delay                 : std_logic      ;
+signal ppsg_cr_cnt_adj_lw_read_in_progress      : std_logic      ;
+signal ppsg_cr_cnt_adj_lw_s0                    : std_logic      ;
+signal ppsg_cr_cnt_adj_lw_s1                    : std_logic      ;
+signal ppsg_cr_cnt_adj_lw_s2                    : std_logic      ;
+signal ppsg_cr_cnt_adj_rwsel                    : std_logic      ;
+signal ppsg_cr_cnt_set_int                      : std_logic      ;
+signal ppsg_cr_cnt_set_int_delay                : std_logic      ;
+signal ppsg_cr_cnt_set_sync0                    : std_logic      ;
+signal ppsg_cr_cnt_set_sync1                    : std_logic      ;
+signal ppsg_cr_cnt_set_sync2                    : std_logic      ;
+signal ppsg_cr_pwidth_int                       : std_logic_vector(27 downto 0);
+signal ppsg_cr_pwidth_swb                       : std_logic      ;
+signal ppsg_cr_pwidth_swb_delay                 : std_logic      ;
+signal ppsg_cr_pwidth_swb_s0                    : std_logic      ;
+signal ppsg_cr_pwidth_swb_s1                    : std_logic      ;
+signal ppsg_cr_pwidth_swb_s2                    : std_logic      ;
+signal ppsg_cntr_nsec_int                       : std_logic_vector(27 downto 0);
+signal ppsg_cntr_nsec_lwb                       : std_logic      ;
+signal ppsg_cntr_nsec_lwb_delay                 : std_logic      ;
+signal ppsg_cntr_nsec_lwb_in_progress           : std_logic      ;
+signal ppsg_cntr_nsec_lwb_s0                    : std_logic      ;
+signal ppsg_cntr_nsec_lwb_s1                    : std_logic      ;
+signal ppsg_cntr_nsec_lwb_s2                    : std_logic      ;
+signal ppsg_cntr_utclo_int                      : std_logic_vector(31 downto 0);
+signal ppsg_cntr_utclo_lwb                      : std_logic      ;
+signal ppsg_cntr_utclo_lwb_delay                : std_logic      ;
+signal ppsg_cntr_utclo_lwb_in_progress          : std_logic      ;
+signal ppsg_cntr_utclo_lwb_s0                   : std_logic      ;
+signal ppsg_cntr_utclo_lwb_s1                   : std_logic      ;
+signal ppsg_cntr_utclo_lwb_s2                   : std_logic      ;
+signal ppsg_cntr_utchi_int                      : std_logic_vector(7 downto 0);
+signal ppsg_cntr_utchi_lwb                      : std_logic      ;
+signal ppsg_cntr_utchi_lwb_delay                : std_logic      ;
+signal ppsg_cntr_utchi_lwb_in_progress          : std_logic      ;
+signal ppsg_cntr_utchi_lwb_s0                   : std_logic      ;
+signal ppsg_cntr_utchi_lwb_s1                   : std_logic      ;
+signal ppsg_cntr_utchi_lwb_s2                   : std_logic      ;
+signal ppsg_escr_sync_int_read                  : std_logic      ;
+signal ppsg_escr_sync_int_write                 : std_logic      ;
+signal ppsg_escr_sync_lw                        : std_logic      ;
+signal ppsg_escr_sync_lw_delay                  : std_logic      ;
+signal ppsg_escr_sync_lw_read_in_progress       : std_logic      ;
+signal ppsg_escr_sync_lw_s0                     : std_logic      ;
+signal ppsg_escr_sync_lw_s1                     : std_logic      ;
+signal ppsg_escr_sync_lw_s2                     : std_logic      ;
+signal ppsg_escr_sync_rwsel                     : std_logic      ;
+signal ppsg_escr_pps_unmask_int                 : std_logic      ;
+signal ppsg_escr_pps_unmask_sync0               : std_logic      ;
+signal ppsg_escr_pps_unmask_sync1               : std_logic      ;
+signal ppsg_escr_pps_valid_int                  : std_logic      ;
+signal ppsg_escr_pps_valid_sync0                : std_logic      ;
+signal ppsg_escr_pps_valid_sync1                : std_logic      ;
+signal ppsg_escr_tm_valid_int                   : std_logic      ;
+signal ppsg_escr_tm_valid_sync0                 : std_logic      ;
+signal ppsg_escr_tm_valid_sync1                 : std_logic      ;
+signal ppsg_escr_sec_set_int                    : std_logic      ;
+signal ppsg_escr_sec_set_int_delay              : std_logic      ;
+signal ppsg_escr_sec_set_sync0                  : std_logic      ;
+signal ppsg_escr_sec_set_sync1                  : std_logic      ;
+signal ppsg_escr_sec_set_sync2                  : std_logic      ;
+signal ppsg_escr_nsec_set_int                   : std_logic      ;
+signal ppsg_escr_nsec_set_int_delay             : std_logic      ;
+signal ppsg_escr_nsec_set_sync0                 : std_logic      ;
+signal ppsg_escr_nsec_set_sync1                 : std_logic      ;
+signal ppsg_escr_nsec_set_sync2                 : std_logic      ;
+signal ack_sreg                                 : std_logic_vector(9 downto 0);
+signal rddata_reg                               : std_logic_vector(31 downto 0);
+signal wrdata_reg                               : std_logic_vector(31 downto 0);
+signal rwaddr_reg                               : std_logic_vector(2 downto 0);
+signal ack_in_progress                          : std_logic      ;
+
+begin
+-- Some internal signals assignments
+  wrdata_reg <= wb_dat_i;
+-- 
+-- Main register bank access process.
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ack_sreg <= "0000000000";
+      ack_in_progress <= '0';
+      rddata_reg <= "00000000000000000000000000000000";
+      ppsg_cr_cnt_rst_int <= '0';
+      ppsg_cr_cnt_rst_int_delay <= '0';
+      ppsg_cr_cnt_en_int <= '0';
+      ppsg_cr_cnt_adj_lw <= '0';
+      ppsg_cr_cnt_adj_lw_delay <= '0';
+      ppsg_cr_cnt_adj_lw_read_in_progress <= '0';
+      ppsg_cr_cnt_adj_rwsel <= '0';
+      ppsg_cr_cnt_adj_int_write <= '0';
+      ppsg_cr_cnt_set_int <= '0';
+      ppsg_cr_cnt_set_int_delay <= '0';
+      ppsg_cr_pwidth_int <= "0000000000000000000000000000";
+      ppsg_cr_pwidth_swb <= '0';
+      ppsg_cr_pwidth_swb_delay <= '0';
+      ppsg_cntr_nsec_lwb <= '0';
+      ppsg_cntr_nsec_lwb_delay <= '0';
+      ppsg_cntr_nsec_lwb_in_progress <= '0';
+      ppsg_cntr_utclo_lwb <= '0';
+      ppsg_cntr_utclo_lwb_delay <= '0';
+      ppsg_cntr_utclo_lwb_in_progress <= '0';
+      ppsg_cntr_utchi_lwb <= '0';
+      ppsg_cntr_utchi_lwb_delay <= '0';
+      ppsg_cntr_utchi_lwb_in_progress <= '0';
+      ppsg_adj_nsec_wr_o <= '0';
+      ppsg_adj_utclo_wr_o <= '0';
+      ppsg_adj_utchi_wr_o <= '0';
+      ppsg_escr_sync_lw <= '0';
+      ppsg_escr_sync_lw_delay <= '0';
+      ppsg_escr_sync_lw_read_in_progress <= '0';
+      ppsg_escr_sync_rwsel <= '0';
+      ppsg_escr_sync_int_write <= '0';
+      ppsg_escr_pps_unmask_int <= '0';
+      ppsg_escr_pps_valid_int <= '0';
+      ppsg_escr_tm_valid_int <= '0';
+      ppsg_escr_sec_set_int <= '0';
+      ppsg_escr_sec_set_int_delay <= '0';
+      ppsg_escr_nsec_set_int <= '0';
+      ppsg_escr_nsec_set_int_delay <= '0';
+    elsif rising_edge(clk_sys_i) then
+-- advance the ACK generator shift register
+      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
+      ack_sreg(9) <= '0';
+      if (ack_in_progress = '1') then
+        if (ack_sreg(0) = '1') then
+          ppsg_adj_nsec_wr_o <= '0';
+          ppsg_adj_utclo_wr_o <= '0';
+          ppsg_adj_utchi_wr_o <= '0';
+          ack_in_progress <= '0';
+        else
+          ppsg_cr_cnt_rst_int <= ppsg_cr_cnt_rst_int_delay;
+          ppsg_cr_cnt_rst_int_delay <= '0';
+          ppsg_cr_cnt_adj_lw <= ppsg_cr_cnt_adj_lw_delay;
+          ppsg_cr_cnt_adj_lw_delay <= '0';
+          if ((ack_sreg(1) = '1') and (ppsg_cr_cnt_adj_lw_read_in_progress = '1')) then
+            rddata_reg(2) <= ppsg_cr_cnt_adj_int_read;
+            ppsg_cr_cnt_adj_lw_read_in_progress <= '0';
+          end if;
+          ppsg_cr_cnt_set_int <= ppsg_cr_cnt_set_int_delay;
+          ppsg_cr_cnt_set_int_delay <= '0';
+          ppsg_cr_pwidth_swb <= ppsg_cr_pwidth_swb_delay;
+          ppsg_cr_pwidth_swb_delay <= '0';
+          ppsg_cntr_nsec_lwb <= ppsg_cntr_nsec_lwb_delay;
+          ppsg_cntr_nsec_lwb_delay <= '0';
+          if ((ack_sreg(1) = '1') and (ppsg_cntr_nsec_lwb_in_progress = '1')) then
+            rddata_reg(27 downto 0) <= ppsg_cntr_nsec_int;
+            ppsg_cntr_nsec_lwb_in_progress <= '0';
+          end if;
+          ppsg_cntr_utclo_lwb <= ppsg_cntr_utclo_lwb_delay;
+          ppsg_cntr_utclo_lwb_delay <= '0';
+          if ((ack_sreg(1) = '1') and (ppsg_cntr_utclo_lwb_in_progress = '1')) then
+            rddata_reg(31 downto 0) <= ppsg_cntr_utclo_int;
+            ppsg_cntr_utclo_lwb_in_progress <= '0';
+          end if;
+          ppsg_cntr_utchi_lwb <= ppsg_cntr_utchi_lwb_delay;
+          ppsg_cntr_utchi_lwb_delay <= '0';
+          if ((ack_sreg(1) = '1') and (ppsg_cntr_utchi_lwb_in_progress = '1')) then
+            rddata_reg(7 downto 0) <= ppsg_cntr_utchi_int;
+            ppsg_cntr_utchi_lwb_in_progress <= '0';
+          end if;
+          ppsg_adj_nsec_wr_o <= '0';
+          ppsg_adj_utclo_wr_o <= '0';
+          ppsg_adj_utchi_wr_o <= '0';
+          ppsg_escr_sync_lw <= ppsg_escr_sync_lw_delay;
+          ppsg_escr_sync_lw_delay <= '0';
+          if ((ack_sreg(1) = '1') and (ppsg_escr_sync_lw_read_in_progress = '1')) then
+            rddata_reg(0) <= ppsg_escr_sync_int_read;
+            ppsg_escr_sync_lw_read_in_progress <= '0';
+          end if;
+          ppsg_escr_sec_set_int <= ppsg_escr_sec_set_int_delay;
+          ppsg_escr_sec_set_int_delay <= '0';
+          ppsg_escr_nsec_set_int <= ppsg_escr_nsec_set_int_delay;
+          ppsg_escr_nsec_set_int_delay <= '0';
+        end if;
+      else
+        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
+          case rwaddr_reg(2 downto 0) is
+          when "000" => 
+            if (wb_we_i = '1') then
+              ppsg_cr_cnt_rst_int <= wrdata_reg(0);
+              ppsg_cr_cnt_rst_int_delay <= wrdata_reg(0);
+              ppsg_cr_cnt_en_int <= wrdata_reg(1);
+              ppsg_cr_cnt_adj_int_write <= wrdata_reg(2);
+              ppsg_cr_cnt_adj_lw <= '1';
+              ppsg_cr_cnt_adj_lw_delay <= '1';
+              ppsg_cr_cnt_adj_lw_read_in_progress <= '0';
+              ppsg_cr_cnt_adj_rwsel <= '1';
+              ppsg_cr_cnt_set_int <= wrdata_reg(3);
+              ppsg_cr_cnt_set_int_delay <= wrdata_reg(3);
+              ppsg_cr_pwidth_int <= wrdata_reg(31 downto 4);
+              ppsg_cr_pwidth_swb <= '1';
+              ppsg_cr_pwidth_swb_delay <= '1';
+            end if;
+            rddata_reg(0) <= '0';
+            rddata_reg(1) <= ppsg_cr_cnt_en_int;
+            if (wb_we_i = '0') then
+              rddata_reg(2) <= 'X';
+              ppsg_cr_cnt_adj_lw <= '1';
+              ppsg_cr_cnt_adj_lw_delay <= '1';
+              ppsg_cr_cnt_adj_lw_read_in_progress <= '1';
+              ppsg_cr_cnt_adj_rwsel <= '0';
+            end if;
+            rddata_reg(3) <= '0';
+            rddata_reg(31 downto 4) <= ppsg_cr_pwidth_int;
+            ack_sreg(5) <= '1';
+            ack_in_progress <= '1';
+          when "001" => 
+            if (wb_we_i = '1') then
+            end if;
+            if (wb_we_i = '0') then
+              ppsg_cntr_nsec_lwb <= '1';
+              ppsg_cntr_nsec_lwb_delay <= '1';
+              ppsg_cntr_nsec_lwb_in_progress <= '1';
+            end if;
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(5) <= '1';
+            ack_in_progress <= '1';
+          when "010" => 
+            if (wb_we_i = '1') then
+            end if;
+            if (wb_we_i = '0') then
+              ppsg_cntr_utclo_lwb <= '1';
+              ppsg_cntr_utclo_lwb_delay <= '1';
+              ppsg_cntr_utclo_lwb_in_progress <= '1';
+            end if;
+            ack_sreg(5) <= '1';
+            ack_in_progress <= '1';
+          when "011" => 
+            if (wb_we_i = '1') then
+            end if;
+            if (wb_we_i = '0') then
+              ppsg_cntr_utchi_lwb <= '1';
+              ppsg_cntr_utchi_lwb_delay <= '1';
+              ppsg_cntr_utchi_lwb_in_progress <= '1';
+            end if;
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(5) <= '1';
+            ack_in_progress <= '1';
+          when "100" => 
+            if (wb_we_i = '1') then
+              ppsg_adj_nsec_wr_o <= '1';
+            end if;
+            rddata_reg(0) <= 'X';
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "101" => 
+            if (wb_we_i = '1') then
+              ppsg_adj_utclo_wr_o <= '1';
+            end if;
+            rddata_reg(0) <= 'X';
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "110" => 
+            if (wb_we_i = '1') then
+              ppsg_adj_utchi_wr_o <= '1';
+            end if;
+            rddata_reg(0) <= 'X';
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "111" => 
+            if (wb_we_i = '1') then
+              ppsg_escr_sync_int_write <= wrdata_reg(0);
+              ppsg_escr_sync_lw <= '1';
+              ppsg_escr_sync_lw_delay <= '1';
+              ppsg_escr_sync_lw_read_in_progress <= '0';
+              ppsg_escr_sync_rwsel <= '1';
+              ppsg_escr_pps_unmask_int <= wrdata_reg(1);
+              ppsg_escr_pps_valid_int <= wrdata_reg(2);
+              ppsg_escr_tm_valid_int <= wrdata_reg(3);
+              ppsg_escr_sec_set_int <= wrdata_reg(4);
+              ppsg_escr_sec_set_int_delay <= wrdata_reg(4);
+              ppsg_escr_nsec_set_int <= wrdata_reg(5);
+              ppsg_escr_nsec_set_int_delay <= wrdata_reg(5);
+            end if;
+            if (wb_we_i = '0') then
+              rddata_reg(0) <= 'X';
+              ppsg_escr_sync_lw <= '1';
+              ppsg_escr_sync_lw_delay <= '1';
+              ppsg_escr_sync_lw_read_in_progress <= '1';
+              ppsg_escr_sync_rwsel <= '0';
+            end if;
+            rddata_reg(1) <= ppsg_escr_pps_unmask_int;
+            rddata_reg(2) <= ppsg_escr_pps_valid_int;
+            rddata_reg(3) <= ppsg_escr_tm_valid_int;
+            rddata_reg(4) <= '0';
+            rddata_reg(5) <= '0';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(5) <= '1';
+            ack_in_progress <= '1';
+          when others =>
+-- prevent the slave from hanging the bus on invalid address
+            ack_in_progress <= '1';
+            ack_sreg(0) <= '1';
+          end case;
+        end if;
+      end if;
+    end if;
+  end process;
+  
+  
+-- Drive the data output bus
+  wb_dat_o <= rddata_reg;
+-- Reset counter
+  process (refclk_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ppsg_cr_cnt_rst_o <= '0';
+      ppsg_cr_cnt_rst_sync0 <= '0';
+      ppsg_cr_cnt_rst_sync1 <= '0';
+      ppsg_cr_cnt_rst_sync2 <= '0';
+    elsif rising_edge(refclk_i) then
+      ppsg_cr_cnt_rst_sync0 <= ppsg_cr_cnt_rst_int;
+      ppsg_cr_cnt_rst_sync1 <= ppsg_cr_cnt_rst_sync0;
+      ppsg_cr_cnt_rst_sync2 <= ppsg_cr_cnt_rst_sync1;
+      ppsg_cr_cnt_rst_o <= ppsg_cr_cnt_rst_sync2 and (not ppsg_cr_cnt_rst_sync1);
+    end if;
+  end process;
+  
+  
+-- Enable counter
+-- synchronizer chain for field : Enable counter (type RW/RO, clk_sys_i <-> refclk_i)
+  process (refclk_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ppsg_cr_cnt_en_o <= '0';
+      ppsg_cr_cnt_en_sync0 <= '0';
+      ppsg_cr_cnt_en_sync1 <= '0';
+    elsif rising_edge(refclk_i) then
+      ppsg_cr_cnt_en_sync0 <= ppsg_cr_cnt_en_int;
+      ppsg_cr_cnt_en_sync1 <= ppsg_cr_cnt_en_sync0;
+      ppsg_cr_cnt_en_o <= ppsg_cr_cnt_en_sync1;
+    end if;
+  end process;
+  
+  
+-- Adjust offset
+-- asynchronous BIT register : Adjust offset (type RW/WO, refclk_i <-> clk_sys_i)
+  process (refclk_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ppsg_cr_cnt_adj_lw_s0 <= '0';
+      ppsg_cr_cnt_adj_lw_s1 <= '0';
+      ppsg_cr_cnt_adj_lw_s2 <= '0';
+      ppsg_cr_cnt_adj_int_read <= '0';
+      ppsg_cr_cnt_adj_load_o <= '0';
+      ppsg_cr_cnt_adj_o <= '0';
+    elsif rising_edge(refclk_i) then
+      ppsg_cr_cnt_adj_lw_s0 <= ppsg_cr_cnt_adj_lw;
+      ppsg_cr_cnt_adj_lw_s1 <= ppsg_cr_cnt_adj_lw_s0;
+      ppsg_cr_cnt_adj_lw_s2 <= ppsg_cr_cnt_adj_lw_s1;
+      if ((ppsg_cr_cnt_adj_lw_s2 = '0') and (ppsg_cr_cnt_adj_lw_s1 = '1')) then
+        if (ppsg_cr_cnt_adj_rwsel = '1') then
+          ppsg_cr_cnt_adj_o <= ppsg_cr_cnt_adj_int_write;
+          ppsg_cr_cnt_adj_load_o <= '1';
+        else
+          ppsg_cr_cnt_adj_load_o <= '0';
+          ppsg_cr_cnt_adj_int_read <= ppsg_cr_cnt_adj_i;
+        end if;
+      else
+        ppsg_cr_cnt_adj_load_o <= '0';
+      end if;
+    end if;
+  end process;
+  
+  
+-- Set time
+  process (refclk_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ppsg_cr_cnt_set_o <= '0';
+      ppsg_cr_cnt_set_sync0 <= '0';
+      ppsg_cr_cnt_set_sync1 <= '0';
+      ppsg_cr_cnt_set_sync2 <= '0';
+    elsif rising_edge(refclk_i) then
+      ppsg_cr_cnt_set_sync0 <= ppsg_cr_cnt_set_int;
+      ppsg_cr_cnt_set_sync1 <= ppsg_cr_cnt_set_sync0;
+      ppsg_cr_cnt_set_sync2 <= ppsg_cr_cnt_set_sync1;
+      ppsg_cr_cnt_set_o <= ppsg_cr_cnt_set_sync2 and (not ppsg_cr_cnt_set_sync1);
+    end if;
+  end process;
+  
+  
+-- PPS Pulse width
+-- asynchronous std_logic_vector register : PPS Pulse width (type RW/RO, refclk_i <-> clk_sys_i)
+  process (refclk_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ppsg_cr_pwidth_swb_s0 <= '0';
+      ppsg_cr_pwidth_swb_s1 <= '0';
+      ppsg_cr_pwidth_swb_s2 <= '0';
+      ppsg_cr_pwidth_o <= "0000000000000000000000000000";
+    elsif rising_edge(refclk_i) then
+      ppsg_cr_pwidth_swb_s0 <= ppsg_cr_pwidth_swb;
+      ppsg_cr_pwidth_swb_s1 <= ppsg_cr_pwidth_swb_s0;
+      ppsg_cr_pwidth_swb_s2 <= ppsg_cr_pwidth_swb_s1;
+      if ((ppsg_cr_pwidth_swb_s2 = '0') and (ppsg_cr_pwidth_swb_s1 = '1')) then
+        ppsg_cr_pwidth_o <= ppsg_cr_pwidth_int;
+      end if;
+    end if;
+  end process;
+  
+  
+-- Nanosecond counter
+-- asynchronous std_logic_vector register : Nanosecond counter (type RO/WO, refclk_i <-> clk_sys_i)
+  process (refclk_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ppsg_cntr_nsec_lwb_s0 <= '0';
+      ppsg_cntr_nsec_lwb_s1 <= '0';
+      ppsg_cntr_nsec_lwb_s2 <= '0';
+      ppsg_cntr_nsec_int <= "0000000000000000000000000000";
+    elsif rising_edge(refclk_i) then
+      ppsg_cntr_nsec_lwb_s0 <= ppsg_cntr_nsec_lwb;
+      ppsg_cntr_nsec_lwb_s1 <= ppsg_cntr_nsec_lwb_s0;
+      ppsg_cntr_nsec_lwb_s2 <= ppsg_cntr_nsec_lwb_s1;
+      if ((ppsg_cntr_nsec_lwb_s1 = '1') and (ppsg_cntr_nsec_lwb_s2 = '0')) then
+        ppsg_cntr_nsec_int <= ppsg_cntr_nsec_i;
+      end if;
+    end if;
+  end process;
+  
+  
+-- UTC Counter
+-- asynchronous std_logic_vector register : UTC Counter (type RO/WO, refclk_i <-> clk_sys_i)
+  process (refclk_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ppsg_cntr_utclo_lwb_s0 <= '0';
+      ppsg_cntr_utclo_lwb_s1 <= '0';
+      ppsg_cntr_utclo_lwb_s2 <= '0';
+      ppsg_cntr_utclo_int <= "00000000000000000000000000000000";
+    elsif rising_edge(refclk_i) then
+      ppsg_cntr_utclo_lwb_s0 <= ppsg_cntr_utclo_lwb;
+      ppsg_cntr_utclo_lwb_s1 <= ppsg_cntr_utclo_lwb_s0;
+      ppsg_cntr_utclo_lwb_s2 <= ppsg_cntr_utclo_lwb_s1;
+      if ((ppsg_cntr_utclo_lwb_s1 = '1') and (ppsg_cntr_utclo_lwb_s2 = '0')) then
+        ppsg_cntr_utclo_int <= ppsg_cntr_utclo_i;
+      end if;
+    end if;
+  end process;
+  
+  
+-- UTC Counter
+-- asynchronous std_logic_vector register : UTC Counter (type RO/WO, refclk_i <-> clk_sys_i)
+  process (refclk_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ppsg_cntr_utchi_lwb_s0 <= '0';
+      ppsg_cntr_utchi_lwb_s1 <= '0';
+      ppsg_cntr_utchi_lwb_s2 <= '0';
+      ppsg_cntr_utchi_int <= "00000000";
+    elsif rising_edge(refclk_i) then
+      ppsg_cntr_utchi_lwb_s0 <= ppsg_cntr_utchi_lwb;
+      ppsg_cntr_utchi_lwb_s1 <= ppsg_cntr_utchi_lwb_s0;
+      ppsg_cntr_utchi_lwb_s2 <= ppsg_cntr_utchi_lwb_s1;
+      if ((ppsg_cntr_utchi_lwb_s1 = '1') and (ppsg_cntr_utchi_lwb_s2 = '0')) then
+        ppsg_cntr_utchi_int <= ppsg_cntr_utchi_i;
+      end if;
+    end if;
+  end process;
+  
+  
+-- Nanosecond adjustment
+-- pass-through field: Nanosecond adjustment in register: Nanosecond adjustment register
+  ppsg_adj_nsec_o <= wrdata_reg(27 downto 0);
+-- UTC Counter adjustment
+-- pass-through field: UTC Counter adjustment in register: UTC Adjustment register (least-significant part)
+  ppsg_adj_utclo_o <= wrdata_reg(31 downto 0);
+-- UTC Counter adjustment
+-- pass-through field: UTC Counter adjustment in register: UTC Adjustment register (most-significant part)
+  ppsg_adj_utchi_o <= wrdata_reg(7 downto 0);
+-- Sync to external PPS input
+-- asynchronous BIT register : Sync to external PPS input (type RW/WO, refclk_i <-> clk_sys_i)
+  process (refclk_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ppsg_escr_sync_lw_s0 <= '0';
+      ppsg_escr_sync_lw_s1 <= '0';
+      ppsg_escr_sync_lw_s2 <= '0';
+      ppsg_escr_sync_int_read <= '0';
+      ppsg_escr_sync_load_o <= '0';
+      ppsg_escr_sync_o <= '0';
+    elsif rising_edge(refclk_i) then
+      ppsg_escr_sync_lw_s0 <= ppsg_escr_sync_lw;
+      ppsg_escr_sync_lw_s1 <= ppsg_escr_sync_lw_s0;
+      ppsg_escr_sync_lw_s2 <= ppsg_escr_sync_lw_s1;
+      if ((ppsg_escr_sync_lw_s2 = '0') and (ppsg_escr_sync_lw_s1 = '1')) then
+        if (ppsg_escr_sync_rwsel = '1') then
+          ppsg_escr_sync_o <= ppsg_escr_sync_int_write;
+          ppsg_escr_sync_load_o <= '1';
+        else
+          ppsg_escr_sync_load_o <= '0';
+          ppsg_escr_sync_int_read <= ppsg_escr_sync_i;
+        end if;
+      else
+        ppsg_escr_sync_load_o <= '0';
+      end if;
+    end if;
+  end process;
+  
+  
+-- PPS unmask output
+-- synchronizer chain for field : PPS unmask output (type RW/RO, clk_sys_i <-> refclk_i)
+  process (refclk_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ppsg_escr_pps_unmask_o <= '0';
+      ppsg_escr_pps_unmask_sync0 <= '0';
+      ppsg_escr_pps_unmask_sync1 <= '0';
+    elsif rising_edge(refclk_i) then
+      ppsg_escr_pps_unmask_sync0 <= ppsg_escr_pps_unmask_int;
+      ppsg_escr_pps_unmask_sync1 <= ppsg_escr_pps_unmask_sync0;
+      ppsg_escr_pps_unmask_o <= ppsg_escr_pps_unmask_sync1;
+    end if;
+  end process;
+  
+  
+-- PPS output valid
+-- synchronizer chain for field : PPS output valid (type RW/RO, clk_sys_i <-> refclk_i)
+  process (refclk_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ppsg_escr_pps_valid_o <= '0';
+      ppsg_escr_pps_valid_sync0 <= '0';
+      ppsg_escr_pps_valid_sync1 <= '0';
+    elsif rising_edge(refclk_i) then
+      ppsg_escr_pps_valid_sync0 <= ppsg_escr_pps_valid_int;
+      ppsg_escr_pps_valid_sync1 <= ppsg_escr_pps_valid_sync0;
+      ppsg_escr_pps_valid_o <= ppsg_escr_pps_valid_sync1;
+    end if;
+  end process;
+  
+  
+-- Timecode output(UTC+cycles) valid
+-- synchronizer chain for field : Timecode output(UTC+cycles) valid (type RW/RO, clk_sys_i <-> refclk_i)
+  process (refclk_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ppsg_escr_tm_valid_o <= '0';
+      ppsg_escr_tm_valid_sync0 <= '0';
+      ppsg_escr_tm_valid_sync1 <= '0';
+    elsif rising_edge(refclk_i) then
+      ppsg_escr_tm_valid_sync0 <= ppsg_escr_tm_valid_int;
+      ppsg_escr_tm_valid_sync1 <= ppsg_escr_tm_valid_sync0;
+      ppsg_escr_tm_valid_o <= ppsg_escr_tm_valid_sync1;
+    end if;
+  end process;
+  
+  
+-- Set seconds counter
+  process (refclk_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ppsg_escr_sec_set_o <= '0';
+      ppsg_escr_sec_set_sync0 <= '0';
+      ppsg_escr_sec_set_sync1 <= '0';
+      ppsg_escr_sec_set_sync2 <= '0';
+    elsif rising_edge(refclk_i) then
+      ppsg_escr_sec_set_sync0 <= ppsg_escr_sec_set_int;
+      ppsg_escr_sec_set_sync1 <= ppsg_escr_sec_set_sync0;
+      ppsg_escr_sec_set_sync2 <= ppsg_escr_sec_set_sync1;
+      ppsg_escr_sec_set_o <= ppsg_escr_sec_set_sync2 and (not ppsg_escr_sec_set_sync1);
+    end if;
+  end process;
+  
+  
+-- Set nanoseconds counter
+  process (refclk_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ppsg_escr_nsec_set_o <= '0';
+      ppsg_escr_nsec_set_sync0 <= '0';
+      ppsg_escr_nsec_set_sync1 <= '0';
+      ppsg_escr_nsec_set_sync2 <= '0';
+    elsif rising_edge(refclk_i) then
+      ppsg_escr_nsec_set_sync0 <= ppsg_escr_nsec_set_int;
+      ppsg_escr_nsec_set_sync1 <= ppsg_escr_nsec_set_sync0;
+      ppsg_escr_nsec_set_sync2 <= ppsg_escr_nsec_set_sync1;
+      ppsg_escr_nsec_set_o <= ppsg_escr_nsec_set_sync2 and (not ppsg_escr_nsec_set_sync1);
+    end if;
+  end process;
+  
+  
+  rwaddr_reg <= wb_adr_i;
+  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
+-- ACK signal generation. Just pass the LSB of ACK counter.
+  wb_ack_o <= ack_sreg(0);
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_pps_gen/wr_pps_gen.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_pps_gen/wr_pps_gen.vhd
new file mode 100644
index 000000000..f79dd0641
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_pps_gen/wr_pps_gen.vhd
@@ -0,0 +1,518 @@
+-------------------------------------------------------------------------------
+-- Title      : PPS Generator & UTC Realtime clock
+-- Project    : WhiteRabbit Switch
+-------------------------------------------------------------------------------
+-- File       : wr_pps_gen.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN (BE-CO-HT)
+-- Created    : 2010-09-02
+-- Last update: 2017-02-20
+-- Platform   : FPGA-generics
+-- Standard   : VHDL
+-------------------------------------------------------------------------------
+-- Description:
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2010-2017 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2010-09-02  1.0      twlostow        Created
+-- 2011-05-09  1.1      twlostow        Added external PPS input
+-- 2011-10-26  1.2      greg.d          Added wb slave adapter
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.gencores_pkg.all;
+use work.genram_pkg.all;
+use work.wishbone_pkg.all;
+
+entity wr_pps_gen is
+  generic(
+    g_interface_mode       : t_wishbone_interface_mode      := CLASSIC;
+    g_address_granularity  : t_wishbone_address_granularity := WORD;
+    g_ref_clock_rate       : integer                        := 125000000;
+    g_ext_clock_rate       : integer                        := 10000000;
+    g_with_ext_clock_input : boolean                        := false
+    );
+  port (
+    clk_ref_i   : in std_logic;
+    clk_sys_i   : in std_logic;
+    rst_ref_n_i : in std_logic;
+    rst_sys_n_i : in std_logic;
+
+    wb_adr_i   : in  std_logic_vector(4 downto 0);
+    wb_dat_i   : in  std_logic_vector(31 downto 0);
+    wb_dat_o   : out std_logic_vector(31 downto 0);
+    wb_cyc_i   : in  std_logic;
+    wb_sel_i   : in  std_logic_vector(3 downto 0);
+    wb_stb_i   : in  std_logic;
+    wb_we_i    : in  std_logic;
+    wb_ack_o   : out std_logic;
+    wb_stall_o : out std_logic;
+
+    -- Link status indicator (used for fast masking of PPS output when link
+    -- goes down
+    link_ok_i : in std_logic;
+
+    -- External PPS input. Warning! This signal is treated as synchronous to
+    -- the clk_ref_i (or the external 10 MHz reference) to prevent sync chain
+    -- delay uncertainities. Setup/hold times must be respected!
+    pps_in_i : in std_logic;
+
+    -- Single-pulse PPS output for synchronizing endpoints to
+    pps_csync_o : out std_logic;
+    pps_out_o   : out std_logic;
+    pps_led_o   : out std_logic;
+
+    pps_valid_o : out std_logic;
+
+    tm_utc_o        : out std_logic_vector(39 downto 0);
+    tm_cycles_o     : out std_logic_vector(27 downto 0);
+    tm_time_valid_o : out std_logic
+    );
+end wr_pps_gen;
+
+architecture behavioral of wr_pps_gen is
+
+  alias rst_n_i : std_logic is rst_sys_n_i;
+
+  constant c_PERIOD : integer := g_ref_clock_rate;
+
+  component pps_gen_wb is
+    port (
+      rst_n_i                : in  std_logic;
+      clk_sys_i              : in  std_logic;
+      wb_adr_i               : in  std_logic_vector(2 downto 0);
+      wb_dat_i               : in  std_logic_vector(31 downto 0);
+      wb_dat_o               : out std_logic_vector(31 downto 0);
+      wb_cyc_i               : in  std_logic;
+      wb_sel_i               : in  std_logic_vector(3 downto 0);
+      wb_stb_i               : in  std_logic;
+      wb_we_i                : in  std_logic;
+      wb_ack_o               : out std_logic;
+      wb_stall_o             : out std_logic;
+      refclk_i               : in  std_logic;
+      ppsg_cr_cnt_rst_o      : out std_logic;
+      ppsg_cr_cnt_en_o       : out std_logic;
+      ppsg_cr_cnt_adj_o      : out std_logic;
+      ppsg_cr_cnt_adj_i      : in  std_logic;
+      ppsg_cr_cnt_adj_load_o : out std_logic;
+      ppsg_cr_cnt_set_o      : out std_logic;
+      ppsg_cr_pwidth_o       : out std_logic_vector(27 downto 0);
+      ppsg_cntr_nsec_i       : in  std_logic_vector(27 downto 0);
+      ppsg_cntr_utclo_i      : in  std_logic_vector(31 downto 0);
+      ppsg_cntr_utchi_i      : in  std_logic_vector(7 downto 0);
+      ppsg_adj_nsec_o        : out std_logic_vector(27 downto 0);
+      ppsg_adj_nsec_wr_o     : out std_logic;
+      ppsg_adj_utclo_o       : out std_logic_vector(31 downto 0);
+      ppsg_adj_utclo_wr_o    : out std_logic;
+      ppsg_adj_utchi_o       : out std_logic_vector(7 downto 0);
+      ppsg_adj_utchi_wr_o    : out std_logic;
+      ppsg_escr_sync_o       : out std_logic;
+      ppsg_escr_sync_i       : in  std_logic;
+      ppsg_escr_sync_load_o  : out std_logic;
+      ppsg_escr_pps_valid_o  : out std_logic;
+      ppsg_escr_tm_valid_o   : out std_logic;
+      ppsg_escr_sec_set_o    : out std_logic;
+      ppsg_escr_nsec_set_o   : out std_logic;
+      ppsg_escr_pps_unmask_o : out std_logic);
+  end component pps_gen_wb;
+
+-- Wisbone slave signals
+  signal ppsg_cr_cnt_rst : std_logic;
+  signal ppsg_cr_cnt_en  : std_logic;
+
+  signal ppsg_cr_cnt_adj_o    : std_logic;
+  signal ppsg_cr_cnt_adj_i    : std_logic;
+  signal ppsg_cr_cnt_adj_load : std_logic;
+
+  signal ppsg_cr_cnt_set_p : std_logic;
+  signal ppsg_cr_pwidth    : std_logic_vector(27 downto 0);
+
+  signal ppsg_cntr_nsec  : std_logic_vector(27 downto 0);
+  signal ppsg_cntr_utclo : std_logic_vector(31 downto 0);
+  signal ppsg_cntr_utchi : std_logic_vector(7 downto 0);
+
+  signal ppsg_adj_nsec       : std_logic_vector(27 downto 0);
+  signal ppsg_adj_nsec_wr    : std_logic;
+  signal ppsg_adj_utclo      : std_logic_vector(31 downto 0);
+  signal ppsg_adj_utclo_wr   : std_logic;
+  signal ppsg_adj_utchi      : std_logic_vector(7 downto 0);
+  signal ppsg_adj_utchi_wr   : std_logic;
+  signal ppsg_escr_sync_load : std_logic;
+  signal ppsg_escr_sync_in   : std_logic;
+  signal ppsg_escr_sync_out  : std_logic;
+  signal ppsg_escr_sec_set   : std_logic;
+  signal ppsg_escr_nsec_set  : std_logic;
+
+  signal ppsg_escr_pps_valid  : std_logic;
+  signal ppsg_escr_tm_valid   : std_logic;
+  signal ppsg_escr_pps_unmask : std_logic;
+
+  signal cntr_nsec    : unsigned (27 downto 0);
+  signal cntr_utc     : unsigned (39 downto 0);
+  signal cntr_pps_ext : unsigned (24 downto 0);
+
+  signal ns_overflow     : std_logic;
+  signal ns_overflow_adv : std_logic;
+  signal cntr_adjust_p   : std_logic;
+
+  signal adj_nsec : unsigned(27 downto 0);
+  signal adj_utc  : unsigned(39 downto 0);
+
+  signal adjust_in_progress_nsec : std_logic;
+
+  signal adjust_in_progress_utc : std_logic;
+
+  signal width_cntr : unsigned(27 downto 0);
+
+  signal sync_in_progress : std_logic;
+  signal ext_sync_p       : std_logic;
+
+  signal resized_addr : std_logic_vector(c_wishbone_address_width-1 downto 0);
+  signal wb_out       : t_wishbone_slave_out;
+  signal wb_in        : t_wishbone_slave_in;
+
+  signal ns_overflow_2nd       : std_logic;
+  signal pps_in_d0, pps_ext_d0 : std_logic;
+
+  signal retime_counter : unsigned(4 downto 0);
+  signal pps_valid_int  : std_logic;
+
+  signal pps_out_int   : std_logic;
+  signal pps_in_refclk : std_logic;
+
+
+
+begin  -- behavioral
+
+
+  resized_addr(4 downto 0)                          <= wb_adr_i;
+  resized_addr(c_wishbone_address_width-1 downto 5) <= (others => '0');
+
+  U_Adapter : wb_slave_adapter
+    generic map (
+      g_master_use_struct  => true,
+      g_master_mode        => CLASSIC,
+      g_master_granularity => WORD,
+      g_slave_use_struct   => false,
+      g_slave_mode         => g_interface_mode,
+      g_slave_granularity  => g_address_granularity)
+    port map (
+      clk_sys_i  => clk_sys_i,
+      rst_n_i    => rst_n_i,
+      master_i   => wb_out,
+      master_o   => wb_in,
+      sl_adr_i   => resized_addr,
+      sl_dat_i   => wb_dat_i,
+      sl_sel_i   => wb_sel_i,
+      sl_cyc_i   => wb_cyc_i,
+      sl_stb_i   => wb_stb_i,
+      sl_we_i    => wb_we_i,
+      sl_dat_o   => wb_dat_o,
+      sl_ack_o   => wb_ack_o,
+      sl_stall_o => wb_stall_o);
+
+
+  U_Sync_pps_refclk : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_ref_i,
+      rst_n_i  => '1',
+      data_i   => pps_in_i,
+      ppulse_o => pps_in_refclk);
+
+
+  ppsg_cntr_nsec  <= std_logic_vector(cntr_nsec);
+  ppsg_cntr_utclo <= std_logic_vector(cntr_utc(31 downto 0));
+  ppsg_cntr_utchi <= std_logic_vector(cntr_utc(39 downto 32));
+
+
+  -- loads adjustment values into internal regsiters
+  p_wishbone_loads : process(clk_sys_i, rst_n_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        adj_nsec <= (others => '0');
+        adj_utc  <= (others => '0');
+      else
+        if(ppsg_adj_utchi_wr = '1') then
+          adj_utc(39 downto 32) <= unsigned(ppsg_adj_utchi);
+        end if;
+
+        if(ppsg_adj_utclo_wr = '1') then
+          adj_utc(31 downto 0) <= unsigned(ppsg_adj_utclo);
+        end if;
+
+        if(ppsg_adj_nsec_wr = '1') then
+          adj_nsec <= unsigned(ppsg_adj_nsec);
+        end if;
+      end if;
+    end if;
+  end process;
+
+  gen_without_external_clock_input : if(not g_with_ext_clock_input) generate
+    ext_sync_p        <= '0';
+    sync_in_progress  <= '0';
+    ppsg_escr_sync_in <= '0';
+  end generate gen_without_external_clock_input;
+
+  gen_with_external_clock_input : if(g_with_ext_clock_input) generate
+
+    p_external_sync : process(clk_ref_i)
+    begin
+      if falling_edge(clk_ref_i) then
+        if(rst_ref_n_i = '0') then
+          sync_in_progress  <= '0';
+          ppsg_escr_sync_in <= '0';
+        else
+          if(ppsg_escr_sync_load = '1') then
+            sync_in_progress  <= ppsg_escr_sync_out;
+            ppsg_escr_sync_in <= '0';
+          else
+            if(sync_in_progress = '1' and pps_in_refclk = '1')
+            then
+              ext_sync_p        <= '1';
+              sync_in_progress  <= '0';
+              ppsg_escr_sync_in <= '1';
+            else
+              ext_sync_p <= '0';
+            end if;
+          end if;
+        end if;
+      end if;
+    end process;
+
+  end generate gen_with_external_clock_input;
+-- Nanosecond counter. Counts from 0 to c_PERIOD-1 every clk_ref_i cycle.
+
+  p_count_nsec : process(clk_ref_i)
+  begin
+    if rising_edge(clk_ref_i) then
+      if rst_ref_n_i = '0' or ppsg_cr_cnt_rst = '1' then
+        cntr_nsec               <= (others => '0');
+        ns_overflow             <= '0';
+        ns_overflow_adv         <= '0';
+        adjust_in_progress_nsec <= '0';
+
+        -- counter is enabled?
+      elsif(ppsg_cr_cnt_en = '1') then
+
+        -- got ADJUST OFFSET command
+        if(cntr_adjust_p = '1') then
+
+-- start waiting for next counter overflow
+          adjust_in_progress_nsec <= '1';
+        end if;
+
+-- got SET TIME command - load the counter with new value
+        if(ppsg_cr_cnt_set_p = '1' or ext_sync_p = '1' or ppsg_escr_nsec_set = '1') then
+          cntr_nsec        <= adj_nsec;
+          ns_overflow      <= '0';
+          ns_overflow_adv  <= '0';
+
+-- got counter overflow:
+        elsif(cntr_nsec = to_unsigned(c_PERIOD-3, cntr_nsec'length)) then
+          ns_overflow     <= '0';
+          ns_overflow_adv <= '1';
+          cntr_nsec       <= cntr_nsec + 1;
+        elsif(cntr_nsec = to_unsigned(c_PERIOD-2, cntr_nsec'length)) then
+          ns_overflow     <= '1';
+          ns_overflow_adv <= '0';
+          cntr_nsec       <= cntr_nsec + 1;
+        elsif(cntr_nsec = to_unsigned(c_PERIOD-1, cntr_nsec'length)) then
+          ns_overflow     <= '0';
+          ns_overflow_adv <= '0';
+          -- we're in the middle of offset adjustment - load the counter with
+          -- offset value instead of resetting it. This equals to subtracting the offset
+          -- but takes less logic.
+          if(adjust_in_progress_nsec = '1') then
+            cntr_nsec               <= adj_nsec;
+            adjust_in_progress_nsec <= '0';
+          else
+            -- normal counter reset. Generate overflow pulse.
+            cntr_nsec <= (others => '0');
+          end if;
+        else
+          ns_overflow     <= '0';
+          ns_overflow_adv <= '0';
+          cntr_nsec       <= cntr_nsec + 1;
+        end if;
+      end if;
+    end if;
+  end process;
+
+
+  p_drive_pps_valid : process(clk_ref_i)
+  begin
+    if rising_edge(clk_ref_i) then
+      if rst_ref_n_i = '0' or ppsg_cr_cnt_rst = '1' then
+        pps_valid_int   <= '0';
+        ns_overflow_2nd <= '0';
+      else
+        if(sync_in_progress = '1' or adjust_in_progress_nsec = '1' or adjust_in_progress_utc = '1') then
+          pps_valid_int   <= '0';
+          ns_overflow_2nd <= '0';
+        elsif(adjust_in_progress_utc = '0' and adjust_in_progress_nsec = '0' and sync_in_progress = '0') then
+
+          if(ns_overflow = '1') then
+            ns_overflow_2nd <= '1';
+            if(ns_overflow_2nd = '1') then
+              pps_valid_int <= '1';
+            end if;
+          end if;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  p_count_utc : process(clk_ref_i)
+  begin
+    if rising_edge(clk_ref_i) then
+      if rst_ref_n_i = '0' or ppsg_cr_cnt_rst = '1' then
+        cntr_utc               <= (others => '0');
+        adjust_in_progress_utc <= '0';
+      elsif(ppsg_cr_cnt_en = '1') then
+
+        if(ppsg_cr_cnt_set_p = '1' or ppsg_escr_sec_set = '1') then
+          cntr_utc        <= adj_utc;
+        elsif(cntr_adjust_p = '1') then
+          adjust_in_progress_utc <= '1';
+
+          if(ns_overflow = '1') then
+            cntr_utc <= cntr_utc +1;
+          end if;
+
+        elsif(adjust_in_progress_utc = '1' and ns_overflow = '1') then
+          cntr_utc               <= cntr_utc + adj_utc + 1;
+          adjust_in_progress_utc <= '0';
+        elsif(ns_overflow = '1') then
+          cntr_utc <= cntr_utc + 1;
+        end if;
+      end if;
+    end if;
+  end process;
+
+-- generate single-cycle PPS pulses for synchronizing endpoint TS counters
+  pps_csync_o <= ns_overflow;
+
+  -- generates variable-width PPS pulses for PPS external output
+  p_gen_pps_out : process(clk_ref_i)
+  begin
+    if rising_edge(clk_ref_i) then
+      if rst_ref_n_i = '0' then
+        pps_out_int <= '0';
+        pps_led_o   <= '0';
+        width_cntr  <= (others => '0');
+      else
+
+        if(ns_overflow_adv = '1') then
+          pps_out_int <= ppsg_escr_pps_valid and
+                         (link_ok_i or ppsg_escr_pps_unmask);
+          width_cntr  <= unsigned(ppsg_cr_pwidth);
+        elsif(ns_overflow = '1') then
+          pps_led_o <= ppsg_escr_pps_valid;
+        else
+          if(width_cntr = to_unsigned(0, width_cntr'length)) then
+            pps_out_int <= '0';
+            pps_led_o   <= '0';
+          else
+            width_cntr <= width_cntr -1;
+          end if;
+        end if;
+      end if;
+    end if;
+
+  end process;
+
+  process(clk_ref_i)
+  begin
+    if rising_edge(clk_ref_i) then
+      if rst_ref_n_i = '0' then
+        pps_out_o <= '0';
+      else
+        pps_out_o <= pps_out_int;
+      end if;
+    end if;
+  end process;
+
+  Uwb_slave : pps_gen_wb
+    port map (
+      rst_n_i                => rst_n_i,
+      clk_sys_i              => clk_sys_i,
+      wb_adr_i               => wb_in.adr(2 downto 0),
+      wb_dat_i               => wb_in.dat,
+      wb_dat_o               => wb_out.dat,
+      wb_cyc_i               => wb_in.cyc,
+      wb_sel_i               => wb_in.sel,
+      wb_stb_i               => wb_in.stb,
+      wb_we_i                => wb_in.we,
+      wb_ack_o               => wb_out.ack,
+      refclk_i               => clk_ref_i,
+      ppsg_cr_cnt_rst_o      => ppsg_cr_cnt_rst,
+      ppsg_cr_cnt_en_o       => ppsg_cr_cnt_en,
+      ppsg_cr_cnt_adj_o      => ppsg_cr_cnt_adj_o,
+      ppsg_cr_cnt_adj_i      => ppsg_cr_cnt_adj_i,
+      ppsg_cr_cnt_adj_load_o => ppsg_cr_cnt_adj_load,
+      ppsg_escr_sync_o       => ppsg_escr_sync_out,
+      ppsg_escr_sync_i       => ppsg_escr_sync_in,
+      ppsg_escr_sync_load_o  => ppsg_escr_sync_load,
+      ppsg_cr_cnt_set_o      => ppsg_cr_cnt_set_p,
+      ppsg_cr_pwidth_o       => ppsg_cr_pwidth,
+      ppsg_cntr_nsec_i       => ppsg_cntr_nsec,
+      ppsg_cntr_utclo_i      => ppsg_cntr_utclo,
+      ppsg_cntr_utchi_i      => ppsg_cntr_utchi,
+      ppsg_adj_nsec_o        => ppsg_adj_nsec,
+      ppsg_adj_nsec_wr_o     => ppsg_adj_nsec_wr,
+      ppsg_adj_utclo_o       => ppsg_adj_utclo,
+      ppsg_adj_utclo_wr_o    => ppsg_adj_utclo_wr,
+      ppsg_adj_utchi_o       => ppsg_adj_utchi,
+      ppsg_adj_utchi_wr_o    => ppsg_adj_utchi_wr,
+      ppsg_escr_pps_valid_o  => ppsg_escr_pps_valid,
+      ppsg_escr_tm_valid_o   => ppsg_escr_tm_valid,
+      ppsg_escr_sec_set_o    => ppsg_escr_sec_set,
+      ppsg_escr_nsec_set_o   => ppsg_escr_nsec_set,
+      ppsg_escr_pps_unmask_o => ppsg_escr_pps_unmask);
+
+-- drive unused signals
+  wb_out.rty   <= '0';
+  wb_out.stall <= '0';
+  wb_out.int   <= '0';
+  wb_out.err   <= '0';
+
+-- start the adjustment upon write of 1 to CNT_ADJ bit
+  cntr_adjust_p <= ppsg_cr_cnt_adj_load and ppsg_cr_cnt_adj_o;
+
+-- drive the readout value of CNT_ADJ to 1 when the adjustment is over
+  ppsg_cr_cnt_adj_i <= pps_valid_int;
+
+  pps_valid_o <= pps_valid_int;
+
+  tm_utc_o        <= std_logic_vector(cntr_utc);
+  tm_cycles_o     <= std_logic_vector(cntr_nsec);
+  tm_time_valid_o <= ppsg_escr_tm_valid;
+
+end behavioral;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_pps_gen/xwr_pps_gen.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_pps_gen/xwr_pps_gen.vhd
new file mode 100644
index 000000000..547a19ab9
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_pps_gen/xwr_pps_gen.vhd
@@ -0,0 +1,162 @@
+-------------------------------------------------------------------------------
+-- Title      : PPS Generator & UTC Realtime clock
+-- Project    : WhiteRabbit Switch
+-------------------------------------------------------------------------------
+-- File       : xwb_pps_gen.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN (BE-CO-HT)
+-- Created    : 2010-09-02
+-- Last update: 2017-02-20
+-- Platform   : FPGA-generics
+-- Standard   : VHDL
+-------------------------------------------------------------------------------
+-- Description:
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2010-2017 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2010-09-02  1.0      twlostow        Created
+-- 2011-05-09  1.1      twlostow        Added external PPS input
+-- 2011-10-26  1.2      greg.d          xwb module
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.gencores_pkg.all;
+use work.wishbone_pkg.all;
+
+entity xwr_pps_gen is
+  generic(
+    g_interface_mode       : t_wishbone_interface_mode      := CLASSIC;
+    g_address_granularity  : t_wishbone_address_granularity := WORD;
+    g_ref_clock_rate       : integer                        := 125000000;
+    g_ext_clock_rate       : integer                        := 10000000;
+    g_with_ext_clock_input : boolean                        := FALSE
+    );
+  port (
+    clk_ref_i   : in std_logic;
+    clk_sys_i   : in std_logic;
+    rst_ref_n_i : in std_logic;
+    rst_sys_n_i : in std_logic;
+
+    slave_i : in  t_wishbone_slave_in;
+    slave_o : out t_wishbone_slave_out;
+
+    link_ok_i : in std_logic;
+
+    pps_in_i : in std_logic;
+
+    -- Single-pulse PPS output for synchronizing endpoints to
+    pps_csync_o : out std_logic;
+    pps_out_o   : out std_logic;
+    pps_led_o   : out std_logic;
+
+    pps_valid_o : out std_logic;
+
+    tm_utc_o        : out std_logic_vector(39 downto 0);
+    tm_cycles_o     : out std_logic_vector(27 downto 0);
+    tm_time_valid_o : out std_logic
+
+    );
+end xwr_pps_gen;
+
+architecture behavioral of xwr_pps_gen is
+
+  component wr_pps_gen is
+    generic(
+      g_interface_mode       : t_wishbone_interface_mode;
+      g_address_granularity  : t_wishbone_address_granularity;
+      g_ref_clock_rate       : integer;
+      g_ext_clock_rate       : integer := 10000000;
+      g_with_ext_clock_input : boolean := FALSE
+      );
+    port (
+      clk_ref_i       : in  std_logic;
+      clk_sys_i       : in  std_logic;
+      rst_ref_n_i     : in  std_logic;
+      rst_sys_n_i     : in  std_logic;
+      wb_adr_i        : in  std_logic_vector(4 downto 0);
+      wb_dat_i        : in  std_logic_vector(31 downto 0);
+      wb_dat_o        : out std_logic_vector(31 downto 0);
+      wb_cyc_i        : in  std_logic;
+      wb_sel_i        : in  std_logic_vector(3 downto 0);
+      wb_stb_i        : in  std_logic;
+      wb_we_i         : in  std_logic;
+      wb_ack_o        : out std_logic;
+      wb_stall_o      : out std_logic;
+      link_ok_i       : in  std_logic;
+      pps_in_i        : in  std_logic;
+      pps_csync_o     : out std_logic;
+      pps_out_o       : out std_logic;
+      pps_led_o       : out std_logic;
+      pps_valid_o     : out std_logic;
+      tm_utc_o        : out std_logic_vector(39 downto 0);
+      tm_cycles_o     : out std_logic_vector(27 downto 0);
+      tm_time_valid_o : out std_logic
+      );
+  end component;
+
+begin  -- behavioral
+
+
+  WRAPPED_PPSGEN : wr_pps_gen
+    generic map(
+      g_interface_mode       => g_interface_mode,
+      g_address_granularity  => g_address_granularity,
+      g_ref_clock_rate       => g_ref_clock_rate,
+      g_ext_clock_rate       => g_ext_clock_rate,
+      g_with_ext_clock_input => g_with_ext_clock_input
+      )
+    port map(
+      clk_ref_i       => clk_ref_i,
+      clk_sys_i       => clk_sys_i,
+      rst_ref_n_i     => rst_ref_n_i,
+      rst_sys_n_i     => rst_sys_n_i,
+      wb_adr_i        => slave_i.adr(4 downto 0),
+      wb_dat_i        => slave_i.dat,
+      wb_dat_o        => slave_o.dat,
+      wb_cyc_i        => slave_i.cyc,
+      wb_sel_i        => slave_i.sel,
+      wb_stb_i        => slave_i.stb,
+      wb_we_i         => slave_i.we,
+      wb_ack_o        => slave_o.ack,
+      wb_stall_o      => slave_o.stall,
+      link_ok_i       => link_ok_i,
+      pps_in_i        => pps_in_i,
+      pps_csync_o     => pps_csync_o,
+      pps_out_o       => pps_out_o,
+      pps_led_o       => pps_led_o,
+      pps_valid_o     => pps_valid_o,
+      tm_utc_o        => tm_utc_o,
+      tm_cycles_o     => tm_cycles_o,
+      tm_time_valid_o => tm_time_valid_o
+      );
+
+
+  slave_o.err <= '0';
+  slave_o.rty <= '0';
+  slave_o.int <= '0';
+
+end behavioral;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_softpll_ng/softpll_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_softpll_ng/softpll_pkg.vhd
new file mode 100644
index 000000000..0fdac142b
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_softpll_ng/softpll_pkg.vhd
@@ -0,0 +1,31 @@
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package softpll_pkg is
+
+  constant c_softpll_max_aux_clocks : integer := 8;
+
+  type t_softpll_phase_detector_type is (CH_DDMTD, CH_BANGBANG);
+
+  type t_softpll_channel_config_array is array(0 to c_softpll_max_aux_clocks-1) of t_softpll_phase_detector_type;
+
+  constant c_softpll_default_channel_config : t_softpll_channel_config_array := (others => CH_DDMTD);
+
+  -- External 10 MHz input divider parameters. 
+  constant c_softpll_ext_div_ref     : integer := 8;
+  constant c_softpll_ext_div_fb      : integer := 50;
+  constant c_softpll_ext_log2_gating : integer := 13;
+
+  constant c_softpll_out_status_off      : std_logic_vector(3 downto 0) := "0000";
+  constant c_softpll_out_status_locking  : std_logic_vector(3 downto 0) := "0001";
+  constant c_softpll_out_status_locked   : std_logic_vector(3 downto 0) := "0010";
+  constant c_softpll_out_status_aligning : std_logic_vector(3 downto 0) := "0011";
+  constant c_softpll_out_status_holdover : std_logic_vector(3 downto 0) := "0100";
+  
+end package;
+
+package body softpll_pkg is
+
+end softpll_pkg;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_softpll_ng/spll_aligner.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_softpll_ng/spll_aligner.vhd
new file mode 100644
index 000000000..941279c02
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_softpll_ng/spll_aligner.vhd
@@ -0,0 +1,180 @@
+-------------------------------------------------------------------------------
+-- Title      : White Rabbit Softcore PLL (new generation) - SoftPLL-ng
+-- Project    : White Rabbit
+-------------------------------------------------------------------------------
+-- File       : spll_aligner.vhd
+-- Author     : Tomasz Włostowski
+-- Company    : CERN BE-CO-HT
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012-2017 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.gencores_pkg.all;
+
+entity spll_aligner is
+  generic (
+    g_counter_width  : integer := 28;
+    g_ref_clock_rate : integer := 125000000;
+    g_in_clock_rate  : integer := 10000000;
+    g_sample_rate    : integer := 100
+    );
+  port (
+    clk_sys_i : in std_logic;
+    clk_in_i  : in std_logic;
+    clk_ref_i : in std_logic;
+
+    rst_n_sys_i    : in std_logic;
+    rst_n_ref_i    : in  std_logic;
+    rst_n_ext_i    : in  std_logic;
+
+    pps_ext_a_i    : in std_logic;
+    pps_csync_p1_i : in std_logic;
+
+    sample_cref_o  : out std_logic_vector(g_counter_width-1 downto 0);
+    sample_cin_o   : out std_logic_vector(g_counter_width-1 downto 0);
+    sample_valid_o : out std_logic;
+    sample_ack_i   : in  std_logic
+    );
+
+end spll_aligner;
+
+architecture rtl of spll_aligner is
+
+  constant c_div_ticks : integer := g_ref_clock_rate / g_sample_rate;
+
+  signal cnt_ref_bin, cnt_in_bin, cnt_in_bin_x      : unsigned(g_counter_width-1 downto 0);
+  signal cnt_in_gray, cnt_in_gray_x, cnt_in_gray_xd : std_logic_vector(g_counter_width-1 downto 0);
+
+  signal cnt_ref_div           : unsigned(g_counter_width-1 downto 0);
+  signal pps_ext_p, pps_ext_d0 : std_logic;
+  signal ref_div_p             : std_logic;
+  signal sample_ready_p        : std_logic;
+begin
+
+  p_ref_counter : process(clk_ref_i)
+  begin
+    if rising_edge(clk_ref_i) then
+      if pps_csync_p1_i = '1' or rst_n_ref_i = '0' then
+        cnt_ref_bin <= to_unsigned(0, g_counter_width);
+      elsif(cnt_ref_bin = g_ref_clock_rate - 1) then
+        cnt_ref_bin <= (others => '0');
+      else
+        cnt_ref_bin <= cnt_ref_bin + 1;
+      end if;
+    end if;
+  end process;
+
+  p_samplerate_divider : process(clk_ref_i)
+  begin
+    if rising_edge(clk_ref_i) then
+      if pps_csync_p1_i = '1' or rst_n_ref_i = '0' then
+        ref_div_p   <= '0';
+        cnt_ref_div <= to_unsigned(0, g_counter_width);
+      elsif (cnt_ref_div = c_div_ticks - 2) then
+        ref_div_p   <= '1';
+        cnt_ref_div <= cnt_ref_div + 1;
+      elsif (cnt_ref_div = c_div_ticks - 1) then
+        ref_div_p   <= '0';
+        cnt_ref_div <= (others => '0');
+      else
+        ref_div_p   <= '0';
+        cnt_ref_div <= cnt_ref_div + 1;
+      end if;
+    end if;
+  end process;
+
+  p_delay_ext_pps : process(clk_in_i)
+  begin
+    if rising_edge(clk_in_i) then
+      pps_ext_d0 <= pps_ext_a_i;
+    end if;
+  end process;
+
+  pps_ext_p <= not pps_ext_d0 and pps_ext_a_i;
+
+  p_in_counter : process(clk_in_i)
+  begin
+    if rising_edge(clk_in_i) then
+      if pps_ext_p = '1' or rst_n_ext_i = '0' then
+        cnt_in_bin <= to_unsigned(2, g_counter_width);
+      elsif(cnt_in_bin = g_in_clock_rate - 1) then
+        cnt_in_bin <= (others => '0');
+      else
+        cnt_in_bin <= cnt_in_bin + 1;
+      end if;
+    end if;
+  end process;
+
+  p_in_bin2gray : process (clk_in_i)
+  begin
+    if rising_edge(clk_in_i) then
+      cnt_in_gray <= f_gray_encode (std_logic_vector(cnt_in_bin));
+    end if;
+  end process;
+
+  p_sample_difference : process(clk_ref_i)
+  begin
+    if rising_edge(clk_ref_i) then
+      cnt_in_gray_x  <= cnt_in_gray;
+      cnt_in_gray_xd <= cnt_in_gray_x;
+
+      if(ref_div_p = '1') then
+        sample_cin_o  <= f_gray_decode(cnt_in_gray_xd, 1);
+        sample_cref_o <= std_logic_vector (cnt_ref_bin);
+      end if;
+    end if;
+  end process;
+
+  U_sync_sampling : gc_pulse_synchronizer2
+    port map (
+      clk_in_i    => clk_ref_i,
+      rst_in_n_i  => rst_n_ref_i,
+      clk_out_i   => clk_sys_i,
+      rst_out_n_i => rst_n_sys_i,
+      d_p_i       => ref_div_p,
+      q_p_o       => sample_ready_p);
+
+
+  p_gen_sample_valid : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_sys_i = '0' then
+        sample_valid_o <= '0';
+      else
+        if sample_ready_p = '1' then
+          sample_valid_o <= '1';
+        elsif sample_ack_i = '1' then
+          sample_valid_o <= '0';
+        end if;
+      end if;
+    end if;
+  end process;
+
+end rtl;
+
+
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_softpll_ng/spll_wb_slave.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_softpll_ng/spll_wb_slave.vhd
new file mode 100644
index 000000000..11a8687b7
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_softpll_ng/spll_wb_slave.vhd
@@ -0,0 +1,939 @@
+---------------------------------------------------------------------------------------
+-- Title          : Wishbone slave core for WR Softcore PLL
+---------------------------------------------------------------------------------------
+-- File           : spll_wb_slave.vhd
+-- Author         : auto-generated by wbgen2 from spll_wb_slave.wb
+-- Created        : Wed Aug 16 22:42:41 2017
+-- Standard       : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE spll_wb_slave.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.wbgen2_pkg.all;
+
+use work.spll_wbgen2_pkg.all;
+
+
+entity spll_wb_slave is
+  generic (
+        g_with_debug_fifo : integer := 1    );
+  port (
+    rst_n_i                                  : in     std_logic;
+    clk_sys_i                                : in     std_logic;
+    wb_adr_i                                 : in     std_logic_vector(5 downto 0);
+    wb_dat_i                                 : in     std_logic_vector(31 downto 0);
+    wb_dat_o                                 : out    std_logic_vector(31 downto 0);
+    wb_cyc_i                                 : in     std_logic;
+    wb_sel_i                                 : in     std_logic_vector(3 downto 0);
+    wb_stb_i                                 : in     std_logic;
+    wb_we_i                                  : in     std_logic;
+    wb_ack_o                                 : out    std_logic;
+    wb_stall_o                               : out    std_logic;
+    wb_int_o                                 : out    std_logic;
+    irq_tag_i                                : in     std_logic;
+    regs_i                                   : in     t_spll_in_registers;
+    regs_o                                   : out    t_spll_out_registers
+  );
+end spll_wb_slave;
+
+architecture syn of spll_wb_slave is
+
+signal spll_eccr_ext_en_int                     : std_logic      ;
+signal spll_eccr_ext_ref_pllrst_int             : std_logic      ;
+signal spll_occr_out_lock_int                   : std_logic_vector(7 downto 0);
+signal spll_deglitch_thr_int                    : std_logic_vector(15 downto 0);
+signal spll_dfr_host_rst_n                      : std_logic      ;
+signal spll_dfr_host_in_int                     : std_logic_vector(47 downto 0);
+signal spll_dfr_host_out_int                    : std_logic_vector(47 downto 0);
+signal spll_dfr_host_rdreq_int                  : std_logic      ;
+signal spll_dfr_host_rdreq_int_d0               : std_logic      ;
+signal spll_trr_rst_n                           : std_logic      ;
+signal spll_trr_in_int                          : std_logic_vector(31 downto 0);
+signal spll_trr_out_int                         : std_logic_vector(31 downto 0);
+signal spll_trr_rdreq_int                       : std_logic      ;
+signal spll_trr_rdreq_int_d0                    : std_logic      ;
+signal eic_idr_int                              : std_logic_vector(0 downto 0);
+signal eic_idr_write_int                        : std_logic      ;
+signal eic_ier_int                              : std_logic_vector(0 downto 0);
+signal eic_ier_write_int                        : std_logic      ;
+signal eic_imr_int                              : std_logic_vector(0 downto 0);
+signal eic_isr_clear_int                        : std_logic_vector(0 downto 0);
+signal eic_isr_status_int                       : std_logic_vector(0 downto 0);
+signal eic_irq_ack_int                          : std_logic_vector(0 downto 0);
+signal eic_isr_write_int                        : std_logic      ;
+signal spll_dfr_host_full_int                   : std_logic      ;
+signal spll_dfr_host_empty_int                  : std_logic      ;
+signal spll_dfr_host_usedw_int                  : std_logic_vector(12 downto 0);
+signal spll_trr_empty_int                       : std_logic      ;
+signal irq_inputs_vector_int                    : std_logic_vector(0 downto 0);
+signal ack_sreg                                 : std_logic_vector(9 downto 0);
+signal rddata_reg                               : std_logic_vector(31 downto 0);
+signal wrdata_reg                               : std_logic_vector(31 downto 0);
+signal rwaddr_reg                               : std_logic_vector(5 downto 0);
+signal ack_in_progress                          : std_logic      ;
+
+begin
+-- Some internal signals assignments
+  wrdata_reg <= wb_dat_i;
+-- 
+-- Main register bank access process.
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ack_sreg <= "0000000000";
+      ack_in_progress <= '0';
+      rddata_reg <= "00000000000000000000000000000000";
+      spll_eccr_ext_en_int <= '0';
+      spll_eccr_ext_ref_pllrst_int <= '0';
+      regs_o.al_cr_valid_load_o <= '0';
+      regs_o.f_dmtd_valid_load_o <= '0';
+      regs_o.f_ref_valid_load_o <= '0';
+      regs_o.f_ext_valid_load_o <= '0';
+      spll_occr_out_lock_int <= "00000000";
+      regs_o.rcer_load_o <= '0';
+      regs_o.ocer_load_o <= '0';
+      regs_o.dac_hpll_wr_o <= '0';
+      regs_o.dac_main_value_wr_o <= '0';
+      regs_o.dac_main_dac_sel_wr_o <= '0';
+      spll_deglitch_thr_int <= "0000000000000000";
+      regs_o.dfr_spll_value_wr_o <= '0';
+      regs_o.dfr_spll_eos_wr_o <= '0';
+      eic_idr_write_int <= '0';
+      eic_ier_write_int <= '0';
+      eic_isr_write_int <= '0';
+      spll_dfr_host_rdreq_int <= '0';
+      spll_trr_rdreq_int <= '0';
+    elsif rising_edge(clk_sys_i) then
+-- advance the ACK generator shift register
+      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
+      ack_sreg(9) <= '0';
+      if (ack_in_progress = '1') then
+        if (ack_sreg(0) = '1') then
+          regs_o.al_cr_valid_load_o <= '0';
+          regs_o.f_dmtd_valid_load_o <= '0';
+          regs_o.f_ref_valid_load_o <= '0';
+          regs_o.f_ext_valid_load_o <= '0';
+          regs_o.rcer_load_o <= '0';
+          regs_o.ocer_load_o <= '0';
+          regs_o.dac_hpll_wr_o <= '0';
+          regs_o.dac_main_value_wr_o <= '0';
+          regs_o.dac_main_dac_sel_wr_o <= '0';
+          regs_o.dfr_spll_value_wr_o <= '0';
+          regs_o.dfr_spll_eos_wr_o <= '0';
+          eic_idr_write_int <= '0';
+          eic_ier_write_int <= '0';
+          eic_isr_write_int <= '0';
+          ack_in_progress <= '0';
+        else
+          regs_o.al_cr_valid_load_o <= '0';
+          regs_o.f_dmtd_valid_load_o <= '0';
+          regs_o.f_ref_valid_load_o <= '0';
+          regs_o.f_ext_valid_load_o <= '0';
+          regs_o.rcer_load_o <= '0';
+          regs_o.ocer_load_o <= '0';
+          regs_o.dac_hpll_wr_o <= '0';
+          regs_o.dac_main_value_wr_o <= '0';
+          regs_o.dac_main_dac_sel_wr_o <= '0';
+          regs_o.dfr_spll_value_wr_o <= '0';
+          regs_o.dfr_spll_eos_wr_o <= '0';
+        end if;
+      else
+        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
+          case rwaddr_reg(5 downto 0) is
+          when "000000" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(13 downto 8) <= "000000";
+            rddata_reg(21 downto 16) <= regs_i.csr_n_ref_i;
+            rddata_reg(26 downto 24) <= regs_i.csr_n_out_i;
+            rddata_reg(27) <= regs_i.csr_dbg_supported_i;
+            rddata_reg(0) <= 'X';
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "000001" => 
+            if (wb_we_i = '1') then
+              spll_eccr_ext_en_int <= wrdata_reg(0);
+              spll_eccr_ext_ref_pllrst_int <= wrdata_reg(31);
+            end if;
+            rddata_reg(0) <= spll_eccr_ext_en_int;
+            rddata_reg(1) <= regs_i.eccr_ext_supported_i;
+            rddata_reg(2) <= regs_i.eccr_ext_ref_locked_i;
+            rddata_reg(3) <= regs_i.eccr_ext_ref_stopped_i;
+            rddata_reg(31) <= spll_eccr_ext_ref_pllrst_int;
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "000010" => 
+            if (wb_we_i = '1') then
+              regs_o.al_cr_valid_load_o <= '1';
+            end if;
+            rddata_reg(8 downto 0) <= regs_i.al_cr_valid_i;
+            rddata_reg(17 downto 9) <= regs_i.al_cr_required_i;
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "000011" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.al_cref_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "000100" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.al_cin_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "000101" => 
+            if (wb_we_i = '1') then
+              regs_o.f_dmtd_valid_load_o <= '1';
+            end if;
+            rddata_reg(27 downto 0) <= regs_i.f_dmtd_freq_i;
+            rddata_reg(28) <= regs_i.f_dmtd_valid_i;
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "000110" => 
+            if (wb_we_i = '1') then
+              regs_o.f_ref_valid_load_o <= '1';
+            end if;
+            rddata_reg(27 downto 0) <= regs_i.f_ref_freq_i;
+            rddata_reg(28) <= regs_i.f_ref_valid_i;
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "000111" => 
+            if (wb_we_i = '1') then
+              regs_o.f_ext_valid_load_o <= '1';
+            end if;
+            rddata_reg(27 downto 0) <= regs_i.f_ext_freq_i;
+            rddata_reg(28) <= regs_i.f_ext_valid_i;
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "001000" => 
+            if (wb_we_i = '1') then
+              spll_occr_out_lock_int <= wrdata_reg(23 downto 16);
+            end if;
+            rddata_reg(15 downto 8) <= regs_i.occr_out_en_i;
+            rddata_reg(23 downto 16) <= spll_occr_out_lock_int;
+            rddata_reg(0) <= 'X';
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "001001" => 
+            if (wb_we_i = '1') then
+              regs_o.rcer_load_o <= '1';
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.rcer_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "001010" => 
+            if (wb_we_i = '1') then
+              regs_o.ocer_load_o <= '1';
+            end if;
+            rddata_reg(7 downto 0) <= regs_i.ocer_i;
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "010000" => 
+            if (wb_we_i = '1') then
+              regs_o.dac_hpll_wr_o <= '1';
+            end if;
+            rddata_reg(0) <= 'X';
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "010001" => 
+            if (wb_we_i = '1') then
+              regs_o.dac_main_value_wr_o <= '1';
+              regs_o.dac_main_dac_sel_wr_o <= '1';
+            end if;
+            rddata_reg(0) <= 'X';
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "010010" => 
+            if (wb_we_i = '1') then
+              spll_deglitch_thr_int <= wrdata_reg(15 downto 0);
+            end if;
+            rddata_reg(15 downto 0) <= spll_deglitch_thr_int;
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "010011" => 
+            if (wb_we_i = '1') then
+              regs_o.dfr_spll_value_wr_o <= '1';
+              regs_o.dfr_spll_eos_wr_o <= '1';
+            end if;
+            rddata_reg(0) <= 'X';
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "011000" => 
+            if (wb_we_i = '1') then
+              eic_idr_write_int <= '1';
+            end if;
+            rddata_reg(0) <= 'X';
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "011001" => 
+            if (wb_we_i = '1') then
+              eic_ier_write_int <= '1';
+            end if;
+            rddata_reg(0) <= 'X';
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "011010" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(0) <= eic_imr_int(0);
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "011011" => 
+            if (wb_we_i = '1') then
+              eic_isr_write_int <= '1';
+            end if;
+            rddata_reg(0) <= eic_isr_status_int(0);
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "011100" => 
+            if (wb_we_i = '1') then
+            end if;
+            if (spll_dfr_host_rdreq_int_d0 = '0') then
+              spll_dfr_host_rdreq_int <= not spll_dfr_host_rdreq_int;
+            else
+              rddata_reg(31 downto 0) <= spll_dfr_host_out_int(31 downto 0);
+              ack_in_progress <= '1';
+              ack_sreg(0) <= '1';
+            end if;
+          when "011101" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(15 downto 0) <= spll_dfr_host_out_int(47 downto 32);
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "011110" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(16) <= spll_dfr_host_full_int;
+            rddata_reg(17) <= spll_dfr_host_empty_int;
+            rddata_reg(12 downto 0) <= spll_dfr_host_usedw_int;
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "011111" => 
+            if (wb_we_i = '1') then
+            end if;
+            if (spll_trr_rdreq_int_d0 = '0') then
+              spll_trr_rdreq_int <= not spll_trr_rdreq_int;
+            else
+              rddata_reg(23 downto 0) <= spll_trr_out_int(23 downto 0);
+              rddata_reg(30 downto 24) <= spll_trr_out_int(30 downto 24);
+              rddata_reg(31) <= spll_trr_out_int(31);
+              ack_in_progress <= '1';
+              ack_sreg(0) <= '1';
+            end if;
+          when "100000" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(17) <= spll_trr_empty_int;
+            rddata_reg(0) <= 'X';
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when others =>
+-- prevent the slave from hanging the bus on invalid address
+            ack_in_progress <= '1';
+            ack_sreg(0) <= '1';
+          end case;
+        end if;
+      end if;
+    end if;
+  end process;
+  
+  
+-- Drive the data output bus
+  wb_dat_o <= rddata_reg;
+-- Number of reference channels (max: 32)
+-- Number of output channels (max: 8)
+-- Debug queue supported
+-- Enable External Clock PLL
+  regs_o.eccr_ext_en_o <= spll_eccr_ext_en_int;
+-- External Clock Input Available
+-- External Clock Reference Present
+-- EXT_REF_STOPPED
+-- EXT_PLL_RST
+  regs_o.eccr_ext_ref_pllrst_o <= spll_eccr_ext_ref_pllrst_int;
+-- Aligner sample valid/select on channel
+  regs_o.al_cr_valid_o <= wrdata_reg(8 downto 0);
+-- Aligner required on channel
+-- Aligner reference counter
+-- Aligner reference counter
+-- FREQ
+-- VALID
+  regs_o.f_dmtd_valid_o <= wrdata_reg(28);
+-- FREQ
+-- VALID
+  regs_o.f_ref_valid_o <= wrdata_reg(28);
+-- FREQ
+-- VALID
+  regs_o.f_ext_valid_o <= wrdata_reg(28);
+-- Output Channel HW enable flag
+-- Output Channel locked flag
+  regs_o.occr_out_lock_o <= spll_occr_out_lock_int;
+-- Reference Channel Enable
+  regs_o.rcer_o <= wrdata_reg(31 downto 0);
+-- Output Channel Enable
+  regs_o.ocer_o <= wrdata_reg(7 downto 0);
+-- DAC value
+-- pass-through field: DAC value in register: Helper DAC Output
+  regs_o.dac_hpll_o <= wrdata_reg(15 downto 0);
+-- DAC value
+-- pass-through field: DAC value in register: Main DAC Output
+  regs_o.dac_main_value_o <= wrdata_reg(15 downto 0);
+-- DAC select
+-- pass-through field: DAC select in register: Main DAC Output
+  regs_o.dac_main_dac_sel_o <= wrdata_reg(19 downto 16);
+-- Threshold
+  regs_o.deglitch_thr_o <= spll_deglitch_thr_int;
+-- Debug Value
+-- pass-through field: Debug Value in register: Debug FIFO Register - SPLL side
+  regs_o.dfr_spll_value_o <= wrdata_reg(30 downto 0);
+-- End-of-Sample
+-- pass-through field: End-of-Sample in register: Debug FIFO Register - SPLL side
+  regs_o.dfr_spll_eos_o <= wrdata_reg(31);
+  genblock_0: if (not (g_with_debug_fifo = 0)) generate
+-- extra code for reg/fifo/mem: Debug FIFO Register - Host side
+    spll_dfr_host_in_int(31 downto 0) <= regs_i.dfr_host_value_i;
+    spll_dfr_host_in_int(47 downto 32) <= regs_i.dfr_host_seq_id_i;
+    spll_dfr_host_rst_n <= rst_n_i;
+    spll_dfr_host_INST : wbgen2_fifo_sync
+      generic map (
+        g_size               => 8192,
+        g_width              => 48,
+        g_usedw_size         => 13
+      )
+      port map (
+        wr_req_i             => regs_i.dfr_host_wr_req_i,
+        wr_full_o            => regs_o.dfr_host_wr_full_o,
+        wr_empty_o           => regs_o.dfr_host_wr_empty_o,
+        wr_usedw_o           => regs_o.dfr_host_wr_usedw_o,
+        rd_full_o            => spll_dfr_host_full_int,
+        rd_empty_o           => spll_dfr_host_empty_int,
+        rd_usedw_o           => spll_dfr_host_usedw_int,
+        rd_req_i             => spll_dfr_host_rdreq_int,
+        rst_n_i              => spll_dfr_host_rst_n,
+        clk_i                => clk_sys_i,
+        wr_data_i            => spll_dfr_host_in_int,
+        rd_data_o            => spll_dfr_host_out_int
+      );
+    
+  end generate genblock_0;
+  genblock_1: if (g_with_debug_fifo = 0) generate
+    regs_o.dfr_host_wr_full_o <= '0';
+    regs_o.dfr_host_wr_empty_o <= '0';
+    regs_o.dfr_host_wr_usedw_o <= "0000000000000";
+  end generate genblock_1;
+-- extra code for reg/fifo/mem: Tag Readout Register
+  spll_trr_in_int(23 downto 0) <= regs_i.trr_value_i;
+  spll_trr_in_int(30 downto 24) <= regs_i.trr_chan_id_i;
+  spll_trr_in_int(31) <= regs_i.trr_disc_i;
+  spll_trr_rst_n <= rst_n_i;
+  spll_trr_INST : wbgen2_fifo_sync
+    generic map (
+      g_size               => 32,
+      g_width              => 32,
+      g_usedw_size         => 5
+    )
+    port map (
+      wr_req_i             => regs_i.trr_wr_req_i,
+      wr_full_o            => regs_o.trr_wr_full_o,
+      wr_empty_o           => regs_o.trr_wr_empty_o,
+      rd_empty_o           => spll_trr_empty_int,
+      rd_req_i             => spll_trr_rdreq_int,
+      rst_n_i              => spll_trr_rst_n,
+      clk_i                => clk_sys_i,
+      wr_data_i            => spll_trr_in_int,
+      rd_data_o            => spll_trr_out_int
+    );
+  
+-- extra code for reg/fifo/mem: Interrupt disable register
+  eic_idr_int(0) <= wrdata_reg(0);
+-- extra code for reg/fifo/mem: Interrupt enable register
+  eic_ier_int(0) <= wrdata_reg(0);
+-- extra code for reg/fifo/mem: Interrupt status register
+  eic_isr_clear_int(0) <= wrdata_reg(0);
+-- extra code for reg/fifo/mem: IRQ_CONTROLLER
+  eic_irq_controller_inst : wbgen2_eic
+    generic map (
+      g_num_interrupts     => 1,
+      g_irq00_mode         => 3,
+      g_irq01_mode         => 0,
+      g_irq02_mode         => 0,
+      g_irq03_mode         => 0,
+      g_irq04_mode         => 0,
+      g_irq05_mode         => 0,
+      g_irq06_mode         => 0,
+      g_irq07_mode         => 0,
+      g_irq08_mode         => 0,
+      g_irq09_mode         => 0,
+      g_irq0a_mode         => 0,
+      g_irq0b_mode         => 0,
+      g_irq0c_mode         => 0,
+      g_irq0d_mode         => 0,
+      g_irq0e_mode         => 0,
+      g_irq0f_mode         => 0,
+      g_irq10_mode         => 0,
+      g_irq11_mode         => 0,
+      g_irq12_mode         => 0,
+      g_irq13_mode         => 0,
+      g_irq14_mode         => 0,
+      g_irq15_mode         => 0,
+      g_irq16_mode         => 0,
+      g_irq17_mode         => 0,
+      g_irq18_mode         => 0,
+      g_irq19_mode         => 0,
+      g_irq1a_mode         => 0,
+      g_irq1b_mode         => 0,
+      g_irq1c_mode         => 0,
+      g_irq1d_mode         => 0,
+      g_irq1e_mode         => 0,
+      g_irq1f_mode         => 0
+    )
+    port map (
+      clk_i                => clk_sys_i,
+      rst_n_i              => rst_n_i,
+      irq_i                => irq_inputs_vector_int,
+      irq_ack_o            => eic_irq_ack_int,
+      reg_imr_o            => eic_imr_int,
+      reg_ier_i            => eic_ier_int,
+      reg_ier_wr_stb_i     => eic_ier_write_int,
+      reg_idr_i            => eic_idr_int,
+      reg_idr_wr_stb_i     => eic_idr_write_int,
+      reg_isr_o            => eic_isr_status_int,
+      reg_isr_i            => eic_isr_clear_int,
+      reg_isr_wr_stb_i     => eic_isr_write_int,
+      wb_irq_o             => wb_int_o
+    );
+  
+  irq_inputs_vector_int(0) <= irq_tag_i;
+-- extra code for reg/fifo/mem: FIFO 'Debug FIFO Register - Host side' data output register 0
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      spll_dfr_host_rdreq_int_d0 <= '0';
+    elsif rising_edge(clk_sys_i) then
+      spll_dfr_host_rdreq_int_d0 <= spll_dfr_host_rdreq_int;
+    end if;
+  end process;
+  
+  
+-- extra code for reg/fifo/mem: FIFO 'Debug FIFO Register - Host side' data output register 1
+-- extra code for reg/fifo/mem: FIFO 'Tag Readout Register' data output register 0
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      spll_trr_rdreq_int_d0 <= '0';
+    elsif rising_edge(clk_sys_i) then
+      spll_trr_rdreq_int_d0 <= spll_trr_rdreq_int;
+    end if;
+  end process;
+  
+  
+  rwaddr_reg <= wb_adr_i;
+  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
+-- ACK signal generation. Just pass the LSB of ACK counter.
+  wb_ack_o <= ack_sreg(0);
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
new file mode 100644
index 000000000..5550a3dd8
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
@@ -0,0 +1,207 @@
+---------------------------------------------------------------------------------------
+-- Title          : Wishbone slave core for WR Softcore PLL
+---------------------------------------------------------------------------------------
+-- File           : spll_wbgen2_pkg.vhd
+-- Author         : auto-generated by wbgen2 from spll_wb_slave.wb
+-- Created        : Wed Aug 16 22:42:41 2017
+-- Standard       : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE spll_wb_slave.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.wbgen2_pkg.all;
+
+package spll_wbgen2_pkg is
+  
+  
+  -- Input registers (user design -> WB slave)
+  
+  type t_spll_in_registers is record
+    csr_n_ref_i                              : std_logic_vector(5 downto 0);
+    csr_n_out_i                              : std_logic_vector(2 downto 0);
+    csr_dbg_supported_i                      : std_logic;
+    eccr_ext_supported_i                     : std_logic;
+    eccr_ext_ref_locked_i                    : std_logic;
+    eccr_ext_ref_stopped_i                   : std_logic;
+    al_cr_valid_i                            : std_logic_vector(8 downto 0);
+    al_cr_required_i                         : std_logic_vector(8 downto 0);
+    al_cref_i                                : std_logic_vector(31 downto 0);
+    al_cin_i                                 : std_logic_vector(31 downto 0);
+    f_dmtd_freq_i                            : std_logic_vector(27 downto 0);
+    f_dmtd_valid_i                           : std_logic;
+    f_ref_freq_i                             : std_logic_vector(27 downto 0);
+    f_ref_valid_i                            : std_logic;
+    f_ext_freq_i                             : std_logic_vector(27 downto 0);
+    f_ext_valid_i                            : std_logic;
+    occr_out_en_i                            : std_logic_vector(7 downto 0);
+    rcer_i                                   : std_logic_vector(31 downto 0);
+    ocer_i                                   : std_logic_vector(7 downto 0);
+    dfr_host_wr_req_i                        : std_logic;
+    dfr_host_value_i                         : std_logic_vector(31 downto 0);
+    dfr_host_seq_id_i                        : std_logic_vector(15 downto 0);
+    trr_wr_req_i                             : std_logic;
+    trr_value_i                              : std_logic_vector(23 downto 0);
+    trr_chan_id_i                            : std_logic_vector(6 downto 0);
+    trr_disc_i                               : std_logic;
+    end record;
+  
+  constant c_spll_in_registers_init_value: t_spll_in_registers := (
+    csr_n_ref_i => (others => '0'),
+    csr_n_out_i => (others => '0'),
+    csr_dbg_supported_i => '0',
+    eccr_ext_supported_i => '0',
+    eccr_ext_ref_locked_i => '0',
+    eccr_ext_ref_stopped_i => '0',
+    al_cr_valid_i => (others => '0'),
+    al_cr_required_i => (others => '0'),
+    al_cref_i => (others => '0'),
+    al_cin_i => (others => '0'),
+    f_dmtd_freq_i => (others => '0'),
+    f_dmtd_valid_i => '0',
+    f_ref_freq_i => (others => '0'),
+    f_ref_valid_i => '0',
+    f_ext_freq_i => (others => '0'),
+    f_ext_valid_i => '0',
+    occr_out_en_i => (others => '0'),
+    rcer_i => (others => '0'),
+    ocer_i => (others => '0'),
+    dfr_host_wr_req_i => '0',
+    dfr_host_value_i => (others => '0'),
+    dfr_host_seq_id_i => (others => '0'),
+    trr_wr_req_i => '0',
+    trr_value_i => (others => '0'),
+    trr_chan_id_i => (others => '0'),
+    trr_disc_i => '0'
+    );
+    
+    -- Output registers (WB slave -> user design)
+    
+    type t_spll_out_registers is record
+      eccr_ext_en_o                            : std_logic;
+      eccr_ext_ref_pllrst_o                    : std_logic;
+      al_cr_valid_o                            : std_logic_vector(8 downto 0);
+      al_cr_valid_load_o                       : std_logic;
+      f_dmtd_valid_o                           : std_logic;
+      f_dmtd_valid_load_o                      : std_logic;
+      f_ref_valid_o                            : std_logic;
+      f_ref_valid_load_o                       : std_logic;
+      f_ext_valid_o                            : std_logic;
+      f_ext_valid_load_o                       : std_logic;
+      occr_out_lock_o                          : std_logic_vector(7 downto 0);
+      rcer_o                                   : std_logic_vector(31 downto 0);
+      rcer_load_o                              : std_logic;
+      ocer_o                                   : std_logic_vector(7 downto 0);
+      ocer_load_o                              : std_logic;
+      dac_hpll_o                               : std_logic_vector(15 downto 0);
+      dac_hpll_wr_o                            : std_logic;
+      dac_main_value_o                         : std_logic_vector(15 downto 0);
+      dac_main_value_wr_o                      : std_logic;
+      dac_main_dac_sel_o                       : std_logic_vector(3 downto 0);
+      dac_main_dac_sel_wr_o                    : std_logic;
+      deglitch_thr_o                           : std_logic_vector(15 downto 0);
+      dfr_spll_value_o                         : std_logic_vector(30 downto 0);
+      dfr_spll_value_wr_o                      : std_logic;
+      dfr_spll_eos_o                           : std_logic;
+      dfr_spll_eos_wr_o                        : std_logic;
+      dfr_host_wr_full_o                       : std_logic;
+      dfr_host_wr_empty_o                      : std_logic;
+      dfr_host_wr_usedw_o                      : std_logic_vector(12 downto 0);
+      trr_wr_full_o                            : std_logic;
+      trr_wr_empty_o                           : std_logic;
+      end record;
+    
+    constant c_spll_out_registers_init_value: t_spll_out_registers := (
+      eccr_ext_en_o => '0',
+      eccr_ext_ref_pllrst_o => '0',
+      al_cr_valid_o => (others => '0'),
+      al_cr_valid_load_o => '0',
+      f_dmtd_valid_o => '0',
+      f_dmtd_valid_load_o => '0',
+      f_ref_valid_o => '0',
+      f_ref_valid_load_o => '0',
+      f_ext_valid_o => '0',
+      f_ext_valid_load_o => '0',
+      occr_out_lock_o => (others => '0'),
+      rcer_o => (others => '0'),
+      rcer_load_o => '0',
+      ocer_o => (others => '0'),
+      ocer_load_o => '0',
+      dac_hpll_o => (others => '0'),
+      dac_hpll_wr_o => '0',
+      dac_main_value_o => (others => '0'),
+      dac_main_value_wr_o => '0',
+      dac_main_dac_sel_o => (others => '0'),
+      dac_main_dac_sel_wr_o => '0',
+      deglitch_thr_o => (others => '0'),
+      dfr_spll_value_o => (others => '0'),
+      dfr_spll_value_wr_o => '0',
+      dfr_spll_eos_o => '0',
+      dfr_spll_eos_wr_o => '0',
+      dfr_host_wr_full_o => '0',
+      dfr_host_wr_empty_o => '0',
+      dfr_host_wr_usedw_o => (others => '0'),
+      trr_wr_full_o => '0',
+      trr_wr_empty_o => '0'
+      );
+    function "or" (left, right: t_spll_in_registers) return t_spll_in_registers;
+    function f_x_to_zero (x:std_logic) return std_logic;
+    function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
+end package;
+
+package body spll_wbgen2_pkg is
+function f_x_to_zero (x:std_logic) return std_logic is
+begin
+if x = '1' then
+return '1';
+else
+return '0';
+end if;
+end function;
+function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
+variable tmp: std_logic_vector(x'length-1 downto 0);
+begin
+for i in 0 to x'length-1 loop
+if x(i) = '1' then
+tmp(i):= '1';
+else
+tmp(i):= '0';
+end if; 
+end loop; 
+return tmp;
+end function;
+function "or" (left, right: t_spll_in_registers) return t_spll_in_registers is
+variable tmp: t_spll_in_registers;
+begin
+tmp.csr_n_ref_i := f_x_to_zero(left.csr_n_ref_i) or f_x_to_zero(right.csr_n_ref_i);
+tmp.csr_n_out_i := f_x_to_zero(left.csr_n_out_i) or f_x_to_zero(right.csr_n_out_i);
+tmp.csr_dbg_supported_i := f_x_to_zero(left.csr_dbg_supported_i) or f_x_to_zero(right.csr_dbg_supported_i);
+tmp.eccr_ext_supported_i := f_x_to_zero(left.eccr_ext_supported_i) or f_x_to_zero(right.eccr_ext_supported_i);
+tmp.eccr_ext_ref_locked_i := f_x_to_zero(left.eccr_ext_ref_locked_i) or f_x_to_zero(right.eccr_ext_ref_locked_i);
+tmp.eccr_ext_ref_stopped_i := f_x_to_zero(left.eccr_ext_ref_stopped_i) or f_x_to_zero(right.eccr_ext_ref_stopped_i);
+tmp.al_cr_valid_i := f_x_to_zero(left.al_cr_valid_i) or f_x_to_zero(right.al_cr_valid_i);
+tmp.al_cr_required_i := f_x_to_zero(left.al_cr_required_i) or f_x_to_zero(right.al_cr_required_i);
+tmp.al_cref_i := f_x_to_zero(left.al_cref_i) or f_x_to_zero(right.al_cref_i);
+tmp.al_cin_i := f_x_to_zero(left.al_cin_i) or f_x_to_zero(right.al_cin_i);
+tmp.f_dmtd_freq_i := f_x_to_zero(left.f_dmtd_freq_i) or f_x_to_zero(right.f_dmtd_freq_i);
+tmp.f_dmtd_valid_i := f_x_to_zero(left.f_dmtd_valid_i) or f_x_to_zero(right.f_dmtd_valid_i);
+tmp.f_ref_freq_i := f_x_to_zero(left.f_ref_freq_i) or f_x_to_zero(right.f_ref_freq_i);
+tmp.f_ref_valid_i := f_x_to_zero(left.f_ref_valid_i) or f_x_to_zero(right.f_ref_valid_i);
+tmp.f_ext_freq_i := f_x_to_zero(left.f_ext_freq_i) or f_x_to_zero(right.f_ext_freq_i);
+tmp.f_ext_valid_i := f_x_to_zero(left.f_ext_valid_i) or f_x_to_zero(right.f_ext_valid_i);
+tmp.occr_out_en_i := f_x_to_zero(left.occr_out_en_i) or f_x_to_zero(right.occr_out_en_i);
+tmp.rcer_i := f_x_to_zero(left.rcer_i) or f_x_to_zero(right.rcer_i);
+tmp.ocer_i := f_x_to_zero(left.ocer_i) or f_x_to_zero(right.ocer_i);
+tmp.dfr_host_wr_req_i := f_x_to_zero(left.dfr_host_wr_req_i) or f_x_to_zero(right.dfr_host_wr_req_i);
+tmp.dfr_host_value_i := f_x_to_zero(left.dfr_host_value_i) or f_x_to_zero(right.dfr_host_value_i);
+tmp.dfr_host_seq_id_i := f_x_to_zero(left.dfr_host_seq_id_i) or f_x_to_zero(right.dfr_host_seq_id_i);
+tmp.trr_wr_req_i := f_x_to_zero(left.trr_wr_req_i) or f_x_to_zero(right.trr_wr_req_i);
+tmp.trr_value_i := f_x_to_zero(left.trr_value_i) or f_x_to_zero(right.trr_value_i);
+tmp.trr_chan_id_i := f_x_to_zero(left.trr_chan_id_i) or f_x_to_zero(right.trr_chan_id_i);
+tmp.trr_disc_i := f_x_to_zero(left.trr_disc_i) or f_x_to_zero(right.trr_disc_i);
+return tmp;
+end function;
+end package body;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_softpll_ng/wr_softpll_ng.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_softpll_ng/wr_softpll_ng.vhd
new file mode 100644
index 000000000..351b60f19
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_softpll_ng/wr_softpll_ng.vhd
@@ -0,0 +1,809 @@
+-------------------------------------------------------------------------------
+-- Title      : White Rabbit Softcore PLL (new generation) - SoftPLL-ng
+-- Project    : White Rabbit
+-------------------------------------------------------------------------------
+-- File       : wr_softpll_ng.vhd
+-- Author     : Tomasz Włostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2011-01-29
+-- Last update: 2017-02-20
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: 
+--
+-- The hardware part of the revised softcore PLL. Incorporates a user-defined
+-- number of DDMTD taggers, a FIFO allowing for sequential readout of
+-- the phase tags and ports for driving oscillator tuning DACs.
+-- The rest of the magic is done in the software.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012-2017 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.gencores_pkg.all;
+use work.wishbone_pkg.all;
+use work.softpll_pkg.all;
+use work.spll_wbgen2_pkg.all;
+
+entity wr_softpll_ng is
+  generic(
+-- Number of bits in phase tags produced by DDMTDs.
+-- Must be large enough to cover at least a hundred of DDMTD periods to ensure
+-- correct operation of the SoftPLL software servo algorithm - that
+-- means, for a typical DMTD frequency offset N=16384, there number of tag bits
+-- should be log2(N) + 7 == 21. Note: the value must match the TAG_BITS constant
+-- in spll_defs.h file!
+    g_tag_bits : integer;
+
+-- These two are obvious:
+    g_num_ref_inputs : integer := 1;
+    g_num_outputs    : integer := 1;
+
+-- When true, an additional FIFO is instantiated, providing a realtime record
+-- of user-selectable SoftPLL parameters (e.g. tag values, phase error, DAC drive).
+-- These values can be read by "spll_dbg_proxy" daemon for further analysis.
+    g_with_debug_fifo : boolean := false;
+
+-- When true, an additional accumulating bang-bang phase detector is instantiated
+-- for wideband locking of the local oscillator to an external stable reference
+-- (e.g. GPSDO/Cesium 10 MHz)
+    g_with_ext_clock_input : boolean := false;
+
+-- When true, DDMTD inputs are reversed (so that the DDMTD offset clocks is
+-- being sampled by the measured clock). This is functionally equivalent to
+-- "direct" operation, but may improve FPGA timing/routability.
+    g_reverse_dmtds : boolean := true;
+
+-- Divides the DDMTD clock inputs by 2, removing the "CLOCK_DEDICATED_ROUTE"
+-- errors under ISE tools, at the cost of bandwidth reduction. Advanced option
+-- use with care.
+    g_divide_input_by_2 : boolean := false;
+
+    g_ref_clock_rate : integer := 125000000;
+    g_ext_clock_rate : integer := 10000000;
+
+
+    g_interface_mode      : t_wishbone_interface_mode      := PIPELINED;
+    g_address_granularity : t_wishbone_address_granularity := WORD
+    );
+
+  port(
+    clk_sys_i    : in std_logic;
+    rst_sys_n_i  : in std_logic;
+    rst_ref_n_i  : in std_logic;
+    rst_ext_n_i  : in std_logic;
+    rst_dmtd_n_i : in std_logic;
+
+-- Reference inputs (i.e. the RX clocks recovered by the PHYs)
+    clk_ref_i : in std_logic_vector(g_num_ref_inputs-1 downto 0);
+
+-- Feedback clocks (i.e. the outputs of the main or auxillary oscillator)
+-- Note: clk_fb_i(0) must be always connected to the primary board's oscillator
+-- (i.e. the one driving the PTP and Ethernet PHY) to ensure correct operation
+-- of the PTP core.
+    clk_fb_i : in std_logic_vector(g_num_outputs-1 downto 0);
+
+-- DMTD Offset clock
+    clk_dmtd_i : in std_logic;
+
+-- External reference clock (e.g. 10 MHz from Cesium/GPSDO). Used only if
+-- g_with_ext_clock_input == true
+    clk_ext_i : in std_logic;
+
+-- External clock, multiplied to 125 MHz using the FPGA's PLL
+    clk_ext_mul_i : in std_logic;
+    clk_ext_mul_locked_i : in std_logic := '1';
+    clk_ext_stopped_i : in std_logic := '0';
+    clk_ext_rst_o : out std_logic;
+
+-- External clock sync/alignment singnal. SoftPLL will align clk_ext_i/clk_fb_i(0)
+-- to match the edges immediately following the rising edge in sync_p_i.
+    pps_csync_p1_i : in std_logic;
+    pps_ext_a_i    : in std_logic;
+
+-- DMTD oscillator drive
+    dac_dmtd_data_o : out std_logic_vector(15 downto 0);
+-- When HI, load the data from dac_dmtd_data_o to the DAC.
+    dac_dmtd_load_o : out std_logic;
+
+-- Output channel DAC value
+    dac_out_data_o : out std_logic_vector(15 downto 0);
+-- Output channel select (0 = Output channel 0, 1 == OC 1, etc...)
+    dac_out_sel_o  : out std_logic_vector(3 downto 0);
+    dac_out_load_o : out std_logic;
+
+-- Output enable input: when HI, enables locking the output(s)
+-- to the reference clock(s)
+    out_enable_i : in  std_logic_vector(g_num_outputs-1 downto 0);
+-- When HI, the respective clock output is locked.
+    out_locked_o : out std_logic_vector(g_num_outputs-1 downto 0);
+
+    wb_adr_i   : in  std_logic_vector(c_wishbone_address_width-1 downto 0);
+    wb_dat_i   : in  std_logic_vector(c_wishbone_data_width-1 downto 0);
+    wb_dat_o   : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+    wb_cyc_i   : in  std_logic;
+    wb_sel_i   : in  std_logic_vector(c_wishbone_data_width/8-1 downto 0);
+    wb_stb_i   : in  std_logic;
+    wb_we_i    : in  std_logic;
+    wb_ack_o   : out std_logic;
+    wb_stall_o : out std_logic;
+    wb_irq_o   : out std_logic;
+    debug_o    : out std_logic_vector(5 downto 0);
+
+-- Debug FIFO readout interrupt
+    dbg_fifo_irq_o : out std_logic
+    );
+
+end wr_softpll_ng;
+
+architecture rtl of wr_softpll_ng is
+
+  alias rst_n_i : std_logic is rst_sys_n_i;
+
+  constant c_log2_replication : integer := 2;
+  constant c_use_multi_dmtd   : boolean := false;
+
+  constant c_DBG_FIFO_THRESHOLD : integer := 8180;
+  constant c_DBG_FIFO_COALESCE  : integer := 100;
+  constant c_BB_ERROR_BITS      : integer := 16;
+
+  component dmtd_with_deglitcher
+    generic (
+      g_counter_bits      : natural;
+      g_divide_input_by_2 : boolean;
+			g_reverse           :	boolean);
+    port (
+      rst_n_dmtdclk_i      : in  std_logic;
+      rst_n_sysclk_i       : in  std_logic;
+      clk_in_i             : in  std_logic;
+      clk_dmtd_i           : in  std_logic;
+      clk_sys_i            : in  std_logic;
+      resync_p_a_i         : in  std_logic := '0';
+      resync_p_o           : out std_logic;
+      resync_start_p_i     : in  std_logic;
+      resync_done_o        : out std_logic;
+      shift_en_i           : in  std_logic;
+      shift_dir_i          : in  std_logic;
+      clk_dmtd_en_i        : in  std_logic := '1';
+      deglitch_threshold_i : in  std_logic_vector(15 downto 0);
+      dbg_dmtdout_o        : out std_logic;
+      tag_o                : out std_logic_vector(g_counter_bits-1 downto 0);
+      tag_stb_p1_o         : out std_logic;
+			dbg_clk_d3_o         : out std_logic);
+  end component;
+
+  component spll_wb_slave
+    generic (
+      g_with_debug_fifo : integer);
+    port (
+      rst_n_i    : in  std_logic;
+      clk_sys_i  : in  std_logic;
+      wb_adr_i   : in  std_logic_vector(5 downto 0);
+      wb_dat_i   : in  std_logic_vector(31 downto 0);
+      wb_dat_o   : out std_logic_vector(31 downto 0);
+      wb_cyc_i   : in  std_logic;
+      wb_sel_i   : in  std_logic_vector(3 downto 0);
+      wb_stb_i   : in  std_logic;
+      wb_we_i    : in  std_logic;
+      wb_ack_o   : out std_logic;
+      wb_stall_o : out std_logic;
+      wb_int_o   : out std_logic;
+      irq_tag_i  : in  std_logic;
+      regs_i     : in  t_spll_in_registers;
+      regs_o     : out t_spll_out_registers);
+  end component;
+
+  component spll_aligner
+    generic (
+      g_counter_width  : integer;
+      g_ref_clock_rate : integer;
+      g_in_clock_rate  : integer;
+      g_sample_rate    : integer);
+    port (
+      clk_sys_i      : in  std_logic;
+      clk_in_i       : in  std_logic;
+      clk_ref_i      : in  std_logic;
+      rst_n_sys_i    : in  std_logic;
+      rst_n_ref_i    : in  std_logic;
+      rst_n_ext_i    : in  std_logic;
+      pps_ext_a_i    : in  std_logic;
+      pps_csync_p1_i : in  std_logic;
+      sample_cref_o  : out std_logic_vector(g_counter_width-1 downto 0);
+      sample_cin_o   : out std_logic_vector(g_counter_width-1 downto 0);
+      sample_valid_o : out std_logic;
+      sample_ack_i   : in  std_logic);
+  end component;
+  function f_num_total_channels
+    return integer is
+  begin
+    if(g_with_ext_clock_input) then
+      return g_num_ref_inputs + g_num_outputs + 1;
+    else
+      return g_num_ref_inputs + g_num_outputs;
+    end if;
+  end f_num_total_channels;
+
+  function f_pick (
+    cond     : boolean;
+    if_true  : std_logic;
+    if_false : std_logic
+    ) return std_logic is
+  begin
+    if(cond) then
+      return if_true;
+    else
+      return if_false;
+    end if;
+  end f_pick;
+
+  function f_pick (
+    cond     : boolean;
+    if_true  : integer;
+    if_false : integer
+    ) return integer is
+  begin
+    if(cond) then
+      return if_true;
+    else
+      return if_false;
+    end if;
+  end f_pick;
+
+  function resize(x : std_logic_vector; new_length : integer) return std_logic_vector is
+    variable tmp : std_logic_vector(new_length-1 downto 0);
+  begin
+    tmp                       := (others => '0');
+    tmp (x'length-1 downto 0) := x;
+    return tmp;
+  end resize;
+
+  type t_tag_array is array (0 to f_num_total_channels-1) of std_logic_vector(g_tag_bits-1 downto 0);
+
+  type t_phase_error_array is array(0 to g_num_outputs-1) of std_logic_vector(c_BB_ERROR_BITS-1 downto 0);
+
+  signal tags, tags_masked                          : t_tag_array;
+  signal tags_grant_p, tags_p, tags_req, tags_grant : std_logic_vector(f_num_total_channels-1 downto 0);
+  signal tag_muxed                                  : std_logic_vector(g_tag_bits-1 downto 0);
+  signal tag_src, tag_src_pre                       : std_logic_vector (5 downto 0);
+  signal tag_valid, tag_valid_pre                   : std_logic;
+
+  signal deglitch_thr_slv : std_logic_vector(15 downto 0);
+
+  signal irq_tag : std_logic;
+
+  signal rcer_int : std_logic_vector(g_num_ref_inputs-1 downto 0);
+  signal ocer_int : std_logic_vector(g_num_outputs-1 downto 0);
+
+  signal wb_irq_out : std_logic;
+
+  signal wb_out   : t_wishbone_slave_out;
+  signal wb_in    : t_wishbone_slave_in;
+  signal regs_in  : t_SPLL_out_registers;
+  signal regs_out : t_SPLL_in_registers;
+
+  -- Debug FIFO signals
+  signal dbg_fifo_almostfull   : std_logic;
+  signal dbg_seq_id            : unsigned(15 downto 0);
+  signal dbg_fifo_permit_write : std_logic;
+  signal dbg_fifo_irq          : std_logic := '0';
+
+  -- Temporary vectors for DDMTD clock selection (straight/reversed)
+  signal dmtd_ref_clk_in, dmtd_ref_clk_dmtd : std_logic_vector(g_num_ref_inputs-1 downto 0);
+  signal rst_n_dmtd_ref_clk                 : std_logic_vector(g_num_ref_inputs-1 downto 0);
+
+  signal dmtd_fb_clk_in, dmtd_fb_clk_dmtd : std_logic_vector(g_num_outputs-1 downto 0);
+  signal rst_n_dmtd_fb_clk                : std_logic_vector(g_num_outputs-1 downto 0);
+
+  signal ext_ref_present : std_logic;
+  signal fb_resync_out   : std_logic_vector(g_num_outputs-1 downto 0);
+
+  signal ref_resync_start_p : std_logic_vector(31 downto 0);
+  signal fb_resync_start_p  : std_logic_vector(15 downto 0);
+
+  type t_aligner_sample_array is array(0 to g_num_outputs) of std_logic_vector(27 downto 0);
+
+  signal aligner_sample_valid, aligner_sample_ack : std_logic_vector(g_num_outputs downto 0);
+  signal aligner_sample_cref, aligner_sample_cin  : t_aligner_sample_array;
+  
+begin  -- rtl
+
+  U_Adapter : wb_slave_adapter
+    generic map(
+      g_master_use_struct  => true,
+      g_master_mode        => CLASSIC,
+      g_master_granularity => WORD,
+      g_slave_use_struct   => false,
+      g_slave_mode         => g_interface_mode,
+      g_slave_granularity  => g_address_granularity)
+    port map (
+      clk_sys_i  => clk_sys_i,
+      rst_n_i    => rst_n_i,
+      master_i   => wb_out,
+      master_o   => wb_in,
+      sl_adr_i   => wb_adr_i,
+      sl_dat_i   => wb_dat_i,
+      sl_sel_i   => wb_sel_i,
+      sl_cyc_i   => wb_cyc_i,
+      sl_stb_i   => wb_stb_i,
+      sl_we_i    => wb_we_i,
+      sl_dat_o   => wb_dat_o,
+      sl_ack_o   => wb_ack_o,
+      sl_stall_o => wb_stall_o);
+
+  U_Meas_DMTD_Freq: gc_frequency_meter
+    generic map (
+      g_with_internal_timebase => false,
+      g_clk_sys_freq           => 1,
+      g_counter_bits           => 28)
+    port map (
+      clk_sys_i    => clk_sys_i,
+      clk_in_i     => clk_dmtd_i,
+      rst_n_i      => rst_n_i,
+      pps_p1_i     => pps_ext_a_i,
+      freq_o       => regs_out.f_dmtd_freq_i,
+      freq_valid_o => open);            -- fixme
+
+  U_Meas_REF_Freq: gc_frequency_meter
+    generic map (
+      g_with_internal_timebase => false,
+      g_clk_sys_freq           => 1,
+      g_counter_bits           => 28)
+    port map (
+      clk_sys_i    => clk_sys_i,
+      clk_in_i     => clk_fb_i(0),
+      rst_n_i      => rst_n_i,
+      pps_p1_i     => pps_ext_a_i,
+      freq_o       => regs_out.f_ref_freq_i,
+      freq_valid_o => open);            -- fixme
+
+  U_Meas_EXT_Freq: gc_frequency_meter
+    generic map (
+      g_with_internal_timebase => false,
+      g_clk_sys_freq           => 1,
+      g_counter_bits           => 28)
+    port map (
+      clk_sys_i    => clk_sys_i,
+      clk_in_i     => clk_ext_i,
+      rst_n_i      => rst_n_i,
+      pps_p1_i     => pps_ext_a_i,
+      freq_o       => regs_out.f_ext_freq_i,
+      freq_valid_o => open);            -- fixme
+  
+
+  gen_ref_dmtds : for i in 0 to g_num_ref_inputs-1 generate
+
+    DMTD_REF : dmtd_with_deglitcher
+      generic map (
+        g_counter_bits      => g_tag_bits,
+        g_divide_input_by_2 => g_divide_input_by_2,
+        g_reverse	    => g_reverse_dmtds)
+      port map (
+        rst_n_dmtdclk_i => rst_dmtd_n_i,
+        rst_n_sysclk_i  => rst_n_i,
+
+        clk_dmtd_i    => clk_dmtd_i,
+        clk_dmtd_en_i => '1',
+
+        clk_sys_i => clk_sys_i,
+        clk_in_i  => clk_ref_i(i),
+
+        resync_done_o    => open,
+        resync_start_p_i => '0',
+        resync_p_a_i     => fb_resync_out(0),
+        resync_p_o       => open,
+
+        tag_o                => tags(i),
+        tag_stb_p1_o         => tags_p(i),
+        shift_en_i           => '0',
+        shift_dir_i          => '0',
+        deglitch_threshold_i => deglitch_thr_slv,
+        dbg_dmtdout_o        => open);
+
+
+  end generate gen_ref_dmtds;
+
+  gen_feedback_dmtds : for i in 0 to g_num_outputs-1 generate
+    
+    DMTD_FB : dmtd_with_deglitcher
+      generic map (
+        g_counter_bits      => g_tag_bits,
+        g_divide_input_by_2 => g_divide_input_by_2,
+        g_reverse           => g_reverse_dmtds)
+      port map (
+        rst_n_dmtdclk_i => rst_dmtd_n_i,
+        rst_n_sysclk_i  => rst_n_i,
+
+        clk_dmtd_i    => clk_dmtd_i,
+        clk_dmtd_en_i => '1',
+
+        clk_sys_i => clk_sys_i,
+        clk_in_i  => clk_fb_i(i),
+
+        resync_done_o    => open,
+        resync_start_p_i => '0',
+        resync_p_a_i     => fb_resync_out(0),
+        resync_p_o       => fb_resync_out(i),
+
+        tag_o        => tags(i+g_num_ref_inputs),
+        tag_stb_p1_o => tags_p(i+g_num_ref_inputs),
+        shift_en_i   => '0',
+        shift_dir_i  => '0',
+
+        deglitch_threshold_i => deglitch_thr_slv,
+        dbg_dmtdout_o        => open,
+				dbg_clk_d3_o         => open); --debug_o(4));
+
+
+  end generate gen_feedback_dmtds;
+
+  -- drive unused debug output
+  debug_o(4) <= '0';
+
+  gen_with_ext_clock_input : if(g_with_ext_clock_input) generate
+
+    debug_o(0) <= fb_resync_out(0);
+    debug_o(1) <= tags_p(g_num_ref_inputs + g_num_outputs);
+    debug_o(2) <= tags_p(g_num_ref_inputs);
+    
+    U_DMTD_EXT : dmtd_with_deglitcher
+      generic map (
+        g_counter_bits      => g_tag_bits,
+        g_divide_input_by_2 => g_divide_input_by_2,
+        g_reverse	    => g_reverse_dmtds)
+      port map (
+        rst_n_dmtdclk_i => rst_dmtd_n_i,
+        rst_n_sysclk_i  => rst_n_i,
+        clk_dmtd_i      => clk_dmtd_i,
+        clk_dmtd_en_i   => '1',
+
+        clk_sys_i => clk_sys_i,
+        clk_in_i  => clk_ext_mul_i,
+
+        resync_done_o    => open,
+        resync_start_p_i => '0',
+        resync_p_a_i     => fb_resync_out(0),
+        resync_p_o       => open,
+
+        tag_o        => tags(g_num_ref_inputs + g_num_outputs),
+        tag_stb_p1_o => tags_p(g_num_ref_inputs + g_num_outputs),
+        shift_en_i   => '0',
+        shift_dir_i  => '0',
+
+        deglitch_threshold_i => deglitch_thr_slv,
+        dbg_dmtdout_o        => debug_o(3),
+        dbg_clk_d3_o         => debug_o(5));
+
+    U_Aligner_EXT : spll_aligner
+      generic map (
+        g_counter_width  => 28,
+        g_ref_clock_rate => g_ref_clock_rate,
+        g_in_clock_rate  => g_ext_clock_rate,
+        g_sample_rate    => 100)
+      port map (
+        clk_sys_i      => clk_sys_i,
+        clk_in_i       => clk_ext_i,
+        clk_ref_i      => clk_fb_i(0),
+        rst_n_sys_i    => rst_n_i,
+        rst_n_ref_i    => rst_ref_n_i,
+        rst_n_ext_i    => rst_ext_n_i,
+        pps_ext_a_i    => pps_ext_a_i,
+        pps_csync_p1_i => pps_csync_p1_i,
+        sample_cref_o  => aligner_sample_cref(g_num_outputs),
+        sample_cin_o   => aligner_sample_cin(g_num_outputs),
+        sample_valid_o => aligner_sample_valid(g_num_outputs),
+        sample_ack_i   => aligner_sample_ack(g_num_outputs)
+        );
+
+    aligner_sample_valid(g_num_outputs-1 downto 0) <= (others => '0');
+
+    aligner_sample_cref(0 to g_num_outputs-1) <= (others => (others => '0'));
+    aligner_sample_cin(0 to g_num_outputs-1)  <= (others => (others => '0'));
+
+    regs_out.eccr_ext_supported_i   <= '1' when g_with_ext_clock_input else '0';
+    regs_out.eccr_ext_ref_locked_i  <= clk_ext_mul_locked_i;
+    regs_out.eccr_ext_ref_stopped_i <= clk_ext_stopped_i;
+    clk_ext_rst_o <= regs_in.eccr_ext_ref_pllrst_o;
+  end generate gen_with_ext_clock_input;
+
+  
+  gen_without_ext_clock_input : if(not g_with_ext_clock_input) generate
+    aligner_sample_valid <= (others => '0');
+    aligner_sample_cref  <= (others => (others => '0'));
+    aligner_sample_cin   <= (others => (others => '0'));
+
+    regs_out.eccr_ext_supported_i            <= '0';
+    regs_out.eccr_ext_ref_locked_i           <= '0';
+    regs_out.eccr_ext_ref_stopped_i          <= '0';
+    clk_ext_rst_o <= '0';
+    -- drive unused debug outputs
+    debug_o(0) <= '0';
+    debug_o(1) <= '0';
+    debug_o(2) <= '0';
+    debug_o(3) <= '0';
+    debug_o(5) <= '0';
+  end generate gen_without_ext_clock_input;
+
+  p_ack_aligner_samples: process(regs_in, aligner_sample_valid)
+  begin
+    regs_out.al_cr_valid_i <= (others => '0');
+    for i in 0 to g_num_outputs loop
+      aligner_sample_ack(i)     <= regs_in.al_cr_valid_o(i) and regs_in.al_cr_valid_load_o;
+      regs_out.al_cr_valid_i(i) <= aligner_sample_valid(i);
+    end loop;  -- i in 0 to g_num_outputs
+  end process;
+
+  p_mux_aligner_samples: process(clk_sys_i)
+    begin
+      if rising_edge(clk_sys_i) then
+        for i in 0 to g_num_outputs loop
+          if(aligner_sample_ack(i) = '1') then
+            regs_out.al_cref_i <= resize( aligner_sample_cref(i), 32 );
+            regs_out.al_cin_i <= resize( aligner_sample_cin(i), 32 );
+          end if;
+        end loop;
+      end if;
+    end process;
+
+  
+  U_WB_SLAVE : spll_wb_slave
+    generic map (
+      g_with_debug_fifo => f_pick(g_with_debug_fifo, 1, 0))
+    port map (
+      clk_sys_i  => clk_sys_i,
+      rst_n_i    => rst_n_i,
+      wb_adr_i   => wb_in.adr(5 downto 0),
+      wb_dat_i   => wb_in.dat,
+      wb_dat_o   => wb_out.dat,
+      wb_cyc_i   => wb_in.cyc,
+      wb_sel_i   => wb_in.sel,
+      wb_stb_i   => wb_in.stb,
+      wb_we_i    => wb_in.we,
+      wb_ack_o   => wb_out.ack,
+      wb_int_o   => wb_irq_out,
+      wb_stall_o => open,
+
+      regs_o => regs_in,
+      regs_i => regs_out,
+
+      irq_tag_i => irq_tag);
+
+    -- drive unused outputs
+    wb_out.err   <= '0';
+    wb_out.rty   <= '0';
+    wb_out.stall <= '0';
+    wb_out.int   <= '0';
+
+  p_ocer_rcer_regs : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        ocer_int <= (others => '0');
+        rcer_int <= (others => '0');
+      else
+        if(regs_in.ocer_load_o = '1') then
+          ocer_int <= regs_in.ocer_o(g_num_outputs -1 downto 0);
+        end if;
+
+        if(regs_in.rcer_load_o = '1') then
+          rcer_int <= regs_in.rcer_o(g_num_ref_inputs -1 downto 0);
+        end if;
+      end if;
+    end if;
+  end process;
+
+  regs_out.ocer_i(g_num_outputs-1 downto 0) <= ocer_int;
+  regs_out.ocer_i(7 downto g_num_outputs)   <= (others => '0');
+
+  regs_out.rcer_i(g_num_ref_inputs-1 downto 0) <= rcer_int;
+  regs_out.rcer_i(31 downto g_num_ref_inputs)  <= (others => '0');
+
+  p_latch_tags : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if(rst_n_i = '0') then
+        tags_req   <= (others => '0');
+        tags_grant <= (others => '0');
+      else
+        f_rr_arbitrate(tags_req, tags_grant, tags_grant);
+
+        for i in 0 to g_num_ref_inputs-1 loop
+          if(tags_p(i) = '1') then
+            tags_req(i) <= rcer_int(i);
+          elsif(tags_grant(i) = '1') then
+            tags_req(i) <= '0';
+          end if;
+        end loop;  -- i
+
+        for i in 0 to g_num_outputs-1 loop
+          if(tags_p(i + g_num_ref_inputs) = '1') then
+            tags_req(i + g_num_ref_inputs) <= ocer_int(i);
+          elsif(tags_grant(i + g_num_ref_inputs) = '1') then
+            tags_req(i + g_num_ref_inputs) <= '0';
+          end if;
+        end loop;  -- i
+
+        if(g_with_ext_clock_input and tags_p(f_num_total_channels-1) = '1') then
+          tags_req(f_num_total_channels-1) <= regs_in.eccr_ext_en_o;
+        elsif(g_with_ext_clock_input and tags_grant(f_num_total_channels-1) = '1') then
+          tags_req(f_num_total_channels-1) <= '0';
+        end if;
+        
+      end if;
+    end if;
+  end process;
+
+  tags_grant_p <= tags_req and tags_grant;
+
+  p_mux_tags : process(clk_sys_i)
+    variable muxed  : std_logic_vector(g_tag_bits-1 downto 0);
+    variable src_id : std_logic_vector(5 downto 0);
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        tag_muxed     <= (others => '0');
+        tag_src_pre   <= (others => '0');
+        tag_src       <= (others => '0');
+        tag_valid_pre <= '0';
+        tag_valid     <= '0';
+      else
+        
+        for i in 0 to f_num_total_channels-1 loop
+          if(tags_grant_p(i) = '1') then
+            tags_masked(i) <= tags(i);
+          else
+            tags_masked(i) <= (others => '0');
+          end if;
+        end loop;  -- i
+
+        if(unsigned(tags_grant_p) /= 0) then
+          tag_valid_pre <= '1';
+        else
+          tag_valid_pre <= '0';
+        end if;
+
+        tag_valid <= tag_valid_pre;
+
+        tag_src_pre <= f_onehot_decode(tags_grant_p, tag_src_pre'length);
+        tag_src     <= tag_src_pre;
+
+        muxed := (others => '0');
+
+        for i in 0 to f_num_total_channels-1 loop
+          muxed := muxed or tags_masked(i);
+        end loop;
+
+        tag_muxed <= muxed;
+        
+      end if;
+    end if;
+  end process;
+
+  regs_out.trr_wr_req_i  <= tag_valid and not regs_in.trr_wr_full_o;
+  regs_out.trr_chan_id_i <= '0'&tag_src;
+
+  regs_out.trr_value_i(g_tag_bits-1 downto 0) <= tag_muxed;
+  regs_out.trr_value_i(23 downto g_tag_bits)  <= (others => '0');
+  
+  regs_out.occr_out_en_i(g_num_outputs-1 downto 0) <= out_enable_i;
+  regs_out.occr_out_en_i(7 downto g_num_outputs)   <= (others => '0');
+
+  out_locked_o <= regs_in.occr_out_lock_o(g_num_outputs-1 downto 0);
+
+  irq_tag <= not regs_in.trr_wr_empty_o;
+
+  deglitch_thr_slv <= regs_in.deglitch_thr_o;
+
+
+
+  -----------------------------------------------------------------------------
+  -- Debugging FIFO
+  -----------------------------------------------------------------------------
+
+  gen_with_debug_fifo : if(g_with_debug_fifo = true) generate
+    
+    dbg_fifo_almostfull <= '1' when unsigned(regs_in.dfr_host_wr_usedw_o) > 8180 else '0';
+
+    p_request_counter : process(clk_sys_i)
+    begin
+      if rising_edge(clk_sys_i) then
+        if rst_n_i = '0' then
+          dbg_seq_id <= (others => '0');
+        else
+          if(regs_in.dfr_spll_eos_o = '1' and regs_in.dfr_spll_eos_wr_o = '1') then
+            dbg_seq_id <= dbg_seq_id + 1;
+          end if;
+        end if;
+      end if;
+    end process;
+
+    p_fifo_permit_write : process(clk_sys_i)
+    begin
+      if rising_edge(clk_sys_i) then
+        if rst_n_i = '0' then
+          dbg_fifo_permit_write <= '1';
+        else
+          if(dbg_fifo_almostfull = '0') then
+            dbg_fifo_permit_write <= '1';
+          elsif(regs_in.dfr_spll_eos_o = '1' and regs_in.dfr_spll_eos_wr_o = '1') then
+            dbg_fifo_permit_write <= '0';
+          end if;
+        end if;
+      end if;
+    end process;
+
+    p_coalesce_fifo_irq : process(clk_sys_i)
+    begin
+      if rising_edge(clk_sys_i) then
+        if rst_n_i = '0' then
+          dbg_fifo_irq <= '0';
+        else
+          if(unsigned(regs_in.dfr_host_wr_usedw_o) = 0) then
+            dbg_fifo_irq <= '0';
+          elsif(unsigned(regs_in.dfr_host_wr_usedw_o) = c_DBG_FIFO_COALESCE) then
+            dbg_fifo_irq <= '1';
+          end if;
+        end if;
+      end if;
+    end process;
+
+    regs_out.dfr_host_wr_req_i <= regs_in.dfr_spll_value_wr_o and dbg_fifo_permit_write;
+    regs_out.dfr_host_value_i  <= regs_in.dfr_spll_eos_o & regs_in.dfr_spll_value_o;
+    regs_out.dfr_host_seq_id_i <= std_logic_vector(dbg_seq_id);
+
+  end generate gen_with_debug_fifo;
+
+  gen_without_debug_fifo : if(g_with_debug_fifo = false) generate
+    dbg_fifo_irq               <= '0';
+    regs_out.dfr_host_wr_req_i <= '0';
+    regs_out.dfr_host_value_i  <= (others => '0');
+    regs_out.dfr_host_seq_id_i <= (others => '0');
+  end generate gen_without_debug_fifo;
+
+  dbg_fifo_irq_o <= dbg_fifo_irq;
+
+  -----------------------------------------------------------------------------
+  -- CSR N_OUT/N_REF fields
+  -----------------------------------------------------------------------------
+
+  regs_out.csr_n_ref_i <= std_logic_vector(to_unsigned(g_num_ref_inputs, regs_out.csr_n_ref_i'length));
+  regs_out.csr_n_out_i <= std_logic_vector(to_unsigned(g_num_outputs, regs_out.csr_n_out_i'length));
+
+  dac_dmtd_load_o <= regs_in.dac_hpll_wr_o;
+  dac_dmtd_data_o <= regs_in.dac_hpll_o;
+
+  dac_out_data_o <= regs_in.dac_main_value_o;
+  dac_out_sel_o  <= regs_in.dac_main_dac_sel_o;
+  dac_out_load_o <= regs_in.dac_main_value_wr_o;
+
+  wb_irq_o <= wb_irq_out;
+
+  regs_out.al_cr_required_i    <= (others => '0');
+  regs_out.csr_dbg_supported_i <= '0';
+  regs_out.f_dmtd_valid_i      <= '0';
+  regs_out.f_ref_valid_i       <= '0';
+  regs_out.f_ext_valid_i       <= '0';
+  regs_out.trr_disc_i          <= '0';
+
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_softpll_ng/xwr_softpll_ng.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_softpll_ng/xwr_softpll_ng.vhd
new file mode 100644
index 000000000..ea3b6ab63
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_softpll_ng/xwr_softpll_ng.vhd
@@ -0,0 +1,244 @@
+-------------------------------------------------------------------------------
+-- Title      : White Rabbit Softcore PLL (new generation) - SoftPLL-ng
+-- Project    : White Rabbit
+-------------------------------------------------------------------------------
+-- File       : xwr_softpll_ng.vhd
+-- Author     : Tomasz Włostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2011-01-29
+-- Last update: 2017-02-20
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: 
+--
+-- Struct'ized version of wr_softpll_ng.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012-2017 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.wishbone_pkg.all;
+use work.softpll_pkg.all;
+
+entity xwr_softpll_ng is
+  generic(
+-- Number of bits in phase tags produced by DDMTDs.
+-- Must be large enough to cover at least a hundred of DDMTD periods to ensure
+-- correct operation of the SoftPLL software servo algorithm - that
+-- means, for a typical DMTD frequency offset N=16384, there number of tag bits
+-- should be log2(N) + 7 == 21. Note: the value must match the TAG_BITS constant
+-- in spll_defs.h file!
+    g_tag_bits : integer;
+
+-- These two are obvious:
+    g_num_ref_inputs : integer := 1;
+    g_num_outputs    : integer := 1;
+
+-- When true, an additional FIFO is instantiated, providing a realtime record
+-- of user-selectable SoftPLL parameters (e.g. tag values, phase error, DAC drive).
+-- These values can be read by "spll_dbg_proxy" daemon for further analysis.
+    g_with_debug_fifo : boolean := false;
+
+-- When true, an additional accumulating bang-bang phase detector is instantiated
+-- for wideband locking of the local oscillator to an external stable reference
+-- (e.g. GPSDO/Cesium 10 MHz)
+    g_with_ext_clock_input : boolean := false;
+
+-- When true, DDMTD inputs are reverse (so that the DDMTD offset clocks is
+-- being sampled by the measured clock). This is functionally equivalent to
+-- "direct" operation, but may improve FPGA timing/routability.
+    g_reverse_dmtds : boolean := true;
+
+-- Divides the DDMTD clock inputs by 2, removing the "CLOCK_DEDICATED_ROUTE"
+-- errors under ISE tools, at the cost of bandwidth reduction. Use with care.
+    g_divide_input_by_2 : boolean := false;
+
+    g_ref_clock_rate : integer := 125000000;
+    g_ext_clock_rate : integer := 10000000;
+
+    g_interface_mode      : t_wishbone_interface_mode      := PIPELINED;
+    g_address_granularity : t_wishbone_address_granularity := BYTE
+    );
+
+  port(
+    clk_sys_i    : in std_logic;
+    rst_sys_n_i  : in std_logic;
+    rst_ref_n_i  : in std_logic;
+    rst_ext_n_i  : in std_logic;
+    rst_dmtd_n_i : in std_logic;
+
+-- Reference inputs (i.e. the RX clocks recovered by the PHYs)
+    clk_ref_i  : in std_logic_vector(g_num_ref_inputs-1 downto 0);
+-- Feedback clocks (i.e. the outputs of the main or aux oscillator)
+    clk_fb_i   : in std_logic_vector(g_num_outputs-1 downto 0);
+-- DMTD Offset clock
+    clk_dmtd_i : in std_logic;
+
+-- External reference clock (e.g. 10 MHz from Cesium/GPSDO). Used only if
+-- g_with_ext_clock_input == true
+    clk_ext_i : in std_logic;
+
+-- External clock, multiplied to 125 MHz using the FPGA's PLL
+    clk_ext_mul_i : in std_logic;
+    clk_ext_mul_locked_i : in std_logic := '1';
+    clk_ext_stopped_i    : in std_logic := '0';
+    clk_ext_rst_o        : out std_logic;
+
+-- External clock sync/alignment singnal. SoftPLL will clk_ext_i/clk_fb_i(0)
+-- to match the edges immediately following the rising edge in sync_p_i.
+    pps_csync_p1_i : in std_logic;
+
+    pps_ext_a_i : in std_logic;
+
+-- DMTD oscillator drive
+    dac_dmtd_data_o : out std_logic_vector(15 downto 0);
+    dac_dmtd_load_o : out std_logic;
+
+-- Output channel DAC value
+    dac_out_data_o : out std_logic_vector(15 downto 0);
+-- Output channel select (0 = channel 0, etc. )
+    dac_out_sel_o  : out std_logic_vector(3 downto 0);
+    dac_out_load_o : out std_logic;
+
+    out_enable_i : in  std_logic_vector(g_num_outputs-1 downto 0);
+    out_locked_o : out std_logic_vector(g_num_outputs-1 downto 0);
+
+    slave_i : in  t_wishbone_slave_in;
+    slave_o : out t_wishbone_slave_out;
+
+    debug_o        : out std_logic_vector(5 downto 0);
+    dbg_fifo_irq_o : out std_logic
+    );
+
+end xwr_softpll_ng;
+
+architecture wrapper of xwr_softpll_ng is
+  component wr_softpll_ng
+    generic (
+      g_tag_bits             : integer;
+      g_num_ref_inputs       : integer;
+      g_num_outputs          : integer;
+      g_with_debug_fifo      : boolean;
+      g_with_ext_clock_input : boolean;
+      g_reverse_dmtds        : boolean;
+      g_divide_input_by_2    : boolean;
+      g_ref_clock_rate       : integer;
+      g_ext_clock_rate       : integer;
+      g_interface_mode       : t_wishbone_interface_mode;
+      g_address_granularity  : t_wishbone_address_granularity);
+    port (
+      clk_sys_i       : in  std_logic;
+      rst_sys_n_i     : in std_logic;
+      rst_ref_n_i     : in std_logic;
+      rst_ext_n_i     : in std_logic;
+      rst_dmtd_n_i    : in std_logic;
+      clk_ref_i       : in  std_logic_vector(g_num_ref_inputs-1 downto 0);
+      clk_fb_i        : in  std_logic_vector(g_num_outputs-1 downto 0);
+      clk_dmtd_i      : in  std_logic;
+      clk_ext_i       : in  std_logic;
+      clk_ext_mul_i   : in  std_logic;
+      clk_ext_mul_locked_i : in  std_logic;
+      clk_ext_stopped_i    : in  std_logic;
+      clk_ext_rst_o        : out std_logic;
+      pps_csync_p1_i  : in  std_logic;
+      pps_ext_a_i     : in  std_logic;
+      dac_dmtd_data_o : out std_logic_vector(15 downto 0);
+      dac_dmtd_load_o : out std_logic;
+      dac_out_data_o  : out std_logic_vector(15 downto 0);
+      dac_out_sel_o   : out std_logic_vector(3 downto 0);
+      dac_out_load_o  : out std_logic;
+      out_enable_i    : in  std_logic_vector(g_num_outputs-1 downto 0);
+      out_locked_o    : out std_logic_vector(g_num_outputs-1 downto 0);
+
+      wb_adr_i   : in  std_logic_vector(c_wishbone_address_width-1 downto 0);
+      wb_dat_i   : in  std_logic_vector(c_wishbone_data_width-1 downto 0);
+      wb_dat_o   : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+      wb_cyc_i   : in  std_logic;
+      wb_sel_i   : in  std_logic_vector(c_wishbone_data_width/8-1 downto 0);
+      wb_stb_i        : in  std_logic;
+      wb_we_i         : in  std_logic;
+      wb_ack_o        : out std_logic;
+      wb_stall_o      : out std_logic;
+      wb_irq_o        : out std_logic;
+      debug_o         : out std_logic_vector(5 downto 0);
+      dbg_fifo_irq_o  : out std_logic);
+  end component;
+  
+begin  -- behavioral
+
+  U_Wrapped_Softpll : wr_softpll_ng
+    generic map (
+      g_tag_bits             => g_tag_bits,
+      g_interface_mode       => g_interface_mode,
+      g_address_granularity  => g_address_granularity,
+      g_num_ref_inputs       => g_num_ref_inputs,
+      g_num_outputs          => g_num_outputs,
+      g_with_debug_fifo      => g_with_debug_fifo,
+      g_with_ext_clock_input => g_with_ext_clock_input,
+      g_reverse_dmtds        => g_reverse_dmtds,
+      g_divide_input_by_2    => g_divide_input_by_2,
+      g_ref_clock_rate  => g_ref_clock_rate,
+      g_ext_clock_rate  => g_ext_clock_rate
+      )
+    port map (
+      clk_sys_i       => clk_sys_i,
+      rst_sys_n_i     => rst_sys_n_i,
+      rst_ref_n_i     => rst_ref_n_i,
+      rst_ext_n_i     => rst_ext_n_i,
+      rst_dmtd_n_i    => rst_dmtd_n_i,
+      clk_ref_i       => clk_ref_i,
+      clk_fb_i        => clk_fb_i,
+      clk_dmtd_i      => clk_dmtd_i,
+      clk_ext_i       => clk_ext_i,
+      clk_ext_mul_i   => clk_ext_mul_i,
+      clk_ext_mul_locked_i => clk_ext_mul_locked_i,
+      clk_ext_stopped_i => clk_ext_stopped_i,
+      clk_ext_rst_o     => clk_ext_rst_o,
+      pps_csync_p1_i  => pps_csync_p1_i,
+      pps_ext_a_i     => pps_ext_a_i,
+      dac_dmtd_data_o => dac_dmtd_data_o,
+      dac_dmtd_load_o => dac_dmtd_load_o,
+      dac_out_data_o  => dac_out_data_o,
+      dac_out_sel_o   => dac_out_sel_o,
+      dac_out_load_o  => dac_out_load_o,
+      out_enable_i    => out_enable_i,
+      out_locked_o    => out_locked_o,
+      wb_adr_i        => slave_i.adr,
+      wb_dat_i        => slave_i.dat,
+      wb_dat_o        => slave_o.dat,
+      wb_cyc_i        => slave_i.cyc,
+      wb_sel_i        => slave_i.sel,
+      wb_stb_i        => slave_i.stb,
+      wb_we_i         => slave_i.we,
+      wb_ack_o        => slave_o.ack,
+      wb_stall_o      => slave_o.stall,
+      wb_irq_o        => slave_o.int,
+      debug_o         => debug_o,
+      dbg_fifo_irq_o  => dbg_fifo_irq_o);
+
+  slave_o.err <= '0';
+  slave_o.rty <= '0';
+  
+end wrapper;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/dropping_buffer.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/dropping_buffer.vhd
new file mode 100644
index 000000000..364ba970f
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/dropping_buffer.vhd
@@ -0,0 +1,142 @@
+-------------------------------------------------------------------------------
+-- Title      : Dropping buffer
+-- Project    : WR Stramers
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/WR_Streamers
+-------------------------------------------------------------------------------
+-- File       : dropping_buffer.vhd
+-- Author     : Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL
+-- Created    : 2012-11-02
+-------------------------------------------------------------------------------
+-- Description:
+--
+-- A FIFO that can be cleared fast
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012-2017 CERN/BE-CO-HT
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.genram_pkg.all; -- needed for f_log2_size()
+
+entity dropping_buffer is
+  generic (
+    g_size       : integer;
+    g_data_width : integer);
+
+  port
+    (
+      clk_i   : in std_logic;
+      rst_n_i : in std_logic;
+
+      d_i        : in  std_logic_vector(g_data_width-1 downto 0);
+      d_req_o    : out std_logic;
+      d_drop_i   : in  std_logic;
+      d_accept_i : in  std_logic;
+      d_valid_i  : in  std_logic;
+
+      d_o       : out std_logic_vector(g_data_width-1 downto 0);
+      d_valid_o : out std_logic;
+      d_req_i   : in  std_logic);
+
+
+end dropping_buffer;
+
+architecture behavioral of dropping_buffer is
+
+  type    t_mem_array is array(0 to g_size-1) of std_logic_vector(g_data_width-1 downto 0);
+  subtype t_counter is unsigned(f_log2_size(g_size)-1 downto 0);
+
+  signal wr_ptr, rd_ptr, boundary : t_counter := (others => '0');
+  signal full, empty_comb         : std_logic;
+  signal empty_reg                : std_logic := '0';
+  signal mem                      : t_mem_array;
+  
+begin  -- behavioral
+
+  p_counters : process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        wr_ptr   <= (others => '0');
+        rd_ptr   <= (others => '0');
+        boundary <= (others => '0');
+      else
+        if(d_accept_i = '1') then
+          boundary <= wr_ptr;
+        end if;
+
+        if(d_drop_i = '1') then
+          wr_ptr <= boundary;
+        elsif(d_valid_i = '1' and full = '0') then
+          wr_ptr <= wr_ptr + 1;
+        end if;
+
+        if (d_req_i = '1' and empty_reg = '0' and empty_comb = '0') then
+          rd_ptr <= rd_ptr + 1;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  empty_comb <= '1' when (boundary = rd_ptr)   else '0';
+  full       <= '1' when (wr_ptr + 1 = rd_ptr) else '0';
+
+  d_req_o <= not full;
+
+  p_empty_reg : process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        empty_reg <= '1';
+      else
+        empty_reg <= empty_comb;
+      end if;
+    end if;
+  end process;
+
+
+  p_mem_read : process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if(d_req_i = '1' and empty_reg = '0' and empty_comb = '0') then
+        d_o       <= mem(to_integer(rd_ptr));
+        d_valid_o <= '1';
+      else
+        d_o       <= (others => '0');
+        d_valid_o <= '0';
+      end if;
+    end if;
+  end process;
+
+  p_mem_write : process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if(d_valid_i = '1') then
+        mem(to_integer(wr_ptr)) <= d_i;
+      end if;
+    end if;
+  end process;
+  
+end behavioral;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/escape_detector.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/escape_detector.vhd
new file mode 100644
index 000000000..bdf112f7a
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/escape_detector.vhd
@@ -0,0 +1,106 @@
+-------------------------------------------------------------------------------
+-- Title      : Escape detecotr
+-- Project    : WR Streamers
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/WR_Streamers
+-------------------------------------------------------------------------------
+-- File       : escape_detector.vhd
+-- Author     : Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL
+-- Created    : 2012-10-01
+-------------------------------------------------------------------------------
+-- Description:
+--
+-- It detects the "escape code" (e.g.0xCAFE) and removes it from the data stream.
+-- See escape_inserter for details
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012-2017 CERN/BE-CO-HT
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity escape_detector is
+  generic(
+    g_data_width  : integer;
+    g_escape_code : std_logic_vector
+    );
+  port(
+    clk_i   : in std_logic;
+    rst_n_i : in std_logic;
+
+
+    d_i               : in  std_logic_vector(g_data_width-1 downto 0);
+    d_detect_enable_i : in  std_logic;
+    d_valid_i         : in  std_logic;
+    d_req_o           : out std_logic;
+
+    d_o        : out std_logic_vector(g_data_width-1 downto 0);
+    d_escape_o : out std_logic;
+    d_valid_o  : out std_logic;
+    d_req_i    : in  std_logic
+    );
+
+end escape_detector;
+
+architecture behavioral of escape_detector is
+
+  type t_state is (IDLE, CHECK_ESCAPE);
+
+  signal state          : t_state;
+  signal is_escape_code : std_logic;
+  
+begin  -- behavioral
+
+  d_req_o <= d_req_i;
+
+  is_escape_code <= '1' when (d_detect_enable_i = '1' and state = IDLE and d_valid_i = '1' and d_i = g_escape_code) else '0';
+
+  d_o <= g_escape_code when (state = CHECK_ESCAPE and d_i = x"0000") else d_i;
+
+  d_valid_o  <= d_valid_i and not is_escape_code;
+  d_escape_o <= '1' when (state = CHECK_ESCAPE and d_i /= x"0000") else '0';
+
+  p_fsm : process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' or d_detect_enable_i = '0' then
+        state <= IDLE;
+      else
+        case state is
+          when IDLE =>
+            if(d_i = g_escape_code and d_valid_i = '1') then
+              state <= CHECK_ESCAPE;
+
+            end if;
+
+          when CHECK_ESCAPE =>
+            if(d_valid_i = '1') then
+              state <= IDLE;
+            end if;
+        end case;
+      end if;
+    end if;
+  end process;
+
+end behavioral;
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/escape_inserter.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/escape_inserter.vhd
new file mode 100644
index 000000000..e289a060d
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/escape_inserter.vhd
@@ -0,0 +1,141 @@
+-------------------------------------------------------------------------------
+-- Title      : Escape insertion unit
+-- Project    : WR Streamers
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/WR_Streamers
+-------------------------------------------------------------------------------
+-- File       : gc_escape_inserter.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2012-10-01
+-- Platform   : FPGA-generic
+-- Standard   : VHDL '93
+------------------------------------------------------------------------------
+-- Description: Unit for inserting escaped codes in a continuous data stream.
+-- Allows for insertion of easily distinguishable control codes, such as start-
+-- or end-of-frame markers. Given an input tuple (E[d_escape_i], D[d_i]), the
+-- output (d_o) is:
+-- - D when E == 0 and D != g_escape_code
+-- - g_escape_code followed by 0 when E == 0 and D == g_escape_code
+-- - g_escape_code followed by D when E == 1.
+-- Note: When E == 1, D must not be 0.
+------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity gc_escape_inserter is
+  generic(
+    -- data path width
+    g_data_width  : integer;
+    -- unique escape character (of g_data_width bits), must not be 0.
+    g_escape_code : std_logic_vector
+    );
+  port(
+    clk_i   : in std_logic;
+    rst_n_i : in std_logic;
+
+    -- data input (unescaped)
+    d_i               : in  std_logic_vector(g_data_width-1 downto 0);
+
+    -- when 1, escape insertion logic is enabled (i.e. if d_i == g_escape_code,
+    -- it's translated to g_escape_code followed by 0 instead of just being passed
+    -- through
+    d_insert_enable_i : in  std_logic;
+
+    -- when 1, d_i is treated as a escaped character
+    d_escape_i        : in  std_logic;
+
+    -- when 1, d_i and d_escape_i contain valid character
+    d_valid_i         : in  std_logic;
+
+    -- when 1, module can accept data in the following clock cycle.
+    d_req_o           : out std_logic;
+
+    -- data output
+    d_o       : out std_logic_vector (g_data_width-1 downto 0);
+
+    -- when 1, d_o contains a valid character
+    d_valid_o : out std_logic;
+
+    -- when 1, d_o/d_valid_o may output a character in the next clock cycle.
+    d_req_i   : in  std_logic
+    );
+
+end gc_escape_inserter;
+
+architecture behavioral of gc_escape_inserter is
+
+  type t_state is (IDLE, INSERT_ESCAPE);
+
+  signal d_prev     : std_logic_vector(g_data_width-1 downto 0);
+  signal d_req_prev : std_logic;
+  signal state      : t_state;
+  signal match_esc_code : std_logic;
+  
+begin  -- behavioral
+
+  match_esc_code <= '1' when d_i = g_escape_code else '0';
+
+  -- stop the traffic if we need to insert an escaped sequence. This
+  -- can happen when
+  -- - the input character is an escape code (d_escape_i = '1')
+  -- - the input character is not to be escaped, but it's equal to g_escape_code
+  d_req_o <= d_req_i and not (d_valid_i and (d_escape_i or match_esc_code));
+
+  d_o <= d_prev when (state = INSERT_ESCAPE) else
+         d_i when d_escape_i = '0' else
+         g_escape_code;
+  
+  d_valid_o <= d_valid_i when (state = IDLE) else
+               d_req_prev;
+
+  p_fsm : process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' or d_insert_enable_i = '0' then
+        state      <= IDLE;
+        d_req_prev <= '0';
+      else
+        d_req_prev <= d_req_i;
+        case state is
+          when IDLE =>
+            -- case 1: escape the escape character sent as normal character
+            if(d_i = g_escape_code and d_valid_i = '1' and d_escape_i = '0') then
+              state  <= INSERT_ESCAPE;
+              d_prev <= x"0000";
+            -- case 2: send an escaped character
+            elsif(d_escape_i = '1' and d_valid_i = '1') then
+              state  <= INSERT_ESCAPE;
+              d_prev <= d_i;
+            end if;
+            
+          when INSERT_ESCAPE =>
+            if(d_req_prev = '1') then
+              state <= IDLE;
+            end if;
+        end case;
+      end if;
+    end if;
+  end process;
+
+end behavioral;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/streamers_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/streamers_pkg.vhd
new file mode 100644
index 000000000..b4fa5a289
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/streamers_pkg.vhd
@@ -0,0 +1,332 @@
+-------------------------------------------------------------------------------
+-- Title      : Package for WR Steamers
+-- Project    : WR Streamers
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/WR_Streamers
+-------------------------------------------------------------------------------
+-- File       : streamers_pkg.vhd
+-- Author     : Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL
+-- Created    : 2012-10-01
+-------------------------------------------------------------------------------
+-- Description:
+--
+-- Package with declaration of streamer components, types and constants.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012-2017 CERN/BE-CO-HT
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.wr_fabric_pkg.all;
+use work.wrcore_pkg.all;
+use work.wishbone_pkg.all;  -- needed for t_wishbone_slave_in, etc
+
+package streamers_pkg is
+  type t_streamers_op_mode is (RX_ONLY, TX_ONLY, TX_AND_RX);
+  -----------------------------------------------------------------------------------------
+  -- Transmission parameters (tx)
+  -----------------------------------------------------------------------------------------
+  type t_tx_streamer_params is record
+    -- Width of data words on tx_data_i, must be multiple of 16 bits.
+    data_width            : integer;
+
+    -- Size of Tx buffer, in data words.
+    buffer_size           : integer;
+
+    -- Minimum number of data words in the TX buffer that will trigger transmission of an
+    -- Ethernet frame. It cannot be breater than g_tx_buffer_size; it is recommended that
+    -- g_tx_buffer_size = 2 * g_tx_threshold.
+    -- Note that in order for a frame to be transmitted, the buffer must conatain at
+    -- least one complete block.ransmitted, the buffer must conatain at
+    -- least one complete block.
+    threshold             : integer;
+
+    -- Maximum number of data words in a single Ethernet frame. It also defines
+    -- the maximum block size (since blocks can't be currently split across
+    -- multiple frames). It cannot be greater than g_tx_buffer_size
+    max_words_per_frame   : integer;
+
+    -- Transmission timeout (in clk_sys_i cycles), after which the contents
+    -- of TX buffer are sent regardless of the amount of data that is currently
+    -- stored in the buffer, so that data in the buffer does not get stuck.
+    timeout               : integer;
+
+    -- DO NOT USE unless you know what you are doing
+    -- legacy: the streamers initially used in Btrain did not check/insert the escape
+    -- code. This is justified if only one block of a known number of words is sent/expected
+    escape_code_disable   : boolean;
+  end record;
+
+  -----------------------------------------------------------------------------------------
+  -- Reception parameters (rx)
+  -----------------------------------------------------------------------------------------
+  type t_rx_streamer_params is record
+    -- Width of the data words, must be multiple of 16 bits. This value set to this generic
+    -- on the receviving device must be the same as the value of g_tx_data_width set on the
+    -- transmitting node. The g_rx_data_width and g_tx_data_width can be set to different
+    -- values in the same device (i.e. instantiation of xwr_transmission entity). It is the
+    -- responsibility of a network designer to make sure these parameters are properly set 
+    -- in the network.
+    data_width            : integer;
+
+    -- Size of RX buffer, in data words.
+    buffer_size           : integer;
+
+    -- DO NOT USE unless you know what you are doing
+    -- legacy: the streamers that were initially used in Btrain did not check/insert 
+    -- the escape code. This is justified if only one block of a known number of words is 
+    -- sent/expected.
+    escape_code_disable   : boolean;
+
+    -- DO NOT USE unless you know what you are doing
+    -- legacy: the streamers that were initially used in Btrain accepted only a fixed
+    -- number of words, regardless of the frame content. If this generic is set to number
+    -- other than zero, only a fixed number of words is accepted. 
+    -- In combination with the g_escape_code_disable generic set to TRUE, the behaviour of
+    -- the "Btrain streamers" can be recreated.
+    expected_words_number : integer;
+  end record;
+
+  constant c_tx_streamer_params_defaut: t_tx_streamer_params :=(
+      data_width            => 32,
+      buffer_size           => 256,
+      threshold             => 128,
+      max_words_per_frame   => 256,
+      timeout               => 1024,
+      escape_code_disable   => FALSE);
+
+  constant c_rx_streamer_params_defaut: t_rx_streamer_params :=(
+      data_width            => 32,
+      buffer_size           => 256,
+      escape_code_disable   => FALSE,
+      expected_words_number => 0);
+
+  type t_rx_streamer_cfg is record
+    -- Local MAC address. Leave at 0x0...0 when using with the WR MAC/Core, it will
+    -- insert its own source MAC.
+    mac_local              : std_logic_vector(47 downto 0);
+    -- Remote MAC address, i.e. MAC of the device from which the data should be accpated
+    mac_remote             : std_logic_vector(47 downto 0);
+    -- Ethertype of our frames. Default value is accepted by standard
+    -- configuration of the WR PTP Core
+    ethertype              : std_logic_vector(15 downto 0);
+    -- 1: accept all broadcast packets
+    -- 0: accept only unicasts
+    accept_broadcasts      : std_logic;
+    -- filtering of streamer frames on reception by source MAC address
+    -- 0: accept frames from any source
+    -- 1: accept frames only from the source MAC address defined in cfg_mac_remote_i
+    filter_remote          : std_logic;
+    -- value in cycles of fixed-latency enforced on data
+    fixed_latency          : std_logic_vector(27 downto 0);
+  end record;
+
+  type t_tx_streamer_cfg is record
+    -- Local MAC address. Leave at 0x0...0 when using with the WR MAC/Core, it will
+    -- insert its own source MAC.
+    mac_local              : std_logic_vector(47 downto 0);
+    -- Destination MAC address, i.e. MAC of a device to which data is streamed.
+    mac_target             : std_logic_vector(47 downto 0);
+    -- Ethertype of our frames. Default value is accepted by standard
+    -- configuration of the WR PTP Core
+    ethertype              : std_logic_vector(15 downto 0);
+    -- enable tagging with VLAN tags
+    qtag_ena               : std_logic;
+    ---VLAN used to tag
+    qtag_vid               : std_logic_vector(11 downto 0);
+    -- priority used to tag
+    qtag_prio              : std_logic_vector(2  downto 0);
+  end record;
+
+  constant c_rx_streamer_cfg_default: t_rx_streamer_cfg :=(
+    mac_local              => x"000000000000",
+    mac_remote             => x"000000000000",
+    ethertype              => x"dbff",
+    accept_broadcasts      => '1',
+    filter_remote          => '0',
+    fixed_latency          => x"0000000");
+
+  constant c_tx_streamer_cfg_default: t_tx_streamer_cfg :=(
+    mac_local              => x"000000000000",
+    mac_target             => x"ffffffffffff",
+    ethertype              => x"dbff",
+    qtag_ena               => '0',
+    qtag_vid               => x"000",
+    qtag_prio              => "000");
+
+  component xtx_streamer
+    generic (
+      g_data_width             : integer := 32;
+      g_tx_buffer_size         : integer := 256;
+      g_tx_threshold           : integer := 128;
+      g_tx_max_words_per_frame : integer := 256;
+      g_tx_timeout             : integer := 1024;
+      g_escape_code_disable    : boolean := FALSE;
+      g_simulation             : integer := 0;
+      g_sim_startup_cnt        : integer := 6250);--100us
+    port (
+      clk_sys_i        : in  std_logic;
+      rst_n_i          : in  std_logic;
+      src_i            : in  t_wrf_source_in;
+      src_o            : out t_wrf_source_out;
+      clk_ref_i        : in  std_logic                     := '0';
+      tm_time_valid_i  : in  std_logic                     := '0';
+      tm_tai_i         : in  std_logic_vector(39 downto 0) := x"0000000000";
+      tm_cycles_i      : in  std_logic_vector(27 downto 0) := x"0000000";
+      link_ok_i        : in  std_logic                     := '1';
+      tx_data_i        : in  std_logic_vector(g_data_width-1 downto 0);
+      tx_valid_i       : in  std_logic;
+      tx_dreq_o        : out std_logic;
+      tx_last_p1_i     : in  std_logic                     := '1';
+      tx_flush_p1_i    : in  std_logic                     := '0';
+      tx_reset_seq_i   : in  std_logic                     := '0';
+      tx_frame_p1_o    : out std_logic;
+      tx_streamer_cfg_i: in t_tx_streamer_cfg := c_tx_streamer_cfg_default);
+  end component;
+  
+  component xrx_streamer
+    generic (
+      g_data_width        : integer := 32;
+      g_buffer_size       : integer := 256;
+      g_escape_code_disable : boolean := FALSE;
+      g_expected_words_number : integer := 0);
+    port (
+      clk_sys_i               : in  std_logic;
+      rst_n_i                 : in  std_logic;
+      snk_i                   : in  t_wrf_sink_in;
+      snk_o                   : out t_wrf_sink_out;
+      clk_ref_i               : in  std_logic                     := '0';
+      tm_time_valid_i         : in  std_logic                     := '0';
+      tm_tai_i                : in  std_logic_vector(39 downto 0) := x"0000000000";
+      tm_cycles_i             : in  std_logic_vector(27 downto 0) := x"0000000";
+      rx_first_p1_o           : out std_logic;
+      rx_last_p1_o            : out std_logic;
+      rx_data_o               : out std_logic_vector(g_data_width-1 downto 0);
+      rx_valid_o              : out std_logic;
+      rx_dreq_i               : in  std_logic;
+      rx_lost_p1_o            : out std_logic := '0';
+      rx_lost_blocks_p1_o     : out std_logic := '0';
+      rx_lost_frames_p1_o     : out std_logic := '0';
+      rx_lost_frames_cnt_o    : out std_logic_vector(14 downto 0);
+      rx_latency_o            : out std_logic_vector(27 downto 0);
+      rx_latency_valid_o      : out std_logic;
+      rx_frame_p1_o           : out std_logic;
+      rx_streamer_cfg_i       : in t_rx_streamer_cfg := c_rx_streamer_cfg_default);
+  end component;
+
+  constant c_WRS_STATS_ARR_SIZE_OUT : integer := 18;
+  constant c_WRS_STATS_ARR_SIZE_IN  : integer := 1;
+
+  component xrtx_streamers_stats is
+    generic (
+      g_streamers_op_mode    : t_streamers_op_mode  := TX_AND_RX;
+      g_cnt_width            : integer := 50;
+      g_acc_width            : integer := 64
+      );
+    port (
+      clk_i                  : in std_logic;
+      rst_n_i                : in std_logic;
+      sent_frame_i           : in std_logic;
+      rcvd_frame_i           : in std_logic;
+      lost_block_i           : in std_logic;
+      lost_frame_i           : in std_logic;
+      lost_frames_cnt_i      : in std_logic_vector(14 downto 0);
+      rcvd_latency_i         : in  std_logic_vector(27 downto 0);
+      rcvd_latency_valid_i   : in  std_logic;
+      clk_ref_i              : in std_logic;
+      tm_time_valid_i        : in std_logic := '0';
+      tm_tai_i               : in std_logic_vector(39 downto 0) := x"0000000000";
+      tm_cycles_i            : in std_logic_vector(27 downto 0) := x"0000000";
+      reset_stats_i          : in std_logic;
+      snapshot_ena_i         : in std_logic := '0';
+      reset_time_tai_o       : out std_logic_vector(39 downto 0) := x"0000000000";
+      reset_time_cycles_o    : out std_logic_vector(27 downto 0) := x"0000000";
+      sent_frame_cnt_o       : out std_logic_vector(g_cnt_width-1 downto 0);
+      rcvd_frame_cnt_o       : out std_logic_vector(g_cnt_width-1 downto 0);
+      lost_frame_cnt_o       : out std_logic_vector(g_cnt_width-1 downto 0);
+      lost_block_cnt_o       : out std_logic_vector(g_cnt_width-1 downto 0);
+      latency_cnt_o          : out std_logic_vector(g_cnt_width-1 downto 0);
+      latency_acc_overflow_o : out std_logic;
+      latency_acc_o          : out std_logic_vector(g_acc_width-1  downto 0);
+      latency_max_o          : out std_logic_vector(27  downto 0);
+      latency_min_o          : out std_logic_vector(27  downto 0);
+      snmp_array_o           : out t_generic_word_array(c_WRS_STATS_ARR_SIZE_OUT-1 downto 0);
+      snmp_array_i           : in  t_generic_word_array(c_WRS_STATS_ARR_SIZE_IN -1 downto 0) := (others => (others=>'0'))
+      );
+  end component;
+
+  constant c_WR_STREAMERS_ARR_SIZE_OUT : integer := c_WRS_STATS_ARR_SIZE_OUT+2;
+  constant c_WR_STREAMERS_ARR_SIZE_IN  : integer := c_WRS_STATS_ARR_SIZE_IN;
+
+  component xwr_streamers is
+  generic (
+    g_streamers_op_mode        : t_streamers_op_mode  := TX_AND_RX;
+    --tx/rx
+    g_tx_streamer_params       : t_tx_streamer_params := c_tx_streamer_params_defaut;
+    g_rx_streamer_params       : t_rx_streamer_params := c_rx_streamer_params_defaut;
+    -- stats
+    g_stats_cnt_width          : integer := 50;
+    g_stats_acc_width          : integer := 64;
+    -- WB i/f
+    g_slave_mode               : t_wishbone_interface_mode      := CLASSIC;
+    g_slave_granularity        : t_wishbone_address_granularity := BYTE;
+    g_simulation               : integer := 0
+    );
+
+  port (
+    clk_sys_i                  : in std_logic;
+    rst_n_i                    : in std_logic;
+    -- WR tx/rx interface
+    src_i                      : in  t_wrf_source_in;
+    src_o                      : out t_wrf_source_out;
+    snk_i                      : in  t_wrf_sink_in;
+    snk_o                      : out t_wrf_sink_out;
+    -- User tx interface
+    tx_data_i                  : in std_logic_vector(g_tx_streamer_params.data_width-1 downto 0);
+    tx_valid_i                 : in std_logic;
+    tx_dreq_o                  : out std_logic;
+    tx_last_p1_i               : in std_logic := '1';
+    tx_flush_p1_i              : in std_logic := '0';
+    -- User rx interface
+    rx_first_p1_o              : out std_logic;
+    rx_last_p1_o               : out std_logic;
+    rx_data_o                  : out std_logic_vector(g_rx_streamer_params.data_width-1 downto 0);
+    rx_valid_o                 : out std_logic;
+    rx_dreq_i                  : in  std_logic;
+    -- WRC Timing interface, used for latency measurement
+    clk_ref_i                  : in std_logic := '0';
+    tm_time_valid_i            : in std_logic := '0';
+    tm_tai_i                   : in std_logic_vector(39 downto 0) := x"0000000000";
+    tm_cycles_i                : in std_logic_vector(27 downto 0) := x"0000000";
+    link_ok_i                  : in std_logic := '1';
+    wb_slave_i                 : in  t_wishbone_slave_in := cc_dummy_slave_in;
+    wb_slave_o                 : out t_wishbone_slave_out;
+    snmp_array_o               : out t_generic_word_array(c_WR_STREAMERS_ARR_SIZE_OUT-1 downto 0);
+    snmp_array_i               : in  t_generic_word_array(c_WR_STREAMERS_ARR_SIZE_IN -1 downto 0);
+    -- Transmission (tx) configuration
+    tx_streamer_cfg_i          : in  t_tx_streamer_cfg := c_tx_streamer_cfg_default;
+    rx_streamer_cfg_i          : in  t_rx_streamer_cfg := c_rx_streamer_cfg_default
+    );
+  end component;
+
+end streamers_pkg;
\ No newline at end of file
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/streamers_priv_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/streamers_priv_pkg.vhd
new file mode 100644
index 000000000..42c9aae8a
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/streamers_priv_pkg.vhd
@@ -0,0 +1,201 @@
+-------------------------------------------------------------------------------
+-- Title      : WR Streamers Private Packages
+-- Project    : WR Streamers
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/WR_Streamers
+-------------------------------------------------------------------------------
+-- File       : streamers_priv_pkg.vhd
+-- Author     : Maciej Lipinski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL
+-- Created    : 2017-04-20
+-------------------------------------------------------------------------------
+-- Description:
+-- Private package of streamers: all the components/functions used only by
+-- streamers, not useful by users/applications
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2017 CERN/BE-CO-HT
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.NUMERIC_STD.ALL;
+use work.wishbone_pkg.all;  -- needed for t_wishbone_slave_in, etc
+use work.streamers_pkg.all;
+use work.wr_streamers_wbgen2_pkg.all;
+
+package streamers_priv_pkg is
+
+  component xtx_streamers_stats is
+    generic (
+      g_cnt_width            : integer := 32);
+    port (
+      clk_i                  : in std_logic;
+      rst_n_i                : in std_logic;
+      sent_frame_i           : in std_logic;
+      reset_stats_i          : in std_logic;
+      snapshot_ena_i         : in std_logic := '0';
+      sent_frame_cnt_o       : out std_logic_vector(g_cnt_width-1 downto 0));
+  end component;
+
+  component xrx_streamers_stats is
+    generic (
+      g_cnt_width            : integer := 32;
+      g_acc_width            : integer := 64);
+    port (
+      clk_i                  : in std_logic;
+      rst_n_i                : in std_logic;
+      rcvd_frame_i           : in std_logic;
+      lost_block_i           : in std_logic;
+      lost_frame_i           : in std_logic;
+      lost_frames_cnt_i      : in std_logic_vector(14 downto 0);
+      rcvd_latency_i         : in  std_logic_vector(27 downto 0);
+      rcvd_latency_valid_i   : in  std_logic;
+      tm_time_valid_i        : in  std_logic;
+      snapshot_ena_i         : in std_logic := '0';
+      reset_stats_i          : in std_logic;
+      rcvd_frame_cnt_o       : out std_logic_vector(g_cnt_width-1 downto 0);
+      lost_frame_cnt_o       : out std_logic_vector(g_cnt_width-1 downto 0);
+      lost_block_cnt_o       : out std_logic_vector(g_cnt_width-1 downto 0);
+      latency_cnt_o          : out std_logic_vector(g_cnt_width-1 downto 0);
+      latency_acc_overflow_o : out std_logic;
+      latency_acc_o          : out std_logic_vector(g_acc_width-1  downto 0);
+      latency_max_o          : out std_logic_vector(27  downto 0);
+      latency_min_o          : out std_logic_vector(27  downto 0));
+  end component;
+
+  component  wr_streamers_wb is
+    port (
+      rst_n_i                                  : in     std_logic;
+      clk_sys_i                                : in     std_logic;
+      wb_adr_i                                 : in     std_logic_vector(5 downto 0);
+      wb_dat_i                                 : in     std_logic_vector(31 downto 0);
+      wb_dat_o                                 : out    std_logic_vector(31 downto 0);
+      wb_cyc_i                                 : in     std_logic;
+      wb_sel_i                                 : in     std_logic_vector(3 downto 0);
+      wb_stb_i                                 : in     std_logic;
+      wb_we_i                                  : in     std_logic;
+      wb_ack_o                                 : out    std_logic;
+      wb_stall_o                               : out    std_logic;
+      regs_i                                   : in     t_wr_streamers_in_registers;
+      regs_o                                   : out    t_wr_streamers_out_registers
+    );
+  end component;
+
+  -- component from wr-core/modules/timing
+  component pulse_stamper
+    port (
+      clk_ref_i       : in  std_logic;
+      clk_sys_i       : in  std_logic;
+      rst_n_i         : in  std_logic;
+      pulse_a_i       : in  std_logic;
+      tm_time_valid_i : in  std_logic;
+      tm_tai_i        : in  std_logic_vector(39 downto 0);
+      tm_cycles_i     : in  std_logic_vector(27 downto 0);
+      tag_tai_o       : out std_logic_vector(39 downto 0);
+      tag_cycles_o    : out std_logic_vector(27 downto 0);
+      tag_valid_o     : out std_logic);
+  end component;
+
+  type t_pipe is record
+    dvalid  : std_logic;
+    dreq    : std_logic;
+    sof     : std_logic;
+    eof     : std_logic;
+    error   : std_logic;
+    data    : std_logic_vector(15 downto 0);
+    addr    : std_logic_vector(1 downto 0);
+    bytesel : std_logic;
+  end record;
+
+  component escape_detector
+    generic (
+      g_data_width  : integer;
+      g_escape_code : std_logic_vector);
+    port (
+      clk_i             : in  std_logic;
+      rst_n_i           : in  std_logic;
+      d_i               : in  std_logic_vector(g_data_width-1 downto 0);
+      d_detect_enable_i : in  std_logic;
+      d_valid_i         : in  std_logic;
+      d_req_o           : out std_logic;
+      d_o               : out std_logic_vector(g_data_width-1 downto 0);
+      d_escape_o        : out std_logic;
+      d_valid_o         : out std_logic;
+      d_req_i           : in  std_logic);
+  end component;
+
+  component dropping_buffer
+    generic (
+      g_size       : integer;
+      g_data_width : integer);
+    port (
+      clk_i      : in  std_logic;
+      rst_n_i    : in  std_logic;
+      d_i        : in  std_logic_vector(g_data_width-1 downto 0);
+      d_req_o    : out std_logic;
+      d_drop_i   : in  std_logic;
+      d_accept_i : in  std_logic;
+      d_valid_i  : in  std_logic;
+      d_o        : out std_logic_vector(g_data_width-1 downto 0);
+      d_valid_o  : out std_logic;
+      d_req_i    : in  std_logic);
+  end component;
+
+  component gc_escape_inserter
+    generic (
+      g_data_width  : integer;
+      g_escape_code : std_logic_vector);
+    port (
+      clk_i             : in  std_logic;
+      rst_n_i           : in  std_logic;
+      d_i               : in  std_logic_vector(g_data_width-1 downto 0);
+      d_insert_enable_i : in  std_logic;
+      d_escape_i        : in  std_logic;
+      d_valid_i         : in  std_logic;
+      d_req_o           : out std_logic;
+      d_o               : out std_logic_vector (g_data_width-1 downto 0);
+      d_valid_o         : out std_logic;
+      d_req_i           : in  std_logic);
+  end component;
+  -- functions
+  function f_dbg_word_starting_at_bit(data_in, start_bit : std_logic_vector; g_data_width: integer) return std_logic_vector;
+
+end streamers_priv_pkg;
+
+package body streamers_priv_pkg is
+
+  function f_dbg_word_starting_at_bit(data_in, start_bit : std_logic_vector; g_data_width: integer) return std_logic_vector is
+    variable sb     : integer := 0;
+    variable result : std_logic_vector(31 downto 0);
+  begin
+    sb     := to_integer(unsigned(start_bit));
+    for i in 0 to 31 loop
+      if (sb + i < g_data_width) then 
+        result(i) := data_in(sb + i);
+      else 
+        result(i) := '0';
+      end if;
+    end loop;
+    return result;
+  end f_dbg_word_starting_at_bit;
+
+end streamers_priv_pkg;
\ No newline at end of file
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/wr_streamers_wb.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/wr_streamers_wb.vhd
new file mode 100644
index 000000000..c18bc310a
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/wr_streamers_wb.vhd
@@ -0,0 +1,706 @@
+---------------------------------------------------------------------------------------
+-- Title          : Wishbone slave core for WR Transmission control, status and debug
+---------------------------------------------------------------------------------------
+-- File           : wr_streamers_wb.vhd
+-- Author         : auto-generated by wbgen2 from wr_streamers_wb.wb
+-- Created        : Wed Aug 16 22:45:12 2017
+-- Version        : 0x00000001
+-- Standard       : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_streamers_wb.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.wr_streamers_wbgen2_pkg.all;
+
+
+entity wr_streamers_wb is
+  port (
+    rst_n_i                                  : in     std_logic;
+    clk_sys_i                                : in     std_logic;
+    wb_adr_i                                 : in     std_logic_vector(5 downto 0);
+    wb_dat_i                                 : in     std_logic_vector(31 downto 0);
+    wb_dat_o                                 : out    std_logic_vector(31 downto 0);
+    wb_cyc_i                                 : in     std_logic;
+    wb_sel_i                                 : in     std_logic_vector(3 downto 0);
+    wb_stb_i                                 : in     std_logic;
+    wb_we_i                                  : in     std_logic;
+    wb_ack_o                                 : out    std_logic;
+    wb_stall_o                               : out    std_logic;
+    regs_i                                   : in     t_wr_streamers_in_registers;
+    regs_o                                   : out    t_wr_streamers_out_registers
+  );
+end wr_streamers_wb;
+
+architecture syn of wr_streamers_wb is
+
+signal wr_streamers_ver_id_int                  : std_logic_vector(31 downto 0);
+signal wr_streamers_sscr1_rst_stats_dly0        : std_logic      ;
+signal wr_streamers_sscr1_rst_stats_int         : std_logic      ;
+signal wr_streamers_sscr1_rst_seq_id_dly0       : std_logic      ;
+signal wr_streamers_sscr1_rst_seq_id_int        : std_logic      ;
+signal wr_streamers_sscr1_snapshot_stats_int    : std_logic      ;
+signal wr_streamers_tx_cfg0_ethertype_int       : std_logic_vector(15 downto 0);
+signal wr_streamers_tx_cfg1_mac_local_lsb_int   : std_logic_vector(31 downto 0);
+signal wr_streamers_tx_cfg2_mac_local_msb_int   : std_logic_vector(15 downto 0);
+signal wr_streamers_tx_cfg3_mac_target_lsb_int  : std_logic_vector(31 downto 0);
+signal wr_streamers_tx_cfg4_mac_target_msb_int  : std_logic_vector(15 downto 0);
+signal wr_streamers_tx_cfg5_qtag_ena_int        : std_logic      ;
+signal wr_streamers_tx_cfg5_qtag_vid_int        : std_logic_vector(11 downto 0);
+signal wr_streamers_tx_cfg5_qtag_prio_int       : std_logic_vector(2 downto 0);
+signal wr_streamers_rx_cfg0_ethertype_int       : std_logic_vector(15 downto 0);
+signal wr_streamers_rx_cfg0_accept_broadcast_int : std_logic      ;
+signal wr_streamers_rx_cfg0_filter_remote_int   : std_logic      ;
+signal wr_streamers_rx_cfg1_mac_local_lsb_int   : std_logic_vector(31 downto 0);
+signal wr_streamers_rx_cfg2_mac_local_msb_int   : std_logic_vector(15 downto 0);
+signal wr_streamers_rx_cfg3_mac_remote_lsb_int  : std_logic_vector(31 downto 0);
+signal wr_streamers_rx_cfg4_mac_remote_msb_int  : std_logic_vector(15 downto 0);
+signal wr_streamers_rx_cfg5_fixed_latency_int   : std_logic_vector(27 downto 0);
+signal wr_streamers_cfg_or_tx_ethtype_int       : std_logic      ;
+signal wr_streamers_cfg_or_tx_mac_loc_int       : std_logic      ;
+signal wr_streamers_cfg_or_tx_mac_tar_int       : std_logic      ;
+signal wr_streamers_cfg_or_tx_qtag_int          : std_logic      ;
+signal wr_streamers_cfg_or_rx_ethertype_int     : std_logic      ;
+signal wr_streamers_cfg_or_rx_mac_loc_int       : std_logic      ;
+signal wr_streamers_cfg_or_rx_mac_rem_int       : std_logic      ;
+signal wr_streamers_cfg_or_rx_acc_broadcast_int : std_logic      ;
+signal wr_streamers_cfg_or_rx_ftr_remote_int    : std_logic      ;
+signal wr_streamers_cfg_or_rx_fix_lat_int       : std_logic      ;
+signal wr_streamers_dbg_ctrl_mux_int            : std_logic      ;
+signal wr_streamers_dbg_ctrl_start_byte_int     : std_logic_vector(7 downto 0);
+signal ack_sreg                                 : std_logic_vector(9 downto 0);
+signal rddata_reg                               : std_logic_vector(31 downto 0);
+signal wrdata_reg                               : std_logic_vector(31 downto 0);
+signal rwaddr_reg                               : std_logic_vector(5 downto 0);
+signal ack_in_progress                          : std_logic      ;
+
+begin
+-- Some internal signals assignments
+  wrdata_reg <= wb_dat_i;
+-- 
+-- Main register bank access process.
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ack_sreg <= "0000000000";
+      ack_in_progress <= '0';
+      rddata_reg <= "00000000000000000000000000000000";
+      wr_streamers_ver_id_int <= "00000000000000000000000000000001";
+      wr_streamers_sscr1_rst_stats_int <= '0';
+      wr_streamers_sscr1_rst_seq_id_int <= '0';
+      wr_streamers_sscr1_snapshot_stats_int <= '0';
+      wr_streamers_tx_cfg0_ethertype_int <= "0000000000000000";
+      wr_streamers_tx_cfg1_mac_local_lsb_int <= "00000000000000000000000000000000";
+      wr_streamers_tx_cfg2_mac_local_msb_int <= "0000000000000000";
+      wr_streamers_tx_cfg3_mac_target_lsb_int <= "00000000000000000000000000000000";
+      wr_streamers_tx_cfg4_mac_target_msb_int <= "0000000000000000";
+      wr_streamers_tx_cfg5_qtag_ena_int <= '0';
+      wr_streamers_tx_cfg5_qtag_vid_int <= "000000000000";
+      wr_streamers_tx_cfg5_qtag_prio_int <= "000";
+      wr_streamers_rx_cfg0_ethertype_int <= "0000000000000000";
+      wr_streamers_rx_cfg0_accept_broadcast_int <= '0';
+      wr_streamers_rx_cfg0_filter_remote_int <= '0';
+      wr_streamers_rx_cfg1_mac_local_lsb_int <= "00000000000000000000000000000000";
+      wr_streamers_rx_cfg2_mac_local_msb_int <= "0000000000000000";
+      wr_streamers_rx_cfg3_mac_remote_lsb_int <= "00000000000000000000000000000000";
+      wr_streamers_rx_cfg4_mac_remote_msb_int <= "0000000000000000";
+      wr_streamers_rx_cfg5_fixed_latency_int <= "0000000000000000000000000000";
+      wr_streamers_cfg_or_tx_ethtype_int <= '0';
+      wr_streamers_cfg_or_tx_mac_loc_int <= '0';
+      wr_streamers_cfg_or_tx_mac_tar_int <= '0';
+      wr_streamers_cfg_or_tx_qtag_int <= '0';
+      wr_streamers_cfg_or_rx_ethertype_int <= '0';
+      wr_streamers_cfg_or_rx_mac_loc_int <= '0';
+      wr_streamers_cfg_or_rx_mac_rem_int <= '0';
+      wr_streamers_cfg_or_rx_acc_broadcast_int <= '0';
+      wr_streamers_cfg_or_rx_ftr_remote_int <= '0';
+      wr_streamers_cfg_or_rx_fix_lat_int <= '0';
+      wr_streamers_dbg_ctrl_mux_int <= '0';
+      wr_streamers_dbg_ctrl_start_byte_int <= "00000000";
+    elsif rising_edge(clk_sys_i) then
+-- advance the ACK generator shift register
+      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
+      ack_sreg(9) <= '0';
+      if (ack_in_progress = '1') then
+        if (ack_sreg(0) = '1') then
+          wr_streamers_sscr1_rst_stats_int <= '0';
+          wr_streamers_sscr1_rst_seq_id_int <= '0';
+          ack_in_progress <= '0';
+        else
+        end if;
+      else
+        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
+          case rwaddr_reg(5 downto 0) is
+          when "000000" => 
+            if (wb_we_i = '1') then
+              wr_streamers_ver_id_int <= wrdata_reg(31 downto 0);
+            end if;
+            rddata_reg(31 downto 0) <= wr_streamers_ver_id_int;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "000001" => 
+            if (wb_we_i = '1') then
+              wr_streamers_sscr1_rst_stats_int <= wrdata_reg(0);
+              wr_streamers_sscr1_rst_seq_id_int <= wrdata_reg(1);
+              wr_streamers_sscr1_snapshot_stats_int <= wrdata_reg(2);
+            end if;
+            rddata_reg(0) <= '0';
+            rddata_reg(1) <= '0';
+            rddata_reg(2) <= wr_streamers_sscr1_snapshot_stats_int;
+            rddata_reg(3) <= regs_i.sscr1_rx_latency_acc_overflow_i;
+            rddata_reg(31 downto 4) <= regs_i.sscr1_rst_ts_cyc_i;
+            ack_sreg(2) <= '1';
+            ack_in_progress <= '1';
+          when "000010" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.sscr2_rst_ts_tai_lsb_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "000011" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(7 downto 0) <= regs_i.sscr3_rst_ts_tai_msb_i;
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "000100" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(27 downto 0) <= regs_i.rx_stat0_rx_latency_max_i;
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "000101" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(27 downto 0) <= regs_i.rx_stat1_rx_latency_min_i;
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "000110" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.tx_stat2_tx_sent_cnt_lsb_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "000111" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.tx_stat3_tx_sent_cnt_msb_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "001000" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.rx_stat4_rx_rcvd_cnt_lsb_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "001001" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.rx_stat5_rx_rcvd_cnt_msb_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "001010" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.rx_stat6_rx_loss_cnt_lsb_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "001011" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.rx_stat7_rx_loss_cnt_msb_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "001100" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.rx_stat8_rx_lost_block_cnt_lsb_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "001101" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.rx_stat9_rx_lost_block_cnt_msb_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "001110" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.rx_stat10_rx_latency_acc_lsb_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "001111" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.rx_stat11_rx_latency_acc_msb_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "010000" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.rx_stat12_rx_latency_acc_cnt_lsb_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "010001" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.rx_stat13_rx_latency_acc_cnt_msb_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "010010" => 
+            if (wb_we_i = '1') then
+              wr_streamers_tx_cfg0_ethertype_int <= wrdata_reg(15 downto 0);
+            end if;
+            rddata_reg(15 downto 0) <= wr_streamers_tx_cfg0_ethertype_int;
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "010011" => 
+            if (wb_we_i = '1') then
+              wr_streamers_tx_cfg1_mac_local_lsb_int <= wrdata_reg(31 downto 0);
+            end if;
+            rddata_reg(31 downto 0) <= wr_streamers_tx_cfg1_mac_local_lsb_int;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "010100" => 
+            if (wb_we_i = '1') then
+              wr_streamers_tx_cfg2_mac_local_msb_int <= wrdata_reg(15 downto 0);
+            end if;
+            rddata_reg(15 downto 0) <= wr_streamers_tx_cfg2_mac_local_msb_int;
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "010101" => 
+            if (wb_we_i = '1') then
+              wr_streamers_tx_cfg3_mac_target_lsb_int <= wrdata_reg(31 downto 0);
+            end if;
+            rddata_reg(31 downto 0) <= wr_streamers_tx_cfg3_mac_target_lsb_int;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "010110" => 
+            if (wb_we_i = '1') then
+              wr_streamers_tx_cfg4_mac_target_msb_int <= wrdata_reg(15 downto 0);
+            end if;
+            rddata_reg(15 downto 0) <= wr_streamers_tx_cfg4_mac_target_msb_int;
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "010111" => 
+            if (wb_we_i = '1') then
+              wr_streamers_tx_cfg5_qtag_ena_int <= wrdata_reg(0);
+              wr_streamers_tx_cfg5_qtag_vid_int <= wrdata_reg(19 downto 8);
+              wr_streamers_tx_cfg5_qtag_prio_int <= wrdata_reg(26 downto 24);
+            end if;
+            rddata_reg(0) <= wr_streamers_tx_cfg5_qtag_ena_int;
+            rddata_reg(19 downto 8) <= wr_streamers_tx_cfg5_qtag_vid_int;
+            rddata_reg(26 downto 24) <= wr_streamers_tx_cfg5_qtag_prio_int;
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "011000" => 
+            if (wb_we_i = '1') then
+              wr_streamers_rx_cfg0_ethertype_int <= wrdata_reg(15 downto 0);
+              wr_streamers_rx_cfg0_accept_broadcast_int <= wrdata_reg(16);
+              wr_streamers_rx_cfg0_filter_remote_int <= wrdata_reg(17);
+            end if;
+            rddata_reg(15 downto 0) <= wr_streamers_rx_cfg0_ethertype_int;
+            rddata_reg(16) <= wr_streamers_rx_cfg0_accept_broadcast_int;
+            rddata_reg(17) <= wr_streamers_rx_cfg0_filter_remote_int;
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "011001" => 
+            if (wb_we_i = '1') then
+              wr_streamers_rx_cfg1_mac_local_lsb_int <= wrdata_reg(31 downto 0);
+            end if;
+            rddata_reg(31 downto 0) <= wr_streamers_rx_cfg1_mac_local_lsb_int;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "011010" => 
+            if (wb_we_i = '1') then
+              wr_streamers_rx_cfg2_mac_local_msb_int <= wrdata_reg(15 downto 0);
+            end if;
+            rddata_reg(15 downto 0) <= wr_streamers_rx_cfg2_mac_local_msb_int;
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "011011" => 
+            if (wb_we_i = '1') then
+              wr_streamers_rx_cfg3_mac_remote_lsb_int <= wrdata_reg(31 downto 0);
+            end if;
+            rddata_reg(31 downto 0) <= wr_streamers_rx_cfg3_mac_remote_lsb_int;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "011100" => 
+            if (wb_we_i = '1') then
+              wr_streamers_rx_cfg4_mac_remote_msb_int <= wrdata_reg(15 downto 0);
+            end if;
+            rddata_reg(15 downto 0) <= wr_streamers_rx_cfg4_mac_remote_msb_int;
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "011101" => 
+            if (wb_we_i = '1') then
+              wr_streamers_rx_cfg5_fixed_latency_int <= wrdata_reg(27 downto 0);
+            end if;
+            rddata_reg(27 downto 0) <= wr_streamers_rx_cfg5_fixed_latency_int;
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "011110" => 
+            if (wb_we_i = '1') then
+              wr_streamers_cfg_or_tx_ethtype_int <= wrdata_reg(0);
+              wr_streamers_cfg_or_tx_mac_loc_int <= wrdata_reg(1);
+              wr_streamers_cfg_or_tx_mac_tar_int <= wrdata_reg(2);
+              wr_streamers_cfg_or_tx_qtag_int <= wrdata_reg(3);
+              wr_streamers_cfg_or_rx_ethertype_int <= wrdata_reg(16);
+              wr_streamers_cfg_or_rx_mac_loc_int <= wrdata_reg(17);
+              wr_streamers_cfg_or_rx_mac_rem_int <= wrdata_reg(18);
+              wr_streamers_cfg_or_rx_acc_broadcast_int <= wrdata_reg(19);
+              wr_streamers_cfg_or_rx_ftr_remote_int <= wrdata_reg(20);
+              wr_streamers_cfg_or_rx_fix_lat_int <= wrdata_reg(21);
+            end if;
+            rddata_reg(0) <= wr_streamers_cfg_or_tx_ethtype_int;
+            rddata_reg(1) <= wr_streamers_cfg_or_tx_mac_loc_int;
+            rddata_reg(2) <= wr_streamers_cfg_or_tx_mac_tar_int;
+            rddata_reg(3) <= wr_streamers_cfg_or_tx_qtag_int;
+            rddata_reg(16) <= wr_streamers_cfg_or_rx_ethertype_int;
+            rddata_reg(17) <= wr_streamers_cfg_or_rx_mac_loc_int;
+            rddata_reg(18) <= wr_streamers_cfg_or_rx_mac_rem_int;
+            rddata_reg(19) <= wr_streamers_cfg_or_rx_acc_broadcast_int;
+            rddata_reg(20) <= wr_streamers_cfg_or_rx_ftr_remote_int;
+            rddata_reg(21) <= wr_streamers_cfg_or_rx_fix_lat_int;
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "011111" => 
+            if (wb_we_i = '1') then
+              wr_streamers_dbg_ctrl_mux_int <= wrdata_reg(0);
+              wr_streamers_dbg_ctrl_start_byte_int <= wrdata_reg(15 downto 8);
+            end if;
+            rddata_reg(0) <= wr_streamers_dbg_ctrl_mux_int;
+            rddata_reg(15 downto 8) <= wr_streamers_dbg_ctrl_start_byte_int;
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "100000" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.dbg_data_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "100001" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.dummy_dummy_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when others =>
+-- prevent the slave from hanging the bus on invalid address
+            ack_in_progress <= '1';
+            ack_sreg(0) <= '1';
+          end case;
+        end if;
+      end if;
+    end if;
+  end process;
+  
+  
+-- Drive the data output bus
+  wb_dat_o <= rddata_reg;
+-- Version identifier
+  regs_o.ver_id_o <= wr_streamers_ver_id_int;
+-- Reset statistics
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      wr_streamers_sscr1_rst_stats_dly0 <= '0';
+      regs_o.sscr1_rst_stats_o <= '0';
+    elsif rising_edge(clk_sys_i) then
+      wr_streamers_sscr1_rst_stats_dly0 <= wr_streamers_sscr1_rst_stats_int;
+      regs_o.sscr1_rst_stats_o <= wr_streamers_sscr1_rst_stats_int and (not wr_streamers_sscr1_rst_stats_dly0);
+    end if;
+  end process;
+  
+  
+-- Reset tx seq id
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      wr_streamers_sscr1_rst_seq_id_dly0 <= '0';
+      regs_o.sscr1_rst_seq_id_o <= '0';
+    elsif rising_edge(clk_sys_i) then
+      wr_streamers_sscr1_rst_seq_id_dly0 <= wr_streamers_sscr1_rst_seq_id_int;
+      regs_o.sscr1_rst_seq_id_o <= wr_streamers_sscr1_rst_seq_id_int and (not wr_streamers_sscr1_rst_seq_id_dly0);
+    end if;
+  end process;
+  
+  
+-- Snapshot statistics
+  regs_o.sscr1_snapshot_stats_o <= wr_streamers_sscr1_snapshot_stats_int;
+-- Latency accumulator overflow
+-- Reset timestamp cycles
+-- Reset timestamp 32 LSB of TAI
+-- Reset timestamp 8 MSB of TAI
+-- WR Streamer frame latency
+-- WR Streamer frame latency
+-- WR Streamer frame sent count (LSB)
+-- WR Streamer frame sent count (MSB)
+-- WR Streamer frame received count (LSB)
+-- WR Streamer frame received count (MSB)
+-- WR Streamer frame loss count (LSB)
+-- WR Streamer frame loss count (MSB)
+-- WR Streamer block loss count (LSB)
+-- WR Streamer block loss count (MSB)
+-- WR Streamer frame latency (LSB)
+-- WR Streamer frame latency (MSB)
+-- WR Streamer frame latency counter (LSB)
+-- WR Streamer frame latency counter (MSB)
+-- Ethertype
+  regs_o.tx_cfg0_ethertype_o <= wr_streamers_tx_cfg0_ethertype_int;
+-- MAC Local LSB
+  regs_o.tx_cfg1_mac_local_lsb_o <= wr_streamers_tx_cfg1_mac_local_lsb_int;
+-- MAC Local MSB
+  regs_o.tx_cfg2_mac_local_msb_o <= wr_streamers_tx_cfg2_mac_local_msb_int;
+-- MAC Target LSB
+  regs_o.tx_cfg3_mac_target_lsb_o <= wr_streamers_tx_cfg3_mac_target_lsb_int;
+-- MAC Target MSB
+  regs_o.tx_cfg4_mac_target_msb_o <= wr_streamers_tx_cfg4_mac_target_msb_int;
+-- Enable tagging with Qtags
+  regs_o.tx_cfg5_qtag_ena_o <= wr_streamers_tx_cfg5_qtag_ena_int;
+-- VLAN ID
+  regs_o.tx_cfg5_qtag_vid_o <= wr_streamers_tx_cfg5_qtag_vid_int;
+-- Priority
+  regs_o.tx_cfg5_qtag_prio_o <= wr_streamers_tx_cfg5_qtag_prio_int;
+-- Ethertype
+  regs_o.rx_cfg0_ethertype_o <= wr_streamers_rx_cfg0_ethertype_int;
+-- Accept Broadcast
+  regs_o.rx_cfg0_accept_broadcast_o <= wr_streamers_rx_cfg0_accept_broadcast_int;
+-- Filter Remote
+  regs_o.rx_cfg0_filter_remote_o <= wr_streamers_rx_cfg0_filter_remote_int;
+-- MAC Local LSB
+  regs_o.rx_cfg1_mac_local_lsb_o <= wr_streamers_rx_cfg1_mac_local_lsb_int;
+-- MAC Local MSB
+  regs_o.rx_cfg2_mac_local_msb_o <= wr_streamers_rx_cfg2_mac_local_msb_int;
+-- MAC Remote LSB
+  regs_o.rx_cfg3_mac_remote_lsb_o <= wr_streamers_rx_cfg3_mac_remote_lsb_int;
+-- MAC Remote MSB
+  regs_o.rx_cfg4_mac_remote_msb_o <= wr_streamers_rx_cfg4_mac_remote_msb_int;
+-- Fixed Latency
+  regs_o.rx_cfg5_fixed_latency_o <= wr_streamers_rx_cfg5_fixed_latency_int;
+-- Tx Ethertype
+  regs_o.cfg_or_tx_ethtype_o <= wr_streamers_cfg_or_tx_ethtype_int;
+-- Tx MAC Local
+  regs_o.cfg_or_tx_mac_loc_o <= wr_streamers_cfg_or_tx_mac_loc_int;
+-- Tx MAC Target
+  regs_o.cfg_or_tx_mac_tar_o <= wr_streamers_cfg_or_tx_mac_tar_int;
+-- QTAG
+  regs_o.cfg_or_tx_qtag_o <= wr_streamers_cfg_or_tx_qtag_int;
+-- Rx Ethertype
+  regs_o.cfg_or_rx_ethertype_o <= wr_streamers_cfg_or_rx_ethertype_int;
+-- Rx MAC Local
+  regs_o.cfg_or_rx_mac_loc_o <= wr_streamers_cfg_or_rx_mac_loc_int;
+-- Rx MAC Remote
+  regs_o.cfg_or_rx_mac_rem_o <= wr_streamers_cfg_or_rx_mac_rem_int;
+-- Rx Accept Broadcast
+  regs_o.cfg_or_rx_acc_broadcast_o <= wr_streamers_cfg_or_rx_acc_broadcast_int;
+-- Rx Filter Remote
+  regs_o.cfg_or_rx_ftr_remote_o <= wr_streamers_cfg_or_rx_ftr_remote_int;
+-- Rx Fixed Latency 
+  regs_o.cfg_or_rx_fix_lat_o <= wr_streamers_cfg_or_rx_fix_lat_int;
+-- Debug Tx (0) or Rx (1)
+  regs_o.dbg_ctrl_mux_o <= wr_streamers_dbg_ctrl_mux_int;
+-- Debug Start byte
+  regs_o.dbg_ctrl_start_byte_o <= wr_streamers_dbg_ctrl_start_byte_int;
+-- Debug content
+-- DUMMY value to read
+  rwaddr_reg <= wb_adr_i;
+  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
+-- ACK signal generation. Just pass the LSB of ACK counter.
+  wb_ack_o <= ack_sreg(0);
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd
new file mode 100644
index 000000000..a39fc326b
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd
@@ -0,0 +1,191 @@
+---------------------------------------------------------------------------------------
+-- Title          : Wishbone slave core for WR Transmission control, status and debug
+---------------------------------------------------------------------------------------
+-- File           : wr_streamers_wbgen2_pkg.vhd
+-- Author         : auto-generated by wbgen2 from wr_streamers_wb.wb
+-- Created        : Wed Aug 16 22:45:12 2017
+-- Version        : 0x00000001
+-- Standard       : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_streamers_wb.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package wr_streamers_wbgen2_pkg is
+  
+  
+  -- Input registers (user design -> WB slave)
+  
+  type t_wr_streamers_in_registers is record
+    sscr1_rx_latency_acc_overflow_i          : std_logic;
+    sscr1_rst_ts_cyc_i                       : std_logic_vector(27 downto 0);
+    sscr2_rst_ts_tai_lsb_i                   : std_logic_vector(31 downto 0);
+    sscr3_rst_ts_tai_msb_i                   : std_logic_vector(7 downto 0);
+    rx_stat0_rx_latency_max_i                : std_logic_vector(27 downto 0);
+    rx_stat1_rx_latency_min_i                : std_logic_vector(27 downto 0);
+    tx_stat2_tx_sent_cnt_lsb_i               : std_logic_vector(31 downto 0);
+    tx_stat3_tx_sent_cnt_msb_i               : std_logic_vector(31 downto 0);
+    rx_stat4_rx_rcvd_cnt_lsb_i               : std_logic_vector(31 downto 0);
+    rx_stat5_rx_rcvd_cnt_msb_i               : std_logic_vector(31 downto 0);
+    rx_stat6_rx_loss_cnt_lsb_i               : std_logic_vector(31 downto 0);
+    rx_stat7_rx_loss_cnt_msb_i               : std_logic_vector(31 downto 0);
+    rx_stat8_rx_lost_block_cnt_lsb_i         : std_logic_vector(31 downto 0);
+    rx_stat9_rx_lost_block_cnt_msb_i         : std_logic_vector(31 downto 0);
+    rx_stat10_rx_latency_acc_lsb_i           : std_logic_vector(31 downto 0);
+    rx_stat11_rx_latency_acc_msb_i           : std_logic_vector(31 downto 0);
+    rx_stat12_rx_latency_acc_cnt_lsb_i       : std_logic_vector(31 downto 0);
+    rx_stat13_rx_latency_acc_cnt_msb_i       : std_logic_vector(31 downto 0);
+    dbg_data_i                               : std_logic_vector(31 downto 0);
+    dummy_dummy_i                            : std_logic_vector(31 downto 0);
+    end record;
+  
+  constant c_wr_streamers_in_registers_init_value: t_wr_streamers_in_registers := (
+    sscr1_rx_latency_acc_overflow_i => '0',
+    sscr1_rst_ts_cyc_i => (others => '0'),
+    sscr2_rst_ts_tai_lsb_i => (others => '0'),
+    sscr3_rst_ts_tai_msb_i => (others => '0'),
+    rx_stat0_rx_latency_max_i => (others => '0'),
+    rx_stat1_rx_latency_min_i => (others => '0'),
+    tx_stat2_tx_sent_cnt_lsb_i => (others => '0'),
+    tx_stat3_tx_sent_cnt_msb_i => (others => '0'),
+    rx_stat4_rx_rcvd_cnt_lsb_i => (others => '0'),
+    rx_stat5_rx_rcvd_cnt_msb_i => (others => '0'),
+    rx_stat6_rx_loss_cnt_lsb_i => (others => '0'),
+    rx_stat7_rx_loss_cnt_msb_i => (others => '0'),
+    rx_stat8_rx_lost_block_cnt_lsb_i => (others => '0'),
+    rx_stat9_rx_lost_block_cnt_msb_i => (others => '0'),
+    rx_stat10_rx_latency_acc_lsb_i => (others => '0'),
+    rx_stat11_rx_latency_acc_msb_i => (others => '0'),
+    rx_stat12_rx_latency_acc_cnt_lsb_i => (others => '0'),
+    rx_stat13_rx_latency_acc_cnt_msb_i => (others => '0'),
+    dbg_data_i => (others => '0'),
+    dummy_dummy_i => (others => '0')
+    );
+    
+    -- Output registers (WB slave -> user design)
+    
+    type t_wr_streamers_out_registers is record
+      ver_id_o                                 : std_logic_vector(31 downto 0);
+      sscr1_rst_stats_o                        : std_logic;
+      sscr1_rst_seq_id_o                       : std_logic;
+      sscr1_snapshot_stats_o                   : std_logic;
+      tx_cfg0_ethertype_o                      : std_logic_vector(15 downto 0);
+      tx_cfg1_mac_local_lsb_o                  : std_logic_vector(31 downto 0);
+      tx_cfg2_mac_local_msb_o                  : std_logic_vector(15 downto 0);
+      tx_cfg3_mac_target_lsb_o                 : std_logic_vector(31 downto 0);
+      tx_cfg4_mac_target_msb_o                 : std_logic_vector(15 downto 0);
+      tx_cfg5_qtag_ena_o                       : std_logic;
+      tx_cfg5_qtag_vid_o                       : std_logic_vector(11 downto 0);
+      tx_cfg5_qtag_prio_o                      : std_logic_vector(2 downto 0);
+      rx_cfg0_ethertype_o                      : std_logic_vector(15 downto 0);
+      rx_cfg0_accept_broadcast_o               : std_logic;
+      rx_cfg0_filter_remote_o                  : std_logic;
+      rx_cfg1_mac_local_lsb_o                  : std_logic_vector(31 downto 0);
+      rx_cfg2_mac_local_msb_o                  : std_logic_vector(15 downto 0);
+      rx_cfg3_mac_remote_lsb_o                 : std_logic_vector(31 downto 0);
+      rx_cfg4_mac_remote_msb_o                 : std_logic_vector(15 downto 0);
+      rx_cfg5_fixed_latency_o                  : std_logic_vector(27 downto 0);
+      cfg_or_tx_ethtype_o                      : std_logic;
+      cfg_or_tx_mac_loc_o                      : std_logic;
+      cfg_or_tx_mac_tar_o                      : std_logic;
+      cfg_or_tx_qtag_o                         : std_logic;
+      cfg_or_rx_ethertype_o                    : std_logic;
+      cfg_or_rx_mac_loc_o                      : std_logic;
+      cfg_or_rx_mac_rem_o                      : std_logic;
+      cfg_or_rx_acc_broadcast_o                : std_logic;
+      cfg_or_rx_ftr_remote_o                   : std_logic;
+      cfg_or_rx_fix_lat_o                      : std_logic;
+      dbg_ctrl_mux_o                           : std_logic;
+      dbg_ctrl_start_byte_o                    : std_logic_vector(7 downto 0);
+      end record;
+    
+    constant c_wr_streamers_out_registers_init_value: t_wr_streamers_out_registers := (
+      ver_id_o => (others => '0'),
+      sscr1_rst_stats_o => '0',
+      sscr1_rst_seq_id_o => '0',
+      sscr1_snapshot_stats_o => '0',
+      tx_cfg0_ethertype_o => (others => '0'),
+      tx_cfg1_mac_local_lsb_o => (others => '0'),
+      tx_cfg2_mac_local_msb_o => (others => '0'),
+      tx_cfg3_mac_target_lsb_o => (others => '0'),
+      tx_cfg4_mac_target_msb_o => (others => '0'),
+      tx_cfg5_qtag_ena_o => '0',
+      tx_cfg5_qtag_vid_o => (others => '0'),
+      tx_cfg5_qtag_prio_o => (others => '0'),
+      rx_cfg0_ethertype_o => (others => '0'),
+      rx_cfg0_accept_broadcast_o => '0',
+      rx_cfg0_filter_remote_o => '0',
+      rx_cfg1_mac_local_lsb_o => (others => '0'),
+      rx_cfg2_mac_local_msb_o => (others => '0'),
+      rx_cfg3_mac_remote_lsb_o => (others => '0'),
+      rx_cfg4_mac_remote_msb_o => (others => '0'),
+      rx_cfg5_fixed_latency_o => (others => '0'),
+      cfg_or_tx_ethtype_o => '0',
+      cfg_or_tx_mac_loc_o => '0',
+      cfg_or_tx_mac_tar_o => '0',
+      cfg_or_tx_qtag_o => '0',
+      cfg_or_rx_ethertype_o => '0',
+      cfg_or_rx_mac_loc_o => '0',
+      cfg_or_rx_mac_rem_o => '0',
+      cfg_or_rx_acc_broadcast_o => '0',
+      cfg_or_rx_ftr_remote_o => '0',
+      cfg_or_rx_fix_lat_o => '0',
+      dbg_ctrl_mux_o => '0',
+      dbg_ctrl_start_byte_o => (others => '0')
+      );
+    function "or" (left, right: t_wr_streamers_in_registers) return t_wr_streamers_in_registers;
+    function f_x_to_zero (x:std_logic) return std_logic;
+    function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
+end package;
+
+package body wr_streamers_wbgen2_pkg is
+function f_x_to_zero (x:std_logic) return std_logic is
+begin
+if x = '1' then
+return '1';
+else
+return '0';
+end if;
+end function;
+function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
+variable tmp: std_logic_vector(x'length-1 downto 0);
+begin
+for i in 0 to x'length-1 loop
+if x(i) = '1' then
+tmp(i):= '1';
+else
+tmp(i):= '0';
+end if; 
+end loop; 
+return tmp;
+end function;
+function "or" (left, right: t_wr_streamers_in_registers) return t_wr_streamers_in_registers is
+variable tmp: t_wr_streamers_in_registers;
+begin
+tmp.sscr1_rx_latency_acc_overflow_i := f_x_to_zero(left.sscr1_rx_latency_acc_overflow_i) or f_x_to_zero(right.sscr1_rx_latency_acc_overflow_i);
+tmp.sscr1_rst_ts_cyc_i := f_x_to_zero(left.sscr1_rst_ts_cyc_i) or f_x_to_zero(right.sscr1_rst_ts_cyc_i);
+tmp.sscr2_rst_ts_tai_lsb_i := f_x_to_zero(left.sscr2_rst_ts_tai_lsb_i) or f_x_to_zero(right.sscr2_rst_ts_tai_lsb_i);
+tmp.sscr3_rst_ts_tai_msb_i := f_x_to_zero(left.sscr3_rst_ts_tai_msb_i) or f_x_to_zero(right.sscr3_rst_ts_tai_msb_i);
+tmp.rx_stat0_rx_latency_max_i := f_x_to_zero(left.rx_stat0_rx_latency_max_i) or f_x_to_zero(right.rx_stat0_rx_latency_max_i);
+tmp.rx_stat1_rx_latency_min_i := f_x_to_zero(left.rx_stat1_rx_latency_min_i) or f_x_to_zero(right.rx_stat1_rx_latency_min_i);
+tmp.tx_stat2_tx_sent_cnt_lsb_i := f_x_to_zero(left.tx_stat2_tx_sent_cnt_lsb_i) or f_x_to_zero(right.tx_stat2_tx_sent_cnt_lsb_i);
+tmp.tx_stat3_tx_sent_cnt_msb_i := f_x_to_zero(left.tx_stat3_tx_sent_cnt_msb_i) or f_x_to_zero(right.tx_stat3_tx_sent_cnt_msb_i);
+tmp.rx_stat4_rx_rcvd_cnt_lsb_i := f_x_to_zero(left.rx_stat4_rx_rcvd_cnt_lsb_i) or f_x_to_zero(right.rx_stat4_rx_rcvd_cnt_lsb_i);
+tmp.rx_stat5_rx_rcvd_cnt_msb_i := f_x_to_zero(left.rx_stat5_rx_rcvd_cnt_msb_i) or f_x_to_zero(right.rx_stat5_rx_rcvd_cnt_msb_i);
+tmp.rx_stat6_rx_loss_cnt_lsb_i := f_x_to_zero(left.rx_stat6_rx_loss_cnt_lsb_i) or f_x_to_zero(right.rx_stat6_rx_loss_cnt_lsb_i);
+tmp.rx_stat7_rx_loss_cnt_msb_i := f_x_to_zero(left.rx_stat7_rx_loss_cnt_msb_i) or f_x_to_zero(right.rx_stat7_rx_loss_cnt_msb_i);
+tmp.rx_stat8_rx_lost_block_cnt_lsb_i := f_x_to_zero(left.rx_stat8_rx_lost_block_cnt_lsb_i) or f_x_to_zero(right.rx_stat8_rx_lost_block_cnt_lsb_i);
+tmp.rx_stat9_rx_lost_block_cnt_msb_i := f_x_to_zero(left.rx_stat9_rx_lost_block_cnt_msb_i) or f_x_to_zero(right.rx_stat9_rx_lost_block_cnt_msb_i);
+tmp.rx_stat10_rx_latency_acc_lsb_i := f_x_to_zero(left.rx_stat10_rx_latency_acc_lsb_i) or f_x_to_zero(right.rx_stat10_rx_latency_acc_lsb_i);
+tmp.rx_stat11_rx_latency_acc_msb_i := f_x_to_zero(left.rx_stat11_rx_latency_acc_msb_i) or f_x_to_zero(right.rx_stat11_rx_latency_acc_msb_i);
+tmp.rx_stat12_rx_latency_acc_cnt_lsb_i := f_x_to_zero(left.rx_stat12_rx_latency_acc_cnt_lsb_i) or f_x_to_zero(right.rx_stat12_rx_latency_acc_cnt_lsb_i);
+tmp.rx_stat13_rx_latency_acc_cnt_msb_i := f_x_to_zero(left.rx_stat13_rx_latency_acc_cnt_msb_i) or f_x_to_zero(right.rx_stat13_rx_latency_acc_cnt_msb_i);
+tmp.dbg_data_i := f_x_to_zero(left.dbg_data_i) or f_x_to_zero(right.dbg_data_i);
+tmp.dummy_dummy_i := f_x_to_zero(left.dummy_dummy_i) or f_x_to_zero(right.dummy_dummy_i);
+return tmp;
+end function;
+end package body;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/xrtx_streamers_stats.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/xrtx_streamers_stats.vhd
new file mode 100644
index 000000000..05f22a807
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/xrtx_streamers_stats.vhd
@@ -0,0 +1,362 @@
+-------------------------------------------------------------------------------
+-- Title      : WR Streamers statistics
+-- Project    : WR Streamers
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/WR_Streamers
+-------------------------------------------------------------------------------
+-- File       : xrtx_streamers_stats.vhd
+-- Author     : Maciej Lipinski
+-- Company    : CERN
+-- Created    : 2016-06-08
+-- Platform   : FPGA-generics
+-- Standard   : VHDL
+-------------------------------------------------------------------------------
+-- Description:
+-- Module to collect, reset, snapshot statistics from the streamers. The
+-- statistics are made available through wishbone I/F (outside this entity)
+-- and diags_i/o (generic input/output arrays of 32-bit registers). Wishbone I/F
+-- can be read via bus (PCI, VME,...). Diags can be read via wrpc commands and 
+-- SNMP.
+--
+-- The module provides basic statistics such as:
+-- * number of sent/received streamer frames
+-- * number of lost frames/blocks
+-- * accumulated latency of streamer frames
+-- * count of the accumulated latencies
+-- * max/min latency
+-- * timestamp of the reset pulse
+--
+-- The module allows to snapshot the statistics values as to have a coherent
+-- view.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2016-2017CERN/BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+library work;
+use work.wishbone_pkg.all;  -- needed for t_wishbone_slave_in, etc
+use work.streamers_pkg.all; -- needed for streamers
+use work.wr_fabric_pkg.all; -- neede for :t_wrf_source_in, etc
+use work.wrcore_pkg.all;    -- needed for t_generic_word_array
+use work.streamers_priv_pkg.all;
+
+entity xrtx_streamers_stats is
+  generic (
+    -- Indicates whether this module instantiates both streamers (rx and tx) or only one
+    -- of them. An application that only receives or only transmits might want to use
+    -- RX_ONLY or TX_ONLY mode to save resources.
+    g_streamers_op_mode    : t_streamers_op_mode  := TX_AND_RX;
+    -- Width of frame counters
+    g_cnt_width            : integer := 50; -- min:15, max:64, 50 bits should be ok for 50 years
+    g_acc_width            : integer := 64  -- max value 64
+    );
+  port (
+    clk_i                  : in std_logic;
+    rst_n_i                : in std_logic;
+
+    -- input signals from streamers
+    sent_frame_i           : in std_logic;
+    rcvd_frame_i           : in std_logic;
+    lost_block_i           : in std_logic;
+    lost_frame_i           : in std_logic;
+    lost_frames_cnt_i      : in std_logic_vector(14 downto 0);
+    rcvd_latency_i         : in  std_logic_vector(27 downto 0);
+    rcvd_latency_valid_i   : in  std_logic;
+
+    clk_ref_i              : in std_logic;
+    tm_time_valid_i        : in std_logic := '0';
+    tm_tai_i               : in std_logic_vector(39 downto 0) := x"0000000000";
+    tm_cycles_i            : in std_logic_vector(27 downto 0) := x"0000000";
+
+    -- statistic control
+    reset_stats_i          : in std_logic;
+    snapshot_ena_i         : in std_logic := '0';
+    ----------------------- statistics ----------------------------------------
+    -- output statistics: time of last reset of statistics
+    reset_time_tai_o       : out std_logic_vector(39 downto 0) := x"0000000000";
+    reset_time_cycles_o    : out std_logic_vector(27 downto 0) := x"0000000";
+    -- output statistics: tx/rx counters
+    sent_frame_cnt_o       : out std_logic_vector(g_cnt_width-1 downto 0);
+    rcvd_frame_cnt_o       : out std_logic_vector(g_cnt_width-1 downto 0);
+    lost_frame_cnt_o       : out std_logic_vector(g_cnt_width-1 downto 0);
+    lost_block_cnt_o       : out std_logic_vector(g_cnt_width-1 downto 0);
+    -- output statistics: latency
+    latency_cnt_o          : out std_logic_vector(g_cnt_width-1 downto 0);
+    latency_acc_overflow_o : out std_logic;
+    latency_acc_o          : out std_logic_vector(g_acc_width-1  downto 0);
+    latency_max_o          : out std_logic_vector(27  downto 0);
+    latency_min_o          : out std_logic_vector(27  downto 0);
+
+    snmp_array_o           : out t_generic_word_array(c_WRS_STATS_ARR_SIZE_OUT-1 downto 0);
+    snmp_array_i           : in  t_generic_word_array(c_WRS_STATS_ARR_SIZE_IN -1 downto 0)
+    );
+
+end xrtx_streamers_stats;
+
+architecture rtl of xrtx_streamers_stats is
+
+  signal reset_time_tai    : std_logic_vector(39 downto 0);
+  signal reset_time_cycles : std_logic_vector(27 downto 0);
+
+  signal sent_frame_cnt    : unsigned(g_cnt_width-1  downto 0);
+  signal rcvd_frame_cnt    : unsigned(g_cnt_width-1  downto 0);
+  signal lost_frame_cnt    : unsigned(g_cnt_width-1  downto 0);
+  signal lost_block_cnt    : unsigned(g_cnt_width-1  downto 0);
+  signal latency_cnt       : unsigned(g_cnt_width-1  downto 0);
+
+  signal latency_max       : std_logic_vector(27  downto 0);
+  signal latency_min       : std_logic_vector(27  downto 0);
+  signal latency_acc       : unsigned(g_acc_width-1+1  downto 0);
+  signal latency_acc_overflow: std_logic;
+
+  signal sent_frame_cnt_out       : std_logic_vector(g_cnt_width-1 downto 0);
+  signal rcvd_frame_cnt_out       : std_logic_vector(g_cnt_width-1 downto 0);
+  signal lost_frame_cnt_out       : std_logic_vector(g_cnt_width-1 downto 0);
+  signal lost_block_cnt_out       : std_logic_vector(g_cnt_width-1 downto 0);
+  signal latency_cnt_out          : std_logic_vector(g_cnt_width-1 downto 0);
+  signal latency_acc_overflow_out : std_logic;
+  signal latency_acc_out          : std_logic_vector(g_acc_width-1  downto 0);
+  signal latency_max_out          : std_logic_vector(27  downto 0);
+  signal latency_min_out          : std_logic_vector(27  downto 0);
+
+  --- statistics resets:
+  signal reset_stats_remote: std_logic;
+  signal reset_stats       : std_logic;
+  signal reset_stats_d1    : std_logic;
+  signal reset_stats_p     : std_logic;
+  signal snapshot_remote_ena  : std_logic;
+  signal snapshot_ena      : std_logic;
+  signal snapshot_ena_d1   : std_logic;
+  
+  -- for code cleanness
+  constant c_cw              : integer := g_cnt_width;
+  constant c_aw              : integer := g_acc_width;
+begin
+
+  -- reset statistics when receiving signal from SNMP or Wishbone
+  reset_stats <= reset_stats_remote or reset_stats_i;
+  -------------------------------------------------------------------------------------------
+  -- produce pulse of reset input signal, this pulse produces timesstamp to be timestamped
+  -------------------------------------------------------------------------------------------
+  -- pulse is on falling and rising edge of the reset signal (reset when signal HIGH)
+  -- in this way, one can 
+  -- 1. read the timestamp of the start of statistics acquisition
+  -- 2. reset HIGH
+  -- 3. read the timestamp of the end of statistics acquisition
+  -- 4. start acqusition
+  -------------------------------------------------------------------------------------------
+  -- when exiting the reset, produce pulse for the timestamper
+  p_stats_reset: process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if (rst_n_i = '0') then
+         reset_stats_p  <= '0';
+         reset_stats_d1 <= '0';
+      else
+        reset_stats_d1 <= reset_stats;
+        reset_stats_p  <= reset_stats xor reset_stats_d1;
+      end if;
+    end if;
+  end process;
+
+  -------------------------------------------------------------------------------------------
+  -- Timestamp of reset
+  -------------------------------------------------------------------------------------------
+  -- process that timestamps the reset so that we can make statistics over time
+  U_Reset_Timestamper : pulse_stamper
+    port map (
+      clk_ref_i       => clk_ref_i,
+      clk_sys_i       => clk_i,
+      rst_n_i         => rst_n_i,
+      pulse_a_i       => reset_stats_p,
+      tm_time_valid_i => tm_time_valid_i,
+      tm_tai_i        => tm_tai_i,
+      tm_cycles_i     => tm_cycles_i,
+      tag_tai_o       => reset_time_tai,
+      tag_cycles_o    => reset_time_cycles);
+
+  reset_time_tai_o    <= reset_time_tai;
+  reset_time_cycles_o <= reset_time_cycles;
+
+  -------------------------------------------------------------------------------------------
+  -- snapshot 
+  -------------------------------------------------------------------------------------------
+  -- snapshot is used to expose to user coherent value, so that the count for accumulated
+  -- latency is coherent with the accumulated latency and the average can be accurately 
+  -- calculated
+  -------------------------------------------------------------------------------------------
+  snapshot_ena <= snapshot_ena_i or snapshot_remote_ena;
+  -- snapshot
+
+  gen_tx_stats: if(g_streamers_op_mode=TX_ONLY OR g_streamers_op_mode=TX_AND_RX) generate
+    U_TX_STATS: xtx_streamers_stats
+      generic map (
+        g_cnt_width            => g_cnt_width
+        )
+      port map(
+        clk_i                  => clk_i,
+        rst_n_i                => rst_n_i,
+        sent_frame_i           => sent_frame_i,
+        reset_stats_i          => reset_stats,
+        snapshot_ena_i         => snapshot_ena,
+        sent_frame_cnt_o       => sent_frame_cnt_out);
+  end generate gen_tx_stats;
+  gen_not_tx_stats: if(g_streamers_op_mode=RX_ONLY) generate
+    sent_frame_cnt_out <= (others => '0');
+  end generate gen_not_tx_stats;
+
+  gen_rx_stats: if(g_streamers_op_mode=RX_ONLY OR g_streamers_op_mode=TX_AND_RX) generate
+    U_RX_STATS: xrx_streamers_stats
+      generic map(
+        g_cnt_width            => g_cnt_width,
+        g_acc_width            => g_acc_width
+        )
+      port map(
+        clk_i                  => clk_i,
+        rst_n_i                => rst_n_i,
+        rcvd_frame_i           => rcvd_frame_i,
+        lost_block_i           => lost_block_i,
+        lost_frame_i           => lost_frame_i,
+        lost_frames_cnt_i      => lost_frames_cnt_i,
+        rcvd_latency_i         => rcvd_latency_i,
+        rcvd_latency_valid_i   => rcvd_latency_valid_i,
+        tm_time_valid_i        => tm_time_valid_i,
+        snapshot_ena_i         => snapshot_ena,
+        reset_stats_i          => reset_stats,
+        rcvd_frame_cnt_o       => rcvd_frame_cnt_out,
+        lost_frame_cnt_o       => lost_frame_cnt_out,
+        lost_block_cnt_o       => lost_block_cnt_out,
+        latency_cnt_o          => latency_cnt_out,
+        latency_acc_overflow_o => latency_acc_overflow_out,
+        latency_acc_o          => latency_acc_out,
+        latency_max_o          => latency_max_out,
+        latency_min_o          => latency_min_out);
+  end generate gen_rx_stats;
+  gen_not_rx_stats: if(g_streamers_op_mode=TX_ONLY) generate
+    rcvd_frame_cnt_out       <= (others => '0');
+    lost_frame_cnt_out       <= (others => '0');
+    lost_block_cnt_out       <= (others => '0');
+    latency_cnt_out          <= (others => '0');
+    latency_acc_overflow_out <= '0';
+    latency_acc_out          <= (others => '0');
+    latency_max_out          <= (others => '0');
+    latency_min_out          <= (others => '0');
+  end generate gen_not_rx_stats;
+  -------------------------------------------------------------------------------------------
+  -- wishbone local output
+  -------------------------------------------------------------------------------------------
+  sent_frame_cnt_o         <= sent_frame_cnt_out;
+  rcvd_frame_cnt_o         <= rcvd_frame_cnt_out;
+  lost_frame_cnt_o         <= lost_frame_cnt_out;
+  lost_block_cnt_o         <= lost_block_cnt_out;
+  latency_max_o            <= latency_max_out;
+  latency_min_o            <= latency_min_out;
+  latency_acc_o            <= latency_acc_out;
+  latency_cnt_o            <= latency_cnt_out;
+  latency_acc_overflow_o   <= latency_acc_overflow_out;
+
+  -------------------------------------------------------------------------------------------
+  -- SNMP remote output
+  -- Generic communication with WRPC that allows SNMP access via generic array of 32-bits 
+  -- std_logic_vectors. The mapping of the generic vectors to meaningful information needs
+  -- to be made available to the user of SNMP
+  -------------------------------------------------------------------------------------------
+  -- check sanity of values
+  assert (c_cw <= 64) 
+    report "g_cnt_width value not suppported by f_pack_streamers_statistics" severity error;
+  assert (c_aw <= 64) 
+    report "g_acc_width value not suppported by f_pack_streamers_statistics" severity error;
+
+  -- translate generic input vectors to meaningful signals
+  reset_stats_remote                  <= snmp_array_i(0)(0);
+  snapshot_remote_ena                 <= snmp_array_i(0)(1);
+
+  snmp_array_o(0)(             0)     <= reset_stats;                   -- loop back for diagnostics
+  snmp_array_o(0)(             1)     <= latency_acc_overflow_out;
+  snmp_array_o(0) (31   downto 2)     <= (others => '0');
+
+  snmp_array_o(1)(   31 downto 0)     <= x"0" & reset_time_cycles( 27 downto 0);
+  snmp_array_o(2)(   31 downto 0)     <= reset_time_tai(    31 downto 0);
+  snmp_array_o(3)(   31 downto 0)     <= x"000000" & reset_time_tai(    39 downto 32);
+
+  -- translate meaningful signals (statistics values) to generic output vectors
+  snmp_array_o(4 )(31   downto 0)     <= x"0" & latency_max_out(27 downto 0);
+  snmp_array_o(5 )(31   downto 0)     <= x"0" & latency_min_out(27 downto 0); 
+
+  CNT_SINGLE_WORD_gen: if(c_cw < 33) generate
+    snmp_array_o(6 )(c_cw-1    downto       0) <= sent_frame_cnt_out;
+    snmp_array_o(6 )(31        downto    c_cw) <= (others => '0');
+    snmp_array_o(7 )(31        downto       0) <= (others => '0');
+
+    snmp_array_o(8 )(c_cw-1    downto       0) <= rcvd_frame_cnt_out;
+    snmp_array_o(8 )(31        downto    c_cw) <= (others => '0');
+    snmp_array_o(9 )(31        downto       0) <= (others => '0');
+
+    snmp_array_o(10)(c_cw-1    downto       0) <= lost_frame_cnt_out;
+    snmp_array_o(10)(31        downto    c_cw) <= (others => '0');
+    snmp_array_o(11)(31        downto       0) <= (others => '0');
+
+    snmp_array_o(12)(c_cw-1    downto       0) <= lost_block_cnt_out;
+    snmp_array_o(12)(31        downto    c_cw) <= (others => '0');
+    snmp_array_o(13)(31        downto       0) <= (others => '0');
+
+    snmp_array_o(14)(c_cw-1    downto       0) <= latency_cnt_out;
+    snmp_array_o(14)(31        downto    c_cw) <= (others => '0');
+    snmp_array_o(15)(31        downto       0) <= (others => '0');
+  end generate;
+  ACC_SINGLE_WORD_gen: if(c_aw < 33) generate
+    snmp_array_o(16)(c_aw-1    downto       0) <= latency_acc_out;
+    snmp_array_o(16)(31        downto    c_aw) <= (others => '0');
+    snmp_array_o(17)(31        downto       0) <= (others => '0');
+  end generate;
+
+  ---
+  CNT_TWO_WORDs_gen:  if(c_cw > 32)  generate
+    snmp_array_o(6 )(31        downto       0) <= sent_frame_cnt_out(31     downto 0);
+    snmp_array_o(7 )(c_cw-32-1 downto       0) <= sent_frame_cnt_out(c_cw-1 downto 32);
+    snmp_array_o(7 )(31        downto c_cw-32) <= (others => '0');
+
+    snmp_array_o(8 )(31        downto       0) <= rcvd_frame_cnt_out(31     downto 0);
+    snmp_array_o(9 )(c_cw-32-1 downto       0) <= rcvd_frame_cnt_out(c_cw-1 downto 32);
+    snmp_array_o(9 )(31        downto c_cw-32) <= (others => '0');
+
+    snmp_array_o(10)(31        downto       0) <= lost_frame_cnt_out(31     downto 0);
+    snmp_array_o(11)(c_cw-32-1 downto       0) <= lost_frame_cnt_out(c_cw-1 downto 32);
+    snmp_array_o(11 )(31       downto c_cw-32) <= (others => '0');
+
+    snmp_array_o(12)(31        downto       0) <= lost_block_cnt_out(31     downto 0);
+    snmp_array_o(13)(c_cw-32-1 downto       0) <= lost_block_cnt_out(c_cw-1 downto 32);
+    snmp_array_o(13 )(31       downto c_cw-32) <= (others => '0');
+
+    snmp_array_o(14)(31        downto       0) <= latency_cnt_out(31     downto 0);
+    snmp_array_o(15)(c_cw-32-1 downto       0) <= latency_cnt_out(c_cw-1 downto 32);
+    snmp_array_o(15 )(31       downto c_cw-32) <= (others => '0');
+  end generate;
+  ACC_TWO_WORDs_gen:   if(c_aw > 32) generate
+    snmp_array_o(16)(31        downto       0) <= latency_acc_out(31     downto 0);
+    snmp_array_o(17)(c_aw-32-1 downto       0) <= latency_acc_out(c_aw-1 downto 32) ;
+    snmp_array_o(17)(31        downto c_aw-32) <= (others => '0'); 
+  end generate;
+
+end rtl;
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/xrx_streamer.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/xrx_streamer.vhd
new file mode 100644
index 000000000..e135c0b08
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/xrx_streamer.vhd
@@ -0,0 +1,677 @@
+-------------------------------------------------------------------------------
+-- Title      : Transmission Streamer
+-- Project    : WR Streamers
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/WR_Streamers
+-------------------------------------------------------------------------------
+-- File       : xrx_streamer.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2012-11-02
+-- Platform   : FPGA-generic
+-- Standard   : VHDL
+-------------------------------------------------------------------------------
+-- Description: A simple core demonstrating how to encapsulate a continuous
+-- stream of data words into Ethernet frames, in a format that is accepted by
+-- the White Rabbit PTP core. This core decodes Ethernet frames encoded by
+-- xtx_streamer. More info in the documentation.
+-------------------------------------------------------------------------------
+-- Copyright (c) 2012-2017 CERN/BE-CO-HT
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.wishbone_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.gencores_pkg.all;
+use work.genram_pkg.all;
+use work.streamers_priv_pkg.all;
+use work.streamers_pkg.all;
+
+entity xrx_streamer is
+  
+  generic (
+    -- Width of the data words, must be multiple of 16 bits. This value set to this generic
+    -- on the receviving device must be the same as the value of g_tx_data_width set on the
+    -- transmitting node. The g_rx_data_width and g_tx_data_width can be set to different
+    -- values in the same device (i.e. instantiation of xwr_transmission entity). It is the
+    -- responsibility of a network designer to make sure these parameters are properly set 
+    -- in the network.
+    g_data_width        : integer := 32;
+
+    -- Size of RX buffer, in data words.
+    g_buffer_size       : integer := 256;
+
+    -- DO NOT USE unless you know what you are doing
+    -- legacy: the streamers that were initially used in Btrain did not check/insert 
+    -- the escape code. This is justified if only one block of a known number of words is 
+    -- sent/expected.
+    g_escape_code_disable : boolean := FALSE;
+
+    -- DO NOT USE unless you know what you are doing
+    -- legacy: the streamers that were initially used in Btrain accepted only a fixed
+    -- number of words, regardless of the frame content. If this generic is set to number
+    -- other than zero, only a fixed number of words is accepted. 
+    -- In combination with the g_escape_code_disable generic set to TRUE, the behaviour of
+    -- the "Btrain streamers" can be recreated.
+    g_expected_words_number : integer := 0
+    );
+
+  port (
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    -- Endpoint/WRC interface 
+    snk_i : in  t_wrf_sink_in;
+    snk_o : out t_wrf_sink_out;
+
+    ---------------------------------------------------------------------------
+    -- WRC Timing interface, used for latency measurement
+    -- Caution: uses clk_ref_i clock domain!
+    ---------------------------------------------------------------------------
+
+    -- White Rabbit reference clock
+    clk_ref_i : in std_logic := '0';
+
+    -- Time valid flag
+    tm_time_valid_i : in std_logic := '0';
+
+    -- TAI seconds
+    tm_tai_i : in std_logic_vector(39 downto 0) := x"0000000000";
+
+    -- Fractional part of the second (in clk_ref_i cycles)
+    tm_cycles_i : in std_logic_vector(27 downto 0) := x"0000000";
+
+    ---------------------------------------------------------------------------
+    -- User interface
+    ---------------------------------------------------------------------------
+
+    -- 1 indicates the 1st word of the data block on rx_data_o.
+    rx_first_p1_o         : out std_logic;
+    -- 1 indicates the last word of the data block on rx_data_o.
+    rx_last_p1_o          : out std_logic;
+    -- Received data.
+    rx_data_o          : out std_logic_vector(g_data_width-1 downto 0);
+    -- 1 indicted that rx_data_o is outputting a valid data word.
+    rx_valid_o         : out std_logic;
+    -- Synchronous data request input: when 1, the streamer may output another
+    -- data word in the subsequent clock cycle.
+    rx_dreq_i          : in  std_logic;
+    -- Lost output: 1 indicates that one or more frames or blocks have been lost
+    -- (left for backward compatibility).
+    rx_lost_p1_o          : out std_logic := '0';
+    -- indicates that one or more blocks within frame are missing
+    rx_lost_blocks_p1_o    :  out std_logic := '0';
+    -- indicates that one or more frames are missing, the number of frames is provied
+    rx_lost_frames_p1_o    :  out std_logic := '0';
+    --number of lost frames, the 0xF...F means that counter overflew
+    rx_lost_frames_cnt_o : out std_logic_vector(14 downto 0);
+    -- Latency measurement output: indicates the transport latency (between the
+    -- TX streamer in remote device and this streamer), in clk_ref_i clock cycles.
+    rx_latency_o       : out std_logic_vector(27 downto 0);
+    -- 1 when the latency on rx_latency_o is valid.
+    rx_latency_valid_o : out std_logic;
+    -- received 	streamer frame (counts all frames, corrupted and not)
+    rx_frame_p1_o         : out std_logic;
+    -- configuration
+    rx_streamer_cfg_i     : in t_rx_streamer_cfg := c_rx_streamer_cfg_default
+    );
+
+end xrx_streamer;
+
+architecture rtl of xrx_streamer is
+
+  type t_rx_state is (IDLE, HEADER, FRAME_SEQ_ID, PAYLOAD, SUBFRAME_HEADER, EOF);
+
+  signal fab, fsm_in : t_pipe;
+
+  signal state : t_rx_state;
+
+  signal ser_count : unsigned(7 downto 0);
+  signal seq_no, seq_new,count  : unsigned(14 downto 0);
+
+  signal crc_match, crc_en, crc_en_masked, crc_restart : std_logic;
+
+  signal detect_escapes, is_escape : std_logic;
+  signal rx_pending                : std_logic;
+
+  signal pack_data, fifo_data : std_logic_vector(g_data_width-1 downto 0);
+
+  signal fifo_drop, fifo_accept, fifo_accept_d0, fifo_dvalid : std_logic;
+  signal fifo_sync, fifo_last, frames_lost, blocks_lost      : std_logic;
+  signal fifo_dout, fifo_din                                 : std_logic_vector(g_data_width + 1 downto 0);
+
+  signal pending_write, fab_dvalid_pre : std_logic;
+
+
+  signal tx_tag_cycles, rx_tag_cycles : std_logic_vector(27 downto 0);
+  signal tx_tag_valid, rx_tag_valid   : std_logic;
+
+  signal got_next_subframe : std_logic;
+  signal is_frame_seq_id : std_logic;
+  signal word_count                                                        : unsigned(11 downto 0);
+  signal sync_seq_no : std_logic;
+
+  -- fixed latency signals
+  type   t_rx_delay_state is (DISABLED, DELAY, ALLOW);
+  signal timestamped        : std_logic;
+  signal delay_cnt          : unsigned(27 downto 0);
+  signal rx_dreq_allow      : std_logic;
+  signal rx_latency         : unsigned(27 downto 0);
+  signal rx_latency_stored  : unsigned(27 downto 0);
+  signal rx_latency_valid   : std_logic;
+  signal delay_state        : t_rx_delay_state;
+  signal rx_dreq            : std_logic;
+  signal is_vlan            : std_logic;
+
+  constant c_fixed_latency_zero : unsigned(27 downto 0) := (others => '0');
+  constant c_timestamper_delay  : unsigned(27 downto 0) := to_unsigned(12, 28); -- cycles
+  
+begin  -- rtl
+
+  U_rx_crc_generator : gc_crc_gen
+    generic map (
+      g_polynomial              => x"1021",
+      g_init_value              => x"ffff",
+      g_residue                 => x"470f",
+      g_data_width              => 16,
+      g_sync_reset              => 1,
+      g_dual_width              => 0,
+      g_registered_match_output => true)
+    port map (
+      clk_i     => clk_sys_i,
+      rst_i     => '0',
+      restart_i => crc_restart,
+      en_i      => crc_en_masked,
+      data_i    => fsm_in.data,
+      half_i    => '0',
+      match_o   => crc_match);
+
+  crc_en_masked <= crc_en and fsm_in.dvalid;
+
+  U_Fabric_Sink : xwb_fabric_sink
+    port map (
+      clk_i     => clk_sys_i,
+      rst_n_i   => rst_n_i,
+      snk_i     => snk_i,
+      snk_o     => snk_o,
+      addr_o    => fab.addr,
+      data_o    => fab.data,
+      dvalid_o  => fab_dvalid_pre,
+      sof_o     => fab.sof,
+      eof_o     => fab.eof,
+      error_o   => fab.error,
+      bytesel_o => fab.bytesel,
+      dreq_i    => fab.dreq);
+
+  fab.dvalid <= '1' when fab_dvalid_pre = '1' and fab.addr = c_WRF_DATA and fab.bytesel = '0' else '0';
+  gen_escape: if (g_escape_code_disable = FALSE) generate
+    U_Escape_Detect : escape_detector
+      generic map (
+        g_data_width  => 16,
+        g_escape_code => x"cafe")
+      port map (
+        clk_i             => clk_sys_i,
+        rst_n_i           => rst_n_i,
+        d_i               => fab.data,
+        d_detect_enable_i => detect_escapes,
+        d_valid_i         => fab.dvalid,
+        d_req_o           => fab.dreq,
+        d_o               => fsm_in.data,
+        d_escape_o        => is_escape,
+        d_valid_o         => fsm_in.dvalid,
+        d_req_i           => fsm_in.dreq);
+  end generate gen_escape;
+  gen_no_escape: if (g_escape_code_disable = TRUE) generate
+    fsm_in.dvalid <= fab.dvalid;
+    fsm_in.data   <= fab.data;
+    fab.dreq      <= fsm_in.dreq;
+    is_escape     <= '0';
+  end generate gen_no_escape;
+  fsm_in.eof <= fab.eof or fab.error;
+  fsm_in.sof <= fab.sof;
+
+
+  U_Output_FIFO : dropping_buffer
+    generic map (
+      g_size       => g_buffer_size,
+      g_data_width => g_data_width + 2)
+    port map (
+      clk_i      => clk_sys_i,
+      rst_n_i    => rst_n_i,
+      d_i        => fifo_din,
+      d_req_o    => fsm_in.dreq,
+      d_drop_i   => fifo_drop,
+      d_accept_i => fifo_accept_d0,
+      d_valid_i  => fifo_dvalid,
+      d_o        => fifo_dout,
+      d_valid_o  => rx_valid_o,
+      d_req_i    => rx_dreq);
+
+  fifo_din(g_data_width+1)          <= fifo_sync;
+  fifo_din(g_data_width)            <= fifo_last or 
+                                        ((not pending_write) and is_escape); -- when word is 16 bits
+  fifo_din(g_data_width-1 downto 0) <= fifo_data;
+
+  rx_data_o  <= fifo_dout(g_data_width-1 downto 0);
+  rx_first_p1_o <= fifo_dout(g_data_width+1);
+  rx_last_p1_o  <= fifo_dout(g_data_width);
+
+  U_RX_Timestamper : pulse_stamper
+    port map (
+      clk_ref_i       => clk_ref_i,
+      clk_sys_i       => clk_sys_i,
+      rst_n_i         => rst_n_i,
+      pulse_a_i       => fsm_in.sof,
+      tm_time_valid_i => tm_time_valid_i,
+      tm_tai_i        => tm_tai_i,
+      tm_cycles_i     => tm_cycles_i,
+      tag_cycles_o    => rx_tag_cycles);
+
+  -------------------------------------------------------------------------------------------
+  -- fixed latency implementation
+  -------------------------------------------------------------------------------------------
+
+  -- mask rx_dreq to prevent reception
+  rx_dreq                           <= rx_dreq_i and rx_dreq_allow;
+  -- produce a pulse when SOF is timestamped, this pulse starts counter in clk_sys clock 
+  -- domain
+  U_sync_with_clk : gc_sync_ffs
+    port map (
+      clk_i          => clk_sys_i,
+      rst_n_i        => rst_n_i,
+      data_i         => fsm_in.sof,
+      synced_o       => timestamped);
+
+  -- introduce fixed latency, if configured to do so
+  p_fixed_latency_fsm : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        delay_state        <= DISABLED;
+        rx_latency_stored  <= (others=>'0');
+        rx_dreq_allow      <= '1';
+        delay_cnt          <= c_timestamper_delay;
+      else
+        case delay_state is
+          when DISABLED => 
+            if unsigned(rx_streamer_cfg_i.fixed_latency) /= c_fixed_latency_zero then
+              delay_state        <= ALLOW;
+            end if;
+            rx_latency_stored  <= (others=>'0');
+            delay_cnt          <= c_timestamper_delay;
+            rx_dreq_allow      <= '1';
+          when ALLOW =>
+            if unsigned(rx_streamer_cfg_i.fixed_latency) = c_fixed_latency_zero then
+              delay_state        <= DISABLED;
+            elsif(rx_latency_valid ='1') then
+              rx_dreq_allow     <= '0';
+              rx_latency_stored <= rx_latency;
+              delay_state       <= DELAY;
+            end if;
+            if(timestamped = '1') then
+              delay_cnt         <= c_timestamper_delay;
+            else
+              delay_cnt <= delay_cnt + 2;
+            end if;
+          when DELAY =>
+            if unsigned(rx_streamer_cfg_i.fixed_latency) <= delay_cnt + rx_latency_stored then
+              rx_latency_stored  <= (others=>'0');
+              rx_dreq_allow      <= '1';
+              delay_state        <= ALLOW;
+            else
+              delay_cnt <= delay_cnt + 2;
+            end if;
+        end case;
+      end if;
+    end if;
+  end process;
+
+  -------------------------------------------------------------------------------------------
+  -- end of fixed latency implementation
+  -- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+  p_fsm : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        state                  <= IDLE;
+        count                  <= (others => '0');
+        seq_no                 <= (others => '1');
+        detect_escapes         <= '0';
+        crc_en                 <= '0';
+        fifo_accept            <= '0';
+        fifo_drop              <= '0';
+        fifo_dvalid            <= '0';
+        pending_write          <= '0';
+        got_next_subframe      <= '0';
+        fifo_sync              <= '0';
+        fifo_last              <= '0';
+        tx_tag_valid           <= '0';
+        ser_count              <= (others => '0');
+        word_count             <= (others => '0');
+        sync_seq_no            <= '1';
+        rx_frame_p1_o          <= '0';
+        rx_lost_frames_cnt_o   <= (others => '0');
+        frames_lost            <= '0';
+        rx_latency             <= (others=>'0');
+        rx_latency_valid       <= '0';
+        blocks_lost            <= '0';
+        pack_data              <= (others=>'0');
+        is_vlan                <= '0';
+      else
+        case state is
+          when IDLE =>
+            detect_escapes     <= '0';
+            crc_en             <= '0';
+            count              <= (others => '0');
+            fifo_accept        <= '0';
+            fifo_drop          <= '0';
+            fifo_dvalid        <= '0';
+            pending_write      <= '0';
+            got_next_subframe  <='0';
+            ser_count          <= (others => '0');
+            fifo_sync          <='0';
+            fifo_last          <= '0';
+            word_count         <= (others => '0');
+            tx_tag_valid       <= '0';
+            rx_frame_p1_o      <= '0';
+            rx_lost_frames_cnt_o <= (others => '0');
+            frames_lost          <= '0';
+            blocks_lost          <= '0';
+            rx_latency           <= (others=>'0');
+            rx_latency_valid     <= '0';
+            is_vlan              <= '0';
+
+            if(fsm_in.sof = '1') then
+              state            <= HEADER;
+            end if;
+
+          when HEADER =>
+            if(fsm_in.eof = '1') then
+              state <= IDLE;
+            elsif(fsm_in.dvalid = '1') then
+              case count(7 downto 0) is
+                when x"00" =>
+                  if(fsm_in.data /= rx_streamer_cfg_i.mac_local(47 downto 32) nor (rx_streamer_cfg_i.accept_broadcasts = '1' and fsm_in.data /= x"ffff")) then
+                    state <= IDLE;
+                  end if;
+                  count <= count + 1;
+                when x"01" =>
+                  if(fsm_in.data /= rx_streamer_cfg_i.mac_local(31 downto 16) nor (rx_streamer_cfg_i.accept_broadcasts = '1' and fsm_in.data /= x"ffff")) then
+                    state <= IDLE;
+                  end if;
+                  count <= count + 1;
+                when x"02" =>
+                  if(fsm_in.data /= rx_streamer_cfg_i.mac_local(15 downto 0) nor (rx_streamer_cfg_i.accept_broadcasts = '1' and fsm_in.data /= x"ffff")) then
+                    state <= IDLE;
+                  end if;
+                  count <= count + 1;
+                when x"03" =>
+                  if(fsm_in.data /= rx_streamer_cfg_i.mac_remote(47 downto 32) and rx_streamer_cfg_i.filter_remote ='1') then
+                    state <= IDLE;
+                  end if;
+                  count <= count + 1;
+                when x"04" =>
+                  if(fsm_in.data /= rx_streamer_cfg_i.mac_remote(31 downto 16) and rx_streamer_cfg_i.filter_remote ='1') then
+                    state <= IDLE;
+                  end if;
+                  count <= count + 1;
+                when x"05" =>
+                  if(fsm_in.data /= rx_streamer_cfg_i.mac_remote(15 downto 0) and rx_streamer_cfg_i.filter_remote ='1') then
+                    state <= IDLE;
+                  end if;
+                  count <= count + 1;
+                when x"06" =>
+                  if(fsm_in.data = x"8100") then
+                    is_vlan <='1';
+                  elsif(fsm_in.data /= rx_streamer_cfg_i.ethertype) then
+                    state   <= IDLE;
+                    is_vlan <='0';
+                  end if;
+                  count <= count + 1;
+                when x"07" =>
+                  if(is_vlan = '0') then
+                    tx_tag_valid               <= fsm_in.data(15);
+                    tx_tag_cycles(27 downto 16)<= fsm_in.data(11 downto 0);
+                  end if;
+                  count <= count + 1;
+                when x"08" =>
+                  if(is_vlan = '0') then
+                    tx_tag_cycles(15 downto 0) <= fsm_in.data;
+                    count                      <= count + 1;
+                    crc_en                     <= '1';
+                    detect_escapes             <= '1';
+                    state                      <= FRAME_SEQ_ID;
+                    rx_frame_p1_o              <= '1';
+                  elsif(fsm_in.data /= rx_streamer_cfg_i.ethertype) then
+                    state <= IDLE;
+                  end if;
+                  count <= count + 1;
+                when x"09" =>
+                  tx_tag_valid               <= fsm_in.data(15);
+                  tx_tag_cycles(27 downto 16)<= fsm_in.data(11 downto 0);
+                   count <= count + 1;
+                when x"0A" =>
+                  tx_tag_cycles(15 downto 0) <= fsm_in.data;
+                  count                      <= count + 1;
+                  crc_en                     <= '1';
+                  detect_escapes             <= '1';
+                  state                      <= FRAME_SEQ_ID;
+                  rx_frame_p1_o              <= '1';
+                  count <= count + 1;
+                when others => null;
+              end case;
+            end if;
+
+          when FRAME_SEQ_ID =>
+            rx_frame_p1_o            <= '0';
+            if(fsm_in.eof = '1') then
+              state <= IDLE;
+            elsif(fsm_in.dvalid = '1') then
+              count               <= "000" & x"001"; -- use as subframe seq_no
+              state               <= PAYLOAD;
+              fifo_drop           <= '0';
+              fifo_accept         <= '0';
+              ser_count           <= (others => '0');
+              word_count          <= word_count + 1; -- count words, increment in advance
+              got_next_subframe   <= '1';
+              if(tx_tag_valid = '1') then
+                rx_latency_valid <= '1';
+                if(unsigned(tx_tag_cycles) > unsigned(rx_tag_cycles)) then
+                  rx_latency <= unsigned(rx_tag_cycles) - unsigned(tx_tag_cycles) + to_unsigned(125000000, 28);
+                else
+                  rx_latency <= unsigned(rx_tag_cycles) - unsigned(tx_tag_cycles);
+                end if;
+                tx_tag_valid <= '0';
+              else
+                rx_latency_valid <= '0';
+              end if;
+
+              if(std_logic_vector(seq_no) /= fsm_in.data(14 downto 0)) then
+                seq_no    <= unsigned(fsm_in.data(14 downto 0))+1;
+                if (sync_seq_no = '1') then -- sync to the first received seq_no
+                  sync_seq_no <= '0';
+                  frames_lost   <= '0';
+                  rx_lost_frames_cnt_o <= (others => '0');
+                else
+                  rx_lost_frames_cnt_o <= std_logic_vector(unsigned(fsm_in.data(14 downto 0)) - seq_no);
+                  frames_lost     <= '1';
+                end if;
+              else
+                seq_no    <= unsigned(seq_no + 1);
+                frames_lost <= '0';
+                rx_lost_frames_cnt_o <= (others => '0');
+              end if;
+            end if;
+
+          when SUBFRAME_HEADER =>
+            fifo_drop   <= '0';
+            fifo_accept <= '0';
+            ser_count <= (others => '0');
+
+            if(fsm_in.eof = '1') then
+              state <= IDLE;
+              got_next_subframe <= '0';
+              blocks_lost <= '0';
+            elsif (fsm_in.dvalid = '1' and is_escape = '1') then
+              got_next_subframe <= '1';
+
+              if(std_logic_vector(count) /= fsm_in.data(14 downto 0)) then
+                count     <= unsigned(fsm_in.data(14 downto 0))+1;
+                blocks_lost <= '1';
+              else
+                count    <= count + 1;
+                blocks_lost <= '0';
+              end if;
+              state <= PAYLOAD;
+            end if;
+
+          when PAYLOAD =>
+            frames_lost <= '0';
+            rx_lost_frames_cnt_o <= (others => '0');
+            rx_latency_valid <= '0';
+            fifo_sync <= got_next_subframe;
+
+            if(fsm_in.eof = '1') then
+              state       <= IDLE;
+              fifo_drop   <= '1';
+              fifo_accept <= '0';
+              got_next_subframe <= '0';
+              
+            elsif(fsm_in.dvalid = '1') then
+
+              
+              
+              if(is_escape = '1') then
+                ser_count <= (others => '0');
+                fifo_last <= '1';
+
+                got_next_subframe <= '1';
+
+                if(fsm_in.data(15) = '1') then
+                  
+                  if(std_logic_vector(count) /= fsm_in.data(14 downto 0)) then
+                    count     <= unsigned(fsm_in.data(14 downto 0));
+                    blocks_lost <= '1';
+                  else
+                    count     <= unsigned(count + 1);
+                    blocks_lost <= '0';
+                  end if;
+                  
+                  state <= PAYLOAD;
+
+                  fifo_accept   <= crc_match;      --_latched;
+                  fifo_drop     <= not crc_match;  --_latched;
+                  fifo_dvalid   <= pending_write and not fifo_dvalid;
+                  pending_write <= '0';
+                  
+                elsif fsm_in.data = x"0bad" then
+                  blocks_lost   <= '0';
+                  state       <= EOF;
+                  fifo_accept <= crc_match;      --_latched;
+                  fifo_drop   <= not crc_match;  --_latched;
+                  fifo_dvalid <= pending_write and not fifo_dvalid;
+                else
+                  blocks_lost   <= '0';
+                  state       <= EOF;
+                  fifo_drop   <= '1';
+                  fifo_accept <= '0';
+                end if;
+
+              else --of:  if(is_escape = '1' or word_count = g_expected_words_number) then
+
+                fifo_last   <= '0';
+                fifo_accept <= '0';
+                fifo_drop   <= '0';
+                blocks_lost   <= '0';
+
+                pack_data(to_integer(ser_count) * 16 + 15 downto to_integer(ser_count) * 16) <= fsm_in.data;
+
+                if(ser_count = g_data_width/16 - 1) then
+                  ser_count                                        <= (others => '0');
+
+                  if (ser_count = x"00") then -- ML: the case when g_data_width == 16
+                     fifo_sync <= got_next_subframe;
+                     fifo_data(g_data_width-1 downto 0)            <= pack_data(g_data_width-1 downto 0);
+                     fifo_dvalid <= not is_escape;
+                     pending_write <= '0';
+                  else
+                    ser_count                                        <= (others => '0');
+                    fifo_data(g_data_width-16-1 downto 0)            <= pack_data(g_data_width-16-1 downto 0);
+                    fifo_data(g_data_width-1 downto g_data_width-16) <= fsm_in.data;
+                    fifo_dvalid                                      <= '0';
+                    pending_write                                    <= '1';
+                  end if;
+                  if(word_count = g_expected_words_number) then
+                    state       <= EOF;
+                    fifo_accept <= '1'; 
+                    fifo_drop   <= '0'; 
+                    fifo_dvalid <= '1';
+                  else
+                    word_count <= word_count + 1;
+                  end if;
+                elsif(ser_count = g_data_width/16-2 and pending_write = '1') then
+                  pending_write <= '0';
+                  ser_count     <= ser_count + 1;
+                  fifo_dvalid   <= '1';
+                  fifo_sync <= got_next_subframe;
+                  got_next_subframe <= '0';
+                else
+                  ser_count   <= ser_count + 1;
+                  fifo_dvalid <= '0';
+                end if;
+                
+              end if;
+            else --of:  elsif(fsm_in.dvalid = '1') then
+              fifo_dvalid <= '0';
+            end if;
+
+            if(fifo_dvalid = '1') then
+              fifo_sync <= '0';
+            end if;
+            
+
+          when EOF =>
+            fifo_dvalid <= '0';
+            fifo_drop   <= '0';
+            fifo_accept <= '0';
+            state       <= IDLE;
+            
+        end case;
+      end if;
+    end if;
+  end process;
+
+  p_delay_fifo_accept : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      fifo_accept_d0 <= fifo_accept;
+    end if;
+  end process;
+
+  rx_lost_p1_o        <= frames_lost or blocks_lost;
+  rx_lost_blocks_p1_o <= blocks_lost;
+  rx_lost_frames_p1_o <= frames_lost;
+  rx_latency_o        <= std_logic_vector(rx_latency);
+  rx_latency_valid_o  <= rx_latency_valid;
+  crc_restart <= '1' when (state = FRAME_SEQ_ID or (is_escape = '1' and fsm_in.data(15) = '1')) else not rst_n_i;
+
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/xrx_streamers_stats.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/xrx_streamers_stats.vhd
new file mode 100644
index 000000000..d2257ce57
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/xrx_streamers_stats.vhd
@@ -0,0 +1,231 @@
+-------------------------------------------------------------------------------
+-- Title      : WR Recpetion Streamers statistics
+-- Project    : White Rabbit Streamers
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/WR_Streamers
+-------------------------------------------------------------------------------
+-- File       : xrx_streamers_stats.vhd
+-- Author     : Maciej Lipinski
+-- Company    : CERN
+-- Created    : 2017-04-19
+-- Platform   : FPGA-generics
+-- Standard   : VHDL
+-------------------------------------------------------------------------------
+-- Description:
+-- This module provies the reception portion of statistics and
+-- allows to snapshot their values. See xrtx_streamers_stats for
+-- more detailed description.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2016 CERN/BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+---------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+library work;
+use work.wishbone_pkg.all;  -- needed for t_wishbone_slave_in, etc
+use work.streamers_pkg.all; -- needed for streamers
+use work.wr_fabric_pkg.all; -- neede for :t_wrf_source_in, etc
+use work.wrcore_pkg.all;    -- needed for t_generic_word_array
+-- use work.wr_transmission_wbgen2_pkg.all;
+
+entity xrx_streamers_stats is
+  
+  generic (
+    -- Width of frame counters
+    g_cnt_width            : integer := 50; -- min:15, max:64, 50 bits should be ok for 50 years
+    g_acc_width            : integer := 64  -- max value 64
+    );
+  port (
+    clk_i                  : in std_logic;
+    rst_n_i                : in std_logic;
+
+    -- input signals from streamers
+    rcvd_frame_i           : in std_logic;
+    lost_block_i           : in std_logic;
+    lost_frame_i           : in std_logic;
+    lost_frames_cnt_i      : in std_logic_vector(14 downto 0);
+    rcvd_latency_i         : in  std_logic_vector(27 downto 0);
+    rcvd_latency_valid_i   : in  std_logic;
+    tm_time_valid_i        : in  std_logic;
+
+    snapshot_ena_i         : in std_logic := '0';
+    reset_stats_i          : in std_logic;
+    ----------------------- statistics ----------------------------------------
+    -- output statistics: tx/rx counters
+    rcvd_frame_cnt_o       : out std_logic_vector(g_cnt_width-1 downto 0);
+    lost_frame_cnt_o       : out std_logic_vector(g_cnt_width-1 downto 0);
+    lost_block_cnt_o       : out std_logic_vector(g_cnt_width-1 downto 0);
+    -- output statistics: latency
+    latency_cnt_o          : out std_logic_vector(g_cnt_width-1 downto 0);
+    latency_acc_overflow_o : out std_logic;
+    latency_acc_o          : out std_logic_vector(g_acc_width-1  downto 0);
+    latency_max_o          : out std_logic_vector(27  downto 0);
+    latency_min_o          : out std_logic_vector(27  downto 0)
+    );
+
+end xrx_streamers_stats;
+  
+architecture rtl of xrx_streamers_stats is
+
+
+  signal rcvd_frame_cnt    : unsigned(g_cnt_width-1  downto 0);
+  signal lost_frame_cnt    : unsigned(g_cnt_width-1  downto 0);
+  signal lost_block_cnt    : unsigned(g_cnt_width-1  downto 0);
+  signal latency_cnt       : unsigned(g_cnt_width-1  downto 0);
+
+  signal latency_max       : std_logic_vector(27  downto 0);
+  signal latency_min       : std_logic_vector(27  downto 0);
+  signal latency_acc       : unsigned(g_acc_width-1+1  downto 0);
+  signal latency_acc_overflow: std_logic;
+
+  -- snaphsot
+  signal rcvd_frame_cnt_d1    : unsigned(g_cnt_width-1  downto 0);
+  signal lost_frame_cnt_d1    : unsigned(g_cnt_width-1  downto 0);
+  signal lost_block_cnt_d1    : unsigned(g_cnt_width-1  downto 0);
+  signal latency_cnt_d1       : unsigned(g_cnt_width-1  downto 0);
+
+  signal latency_max_d1       : std_logic_vector(27  downto 0);
+  signal latency_min_d1       : std_logic_vector(27  downto 0);
+  signal latency_acc_d1       : unsigned(g_acc_width-1+1  downto 0);
+  signal latency_acc_overflow_d1: std_logic;
+
+  signal snapshot_ena_d1   : std_logic;
+
+begin
+
+  -------------------------------------------------------------------------------------------
+  -- frame/block statistics, i.e. lost, sent, received
+  -------------------------------------------------------------------------------------------
+  -- process that counts: receved/lost frames
+  p_cnts: process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if (rst_n_i = '0' or reset_stats_i = '1') then
+        rcvd_frame_cnt        <= (others => '0');
+        lost_frame_cnt        <= (others => '0');
+        lost_block_cnt        <= (others => '0');
+      else
+        -- count received frames
+        if(rcvd_frame_i = '1') then
+          rcvd_frame_cnt <= rcvd_frame_cnt + 1;
+        end if;
+        -- count lost frames
+        if(lost_frame_i = '1') then
+          lost_frame_cnt <= lost_frame_cnt + resize(unsigned(lost_frames_cnt_i),lost_frame_cnt'length);
+        end if;
+        -- count lost blocks
+        if(lost_block_i = '1') then
+          lost_block_cnt <= lost_block_cnt + 1;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  -------------------------------------------------------------------------------------------
+  -- latency statistics
+  -------------------------------------------------------------------------------------------
+  p_latency_stats: process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if (rst_n_i = '0' or reset_stats_i = '1') then
+        latency_max            <= (others => '0');
+        latency_min            <= (others => '1');
+        latency_acc            <= (others => '0');
+        latency_cnt            <= (others => '0');
+        latency_acc_overflow   <= '0';
+      else
+        if(rcvd_latency_valid_i = '1' and tm_time_valid_i = '1') then
+          if(latency_max < rcvd_latency_i) then
+            latency_max <= rcvd_latency_i;
+          end if;
+          if(latency_min > rcvd_latency_i) then
+            latency_min <= rcvd_latency_i;
+          end if;
+          if(latency_acc(g_acc_width) ='1') then
+            latency_acc_overflow   <= '1';
+          end if;
+          latency_cnt <= latency_cnt + 1;
+          latency_acc <= latency_acc + resize(unsigned(rcvd_latency_i),latency_acc'length);
+        end if;
+      end if;
+    end if;
+  end process;
+
+  -------------------------------------------------------------------------------------------
+  -- snapshot 
+  -------------------------------------------------------------------------------------------
+  -- snapshot is used to expose to user coherent value, so that the count for accumulated
+  -- latency is coherent with the accumulated latency and the average can be accurately 
+  -- calculated
+  -------------------------------------------------------------------------------------------
+
+  -- snapshot
+  p_stats_snapshot: process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if (rst_n_i = '0') then
+         snapshot_ena_d1         <= '0';
+         rcvd_frame_cnt_d1       <= (others=>'0');
+         lost_frame_cnt_d1       <= (others=>'0');
+         lost_block_cnt_d1       <= (others=>'0');
+         latency_cnt_d1          <= (others=>'0');
+
+         latency_max_d1          <= (others=>'0');
+         latency_min_d1          <= (others=>'0');
+         latency_acc_d1          <= (others=>'0');
+         latency_acc_overflow_d1 <= '0';
+      else
+        if(snapshot_ena_i = '1' and snapshot_ena_d1 = '0') then
+         rcvd_frame_cnt_d1       <= rcvd_frame_cnt;
+         lost_frame_cnt_d1       <= lost_frame_cnt;
+         lost_block_cnt_d1       <= lost_block_cnt;
+         latency_cnt_d1          <= latency_cnt;
+
+         latency_max_d1          <= latency_max;
+         latency_min_d1          <= latency_min;
+         latency_acc_d1          <= latency_acc;
+         latency_acc_overflow_d1 <= latency_acc_overflow;
+        end if;
+        snapshot_ena_d1 <= snapshot_ena_i;
+      end if;
+    end if;
+  end process;
+
+  -------------------------------------------------------------------------------------------
+  -- snapshot or current value
+  -------------------------------------------------------------------------------------------
+  rcvd_frame_cnt_o       <= std_logic_vector(rcvd_frame_cnt_d1) when (snapshot_ena_d1 = '1') else
+                            std_logic_vector(rcvd_frame_cnt);
+  lost_frame_cnt_o       <= std_logic_vector(lost_frame_cnt_d1) when (snapshot_ena_d1 = '1') else
+                            std_logic_vector(lost_frame_cnt);
+  lost_block_cnt_o       <= std_logic_vector(lost_block_cnt_d1) when (snapshot_ena_d1 = '1') else
+                            std_logic_vector(lost_block_cnt);
+  latency_max_o          <= latency_max_d1 when (snapshot_ena_d1 = '1') else
+                            latency_max;
+  latency_min_o          <= latency_min_d1 when (snapshot_ena_d1 = '1') else
+                            latency_min;
+  latency_acc_o          <= std_logic_vector(latency_acc_d1(g_acc_width-1 downto 0)) when (snapshot_ena_d1 = '1') else
+                            std_logic_vector(latency_acc(g_acc_width-1 downto 0));
+  latency_cnt_o          <= std_logic_vector(latency_cnt_d1) when (snapshot_ena_d1 = '1') else
+                            std_logic_vector(latency_cnt);
+  latency_acc_overflow_o <= latency_acc_overflow_d1  when (snapshot_ena_d1 = '1') else
+                            latency_acc_overflow;
+
+end rtl;
\ No newline at end of file
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/xtx_streamer.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/xtx_streamer.vhd
new file mode 100644
index 000000000..fea78ab7e
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/xtx_streamer.vhd
@@ -0,0 +1,597 @@
+-------------------------------------------------------------------------------
+-- Title      : Reception streamer
+-- Project    : WR streamers
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/WR_Streamers
+-------------------------------------------------------------------------------
+-- File       : xtx_streamer.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2012-11-02
+-- Platform   : FPGA-generic
+-- Standard   : VHDL
+-------------------------------------------------------------------------------
+-- Description: A simple core demonstrating how to encapsulate a continuous
+-- stream of data words into Ethernet frames, in a format that is accepted by
+-- the White Rabbit PTP core. More info in the documentation.
+-------------------------------------------------------------------------------
+-- Copyright (c) 2012-2017 CERN/BE-CO-HT
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.wishbone_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.gencores_pkg.all;
+use work.genram_pkg.all;
+use work.streamers_priv_pkg.all;
+use work.streamers_pkg.all;
+
+entity xtx_streamer is
+  generic (
+    -- Width of data words on tx_data_i, must be multiple of 16 bits.
+    g_data_width : integer := 32;
+
+    -- Size of Tx buffer, in data words.
+    g_tx_buffer_size : integer := 256;
+
+    -- Minimum number of data words in the TX buffer that will trigger transmission of an
+    -- Ethernet frame. It cannot be breater than g_tx_buffer_size; it is recommended that
+    -- g_tx_buffer_size = 2 * g_tx_threshold.
+    -- Note that in order for a frame to be transmitted, the buffer must conatain at
+    -- least one complete block.
+    g_tx_threshold : integer := 128;
+
+    -- Maximum number of data words in a single Ethernet frame. It also defines
+    -- the maximum block size (since blocks can't be currently split across
+    -- multiple frames). It cannot be greater than g_tx_buffer_size
+    g_tx_max_words_per_frame : integer := 256;
+
+    -- Transmission timeout (in clk_sys_i cycles), after which the contents
+    -- of TX buffer are sent regardless of the amount of data that is currently
+    -- stored in the buffer, so that data in the buffer does not get stuck.
+    g_tx_timeout : integer := 1024;
+
+    -- DO NOT USE unless you know what you are doing
+    -- legacy stuff: the streamers initially used in Btrain did not check/insert the escape
+    -- code. This is justified if only one block of a known number of words is sent/expected
+    g_escape_code_disable : boolean := FALSE;
+
+    -- simulation mode: it is set to override the startaup-timer, the value with which 
+    -- the timer is overriden is set in the second generic 
+    g_simulation : integer :=0;
+    -- startup counter, used only in simulatin mode (value in 16ns cycles)
+    g_sim_startup_cnt : integer := 6250-- 100us
+    );
+
+  port (
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    -- Endpoint/WRC interface - packet source
+    src_i : in  t_wrf_source_in;
+    src_o : out t_wrf_source_out;
+
+    ---------------------------------------------------------------------------
+    -- WRC Timing interface, used for latency measurement
+    -- Caution: uses clk_ref_i clock domain!
+    ---------------------------------------------------------------------------
+
+    -- White Rabbit reference clock
+    clk_ref_i : in std_logic := '0';
+
+    -- Time valid flag
+    tm_time_valid_i : in std_logic := '0';
+
+    -- TAI seconds
+    tm_tai_i : in std_logic_vector(39 downto 0) := x"0000000000";
+
+    -- Fractional part of the second (in clk_ref_i cycles)
+    tm_cycles_i : in std_logic_vector(27 downto 0) := x"0000000";
+
+    -- status of the link, in principle the tx can be done only if link is oK
+    link_ok_i                  : in std_logic := '1';
+    ---------------------------------------------------------------------------
+    -- User interface
+    ---------------------------------------------------------------------------
+
+    -- Data word to be sent.
+    tx_data_i : in std_logic_vector(g_data_width-1 downto 0);
+
+    -- 1 indicates that the tx_data_i contains a valid data word.
+    tx_valid_i : in std_logic;
+
+    -- Synchronous data request: if active, the user may send a data word in
+    -- the following clock cycle.
+    tx_dreq_o : out std_logic;
+
+    -- Last signal. Can be used to indicate the last data word in a larger
+    -- block of samples (see documentation for more details).
+    tx_last_p1_i : in std_logic := '1';
+
+    -- Flush input. When asserted, the streamer will immediatly send out all
+    -- the data that is stored in its TX buffer, ignoring g_tx_timeout.
+    tx_flush_p1_i : in std_logic := '0';
+
+    -- Reset sequence number. When asserted, the internal sequence number
+    -- generator used to detect loss of frames is reset to 0. Advanced feature.
+    tx_reset_seq_i : in std_logic := '0';
+    -- successfully sent streamer frame
+    tx_frame_p1_o : out std_logic;
+    -- Configuration
+    tx_streamer_cfg_i : in t_tx_streamer_cfg := c_tx_streamer_cfg_default
+    );
+
+end xtx_streamer;
+
+architecture rtl of xtx_streamer is
+
+  type t_tx_state is (IDLE, SOF, ETH_HEADER, FRAME_SEQ_ID, SUBFRAME_HEADER, PAYLOAD, CRC_WORD, PADDING, EOF);
+
+  constant c_min_packet_size : integer := 32;
+
+  signal tx_threshold_hit : std_logic;
+  signal tx_timeout_hit   : std_logic;
+  signal tx_flush_latched : std_logic;
+
+  signal tx_fifo_last, tx_fifo_we, tx_fifo_full, tx_fifo_empty, tx_fifo_rd : std_logic;
+  signal tx_fifo_q, tx_fifo_d                                              : std_logic_vector(g_data_width downto 0);
+  signal state                                                             : t_tx_state;
+  signal seq_no, count                                                     : unsigned(14 downto 0);
+  signal ser_count                                                         : unsigned(7 downto 0);
+  signal word_count                                                        : unsigned(11 downto 0); --2^12 = 4096*2 bytes (can accommodate jambo frame)
+  signal total_words                                                       : unsigned(10 downto 0);
+
+  signal timeout_counter : unsigned(11 downto 0);
+
+  signal pack_data : std_logic_vector(15 downto 0);
+
+  signal fsm_out, escaper, fab_src     : t_pipe;
+  signal fsm_escape, fsm_escape_enable : std_logic;
+
+  signal crc_en, crc_en_masked, crc_reset : std_logic;
+  signal crc_value                        : std_logic_vector(15 downto 0);
+
+  signal tx_almost_empty, tx_almost_full : std_logic;
+
+  signal buf_frame_count : unsigned(5 downto 0) := (others => '0');
+
+
+  signal tag_cycles                   : std_logic_vector(27 downto 0);
+  signal tag_valid, tag_valid_latched : std_logic;
+
+  signal link_ok_delay_cnt         : unsigned(25 downto 0);
+  constant c_link_ok_rst_delay     : unsigned(25 downto 0) := to_unsigned(62500000, 26);-- 1s
+  constant c_link_ok_rst_delay_sim : unsigned(25 downto 0) := to_unsigned(g_sim_startup_cnt, 26);
+
+begin  -- rtl
+
+  -------------------------------------------------------------------------------------------
+  -- check sanity of input generics
+  -------------------------------------------------------------------------------------------
+  assert g_tx_buffer_size >= g_tx_threshold
+    report "The size of the tx buffer must be greater or equal the tx threashold"
+    severity FAILURE;
+
+  assert g_tx_buffer_size >= g_tx_max_words_per_frame
+    report "The size of tx buffer must be greater or equal the max number of words in frame"
+    severity FAILURE;
+  -------------------------------------------------------------------------------------------
+
+  U_tx_crc_generator : gc_crc_gen
+    generic map (
+      g_polynomial              => x"1021",
+      g_init_value              => x"ffff",
+      g_residue                 => x"0000",
+      g_data_width              => 16,
+      g_sync_reset              => 1,
+      g_dual_width              => 0,
+      g_registered_match_output => false,
+      g_registered_crc_output   => false)
+    port map (
+      clk_i     => clk_sys_i,
+      rst_i     => crc_reset,
+      restart_i => '0',
+      en_i      => crc_en_masked,
+      data_i    => fsm_out.data,
+      half_i    => '0',
+      crc_o     => crc_value);
+
+  crc_en_masked <= crc_en and fsm_out.dvalid;
+
+  U_Fab_Source : xwb_fabric_source
+    port map (
+      clk_i     => clk_sys_i,
+      rst_n_i   => rst_n_i,
+      src_i     => src_i,
+      src_o     => src_o,
+      addr_i    => c_WRF_DATA,
+      data_i    => fab_src.data,
+      dvalid_i  => fab_src.dvalid,
+      sof_i     => fab_src.sof,
+      eof_i     => fab_src.eof,
+      error_i   => '0',
+      bytesel_i => '0',
+      dreq_o    => fab_src.dreq);
+
+  fab_src.sof <= fsm_out.sof;
+  fab_src.eof <= fsm_out.eof;
+
+  
+  gen_escape: if (g_escape_code_disable = FALSE) generate
+    U_Insert_Escape : gc_escape_inserter
+      generic map (
+        g_data_width  => 16,
+        g_escape_code => x"cafe")
+      port map (
+        clk_i             => clk_sys_i,
+        rst_n_i           => rst_n_i,
+        d_i               => fsm_out.data,
+        d_insert_enable_i => fsm_escape_enable,
+        d_escape_i        => fsm_escape,
+        d_valid_i         => fsm_out.dvalid,
+        d_req_o           => fsm_out.dreq,
+
+        d_o       => fab_src.data,
+        d_valid_o => fab_src.dvalid,
+        d_req_i   => fab_src.dreq);
+  end generate gen_escape;
+  gen_no_escape: if (g_escape_code_disable = TRUE) generate
+    fab_src.data   <= fsm_out.data;
+    fab_src.dvalid <= fsm_out.dvalid;
+    fsm_out.dreq   <= fab_src.dreq;
+  end generate gen_no_escape;
+
+  tx_fifo_we <= tx_valid_i and not tx_fifo_full;
+  tx_fifo_d  <= tx_last_p1_i & tx_data_i;
+
+  U_TX_Buffer : generic_sync_fifo
+    generic map (
+      g_data_width             => g_data_width + 1,
+      g_size                   => g_tx_buffer_size,
+      g_with_almost_full       => true,
+      g_with_almost_empty      => true,
+      g_almost_empty_threshold => g_tx_threshold,
+      g_almost_full_threshold  => g_tx_buffer_size - 2,
+      g_show_ahead             => true)
+    port map (
+      rst_n_i        => rst_n_i,
+      clk_i          => clk_sys_i,
+      d_i            => tx_fifo_d,
+      we_i           => tx_fifo_we,
+      q_o            => tx_fifo_q,
+      rd_i           => tx_fifo_rd,
+      empty_o        => tx_fifo_empty,
+      full_o         => tx_fifo_full,
+      almost_empty_o => tx_almost_empty,
+      almost_full_o  => tx_almost_full
+      );
+  tx_fifo_rd       <= '1' when (state = PAYLOAD    and ser_count = g_data_width/16-1 and 
+                          fsm_out.dreq = '1' and tx_fifo_empty = '0')         else
+                      '0';
+  tx_threshold_hit <= '1' when tx_almost_empty = '0' and (buf_frame_count /= 0) else '0';
+  tx_fifo_last     <= tx_fifo_q(g_data_width);
+
+  U_Timestamper : pulse_stamper
+    port map (
+      clk_ref_i       => clk_ref_i,
+      clk_sys_i       => clk_sys_i,
+      rst_n_i         => rst_n_i,
+      pulse_a_i       => fsm_out.sof,
+      tm_time_valid_i => tm_time_valid_i,
+      tm_tai_i        => tm_tai_i,
+      tm_cycles_i     => tm_cycles_i,
+      tag_tai_o       => open,
+      tag_cycles_o    => tag_cycles,
+      tag_valid_o     => tag_valid);
+
+  p_frame_counter : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        buf_frame_count <= (others => '0');
+      else
+        if(tx_fifo_we = '1' and tx_last_p1_i = '1' and (tx_fifo_rd = '0' or tx_fifo_last = '0')) then
+          buf_frame_count <= buf_frame_count+ 1;
+        elsif((tx_fifo_we = '0' or tx_last_p1_i = '0') and (tx_fifo_rd = '1' and tx_fifo_last = '1')) then
+          buf_frame_count <= buf_frame_count - 1;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  p_tx_timeout : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        timeout_counter <= (others => '0');
+        tx_timeout_hit  <= '0';
+      else
+        if(tx_fifo_empty = '0' and tx_threshold_hit = '0') then
+          timeout_counter <= timeout_counter + 1;
+        else
+          timeout_counter <= (others => '0');
+        end if;
+
+        if(timeout_counter = g_tx_timeout) then
+          tx_timeout_hit <= '1';
+        else
+          tx_timeout_hit <= '0';
+        end if;
+      end if;
+    end if;
+  end process;
+
+  p_fsm : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        state          <= IDLE;
+        fsm_out.sof    <= '0';
+        fsm_out.eof    <= '0';
+        fsm_out.dvalid <= '0';
+        fsm_out.data   <= (others => '0');
+        count          <= (others => '0');
+        seq_no         <= (others => '0');
+        word_count     <= (others => '0');
+        crc_en         <= '0';
+        crc_reset      <= '1';
+        tx_frame_p1_o     <= '0';
+        tag_valid_latched <= '0';
+        tx_flush_latched  <= '0';
+        fsm_escape_enable <= '0';
+        fsm_escape        <= '0';
+        ser_count         <= (others => '0');
+      else
+        if(tx_reset_seq_i = '1') then
+          seq_no <= (others => '0');
+        end if;
+        if(tag_valid = '1') then 
+          tag_valid_latched <= '1'; -- overriden in IDLE
+        end if;
+        tx_flush_latched <= '0';-- overriden in IDLE
+
+        case state is
+          when IDLE =>
+            tag_valid_latched <= '0';
+            tx_flush_latched  <= tx_flush_p1_i or tx_timeout_hit;
+            crc_en         <= '0';
+            crc_reset      <= '0';
+            fsm_out.eof    <= '0';
+            tx_frame_p1_o  <= '0';
+
+            if(fsm_out.dreq = '1' and (tx_flush_latched = '1' or tx_flush_p1_i = '1' or tx_threshold_hit = '1')) then
+              state       <= SOF;
+              fsm_out.sof <= '1';
+            end if;
+
+            fsm_escape_enable <= '0';
+            fsm_escape        <= '0';
+
+          when SOF =>
+            fsm_out.sof <= '0';
+            ser_count   <= (others => '0');
+            state       <= ETH_HEADER;
+            count       <= (others => '0');
+            word_count  <= (others => '0');
+
+          when ETH_HEADER =>
+            if(fsm_out.dreq = '1') then
+              case count(7 downto 0) is
+                when x"00" =>
+                  fsm_out.data <= tx_streamer_cfg_i.mac_target(47 downto 32);
+                  count        <= count + 1;
+                when x"01" =>
+                  fsm_out.data <= tx_streamer_cfg_i.mac_target(31 downto 16);
+                  count        <= count + 1;
+                when x"02" =>
+                  fsm_out.data <= tx_streamer_cfg_i.mac_target(15 downto 0);
+                  count        <= count + 1;
+                when x"03" =>
+                  fsm_out.data <= tx_streamer_cfg_i.mac_local(47 downto 32);
+                  count        <= count + 1;
+                when x"04" =>
+                  fsm_out.data <= tx_streamer_cfg_i.mac_local(31 downto 16);
+                  count        <= count + 1;
+                when x"05" =>
+                  fsm_out.data <= tx_streamer_cfg_i.mac_local(15 downto 0);
+                  count        <= count + 1;
+                when x"06" =>
+                  if(tx_streamer_cfg_i.qtag_ena = '0') then
+                    fsm_out.data <= tx_streamer_cfg_i.ethertype;
+                  else
+                    fsm_out.data <= x"8100";
+                  end if;
+                  count        <= count + 1;
+                when x"07" =>
+                  if(tx_streamer_cfg_i.qtag_ena = '0') then
+                    fsm_out.data <= tag_valid_latched & "000" & tag_cycles(27 downto 16);
+                  else
+                    fsm_out.data <= tx_streamer_cfg_i.qtag_prio & '0' & tx_streamer_cfg_i.qtag_vid;
+                  end if;
+                  count        <= count + 1;
+                when x"08" =>
+                  if(tx_streamer_cfg_i.qtag_ena = '0') then
+                    fsm_out.data <= tag_cycles(15 downto 0);
+                    state        <= FRAME_SEQ_ID;
+                  else
+                    fsm_out.data <= tx_streamer_cfg_i.ethertype;
+                  end if;
+                  count        <= count + 1;
+                when x"09" =>
+                  fsm_out.data <= tag_valid_latched & "000" & tag_cycles(27 downto 16);
+                  count        <= count + 1;
+                when x"0A" =>
+                  fsm_out.data <= tag_cycles(15 downto 0);
+                  state        <= FRAME_SEQ_ID;
+                  count        <= count + 1;
+                when others =>
+                  fsm_out.data <= (others => 'X');
+                  count        <= (others => 'X');
+              end case;
+              fsm_out.dvalid <= '1';
+            else
+              fsm_out.dvalid <= '0';
+            end if;
+          when FRAME_SEQ_ID =>
+            if(fsm_out.dreq = '1') then
+              fsm_out.data      <= '1' & std_logic_vector(seq_no);
+              seq_no            <= seq_no + 1;
+              count             <= "000" & x"001";
+              fsm_out.dvalid    <= '1';
+              fsm_escape        <= '0';
+              fsm_escape_enable <= '1';
+              crc_en            <= '1';
+              crc_reset         <= '0';
+              state             <= PAYLOAD;
+            else
+              fsm_out.dvalid    <= '0';
+            end if;
+          
+          when SUBFRAME_HEADER =>
+            crc_en    <= '1';
+            crc_reset <= '0';
+
+            if(fsm_out.dreq = '1') then
+              fsm_out.dvalid    <= '1';
+              fsm_escape        <= '1';
+              fsm_escape_enable <= '1';
+              fsm_out.data      <= '1' & std_logic_vector(count);
+              count             <= count + 1;
+              state             <= PAYLOAD;
+            else
+              fsm_out.dvalid <= '0';
+              fsm_out.data   <= (others => 'X');
+            end if;
+
+          when PAYLOAD =>
+            fsm_escape <= '0';
+
+            if(fsm_out.dreq = '1') then
+              -- next subframe?
+              if(tx_fifo_empty = '1' or (ser_count = g_data_width/16-1 and tx_fifo_last = '1')) then
+                state <= CRC_WORD;
+              end if;
+
+              if(ser_count = g_data_width/16-1) then
+                word_count   <= word_count + 1;
+                ser_count    <= (others => '0');
+              else
+                ser_count    <= ser_count + 1;
+              end if;
+
+              fsm_out.data   <= tx_fifo_q((to_integer(ser_count) + 1)* 16 -1 downto to_integer(ser_count) * 16);
+              fsm_out.dvalid <= not tx_fifo_empty;
+            else
+              fsm_out.data   <= (others => 'X');
+              fsm_out.dvalid <= '0';
+            end if;
+
+          when CRC_WORD =>
+            crc_en    <= '0';
+            ser_count <= (others => '0');
+
+            if(fsm_out.dreq = '1') then
+              fsm_out.dvalid <= '1';
+              fsm_out.data   <= crc_value;
+
+              crc_reset <= '1';
+
+              if(tx_fifo_empty = '1' or word_count >= g_tx_max_words_per_frame) then
+                state <= PADDING;
+              else
+                state <= SUBFRAME_HEADER;
+              end if;
+            else
+              fsm_out.data   <= (others => 'X');
+              fsm_out.dvalid <= '0';
+            end if;
+
+          when PADDING =>
+            if(fsm_out.dreq = '1') then
+              fsm_escape     <= '1';
+              fsm_out.dvalid <= '1';
+              fsm_out.data   <= x"0bad"; 
+              if(total_words >= c_min_packet_size) then
+                state <= EOF;
+              end if;
+              crc_reset <= '0';
+            else
+              fsm_out.dvalid <= '0';
+              fsm_out.data   <= (others => 'X');
+            end if;
+            
+          when EOF =>
+            fsm_out.dvalid <= '0';
+            if(fsm_out.dreq = '1') then
+              fsm_out.eof <= '1';
+              tx_frame_p1_o  <= '1';
+              state       <= IDLE;
+            end if;
+        end case;
+      end if;
+    end if;
+  end process;
+
+  p_count_words : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        total_words <= (others => '0');
+      else
+        if fsm_out.sof = '1' then
+          total_words <= (others => '0');
+        elsif fsm_out.dvalid = '1' then
+          total_words <= total_words +1;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  -- after reset, leave some time before accepting requests. This delay 
+  -- is dependent on link_ok signal. This is because after startup (and
+  -- any reset possibly) the PHY first shows link_ok but it is latter 
+  -- restarted by softare... it is a bit of a mess in which we better
+  -- not send anything. Once this startup is done, we only relay on 
+  -- link_ok, i.e. we do not accept requests when link_ok is false.
+  -- During operation (i.e. after start-up/reset, the behaviour of link_ok
+  -- signal is satisfactory
+  p_delay_reset: process(clk_sys_i)
+    begin
+      if rising_edge(clk_sys_i) then
+        if rst_n_i = '0' then
+          if(g_simulation = 1) then
+            link_ok_delay_cnt     <= c_link_ok_rst_delay_sim;
+          else
+            link_ok_delay_cnt     <= c_link_ok_rst_delay;
+          end if;
+        else
+          -- first initial moments of link_ok_i high are ignored
+          if(link_ok_i = '1' and link_ok_delay_cnt > 0) then
+            link_ok_delay_cnt     <= link_ok_delay_cnt-1;
+          end if;
+        end if;
+      end if;
+    end process;
+
+  tx_dreq_o <= '0' when (link_ok_delay_cnt > 0) else
+               (not tx_almost_full) and link_ok_i;
+
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/xtx_streamers_stats.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/xtx_streamers_stats.vhd
new file mode 100644
index 000000000..983e4e640
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/xtx_streamers_stats.vhd
@@ -0,0 +1,125 @@
+-------------------------------------------------------------------------------
+-- Title      : WR tx streamers statistics
+-- Project    : WR streamers
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/WR_Streamers
+-------------------------------------------------------------------------------
+-- File       : xrtx_streamers_stats.vhd
+-- Author     : Maciej Lipinski
+-- Company    : CERN
+-- Created    : 2017-04-19
+-- Platform   : FPGA-generics
+-- Standard   : VHDL
+-------------------------------------------------------------------------------
+-- Description:
+-- This module provies the reception portion of statistics and
+-- allows to snapshot their values. See xrtx_streamers_stats for
+-- more detailed description.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2017 CERN/BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+library work;
+use work.wishbone_pkg.all;  -- needed for t_wishbone_slave_in, etc
+use work.streamers_pkg.all; -- needed for streamers
+use work.wr_fabric_pkg.all; -- neede for :t_wrf_source_in, etc
+use work.wrcore_pkg.all;    -- needed for t_generic_word_array
+-- use work.wr_transmission_wbgen2_pkg.all;
+
+entity xtx_streamers_stats is
+  
+  generic (
+    -- Width of frame counters
+    g_cnt_width            : integer := 32 -- minimum 15 bits, max 32
+    );
+  port (
+    clk_i                  : in std_logic;
+    rst_n_i                : in std_logic;
+
+    -- input signals from streamers
+    sent_frame_i           : in std_logic;
+
+    -- statistic control
+    reset_stats_i          : in std_logic;
+    snapshot_ena_i         : in std_logic := '0';
+    ----------------------- statistics ----------------------------------------
+    -- output statistics: tx/rx counters
+    sent_frame_cnt_o       : out std_logic_vector(g_cnt_width-1 downto 0)
+  );
+
+end xtx_streamers_stats;
+  
+architecture rtl of xtx_streamers_stats is
+
+  signal sent_frame_cnt    : unsigned(g_cnt_width-1  downto 0);
+  signal sent_frame_cnt_d1 : unsigned(g_cnt_width-1  downto 0);
+  signal snapshot_ena_d1   : std_logic;
+begin
+
+  -------------------------------------------------------------------------------------------
+  -- frame/block statistics, i.e. lost, sent, received
+  -------------------------------------------------------------------------------------------
+  -- process that counts
+  p_cnts: process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if (rst_n_i = '0' or reset_stats_i = '1') then
+        sent_frame_cnt        <= (others => '0');
+      else
+        -- count sent frames
+        if(sent_frame_i = '1') then
+          sent_frame_cnt <= sent_frame_cnt + 1;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  -------------------------------------------------------------------------------------------
+  -- snapshot 
+  -------------------------------------------------------------------------------------------
+  -- snapshot is used to expose to user coherent value, so that the count for accumulated
+  -- latency is coherent with the accumulated latency and the average can be accurately 
+  -- calculated
+  -------------------------------------------------------------------------------------------
+  p_stats_snapshot: process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if (rst_n_i = '0') then
+         snapshot_ena_d1         <= '0';
+         sent_frame_cnt_d1       <= (others=>'0');
+      else
+        if(snapshot_ena_i = '1' and snapshot_ena_d1 = '0') then
+         sent_frame_cnt_d1       <= sent_frame_cnt;
+        end if;
+        snapshot_ena_d1 <= snapshot_ena_i;
+      end if;
+    end if;
+  end process;
+
+  -------------------------------------------------------------------------------------------
+  -- snapshot or current value
+  -------------------------------------------------------------------------------------------
+  sent_frame_cnt_o       <= std_logic_vector(sent_frame_cnt_d1) when (snapshot_ena_d1 = '1') else
+                            std_logic_vector(sent_frame_cnt);
+
+end rtl;
\ No newline at end of file
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/xwr_streamers.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/xwr_streamers.vhd
new file mode 100644
index 000000000..774a54a37
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/xwr_streamers.vhd
@@ -0,0 +1,467 @@
+-------------------------------------------------------------------------------
+-- Title      : WR Streamrs
+-- Project    : WR Streamers
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/WR_Streamers
+-------------------------------------------------------------------------------
+-- File       : xwr_streamers.vhd (renamed from xwr_transmission.vhd)
+-- Author     : Maciej Lipinski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL
+-- Created    : 2016-05-30
+-------------------------------------------------------------------------------
+-- Description:
+--
+-- This module is a top-level entity for WR streamers to be used conveniently
+-- in application. It is inlcluded in the board top entity of wr-cores as one
+-- of transportation means.
+--
+-- It allows to send and receive streames of data over Ethernet network. In
+-- other words, it provides communication over Ethernet network that looks as
+-- FIFO: one one node (e.g. SPEC, the user writes to tx streamer words of 
+-- configureable size. These words are received by the rx streamer in another
+-- node (e.g. SVEC) in the same order. 
+--
+-- This module wraps WR_Streamers-related stuff: i.e.
+-- 1) IP core modules provided in wr-cores: xtx_streamer, xrx_streamer,
+--    xrtx_streamers_stats
+-- 2) wishbone registers that provide access to the statistics and streamer's
+--    control/status registers.
+--
+-- This module interfaces:
+-- 1) WR PTP Core for transmission/reception of raw ethernet frames
+-- 2) Application-specific module for transmission/reception of data
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2016 CERN/BE-CO-HT
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+---------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+library work;
+use work.wishbone_pkg.all;  -- needed for t_wishbone_slave_in, etc
+use work.streamers_pkg.all; -- needed for streamers and  c_WR_TRANS_ARR_SIZE_*
+use work.wr_fabric_pkg.all; -- needed for :t_wrf_source_in, etc
+use work.wrcore_pkg.all;    -- needed for t_generic_word_array
+use work.wr_streamers_wbgen2_pkg.all;
+use work.streamers_priv_pkg.all;
+
+entity xwr_streamers is
+  generic (
+    -- Indicates whether this module instantiates both streamers (rx and tx) or only one
+    -- of them. An application that only receives or only transmits might want to use
+    -- RX_ONLY or TX_ONLY mode to save resources.
+    g_streamers_op_mode        : t_streamers_op_mode  := TX_AND_RX;
+    -----------------------------------------------------------------------------------------
+    -- Transmission/reception parameters
+    -----------------------------------------------------------------------------------------
+    g_tx_streamer_params       : t_tx_streamer_params := c_tx_streamer_params_defaut;
+    g_rx_streamer_params       : t_rx_streamer_params := c_rx_streamer_params_defaut;
+    -----------------------------------------------------------------------------------------
+    -- Statistics config
+    -----------------------------------------------------------------------------------------
+    -- width of counters: frame rx/tx/lost, block lost, counter of accumuted latency
+    -- (min:15, max:64, 50 bits should be ok for 50 years)
+    g_stats_cnt_width          : integer := 50;
+    -- width of latency accumulator (max value 64)
+    g_stats_acc_width          : integer := 64;
+    -----------------------------------------------------------------------------------------
+    -- WB I/F configuration
+    -----------------------------------------------------------------------------------------
+    g_slave_mode               : t_wishbone_interface_mode      := CLASSIC;
+    g_slave_granularity        : t_wishbone_address_granularity := BYTE;
+    g_simulation               : integer := 0
+    );
+
+  port (
+    clk_sys_i                  : in std_logic;
+    rst_n_i                    : in std_logic;
+
+    ---------------------------------------------------------------------------
+    -- WR tx/rx interface
+    ---------------------------------------------------------------------------
+    -- Tx
+    src_i                      : in  t_wrf_source_in;
+    src_o                      : out t_wrf_source_out;
+    -- Rx
+    snk_i                      : in  t_wrf_sink_in;
+    snk_o                      : out t_wrf_sink_out;
+
+    ---------------------------------------------------------------------------
+    -- User tx interface
+    ---------------------------------------------------------------------------
+    -- Data word to be sent.
+    tx_data_i                  : in std_logic_vector(g_tx_streamer_params.data_width-1 downto 0);
+    -- 1 indicates that the tx_data_i contains a valid data word.
+    tx_valid_i                 : in std_logic;
+    -- Synchronous data request: if active, the user may send a data word in
+    -- the following clock cycle.
+    tx_dreq_o                  : out std_logic;
+    -- Last signal. Can be used to indicate the last data word in a larger
+    -- block of samples (see documentation for more details).
+    tx_last_p1_i               : in std_logic := '1';
+    -- Flush input. When asserted, the streamer will immediatly send out all
+    -- the data that is stored in its TX buffer, ignoring g_tx_timeout.
+    tx_flush_p1_i              : in std_logic := '0';
+
+    ---------------------------------------------------------------------------
+    -- User rx interface
+    ---------------------------------------------------------------------------
+    -- 1 indicates the 1st word of the data block on rx_data_o.
+    rx_first_p1_o              : out std_logic;
+    -- 1 indicates the last word of the data block on rx_data_o.
+    rx_last_p1_o               : out std_logic;
+    -- Received data.
+    rx_data_o                  : out std_logic_vector(g_rx_streamer_params.data_width-1 downto 0);
+    -- 1 indicted that rx_data_o is outputting a valid data word.
+    rx_valid_o                 : out std_logic;
+    -- Synchronous data request input: when 1, the streamer may output another
+    -- data word in the subsequent clock cycle.
+    rx_dreq_i                  : in  std_logic;
+
+    ---------------------------------------------------------------------------
+    -- WRC Timing interface, used for latency measurement
+    ---------------------------------------------------------------------------
+
+    -- White Rabbit reference clock
+    clk_ref_i                  : in std_logic := '0';
+    -- Time valid flag
+    tm_time_valid_i            : in std_logic := '0';
+    -- TAI seconds
+    tm_tai_i                   : in std_logic_vector(39 downto 0) := x"0000000000";
+    -- Fractional part of the second (in clk_ref_i cycles)
+    tm_cycles_i                : in std_logic_vector(27 downto 0) := x"0000000";
+
+    -- status of the link, in principle the tx can be done only if link is oK
+    link_ok_i                  : in std_logic;
+    -- wishbone interface 
+    wb_slave_i                 : in  t_wishbone_slave_in := cc_dummy_slave_in;
+    wb_slave_o                 : out t_wishbone_slave_out;
+
+    snmp_array_o               : out t_generic_word_array(c_WR_STREAMERS_ARR_SIZE_OUT-1 downto 0);
+    snmp_array_i               : in  t_generic_word_array(c_WR_STREAMERS_ARR_SIZE_IN -1 downto 0);
+
+    -----------------------------------------------------------------------------------------
+    -- Transmission and Reception configuration
+    -----------------------------------------------------------------------------------------
+    tx_streamer_cfg_i          : in t_tx_streamer_cfg := c_tx_streamer_cfg_default;
+    rx_streamer_cfg_i          : in t_rx_streamer_cfg := c_rx_streamer_cfg_default
+    );
+
+end xwr_streamers;
+
+architecture rtl of xwr_streamers is
+
+  signal to_wb              : t_wr_streamers_in_registers;
+  signal from_wb            : t_wr_streamers_out_registers;
+  signal dbg_word                : std_logic_vector(31 downto 0);
+  signal start_bit               : std_logic_vector(from_wb.dbg_ctrl_start_byte_o'length-1+3 downto 0);
+  signal rx_data                 : std_logic_vector(g_rx_streamer_params.data_width-1 downto 0);
+  signal wb_regs_slave_in        : t_wishbone_slave_in;
+  signal wb_regs_slave_out       : t_wishbone_slave_out;  
+  signal tx_frame                : std_logic;
+  signal reset_time_tai          : std_logic_vector(39 downto 0);
+  signal latency_acc             : std_logic_vector(g_stats_acc_width-1 downto 0);
+  signal latency_cnt             : std_logic_vector(g_stats_cnt_width-1 downto 0);
+  signal sent_frame_cnt_out      : std_logic_vector(g_stats_cnt_width-1 downto 0);
+  signal rcvd_frame_cnt_out      : std_logic_vector(g_stats_cnt_width-1 downto 0);
+  signal lost_frame_cnt_out      : std_logic_vector(g_stats_cnt_width-1 downto 0);
+  signal lost_block_cnt_out      : std_logic_vector(g_stats_cnt_width-1 downto 0);
+  signal rx_valid                : std_logic;
+
+  signal rx_latency_valid        : std_logic;
+  signal rx_latency              : std_logic_vector(27 downto 0);
+  signal rx_lost_frames          : std_logic;
+  signal rx_lost_frames_cnt      : std_logic_vector(14 downto 0);
+  signal rx_lost_blocks          : std_logic;
+  signal rx_frame                : std_logic;
+
+  signal tx_streamer_cfg         : t_tx_streamer_cfg;
+  signal rx_streamer_cfg         : t_rx_streamer_cfg;
+
+  -- for code cleanness
+  constant c_cw              : integer := g_stats_cnt_width;
+  constant c_aw              : integer := g_stats_acc_width;
+begin
+
+  -------------------------------------------------------------------------------------------
+  -- Instantiate transmission streamer, if configured to do so
+  -------------------------------------------------------------------------------------------
+  gen_tx: if(g_streamers_op_mode=TX_ONLY OR g_streamers_op_mode=TX_AND_RX) generate
+    U_TX: xtx_streamer
+      generic map(
+        g_data_width             => g_tx_streamer_params.data_width,
+        g_tx_buffer_size         => g_tx_streamer_params.buffer_size,
+        g_tx_threshold           => g_tx_streamer_params.threshold,
+        g_tx_max_words_per_frame => g_tx_streamer_params.max_words_per_frame,
+        g_tx_timeout             => g_tx_streamer_params.timeout,
+        g_escape_code_disable    => g_tx_streamer_params.escape_code_disable,
+        g_simulation             => g_simulation)
+      port map(
+        clk_sys_i                => clk_sys_i,
+        rst_n_i                  => rst_n_i,
+        src_i                    => src_i,
+        src_o                    => src_o,
+        clk_ref_i                => clk_ref_i,
+        tm_time_valid_i          => tm_time_valid_i,
+        tm_tai_i                 => tm_tai_i,
+        tm_cycles_i              => tm_cycles_i,
+        link_ok_i                => link_ok_i,
+        tx_data_i                => tx_data_i,
+        tx_valid_i               => tx_valid_i,
+        tx_dreq_o                => tx_dreq_o,
+        tx_last_p1_i             => tx_last_p1_i,
+        tx_flush_p1_i            => tx_flush_p1_i,
+        tx_reset_seq_i           => from_wb.sscr1_rst_seq_id_o,
+        tx_frame_p1_o            => tx_frame,
+        tx_streamer_cfg_i        => tx_streamer_cfg);
+  end generate gen_tx;
+
+  gen_not_tx: if(g_streamers_op_mode=RX_ONLY) generate
+    src_o      <= c_dummy_snk_in;
+    tx_dreq_o  <= '0';
+    tx_frame   <= '0';
+  end generate gen_not_tx;
+
+  -------------------------------------------------------------------------------------------
+  -- -- Instantiate reception streamer, if configured to do so
+  -------------------------------------------------------------------------------------------
+  gen_rx: if(g_streamers_op_mode=RX_ONLY OR g_streamers_op_mode=TX_AND_RX) generate
+    U_RX: xrx_streamer
+      generic map(
+        g_data_width             => g_rx_streamer_params.data_width,
+        g_buffer_size            => g_rx_streamer_params.buffer_size,
+        g_escape_code_disable    => g_rx_streamer_params.escape_code_disable,
+        g_expected_words_number  => g_rx_streamer_params.expected_words_number
+        )
+      port map(
+        clk_sys_i                => clk_sys_i,
+        rst_n_i                  => rst_n_i,
+        snk_i                    => snk_i,
+        snk_o                    => snk_o,
+        clk_ref_i                => clk_ref_i,
+        tm_time_valid_i          => tm_time_valid_i,
+        tm_tai_i                 => tm_tai_i,
+        tm_cycles_i              => tm_cycles_i,
+        rx_first_p1_o            => rx_first_p1_o,
+        rx_last_p1_o             => rx_last_p1_o,
+        rx_data_o                => rx_data,
+        rx_valid_o               => rx_valid,
+        rx_dreq_i                => rx_dreq_i,
+        rx_lost_p1_o             => rx_lost_blocks,
+        rx_lost_frames_p1_o      => rx_lost_frames,
+        rx_lost_frames_cnt_o     => rx_lost_frames_cnt,
+        rx_latency_o             => rx_latency,
+        rx_latency_valid_o       => rx_latency_valid,
+        rx_frame_p1_o            => rx_frame,
+        rx_streamer_cfg_i        => rx_streamer_cfg);
+  end generate gen_rx;
+  gen_not_rx: if(g_streamers_op_mode=TX_ONLY) generate
+    snk_o         <= c_dummy_src_in;
+    rx_first_p1_o <= '0';
+    rx_last_p1_o  <= '0';
+    rx_data       <= (others => '0');
+    rx_valid      <= '0';
+  end generate gen_not_rx;
+
+  -------------------------------------------------------------------------------------------
+  -- Instantiate statistics module - it calculates statistics of rx/tx frames
+  -------------------------------------------------------------------------------------------
+  U_STATS: xrtx_streamers_stats
+    generic map(
+      g_streamers_op_mode      => g_streamers_op_mode,
+      g_cnt_width              => g_stats_cnt_width,
+      g_acc_width              => g_stats_acc_width
+      )
+    port map(
+      clk_i                    => clk_sys_i,
+      rst_n_i                  => rst_n_i,
+      sent_frame_i             => tx_frame,
+      rcvd_frame_i             => rx_frame,
+      lost_frame_i             => rx_lost_frames,
+      lost_block_i             => rx_lost_blocks,
+      lost_frames_cnt_i        => rx_lost_frames_cnt,
+      rcvd_latency_i           => rx_latency,
+      rcvd_latency_valid_i     => rx_latency_valid,
+      clk_ref_i                => clk_ref_i,
+      tm_time_valid_i          => tm_time_valid_i,
+      tm_tai_i                 => tm_tai_i,
+      tm_cycles_i              => tm_cycles_i,
+      reset_stats_i            => from_wb.sscr1_rst_stats_o,
+      snapshot_ena_i           => from_wb.sscr1_snapshot_stats_o,
+      reset_time_tai_o         => reset_time_tai,
+      reset_time_cycles_o      => to_wb.sscr1_rst_ts_cyc_i,
+      sent_frame_cnt_o         => sent_frame_cnt_out,
+      rcvd_frame_cnt_o         => rcvd_frame_cnt_out,
+      lost_frame_cnt_o         => lost_frame_cnt_out,
+      lost_block_cnt_o         => lost_block_cnt_out,
+      latency_cnt_o            => latency_cnt,
+      latency_acc_o            => latency_acc,
+      latency_max_o            => to_wb.rx_stat0_rx_latency_max_i,
+      latency_min_o            => to_wb.rx_stat1_rx_latency_min_i,
+      latency_acc_overflow_o   => to_wb.sscr1_rx_latency_acc_overflow_i,
+      snmp_array_o             => snmp_array_o(c_WRS_STATS_ARR_SIZE_OUT-1 downto 0),
+      snmp_array_i             => snmp_array_i
+      );
+
+  to_wb.sscr2_rst_ts_tai_lsb_i             <= reset_time_tai(31 downto 0);
+  to_wb.sscr3_rst_ts_tai_msb_i             <= reset_time_tai(39 downto 32);
+
+  assert (g_stats_acc_width <= 64 and g_stats_acc_width > 32)
+    report "g_stats_acc_width (c_aw) must be between 33 and 64" severity error;
+  assert (g_stats_cnt_width <= 64 and g_stats_cnt_width > 32)
+    report "g_stats_cnt_width (c_cw) must be between 33 and 64" severity error;
+
+  to_wb.tx_stat2_tx_sent_cnt_lsb_i                             <= sent_frame_cnt_out(31     downto 0);
+  to_wb.tx_stat3_tx_sent_cnt_msb_i        (c_cw-32-1 downto 0) <= sent_frame_cnt_out(c_cw-1 downto 32);
+  to_wb.rx_stat4_rx_rcvd_cnt_lsb_i                             <= rcvd_frame_cnt_out(31     downto 0);
+  to_wb.rx_stat5_rx_rcvd_cnt_msb_i        (c_cw-32-1 downto 0) <= rcvd_frame_cnt_out(c_cw-1 downto 32);
+  to_wb.rx_stat6_rx_loss_cnt_lsb_i                             <= lost_frame_cnt_out(31     downto 0);
+  to_wb.rx_stat7_rx_loss_cnt_msb_i        (c_cw-32-1 downto 0) <= lost_frame_cnt_out(c_cw-1 downto 32);
+  to_wb.rx_stat8_rx_lost_block_cnt_lsb_i                       <= lost_block_cnt_out(31     downto 0);
+  to_wb.rx_stat9_rx_lost_block_cnt_msb_i  (c_cw-32-1 downto 0) <= lost_block_cnt_out(c_cw-1 downto 32);
+  to_wb.rx_stat10_rx_latency_acc_lsb_i                         <= latency_acc       (31     downto 0);
+  to_wb.rx_stat11_rx_latency_acc_msb_i    (c_aw-32-1 downto 0) <= latency_acc       (c_aw-1 downto 32);
+  to_wb.rx_stat12_rx_latency_acc_cnt_lsb_i                     <= latency_cnt       (31     downto 0);
+  to_wb.rx_stat13_rx_latency_acc_cnt_msb_i(c_cw-32-1 downto 0) <= latency_cnt       (c_cw-1 downto 32);
+
+  rx_data_o  <= rx_data;
+  rx_valid_o <= rx_valid;
+
+  -------------------------------------------------------------------------------------------
+  -- Wishbone access to statistics and configuration
+  -------------------------------------------------------------------------------------------
+  U_WB_ADAPTER : wb_slave_adapter
+    generic map (
+      g_master_use_struct  => true,
+      g_master_mode        => CLASSIC,
+      g_master_granularity => WORD,
+      g_slave_use_struct   => true,
+      g_slave_mode         => g_slave_mode,
+      g_slave_granularity  => g_slave_granularity)
+    port map (
+      clk_sys_i  => clk_sys_i,
+      rst_n_i    => rst_n_i,
+      slave_i    => wb_slave_i,
+      slave_o    => wb_slave_o,
+      master_i   => wb_regs_slave_out,
+      master_o   => wb_regs_slave_in);
+
+  U_WB:  wr_streamers_wb
+    port map (
+      rst_n_i      => rst_n_i,
+      clk_sys_i    => clk_sys_i,
+      wb_adr_i     => wb_regs_slave_in.adr(5 downto 0),
+      wb_dat_i     => wb_regs_slave_in.dat,
+      wb_dat_o     => wb_regs_slave_out.dat,
+      wb_cyc_i     => wb_regs_slave_in.cyc,
+      wb_sel_i     => wb_regs_slave_in.sel(3 downto 0),
+      wb_stb_i     => wb_regs_slave_in.stb,
+      wb_we_i      => wb_regs_slave_in.we,
+      wb_ack_o     => wb_regs_slave_out.ack,
+      wb_stall_o   => wb_regs_slave_out.stall,
+      regs_i       => to_wb,
+      regs_o       => from_wb
+    );
+
+  -------------------------------------------------------------------------------------------
+  -- Provide generic debugging through WB - user can read 32 bits from each send or received
+  -- word. It is possible to configure through WB which 32-bits of each word should be 
+  -- "snooped". In particular, user can sent:
+  -- * whether he/she wishes to look at received or sent words
+  -- * the byte number at which the snooping shall start, i.e. say users sets byte=2, it means
+  --   that he will be able to read through wishbone bytes 3-6 of each word, provided the
+  --   word is of sufficient width
+  -------------------------------------------------------------------------------------------
+  start_bit <= from_wb.dbg_ctrl_start_byte_o & "000";
+  p_debug_mux: process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        dbg_word <= (others =>'0');
+      else
+        if(from_wb.dbg_ctrl_mux_o = '1') then --rx
+          if(rx_valid = '1') then
+            dbg_word <= f_dbg_word_starting_at_bit(rx_data,start_bit,g_rx_streamer_params.data_width);
+          end if;
+        else -- tx
+          if(tx_valid_i = '1') then
+            dbg_word <= f_dbg_word_starting_at_bit(tx_data_i,start_bit,g_tx_streamer_params.data_width);
+          end if;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  snmp_array_o(c_WRS_STATS_ARR_SIZE_OUT)   <= dbg_word;
+  snmp_array_o(c_WRS_STATS_ARR_SIZE_OUT+1) <= x"DEADBEEF";
+
+  to_wb.dbg_data_i      <= dbg_word;
+  to_wb.dummy_dummy_i   <= x"DEADBEEF";
+
+  -------------------------------------------------------------------------------------------
+  -- set configuration: the user can access configuration through two channels:
+  -- 1) records (tx_streamer_cfg & rx_streamer_cfg) with input signals
+  -- 2) wishbone write
+  -- By default, the input signals are used. A user can overwrite this default
+  -- configuration using WB access. To override the default configuration two 
+  -- values needs to be written:
+  -- 1) the value of a proper configuration, e.g.: tx_cfg0_ethertype, rx_cfg0_filter_remote
+  -- 2) bit that enables overriding of the configuration, e.g. cfg_or_tx_ethtype and
+  --    cfg_or_rx_ftr_remote_o respectively
+  -- The latter (overriding bit) is the so that user can first configure all values
+  -- that he wishes to and then enable all his desired configuration at the same instant.
+  -- Otherwise, during the transition (e.g. between writing lsb and msb of MAC), the
+  -- behaviour could be unpredictable.
+  -------------------------------------------------------------------------------------------
+  -- tx config
+  tx_streamer_cfg.ethertype         <= from_wb.tx_cfg0_ethertype_o        when (from_wb.cfg_or_tx_ethtype_o='1') else
+                                       tx_streamer_cfg_i.ethertype;
+  tx_streamer_cfg.mac_local         <= from_wb.tx_cfg2_mac_local_msb_o &
+                                       from_wb.tx_cfg1_mac_local_lsb_o    when (from_wb.cfg_or_tx_mac_loc_o='1') else
+                                       tx_streamer_cfg_i.mac_local;
+  tx_streamer_cfg.mac_target        <= from_wb.tx_cfg4_mac_target_msb_o &
+                                       from_wb.tx_cfg3_mac_target_lsb_o   when (from_wb.cfg_or_tx_mac_tar_o='1') else
+                                       tx_streamer_cfg_i.mac_target;
+  tx_streamer_cfg.qtag_ena          <= from_wb.tx_cfg5_qtag_ena_o         when (from_wb.cfg_or_tx_qtag_o='1') else
+                                       tx_streamer_cfg_i.qtag_ena;
+  tx_streamer_cfg.qtag_vid          <= from_wb.tx_cfg5_qtag_vid_o         when (from_wb.cfg_or_tx_qtag_o='1') else
+                                       tx_streamer_cfg_i.qtag_vid;
+  tx_streamer_cfg.qtag_prio         <= from_wb.tx_cfg5_qtag_prio_o        when (from_wb.cfg_or_tx_qtag_o='1') else
+                                       tx_streamer_cfg_i.qtag_prio;
+
+  -- rx config
+  rx_streamer_cfg.ethertype         <= from_wb.rx_cfg0_ethertype_o        when (from_wb.cfg_or_rx_ethertype_o='1') else
+                                       rx_streamer_cfg_i.ethertype;
+  rx_streamer_cfg.mac_local         <= from_wb.rx_cfg2_mac_local_msb_o &
+                                       from_wb.rx_cfg1_mac_local_lsb_o    when (from_wb.cfg_or_rx_mac_loc_o='1') else
+                                       rx_streamer_cfg_i.mac_local;
+  rx_streamer_cfg.mac_remote        <= from_wb.rx_cfg4_mac_remote_msb_o &
+                                       from_wb.rx_cfg3_mac_remote_lsb_o   when (from_wb.cfg_or_rx_mac_rem_o='1') else
+                                       rx_streamer_cfg_i.mac_remote;
+  rx_streamer_cfg.accept_broadcasts <= from_wb.rx_cfg0_accept_broadcast_o when (from_wb.cfg_or_rx_acc_broadcast_o='1') else
+                                       rx_streamer_cfg_i.accept_broadcasts;
+  rx_streamer_cfg.filter_remote     <= from_wb.rx_cfg0_filter_remote_o    when (from_wb.cfg_or_rx_ftr_remote_o='1') else
+                                       rx_streamer_cfg_i.filter_remote;
+  rx_streamer_cfg.fixed_latency     <= from_wb.rx_cfg5_fixed_latency_o    when (from_wb.cfg_or_rx_fix_lat_o='1') else
+                                       rx_streamer_cfg_i.fixed_latency;
+end rtl;
\ No newline at end of file
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_tbi_phy/disparity_gen_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_tbi_phy/disparity_gen_pkg.vhd
new file mode 100644
index 000000000..3c23afa59
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_tbi_phy/disparity_gen_pkg.vhd
@@ -0,0 +1,90 @@
+-- 8b10b disparity generator, based on 8b10b encoder core (c) Mathias Kreider
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package disparity_gen_pkg is
+
+  type t_8b10b_disparity is (RD_PLUS, RD_MINUS);
+  
+  function f_next_8b10b_disparity8 (cur_disp : t_8b10b_disparity;
+                                    ctrl     : std_logic;
+                                    data     : std_logic_vector)
+    return t_8b10b_disparity;
+
+  function f_next_8b10b_disparity16 (
+    cur_disp : t_8b10b_disparity;
+    ctrl     : std_logic_vector;
+    data     : std_logic_vector)
+    return t_8b10b_disparity;
+
+  function to_std_logic(t : t_8b10b_disparity) return std_logic;
+
+  
+
+end disparity_gen_pkg;
+
+package body disparity_gen_pkg is
+
+  function f_next_8b10b_disparity8(cur_disp : t_8b10b_disparity;
+                                   ctrl     : std_logic;
+                                   data     : std_logic_vector) return t_8b10b_disparity is
+
+    constant c_disPar_6b : std_logic_vector(0 to 31) := ("11101000100000011000000110010111");
+
+    constant c_disPar_4b    : std_logic_vector(0 to 7) := ("10001001");
+    variable dp4bit, dp6bit : std_logic;
+    variable new_disp       : t_8b10b_disparity;
+  begin
+-- use 3bit at 7-5 as index for 4bit code and disparity table \n
+
+    dp4bit := c_disPar_4b(to_integer(unsigned(data(7 downto 5))));
+    dp6bit := c_disPar_6b(to_integer(unsigned(data(4 downto 0))));
+
+    new_disp := cur_disp;
+
+    case cur_disp is
+      when RD_MINUS =>
+        if (ctrl xor dp6bit xor dp4bit) /= '0' then
+          new_disp := RD_PLUS;
+        end if;
+
+      when RD_PLUS =>
+        if (ctrl xor dp6bit xor dP4bit) /= '0' then
+          new_disp := RD_MINUS;
+        end if;
+    end case;
+
+    if ( data(1 downto 0) /= "00" and ctrl = '1') then
+      new_disp := cur_disp;
+    end if;
+    
+    return new_disp;
+  end f_next_8b10b_disparity8;
+
+  function f_next_8b10b_disparity16(cur_disp : t_8b10b_disparity;
+                                    ctrl     : std_logic_vector;
+                                    data     : std_logic_vector) return t_8b10b_disparity is
+
+    variable tmp : t_8b10b_disparity;
+    variable msb : std_logic_vector(7 downto 0);
+  begin
+
+    msb := data(15 downto 8);
+    tmp := f_next_8b10b_disparity8(cur_disp, ctrl(1), msb);
+    tmp := f_next_8b10b_disparity8(tmp, ctrl(0), data(7 downto 0));
+    return tmp;
+  end f_next_8b10b_disparity16;
+
+  function to_std_logic(t : t_8b10b_disparity) return std_logic is
+  begin
+    if(t = RD_MINUS) then
+      return '0';
+    else
+      return '1';
+    end if;
+  end to_std_logic;
+
+end package body;
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/wr_core.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/wr_core.vhd
new file mode 100644
index 000000000..c87f5a405
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/wr_core.vhd
@@ -0,0 +1,1157 @@
+-------------------------------------------------------------------------------
+-- Title      : WhiteRabbit PTP Core
+-- Project    : WhiteRabbit
+-------------------------------------------------------------------------------
+-- File       : wr_core.vhd
+-- Author     : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
+-- Company    : CERN (BE-CO-HT)
+-- Created    : 2011-02-02
+-- Last update: 2017-05-29
+-- Platform   : FPGA-generics
+-- Standard   : VHDL
+-------------------------------------------------------------------------------
+-- Description:
+-- WR PTP Core is a HDL module implementing a complete gigabit Ethernet
+-- interface (MAC + PCS + PHY) with integrated PTP slave ordinary clock
+-- compatible with White Rabbit protocol. It performs subnanosecond clock
+-- synchronization via WR protocol and also acts as an Ethernet "gateway",
+-- providing access to TX/RX interfaces of the built-in WR MAC.
+--
+-- Starting from version 2.0 all modules are interconnected with pipelined
+-- wishbone interface (using wb crossbars). Separate pipelined wishbone bus is
+-- used for passing packets between Endpoint, Mini-NIC and External
+-- MAC interface.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012 - 2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Memory map:
+--  0x00000000: I/D Memory
+--  0x00020000: Peripheral interconnect
+--      +0x000: Minic
+--      +0x100: Endpoint
+--      +0x200: Softpll
+--      +0x300: PPS gen
+--      +0x400: Syscon
+--      +0x500: UART
+--      +0x600: OneWire
+--      +0x700: Auxillary space (Etherbone config, etc)
+--      +0x800: WRPC diagnostics registers
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.wrcore_pkg.all;
+use work.gencores_pkg.all;
+use work.genram_pkg.all;
+use work.wishbone_pkg.all;
+use work.endpoint_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.sysc_wbgen2_pkg.all;
+use work.softpll_pkg.all;
+
+entity wr_core is
+  generic(
+    --if set to 1, then blocks in PCS use smaller calibration counter to speed
+    --up simulation
+    g_simulation                : integer                        := 0;
+    g_with_external_clock_input : boolean                        := true;
+    --
+    g_board_name                : string                         := "NA  ";
+    g_flash_secsz_kb            : integer                        := 256;        -- default for SVEC (M25P128)
+    g_flash_sdbfs_baddr         : integer                        := 16#600000#; -- default for SVEC (M25P128)
+    g_phys_uart                 : boolean                        := true;
+    g_virtual_uart              : boolean                        := true;
+    g_aux_clks                  : integer                        := 0;
+    g_rx_buffer_size            : integer                        := 1024;
+    g_tx_runt_padding           : boolean                        := true;
+    g_dpram_initf               : string                         := "default";
+    g_dpram_size                : integer                        := 131072/4;  --in 32-bit words
+    g_interface_mode            : t_wishbone_interface_mode      := PIPELINED;
+    g_address_granularity       : t_wishbone_address_granularity := BYTE;
+    g_aux_sdb                   : t_sdb_device                   := c_wrc_periph3_sdb;
+    g_softpll_enable_debugger   : boolean                        := false;
+    g_vuart_fifo_size           : integer                        := 1024;
+    g_pcs_16bit                 : boolean                        := false;
+    g_records_for_phy           : boolean                        := false;
+    g_diag_id                   : integer                        := 0;
+    g_diag_ver                  : integer                        := 0;
+    g_diag_ro_size              : integer                        := 0;
+    g_diag_rw_size              : integer                        := 0);
+  port(
+    ---------------------------------------------------------------------------
+    -- Clocks/resets
+    ---------------------------------------------------------------------------
+
+    -- system reference clock (any frequency <= f(clk_ref_i))
+    clk_sys_i : in std_logic;
+
+    -- DDMTD offset clock (125.x MHz)
+    clk_dmtd_i : in std_logic;
+
+    -- Timing reference (125 MHz)
+    clk_ref_i : in std_logic;
+
+    -- Aux clocks (i.e. the FMC clock), which can be disciplined by the WR Core
+    clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
+
+    clk_ext_mul_i : in std_logic := '0';
+    clk_ext_mul_locked_i  : in  std_logic := '1';
+    clk_ext_stopped_i     : in  std_logic := '0';
+    clk_ext_rst_o         : out std_logic;
+
+    -- External 10 MHz reference (cesium, GPSDO, etc.), used in Grandmaster mode
+    clk_ext_i : in std_logic := '0';
+
+    -- External PPS input (cesium, GPSDO, etc.), used in Grandmaster mode
+    pps_ext_i : in std_logic := '0';
+
+    rst_n_i : in std_logic;
+
+    -----------------------------------------
+    --Timing system
+    -----------------------------------------
+    dac_hpll_load_p1_o : out std_logic;
+    dac_hpll_data_o    : out std_logic_vector(15 downto 0);
+
+    dac_dpll_load_p1_o : out std_logic;
+    dac_dpll_data_o    : out std_logic_vector(15 downto 0);
+
+    -- PHY I/f
+    phy_ref_clk_i : in std_logic;
+
+    phy_tx_data_o      : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
+    phy_tx_k_o         : out std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
+    phy_tx_disparity_i : in  std_logic;
+    phy_tx_enc_err_i   : in  std_logic;
+
+    phy_rx_data_i     : in std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
+    phy_rx_rbclk_i    : in std_logic;
+    phy_rx_k_i        : in std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
+    phy_rx_enc_err_i  : in std_logic;
+    phy_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0);
+
+    phy_rst_o            : out std_logic;
+    phy_rdy_i            : in  std_logic := '1';
+    phy_loopen_o         : out std_logic;
+    phy_loopen_vec_o     : out std_logic_vector(2 downto 0);
+    phy_tx_prbs_sel_o    : out std_logic_vector(2 downto 0);
+    phy_sfp_tx_fault_i   : in std_logic := '0';
+    phy_sfp_los_i        : in std_logic := '0';
+    phy_sfp_tx_disable_o : out std_logic;
+
+    -- PHY I/F record-based
+    phy8_o  : out t_phy_8bits_from_wrc;
+    phy8_i  : in  t_phy_8bits_to_wrc  := c_dummy_phy8_to_wrc;
+    phy16_o : out t_phy_16bits_from_wrc;
+    phy16_i : in  t_phy_16bits_to_wrc := c_dummy_phy16_to_wrc;
+
+    -----------------------------------------
+    --GPIO
+    -----------------------------------------
+    led_act_o  : out std_logic;
+    led_link_o : out std_logic;
+    scl_o      : out std_logic;
+    scl_i      : in  std_logic := '1';
+    sda_o      : out std_logic;
+    sda_i      : in  std_logic := '1';
+    sfp_scl_o  : out std_logic;
+    sfp_scl_i  : in  std_logic := '1';
+    sfp_sda_o  : out std_logic;
+    sfp_sda_i  : in  std_logic := '1';
+    sfp_det_i  : in  std_logic := '1';
+    btn1_i     : in  std_logic := '1';
+    btn2_i     : in  std_logic := '1';
+    spi_sclk_o : out std_logic;
+    spi_ncs_o  : out std_logic;
+    spi_mosi_o : out std_logic;
+    spi_miso_i : in  std_logic := '0';
+
+    -----------------------------------------
+    --UART
+    -----------------------------------------
+    uart_rxd_i : in  std_logic := '1';
+    uart_txd_o : out std_logic;
+
+    -----------------------------------------
+    -- 1-wire
+    -----------------------------------------
+    owr_pwren_o : out std_logic_vector(1 downto 0);
+    owr_en_o    : out std_logic_vector(1 downto 0);
+    owr_i       : in  std_logic_vector(1 downto 0) := (others => '1');
+
+    -----------------------------------------
+    --External WB interface
+    -----------------------------------------
+    wb_adr_i   : in  std_logic_vector(c_wishbone_address_width-1 downto 0)   := (others => '0');
+    wb_dat_i   : in  std_logic_vector(c_wishbone_data_width-1 downto 0)      := (others => '0');
+    wb_dat_o   : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+    wb_sel_i   : in  std_logic_vector(c_wishbone_address_width/8-1 downto 0) := (others => '0');
+    wb_we_i    : in  std_logic                                               := '0';
+    wb_cyc_i   : in  std_logic                                               := '0';
+    wb_stb_i   : in  std_logic                                               := '0';
+    wb_ack_o   : out std_logic;
+    wb_err_o   : out std_logic;
+    wb_rty_o   : out std_logic;
+    wb_stall_o : out std_logic;
+
+    -----------------------------------------
+    -- Auxillary WB master
+    -----------------------------------------
+    aux_adr_o   : out std_logic_vector(c_wishbone_address_width-1 downto 0);
+    aux_dat_o   : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+    aux_dat_i   : in  std_logic_vector(c_wishbone_data_width-1 downto 0);
+    aux_sel_o   : out std_logic_vector(c_wishbone_address_width/8-1 downto 0);
+    aux_we_o    : out std_logic;
+    aux_cyc_o   : out std_logic;
+    aux_stb_o   : out std_logic;
+    aux_ack_i   : in  std_logic := '1';
+    aux_stall_i : in  std_logic := '0';
+
+    -----------------------------------------
+    -- External Fabric I/F
+    -----------------------------------------
+    ext_snk_adr_i   : in  std_logic_vector(1 downto 0)  := "00";
+    ext_snk_dat_i   : in  std_logic_vector(15 downto 0) := x"0000";
+    ext_snk_sel_i   : in  std_logic_vector(1 downto 0)  := "00";
+    ext_snk_cyc_i   : in  std_logic                     := '0';
+    ext_snk_we_i    : in  std_logic                     := '0';
+    ext_snk_stb_i   : in  std_logic                     := '0';
+    ext_snk_ack_o   : out std_logic;
+    ext_snk_err_o   : out std_logic;
+    ext_snk_stall_o : out std_logic;
+
+    ext_src_adr_o   : out std_logic_vector(1 downto 0);
+    ext_src_dat_o   : out std_logic_vector(15 downto 0);
+    ext_src_sel_o   : out std_logic_vector(1 downto 0);
+    ext_src_cyc_o   : out std_logic;
+    ext_src_stb_o   : out std_logic;
+    ext_src_we_o    : out std_logic;
+    ext_src_ack_i   : in  std_logic := '1';
+    ext_src_err_i   : in  std_logic := '0';
+    ext_src_stall_i : in  std_logic := '0';
+
+    ------------------------------------------
+    -- External TX Timestamp I/F
+    ------------------------------------------
+    txtsu_port_id_o      : out std_logic_vector(4 downto 0);
+    txtsu_frame_id_o     : out std_logic_vector(15 downto 0);
+    txtsu_ts_value_o     : out std_logic_vector(31 downto 0);
+    txtsu_ts_incorrect_o : out std_logic;
+    txtsu_stb_o          : out std_logic;
+    txtsu_ack_i          : in  std_logic := '1';
+
+    -----------------------------------------
+    -- Timestamp helper signals, used for Absolute Calibration
+    -----------------------------------------
+    abscal_txts_o        : out std_logic;
+    abscal_rxts_o        : out std_logic;
+
+    -----------------------------------------
+    -- Pause Frame Control
+    -----------------------------------------
+    fc_tx_pause_req_i   : in  std_logic                     := '0';
+    fc_tx_pause_delay_i : in  std_logic_vector(15 downto 0) := x"0000";
+    fc_tx_pause_ready_o : out std_logic;
+
+    -----------------------------------------
+    -- Timecode/Servo Control
+    -----------------------------------------
+
+    tm_link_up_o         : out std_logic;
+    -- DAC Control
+    tm_dac_value_o       : out std_logic_vector(23 downto 0);
+    tm_dac_wr_o          : out std_logic_vector(g_aux_clks-1 downto 0);
+    -- Aux clock lock enable
+    tm_clk_aux_lock_en_i : in  std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
+    -- Aux clock locked flag
+    tm_clk_aux_locked_o  : out std_logic_vector(g_aux_clks-1 downto 0);
+    -- Timecode output
+    tm_time_valid_o      : out std_logic;
+    tm_tai_o             : out std_logic_vector(39 downto 0);
+    tm_cycles_o          : out std_logic_vector(27 downto 0);
+    -- 1PPS output
+    pps_csync_o          : out std_logic;
+    pps_p_o              : out std_logic;
+    pps_led_o            : out std_logic;
+
+    rst_aux_n_o : out std_logic;
+
+    link_ok_o : out std_logic;
+
+    -------------------------------------
+    -- DIAG to/from external modules
+    -------------------------------------
+    aux_diag_i : in  t_generic_word_array(g_diag_ro_size-1 downto 0) := (others=>(others=>'0'));
+    aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0)
+    );
+end wr_core;
+
+architecture struct of wr_core is
+
+  function f_choose_lm32_firmware_file return string is
+  begin
+    if(g_dpram_initf = "default") then
+      if(g_simulation /= 0) then
+        report "[WR Core] Using simulation LM32 firmware." severity note;
+        return "wrc-simulation.ram";
+      else
+        report "[WR Core] Using release LM32 firmware." severity note;
+        return "wrc-release.ram";
+      end if;
+    else
+      report "[WR Core] Using user-provided LM32 firmware." severity note;
+      return g_dpram_initf;
+    end if;
+  end function;
+
+  function f_check_if_lm32_firmware_necessary return boolean is
+  begin
+    if(g_dpram_initf /= "") then
+      return true;
+    else
+      return false;
+    end if;
+  end function;
+
+  -----------------------------------------------------------------------------
+  --Local resets for peripheral
+  -----------------------------------------------------------------------------
+  signal rst_wrc_n : std_logic;
+  signal rst_net_n : std_logic;
+
+  -----------------------------------------------------------------------------
+  --Local resets (resynced)
+  -----------------------------------------------------------------------------
+  signal rst_net_resync_ref_n   : std_logic;
+  signal rst_net_resync_ext_n   : std_logic;
+  signal rst_net_resync_dmtd_n  : std_logic;
+  signal rst_net_resync_rxclk_n : std_logic;
+  signal rst_net_resync_txclk_n : std_logic;
+
+  -----------------------------------------------------------------------------
+  --PPS generator
+  -----------------------------------------------------------------------------
+  signal s_pps_csync : std_logic;
+  signal pps_valid   : std_logic;
+  signal ppsg_link_ok: std_logic;
+
+  signal ppsg_wb_in  : t_wishbone_slave_in;
+  signal ppsg_wb_out : t_wishbone_slave_out;
+
+  -----------------------------------------------------------------------------
+  --Timing system
+  -----------------------------------------------------------------------------
+  signal phy_rx_clk  : std_logic;
+  signal phy_tx_clk  : std_logic;
+  signal spll_wb_in  : t_wishbone_slave_in;
+  signal spll_wb_out : t_wishbone_slave_out;
+
+  -----------------------------------------------------------------------------
+  --Endpoint
+  -----------------------------------------------------------------------------
+  signal ep_txtsu_port_id           : std_logic_vector(4 downto 0);
+  signal ep_txtsu_frame_id          : std_logic_vector(15 downto 0);
+  signal ep_txtsu_ts_value          : std_logic_vector(31 downto 0);
+  signal ep_txtsu_ts_incorrect      : std_logic;
+  signal ep_txtsu_stb, ep_txtsu_ack : std_logic;
+  signal ep_led_link                : std_logic;
+
+  signal phy_rst : std_logic;
+
+  constant c_mnic_memsize_log2 : integer := f_log2_size(g_dpram_size);
+
+  -----------------------------------------------------------------------------
+  --Mini-NIC
+  -----------------------------------------------------------------------------
+  signal mnic_mem_data_o : std_logic_vector(31 downto 0);
+  signal mnic_mem_addr_o : std_logic_vector(c_mnic_memsize_log2-1 downto 0);
+  signal mnic_mem_wr_o   : std_logic;
+  signal mnic_txtsu_ack  : std_logic;
+  signal mnic_txtsu_stb  : std_logic;
+
+  -----------------------------------------------------------------------------
+  --Dual-port RAM
+  -----------------------------------------------------------------------------
+  signal dpram_wbb_i : t_wishbone_slave_in;
+
+  -----------------------------------------------------------------------------
+  --WB Peripherials
+  -----------------------------------------------------------------------------
+  signal periph_slave_i : t_wishbone_slave_in_array(0 to 3);
+  signal periph_slave_o : t_wishbone_slave_out_array(0 to 3);
+  signal sysc_in_regs   : t_sysc_in_registers;
+  signal sysc_out_regs  : t_sysc_out_registers;
+
+  -----------------------------------------------------------------------------
+  --WB Secondary Crossbar
+  -----------------------------------------------------------------------------
+  constant c_secbar_layout : t_sdb_record_array(8 downto 0) :=
+    (0 => f_sdb_embed_device(c_xwr_mini_nic_sdb, x"00000000"),
+     1 => f_sdb_embed_device(c_xwr_endpoint_sdb, x"00000100"),
+     2 => f_sdb_embed_device(c_xwr_softpll_ng_sdb, x"00000200"),
+     3 => f_sdb_embed_device(c_xwr_pps_gen_sdb, x"00000300"),
+     4 => f_sdb_embed_device(c_wrc_periph0_sdb, x"00000400"),  -- Syscon
+     5 => f_sdb_embed_device(c_wrc_periph1_sdb, x"00000500"),  -- UART
+     6 => f_sdb_embed_device(c_wrc_periph2_sdb, x"00000600"),  -- 1-Wire
+     7 => f_sdb_embed_device(g_aux_sdb,         x"00000700"),  -- aux WB bus
+     8 => f_sdb_embed_device(c_wrc_periph4_sdb, x"00000800")   -- WRPC diag registers
+     );
+
+  constant c_secbar_sdb_address : t_wishbone_address := x"00000C00";
+  constant c_secbar_bridge_sdb  : t_sdb_bridge       :=
+    f_xwb_bridge_layout_sdb(true, c_secbar_layout, c_secbar_sdb_address);
+
+  signal secbar_master_i : t_wishbone_master_in_array(8 downto 0);
+  signal secbar_master_o : t_wishbone_master_out_array(8 downto 0);
+
+  -----------------------------------------------------------------------------
+  --WB intercon
+  -----------------------------------------------------------------------------
+  constant c_layout : t_sdb_record_array(1 downto 0) :=
+    (0 => f_sdb_embed_device(f_xwb_dpram(g_dpram_size), x"00000000"),
+     1 => f_sdb_embed_bridge(c_secbar_bridge_sdb, x"00020000"));
+  constant c_sdb_address : t_wishbone_address := x"00030000";
+
+  signal cbar_slave_i  : t_wishbone_slave_in_array (2 downto 0);
+  signal cbar_slave_o  : t_wishbone_slave_out_array(2 downto 0);
+  signal cbar_master_i : t_wishbone_master_in_array(1 downto 0);
+  signal cbar_master_o : t_wishbone_master_out_array(1 downto 0);
+
+  -----------------------------------------------------------------------------
+  --External WB interface
+  -----------------------------------------------------------------------------
+  signal ext_wb_in  : t_wishbone_slave_in;
+  signal ext_wb_out : t_wishbone_slave_out;
+
+  -----------------------------------------------------------------------------
+  -- External Tx TSU interface
+  -----------------------------------------------------------------------------
+
+  --===========================--
+  --         For SPEC          --
+  --===========================--
+
+  signal hpll_auxout  : std_logic_vector(2 downto 0);
+  signal dmpll_auxout : std_logic_vector(2 downto 0);
+
+  signal clk_ref_slv : std_logic_vector(0 downto 0);
+  signal clk_rx_slv  : std_logic_vector(0 downto 0);
+
+  signal s_dummy_addr : std_logic_vector(31 downto 0);
+
+  signal softpll_irq : std_logic;
+
+  signal lm32_irq_slv : std_logic_vector(31 downto 0);
+
+
+  signal ep_wb_in  : t_wishbone_slave_in;
+  signal ep_wb_out : t_wishbone_slave_out;
+
+  signal minic_wb_in  : t_wishbone_slave_in;
+  signal minic_wb_out : t_wishbone_slave_out;
+
+  signal ep_src_out : t_wrf_source_out;
+  signal ep_src_in  : t_wrf_source_in;
+  signal ep_snk_out : t_wrf_sink_out;
+  signal ep_snk_in  : t_wrf_sink_in;
+
+
+  signal mux_src_out : t_wrf_source_out_array(1 downto 0);
+  signal mux_src_in  : t_wrf_source_in_array(1 downto 0);
+  signal mux_snk_out : t_wrf_sink_out_array(1 downto 0);
+  signal mux_snk_in  : t_wrf_sink_in_array(1 downto 0);
+  signal mux_class   : t_wrf_mux_class(1 downto 0);
+
+  signal spll_out_locked : std_logic_vector(g_aux_clks downto 0);
+
+  signal dac_dpll_data    : std_logic_vector(15 downto 0);
+  signal dac_dpll_sel     : std_logic_vector(3 downto 0);
+  signal dac_dpll_load_p1 : std_logic;
+
+  signal clk_fb     : std_logic_vector(g_aux_clks downto 0);
+  signal out_enable : std_logic_vector(g_aux_clks downto 0);
+
+  --component chipscope_ila
+  --  port (
+  --    CONTROL : inout std_logic_vector(35 downto 0);
+  --    CLK     : in    std_logic;
+  --    TRIG0   : in    std_logic_vector(31 downto 0);
+  --    TRIG1   : in    std_logic_vector(31 downto 0);
+  --    TRIG2   : in    std_logic_vector(31 downto 0);
+  --    TRIG3   : in    std_logic_vector(31 downto 0));
+  --end component;
+
+  --component chipscope_icon
+  --  port (
+  --    CONTROL0 : inout std_logic_vector (35 downto 0));
+  --end component;
+
+  --signal CONTROL : std_logic_vector(35 downto 0);
+  --signal CLK     : std_logic;
+  --signal TRIG0   : std_logic_vector(31 downto 0);
+  --signal TRIG1   : std_logic_vector(31 downto 0);
+  --signal TRIG2   : std_logic_vector(31 downto 0);
+  --signal TRIG3   : std_logic_vector(31 downto 0);
+begin
+
+  -----------------------------------------------------------------------------
+  -- PHY TX/RX clock selection based on generics
+  -----------------------------------------------------------------------------
+
+  GEN_16BIT_PHY_IF: if g_pcs_16bit and g_records_for_phy generate
+    phy_rx_clk <= phy16_i.rx_clk;
+    phy_tx_clk <= phy16_i.ref_clk;
+  end generate;
+
+  GEN_8BIT_PHY_IF: if not g_pcs_16bit and g_records_for_phy generate
+    phy_rx_clk <= phy8_i.rx_clk;
+    phy_tx_clk <= phy8_i.ref_clk;
+  end generate;
+
+  GEN_STD_PHY_IF: if not g_records_for_phy generate
+    phy_rx_clk <= phy_rx_rbclk_i;
+    phy_tx_clk <= phy_ref_clk_i;
+  end generate;
+
+  -----------------------------------------------------------------------------
+  -- Reset resync and distribution
+  -----------------------------------------------------------------------------
+
+  rst_aux_n_o <= rst_net_n;
+
+  U_Sync_reset_refclk : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_ref_i,
+      rst_n_i  => '1',
+      data_i   => rst_net_n,
+      synced_o => rst_net_resync_ref_n);
+
+  U_sync_reset_dmtd : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_dmtd_i,
+      rst_n_i  => '1',
+      data_i   => rst_net_n,
+      synced_o => rst_net_resync_dmtd_n);
+
+  U_sync_reset_ext : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_ext_i,
+      rst_n_i  => '1',
+      data_i   => rst_net_n,
+      synced_o => rst_net_resync_ext_n);
+
+  U_sync_reset_rxclk : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => phy_rx_clk,
+      rst_n_i  => '1',
+      data_i   => rst_net_n,
+      synced_o => rst_net_resync_rxclk_n);
+
+  U_sync_reset_txclk : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => phy_tx_clk,
+      rst_n_i  => '1',
+      data_i   => rst_net_n,
+      synced_o => rst_net_resync_txclk_n);
+
+  -----------------------------------------------------------------------------
+  -- PPS generator
+  -----------------------------------------------------------------------------
+  PPS_GEN : xwr_pps_gen
+    generic map(
+      g_interface_mode       => PIPELINED,
+      g_address_granularity  => BYTE,
+      g_ref_clock_rate       => f_refclk_rate(g_pcs_16bit),
+      g_ext_clock_rate       => 10000000,
+      g_with_ext_clock_input => g_with_external_clock_input)
+    port map(
+      clk_ref_i => clk_ref_i,
+      clk_sys_i => clk_sys_i,
+
+      rst_sys_n_i => rst_net_n,
+      rst_ref_n_i => rst_net_resync_ref_n,
+
+      slave_i => ppsg_wb_in,
+      slave_o => ppsg_wb_out,
+
+      -- used for fast masking of PPS output when link goes down
+      link_ok_i => ppsg_link_ok,
+
+      -- Single-pulse PPS output for synchronizing endpoint to
+      pps_in_i    => pps_ext_i,
+      pps_csync_o => s_pps_csync,
+      pps_out_o   => pps_p_o,
+      pps_led_o   => pps_led_o,
+      pps_valid_o => pps_valid,
+
+      tm_utc_o        => tm_tai_o,
+      tm_cycles_o     => tm_cycles_o,
+      tm_time_valid_o => tm_time_valid_o
+      );
+  ppsg_link_ok <= not phy_rst;
+  pps_csync_o  <= s_pps_csync;
+
+  -----------------------------------------------------------------------------
+  -- Software PLL
+  -----------------------------------------------------------------------------
+  U_SOFTPLL : xwr_softpll_ng
+    generic map(
+      g_with_ext_clock_input => g_with_external_clock_input,
+      g_reverse_dmtds        => false,
+      g_divide_input_by_2    => not g_pcs_16bit,
+      g_with_debug_fifo      => g_softpll_enable_debugger,
+      g_tag_bits             => 22,
+      g_interface_mode       => PIPELINED,
+      g_address_granularity  => BYTE,
+      g_num_ref_inputs       => 1,
+      g_num_outputs          => 1 + g_aux_clks,
+      g_ref_clock_rate       => f_refclk_rate(g_pcs_16bit),
+      g_ext_clock_rate       => 10000000)
+    port map(
+      clk_sys_i    => clk_sys_i,
+      rst_sys_n_i  => rst_net_n,
+      rst_ref_n_i  => rst_net_resync_ref_n,
+      rst_ext_n_i  => rst_net_resync_ext_n,
+      rst_dmtd_n_i => rst_net_resync_dmtd_n,
+
+      -- Reference inputs (i.e. the RX clocks recovered by the PHYs)
+      clk_ref_i(0) => phy_rx_clk,
+      -- Feedback clocks (i.e. the outputs of the main or aux oscillator)
+      clk_fb_i     => clk_fb,
+      -- DMTD Offset clock
+      clk_dmtd_i   => clk_dmtd_i,
+
+      clk_ext_i     => clk_ext_i,
+      clk_ext_mul_i => clk_ext_mul_i,
+      clk_ext_mul_locked_i => clk_ext_mul_locked_i,
+      clk_ext_stopped_i    => clk_ext_stopped_i,
+      clk_ext_rst_o        => clk_ext_rst_o,
+
+      pps_csync_p1_i => s_pps_csync,
+      pps_ext_a_i => pps_ext_i,
+
+      -- DMTD oscillator drive
+      dac_dmtd_data_o => dac_hpll_data_o,
+      dac_dmtd_load_o => dac_hpll_load_p1_o,
+
+      -- Output channel DAC value
+      dac_out_data_o => dac_dpll_data,  --: out std_logic_vector(15 downto 0);
+      -- Output channel select (0 = channel 0, etc. )
+      dac_out_sel_o  => dac_dpll_sel,   --for now use only one output
+      dac_out_load_o => dac_dpll_load_p1,
+
+      out_enable_i => out_enable,
+
+      out_locked_o => spll_out_locked,
+
+      slave_i => spll_wb_in,
+      slave_o => spll_wb_out,
+
+      debug_o => open);
+
+  clk_fb(0)                       <= clk_ref_i;
+  clk_fb(g_aux_clks downto 1)     <= clk_aux_i;
+  out_enable(0)                   <= '1';
+  out_enable(g_aux_clks downto 1) <= tm_clk_aux_lock_en_i;
+
+  dac_dpll_data_o    <= dac_dpll_data;
+  dac_dpll_load_p1_o <= '1' when (dac_dpll_load_p1 = '1' and dac_dpll_sel = x"0") else '0';
+
+  tm_dac_value_o <= x"00" & dac_dpll_data;
+
+  p_decode_dac_writes : process(dac_dpll_load_p1, dac_dpll_sel)
+  begin
+    for i in 0 to g_aux_clks-1 loop
+      if dac_dpll_sel = std_logic_vector(to_unsigned(i+1, 4)) then
+        tm_dac_wr_o(i) <= dac_dpll_load_p1;
+      else
+        tm_dac_wr_o(i) <= '0';
+      end if;
+    end loop;  -- i
+  end process;
+
+  locked_spll : if g_aux_clks > 0 generate
+    tm_clk_aux_locked_o <= spll_out_locked(g_aux_clks downto 1);
+  end generate;
+
+  softpll_irq <= spll_wb_out.int;
+
+  -----------------------------------------------------------------------------
+  -- Endpoint
+  -----------------------------------------------------------------------------
+  U_Endpoint : xwr_endpoint
+    generic map (
+      g_interface_mode      => PIPELINED,
+      g_address_granularity => BYTE,
+      g_simulation          => f_int2bool(g_simulation),
+      g_tx_runt_padding     => g_tx_runt_padding,
+      g_pcs_16bit           => g_pcs_16bit,
+      g_records_for_phy     => g_records_for_phy,
+      g_rx_buffer_size      => g_rx_buffer_size,
+      g_with_rx_buffer      => true,
+      g_with_flow_control   => false,
+      g_with_timestamper    => true,
+      g_with_dpi_classifier => true,
+      g_with_vlans          => false,
+      g_with_rtu            => false,
+      g_with_leds           => true,
+      g_with_packet_injection => false,
+      g_use_new_rxcrc       => true,
+      g_use_new_txcrc       => false)
+    port map (
+      clk_ref_i      => clk_ref_i,
+      clk_sys_i      => clk_sys_i,
+      clk_dmtd_i     => clk_dmtd_i,
+      rst_sys_n_i    => rst_net_n,
+      rst_ref_n_i    => rst_net_resync_ref_n,
+      rst_dmtd_n_i   => rst_net_resync_dmtd_n,
+      rst_txclk_n_i  => rst_net_resync_txclk_n,
+      rst_rxclk_n_i  => rst_net_resync_rxclk_n,
+      pps_csync_p1_i => s_pps_csync,
+      pps_valid_i    => pps_valid,
+
+      phy_rst_o            => phy_rst,
+      phy_rdy_i            => phy_rdy_i,
+      phy_loopen_o         => phy_loopen_o,
+      phy_loopen_vec_o     => phy_loopen_vec_o,
+      phy_tx_prbs_sel_o    => phy_tx_prbs_sel_o,
+      phy_sfp_tx_fault_i   => phy_sfp_tx_fault_i,
+      phy_sfp_los_i        => phy_sfp_los_i,
+      phy_sfp_tx_disable_o => phy_sfp_tx_disable_o,
+      phy_ref_clk_i        => phy_ref_clk_i,
+      phy_tx_data_o        => phy_tx_data_o,
+      phy_tx_k_o           => phy_tx_k_o,
+      phy_tx_disparity_i   => phy_tx_disparity_i,
+      phy_tx_enc_err_i     => phy_tx_enc_err_i,
+      phy_rx_data_i        => phy_rx_data_i,
+      phy_rx_clk_i         => phy_rx_rbclk_i,
+      phy_rx_k_i           => phy_rx_k_i,
+      phy_rx_enc_err_i     => phy_rx_enc_err_i,
+      phy_rx_bitslide_i    => phy_rx_bitslide_i,
+
+      phy8_o  => phy8_o,
+      phy8_i  => phy8_i,
+      phy16_o => phy16_o,
+      phy16_i => phy16_i,
+
+      src_o => ep_src_out,
+      src_i => ep_src_in,
+      snk_o => ep_snk_out,
+      snk_i => ep_snk_in,
+
+      txtsu_port_id_o      => ep_txtsu_port_id,
+      txtsu_frame_id_o     => ep_txtsu_frame_id,
+      txtsu_ts_value_o     => ep_txtsu_ts_value,
+      txtsu_ts_incorrect_o => ep_txtsu_ts_incorrect,
+      txtsu_stb_o          => ep_txtsu_stb,
+      txtsu_ack_i          => ep_txtsu_ack,
+      wb_i                 => ep_wb_in,
+      wb_o                 => ep_wb_out,
+      rmon_events_o        => open,
+      txts_o               => abscal_txts_o,
+      rxts_o               => abscal_rxts_o,
+      fc_tx_pause_req_i    => fc_tx_pause_req_i,
+      fc_tx_pause_delay_i  => fc_tx_pause_delay_i,
+      fc_tx_pause_ready_o  => fc_tx_pause_ready_o,
+      led_link_o           => ep_led_link,
+      led_act_o            => led_act_o);
+
+  led_link_o   <= ep_led_link;
+  link_ok_o    <= ep_led_link;
+
+  tm_link_up_o <= ep_led_link;
+
+  phy_rst_o <= phy_rst;
+
+  -----------------------------------------------------------------------------
+  -- Mini-NIC
+  -----------------------------------------------------------------------------
+  MINI_NIC : xwr_mini_nic
+    generic map (
+      g_interface_mode       => PIPELINED,
+      g_address_granularity  => BYTE,
+      g_tx_fifo_size         => 1024,
+      g_rx_fifo_size         => 2048,
+      g_buffer_little_endian => false)
+    port map (
+      clk_sys_i => clk_sys_i,
+      rst_n_i   => rst_net_n,
+
+      src_o => mux_snk_in(0),
+      src_i => mux_snk_out(0),
+      snk_o => mux_src_in(0),
+      snk_i => mux_src_out(0),
+
+      txtsu_port_id_i     => ep_txtsu_port_id,
+      txtsu_frame_id_i    => ep_txtsu_frame_id,
+      txtsu_tsval_i       => ep_txtsu_ts_value,
+      txtsu_tsincorrect_i => ep_txtsu_ts_incorrect,
+      txtsu_stb_i         => mnic_txtsu_stb,
+      txtsu_ack_o         => mnic_txtsu_ack,
+
+      wb_i => minic_wb_in,
+      wb_o => minic_wb_out
+      );
+
+  lm32_irq_slv(31 downto 1) <= (others => '0');
+  lm32_irq_slv(0)           <= softpll_irq;  -- according to the doc, it's active low.
+
+  -----------------------------------------------------------------------------
+  -- LM32
+  -----------------------------------------------------------------------------
+  LM32_CORE : xwb_lm32
+    generic map(g_profile => "medium_icache")
+    port map(
+      clk_sys_i => clk_sys_i,
+      rst_n_i   => rst_wrc_n,
+      irq_i     => lm32_irq_slv,
+
+      dwb_o => cbar_slave_i(0),
+      dwb_i => cbar_slave_o(0),
+      iwb_o => cbar_slave_i(1),
+      iwb_i => cbar_slave_o(1)
+      );
+
+  -----------------------------------------------------------------------------
+  -- Dual-port RAM
+  -----------------------------------------------------------------------------
+  DPRAM : xwb_dpram
+    generic map(
+      g_size                  => g_dpram_size,
+      g_init_file             => f_choose_lm32_firmware_file,
+      g_must_have_init_file   => f_check_if_lm32_firmware_necessary,
+      g_slave1_interface_mode => PIPELINED,
+      g_slave2_interface_mode => PIPELINED,
+      g_slave1_granularity    => BYTE,
+      g_slave2_granularity    => WORD)
+    port map(
+      clk_sys_i => clk_sys_i,
+      rst_n_i   => rst_n_i,
+
+      slave1_i => cbar_master_o(0),
+      slave1_o => cbar_master_i(0),
+      slave2_i => dpram_wbb_i,
+      slave2_o => open
+      );
+
+  dpram_wbb_i.cyc <= '0';
+  dpram_wbb_i.stb <= '0';
+  dpram_wbb_i.adr <= (c_mnic_memsize_log2-1 downto 0 => '0', others=>'0'); --mnic_mem_addr_o;
+  dpram_wbb_i.sel <= "1111";
+  dpram_wbb_i.we  <= '0'; --mnic_mem_wr_o;
+  dpram_wbb_i.dat <= (others=>'0'); --mnic_mem_data_o;
+
+  -----------------------------------------------------------------------------
+  -- WB Peripherials
+  -----------------------------------------------------------------------------
+  PERIPH : wrc_periph
+    generic map(
+      g_board_name      => g_board_name,
+      g_flash_secsz_kb  => g_flash_secsz_kb,
+      g_flash_sdbfs_baddr => g_flash_sdbfs_baddr,
+      g_phys_uart       => g_phys_uart,
+      g_virtual_uart    => g_virtual_uart,
+      g_mem_words       => g_dpram_size,
+      g_vuart_fifo_size => g_vuart_fifo_size,
+      g_diag_id         => g_diag_id,
+      g_diag_ver        => g_diag_ver,
+      g_diag_ro_size    => g_diag_ro_size,
+      g_diag_rw_size    => g_diag_rw_size)
+    port map(
+      clk_sys_i   => clk_sys_i,
+      rst_n_i     => rst_n_i,
+      rst_net_n_o => rst_net_n,
+      rst_wrc_n_o => rst_wrc_n,
+
+      led_red_o   => open,              --led_red_o,
+      led_green_o => open,              --led_green_o,
+      scl_o       => scl_o,
+      scl_i       => scl_i,
+      sda_o       => sda_o,
+      sda_i       => sda_i,
+      sfp_scl_o   => sfp_scl_o,
+      sfp_scl_i   => sfp_scl_i,
+      sfp_sda_o   => sfp_sda_o,
+      sfp_sda_i   => sfp_sda_i,
+      sfp_det_i   => sfp_det_i,
+      memsize_i   => "0000",
+      btn1_i      => btn1_i,
+      btn2_i      => btn2_i,
+      spi_sclk_o  => spi_sclk_o,
+      spi_ncs_o   => spi_ncs_o,
+      spi_mosi_o  => spi_mosi_o,
+      spi_miso_i  => spi_miso_i,
+
+      slave_i => periph_slave_i,
+      slave_o => periph_slave_o,
+
+      uart_rxd_i => uart_rxd_i,
+      uart_txd_o => uart_txd_o,
+
+      owr_pwren_o => owr_pwren_o,
+      owr_en_o    => owr_en_o,
+      owr_i       => owr_i,
+
+      diag_array_in  => aux_diag_i,
+      diag_array_out => aux_diag_o
+      );
+
+  U_Adapter : wb_slave_adapter
+    generic map(
+      g_master_use_struct  => true,
+      g_master_mode        => PIPELINED,
+      g_master_granularity => BYTE,
+      g_slave_use_struct   => false,
+      g_slave_mode         => g_interface_mode,
+      g_slave_granularity  => g_address_granularity)
+    port map (
+      clk_sys_i  => clk_sys_i,
+      rst_n_i    => rst_n_i,
+      master_i   => ext_wb_out,
+      master_o   => ext_wb_in,
+      sl_adr_i   => wb_adr_i,
+      sl_dat_i   => wb_dat_i,
+      sl_sel_i   => wb_sel_i,
+      sl_cyc_i   => wb_cyc_i,
+      sl_stb_i   => wb_stb_i,
+      sl_we_i    => wb_we_i,
+      sl_dat_o   => wb_dat_o,
+      sl_ack_o   => wb_ack_o,
+      sl_err_o   => wb_err_o,
+      sl_rty_o   => wb_rty_o,
+      sl_stall_o => wb_stall_o);
+
+  -----------------------------------------------------------------------------
+  -- WB intercon
+  -----------------------------------------------------------------------------
+  WB_CON : xwb_sdb_crossbar
+    generic map(
+      g_num_masters => 3,
+      g_num_slaves  => 2,
+      g_registered  => true,
+      g_wraparound  => true,
+      g_layout      => c_layout,
+      g_sdb_addr    => c_sdb_address
+      )
+    port map(
+      clk_sys_i => clk_sys_i,
+      rst_n_i   => rst_n_i,
+      -- Master connections (INTERCON is a slave)
+      slave_i   => cbar_slave_i,
+      slave_o   => cbar_slave_o,
+      -- Slave connections (INTERCON is a master)
+      master_i  => cbar_master_i,
+      master_o  => cbar_master_o
+      );
+
+  cbar_slave_i(2) <= ext_wb_in;
+  ext_wb_out      <= cbar_slave_o(2);
+
+  --chipscope_ila_1 : chipscope_ila
+  --  port map (
+  --    CONTROL => CONTROL,
+  --    CLK     => clk_sys_i,
+  --    TRIG0   => TRIG0,
+  --    TRIG1   => TRIG1,
+  --    TRIG2   => TRIG2,
+  --    TRIG3   => TRIG3);
+
+  --chipscope_icon_1 : chipscope_icon
+  --  port map (
+  --    CONTROL0 => CONTROL);
+
+  --TRIG0(15 downto 0)  <= ep_snk_in.dat;
+  --trig0(17 downto 16) <= ep_snk_in.adr;
+  --trig0(19 downto 18) <= ep_snk_in.sel;
+  --trig0(20) <= ep_snk_in.cyc;
+  --trig0(21) <= ep_snk_in.stb;
+  --trig0(22) <= ep_snk_in.we;
+  --trig0(23) <= ep_snk_out.ack;
+  --trig0(24) <= ep_snk_out.stall;
+  --trig0(26) <= ep_snk_out.err;
+
+  --TRIG1(15 downto 0)  <= mux_snk_in(0).dat;
+  --trig1(17 downto 16) <= mux_snk_in(0).adr;
+  --trig1(19 downto 18) <= mux_snk_in(0).sel;
+  --trig1(20) <= mux_snk_in(0).cyc;
+  --trig1(21) <= mux_snk_in(0).stb;
+  --trig1(22) <= mux_snk_in(0).we;
+  --trig1(23) <= mux_snk_out(0).ack;
+  --trig1(24) <= mux_snk_out(0).stall;
+  --trig1(26) <= mux_snk_out(0).err;
+
+  --TRIG2(15 downto 0)  <= mux_snk_in(1).dat;
+  --trig2(17 downto 16) <= mux_snk_in(1).adr;
+  --trig2(19 downto 18) <= mux_snk_in(1).sel;
+  --trig2(20) <= mux_snk_in(1).cyc;
+  --trig2(21) <= mux_snk_in(1).stb;
+  --trig2(22) <= mux_snk_in(1).we;
+  --trig2(23) <= mux_snk_out(1).ack;
+  --trig2(24) <= mux_snk_out(1).stall;
+  --trig2(26) <= mux_snk_out(1).err;
+  -----------------------------------------------------------------------------
+  -- WB Secondary Crossbar
+  -----------------------------------------------------------------------------
+  WB_SECONDARY_CON : xwb_sdb_crossbar
+    generic map(
+      g_num_masters => 1,
+      g_num_slaves  => 9,
+      g_registered  => true,
+      g_wraparound  => true,
+      g_layout      => c_secbar_layout,
+      g_sdb_addr    => c_secbar_sdb_address
+      )
+    port map(
+      clk_sys_i  => clk_sys_i,
+      rst_n_i    => rst_n_i,
+      -- Master connections (INTERCON is a slave)
+      slave_i(0) => cbar_master_o(1),
+      slave_o(0) => cbar_master_i(1),
+      -- Slave connections (INTERCON is a master)
+      master_i   => secbar_master_i,
+      master_o   => secbar_master_o
+      );
+
+  secbar_master_i(0) <= minic_wb_out;
+  minic_wb_in        <= secbar_master_o(0);
+  secbar_master_i(1) <= ep_wb_out;
+  ep_wb_in           <= secbar_master_o(1);
+  secbar_master_i(2) <= spll_wb_out;
+  spll_wb_in         <= secbar_master_o(2);
+  secbar_master_i(3) <= ppsg_wb_out;
+  ppsg_wb_in         <= secbar_master_o(3);
+  --peripherials
+  secbar_master_i(4) <= periph_slave_o(0);
+  secbar_master_i(5) <= periph_slave_o(1);
+  secbar_master_i(6) <= periph_slave_o(2);
+  secbar_master_i(8) <= periph_slave_o(3);
+  periph_slave_i(0)  <= secbar_master_o(4);
+  periph_slave_i(1)  <= secbar_master_o(5);
+  periph_slave_i(2)  <= secbar_master_o(6);
+  periph_slave_i(3)  <= secbar_master_o(8);
+
+
+  aux_adr_o <= secbar_master_o(7).adr;
+  aux_dat_o <= secbar_master_o(7).dat;
+  aux_sel_o <= secbar_master_o(7).sel;
+  aux_cyc_o <= secbar_master_o(7).cyc;
+  aux_stb_o <= secbar_master_o(7).stb;
+  aux_we_o  <= secbar_master_o(7).we;
+
+  secbar_master_i(7).dat   <= aux_dat_i;
+  secbar_master_i(7).ack   <= aux_ack_i;
+  secbar_master_i(7).stall <= aux_stall_i;
+  secbar_master_i(7).err   <= '0';
+  secbar_master_i(7).rty   <= '0';
+  secbar_master_i(7).int   <= '0';
+
+  --secbar_master_i(6).err <= '0';
+  --secbar_master_i(5).err <= '0';
+  --secbar_master_i(4).err <= '0';
+  --secbar_master_i(3).err <= '0';
+  --secbar_master_i(2).err <= '0';
+  --secbar_master_i(1).err <= '0';
+  --secbar_master_i(0).err <= '0';
+
+  --secbar_master_i(6).rty <= '0';
+  --secbar_master_i(5).rty <= '0';
+  --secbar_master_i(4).rty <= '0';
+  --secbar_master_i(3).rty <= '0';
+  --secbar_master_i(2).rty <= '0';
+  --secbar_master_i(1).rty <= '0';
+  --secbar_master_i(0).rty <= '0';
+
+
+
+  -----------------------------------------------------------------------------
+  -- WBP MUX
+  -----------------------------------------------------------------------------
+  U_WBP_Mux : xwrf_mux
+    generic map(
+      g_muxed_ports => 2)
+    port map (
+      clk_sys_i   => clk_sys_i,
+      rst_n_i     => rst_net_n,
+      ep_src_o    => ep_snk_in,
+      ep_src_i    => ep_snk_out,
+      ep_snk_o    => ep_src_in,
+      ep_snk_i    => ep_src_out,
+      mux_src_o   => mux_src_out,
+      mux_src_i   => mux_src_in,
+      mux_snk_o   => mux_snk_out,
+      mux_snk_i   => mux_snk_in,
+      mux_class_i => mux_class);
+
+  mux_class(0)  <= x"0f";
+  mux_class(1)  <= x"f0";
+  ext_src_adr_o <= mux_src_out(1).adr;
+  ext_src_dat_o <= mux_src_out(1).dat;
+  ext_src_stb_o <= mux_src_out(1).stb;
+  ext_src_cyc_o <= mux_src_out(1).cyc;
+  ext_src_sel_o <= mux_src_out(1).sel;
+  ext_src_we_o  <= '1';
+
+  mux_src_in(1).ack   <= ext_src_ack_i;
+  mux_src_in(1).stall <= ext_src_stall_i;
+  mux_src_in(1).err   <= ext_src_err_i;
+  mux_src_in(1).rty   <= '0';
+
+  mux_snk_in(1).adr <= ext_snk_adr_i;
+  mux_snk_in(1).dat <= ext_snk_dat_i;
+  mux_snk_in(1).stb <= ext_snk_stb_i;
+  mux_snk_in(1).cyc <= ext_snk_cyc_i;
+  mux_snk_in(1).sel <= ext_snk_sel_i;
+  mux_snk_in(1).we  <= ext_snk_we_i;
+
+  ext_snk_ack_o   <= mux_snk_out(1).ack;
+  ext_snk_err_o   <= mux_snk_out(1).err;
+  ext_snk_stall_o <= mux_snk_out(1).stall;
+
+  -----------------------------------------------------------------------------
+  -- External Tx Timestamping I/F
+  -----------------------------------------------------------------------------
+  txtsu_port_id_o      <= ep_txtsu_port_id;
+  txtsu_frame_id_o     <= ep_txtsu_frame_id;
+  txtsu_ts_value_o     <= ep_txtsu_ts_value;
+  txtsu_ts_incorrect_o <= ep_txtsu_ts_incorrect;
+
+  -- ts goes to external I/F
+  txtsu_stb_o          <= '1' when (ep_txtsu_stb = '1' and (ep_txtsu_frame_id /= x"0000")) else
+                          '0';
+  -- ts goes to minic
+  mnic_txtsu_stb      <=  '1' when (ep_txtsu_stb = '1' and (ep_txtsu_frame_id  = x"0000")) else
+                          '0';
+
+  ep_txtsu_ack <= txtsu_ack_i or mnic_txtsu_ack;
+
+end struct;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/wrc_diags_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/wrc_diags_pkg.vhd
new file mode 100644
index 000000000..1bedca028
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/wrc_diags_pkg.vhd
@@ -0,0 +1,134 @@
+---------------------------------------------------------------------------------------
+-- Title          : Wishbone slave core for WR Core Diagnostics
+---------------------------------------------------------------------------------------
+-- File           : wrc_diags_pkg.vhd
+-- Author         : auto-generated by wbgen2 from wrc_diags_wb.wb
+-- Created        : Mon Nov 27 13:37:56 2017
+-- Version        : 0x00000001
+-- Standard       : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_diags_wb.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package wrc_diags_wbgen2_pkg is
+  
+  
+  -- Input registers (user design -> WB slave)
+  
+  type t_wrc_diags_in_registers is record
+    ctrl_data_valid_i                        : std_logic;
+    wdiag_sstat_wr_mode_i                    : std_logic;
+    wdiag_sstat_servostate_i                 : std_logic_vector(3 downto 0);
+    wdiag_pstat_link_i                       : std_logic;
+    wdiag_pstat_locked_i                     : std_logic;
+    wdiag_ptpstat_ptpstate_i                 : std_logic_vector(7 downto 0);
+    wdiag_astat_aux_i                        : std_logic_vector(7 downto 0);
+    wdiag_txfcnt_i                           : std_logic_vector(31 downto 0);
+    wdiag_rxfcnt_i                           : std_logic_vector(31 downto 0);
+    wdiag_sec_msb_i                          : std_logic_vector(31 downto 0);
+    wdiag_sec_lsb_i                          : std_logic_vector(31 downto 0);
+    wdiag_ns_i                               : std_logic_vector(31 downto 0);
+    wdiag_mu_msb_i                           : std_logic_vector(31 downto 0);
+    wdiag_mu_lsb_i                           : std_logic_vector(31 downto 0);
+    wdiag_dms_msb_i                          : std_logic_vector(31 downto 0);
+    wdiag_dms_lsb_i                          : std_logic_vector(31 downto 0);
+    wdiag_asym_i                             : std_logic_vector(31 downto 0);
+    wdiag_cko_i                              : std_logic_vector(31 downto 0);
+    wdiag_setp_i                             : std_logic_vector(31 downto 0);
+    wdiag_ucnt_i                             : std_logic_vector(31 downto 0);
+    wdiag_temp_i                             : std_logic_vector(31 downto 0);
+    end record;
+  
+  constant c_wrc_diags_in_registers_init_value: t_wrc_diags_in_registers := (
+    ctrl_data_valid_i => '0',
+    wdiag_sstat_wr_mode_i => '0',
+    wdiag_sstat_servostate_i => (others => '0'),
+    wdiag_pstat_link_i => '0',
+    wdiag_pstat_locked_i => '0',
+    wdiag_ptpstat_ptpstate_i => (others => '0'),
+    wdiag_astat_aux_i => (others => '0'),
+    wdiag_txfcnt_i => (others => '0'),
+    wdiag_rxfcnt_i => (others => '0'),
+    wdiag_sec_msb_i => (others => '0'),
+    wdiag_sec_lsb_i => (others => '0'),
+    wdiag_ns_i => (others => '0'),
+    wdiag_mu_msb_i => (others => '0'),
+    wdiag_mu_lsb_i => (others => '0'),
+    wdiag_dms_msb_i => (others => '0'),
+    wdiag_dms_lsb_i => (others => '0'),
+    wdiag_asym_i => (others => '0'),
+    wdiag_cko_i => (others => '0'),
+    wdiag_setp_i => (others => '0'),
+    wdiag_ucnt_i => (others => '0'),
+    wdiag_temp_i => (others => '0')
+    );
+    
+    -- Output registers (WB slave -> user design)
+    
+    type t_wrc_diags_out_registers is record
+      ver_id_o                                 : std_logic_vector(31 downto 0);
+      ctrl_data_snapshot_o                     : std_logic;
+      end record;
+    
+    constant c_wrc_diags_out_registers_init_value: t_wrc_diags_out_registers := (
+      ver_id_o => (others => '0'),
+      ctrl_data_snapshot_o => '0'
+      );
+    function "or" (left, right: t_wrc_diags_in_registers) return t_wrc_diags_in_registers;
+    function f_x_to_zero (x:std_logic) return std_logic;
+    function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
+end package;
+
+package body wrc_diags_wbgen2_pkg is
+function f_x_to_zero (x:std_logic) return std_logic is
+begin
+if x = '1' then
+return '1';
+else
+return '0';
+end if;
+end function;
+function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
+variable tmp: std_logic_vector(x'length-1 downto 0);
+begin
+for i in 0 to x'length-1 loop
+if x(i) = '1' then
+tmp(i):= '1';
+else
+tmp(i):= '0';
+end if; 
+end loop; 
+return tmp;
+end function;
+function "or" (left, right: t_wrc_diags_in_registers) return t_wrc_diags_in_registers is
+variable tmp: t_wrc_diags_in_registers;
+begin
+tmp.ctrl_data_valid_i := f_x_to_zero(left.ctrl_data_valid_i) or f_x_to_zero(right.ctrl_data_valid_i);
+tmp.wdiag_sstat_wr_mode_i := f_x_to_zero(left.wdiag_sstat_wr_mode_i) or f_x_to_zero(right.wdiag_sstat_wr_mode_i);
+tmp.wdiag_sstat_servostate_i := f_x_to_zero(left.wdiag_sstat_servostate_i) or f_x_to_zero(right.wdiag_sstat_servostate_i);
+tmp.wdiag_pstat_link_i := f_x_to_zero(left.wdiag_pstat_link_i) or f_x_to_zero(right.wdiag_pstat_link_i);
+tmp.wdiag_pstat_locked_i := f_x_to_zero(left.wdiag_pstat_locked_i) or f_x_to_zero(right.wdiag_pstat_locked_i);
+tmp.wdiag_ptpstat_ptpstate_i := f_x_to_zero(left.wdiag_ptpstat_ptpstate_i) or f_x_to_zero(right.wdiag_ptpstat_ptpstate_i);
+tmp.wdiag_astat_aux_i := f_x_to_zero(left.wdiag_astat_aux_i) or f_x_to_zero(right.wdiag_astat_aux_i);
+tmp.wdiag_txfcnt_i := f_x_to_zero(left.wdiag_txfcnt_i) or f_x_to_zero(right.wdiag_txfcnt_i);
+tmp.wdiag_rxfcnt_i := f_x_to_zero(left.wdiag_rxfcnt_i) or f_x_to_zero(right.wdiag_rxfcnt_i);
+tmp.wdiag_sec_msb_i := f_x_to_zero(left.wdiag_sec_msb_i) or f_x_to_zero(right.wdiag_sec_msb_i);
+tmp.wdiag_sec_lsb_i := f_x_to_zero(left.wdiag_sec_lsb_i) or f_x_to_zero(right.wdiag_sec_lsb_i);
+tmp.wdiag_ns_i := f_x_to_zero(left.wdiag_ns_i) or f_x_to_zero(right.wdiag_ns_i);
+tmp.wdiag_mu_msb_i := f_x_to_zero(left.wdiag_mu_msb_i) or f_x_to_zero(right.wdiag_mu_msb_i);
+tmp.wdiag_mu_lsb_i := f_x_to_zero(left.wdiag_mu_lsb_i) or f_x_to_zero(right.wdiag_mu_lsb_i);
+tmp.wdiag_dms_msb_i := f_x_to_zero(left.wdiag_dms_msb_i) or f_x_to_zero(right.wdiag_dms_msb_i);
+tmp.wdiag_dms_lsb_i := f_x_to_zero(left.wdiag_dms_lsb_i) or f_x_to_zero(right.wdiag_dms_lsb_i);
+tmp.wdiag_asym_i := f_x_to_zero(left.wdiag_asym_i) or f_x_to_zero(right.wdiag_asym_i);
+tmp.wdiag_cko_i := f_x_to_zero(left.wdiag_cko_i) or f_x_to_zero(right.wdiag_cko_i);
+tmp.wdiag_setp_i := f_x_to_zero(left.wdiag_setp_i) or f_x_to_zero(right.wdiag_setp_i);
+tmp.wdiag_ucnt_i := f_x_to_zero(left.wdiag_ucnt_i) or f_x_to_zero(right.wdiag_ucnt_i);
+tmp.wdiag_temp_i := f_x_to_zero(left.wdiag_temp_i) or f_x_to_zero(right.wdiag_temp_i);
+return tmp;
+end function;
+end package body;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/wrc_diags_wb.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/wrc_diags_wb.vhd
new file mode 100644
index 000000000..99b6e9252
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/wrc_diags_wb.vhd
@@ -0,0 +1,376 @@
+---------------------------------------------------------------------------------------
+-- Title          : Wishbone slave core for WR Core Diagnostics
+---------------------------------------------------------------------------------------
+-- File           : wrc_diags_wb.vhd
+-- Author         : auto-generated by wbgen2 from wrc_diags_wb.wb
+-- Created        : Mon Nov 27 13:37:56 2017
+-- Version        : 0x00000001
+-- Standard       : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_diags_wb.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.wrc_diags_wbgen2_pkg.all;
+
+
+entity wrc_diags_wb is
+  port (
+    rst_n_i                                  : in     std_logic;
+    clk_sys_i                                : in     std_logic;
+    wb_adr_i                                 : in     std_logic_vector(4 downto 0);
+    wb_dat_i                                 : in     std_logic_vector(31 downto 0);
+    wb_dat_o                                 : out    std_logic_vector(31 downto 0);
+    wb_cyc_i                                 : in     std_logic;
+    wb_sel_i                                 : in     std_logic_vector(3 downto 0);
+    wb_stb_i                                 : in     std_logic;
+    wb_we_i                                  : in     std_logic;
+    wb_ack_o                                 : out    std_logic;
+    wb_stall_o                               : out    std_logic;
+    regs_i                                   : in     t_wrc_diags_in_registers;
+    regs_o                                   : out    t_wrc_diags_out_registers
+  );
+end wrc_diags_wb;
+
+architecture syn of wrc_diags_wb is
+
+signal wrc_diags_ver_id_int                     : std_logic_vector(31 downto 0);
+signal wrc_diags_ctrl_data_snapshot_int         : std_logic      ;
+signal ack_sreg                                 : std_logic_vector(9 downto 0);
+signal rddata_reg                               : std_logic_vector(31 downto 0);
+signal wrdata_reg                               : std_logic_vector(31 downto 0);
+signal rwaddr_reg                               : std_logic_vector(4 downto 0);
+signal ack_in_progress                          : std_logic      ;
+
+begin
+-- Some internal signals assignments
+  wrdata_reg <= wb_dat_i;
+-- 
+-- Main register bank access process.
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ack_sreg <= "0000000000";
+      ack_in_progress <= '0';
+      rddata_reg <= "00000000000000000000000000000000";
+      wrc_diags_ver_id_int <= "00000000000000000000000000000001";
+      wrc_diags_ctrl_data_snapshot_int <= '0';
+    elsif rising_edge(clk_sys_i) then
+-- advance the ACK generator shift register
+      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
+      ack_sreg(9) <= '0';
+      if (ack_in_progress = '1') then
+        if (ack_sreg(0) = '1') then
+          ack_in_progress <= '0';
+        else
+        end if;
+      else
+        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
+          case rwaddr_reg(4 downto 0) is
+          when "00000" => 
+            if (wb_we_i = '1') then
+              wrc_diags_ver_id_int <= wrdata_reg(31 downto 0);
+            end if;
+            rddata_reg(31 downto 0) <= wrc_diags_ver_id_int;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00001" => 
+            if (wb_we_i = '1') then
+              wrc_diags_ctrl_data_snapshot_int <= wrdata_reg(8);
+            end if;
+            rddata_reg(0) <= regs_i.ctrl_data_valid_i;
+            rddata_reg(8) <= wrc_diags_ctrl_data_snapshot_int;
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00010" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(0) <= regs_i.wdiag_sstat_wr_mode_i;
+            rddata_reg(11 downto 8) <= regs_i.wdiag_sstat_servostate_i;
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00011" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(0) <= regs_i.wdiag_pstat_link_i;
+            rddata_reg(1) <= regs_i.wdiag_pstat_locked_i;
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00100" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(7 downto 0) <= regs_i.wdiag_ptpstat_ptpstate_i;
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00101" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(7 downto 0) <= regs_i.wdiag_astat_aux_i;
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00110" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.wdiag_txfcnt_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00111" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.wdiag_rxfcnt_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01000" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.wdiag_sec_msb_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01001" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.wdiag_sec_lsb_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01010" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.wdiag_ns_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01011" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.wdiag_mu_msb_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01100" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.wdiag_mu_lsb_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01101" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.wdiag_dms_msb_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01110" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.wdiag_dms_lsb_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01111" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.wdiag_asym_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "10000" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.wdiag_cko_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "10001" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.wdiag_setp_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "10010" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.wdiag_ucnt_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "10011" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.wdiag_temp_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when others =>
+-- prevent the slave from hanging the bus on invalid address
+            ack_in_progress <= '1';
+            ack_sreg(0) <= '1';
+          end case;
+        end if;
+      end if;
+    end if;
+  end process;
+  
+  
+-- Drive the data output bus
+  wb_dat_o <= rddata_reg;
+-- Version identifier
+  regs_o.ver_id_o <= wrc_diags_ver_id_int;
+-- WR DIAG data valid
+-- WR DIAG data snapshot
+  regs_o.ctrl_data_snapshot_o <= wrc_diags_ctrl_data_snapshot_int;
+-- WR valid
+-- Servo State
+-- Link Status
+-- PLL Locked
+-- PTP State
+-- AUX channel
+-- Data
+-- Data
+-- Data
+-- Data
+-- Data
+-- Data
+-- Data
+-- Data
+-- Data
+-- Data
+-- Data
+-- Data
+-- Data
+-- Data
+  rwaddr_reg <= wb_adr_i;
+  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
+-- ACK signal generation. Just pass the LSB of ACK counter.
+  wb_ack_o <= ack_sreg(0);
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/wrc_periph.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/wrc_periph.vhd
new file mode 100644
index 000000000..ee6035524
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/wrc_periph.vhd
@@ -0,0 +1,520 @@
+-------------------------------------------------------------------------------
+-- Title      : WhiteRabbit PTP Core peripherials
+-- Project    : WhiteRabbit
+-------------------------------------------------------------------------------
+-- File       : wrc_periph.vhd
+-- Author     : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
+-- Company    : CERN (BE-CO-HT)
+-- Created    : 2011-04-04
+-- Last update: 2017-04-25
+-- Platform   : FPGA-generics
+-- Standard   : VHDL
+-------------------------------------------------------------------------------
+-- Description:
+-- WRC_PERIPH integrates WRC_SYSCON, UART/VUART, 1-Wire Master, WRPC_DIAGS
+-- 
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012 - 2017 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.wrcore_pkg.all;
+use work.wishbone_pkg.all;
+use work.sysc_wbgen2_pkg.all;
+use work.wrc_diags_wbgen2_pkg.all;
+
+entity wrc_periph is
+  generic(
+    g_board_name      : string  := "NA  ";
+    g_flash_secsz_kb    : integer := 256;        -- default for SVEC (M25P128)
+    g_flash_sdbfs_baddr : integer := 16#600000#; -- default for SVEC (M25P128)
+    g_phys_uart       : boolean := true;
+    g_virtual_uart    : boolean := false;
+    g_cntr_period     : integer := 62500;
+    g_mem_words       : integer := 16384;   --in 32-bit words
+    g_vuart_fifo_size : integer := 1024;
+    g_diag_id         : integer := 0;
+    g_diag_ver        : integer := 0;
+    g_diag_ro_size    : integer := 0;
+    g_diag_rw_size    : integer := 0
+    );
+  port(
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    rst_net_n_o : out std_logic;
+    rst_wrc_n_o : out std_logic;
+
+    led_red_o   : out std_logic;
+    led_green_o : out std_logic;
+    scl_o       : out std_logic;
+    scl_i       : in  std_logic;
+    sda_o       : out std_logic;
+    sda_i       : in  std_logic;
+    sfp_scl_o   : out std_logic;
+    sfp_scl_i   : in  std_logic;
+    sfp_sda_o   : out std_logic;
+    sfp_sda_i   : in  std_logic;
+    sfp_det_i   : in  std_logic;
+    memsize_i   : in  std_logic_vector(3 downto 0);
+    btn1_i      : in  std_logic;
+    btn2_i      : in  std_logic;
+    spi_sclk_o  : out std_logic;
+    spi_ncs_o   : out std_logic;
+    spi_mosi_o  : out std_logic;
+    spi_miso_i  : in  std_logic;
+
+    slave_i : in  t_wishbone_slave_in_array(0 to 3);
+    slave_o : out t_wishbone_slave_out_array(0 to 3);
+
+    uart_rxd_i : in  std_logic;
+    uart_txd_o : out std_logic;
+
+    -- 1-Wire
+    owr_pwren_o: out std_logic_vector(1 downto 0);
+    owr_en_o : out std_logic_vector(1 downto 0);
+    owr_i    : in  std_logic_vector(1 downto 0);
+
+    -- optional diagnostics from external HDL modules
+    diag_array_in  : in  t_generic_word_array(g_diag_ro_size-1 downto 0) := (others=>(others=>'0'));
+    diag_array_out : out t_generic_word_array(g_diag_rw_size-1 downto 0)
+    );
+end wrc_periph;
+
+architecture struct of wrc_periph is
+
+  function f_cnt_memsize(words : integer) return std_logic_vector is
+  begin
+    return std_logic_vector(to_unsigned(words * 4 / 1024 / 16 - 1, 4));
+    -- *4     - to get size in bytes
+    -- /1024  - to get size in kB
+    -- /16 -1 - to get size in format of MEMSIZE@sysc_hwfr register
+  end f_cnt_memsize;
+
+  function f_board_name_conv(name : string) return std_logic_vector is
+    variable ret : std_logic_vector(31 downto 0);
+  begin
+    assert (name'length= 4)
+    report "Board name has to be exactly 4 letters string" severity failure;
+    ret(31 downto 24) := std_logic_vector(to_unsigned(character'pos(name(1)), 8));
+    ret(23 downto 16) := std_logic_vector(to_unsigned(character'pos(name(2)), 8));
+    ret(15 downto  8) := std_logic_vector(to_unsigned(character'pos(name(3)), 8));
+    ret( 7 downto  0) := std_logic_vector(to_unsigned(character'pos(name(4)), 8));
+    return ret;
+  end f_board_name_conv;
+
+  signal sysc_regs_i : t_sysc_in_registers;
+  signal sysc_regs_o : t_sysc_out_registers;
+
+  signal cntr_div      : unsigned(23 downto 0);
+  signal cntr_tics     : unsigned(31 downto 0);
+  signal cntr_overflow : std_logic;
+  
+  signal rst_wrc_n_o_reg : std_logic := '1';
+  signal diag_adr : unsigned(15 downto 0);
+  signal diag_dat : std_logic_vector(31 downto 0);
+  signal diag_out_regs : t_generic_word_array(g_diag_rw_size - 1 downto 0);
+  signal diag_in       : t_generic_word_array(g_diag_ro_size + g_diag_rw_size-1 downto 0);
+  signal wrpc_diag_regs_in     : t_wrc_diags_in_registers;
+  signal wrpc_diag_regs_out    : t_wrc_diags_out_registers;
+
+begin
+
+  rst_wrc_n_o <= rst_n_i and rst_wrc_n_o_reg;
+  process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if(rst_n_i = '0') then
+        rst_net_n_o <= '0';
+        rst_wrc_n_o_reg <= '1';
+      else
+
+        if(sysc_regs_o.rstr_trig_wr_o = '1' and sysc_regs_o.rstr_trig_o = x"deadbee") then
+          rst_wrc_n_o_reg <= not sysc_regs_o.rstr_rst_o;
+        end if; 
+            
+        rst_net_n_o <= not sysc_regs_o.gpsr_net_rst_o;
+      end if; 
+    end if; 
+  end process;
+  
+  -------------------------------------
+  -- LEDs
+  -------------------------------------
+  process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if(sysc_regs_o.gpsr_led_link_o = '1') then
+        led_red_o <= '1';
+      elsif(sysc_regs_o.gpcr_led_link_o = '1') then
+        led_red_o <= '0';
+      end if;
+
+      if(sysc_regs_o.gpsr_led_stat_o = '1') then
+        led_green_o <= '1';
+      elsif(sysc_regs_o.gpcr_led_stat_o = '1') then
+        led_green_o <= '0';
+      end if;
+    end if;
+  end process;
+
+  -------------------------------------
+  -- buttons
+  -------------------------------------
+  sysc_regs_i.gpsr_btn1_i <= btn1_i;
+  sysc_regs_i.gpsr_btn2_i <= btn2_i;
+
+  -------------------------------------
+  -- MEMSIZE
+  -------------------------------------
+  sysc_regs_i.hwfr_memsize_i(3 downto 0) <= f_cnt_memsize(g_mem_words);
+
+  -------------------------------------
+  -- BOARD NAME and Flash info
+  -------------------------------------
+  sysc_regs_i.hwir_name_i         <= f_board_name_conv(g_board_name);
+  sysc_regs_i.hwfr_storage_sec_i  <= std_logic_vector(to_unsigned(g_flash_secsz_kb, 16));
+  sysc_regs_i.hwfr_storage_type_i <= "00";  -- for now these parameters are only for Flash
+  sysc_regs_i.sdbfs_baddr_i       <= std_logic_vector(to_unsigned(g_flash_sdbfs_baddr, 32));
+
+  -------------------------------------
+  -- TIMER
+  -------------------------------------
+  sysc_regs_i.tvr_i      <= std_logic_vector(cntr_tics);
+  sysc_regs_i.tcr_tdiv_i <= (others => '0');
+
+  process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if(rst_n_i = '0') then
+        cntr_div      <= (others => '0');
+        cntr_overflow <= '0';
+      elsif(sysc_regs_o.tcr_enable_o = '1') then
+        if(cntr_div = g_cntr_period-1) then
+          cntr_div      <= (others => '0');
+          cntr_overflow <= '1';
+        else
+          cntr_div      <= cntr_div + 1;
+          cntr_overflow <= '0';
+        end if;
+      end if;
+    end if;
+  end process;
+
+  --msec counter
+  process(clk_sys_i)
+  begin
+    if(rising_edge(clk_sys_i)) then
+      if(rst_n_i = '0') then
+        cntr_tics <= (others => '0');
+      elsif(cntr_overflow = '1') then
+        cntr_tics <= cntr_tics + 1;
+      end if;
+    end if;
+  end process;
+
+  -------------------------------------
+  -- I2C - FMC
+  -------------------------------------
+  p_drive_i2c : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        scl_o <= '1';
+        sda_o <= '1';
+      else
+        if(sysc_regs_o.gpsr_fmc_sda_load_o = '1' and sysc_regs_o.gpsr_fmc_sda_o = '1') then
+          sda_o <= '1';
+        elsif(sysc_regs_o.gpcr_fmc_sda_o = '1') then
+          sda_o <= '0';
+        end if;
+
+        if(sysc_regs_o.gpsr_fmc_scl_load_o = '1' and sysc_regs_o.gpsr_fmc_scl_o = '1') then
+          scl_o <= '1';
+        elsif(sysc_regs_o.gpcr_fmc_scl_o = '1') then
+          scl_o <= '0';
+        end if;
+      end if;
+    end if;
+  end process;
+
+  sysc_regs_i.gpsr_fmc_sda_i <= sda_i;
+  sysc_regs_i.gpsr_fmc_scl_i <= scl_i;
+
+  -------------------------------------
+  -- I2C - SFP
+  -------------------------------------
+  p_drive_sfpi2c : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        sfp_scl_o <= '1';
+        sfp_sda_o <= '1';
+      else
+        if(sysc_regs_o.gpsr_sfp_sda_load_o = '1' and sysc_regs_o.gpsr_sfp_sda_o = '1') then
+          sfp_sda_o <= '1';
+        elsif(sysc_regs_o.gpcr_sfp_sda_o = '1') then
+          sfp_sda_o <= '0';
+        end if;
+
+        if(sysc_regs_o.gpsr_sfp_scl_load_o = '1' and sysc_regs_o.gpsr_sfp_scl_o = '1') then
+          sfp_scl_o <= '1';
+        elsif(sysc_regs_o.gpcr_sfp_scl_o = '1') then
+          sfp_scl_o <= '0';
+        end if;
+      end if;
+    end if;
+  end process;
+
+  sysc_regs_i.gpsr_sfp_sda_i <= sfp_sda_i;
+  sysc_regs_i.gpsr_sfp_scl_i <= sfp_scl_i;
+
+  sysc_regs_i.gpsr_sfp_det_i <= sfp_det_i;
+
+  -------------------------------------
+  -- SPI - Flash
+  -------------------------------------
+  p_drive_spi: process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        spi_sclk_o  <= '0';
+        spi_mosi_o  <= '0';
+        spi_ncs_o   <= '1';
+      else
+        if(sysc_regs_o.gpsr_spi_sclk_load_o = '1' and sysc_regs_o.gpsr_spi_sclk_o = '1') then
+          spi_sclk_o <= '1';
+        elsif(sysc_regs_o.gpcr_spi_sclk_o = '1') then
+          spi_sclk_o <= '0';
+        end if;
+
+        if(sysc_regs_o.gpsr_spi_ncs_load_o = '1' and sysc_regs_o.gpsr_spi_ncs_o = '1') then
+          spi_ncs_o <= '1';
+        elsif(sysc_regs_o.gpcr_spi_cs_o = '1') then
+          spi_ncs_o <= '0';
+        end if;
+
+        if(sysc_regs_o.gpsr_spi_mosi_load_o = '1' and sysc_regs_o.gpsr_spi_mosi_o = '1') then
+          spi_mosi_o <= '1';
+        elsif(sysc_regs_o.gpcr_spi_mosi_o = '1') then
+          spi_mosi_o <= '0';
+        end if;
+      end if;
+    end if;
+  end process;
+  sysc_regs_i.gpsr_spi_sclk_i <= '0';
+  sysc_regs_i.gpsr_spi_ncs_i  <= '0';
+  sysc_regs_i.gpsr_spi_mosi_i <= '0';
+  sysc_regs_i.gpsr_spi_miso_i <= spi_miso_i;
+
+
+  -------------------------------------
+  -- DIAG to/from external modules
+  -------------------------------------
+  -- first, provide all the constants
+  sysc_regs_i.diag_info_id_i  <= std_logic_vector(to_unsigned(g_diag_id, 16));
+  sysc_regs_i.diag_info_ver_i <= std_logic_vector(to_unsigned(g_diag_ver, 16));
+  sysc_regs_i.diag_nw_ro_i  <= std_logic_vector(to_unsigned(g_diag_ro_size, 16));
+  sysc_regs_i.diag_nw_rw_i <= std_logic_vector(to_unsigned(g_diag_rw_size, 16));
+
+  diag_array_out <= diag_out_regs;
+  -- r/w registers can be also read
+  diag_in(g_diag_rw_size - 1 downto 0) <= diag_out_regs;
+  -- r/o array after r/w registers for reading
+  diag_in(g_diag_ro_size + g_diag_rw_size-1 downto g_diag_rw_size) <= diag_array_in;
+
+  p_diag_rw: process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        diag_adr <= (others=>'0');
+        diag_dat <= (others=>'0');
+      else
+        if sysc_regs_o.diag_cr_adr_load_o = '1' then
+          diag_adr <= unsigned(sysc_regs_o.diag_cr_adr_o);
+        end if;
+        if sysc_regs_o.diag_dat_load_o = '1' then
+          diag_dat <= sysc_regs_o.diag_dat_o;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  sysc_regs_i.diag_cr_adr_i    <= std_logic_vector(diag_adr);
+  GEN_DIAG_NODAT: if g_diag_rw_size = 0 and g_diag_ro_size = 0 generate
+    sysc_regs_i.diag_dat_i <= (others=>'0');
+  end generate;
+  GEN_DIAG_DAT: if g_diag_rw_size /= 0 or g_diag_ro_size /= 0 generate
+    sysc_regs_i.diag_dat_i <= diag_in(to_integer(diag_adr));
+  end generate;
+
+  -- Write request for each r/w register
+  GEN_DIAG_W: if g_diag_rw_size > 0 generate
+    GEN_LOOP: for I in 0 to g_diag_rw_size-1 generate
+
+      process(clk_sys_i)
+      begin
+        if rising_edge(clk_sys_i) then
+          if rst_n_i = '0' then
+            diag_out_regs(I) <= (others=>'0');
+          elsif sysc_regs_o.diag_cr_adr_load_o = '1' and sysc_regs_o.diag_cr_rw_o = '1' and
+            to_integer(unsigned(sysc_regs_o.diag_cr_adr_o)) = I then
+              diag_out_regs(I) <= diag_dat;
+          end if;
+        end if;
+      end process;
+
+    end generate;
+  end generate;
+
+  GEN_NODIAG_W: if g_diag_rw_size = 0 generate
+    diag_array_out <= (others=>(others=>'0'));
+  end generate;
+
+  ----------------------------------------
+  -- SYSCON
+  ----------------------------------------
+  SYSCON : entity work.wrc_syscon_wb
+    port map (
+      rst_n_i    => rst_n_i,
+      clk_sys_i  => clk_sys_i,
+      wb_adr_i   => slave_i(0).adr(6 downto 2), -- shift address for word addressing
+      wb_dat_i   => slave_i(0).dat,
+      wb_dat_o   => slave_o(0).dat,
+      wb_cyc_i   => slave_i(0).cyc,
+      wb_sel_i   => slave_i(0).sel,
+      wb_stb_i   => slave_i(0).stb,
+      wb_we_i    => slave_i(0).we,
+      wb_ack_o   => slave_o(0).ack,
+      wb_stall_o => slave_o(0).stall,
+      regs_i     => sysc_regs_i,
+      regs_o     => sysc_regs_o);
+
+  slave_o(0).err <= '0';
+  slave_o(0).rty <= '0';
+  slave_o(0).int <= '0';
+
+  --------------------------------------
+  -- UART
+  --------------------------------------
+  UART : xwb_simple_uart
+    generic map(
+      g_with_virtual_uart   => g_virtual_uart,
+      g_with_physical_uart  => g_phys_uart,
+      g_interface_mode      => PIPELINED,
+      g_address_granularity => BYTE,
+      g_vuart_fifo_size     => g_vuart_fifo_size
+      )
+    port map(
+      clk_sys_i => clk_sys_i,
+      rst_n_i   => rst_n_i,
+
+      -- Wishbone
+      slave_i => slave_i(1),
+      slave_o => slave_o(1),
+      desc_o  => open,
+
+      uart_rxd_i => uart_rxd_i,
+      uart_txd_o => uart_txd_o
+      );
+
+  --------------------------------------
+  -- 1-WIRE
+  --------------------------------------
+  ONEWIRE : xwb_onewire_master
+    generic map(
+      g_interface_mode      => PIPELINED,
+      g_address_granularity => BYTE,
+      g_num_ports           => 2,
+      g_ow_btp_normal       => "5.0",
+      g_ow_btp_overdrive    => "1.0"
+      )
+    port map(
+      clk_sys_i => clk_sys_i,
+      rst_n_i   => rst_n_i,
+
+      -- Wishbone
+      slave_i => slave_i(2),
+      slave_o => slave_o(2),
+      desc_o  => open,
+
+      owr_pwren_o => owr_pwren_o,
+      owr_en_o => owr_en_o,
+      owr_i    => owr_i
+      );
+
+  --------------------------------------
+  -- WRPC Diags
+  --------------------------------------
+
+  -- access through WB (PCI/VME/application) to diagnostics of WRPC
+  DIAGS: xwr_diags_wb
+    generic map(
+      g_interface_mode      => PIPELINED,
+      g_address_granularity => BYTE
+    )
+    port map(
+      rst_n_i   => rst_n_i,
+      clk_sys_i => clk_sys_i,
+
+      slave_i   => slave_i(3),
+      slave_o   => slave_o(3),
+
+      regs_i    => wrpc_diag_regs_in,
+      regs_o    => wrpc_diag_regs_out
+    );
+
+   -- the information written to syscon WB registers by LM32 are available to the
+   -- user via diag WB registers
+   -- It might look strange that we use two WB modules for that. Since both LM32
+   -- and user application need to access these registers through the same
+   -- wishbone interface we would needed these registers to be R/W. By creating
+   -- another module (xwr_diags_wb) we make read-only registers to be read by
+   -- the external tool. We want to minimize the possibility of user application
+   -- overwriting these values, thus we want them to be read-only.
+   sysc_regs_i.wdiag_ctrl_data_snapshot_i      <= wrpc_diag_regs_out.ctrl_data_snapshot_o;
+   wrpc_diag_regs_in.ctrl_data_valid_i         <= sysc_regs_o.wdiag_ctrl_data_valid_o;
+   wrpc_diag_regs_in.wdiag_sstat_wr_mode_i     <= sysc_regs_o.wdiag_sstat_wr_mode_o;
+   wrpc_diag_regs_in.wdiag_sstat_servostate_i  <= sysc_regs_o.wdiag_sstat_servostate_o;
+   wrpc_diag_regs_in.wdiag_pstat_link_i        <= sysc_regs_o.wdiag_pstat_link_o;
+   wrpc_diag_regs_in.wdiag_pstat_locked_i      <= sysc_regs_o.wdiag_pstat_locked_o;
+   wrpc_diag_regs_in.wdiag_ptpstat_ptpstate_i  <= sysc_regs_o.wdiag_ptpstat_ptpstate_o;
+   wrpc_diag_regs_in.wdiag_astat_aux_i         <= sysc_regs_o.wdiag_astat_aux_o;
+   wrpc_diag_regs_in.wdiag_txfcnt_i            <= sysc_regs_o.wdiag_txfcnt_o;
+   wrpc_diag_regs_in.wdiag_rxfcnt_i            <= sysc_regs_o.wdiag_rxfcnt_o;
+   wrpc_diag_regs_in.wdiag_sec_msb_i           <= sysc_regs_o.wdiag_sec_msb_o;
+   wrpc_diag_regs_in.wdiag_sec_lsb_i           <= sysc_regs_o.wdiag_sec_lsb_o;
+   wrpc_diag_regs_in.wdiag_ns_i                <= sysc_regs_o.wdiag_ns_o;
+   wrpc_diag_regs_in.wdiag_mu_msb_i            <= sysc_regs_o.wdiag_mu_msb_o;
+   wrpc_diag_regs_in.wdiag_mu_lsb_i            <= sysc_regs_o.wdiag_mu_lsb_o;
+   wrpc_diag_regs_in.wdiag_dms_msb_i           <= sysc_regs_o.wdiag_dms_msb_o;
+   wrpc_diag_regs_in.wdiag_dms_lsb_i           <= sysc_regs_o.wdiag_dms_lsb_o;
+   wrpc_diag_regs_in.wdiag_asym_i              <= sysc_regs_o.wdiag_asym_o;
+   wrpc_diag_regs_in.wdiag_cko_i               <= sysc_regs_o.wdiag_cko_o;
+   wrpc_diag_regs_in.wdiag_setp_i              <= sysc_regs_o.wdiag_setp_o;
+   wrpc_diag_regs_in.wdiag_ucnt_i              <= sysc_regs_o.wdiag_ucnt_o;
+   wrpc_diag_regs_in.wdiag_temp_i              <= sysc_regs_o.wdiag_temp_o;
+
+end struct;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/wrc_syscon_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/wrc_syscon_pkg.vhd
new file mode 100644
index 000000000..9b33530ce
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/wrc_syscon_pkg.vhd
@@ -0,0 +1,253 @@
+---------------------------------------------------------------------------------------
+-- Title          : Wishbone slave core for WR Core System Controller
+---------------------------------------------------------------------------------------
+-- File           : wrc_syscon_pkg.vhd
+-- Author         : auto-generated by wbgen2 from wrc_syscon_wb.wb
+-- Created        : Mon Nov 27 13:37:56 2017
+-- Standard       : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package sysc_wbgen2_pkg is
+  
+  
+  -- Input registers (user design -> WB slave)
+  
+  type t_sysc_in_registers is record
+    gpsr_fmc_scl_i                           : std_logic;
+    gpsr_fmc_sda_i                           : std_logic;
+    gpsr_btn1_i                              : std_logic;
+    gpsr_btn2_i                              : std_logic;
+    gpsr_sfp_det_i                           : std_logic;
+    gpsr_sfp_scl_i                           : std_logic;
+    gpsr_sfp_sda_i                           : std_logic;
+    gpsr_spi_sclk_i                          : std_logic;
+    gpsr_spi_ncs_i                           : std_logic;
+    gpsr_spi_mosi_i                          : std_logic;
+    gpsr_spi_miso_i                          : std_logic;
+    hwfr_memsize_i                           : std_logic_vector(3 downto 0);
+    hwfr_storage_type_i                      : std_logic_vector(1 downto 0);
+    hwfr_storage_sec_i                       : std_logic_vector(15 downto 0);
+    hwir_name_i                              : std_logic_vector(31 downto 0);
+    sdbfs_baddr_i                            : std_logic_vector(31 downto 0);
+    tcr_tdiv_i                               : std_logic_vector(11 downto 0);
+    tvr_i                                    : std_logic_vector(31 downto 0);
+    diag_info_ver_i                          : std_logic_vector(15 downto 0);
+    diag_info_id_i                           : std_logic_vector(15 downto 0);
+    diag_nw_rw_i                             : std_logic_vector(15 downto 0);
+    diag_nw_ro_i                             : std_logic_vector(15 downto 0);
+    diag_cr_adr_i                            : std_logic_vector(15 downto 0);
+    diag_dat_i                               : std_logic_vector(31 downto 0);
+    wdiag_ctrl_data_snapshot_i               : std_logic;
+    end record;
+  
+  constant c_sysc_in_registers_init_value: t_sysc_in_registers := (
+    gpsr_fmc_scl_i => '0',
+    gpsr_fmc_sda_i => '0',
+    gpsr_btn1_i => '0',
+    gpsr_btn2_i => '0',
+    gpsr_sfp_det_i => '0',
+    gpsr_sfp_scl_i => '0',
+    gpsr_sfp_sda_i => '0',
+    gpsr_spi_sclk_i => '0',
+    gpsr_spi_ncs_i => '0',
+    gpsr_spi_mosi_i => '0',
+    gpsr_spi_miso_i => '0',
+    hwfr_memsize_i => (others => '0'),
+    hwfr_storage_type_i => (others => '0'),
+    hwfr_storage_sec_i => (others => '0'),
+    hwir_name_i => (others => '0'),
+    sdbfs_baddr_i => (others => '0'),
+    tcr_tdiv_i => (others => '0'),
+    tvr_i => (others => '0'),
+    diag_info_ver_i => (others => '0'),
+    diag_info_id_i => (others => '0'),
+    diag_nw_rw_i => (others => '0'),
+    diag_nw_ro_i => (others => '0'),
+    diag_cr_adr_i => (others => '0'),
+    diag_dat_i => (others => '0'),
+    wdiag_ctrl_data_snapshot_i => '0'
+    );
+    
+    -- Output registers (WB slave -> user design)
+    
+    type t_sysc_out_registers is record
+      rstr_trig_o                              : std_logic_vector(27 downto 0);
+      rstr_trig_wr_o                           : std_logic;
+      rstr_rst_o                               : std_logic;
+      gpsr_led_stat_o                          : std_logic;
+      gpsr_led_link_o                          : std_logic;
+      gpsr_fmc_scl_o                           : std_logic;
+      gpsr_fmc_scl_load_o                      : std_logic;
+      gpsr_fmc_sda_o                           : std_logic;
+      gpsr_fmc_sda_load_o                      : std_logic;
+      gpsr_net_rst_o                           : std_logic;
+      gpsr_sfp_scl_o                           : std_logic;
+      gpsr_sfp_scl_load_o                      : std_logic;
+      gpsr_sfp_sda_o                           : std_logic;
+      gpsr_sfp_sda_load_o                      : std_logic;
+      gpsr_spi_sclk_o                          : std_logic;
+      gpsr_spi_sclk_load_o                     : std_logic;
+      gpsr_spi_ncs_o                           : std_logic;
+      gpsr_spi_ncs_load_o                      : std_logic;
+      gpsr_spi_mosi_o                          : std_logic;
+      gpsr_spi_mosi_load_o                     : std_logic;
+      gpcr_led_stat_o                          : std_logic;
+      gpcr_led_link_o                          : std_logic;
+      gpcr_fmc_scl_o                           : std_logic;
+      gpcr_fmc_sda_o                           : std_logic;
+      gpcr_sfp_scl_o                           : std_logic;
+      gpcr_sfp_sda_o                           : std_logic;
+      gpcr_spi_sclk_o                          : std_logic;
+      gpcr_spi_cs_o                            : std_logic;
+      gpcr_spi_mosi_o                          : std_logic;
+      tcr_enable_o                             : std_logic;
+      diag_cr_adr_o                            : std_logic_vector(15 downto 0);
+      diag_cr_adr_load_o                       : std_logic;
+      diag_cr_rw_o                             : std_logic;
+      diag_dat_o                               : std_logic_vector(31 downto 0);
+      diag_dat_load_o                          : std_logic;
+      wdiag_ctrl_data_valid_o                  : std_logic;
+      wdiag_sstat_wr_mode_o                    : std_logic;
+      wdiag_sstat_servostate_o                 : std_logic_vector(3 downto 0);
+      wdiag_pstat_link_o                       : std_logic;
+      wdiag_pstat_locked_o                     : std_logic;
+      wdiag_ptpstat_ptpstate_o                 : std_logic_vector(7 downto 0);
+      wdiag_astat_aux_o                        : std_logic_vector(7 downto 0);
+      wdiag_txfcnt_o                           : std_logic_vector(31 downto 0);
+      wdiag_rxfcnt_o                           : std_logic_vector(31 downto 0);
+      wdiag_sec_msb_o                          : std_logic_vector(31 downto 0);
+      wdiag_sec_lsb_o                          : std_logic_vector(31 downto 0);
+      wdiag_ns_o                               : std_logic_vector(31 downto 0);
+      wdiag_mu_msb_o                           : std_logic_vector(31 downto 0);
+      wdiag_mu_lsb_o                           : std_logic_vector(31 downto 0);
+      wdiag_dms_msb_o                          : std_logic_vector(31 downto 0);
+      wdiag_dms_lsb_o                          : std_logic_vector(31 downto 0);
+      wdiag_asym_o                             : std_logic_vector(31 downto 0);
+      wdiag_cko_o                              : std_logic_vector(31 downto 0);
+      wdiag_setp_o                             : std_logic_vector(31 downto 0);
+      wdiag_ucnt_o                             : std_logic_vector(31 downto 0);
+      wdiag_temp_o                             : std_logic_vector(31 downto 0);
+      end record;
+    
+    constant c_sysc_out_registers_init_value: t_sysc_out_registers := (
+      rstr_trig_o => (others => '0'),
+      rstr_trig_wr_o => '0',
+      rstr_rst_o => '0',
+      gpsr_led_stat_o => '0',
+      gpsr_led_link_o => '0',
+      gpsr_fmc_scl_o => '0',
+      gpsr_fmc_scl_load_o => '0',
+      gpsr_fmc_sda_o => '0',
+      gpsr_fmc_sda_load_o => '0',
+      gpsr_net_rst_o => '0',
+      gpsr_sfp_scl_o => '0',
+      gpsr_sfp_scl_load_o => '0',
+      gpsr_sfp_sda_o => '0',
+      gpsr_sfp_sda_load_o => '0',
+      gpsr_spi_sclk_o => '0',
+      gpsr_spi_sclk_load_o => '0',
+      gpsr_spi_ncs_o => '0',
+      gpsr_spi_ncs_load_o => '0',
+      gpsr_spi_mosi_o => '0',
+      gpsr_spi_mosi_load_o => '0',
+      gpcr_led_stat_o => '0',
+      gpcr_led_link_o => '0',
+      gpcr_fmc_scl_o => '0',
+      gpcr_fmc_sda_o => '0',
+      gpcr_sfp_scl_o => '0',
+      gpcr_sfp_sda_o => '0',
+      gpcr_spi_sclk_o => '0',
+      gpcr_spi_cs_o => '0',
+      gpcr_spi_mosi_o => '0',
+      tcr_enable_o => '0',
+      diag_cr_adr_o => (others => '0'),
+      diag_cr_adr_load_o => '0',
+      diag_cr_rw_o => '0',
+      diag_dat_o => (others => '0'),
+      diag_dat_load_o => '0',
+      wdiag_ctrl_data_valid_o => '0',
+      wdiag_sstat_wr_mode_o => '0',
+      wdiag_sstat_servostate_o => (others => '0'),
+      wdiag_pstat_link_o => '0',
+      wdiag_pstat_locked_o => '0',
+      wdiag_ptpstat_ptpstate_o => (others => '0'),
+      wdiag_astat_aux_o => (others => '0'),
+      wdiag_txfcnt_o => (others => '0'),
+      wdiag_rxfcnt_o => (others => '0'),
+      wdiag_sec_msb_o => (others => '0'),
+      wdiag_sec_lsb_o => (others => '0'),
+      wdiag_ns_o => (others => '0'),
+      wdiag_mu_msb_o => (others => '0'),
+      wdiag_mu_lsb_o => (others => '0'),
+      wdiag_dms_msb_o => (others => '0'),
+      wdiag_dms_lsb_o => (others => '0'),
+      wdiag_asym_o => (others => '0'),
+      wdiag_cko_o => (others => '0'),
+      wdiag_setp_o => (others => '0'),
+      wdiag_ucnt_o => (others => '0'),
+      wdiag_temp_o => (others => '0')
+      );
+    function "or" (left, right: t_sysc_in_registers) return t_sysc_in_registers;
+    function f_x_to_zero (x:std_logic) return std_logic;
+    function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
+end package;
+
+package body sysc_wbgen2_pkg is
+function f_x_to_zero (x:std_logic) return std_logic is
+begin
+if x = '1' then
+return '1';
+else
+return '0';
+end if;
+end function;
+function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
+variable tmp: std_logic_vector(x'length-1 downto 0);
+begin
+for i in 0 to x'length-1 loop
+if x(i) = '1' then
+tmp(i):= '1';
+else
+tmp(i):= '0';
+end if; 
+end loop; 
+return tmp;
+end function;
+function "or" (left, right: t_sysc_in_registers) return t_sysc_in_registers is
+variable tmp: t_sysc_in_registers;
+begin
+tmp.gpsr_fmc_scl_i := f_x_to_zero(left.gpsr_fmc_scl_i) or f_x_to_zero(right.gpsr_fmc_scl_i);
+tmp.gpsr_fmc_sda_i := f_x_to_zero(left.gpsr_fmc_sda_i) or f_x_to_zero(right.gpsr_fmc_sda_i);
+tmp.gpsr_btn1_i := f_x_to_zero(left.gpsr_btn1_i) or f_x_to_zero(right.gpsr_btn1_i);
+tmp.gpsr_btn2_i := f_x_to_zero(left.gpsr_btn2_i) or f_x_to_zero(right.gpsr_btn2_i);
+tmp.gpsr_sfp_det_i := f_x_to_zero(left.gpsr_sfp_det_i) or f_x_to_zero(right.gpsr_sfp_det_i);
+tmp.gpsr_sfp_scl_i := f_x_to_zero(left.gpsr_sfp_scl_i) or f_x_to_zero(right.gpsr_sfp_scl_i);
+tmp.gpsr_sfp_sda_i := f_x_to_zero(left.gpsr_sfp_sda_i) or f_x_to_zero(right.gpsr_sfp_sda_i);
+tmp.gpsr_spi_sclk_i := f_x_to_zero(left.gpsr_spi_sclk_i) or f_x_to_zero(right.gpsr_spi_sclk_i);
+tmp.gpsr_spi_ncs_i := f_x_to_zero(left.gpsr_spi_ncs_i) or f_x_to_zero(right.gpsr_spi_ncs_i);
+tmp.gpsr_spi_mosi_i := f_x_to_zero(left.gpsr_spi_mosi_i) or f_x_to_zero(right.gpsr_spi_mosi_i);
+tmp.gpsr_spi_miso_i := f_x_to_zero(left.gpsr_spi_miso_i) or f_x_to_zero(right.gpsr_spi_miso_i);
+tmp.hwfr_memsize_i := f_x_to_zero(left.hwfr_memsize_i) or f_x_to_zero(right.hwfr_memsize_i);
+tmp.hwfr_storage_type_i := f_x_to_zero(left.hwfr_storage_type_i) or f_x_to_zero(right.hwfr_storage_type_i);
+tmp.hwfr_storage_sec_i := f_x_to_zero(left.hwfr_storage_sec_i) or f_x_to_zero(right.hwfr_storage_sec_i);
+tmp.hwir_name_i := f_x_to_zero(left.hwir_name_i) or f_x_to_zero(right.hwir_name_i);
+tmp.sdbfs_baddr_i := f_x_to_zero(left.sdbfs_baddr_i) or f_x_to_zero(right.sdbfs_baddr_i);
+tmp.tcr_tdiv_i := f_x_to_zero(left.tcr_tdiv_i) or f_x_to_zero(right.tcr_tdiv_i);
+tmp.tvr_i := f_x_to_zero(left.tvr_i) or f_x_to_zero(right.tvr_i);
+tmp.diag_info_ver_i := f_x_to_zero(left.diag_info_ver_i) or f_x_to_zero(right.diag_info_ver_i);
+tmp.diag_info_id_i := f_x_to_zero(left.diag_info_id_i) or f_x_to_zero(right.diag_info_id_i);
+tmp.diag_nw_rw_i := f_x_to_zero(left.diag_nw_rw_i) or f_x_to_zero(right.diag_nw_rw_i);
+tmp.diag_nw_ro_i := f_x_to_zero(left.diag_nw_ro_i) or f_x_to_zero(right.diag_nw_ro_i);
+tmp.diag_cr_adr_i := f_x_to_zero(left.diag_cr_adr_i) or f_x_to_zero(right.diag_cr_adr_i);
+tmp.diag_dat_i := f_x_to_zero(left.diag_dat_i) or f_x_to_zero(right.diag_dat_i);
+tmp.wdiag_ctrl_data_snapshot_i := f_x_to_zero(left.wdiag_ctrl_data_snapshot_i) or f_x_to_zero(right.wdiag_ctrl_data_snapshot_i);
+return tmp;
+end function;
+end package body;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/wrc_syscon_wb.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/wrc_syscon_wb.vhd
new file mode 100644
index 000000000..82bfb0e66
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/wrc_syscon_wb.vhd
@@ -0,0 +1,975 @@
+---------------------------------------------------------------------------------------
+-- Title          : Wishbone slave core for WR Core System Controller
+---------------------------------------------------------------------------------------
+-- File           : wrc_syscon_wb.vhd
+-- Author         : auto-generated by wbgen2 from wrc_syscon_wb.wb
+-- Created        : Mon Nov 27 13:37:56 2017
+-- Standard       : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.sysc_wbgen2_pkg.all;
+
+
+entity wrc_syscon_wb is
+  port (
+    rst_n_i                                  : in     std_logic;
+    clk_sys_i                                : in     std_logic;
+    wb_adr_i                                 : in     std_logic_vector(4 downto 0);
+    wb_dat_i                                 : in     std_logic_vector(31 downto 0);
+    wb_dat_o                                 : out    std_logic_vector(31 downto 0);
+    wb_cyc_i                                 : in     std_logic;
+    wb_sel_i                                 : in     std_logic_vector(3 downto 0);
+    wb_stb_i                                 : in     std_logic;
+    wb_we_i                                  : in     std_logic;
+    wb_ack_o                                 : out    std_logic;
+    wb_stall_o                               : out    std_logic;
+    regs_i                                   : in     t_sysc_in_registers;
+    regs_o                                   : out    t_sysc_out_registers
+  );
+end wrc_syscon_wb;
+
+architecture syn of wrc_syscon_wb is
+
+signal sysc_rstr_rst_int                        : std_logic      ;
+signal sysc_gpsr_led_stat_dly0                  : std_logic      ;
+signal sysc_gpsr_led_stat_int                   : std_logic      ;
+signal sysc_gpsr_led_link_dly0                  : std_logic      ;
+signal sysc_gpsr_led_link_int                   : std_logic      ;
+signal sysc_gpsr_net_rst_dly0                   : std_logic      ;
+signal sysc_gpsr_net_rst_int                    : std_logic      ;
+signal sysc_gpcr_led_stat_dly0                  : std_logic      ;
+signal sysc_gpcr_led_stat_int                   : std_logic      ;
+signal sysc_gpcr_led_link_dly0                  : std_logic      ;
+signal sysc_gpcr_led_link_int                   : std_logic      ;
+signal sysc_gpcr_fmc_scl_dly0                   : std_logic      ;
+signal sysc_gpcr_fmc_scl_int                    : std_logic      ;
+signal sysc_gpcr_fmc_sda_dly0                   : std_logic      ;
+signal sysc_gpcr_fmc_sda_int                    : std_logic      ;
+signal sysc_gpcr_sfp_scl_dly0                   : std_logic      ;
+signal sysc_gpcr_sfp_scl_int                    : std_logic      ;
+signal sysc_gpcr_sfp_sda_dly0                   : std_logic      ;
+signal sysc_gpcr_sfp_sda_int                    : std_logic      ;
+signal sysc_gpcr_spi_sclk_dly0                  : std_logic      ;
+signal sysc_gpcr_spi_sclk_int                   : std_logic      ;
+signal sysc_gpcr_spi_cs_dly0                    : std_logic      ;
+signal sysc_gpcr_spi_cs_int                     : std_logic      ;
+signal sysc_gpcr_spi_mosi_dly0                  : std_logic      ;
+signal sysc_gpcr_spi_mosi_int                   : std_logic      ;
+signal sysc_tcr_enable_int                      : std_logic      ;
+signal sysc_diag_cr_rw_int                      : std_logic      ;
+signal sysc_wdiag_ctrl_data_valid_int           : std_logic      ;
+signal sysc_wdiag_sstat_wr_mode_int             : std_logic      ;
+signal sysc_wdiag_sstat_servostate_int          : std_logic_vector(3 downto 0);
+signal sysc_wdiag_pstat_link_int                : std_logic      ;
+signal sysc_wdiag_pstat_locked_int              : std_logic      ;
+signal sysc_wdiag_ptpstat_ptpstate_int          : std_logic_vector(7 downto 0);
+signal sysc_wdiag_astat_aux_int                 : std_logic_vector(7 downto 0);
+signal sysc_wdiag_txfcnt_int                    : std_logic_vector(31 downto 0);
+signal sysc_wdiag_rxfcnt_int                    : std_logic_vector(31 downto 0);
+signal sysc_wdiag_sec_msb_int                   : std_logic_vector(31 downto 0);
+signal sysc_wdiag_sec_lsb_int                   : std_logic_vector(31 downto 0);
+signal sysc_wdiag_ns_int                        : std_logic_vector(31 downto 0);
+signal sysc_wdiag_mu_msb_int                    : std_logic_vector(31 downto 0);
+signal sysc_wdiag_mu_lsb_int                    : std_logic_vector(31 downto 0);
+signal sysc_wdiag_dms_msb_int                   : std_logic_vector(31 downto 0);
+signal sysc_wdiag_dms_lsb_int                   : std_logic_vector(31 downto 0);
+signal sysc_wdiag_asym_int                      : std_logic_vector(31 downto 0);
+signal sysc_wdiag_cko_int                       : std_logic_vector(31 downto 0);
+signal sysc_wdiag_setp_int                      : std_logic_vector(31 downto 0);
+signal sysc_wdiag_ucnt_int                      : std_logic_vector(31 downto 0);
+signal sysc_wdiag_temp_int                      : std_logic_vector(31 downto 0);
+signal ack_sreg                                 : std_logic_vector(9 downto 0);
+signal rddata_reg                               : std_logic_vector(31 downto 0);
+signal wrdata_reg                               : std_logic_vector(31 downto 0);
+signal rwaddr_reg                               : std_logic_vector(4 downto 0);
+signal ack_in_progress                          : std_logic      ;
+
+begin
+-- Some internal signals assignments
+  wrdata_reg <= wb_dat_i;
+-- 
+-- Main register bank access process.
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ack_sreg <= "0000000000";
+      ack_in_progress <= '0';
+      rddata_reg <= "00000000000000000000000000000000";
+      regs_o.rstr_trig_wr_o <= '0';
+      sysc_rstr_rst_int <= '0';
+      sysc_gpsr_led_stat_int <= '0';
+      sysc_gpsr_led_link_int <= '0';
+      regs_o.gpsr_fmc_scl_load_o <= '0';
+      regs_o.gpsr_fmc_sda_load_o <= '0';
+      sysc_gpsr_net_rst_int <= '0';
+      regs_o.gpsr_sfp_scl_load_o <= '0';
+      regs_o.gpsr_sfp_sda_load_o <= '0';
+      regs_o.gpsr_spi_sclk_load_o <= '0';
+      regs_o.gpsr_spi_ncs_load_o <= '0';
+      regs_o.gpsr_spi_mosi_load_o <= '0';
+      sysc_gpcr_led_stat_int <= '0';
+      sysc_gpcr_led_link_int <= '0';
+      sysc_gpcr_fmc_scl_int <= '0';
+      sysc_gpcr_fmc_sda_int <= '0';
+      sysc_gpcr_sfp_scl_int <= '0';
+      sysc_gpcr_sfp_sda_int <= '0';
+      sysc_gpcr_spi_sclk_int <= '0';
+      sysc_gpcr_spi_cs_int <= '0';
+      sysc_gpcr_spi_mosi_int <= '0';
+      sysc_tcr_enable_int <= '0';
+      regs_o.diag_cr_adr_load_o <= '0';
+      sysc_diag_cr_rw_int <= '0';
+      regs_o.diag_dat_load_o <= '0';
+      sysc_wdiag_ctrl_data_valid_int <= '0';
+      sysc_wdiag_sstat_wr_mode_int <= '0';
+      sysc_wdiag_sstat_servostate_int <= "0000";
+      sysc_wdiag_pstat_link_int <= '0';
+      sysc_wdiag_pstat_locked_int <= '0';
+      sysc_wdiag_ptpstat_ptpstate_int <= "00000000";
+      sysc_wdiag_astat_aux_int <= "00000000";
+      sysc_wdiag_txfcnt_int <= "00000000000000000000000000000000";
+      sysc_wdiag_rxfcnt_int <= "00000000000000000000000000000000";
+      sysc_wdiag_sec_msb_int <= "00000000000000000000000000000000";
+      sysc_wdiag_sec_lsb_int <= "00000000000000000000000000000000";
+      sysc_wdiag_ns_int <= "00000000000000000000000000000000";
+      sysc_wdiag_mu_msb_int <= "00000000000000000000000000000000";
+      sysc_wdiag_mu_lsb_int <= "00000000000000000000000000000000";
+      sysc_wdiag_dms_msb_int <= "00000000000000000000000000000000";
+      sysc_wdiag_dms_lsb_int <= "00000000000000000000000000000000";
+      sysc_wdiag_asym_int <= "00000000000000000000000000000000";
+      sysc_wdiag_cko_int <= "00000000000000000000000000000000";
+      sysc_wdiag_setp_int <= "00000000000000000000000000000000";
+      sysc_wdiag_ucnt_int <= "00000000000000000000000000000000";
+      sysc_wdiag_temp_int <= "00000000000000000000000000000000";
+    elsif rising_edge(clk_sys_i) then
+-- advance the ACK generator shift register
+      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
+      ack_sreg(9) <= '0';
+      if (ack_in_progress = '1') then
+        if (ack_sreg(0) = '1') then
+          regs_o.rstr_trig_wr_o <= '0';
+          sysc_gpsr_led_stat_int <= '0';
+          sysc_gpsr_led_link_int <= '0';
+          regs_o.gpsr_fmc_scl_load_o <= '0';
+          regs_o.gpsr_fmc_sda_load_o <= '0';
+          sysc_gpsr_net_rst_int <= '0';
+          regs_o.gpsr_sfp_scl_load_o <= '0';
+          regs_o.gpsr_sfp_sda_load_o <= '0';
+          regs_o.gpsr_spi_sclk_load_o <= '0';
+          regs_o.gpsr_spi_ncs_load_o <= '0';
+          regs_o.gpsr_spi_mosi_load_o <= '0';
+          sysc_gpcr_led_stat_int <= '0';
+          sysc_gpcr_led_link_int <= '0';
+          sysc_gpcr_fmc_scl_int <= '0';
+          sysc_gpcr_fmc_sda_int <= '0';
+          sysc_gpcr_sfp_scl_int <= '0';
+          sysc_gpcr_sfp_sda_int <= '0';
+          sysc_gpcr_spi_sclk_int <= '0';
+          sysc_gpcr_spi_cs_int <= '0';
+          sysc_gpcr_spi_mosi_int <= '0';
+          regs_o.diag_cr_adr_load_o <= '0';
+          regs_o.diag_dat_load_o <= '0';
+          ack_in_progress <= '0';
+        else
+          regs_o.rstr_trig_wr_o <= '0';
+          regs_o.gpsr_fmc_scl_load_o <= '0';
+          regs_o.gpsr_fmc_sda_load_o <= '0';
+          regs_o.gpsr_sfp_scl_load_o <= '0';
+          regs_o.gpsr_sfp_sda_load_o <= '0';
+          regs_o.gpsr_spi_sclk_load_o <= '0';
+          regs_o.gpsr_spi_ncs_load_o <= '0';
+          regs_o.gpsr_spi_mosi_load_o <= '0';
+          regs_o.diag_cr_adr_load_o <= '0';
+          regs_o.diag_dat_load_o <= '0';
+        end if;
+      else
+        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
+          case rwaddr_reg(4 downto 0) is
+          when "00000" => 
+            if (wb_we_i = '1') then
+              regs_o.rstr_trig_wr_o <= '1';
+              sysc_rstr_rst_int <= wrdata_reg(28);
+            end if;
+            rddata_reg(28) <= sysc_rstr_rst_int;
+            rddata_reg(0) <= 'X';
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00001" => 
+            if (wb_we_i = '1') then
+              sysc_gpsr_led_stat_int <= wrdata_reg(0);
+              sysc_gpsr_led_link_int <= wrdata_reg(1);
+              regs_o.gpsr_fmc_scl_load_o <= '1';
+              regs_o.gpsr_fmc_sda_load_o <= '1';
+              sysc_gpsr_net_rst_int <= wrdata_reg(4);
+              regs_o.gpsr_sfp_scl_load_o <= '1';
+              regs_o.gpsr_sfp_sda_load_o <= '1';
+              regs_o.gpsr_spi_sclk_load_o <= '1';
+              regs_o.gpsr_spi_ncs_load_o <= '1';
+              regs_o.gpsr_spi_mosi_load_o <= '1';
+            end if;
+            rddata_reg(0) <= '0';
+            rddata_reg(1) <= '0';
+            rddata_reg(2) <= regs_i.gpsr_fmc_scl_i;
+            rddata_reg(3) <= regs_i.gpsr_fmc_sda_i;
+            rddata_reg(4) <= '0';
+            rddata_reg(5) <= regs_i.gpsr_btn1_i;
+            rddata_reg(6) <= regs_i.gpsr_btn2_i;
+            rddata_reg(7) <= regs_i.gpsr_sfp_det_i;
+            rddata_reg(8) <= regs_i.gpsr_sfp_scl_i;
+            rddata_reg(9) <= regs_i.gpsr_sfp_sda_i;
+            rddata_reg(10) <= regs_i.gpsr_spi_sclk_i;
+            rddata_reg(11) <= regs_i.gpsr_spi_ncs_i;
+            rddata_reg(12) <= regs_i.gpsr_spi_mosi_i;
+            rddata_reg(13) <= regs_i.gpsr_spi_miso_i;
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(2) <= '1';
+            ack_in_progress <= '1';
+          when "00010" => 
+            if (wb_we_i = '1') then
+              sysc_gpcr_led_stat_int <= wrdata_reg(0);
+              sysc_gpcr_led_link_int <= wrdata_reg(1);
+              sysc_gpcr_fmc_scl_int <= wrdata_reg(2);
+              sysc_gpcr_fmc_sda_int <= wrdata_reg(3);
+              sysc_gpcr_sfp_scl_int <= wrdata_reg(8);
+              sysc_gpcr_sfp_sda_int <= wrdata_reg(9);
+              sysc_gpcr_spi_sclk_int <= wrdata_reg(10);
+              sysc_gpcr_spi_cs_int <= wrdata_reg(11);
+              sysc_gpcr_spi_mosi_int <= wrdata_reg(12);
+            end if;
+            rddata_reg(0) <= '0';
+            rddata_reg(1) <= '0';
+            rddata_reg(2) <= '0';
+            rddata_reg(3) <= '0';
+            rddata_reg(8) <= '0';
+            rddata_reg(9) <= '0';
+            rddata_reg(10) <= '0';
+            rddata_reg(11) <= '0';
+            rddata_reg(12) <= '0';
+            rddata_reg(0) <= 'X';
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(2) <= '1';
+            ack_in_progress <= '1';
+          when "00011" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(3 downto 0) <= regs_i.hwfr_memsize_i;
+            rddata_reg(9 downto 8) <= regs_i.hwfr_storage_type_i;
+            rddata_reg(31 downto 16) <= regs_i.hwfr_storage_sec_i;
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00100" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.hwir_name_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00101" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.sdbfs_baddr_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00110" => 
+            if (wb_we_i = '1') then
+              sysc_tcr_enable_int <= wrdata_reg(31);
+            end if;
+            rddata_reg(11 downto 0) <= regs_i.tcr_tdiv_i;
+            rddata_reg(31) <= sysc_tcr_enable_int;
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00111" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.tvr_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01000" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(15 downto 0) <= regs_i.diag_info_ver_i;
+            rddata_reg(31 downto 16) <= regs_i.diag_info_id_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01001" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(15 downto 0) <= regs_i.diag_nw_rw_i;
+            rddata_reg(31 downto 16) <= regs_i.diag_nw_ro_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01010" => 
+            if (wb_we_i = '1') then
+              regs_o.diag_cr_adr_load_o <= '1';
+              sysc_diag_cr_rw_int <= wrdata_reg(31);
+            end if;
+            rddata_reg(15 downto 0) <= regs_i.diag_cr_adr_i;
+            rddata_reg(31) <= sysc_diag_cr_rw_int;
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01011" => 
+            if (wb_we_i = '1') then
+              regs_o.diag_dat_load_o <= '1';
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.diag_dat_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01100" => 
+            if (wb_we_i = '1') then
+              sysc_wdiag_ctrl_data_valid_int <= wrdata_reg(0);
+            end if;
+            rddata_reg(0) <= sysc_wdiag_ctrl_data_valid_int;
+            rddata_reg(8) <= regs_i.wdiag_ctrl_data_snapshot_i;
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01101" => 
+            if (wb_we_i = '1') then
+              sysc_wdiag_sstat_wr_mode_int <= wrdata_reg(0);
+              sysc_wdiag_sstat_servostate_int <= wrdata_reg(11 downto 8);
+            end if;
+            rddata_reg(0) <= sysc_wdiag_sstat_wr_mode_int;
+            rddata_reg(11 downto 8) <= sysc_wdiag_sstat_servostate_int;
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01110" => 
+            if (wb_we_i = '1') then
+              sysc_wdiag_pstat_link_int <= wrdata_reg(0);
+              sysc_wdiag_pstat_locked_int <= wrdata_reg(1);
+            end if;
+            rddata_reg(0) <= sysc_wdiag_pstat_link_int;
+            rddata_reg(1) <= sysc_wdiag_pstat_locked_int;
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01111" => 
+            if (wb_we_i = '1') then
+              sysc_wdiag_ptpstat_ptpstate_int <= wrdata_reg(7 downto 0);
+            end if;
+            rddata_reg(7 downto 0) <= sysc_wdiag_ptpstat_ptpstate_int;
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "10000" => 
+            if (wb_we_i = '1') then
+              sysc_wdiag_astat_aux_int <= wrdata_reg(7 downto 0);
+            end if;
+            rddata_reg(7 downto 0) <= sysc_wdiag_astat_aux_int;
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "10001" => 
+            if (wb_we_i = '1') then
+              sysc_wdiag_txfcnt_int <= wrdata_reg(31 downto 0);
+            end if;
+            rddata_reg(31 downto 0) <= sysc_wdiag_txfcnt_int;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "10010" => 
+            if (wb_we_i = '1') then
+              sysc_wdiag_rxfcnt_int <= wrdata_reg(31 downto 0);
+            end if;
+            rddata_reg(31 downto 0) <= sysc_wdiag_rxfcnt_int;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "10011" => 
+            if (wb_we_i = '1') then
+              sysc_wdiag_sec_msb_int <= wrdata_reg(31 downto 0);
+            end if;
+            rddata_reg(31 downto 0) <= sysc_wdiag_sec_msb_int;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "10100" => 
+            if (wb_we_i = '1') then
+              sysc_wdiag_sec_lsb_int <= wrdata_reg(31 downto 0);
+            end if;
+            rddata_reg(31 downto 0) <= sysc_wdiag_sec_lsb_int;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "10101" => 
+            if (wb_we_i = '1') then
+              sysc_wdiag_ns_int <= wrdata_reg(31 downto 0);
+            end if;
+            rddata_reg(31 downto 0) <= sysc_wdiag_ns_int;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "10110" => 
+            if (wb_we_i = '1') then
+              sysc_wdiag_mu_msb_int <= wrdata_reg(31 downto 0);
+            end if;
+            rddata_reg(31 downto 0) <= sysc_wdiag_mu_msb_int;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "10111" => 
+            if (wb_we_i = '1') then
+              sysc_wdiag_mu_lsb_int <= wrdata_reg(31 downto 0);
+            end if;
+            rddata_reg(31 downto 0) <= sysc_wdiag_mu_lsb_int;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "11000" => 
+            if (wb_we_i = '1') then
+              sysc_wdiag_dms_msb_int <= wrdata_reg(31 downto 0);
+            end if;
+            rddata_reg(31 downto 0) <= sysc_wdiag_dms_msb_int;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "11001" => 
+            if (wb_we_i = '1') then
+              sysc_wdiag_dms_lsb_int <= wrdata_reg(31 downto 0);
+            end if;
+            rddata_reg(31 downto 0) <= sysc_wdiag_dms_lsb_int;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "11010" => 
+            if (wb_we_i = '1') then
+              sysc_wdiag_asym_int <= wrdata_reg(31 downto 0);
+            end if;
+            rddata_reg(31 downto 0) <= sysc_wdiag_asym_int;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "11011" => 
+            if (wb_we_i = '1') then
+              sysc_wdiag_cko_int <= wrdata_reg(31 downto 0);
+            end if;
+            rddata_reg(31 downto 0) <= sysc_wdiag_cko_int;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "11100" => 
+            if (wb_we_i = '1') then
+              sysc_wdiag_setp_int <= wrdata_reg(31 downto 0);
+            end if;
+            rddata_reg(31 downto 0) <= sysc_wdiag_setp_int;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "11101" => 
+            if (wb_we_i = '1') then
+              sysc_wdiag_ucnt_int <= wrdata_reg(31 downto 0);
+            end if;
+            rddata_reg(31 downto 0) <= sysc_wdiag_ucnt_int;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "11110" => 
+            if (wb_we_i = '1') then
+              sysc_wdiag_temp_int <= wrdata_reg(31 downto 0);
+            end if;
+            rddata_reg(31 downto 0) <= sysc_wdiag_temp_int;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when others =>
+-- prevent the slave from hanging the bus on invalid address
+            ack_in_progress <= '1';
+            ack_sreg(0) <= '1';
+          end case;
+        end if;
+      end if;
+    end if;
+  end process;
+  
+  
+-- Drive the data output bus
+  wb_dat_o <= rddata_reg;
+-- Reset trigger
+-- pass-through field: Reset trigger in register: Syscon reset register
+  regs_o.rstr_trig_o <= wrdata_reg(27 downto 0);
+-- Reset line state value
+  regs_o.rstr_rst_o <= sysc_rstr_rst_int;
+-- Status LED
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      sysc_gpsr_led_stat_dly0 <= '0';
+      regs_o.gpsr_led_stat_o <= '0';
+    elsif rising_edge(clk_sys_i) then
+      sysc_gpsr_led_stat_dly0 <= sysc_gpsr_led_stat_int;
+      regs_o.gpsr_led_stat_o <= sysc_gpsr_led_stat_int and (not sysc_gpsr_led_stat_dly0);
+    end if;
+  end process;
+  
+  
+-- Link LED
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      sysc_gpsr_led_link_dly0 <= '0';
+      regs_o.gpsr_led_link_o <= '0';
+    elsif rising_edge(clk_sys_i) then
+      sysc_gpsr_led_link_dly0 <= sysc_gpsr_led_link_int;
+      regs_o.gpsr_led_link_o <= sysc_gpsr_led_link_int and (not sysc_gpsr_led_link_dly0);
+    end if;
+  end process;
+  
+  
+-- FMC I2C bitbanged SCL
+  regs_o.gpsr_fmc_scl_o <= wrdata_reg(2);
+-- FMC I2C bitbanged SDA
+  regs_o.gpsr_fmc_sda_o <= wrdata_reg(3);
+-- Network AP reset
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      sysc_gpsr_net_rst_dly0 <= '0';
+      regs_o.gpsr_net_rst_o <= '0';
+    elsif rising_edge(clk_sys_i) then
+      sysc_gpsr_net_rst_dly0 <= sysc_gpsr_net_rst_int;
+      regs_o.gpsr_net_rst_o <= sysc_gpsr_net_rst_int and (not sysc_gpsr_net_rst_dly0);
+    end if;
+  end process;
+  
+  
+-- SPEC Pushbutton 1 state
+-- SPEC Pushbutton 2 state
+-- SFP detect (MOD_DEF0 signal)
+-- SFP I2C bitbanged SCL
+  regs_o.gpsr_sfp_scl_o <= wrdata_reg(8);
+-- SFP I2C bitbanged SDA
+  regs_o.gpsr_sfp_sda_o <= wrdata_reg(9);
+-- SPI bitbanged SCLK
+  regs_o.gpsr_spi_sclk_o <= wrdata_reg(10);
+-- SPI bitbanged NCS
+  regs_o.gpsr_spi_ncs_o <= wrdata_reg(11);
+-- SPI bitbanged MOSI
+  regs_o.gpsr_spi_mosi_o <= wrdata_reg(12);
+-- SPI bitbanged MISO
+-- Status LED
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      sysc_gpcr_led_stat_dly0 <= '0';
+      regs_o.gpcr_led_stat_o <= '0';
+    elsif rising_edge(clk_sys_i) then
+      sysc_gpcr_led_stat_dly0 <= sysc_gpcr_led_stat_int;
+      regs_o.gpcr_led_stat_o <= sysc_gpcr_led_stat_int and (not sysc_gpcr_led_stat_dly0);
+    end if;
+  end process;
+  
+  
+-- Link LED
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      sysc_gpcr_led_link_dly0 <= '0';
+      regs_o.gpcr_led_link_o <= '0';
+    elsif rising_edge(clk_sys_i) then
+      sysc_gpcr_led_link_dly0 <= sysc_gpcr_led_link_int;
+      regs_o.gpcr_led_link_o <= sysc_gpcr_led_link_int and (not sysc_gpcr_led_link_dly0);
+    end if;
+  end process;
+  
+  
+-- FMC I2C bitbanged SCL
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      sysc_gpcr_fmc_scl_dly0 <= '0';
+      regs_o.gpcr_fmc_scl_o <= '0';
+    elsif rising_edge(clk_sys_i) then
+      sysc_gpcr_fmc_scl_dly0 <= sysc_gpcr_fmc_scl_int;
+      regs_o.gpcr_fmc_scl_o <= sysc_gpcr_fmc_scl_int and (not sysc_gpcr_fmc_scl_dly0);
+    end if;
+  end process;
+  
+  
+-- FMC I2C bitbanged SDA
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      sysc_gpcr_fmc_sda_dly0 <= '0';
+      regs_o.gpcr_fmc_sda_o <= '0';
+    elsif rising_edge(clk_sys_i) then
+      sysc_gpcr_fmc_sda_dly0 <= sysc_gpcr_fmc_sda_int;
+      regs_o.gpcr_fmc_sda_o <= sysc_gpcr_fmc_sda_int and (not sysc_gpcr_fmc_sda_dly0);
+    end if;
+  end process;
+  
+  
+-- SFP I2C bitbanged SCL
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      sysc_gpcr_sfp_scl_dly0 <= '0';
+      regs_o.gpcr_sfp_scl_o <= '0';
+    elsif rising_edge(clk_sys_i) then
+      sysc_gpcr_sfp_scl_dly0 <= sysc_gpcr_sfp_scl_int;
+      regs_o.gpcr_sfp_scl_o <= sysc_gpcr_sfp_scl_int and (not sysc_gpcr_sfp_scl_dly0);
+    end if;
+  end process;
+  
+  
+-- FMC I2C bitbanged SDA
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      sysc_gpcr_sfp_sda_dly0 <= '0';
+      regs_o.gpcr_sfp_sda_o <= '0';
+    elsif rising_edge(clk_sys_i) then
+      sysc_gpcr_sfp_sda_dly0 <= sysc_gpcr_sfp_sda_int;
+      regs_o.gpcr_sfp_sda_o <= sysc_gpcr_sfp_sda_int and (not sysc_gpcr_sfp_sda_dly0);
+    end if;
+  end process;
+  
+  
+-- SPI bitbanged SCLK
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      sysc_gpcr_spi_sclk_dly0 <= '0';
+      regs_o.gpcr_spi_sclk_o <= '0';
+    elsif rising_edge(clk_sys_i) then
+      sysc_gpcr_spi_sclk_dly0 <= sysc_gpcr_spi_sclk_int;
+      regs_o.gpcr_spi_sclk_o <= sysc_gpcr_spi_sclk_int and (not sysc_gpcr_spi_sclk_dly0);
+    end if;
+  end process;
+  
+  
+-- SPI bitbanged CS
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      sysc_gpcr_spi_cs_dly0 <= '0';
+      regs_o.gpcr_spi_cs_o <= '0';
+    elsif rising_edge(clk_sys_i) then
+      sysc_gpcr_spi_cs_dly0 <= sysc_gpcr_spi_cs_int;
+      regs_o.gpcr_spi_cs_o <= sysc_gpcr_spi_cs_int and (not sysc_gpcr_spi_cs_dly0);
+    end if;
+  end process;
+  
+  
+-- SPI bitbanged MOSI
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      sysc_gpcr_spi_mosi_dly0 <= '0';
+      regs_o.gpcr_spi_mosi_o <= '0';
+    elsif rising_edge(clk_sys_i) then
+      sysc_gpcr_spi_mosi_dly0 <= sysc_gpcr_spi_mosi_int;
+      regs_o.gpcr_spi_mosi_o <= sysc_gpcr_spi_mosi_int and (not sysc_gpcr_spi_mosi_dly0);
+    end if;
+  end process;
+  
+  
+-- Memory size
+-- Storage type
+-- Storage sector size
+-- Board name
+-- Base address
+-- Timer Divider
+-- Timer Enable
+  regs_o.tcr_enable_o <= sysc_tcr_enable_int;
+-- Timer Counter Value
+-- Ver
+-- Id
+-- Read/write words
+-- Read-only words
+-- Address
+  regs_o.diag_cr_adr_o <= wrdata_reg(15 downto 0);
+-- R/W
+  regs_o.diag_cr_rw_o <= sysc_diag_cr_rw_int;
+-- Data
+  regs_o.diag_dat_o <= wrdata_reg(31 downto 0);
+-- WR DIAG data valid
+  regs_o.wdiag_ctrl_data_valid_o <= sysc_wdiag_ctrl_data_valid_int;
+-- WR DIAG data snapshot
+-- WR valid
+  regs_o.wdiag_sstat_wr_mode_o <= sysc_wdiag_sstat_wr_mode_int;
+-- Servo State
+  regs_o.wdiag_sstat_servostate_o <= sysc_wdiag_sstat_servostate_int;
+-- Link Status
+  regs_o.wdiag_pstat_link_o <= sysc_wdiag_pstat_link_int;
+-- PLL Locked
+  regs_o.wdiag_pstat_locked_o <= sysc_wdiag_pstat_locked_int;
+-- PTP State
+  regs_o.wdiag_ptpstat_ptpstate_o <= sysc_wdiag_ptpstat_ptpstate_int;
+-- AUX channel
+  regs_o.wdiag_astat_aux_o <= sysc_wdiag_astat_aux_int;
+-- Data
+  regs_o.wdiag_txfcnt_o <= sysc_wdiag_txfcnt_int;
+-- Data
+  regs_o.wdiag_rxfcnt_o <= sysc_wdiag_rxfcnt_int;
+-- Data
+  regs_o.wdiag_sec_msb_o <= sysc_wdiag_sec_msb_int;
+-- Data
+  regs_o.wdiag_sec_lsb_o <= sysc_wdiag_sec_lsb_int;
+-- Data
+  regs_o.wdiag_ns_o <= sysc_wdiag_ns_int;
+-- Data
+  regs_o.wdiag_mu_msb_o <= sysc_wdiag_mu_msb_int;
+-- Data
+  regs_o.wdiag_mu_lsb_o <= sysc_wdiag_mu_lsb_int;
+-- Data
+  regs_o.wdiag_dms_msb_o <= sysc_wdiag_dms_msb_int;
+-- Data
+  regs_o.wdiag_dms_lsb_o <= sysc_wdiag_dms_lsb_int;
+-- Data
+  regs_o.wdiag_asym_o <= sysc_wdiag_asym_int;
+-- Data
+  regs_o.wdiag_cko_o <= sysc_wdiag_cko_int;
+-- Data
+  regs_o.wdiag_setp_o <= sysc_wdiag_setp_int;
+-- Data
+  regs_o.wdiag_ucnt_o <= sysc_wdiag_ucnt_int;
+-- Data
+  regs_o.wdiag_temp_o <= sysc_wdiag_temp_int;
+  rwaddr_reg <= wb_adr_i;
+  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
+-- ACK signal generation. Just pass the LSB of ACK counter.
+  wb_ack_o <= ack_sreg(0);
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/wrcore_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/wrcore_pkg.vhd
new file mode 100644
index 000000000..a16166cfe
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/wrcore_pkg.vhd
@@ -0,0 +1,769 @@
+-------------------------------------------------------------------------------
+-- Title      : WhiteRabbit PTP Core
+-- Project    : WhiteRabbit
+-------------------------------------------------------------------------------
+-- File       : wrcore_pkg.vhd
+-- Author     : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
+-- Company    : CERN (BE-CO-HT)
+-- Created    : 2011-05-11
+-- Last update: 2017-05-29
+-- Platform   : FPGA-generics
+-- Standard   : VHDL
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012 - 2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.genram_pkg.all;
+use work.wishbone_pkg.all;
+use work.sysc_wbgen2_pkg.all;
+use work.wrc_diags_wbgen2_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.endpoint_pkg.all;
+use work.softpll_pkg.all;
+
+package wrcore_pkg is
+
+  function f_refclk_rate(pcs_16 : boolean) return integer;
+
+  type t_generic_word_array is array (natural range <>) of std_logic_vector(31 downto 0);
+
+  ----------------------------------------------------------------------------- 
+  --PPS generator
+  -----------------------------------------------------------------------------
+  constant c_xwr_pps_gen_sdb : t_sdb_device := (
+    abi_class     => x"0000",              -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"01",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"7",                 -- 8/16/32-bit port granularity
+    sdb_component => (
+      addr_first  => x"0000000000000000",
+      addr_last   => x"00000000000000ff",
+      product     => (
+        vendor_id => x"000000000000CE42",  -- CERN
+        device_id => x"de0d8ced",
+        version   => x"00000001",
+        date      => x"20120305",
+        name      => "WR-PPS-Generator   ")));
+
+  component xwr_pps_gen is
+    generic(
+      g_interface_mode       : t_wishbone_interface_mode;
+      g_address_granularity  : t_wishbone_address_granularity;
+      g_ref_clock_rate       : integer;
+      g_ext_clock_rate       : integer;
+      g_with_ext_clock_input : boolean
+      );
+    port (
+      clk_ref_i       : in  std_logic;
+      clk_sys_i       : in  std_logic;
+      rst_ref_n_i     : in  std_logic;
+      rst_sys_n_i     : in  std_logic;
+      slave_i         : in  t_wishbone_slave_in;
+      slave_o         : out t_wishbone_slave_out;
+      link_ok_i       : in  std_logic;
+      pps_in_i        : in  std_logic;
+      pps_csync_o     : out std_logic;
+      pps_out_o       : out std_logic;
+      pps_led_o       : out std_logic;
+      pps_valid_o     : out std_logic;
+      tm_utc_o        : out std_logic_vector(39 downto 0);
+      tm_cycles_o     : out std_logic_vector(27 downto 0);
+      tm_time_valid_o : out std_logic
+      );
+  end component;
+
+  -----------------------------------------------------------------------------
+  --Mini NIC
+  -----------------------------------------------------------------------------
+  constant c_xwr_mini_nic_sdb : t_sdb_device := (
+    abi_class     => x"0000",              -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"01",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"7",                 -- 8/16/32-bit port granularity
+    sdb_component => (
+      addr_first  => x"0000000000000000",
+      addr_last   => x"00000000000000ff",
+      product     => (
+        vendor_id => x"000000000000CE42",  -- CERN
+        device_id => x"ab28633a",
+        version   => x"00000001",
+        date      => x"20120305",
+        name      => "WR-Mini-NIC        ")));
+
+  component xwr_mini_nic
+    generic (
+      g_interface_mode       : t_wishbone_interface_mode;
+      g_address_granularity  : t_wishbone_address_granularity;
+      g_tx_fifo_size         : integer;
+      g_rx_fifo_size         : integer;
+      g_buffer_little_endian : boolean);
+    port (
+      clk_sys_i           : in  std_logic;
+      rst_n_i             : in  std_logic;
+      src_o               : out t_wrf_source_out;
+      src_i               : in  t_wrf_source_in;
+      snk_o               : out t_wrf_sink_out;
+      snk_i               : in  t_wrf_sink_in;
+      txtsu_port_id_i     : in  std_logic_vector(4 downto 0);
+      txtsu_frame_id_i    : in  std_logic_vector(16 - 1 downto 0);
+      txtsu_tsval_i       : in  std_logic_vector(28 + 4 - 1 downto 0);
+      txtsu_tsincorrect_i : in  std_logic;
+      txtsu_stb_i         : in  std_logic;
+      txtsu_ack_o         : out std_logic;
+      wb_i                : in  t_wishbone_slave_in;
+      wb_o                : out t_wishbone_slave_out);
+  end component;
+
+  -----------------------------------------------------------------------------
+  -- PERIPHERIALS
+  -----------------------------------------------------------------------------
+  component xwr_diags_wb is
+    generic(
+      g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
+      g_address_granularity : t_wishbone_address_granularity := WORD
+    );
+    port (
+      rst_n_i   : in  std_logic;
+      clk_sys_i : in  std_logic;
+
+      slave_i   : in  t_wishbone_slave_in;
+      slave_o   : out t_wishbone_slave_out;
+
+      regs_i    : in  t_wrc_diags_in_registers;
+      regs_o    : out t_wrc_diags_out_registers
+    );
+  end component;
+
+  constant c_wrc_periph0_sdb : t_sdb_device := (
+    abi_class     => x"0000",              -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"01",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"7",                 -- 8/16/32-bit port granularity
+    sdb_component => (
+      addr_first  => x"0000000000000000",
+      addr_last   => x"00000000000000ff",
+      product     => (
+        vendor_id => x"000000000000CE42",  -- CERN
+        device_id => x"ff07fc47",
+        version   => x"00000001",
+        date      => x"20120305",
+        name      => "WR-Periph-Syscon   ")));
+
+  constant c_wrc_periph1_sdb : t_sdb_device := (
+    abi_class     => x"0000",              -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"01",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"7",                 -- 8/16/32-bit port granularity
+    sdb_component => (
+      addr_first  => x"0000000000000000",
+      addr_last   => x"00000000000000ff",
+      product     => (
+        vendor_id => x"000000000000CE42",  -- CERN
+        device_id => x"e2d13d04",
+        version   => x"00000001",
+        date      => x"20120305",
+        name      => "WR-Periph-UART     ")));
+
+  constant c_wrc_periph2_sdb : t_sdb_device := (
+    abi_class     => x"0000",              -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"01",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"7",                 -- 8/16/32-bit port granularity
+    sdb_component => (
+      addr_first  => x"0000000000000000",
+      addr_last   => x"00000000000000ff",
+      product     => (
+        vendor_id => x"000000000000CE42",  -- CERN
+        device_id => x"779c5443",
+        version   => x"00000001",
+        date      => x"20120305",
+        name      => "WR-Periph-1Wire    ")));
+
+
+  constant c_wrc_periph3_sdb : t_sdb_device := (
+    abi_class     => x"0000",              -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"01",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"7",                 -- 8/16/32-bit port granularity
+    sdb_component => (
+      addr_first  => x"0000000000000000",
+      addr_last   => x"00000000000000ff",
+      product     => (
+        vendor_id => x"000000000000CE42",  -- CERN
+        device_id => x"779c5445",
+        version   => x"00000001",
+        date      => x"20120615",
+        name      => "WR-Periph-AuxWB    ")));
+
+  constant c_wrc_periph4_sdb : t_sdb_device := (
+    abi_class     => x"0000",              -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"01",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"7",                 -- 8/16/32-bit port granularity
+    sdb_component => (
+      addr_first  => x"0000000000000000",
+      addr_last   => x"00000000000000ff",
+      product     => (
+        vendor_id => x"000000000000CE42",  -- CERN
+        device_id => x"779c5446",
+        version   => x"00000001",
+        date      => x"20170424",
+        name      => "WR-Periph-WRPC-DIAG")));
+
+  component wrc_periph is
+    generic(
+      g_board_name      : string  := "NA  ";
+      g_flash_secsz_kb    : integer := 64;
+      g_flash_sdbfs_baddr : integer := 16#2e0000#;
+      g_phys_uart       : boolean := true;
+      g_virtual_uart    : boolean := false;
+      g_cntr_period     : integer := 62500;
+      g_mem_words       : integer := 16384;
+      g_vuart_fifo_size : integer := 1024;
+      g_diag_id         : integer := 0;
+      g_diag_ver        : integer := 0;
+      g_diag_ro_size    : integer := 0;
+      g_diag_rw_size    : integer := 0
+      );
+    port(
+      clk_sys_i   : in  std_logic;
+      rst_n_i     : in  std_logic;
+      rst_net_n_o : out std_logic;
+      rst_wrc_n_o : out std_logic;
+      led_red_o   : out std_logic;
+      led_green_o : out std_logic;
+      scl_o       : out std_logic;
+      scl_i       : in  std_logic;
+      sda_o       : out std_logic;
+      sda_i       : in  std_logic;
+      sfp_scl_o   : out std_logic;
+      sfp_scl_i   : in  std_logic;
+      sfp_sda_o   : out std_logic;
+      sfp_sda_i   : in  std_logic;
+      sfp_det_i   : in  std_logic;
+      memsize_i   : in  std_logic_vector(3 downto 0);
+      btn1_i      : in  std_logic;
+      btn2_i      : in  std_logic;
+      spi_sclk_o  : out std_logic;
+      spi_ncs_o   : out std_logic;
+      spi_mosi_o  : out std_logic;
+      spi_miso_i  : in  std_logic;
+      slave_i     : in  t_wishbone_slave_in_array(0 to 3);
+      slave_o     : out t_wishbone_slave_out_array(0 to 3);
+      uart_rxd_i  : in  std_logic;
+      uart_txd_o  : out std_logic;
+      owr_pwren_o : out std_logic_vector(1 downto 0);
+      owr_en_o    : out std_logic_vector(1 downto 0);
+      owr_i       : in  std_logic_vector(1 downto 0);
+      diag_array_in  : in  t_generic_word_array(g_diag_ro_size-1 downto 0);
+      diag_array_out : out t_generic_word_array(g_diag_rw_size-1 downto 0)
+      );
+  end component;
+
+  -----------------------------------------------------------------------------
+  -- Soft-PLL
+  -----------------------------------------------------------------------------
+  constant c_xwr_softpll_ng_sdb : t_sdb_device := (
+    abi_class     => x"0000",              -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"01",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"7",                 -- 8/16/32-bit port granularity
+    sdb_component => (
+      addr_first  => x"0000000000000000",
+      addr_last   => x"00000000000000ff",
+      product     => (
+        vendor_id => x"000000000000CE42",  -- CERN
+        device_id => x"65158dc0",
+        version   => x"00000002",
+        date      => x"20120305",
+        name      => "WR-Soft-PLL        ")));
+
+  component xwr_softpll_ng
+    generic (
+      g_tag_bits             : integer;
+      g_num_ref_inputs       : integer;
+      g_num_outputs          : integer;
+      g_with_debug_fifo      : boolean;
+      g_with_ext_clock_input : boolean;
+      g_reverse_dmtds        : boolean;
+      g_divide_input_by_2    : boolean;
+      g_ref_clock_rate       : integer;
+      g_ext_clock_rate       : integer;
+      g_interface_mode       : t_wishbone_interface_mode;
+      g_address_granularity  : t_wishbone_address_granularity);
+    port (
+      clk_sys_i       : in  std_logic;
+      rst_sys_n_i     : in  std_logic;
+      rst_ref_n_i     : in  std_logic;
+      rst_ext_n_i     : in  std_logic;
+      rst_dmtd_n_i    : in  std_logic;
+      clk_ref_i       : in  std_logic_vector(g_num_ref_inputs-1 downto 0);
+      clk_fb_i        : in  std_logic_vector(g_num_outputs-1 downto 0);
+      clk_dmtd_i      : in  std_logic;
+      clk_ext_i       : in  std_logic;
+      clk_ext_mul_i   : in  std_logic;
+      clk_ext_mul_locked_i : in std_logic;
+      clk_ext_stopped_i    : in std_logic;
+      clk_ext_rst_o        : out std_logic;
+      pps_csync_p1_i  : in  std_logic;
+      pps_ext_a_i     : in  std_logic;
+      dac_dmtd_data_o : out std_logic_vector(15 downto 0);
+      dac_dmtd_load_o : out std_logic;
+      dac_out_data_o  : out std_logic_vector(15 downto 0);
+      dac_out_sel_o   : out std_logic_vector(3 downto 0);
+      dac_out_load_o  : out std_logic;
+      out_enable_i    : in  std_logic_vector(g_num_outputs-1 downto 0);
+      out_locked_o    : out std_logic_vector(g_num_outputs-1 downto 0);
+      slave_i         : in  t_wishbone_slave_in;
+      slave_o         : out t_wishbone_slave_out;
+      debug_o         : out std_logic_vector(5 downto 0);
+      dbg_fifo_irq_o  : out std_logic);
+  end component;
+  
+  constant cc_unused_master_in : t_wishbone_master_in :=
+    ('1', '0', '0', '0', '0', cc_dummy_data);
+
+  -----------------------------------------------------------------------------
+  -- Public WR component definitions
+  -----------------------------------------------------------------------------
+  component xwr_core is
+    generic(
+      g_simulation                : integer                        := 0;
+      g_board_name                : string                         := "NA  ";
+      g_flash_secsz_kb            : integer                        := 256;        -- default for SVEC (M25P128)
+      g_flash_sdbfs_baddr         : integer                        := 16#600000#; -- default for SVEC (M25P128)
+      g_phys_uart                 : boolean                        := true;
+      g_virtual_uart              : boolean                        := true;
+      g_with_external_clock_input : boolean                        := true;
+      g_aux_clks                  : integer                        := 0;
+      g_ep_rxbuf_size             : integer                        := 1024;
+      g_tx_runt_padding           : boolean                        := true;
+      g_dpram_initf               : string                         := "default";
+      g_dpram_size                : integer                        := 131072/4;  --in 32-bit words
+      g_interface_mode            : t_wishbone_interface_mode      := PIPELINED;
+      g_address_granularity       : t_wishbone_address_granularity := BYTE;
+      g_aux_sdb                   : t_sdb_device                   := c_wrc_periph3_sdb;
+      g_softpll_enable_debugger   : boolean                        := false;
+      g_vuart_fifo_size           : integer                        := 1024;
+      g_pcs_16bit                 : boolean                        := false;
+      g_records_for_phy           : boolean                        := false;
+      g_diag_id                   : integer                        := 0;
+      g_diag_ver                  : integer                        := 0;
+      g_diag_ro_size              : integer                        := 0;
+      g_diag_rw_size              : integer                        := 0);
+    port(
+      clk_sys_i            : in std_logic;
+      clk_dmtd_i           : in std_logic := '0';
+      clk_ref_i            : in std_logic;
+      clk_aux_i            : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
+      clk_ext_mul_i        : in std_logic := '0';
+      clk_ext_mul_locked_i : in std_logic := '1';
+      clk_ext_stopped_i    : in std_logic := '0';
+      clk_ext_rst_o        : out std_logic;
+      clk_ext_i            : in std_logic := '0';
+      pps_ext_i            : in std_logic := '0';
+      rst_n_i              : in std_logic;
+
+      dac_hpll_load_p1_o   : out std_logic;
+      dac_hpll_data_o      : out std_logic_vector(15 downto 0);
+      dac_dpll_load_p1_o   : out std_logic;
+      dac_dpll_data_o      : out std_logic_vector(15 downto 0);
+      -----------------------------------------
+      -- PHY I/f
+      -----------------------------------------
+      phy_ref_clk_i        : in  std_logic                    := '0';
+      phy_tx_data_o        : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
+      phy_tx_k_o           : out std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
+      phy_tx_disparity_i   : in  std_logic                    := '0';
+      phy_tx_enc_err_i     : in  std_logic                    := '0';
+      phy_rx_data_i        : in  std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
+      phy_rx_rbclk_i       : in  std_logic                    := '0';
+      phy_rx_k_i           : in  std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
+      phy_rx_enc_err_i     : in  std_logic                    := '0';
+      phy_rx_bitslide_i    : in  std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
+      phy_rst_o            : out std_logic;
+      phy_rdy_i            : in  std_logic := '1';
+      phy_loopen_o         : out std_logic;
+      phy_loopen_vec_o     : out std_logic_vector(2 downto 0);
+      phy_tx_prbs_sel_o    : out std_logic_vector(2 downto 0);
+      phy_sfp_tx_fault_i   : in std_logic := '0';
+      phy_sfp_los_i        : in std_logic := '0';
+      phy_sfp_tx_disable_o : out std_logic;
+      -----------------------------------------
+      -- PHY I/f - record-based
+      -- selection done with g_records_for_phy
+      -----------------------------------------
+      phy8_o  : out t_phy_8bits_from_wrc;
+      phy8_i  : in  t_phy_8bits_to_wrc  := c_dummy_phy8_to_wrc;
+      phy16_o : out t_phy_16bits_from_wrc;
+      phy16_i : in  t_phy_16bits_to_wrc := c_dummy_phy16_to_wrc;
+
+      led_act_o  : out std_logic;
+      led_link_o : out std_logic;
+      scl_o      : out std_logic;
+      scl_i      : in  std_logic := 'H';
+      sda_o      : out std_logic;
+      sda_i      : in  std_logic := 'H';
+      sfp_scl_o  : out std_logic;
+      sfp_scl_i  : in  std_logic := 'H';
+      sfp_sda_o  : out std_logic;
+      sfp_sda_i  : in  std_logic := 'H';
+      sfp_det_i  : in  std_logic := '1';
+      btn1_i     : in  std_logic := 'H';
+      btn2_i     : in  std_logic := 'H';
+      spi_sclk_o : out std_logic;
+      spi_ncs_o  : out std_logic;
+      spi_mosi_o : out std_logic;
+      spi_miso_i : in  std_logic := '0';
+
+      uart_rxd_i : in  std_logic := 'H';
+      uart_txd_o : out std_logic;
+
+      owr_pwren_o : out std_logic_vector(1 downto 0);
+      owr_en_o    : out std_logic_vector(1 downto 0);
+      owr_i       : in  std_logic_vector(1 downto 0) := "HH";
+
+      slave_i : in  t_wishbone_slave_in := cc_dummy_slave_in;
+      slave_o : out t_wishbone_slave_out;
+
+      aux_master_o : out t_wishbone_master_out;
+      aux_master_i : in  t_wishbone_master_in := cc_unused_master_in;
+
+      wrf_src_o : out t_wrf_source_out;
+      wrf_src_i : in  t_wrf_source_in := c_dummy_src_in;
+      wrf_snk_o : out t_wrf_sink_out;
+      wrf_snk_i : in  t_wrf_sink_in   := c_dummy_snk_in;
+
+      timestamps_o     : out t_txtsu_timestamp;
+      timestamps_ack_i : in  std_logic := '1';
+
+      abscal_txts_o       : out std_logic;
+      abscal_rxts_o       : out std_logic;
+
+      fc_tx_pause_req_i   : in  std_logic                     := '0';
+      fc_tx_pause_delay_i : in  std_logic_vector(15 downto 0) := x"0000";
+      fc_tx_pause_ready_o : out std_logic;
+
+      tm_link_up_o         : out std_logic;
+      tm_dac_value_o       : out std_logic_vector(23 downto 0);
+      tm_dac_wr_o          : out std_logic_vector(g_aux_clks-1 downto 0);
+      tm_clk_aux_lock_en_i : in  std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
+      tm_clk_aux_locked_o  : out std_logic_vector(g_aux_clks-1 downto 0);
+      tm_time_valid_o      : out std_logic;
+      tm_tai_o             : out std_logic_vector(39 downto 0);
+      tm_cycles_o          : out std_logic_vector(27 downto 0);
+      pps_csync_o          : out std_logic;
+      pps_p_o              : out std_logic;
+      pps_led_o            : out std_logic;
+
+      rst_aux_n_o : out std_logic;
+
+      link_ok_o : out std_logic;
+
+      aux_diag_i : in  t_generic_word_array(g_diag_ro_size-1 downto 0) := (others=>(others=>'0'));
+      aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0)
+      );
+  end component;
+
+  component wr_core is
+    generic(
+      --if set to 1, then blocks in PCS use smaller calibration counter to speed 
+      --up simulation
+      g_simulation                : integer                        := 0;
+      g_with_external_clock_input : boolean                        := true;
+      --
+      g_board_name                : string                         := "NA  ";
+      g_flash_secsz_kb            : integer                        := 256;        -- default for SVEC (M25P128)
+      g_flash_sdbfs_baddr         : integer                        := 16#600000#; -- default for SVEC (M25P128)
+      g_phys_uart                 : boolean                        := true;
+      g_virtual_uart              : boolean                        := true;
+      g_aux_clks                  : integer                        := 0;
+      g_rx_buffer_size            : integer                        := 1024;
+      g_tx_runt_padding           : boolean                        := true;
+      g_dpram_initf               : string                         := "default";
+      g_dpram_size                : integer                        := 131072/4;  --in 32-bit words
+      g_interface_mode            : t_wishbone_interface_mode      := PIPELINED;
+      g_address_granularity       : t_wishbone_address_granularity := BYTE;
+      g_aux_sdb                   : t_sdb_device                   := c_wrc_periph3_sdb;
+      g_softpll_enable_debugger   : boolean                        := false;
+      g_vuart_fifo_size           : integer                        := 1024;
+      g_pcs_16bit                 : boolean                        := false;
+      g_records_for_phy           : boolean                        := false;
+      g_diag_id                   : integer                        := 0;
+      g_diag_ver                  : integer                        := 0;
+      g_diag_ro_size              : integer                        := 0;
+      g_diag_rw_size              : integer                        := 0);
+    port(
+      ---------------------------------------------------------------------------
+      -- Clocks/resets
+      ---------------------------------------------------------------------------
+
+      -- system reference clock (any frequency <= f(clk_ref_i))
+      clk_sys_i : in std_logic;
+
+      -- DDMTD offset clock (125.x MHz)
+      clk_dmtd_i : in std_logic := '0';
+
+      -- Timing reference (125 MHz)
+      clk_ref_i : in std_logic;
+
+      -- Aux clocks (i.e. the FMC clock), which can be disciplined by the WR Core
+      clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
+
+      -- External 10 MHz reference (cesium, GPSDO, etc.), used in Grandmaster mode
+      clk_ext_i : in std_logic := '0';
+
+      clk_ext_mul_i : in std_logic := '0';
+      clk_ext_mul_locked_i : in std_logic := '1';
+      clk_ext_stopped_i    : in std_logic := '0';
+      clk_ext_rst_o        : out std_logic;
+
+      -- External PPS input (cesium, GPSDO, etc.), used in Grandmaster mode
+      pps_ext_i : in std_logic := '0';
+
+      rst_n_i : in std_logic;
+
+      -----------------------------------------
+      --Timing system
+      -----------------------------------------
+      dac_hpll_load_p1_o : out std_logic;
+      dac_hpll_data_o    : out std_logic_vector(15 downto 0);
+
+      dac_dpll_load_p1_o : out std_logic;
+      dac_dpll_data_o    : out std_logic_vector(15 downto 0);
+
+      -----------------------------------------
+      -- PHY I/f
+      -----------------------------------------
+      phy_ref_clk_i : in std_logic;
+
+      phy_tx_data_o      : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
+      phy_tx_k_o         : out std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
+      phy_tx_disparity_i : in  std_logic := '0';
+      phy_tx_enc_err_i   : in  std_logic := '0';
+
+      phy_rx_data_i     : in std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
+      phy_rx_rbclk_i    : in std_logic                    := '0';
+      phy_rx_k_i        : in std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0):= (others=>'0');
+      phy_rx_enc_err_i  : in std_logic                    := '0';
+      phy_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
+
+      phy_rst_o    : out std_logic;
+      phy_rdy_i    : in  std_logic := '1';
+      phy_loopen_o         : out std_logic;
+      phy_loopen_vec_o     : out std_logic_vector(2 downto 0);
+      phy_tx_prbs_sel_o    : out std_logic_vector(2 downto 0);
+      phy_sfp_tx_fault_i   : in std_logic := '0';
+      phy_sfp_los_i        : in std_logic := '0';
+      phy_sfp_tx_disable_o : out std_logic;
+      -----------------------------------------
+      -- PHY I/f - record-based
+      -- selection done with g_records_for_phy
+      -----------------------------------------
+      phy8_o  : out t_phy_8bits_from_wrc;
+      phy8_i  : in  t_phy_8bits_to_wrc  := c_dummy_phy8_to_wrc;
+      phy16_o : out t_phy_16bits_from_wrc;
+      phy16_i : in  t_phy_16bits_to_wrc := c_dummy_phy16_to_wrc;
+
+      -----------------------------------------
+      --GPIO
+      -----------------------------------------
+      led_act_o  : out std_logic;
+      led_link_o : out std_logic;
+      scl_o      : out std_logic;
+      scl_i      : in  std_logic := '1';
+      sda_o      : out std_logic;
+      sda_i      : in  std_logic := '1';
+      sfp_scl_o  : out std_logic;
+      sfp_scl_i  : in  std_logic := '1';
+      sfp_sda_o  : out std_logic;
+      sfp_sda_i  : in  std_logic := '1';
+      sfp_det_i  : in  std_logic := '1';
+      btn1_i     : in  std_logic := '1';
+      btn2_i     : in  std_logic := '1';
+      spi_sclk_o : out std_logic;
+      spi_ncs_o  : out std_logic;
+      spi_mosi_o : out std_logic;
+      spi_miso_i : in  std_logic := '0';
+
+      -----------------------------------------
+      --UART
+      -----------------------------------------
+      uart_rxd_i : in  std_logic := '0';
+      uart_txd_o : out std_logic;
+
+      -----------------------------------------
+      -- 1-wire
+      -----------------------------------------
+      owr_pwren_o : out std_logic_vector(1 downto 0);
+      owr_en_o    : out std_logic_vector(1 downto 0);
+      owr_i       : in  std_logic_vector(1 downto 0) := (others => '1');
+
+      -----------------------------------------
+      --External WB interface
+      -----------------------------------------
+      wb_adr_i   : in  std_logic_vector(c_wishbone_address_width-1 downto 0)   := (others => '0');
+      wb_dat_i   : in  std_logic_vector(c_wishbone_data_width-1 downto 0)      := (others => '0');
+      wb_dat_o   : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+      wb_sel_i   : in  std_logic_vector(c_wishbone_address_width/8-1 downto 0) := (others => '0');
+      wb_we_i    : in  std_logic                                               := '0';
+      wb_cyc_i   : in  std_logic                                               := '0';
+      wb_stb_i   : in  std_logic                                               := '0';
+      wb_ack_o   : out std_logic;
+      wb_err_o   : out std_logic;
+      wb_rty_o   : out std_logic;
+      wb_stall_o : out std_logic;
+
+      -----------------------------------------
+      -- Auxillary WB master
+      -----------------------------------------
+      aux_adr_o   : out std_logic_vector(c_wishbone_address_width-1 downto 0);
+      aux_dat_o   : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+      aux_dat_i   : in  std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
+      aux_sel_o   : out std_logic_vector(c_wishbone_address_width/8-1 downto 0);
+      aux_we_o    : out std_logic;
+      aux_cyc_o   : out std_logic;
+      aux_stb_o   : out std_logic;
+      aux_ack_i   : in  std_logic                                          := '1';
+      aux_stall_i : in  std_logic                                          := '0';
+
+      -----------------------------------------
+      -- External Fabric I/F
+      -----------------------------------------
+      ext_snk_adr_i   : in  std_logic_vector(1 downto 0)  := "00";
+      ext_snk_dat_i   : in  std_logic_vector(15 downto 0) := x"0000";
+      ext_snk_sel_i   : in  std_logic_vector(1 downto 0)  := "00";
+      ext_snk_cyc_i   : in  std_logic                     := '0';
+      ext_snk_we_i    : in  std_logic                     := '0';
+      ext_snk_stb_i   : in  std_logic                     := '0';
+      ext_snk_ack_o   : out std_logic;
+      ext_snk_err_o   : out std_logic;
+      ext_snk_stall_o : out std_logic;
+
+      ext_src_adr_o   : out std_logic_vector(1 downto 0);
+      ext_src_dat_o   : out std_logic_vector(15 downto 0);
+      ext_src_sel_o   : out std_logic_vector(1 downto 0);
+      ext_src_cyc_o   : out std_logic;
+      ext_src_stb_o   : out std_logic;
+      ext_src_we_o    : out std_logic;
+      ext_src_ack_i   : in  std_logic := '1';
+      ext_src_err_i   : in  std_logic := '0';
+      ext_src_stall_i : in  std_logic := '0';
+
+      ------------------------------------------
+      -- External TX Timestamp I/F
+      ------------------------------------------
+      txtsu_port_id_o      : out std_logic_vector(4 downto 0);
+      txtsu_frame_id_o     : out std_logic_vector(15 downto 0);
+      txtsu_ts_value_o     : out std_logic_vector(31 downto 0);
+      txtsu_ts_incorrect_o : out std_logic;
+      txtsu_stb_o          : out std_logic;
+      txtsu_ack_i          : in  std_logic := '1';
+
+      -----------------------------------------
+      -- Timestamp helper signals, used for Absolute Calibration
+      -----------------------------------------
+      abscal_txts_o        : out std_logic;
+      abscal_rxts_o        : out std_logic;
+
+      -----------------------------------------
+      -- Pause Frame Control
+      -----------------------------------------
+      fc_tx_pause_req_i   : in  std_logic                     := '0';
+      fc_tx_pause_delay_i : in  std_logic_vector(15 downto 0) := x"0000";
+      fc_tx_pause_ready_o : out std_logic;
+
+      -----------------------------------------
+      -- Timecode/Servo Control
+      -----------------------------------------
+
+      tm_link_up_o         : out std_logic;
+
+      tm_dac_value_o       : out std_logic_vector(23 downto 0);
+      tm_dac_wr_o          : out std_logic_vector(g_aux_clks-1 downto 0) ;
+      tm_clk_aux_lock_en_i : in  std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
+      tm_clk_aux_locked_o  : out std_logic_vector(g_aux_clks-1 downto 0) ;
+
+      -- Timecode output
+      tm_time_valid_o      : out std_logic;
+      tm_tai_o             : out std_logic_vector(39 downto 0);
+      tm_cycles_o          : out std_logic_vector(27 downto 0);
+      -- 1PPS output
+      pps_csync_o          : out std_logic;
+      pps_p_o              : out std_logic;
+      pps_led_o            : out std_logic;
+
+      rst_aux_n_o : out std_logic;
+
+      link_ok_o : out std_logic;
+
+      -------------------------------------
+      -- DIAG to/from external modules
+      -------------------------------------
+      aux_diag_i : in  t_generic_word_array(g_diag_ro_size-1 downto 0) := (others=>(others=>'0'));
+      aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0)
+      );
+  end component;
+
+  component spec_serial_dac_arb
+    generic(
+      g_invert_sclk    : boolean;
+      g_num_extra_bits : integer);        
+    port (
+      clk_i       : in  std_logic;
+      rst_n_i     : in  std_logic;
+      val1_i      : in  std_logic_vector(15 downto 0);
+      load1_i     : in  std_logic;
+      val2_i      : in  std_logic_vector(15 downto 0);
+      load2_i     : in  std_logic;
+      dac_cs_n_o  : out std_logic_vector(1 downto 0);
+      dac_clr_n_o : out std_logic;
+      dac_sclk_o  : out std_logic;
+      dac_din_o   : out std_logic);
+  end component;
+
+end wrcore_pkg;
+
+package body wrcore_pkg is
+
+  function f_refclk_rate(pcs_16 : boolean)
+    return integer is
+  begin
+    if (pcs_16) then
+      return 62500000;
+    else
+      return 125000000;
+    end if;
+  end function;
+
+end package body wrcore_pkg;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/xwr_core.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/xwr_core.vhd
new file mode 100644
index 000000000..25bcc92a1
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/xwr_core.vhd
@@ -0,0 +1,448 @@
+-------------------------------------------------------------------------------
+-- Title      : WhiteRabbit PTP Core
+-- Project    : WhiteRabbit
+-------------------------------------------------------------------------------
+-- File       : xwr_core.vhd
+-- Author     : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
+-- Company    : CERN (BE-CO-HT)
+-- Created    : 2011-02-02
+-- Last update: 2017-05-29
+-- Platform   : FPGA-generics
+-- Standard   : VHDL
+-------------------------------------------------------------------------------
+-- Description:
+-- WR PTP Core is a HDL module implementing a complete gigabit Ethernet 
+-- interface (MAC + PCS + PHY) with integrated PTP slave ordinary clock 
+-- compatible with White Rabbit protocol. It performs subnanosecond clock 
+-- synchronization via WR protocol and also acts as an Ethernet "gateway", 
+-- providing access to TX/RX interfaces of the built-in WR MAC.
+--
+-- Starting from version 2.0 all modules are interconnected with pipelined
+-- wishbone interface (using wb crossbar and bus fanout). Separate pipelined
+-- wishbone bus is used for passing packets between Endpoint, Mini-NIC
+-- and External MAC interface.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012 - 2017 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Memory map:
+--  0x00000000: I/D Memory
+--  0x00020000: Peripheral interconnect
+--      +0x000: Minic
+--      +0x100: Endpoint
+--      +0x200: Softpll
+--      +0x300: PPS gen
+--      +0x400: Syscon
+--      +0x500: UART
+--      +0x600: OneWire
+--      +0x700: Auxillary space (Etherbone config, etc)
+--      +0x800: WRPC diagnostics registers
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.wrcore_pkg.all;
+use work.genram_pkg.all;
+use work.wishbone_pkg.all;
+use work.endpoint_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.sysc_wbgen2_pkg.all;
+use work.softpll_pkg.all;
+
+
+entity xwr_core is
+  generic(
+    --if set to 1, then blocks in PCS use smaller calibration counter to speed 
+    --up simulation
+    g_simulation                : integer                        := 0;
+    g_with_external_clock_input : boolean                        := true;
+    --
+    g_board_name                : string                         := "NA  ";
+    g_flash_secsz_kb            : integer                        := 256;        -- default for SVEC (M25P128)
+    g_flash_sdbfs_baddr         : integer                        := 16#600000#; -- default for SVEC (M25P128)
+    g_phys_uart                 : boolean                        := true;
+    g_virtual_uart              : boolean                        := true;
+    g_aux_clks                  : integer                        := 0;
+    g_ep_rxbuf_size             : integer                        := 1024;
+    g_tx_runt_padding           : boolean                        := true;
+    g_dpram_initf               : string                         := "";
+    g_dpram_size                : integer                        := 131072/4;  --in 32-bit words
+    g_interface_mode            : t_wishbone_interface_mode      := PIPELINED;
+    g_address_granularity       : t_wishbone_address_granularity := BYTE;
+    g_aux_sdb                   : t_sdb_device                   := c_wrc_periph3_sdb;
+    g_softpll_enable_debugger   : boolean                        := false;
+    g_vuart_fifo_size           : integer                        := 1024;
+    g_pcs_16bit                 : boolean                        := false;
+    g_records_for_phy           : boolean                        := false;
+    g_diag_id                   : integer                        := 0;
+    g_diag_ver                  : integer                        := 0;
+    g_diag_ro_size              : integer                        := 0;
+    g_diag_rw_size              : integer                        := 0);
+  port(
+    ---------------------------------------------------------------------------
+    -- Clocks/resets
+    ---------------------------------------------------------------------------
+
+    -- system reference clock (any frequency <= f(clk_ref_i))
+    clk_sys_i : in std_logic;
+
+    -- DDMTD offset clock (125.x MHz)
+    clk_dmtd_i : in std_logic;
+
+    -- Timing reference (125 MHz)
+    clk_ref_i : in std_logic;
+
+    -- Aux clock (i.e. the FMC clock), which can be disciplined by the WR Core
+    clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
+
+    -- External 10 MHz reference (cesium, GPSDO, etc.), used in Grandmaster mode
+    clk_ext_i : in std_logic := '0';
+
+    clk_ext_mul_i : in std_logic := '0';
+    clk_ext_mul_locked_i : in std_logic := '1';
+    clk_ext_stopped_i    : in  std_logic := '0';
+    clk_ext_rst_o        : out std_logic;
+
+    -- External PPS input (cesium, GPSDO, etc.), used in Grandmaster mode
+    pps_ext_i : in std_logic := '0';
+
+    rst_n_i : in std_logic;
+
+    -----------------------------------------
+    --Timing system
+    -----------------------------------------
+    dac_hpll_load_p1_o : out std_logic;
+    dac_hpll_data_o    : out std_logic_vector(15 downto 0);
+
+    dac_dpll_load_p1_o : out std_logic;
+    dac_dpll_data_o    : out std_logic_vector(15 downto 0);
+
+    -----------------------------------------
+    -- PHY I/f
+    -----------------------------------------
+    phy_ref_clk_i : in std_logic;
+
+    phy_tx_data_o        : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
+    phy_tx_k_o           : out std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
+    phy_tx_disparity_i   : in  std_logic;
+    phy_tx_enc_err_i     : in  std_logic;
+
+    phy_rx_data_i        : in std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
+    phy_rx_rbclk_i       : in std_logic;
+    phy_rx_k_i           : in std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
+    phy_rx_enc_err_i     : in std_logic;
+    phy_rx_bitslide_i    : in std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0);
+
+    phy_rst_o            : out std_logic;
+    phy_rdy_i            : in  std_logic := '1';
+    phy_loopen_o         : out std_logic;
+    phy_loopen_vec_o     : out std_logic_vector(2 downto 0);
+    phy_tx_prbs_sel_o    : out std_logic_vector(2 downto 0);
+    phy_sfp_tx_fault_i   : in std_logic := '0';
+    phy_sfp_los_i        : in std_logic := '0';
+    phy_sfp_tx_disable_o : out std_logic;
+    -----------------------------------------
+    -- PHY I/f - record-based
+    -- selection done with g_records_for_phy
+    -----------------------------------------
+    phy8_o               : out t_phy_8bits_from_wrc;
+    phy8_i               : in  t_phy_8bits_to_wrc  := c_dummy_phy8_to_wrc;
+    phy16_o              : out t_phy_16bits_from_wrc;
+    phy16_i              : in  t_phy_16bits_to_wrc := c_dummy_phy16_to_wrc;
+   
+    -----------------------------------------
+    --GPIO
+    -----------------------------------------
+    led_act_o  : out std_logic;
+    led_link_o : out std_logic;
+    scl_o      : out std_logic;
+    scl_i      : in  std_logic := '1';
+    sda_o      : out std_logic;
+    sda_i      : in  std_logic := '1';
+    sfp_scl_o  : out std_logic;
+    sfp_scl_i  : in  std_logic := '1';
+    sfp_sda_o  : out std_logic;
+    sfp_sda_i  : in  std_logic := '1';
+    sfp_det_i  : in  std_logic;
+    btn1_i     : in  std_logic := '1';
+    btn2_i     : in  std_logic := '1';
+    spi_sclk_o : out std_logic;
+    spi_ncs_o  : out std_logic;
+    spi_mosi_o : out std_logic;
+    spi_miso_i : in  std_logic := '0';
+
+    -----------------------------------------
+    --UART
+    -----------------------------------------
+    uart_rxd_i : in  std_logic := '0';
+    uart_txd_o : out std_logic;
+
+    -----------------------------------------
+    -- 1-wire
+    -----------------------------------------
+    owr_pwren_o : out std_logic_vector(1 downto 0);
+    owr_en_o    : out std_logic_vector(1 downto 0);
+    owr_i       : in  std_logic_vector(1 downto 0) := (others => '1');
+
+    -----------------------------------------
+    --External WB interface
+    -----------------------------------------
+    slave_i : in  t_wishbone_slave_in := cc_dummy_slave_in;
+    slave_o : out t_wishbone_slave_out;
+
+    aux_master_o : out t_wishbone_master_out;
+    aux_master_i : in  t_wishbone_master_in := cc_dummy_master_in;
+
+    -----------------------------------------
+    -- External Fabric I/F
+    -----------------------------------------
+    wrf_src_o : out t_wrf_source_out;
+    wrf_src_i : in  t_wrf_source_in := c_dummy_src_in;
+    wrf_snk_o : out t_wrf_sink_out;
+    wrf_snk_i : in  t_wrf_sink_in   := c_dummy_snk_in;
+
+    -----------------------------------------
+    -- External Tx Timestamping I/F
+    -----------------------------------------
+    timestamps_o     : out t_txtsu_timestamp;
+    timestamps_ack_i : in  std_logic := '1';
+
+    -----------------------------------------
+    -- Timestamp helper signals, used for Absolute Calibration
+    -----------------------------------------
+    abscal_txts_o       : out std_logic;
+    abscal_rxts_o       : out std_logic;
+
+    -----------------------------------------
+    -- Pause Frame Control
+    -----------------------------------------
+    fc_tx_pause_req_i   : in  std_logic                     := '0';
+    fc_tx_pause_delay_i : in  std_logic_vector(15 downto 0) := x"0000";
+    fc_tx_pause_ready_o : out std_logic;
+
+    -----------------------------------------
+    -- Timecode/Servo Control
+    -----------------------------------------
+
+    tm_link_up_o         : out std_logic;
+    -- DAC Control
+    tm_dac_value_o       : out std_logic_vector(23 downto 0);
+    tm_dac_wr_o          : out std_logic_vector(g_aux_clks-1 downto 0);
+    -- Aux clock lock enable
+    tm_clk_aux_lock_en_i : in  std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
+    -- Aux clock locked flag
+    tm_clk_aux_locked_o  : out std_logic_vector(g_aux_clks-1 downto 0);
+    -- Timecode output
+    tm_time_valid_o      : out std_logic;
+    tm_tai_o             : out std_logic_vector(39 downto 0);
+    tm_cycles_o          : out std_logic_vector(27 downto 0);
+    -- 1PPS output
+    pps_csync_o          : out std_logic;
+    pps_p_o              : out std_logic;
+    pps_led_o            : out std_logic;
+
+    rst_aux_n_o : out std_logic;
+
+    aux_diag_i    : in  t_generic_word_array(g_diag_ro_size-1 downto 0) := (others =>(others=>'0'));
+    aux_diag_o    : out t_generic_word_array(g_diag_rw_size-1 downto 0);
+
+    link_ok_o : out std_logic
+    );
+end xwr_core;
+
+architecture struct of xwr_core is
+begin
+
+  WRPC : wr_core
+    generic map(
+      g_simulation                => g_simulation,
+      g_board_name                => g_board_name,
+      g_flash_secsz_kb            => g_flash_secsz_kb,
+      g_flash_sdbfs_baddr         => g_flash_sdbfs_baddr,
+      g_phys_uart                 => g_phys_uart,
+      g_virtual_uart              => g_virtual_uart,
+      g_rx_buffer_size            => g_ep_rxbuf_size,
+      g_tx_runt_padding           => g_tx_runt_padding,
+      g_with_external_clock_input => g_with_external_clock_input,
+      g_aux_clks                  => g_aux_clks,
+      g_dpram_initf               => g_dpram_initf,
+      g_dpram_size                => g_dpram_size,
+      g_interface_mode            => g_interface_mode,
+      g_address_granularity       => g_address_granularity,
+      g_aux_sdb                   => g_aux_sdb,
+      g_softpll_enable_debugger   => g_softpll_enable_debugger,
+      g_vuart_fifo_size           => g_vuart_fifo_size,
+      g_pcs_16bit                 => g_pcs_16bit,
+      g_records_for_phy           => g_records_for_phy,
+      g_diag_id                   => g_diag_id,
+      g_diag_ver                  => g_diag_ver,
+      g_diag_ro_size              => g_diag_ro_size,
+      g_diag_rw_size              => g_diag_rw_size
+      )
+    port map(
+      clk_sys_i     => clk_sys_i,
+      clk_dmtd_i    => clk_dmtd_i,
+      clk_ref_i     => clk_ref_i,
+      clk_aux_i     => clk_aux_i,
+      clk_ext_i     => clk_ext_i,
+      clk_ext_mul_i => clk_ext_mul_i,
+      clk_ext_mul_locked_i  => clk_ext_mul_locked_i,
+      clk_ext_stopped_i => clk_ext_stopped_i,
+      clk_ext_rst_o     => clk_ext_rst_o,
+      pps_ext_i     => pps_ext_i,
+      rst_n_i       => rst_n_i,
+
+      dac_hpll_load_p1_o   => dac_hpll_load_p1_o,
+      dac_hpll_data_o      => dac_hpll_data_o,
+      dac_dpll_load_p1_o   => dac_dpll_load_p1_o,
+      dac_dpll_data_o      => dac_dpll_data_o,
+
+      phy_ref_clk_i        => phy_ref_clk_i,
+      phy_tx_data_o        => phy_tx_data_o,
+      phy_tx_k_o           => phy_tx_k_o,
+      phy_tx_disparity_i   => phy_tx_disparity_i,
+      phy_tx_enc_err_i     => phy_tx_enc_err_i,
+      phy_rx_data_i        => phy_rx_data_i,
+      phy_rx_rbclk_i       => phy_rx_rbclk_i,
+      phy_rx_k_i           => phy_rx_k_i,
+      phy_rx_enc_err_i     => phy_rx_enc_err_i,
+      phy_rx_bitslide_i    => phy_rx_bitslide_i,
+      phy_rst_o            => phy_rst_o,
+      phy_rdy_i            => phy_rdy_i,
+      phy_loopen_o         => phy_loopen_o,
+      phy_loopen_vec_o     => phy_loopen_vec_o,
+      phy_tx_prbs_sel_o    => phy_tx_prbs_sel_o,
+      phy_sfp_tx_fault_i   => phy_sfp_tx_fault_i,
+      phy_sfp_los_i        => phy_sfp_los_i,
+      phy_sfp_tx_disable_o => phy_sfp_tx_disable_o,
+
+      phy8_o     => phy8_o,
+      phy8_i     => phy8_i,
+      phy16_o    => phy16_o,
+      phy16_i    => phy16_i,
+
+      led_act_o  => led_act_o,
+      led_link_o => led_link_o,
+      scl_o      => scl_o,
+      scl_i      => scl_i,
+      sda_o      => sda_o,
+      sda_i      => sda_i,
+      sfp_scl_o  => sfp_scl_o,
+      sfp_scl_i  => sfp_scl_i,
+      sfp_sda_o  => sfp_sda_o,
+      sfp_sda_i  => sfp_sda_i,
+      sfp_det_i  => sfp_det_i,
+      btn1_i     => btn1_i,
+      btn2_i     => btn2_i,
+      spi_sclk_o => spi_sclk_o,
+      spi_ncs_o  => spi_ncs_o,
+      spi_mosi_o => spi_mosi_o,
+      spi_miso_i => spi_miso_i,
+      uart_rxd_i => uart_rxd_i,
+      uart_txd_o => uart_txd_o,
+
+      owr_pwren_o => owr_pwren_o,
+      owr_en_o    => owr_en_o,
+      owr_i       => owr_i,
+
+      wb_adr_i   => slave_i.adr,
+      wb_dat_i   => slave_i.dat,
+      wb_dat_o   => slave_o.dat,
+      wb_sel_i   => slave_i.sel,
+      wb_we_i    => slave_i.we,
+      wb_cyc_i   => slave_i.cyc,
+      wb_stb_i   => slave_i.stb,
+      wb_ack_o   => slave_o.ack,
+      wb_err_o   => slave_o.err,
+      wb_rty_o   => slave_o.rty,
+      wb_stall_o => slave_o.stall,
+
+      aux_adr_o   => aux_master_o.adr,
+      aux_dat_o   => aux_master_o.dat,
+      aux_sel_o   => aux_master_o.sel,
+      aux_cyc_o   => aux_master_o.cyc,
+      aux_stb_o   => aux_master_o.stb,
+      aux_we_o    => aux_master_o.we,
+      aux_stall_i => aux_master_i.stall,
+      aux_ack_i   => aux_master_i.ack,
+      aux_dat_i   => aux_master_i.dat,
+
+      ext_snk_adr_i   => wrf_snk_i.adr,
+      ext_snk_dat_i   => wrf_snk_i.dat,
+      ext_snk_sel_i   => wrf_snk_i.sel,
+      ext_snk_cyc_i   => wrf_snk_i.cyc,
+      ext_snk_we_i    => wrf_snk_i.we,
+      ext_snk_stb_i   => wrf_snk_i.stb,
+      ext_snk_ack_o   => wrf_snk_o.ack,
+      ext_snk_err_o   => wrf_snk_o.err,
+      ext_snk_stall_o => wrf_snk_o.stall,
+
+      ext_src_adr_o   => wrf_src_o.adr,
+      ext_src_dat_o   => wrf_src_o.dat,
+      ext_src_sel_o   => wrf_src_o.sel,
+      ext_src_cyc_o   => wrf_src_o.cyc,
+      ext_src_stb_o   => wrf_src_o.stb,
+      ext_src_we_o    => wrf_src_o.we,
+      ext_src_ack_i   => wrf_src_i.ack,
+      ext_src_err_i   => wrf_src_i.err,
+      ext_src_stall_i => wrf_src_i.stall,
+
+      txtsu_port_id_o      => timestamps_o.port_id(4 downto 0),
+      txtsu_frame_id_o     => timestamps_o.frame_id,
+      txtsu_ts_value_o     => timestamps_o.tsval,
+      txtsu_ts_incorrect_o => timestamps_o.incorrect,
+      txtsu_stb_o          => timestamps_o.stb,
+      txtsu_ack_i          => timestamps_ack_i,
+
+      abscal_txts_o        => abscal_txts_o,
+      abscal_rxts_o        => abscal_rxts_o,
+      
+      fc_tx_pause_req_i    => fc_tx_pause_req_i,
+      fc_tx_pause_delay_i  => fc_tx_pause_delay_i,
+      fc_tx_pause_ready_o  => fc_tx_pause_ready_o,
+
+      tm_link_up_o         => tm_link_up_o,
+      tm_dac_value_o       => tm_dac_value_o,
+      tm_dac_wr_o          => tm_dac_wr_o,
+      tm_clk_aux_lock_en_i => tm_clk_aux_lock_en_i,
+      tm_clk_aux_locked_o  => tm_clk_aux_locked_o,
+      tm_time_valid_o      => tm_time_valid_o,
+      tm_tai_o             => tm_tai_o,
+      tm_cycles_o          => tm_cycles_o,
+      pps_csync_o          => pps_csync_o,
+      pps_p_o              => pps_p_o,
+      pps_led_o            => pps_led_o,
+
+      rst_aux_n_o => rst_aux_n_o,
+
+      link_ok_o => link_ok_o,
+
+      aux_diag_i => aux_diag_i,
+      aux_diag_o => aux_diag_o
+      );
+
+  timestamps_o.port_id(5) <= '0';
+
+  slave_o.int <= '0';
+
+  wrf_snk_o.rty <= '0';
+
+end struct;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/xwrc_diags_wb.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/xwrc_diags_wb.vhd
new file mode 100644
index 000000000..cce48c8b1
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/xwrc_diags_wb.vhd
@@ -0,0 +1,132 @@
+-------------------------------------------------------------------------------
+-- Title      : WR PTP Core Diagnostics
+-- Project    : WhiteRabbit
+-------------------------------------------------------------------------------
+-- File       : xwrc_diags_wb.vhd
+-- Author     : Maciej Lipinski <maciej.lipinski@cern.ch>
+-- Company    : CERN
+-- Created    : 2017-04-24
+-- Platform   : FPGA-generics
+-- Standard   : VHDL
+-------------------------------------------------------------------------------
+-- Description:
+-- Wrapper for wrc_diags_wb. Uses types instead of std_logic signals and
+-- can use pipelined or classic wishbone.
+--
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.wishbone_pkg.all;
+use work.wrc_diags_wbgen2_pkg.all;
+
+entity xwr_diags_wb is
+  generic(
+    g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
+    g_address_granularity : t_wishbone_address_granularity := WORD
+  );
+  port (
+    rst_n_i   : in  std_logic;
+    clk_sys_i : in  std_logic;
+
+    slave_i   : in  t_wishbone_slave_in;
+    slave_o   : out t_wishbone_slave_out;
+
+    regs_i    : in  t_wrc_diags_in_registers;
+    regs_o    : out t_wrc_diags_out_registers
+  );
+end xwr_diags_wb;
+
+architecture syn of xwr_diags_wb is
+
+  component wrc_diags_wb is
+    port (
+      rst_n_i                                  : in     std_logic;
+      clk_sys_i                                : in     std_logic;
+      wb_adr_i                                 : in     std_logic_vector(4 downto 0);
+      wb_dat_i                                 : in     std_logic_vector(31 downto 0);
+      wb_dat_o                                 : out    std_logic_vector(31 downto 0);
+      wb_cyc_i                                 : in     std_logic;
+      wb_sel_i                                 : in     std_logic_vector(3 downto 0);
+      wb_stb_i                                 : in     std_logic;
+      wb_we_i                                  : in     std_logic;
+      wb_ack_o                                 : out    std_logic;
+      wb_stall_o                               : out    std_logic;
+      regs_i                                   : in     t_wrc_diags_in_registers;
+      regs_o                                   : out    t_wrc_diags_out_registers
+    );
+  end component;
+
+
+  signal wb_out : t_wishbone_slave_out;
+  signal wb_in  : t_wishbone_slave_in;
+
+begin
+
+  U_Adapter : wb_slave_adapter
+    generic map(
+      g_master_use_struct  => true,
+      g_master_mode        => CLASSIC,
+      g_master_granularity => WORD,
+      g_slave_use_struct   => false,
+      g_slave_mode         => g_interface_mode,
+      g_slave_granularity  => g_address_granularity)
+    port map (
+      clk_sys_i  => clk_sys_i,
+      rst_n_i    => rst_n_i,
+      master_i   => wb_out,
+      master_o   => wb_in,
+      sl_adr_i   => slave_i.adr,
+      sl_dat_i   => slave_i.dat,
+      sl_sel_i   => slave_i.sel,
+      sl_cyc_i   => slave_i.cyc,
+      sl_stb_i   => slave_i.stb,
+      sl_we_i    => slave_i.we,
+      sl_dat_o   => slave_o.dat, 
+      sl_ack_o   => slave_o.ack,
+      sl_stall_o => slave_o.stall);
+
+  WRAPPED_DIAGS: wrc_diags_wb
+    port map(
+      rst_n_i    => rst_n_i,
+      clk_sys_i  => clk_sys_i,
+      wb_adr_i   => wb_in.adr(4 downto 0),
+      wb_dat_i   => wb_in.dat,
+      wb_dat_o   => wb_out.dat,
+      wb_cyc_i   => wb_in.cyc,
+      wb_sel_i   => wb_in.sel,
+      wb_stb_i   => wb_in.stb,
+      wb_we_i    => wb_in.we,
+      wb_ack_o   => wb_out.ack,
+      wb_stall_o => wb_out.stall,
+      regs_i     => regs_i,
+      regs_o     => regs_o);
+
+  slave_o.err <= '0';
+  slave_o.rty <= '0';
+  slave_o.int <= '0';
+
+end syn;
+
+
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper.vhd
new file mode 100644
index 000000000..f981871f4
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper.vhd
@@ -0,0 +1,491 @@
+-------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version : 3.6
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard
+--  /   /         Filename : whiterabbit_gtpe2_channel_wrapper.vhd
+-- /___/   /\     
+-- \   \  /  \ 
+--  \___\/\___\
+--
+--
+-- Module whiterabbit_gtpe2_channel_wrapper (a GT Wrapper)
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+
+--***************************** Entity Declaration ****************************
+
+entity whiterabbit_gtpe2_channel_wrapper is
+generic
+(
+    -- Simulation attributes
+    EXAMPLE_SIMULATION             : integer  := 0;      -- Set to 1 for simulation
+    WRAPPER_SIM_GTRESET_SPEEDUP    : string   := "FALSE" -- Set to "true" to speed up sim reset
+);
+port
+(
+    --_________________________________________________________________________
+    --_________________________________________________________________________
+    --____________________________CHANNEL PORTS________________________________
+    GT0_DRP_BUSY_OUT                        : out  std_logic; 
+    ---------------------------- Channel - DRP Ports  --------------------------
+    GT0_DRPADDR_IN                          : in   std_logic_vector(8 downto 0);
+    GT0_DRPCLK_IN                           : in   std_logic;
+    GT0_DRPDI_IN                            : in   std_logic_vector(15 downto 0);
+    GT0_DRPDO_OUT                           : out  std_logic_vector(15 downto 0);
+    GT0_DRPEN_IN                            : in   std_logic;
+    GT0_DRPRDY_OUT                          : out  std_logic;
+    GT0_DRPWE_IN                            : in   std_logic;
+    ------------------------------- Loopback Ports -----------------------------
+    GT0_LOOPBACK_IN                         : in   std_logic_vector(2 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    GT0_RXUSERRDY_IN                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    GT0_EYESCANDATAERROR_OUT                : out  std_logic;
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    GT0_RXDATA_OUT                          : out  std_logic_vector(15 downto 0);
+    GT0_RXUSRCLK_IN                         : in   std_logic;
+    GT0_RXUSRCLK2_IN                        : in   std_logic;
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    GT0_RXCHARISCOMMA_OUT                   : out  std_logic_vector(1 downto 0);
+    GT0_RXCHARISK_OUT                       : out  std_logic_vector(1 downto 0);
+    GT0_RXDISPERR_OUT                       : out  std_logic_vector(1 downto 0);
+    GT0_RXNOTINTABLE_OUT                    : out  std_logic_vector(1 downto 0);
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    GT0_GTPRXN_IN                           : in   std_logic;
+    GT0_GTPRXP_IN                           : in   std_logic;
+    -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
+    GT0_RXBYTEISALIGNED_OUT                 : out  std_logic;
+    GT0_RXCOMMADET_OUT                      : out  std_logic;
+    GT0_RXSLIDE_IN                          : in   std_logic;
+    --------------------- Receive Ports - RX Equilizer Ports -------------------
+    GT0_RXLPMHFHOLD_IN                      : in   std_logic;
+    GT0_RXLPMLFHOLD_IN                      : in   std_logic;
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    GT0_RXOUTCLK_OUT                        : out  std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    GT0_GTRXRESET_IN                        : in   std_logic;
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    GT0_RXRESETDONE_OUT                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    GT0_GTTXRESET_IN                        : in   std_logic;
+    GT0_TXUSERRDY_IN                        : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    GT0_TXDATA_IN                           : in   std_logic_vector(15 downto 0);
+    GT0_TXUSRCLK_IN                         : in   std_logic;
+    GT0_TXUSRCLK2_IN                        : in   std_logic;
+    ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
+    GT0_TXCHARISK_IN                        : in   std_logic_vector(1 downto 0);
+    --------------- Transmit Ports - TX Configurable Driver Ports --------------
+    GT0_GTPTXN_OUT                          : out  std_logic;
+    GT0_GTPTXP_OUT                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    GT0_TXOUTCLK_OUT                        : out  std_logic;
+    GT0_TXOUTCLKFABRIC_OUT                  : out  std_logic;
+    GT0_TXOUTCLKPCS_OUT                     : out  std_logic;
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    GT0_TXRESETDONE_OUT                     : out  std_logic;
+    ------------------ Transmit Ports - pattern Generator Ports ----------------
+    GT0_TXPRBSSEL_IN                        : in   std_logic_vector(2 downto 0);
+
+	
+    --____________________________COMMON PORTS________________________________
+    ----------------- Common Block - GTPE2_COMMON Clocking Ports ---------------
+    GT0_GTREFCLK0_IN                        : in   std_logic;
+    -------------------------- Common Block - PLL Ports ------------------------
+    GT0_PLL1LOCK_OUT                        : out  std_logic;
+    GT0_PLL1LOCKDETCLK_IN                   : in   std_logic;
+    GT0_PLL1REFCLKLOST_OUT                  : out  std_logic;
+    GT0_PLL1RESET_IN                        : in   std_logic
+
+
+);
+
+
+end whiterabbit_gtpe2_channel_wrapper;
+    
+architecture RTL of whiterabbit_gtpe2_channel_wrapper is
+
+    attribute CORE_GENERATION_INFO : string;
+    attribute CORE_GENERATION_INFO of RTL : architecture is "whiterabbit_gtpe2_channel_wrapper,gtwizard_v3_6_1,{protocol_file=Start_from_scratch}";
+
+
+--***********************************Parameter Declarations********************
+
+    constant DLY : time := 1 ns;
+
+--***************************** Signal Declarations *****************************
+
+    -- ground and tied_to_vcc_i signals
+    signal  tied_to_ground_i                :   std_logic;
+    signal  tied_to_ground_vec_i            :   std_logic_vector(63 downto 0);
+    signal  tied_to_vcc_i                   :   std_logic;
+    signal   gt0_pll0outclk_i       :   std_logic;
+    signal   gt0_pll0outrefclk_i    :   std_logic;
+    signal   gt0_pll1outclk_i       :   std_logic;
+    signal   gt0_pll1outrefclk_i    :   std_logic;
+
+ 
+    signal  gt0_mgtrefclktx_i           :   std_logic_vector(1 downto 0);
+    signal  gt0_mgtrefclkrx_i           :   std_logic_vector(1 downto 0);
+ 
+
+    signal   gt0_pll0clk_i       :   std_logic;
+    signal   gt0_pll0refclk_i    :   std_logic;
+    signal   gt0_pll1clk_i       :   std_logic;
+    signal   gt0_pll1refclk_i    :   std_logic;
+    signal    gt0_rst_i                       : std_logic;
+      
+
+
+
+--*************************** Component Declarations **************************
+component whiterabbit_gtpe2_channel_wrapper_gt
+generic
+(
+    -- Simulation attributes
+    GT_SIM_GTRESET_SPEEDUP    : string := "false";
+    EXAMPLE_SIMULATION        : integer  := 0;  
+    TXSYNC_OVRD_IN            : bit    := '0';
+    TXSYNC_MULTILANE_IN       : bit    := '0'     
+);
+port 
+(   
+    RST_IN                                  : in   std_logic;
+    DRP_BUSY_OUT                            : out  std_logic;
+   
+    ---------------------------- Channel - DRP Ports  --------------------------
+    DRPADDR_IN                              : in   std_logic_vector(8 downto 0);
+    DRPCLK_IN                               : in   std_logic;
+    DRPDI_IN                                : in   std_logic_vector(15 downto 0);
+    DRPDO_OUT                               : out  std_logic_vector(15 downto 0);
+    DRPEN_IN                                : in   std_logic;
+    DRPRDY_OUT                              : out  std_logic;
+    DRPWE_IN                                : in   std_logic;
+    ------------------------ GTPE2_CHANNEL Clocking Ports ----------------------
+    PLL0CLK_IN                              : in   std_logic;
+    PLL0REFCLK_IN                           : in   std_logic;
+    PLL1CLK_IN                              : in   std_logic;
+    PLL1REFCLK_IN                           : in   std_logic;
+    ------------------------------- Loopback Ports -----------------------------
+    LOOPBACK_IN                             : in   std_logic_vector(2 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    RXUSERRDY_IN                            : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    EYESCANDATAERROR_OUT                    : out  std_logic;
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    RXDATA_OUT                              : out  std_logic_vector(15 downto 0);
+    RXUSRCLK_IN                             : in   std_logic;
+    RXUSRCLK2_IN                            : in   std_logic;
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    RXCHARISCOMMA_OUT                       : out  std_logic_vector(1 downto 0);
+    RXCHARISK_OUT                           : out  std_logic_vector(1 downto 0);
+    RXDISPERR_OUT                           : out  std_logic_vector(1 downto 0);
+    RXNOTINTABLE_OUT                        : out  std_logic_vector(1 downto 0);
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    GTPRXN_IN                               : in   std_logic;
+    GTPRXP_IN                               : in   std_logic;
+    -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
+    RXBYTEISALIGNED_OUT                     : out  std_logic;
+    RXCOMMADET_OUT                          : out  std_logic;
+    RXSLIDE_IN                              : in   std_logic;
+    --------------------- Receive Ports - RX Equilizer Ports -------------------
+    RXLPMHFHOLD_IN                          : in   std_logic;
+    RXLPMLFHOLD_IN                          : in   std_logic;
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    RXOUTCLK_OUT                            : out  std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    GTRXRESET_IN                            : in   std_logic;
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    RXRESETDONE_OUT                         : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    GTTXRESET_IN                            : in   std_logic;
+    TXUSERRDY_IN                            : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    TXDATA_IN                               : in   std_logic_vector(15 downto 0);
+    TXUSRCLK_IN                             : in   std_logic;
+    TXUSRCLK2_IN                            : in   std_logic;
+    ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
+    TXCHARISK_IN                            : in   std_logic_vector(1 downto 0);
+    --------------- Transmit Ports - TX Configurable Driver Ports --------------
+    GTPTXN_OUT                              : out  std_logic;
+    GTPTXP_OUT                              : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    TXOUTCLK_OUT                            : out  std_logic;
+    TXOUTCLKFABRIC_OUT                      : out  std_logic;
+    TXOUTCLKPCS_OUT                         : out  std_logic;
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    TXRESETDONE_OUT                         : out  std_logic;
+    ------------------ Transmit Ports - pattern Generator Ports ----------------
+    TXPRBSSEL_IN                            : in   std_logic_vector(2 downto 0)
+
+
+);
+end component;
+
+
+    constant PLL0_FBDIV_IN      :   integer := 1;
+    constant PLL1_FBDIV_IN      :   integer := 4;
+    constant PLL0_FBDIV_45_IN   :   integer := 4;
+    constant PLL1_FBDIV_45_IN   :   integer := 5;
+    constant PLL0_REFCLK_DIV_IN :   integer := 1;
+    constant PLL1_REFCLK_DIV_IN :   integer := 1;
+
+--********************************* Main Body of Code**************************
+
+begin                       
+
+    tied_to_ground_i                    <= '0';
+    tied_to_ground_vec_i(63 downto 0)   <= (others => '0');
+    tied_to_vcc_i                       <= '1';
+    gt0_pll0clk_i    <= gt0_pll0outclk_i;  
+    gt0_pll0refclk_i <= gt0_pll0outrefclk_i; 
+    gt0_pll1clk_i    <= gt0_pll1outclk_i;  
+    gt0_pll1refclk_i <= gt0_pll1outrefclk_i; 
+      
+    gt0_rst_i        <= GT0_PLL1RESET_IN;
+   
+    
+    --------------------------- GT Instances  -------------------------------   
+    --_________________________________________________________________________
+    --_________________________________________________________________________
+    GT_INST : whiterabbit_gtpe2_channel_wrapper_gt
+    generic map
+    (
+        -- Simulation attributes
+        GT_SIM_GTRESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP,
+        EXAMPLE_SIMULATION     => EXAMPLE_SIMULATION,
+        TXSYNC_OVRD_IN         => ('0'),
+        TXSYNC_MULTILANE_IN    => ('0')
+    )
+    port map
+    (
+        RST_IN                          =>      gt0_rst_i,
+        DRP_BUSY_OUT                    =>      GT0_DRP_BUSY_OUT,
+    
+        ---------------------------- Channel - DRP Ports  --------------------------
+        DRPADDR_IN                      =>      GT0_DRPADDR_IN,
+        DRPCLK_IN                       =>      GT0_DRPCLK_IN,
+        DRPDI_IN                        =>      GT0_DRPDI_IN,
+        DRPDO_OUT                       =>      GT0_DRPDO_OUT,
+        DRPEN_IN                        =>      GT0_DRPEN_IN,
+        DRPRDY_OUT                      =>      GT0_DRPRDY_OUT,
+        DRPWE_IN                        =>      GT0_DRPWE_IN,
+        ------------------------ GTPE2_CHANNEL Clocking Ports ----------------------
+        PLL0CLK_IN                      =>      gt0_pll0clk_i,
+        PLL0REFCLK_IN                   =>      gt0_pll0refclk_i,
+        PLL1CLK_IN                      =>      gt0_pll1clk_i,
+        PLL1REFCLK_IN                   =>      gt0_pll1refclk_i,
+        ------------------------------- Loopback Ports -----------------------------
+        LOOPBACK_IN                     =>      GT0_LOOPBACK_IN,
+        --------------------- RX Initialization and Reset Ports --------------------
+        RXUSERRDY_IN                    =>      GT0_RXUSERRDY_IN,
+        -------------------------- RX Margin Analysis Ports ------------------------
+        EYESCANDATAERROR_OUT            =>      GT0_EYESCANDATAERROR_OUT,
+        ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+        RXDATA_OUT                      =>      GT0_RXDATA_OUT,
+        RXUSRCLK_IN                     =>      GT0_RXUSRCLK_IN,
+        RXUSRCLK2_IN                    =>      GT0_RXUSRCLK2_IN,
+        ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+        RXCHARISCOMMA_OUT               =>      GT0_RXCHARISCOMMA_OUT,
+        RXCHARISK_OUT                   =>      GT0_RXCHARISK_OUT,
+        RXDISPERR_OUT                   =>      GT0_RXDISPERR_OUT,
+        RXNOTINTABLE_OUT                =>      GT0_RXNOTINTABLE_OUT,
+        ------------------------ Receive Ports - RX AFE Ports ----------------------
+        GTPRXN_IN                       =>      GT0_GTPRXN_IN,
+        GTPRXP_IN                       =>      GT0_GTPRXP_IN,
+        -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
+        RXBYTEISALIGNED_OUT             =>      GT0_RXBYTEISALIGNED_OUT,
+        RXCOMMADET_OUT                  =>      GT0_RXCOMMADET_OUT,
+        RXSLIDE_IN                      =>      GT0_RXSLIDE_IN,
+        --------------------- Receive Ports - RX Equilizer Ports -------------------
+        RXLPMHFHOLD_IN                  =>      GT0_RXLPMHFHOLD_IN,
+        RXLPMLFHOLD_IN                  =>      GT0_RXLPMLFHOLD_IN,
+        --------------- Receive Ports - RX Fabric Output Control Ports -------------
+        RXOUTCLK_OUT                    =>      GT0_RXOUTCLK_OUT,
+        ------------- Receive Ports - RX Initialization and Reset Ports ------------
+        GTRXRESET_IN                    =>      GT0_GTRXRESET_IN,
+        -------------- Receive Ports -RX Initialization and Reset Ports ------------
+        RXRESETDONE_OUT                 =>      GT0_RXRESETDONE_OUT,
+        --------------------- TX Initialization and Reset Ports --------------------
+        GTTXRESET_IN                    =>      GT0_GTTXRESET_IN,
+        TXUSERRDY_IN                    =>      GT0_TXUSERRDY_IN,
+        ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+        TXDATA_IN                       =>      GT0_TXDATA_IN,
+        TXUSRCLK_IN                     =>      GT0_TXUSRCLK_IN,
+        TXUSRCLK2_IN                    =>      GT0_TXUSRCLK2_IN,
+        ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
+        TXCHARISK_IN                    =>      GT0_TXCHARISK_IN,
+        --------------- Transmit Ports - TX Configurable Driver Ports --------------
+        GTPTXN_OUT                      =>      GT0_GTPTXN_OUT,
+        GTPTXP_OUT                      =>      GT0_GTPTXP_OUT,
+        ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+        TXOUTCLK_OUT                    =>      GT0_TXOUTCLK_OUT,
+        TXOUTCLKFABRIC_OUT              =>      GT0_TXOUTCLKFABRIC_OUT,
+        TXOUTCLKPCS_OUT                 =>      GT0_TXOUTCLKPCS_OUT,
+        ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+        TXRESETDONE_OUT                 =>      GT0_TXRESETDONE_OUT,
+        ------------------ Transmit Ports - pattern Generator Ports ----------------
+        TXPRBSSEL_IN                    =>      GT0_TXPRBSSEL_IN
+
+    );
+
+
+    --_________________________________________________________________________
+    --_________________________________________________________________________
+    --_________________________GTPE2_COMMON____________________________________
+
+    gtpe2_common_0_i : GTPE2_COMMON
+    generic map
+    (
+            -- Simulation attributes
+            SIM_RESET_SPEEDUP    => WRAPPER_SIM_GTRESET_SPEEDUP,
+            SIM_PLL0REFCLK_SEL   => ("001"),
+            SIM_PLL1REFCLK_SEL   => ("001"),
+            SIM_VERSION          => ("1.0"),
+
+            PLL0_FBDIV           => PLL0_FBDIV_IN     ,	
+	    PLL0_FBDIV_45        => PLL0_FBDIV_45_IN  ,	
+	    PLL0_REFCLK_DIV      => PLL0_REFCLK_DIV_IN,	
+	    PLL1_FBDIV           => PLL1_FBDIV_IN     ,	
+	    PLL1_FBDIV_45        => PLL1_FBDIV_45_IN  ,	
+	    PLL1_REFCLK_DIV      => PLL1_REFCLK_DIV_IN,	            
+
+
+       ------------------COMMON BLOCK Attributes---------------
+        BIAS_CFG                                =>     (x"0000000000050001"),
+        COMMON_CFG                              =>     (x"00000000"),
+
+       ----------------------------PLL Attributes----------------------------
+        PLL0_CFG                                =>     (x"01F03DC"),
+        PLL0_DMON_CFG                           =>     ('0'),
+        PLL0_INIT_CFG                           =>     (x"00001E"),
+        PLL0_LOCK_CFG                           =>     (x"1E8"),
+        PLL1_CFG                                =>     (x"01F03DC"),
+        PLL1_DMON_CFG                           =>     ('0'),
+        PLL1_INIT_CFG                           =>     (x"00001E"),
+        PLL1_LOCK_CFG                           =>     (x"1E8"),
+        PLL_CLKOUT_CFG                          =>     (x"00"),
+
+       ----------------------------Reserved Attributes----------------------------
+        RSVD_ATTR0                              =>     (x"0000"),
+        RSVD_ATTR1                              =>     (x"0000")
+
+        
+    )
+    port map
+    (
+	     DMONITOROUT             => open,	
+        ------------- Common Block  - Dynamic Reconfiguration Port (DRP) -----------
+        DRPADDR                         =>      tied_to_ground_vec_i(7 downto 0),
+        DRPCLK                          =>      tied_to_ground_i,
+        DRPDI                           =>      tied_to_ground_vec_i(15 downto 0),
+        DRPDO                           =>      open,
+        DRPEN                           =>      tied_to_ground_i,
+        DRPRDY                          =>      open,
+        DRPWE                           =>      tied_to_ground_i,
+        ----------------- Common Block - GTPE2_COMMON Clocking Ports ---------------
+        GTEASTREFCLK0                   =>      tied_to_ground_i,
+        GTEASTREFCLK1                   =>      tied_to_ground_i,
+        GTGREFCLK1                      =>      tied_to_ground_i,
+        GTREFCLK0                       =>      GT0_GTREFCLK0_IN,
+        GTREFCLK1                       =>      tied_to_ground_i,
+        GTWESTREFCLK0                   =>      tied_to_ground_i,
+        GTWESTREFCLK1                   =>      tied_to_ground_i,
+        PLL0OUTCLK                      =>      gt0_pll0outclk_i,
+        PLL0OUTREFCLK                   =>      gt0_pll0outrefclk_i,
+        PLL1OUTCLK                      =>      gt0_pll1outclk_i,
+        PLL1OUTREFCLK                   =>      gt0_pll1outrefclk_i,
+        -------------------------- Common Block - PLL Ports ------------------------
+        PLL0FBCLKLOST                   =>      open,
+        PLL0LOCK                        =>      open,
+        PLL0LOCKDETCLK                  =>      tied_to_ground_i,
+        PLL0LOCKEN                      =>      tied_to_vcc_i,
+        PLL0PD                          =>      '1',
+        PLL0REFCLKLOST                  =>      open,
+        PLL0REFCLKSEL                   =>      "001",
+        PLL0RESET                       =>      tied_to_ground_i,
+        PLL1FBCLKLOST                   =>      open,
+        PLL1LOCK                        =>      GT0_PLL1LOCK_OUT,
+        PLL1LOCKDETCLK                  =>      GT0_PLL1LOCKDETCLK_IN,
+        PLL1LOCKEN                      =>      tied_to_vcc_i,
+        PLL1PD                          =>      tied_to_ground_i,
+        PLL1REFCLKLOST                  =>      GT0_PLL1REFCLKLOST_OUT,
+        PLL1REFCLKSEL                   =>      "001",
+        PLL1RESET                       =>      GT0_PLL1RESET_IN,
+        ---------------------------- Common Block - Ports --------------------------
+        BGRCALOVRDENB                   =>      tied_to_vcc_i,
+        GTGREFCLK0                      =>      tied_to_ground_i,
+        PLLRSVD1                        =>      "0000000000000000",
+        PLLRSVD2                        =>      "00000",
+        REFCLKOUTMONITOR0               =>      open,
+        REFCLKOUTMONITOR1               =>      open,
+        ------------------------ Common Block - RX AFE Ports -----------------------
+        PMARSVDOUT                      =>      open,
+        --------------------------------- QPLL Ports -------------------------------
+        BGBYPASSB                       =>      tied_to_vcc_i,
+        BGMONITORENB                    =>      tied_to_vcc_i,
+        BGPDB                           =>      tied_to_vcc_i,
+        BGRCALOVRD                      =>      "00000",           -- ug482 table 2-8 says "111111"
+        PMARSVD                         =>      "00000000",
+        RCALENB                         =>      tied_to_vcc_i
+
+    );
+
+     
+end RTL;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gt.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gt.vhd
new file mode 100644
index 000000000..90ca8f391
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gt.vhd
@@ -0,0 +1,1013 @@
+-------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version : 3.6
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard
+--  /   /         Filename : whiterabbit_gtpe2_channel_wrapper_gt.vhd
+-- /___/   /\     
+-- \   \  /  \ 
+--  \___\/\___\
+--
+--
+-- Module whiterabbit_gtpe2_channel_wrapper_GT (a GT Wrapper)
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+--***************************** Entity Declaration ****************************
+
+entity whiterabbit_gtpe2_channel_wrapper_gt is
+generic
+(
+    -- Simulation attributes
+    GT_SIM_GTRESET_SPEEDUP    : string := "FALSE"; -- Set to "true" to speed up sim reset
+    EXAMPLE_SIMULATION        : integer  := 0;     -- Set to 1 for simulation
+    TXSYNC_OVRD_IN            : bit    := '0';
+    TXSYNC_MULTILANE_IN       : bit    := '0' 
+);
+port 
+(
+  RST_IN         : in   std_logic;          -- Connect to System Reset
+  DRP_BUSY_OUT   : out  std_logic;          -- Indicates that the DRP bus is not accessible to the User
+    ---------------------------- Channel - DRP Ports  --------------------------
+    drpaddr_in                              : in   std_logic_vector(8 downto 0);
+    drpclk_in                               : in   std_logic;
+    drpdi_in                                : in   std_logic_vector(15 downto 0);
+    drpdo_out                               : out  std_logic_vector(15 downto 0);
+    drpen_in                                : in   std_logic;
+    drprdy_out                              : out  std_logic;
+    drpwe_in                                : in   std_logic;
+    ------------------------ GTPE2_CHANNEL Clocking Ports ----------------------
+    pll0clk_in                              : in   std_logic;
+    pll0refclk_in                           : in   std_logic;
+    pll1clk_in                              : in   std_logic;
+    pll1refclk_in                           : in   std_logic;
+    ------------------------------- Loopback Ports -----------------------------
+    loopback_in                             : in   std_logic_vector(2 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    rxuserrdy_in                            : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    eyescandataerror_out                    : out  std_logic;
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    rxdata_out                              : out  std_logic_vector(15 downto 0);
+    rxusrclk_in                             : in   std_logic;
+    rxusrclk2_in                            : in   std_logic;
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    rxchariscomma_out                       : out  std_logic_vector(1 downto 0);
+    rxcharisk_out                           : out  std_logic_vector(1 downto 0);
+    rxdisperr_out                           : out  std_logic_vector(1 downto 0);
+    rxnotintable_out                        : out  std_logic_vector(1 downto 0);
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gtprxn_in                               : in   std_logic;
+    gtprxp_in                               : in   std_logic;
+    -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
+    rxbyteisaligned_out                     : out  std_logic;
+    rxcommadet_out                          : out  std_logic;
+    rxslide_in                              : in   std_logic;
+    --------------------- Receive Ports - RX Equilizer Ports -------------------
+    rxlpmhfhold_in                          : in   std_logic;
+    rxlpmlfhold_in                          : in   std_logic;
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    rxoutclk_out                            : out  std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gtrxreset_in                            : in   std_logic;
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    rxresetdone_out                         : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gttxreset_in                            : in   std_logic;
+    txuserrdy_in                            : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    txdata_in                               : in   std_logic_vector(15 downto 0);
+    txusrclk_in                             : in   std_logic;
+    txusrclk2_in                            : in   std_logic;
+    ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
+    txcharisk_in                            : in   std_logic_vector(1 downto 0);
+    --------------- Transmit Ports - TX Configurable Driver Ports --------------
+    gtptxn_out                              : out  std_logic;
+    gtptxp_out                              : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    txoutclk_out                            : out  std_logic;
+    txoutclkfabric_out                      : out  std_logic;
+    txoutclkpcs_out                         : out  std_logic;
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    txresetdone_out                         : out  std_logic;
+    ------------------ Transmit Ports - pattern Generator Ports ----------------
+    txprbssel_in                            : in   std_logic_vector(2 downto 0)
+
+);
+
+
+end whiterabbit_gtpe2_channel_wrapper_gt;
+
+architecture RTL of whiterabbit_gtpe2_channel_wrapper_gt is
+
+--*************************** Component Declarations **************************
+component whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq  
+  port ( 
+    RST           : IN  std_logic;
+    GTRXRESET_IN  : IN  std_logic;    
+    RXPMARESETDONE: IN  std_logic;
+    GTRXRESET_OUT : OUT std_logic;
+
+    DRPCLK        : IN  std_logic;
+    DRPADDR       : OUT std_logic_vector(8 downto 0);
+    DRPDO	  : IN  std_logic_vector(15 downto 0);
+    DRPDI         : OUT std_logic_vector(15 downto 0);
+    DRPRDY        : IN  std_logic;
+    DRPEN	  : OUT std_logic;
+    DRPWE         : OUT std_logic;
+    DRP_OP_DONE   : OUT std_logic
+);
+end component;
+
+--component whiterabbitgtp_wrapper_rxpmarst_seq 
+--  port ( 
+--    RST                : IN  std_logic;
+--    RXPMARESET_IN      : IN  std_logic;    
+--    RXPMARESETDONE     : IN  std_logic;
+--    RXPMARESET_OUT     : OUT std_logic;
+--
+--    DRPCLK             : IN  std_logic;
+--    DRPADDR            : OUT std_logic_vector(8 downto 0);
+--    DRPDO              : IN  std_logic_vector(15 downto 0);
+--    DRPDI              : OUT std_logic_vector(15 downto 0);
+--    DRPRDY             : IN  std_logic;
+--    DRPEN              : OUT std_logic;
+--    DRPWE              : OUT std_logic;
+--    DRP_BUSY_IN        : IN  std_logic;
+--    DRP_PMA_BUSY_OUT   : OUT std_logic
+--);
+--end component;
+--
+--
+--component whiterabbitgtp_wrapper_rxrate_seq 
+--  port ( 
+--    RST                : IN  std_logic;
+--    RXRATE_IN          : IN  std_logic_vector(2 downto 0);    
+--    RXPMARESETDONE     : IN  std_logic;
+--    RXRATE_OUT         : OUT std_logic_vector(2 downto 0);
+--
+--    DRPCLK             : IN  std_logic;
+--    DRPADDR            : OUT std_logic_vector(8 downto 0);
+--    DRPDO              : IN  std_logic_vector(15 downto 0);
+--    DRPDI              : OUT std_logic_vector(15 downto 0);
+--    DRPRDY             : IN  std_logic;
+--    DRPEN              : OUT std_logic;
+--    DRPWE              : OUT std_logic;
+--    DRP_BUSY_IN        : IN  std_logic;
+--    DRP_RATE_BUSY_OUT  : OUT std_logic
+--);
+--end component;
+
+--**************************** Signal Declarations ****************************
+
+    -- ground and tied_to_vcc_i signals
+    signal  tied_to_ground_i                :   std_logic;
+    signal  tied_to_ground_vec_i            :   std_logic_vector(63 downto 0);
+    signal  tied_to_vcc_i                   :   std_logic;
+
+
+    signal    rxpmaresetdone_t                : std_logic;
+    signal    gtrxreset_out                   : std_logic;
+    signal    rxpmareset_out                  : std_logic;
+    signal    rxrate_out                      : std_logic_vector(2 downto 0);
+    signal    drp_op_done                     : std_logic;
+    signal    drp_pma_busy                    : std_logic;
+    signal    drp_rate_busy                   : std_logic;
+    signal    drp_busy_i1                     : std_logic:= '0';
+    signal    drp_busy_i2                     : std_logic:= '0';
+    signal    drpen_rst_t                     : std_logic;
+    signal    drpaddr_rst_t                   : std_logic_vector(8 downto 0);
+    signal    drpwe_rst_t                     : std_logic;
+    signal    drpdo_rst_t                     : std_logic_vector(15 downto 0);
+    signal    drpdi_rst_t                     : std_logic_vector(15 downto 0);
+    signal    drprdy_rst_t                    : std_logic;
+    signal    drpen_pma_t                     : std_logic;
+    signal    drpaddr_pma_t                   : std_logic_vector(8 downto 0);
+    signal    drpwe_pma_t                     : std_logic;
+    signal    drpdo_pma_t                     : std_logic_vector(15 downto 0);
+    signal    drpdi_pma_t                     : std_logic_vector(15 downto 0);
+    signal    drprdy_pma_t                    : std_logic;
+    signal    drpen_rate_t                    : std_logic;
+    signal    drpaddr_rate_t                  : std_logic_vector(8 downto 0);
+    signal    drpwe_rate_t                    : std_logic;
+    signal    drpdo_rate_t                    : std_logic_vector(15 downto 0);
+    signal    drpdi_rate_t                    : std_logic_vector(15 downto 0);
+    signal    drprdy_rate_t                   : std_logic;
+    signal    drpen_i                         : std_logic;
+    signal    drpaddr_i                       : std_logic_vector(8 downto 0);
+    signal    drpwe_i                         : std_logic;
+    signal    drpdo_i                         : std_logic_vector(15 downto 0);
+    signal    drpdi_i                         : std_logic_vector(15 downto 0);
+    signal    drprdy_i                        : std_logic;
+
+    -- RX Datapath signals
+    signal rxdata_i                         :   std_logic_vector(31 downto 0);      
+    signal rxchariscomma_float_i            :   std_logic_vector(1 downto 0);
+    signal rxcharisk_float_i                :   std_logic_vector(1 downto 0);
+    signal rxdisperr_float_i                :   std_logic_vector(1 downto 0);
+    signal rxnotintable_float_i             :   std_logic_vector(1 downto 0);
+    signal rxrundisp_float_i                :   std_logic_vector(1 downto 0);
+
+
+    -- TX Datapath signals
+    signal txdata_i                         :   std_logic_vector(31 downto 0);
+    signal txkerr_float_i                   :   std_logic_vector(1 downto 0);
+    signal txrundisp_float_i                :   std_logic_vector(1 downto 0);
+    signal rxdatavalid_float_i              :   std_logic;
+        
+--******************************** Main Body of Code***************************
+                       
+begin                      
+
+    ---------------------------  Static signal Assignments ---------------------   
+
+    tied_to_ground_i                    <= '0';
+    tied_to_ground_vec_i(63 downto 0)   <= (others => '0');
+    tied_to_vcc_i                       <= '1';
+
+    -------------------  GT Datapath byte mapping  -----------------
+    RXDATA_OUT    <=   rxdata_i(15 downto 0);
+
+    txdata_i    <=   (tied_to_ground_vec_i(15 downto 0) & TXDATA_IN);
+
+
+
+    ----------------------------- GTPE2 Instance  --------------------------   
+
+    gtpe2_i : GTPE2_CHANNEL
+    generic map
+    (
+
+        --_______________________ Simulation-Only Attributes ___________________
+
+        SIM_RECEIVER_DETECT_PASS   =>      ("TRUE"),
+        SIM_RESET_SPEEDUP          =>      (GT_SIM_GTRESET_SPEEDUP),
+        SIM_TX_EIDLE_DRIVE_LEVEL   =>      ("X"),
+        SIM_VERSION                =>      ("2.0"),
+        
+
+       ------------------RX Byte and Word Alignment Attributes---------------
+        ALIGN_COMMA_DOUBLE                      =>     ("FALSE"),
+        ALIGN_COMMA_ENABLE                      =>     ("0001111111"),
+        ALIGN_COMMA_WORD                        =>     (2),
+        ALIGN_MCOMMA_DET                        =>     ("TRUE"),
+        ALIGN_MCOMMA_VALUE                      =>     ("1010000011"),
+        ALIGN_PCOMMA_DET                        =>     ("TRUE"),
+        ALIGN_PCOMMA_VALUE                      =>     ("0101111100"),
+        SHOW_REALIGN_COMMA                      =>     ("FALSE"),
+        RXSLIDE_AUTO_WAIT                       =>     (7),
+        RXSLIDE_MODE                            =>     ("PCS"),
+        RX_SIG_VALID_DLY                        =>     (10),
+
+       ------------------RX 8B/10B Decoder Attributes---------------
+        RX_DISPERR_SEQ_MATCH                    =>     ("TRUE"),
+        DEC_MCOMMA_DETECT                       =>     ("TRUE"),
+        DEC_PCOMMA_DETECT                       =>     ("TRUE"),
+        DEC_VALID_COMMA_ONLY                    =>     ("TRUE"),
+
+       ------------------------RX Clock Correction Attributes----------------------
+        CBCC_DATA_SOURCE_SEL                    =>     ("DECODED"),
+        CLK_COR_SEQ_2_USE                       =>     ("FALSE"),
+        CLK_COR_KEEP_IDLE                       =>     ("FALSE"),
+        CLK_COR_MAX_LAT                         =>     (10),
+        CLK_COR_MIN_LAT                         =>     (8),
+        CLK_COR_PRECEDENCE                      =>     ("TRUE"),
+        CLK_COR_REPEAT_WAIT                     =>     (0),
+        CLK_COR_SEQ_LEN                         =>     (1),
+        CLK_COR_SEQ_1_ENABLE                    =>     ("1111"),
+        CLK_COR_SEQ_1_1                         =>     ("0100000000"),
+        CLK_COR_SEQ_1_2                         =>     ("0000000000"),
+        CLK_COR_SEQ_1_3                         =>     ("0000000000"),
+        CLK_COR_SEQ_1_4                         =>     ("0000000000"),
+        CLK_CORRECT_USE                         =>     ("FALSE"),
+        CLK_COR_SEQ_2_ENABLE                    =>     ("1111"),
+        CLK_COR_SEQ_2_1                         =>     ("0100000000"),
+        CLK_COR_SEQ_2_2                         =>     ("0000000000"),
+        CLK_COR_SEQ_2_3                         =>     ("0000000000"),
+        CLK_COR_SEQ_2_4                         =>     ("0000000000"),
+
+       ------------------------RX Channel Bonding Attributes----------------------
+        CHAN_BOND_KEEP_ALIGN                    =>     ("FALSE"),
+        CHAN_BOND_MAX_SKEW                      =>     (1),
+        CHAN_BOND_SEQ_LEN                       =>     (1),
+        CHAN_BOND_SEQ_1_1                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_1_2                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_1_3                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_1_4                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_1_ENABLE                  =>     ("1111"),
+        CHAN_BOND_SEQ_2_1                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_2_2                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_2_3                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_2_4                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_2_ENABLE                  =>     ("1111"),
+        CHAN_BOND_SEQ_2_USE                     =>     ("FALSE"),
+        FTS_DESKEW_SEQ_ENABLE                   =>     ("1111"),
+        FTS_LANE_DESKEW_CFG                     =>     ("1111"),
+        FTS_LANE_DESKEW_EN                      =>     ("FALSE"),
+
+       ---------------------------RX Margin Analysis Attributes----------------------------
+        ES_CONTROL                              =>     ("000000"),
+        ES_ERRDET_EN                            =>     ("FALSE"),
+        ES_EYE_SCAN_EN                          =>     ("FALSE"),
+        ES_HORZ_OFFSET                          =>     (x"010"),
+        ES_PMA_CFG                              =>     ("0000000000"),
+        ES_PRESCALE                             =>     ("00000"),
+        ES_QUALIFIER                            =>     (x"00000000000000000000"),
+        ES_QUAL_MASK                            =>     (x"00000000000000000000"),
+        ES_SDATA_MASK                           =>     (x"00000000000000000000"),
+        ES_VERT_OFFSET                          =>     ("000000000"),
+
+       -------------------------FPGA RX Interface Attributes-------------------------
+        RX_DATA_WIDTH                           =>     (20),
+
+       ---------------------------PMA Attributes----------------------------
+        OUTREFCLK_SEL_INV                       =>     ("11"),
+        PMA_RSV                                 =>     (x"00000333"),
+        PMA_RSV2                                =>     (x"00002040"),
+        PMA_RSV3                                =>     ("00"),
+        PMA_RSV4                                =>     ("0000"),
+        RX_BIAS_CFG                             =>     ("0000111100110011"),
+        DMONITOR_CFG                            =>     (x"000A00"),
+        RX_CM_SEL                               =>     ("01"),
+        RX_CM_TRIM                              =>     ("0000"),
+        RX_DEBUG_CFG                            =>     ("00000000000000"),
+        RX_OS_CFG                               =>     ("0000010000000"),
+        TERM_RCAL_CFG                           =>     ("100001000010000"),
+        TERM_RCAL_OVRD                          =>     ("000"),
+        TST_RSV                                 =>     (x"00000000"),
+        RX_CLK25_DIV                            =>     (5),
+        TX_CLK25_DIV                            =>     (5),
+        UCODEER_CLR                             =>     ('0'),
+
+       ---------------------------PCI Express Attributes----------------------------
+        PCS_PCIE_EN                             =>     ("FALSE"),
+
+       ---------------------------PCS Attributes----------------------------
+        PCS_RSVD_ATTR                           =>     (x"000000000000"),
+
+       -------------RX Buffer Attributes------------
+        RXBUF_ADDR_MODE                         =>     ("FAST"),
+        RXBUF_EIDLE_HI_CNT                      =>     ("1000"),
+        RXBUF_EIDLE_LO_CNT                      =>     ("0000"),
+        RXBUF_EN                                =>     ("TRUE"),
+        RX_BUFFER_CFG                           =>     ("000000"),
+        RXBUF_RESET_ON_CB_CHANGE                =>     ("TRUE"),
+        RXBUF_RESET_ON_COMMAALIGN               =>     ("FALSE"),
+        RXBUF_RESET_ON_EIDLE                    =>     ("FALSE"),
+        RXBUF_RESET_ON_RATE_CHANGE              =>     ("TRUE"),
+        RXBUFRESET_TIME                         =>     ("00001"),
+        RXBUF_THRESH_OVFLW                      =>     (61),
+        RXBUF_THRESH_OVRD                       =>     ("FALSE"),
+        RXBUF_THRESH_UNDFLW                     =>     (4),
+        RXDLY_CFG                               =>     (x"001F"),
+        RXDLY_LCFG                              =>     (x"030"),
+        RXDLY_TAP_CFG                           =>     (x"0000"),
+        RXPH_CFG                                =>     (x"C00002"),
+        RXPHDLY_CFG                             =>     (x"084020"),
+        RXPH_MONITOR_SEL                        =>     ("00000"),
+        RX_XCLK_SEL                             =>     ("RXREC"),
+        RX_DDI_SEL                              =>     ("000000"),
+        RX_DEFER_RESET_BUF_EN                   =>     ("TRUE"),
+
+       -----------------------CDR Attributes-------------------------
+
+       --For Display Port, HBR/RBR- set RXCDR_CFG=72'h0380008bff40200008
+
+       --For Display Port, HBR2 -   set RXCDR_CFG=72'h038c008bff20200010
+
+       --For SATA Gen1 GTX- set RXCDR_CFG=72'h03_8000_8BFF_4010_0008
+
+       --For SATA Gen2 GTX- set RXCDR_CFG=72'h03_8800_8BFF_4020_0008
+
+       --For SATA Gen3 GTX- set RXCDR_CFG=72'h03_8000_8BFF_1020_0010
+
+       --For SATA Gen3 GTP- set RXCDR_CFG=83'h0_0000_87FE_2060_2444_1010
+
+       --For SATA Gen2 GTP- set RXCDR_CFG=83'h0_0000_47FE_2060_2448_1010
+
+       --For SATA Gen1 GTP- set RXCDR_CFG=83'h0_0000_47FE_1060_2448_1010
+        RXCDR_CFG                               =>     (x"0000107FE106001041010"),
+        RXCDR_FR_RESET_ON_EIDLE                 =>     ('0'),
+        RXCDR_HOLD_DURING_EIDLE                 =>     ('0'),
+        RXCDR_PH_RESET_ON_EIDLE                 =>     ('0'),
+        RXCDR_LOCK_CFG                          =>     ("001001"),
+
+       -------------------RX Initialization and Reset Attributes-------------------
+        RXCDRFREQRESET_TIME                     =>     ("00001"),
+        RXCDRPHRESET_TIME                       =>     ("00001"),
+        RXISCANRESET_TIME                       =>     ("00001"),
+        RXPCSRESET_TIME                         =>     ("00001"),
+        RXPMARESET_TIME                         =>     ("00011"),
+
+       -------------------RX OOB Signaling Attributes-------------------
+        RXOOB_CFG                               =>     ("0000110"),
+
+       -------------------------RX Gearbox Attributes---------------------------
+        RXGEARBOX_EN                            =>     ("FALSE"),
+        GEARBOX_MODE                            =>     ("000"),
+
+       -------------------------PRBS Detection Attribute-----------------------
+        RXPRBS_ERR_LOOPBACK                     =>     ('0'),
+
+       -------------Power-Down Attributes----------
+        PD_TRANS_TIME_FROM_P2                   =>     (x"03c"),
+        PD_TRANS_TIME_NONE_P2                   =>     (x"3c"),
+        PD_TRANS_TIME_TO_P2                     =>     (x"64"),
+
+       -------------RX OOB Signaling Attributes----------
+        SAS_MAX_COM                             =>     (64),
+        SAS_MIN_COM                             =>     (36),
+        SATA_BURST_SEQ_LEN                      =>     ("0101"),
+        SATA_BURST_VAL                          =>     ("100"),
+        SATA_EIDLE_VAL                          =>     ("100"),
+        SATA_MAX_BURST                          =>     (8),
+        SATA_MAX_INIT                           =>     (21),
+        SATA_MAX_WAKE                           =>     (7),
+        SATA_MIN_BURST                          =>     (4),
+        SATA_MIN_INIT                           =>     (12),
+        SATA_MIN_WAKE                           =>     (4),
+
+       -------------RX Fabric Clock Output Control Attributes----------
+        TRANS_TIME_RATE                         =>     (x"0E"),
+
+       --------------TX Buffer Attributes----------------
+        TXBUF_EN                                =>     ("TRUE"),
+        TXBUF_RESET_ON_RATE_CHANGE              =>     ("TRUE"),
+        TXDLY_CFG                               =>     (x"001F"),
+        TXDLY_LCFG                              =>     (x"030"),
+        TXDLY_TAP_CFG                           =>     (x"0000"),
+        TXPH_CFG                                =>     (x"0780"),
+        TXPHDLY_CFG                             =>     (x"084020"),
+        TXPH_MONITOR_SEL                        =>     ("00000"),
+        TX_XCLK_SEL                             =>     ("TXOUT"),
+
+       -------------------------FPGA TX Interface Attributes-------------------------
+        TX_DATA_WIDTH                           =>     (20),
+
+       -------------------------TX Configurable Driver Attributes-------------------------
+        TX_DEEMPH0                              =>     ("000000"),
+        TX_DEEMPH1                              =>     ("000000"),
+        TX_EIDLE_ASSERT_DELAY                   =>     ("110"),
+        TX_EIDLE_DEASSERT_DELAY                 =>     ("100"),
+        TX_LOOPBACK_DRIVE_HIZ                   =>     ("FALSE"),
+        TX_MAINCURSOR_SEL                       =>     ('0'),
+        TX_DRIVE_MODE                           =>     ("DIRECT"),
+        TX_MARGIN_FULL_0                        =>     ("1001110"),
+        TX_MARGIN_FULL_1                        =>     ("1001001"),
+        TX_MARGIN_FULL_2                        =>     ("1000101"),
+        TX_MARGIN_FULL_3                        =>     ("1000010"),
+        TX_MARGIN_FULL_4                        =>     ("1000000"),
+        TX_MARGIN_LOW_0                         =>     ("1000110"),
+        TX_MARGIN_LOW_1                         =>     ("1000100"),
+        TX_MARGIN_LOW_2                         =>     ("1000010"),
+        TX_MARGIN_LOW_3                         =>     ("1000000"),
+        TX_MARGIN_LOW_4                         =>     ("1000000"),
+
+       -------------------------TX Gearbox Attributes--------------------------
+        TXGEARBOX_EN                            =>     ("FALSE"),
+
+       -------------------------TX Initialization and Reset Attributes--------------------------
+        TXPCSRESET_TIME                         =>     ("00001"),
+        TXPMARESET_TIME                         =>     ("00001"),
+
+       -------------------------TX Receiver Detection Attributes--------------------------
+        TX_RXDETECT_CFG                         =>     (x"1832"),
+        TX_RXDETECT_REF                         =>     ("100"),
+
+       ------------------ JTAG Attributes ---------------
+        ACJTAG_DEBUG_MODE                       =>     ('0'),
+        ACJTAG_MODE                             =>     ('0'),
+        ACJTAG_RESET                            =>     ('0'),
+
+       ------------------ CDR Attributes ---------------
+        CFOK_CFG                                =>     (x"49000040E80"),
+        CFOK_CFG2                               =>     ("0100000"),
+        CFOK_CFG3                               =>     ("0100000"),
+        CFOK_CFG4                               =>     ('0'),
+        CFOK_CFG5                               =>     (x"0"),
+        CFOK_CFG6                               =>     ("0000"),
+        RXOSCALRESET_TIME                       =>     ("00011"),
+        RXOSCALRESET_TIMEOUT                    =>     ("00000"),
+
+       ------------------ PMA Attributes ---------------
+        CLK_COMMON_SWING                        =>     ('0'),
+        RX_CLKMUX_EN                            =>     ('1'),
+        TX_CLKMUX_EN                            =>     ('1'),
+        ES_CLK_PHASE_SEL                        =>     ('0'),
+        USE_PCS_CLK_PHASE_SEL                   =>     ('0'),
+        PMA_RSV6                                =>     ('0'),
+        PMA_RSV7                                =>     ('0'),
+
+       ------------------ TX Configuration Driver Attributes ---------------
+        TX_PREDRIVER_MODE                       =>     ('0'),
+        PMA_RSV5                                =>     ('0'),
+        SATA_PLL_CFG                            =>     ("VCO_3000MHZ"),
+
+       ------------------ RX Fabric Clock Output Control Attributes ---------------
+        RXOUT_DIV                               =>     (4),
+
+       ------------------ TX Fabric Clock Output Control Attributes ---------------
+        TXOUT_DIV                               =>     (4),
+
+       ------------------ RX Phase Interpolator Attributes---------------
+        RXPI_CFG0                               =>     ("000"),
+        RXPI_CFG1                               =>     ('1'),
+        RXPI_CFG2                               =>     ('1'),
+
+       --------------RX Equalizer Attributes-------------
+        ADAPT_CFG0                              =>     (x"00000"),
+        RXLPMRESET_TIME                         =>     ("0001111"),
+        RXLPM_BIAS_STARTUP_DISABLE              =>     ('0'),
+        RXLPM_CFG                               =>     ("0110"),
+        RXLPM_CFG1                              =>     ('0'),
+        RXLPM_CM_CFG                            =>     ('0'),
+        RXLPM_GC_CFG                            =>     ("111100010"),
+        RXLPM_GC_CFG2                           =>     ("001"),
+        RXLPM_HF_CFG                            =>     ("00001111110000"),
+        RXLPM_HF_CFG2                           =>     ("01010"),
+        RXLPM_HF_CFG3                           =>     ("0000"),
+        RXLPM_HOLD_DURING_EIDLE                 =>     ('0'),
+        RXLPM_INCM_CFG                          =>     ('0'),
+        RXLPM_IPCM_CFG                          =>     ('1'),
+        RXLPM_LF_CFG                            =>     ("000000001111110000"),
+        RXLPM_LF_CFG2                           =>     ("01010"),
+        RXLPM_OSINT_CFG                         =>     ("100"),
+
+       ------------------ TX Phase Interpolator PPM Controller Attributes---------------
+        TXPI_CFG0                               =>     ("00"),
+        TXPI_CFG1                               =>     ("00"),
+        TXPI_CFG2                               =>     ("00"),
+        TXPI_CFG3                               =>     ('0'),
+        TXPI_CFG4                               =>     ('0'),
+        TXPI_CFG5                               =>     ("000"),
+        TXPI_GREY_SEL                           =>     ('0'),
+        TXPI_INVSTROBE_SEL                      =>     ('0'),
+        TXPI_PPMCLK_SEL                         =>     ("TXUSRCLK2"),
+        TXPI_PPM_CFG                            =>     (x"00"),
+        TXPI_SYNFREQ_PPM                        =>     ("001"),
+
+       ------------------ LOOPBACK Attributes---------------
+        LOOPBACK_CFG                            =>     ('0'),
+        PMA_LOOPBACK_CFG                        =>     ('0'),
+
+       ------------------RX OOB Signalling Attributes---------------
+        RXOOB_CLK_CFG                           =>     ("PMA"),
+
+       ------------------TX OOB Signalling Attributes---------------
+        TXOOB_CFG                               =>     ('0'),
+
+       ------------------RX Buffer Attributes---------------
+        RXSYNC_MULTILANE                        =>     ('0'),
+        RXSYNC_OVRD                             =>     ('0'),
+        RXSYNC_SKIP_DA                          =>     ('0'),
+
+       ------------------TX Buffer Attributes---------------
+        TXSYNC_MULTILANE                        =>     (TXSYNC_MULTILANE_IN),
+        TXSYNC_OVRD                             =>     (TXSYNC_OVRD_IN),
+        TXSYNC_SKIP_DA                          =>     ('0')
+
+
+    )
+    port map
+    (
+                                --------------------------------- CPLL Ports -------------------------------
+        GTRSVD                          =>      "0000000000000000",
+        PCSRSVDIN                       =>      "0000000000000000",
+        TSTIN                           =>      "11111111111111111111",
+        ---------------------------- Channel - DRP Ports  --------------------------
+        DRPADDR                         =>      drpaddr_i,
+        DRPCLK                          =>      DRPCLK_IN,
+        DRPDI                           =>      drpdi_i,
+        DRPDO                           =>      drpdo_i,
+        DRPEN                           =>      drpen_i,
+        DRPRDY                          =>      drprdy_i,
+        DRPWE                           =>      drpwe_i,
+        ------------------------------- Clocking Ports -----------------------------
+        RXSYSCLKSEL                     =>      "11",
+        TXSYSCLKSEL                     =>      "11",
+        ----------------- FPGA TX Interface Datapath Configuration  ----------------
+        TX8B10BEN                       =>      tied_to_vcc_i,
+        ------------------------ GTPE2_CHANNEL Clocking Ports ----------------------
+        PLL0CLK                         =>      PLL0CLK_IN,
+        PLL0REFCLK                      =>      PLL0REFCLK_IN,
+        PLL1CLK                         =>      PLL1CLK_IN,
+        PLL1REFCLK                      =>      PLL1REFCLK_IN,
+        ------------------------------- Loopback Ports -----------------------------
+        LOOPBACK                        =>      LOOPBACK_IN,
+        ----------------------------- PCI Express Ports ----------------------------
+        PHYSTATUS                       =>      open,
+        RXRATE                          =>      tied_to_ground_vec_i(2 downto 0),
+        RXVALID                         =>      open,
+        ----------------------------- PMA Reserved Ports ---------------------------
+        PMARSVDIN3                      =>      '0',
+        PMARSVDIN4                      =>      '0',
+        ------------------------------ Power-Down Ports ----------------------------
+        RXPD                            =>      "00",
+        TXPD                            =>      "00",
+        -------------------------- RX 8B/10B Decoder Ports -------------------------
+        SETERRSTATUS                    =>      tied_to_ground_i,
+        --------------------- RX Initialization and Reset Ports --------------------
+        EYESCANRESET                    =>      tied_to_ground_i,
+        RXUSERRDY                       =>      RXUSERRDY_IN,
+        -------------------------- RX Margin Analysis Ports ------------------------
+        EYESCANDATAERROR                =>      EYESCANDATAERROR_OUT,
+        EYESCANMODE                     =>      tied_to_ground_i,
+        EYESCANTRIGGER                  =>      tied_to_ground_i,
+        ------------------------------- Receive Ports ------------------------------
+        CLKRSVD0                        =>      tied_to_ground_i,
+        CLKRSVD1                        =>      tied_to_ground_i,
+        DMONFIFORESET                   =>      tied_to_ground_i,
+        DMONITORCLK                     =>      tied_to_ground_i,
+        RXPMARESETDONE                  =>      rxpmaresetdone_t,
+        SIGVALIDCLK                     =>      tied_to_ground_i,
+        ------------------------- Receive Ports - CDR Ports ------------------------
+        RXCDRFREQRESET                  =>      tied_to_ground_i,
+        RXCDRHOLD                       =>      tied_to_ground_i,
+        RXCDRLOCK                       =>      open,
+        RXCDROVRDEN                     =>      tied_to_ground_i,
+        RXCDRRESET                      =>      tied_to_ground_i,
+        RXCDRRESETRSV                   =>      tied_to_ground_i,
+        RXOSCALRESET                    =>      tied_to_ground_i,
+        RXOSINTCFG                      =>      "0010",
+        RXOSINTDONE                     =>      open,
+        RXOSINTHOLD                     =>      tied_to_ground_i,
+        RXOSINTOVRDEN                   =>      tied_to_ground_i,
+        RXOSINTPD                       =>      tied_to_ground_i,
+        RXOSINTSTARTED                  =>      open,
+        RXOSINTSTROBE                   =>      tied_to_ground_i,
+        RXOSINTSTROBESTARTED            =>      open,
+        RXOSINTTESTOVRDEN               =>      tied_to_ground_i,
+        ------------------- Receive Ports - Clock Correction Ports -----------------
+        RXCLKCORCNT                     =>      open,
+        ---------- Receive Ports - FPGA RX Interface Datapath Configuration --------
+        RX8B10BEN                       =>      tied_to_vcc_i,
+        ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+        RXDATA                          =>      rxdata_i,
+        RXUSRCLK                        =>      RXUSRCLK_IN,
+        RXUSRCLK2                       =>      RXUSRCLK2_IN,
+        ------------------- Receive Ports - Pattern Checker Ports ------------------
+        RXPRBSERR                       =>      open,
+        RXPRBSSEL                       =>      tied_to_ground_vec_i(2 downto 0),
+        ------------------- Receive Ports - Pattern Checker ports ------------------
+        RXPRBSCNTRESET                  =>      tied_to_ground_i,
+        ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+        RXCHARISCOMMA(3 downto 2)       =>      rxchariscomma_float_i,
+        RXCHARISCOMMA(1 downto 0)       =>      RXCHARISCOMMA_OUT,
+        RXCHARISK(3 downto 2)           =>      rxcharisk_float_i,
+        RXCHARISK(1 downto 0)           =>      RXCHARISK_OUT,
+        RXDISPERR(3 downto 2)           =>      rxdisperr_float_i,
+        RXDISPERR(1 downto 0)           =>      RXDISPERR_OUT,
+        RXNOTINTABLE(3 downto 2)        =>      rxnotintable_float_i,
+        RXNOTINTABLE(1 downto 0)        =>      RXNOTINTABLE_OUT,
+        ------------------------ Receive Ports - RX AFE Ports ----------------------
+        GTPRXN                          =>      GTPRXN_IN,
+        GTPRXP                          =>      GTPRXP_IN,
+        PMARSVDIN2                      =>      '0',
+        PMARSVDOUT0                     =>      open,
+        PMARSVDOUT1                     =>      open,
+        ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+        RXBUFRESET                      =>      tied_to_ground_i,
+        RXBUFSTATUS                     =>      open,
+        RXDDIEN                         =>      tied_to_ground_i,
+        RXDLYBYPASS                     =>      tied_to_vcc_i,
+        RXDLYEN                         =>      tied_to_ground_i,
+        RXDLYOVRDEN                     =>      tied_to_ground_i,
+        RXDLYSRESET                     =>      tied_to_ground_i,
+        RXDLYSRESETDONE                 =>      open,
+        RXPHALIGN                       =>      tied_to_ground_i,
+        RXPHALIGNDONE                   =>      open,
+        RXPHALIGNEN                     =>      tied_to_ground_i,
+        RXPHDLYPD                       =>      tied_to_ground_i,
+        RXPHDLYRESET                    =>      tied_to_ground_i,
+        RXPHMONITOR                     =>      open,
+        RXPHOVRDEN                      =>      tied_to_ground_i,
+        RXPHSLIPMONITOR                 =>      open,
+        RXSTATUS                        =>      open,
+        RXSYNCALLIN                     =>      tied_to_ground_i,
+        RXSYNCDONE                      =>      open,
+        RXSYNCIN                        =>      tied_to_ground_i,
+        RXSYNCMODE                      =>      tied_to_ground_i,
+        RXSYNCOUT                       =>      open,
+        -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
+        RXBYTEISALIGNED                 =>      RXBYTEISALIGNED_OUT,
+        RXBYTEREALIGN                   =>      open,
+        RXCOMMADET                      =>      RXCOMMADET_OUT,
+        RXCOMMADETEN                    =>      tied_to_vcc_i,
+        RXMCOMMAALIGNEN                 =>      tied_to_ground_i,
+        RXPCOMMAALIGNEN                 =>      tied_to_ground_i,
+        RXSLIDE                         =>      RXSLIDE_IN,
+        ------------------ Receive Ports - RX Channel Bonding Ports ----------------
+        RXCHANBONDSEQ                   =>      open,
+        RXCHBONDEN                      =>      tied_to_ground_i,
+        RXCHBONDI                       =>      "0000",
+        RXCHBONDLEVEL                   =>      tied_to_ground_vec_i(2 downto 0),
+        RXCHBONDMASTER                  =>      tied_to_ground_i,
+        RXCHBONDO                       =>      open,
+        RXCHBONDSLAVE                   =>      tied_to_ground_i,
+        ----------------- Receive Ports - RX Channel Bonding Ports  ----------------
+        RXCHANISALIGNED                 =>      open,
+        RXCHANREALIGN                   =>      open,
+        ------------ Receive Ports - RX Decision Feedback Equalizer(DFE) -----------
+        DMONITOROUT                     =>      open,
+        RXADAPTSELTEST                  =>      tied_to_ground_vec_i(13 downto 0),
+        RXDFEXYDEN                      =>      tied_to_ground_i,
+        RXOSINTEN                       =>      '1',
+        RXOSINTID0                      =>      tied_to_ground_vec_i(3 downto 0),
+        RXOSINTNTRLEN                   =>      tied_to_ground_i,
+        RXOSINTSTROBEDONE               =>      open,
+        ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
+        RXLPMLFOVRDEN                   =>      tied_to_ground_i,
+        RXLPMOSINTNTRLEN                =>      tied_to_ground_i,
+        -------------------- Receive Ports - RX Equailizer Ports -------------------
+        RXLPMHFHOLD                     =>      rxlpmhfhold_in,
+        RXLPMHFOVRDEN                   =>      tied_to_ground_i,
+        RXLPMLFHOLD                     =>      rxlpmlfhold_in,
+        --------------------- Receive Ports - RX Equalizer Ports -------------------
+        RXOSHOLD                        =>      tied_to_ground_i,
+        RXOSOVRDEN                      =>      tied_to_ground_i,
+        ------------ Receive Ports - RX Fabric ClocK Output Control Ports ----------
+        RXRATEDONE                      =>      open,
+        ----------- Receive Ports - RX Fabric Clock Output Control Ports  ----------
+        RXRATEMODE                      =>      '0',
+        --------------- Receive Ports - RX Fabric Output Control Ports -------------
+        RXOUTCLK                        =>      RXOUTCLK_OUT,
+        RXOUTCLKFABRIC                  =>      open,
+        RXOUTCLKPCS                     =>      open,
+        RXOUTCLKSEL                     =>      "010",
+        ---------------------- Receive Ports - RX Gearbox Ports --------------------
+        RXDATAVALID                     =>      open,
+        RXHEADER                        =>      open,
+        RXHEADERVALID                   =>      open,
+        RXSTARTOFSEQ                    =>      open,
+        --------------------- Receive Ports - RX Gearbox Ports  --------------------
+        RXGEARBOXSLIP                   =>      tied_to_ground_i,
+        ------------- Receive Ports - RX Initialization and Reset Ports ------------
+        GTRXRESET                       =>      gtrxreset_out,
+        RXLPMRESET                      =>      tied_to_ground_i,
+        RXOOBRESET                      =>      tied_to_ground_i,
+        RXPCSRESET                      =>      tied_to_ground_i,
+        RXPMARESET                      =>      tied_to_ground_i,
+        ------------------- Receive Ports - RX OOB Signaling ports -----------------
+        RXCOMSASDET                     =>      open,
+        RXCOMWAKEDET                    =>      open,
+        ------------------ Receive Ports - RX OOB Signaling ports  -----------------
+        RXCOMINITDET                    =>      open,
+        ------------------ Receive Ports - RX OOB signalling Ports -----------------
+        RXELECIDLE                      =>      open,
+        RXELECIDLEMODE                  =>      "11",
+        ----------------- Receive Ports - RX Polarity Control Ports ----------------
+        RXPOLARITY                      =>      tied_to_ground_i,
+        -------------- Receive Ports -RX Initialization and Reset Ports ------------
+        RXRESETDONE                     =>      RXRESETDONE_OUT,
+        --------------------------- TX Buffer Bypass Ports -------------------------
+        TXPHDLYTSTCLK                   =>      tied_to_ground_i,
+        ------------------------ TX Configurable Driver Ports ----------------------
+        TXPOSTCURSOR                    =>      "00000",
+        TXPOSTCURSORINV                 =>      tied_to_ground_i,
+        TXPRECURSOR                     =>      tied_to_ground_vec_i(4 downto 0),
+        TXPRECURSORINV                  =>      tied_to_ground_i,
+        -------------------- TX Fabric Clock Output Control Ports ------------------
+        TXRATEMODE                      =>      tied_to_ground_i,
+        --------------------- TX Initialization and Reset Ports --------------------
+        CFGRESET                        =>      tied_to_ground_i,
+        GTTXRESET                       =>      GTTXRESET_IN,
+        PCSRSVDOUT                      =>      open,
+        TXUSERRDY                       =>      TXUSERRDY_IN,
+        ----------------- TX Phase Interpolator PPM Controller Ports ---------------
+        TXPIPPMEN                       =>      tied_to_ground_i,
+        TXPIPPMOVRDEN                   =>      tied_to_ground_i,
+        TXPIPPMPD                       =>      tied_to_ground_i,
+        TXPIPPMSEL                      =>      tied_to_vcc_i,
+        TXPIPPMSTEPSIZE                 =>      tied_to_ground_vec_i(4 downto 0),
+        ---------------------- Transceiver Reset Mode Operation --------------------
+        GTRESETSEL                      =>      tied_to_ground_i,
+        RESETOVRD                       =>      tied_to_ground_i,
+        ------------------------------- Transmit Ports -----------------------------
+        TXPMARESETDONE                  =>      open,
+        ----------------- Transmit Ports - Configurable Driver Ports ---------------
+        PMARSVDIN0                      =>      '0',
+        PMARSVDIN1                      =>      '0',
+        ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+        TXDATA                          =>      txdata_i,
+        TXUSRCLK                        =>      TXUSRCLK_IN,
+        TXUSRCLK2                       =>      TXUSRCLK2_IN,
+        --------------------- Transmit Ports - PCI Express Ports -------------------
+        TXELECIDLE                      =>      tied_to_ground_i,
+        TXMARGIN                        =>      tied_to_ground_vec_i(2 downto 0),
+        TXRATE                          =>      tied_to_ground_vec_i(2 downto 0),
+        TXSWING                         =>      tied_to_ground_i,
+        ------------------ Transmit Ports - Pattern Generator Ports ----------------
+        TXPRBSFORCEERR                  =>      tied_to_ground_i,
+        ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
+        TX8B10BBYPASS                   =>      tied_to_ground_vec_i(3 downto 0),
+        TXCHARDISPMODE                  =>      tied_to_ground_vec_i(3 downto 0),
+        TXCHARDISPVAL                   =>      tied_to_ground_vec_i(3 downto 0),
+        TXCHARISK(3 downto 2)           =>      tied_to_ground_vec_i(1 downto 0),
+        TXCHARISK(1 downto 0)           =>      TXCHARISK_IN,
+        ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+        TXDLYBYPASS                     =>      tied_to_vcc_i,
+        TXDLYEN                         =>      tied_to_ground_i,
+        TXDLYHOLD                       =>      tied_to_ground_i,
+        TXDLYOVRDEN                     =>      tied_to_ground_i,
+        TXDLYSRESET                     =>      tied_to_ground_i,
+        TXDLYSRESETDONE                 =>      open,
+        TXDLYUPDOWN                     =>      tied_to_ground_i,
+        TXPHALIGN                       =>      tied_to_ground_i,
+        TXPHALIGNDONE                   =>      open,
+        TXPHALIGNEN                     =>      tied_to_ground_i,
+        TXPHDLYPD                       =>      tied_to_ground_i,
+        TXPHDLYRESET                    =>      tied_to_ground_i,
+        TXPHINIT                        =>      tied_to_ground_i,
+        TXPHINITDONE                    =>      open,
+        TXPHOVRDEN                      =>      tied_to_ground_i,
+        ---------------------- Transmit Ports - TX Buffer Ports --------------------
+        TXBUFSTATUS                     =>      open,
+        ------------ Transmit Ports - TX Buffer and Phase Alignment Ports ----------
+        TXSYNCALLIN                     =>      tied_to_ground_i,
+        TXSYNCDONE                      =>      open,
+        TXSYNCIN                        =>      tied_to_ground_i,
+        TXSYNCMODE                      =>      tied_to_ground_i,
+        TXSYNCOUT                       =>      open,
+        --------------- Transmit Ports - TX Configurable Driver Ports --------------
+        GTPTXN                          =>      GTPTXN_OUT,
+        GTPTXP                          =>      GTPTXP_OUT,
+        TXBUFDIFFCTRL                   =>      "100",
+        TXDEEMPH                        =>      tied_to_ground_i,
+        TXDIFFCTRL                      =>      "1000",
+        TXDIFFPD                        =>      tied_to_ground_i,
+        TXINHIBIT                       =>      tied_to_ground_i,
+        TXMAINCURSOR                    =>      "0000000",
+        TXPISOPD                        =>      tied_to_ground_i,
+        ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+        TXOUTCLK                        =>      TXOUTCLK_OUT,
+        TXOUTCLKFABRIC                  =>      TXOUTCLKFABRIC_OUT,
+        TXOUTCLKPCS                     =>      TXOUTCLKPCS_OUT,
+        TXOUTCLKSEL                     =>      "010",
+        TXRATEDONE                      =>      open,
+        --------------------- Transmit Ports - TX Gearbox Ports --------------------
+        TXGEARBOXREADY                  =>      open,
+        TXHEADER                        =>      tied_to_ground_vec_i(2 downto 0),
+        TXSEQUENCE                      =>      tied_to_ground_vec_i(6 downto 0),
+        TXSTARTSEQ                      =>      tied_to_ground_i,
+        ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+        TXPCSRESET                      =>      tied_to_ground_i,
+        TXPMARESET                      =>      tied_to_ground_i,
+        TXRESETDONE                     =>      TXRESETDONE_OUT,
+        ------------------ Transmit Ports - TX OOB signalling Ports ----------------
+        TXCOMFINISH                     =>      open,
+        TXCOMINIT                       =>      tied_to_ground_i,
+        TXCOMSAS                        =>      tied_to_ground_i,
+        TXCOMWAKE                       =>      tied_to_ground_i,
+        TXPDELECIDLEMODE                =>      tied_to_ground_i,
+        ----------------- Transmit Ports - TX Polarity Control Ports ---------------
+        TXPOLARITY                      =>      tied_to_ground_i,
+        --------------- Transmit Ports - TX Receiver Detection Ports  --------------
+        TXDETECTRX                      =>      tied_to_ground_i,
+        ------------------ Transmit Ports - pattern Generator Ports ----------------
+        TXPRBSSEL                       =>      TXPRBSSEL_IN
+
+    );
+
+     ------------------------- Soft Fix for Production Silicon----------------------
+       gtrxreset_seq_i  : whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq 
+       port map
+            (
+        RST                             =>      RST_IN,
+        GTRXRESET_IN                    =>      GTRXRESET_IN,
+        RXPMARESETDONE                  =>      rxpmaresetdone_t,
+        GTRXRESET_OUT                   =>      gtrxreset_out,
+        DRP_OP_DONE                     =>      drp_op_done,
+        DRPCLK                          =>      DRPCLK_IN,
+        DRPEN                           =>      drpen_rst_t,
+        DRPADDR                         =>      drpaddr_rst_t,
+        DRPWE                           =>      drpwe_rst_t,
+        DRPDO                           =>      drpdo_rst_t,
+        DRPDI                           =>      drpdi_rst_t,
+        DRPRDY                          =>      drprdy_rst_t
+            ); 
+
+
+      drpen_i       <= drpen_rst_t     when drp_op_done ='0'   else
+                       drpen_pma_t     when drp_pma_busy = '1' else
+                       drpen_rate_t    when drp_rate_busy ='1' else DRPEN_IN;
+
+
+      drpaddr_i     <= drpaddr_rst_t   when drp_op_done ='0'   else
+                       drpaddr_pma_t   when drp_pma_busy = '1' else
+                       drpaddr_rate_t  when drp_rate_busy ='1' else DRPADDR_IN;
+
+
+      drpwe_i       <= drpwe_rst_t     when drp_op_done ='0'   else
+                       drpwe_pma_t     when drp_pma_busy = '1' else
+                       drpwe_rate_t    when drp_rate_busy ='1' else DRPWE_IN;
+
+
+
+      DRPDO_OUT      <=  drpdo_i when (drp_op_done='1' or drp_pma_busy='0' or drp_rate_busy='0') else x"0000";
+
+      drpdo_rst_t    <=  drpdo_i;
+
+      drpdo_pma_t    <=  drpdo_i;
+
+      drpdo_rate_t   <=  drpdo_i;
+
+
+      drpdi_i        <=  drpdi_rst_t     when drp_op_done ='0'   else
+                         drpdi_pma_t     when drp_pma_busy = '1' else
+                         drpdi_rate_t    when drp_rate_busy ='1' else DRPDI_IN;
+
+
+      DRPRDY_OUT     <=  drprdy_i when (drp_op_done='1' or drp_pma_busy='0' or drp_rate_busy='0') else '0';
+
+      drprdy_rst_t   <=  drprdy_i;
+
+      drprdy_pma_t   <=  drprdy_i;
+
+      drprdy_rate_t  <=  drprdy_i;
+
+
+   drp_pma_busy <= '0';
+   drp_rate_busy <= '0';
+
+  process (DRPCLK_IN)
+  begin
+     if(rising_edge(DRPCLK_IN)) then
+        if(drp_op_done = '0' or drp_rate_busy='1') then
+           drp_busy_i1 <= '1';
+        else
+           drp_busy_i1 <= '0';
+        end if;
+     end if;
+  end process;
+
+  process (DRPCLK_IN)
+  begin
+     if(rising_edge(DRPCLK_IN)) then
+        if(drp_op_done = '0' or drp_pma_busy='1') then
+           drp_busy_i2 <= '1';
+        else
+           drp_busy_i2 <= '0';
+        end if;
+     end if;
+  end process;
+
+    DRP_BUSY_OUT <= drp_busy_i1 or drp_busy_i2;
+
+
+
+
+ end RTL;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq.vhd
new file mode 100644
index 000000000..5fc534d53
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq.vhd
@@ -0,0 +1,342 @@
+------------------------------------------------------------------------------/
+--   ____  ____ 
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version : 3.6
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard
+--  /   /         Filename : whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq.vhd
+-- /___/   /\     
+-- \   \  /  \ 
+--  \___\/\___\
+--
+--
+-- Module whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.gencores_pkg.all;
+
+ENTITY whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq IS
+  port ( 
+    RST           : IN  std_logic; --Please add a synchroniser if it is not generated in DRPCLK domain.
+    GTRXRESET_IN  : IN  std_logic; --Please add a synchroniser if it is not generated in DRPCLK domain.    
+    RXPMARESETDONE: IN  std_logic;
+    GTRXRESET_OUT : OUT std_logic;
+
+    DRPCLK        : IN  std_logic;
+    DRPADDR       : OUT std_logic_vector(8 downto 0);
+    DRPDO	  : IN  std_logic_vector(15 downto 0);
+    DRPDI         : OUT std_logic_vector(15 downto 0);
+    DRPRDY        : IN  std_logic;
+    DRPEN	  : OUT std_logic;
+    DRPWE         : OUT std_logic;
+    DRP_OP_DONE   : OUT std_logic
+);
+END whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq;
+
+ARCHITECTURE Behavioral of whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq is
+
+
+--  component whiterabbit_gtpe2_channel_wrapper_sync_block
+--   generic (
+--     INITIALISE : bit_vector(5 downto 0) := "000000"
+--   );
+--   port  (
+--             clk           : in  std_logic;
+--             data_in       : in  std_logic;
+--             data_out      : out std_logic
+--          );
+--   end component;
+
+  constant DLY                : time := 1 ns;
+  type state_type is (idle,
+                      drp_rd,
+                      wait_rd_data,
+                      wr_16,
+                      wait_wr_done1,
+                      wait_pmareset,
+                      wr_20,
+                      wait_wr_done2);
+
+  signal  state               : state_type := idle;
+  signal  next_state          : state_type := idle;
+  signal  gtrxreset_s         : std_logic;
+  signal  gtrxreset_ss        : std_logic;
+  signal  rxpmaresetdone_ss   : std_logic;
+  signal  rxpmaresetdone_sss  : std_logic;
+  signal  rd_data             : std_logic_vector(15 downto 0);
+  signal  next_rd_data        : std_logic_vector(15 downto 0);
+  signal  original_rd_data        : std_logic_vector(15 downto 0);
+  signal  pmarstdone_fall_edge:std_logic;
+  signal  gtrxreset_i         :std_logic;
+  signal  flag                :std_logic := '0';
+  signal  gtrxreset_o         :std_logic;
+  signal  drpen_o             :std_logic;
+  signal  drpwe_o             :std_logic;
+  signal  drpaddr_o           :std_logic_vector(8 downto 0);
+  signal  drpdi_o             :std_logic_vector(15 downto 0);
+  signal  drp_op_done_o       :std_logic;
+  signal  rst_n               :std_logic;
+BEGIN
+
+-- sync0_RXPMARESETDONE : whiterabbit_gtpe2_channel_wrapper_sync_block
+--  port map
+--         (
+--            clk             =>  DRPCLK,
+--            data_in         =>  RXPMARESETDONE,
+--            data_out        =>  rxpmaresetdone_ss
+--         );
+
+  rst_n <= not RST;
+
+  sync0_RXPMARESETDONE : gc_sync_ffs
+  port map
+         (
+            clk_i          =>  DRPCLK,
+            rst_n_i        =>  rst_n,
+            data_i         =>  RXPMARESETDONE,
+            synced_o       =>  rxpmaresetdone_ss,
+            npulse_o       =>  open,
+            ppulse_o       =>  open
+         );
+
+--output assignment	
+  GTRXRESET_OUT <= gtrxreset_o;
+  DRPEN         <= drpen_o;
+  DRPWE         <= drpwe_o;
+  DRPADDR       <= drpaddr_o;
+  DRPDI         <= drpdi_o;
+  DRP_OP_DONE   <= drp_op_done_o;
+
+  PROCESS (DRPCLK,RST)
+  BEGIN
+    IF (RST = '1') THEN
+      state              <= idle              after DLY;
+      gtrxreset_s        <= '0'               after DLY;
+      gtrxreset_ss       <= '0'               after DLY;
+      rxpmaresetdone_sss <= '0'               after DLY;
+      rd_data            <= x"0000"           after DLY;
+      gtrxreset_o        <= '0'               after DLY;
+    ELSIF (DRPCLK'event and DRPCLK='1') THEN
+      state              <= next_state        after DLY;
+      gtrxreset_s        <= GTRXRESET_IN      after DLY;
+      gtrxreset_ss       <= gtrxreset_s       after DLY;
+      rxpmaresetdone_sss <= rxpmaresetdone_ss after DLY;
+      rd_data            <= next_rd_data      after DLY;
+      gtrxreset_o        <= gtrxreset_i       after DLY;
+    END IF;
+  END PROCESS;
+
+  PROCESS (DRPCLK,GTRXRESET_IN)
+  BEGIN
+    IF (GTRXRESET_IN = '1') THEN
+       drp_op_done_o  <= '0'       after DLY;
+
+    ELSIF (DRPCLK'event and DRPCLK='1') THEN
+      IF (state = wait_wr_done2 and DRPRDY = '1') THEN
+         drp_op_done_o  <= '1'       after DLY;
+      ELSE
+         drp_op_done_o  <= drp_op_done_o       after DLY;
+      END IF;
+    END IF;
+  END PROCESS;
+
+  pmarstdone_fall_edge <= (not rxpmaresetdone_ss) and (rxpmaresetdone_sss);
+
+  PROCESS (gtrxreset_ss,DRPRDY,state,pmarstdone_fall_edge)
+  BEGIN
+    CASE state IS
+
+      WHEN idle         =>
+        IF (gtrxreset_ss='1') THEN
+          next_state <= drp_rd;
+        ELSE
+          next_state <= idle;
+	END IF;
+
+      WHEN drp_rd       =>
+	next_state<= wait_rd_data;
+
+      WHEN wait_rd_data =>
+        IF (DRPRDY='1')THEN
+          next_state <= wr_16;
+        ELSE
+          next_state <= wait_rd_data;
+        END IF;
+
+      WHEN wr_16 => 
+	next_state <= wait_wr_done1;
+
+      WHEN wait_wr_done1 => 
+	IF (DRPRDY='1') THEN
+	  next_state <= wait_pmareset;
+        ELSE
+	  next_state <= wait_wr_done1;
+        END IF;
+
+      WHEN wait_pmareset =>
+	IF (pmarstdone_fall_edge='1') THEN
+          next_state <= wr_20;
+        ELSE
+          next_state <= wait_pmareset;
+        END IF;
+
+      WHEN wr_20         =>
+        next_state <= wait_wr_done2;
+
+      WHEN wait_wr_done2 =>
+	IF (DRPRDY='1') THEN
+          next_state <= idle;
+        ELSE
+          next_state <= wait_wr_done2;
+	END IF;
+
+      WHEN others=>
+          next_state <= idle;
+ 
+    END CASE;
+  END PROCESS;
+
+-- drives DRP interface and GTRXRESET_OUT
+  PROCESS(DRPRDY,state,rd_data,DRPDO,gtrxreset_ss,flag,original_rd_data)
+  BEGIN
+-- assert gtrxreset_out until wr to 16-bit is complete
+-- RX_DATA_WIDTH is located at addr x"0011", [13 downto 11]
+-- encoding is this : /16 = x "2", /20 = x"3", /32 = x"4", /40 = x"5"
+    gtrxreset_i  <= '0';
+    drpaddr_o    <= '0'& x"11"; -- 000010001
+    drpen_o      <= '0';
+    drpwe_o      <= '0';
+    drpdi_o      <= x"0000";
+    next_rd_data <= rd_data;
+
+    CASE state IS 
+
+     --do nothing to DRP or reset
+      WHEN idle   => null;
+
+      --assert reset and issue rd
+      WHEN drp_rd => 
+	gtrxreset_i <= '1';
+       	drpen_o     <= '1';
+	drpwe_o     <= '0';
+
+      --assert reset and wait to load rd data
+      WHEN wait_rd_data =>  
+        gtrxreset_i <= '1';
+        IF (DRPRDY='1' and flag = '0') THEN
+          next_rd_data <= DRPDO;
+        ELSIF (DRPRDY='1' and flag = '1') THEN
+          next_rd_data <= original_rd_data;
+          ELSE
+            next_rd_data <= rd_data;
+          END IF;
+
+      --assert reset and write to 16-bit mode
+      WHEN wr_16=>
+	gtrxreset_i<= '1';
+ 	drpen_o    <= '1';
+	drpwe_o    <= '1';
+        -- Addr "00001001" [11] = '0' puts width mode in /16 or /32
+       drpdi_o <= rd_data(15 downto 12) & '0' & rd_data(10 downto 0);
+       
+      --keep asserting reset until write to 16-bit mode is complete
+      WHEN wait_wr_done1=> 
+	gtrxreset_i <= '1';
+
+      --deassert reset and no DRP access until 2nd pmareset
+      WHEN wait_pmareset => null;
+          IF (gtrxreset_ss='1') THEN
+             gtrxreset_i <= '1';
+          ELSE
+             gtrxreset_i <= '0';
+          END IF;
+
+      --write to 20-bit mode
+      WHEN wr_20 =>  
+        drpen_o <='1';
+        drpwe_o <= '1';
+        drpdi_o <= rd_data(15 downto 0); --restore user setting per prev read
+
+      --wait to complete write to 20-bit mode
+      WHEN wait_wr_done2 => 
+
+
+      WHEN others        => null;  
+
+     END CASE;
+  END PROCESS;
+
+  process (DRPCLK)
+  begin
+    if (DRPCLK'event and DRPCLK='1') then
+      if( state = wr_16 or state = wait_pmareset or state = wr_20 or state = wait_wr_done1) then
+        flag <= '1';
+      elsif(state = wait_wr_done2) then
+        flag <= '0';
+      end if; 
+    end if;
+  end process;
+
+  process (DRPCLK)
+  begin
+    if (DRPCLK'event and DRPCLK='1') then
+      if( state = wait_rd_data and DRPRDY ='1' and flag = '0') then
+        original_rd_data <= DRPDO;
+      end if; 
+    end if; 
+  end process;
+
+END Behavioral;
+
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/family7-gtp/wr_gtp_phy_family7.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/family7-gtp/wr_gtp_phy_family7.vhd
new file mode 100644
index 000000000..a075865d9
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/family7-gtp/wr_gtp_phy_family7.vhd
@@ -0,0 +1,521 @@
+-------------------------------------------------------------------------------
+-- Title      : Deterministic Xilinx GTP wrapper - artix-7 top module
+-- Project    : White Rabbit Switch
+-------------------------------------------------------------------------------
+-- File       : wr_gtp_phy_family7.vhd
+-- Author     : Peter Jansweijer, Rick Lohlefink, Tomasz Wlostowski
+-- Company    : Nikhef, CERN BE-CO-HT
+-- Created    : 2016-05-19
+-- Last update: 2016-05-19
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Dual channel wrapper for Xilinx Artix-7 GTP adapted for
+-- deterministic delays at 1.25 Gbps.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2009-2011 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-- 
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author    Description
+-- 2016-05-19  0.1      PeterJ    Initial release based on "wr_gtx_phy_kintex7.vhd"
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.gencores_pkg.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+library work;
+
+use work.disparity_gen_pkg.all;
+
+entity wr_gtp_phy_family7 is
+  generic (
+    -- set to non-zero value to speed up the simulation by reducing some delays
+    g_simulation     : integer := 0
+  );
+  port (
+    -- Dedicated reference 125 MHz clock for the GTP transceiver
+    clk_gtp_i        : in   std_logic;
+
+    -- TX path, synchronous to tx_out_clk_o (62.5 MHz):
+    tx_out_clk_o     : out  std_logic;
+    tx_locked_o      : out  std_logic;
+
+    -- data input (8 bits, not 8b10b-encoded)
+    tx_data_i        : in   std_logic_vector(15 downto 0) := (others => '0');
+
+    -- 1 when tx_data_i contains a control code, 0 when it's a data byte
+    tx_k_i           : in   std_logic_vector(1 downto 0) := (others => '0');
+
+    -- disparity of the currently transmitted 8b10b code (1 = plus, 0 = minus).
+    -- Necessary for the PCS to generate proper frame termination sequences.
+    -- Generated for the 2nd byte (LSB) of tx_data_i.
+    tx_disparity_o   : out  std_logic;
+
+    -- Encoding error indication (1 = error, 0 = no error)
+    tx_enc_err_o     : out  std_logic;
+
+    -- RX path, synchronous to ch0_rx_rbclk_o.
+
+    -- RX recovered clock
+    rx_rbclk_o       : out  std_logic;
+
+    -- 8b10b-decoded data output. The data output must be kept invalid before
+    -- the transceiver is locked on the incoming signal to prevent the EP from
+    -- detecting a false carrier.
+    rx_data_o        : out  std_logic_vector(15 downto 0);
+
+    -- 1 when the byte on rx_data_o is a control code
+    rx_k_o           : out  std_logic_vector(1 downto 0);
+
+    -- encoding error indication
+    rx_enc_err_o     : out  std_logic;
+
+    -- RX bitslide indication, indicating the delay of the RX path of the
+    -- transceiver (in UIs). Must be valid when ch0_rx_data_o is valid.
+    rx_bitslide_o    : out  std_logic_vector(4 downto 0);
+
+    -- reset input, active hi
+    rst_i            : in   std_logic := '0';
+    loopen_i         : in   std_logic_vector(2 downto 0) := (others => '0');
+    tx_prbs_sel_i    : in   std_logic_vector(2 downto 0) := (others => '0');
+
+    pad_rxn_i        : in   std_logic := '0';
+    pad_rxp_i        : in   std_logic := '0';
+
+    pad_txn_o        : out  std_logic;
+    pad_txp_o        : out  std_logic;
+
+    rdy_o            : out  std_logic
+  );
+end entity wr_gtp_phy_family7;
+
+--------------------------------------------------------------------------------
+-- Object        : Architecture work.wr_gtp_phy_family7.structure
+-- Last modified : Mon Nov 23 12:54:18 2015.
+--------------------------------------------------------------------------------
+
+architecture structure of wr_gtp_phy_family7 is
+  constant REQ_DELAY           : integer := 500;                      -- unit = ns
+  constant CLK_PER             : integer := 8;                        -- unit = ns
+  constant INITIAL_WAIT_CYCLES : integer := REQ_DELAY / CLK_PER;      -- Required 500 ns divided by RefClk period
+  constant TOTAL_DELAY         : integer := INITIAL_WAIT_CYCLES + 10; -- Add 10 clock cycles as delay to be sure
+  
+  constant c_rxcdrlock_max     : integer := 3;
+  constant c_reset_cnt_max     : integer := 64;                       -- Reset pulse width 64 * 8 = 512 ns
+  
+  type state_type is (init, count, count_done, wait_reset);
+  signal state : state_type;
+  
+  signal rst_synced         : std_logic;
+  signal rst_int            : std_logic;
+  signal rx_rec_clk         : std_logic;
+  signal rx_rec_clk_bufin   : std_logic;
+  
+  attribute buffer_type     : string;
+  attribute buffer_type of rx_rec_clk_bufin : signal is "bufg";
+  
+  signal tx_out_clk         :    std_logic;
+  signal tx_out_clk_bufin   :    std_logic;
+  
+  --attribute buffer_type of tx_out_clk_bufin : signal is "bufg";
+  
+  signal rx_lost_lock       : std_logic;
+  signal ready_for_reset    : std_logic := '0';
+  signal serdes_ready       : std_logic := '0';
+  signal rx_slide           : std_logic := '0';
+  signal rx_rst_done        : std_logic;
+  signal tx_rst_done        : std_logic;
+  signal rx_comma_det       : std_logic;
+  signal rx_byte_is_aligned : std_logic;
+  signal forced_rx_reset    : std_logic;
+  signal rx_synced          : std_logic;
+  signal rst_done           : std_logic;
+  signal rst_done_n         : std_logic;
+  signal pll_locked_i       : std_logic;
+  signal pll_locked_n_i     : std_logic;
+  signal rx_reset           : std_logic;
+  signal rx_k_int           : std_logic_vector(1 downto 0);
+  signal rx_data_int        : std_logic_vector(15 downto 0);
+  signal rx_disp_err        : std_logic_vector(1 downto 0);
+  signal rx_code_err        : std_logic_vector(1 downto 0);
+  signal cur_disp           : t_8b10b_disparity;
+  signal tx_is_k_swapped    : std_logic_vector(1 downto 0);
+  signal tx_data_swapped    : std_logic_vector(15 downto 0);
+
+  component whiterabbit_gtpe2_channel_wrapper is
+  generic
+  (
+      -- Simulation attributes
+      EXAMPLE_SIMULATION             : integer  := 0;      -- Set to 1 for simulation
+      WRAPPER_SIM_GTRESET_SPEEDUP    : string := "FALSE" -- Set to "true" to speed up sim reset
+  );
+  port
+  (
+      --_________________________________________________________________________
+      --____________________________CHANNEL PORTS________________________________
+      GT0_DRP_BUSY_OUT         : out std_logic; 
+      ---------------------------- Channel - DRP Ports  --------------------------
+      GT0_DRPADDR_IN           : in  std_logic_vector(8 downto 0);
+      GT0_DRPCLK_IN            : in  std_logic;
+      GT0_DRPDI_IN             : in  std_logic_vector(15 downto 0);
+      GT0_DRPDO_OUT            : out std_logic_vector(15 downto 0);
+      GT0_DRPEN_IN             : in  std_logic;
+      GT0_DRPRDY_OUT           : out std_logic;
+      GT0_DRPWE_IN             : in  std_logic;
+      ------------------------------- Loopback Ports -----------------------------
+      GT0_LOOPBACK_IN          : in  std_logic_vector(2 downto 0);
+      --------------------- RX Initialization and Reset Ports --------------------
+      GT0_RXUSERRDY_IN         : in  std_logic;
+      -------------------------- RX Margin Analysis Ports ------------------------
+      GT0_EYESCANDATAERROR_OUT : out std_logic;
+      ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+      GT0_RXDATA_OUT           : out  std_logic_vector(15 downto 0);
+      GT0_RXUSRCLK_IN          : in  std_logic;
+      GT0_RXUSRCLK2_IN         : in  std_logic;
+      ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+      GT0_RXCHARISCOMMA_OUT    : out  std_logic_vector(1 downto 0);
+      GT0_RXCHARISK_OUT        : out  std_logic_vector(1 downto 0);
+      GT0_RXDISPERR_OUT        : out  std_logic_vector(1 downto 0);
+      GT0_RXNOTINTABLE_OUT     : out  std_logic_vector(1 downto 0);
+      ------------------------ Receive Ports - RX AFE Ports ----------------------
+      GT0_GTPRXN_IN            : in  std_logic;
+      GT0_GTPRXP_IN            : in  std_logic;
+      -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
+      GT0_RXBYTEISALIGNED_OUT  : out  std_logic;
+      GT0_RXCOMMADET_OUT       : out  std_logic;
+      GT0_RXSLIDE_IN           : in  std_logic;
+      --------------------- Receive Ports - RX Equilizer Ports -------------------
+      GT0_RXLPMHFHOLD_IN       : in  std_logic;
+      GT0_RXLPMLFHOLD_IN       : in  std_logic;
+      --------------- Receive Ports - RX Fabric Output Control Ports -------------
+      GT0_RXOUTCLK_OUT         : out std_logic;
+      ------------- Receive Ports - RX Initialization and Reset Ports ------------
+      GT0_GTRXRESET_IN         : in  std_logic;
+      -------------- Receive Ports -RX Initialization and Reset Ports ------------
+      GT0_RXRESETDONE_OUT      : out  std_logic;
+      --------------------- TX Initialization and Reset Ports --------------------
+      GT0_GTTXRESET_IN         : in  std_logic;
+      GT0_TXUSERRDY_IN         : in  std_logic;
+      ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+      GT0_TXDATA_IN            : in  std_logic_vector(15 downto 0);
+      GT0_TXUSRCLK_IN          : in  std_logic;
+      GT0_TXUSRCLK2_IN         : in  std_logic;
+      ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
+      GT0_TXCHARISK_IN         : in  std_logic_vector(1 downto 0);
+      --------------- Transmit Ports - TX Configurable Driver Ports --------------
+      GT0_GTPTXN_OUT           : out std_logic;
+      GT0_GTPTXP_OUT           : out std_logic;
+      ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+      GT0_TXOUTCLK_OUT         : out std_logic;
+      GT0_TXOUTCLKFABRIC_OUT   : out std_logic;
+      GT0_TXOUTCLKPCS_OUT      : out std_logic;
+      ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+      GT0_TXRESETDONE_OUT      : out std_logic;
+      ------------------ Transmit Ports - pattern Generator Ports ----------------
+      GT0_TXPRBSSEL_IN         : in  std_logic_vector(2 downto 0);
+  
+  
+      --____________________________COMMON PORTS________________________________
+      ----------------- Common Block - GTPE2_COMMON Clocking Ports ---------------
+      GT0_GTREFCLK0_IN         : in  std_logic;
+      -------------------------- Common Block - PLL Ports ------------------------
+      GT0_PLL1LOCK_OUT         : out std_logic;
+      GT0_PLL1LOCKDETCLK_IN    : in  std_logic;
+      GT0_PLL1REFCLKLOST_OUT   : out std_logic;
+      GT0_PLL1RESET_IN         : in  std_logic
+  
+  
+  );
+  end component whiterabbit_gtpe2_channel_wrapper;
+  
+  component gtp_bitslide is
+  generic (
+    g_simulation             :    integer;
+    g_target                 :    string := "artix7"
+  );
+  port (
+    gtp_rst_i                : in  std_logic;
+    gtp_rx_clk_i             : in  std_logic;
+    gtp_rx_comma_det_i       : in  std_logic;
+    gtp_rx_byte_is_aligned_i : in  std_logic;
+    serdes_ready_i           : in  std_logic;
+    gtp_rx_slide_o           : out std_logic;
+    gtp_rx_cdr_rst_o         : out std_logic;
+    bitslide_o               : out std_logic_vector(4 downto 0);
+    synced_o                 : out std_logic
+  );
+  end component;
+
+  component BUFG
+    port (
+      I : in  std_ulogic;
+      O : out  std_ulogic);
+  end component BUFG;
+
+  function f_to_bool(x : integer) return string is
+    begin
+      if(x /= 0) then
+        return "TRUE";
+      else
+        return "FALSE";
+      end if;
+    end f_to_bool;
+
+begin
+
+  U_EdgeDet_rst_i : gc_sync_ffs port map (
+    clk_i    => clk_gtp_i,
+    rst_n_i    => '1',
+    data_i    => rst_i,
+    ppulse_o  => rst_synced);
+  
+  p_reset_pulse : process(clk_gtp_i, rst_synced)
+    variable reset_cnt      : integer range 0 to c_reset_cnt_max;
+  begin
+    if(rst_synced = '1') then
+      reset_cnt := 0;
+      rst_int <= '1';
+    elsif rising_edge(clk_gtp_i) then
+      if reset_cnt /= c_reset_cnt_max then
+        reset_cnt := reset_cnt + 1;
+        rst_int <= '1';
+      else
+        rst_int <= '0';
+      end if;
+    end if;
+  end process;  
+
+  -- ug482 "GTP Transceiver TX/RX Reset in Response to Completion of Configuration"
+  --   1. Wait a minimum of 500 ns after configuration is complete
+  process(clk_gtp_i, rst_int) is
+    variable reset_counter : integer range 0 to TOTAL_DELAY := 0;
+  begin
+    if rst_int = '1' then
+      state <= init;
+    elsif rising_edge(clk_gtp_i) then
+      case state is
+        when init =>
+          reset_counter := 0;
+          state <= count;
+        when count =>
+          if reset_counter = TOTAL_DELAY then
+            reset_counter := 0;
+            state <= count_done;
+          else
+            reset_counter := reset_counter + 1;
+            state <= count;
+          end if;
+        when count_done =>
+          state <= wait_reset;
+        when wait_reset =>
+          state <= wait_reset;
+      end case;
+    end if;
+  end process;
+  
+  ready_for_reset <= '1' when state = count_done else '0';
+  
+  -- 7-Series GTP RXCDRLOCK is reserved (ug482 Table 4.11) and can not be used for detection of proper RX lock.
+  -- Instead use rx_code_err (i.e. RXNOTINTABLE) to check integrity of the received characters.
+  process(rx_rec_clk, rst_int) is
+  begin
+    if rst_int = '1' then
+      rx_lost_lock <= '1';
+    elsif rising_edge(rx_rec_clk) then
+      if rx_synced = '1' then
+        if rx_code_err > "00" then
+          rx_lost_lock <= '1';
+        else
+          rx_lost_lock <= '0';
+        end if;
+      else
+        rx_lost_lock <= '0';
+      end if;
+    end if;
+  end process;
+
+  tx_enc_err_o <= '0';
+  
+  U_BUF_TxOutClk: BUFG
+    port map(
+      I => tx_out_clk_bufin,
+      O => tx_out_clk);
+
+  tx_out_clk_o <= tx_out_clk;
+  tx_locked_o <= pll_locked_i;
+    
+  U_BUF_RxRecClk: BUFG
+    port map(
+      I => rx_rec_clk_bufin,
+      O => rx_rec_clk);
+      
+  rx_rbclk_o <= rx_rec_clk;
+
+  tx_is_k_swapped <= tx_k_i(0) & tx_k_i(1);
+  tx_data_swapped <= tx_data_i(7 downto 0) & tx_data_i(15 downto 8);
+  
+  U_GTP_INST : whiterabbit_gtpe2_channel_wrapper
+  generic map
+  (
+    -- Simulation attributes
+    EXAMPLE_SIMULATION           => g_simulation,
+    WRAPPER_SIM_GTRESET_SPEEDUP  => f_to_bool(g_simulation)
+  )
+  port map
+  (
+    --_________________________________________________________________________
+    --_________________________________________________________________________
+    --____________________________CHANNEL PORTS________________________________
+    GT0_DRP_BUSY_OUT         =>  open,
+    ---------------------------- Channel - DRP Ports  --------------------------
+    GT0_DRPADDR_IN           =>  (others => '0'),
+    GT0_DRPCLK_IN            =>  clk_gtp_i,
+    GT0_DRPDI_IN             =>  (others => '0'),
+    GT0_DRPDO_OUT            =>  open,
+    GT0_DRPEN_IN             =>  '0',
+    GT0_DRPRDY_OUT           =>  open,
+    GT0_DRPWE_IN             =>  '0',
+    ------------------------------- Loopback Ports -----------------------------
+    GT0_LOOPBACK_IN          =>  loopen_i,
+    --------------------- RX Initialization and Reset Ports --------------------
+    GT0_RXUSERRDY_IN         =>  pll_locked_i,
+    -------------------------- RX Margin Analysis Ports ------------------------
+    GT0_EYESCANDATAERROR_OUT =>  open,
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    GT0_RXDATA_OUT           =>  rx_data_int,
+    GT0_RXUSRCLK_IN          =>  rx_rec_clk,
+    GT0_RXUSRCLK2_IN         =>  rx_rec_clk,
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    GT0_RXCHARISCOMMA_OUT    =>  open,
+    GT0_RXCHARISK_OUT        =>  rx_k_int,
+    GT0_RXDISPERR_OUT        =>  rx_disp_err,
+    GT0_RXNOTINTABLE_OUT     =>  rx_code_err,
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    GT0_GTPRXN_IN            =>  pad_rxn_i,
+    GT0_GTPRXP_IN            =>  pad_rxp_i,
+    -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
+    GT0_RXBYTEISALIGNED_OUT  =>  rx_byte_is_aligned,
+    GT0_RXCOMMADET_OUT       =>  rx_comma_det,
+    GT0_RXSLIDE_IN           =>  rx_slide,
+    --------------------- Receive Ports - RX Equilizer Ports -------------------
+    GT0_RXLPMHFHOLD_IN       =>  '0',
+    GT0_RXLPMLFHOLD_IN       =>  '0',
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    GT0_RXOUTCLK_OUT         =>  rx_rec_clk_bufin,
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    GT0_GTRXRESET_IN         =>  rx_reset,
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    GT0_RXRESETDONE_OUT      =>  rx_rst_done,
+    --------------------- TX Initialization and Reset Ports --------------------
+    GT0_GTTXRESET_IN         =>  pll_locked_n_i,
+    GT0_TXUSERRDY_IN         =>  pll_locked_i,
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    GT0_TXDATA_IN            =>  tx_data_swapped,
+    GT0_TXUSRCLK_IN          =>  tx_out_clk,
+    GT0_TXUSRCLK2_IN         =>  tx_out_clk,
+    ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
+    GT0_TXCHARISK_IN         =>  tx_is_k_swapped,
+    --------------- Transmit Ports - TX Configurable Driver Ports --------------
+    GT0_GTPTXN_OUT           =>  pad_txn_o,
+    GT0_GTPTXP_OUT           =>  pad_txp_o,
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    GT0_TXOUTCLK_OUT         =>  tx_out_clk_bufin,
+    GT0_TXOUTCLKFABRIC_OUT   =>  open,
+    GT0_TXOUTCLKPCS_OUT      =>  open,
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    GT0_TXRESETDONE_OUT      =>  tx_rst_done,
+        ------------------ Transmit Ports - pattern Generator Ports ----------------
+    GT0_TXPRBSSEL_IN         =>  tx_prbs_sel_i,
+
+    --____________________________COMMON PORTS________________________________
+    ----------------- Common Block - GTPE2_COMMON Clocking Ports ---------------
+    GT0_GTREFCLK0_IN         =>  clk_gtp_i,
+    -------------------------- Common Block - PLL Ports ------------------------
+    GT0_PLL1LOCK_OUT         =>  pll_locked_i,
+    GT0_PLL1LOCKDETCLK_IN    =>  '0',
+    GT0_PLL1REFCLKLOST_OUT   =>  open,
+    GT0_PLL1RESET_IN         =>  ready_for_reset
+  );
+  
+  U_Bitslide : gtp_bitslide
+  generic map (
+    g_simulation             =>  g_simulation,
+    g_target                 =>  ("artix7")
+  )
+  port map (
+    gtp_rst_i                =>  rst_done_n,
+    gtp_rx_clk_i             =>  rx_rec_clk,
+    gtp_rx_comma_det_i       =>  rx_comma_det,
+    gtp_rx_byte_is_aligned_i =>  rx_byte_is_aligned,
+    serdes_ready_i           =>  serdes_ready,
+    gtp_rx_slide_o           =>  rx_slide,
+    gtp_rx_cdr_rst_o         =>  forced_rx_reset,
+    bitslide_o               =>  rx_bitslide_o,
+    synced_o                 =>  rx_synced
+  );
+
+  pll_locked_n_i <= not pll_locked_i;
+  serdes_ready <= not rx_lost_lock and pll_locked_i and tx_rst_done and rx_rst_done;
+  rst_done <= tx_rst_done and rx_rst_done;
+  rst_done_n <= not rst_done;
+  rx_reset <= pll_locked_n_i or forced_rx_reset;
+  rdy_o <= serdes_ready;
+
+  p_gen_rx_outputs : process(rx_rec_clk, rst_done_n)
+  begin
+    if(rst_done_n = '1') then
+      rx_data_o    <= (others => '0');
+      rx_k_o       <= (others => '0');
+      rx_enc_err_o <= '0';
+    elsif rising_edge(rx_rec_clk) then
+      if(serdes_ready = '1' and rx_synced = '1') then
+      rx_data_o    <= rx_data_int(7 downto 0) & rx_data_int(15 downto 8);
+      rx_k_o       <= rx_k_int(0) & rx_k_int(1);
+      rx_enc_err_o <= rx_disp_err(0) or rx_disp_err(1) or rx_code_err(0) or rx_code_err(1);
+      else
+      rx_data_o    <= (others => '1');
+      rx_k_o       <= (others => '1');
+      rx_enc_err_o <= '1';
+      end if;
+    end if;
+  end process;
+
+  p_gen_tx_disparity : process(tx_out_clk, rst_done_n)
+  begin
+    if rising_edge(tx_out_clk) then
+      if rst_done_n = '1' then
+      cur_disp <= RD_MINUS;
+      else
+      cur_disp <= f_next_8b10b_disparity16(cur_disp, tx_k_i, tx_data_i);
+      end if;
+    end if;
+  end process;
+
+  tx_disparity_o <= to_std_logic(cur_disp);
+end architecture structure ; -- of wr_gtp_phy_family7
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/family7-gtx/whiterabbit_gtxe2_channel_wrapper_gt.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/family7-gtx/whiterabbit_gtxe2_channel_wrapper_gt.vhd
new file mode 100644
index 000000000..dcf8eb32d
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/family7-gtx/whiterabbit_gtxe2_channel_wrapper_gt.vhd
@@ -0,0 +1,803 @@
+-------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version : 2.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard
+--  /   /         Filename : whiterabbit_gtxe2_channel_wrapper_gt.vhd
+-- /___/   /\     
+-- \   \  /  \ 
+--  \___\/\___\
+--
+--
+-- Module whiterabbit_gtxe2_channel_wrapper_GT (a GT Wrapper)
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+--***************************** Entity Declaration ****************************
+
+entity whiterabbit_gtxe2_channel_wrapper_GT is
+generic
+(
+    -- Simulation attributes
+    GT_SIM_GTRESET_SPEEDUP    : string     :=  "FALSE";        -- Set to "true" to speed up sim reset
+    RX_DFE_KL_CFG2_IN         : bit_vector :=   X"3010D90C";
+    PMA_RSV_IN                : bit_vector :=  x"00018480";
+    PCS_RSVD_ATTR_IN          : bit_vector :=   X"000000000000"
+);
+port 
+(
+    --------------------------------- CPLL Ports -------------------------------
+    CPLLFBCLKLOST_OUT                       : out  std_logic;
+    CPLLLOCK_OUT                            : out  std_logic;
+    CPLLLOCKDETCLK_IN                       : in   std_logic;
+    CPLLREFCLKLOST_OUT                      : out  std_logic;
+    CPLLRESET_IN                            : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    GTREFCLK0_IN                            : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    DRPADDR_IN                              : in   std_logic_vector(8 downto 0);
+    DRPCLK_IN                               : in   std_logic;
+    DRPDI_IN                                : in   std_logic_vector(15 downto 0);
+    DRPDO_OUT                               : out  std_logic_vector(15 downto 0);
+    DRPEN_IN                                : in   std_logic;
+    DRPRDY_OUT                              : out  std_logic;
+    DRPWE_IN                                : in   std_logic;
+    ------------------------------- Clocking Ports -----------------------------
+    QPLLCLK_IN                              : in   std_logic;
+    QPLLREFCLK_IN                           : in   std_logic;
+    ------------------------------- Loopback Ports -----------------------------
+    LOOPBACK_IN                             : in   std_logic_vector(2 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    RXUSERRDY_IN                            : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    EYESCANDATAERROR_OUT                    : out  std_logic;
+    ------------------------- Receive Ports - CDR Ports ------------------------
+    RXCDRLOCK_OUT                           : out  std_logic;
+    RXCDRRESET_IN                           : in   std_logic;
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    RXUSRCLK_IN                             : in   std_logic;
+    RXUSRCLK2_IN                            : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    RXDATA_OUT                              : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    RXDISPERR_OUT                           : out  std_logic_vector(1 downto 0);
+    RXNOTINTABLE_OUT                        : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    GTXRXP_IN                               : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    GTXRXN_IN                               : in   std_logic;
+    -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
+    RXBYTEISALIGNED_OUT                     : out  std_logic;
+    RXCOMMADET_OUT                          : out  std_logic;
+    --------------------- Receive Ports - RX Equilizer Ports -------------------
+    RXLPMHFHOLD_IN                          : in   std_logic;
+    RXLPMLFHOLD_IN                          : in   std_logic;
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    RXOUTCLK_OUT                            : out  std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    GTRXRESET_IN                            : in   std_logic;
+    RXPMARESET_IN                           : in   std_logic;
+    ---------------------- Receive Ports - RX gearbox ports --------------------
+    RXSLIDE_IN                              : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    RXCHARISK_OUT                           : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    RXRESETDONE_OUT                         : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    GTTXRESET_IN                            : in   std_logic;
+    TXUSERRDY_IN                            : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    TXUSRCLK_IN                             : in   std_logic;
+    TXUSRCLK2_IN                            : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    TXDATA_IN                               : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    GTXTXN_OUT                              : out  std_logic;
+    GTXTXP_OUT                              : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    TXOUTCLK_OUT                            : out  std_logic;
+    TXOUTCLKFABRIC_OUT                      : out  std_logic;
+    TXOUTCLKPCS_OUT                         : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    TXCHARISK_IN                            : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    TXRESETDONE_OUT                         : out  std_logic;
+    ------------------ Transmit Ports - pattern Generator Ports ----------------
+    TXPRBSSEL_IN                            : in   std_logic_vector(2 downto 0)
+
+);
+
+
+end whiterabbit_gtxe2_channel_wrapper_GT;
+
+architecture RTL of whiterabbit_gtxe2_channel_wrapper_GT is
+    
+--**************************** Signal Declarations ****************************
+
+    -- ground and tied_to_vcc_i signals
+    signal  tied_to_ground_i                :   std_logic;
+    signal  tied_to_ground_vec_i            :   std_logic_vector(63 downto 0);
+    signal  tied_to_vcc_i                   :   std_logic;
+
+
+
+    -- RX Datapath signals
+    signal rxdata_i                         :   std_logic_vector(63 downto 0);      
+    signal rxchariscomma_float_i            :   std_logic_vector(5 downto 0);
+    signal rxcharisk_float_i                :   std_logic_vector(5 downto 0);
+    signal rxdisperr_float_i                :   std_logic_vector(5 downto 0);
+    signal rxnotintable_float_i             :   std_logic_vector(5 downto 0);
+    signal rxrundisp_float_i                :   std_logic_vector(5 downto 0);
+    
+
+
+    -- TX Datapath signals
+    signal txdata_i                         :   std_logic_vector(63 downto 0);
+    signal txkerr_float_i                   :   std_logic_vector(5 downto 0);
+    signal txrundisp_float_i                :   std_logic_vector(5 downto 0);
+
+
+--******************************** Main Body of Code***************************
+                       
+begin                      
+
+    ---------------------------  Static signal Assignments ---------------------   
+
+    tied_to_ground_i                    <= '0';
+    tied_to_ground_vec_i(63 downto 0)   <= (others => '0');
+    tied_to_vcc_i                       <= '1';
+
+    -------------------  GT Datapath byte mapping  -----------------
+
+    RXDATA_OUT    <=   rxdata_i(15 downto 0);
+
+    txdata_i    <=   (tied_to_ground_vec_i(47 downto 0) & TXDATA_IN);
+
+
+
+    ----------------------------- GTXE2 Instance  --------------------------   
+
+    gtxe2_i :GTXE2_CHANNEL
+    generic map
+    (
+
+        --_______________________ Simulation-Only Attributes ___________________
+
+        SIM_RECEIVER_DETECT_PASS   =>      ("TRUE"),
+        SIM_RESET_SPEEDUP          =>      (GT_SIM_GTRESET_SPEEDUP),
+        SIM_TX_EIDLE_DRIVE_LEVEL   =>      ("X"),
+        SIM_CPLLREFCLK_SEL         =>      ("001"),
+        SIM_VERSION                =>      ("4.0"), 
+        
+
+       ------------------RX Byte and Word Alignment Attributes---------------
+        ALIGN_COMMA_DOUBLE                      =>     ("FALSE"),
+        ALIGN_COMMA_ENABLE                      =>     ("0001111111"),
+        ALIGN_COMMA_WORD                        =>     (2),
+        ALIGN_MCOMMA_DET                        =>     ("TRUE"),
+        ALIGN_MCOMMA_VALUE                      =>     ("1010000011"),
+        ALIGN_PCOMMA_DET                        =>     ("TRUE"),
+        ALIGN_PCOMMA_VALUE                      =>     ("0101111100"),
+        SHOW_REALIGN_COMMA                      =>     ("FALSE"),
+        RXSLIDE_AUTO_WAIT                       =>     (7),
+        RXSLIDE_MODE                            =>     ("PCS"),
+        RX_SIG_VALID_DLY                        =>     (10),
+
+       ------------------RX 8B/10B Decoder Attributes---------------
+        RX_DISPERR_SEQ_MATCH                    =>     ("TRUE"),
+        DEC_MCOMMA_DETECT                       =>     ("TRUE"),
+        DEC_PCOMMA_DETECT                       =>     ("TRUE"),
+        DEC_VALID_COMMA_ONLY                    =>     ("TRUE"),
+
+       ------------------------RX Clock Correction Attributes----------------------
+        CBCC_DATA_SOURCE_SEL                    =>     ("DECODED"),
+        CLK_COR_SEQ_2_USE                       =>     ("FALSE"),
+        CLK_COR_KEEP_IDLE                       =>     ("FALSE"),
+        CLK_COR_MAX_LAT                         =>     (10),
+        CLK_COR_MIN_LAT                         =>     (8),
+        CLK_COR_PRECEDENCE                      =>     ("TRUE"),
+        CLK_COR_REPEAT_WAIT                     =>     (0),
+        CLK_COR_SEQ_LEN                         =>     (1),
+        CLK_COR_SEQ_1_ENABLE                    =>     ("1111"),
+        CLK_COR_SEQ_1_1                         =>     ("0000000000"),
+        CLK_COR_SEQ_1_2                         =>     ("0000000000"),
+        CLK_COR_SEQ_1_3                         =>     ("0000000000"),
+        CLK_COR_SEQ_1_4                         =>     ("0000000000"),
+        CLK_CORRECT_USE                         =>     ("FALSE"),
+        CLK_COR_SEQ_2_ENABLE                    =>     ("1111"),
+        CLK_COR_SEQ_2_1                         =>     ("0000000000"),
+        CLK_COR_SEQ_2_2                         =>     ("0000000000"),
+        CLK_COR_SEQ_2_3                         =>     ("0000000000"),
+        CLK_COR_SEQ_2_4                         =>     ("0000000000"),
+
+       ------------------------RX Channel Bonding Attributes----------------------
+        CHAN_BOND_KEEP_ALIGN                    =>     ("FALSE"),
+        CHAN_BOND_MAX_SKEW                      =>     (1),
+        CHAN_BOND_SEQ_LEN                       =>     (1),
+        CHAN_BOND_SEQ_1_1                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_1_2                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_1_3                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_1_4                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_1_ENABLE                  =>     ("1111"),
+        CHAN_BOND_SEQ_2_1                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_2_2                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_2_3                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_2_4                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_2_ENABLE                  =>     ("1111"),
+        CHAN_BOND_SEQ_2_USE                     =>     ("FALSE"),
+        FTS_DESKEW_SEQ_ENABLE                   =>     ("1111"),
+        FTS_LANE_DESKEW_CFG                     =>     ("1111"),
+        FTS_LANE_DESKEW_EN                      =>     ("FALSE"),
+
+       ---------------------------RX Margin Analysis Attributes----------------------------
+        ES_CONTROL                              =>     ("000000"),
+        ES_ERRDET_EN                            =>     ("FALSE"),
+        ES_EYE_SCAN_EN                          =>     ("TRUE"),
+        ES_HORZ_OFFSET                          =>     (x"000"),
+        ES_PMA_CFG                              =>     ("0000000000"),
+        ES_PRESCALE                             =>     ("00000"),
+        ES_QUALIFIER                            =>     (x"00000000000000000000"),
+        ES_QUAL_MASK                            =>     (x"00000000000000000000"),
+        ES_SDATA_MASK                           =>     (x"00000000000000000000"),
+        ES_VERT_OFFSET                          =>     ("000000000"),
+
+       -------------------------FPGA RX Interface Attributes-------------------------
+        RX_DATA_WIDTH                           =>     (20),
+
+       ---------------------------PMA Attributes----------------------------
+        OUTREFCLK_SEL_INV                       =>     ("11"),
+        PMA_RSV                                 =>     (PMA_RSV_IN),
+        PMA_RSV2                                =>     (x"2040"),
+        PMA_RSV3                                =>     ("00"),
+        PMA_RSV4                                =>     (x"00000000"),
+        RX_BIAS_CFG                             =>     ("000000000100"),
+        DMONITOR_CFG                            =>     (x"000A00"),
+        RX_CM_SEL                               =>     ("00"),
+        RX_CM_TRIM                              =>     ("000"),
+        RX_DEBUG_CFG                            =>     ("000000000000"),
+        RX_OS_CFG                               =>     ("0000010000000"),
+        TERM_RCAL_CFG                           =>     ("10000"),
+        TERM_RCAL_OVRD                          =>     ('0'),
+        TST_RSV                                 =>     (x"00000000"),
+        RX_CLK25_DIV                            =>     (5),
+        TX_CLK25_DIV                            =>     (5),
+        UCODEER_CLR                             =>     ('0'),
+
+       ---------------------------PCI Express Attributes----------------------------
+        PCS_PCIE_EN                             =>     ("FALSE"),
+
+       ---------------------------PCS Attributes----------------------------
+        PCS_RSVD_ATTR                           =>     (PCS_RSVD_ATTR_IN),
+
+       -------------RX Buffer Attributes------------
+        RXBUF_ADDR_MODE                         =>     ("FAST"),
+        RXBUF_EIDLE_HI_CNT                      =>     ("1000"),
+        RXBUF_EIDLE_LO_CNT                      =>     ("0000"),
+        RXBUF_EN                                =>     ("TRUE"),
+        RX_BUFFER_CFG                           =>     ("000000"),
+        RXBUF_RESET_ON_CB_CHANGE                =>     ("TRUE"),
+        RXBUF_RESET_ON_COMMAALIGN               =>     ("FALSE"),
+        RXBUF_RESET_ON_EIDLE                    =>     ("FALSE"),
+        RXBUF_RESET_ON_RATE_CHANGE              =>     ("TRUE"),
+        RXBUFRESET_TIME                         =>     ("00001"),
+        RXBUF_THRESH_OVFLW                      =>     (61),
+        RXBUF_THRESH_OVRD                       =>     ("FALSE"),
+        RXBUF_THRESH_UNDFLW                     =>     (4),
+        RXDLY_CFG                               =>     (x"001F"),
+        RXDLY_LCFG                              =>     (x"030"),
+        RXDLY_TAP_CFG                           =>     (x"0000"),
+        RXPH_CFG                                =>     (x"000000"),
+        RXPHDLY_CFG                             =>     (x"084020"),
+        RXPH_MONITOR_SEL                        =>     ("00000"),
+        RX_XCLK_SEL                             =>     ("RXREC"),
+        RX_DDI_SEL                              =>     ("000000"),
+        RX_DEFER_RESET_BUF_EN                   =>     ("TRUE"),
+
+       -----------------------CDR Attributes-------------------------
+
+       --For GTX only: Display Port, HBR/RBR- set RXCDR_CFG=72'h0380008bff40200002
+
+       --For GTX only: Display Port, HBR2 -   set RXCDR_CFG=72'h03000023ff10200020
+        RXCDR_CFG                               =>     (x"03000023ff10100020"),
+        RXCDR_FR_RESET_ON_EIDLE                 =>     ('0'),
+        RXCDR_HOLD_DURING_EIDLE                 =>     ('0'),
+        RXCDR_PH_RESET_ON_EIDLE                 =>     ('0'),
+        RXCDR_LOCK_CFG                          =>     ("010101"),
+
+       -------------------RX Initialization and Reset Attributes-------------------
+        RXCDRFREQRESET_TIME                     =>     ("00001"),
+        RXCDRPHRESET_TIME                       =>     ("00001"),
+        RXISCANRESET_TIME                       =>     ("00001"),
+        RXPCSRESET_TIME                         =>     ("00001"),
+        RXPMARESET_TIME                         =>     ("00011"),
+
+       -------------------RX OOB Signaling Attributes-------------------
+        RXOOB_CFG                               =>     ("0000110"),
+
+       -------------------------RX Gearbox Attributes---------------------------
+        RXGEARBOX_EN                            =>     ("FALSE"),
+        GEARBOX_MODE                            =>     ("000"),
+
+       -------------------------PRBS Detection Attribute-----------------------
+        RXPRBS_ERR_LOOPBACK                     =>     ('0'),
+
+       -------------Power-Down Attributes----------
+        PD_TRANS_TIME_FROM_P2                   =>     (x"03c"),
+        PD_TRANS_TIME_NONE_P2                   =>     (x"3c"),
+        PD_TRANS_TIME_TO_P2                     =>     (x"64"),
+
+       -------------RX OOB Signaling Attributes----------
+        SAS_MAX_COM                             =>     (64),
+        SAS_MIN_COM                             =>     (36),
+        SATA_BURST_SEQ_LEN                      =>     ("1111"),
+        SATA_BURST_VAL                          =>     ("100"),
+        SATA_EIDLE_VAL                          =>     ("100"),
+        SATA_MAX_BURST                          =>     (8),
+        SATA_MAX_INIT                           =>     (21),
+        SATA_MAX_WAKE                           =>     (7),
+        SATA_MIN_BURST                          =>     (4),
+        SATA_MIN_INIT                           =>     (12),
+        SATA_MIN_WAKE                           =>     (4),
+
+       -------------RX Fabric Clock Output Control Attributes----------
+        TRANS_TIME_RATE                         =>     (x"0E"),
+
+       --------------TX Buffer Attributes----------------
+        TXBUF_EN                                =>     ("TRUE"),
+        TXBUF_RESET_ON_RATE_CHANGE              =>     ("TRUE"),
+        TXDLY_CFG                               =>     (x"001F"),
+        TXDLY_LCFG                              =>     (x"030"),
+        TXDLY_TAP_CFG                           =>     (x"0000"),
+        TXPH_CFG                                =>     (x"0780"),
+        TXPHDLY_CFG                             =>     (x"084020"),
+        TXPH_MONITOR_SEL                        =>     ("00000"),
+        TX_XCLK_SEL                             =>     ("TXOUT"),
+
+       -------------------------FPGA TX Interface Attributes-------------------------
+        TX_DATA_WIDTH                           =>     (20),
+
+       -------------------------TX Configurable Driver Attributes-------------------------
+        TX_DEEMPH0                              =>     ("00000"),
+        TX_DEEMPH1                              =>     ("00000"),
+        TX_EIDLE_ASSERT_DELAY                   =>     ("110"),
+        TX_EIDLE_DEASSERT_DELAY                 =>     ("100"),
+        TX_LOOPBACK_DRIVE_HIZ                   =>     ("FALSE"),
+        TX_MAINCURSOR_SEL                       =>     ('0'),
+        TX_DRIVE_MODE                           =>     ("DIRECT"),
+        TX_MARGIN_FULL_0                        =>     ("1001110"),
+        TX_MARGIN_FULL_1                        =>     ("1001001"),
+        TX_MARGIN_FULL_2                        =>     ("1000101"),
+        TX_MARGIN_FULL_3                        =>     ("1000010"),
+        TX_MARGIN_FULL_4                        =>     ("1000000"),
+        TX_MARGIN_LOW_0                         =>     ("1000110"),
+        TX_MARGIN_LOW_1                         =>     ("1000100"),
+        TX_MARGIN_LOW_2                         =>     ("1000010"),
+        TX_MARGIN_LOW_3                         =>     ("1000000"),
+        TX_MARGIN_LOW_4                         =>     ("1000000"),
+
+       -------------------------TX Gearbox Attributes--------------------------
+        TXGEARBOX_EN                            =>     ("FALSE"),
+
+       -------------------------TX Initialization and Reset Attributes--------------------------
+        TXPCSRESET_TIME                         =>     ("00001"),
+        TXPMARESET_TIME                         =>     ("00001"),
+
+       -------------------------TX Receiver Detection Attributes--------------------------
+        TX_RXDETECT_CFG                         =>     (x"1832"),
+        TX_RXDETECT_REF                         =>     ("100"),
+
+       ----------------------------CPLL Attributes----------------------------
+        CPLL_CFG                                =>     (x"BC07DC"),
+        CPLL_FBDIV                              =>     (4),
+        CPLL_FBDIV_45                           =>     (5),
+        CPLL_INIT_CFG                           =>     (x"00001E"),
+        CPLL_LOCK_CFG                           =>     (x"01E8"),
+        CPLL_REFCLK_DIV                         =>     (1),
+        RXOUT_DIV                               =>     (4),
+        TXOUT_DIV                               =>     (4),
+        SATA_CPLL_CFG                           =>     ("VCO_3000MHZ"),
+
+       --------------RX Initialization and Reset Attributes-------------
+        RXDFELPMRESET_TIME                      =>     ("0001111"),
+
+       --------------RX Equalizer Attributes-------------
+        RXLPM_HF_CFG                            =>     ("00000011110000"),
+        RXLPM_LF_CFG                            =>     ("00000011110000"),
+        RX_DFE_GAIN_CFG                         =>     (x"020FEA"),
+        RX_DFE_H2_CFG                           =>     ("000000000000"),
+        RX_DFE_H3_CFG                           =>     ("000001000000"),
+        RX_DFE_H4_CFG                           =>     ("00011110000"),
+        RX_DFE_H5_CFG                           =>     ("00011100000"),
+        RX_DFE_KL_CFG                           =>     ("0000011111110"),
+        RX_DFE_LPM_CFG                          =>     (x"0904"),
+        RX_DFE_LPM_HOLD_DURING_EIDLE            =>     ('0'),
+        RX_DFE_UT_CFG                           =>     ("10001111000000000"),
+        RX_DFE_VP_CFG                           =>     ("00011111100000011"),
+
+       -------------------------Power-Down Attributes-------------------------
+        RX_CLKMUX_PD                            =>     ('1'),
+        TX_CLKMUX_PD                            =>     ('1'),
+
+       -------------------------FPGA RX Interface Attribute-------------------------
+        RX_INT_DATAWIDTH                        =>     (0),
+
+       -------------------------FPGA TX Interface Attribute-------------------------
+        TX_INT_DATAWIDTH                        =>     (0),
+
+       ------------------TX Configurable Driver Attributes---------------
+        TX_QPI_STATUS_EN                        =>     ('0'),
+
+       -------------------------RX Equalizer Attributes--------------------------
+        RX_DFE_KL_CFG2                          =>     (RX_DFE_KL_CFG2_IN),
+        RX_DFE_XYD_CFG                          =>     ("0000000000000"),
+
+       -------------------------TX Configurable Driver Attributes--------------------------
+        TX_PREDRIVER_MODE                       =>     ('0')
+
+
+    )
+    port map
+    (
+                      --------------------------------- CPLL Ports -------------------------------
+        CPLLFBCLKLOST                   =>      CPLLFBCLKLOST_OUT,
+        CPLLLOCK                        =>      CPLLLOCK_OUT,
+        CPLLLOCKDETCLK                  =>      CPLLLOCKDETCLK_IN,
+        CPLLLOCKEN                      =>      tied_to_vcc_i,
+        CPLLPD                          =>      tied_to_ground_i,
+        CPLLREFCLKLOST                  =>      CPLLREFCLKLOST_OUT,
+        CPLLREFCLKSEL                   =>      "001",
+        CPLLRESET                       =>      CPLLRESET_IN,
+        GTRSVD                          =>      "0000000000000000",
+        PCSRSVDIN                       =>      "0000000000000000",
+        PCSRSVDIN2                      =>      "00000",
+        PMARSVDIN                       =>      "00000",
+        PMARSVDIN2                      =>      "00000",
+        TSTIN                           =>      "11111111111111111111",
+        TSTOUT                          =>      open,
+        ---------------------------------- Channel ---------------------------------
+        CLKRSVD                         =>      "0000",
+        -------------------------- Channel - Clocking Ports ------------------------
+        GTGREFCLK                       =>      tied_to_ground_i,
+        GTNORTHREFCLK0                  =>      tied_to_ground_i,
+        GTNORTHREFCLK1                  =>      tied_to_ground_i,
+        GTREFCLK0                       =>      GTREFCLK0_IN,
+        GTREFCLK1                       =>      tied_to_ground_i,
+        GTSOUTHREFCLK0                  =>      tied_to_ground_i,
+        GTSOUTHREFCLK1                  =>      tied_to_ground_i,
+        ---------------------------- Channel - DRP Ports  --------------------------
+        DRPADDR                         =>      DRPADDR_IN,
+        DRPCLK                          =>      DRPCLK_IN,
+        DRPDI                           =>      DRPDI_IN,
+        DRPDO                           =>      DRPDO_OUT,
+        DRPEN                           =>      DRPEN_IN,
+        DRPRDY                          =>      DRPRDY_OUT,
+        DRPWE                           =>      DRPWE_IN,
+        ------------------------------- Clocking Ports -----------------------------
+        GTREFCLKMONITOR                 =>      open,
+        QPLLCLK                         =>      QPLLCLK_IN,
+        QPLLREFCLK                      =>      QPLLREFCLK_IN,
+        RXSYSCLKSEL                     =>      "00",
+        TXSYSCLKSEL                     =>      "00",
+        --------------------------- Digital Monitor Ports --------------------------
+        DMONITOROUT                     =>      open,
+        ----------------- FPGA TX Interface Datapath Configuration  ----------------
+        TX8B10BEN                       =>      tied_to_vcc_i,
+        ------------------------------- Loopback Ports -----------------------------
+        LOOPBACK                        =>      LOOPBACK_IN,
+        ----------------------------- PCI Express Ports ----------------------------
+        PHYSTATUS                       =>      open,
+        RXRATE                          =>      tied_to_ground_vec_i(2 downto 0),
+        RXVALID                         =>      open,
+        ------------------------------ Power-Down Ports ----------------------------
+        RXPD                            =>      "00",
+        TXPD                            =>      "00",
+        -------------------------- RX 8B/10B Decoder Ports -------------------------
+        SETERRSTATUS                    =>      tied_to_ground_i,
+        --------------------- RX Initialization and Reset Ports --------------------
+        EYESCANRESET                    =>      tied_to_ground_i,
+        RXUSERRDY                       =>      RXUSERRDY_IN,
+        -------------------------- RX Margin Analysis Ports ------------------------
+        EYESCANDATAERROR                =>      EYESCANDATAERROR_OUT,
+        EYESCANMODE                     =>      tied_to_ground_i,
+        EYESCANTRIGGER                  =>      tied_to_ground_i,
+        ------------------------- Receive Ports - CDR Ports ------------------------
+        RXCDRFREQRESET                  =>      tied_to_ground_i,
+        RXCDRHOLD                       =>      tied_to_ground_i,
+        RXCDRLOCK                       =>      RXCDRLOCK_OUT,
+        RXCDROVRDEN                     =>      tied_to_ground_i,
+--        RXCDRRESET                      =>      tied_to_ground_i,
+        RXCDRRESET                      =>      RXCDRRESET_IN,
+        RXCDRRESETRSV                   =>      tied_to_ground_i,
+        ------------------- Receive Ports - Clock Correction Ports -----------------
+        RXCLKCORCNT                     =>      open,
+        ---------- Receive Ports - FPGA RX Interface Datapath Configuration --------
+        RX8B10BEN                       =>      tied_to_vcc_i,
+        ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+        RXUSRCLK                        =>      RXUSRCLK_IN,
+        RXUSRCLK2                       =>      RXUSRCLK2_IN,
+        ------------------ Receive Ports - FPGA RX interface Ports -----------------
+        RXDATA                          =>      rxdata_i,
+        ------------------- Receive Ports - Pattern Checker Ports ------------------
+        RXPRBSERR                       =>      open,
+        RXPRBSSEL                       =>      tied_to_ground_vec_i(2 downto 0),
+        ------------------- Receive Ports - Pattern Checker ports ------------------
+        RXPRBSCNTRESET                  =>      tied_to_ground_i,
+        -------------------- Receive Ports - RX  Equalizer Ports -------------------
+        RXDFEXYDEN                      =>      tied_to_ground_i,
+        RXDFEXYDHOLD                    =>      tied_to_ground_i,
+        RXDFEXYDOVRDEN                  =>      tied_to_ground_i,
+        ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+        RXDISPERR(7 downto 2)           =>      rxdisperr_float_i,
+        RXDISPERR(1 downto 0)           =>      RXDISPERR_OUT,
+        RXNOTINTABLE(7 downto 2)        =>      rxnotintable_float_i,
+        RXNOTINTABLE(1 downto 0)        =>      RXNOTINTABLE_OUT,
+        --------------------------- Receive Ports - RX AFE -------------------------
+        GTXRXP                          =>      GTXRXP_IN,
+        ------------------------ Receive Ports - RX AFE Ports ----------------------
+        GTXRXN                          =>      GTXRXN_IN,
+        ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+        RXBUFRESET                      =>      tied_to_ground_i,
+        RXBUFSTATUS                     =>      open,
+        RXDDIEN                         =>      tied_to_ground_i,
+        RXDLYBYPASS                     =>      tied_to_vcc_i,
+        RXDLYEN                         =>      tied_to_ground_i,
+        RXDLYOVRDEN                     =>      tied_to_ground_i,
+        RXDLYSRESET                     =>      tied_to_ground_i,
+        RXDLYSRESETDONE                 =>      open,
+        RXPHALIGN                       =>      tied_to_ground_i,
+        RXPHALIGNDONE                   =>      open,
+        RXPHALIGNEN                     =>      tied_to_ground_i,
+        RXPHDLYPD                       =>      tied_to_ground_i,
+        RXPHDLYRESET                    =>      tied_to_ground_i,
+        RXPHMONITOR                     =>      open,
+        RXPHOVRDEN                      =>      tied_to_ground_i,
+        RXPHSLIPMONITOR                 =>      open,
+        RXSTATUS                        =>      open,
+        -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
+        RXBYTEISALIGNED                 =>      RXBYTEISALIGNED_OUT,
+        RXBYTEREALIGN                   =>      open,
+        RXCOMMADET                      =>      RXCOMMADET_OUT,
+        RXCOMMADETEN                    =>      tied_to_vcc_i,
+        RXMCOMMAALIGNEN                 =>      tied_to_ground_i,
+        RXPCOMMAALIGNEN                 =>      tied_to_ground_i,
+        ------------------ Receive Ports - RX Channel Bonding Ports ----------------
+        RXCHANBONDSEQ                   =>      open,
+        RXCHBONDEN                      =>      tied_to_ground_i,
+        RXCHBONDLEVEL                   =>      tied_to_ground_vec_i(2 downto 0),
+        RXCHBONDMASTER                  =>      tied_to_ground_i,
+        RXCHBONDO                       =>      open,
+        RXCHBONDSLAVE                   =>      tied_to_ground_i,
+        ----------------- Receive Ports - RX Channel Bonding Ports  ----------------
+        RXCHANISALIGNED                 =>      open,
+        RXCHANREALIGN                   =>      open,
+        --------------------- Receive Ports - RX Equalizer Ports -------------------
+        RXDFEAGCHOLD                    =>      tied_to_ground_i,
+        RXDFEAGCOVRDEN                  =>      tied_to_ground_i,
+        RXDFECM1EN                      =>      tied_to_ground_i,
+        RXDFELFHOLD                     =>      tied_to_ground_i,
+        RXDFELFOVRDEN                   =>      tied_to_ground_i,
+        RXDFELPMRESET                   =>      tied_to_ground_i,
+        RXDFETAP2HOLD                   =>      tied_to_ground_i,
+        RXDFETAP2OVRDEN                 =>      tied_to_ground_i,
+        RXDFETAP3HOLD                   =>      tied_to_ground_i,
+        RXDFETAP3OVRDEN                 =>      tied_to_ground_i,
+        RXDFETAP4HOLD                   =>      tied_to_ground_i,
+        RXDFETAP4OVRDEN                 =>      tied_to_ground_i,
+        RXDFETAP5HOLD                   =>      tied_to_ground_i,
+        RXDFETAP5OVRDEN                 =>      tied_to_ground_i,
+        RXDFEUTHOLD                     =>      tied_to_ground_i,
+        RXDFEUTOVRDEN                   =>      tied_to_ground_i,
+        RXDFEVPHOLD                     =>      tied_to_ground_i,
+        RXDFEVPOVRDEN                   =>      tied_to_ground_i,
+        RXDFEVSEN                       =>      tied_to_ground_i,
+        RXLPMLFKLOVRDEN                 =>      tied_to_ground_i,
+        RXMONITOROUT                    =>      open,
+        RXMONITORSEL                    =>      "00",
+        RXOSHOLD                        =>      tied_to_ground_i,
+        RXOSOVRDEN                      =>      tied_to_ground_i,
+        --------------------- Receive Ports - RX Equilizer Ports -------------------
+        RXLPMHFHOLD                     =>      RXLPMHFHOLD_IN,
+        RXLPMHFOVRDEN                   =>      tied_to_ground_i,
+        RXLPMLFHOLD                     =>      RXLPMLFHOLD_IN,
+        ------------ Receive Ports - RX Fabric ClocK Output Control Ports ----------
+        RXRATEDONE                      =>      open,
+        --------------- Receive Ports - RX Fabric Output Control Ports -------------
+        RXOUTCLK                        =>      RXOUTCLK_OUT,
+        RXOUTCLKFABRIC                  =>      open,
+        RXOUTCLKPCS                     =>      open,
+        RXOUTCLKSEL                     =>      "010",
+        ---------------------- Receive Ports - RX Gearbox Ports --------------------
+        RXDATAVALID                     =>      open,
+        RXHEADER                        =>      open,
+        RXHEADERVALID                   =>      open,
+        RXSTARTOFSEQ                    =>      open,
+        --------------------- Receive Ports - RX Gearbox Ports  --------------------
+        RXGEARBOXSLIP                   =>      tied_to_ground_i,
+        ------------- Receive Ports - RX Initialization and Reset Ports ------------
+        GTRXRESET                       =>      GTRXRESET_IN,
+        RXOOBRESET                      =>      tied_to_ground_i,
+        RXPCSRESET                      =>      tied_to_ground_i,
+        RXPMARESET                      =>      RXPMARESET_IN,
+        ------------------ Receive Ports - RX Margin Analysis ports ----------------
+        RXLPMEN                         =>      tied_to_vcc_i,
+        ------------------- Receive Ports - RX OOB Signaling ports -----------------
+        RXCOMSASDET                     =>      open,
+        RXCOMWAKEDET                    =>      open,
+        ------------------ Receive Ports - RX OOB Signaling ports  -----------------
+        RXCOMINITDET                    =>      open,
+        ------------------ Receive Ports - RX OOB signalling Ports -----------------
+        RXELECIDLE                      =>      open,
+        RXELECIDLEMODE                  =>      "11",
+        ----------------- Receive Ports - RX Polarity Control Ports ----------------
+        RXPOLARITY                      =>      tied_to_ground_i,
+        ---------------------- Receive Ports - RX gearbox ports --------------------
+        RXSLIDE                         =>      RXSLIDE_IN,
+        ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+        RXCHARISCOMMA                   =>      open,
+        RXCHARISK(7 downto 2)           =>      rxcharisk_float_i,
+        RXCHARISK(1 downto 0)           =>      RXCHARISK_OUT,
+        ------------------ Receive Ports - Rx Channel Bonding Ports ----------------
+        RXCHBONDI                       =>      "00000",
+        -------------- Receive Ports -RX Initialization and Reset Ports ------------
+        RXRESETDONE                     =>      RXRESETDONE_OUT,
+        -------------------------------- Rx AFE Ports ------------------------------
+        RXQPIEN                         =>      tied_to_ground_i,
+        RXQPISENN                       =>      open,
+        RXQPISENP                       =>      open,
+        --------------------------- TX Buffer Bypass Ports -------------------------
+        TXPHDLYTSTCLK                   =>      tied_to_ground_i,
+        ------------------------ TX Configurable Driver Ports ----------------------
+        TXPOSTCURSOR                    =>      "00000",
+        TXPOSTCURSORINV                 =>      tied_to_ground_i,
+        TXPRECURSOR                     =>      tied_to_ground_vec_i(4 downto 0),
+        TXPRECURSORINV                  =>      tied_to_ground_i,
+        TXQPIBIASEN                     =>      tied_to_ground_i,
+        TXQPISTRONGPDOWN                =>      tied_to_ground_i,
+        TXQPIWEAKPUP                    =>      tied_to_ground_i,
+        --------------------- TX Initialization and Reset Ports --------------------
+        CFGRESET                        =>      tied_to_ground_i,
+        GTTXRESET                       =>      GTTXRESET_IN,
+        PCSRSVDOUT                      =>      open,
+        TXUSERRDY                       =>      TXUSERRDY_IN,
+        ---------------------- Transceiver Reset Mode Operation --------------------
+        GTRESETSEL                      =>      tied_to_ground_i,
+        RESETOVRD                       =>      tied_to_ground_i,
+        ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
+        TXCHARDISPMODE                  =>      tied_to_ground_vec_i(7 downto 0),
+        TXCHARDISPVAL                   =>      tied_to_ground_vec_i(7 downto 0),
+        ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+        TXUSRCLK                        =>      TXUSRCLK_IN,
+        TXUSRCLK2                       =>      TXUSRCLK2_IN,
+        --------------------- Transmit Ports - PCI Express Ports -------------------
+        TXELECIDLE                      =>      tied_to_ground_i,
+        TXMARGIN                        =>      tied_to_ground_vec_i(2 downto 0),
+        TXRATE                          =>      tied_to_ground_vec_i(2 downto 0),
+        TXSWING                         =>      tied_to_ground_i,
+        ------------------ Transmit Ports - Pattern Generator Ports ----------------
+        TXPRBSFORCEERR                  =>      tied_to_ground_i,
+        ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+        TXDLYBYPASS                     =>      tied_to_vcc_i,
+        TXDLYEN                         =>      tied_to_ground_i,
+        TXDLYHOLD                       =>      tied_to_ground_i,
+        TXDLYOVRDEN                     =>      tied_to_ground_i,
+        TXDLYSRESET                     =>      tied_to_ground_i,
+        TXDLYSRESETDONE                 =>      open,
+        TXDLYUPDOWN                     =>      tied_to_ground_i,
+        TXPHALIGN                       =>      tied_to_ground_i,
+        TXPHALIGNDONE                   =>      open,
+        TXPHALIGNEN                     =>      tied_to_ground_i,
+        TXPHDLYPD                       =>      tied_to_ground_i,
+        TXPHDLYRESET                    =>      tied_to_ground_i,
+        TXPHINIT                        =>      tied_to_ground_i,
+        TXPHINITDONE                    =>      open,
+        TXPHOVRDEN                      =>      tied_to_ground_i,
+        ---------------------- Transmit Ports - TX Buffer Ports --------------------
+        TXBUFSTATUS                     =>      open,
+        --------------- Transmit Ports - TX Configurable Driver Ports --------------
+        TXBUFDIFFCTRL                   =>      "100",
+        TXDEEMPH                        =>      tied_to_ground_i,
+        TXDIFFCTRL                      =>      "1000",
+        TXDIFFPD                        =>      tied_to_ground_i,
+        TXINHIBIT                       =>      tied_to_ground_i,
+        TXMAINCURSOR                    =>      "0000000",
+        TXPISOPD                        =>      tied_to_ground_i,
+        ------------------ Transmit Ports - TX Data Path interface -----------------
+        TXDATA                          =>      txdata_i,
+        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+        GTXTXN                          =>      GTXTXN_OUT,
+        GTXTXP                          =>      GTXTXP_OUT,
+        ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+        TXOUTCLK                        =>      TXOUTCLK_OUT,
+        TXOUTCLKFABRIC                  =>      TXOUTCLKFABRIC_OUT,
+        TXOUTCLKPCS                     =>      TXOUTCLKPCS_OUT,
+        TXOUTCLKSEL                     =>      "010",
+        TXRATEDONE                      =>      open,
+        --------------------- Transmit Ports - TX Gearbox Ports --------------------
+        TXCHARISK(7 downto 2)           =>      tied_to_ground_vec_i(5 downto 0),
+        TXCHARISK(1 downto 0)           =>      TXCHARISK_IN,
+        TXGEARBOXREADY                  =>      open,
+        TXHEADER                        =>      tied_to_ground_vec_i(2 downto 0),
+        TXSEQUENCE                      =>      tied_to_ground_vec_i(6 downto 0),
+        TXSTARTSEQ                      =>      tied_to_ground_i,
+        ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+        TXPCSRESET                      =>      tied_to_ground_i,
+        TXPMARESET                      =>      tied_to_ground_i,
+        TXRESETDONE                     =>      TXRESETDONE_OUT,
+        ------------------ Transmit Ports - TX OOB signalling Ports ----------------
+        TXCOMFINISH                     =>      open,
+        TXCOMINIT                       =>      tied_to_ground_i,
+        TXCOMSAS                        =>      tied_to_ground_i,
+        TXCOMWAKE                       =>      tied_to_ground_i,
+        TXPDELECIDLEMODE                =>      tied_to_ground_i,
+        ----------------- Transmit Ports - TX Polarity Control Ports ---------------
+        TXPOLARITY                      =>      tied_to_ground_i,
+        --------------- Transmit Ports - TX Receiver Detection Ports  --------------
+        TXDETECTRX                      =>      tied_to_ground_i,
+        ------------------ Transmit Ports - TX8b/10b Encoder Ports -----------------
+        TX8B10BBYPASS                   =>      tied_to_ground_vec_i(7 downto 0),
+        ------------------ Transmit Ports - pattern Generator Ports ----------------
+        TXPRBSSEL                       =>      TXPRBSSEL_IN,
+        ----------------------- Tx Configurable Driver  Ports ----------------------
+        TXQPISENN                       =>      open,
+        TXQPISENP                       =>      open
+
+    );
+ 
+ end RTL;
+
+
+ 
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/family7-gtx/wr_gtx_phy_family7.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/family7-gtx/wr_gtx_phy_family7.vhd
new file mode 100644
index 000000000..bc1249fa1
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/family7-gtx/wr_gtx_phy_family7.vhd
@@ -0,0 +1,505 @@
+-------------------------------------------------------------------------------
+-- Title      : Deterministic Xilinx GTX wrapper - kintex-7 top module
+-- Project    : White Rabbit Switch
+-------------------------------------------------------------------------------
+-- File       : wr_gtx_phy_family7.vhd
+-- Author     : Peter Jansweijer, Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2013-04-08
+-- Last update: 2013-04-08
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Dual channel wrapper for Xilinx Kintex-7 GTX adapted for
+-- deterministic delays at 1.25 Gbps.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2010 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-- 
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author    Description
+-- 2013-04-08  0.1      PeterJ    Initial release based on "wr_gtx_phy_virtex6.vhd"
+-- 2013-08-19  0.2      PeterJ    Implemented a small delay before a rx_cdr_lock is propgated
+-- 2014-02_19  0.3      Peterj    Added tx_locked_o to indicate that the cpll reached the lock status
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.gencores_pkg.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+library work;
+--use work.gencores_pkg.all;
+use work.disparity_gen_pkg.all;
+
+entity wr_gtx_phy_family7 is
+
+  generic (
+    -- set to non-zero value to speed up the simulation by reducing some delays
+    g_simulation         : integer := 0
+    );
+
+  port (
+    -- Dedicated reference 125 MHz clock for the GTX transceiver
+    clk_gtx_i : in std_logic;
+
+    -- TX path, synchronous to tx_out_clk_o (62.5 MHz):
+    tx_out_clk_o : out std_logic;
+    tx_locked_o  : out std_logic;
+
+    -- data input (8 bits, not 8b10b-encoded)
+    tx_data_i : in std_logic_vector(15 downto 0);
+
+    -- 1 when tx_data_i contains a control code, 0 when it's a data byte
+    tx_k_i : in std_logic_vector(1 downto 0);
+
+    -- disparity of the currently transmitted 8b10b code (1 = plus, 0 = minus).
+    -- Necessary for the PCS to generate proper frame termination sequences.
+    -- Generated for the 2nd byte (LSB) of tx_data_i.
+    tx_disparity_o : out std_logic;
+
+    -- Encoding error indication (1 = error, 0 = no error)
+    tx_enc_err_o : out std_logic;
+
+    -- RX path, synchronous to ch0_rx_rbclk_o.
+
+    -- RX recovered clock
+    rx_rbclk_o : out std_logic;
+
+    -- 8b10b-decoded data output. The data output must be kept invalid before
+    -- the transceiver is locked on the incoming signal to prevent the EP from
+    -- detecting a false carrier.
+    rx_data_o : out std_logic_vector(15 downto 0);
+
+    -- 1 when the byte on rx_data_o is a control code
+    rx_k_o : out std_logic_vector(1 downto 0);
+
+    -- encoding error indication
+    rx_enc_err_o : out std_logic;
+
+    -- RX bitslide indication, indicating the delay of the RX path of the
+    -- transceiver (in UIs). Must be valid when ch0_rx_data_o is valid.
+    rx_bitslide_o : out std_logic_vector(4 downto 0);
+
+    -- reset input, active hi
+    rst_i         : in std_logic;
+    loopen_i      : in std_logic_vector(2 downto 0);
+    tx_prbs_sel_i : in std_logic_vector(2 downto 0);
+    pad_txn_o : out std_logic;
+    pad_txp_o : out std_logic;
+
+    pad_rxn_i : in std_logic := '0';
+    pad_rxp_i : in std_logic := '0';
+
+    rdy_o     : out std_logic);
+end wr_gtx_phy_family7;
+
+architecture rtl of wr_gtx_phy_family7 is
+
+  component WHITERABBIT_GTXE2_CHANNEL_WRAPPER_GT is
+    generic
+    (
+        -- Simulation attributes
+        GT_SIM_GTRESET_SPEEDUP    : string     :=  "TRUE";        -- Set to "TRUE" to speed up sim reset (Need Capital Letters!)
+        RX_DFE_KL_CFG2_IN         : bit_vector :=   X"3010D90C";
+        PMA_RSV_IN                : bit_vector :=   X"00018480";
+        PCS_RSVD_ATTR_IN          : bit_vector :=   X"000000000000"
+    );
+    port 
+    (
+    --------------------------------- CPLL Ports -------------------------------
+    CPLLFBCLKLOST_OUT                       : out  std_logic;
+    CPLLLOCK_OUT                            : out  std_logic;
+    CPLLLOCKDETCLK_IN                       : in   std_logic;
+    CPLLREFCLKLOST_OUT                      : out  std_logic;
+    CPLLRESET_IN                            : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    GTREFCLK0_IN                            : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    DRPADDR_IN                              : in   std_logic_vector(8 downto 0);
+    DRPCLK_IN                               : in   std_logic;
+    DRPDI_IN                                : in   std_logic_vector(15 downto 0);
+    DRPDO_OUT                               : out  std_logic_vector(15 downto 0);
+    DRPEN_IN                                : in   std_logic;
+    DRPRDY_OUT                              : out  std_logic;
+    DRPWE_IN                                : in   std_logic;
+    ------------------------------- Clocking Ports -----------------------------
+    QPLLCLK_IN                              : in   std_logic;
+    QPLLREFCLK_IN                           : in   std_logic;
+    ------------------------------- Loopback Ports -----------------------------
+    LOOPBACK_IN                             : in   std_logic_vector(2 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    RXUSERRDY_IN                            : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    EYESCANDATAERROR_OUT                    : out  std_logic;
+    ------------------------- Receive Ports - CDR Ports ------------------------
+    RXCDRLOCK_OUT                           : out  std_logic;
+    RXCDRRESET_IN                           : in   std_logic;
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    RXUSRCLK_IN                             : in   std_logic;
+    RXUSRCLK2_IN                            : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    RXDATA_OUT                              : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    RXDISPERR_OUT                           : out  std_logic_vector(1 downto 0);
+    RXNOTINTABLE_OUT                        : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    GTXRXP_IN                               : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    GTXRXN_IN                               : in   std_logic;
+    -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
+    RXBYTEISALIGNED_OUT                     : out  std_logic;
+    RXCOMMADET_OUT                          : out  std_logic;
+    --------------------- Receive Ports - RX Equilizer Ports -------------------
+    RXLPMHFHOLD_IN                          : in   std_logic;
+    RXLPMLFHOLD_IN                          : in   std_logic;
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    RXOUTCLK_OUT                            : out  std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    GTRXRESET_IN                            : in   std_logic;
+    RXPMARESET_IN                           : in   std_logic;
+    ---------------------- Receive Ports - RX gearbox ports --------------------
+    RXSLIDE_IN                              : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    RXCHARISK_OUT                           : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    RXRESETDONE_OUT                         : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    GTTXRESET_IN                            : in   std_logic;
+    TXUSERRDY_IN                            : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    TXUSRCLK_IN                             : in   std_logic;
+    TXUSRCLK2_IN                            : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    TXDATA_IN                               : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    GTXTXN_OUT                              : out  std_logic;
+    GTXTXP_OUT                              : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    TXOUTCLK_OUT                            : out  std_logic;
+    TXOUTCLKFABRIC_OUT                      : out  std_logic;
+    TXOUTCLKPCS_OUT                         : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    TXCHARISK_IN                            : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    TXRESETDONE_OUT                         : out  std_logic;
+    ------------------ Transmit Ports - pattern Generator Ports ----------------
+    TXPRBSSEL_IN                            : in   std_logic_vector(2 downto 0)
+	);
+  end component WHITERABBIT_GTXE2_CHANNEL_WRAPPER_GT;
+
+  component BUFG
+    port (
+      O : out std_ulogic;
+      I : in  std_ulogic);
+  end component;
+
+  component gtp_bitslide
+    generic (
+      g_simulation : integer;
+      g_target     : string := "virtex6");
+    port (
+      gtp_rst_i                : in  std_logic;
+      gtp_rx_clk_i             : in  std_logic;
+      gtp_rx_comma_det_i       : in  std_logic;
+      gtp_rx_byte_is_aligned_i : in  std_logic;
+      serdes_ready_i           : in  std_logic;
+      gtp_rx_slide_o           : out std_logic;
+      gtp_rx_cdr_rst_o         : out std_logic;
+      bitslide_o               : out std_logic_vector(4 downto 0);
+      synced_o                 : out std_logic);
+  end component;
+
+  constant c_rxcdrlock_max            : integer := 3;
+  constant c_reset_cnt_max            : integer := 64;	-- Reset pulse width 64 * 8 = 512 ns
+  
+  signal rst_synced                   : std_logic;
+  signal rst_int                      : std_logic;
+--  signal trig0, trig1, trig2, trig3   : std_logic_vector(31 downto 0);
+
+  signal rx_rec_clk_bufin             : std_logic;
+  signal rx_rec_clk                   : std_logic;
+  signal tx_out_clk_bufin             : std_logic;
+  signal tx_out_clk                   : std_logic;
+  signal rx_cdr_lock                  : std_logic;
+  signal rx_cdr_lock_filtered         : std_logic;
+
+  signal tx_rst_done, rx_rst_done     : std_logic;
+  signal txpll_lockdet, rxpll_lockdet : std_logic;
+  signal pll_lockdet                  : std_logic;
+  signal cpll_lockdet                 : std_logic;
+  signal gtreset                      : std_logic;
+
+  signal rx_comma_det                 : std_logic;
+  signal rx_byte_is_aligned           : std_logic;
+
+  signal everything_ready             : std_logic;
+  signal rx_slide                     : std_logic;
+  signal rx_cdr_rst                   : std_logic;
+  signal rx_synced                    : std_logic;
+  signal rst_done                     : std_logic;
+  signal rst_done_n                   : std_logic;
+ 
+  signal rx_k_int                     : std_logic_vector(1 downto 0);
+  signal rx_data_int                  : std_logic_vector(15 downto 0);
+
+  signal rx_disp_err, rx_code_err     : std_logic_vector(1 downto 0);
+
+  signal tx_is_k_swapped              : std_logic_vector(1 downto 0);
+  signal tx_data_swapped              : std_logic_vector(15 downto 0);
+
+  signal cur_disp                     : t_8b10b_disparity;
+
+begin  -- rtl
+
+  -- There is a hen and egg problem with the reset in wr_core. Some reset signals are
+  -- synchronized by rx_rbclk_o but this signal is de-asserted by the same reset.
+  -- Therefore the rst_i is made edge sensitive and an internal reset pulse is generated for the PHY.
+  -- After this reset pulse signal rx_rbclk_o starts clocking again and the (still asserted) system
+  -- wide reset signal can by synchronized with this clock.
+
+  -- Note that the rst_i originates from the clk_sys domain. Synchronisation is not needed
+  -- when the clk_sys is phase locked with clk_gtx_i (which is usually the case) but is a safety
+  -- measure. Add a false path for U_EdgeDet_rst_i_reg_sync0 to the timing constraints.
+  U_EdgeDet_rst_i : gc_sync_ffs port map (
+    clk_i    => clk_gtx_i,
+    rst_n_i  => '1',
+    data_i   => rst_i,
+    ppulse_o => rst_synced);
+
+  p_reset_pulse : process(clk_gtx_i, rst_synced)
+    variable reset_cnt      : integer range 0 to c_reset_cnt_max;
+  begin
+    if(rst_synced = '1') then
+      reset_cnt := 0;
+      rst_int <= '1';
+    elsif rising_edge(clk_gtx_i) then
+      if reset_cnt /= c_reset_cnt_max then
+        reset_cnt := reset_cnt + 1;
+		rst_int <= '1';
+      else
+        rst_int <= '0';
+      end if;
+    end if;
+  end process;  
+
+  tx_enc_err_o <= '0';
+
+  U_BUF_TxOutClk : BUFG
+    port map (
+      I => tx_out_clk_bufin,
+      O => tx_out_clk);
+
+   tx_out_clk_o <= tx_out_clk;
+   tx_locked_o  <= cpll_lockdet;
+
+      U_BUF_RxRecClk : BUFG
+    port map (
+      I => rx_rec_clk_bufin,
+      O => rx_rec_clk);
+
+  rx_rbclk_o <= rx_rec_clk;
+    
+  tx_is_k_swapped <= tx_k_i(0) & tx_k_i(1);
+  tx_data_swapped <= tx_data_i(7 downto 0) & tx_data_i(15 downto 8);
+  
+U_GTX_INST : WHITERABBIT_GTXE2_CHANNEL_WRAPPER_GT
+    generic map
+    (
+       -- Simulation attributes
+       GT_SIM_GTRESET_SPEEDUP    =>  "TRUE"        -- Set to "true" to speed up sim reset
+    )
+    port map
+    (
+		--------------------------------- CPLL Ports -------------------------------
+		CPLLFBCLKLOST_OUT          => open,
+		CPLLLOCK_OUT               => cpll_lockdet,
+		CPLLLOCKDETCLK_IN          => '0',
+		CPLLREFCLKLOST_OUT         => open,
+		CPLLRESET_IN               => rst_int,
+		-------------------------- Channel - Clocking Ports ------------------------
+		GTREFCLK0_IN               => clk_gtx_i,
+		---------------------------- Channel - DRP Ports  --------------------------
+		DRPADDR_IN                 => (Others => '0'),
+		DRPCLK_IN                  => '0',
+		DRPDI_IN                   => (Others => '0'),
+		DRPDO_OUT                  => open,
+		DRPEN_IN                   => '0',
+		DRPRDY_OUT                 => open,
+		DRPWE_IN                   => '0',
+		------------------------------- Clocking Ports -----------------------------
+		QPLLCLK_IN                 => '0',
+		QPLLREFCLK_IN              => '0',
+		------------------------------- Loopback Ports -----------------------------
+		LOOPBACK_IN                => loopen_i,
+		--------------------- RX Initialization and Reset Ports --------------------
+--		RXUSERRDY_IN               => rx_cdr_lock,
+		RXUSERRDY_IN               => rx_cdr_lock_filtered,
+		-------------------------- RX Margin Analysis Ports ------------------------
+		EYESCANDATAERROR_OUT       => open,
+		------------------------- Receive Ports - CDR Ports ------------------------
+		RXCDRLOCK_OUT              => rx_cdr_lock,
+		RXCDRRESET_IN              => rx_cdr_rst,   -- this port cannot be generated by the CoreGen GUI, it cannot be turnes "on"                           : in   std_logic;
+		------------------ Receive Ports - FPGA RX Interface Ports -----------------
+		RXUSRCLK_IN                => rx_rec_clk,
+		RXUSRCLK2_IN               => rx_rec_clk,
+		------------------ Receive Ports - FPGA RX interface Ports -----------------
+		RXDATA_OUT                 => rx_data_int,
+		------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+		RXDISPERR_OUT              => rx_disp_err,
+		RXNOTINTABLE_OUT           => rx_code_err,
+		--------------------------- Receive Ports - RX AFE -------------------------
+		GTXRXP_IN                  => pad_rxp_i,
+		------------------------ Receive Ports - RX AFE Ports ----------------------
+		GTXRXN_IN                  => pad_rxn_i,
+		-------------- Receive Ports - RX Byte and Word Alignment Ports ------------
+		RXBYTEISALIGNED_OUT        => rx_byte_is_aligned,
+		RXCOMMADET_OUT             => rx_comma_det,
+		--------------------- Receive Ports - RX Equilizer Ports -------------------
+		RXLPMHFHOLD_IN             => '0',          -- this port is always generated by the CoreGen GUI and cannot be turned "off"
+		RXLPMLFHOLD_IN             => '0',          -- this port is always generated by the CoreGen GUI and cannot be turned "off"
+		--------------- Receive Ports - RX Fabric Output Control Ports -------------
+		RXOUTCLK_OUT               => rx_rec_clk_bufin,
+		------------- Receive Ports - RX Initialization and Reset Ports ------------
+		GTRXRESET_IN               => gtreset,
+		RXPMARESET_IN              => '0',
+		---------------------- Receive Ports - RX gearbox ports --------------------
+		RXSLIDE_IN                 => rx_slide,
+		------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+		RXCHARISK_OUT              => rx_k_int,
+		-------------- Receive Ports -RX Initialization and Reset Ports ------------
+		RXRESETDONE_OUT            => rx_rst_done,
+		--------------------- TX Initialization and Reset Ports --------------------
+		GTTXRESET_IN               => gtreset,
+		TXUSERRDY_IN               => cpll_lockdet,
+		------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+		TXUSRCLK_IN                => tx_out_clk,
+		TXUSRCLK2_IN               => tx_out_clk,
+		------------------ Transmit Ports - TX Data Path interface -----------------
+		TXDATA_IN                  => tx_data_swapped,
+--       TXDATA_IN                  => tx_data_i,
+		---------------- Transmit Ports - TX Driver and OOB signaling --------------
+		GTXTXN_OUT                 => pad_txn_o,
+		GTXTXP_OUT                 => pad_txp_o,
+		----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+		TXOUTCLK_OUT               => tx_out_clk_bufin,
+		TXOUTCLKFABRIC_OUT         => open,
+		TXOUTCLKPCS_OUT            => open,
+		--------------------- Transmit Ports - TX Gearbox Ports --------------------
+		TXCHARISK_IN               => tx_is_k_swapped,
+--       TXCHARISK_IN               => tx_k_i,
+		------------- Transmit Ports - TX Initialization and Reset Ports -----------
+		TXRESETDONE_OUT            => tx_rst_done,
+                ------------------ Transmit Ports - pattern Generator Ports ----------------
+    TXPRBSSEL_IN               => tx_prbs_sel_i
+    );
+
+  U_Bitslide : gtp_bitslide
+    generic map (
+      g_simulation => g_simulation,
+      g_target     => "kintex7")
+    port map (
+      gtp_rst_i                => rst_done_n,
+      gtp_rx_clk_i             => rx_rec_clk,
+      gtp_rx_comma_det_i       => rx_comma_det,
+      gtp_rx_byte_is_aligned_i => rx_byte_is_aligned,
+      serdes_ready_i           => everything_ready,
+      gtp_rx_slide_o           => rx_slide,
+      gtp_rx_cdr_rst_o         => rx_cdr_rst,
+      bitslide_o               => rx_bitslide_o,
+      synced_o                 => rx_synced);
+
+  txpll_lockdet    <= cpll_lockdet;
+--  rxpll_lockdet    <= rx_cdr_lock;
+  rxpll_lockdet    <= rx_cdr_lock_filtered;
+  gtreset          <= not cpll_lockdet;
+  rst_done         <= rx_rst_done and tx_rst_done;
+  rst_done_n       <= not rst_done;
+  pll_lockdet      <= txpll_lockdet and rxpll_lockdet;
+  everything_ready <= rst_done and pll_lockdet;
+  rdy_o            <= everything_ready;
+
+--  trig2(3) <= rx_rst_done;
+--  trig2(4) <= tx_rst_done;
+--  trig2(5) <= txpll_lockdet;
+--  trig2(6) <= rxpll_lockdet;
+--  trig2(7) <= '1';
+
+  -- 2013 August 19: Peterj
+  -- The family 7 GTX seem to have an artifact in rx_cdr_lock. For no reason lock may be lost for a clock cycle
+  -- There is not much information on the web but examples of "Series-7 Integrated Block for PCI Express" (pipe_user.v)
+  -- show that Xilinx itself implements a small delay before an rx_cdr_lock is propagated.
+  p_rx_cdr_lock_filter : process(rx_rec_clk, rst_int)
+    variable rxcdrlock_cnt      : integer range 0 to c_rxcdrlock_max;
+  begin
+    if(rst_int = '1') then  
+      rxcdrlock_cnt := 0;
+      rx_cdr_lock_filtered <= '0';
+    elsif rising_edge(rx_rec_clk) then
+      if rx_cdr_lock = '0' then
+        if rxcdrlock_cnt /= c_rxcdrlock_max then
+           rxcdrlock_cnt := rxcdrlock_cnt + 1;
+        else
+           rx_cdr_lock_filtered <= '0';
+        end if;
+      else
+        rxcdrlock_cnt := 0;
+        rx_cdr_lock_filtered <= '1';
+      end if;
+    end if;
+  end process;
+
+  p_gen_rx_outputs : process(rx_rec_clk, rst_done_n)
+  begin
+    if(rst_done_n = '1') then
+      rx_data_o    <= (others => '0');
+      rx_k_o       <= (others => '0');
+      rx_enc_err_o <= '0';
+    elsif rising_edge(rx_rec_clk) then
+      if(everything_ready = '1' and rx_synced = '1') then
+        rx_data_o    <= rx_data_int(7 downto 0) & rx_data_int(15 downto 8);
+        rx_k_o       <= rx_k_int(0) & rx_k_int(1);
+        rx_enc_err_o <= rx_disp_err(0) or rx_disp_err(1) or rx_code_err(0) or rx_code_err(1);
+      else
+        rx_data_o    <= (others => '1');
+        rx_k_o       <= (others => '1');
+        rx_enc_err_o <= '1';
+      end if;
+    end if;
+  end process;
+
+  p_gen_tx_disparity : process(tx_out_clk, rst_done_n)
+  begin
+    if rising_edge(tx_out_clk) then
+      if rst_done_n = '1' then
+        cur_disp <= RD_MINUS;
+      else
+        cur_disp <= f_next_8b10b_disparity16(cur_disp, tx_k_i, tx_data_i);
+      end if;
+    end if;
+  end process;
+
+  tx_disparity_o <= to_std_logic(cur_disp);
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd
new file mode 100644
index 000000000..07ca69aa5
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd
@@ -0,0 +1,230 @@
+-------------------------------------------------------------------------------
+-- Title      : Deterministic Xilinx GTP wrapper - bitslide state machine
+-- Project    : White Rabbit Switch
+-------------------------------------------------------------------------------
+-- File       : gtp_bitslide.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2010-11-18
+-- Last update: 2013-12-20
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Module implements a manual bitslide alignment state machine and
+-- provides the obtained bitslide value to the MAC.
+-------------------------------------------------------------------------------
+--
+-- Original EASE design (c) 2010 NIKHEF / Peter Jansweijer and Henk Peek
+-- VHDL port (c) 2010 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author    Description
+-- 2010-11-18  0.4      twlostow  Ported EASE design to VHDL 
+-- 2011-02-07  0.5      twlostow  Verified on Spartan6 GTP
+-- 2011-09-12  0.6      twlostow  Virtex6 port
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity gtp_bitslide is
+  
+  generic (
+-- set to non-zero value to enable some simulation speedups (reduce delays)
+    g_simulation : integer;
+    g_target     : string := "spartan6");
+
+  port (
+    gtp_rst_i : in std_logic;
+
+-- GTP
+    gtp_rx_clk_i : in std_logic;
+
+-- '1' indicates that the GTP has detected a comma in the incoming serial stream
+    gtp_rx_comma_det_i : in std_logic;
+
+
+    gtp_rx_byte_is_aligned_i : in std_logic;
+
+-- GTP ready flag (PLL locked and RX signal present)
+    serdes_ready_i : in std_logic;
+
+-- GTP manual bitslip control line
+    gtp_rx_slide_o : out std_logic;
+
+-- GTP CDR reset, asserted when the link is lost to set the bitslide to a known
+-- value
+    gtp_rx_cdr_rst_o : out std_logic;
+
+-- Current bitslide, in UIs
+    bitslide_o : out std_logic_vector(4 downto 0);
+
+-- '1' when the bitsliding has been completed and the link is up
+    synced_o : out std_logic
+    );
+
+end gtp_bitslide;
+
+
+architecture behavioral of gtp_bitslide is
+
+
+
+  function f_eval_sync_detect_threshold
+    return integer is
+  begin
+    if(g_simulation /= 0) then
+      return 256;
+    else
+      return 4000000;
+    end if;
+  end f_eval_sync_detect_threshold;
+
+  function f_eval_pause_tics return integer is
+  begin
+    if(g_target = "spartan6") then
+      return 31;
+    else
+      return 63;
+    end if;
+  end f_eval_pause_tics;
+
+  function f_max_bts return integer is
+  begin
+    if(g_target = "spartan6") then
+      return 10;
+    else
+      return 20;
+    end if;
+  end f_max_bts;
+
+  constant c_pause_tics            : integer := f_eval_pause_tics;
+  constant c_sync_detect_threshold : integer := f_eval_sync_detect_threshold;
+  constant c_max_bts               : integer := f_max_bts;
+
+
+  type t_bitslide_fsm_state is (S_SYNC_LOST, S_STABILIZE, S_SLIDE, S_PAUSE, S_GOT_SYNC, S_RESET_CDR);
+  signal cur_slide : unsigned(4 downto 0);
+  signal state     : t_bitslide_fsm_state;
+  signal counter   : unsigned(23 downto 0);
+
+  signal commas_missed : unsigned(4 downto 0);
+  
+begin  -- behavioral
+
+  p_do_slide : process(gtp_rx_clk_i, gtp_rst_i)
+  begin
+    if gtp_rst_i = '1' then
+      state            <= S_SYNC_LOST;
+      gtp_rx_slide_o   <= '0';
+      counter          <= (others => '0');
+      synced_o         <= '0';
+      gtp_rx_cdr_rst_o <= '0';
+    elsif rising_edge(gtp_rx_clk_i) then
+      
+      if(serdes_ready_i = '0') then
+        state <= S_SYNC_LOST;
+      end if;
+
+      case state is
+
+-- State: synchronization lost. Waits until a comma pattern is detected
+        when S_SYNC_LOST =>
+          cur_slide        <= (others => '0');
+          counter          <= (others => '0');
+          gtp_rx_slide_o   <= '0';
+          synced_o         <= '0';
+          gtp_rx_cdr_rst_o <= '0';
+          commas_missed    <= (others => '0');
+
+          if(gtp_rx_comma_det_i = '1') then
+            state <= S_STABILIZE;
+          end if;
+
+-- State: stabilize: 
+          
+        when S_STABILIZE =>
+          
+          
+          if(gtp_rx_comma_det_i = '1') then
+            counter       <= counter + 1;
+            commas_missed <= (others => '0');
+          else
+
+            commas_missed <= commas_missed + 1;
+            if(commas_missed(3) = '1') then
+              state <= S_SYNC_LOST;
+            end if;
+          end if;
+
+          if(counter = to_unsigned(c_sync_detect_threshold, counter'length)) then
+            counter <= (others => '0');
+            state   <= S_PAUSE;
+          end if;
+
+          if(serdes_ready_i = '0') then
+            state <= S_SYNC_LOST;
+          end if;
+
+        when S_SLIDE =>
+          if (cur_slide < c_max_bts-1) then
+            cur_slide <= cur_slide + 1;
+          else
+            cur_slide <= (others=>'0');
+          end if;
+          gtp_rx_slide_o <= '1';
+          counter        <= (others => '0');
+
+          state <= S_PAUSE;
+
+          if(serdes_ready_i = '0') then
+            state <= S_SYNC_LOST;
+          end if;
+
+        when S_PAUSE =>
+          counter        <= counter + 1;
+          gtp_rx_slide_o <= '0';
+
+          if(counter = to_unsigned(c_pause_tics, counter'length)) then
+
+            if(gtp_rx_byte_is_aligned_i = '0') then
+              state <= S_SLIDE;
+            else
+              state <= S_GOT_SYNC;
+            end if;
+          end if;
+
+        when S_GOT_SYNC =>
+          gtp_rx_slide_o <= '0';
+          bitslide_o     <= std_logic_vector(cur_slide(4 downto 0));
+          synced_o       <= '1';
+          if(gtp_rx_byte_is_aligned_i = '0' or serdes_ready_i = '0') then
+            gtp_rx_cdr_rst_o <= '1';
+            state            <= S_SYNC_LOST;
+          end if;
+        when others => null;
+      end case;
+    end if;
+  end process;
+  
+  
+
+end behavioral;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/spartan6/gtp_phase_align.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/spartan6/gtp_phase_align.vhd
new file mode 100644
index 000000000..a95ecdd22
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/spartan6/gtp_phase_align.vhd
@@ -0,0 +1,137 @@
+------------------------------------------------------------------------------
+-- Title      : Deterministic Xilinx GTP wrapper - TX phase alignment
+-- Project    : White Rabbit Switch
+-------------------------------------------------------------------------------
+-- File       : gtp_phase_align.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2010-11-18
+-- Last update: 2011-09-12
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: TX phase alignment state machine, as recommended by Xilinx.
+-------------------------------------------------------------------------------
+--
+-- Original EASE design (c) 2010 NIKHEF / Peter Jansweijer and Henk Peek
+-- VHDL port (c) 2010 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author    Description
+-- 2010-11-18  0.4      twlostow  Ported EASE design to VHDL 
+-- 2011-02-07  0.5      twlostow  Verified on Spartan6 GTP
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity gtp_phase_align is
+  generic
+    (g_simulation : integer);
+  
+  port (
+    gtp_rst_i    : in std_logic;
+    gtp_tx_clk_i : in std_logic;
+
+    gtp_tx_en_pma_phase_align_o : out std_logic;
+    gtp_tx_pma_set_phase_o      : out std_logic;
+
+    align_en_i   : in  std_logic;
+    align_done_o : out std_logic
+    );
+
+end gtp_phase_align;
+
+architecture behavioral of gtp_phase_align is
+
+  constant c_wait_en_phase_align  : integer := 32;
+  constant c_wait_set_phase_align : integer := 512;
+  constant c_phase_align_duration : integer := 8192;
+
+
+  type t_align_state is (S_ALIGN_IDLE, S_ALIGN_PAUSE, S_ALIGN_WAIT, S_ALIGN_SET_PHASE, S_ALIGN_DONE);
+
+  signal counter : unsigned(13 downto 0);
+  signal state   : t_align_state;
+
+  
+begin  -- behavioral
+
+  p_align : process(gtp_tx_clk_i, gtp_rst_i)
+  begin
+    if rising_edge(gtp_tx_clk_i) then
+      if gtp_rst_i = '1' then
+        gtp_tx_en_pma_phase_align_o <= '0';
+        gtp_tx_pma_set_phase_o      <= '0';
+        counter                     <= (others => '0');
+        align_done_o                <= '0';
+        state                       <= S_ALIGN_IDLE;
+      else
+        if(align_en_i = '0') then
+          state <= S_ALIGN_IDLE;
+        else
+
+          case (state) is
+            when S_ALIGN_IDLE =>
+              gtp_tx_en_pma_phase_align_o <= '0';
+              gtp_tx_pma_set_phase_o      <= '0';
+              counter                     <= (others => '0');
+              align_done_o                <= '0';
+
+              if(align_en_i = '1') then
+                state <= S_ALIGN_PAUSE;
+              end if;
+
+            when S_ALIGN_PAUSE =>
+              counter <= counter + 1;
+              if(counter = to_unsigned(c_wait_en_phase_align, counter'length)) then
+                state <= S_ALIGN_WAIT;
+              end if;
+
+            when S_ALIGN_WAIT =>
+              gtp_tx_en_pma_phase_align_o <= '1';
+              counter                     <= counter + 1;
+              if(counter = to_unsigned(c_wait_en_phase_align + c_wait_set_phase_align, counter'length)) then
+                state <= S_ALIGN_SET_PHASE;
+              end if;
+
+            when S_ALIGN_SET_PHASE =>
+              counter                <= counter +1;
+              gtp_tx_pma_set_phase_o <= '1';
+
+              if(counter = to_unsigned(c_wait_en_phase_align + c_wait_set_phase_align + c_phase_align_duration, counter'length)) then
+                state <= S_ALIGN_DONE;
+              end if;
+
+            when S_ALIGN_DONE =>
+              gtp_tx_pma_set_phase_o <= '0';
+              counter                <= (others => '0');
+              align_done_o           <= '1';
+            when others => null;
+          end case;
+        end if;
+      end if;
+    end if;
+  end process;
+  
+
+end behavioral;
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/spartan6/whiterabbitgtp_wrapper_tile_spartan6.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/spartan6/whiterabbitgtp_wrapper_tile_spartan6.vhd
new file mode 100644
index 000000000..9a97d3d91
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/spartan6/whiterabbitgtp_wrapper_tile_spartan6.vhd
@@ -0,0 +1,712 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.all;
+
+--***************************** Entity Declaration ****************************
+
+entity WHITERABBITGTP_WRAPPER_TILE_SPARTAN6 is
+  generic
+    (
+      TILE_SIM_GTPRESET_SPEEDUP : integer := 0;  -- Set to 1 to speed up sim reset
+      TILE_CLK25_DIVIDER_0      : integer := 4;
+      TILE_CLK25_DIVIDER_1      : integer := 4;
+      TILE_PLL_DIVSEL_FB_0      : integer := 5;
+      TILE_PLL_DIVSEL_FB_1      : integer := 5;
+      TILE_PLL_DIVSEL_REF_0     : integer := 2;
+      TILE_PLL_DIVSEL_REF_1     : integer := 2;
+      TILE_PLL_SOURCE_0         : string  := "PLL0";
+      TILE_PLL_SOURCE_1         : string  := "PLL1"
+      );
+  port
+    (
+      ------------------------ Loopback and Powerdown Ports ----------------------
+      LOOPBACK0_IN         : in  std_logic_vector(2 downto 0);
+      LOOPBACK1_IN         : in  std_logic_vector(2 downto 0);
+      REFCLKOUT0_OUT           : out std_logic;
+      REFCLKOUT1_OUT           : out std_logic;
+      --------------------------------- PLL Ports --------------------------------
+      CLK00_IN             : in  std_logic;
+      CLK01_IN             : in  std_logic;
+      CLK10_IN             : in  std_logic;
+      CLK11_IN             : in  std_logic;
+      GTPRESET0_IN         : in  std_logic;
+      GTPRESET1_IN         : in  std_logic;
+      PLLLKDET0_OUT        : out std_logic;
+      PLLLKDET1_OUT        : out std_logic;
+      RESETDONE0_OUT       : out std_logic;
+      RESETDONE1_OUT       : out std_logic;
+      ----------------------- Receive Ports - 8b10b Decoder ----------------------
+      RXCHARISK0_OUT       : out std_logic;
+      RXCHARISK1_OUT       : out std_logic;
+      RXDISPERR0_OUT       : out std_logic;
+      RXDISPERR1_OUT       : out std_logic;
+      RXNOTINTABLE0_OUT    : out std_logic;
+      RXNOTINTABLE1_OUT    : out std_logic;
+      --------------- Receive Ports - Comma Detection and Alignment --------------
+      RXBYTEISALIGNED0_OUT : out std_logic;
+      RXBYTEISALIGNED1_OUT : out std_logic;
+      RXCOMMADET0_OUT      : out std_logic;
+      RXCOMMADET1_OUT      : out std_logic;
+      RXSLIDE0_IN          : in  std_logic;
+      RXSLIDE1_IN          : in  std_logic;
+      ------------------- Receive Ports - RX Data Path interface -----------------
+      RXDATA0_OUT          : out std_logic_vector(7 downto 0);
+      RXDATA1_OUT          : out std_logic_vector(7 downto 0);
+      RXUSRCLK0_IN         : in  std_logic;
+      RXUSRCLK1_IN         : in  std_logic;
+      RXUSRCLK20_IN        : in  std_logic;
+      RXUSRCLK21_IN        : in  std_logic;
+      ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
+      RXCDRRESET0_IN       : in  std_logic;
+      RXCDRRESET1_IN       : in  std_logic;
+      RXN0_IN              : in  std_logic;
+      RXN1_IN              : in  std_logic;
+      RXP0_IN              : in  std_logic;
+      RXP1_IN              : in  std_logic;
+      ---------------------------- TX/RX Datapath Ports --------------------------
+      GTPCLKFBEAST_OUT     : out std_logic_vector(1 downto 0);
+      GTPCLKFBWEST_OUT     : out std_logic_vector(1 downto 0);
+      GTPCLKOUT0_OUT       : out std_logic_vector(1 downto 0);
+      GTPCLKOUT1_OUT       : out std_logic_vector(1 downto 0);
+      ------------------- Transmit Ports - 8b10b Encoder Control -----------------
+      TXCHARISK0_IN        : in  std_logic;
+      TXCHARISK1_IN        : in  std_logic;
+
+      TXCHARDISPMODE0_IN: in std_logic;
+      TXCHARDISPMODE1_IN: in std_logic;
+
+      TXCHARDISPVAL0_IN: in std_logic;
+      TXCHARDISPVAL1_IN: in std_logic;
+
+      TXRUNDISP0_OUT       : out std_logic_vector(3 downto 0);
+      TXRUNDISP1_OUT       : out std_logic_vector(3 downto 0);
+
+      --------------- Transmit Ports - TX Buffer and Phase Alignment -------------
+      TXENPMAPHASEALIGN0_IN : in  std_logic;
+      TXENPMAPHASEALIGN1_IN : in  std_logic;
+      TXPMASETPHASE0_IN     : in  std_logic;
+      TXPMASETPHASE1_IN     : in  std_logic;
+      ------------------ Transmit Ports - TX Data Path interface -----------------
+      TXDATA0_IN            : in  std_logic_vector(7 downto 0);
+      TXDATA1_IN            : in  std_logic_vector(7 downto 0);
+      TXUSRCLK0_IN          : in  std_logic;
+      TXUSRCLK1_IN          : in  std_logic;
+      TXUSRCLK20_IN         : in  std_logic;
+      TXUSRCLK21_IN         : in  std_logic;
+      --------------- Transmit Ports - TX Driver and OOB signalling --------------
+      TXN0_OUT              : out std_logic;
+      TXN1_OUT              : out std_logic;
+      TXP0_OUT              : out std_logic;
+      TXP1_OUT              : out std_logic;
+      --------------- Transmit Ports - PRBS Generator ----------------------------
+      TXENPRBSTST0_IN       : in  std_logic_vector(2 downto 0);
+      TXENPRBSTST1_IN       : in  std_logic_vector(2 downto 0)
+
+      );
+
+
+end WHITERABBITGTP_WRAPPER_TILE_SPARTAN6;
+
+architecture RTL of WHITERABBITGTP_WRAPPER_TILE_SPARTAN6 is
+
+--**************************** Signal Declarations ****************************
+
+  -- ground and tied_to_vcc_i signals
+  signal tied_to_ground_i     : std_logic;
+  signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
+  signal tied_to_vcc_i        : std_logic;
+  signal tied_to_vcc_vec_i    : std_logic_vector(63 downto 0);
+
+
+
+  -- RX Datapath signals
+  signal rxdata0_i              : std_logic_vector(31 downto 0);
+  signal rxchariscomma0_float_i : std_logic_vector(2 downto 0);
+  signal rxcharisk0_float_i     : std_logic_vector(2 downto 0);
+  signal rxdisperr0_float_i     : std_logic_vector(2 downto 0);
+  signal rxnotintable0_float_i  : std_logic_vector(2 downto 0);
+  signal rxrundisp0_float_i     : std_logic_vector(2 downto 0);
+
+
+  -- TX Datapath signals
+  signal txdata0_i          : std_logic_vector(31 downto 0);
+  signal txkerr0_float_i    : std_logic_vector(2 downto 0);
+  signal txrundisp0_float_i : std_logic_vector(2 downto 0);
+
+
+  -- RX Datapath signals
+  signal rxdata1_i              : std_logic_vector(31 downto 0);
+  signal rxchariscomma1_float_i : std_logic_vector(2 downto 0);
+  signal rxcharisk1_float_i     : std_logic_vector(2 downto 0);
+  signal rxdisperr1_float_i     : std_logic_vector(2 downto 0);
+  signal rxnotintable1_float_i  : std_logic_vector(2 downto 0);
+  signal rxrundisp1_float_i     : std_logic_vector(2 downto 0);
+
+
+  -- TX Datapath signals
+  signal txdata1_i          : std_logic_vector(31 downto 0);
+  signal txkerr1_float_i    : std_logic_vector(2 downto 0);
+  signal txrundisp1_float_i : std_logic_vector(2 downto 0);
+
+--******************************** Main Body of Code***************************
+  
+begin
+
+  ---------------------------  Static signal Assignments ---------------------   
+
+  tied_to_ground_i                  <= '0';
+  tied_to_ground_vec_i(63 downto 0) <= (others => '0');
+  tied_to_vcc_i                     <= '1';
+  tied_to_vcc_vec_i(63 downto 0)    <= (others => '1');
+
+  -------------------  GTP Datapath byte mapping  -----------------    
+
+  RXDATA0_OUT <= rxdata0_i(7 downto 0);
+
+  txdata0_i <= (tied_to_ground_vec_i(23 downto 0) & TXDATA0_IN);
+
+  RXDATA1_OUT <= rxdata1_i(7 downto 0);
+
+  txdata1_i <= (tied_to_ground_vec_i(23 downto 0) & TXDATA1_IN);
+
+
+
+  ----------------------------- GTPA1_DUAL Instance  --------------------------   
+
+  gtpa1_dual_i : GTPA1_DUAL
+    generic map
+    (
+
+      --_______________________ Simulation-Only Attributes ___________________
+
+      SIM_RECEIVER_DETECT_PASS => (true),
+      SIM_TX_ELEC_IDLE_LEVEL   => ("X"),
+      SIM_VERSION              => ("2.0"),
+      SIM_REFCLK0_SOURCE       => ("000"),
+      SIM_REFCLK1_SOURCE       => ("000"),
+      SIM_GTPRESET_SPEEDUP     => (TILE_SIM_GTPRESET_SPEEDUP),
+      CLK25_DIVIDER_0          => (TILE_CLK25_DIVIDER_0),
+      CLK25_DIVIDER_1          => (TILE_CLK25_DIVIDER_1),
+      PLL_DIVSEL_FB_0          => (TILE_PLL_DIVSEL_FB_0),
+      PLL_DIVSEL_FB_1          => (TILE_PLL_DIVSEL_FB_1),
+      PLL_DIVSEL_REF_0         => (TILE_PLL_DIVSEL_REF_0),
+      PLL_DIVSEL_REF_1         => (TILE_PLL_DIVSEL_REF_1),
+
+
+      --PLL Attributes
+      CLKINDC_B_0        => (true),
+      CLKRCV_TRST_0      => (true),
+      OOB_CLK_DIVIDER_0  => (4),
+      PLL_COM_CFG_0      => (x"21680a"),
+      PLL_CP_CFG_0       => (x"00"),
+      PLL_RXDIVSEL_OUT_0 => (2),
+      PLL_SATA_0         => (false),
+      PLL_SOURCE_0       => (TILE_PLL_SOURCE_0),
+      PLL_TXDIVSEL_OUT_0 => (2),
+      PLLLKDET_CFG_0     => ("111"),
+
+      --
+      CLKINDC_B_1        => (true),
+      CLKRCV_TRST_1      => (true),
+      OOB_CLK_DIVIDER_1  => (4),
+      PLL_COM_CFG_1      => (x"21680a"),
+      PLL_CP_CFG_1       => (x"00"),
+      PLL_RXDIVSEL_OUT_1 => (2),
+      PLL_SATA_1         => (false),
+      PLL_SOURCE_1       => (TILE_PLL_SOURCE_1),
+      PLL_TXDIVSEL_OUT_1 => (2),
+      PLLLKDET_CFG_1     => ("111"),
+      PMA_COM_CFG_EAST   => (x"000008000"),
+      PMA_COM_CFG_WEST   => (x"000008000"),
+      TST_ATTR_0         => (x"00000000"),
+      TST_ATTR_1         => (x"00000000"),
+
+      --TX Interface Attributes
+      CLK_OUT_GTP_SEL_0 => ("REFCLKPLL0"),
+      TX_TDCC_CFG_0     => ("00"),
+      CLK_OUT_GTP_SEL_1 => ("REFCLKPLL1"),
+      TX_TDCC_CFG_1     => ("00"),
+
+      --TX Buffer and Phase Alignment Attributes
+      PMA_TX_CFG_0    => (x"80082"),
+      TX_BUFFER_USE_0 => (false),
+      TX_XCLK_SEL_0   => ("TXUSR"),
+      TXRX_INVERT_0   => ("111"),
+      PMA_TX_CFG_1    => (x"80082"),
+      TX_BUFFER_USE_1 => (false),
+      TX_XCLK_SEL_1   => ("TXUSR"),
+      TXRX_INVERT_1   => ("111"),
+
+      --TX Driver and OOB signalling Attributes
+      CM_TRIM_0       => ("00"),
+      TX_IDLE_DELAY_0 => ("011"),
+      CM_TRIM_1       => ("00"),
+      TX_IDLE_DELAY_1 => ("011"),
+
+      --TX PIPE/SATA Attributes
+      COM_BURST_VAL_0 => ("1111"),
+      COM_BURST_VAL_1 => ("1111"),
+
+      --RX Driver,OOB signalling,Coupling and Eq,CDR Attributes
+      AC_CAP_DIS_0          => (true),
+      OOBDETECT_THRESHOLD_0 => ("110"),
+      PMA_CDR_SCAN_0        => (x"6404040"),
+      PMA_RX_CFG_0          => (x"05ce048"),
+      PMA_RXSYNC_CFG_0      => (x"00"),
+      RCV_TERM_GND_0        => (false),
+      RCV_TERM_VTTRX_0      => (false),
+      RXEQ_CFG_0            => ("01111011"),
+      TERMINATION_CTRL_0    => ("10100"),
+      TERMINATION_OVRD_0    => (false),
+      TX_DETECT_RX_CFG_0    => (x"1832"),
+      AC_CAP_DIS_1          => (true),
+      OOBDETECT_THRESHOLD_1 => ("110"),
+      PMA_CDR_SCAN_1        => (x"6404040"),
+      PMA_RX_CFG_1          => (x"05ce048"),
+      PMA_RXSYNC_CFG_1      => (x"00"),
+      RCV_TERM_GND_1        => (false),
+      RCV_TERM_VTTRX_1      => (false),
+      RXEQ_CFG_1            => ("01111011"),
+      TERMINATION_CTRL_1    => ("10100"),
+      TERMINATION_OVRD_1    => (false),
+      TX_DETECT_RX_CFG_1    => (x"1832"),
+
+      --PRBS Detection Attributes
+      RXPRBSERR_LOOPBACK_0 => ('0'),
+      RXPRBSERR_LOOPBACK_1 => ('0'),
+
+      --Comma Detection and Alignment Attributes
+      ALIGN_COMMA_WORD_0     => (1),
+      COMMA_10B_ENABLE_0     => ("1111111111"),
+      DEC_MCOMMA_DETECT_0    => (false),
+      DEC_PCOMMA_DETECT_0    => (false),
+      DEC_VALID_COMMA_ONLY_0 => (true),
+      MCOMMA_10B_VALUE_0     => ("1010000011"),
+      MCOMMA_DETECT_0        => (true),
+      PCOMMA_10B_VALUE_0     => ("0101111100"),
+      PCOMMA_DETECT_0        => (true),
+      RX_SLIDE_MODE_0        => ("PCS"),
+      ALIGN_COMMA_WORD_1     => (1),
+      COMMA_10B_ENABLE_1     => ("1111111111"),
+      DEC_MCOMMA_DETECT_1    => (false),
+      DEC_PCOMMA_DETECT_1    => (false),
+      DEC_VALID_COMMA_ONLY_1 => (true),
+      MCOMMA_10B_VALUE_1     => ("1010000011"),
+      MCOMMA_DETECT_1        => (true),
+      PCOMMA_10B_VALUE_1     => ("0101111100"),
+      PCOMMA_DETECT_1        => (true),
+      RX_SLIDE_MODE_1        => ("PCS"),
+
+      --RX Loss-of-sync State Machine Attributes
+      RX_LOS_INVALID_INCR_0 => (8),
+      RX_LOS_THRESHOLD_0    => (128),
+      RX_LOSS_OF_SYNC_FSM_0 => (false),
+      RX_LOS_INVALID_INCR_1 => (8),
+      RX_LOS_THRESHOLD_1    => (128),
+      RX_LOSS_OF_SYNC_FSM_1 => (false),
+
+      --RX Elastic Buffer and Phase alignment Attributes
+      RX_BUFFER_USE_0        => (true),
+      RX_EN_IDLE_RESET_BUF_0 => (true),
+      RX_IDLE_HI_CNT_0       => ("1000"),
+      RX_IDLE_LO_CNT_0       => ("0000"),
+      RX_XCLK_SEL_0          => ("RXREC"),
+      RX_BUFFER_USE_1        => (true),
+      RX_EN_IDLE_RESET_BUF_1 => (true),
+      RX_IDLE_HI_CNT_1       => ("1000"),
+      RX_IDLE_LO_CNT_1       => ("0000"),
+      RX_XCLK_SEL_1          => ("RXREC"),
+
+      --Clock Correction Attributes
+      CLK_COR_ADJ_LEN_0          => (1),
+      CLK_COR_DET_LEN_0          => (1),
+      CLK_COR_INSERT_IDLE_FLAG_0 => (false),
+      CLK_COR_KEEP_IDLE_0        => (false),
+      CLK_COR_MAX_LAT_0          => (18),
+      CLK_COR_MIN_LAT_0          => (16),
+      CLK_COR_PRECEDENCE_0       => (true),
+      CLK_COR_REPEAT_WAIT_0      => (0),
+      CLK_COR_SEQ_1_1_0          => ("0100000000"),
+      CLK_COR_SEQ_1_2_0          => ("0000000000"),
+      CLK_COR_SEQ_1_3_0          => ("0000000000"),
+      CLK_COR_SEQ_1_4_0          => ("0000000000"),
+      CLK_COR_SEQ_1_ENABLE_0     => ("0000"),
+      CLK_COR_SEQ_2_1_0          => ("0100000000"),
+      CLK_COR_SEQ_2_2_0          => ("0000000000"),
+      CLK_COR_SEQ_2_3_0          => ("0000000000"),
+      CLK_COR_SEQ_2_4_0          => ("0000000000"),
+      CLK_COR_SEQ_2_ENABLE_0     => ("0000"),
+      CLK_COR_SEQ_2_USE_0        => (false),
+      CLK_CORRECT_USE_0          => (false),
+      RX_DECODE_SEQ_MATCH_0      => (true),
+      CLK_COR_ADJ_LEN_1          => (1),
+      CLK_COR_DET_LEN_1          => (1),
+      CLK_COR_INSERT_IDLE_FLAG_1 => (false),
+      CLK_COR_KEEP_IDLE_1        => (false),
+      CLK_COR_MAX_LAT_1          => (18),
+      CLK_COR_MIN_LAT_1          => (16),
+      CLK_COR_PRECEDENCE_1       => (true),
+      CLK_COR_REPEAT_WAIT_1      => (0),
+      CLK_COR_SEQ_1_1_1          => ("0100000000"),
+      CLK_COR_SEQ_1_2_1          => ("0000000000"),
+      CLK_COR_SEQ_1_3_1          => ("0000000000"),
+      CLK_COR_SEQ_1_4_1          => ("0000000000"),
+      CLK_COR_SEQ_1_ENABLE_1     => ("0000"),
+      CLK_COR_SEQ_2_1_1          => ("0100000000"),
+      CLK_COR_SEQ_2_2_1          => ("0000000000"),
+      CLK_COR_SEQ_2_3_1          => ("0000000000"),
+      CLK_COR_SEQ_2_4_1          => ("0000000000"),
+      CLK_COR_SEQ_2_ENABLE_1     => ("0000"),
+      CLK_COR_SEQ_2_USE_1        => (false),
+      CLK_CORRECT_USE_1          => (false),
+      RX_DECODE_SEQ_MATCH_1      => (true),
+
+      --Channel Bonding Attributes
+      CHAN_BOND_1_MAX_SKEW_0   => (1),
+      CHAN_BOND_2_MAX_SKEW_0   => (1),
+      CHAN_BOND_KEEP_ALIGN_0   => (false),
+      CHAN_BOND_SEQ_1_1_0      => ("0000000000"),
+      CHAN_BOND_SEQ_1_2_0      => ("0000000000"),
+      CHAN_BOND_SEQ_1_3_0      => ("0000000000"),
+      CHAN_BOND_SEQ_1_4_0      => ("0000000000"),
+      CHAN_BOND_SEQ_1_ENABLE_0 => ("0000"),
+      CHAN_BOND_SEQ_2_1_0      => ("0000000000"),
+      CHAN_BOND_SEQ_2_2_0      => ("0000000000"),
+      CHAN_BOND_SEQ_2_3_0      => ("0000000000"),
+      CHAN_BOND_SEQ_2_4_0      => ("0000000000"),
+      CHAN_BOND_SEQ_2_ENABLE_0 => ("0000"),
+      CHAN_BOND_SEQ_2_USE_0    => (false),
+      CHAN_BOND_SEQ_LEN_0      => (1),
+      RX_EN_MODE_RESET_BUF_0   => (true),
+      CHAN_BOND_1_MAX_SKEW_1   => (1),
+      CHAN_BOND_2_MAX_SKEW_1   => (1),
+      CHAN_BOND_KEEP_ALIGN_1   => (false),
+      CHAN_BOND_SEQ_1_1_1      => ("0000000000"),
+      CHAN_BOND_SEQ_1_2_1      => ("0000000000"),
+      CHAN_BOND_SEQ_1_3_1      => ("0000000000"),
+      CHAN_BOND_SEQ_1_4_1      => ("0000000000"),
+      CHAN_BOND_SEQ_1_ENABLE_1 => ("0000"),
+      CHAN_BOND_SEQ_2_1_1      => ("0000000000"),
+      CHAN_BOND_SEQ_2_2_1      => ("0000000000"),
+      CHAN_BOND_SEQ_2_3_1      => ("0000000000"),
+      CHAN_BOND_SEQ_2_4_1      => ("0000000000"),
+      CHAN_BOND_SEQ_2_ENABLE_1 => ("0000"),
+      CHAN_BOND_SEQ_2_USE_1    => (false),
+      CHAN_BOND_SEQ_LEN_1      => (1),
+      RX_EN_MODE_RESET_BUF_1   => (true),
+
+      --RX PCI Express Attributes
+      CB2_INH_CC_PERIOD_0   => (8),
+      CDR_PH_ADJ_TIME_0     => ("01010"),
+      PCI_EXPRESS_MODE_0    => (false),
+      RX_EN_IDLE_HOLD_CDR_0 => (false),
+      RX_EN_IDLE_RESET_FR_0 => (true),
+      RX_EN_IDLE_RESET_PH_0 => (true),
+      RX_STATUS_FMT_0       => ("PCIE"),
+      TRANS_TIME_FROM_P2_0  => (x"03c"),
+      TRANS_TIME_NON_P2_0   => (x"19"),
+      TRANS_TIME_TO_P2_0    => (x"064"),
+      CB2_INH_CC_PERIOD_1   => (8),
+      CDR_PH_ADJ_TIME_1     => ("01010"),
+      PCI_EXPRESS_MODE_1    => (false),
+      RX_EN_IDLE_HOLD_CDR_1 => (false),
+      RX_EN_IDLE_RESET_FR_1 => (true),
+      RX_EN_IDLE_RESET_PH_1 => (true),
+      RX_STATUS_FMT_1       => ("PCIE"),
+      TRANS_TIME_FROM_P2_1  => (x"03c"),
+      TRANS_TIME_NON_P2_1   => (x"19"),
+      TRANS_TIME_TO_P2_1    => (x"064"),
+
+      --RX SATA Attributes
+      SATA_BURST_VAL_0 => ("100"),
+      SATA_IDLE_VAL_0  => ("100"),
+      SATA_MAX_BURST_0 => (9),
+      SATA_MAX_INIT_0  => (27),
+      SATA_MAX_WAKE_0  => (9),
+      SATA_MIN_BURST_0 => (5),
+      SATA_MIN_INIT_0  => (15),
+      SATA_MIN_WAKE_0  => (5),
+      SATA_BURST_VAL_1 => ("100"),
+      SATA_IDLE_VAL_1  => ("100"),
+      SATA_MAX_BURST_1 => (9),
+      SATA_MAX_INIT_1  => (27),
+      SATA_MAX_WAKE_1  => (9),
+      SATA_MIN_BURST_1 => (5),
+      SATA_MIN_INIT_1  => (15),
+      SATA_MIN_WAKE_1  => (5)
+
+
+      ) 
+    port map
+    (
+      ------------------------ Loopback and Powerdown Ports ----------------------
+      LOOPBACK0                 => LOOPBACK0_IN,
+      LOOPBACK1                 => LOOPBACK1_IN,
+      RXPOWERDOWN0              => tied_to_ground_vec_i(1 downto 0),
+      RXPOWERDOWN1              => tied_to_ground_vec_i(1 downto 0),
+      TXPOWERDOWN0              => tied_to_ground_vec_i(1 downto 0),
+      TXPOWERDOWN1              => tied_to_ground_vec_i(1 downto 0),
+      --------------------------------- PLL Ports --------------------------------
+      CLK00                     => CLK00_IN,
+      CLK01                     => CLK01_IN,
+      CLK10                     => CLK10_IN,
+      CLK11                     => CLK11_IN,
+      CLKINEAST0                => tied_to_ground_i,
+      CLKINEAST1                => tied_to_ground_i,
+      CLKINWEST0                => tied_to_ground_i,
+      CLKINWEST1                => tied_to_ground_i,
+      GCLK00                    => tied_to_ground_i,
+      GCLK01                    => tied_to_ground_i,
+      GCLK10                    => tied_to_ground_i,
+      GCLK11                    => tied_to_ground_i,
+      GTPRESET0                 => GTPRESET0_IN,
+      GTPRESET1                 => GTPRESET1_IN,
+      GTPTEST0                  => "00010000",
+      GTPTEST1                  => "00010000",
+      INTDATAWIDTH0             => tied_to_vcc_i,
+      INTDATAWIDTH1             => tied_to_vcc_i,
+      PLLCLK00                  => tied_to_ground_i,
+      PLLCLK01                  => tied_to_ground_i,
+      PLLCLK10                  => tied_to_ground_i,
+      PLLCLK11                  => tied_to_ground_i,
+      PLLLKDET0                 => PLLLKDET0_OUT,
+      PLLLKDET1                 => PLLLKDET1_OUT,
+      PLLLKDETEN0               => tied_to_vcc_i,
+      PLLLKDETEN1               => tied_to_vcc_i,
+      PLLPOWERDOWN0             => tied_to_ground_i,
+      PLLPOWERDOWN1             => tied_to_ground_i,
+      REFCLKOUT0                => REFCLKOUT0_OUT,
+      REFCLKOUT1                => REFCLKOUT1_OUT,
+      REFCLKPLL0                => open,
+      REFCLKPLL1                => open,
+      REFCLKPWRDNB0             => tied_to_vcc_i,
+      REFCLKPWRDNB1             => tied_to_vcc_i,
+      REFSELDYPLL0              => tied_to_ground_vec_i(2 downto 0),
+      REFSELDYPLL1              => tied_to_ground_vec_i(2 downto 0),
+      RESETDONE0                => RESETDONE0_OUT,
+      RESETDONE1                => RESETDONE1_OUT,
+      TSTCLK0                   => tied_to_ground_i,
+      TSTCLK1                   => tied_to_ground_i,
+      TSTIN0                    => tied_to_ground_vec_i(11 downto 0),
+      TSTIN1                    => tied_to_ground_vec_i(11 downto 0),
+      TSTOUT0                   => open,
+      TSTOUT1                   => open,
+      ----------------------- Receive Ports - 8b10b Decoder ----------------------
+      RXCHARISCOMMA0            => open,
+      RXCHARISCOMMA1            => open,
+      RXCHARISK0(3 downto 1)    => rxcharisk0_float_i,
+      RXCHARISK0(0)             => RXCHARISK0_OUT,
+      RXCHARISK1(3 downto 1)    => rxcharisk1_float_i,
+      RXCHARISK1(0)             => RXCHARISK1_OUT,
+      RXDEC8B10BUSE0            => tied_to_vcc_i,
+      RXDEC8B10BUSE1            => tied_to_vcc_i,
+      RXDISPERR0(3 downto 1)    => rxdisperr0_float_i,
+      RXDISPERR0(0)             => RXDISPERR0_OUT,
+      RXDISPERR1(3 downto 1)    => rxdisperr1_float_i,
+      RXDISPERR1(0)             => RXDISPERR1_OUT,
+      RXNOTINTABLE0(3 downto 1) => rxnotintable0_float_i,
+      RXNOTINTABLE0(0)          => RXNOTINTABLE0_OUT,
+      RXNOTINTABLE1(3 downto 1) => rxnotintable1_float_i,
+      RXNOTINTABLE1(0)          => RXNOTINTABLE1_OUT,
+      RXRUNDISP0                => open,
+      RXRUNDISP1                => open,
+      USRCODEERR0               => tied_to_ground_i,
+      USRCODEERR1               => tied_to_ground_i,
+      ---------------------- Receive Ports - Channel Bonding ---------------------
+      RXCHANBONDSEQ0            => open,
+      RXCHANBONDSEQ1            => open,
+      RXCHANISALIGNED0          => open,
+      RXCHANISALIGNED1          => open,
+      RXCHANREALIGN0            => open,
+      RXCHANREALIGN1            => open,
+      RXCHBONDI                 => tied_to_ground_vec_i(2 downto 0),
+      RXCHBONDMASTER0           => tied_to_ground_i,
+      RXCHBONDMASTER1           => tied_to_ground_i,
+      RXCHBONDO                 => open,
+      RXCHBONDSLAVE0            => tied_to_ground_i,
+      RXCHBONDSLAVE1            => tied_to_ground_i,
+      RXENCHANSYNC0             => tied_to_ground_i,
+      RXENCHANSYNC1             => tied_to_ground_i,
+      ---------------------- Receive Ports - Clock Correction --------------------
+      RXCLKCORCNT0              => open,
+      RXCLKCORCNT1              => open,
+      --------------- Receive Ports - Comma Detection and Alignment --------------
+      RXBYTEISALIGNED0          => RXBYTEISALIGNED0_OUT,
+      RXBYTEISALIGNED1          => RXBYTEISALIGNED1_OUT,
+      RXBYTEREALIGN0            => open,
+      RXBYTEREALIGN1            => open,
+      RXCOMMADET0               => RXCOMMADET0_OUT,
+      RXCOMMADET1               => RXCOMMADET1_OUT,
+      RXCOMMADETUSE0            => tied_to_vcc_i,
+      RXCOMMADETUSE1            => tied_to_vcc_i,
+      RXENMCOMMAALIGN0          => tied_to_ground_i,
+      RXENMCOMMAALIGN1          => tied_to_ground_i,
+      RXENPCOMMAALIGN0          => tied_to_ground_i,
+      RXENPCOMMAALIGN1          => tied_to_ground_i,
+      RXSLIDE0                  => RXSLIDE0_IN,
+      RXSLIDE1                  => RXSLIDE1_IN,
+      ----------------------- Receive Ports - PRBS Detection ---------------------
+      PRBSCNTRESET0             => tied_to_ground_i,
+      PRBSCNTRESET1             => tied_to_ground_i,
+      RXENPRBSTST0              => tied_to_ground_vec_i(2 downto 0),
+      RXENPRBSTST1              => tied_to_ground_vec_i(2 downto 0),
+      RXPRBSERR0                => open,
+      RXPRBSERR1                => open,
+      ------------------- Receive Ports - RX Data Path interface -----------------
+      RXDATA0                   => rxdata0_i,
+      RXDATA1                   => rxdata1_i,
+      RXDATAWIDTH0              => "00",
+      RXDATAWIDTH1              => "00",
+      RXRECCLK0                 => open,
+      RXRECCLK1                 => open,
+      RXRESET0                  => tied_to_ground_i,
+      RXRESET1                  => tied_to_ground_i,
+      RXUSRCLK0                 => RXUSRCLK0_IN,
+      RXUSRCLK1                 => RXUSRCLK1_IN,
+      RXUSRCLK20                => RXUSRCLK20_IN,
+      RXUSRCLK21                => RXUSRCLK21_IN,
+      ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
+      GATERXELECIDLE0           => tied_to_ground_i,
+      GATERXELECIDLE1           => tied_to_ground_i,
+      IGNORESIGDET0             => tied_to_ground_i,
+      IGNORESIGDET1             => tied_to_ground_i,
+      RCALINEAST                => tied_to_ground_vec_i(4 downto 0),
+      RCALINWEST                => tied_to_ground_vec_i(4 downto 0),
+      RCALOUTEAST               => open,
+      RCALOUTWEST               => open,
+      RXCDRRESET0               => RXCDRRESET0_IN,
+      RXCDRRESET1               => RXCDRRESET1_IN,
+      RXELECIDLE0               => open,
+      RXELECIDLE1               => open,
+      RXEQMIX0                  => "00",
+      RXEQMIX1                  => "00",
+      RXN0                      => RXN0_IN,
+      RXN1                      => RXN1_IN,
+      RXP0                      => RXP0_IN,
+      RXP1                      => RXP1_IN,
+      ----------- Receive Ports - RX Elastic Buffer and Phase Alignment ----------
+      RXBUFRESET0               => tied_to_ground_i,
+      RXBUFRESET1               => tied_to_ground_i,
+      RXBUFSTATUS0              => open,
+      RXBUFSTATUS1              => open,
+      RXENPMAPHASEALIGN0        => tied_to_ground_i,
+      RXENPMAPHASEALIGN1        => tied_to_ground_i,
+      RXPMASETPHASE0            => tied_to_ground_i,
+      RXPMASETPHASE1            => tied_to_ground_i,
+      RXSTATUS0                 => open,
+      RXSTATUS1                 => open,
+      --------------- Receive Ports - RX Loss-of-sync State Machine --------------
+      RXLOSSOFSYNC0             => open,
+      RXLOSSOFSYNC1             => open,
+      -------------- Receive Ports - RX Pipe Control for PCI Express -------------
+      PHYSTATUS0                => open,
+      PHYSTATUS1                => open,
+      RXVALID0                  => open,
+      RXVALID1                  => open,
+      -------------------- Receive Ports - RX Polarity Control -------------------
+      RXPOLARITY0               => tied_to_ground_i,
+      RXPOLARITY1               => tied_to_ground_i,
+      ------------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------
+      DADDR                     => tied_to_ground_vec_i(7 downto 0),
+      DCLK                      => tied_to_ground_i,
+      DEN                       => tied_to_ground_i,
+      DI                        => tied_to_ground_vec_i(15 downto 0),
+      DRDY                      => open,
+      DRPDO                     => open,
+      DWE                       => tied_to_ground_i,
+      ---------------------------- TX/RX Datapath Ports --------------------------
+      GTPCLKFBEAST              => GTPCLKFBEAST_OUT,
+      GTPCLKFBSEL0EAST          => "10",
+      GTPCLKFBSEL0WEST          => "00",
+      GTPCLKFBSEL1EAST          => "11",
+      GTPCLKFBSEL1WEST          => "01",
+      GTPCLKFBWEST              => GTPCLKFBWEST_OUT,
+      GTPCLKOUT0                => GTPCLKOUT0_OUT,
+      GTPCLKOUT1                => GTPCLKOUT1_OUT,
+      ------------------- Transmit Ports - 8b10b Encoder Control -----------------
+      TXBYPASS8B10B0            => tied_to_ground_vec_i(3 downto 0),
+      TXBYPASS8B10B1            => tied_to_ground_vec_i(3 downto 0),
+
+      TXCHARDISPMODE0(0)           => TXCHARDISPMODE0_IN,
+      TXCHARDISPMODE0(3 downto 1) => tied_to_ground_vec_i(2 downto 0),
+
+      TXCHARDISPMODE1(0)           => TXCHARDISPMODE1_IN,
+      TXCHARDISPMODE1(3 downto 1) => tied_to_ground_vec_i(2 downto 0),
+
+      TXCHARDISPVAL0(0)           => TXCHARDISPVAL0_IN,
+      TXCHARDISPVAL0(3 downto 1) => tied_to_ground_vec_i(2 downto 0),
+
+      TXCHARDISPVAL1(0)           => TXCHARDISPVAL1_IN,
+      TXCHARDISPVAL1(3 downto 1) => tied_to_ground_vec_i(2 downto 0),
+      
+      TXCHARISK0(3 downto 1)    => tied_to_ground_vec_i(2 downto 0),
+      TXCHARISK0(0)             => TXCHARISK0_IN,
+      TXCHARISK1(3 downto 1)    => tied_to_ground_vec_i(2 downto 0),
+      TXCHARISK1(0)             => TXCHARISK1_IN,
+      TXENC8B10BUSE0            => tied_to_vcc_i,
+      TXENC8B10BUSE1            => tied_to_vcc_i,
+      TXKERR0                   => open,
+      TXKERR1                   => open,
+      TXRUNDISP0                => TXRUNDISP0_OUT,
+      TXRUNDISP1                => TXRUNDISP1_OUT,
+      --------------- Transmit Ports - TX Buffer and Phase Alignment -------------
+      TXBUFSTATUS0              => open,
+      TXBUFSTATUS1              => open,
+      TXENPMAPHASEALIGN0        => TXENPMAPHASEALIGN0_IN,
+      TXENPMAPHASEALIGN1        => TXENPMAPHASEALIGN1_IN,
+      TXPMASETPHASE0            => TXPMASETPHASE0_IN,
+      TXPMASETPHASE1            => TXPMASETPHASE1_IN,
+      ------------------ Transmit Ports - TX Data Path interface -----------------
+      TXDATA0                   => txdata0_i,
+      TXDATA1                   => txdata1_i,
+      TXDATAWIDTH0              => "00",
+      TXDATAWIDTH1              => "00",
+      TXOUTCLK0                 => open,
+      TXOUTCLK1                 => open,
+      TXRESET0                  => tied_to_ground_i,
+      TXRESET1                  => tied_to_ground_i,
+      TXUSRCLK0                 => TXUSRCLK0_IN,
+      TXUSRCLK1                 => TXUSRCLK1_IN,
+      TXUSRCLK20                => TXUSRCLK20_IN,
+      TXUSRCLK21                => TXUSRCLK21_IN,
+      --------------- Transmit Ports - TX Driver and OOB signalling --------------
+      TXBUFDIFFCTRL0            => "101",
+      TXBUFDIFFCTRL1            => "101",
+      TXDIFFCTRL0               => "0110",
+      TXDIFFCTRL1               => "0110",
+      TXINHIBIT0                => tied_to_ground_i,
+      TXINHIBIT1                => tied_to_ground_i,
+      TXN0                      => TXN0_OUT,
+      TXN1                      => TXN1_OUT,
+      TXP0                      => TXP0_OUT,
+      TXP1                      => TXP1_OUT,
+      TXPREEMPHASIS0            => "000",
+      TXPREEMPHASIS1            => "000",
+      --------------------- Transmit Ports - TX PRBS Generator -------------------
+      TXENPRBSTST0              => TXENPRBSTST0_IN,
+      TXENPRBSTST1              => TXENPRBSTST1_IN,
+      TXPRBSFORCEERR0           => tied_to_ground_i,
+      TXPRBSFORCEERR1           => tied_to_ground_i,
+      -------------------- Transmit Ports - TX Polarity Control ------------------
+      TXPOLARITY0               => tied_to_ground_i,
+      TXPOLARITY1               => tied_to_ground_i,
+      ----------------- Transmit Ports - TX Ports for PCI Express ----------------
+      TXDETECTRX0               => tied_to_ground_i,
+      TXDETECTRX1               => tied_to_ground_i,
+      TXELECIDLE0               => tied_to_ground_i,
+      TXELECIDLE1               => tied_to_ground_i,
+      TXPDOWNASYNCH0            => tied_to_ground_i,
+      TXPDOWNASYNCH1            => tied_to_ground_i,
+      --------------------- Transmit Ports - TX Ports for SATA -------------------
+      TXCOMSTART0               => tied_to_ground_i,
+      TXCOMSTART1               => tied_to_ground_i,
+      TXCOMTYPE0                => tied_to_ground_i,
+      TXCOMTYPE1                => tied_to_ground_i
+
+      );
+
+end RTL;
+
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/spartan6/wr_gtp_phy_spartan6.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/spartan6/wr_gtp_phy_spartan6.vhd
new file mode 100644
index 000000000..ca7480834
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/spartan6/wr_gtp_phy_spartan6.vhd
@@ -0,0 +1,816 @@
+-------------------------------------------------------------------------------
+-- Title      : Deterministic Xilinx GTP wrapper - Spartan-6 top module
+-- Project    : White Rabbit Switch
+-------------------------------------------------------------------------------
+-- File       : wr_gtp_phy_spartan6.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2010-11-18
+-- Last update: 2017-05-24
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Dual channel wrapper for Xilinx Spartan-6 GTP adapted for
+-- deterministic delays at 1.25 Gbps.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2010 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-- 
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author    Description
+-- 2010-11-18  0.4      twlostow  Initial release
+-- 2011-02-07  0.5      twlostow  Verified on Spartan6 GTP (single channel only)
+-- 2011-05-15  0.6      twlostow  Added reference clock output
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+library work;
+use work.gencores_pkg.all;
+use work.disparity_gen_pkg.all;
+
+entity wr_gtp_phy_spartan6 is
+
+  generic (
+    -- set to non-zero value to speed up the simulation by reducing some delays
+    g_simulation      : integer := 1;
+    g_force_disparity : integer := 0;
+    g_enable_ch0      : integer := 1;
+    g_enable_ch1      : integer := 1
+    );
+
+  port (
+    -- Port 0
+
+    -- dedicated GTP clock input
+    gtp_clk_i : in std_logic;
+
+    -- TX path, synchronous to ch0_ref_clk_i
+    ch0_ref_clk_i : in std_logic;
+
+    -- data input (8 bits, not 8b10b-encoded)
+    ch0_tx_data_i : in std_logic_vector(7 downto 0);
+
+    -- 1 when tx_data_i contains a control code, 0 when it's a data byte
+    ch0_tx_k_i : in std_logic;
+
+    -- disparity of the currently transmitted 8b10b code (1 = plus, 0 = minus).
+    -- Necessary for the PCS to generate proper frame termination sequences.
+    ch0_tx_disparity_o : out std_logic;
+
+    -- Encoding error indication (1 = error, 0 = no error)
+    ch0_tx_enc_err_o : out std_logic;
+
+    -- RX path, synchronous to ch0_rx_rbclk_o.
+
+    -- RX recovered clock
+    ch0_rx_rbclk_o : out std_logic;
+
+    -- 8b10b-decoded data output. The data output must be kept invalid before
+    -- the transceiver is locked on the incoming signal to prevent the EP from
+    -- detecting a false carrier.
+    ch0_rx_data_o : out std_logic_vector(7 downto 0);
+
+    -- 1 when the byte on rx_data_o is a control code
+    ch0_rx_k_o : out std_logic;
+
+    -- encoding error indication
+    ch0_rx_enc_err_o : out std_logic;
+
+    -- RX bitslide indication, indicating the delay of the RX path of the
+    -- transceiver (in UIs). Must be valid when ch0_rx_data_o is valid.
+    ch0_rx_bitslide_o : out std_logic_vector(3 downto 0);
+
+    -- reset input, active hi
+    ch0_rst_i : in std_logic;
+
+    -- local loopback enable (Tx->Rx), active hi
+    ch0_loopen_i : in std_logic;
+    ch0_loopen_vec_i : in std_logic_vector(2 downto 0) := (others=>'0');
+
+    -- PRBS select (see Xilinx UG386 Table 3-15; "000" = Standard operation, pattern generator off)
+    ch0_tx_prbs_sel_i  : in std_logic_vector(2 downto 0) := (others=>'0');
+
+    -- gtp0 ready: locked & aligned
+    ch0_rdy_o : out std_logic;
+
+-- Port 1
+    ch1_ref_clk_i : in std_logic;
+
+    ch1_tx_data_i      : in  std_logic_vector(7 downto 0) := "00000000";
+    ch1_tx_k_i         : in  std_logic                    := '0';
+    ch1_tx_disparity_o : out std_logic;
+    ch1_tx_enc_err_o   : out std_logic;
+
+    ch1_rx_data_o     : out std_logic_vector(7 downto 0);
+    ch1_rx_rbclk_o    : out std_logic;
+    ch1_rx_k_o        : out std_logic;
+    ch1_rx_enc_err_o  : out std_logic;
+    ch1_rx_bitslide_o : out std_logic_vector(3 downto 0);
+
+    ch1_rst_i    : in std_logic := '0';
+    ch1_loopen_i : in std_logic := '0';
+    ch1_loopen_vec_i : in std_logic_vector(2 downto 0) := (others=>'0');
+    ch1_tx_prbs_sel_i: in std_logic_vector(2 downto 0) := (others=>'0');
+    ch1_rdy_o    : out std_logic;
+
+-- Serial I/O
+
+    pad_txn0_o : out std_logic;
+    pad_txp0_o : out std_logic;
+
+    pad_rxn0_i : in std_logic := '0';
+    pad_rxp0_i : in std_logic := '0';
+
+    pad_txn1_o : out std_logic;
+    pad_txp1_o : out std_logic;
+
+    pad_rxn1_i : in std_logic := '0';
+    pad_rxp1_i : in std_logic := '0'
+    );
+
+
+end wr_gtp_phy_spartan6;
+
+architecture rtl of wr_gtp_phy_spartan6 is
+
+  component WHITERABBITGTP_WRAPPER_TILE_SPARTAN6
+    generic (
+      TILE_SIM_GTPRESET_SPEEDUP : integer;
+      TILE_CLK25_DIVIDER_0      : integer;
+      TILE_CLK25_DIVIDER_1      : integer;
+      TILE_PLL_DIVSEL_FB_0      : integer;
+      TILE_PLL_DIVSEL_FB_1      : integer;
+      TILE_PLL_DIVSEL_REF_0     : integer;
+      TILE_PLL_DIVSEL_REF_1     : integer;
+      TILE_PLL_SOURCE_0         : string;
+      TILE_PLL_SOURCE_1         : string);
+    port (
+      LOOPBACK0_IN          : in  std_logic_vector(2 downto 0);
+      LOOPBACK1_IN          : in  std_logic_vector(2 downto 0);
+      REFCLKOUT0_OUT        : out std_logic;
+      REFCLKOUT1_OUT        : out std_logic;
+      CLK00_IN              : in  std_logic;
+      CLK01_IN              : in  std_logic;
+      CLK10_IN              : in  std_logic;
+      CLK11_IN              : in  std_logic;
+      GTPRESET0_IN          : in  std_logic;
+      GTPRESET1_IN          : in  std_logic;
+      PLLLKDET0_OUT         : out std_logic;
+      PLLLKDET1_OUT         : out std_logic;
+      RESETDONE0_OUT        : out std_logic;
+      RESETDONE1_OUT        : out std_logic;
+      RXCHARISK0_OUT        : out std_logic;
+      RXCHARISK1_OUT        : out std_logic;
+      RXDISPERR0_OUT        : out std_logic;
+      RXDISPERR1_OUT        : out std_logic;
+      RXNOTINTABLE0_OUT     : out std_logic;
+      RXNOTINTABLE1_OUT     : out std_logic;
+      RXBYTEISALIGNED0_OUT  : out std_logic;
+      RXBYTEISALIGNED1_OUT  : out std_logic;
+      RXCOMMADET0_OUT       : out std_logic;
+      RXCOMMADET1_OUT       : out std_logic;
+      RXSLIDE0_IN           : in  std_logic;
+      RXSLIDE1_IN           : in  std_logic;
+      RXDATA0_OUT           : out std_logic_vector(7 downto 0);
+      RXDATA1_OUT           : out std_logic_vector(7 downto 0);
+      RXUSRCLK0_IN          : in  std_logic;
+      RXUSRCLK1_IN          : in  std_logic;
+      RXUSRCLK20_IN         : in  std_logic;
+      RXUSRCLK21_IN         : in  std_logic;
+      RXCDRRESET0_IN        : in  std_logic;
+      RXCDRRESET1_IN        : in  std_logic;
+      RXN0_IN               : in  std_logic;
+      RXN1_IN               : in  std_logic;
+      RXP0_IN               : in  std_logic;
+      RXP1_IN               : in  std_logic;
+      GTPCLKFBEAST_OUT      : out std_logic_vector(1 downto 0);
+      GTPCLKFBWEST_OUT      : out std_logic_vector(1 downto 0);
+      GTPCLKOUT0_OUT        : out std_logic_vector(1 downto 0);
+      GTPCLKOUT1_OUT        : out std_logic_vector(1 downto 0);
+      TXCHARISK0_IN         : in  std_logic;
+      TXCHARISK1_IN         : in  std_logic;
+      TXCHARDISPMODE0_IN    : in  std_logic;
+      TXCHARDISPMODE1_IN    : in  std_logic;
+      TXCHARDISPVAL0_IN     : in  std_logic;
+      TXCHARDISPVAL1_IN     : in  std_logic;
+      TXRUNDISP0_OUT        : out std_logic_vector(3 downto 0);
+      TXRUNDISP1_OUT        : out std_logic_vector(3 downto 0);
+      TXENPMAPHASEALIGN0_IN : in  std_logic;
+      TXENPMAPHASEALIGN1_IN : in  std_logic;
+      TXPMASETPHASE0_IN     : in  std_logic;
+      TXPMASETPHASE1_IN     : in  std_logic;
+      TXDATA0_IN            : in  std_logic_vector(7 downto 0);
+      TXDATA1_IN            : in  std_logic_vector(7 downto 0);
+      TXUSRCLK0_IN          : in  std_logic;
+      TXUSRCLK1_IN          : in  std_logic;
+      TXUSRCLK20_IN         : in  std_logic;
+      TXUSRCLK21_IN         : in  std_logic;
+      TXN0_OUT              : out std_logic;
+      TXN1_OUT              : out std_logic;
+      TXP0_OUT              : out std_logic;
+      TXP1_OUT              : out std_logic;
+      TXENPRBSTST0_IN       : in  std_logic_vector(2 downto 0);
+      TXENPRBSTST1_IN       : in  std_logic_vector(2 downto 0));
+  end component;
+
+  component gtp_phase_align
+    generic(
+      g_simulation : integer);
+    port (
+      gtp_rst_i                   : in  std_logic;
+      gtp_tx_clk_i                : in  std_logic;
+      gtp_tx_en_pma_phase_align_o : out std_logic;
+      gtp_tx_pma_set_phase_o      : out std_logic;
+      align_en_i                  : in  std_logic;
+      align_done_o                : out std_logic);
+  end component;
+
+  component gtp_bitslide
+    generic(
+      g_simulation : integer;
+      g_target     : string := "spartan6");
+    port (
+      gtp_rst_i                : in  std_logic;
+      gtp_rx_clk_i             : in  std_logic;
+      gtp_rx_comma_det_i       : in  std_logic;
+      gtp_rx_byte_is_aligned_i : in  std_logic;
+      serdes_ready_i           : in  std_logic;
+      gtp_rx_slide_o           : out std_logic;
+      gtp_rx_cdr_rst_o         : out std_logic;
+      bitslide_o               : out std_logic_vector(4 downto 0);
+      synced_o                 : out std_logic);
+  end component;
+
+  signal ch0_gtp_reset        : std_logic;
+  signal ch0_gtp_loopback     : std_logic_vector(2 downto 0) := "000";
+  signal ch0_gtp_reset_done   : std_logic;
+  signal ch0_gtp_pll_lockdet  : std_logic;
+  signal ch0_tx_pma_set_phase : std_logic                    := '0';
+
+  signal ch0_tx_rundisp_vec : std_logic_vector(3 downto 0);
+
+  signal ch0_tx_en_pma_phase_align : std_logic := '0';
+
+  signal ch0_rx_data_int                : std_logic_vector(7 downto 0);
+  signal ch0_rx_k_int                   : std_logic;
+  signal ch0_rx_disperr, ch0_rx_invcode : std_logic;
+
+  signal ch0_rx_byte_is_aligned : std_logic;
+  signal ch0_rx_comma_det       : std_logic;
+  signal ch0_rx_cdr_rst         : std_logic := '0';
+  signal ch0_rx_rec_clk_pad     : std_logic;
+  signal ch0_rx_rec_clk         : std_logic;
+  signal ch0_rx_data            : std_logic_vector(7 downto 0);
+  signal ch0_rx_k               : std_logic;
+  signal ch0_rx_enc_err         : std_logic;
+  signal ch0_rx_divclk          : std_logic;
+  signal ch0_rx_slide           : std_logic := '0';
+
+  signal ch0_gtp_locked : std_logic;
+  signal ch0_align_done : std_logic;
+  signal ch0_rx_synced  : std_logic;
+
+  signal ch0_gtp_clkout_int                                : std_logic_vector(1 downto 0);
+  signal ch0_rx_enable_output, ch0_rx_enable_output_synced : std_logic;
+
+
+  signal ch1_gtp_reset        : std_logic;
+  signal ch1_gtp_loopback     : std_logic_vector(2 downto 0) := "000";
+  signal ch1_gtp_reset_done   : std_logic;
+  signal ch1_gtp_pll_lockdet  : std_logic;
+  signal ch1_tx_pma_set_phase : std_logic                    := '0';
+
+  signal ch1_tx_rundisp_vec : std_logic_vector(3 downto 0);
+
+  signal ch1_tx_en_pma_phase_align : std_logic := '0';
+
+  signal ch1_rx_data_int                : std_logic_vector(7 downto 0);
+  signal ch1_rx_k_int                   : std_logic;
+  signal ch1_rx_disperr, ch1_rx_invcode : std_logic;
+
+  signal ch1_rx_byte_is_aligned : std_logic;
+  signal ch1_rx_comma_det       : std_logic;
+  signal ch1_rx_cdr_rst         : std_logic := '0';
+  signal ch1_rx_rec_clk_pad     : std_logic;
+  signal ch1_rx_rec_clk         : std_logic;
+  signal ch1_rx_data            : std_logic_vector(7 downto 0);
+  signal ch1_rx_k               : std_logic;
+  signal ch1_rx_enc_err         : std_logic;
+  
+  signal ch1_rx_divclk          : std_logic;
+  signal ch1_rx_slide           : std_logic := '0';
+
+  signal ch1_gtp_locked : std_logic;
+  signal ch1_align_done : std_logic;
+  signal ch1_rx_synced  : std_logic;
+
+  signal ch1_gtp_clkout_int                                : std_logic_vector(1 downto 0);
+  signal ch1_rx_enable_output, ch1_rx_enable_output_synced : std_logic;
+
+  signal ch0_rst_synced    : std_logic;
+  signal ch0_rst_d0        : std_logic;
+  signal ch0_reset_counter : unsigned(9 downto 0);
+
+  signal ch1_rst_synced    : std_logic;
+  signal ch1_rst_d0        : std_logic;
+  signal ch1_reset_counter : unsigned(9 downto 0);
+
+  signal ch0_rx_bitslide_int : std_logic_vector(4 downto 0);
+  signal ch1_rx_bitslide_int : std_logic_vector(4 downto 0);
+
+  signal ch0_ref_clk_in : std_logic_vector(1 downto 0);
+  signal ch1_ref_clk_in : std_logic_vector(1 downto 0);
+
+
+  signal ch0_disparity_set : std_logic;
+  signal ch1_disparity_set : std_logic;
+
+  signal ch0_tx_chardispmode : std_logic;
+  signal ch1_tx_chardispmode : std_logic;
+
+  signal ch0_tx_chardispval : std_logic;
+  signal ch1_tx_chardispval : std_logic;
+
+
+
+  component enc_8b10b
+    port (
+      clk_i     : in  std_logic;
+      rst_n_i   : in  std_logic;
+      ctrl_i    : in  std_logic;
+      in_8b_i   : in  std_logic_vector(7 downto 0);
+      err_o     : out std_logic;
+      dispar_o  : out std_logic;
+      out_10b_o : out std_logic_vector(9 downto 0));
+  end component;
+
+  signal ch0_rst_n : std_logic;
+  signal ch1_rst_n : std_logic;
+
+  signal ch0_cur_disp  : t_8b10b_disparity;
+  signal ch0_disp_pipe : std_logic_vector(1 downto 0);
+  signal ch1_cur_disp  : t_8b10b_disparity;
+  signal ch1_disp_pipe : std_logic_vector(1 downto 0);
+  
+begin  -- rtl
+  -------------------------------------------------------------------------------
+  -- Channel 0 logic
+  -------------------------------------------------------------------------------
+
+  gen_with_channel0 : if(g_enable_ch0 /= 0) generate
+    ch0_rst_n          <= not ch0_gtp_reset;
+    ch0_tx_disparity_o <= ch0_disp_pipe(0);
+
+    ch0_gtp_reset      <= ch0_rst_synced or std_logic(not ch0_reset_counter(ch0_reset_counter'left));
+    ch0_rx_rec_clk_pad <= ch0_gtp_clkout_int(1);
+    ch0_ref_clk_in(0)  <= gtp_clk_i;
+    ch0_ref_clk_in(1)  <= '0';
+    -- Near-end PMA loopback or loopback selected with ch1_loopen_vec_i
+    ch0_gtp_loopback <= "010" when(ch0_loopen_i = '1') else
+                        ch0_loopen_vec_i;
+
+    gen_disp_ch0 : process(ch0_ref_clk_i)
+    begin
+      if rising_edge(ch0_ref_clk_i) then
+        if(ch0_tx_chardispmode = '1' or ch0_rst_n = '0') then
+          if(g_force_disparity = 0) then
+            ch0_cur_disp <= RD_MINUS;
+          else
+            ch0_cur_disp <= RD_PLUS;
+          end if;
+          ch0_disp_pipe <= (others => '0');
+        else
+          ch0_cur_disp     <= f_next_8b10b_disparity8(ch0_cur_disp, ch0_tx_k_i, ch0_tx_data_i);
+          ch0_disp_pipe(0) <= to_std_logic(ch0_cur_disp);
+          ch0_disp_pipe(1) <= ch0_disp_pipe(0);
+        end if;
+      end if;
+    end process;
+
+
+    p_gen_reset_ch0 : process(ch0_ref_clk_i)
+    begin
+      if rising_edge(ch0_ref_clk_i) then
+
+        ch0_rst_d0     <= ch0_rst_i;
+        ch0_rst_synced <= ch0_rst_d0;
+
+        if(ch0_rst_synced = '1') then
+          ch0_reset_counter <= (others => '0');
+        else
+          if(ch0_reset_counter(ch0_reset_counter'left) = '0') then
+            ch0_reset_counter <= ch0_reset_counter + 1;
+          end if;
+        end if;
+      end if;
+    end process;
+
+
+    U_Rbclk_buf_ch0 : BUFIO2
+      port map (
+        DIVCLK       => ch0_rx_divclk,
+        IOCLK        => open,
+        SERDESSTROBE => open,
+        I            => ch0_rx_rec_clk_pad);
+
+    U_Rbclk_bufg_ch0 : BUFG
+      port map (
+        I => ch0_rx_divclk,
+        O => ch0_rx_rec_clk
+        );
+
+    ch0_gtp_locked   <= ch0_gtp_pll_lockdet and ch0_gtp_reset_done;
+    ch0_tx_enc_err_o <= '0';
+
+    U_align_ch0 : gtp_phase_align
+      generic map (
+        g_simulation => g_simulation) 
+      port map (
+        gtp_rst_i                   => ch0_gtp_reset,
+        gtp_tx_clk_i                => ch0_ref_clk_i,
+        gtp_tx_en_pma_phase_align_o => ch0_tx_en_pma_phase_align,
+        gtp_tx_pma_set_phase_o      => ch0_tx_pma_set_phase,
+        align_en_i                  => ch0_gtp_locked,
+        align_done_o                => ch0_align_done);
+
+    U_bitslide_ch0 : gtp_bitslide
+      generic map (
+        g_simulation => g_simulation)
+      port map (
+        gtp_rst_i                => ch0_gtp_reset,
+        gtp_rx_clk_i             => ch0_rx_rec_clk,
+        gtp_rx_comma_det_i       => ch0_rx_comma_det,
+        gtp_rx_byte_is_aligned_i => ch0_rx_byte_is_aligned,
+        serdes_ready_i           => ch0_gtp_locked,
+        gtp_rx_slide_o           => ch0_rx_slide,
+        gtp_rx_cdr_rst_o         => ch0_rx_cdr_rst,
+        bitslide_o               => ch0_rx_bitslide_int,
+        synced_o                 => ch0_rx_synced);
+
+    ch0_rx_bitslide_o    <= ch0_rx_bitslide_int(3 downto 0);
+    ch0_rx_enable_output <= ch0_rx_synced and ch0_align_done;
+
+    U_sync_oen_ch0 : gc_sync_ffs
+      generic map (
+        g_sync_edge => "positive")
+      port map (
+        clk_i    => ch0_rx_rec_clk,
+        rst_n_i  => '1',
+        data_i   => ch0_rx_enable_output,
+        synced_o => ch0_rx_enable_output_synced,
+        npulse_o => open,
+        ppulse_o => open);
+
+    p_force_proper_disparity_ch0 : process(ch0_ref_clk_i, ch0_gtp_reset)
+    begin
+      if (ch0_gtp_reset = '1') then
+        ch0_disparity_set   <= '0';
+        ch0_tx_chardispval  <= '0';
+        ch0_tx_chardispmode <= '0';
+      elsif rising_edge(ch0_ref_clk_i) then
+        if(ch0_disparity_set = '0' and ch0_tx_k_i = '1' and ch0_tx_data_i = x"bc" and ch0_align_done = '1') then
+          ch0_disparity_set <= '1';
+          if(g_force_disparity = 0) then
+            ch0_tx_chardispval <= '0';
+          else
+            ch0_tx_chardispval <= '1';
+          end if;
+          ch0_tx_chardispmode <= '1';
+        else
+          ch0_tx_chardispmode <= '0';
+          ch0_tx_chardispval  <= '0';
+        end if;
+      end if;
+    end process;
+
+    p_gen_output_ch0 : process(ch0_rx_rec_clk, ch0_gtp_reset)
+    begin
+      if(ch0_gtp_reset = '1') then
+        ch0_rx_data      <= (others => '0');
+        ch0_rx_k         <= '0';
+        ch0_rx_enc_err   <= '0';
+        
+      elsif rising_edge(ch0_rx_rec_clk) then
+        if(ch0_rx_enable_output_synced = '0') then
+-- make sure the output data is invalid when the link is down and that it will
+-- trigger the sync loss detection
+          ch0_rx_data      <= (others => '0');
+          ch0_rx_k         <= '1';
+          ch0_rx_enc_err   <= '1';
+        else
+          ch0_rx_data      <= ch0_rx_data_int;
+          ch0_rx_k         <= ch0_rx_k_int;
+          ch0_rx_enc_err   <= ch0_rx_disperr or ch0_rx_invcode;
+        end if;
+      end if;
+    end process;
+
+
+-- drive the recovered clock output
+    ch0_rx_rbclk_o <= ch0_rx_rec_clk;
+    -- drive ch0 ready indicator as well
+    ch0_rdy_o <= ch0_rx_enable_output_synced;
+    -- Note that the above clock assignment takes one delta delay in a simulator.
+    -- In order to keep clock and data signals aligned, re-assign rx_data, rx_k
+    -- and rx_enc_err (also adding one delta delay). This is purely necessary for
+    -- proper simulation only.
+    ch0_rx_data_o    <= ch0_rx_data;
+    ch0_rx_k_o       <= ch0_rx_k;
+    ch0_rx_enc_err_o <= ch0_rx_enc_err;
+  end generate gen_with_channel0;
+
+  -------------------------------------------------------------------------------
+  -- Channel 1 logic
+  -------------------------------------------------------------------------------
+
+  gen_with_channel1 : if(g_enable_ch1 /= 0) generate
+
+    ch1_rst_n          <= not ch1_gtp_reset;
+    ch1_tx_disparity_o <= ch1_disp_pipe(1);
+
+    ch1_gtp_reset      <= ch1_rst_synced or std_logic(not ch1_reset_counter(ch1_reset_counter'left));
+    ch1_rx_rec_clk_pad <= ch1_gtp_clkout_int(1);
+    ch1_ref_clk_in(0)  <= gtp_clk_i;
+    ch1_ref_clk_in(1)  <= '0';
+    -- Near-end PMA loopback or loopback selected with ch1_loopen_vec_i
+    ch1_gtp_loopback <= "010" when(ch1_loopen_i = '1') else
+                        ch1_loopen_vec_i;
+
+    gen_disp_ch1 : process(ch1_ref_clk_i)
+    begin
+      if rising_edge(ch1_ref_clk_i) then
+        if(ch1_tx_chardispmode = '1' or ch1_rst_n = '0') then
+          if(g_force_disparity = 0) then
+            ch1_cur_disp <= RD_MINUS;
+          else
+            ch1_cur_disp <= RD_PLUS;
+          end if;
+          ch1_disp_pipe <= (others => '0');
+        else
+          ch1_cur_disp     <= f_next_8b10b_disparity8(ch1_cur_disp, ch1_tx_k_i, ch1_tx_data_i);
+          ch1_disp_pipe(0) <= to_std_logic(ch1_cur_disp);
+          ch1_disp_pipe(1) <= ch1_disp_pipe(0);
+        end if;
+      end if;
+    end process;
+
+    p_gen_reset_ch1 : process(ch1_ref_clk_i)
+    begin
+      if rising_edge(ch1_ref_clk_i) then
+
+        ch1_rst_d0     <= ch1_rst_i;
+        ch1_rst_synced <= ch1_rst_d0;
+
+        if(ch1_rst_synced = '1') then
+          ch1_reset_counter <= (others => '0');
+        else
+          if(ch1_reset_counter(ch1_reset_counter'left) = '0') then
+            ch1_reset_counter <= ch1_reset_counter + 1;
+          end if;
+        end if;
+      end if;
+    end process;
+
+    U_Rbclk_buf_ch1 : BUFIO2
+      port map (
+        DIVCLK       => ch1_rx_divclk,
+        IOCLK        => open,
+        SERDESSTROBE => open,
+        I            => ch1_rx_rec_clk_pad);
+
+    U_Rbclk_bufg_ch1 : BUFG
+      port map (
+        I => ch1_rx_divclk,
+        O => ch1_rx_rec_clk
+        );
+
+    ch1_gtp_locked   <= ch1_gtp_pll_lockdet and ch1_gtp_reset_done;
+    ch1_tx_enc_err_o <= '0';
+
+    U_align_ch1 : gtp_phase_align
+      generic map (
+        g_simulation => g_simulation) 
+      port map (
+        gtp_rst_i                   => ch1_gtp_reset,
+        gtp_tx_clk_i                => ch1_ref_clk_i,
+        gtp_tx_en_pma_phase_align_o => ch1_tx_en_pma_phase_align,
+        gtp_tx_pma_set_phase_o      => ch1_tx_pma_set_phase,
+        align_en_i                  => ch1_gtp_locked,
+        align_done_o                => ch1_align_done);
+
+    U_bitslide_ch1 : gtp_bitslide
+      generic map (
+        g_simulation => g_simulation)
+      port map (
+        gtp_rst_i                => ch1_gtp_reset,
+        gtp_rx_clk_i             => ch1_rx_rec_clk,
+        gtp_rx_comma_det_i       => ch1_rx_comma_det,
+        gtp_rx_byte_is_aligned_i => ch1_rx_byte_is_aligned,
+        serdes_ready_i           => ch1_gtp_locked,
+        gtp_rx_slide_o           => ch1_rx_slide,
+        gtp_rx_cdr_rst_o         => ch1_rx_cdr_rst,
+        bitslide_o               => ch1_rx_bitslide_int,
+        synced_o                 => ch1_rx_synced);
+
+    ch1_rx_bitslide_o    <= ch1_rx_bitslide_int(3 downto 0);
+    ch1_rx_enable_output <= ch1_rx_synced and ch1_align_done;
+
+    U_sync_oen_ch1 : gc_sync_ffs
+      generic map (
+        g_sync_edge => "positive")
+      port map (
+        clk_i    => ch1_rx_rec_clk,
+        rst_n_i  => '1',
+        data_i   => ch1_rx_enable_output,
+        synced_o => ch1_rx_enable_output_synced,
+        npulse_o => open,
+        ppulse_o => open);
+
+    p_force_proper_disparity_ch1 : process(ch1_ref_clk_i, ch1_gtp_reset)
+    begin
+      if (ch1_gtp_reset = '1') then
+        ch1_disparity_set   <= '0';
+        ch1_tx_chardispval  <= '0';
+        ch1_tx_chardispmode <= '0';
+        
+      elsif rising_edge(ch1_ref_clk_i) then
+        if(ch1_disparity_set = '0' and ch1_tx_k_i = '1' and ch1_tx_data_i = x"bc" and ch1_align_done = '1') then
+          ch1_disparity_set <= '1';
+          if(g_force_disparity = 0) then
+            ch1_tx_chardispval <= '0';
+          else
+            ch1_tx_chardispval <= '1';
+          end if;
+          ch1_tx_chardispmode <= '1';
+        else
+          ch1_tx_chardispmode <= '0';
+          ch1_tx_chardispval  <= '0';
+        end if;
+      end if;
+    end process;
+
+    p_gen_output_ch1 : process(ch1_rx_rec_clk, ch1_rst_i)
+    begin
+      if(ch1_rst_i = '1') then
+        ch1_rx_data    <= (others => '0');
+        ch1_rx_k       <= '0';
+        ch1_rx_enc_err <= '0';
+        
+      elsif rising_edge(ch1_rx_rec_clk) then
+        if(ch1_rx_enable_output_synced = '0') then
+-- make sure the output data is invalid when the link is down and that it will
+-- trigger the sync loss detection
+          ch1_rx_data    <= (others => '0');
+          ch1_rx_k       <= '1';
+          ch1_rx_enc_err <= '1';
+        else
+          ch1_rx_data    <= ch1_rx_data_int;
+          ch1_rx_k       <= ch1_rx_k_int;
+          ch1_rx_enc_err <= ch1_rx_disperr or ch1_rx_invcode;
+        end if;
+      end if;
+    end process;
+
+    ch1_rx_rbclk_o <= ch1_rx_rec_clk;
+    ch1_rdy_o <= ch1_rx_enable_output_synced;
+    -- Note that the above clock assignment takes one delta delay in a simulator.
+    -- In order to keep clock and data signals aligned, re-assign rx_data, rx_k
+    -- and rx_enc_err (also adding one delta delay). This is purely necessary for
+    -- proper simulation only.
+    ch1_rx_data_o    <= ch1_rx_data;
+    ch1_rx_k_o       <= ch1_rx_k;
+    ch1_rx_enc_err_o <= ch1_rx_enc_err;
+  end generate gen_with_channel1;
+
+  U_GTP_TILE_INST : WHITERABBITGTP_WRAPPER_TILE_SPARTAN6
+    generic map
+    (
+      TILE_SIM_GTPRESET_SPEEDUP => g_simulation,  -- Set to 1 to speed up sim reset
+      TILE_CLK25_DIVIDER_0      => 5,
+      TILE_CLK25_DIVIDER_1      => 5,
+      TILE_PLL_DIVSEL_FB_0      => 2,
+      TILE_PLL_DIVSEL_FB_1      => 2,
+      TILE_PLL_DIVSEL_REF_0     => 1,
+      TILE_PLL_DIVSEL_REF_1     => 1,
+
+      -- 
+      TILE_PLL_SOURCE_0 => "PLL0",
+      TILE_PLL_SOURCE_1 => "PLL1"
+      )
+    port map
+    (
+      ------------------------ Loopback and Powerdown Ports ----------------------
+      LOOPBACK0_IN => ch0_gtp_loopback,
+      LOOPBACK1_IN => ch1_gtp_loopback,
+      --------------------------------- PLL Ports --------------------------------
+
+      REFCLKOUT0_OUT => open,
+      REFCLKOUT1_OUT => open,
+      CLK00_IN       => ch0_ref_clk_in(0),
+      CLK01_IN       => ch1_ref_clk_in(0),
+      CLK10_IN       => ch0_ref_clk_in(1),
+      CLK11_IN       => ch1_ref_clk_in(1),
+      GTPRESET0_IN   => ch0_gtp_reset,
+      GTPRESET1_IN   => ch1_gtp_reset,
+      PLLLKDET0_OUT  => ch0_gtp_pll_lockdet,
+      PLLLKDET1_OUT  => ch1_gtp_pll_lockdet,
+      RESETDONE0_OUT => ch0_gtp_reset_done,
+      RESETDONE1_OUT => ch1_gtp_reset_done,
+
+      ----------------------- Receive Ports - 8b10b Decoder ----------------------
+      RXCHARISK0_OUT    => ch0_rx_k_int,
+      RXCHARISK1_OUT    => ch1_rx_k_int,
+      RXDISPERR0_OUT    => ch0_rx_disperr,
+      RXDISPERR1_OUT    => ch1_rx_disperr,
+      RXNOTINTABLE0_OUT => ch0_rx_invcode,
+      RXNOTINTABLE1_OUT => ch1_rx_invcode,
+
+      --------------- Receive Ports - Comma Detection and Alignment --------------
+      RXBYTEISALIGNED0_OUT => ch0_rx_byte_is_aligned,
+      RXBYTEISALIGNED1_OUT => ch1_rx_byte_is_aligned,
+      RXCOMMADET0_OUT      => ch0_rx_comma_det,
+      RXCOMMADET1_OUT      => ch1_rx_comma_det,
+      RXSLIDE0_IN          => ch0_rx_slide,
+      RXSLIDE1_IN          => ch1_rx_slide,
+
+      ------------------- Receive Ports - RX Data Path interface -----------------
+      RXDATA0_OUT   => ch0_rx_data_int,
+      RXDATA1_OUT   => ch1_rx_data_int,
+      RXUSRCLK0_IN  => ch0_rx_rec_clk,
+      RXUSRCLK1_IN  => ch1_rx_rec_clk,
+      RXUSRCLK20_IN => ch0_rx_rec_clk,
+      RXUSRCLK21_IN => ch1_rx_rec_clk,
+
+      ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
+      RXCDRRESET0_IN => ch0_rx_cdr_rst,
+      RXCDRRESET1_IN => ch1_rx_cdr_rst,
+      RXN0_IN        => pad_rxn0_i,
+      RXN1_IN        => pad_rxn1_i,
+      RXP0_IN        => pad_rxp0_i,
+      RXP1_IN        => pad_rxp1_i,
+
+      ---------------------------- TX/RX Datapath Ports --------------------------
+      GTPCLKFBEAST_OUT => open,
+      GTPCLKFBWEST_OUT => open,
+      GTPCLKOUT0_OUT   => ch0_gtp_clkout_int,
+      GTPCLKOUT1_OUT   => ch1_gtp_clkout_int,
+      ------------------- Transmit Ports - 8b10b Encoder Control -----------------
+      TXCHARISK0_IN    => ch0_tx_k_i,
+      TXCHARISK1_IN    => ch1_tx_k_i,
+      TXRUNDISP0_OUT   => ch0_tx_rundisp_vec,
+      TXRUNDISP1_OUT   => ch1_tx_rundisp_vec,
+
+      TXCHARDISPMODE0_IN => ch0_tx_chardispmode,
+      TXCHARDISPMODE1_IN => ch1_tx_chardispmode,
+      TXCHARDISPVAL0_IN  => ch0_tx_chardispval,
+      TXCHARDISPVAL1_IN  => ch1_tx_chardispval,
+
+      --------------- Transmit Ports - TX Buffer and Phase Alignment -------------
+      TXENPMAPHASEALIGN0_IN => ch0_tx_en_pma_phase_align,
+      TXENPMAPHASEALIGN1_IN => ch1_tx_en_pma_phase_align,
+      TXPMASETPHASE0_IN     => ch0_tx_pma_set_phase,
+      TXPMASETPHASE1_IN     => ch1_tx_pma_set_phase,
+      ------------------ Transmit Ports - TX Data Path interface -----------------
+      TXDATA0_IN            => ch0_tx_data_i,
+      TXDATA1_IN            => ch1_tx_data_i,
+      TXUSRCLK0_IN          => ch0_ref_clk_i,
+      TXUSRCLK1_IN          => ch1_ref_clk_i,
+      TXUSRCLK20_IN         => ch0_ref_clk_i,
+      TXUSRCLK21_IN         => ch1_ref_clk_i,
+      --------------- Transmit Ports - TX Driver and OOB signalling --------------
+      TXN0_OUT              => pad_txn0_o,
+      TXN1_OUT              => pad_txn1_o,
+      TXP0_OUT              => pad_txp0_o,
+      TXP1_OUT              => pad_txp1_o,
+      --------------- Transmit Ports - TX PRBS Generator -------------------------
+      TXENPRBSTST0_IN       => ch0_tx_prbs_sel_i,
+      TXENPRBSTST1_IN       => ch1_tx_prbs_sel_i
+
+      );
+
+
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_xilinx_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_xilinx_pkg.vhd
new file mode 100644
index 000000000..5f9f76415
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_xilinx_pkg.vhd
@@ -0,0 +1,192 @@
+-------------------------------------------------------------------------------
+-- Title      : Platform-dependent components needed for WR PTP Core on Xilinx
+-- Project    : WR PTP Core
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
+-------------------------------------------------------------------------------
+-- File       : wr_xilinx_pkg.vhd
+-- Author     : Maciej Lipinski, Grzegorz Daniluk, Dimitrios Lampridis
+-- Company    : CERN
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2016-2017 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.endpoint_pkg.all;
+
+package wr_xilinx_pkg is
+
+  component xwrc_platform_xilinx is
+    generic (
+      g_fpga_family               : string  := "spartan6";
+      g_with_external_clock_input : boolean := FALSE;
+      g_use_default_plls          : boolean := TRUE;
+      g_gtp_enable_ch0            : integer := 0;
+      g_gtp_enable_ch1            : integer := 1;
+      g_simulation                : integer := 0;
+      g_use_ibufgds               : boolean := false);
+    port (
+      areset_n_i            : in  std_logic             := '1';
+      clk_10m_ext_i         : in  std_logic             := '0';
+      clk_125m_gtp_p_i      : in  std_logic;
+      clk_125m_gtp_n_i      : in  std_logic;
+      clk_20m_vcxo_i        : in  std_logic             := '0';
+      clk_125m_pllref_i     : in  std_logic             := '0';
+      clk_125m_dmtd_i       : in  std_logic             := '0';
+      clk_62m5_dmtd_i       : in  std_logic             := '0';
+      clk_dmtd_locked_i     : in  std_logic             := '1';
+      clk_62m5_sys_i        : in  std_logic             := '0';
+      clk_sys_locked_i      : in  std_logic             := '1';
+      clk_125m_ref_i        : in  std_logic             := '0';
+      clk_ref_locked_i      : in  std_logic             := '1';
+      clk_125m_ext_i        : in  std_logic             := '0';
+      clk_ext_locked_i      : in  std_logic             := '1';
+      clk_ext_stopped_i     : in  std_logic             := '0';
+      clk_ext_rst_o         : out std_logic;
+      sfp_txn_o             : out std_logic;
+      sfp_txp_o             : out std_logic;
+      sfp_rxn_i             : in  std_logic;
+      sfp_rxp_i             : in  std_logic;
+      sfp_tx_fault_i        : in  std_logic             := '0';
+      sfp_los_i             : in  std_logic             := '0';
+      sfp_tx_disable_o      : out std_logic;
+      clk_62m5_sys_o        : out std_logic;
+      clk_125m_ref_o        : out std_logic;
+      clk_ref_locked_o      : out std_logic;
+      clk_62m5_dmtd_o       : out std_logic;
+      pll_locked_o          : out std_logic;
+      clk_10m_ext_o         : out std_logic;
+      phy8_o                : out t_phy_8bits_to_wrc;
+      phy8_i                : in  t_phy_8bits_from_wrc  := c_dummy_phy8_from_wrc;
+      phy16_o               : out t_phy_16bits_to_wrc;
+      phy16_i               : in  t_phy_16bits_from_wrc := c_dummy_phy16_from_wrc;
+      ext_ref_mul_o         : out std_logic;
+      ext_ref_mul_locked_o  : out std_logic;
+      ext_ref_mul_stopped_o : out std_logic;
+      ext_ref_rst_i         : in  std_logic             := '0');
+  end component xwrc_platform_xilinx;
+
+  component wr_gtp_phy_spartan6
+    generic (
+      g_enable_ch0 : integer := 1;
+      g_enable_ch1 : integer := 1;
+      g_simulation : integer := 0);
+    port (
+      gtp_clk_i          : in  std_logic;
+      ch0_ref_clk_i      : in  std_logic                    := '0';
+      ch0_tx_data_i      : in  std_logic_vector(7 downto 0) := "00000000";
+      ch0_tx_k_i         : in  std_logic                    := '0';
+      ch0_tx_disparity_o : out std_logic;
+      ch0_tx_enc_err_o   : out std_logic;
+      ch0_rx_rbclk_o     : out std_logic;
+      ch0_rx_data_o      : out std_logic_vector(7 downto 0);
+      ch0_rx_k_o         : out std_logic;
+      ch0_rx_enc_err_o   : out std_logic;
+      ch0_rx_bitslide_o  : out std_logic_vector(3 downto 0);
+      ch0_rst_i          : in  std_logic                    := '0';
+      ch0_loopen_i       : in  std_logic                    := '0';
+      ch0_loopen_vec_i   : in  std_logic_vector(2 downto 0) := (others => '0');
+      ch0_tx_prbs_sel_i  : in  std_logic_vector(2 downto 0) := (others => '0');
+      ch0_rdy_o          : out std_logic;
+      ch1_ref_clk_i      : in  std_logic;
+      ch1_tx_data_i      : in  std_logic_vector(7 downto 0) := "00000000";
+      ch1_tx_k_i         : in  std_logic                    := '0';
+      ch1_tx_disparity_o : out std_logic;
+      ch1_tx_enc_err_o   : out std_logic;
+      ch1_rx_data_o      : out std_logic_vector(7 downto 0);
+      ch1_rx_rbclk_o     : out std_logic;
+      ch1_rx_k_o         : out std_logic;
+      ch1_rx_enc_err_o   : out std_logic;
+      ch1_rx_bitslide_o  : out std_logic_vector(3 downto 0);
+      ch1_rst_i          : in  std_logic                    := '0';
+      ch1_loopen_i       : in  std_logic                    := '0';
+      ch1_loopen_vec_i   : in  std_logic_vector(2 downto 0) := (others => '0');
+      ch1_tx_prbs_sel_i  : in  std_logic_vector(2 downto 0) := (others => '0');
+      ch1_rdy_o          : out std_logic;
+      pad_txn0_o         : out std_logic;
+      pad_txp0_o         : out std_logic;
+      pad_rxn0_i         : in  std_logic                    := '0';
+      pad_rxp0_i         : in  std_logic                    := '0';
+      pad_txn1_o         : out std_logic;
+      pad_txp1_o         : out std_logic;
+      pad_rxn1_i         : in  std_logic                    := '0';
+      pad_rxp1_i         : in  std_logic                    := '0');
+  end component;
+
+  component wr_gtx_phy_family7 is
+    generic (
+      -- set to non-zero value to speed up the simulation by reducing some delays
+      g_simulation : integer := 0);
+    port (
+      clk_gtx_i      : in  std_logic;
+      tx_out_clk_o   : out std_logic;
+      tx_locked_o    : out std_logic;
+      tx_data_i      : in  std_logic_vector(15 downto 0);
+      tx_k_i         : in  std_logic_vector(1 downto 0);
+      tx_disparity_o : out std_logic;
+      tx_enc_err_o   : out std_logic;
+      rx_rbclk_o     : out std_logic;
+      rx_data_o      : out std_logic_vector(15 downto 0);
+      rx_k_o         : out std_logic_vector(1 downto 0);
+      rx_enc_err_o   : out std_logic;
+      rx_bitslide_o  : out std_logic_vector(4 downto 0);
+      rst_i          : in  std_logic;
+      loopen_i       : in  std_logic_vector(2 downto 0);
+      tx_prbs_sel_i  : in  std_logic_vector(2 downto 0);
+      pad_txn_o      : out std_logic;
+      pad_txp_o      : out std_logic;
+      pad_rxn_i      : in  std_logic := '0';
+      pad_rxp_i      : in  std_logic := '0';
+      rdy_o          : out std_logic);
+  end component;
+
+  component wr_gtp_phy_family7 is
+    generic (
+      -- set to non-zero value to speed up the simulation by reducing some delays
+      g_simulation : integer := 0);
+    port (
+      clk_gtp_i      : in  std_logic;
+      tx_out_clk_o   : out std_logic;
+      tx_locked_o    : out std_logic;
+      tx_data_i      : in  std_logic_vector(15 downto 0);
+      tx_k_i         : in  std_logic_vector(1 downto 0);
+      tx_disparity_o : out std_logic;
+      tx_enc_err_o   : out std_logic;
+      rx_rbclk_o     : out std_logic;
+      rx_data_o      : out std_logic_vector(15 downto 0);
+      rx_k_o         : out std_logic_vector(1 downto 0);
+      rx_enc_err_o   : out std_logic;
+      rx_bitslide_o  : out std_logic_vector(4 downto 0);
+      rst_i          : in  std_logic;
+      loopen_i       : in  std_logic_vector(2 downto 0);
+      tx_prbs_sel_i  : in  std_logic_vector(2 downto 0);
+      pad_txn_o      : out std_logic;
+      pad_txp_o      : out std_logic;
+      pad_rxn_i      : in  std_logic := '0';
+      pad_rxp_i      : in  std_logic := '0';
+      rdy_o          : out std_logic);
+  end component;
+
+end wr_xilinx_pkg;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/xwrc_platform_xilinx.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/xwrc_platform_xilinx.vhd
new file mode 100644
index 000000000..c36d7c3c1
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/xwrc_platform_xilinx.vhd
@@ -0,0 +1,1095 @@
+-------------------------------------------------------------------------------
+-- Title      : Platform-dependent components needed for WR PTP Core on Xilinx
+-- Project    : WR PTP Core
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
+-------------------------------------------------------------------------------
+-- File       : wrc_platform_xilinx.vhd
+-- Author     : Maciej Lipinski, Grzegorz Daniluk, Dimitrios Lampridis
+-- Company    : CERN
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description:
+-- This module instantiates platform-specific modules that are needed by the
+-- WR PTP Core (WRPC) to interface hardware on Xilinx FPGA. In particular it
+-- contains:
+-- * PHY
+-- * PLLs
+-- * buffers
+--
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2016-2017 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.endpoint_pkg.all;
+use work.gencores_pkg.all;
+use work.wr_xilinx_pkg.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity xwrc_platform_xilinx is
+  generic
+    (
+      -- Define the family/model of Xilinx FPGA
+      -- (supported: for now only spartan6)
+      g_fpga_family               : string  := "spartan6";
+      -- Select whether to include external ref clock input
+      g_with_external_clock_input : boolean := FALSE;
+      -- Set to FALSE if you want to instantiate your own PLLs
+      g_use_default_plls          : boolean := TRUE;
+      -- Select GTP channel to use (only one can be active)
+      g_gtp_enable_ch0            : integer := 0;
+      g_gtp_enable_ch1            : integer := 1;
+      -- Set to TRUE will speed up some initialization processes
+      g_simulation                : integer := 0;
+      g_use_ibufgds               : boolean := false
+      );
+  port (
+    ---------------------------------------------------------------------------
+    -- Asynchronous reset (active low)
+    ---------------------------------------------------------------------------
+    areset_n_i            : in  std_logic;
+    ---------------------------------------------------------------------------
+    -- 10MHz ext ref clock input (g_with_external_clock_input = TRUE)
+    ---------------------------------------------------------------------------
+    clk_10m_ext_i         : in  std_logic             := '0';
+    ---------------------------------------------------------------------------
+    -- 125 MHz GTP/GTX reference
+    -- If g_use_ibufgds=false then connect buffered clock to clk_125m_gtp_p_i
+    ---------------------------------------------------------------------------
+    clk_125m_gtp_p_i      : in  std_logic;
+    clk_125m_gtp_n_i      : in  std_logic;
+    ---------------------------------------------------------------------------
+    -- Clock inputs for default PLLs (g_use_default_plls = TRUE)
+    ---------------------------------------------------------------------------
+    -- 20MHz VCXO clock
+    clk_20m_vcxo_i        : in  std_logic             := '0';
+    -- 125.000 MHz PLL reference
+    clk_125m_pllref_i     : in  std_logic             := '0';
+    -- 124.992 MHz DMTD reference (CLBv3 reference design)
+    clk_125m_dmtd_i       : in  std_logic             := '0';
+    ---------------------------------------------------------------------------
+    -- Clock inputs from custom PLLs (g_use_default_plls = FALSE)
+    ---------------------------------------------------------------------------
+    -- 62.5MHz DMTD offset clock and lock status
+    clk_62m5_dmtd_i       : in  std_logic             := '0';
+    clk_dmtd_locked_i     : in  std_logic             := '1';
+    -- 62.5MHz Main system clock and lock status
+    clk_62m5_sys_i        : in  std_logic             := '0';
+    clk_sys_locked_i      : in  std_logic             := '1';
+    -- 125MHz  Reference clock
+    clk_125m_ref_i        : in  std_logic             := '0';
+    clk_ref_locked_i      : in  std_logic             := '1';
+    -- 125MHz derived from 10MHz external reference and lock status
+    -- (when g_with_external_clock_input = TRUE)
+    clk_125m_ext_i        : in  std_logic             := '0';
+    clk_ext_locked_i      : in  std_logic             := '1';
+    clk_ext_stopped_i     : in  std_logic             := '0';
+    clk_ext_rst_o         : out std_logic;
+    ---------------------------------------------------------------------------
+    -- SFP
+    ---------------------------------------------------------------------------
+    sfp_txn_o             : out std_logic;
+    sfp_txp_o             : out std_logic;
+    sfp_rxn_i             : in  std_logic;
+    sfp_rxp_i             : in  std_logic;
+    sfp_tx_fault_i        : in  std_logic             := '0';
+    sfp_los_i             : in  std_logic             := '0';
+    sfp_tx_disable_o      : out std_logic;
+    ---------------------------------------------------------------------------
+    --Interface to WR PTP Core (WRPC)
+    ---------------------------------------------------------------------------
+    -- PLL outputs
+    clk_62m5_sys_o        : out std_logic;
+    clk_125m_ref_o        : out std_logic;
+    clk_ref_locked_o      : out std_logic;
+    clk_62m5_dmtd_o       : out std_logic;
+    pll_locked_o          : out std_logic;
+    clk_10m_ext_o         : out std_logic;
+    -- PHY
+    phy8_o                : out t_phy_8bits_to_wrc;
+    phy8_i                : in  t_phy_8bits_from_wrc  := c_dummy_phy8_from_wrc;
+    phy16_o               : out t_phy_16bits_to_wrc;
+    phy16_i               : in  t_phy_16bits_from_wrc := c_dummy_phy16_from_wrc;
+    -- External reference
+    ext_ref_mul_o         : out std_logic;
+    ext_ref_mul_locked_o  : out std_logic;
+    ext_ref_mul_stopped_o : out std_logic;
+    ext_ref_rst_i         : in  std_logic             := '0'
+    );
+
+end entity xwrc_platform_xilinx;
+
+architecture rtl of xwrc_platform_xilinx is
+
+  -----------------------------------------------------------------------------
+  -- Signals declaration
+  -----------------------------------------------------------------------------
+
+  signal pll_arst            : std_logic := '0';
+  signal clk_125m_pllref_buf : std_logic;
+
+begin  -- architecture rtl
+
+  -----------------------------------------------------------------------------
+  -- Check for unsupported features and/or misconfiguration
+  -----------------------------------------------------------------------------
+  gen_unknown_fpga : if (g_fpga_family /= "spartan6" and g_fpga_family /= "kintex7" and g_fpga_family /= "artix7") generate
+    assert FALSE
+      report "Xilinx FPGA family [" & g_fpga_family & "] is not supported"
+      severity ERROR;
+  end generate gen_unknown_fpga;
+
+  gen_single_gtp_channel : if (g_gtp_enable_ch0 /= 0 and g_gtp_enable_ch1 /= 0)
+  generate
+    assert FALSE
+      report "Cannot enable both GTP channels simultaneously"
+      severity ERROR;
+  end generate gen_single_gtp_channel;
+
+  -----------------------------------------------------------------------------
+  -- Clock PLLs
+  -----------------------------------------------------------------------------
+
+  -- active high async reset for PLLs
+  pll_arst <= not areset_n_i;
+
+  gen_default_plls : if (g_use_default_plls = TRUE) generate
+
+    -- Default PLL setup consists of two PLLs.
+    -- One takes a 125MHz clock signal as input and produces the
+    -- 62.5MHz WR PTP core main system clock.
+    -- The other PLL takes a 20MHz clock signal as input and produces the
+    -- 62.5MHz DMTD clock.
+    --
+    -- A third PLL is instantiated if also g_with_external_clock_input = TRUE.
+    -- In that case, a 10MHz external reference is multiplied to generate a
+    -- 125MHz reference clock
+    gen_spartan6_default_plls : if (g_fpga_family = "spartan6") generate
+
+      signal clk_sys          : std_logic;
+      signal clk_sys_out      : std_logic;
+      signal clk_sys_fb       : std_logic;
+      signal pll_sys_locked   : std_logic;
+      signal clk_dmtd         : std_logic;
+      signal clk_dmtd_fb      : std_logic;
+      signal pll_dmtd_locked  : std_logic;
+      signal clk_20m_vcxo_buf : std_logic;
+
+    begin  --gen_spartan6_default_plls
+
+      -- System PLL
+      cmp_sys_clk_pll : PLL_BASE
+        generic map (
+          BANDWIDTH          => "OPTIMIZED",
+          CLK_FEEDBACK       => "CLKFBOUT",
+          COMPENSATION       => "INTERNAL",
+          DIVCLK_DIVIDE      => 1,
+          CLKFBOUT_MULT      => 8,
+          CLKFBOUT_PHASE     => 0.000,
+          CLKOUT0_DIVIDE     => 16,
+          CLKOUT0_PHASE      => 0.000,
+          CLKOUT0_DUTY_CYCLE => 0.500,
+          CLKIN_PERIOD       => 8.0,
+          REF_JITTER         => 0.016)
+        port map (
+          CLKFBOUT => clk_sys_fb,
+          CLKOUT0  => clk_sys,
+          LOCKED   => pll_sys_locked,
+          RST      => pll_arst,
+          CLKFBIN  => clk_sys_fb,
+          CLKIN    => clk_125m_pllref_buf);
+
+      -- System PLL input clock buffer
+      cmp_clk_sys_buf_i : BUFG
+        port map (
+          O => clk_125m_pllref_buf,
+          I => clk_125m_pllref_i);
+
+      -- System PLL output clock buffer
+      cmp_clk_sys_buf_o : BUFG
+        port map (
+          O => clk_sys_out,
+          I => clk_sys);
+
+      clk_62m5_sys_o <= clk_sys_out;
+      clk_125m_ref_o <= clk_125m_pllref_buf;
+      pll_locked_o   <= pll_sys_locked and pll_dmtd_locked;
+      clk_ref_locked_o <= '1';
+
+      -- DMTD PLL
+      cmp_dmtd_clk_pll : PLL_BASE
+        generic map (
+          BANDWIDTH          => "OPTIMIZED",
+          CLK_FEEDBACK       => "CLKFBOUT",
+          COMPENSATION       => "INTERNAL",
+          DIVCLK_DIVIDE      => 1,
+          CLKFBOUT_MULT      => 50,
+          CLKFBOUT_PHASE     => 0.000,
+          CLKOUT0_DIVIDE     => 16,
+          CLKOUT0_PHASE      => 0.000,
+          CLKOUT0_DUTY_CYCLE => 0.500,
+          CLKIN_PERIOD       => 50.0,
+          REF_JITTER         => 0.016)
+        port map (
+          CLKFBOUT => clk_dmtd_fb,
+          CLKOUT0  => clk_dmtd,
+          LOCKED   => pll_dmtd_locked,
+          RST      => pll_arst,
+          CLKFBIN  => clk_dmtd_fb,
+          CLKIN    => clk_20m_vcxo_buf);
+
+      -- DMTD PLL input clock buffer
+      cmp_clk_dmtd_buf_i : BUFG
+        port map (
+          O => clk_20m_vcxo_buf,
+          I => clk_20m_vcxo_i);
+
+      -- DMTD PLL output clock buffer
+      cmp_clk_dmtd_buf_o : BUFG
+        port map (
+          O => clk_62m5_dmtd_o,
+          I => clk_dmtd);
+
+
+      gen_spartan6_ext_ref_pll : if (g_with_external_clock_input = TRUE) generate
+
+        signal clk_ext_fbi  : std_logic;
+        signal clk_ext_fbo  : std_logic;
+        signal clk_ext_buf  : std_logic;
+        signal clk_ext      : std_logic;
+        signal clk_ext_stat : std_logic_vector(7 downto 0);
+        signal pll_ext_rst  : std_logic;
+
+      begin  --gen_spartan6_ext_ref_pll
+
+        -- External reference DCM
+        cmp_ext_ref_pll : DCM_SP
+          generic map
+          (CLKDV_DIVIDE       => 2.000,
+           CLKFX_DIVIDE       => 2,
+           CLKFX_MULTIPLY     => 25,
+           CLKIN_DIVIDE_BY_2  => FALSE,
+           CLKIN_PERIOD       => 100.0,
+           CLKOUT_PHASE_SHIFT => "NONE",
+           CLK_FEEDBACK       => "1X",
+           DESKEW_ADJUST      => "SYSTEM_SYNCHRONOUS",
+           PHASE_SHIFT        => 0,
+           STARTUP_WAIT       => FALSE)
+          port map
+          -- Input clock
+          (CLKIN    => clk_ext_buf,
+           CLKFB    => clk_ext_fbi,
+           -- Output clocks
+           CLK0     => clk_ext_fbo,
+           CLKFX    => clk_ext,
+           -- Ports for dynamic phase shift
+           PSCLK    => '0',
+           PSEN     => '0',
+           PSINCDEC => '0',
+           PSDONE   => open,
+           -- Other control and status signals
+           LOCKED   => ext_ref_mul_locked_o,
+           STATUS   => clk_ext_stat,
+           RST      => pll_ext_rst,
+           -- Unused pin, tie low
+           DSSEN    => '0');
+
+        ext_ref_mul_stopped_o <= clk_ext_stat(1);
+
+        -- External reference input buffer
+        cmp_clk_ext_buf_i : BUFG
+          port map
+          (O => clk_ext_buf,
+           I => clk_10m_ext_i);
+
+        clk_10m_ext_o <= clk_ext_buf;
+
+        -- External reference feedback buffer
+        cmp_clk_ext_buf_fb : BUFG
+          port map
+          (O => clk_ext_fbi,
+           I => clk_ext_fbo);
+
+        -- External reference output buffer
+        cmp_clk_ext_buf_o : BUFG
+          port map
+          (O => ext_ref_mul_o,
+           I => clk_ext);
+
+        cmp_extend_ext_reset : gc_extend_pulse
+          generic map (
+            g_width => 1000)
+          port map (
+            clk_i      => clk_sys_out,
+            rst_n_i    => pll_sys_locked,
+            pulse_i    => ext_ref_rst_i,
+            extended_o => pll_ext_rst);
+
+      end generate gen_spartan6_ext_ref_pll;
+
+    end generate gen_spartan6_default_plls;
+
+    ---------------------------------------------------------------------------
+    --   Kintex7 PLLs
+    ---------------------------------------------------------------------------
+    gen_kintex7_default_plls : if (g_fpga_family = "kintex7") generate
+
+      signal clk_sys          : std_logic;
+      signal clk_sys_out      : std_logic;
+      signal clk_sys_fb       : std_logic;
+      signal pll_sys_locked   : std_logic;
+      signal clk_dmtd         : std_logic;
+      signal clk_dmtd_fb      : std_logic;
+      signal pll_dmtd_locked  : std_logic;
+      signal clk_20m_vcxo_buf : std_logic;
+
+    begin
+      -- System PLL (125 MHz -> 62.5 MHz)
+      cmp_sys_clk_pll : MMCME2_ADV
+        generic map (
+          BANDWIDTH            => "OPTIMIZED",
+          CLKOUT4_CASCADE      => false,
+          COMPENSATION         => "ZHOLD",
+          STARTUP_WAIT         => false,
+          DIVCLK_DIVIDE        => 1,
+          CLKFBOUT_MULT_F      => 8.000,     -- 125 MHz x 8.
+          CLKFBOUT_PHASE       => 0.000,
+          CLKFBOUT_USE_FINE_PS => false,
+
+          CLKOUT0_DIVIDE_F    => 16.000,     -- 62.5 MHz sys clock
+          CLKOUT0_PHASE       => 0.000,
+          CLKOUT0_DUTY_CYCLE  => 0.500,
+          CLKOUT0_USE_FINE_PS => false,
+
+          CLKIN1_PERIOD => 8.000,            -- 8 ns means 125 MHz
+          REF_JITTER1   => 0.010)
+        port map (
+          -- Output clocks
+          CLKFBOUT     => clk_sys_fb,
+          CLKOUT0      => clk_sys,
+          -- Input clock control
+          CLKFBIN      => clk_sys_fb,
+          CLKIN1       => clk_125m_pllref_buf,
+          CLKIN2       => '0',
+          -- Tied to always select the primary input clock
+          CLKINSEL     => '1',
+          -- Ports for dynamic reconfiguration
+          DADDR        => (others => '0'),
+          DCLK         => '0',
+          DEN          => '0',
+          DI           => (others => '0'),
+          DO           => open,
+          DRDY         => open,
+          DWE          => '0',
+          -- Ports for dynamic phase shift
+          PSCLK        => '0',
+          PSEN         => '0',
+          PSINCDEC     => '0',
+          PSDONE       => open,
+          -- Other control and status signals
+          LOCKED       => pll_sys_locked,
+          CLKINSTOPPED => open,
+          CLKFBSTOPPED => open,
+          PWRDWN       => '0',
+          RST          => pll_arst);
+
+      -- System PLL output clock buffer
+      cmp_clk_sys_buf_o : BUFG
+      port map (
+        I => clk_sys,
+        O => clk_sys_out);
+
+      clk_62m5_sys_o <= clk_sys_out;
+      pll_locked_o   <= pll_dmtd_locked and pll_sys_locked;
+
+      -- DMTD PLL (20 MHz -> ~62,5 MHz)
+      cmp_dmtd_clk_pll : MMCME2_ADV
+        generic map (
+          BANDWIDTH            => "OPTIMIZED",
+          CLKOUT4_CASCADE      => false,
+          COMPENSATION         => "ZHOLD",
+          STARTUP_WAIT         => false,
+          DIVCLK_DIVIDE        => 1,
+          CLKFBOUT_MULT_F      => 50.000,    -- 20 MHz -> 1 GHz
+          CLKFBOUT_PHASE       => 0.000,
+          CLKFBOUT_USE_FINE_PS => false,
+          CLKOUT0_DIVIDE_F     => 16.000,    -- 1GHz/16 -> 62.5 MHz
+          CLKOUT0_PHASE        => 0.000,
+          CLKOUT0_DUTY_CYCLE   => 0.500,
+          CLKOUT0_USE_FINE_PS  => false,
+          CLKOUT1_DIVIDE       => 16,        -- 1GHz/16 -> 62.5 MHz
+          CLKOUT1_PHASE        => 0.000,
+          CLKOUT1_DUTY_CYCLE   => 0.500,
+          CLKOUT1_USE_FINE_PS  => false,
+          CLKIN1_PERIOD        => 50.000,    -- 50ns for 20 MHz
+          REF_JITTER1          => 0.010)
+        port map (
+          -- Output clocks
+          CLKFBOUT     => clk_dmtd_fb,
+          CLKOUT0      => clk_dmtd,
+          -- Input clock control
+          CLKFBIN      => clk_dmtd_fb,
+          CLKIN1       => clk_20m_vcxo_buf,
+          CLKIN2       => '0',
+          -- Tied to always select the primary input clock
+          CLKINSEL     => '1',
+          -- Ports for dynamic reconfiguration
+          DADDR        => (others => '0'),
+          DCLK         => '0',
+          DEN          => '0',
+          DI           => (others => '0'),
+          DO           => open,
+          DRDY         => open,
+          DWE          => '0',
+          -- Ports for dynamic phase shift
+          PSCLK        => '0',
+          PSEN         => '0',
+          PSINCDEC     => '0',
+          PSDONE       => open,
+          -- Other control and status signals
+          LOCKED       => pll_dmtd_locked,
+          CLKINSTOPPED => open,
+          CLKFBSTOPPED => open,
+          PWRDWN       => '0',
+          RST          => pll_arst);
+
+      -- DMTD PLL input clock buffer
+      cmp_clk_dmtd_buf_i : BUFG
+        port map (
+          O => clk_20m_vcxo_buf,
+          I => clk_20m_vcxo_i);
+
+      -- DMTD PLL output clock buffer
+      cmp_clk_dmtd_buf_o : BUFG
+        port map (
+          O => clk_62m5_dmtd_o,
+          I => clk_dmtd);
+
+      -- External 10MHz reference PLL for Kintex7
+      gen_kintex7_ext_ref_pll : if (g_with_external_clock_input = TRUE) generate
+        
+        signal clk_ext_fbi : std_logic;
+        signal clk_ext_fbo : std_logic;
+        signal clk_ext_buf : std_logic;
+        signal clk_ext_mul : std_logic;
+        signal pll_ext_rst : std_logic;
+
+      begin
+        mmcm_adv_inst : MMCME2_ADV
+          generic map (
+            BANDWIDTH            => "OPTIMIZED",
+            CLKOUT4_CASCADE      => FALSE,
+            COMPENSATION         => "ZHOLD",
+            STARTUP_WAIT         => FALSE,
+            DIVCLK_DIVIDE        => 1,
+            CLKFBOUT_MULT_F      => 62.500,
+            CLKFBOUT_PHASE       => 0.000,
+            CLKFBOUT_USE_FINE_PS => FALSE,
+            CLKOUT0_DIVIDE_F     => 10.000,
+            CLKOUT0_PHASE        => 0.000,
+            CLKOUT0_DUTY_CYCLE   => 0.500,
+            CLKOUT0_USE_FINE_PS  => FALSE,
+            CLKIN1_PERIOD        => 100.000,
+            REF_JITTER1          => 0.005)
+          port map (
+            -- Output clocks
+            CLKFBOUT  => clk_ext_fbo,
+            CLKOUT0   => clk_ext_mul,
+            -- Input clock control
+            CLKFBIN   => clk_ext_fbi,
+            CLKIN1    => clk_ext_buf,
+            CLKIN2    => '0',
+            -- Tied to always select the primary input clock
+            CLKINSEL  => '1',
+            -- Ports for dynamic reconfiguration
+            DADDR     => (others => '0'),
+            DCLK      => '0',
+            DEN       => '0',
+            DI        => (others => '0'),
+            DO        => open,
+            DRDY      => open,
+            DWE       => '0',
+            -- Ports for dynamic phase shift
+            PSCLK     => '0',
+            PSEN      => '0',
+            PSINCDEC  => '0',
+            PSDONE    => open, -- Other control and status signals
+            LOCKED    => ext_ref_mul_locked_o,
+            CLKINSTOPPED => ext_ref_mul_stopped_o,
+            CLKFBSTOPPED => open,
+            PWRDWN   => '0',
+            RST      => pll_ext_rst);
+
+        -- External reference input buffer
+        cmp_clk_ext_buf_i : BUFG
+          port map (
+            O => clk_ext_buf,
+            I => clk_10m_ext_i);
+
+        clk_10m_ext_o <= clk_ext_buf;
+
+        -- External reference feedback buffer
+        cmp_clk_ext_buf_fb : BUFG
+          port map (
+            O => clk_ext_fbi,
+            I => clk_ext_fbo);
+
+        -- External reference output buffer
+        cmp_clk_ext_buf_o : BUFG
+          port map (
+            O => ext_ref_mul_o,
+            I => clk_ext_mul);
+
+        cmp_extend_ext_reset : gc_extend_pulse
+          generic map (
+            g_width => 1000)
+          port map (
+            clk_i      => clk_sys_out,
+            rst_n_i    => pll_sys_locked,
+            pulse_i    => ext_ref_rst_i,
+            extended_o => pll_ext_rst);
+
+      end generate gen_kintex7_ext_ref_pll;
+
+    end generate gen_kintex7_default_plls;
+
+    ---------------------------------------------------------------------------
+    --   Artix7 PLLs
+    ---------------------------------------------------------------------------
+    gen_artix7_default_plls : if (g_fpga_family = "artix7") generate
+
+      signal clk_sys          : std_logic;
+      signal clk_sys_out      : std_logic;
+      signal clk_sys_fb       : std_logic;
+      signal pll_sys_locked   : std_logic;
+      signal clk_dmtd         : std_logic := '0'; -- initialize for simulation
+--      signal clk_dmtd_fb      : std_logic;
+--      signal pll_dmtd_locked  : std_logic;
+--      signal clk_20m_vcxo_buf : std_logic;
+
+    begin
+      -- System PLL (125 MHz -> 62.5 MHz)
+      cmp_sys_clk_pll : MMCME2_ADV
+        generic map (
+          BANDWIDTH            => "OPTIMIZED",
+          CLKOUT4_CASCADE      => false,
+          COMPENSATION         => "ZHOLD",
+          STARTUP_WAIT         => false,
+          DIVCLK_DIVIDE        => 1,
+          CLKFBOUT_MULT_F      => 8.000,     -- 125 MHz x 8.
+          CLKFBOUT_PHASE       => 0.000,
+          CLKFBOUT_USE_FINE_PS => false,
+
+          CLKOUT0_DIVIDE_F    => 16.000,     -- 62.5 MHz sys clock
+          CLKOUT0_PHASE       => 0.000,
+          CLKOUT0_DUTY_CYCLE  => 0.500,
+          CLKOUT0_USE_FINE_PS => false,
+
+          CLKIN1_PERIOD => 8.000,            -- 8 ns means 125 MHz
+          REF_JITTER1   => 0.010)
+        port map (
+          -- Output clocks
+          CLKFBOUT     => clk_sys_fb,
+          CLKOUT0      => clk_sys,
+          -- Input clock control
+          CLKFBIN      => clk_sys_fb,
+          CLKIN1       => clk_125m_pllref_buf,
+          CLKIN2       => '0',
+          -- Tied to always select the primary input clock
+          CLKINSEL     => '1',
+          -- Ports for dynamic reconfiguration
+          DADDR        => (others => '0'),
+          DCLK         => '0',
+          DEN          => '0',
+          DI           => (others => '0'),
+          DO           => open,
+          DRDY         => open,
+          DWE          => '0',
+          -- Ports for dynamic phase shift
+          PSCLK        => '0',
+          PSEN         => '0',
+          PSINCDEC     => '0',
+          PSDONE       => open,
+          -- Other control and status signals
+          LOCKED       => pll_sys_locked,
+          CLKINSTOPPED => open,
+          CLKFBSTOPPED => open,
+          PWRDWN       => '0',
+          RST          => pll_arst);
+
+      -- System PLL output clock buffer
+      cmp_clk_sys_buf_o : BUFG
+      port map (
+        I => clk_sys,
+        O => clk_sys_out);
+
+      clk_62m5_sys_o <= clk_sys_out;
+--      pll_locked_o   <= pll_dmtd_locked and pll_sys_locked;
+      pll_locked_o   <= pll_sys_locked;
+
+--      -- DMTD PLL (20 MHz -> ~62,5 MHz)
+--      cmp_dmtd_clk_pll : MMCME2_ADV
+--        generic map (
+--          BANDWIDTH            => "OPTIMIZED",
+--          CLKOUT4_CASCADE      => false,
+--          COMPENSATION         => "ZHOLD",
+--          STARTUP_WAIT         => false,
+--          DIVCLK_DIVIDE        => 1,
+--          CLKFBOUT_MULT_F      => 50.000,    -- 20 MHz -> 1 GHz
+--          CLKFBOUT_PHASE       => 0.000,
+--          CLKFBOUT_USE_FINE_PS => false,
+--          CLKOUT0_DIVIDE_F     => 16.000,    -- 1GHz/16 -> 62.5 MHz
+--          CLKOUT0_PHASE        => 0.000,
+--          CLKOUT0_DUTY_CYCLE   => 0.500,
+--          CLKOUT0_USE_FINE_PS  => false,
+--          CLKOUT1_DIVIDE       => 16,        -- 1GHz/16 -> 62.5 MHz
+--          CLKOUT1_PHASE        => 0.000,
+--          CLKOUT1_DUTY_CYCLE   => 0.500,
+--          CLKOUT1_USE_FINE_PS  => false,
+--          CLKIN1_PERIOD        => 50.000,    -- 50ns for 20 MHz
+--          REF_JITTER1          => 0.010)
+--        port map (
+--          -- Output clocks
+--          CLKFBOUT     => clk_dmtd_fb,
+--          CLKOUT0      => clk_dmtd,
+--          -- Input clock control
+--          CLKFBIN      => clk_dmtd_fb,
+--          CLKIN1       => clk_20m_vcxo_buf,
+--          CLKIN2       => '0',
+--          -- Tied to always select the primary input clock
+--          CLKINSEL     => '1',
+--          -- Ports for dynamic reconfiguration
+--          DADDR        => (others => '0'),
+--          DCLK         => '0',
+--          DEN          => '0',
+--          DI           => (others => '0'),
+--          DO           => open,
+--          DRDY         => open,
+--          DWE          => '0',
+--          -- Ports for dynamic phase shift
+--          PSCLK        => '0',
+--          PSEN         => '0',
+--          PSINCDEC     => '0',
+--          PSDONE       => open,
+--          -- Other control and status signals
+--          LOCKED       => pll_dmtd_locked,
+--          CLKINSTOPPED => open,
+--          CLKFBSTOPPED => open,
+--          PWRDWN       => '0',
+--          RST          => pll_arst);
+--
+--      -- DMTD PLL input clock buffer
+--      cmp_clk_dmtd_buf_i : BUFG
+--        port map (
+--          O => clk_20m_vcxo_buf,
+--          I => clk_20m_vcxo_i);
+--
+
+      -- DMTD Div2 (124.9920 MHz -> 62,496 MHz)
+      process(clk_125m_dmtd_i)
+      begin
+        if rising_edge(clk_125m_dmtd_i) then
+          clk_dmtd <= not clk_dmtd;
+        end if;
+      end process;
+
+      -- DMTD PLL output clock buffer
+      cmp_clk_dmtd_buf_o : BUFG
+        port map (
+          O => clk_62m5_dmtd_o,
+          I => clk_dmtd);
+
+      -- External 10MHz reference PLL for Artix7
+      gen_artix7_ext_ref_pll : if (g_with_external_clock_input = TRUE) generate
+        
+        signal clk_ext_fbi : std_logic;
+        signal clk_ext_fbo : std_logic;
+        signal clk_ext_buf : std_logic;
+        signal clk_ext_mul : std_logic;
+        signal pll_ext_rst : std_logic;
+
+      begin
+        mmcm_adv_inst : MMCME2_ADV
+          generic map (
+            BANDWIDTH            => "OPTIMIZED",
+            CLKOUT4_CASCADE      => FALSE,
+            COMPENSATION         => "ZHOLD",
+            STARTUP_WAIT         => FALSE,
+            DIVCLK_DIVIDE        => 1,
+            CLKFBOUT_MULT_F      => 62.500,
+            CLKFBOUT_PHASE       => 0.000,
+            CLKFBOUT_USE_FINE_PS => FALSE,
+            CLKOUT0_DIVIDE_F     => 10.000,
+            CLKOUT0_PHASE        => 0.000,
+            CLKOUT0_DUTY_CYCLE   => 0.500,
+            CLKOUT0_USE_FINE_PS  => FALSE,
+            CLKIN1_PERIOD        => 100.000,
+            REF_JITTER1          => 0.005)
+          port map (
+            -- Output clocks
+            CLKFBOUT  => clk_ext_fbo,
+            CLKOUT0   => clk_ext_mul,
+            -- Input clock control
+            CLKFBIN   => clk_ext_fbi,
+            CLKIN1    => clk_ext_buf,
+            CLKIN2    => '0',
+            -- Tied to always select the primary input clock
+            CLKINSEL  => '1',
+            -- Ports for dynamic reconfiguration
+            DADDR     => (others => '0'),
+            DCLK      => '0',
+            DEN       => '0',
+            DI        => (others => '0'),
+            DO        => open,
+            DRDY      => open,
+            DWE       => '0',
+            -- Ports for dynamic phase shift
+            PSCLK     => '0',
+            PSEN      => '0',
+            PSINCDEC  => '0',
+            PSDONE    => open, -- Other control and status signals
+            LOCKED    => ext_ref_mul_locked_o,
+            CLKINSTOPPED => ext_ref_mul_stopped_o,
+            CLKFBSTOPPED => open,
+            PWRDWN   => '0',
+            RST      => pll_ext_rst);
+
+        -- External reference input buffer
+        cmp_clk_ext_buf_i : BUFG
+          port map (
+            O => clk_ext_buf,
+            I => clk_10m_ext_i);
+
+        clk_10m_ext_o <= clk_ext_buf;
+
+        -- External reference feedback buffer
+        cmp_clk_ext_buf_fb : BUFG
+          port map (
+            O => clk_ext_fbi,
+            I => clk_ext_fbo);
+
+        -- External reference output buffer
+        cmp_clk_ext_buf_o : BUFG
+          port map (
+            O => ext_ref_mul_o,
+            I => clk_ext_mul);
+
+        cmp_extend_ext_reset : gc_extend_pulse
+          generic map (
+            g_width => 1000)
+          port map (
+            clk_i      => clk_sys_out,
+            rst_n_i    => pll_sys_locked,
+            pulse_i    => ext_ref_rst_i,
+            extended_o => pll_ext_rst);
+
+      end generate gen_artix7_ext_ref_pll;
+
+    end generate gen_artix7_default_plls;
+    ---------------------------------------------------------------------------
+    
+    gen_no_ext_ref_pll : if (g_with_external_clock_input = FALSE) generate
+      clk_10m_ext_o         <= '0';
+      ext_ref_mul_o         <= '0';
+      ext_ref_mul_locked_o  <= '1';
+      ext_ref_mul_stopped_o <= '1';
+    end generate gen_no_ext_ref_pll;
+
+  end generate gen_default_plls;
+
+  -- If external PLLs are used, just copy clock inputs to outputs
+  gen_custom_plls : if (g_use_default_plls = FALSE) generate
+
+    clk_62m5_sys_o  <= clk_62m5_sys_i;
+    clk_62m5_dmtd_o <= clk_62m5_dmtd_i;
+    clk_125m_ref_o  <= clk_125m_ref_i;
+
+    pll_locked_o     <= clk_sys_locked_i and clk_dmtd_locked_i;
+    clk_ref_locked_o <= clk_ref_locked_i;
+
+    ext_ref_mul_o         <= clk_125m_ext_i;
+    ext_ref_mul_locked_o  <= clk_ext_locked_i;
+    ext_ref_mul_stopped_o <= clk_ext_stopped_i;
+
+  end generate gen_custom_plls;
+
+  -- always pass ext reference reset input to output, even when not used
+  clk_ext_rst_o <= ext_ref_rst_i;
+
+  -----------------------------------------------------------------------------
+  -- Transceiver PHY
+  -----------------------------------------------------------------------------
+
+  gen_phy_spartan6 : if(g_fpga_family = "spartan6") generate
+
+    signal clk_125m_gtp_buf : std_logic;
+
+    signal ch0_phy8_out, ch1_phy8_out : t_phy_8bits_to_wrc;
+
+    signal ch0_sfp_txn, ch0_sfp_txp : std_logic;
+    signal ch1_sfp_txn, ch1_sfp_txp : std_logic;
+    signal ch0_sfp_rxn, ch0_sfp_rxp : std_logic;
+    signal ch1_sfp_rxn, ch1_sfp_rxp : std_logic;
+
+  begin
+
+    cmp_ibufgds_gtp : IBUFGDS
+      generic map (
+        DIFF_TERM    => TRUE,
+        IBUF_LOW_PWR => TRUE,
+        IOSTANDARD   => "DEFAULT")
+      port map (
+        O  => clk_125m_gtp_buf,
+        I  => clk_125m_gtp_p_i,
+        IB => clk_125m_gtp_n_i);
+
+
+    cmp_gtp : wr_gtp_phy_spartan6
+      generic map (
+        g_simulation => g_simulation,
+        g_enable_ch0 => g_gtp_enable_ch0,
+        g_enable_ch1 => g_gtp_enable_ch1)
+      port map (
+        gtp_clk_i          => clk_125m_gtp_buf,
+        ch0_ref_clk_i      => clk_125m_pllref_buf,
+        ch0_tx_data_i      => phy8_i.tx_data,
+        ch0_tx_k_i         => phy8_i.tx_k(0),
+        ch0_tx_disparity_o => ch0_phy8_out.tx_disparity,
+        ch0_tx_enc_err_o   => ch0_phy8_out.tx_enc_err,
+        ch0_rx_data_o      => ch0_phy8_out.rx_data,
+        ch0_rx_rbclk_o     => ch0_phy8_out.rx_clk,
+        ch0_rx_k_o         => ch0_phy8_out.rx_k(0),
+        ch0_rx_enc_err_o   => ch0_phy8_out.rx_enc_err,
+        ch0_rx_bitslide_o  => ch0_phy8_out.rx_bitslide,
+        ch0_rst_i          => phy8_i.rst,
+        ch0_loopen_i       => phy8_i.loopen,
+        ch0_loopen_vec_i   => phy8_i.loopen_vec,
+        ch0_tx_prbs_sel_i  => phy8_i.tx_prbs_sel,
+        ch0_rdy_o          => ch0_phy8_out.rdy,
+        ch1_ref_clk_i      => clk_125m_pllref_buf,
+        ch1_tx_data_i      => phy8_i.tx_data,
+        ch1_tx_k_i         => phy8_i.tx_k(0),
+        ch1_tx_disparity_o => ch1_phy8_out.tx_disparity,
+        ch1_tx_enc_err_o   => ch1_phy8_out.tx_enc_err,
+        ch1_rx_data_o      => ch1_phy8_out.rx_data,
+        ch1_rx_rbclk_o     => ch1_phy8_out.rx_clk,
+        ch1_rx_k_o         => ch1_phy8_out.rx_k(0),
+        ch1_rx_enc_err_o   => ch1_phy8_out.rx_enc_err,
+        ch1_rx_bitslide_o  => ch1_phy8_out.rx_bitslide,
+        ch1_rst_i          => phy8_i.rst,
+        ch1_loopen_i       => phy8_i.loopen,
+        ch1_loopen_vec_i   => phy8_i.loopen_vec,
+        ch1_tx_prbs_sel_i  => phy8_i.tx_prbs_sel,
+        ch1_rdy_o          => ch1_phy8_out.rdy,
+        pad_txn0_o         => ch0_sfp_txn,
+        pad_txp0_o         => ch0_sfp_txp,
+        pad_rxn0_i         => ch0_sfp_rxn,
+        pad_rxp0_i         => ch0_sfp_rxp,
+        pad_txn1_o         => ch1_sfp_txn,
+        pad_txp1_o         => ch1_sfp_txp,
+        pad_rxn1_i         => ch1_sfp_rxn,
+        pad_rxp1_i         => ch1_sfp_rxp
+        );
+
+    gen_gtp_ch0 : if (g_gtp_enable_ch0 = 1) generate
+      ch0_phy8_out.ref_clk      <= clk_125m_pllref_buf;
+      ch0_phy8_out.sfp_tx_fault <= sfp_tx_fault_i;
+      ch0_phy8_out.sfp_los      <= sfp_los_i;
+      phy8_o                    <= ch0_phy8_out;
+      sfp_txp_o                 <= ch0_sfp_txp;
+      sfp_txn_o                 <= ch0_sfp_txn;
+      ch0_sfp_rxp               <= sfp_rxp_i;
+      ch0_sfp_rxn               <= sfp_rxn_i;
+    end generate gen_gtp_ch0;
+
+    gen_gtp_ch1 : if (g_gtp_enable_ch1 = 1) generate
+      ch1_phy8_out.ref_clk      <= clk_125m_pllref_buf;
+      ch1_phy8_out.sfp_tx_fault <= sfp_tx_fault_i;
+      ch1_phy8_out.sfp_los      <= sfp_los_i;
+      phy8_o                    <= ch1_phy8_out;
+      sfp_txp_o                 <= ch1_sfp_txp;
+      sfp_txn_o                 <= ch1_sfp_txn;
+      ch1_sfp_rxp               <= sfp_rxp_i;
+      ch1_sfp_rxn               <= sfp_rxn_i;
+    end generate gen_gtp_ch1;
+
+    sfp_tx_disable_o <= phy8_i.sfp_tx_disable;
+
+    phy16_o <= c_dummy_phy16_to_wrc;
+
+  end generate gen_phy_spartan6;
+
+  ---------------------------------------------------------------------------
+  --   Kintex7 PHY
+  ---------------------------------------------------------------------------
+
+  gen_phy_kintex7 : if (g_fpga_family = "kintex7") generate
+
+    signal clk_ref          : std_logic;
+    signal clk_125m_gtx_buf : std_logic;
+    signal clk_ref_locked   : std_logic;
+
+  begin
+
+    gen_ibufgds: if (g_use_ibufgds=true) generate
+    begin
+      -- Dedicated GTX clock.
+      cmp_gtp_dedicated_clk : IBUFDS_GTE2
+        generic map(
+          CLKCM_CFG    => true,
+          CLKRCV_TRST  => true,
+          CLKSWING_CFG => "11")
+        port map (
+          O     => clk_125m_gtx_buf,
+          ODIV2 => open,
+          CEB   => '0',
+          I     => clk_125m_gtp_p_i,
+          IB    => clk_125m_gtp_n_i);
+    end generate gen_ibufgds;
+
+    gen_no_ibufgds: if (g_use_ibufgds=false) generate
+    begin
+      clk_125m_gtx_buf <= clk_125m_gtp_p_i;
+    end generate gen_no_ibufgds;
+
+
+    -- System PLL input clock buffer
+    cmp_clk_sys_buf_i : BUFG
+      port map (
+        I => clk_125m_gtx_buf,
+        O => clk_125m_pllref_buf);
+
+    cmp_gtx: wr_gtx_phy_family7
+      generic map(
+        g_simulation => g_simulation)
+      port map(
+        clk_gtx_i      => clk_125m_gtx_buf,
+        tx_out_clk_o   => clk_ref,
+        tx_data_i      => phy16_i.tx_data,
+        tx_k_i         => phy16_i.tx_k,
+        tx_disparity_o => phy16_o.tx_disparity,
+        tx_enc_err_o   => phy16_o.tx_enc_err,
+        rx_rbclk_o     => phy16_o.rx_clk,
+        rx_data_o      => phy16_o.rx_data,
+        rx_k_o         => phy16_o.rx_k,
+        rx_enc_err_o   => phy16_o.rx_enc_err,
+        rx_bitslide_o  => phy16_o.rx_bitslide,
+        rst_i          => phy16_i.rst,
+        loopen_i       => phy16_i.loopen_vec,
+        tx_prbs_sel_i  => phy16_i.tx_prbs_sel,
+        rdy_o          => phy16_o.rdy,
+
+        pad_txn_o => sfp_txn_o,
+        pad_txp_o => sfp_txp_o,
+        pad_rxn_i => sfp_rxn_i,
+        pad_rxp_i => sfp_rxp_i,
+
+        tx_locked_o   => clk_ref_locked);
+
+    clk_125m_ref_o       <= clk_ref;
+    clk_ref_locked_o     <= clk_ref_locked;
+    phy16_o.ref_clk      <= clk_ref;
+    phy16_o.sfp_tx_fault <= sfp_tx_fault_i;
+    phy16_o.sfp_los      <= sfp_los_i;
+    sfp_tx_disable_o     <= phy16_i.sfp_tx_disable;
+
+    phy8_o <= c_dummy_phy8_to_wrc;
+
+  end generate gen_phy_kintex7;
+
+  ---------------------------------------------------------------------------
+  --   Artix7 PHY
+  ---------------------------------------------------------------------------
+
+  gen_phy_artix7 : if (g_fpga_family = "artix7") generate
+
+    signal clk_ref          : std_logic;
+    signal clk_125m_gtp_buf : std_logic;
+    signal clk_ref_locked   : std_logic;
+
+  begin
+
+    -- Dedicated GTP clock.
+    cmp_gtp_dedicated_clk : IBUFDS_GTE2
+      generic map(
+        CLKCM_CFG    => true,
+        CLKRCV_TRST  => true,
+        CLKSWING_CFG => "11")
+      port map (
+        O     => clk_125m_gtp_buf,
+        ODIV2 => open,
+        CEB   => '0',
+        I     => clk_125m_gtp_p_i,
+        IB    => clk_125m_gtp_n_i);
+
+    -- System PLL input clock buffer
+    cmp_clk_sys_buf_i : BUFG
+      port map (
+        I => clk_125m_gtp_buf,
+        O => clk_125m_pllref_buf);
+
+    cmp_gtp: wr_gtp_phy_family7
+      generic map(
+        g_simulation => g_simulation)
+      port map(
+        clk_gtp_i      => clk_125m_gtp_buf,
+        tx_out_clk_o   => clk_ref,
+        tx_data_i      => phy16_i.tx_data,
+        tx_k_i         => phy16_i.tx_k,
+        tx_disparity_o => phy16_o.tx_disparity,
+        tx_enc_err_o   => phy16_o.tx_enc_err,
+        rx_rbclk_o     => phy16_o.rx_clk,
+        rx_data_o      => phy16_o.rx_data,
+        rx_k_o         => phy16_o.rx_k,
+        rx_enc_err_o   => phy16_o.rx_enc_err,
+        rx_bitslide_o  => phy16_o.rx_bitslide,
+        rst_i          => phy16_i.rst,
+        loopen_i       => phy16_i.loopen_vec,
+        tx_prbs_sel_i  => phy16_i.tx_prbs_sel,
+        rdy_o          => phy16_o.rdy,
+
+        pad_txn_o => sfp_txn_o,
+        pad_txp_o => sfp_txp_o,
+        pad_rxn_i => sfp_rxn_i,
+        pad_rxp_i => sfp_rxp_i,
+
+        tx_locked_o   => clk_ref_locked);
+
+    clk_125m_ref_o       <= clk_ref;
+    clk_ref_locked_o     <= clk_ref_locked;
+    phy16_o.ref_clk      <= clk_ref;
+    phy16_o.sfp_tx_fault <= sfp_tx_fault_i;
+    phy16_o.sfp_los      <= sfp_los_i;
+    sfp_tx_disable_o     <= phy16_i.sfp_tx_disable;
+
+    phy8_o <= c_dummy_phy8_to_wrc;
+
+  end generate gen_phy_artix7;
+
+  ---------------------------------------------------------------------------
+
+end architecture rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/source.txt b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/source.txt
new file mode 100644
index 000000000..52c657abc
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/source.txt
@@ -0,0 +1,2 @@
+This directory is a subset of the following tag:
+https://www.ohwr.org/projects/wr-cores/repository?utf8=%E2%9C%93&rev=wrpc-v4.2&branch=master&tag=wrpc-v4.2
diff --git a/fpga/usrp3/lib/wishbone/Makefile.srcs b/fpga/usrp3/lib/wishbone/Makefile.srcs
new file mode 100644
index 000000000..6459de834
--- /dev/null
+++ b/fpga/usrp3/lib/wishbone/Makefile.srcs
@@ -0,0 +1,19 @@
+#
+# Copyright 2010-2012 Ettus Research LLC
+#
+
+##################################################
+# Wishbone Perifs
+##################################################
+WISHBONE_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/wishbone/, \
+simple_uart_rx.v \
+simple_uart_tx.v \
+simple_uart.v \
+wb_1master.v \
+settings_bus.v \
+settings_readback.v \
+i2c_master_top.v \
+i2c_master_bit_ctrl.v \
+i2c_master_byte_ctrl.v \
+axi_stream_to_wb.v \
+))
diff --git a/fpga/usrp3/lib/wishbone/axi_stream_to_wb.v b/fpga/usrp3/lib/wishbone/axi_stream_to_wb.v
new file mode 100644
index 000000000..6add3635a
--- /dev/null
+++ b/fpga/usrp3/lib/wishbone/axi_stream_to_wb.v
@@ -0,0 +1,266 @@
+//
+// Copyright 2012 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+// AXI stream to/from wishbone
+// Input is an axi stream which wites into a BRAM.
+// Output is an axi stream which reads from a BRAM.
+// This RAM can also be accessed from a wishbone interface.
+
+// From the wishbone interface we need to be able to:
+
+// Ask the module if a completed packet is available.
+// Read number of bytes/lines in the BRAM.
+// Release the completed packet.
+
+// Ask the module if an outgoing slot is available.
+// Write number of bytes/lines in the BRAM.
+// Release the completed packet.
+
+module axi_stream_to_wb
+#(
+    parameter AWIDTH = 13, //WB addr width and buffering size in bytes
+    parameter UWIDTH = 4, //stream user width
+    parameter CTRL_ADDR = 0 //ctrl/status register
+)
+(
+    //-- the wishbone interface
+    input clk_i, input rst_i,
+    input we_i, input stb_i, input cyc_i, output reg ack_o,
+    input [AWIDTH-1:0] adr_i, input [31:0] dat_i, output reg [31:0] dat_o,
+
+    //-- the axi stream interface input
+    input [63:0] rx_tdata,
+    input [3:0] rx_tuser,
+    input rx_tlast,
+    input rx_tvalid,
+    output rx_tready,
+
+    //-- the axi stream interface output
+    output [63:0] tx_tdata,
+    output [3:0] tx_tuser,
+    output tx_tlast,
+    output tx_tvalid,
+    input tx_tready,
+
+    output [31:0] debug_rx,
+    output [31:0] debug_tx
+);
+
+    reg stb_i_del;
+    always @(posedge clk_i) begin
+        if (rst_i) stb_i_del <= 0;
+        else stb_i_del <= stb_i;
+    end
+
+    reg ack_o_del;
+    always @(posedge clk_i) begin
+        if (rst_i)  ack_o_del <= 0;
+        else        ack_o_del <= ack_o;
+    end
+
+    //drive the ack signal
+    always @(posedge clk_i) begin
+        if (rst_i)      ack_o <= 0;
+        else if (we_i)  ack_o <= stb_i & ~ack_o;
+        else            ack_o <= stb_i & stb_i_del & ~ack_o & ~ack_o_del;
+    end
+
+    //control registers, status
+    reg [AWIDTH-1:0] tx_bytes, rx_bytes;
+    reg tx_error, rx_error;
+    wire rx_state_flag, tx_state_flag;
+    reg rx_proc_flag, tx_proc_flag;
+
+    //assign status
+    wire [31:0] status;
+    assign status[31] = rx_state_flag;
+    assign status[30] = tx_state_flag;
+    assign status[29] = rx_error;
+    assign status[AWIDTH-1:0] = rx_bytes;
+
+   // Create some piplining to break timing paths.
+   reg 		ctrl_addressed;
+   always @(posedge clk_i)
+     if (rst_i)
+       ctrl_addressed <= 1'b0;
+     else if(adr_i == CTRL_ADDR)
+       ctrl_addressed <= 1'b1;
+     else
+       ctrl_addressed <= 1'b0;
+       
+    //assign control
+    always @(posedge clk_i) begin
+        if (rst_i) begin
+            rx_proc_flag <= 0;
+            tx_proc_flag <= 0;
+            tx_error <= 0;
+            tx_bytes <= 0;
+        end
+        else if (we_i && ack_o && ctrl_addressed) begin
+            rx_proc_flag <= dat_i[31];
+            tx_proc_flag <= dat_i[30];
+            tx_error <= dat_i[29];
+            tx_bytes <= dat_i[AWIDTH-1:0];
+        end
+    end
+
+    //------------------------------------------------------------------
+    //-- block ram interface between wb and input stream
+    //------------------------------------------------------------------
+    reg [AWIDTH-4:0] rx_counter;
+    wire [63:0] rx_bram_data64;
+    ram_2port #(.DWIDTH(64), .AWIDTH(AWIDTH-3)) input_stream_bram
+    (
+        .clka(clk_i), .ena(rx_tready), .wea(rx_tvalid),
+        .addra(rx_counter), .dia(rx_tdata), .doa(),
+        .clkb(clk_i), .enb(stb_i), .web(1'b0),
+        .addrb(adr_i[AWIDTH-1:3]), .dib({64{1'b1}}), .dob(rx_bram_data64)
+    );
+
+    //select the data source, status, or upper/lower 32 from bram
+    wire [31:0] dat_o_pipeline;
+    assign dat_o_pipeline = ctrl_addressed ? status : ((!adr_i[2])? rx_bram_data64[63:32]: rx_bram_data64[31:0]);
+    always @(posedge clk_i) begin
+        dat_o <= dat_o_pipeline;
+    end
+
+    //------------------------------------------------------------------
+    //-- block ram interface between wb and output stream
+    //------------------------------------------------------------------
+    reg [AWIDTH-4:0] tx_counter;
+    wire enb_out;
+    wire [63:0] tx_bram_data64;
+    ram_2port #(.DWIDTH(64), .AWIDTH(AWIDTH-3)) output_stream_bram
+    (
+        .clka(clk_i), .ena(enb_out), .wea(1'b0),
+        .addra(tx_counter), .dia({64{1'b1}}), .doa(tx_tdata),
+        .clkb(clk_i), .enb(stb_i), .web(we_i && adr_i[2]),
+        .addrb(adr_i[AWIDTH-1:3]), .dib(tx_bram_data64), .dob()
+    );
+
+    //write 64 bit chunks, so register the lower write
+    reg [31:0] dat_i_reg;
+    always @(posedge clk_i) begin
+        if (we_i && stb_i && !adr_i[2]) dat_i_reg <= dat_i;
+    end
+    assign tx_bram_data64 = {dat_i_reg, dat_i};
+
+    //------------------------------------------------------------------
+    //-- state machine to drive input stream
+    //------------------------------------------------------------------
+    localparam RX_STATE_READY = 0; //waits for proc flag 0
+    localparam RX_STATE_WRITE = 1; //writes stream to bram
+    localparam RX_STATE_RELEASE = 2; //waits for proc to flag 1
+    reg [1:0] rx_state;
+
+    always @(posedge clk_i) begin
+        if (rst_i) begin
+            rx_state <= RX_STATE_READY;
+            rx_counter <= 0;
+            rx_error <= 0;
+            rx_bytes <= 0;
+        end
+        else case (rx_state)
+
+        RX_STATE_READY: begin
+            if (!rx_proc_flag) rx_state <= RX_STATE_WRITE;
+            rx_counter <= 0;
+        end
+
+        RX_STATE_WRITE: begin
+            if (rx_tready && rx_tvalid) begin
+                rx_counter <= rx_counter + 1'b1;
+                if (rx_tlast) begin
+                    rx_state <= RX_STATE_RELEASE;
+                    rx_bytes <= {rx_counter + 1'b1, rx_tuser[2:0]};
+                    rx_error <= rx_tuser[3];
+                end
+            end
+        end
+
+        RX_STATE_RELEASE: begin
+            if (rx_proc_flag) rx_state <= RX_STATE_READY;
+            rx_counter <= 0;
+        end
+
+        default: rx_state <= RX_STATE_READY;
+        endcase //rx_state
+    end
+
+    //flag tells the processor when it can grab some input buffer
+    assign rx_state_flag = (rx_state == RX_STATE_RELEASE);
+
+    //always ready to accept input data in the write state
+    assign rx_tready = (rx_state == RX_STATE_WRITE);
+
+    //------------------------------------------------------------------
+    //-- state machine to drive output stream
+    //------------------------------------------------------------------
+    localparam TX_STATE_READY = 0;  //waits for proc flag 0
+    localparam TX_STATE_WRITE = 1; //writes bram to stream
+    localparam TX_STATE_RELEASE = 2; //waits for proc to flag 1
+    reg [1:0] tx_state;
+
+    always @(posedge clk_i) begin
+        if (rst_i) begin
+            tx_state <= TX_STATE_READY;
+            tx_counter <= 0;
+        end
+        else case (tx_state)
+
+        TX_STATE_READY: begin
+            if (tx_proc_flag) begin
+                tx_state <= TX_STATE_WRITE;
+                tx_counter <= 1;
+            end
+            else tx_counter <= 0;
+        end
+
+        TX_STATE_WRITE: begin
+            if (tx_tready && tx_tvalid) begin
+                tx_counter <= tx_counter + 1'b1;
+                if (tx_tlast) begin
+                    tx_state <= TX_STATE_RELEASE;
+                end
+            end
+        end
+
+        TX_STATE_RELEASE: begin
+            if (!tx_proc_flag) tx_state <= TX_STATE_READY;
+            tx_counter <= 0;
+        end
+
+        default: tx_state <= TX_STATE_READY;
+        endcase //tx_state
+    end
+
+    //flag tells the processor when it can grab available out buffer
+    assign tx_state_flag = (tx_state == TX_STATE_READY);
+
+    //the output user bus assignment (non-zero only at end)
+    assign tx_tuser = (tx_tlast)? {tx_error, tx_bytes[2:0]} : 4'b0;
+
+    //end of frame signal
+    assign tx_tlast = (tx_counter == tx_bytes[AWIDTH-1:3]);
+
+    //output is always valid in state write
+    assign tx_tvalid = (tx_state == TX_STATE_WRITE);
+
+    //enable the read so we can pre-read due to read 1 cycle delay
+    assign enb_out = (tx_state == TX_STATE_WRITE)? (tx_tvalid && tx_tready) : 1'b1;
+
+    assign debug_rx = {
+        rx_state, rx_tlast, rx_tvalid, rx_tready, rx_tuser[2:0], //8
+        rx_proc_flag, rx_state_flag, rx_tdata[21:0] //24
+    };
+    assign debug_tx = {
+        tx_state, tx_tlast, tx_tvalid, tx_tready, tx_tuser[2:0], //8
+        tx_proc_flag, tx_state_flag, tx_tdata[21:0] //24
+    };
+
+endmodule //axi_stream_to_wb
diff --git a/fpga/usrp3/lib/wishbone/i2c_master_bit_ctrl.v b/fpga/usrp3/lib/wishbone/i2c_master_bit_ctrl.v
new file mode 100644
index 000000000..68ec27004
--- /dev/null
+++ b/fpga/usrp3/lib/wishbone/i2c_master_bit_ctrl.v
@@ -0,0 +1,538 @@
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  WISHBONE rev.B2 compliant I2C Master bit-controller        ////
+////                                                             ////
+////                                                             ////
+////  Author: Richard Herveille                                  ////
+////          richard@asics.ws                                   ////
+////          www.asics.ws                                       ////
+////                                                             ////
+////  Downloaded from: http://www.opencores.org/projects/i2c/    ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2001 Richard Herveille                        ////
+////                    richard@asics.ws                         ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+//  CVS Log
+//
+//  $Id: i2c_master_bit_ctrl.v,v 1.12 2006/09/04 09:08:13 rherveille Exp $
+//
+//  $Date: 2006/09/04 09:08:13 $
+//  $Revision: 1.12 $
+//  $Author: rherveille $
+//  $Locker:  $
+//  $State: Exp $
+//
+// Change History:
+//               $Log: i2c_master_bit_ctrl.v,v $
+//               Revision 1.12  2006/09/04 09:08:13  rherveille
+//               fixed short scl high pulse after clock stretch
+//               fixed slave model not returning correct '(n)ack' signal
+//
+//               Revision 1.11  2004/05/07 11:02:26  rherveille
+//               Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.
+//
+//               Revision 1.10  2003/08/09 07:01:33  rherveille
+//               Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
+//               Fixed a potential bug in the byte controller's host-acknowledge generation.
+//
+//               Revision 1.9  2003/03/10 14:26:37  rherveille
+//               Fixed cmd_ack generation item (no bug).
+//
+//               Revision 1.8  2003/02/05 00:06:10  rherveille
+//               Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.
+//
+//               Revision 1.7  2002/12/26 16:05:12  rherveille
+//               Small code simplifications
+//
+//               Revision 1.6  2002/12/26 15:02:32  rherveille
+//               Core is now a Multimaster I2C controller
+//
+//               Revision 1.5  2002/11/30 22:24:40  rherveille
+//               Cleaned up code
+//
+//               Revision 1.4  2002/10/30 18:10:07  rherveille
+//               Fixed some reported minor start/stop generation timing issuess.
+//
+//               Revision 1.3  2002/06/15 07:37:03  rherveille
+//               Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
+//
+//               Revision 1.2  2001/11/05 11:59:25  rherveille
+//               Fixed wb_ack_o generation bug.
+//               Fixed bug in the byte_controller statemachine.
+//               Added headers.
+//
+
+//
+/////////////////////////////////////
+// Bit controller section
+/////////////////////////////////////
+//
+// Translate simple commands into SCL/SDA transitions
+// Each command has 5 states, A/B/C/D/idle
+//
+// start:	SCL	~~~~~~~~~~\____
+//	SDA	~~~~~~~~\______
+//		 x | A | B | C | D | i
+//
+// repstart	SCL	____/~~~~\___
+//	SDA	__/~~~\______
+//		 x | A | B | C | D | i
+//
+// stop	SCL	____/~~~~~~~~
+//	SDA	==\____/~~~~~
+//		 x | A | B | C | D | i
+//
+//- write	SCL	____/~~~~\____
+//	SDA	==X=========X=
+//		 x | A | B | C | D | i
+//
+//- read	SCL	____/~~~~\____
+//	SDA	XXXX=====XXXX
+//		 x | A | B | C | D | i
+//
+
+// Timing:     Normal mode      Fast mode
+///////////////////////////////////////////////////////////////////////
+// Fscl        100KHz           400KHz
+// Th_scl      4.0us            0.6us   High period of SCL
+// Tl_scl      4.7us            1.3us   Low period of SCL
+// Tsu:sta     4.7us            0.6us   setup time for a repeated start condition
+// Tsu:sto     4.0us            0.6us   setup time for a stop conditon
+// Tbuf        4.7us            1.3us   Bus free time between a stop and start condition
+//
+
+// synopsys translate_off
+//`include "timescale.v"
+// synopsys translate_on
+
+`include "i2c_master_defines.v"
+
+module i2c_master_bit_ctrl(
+	clk, rst, nReset, 
+	clk_cnt, ena, cmd, cmd_ack, busy, al, din, dout,
+	scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen
+	);
+
+	//
+	// inputs & outputs
+	//
+	input clk;
+	input rst;
+	input nReset;
+	input ena;            // core enable signal
+
+	input [15:0] clk_cnt; // clock prescale value
+
+	input  [3:0] cmd;
+	output       cmd_ack; // command complete acknowledge
+	reg cmd_ack;
+	output       busy;    // i2c bus busy
+	reg busy;
+	output       al;      // i2c bus arbitration lost
+	reg al;
+
+	input  din;
+	output dout;
+	reg dout;
+
+	// I2C lines
+	input  scl_i;         // i2c clock line input
+	output scl_o;         // i2c clock line output
+	output scl_oen;       // i2c clock line output enable (active low)
+	reg scl_oen;
+	input  sda_i;         // i2c data line input
+	output sda_o;         // i2c data line output
+	output sda_oen;       // i2c data line output enable (active low)
+	reg sda_oen;
+
+
+	//
+	// variable declarations
+	//
+
+	reg sSCL, sSDA;             // synchronized SCL and SDA inputs
+	reg dscl_oen;               // delayed scl_oen
+	reg sda_chk;                // check SDA output (Multi-master arbitration)
+	reg clk_en;                 // clock generation signals
+	wire slave_wait;
+//	reg [15:0] cnt = clk_cnt;   // clock divider counter (simulation)
+	reg [15:0] cnt;             // clock divider counter (synthesis)
+
+	// state machine variable
+	reg [16:0] c_state; // synopsys enum_state
+
+	//
+	// module body
+	//
+
+	// whenever the slave is not ready it can delay the cycle by pulling SCL low
+	// delay scl_oen
+	always @(posedge clk)
+	  dscl_oen <= #1 scl_oen;
+
+	assign slave_wait = dscl_oen && !sSCL;
+
+
+	// generate clk enable signal
+	always @(posedge clk or negedge nReset)
+	  if(~nReset)
+	    begin
+	        cnt    <= #1 16'h0;
+	        clk_en <= #1 1'b1;
+	    end
+	  else if (rst)
+	    begin
+	        cnt    <= #1 16'h0;
+	        clk_en <= #1 1'b1;
+	    end
+	  else if ( ~|cnt || !ena)
+	    begin
+	        cnt    <= #1 clk_cnt;
+	        clk_en <= #1 1'b1;
+	    end
+	  else if (slave_wait)
+	    begin
+	        cnt    <= #1 cnt;
+	        clk_en <= #1 1'b0;    
+	    end
+	  else
+	    begin
+	        cnt    <= #1 cnt - 16'h1;
+	        clk_en <= #1 1'b0;
+	    end
+
+
+	// generate bus status controller
+	reg dSCL, dSDA;
+	reg sta_condition;
+	reg sto_condition;
+
+	// synchronize SCL and SDA inputs
+	// reduce metastability risc
+	always @(posedge clk or negedge nReset)
+	  if (~nReset)
+	    begin
+	        sSCL <= #1 1'b1;
+	        sSDA <= #1 1'b1;
+
+	        dSCL <= #1 1'b1;
+	        dSDA <= #1 1'b1;
+	    end
+	  else if (rst)
+	    begin
+	        sSCL <= #1 1'b1;
+	        sSDA <= #1 1'b1;
+
+	        dSCL <= #1 1'b1;
+	        dSDA <= #1 1'b1;
+	    end
+	  else
+	    begin
+	        sSCL <= #1 scl_i;
+	        sSDA <= #1 sda_i;
+
+	        dSCL <= #1 sSCL;
+	        dSDA <= #1 sSDA;
+	    end
+
+	// detect start condition => detect falling edge on SDA while SCL is high
+	// detect stop condition => detect rising edge on SDA while SCL is high
+	always @(posedge clk or negedge nReset)
+	  if (~nReset)
+	    begin
+	        sta_condition <= #1 1'b0;
+	        sto_condition <= #1 1'b0;
+	    end
+	  else if (rst)
+	    begin
+	        sta_condition <= #1 1'b0;
+	        sto_condition <= #1 1'b0;
+	    end
+	  else
+	    begin
+	        sta_condition <= #1 ~sSDA &  dSDA & sSCL;
+	        sto_condition <= #1  sSDA & ~dSDA & sSCL;
+	    end
+
+	// generate i2c bus busy signal
+	always @(posedge clk or negedge nReset)
+	  if(!nReset)
+	    busy <= #1 1'b0;
+	  else if (rst)
+	    busy <= #1 1'b0;
+	  else
+	    busy <= #1 (sta_condition | busy) & ~sto_condition;
+
+	// generate arbitration lost signal
+	// aribitration lost when:
+	// 1) master drives SDA high, but the i2c bus is low
+	// 2) stop detected while not requested
+	reg cmd_stop;
+	always @(posedge clk or negedge nReset)
+	  if (~nReset)
+	    cmd_stop <= #1 1'b0;
+	  else if (rst)
+	    cmd_stop <= #1 1'b0;
+	  else if (clk_en)
+	    cmd_stop <= #1 cmd == `I2C_CMD_STOP;
+
+	always @(posedge clk or negedge nReset)
+	  if (~nReset)
+	    al <= #1 1'b0;
+	  else if (rst)
+	    al <= #1 1'b0;
+	  else
+	    al <= #1 (sda_chk & ~sSDA & sda_oen) | (|c_state & sto_condition & ~cmd_stop);
+
+
+	// generate dout signal (store SDA on rising edge of SCL)
+	always @(posedge clk)
+	  if(sSCL & ~dSCL)
+	    dout <= #1 sSDA;
+
+	// generate statemachine
+
+	// nxt_state decoder
+	parameter [16:0] idle    = 17'b0_0000_0000_0000_0000;
+	parameter [16:0] start_a = 17'b0_0000_0000_0000_0001;
+	parameter [16:0] start_b = 17'b0_0000_0000_0000_0010;
+	parameter [16:0] start_c = 17'b0_0000_0000_0000_0100;
+	parameter [16:0] start_d = 17'b0_0000_0000_0000_1000;
+	parameter [16:0] start_e = 17'b0_0000_0000_0001_0000;
+	parameter [16:0] stop_a  = 17'b0_0000_0000_0010_0000;
+	parameter [16:0] stop_b  = 17'b0_0000_0000_0100_0000;
+	parameter [16:0] stop_c  = 17'b0_0000_0000_1000_0000;
+	parameter [16:0] stop_d  = 17'b0_0000_0001_0000_0000;
+	parameter [16:0] rd_a    = 17'b0_0000_0010_0000_0000;
+	parameter [16:0] rd_b    = 17'b0_0000_0100_0000_0000;
+	parameter [16:0] rd_c    = 17'b0_0000_1000_0000_0000;
+	parameter [16:0] rd_d    = 17'b0_0001_0000_0000_0000;
+	parameter [16:0] wr_a    = 17'b0_0010_0000_0000_0000;
+	parameter [16:0] wr_b    = 17'b0_0100_0000_0000_0000;
+	parameter [16:0] wr_c    = 17'b0_1000_0000_0000_0000;
+	parameter [16:0] wr_d    = 17'b1_0000_0000_0000_0000;
+
+	always @(posedge clk or negedge nReset)
+	  if (!nReset)
+	    begin
+	        c_state <= #1 idle;
+	        cmd_ack <= #1 1'b0;
+	        scl_oen <= #1 1'b1;
+	        sda_oen <= #1 1'b1;
+	        sda_chk <= #1 1'b0;
+	    end
+	  else if (rst | al)
+	    begin
+	        c_state <= #1 idle;
+	        cmd_ack <= #1 1'b0;
+	        scl_oen <= #1 1'b1;
+	        sda_oen <= #1 1'b1;
+	        sda_chk <= #1 1'b0;
+	    end
+	  else
+	    begin
+	        cmd_ack   <= #1 1'b0; // default no command acknowledge + assert cmd_ack only 1clk cycle
+
+	        if (clk_en)
+	          case (c_state) // synopsys full_case parallel_case
+	            // idle state
+	            idle:
+	            begin
+	                case (cmd) // synopsys full_case parallel_case
+	                  `I2C_CMD_START:
+	                     c_state <= #1 start_a;
+
+	                  `I2C_CMD_STOP:
+	                     c_state <= #1 stop_a;
+
+	                  `I2C_CMD_WRITE:
+	                     c_state <= #1 wr_a;
+
+	                  `I2C_CMD_READ:
+	                     c_state <= #1 rd_a;
+
+	                  default:
+	                    c_state <= #1 idle;
+	                endcase
+
+	                scl_oen <= #1 scl_oen; // keep SCL in same state
+	                sda_oen <= #1 sda_oen; // keep SDA in same state
+	                sda_chk <= #1 1'b0;    // don't check SDA output
+	            end
+
+	            // start
+	            start_a:
+	            begin
+	                c_state <= #1 start_b;
+	                scl_oen <= #1 scl_oen; // keep SCL in same state
+	                sda_oen <= #1 1'b1;    // set SDA high
+	                sda_chk <= #1 1'b0;    // don't check SDA output
+	            end
+
+	            start_b:
+	            begin
+	                c_state <= #1 start_c;
+	                scl_oen <= #1 1'b1; // set SCL high
+	                sda_oen <= #1 1'b1; // keep SDA high
+	                sda_chk <= #1 1'b0; // don't check SDA output
+	            end
+
+	            start_c:
+	            begin
+	                c_state <= #1 start_d;
+	                scl_oen <= #1 1'b1; // keep SCL high
+	                sda_oen <= #1 1'b0; // set SDA low
+	                sda_chk <= #1 1'b0; // don't check SDA output
+	            end
+
+	            start_d:
+	            begin
+	                c_state <= #1 start_e;
+	                scl_oen <= #1 1'b1; // keep SCL high
+	                sda_oen <= #1 1'b0; // keep SDA low
+	                sda_chk <= #1 1'b0; // don't check SDA output
+	            end
+
+	            start_e:
+	            begin
+	                c_state <= #1 idle;
+	                cmd_ack <= #1 1'b1;
+	                scl_oen <= #1 1'b0; // set SCL low
+	                sda_oen <= #1 1'b0; // keep SDA low
+	                sda_chk <= #1 1'b0; // don't check SDA output
+	            end
+
+	            // stop
+	            stop_a:
+	            begin
+	                c_state <= #1 stop_b;
+	                scl_oen <= #1 1'b0; // keep SCL low
+	                sda_oen <= #1 1'b0; // set SDA low
+	                sda_chk <= #1 1'b0; // don't check SDA output
+	            end
+
+	            stop_b:
+	            begin
+	                c_state <= #1 stop_c;
+	                scl_oen <= #1 1'b1; // set SCL high
+	                sda_oen <= #1 1'b0; // keep SDA low
+	                sda_chk <= #1 1'b0; // don't check SDA output
+	            end
+
+	            stop_c:
+	            begin
+	                c_state <= #1 stop_d;
+	                scl_oen <= #1 1'b1; // keep SCL high
+	                sda_oen <= #1 1'b0; // keep SDA low
+	                sda_chk <= #1 1'b0; // don't check SDA output
+	            end
+
+	            stop_d:
+	            begin
+	                c_state <= #1 idle;
+	                cmd_ack <= #1 1'b1;
+	                scl_oen <= #1 1'b1; // keep SCL high
+	                sda_oen <= #1 1'b1; // set SDA high
+	                sda_chk <= #1 1'b0; // don't check SDA output
+	            end
+
+	            // read
+	            rd_a:
+	            begin
+	                c_state <= #1 rd_b;
+	                scl_oen <= #1 1'b0; // keep SCL low
+	                sda_oen <= #1 1'b1; // tri-state SDA
+	                sda_chk <= #1 1'b0; // don't check SDA output
+	            end
+
+	            rd_b:
+	            begin
+	                c_state <= #1 rd_c;
+	                scl_oen <= #1 1'b1; // set SCL high
+	                sda_oen <= #1 1'b1; // keep SDA tri-stated
+	                sda_chk <= #1 1'b0; // don't check SDA output
+	            end
+
+	            rd_c:
+	            begin
+	                c_state <= #1 rd_d;
+	                scl_oen <= #1 1'b1; // keep SCL high
+	                sda_oen <= #1 1'b1; // keep SDA tri-stated
+	                sda_chk <= #1 1'b0; // don't check SDA output
+	            end
+
+	            rd_d:
+	            begin
+	                c_state <= #1 idle;
+	                cmd_ack <= #1 1'b1;
+	                scl_oen <= #1 1'b0; // set SCL low
+	                sda_oen <= #1 1'b1; // keep SDA tri-stated
+	                sda_chk <= #1 1'b0; // don't check SDA output
+	            end
+
+	            // write
+	            wr_a:
+	            begin
+	                c_state <= #1 wr_b;
+	                scl_oen <= #1 1'b0; // keep SCL low
+	                sda_oen <= #1 din;  // set SDA
+	                sda_chk <= #1 1'b0; // don't check SDA output (SCL low)
+	            end
+
+	            wr_b:
+	            begin
+	                c_state <= #1 wr_c;
+	                scl_oen <= #1 1'b1; // set SCL high
+	                sda_oen <= #1 din;  // keep SDA
+	                sda_chk <= #1 1'b1; // check SDA output
+	            end
+
+	            wr_c:
+	            begin
+	                c_state <= #1 wr_d;
+	                scl_oen <= #1 1'b1; // keep SCL high
+	                sda_oen <= #1 din;
+	                sda_chk <= #1 1'b1; // check SDA output
+	            end
+
+	            wr_d:
+	            begin
+	                c_state <= #1 idle;
+	                cmd_ack <= #1 1'b1;
+	                scl_oen <= #1 1'b0; // set SCL low
+	                sda_oen <= #1 din;
+	                sda_chk <= #1 1'b0; // don't check SDA output (SCL low)
+	            end
+
+	          endcase
+	    end
+
+
+	// assign scl and sda output (always gnd)
+	assign scl_o = 1'b0;
+	assign sda_o = 1'b0;
+
+endmodule
diff --git a/fpga/usrp3/lib/wishbone/i2c_master_byte_ctrl.v b/fpga/usrp3/lib/wishbone/i2c_master_byte_ctrl.v
new file mode 100644
index 000000000..784b58188
--- /dev/null
+++ b/fpga/usrp3/lib/wishbone/i2c_master_byte_ctrl.v
@@ -0,0 +1,344 @@
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  WISHBONE rev.B2 compliant I2C Master byte-controller       ////
+////                                                             ////
+////                                                             ////
+////  Author: Richard Herveille                                  ////
+////          richard@asics.ws                                   ////
+////          www.asics.ws                                       ////
+////                                                             ////
+////  Downloaded from: http://www.opencores.org/projects/i2c/    ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2001 Richard Herveille                        ////
+////                    richard@asics.ws                         ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+//  CVS Log
+//
+//  $Id: i2c_master_byte_ctrl.v,v 1.7 2004/02/18 11:40:46 rherveille Exp $
+//
+//  $Date: 2004/02/18 11:40:46 $
+//  $Revision: 1.7 $
+//  $Author: rherveille $
+//  $Locker:  $
+//  $State: Exp $
+//
+// Change History:
+//               $Log: i2c_master_byte_ctrl.v,v $
+//               Revision 1.7  2004/02/18 11:40:46  rherveille
+//               Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command.
+//
+//               Revision 1.6  2003/08/09 07:01:33  rherveille
+//               Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
+//               Fixed a potential bug in the byte controller's host-acknowledge generation.
+//
+//               Revision 1.5  2002/12/26 15:02:32  rherveille
+//               Core is now a Multimaster I2C controller
+//
+//               Revision 1.4  2002/11/30 22:24:40  rherveille
+//               Cleaned up code
+//
+//               Revision 1.3  2001/11/05 11:59:25  rherveille
+//               Fixed wb_ack_o generation bug.
+//               Fixed bug in the byte_controller statemachine.
+//               Added headers.
+//
+
+// synopsys translate_off
+//`include "timescale.v"
+// synopsys translate_on
+
+`include "i2c_master_defines.v"
+
+module i2c_master_byte_ctrl (
+	clk, rst, nReset, ena, clk_cnt, start, stop, read, write, ack_in, din,
+	cmd_ack, ack_out, dout, i2c_busy, i2c_al, scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen );
+
+	//
+	// inputs & outputs
+	//
+	input clk;     // master clock
+	input rst;     // synchronous active high reset
+	input nReset;  // asynchronous active low reset
+	input ena;     // core enable signal
+
+	input [15:0] clk_cnt; // 4x SCL
+
+	// control inputs
+	input       start;
+	input       stop;
+	input       read;
+	input       write;
+	input       ack_in;
+	input [7:0] din;
+
+	// status outputs
+	output       cmd_ack;
+	reg cmd_ack;
+	output       ack_out;
+	reg ack_out;
+	output       i2c_busy;
+	output       i2c_al;
+	output [7:0] dout;
+
+	// I2C signals
+	input  scl_i;
+	output scl_o;
+	output scl_oen;
+	input  sda_i;
+	output sda_o;
+	output sda_oen;
+
+
+	//
+	// Variable declarations
+	//
+
+	// statemachine
+	parameter [4:0] ST_IDLE  = 5'b0_0000;
+	parameter [4:0] ST_START = 5'b0_0001;
+	parameter [4:0] ST_READ  = 5'b0_0010;
+	parameter [4:0] ST_WRITE = 5'b0_0100;
+	parameter [4:0] ST_ACK   = 5'b0_1000;
+	parameter [4:0] ST_STOP  = 5'b1_0000;
+
+	// signals for bit_controller
+	reg  [3:0] core_cmd;
+	reg        core_txd;
+	wire       core_ack, core_rxd;
+
+	// signals for shift register
+	reg [7:0] sr; //8bit shift register
+	reg       shift, ld;
+
+	// signals for state machine
+	wire       go;
+	reg  [2:0] dcnt;
+	wire       cnt_done;
+
+	//
+	// Module body
+	//
+
+	// hookup bit_controller
+	i2c_master_bit_ctrl bit_controller (
+		.clk     ( clk      ),
+		.rst     ( rst      ),
+		.nReset  ( nReset   ),
+		.ena     ( ena      ),
+		.clk_cnt ( clk_cnt  ),
+		.cmd     ( core_cmd ),
+		.cmd_ack ( core_ack ),
+		.busy    ( i2c_busy ),
+		.al      ( i2c_al   ),
+		.din     ( core_txd ),
+		.dout    ( core_rxd ),
+		.scl_i   ( scl_i    ),
+		.scl_o   ( scl_o    ),
+		.scl_oen ( scl_oen  ),
+		.sda_i   ( sda_i    ),
+		.sda_o   ( sda_o    ),
+		.sda_oen ( sda_oen  )
+	);
+
+	// generate go-signal
+	assign go = (read | write | stop) & ~cmd_ack;
+
+	// assign dout output to shift-register
+	assign dout = sr;
+
+	// generate shift register
+	always @(posedge clk or negedge nReset)
+	  if (!nReset)
+	    sr <= #1 8'h0;
+	  else if (rst)
+	    sr <= #1 8'h0;
+	  else if (ld)
+	    sr <= #1 din;
+	  else if (shift)
+	    sr <= #1 {sr[6:0], core_rxd};
+
+	// generate counter
+	always @(posedge clk or negedge nReset)
+	  if (!nReset)
+	    dcnt <= #1 3'h0;
+	  else if (rst)
+	    dcnt <= #1 3'h0;
+	  else if (ld)
+	    dcnt <= #1 3'h7;
+	  else if (shift)
+	    dcnt <= #1 dcnt - 3'h1;
+
+	assign cnt_done = ~(|dcnt);
+
+	//
+	// state machine
+	//
+	reg [4:0] c_state; // synopsis enum_state
+
+	always @(posedge clk or negedge nReset)
+	  if (!nReset)
+	    begin
+	        core_cmd <= #1 `I2C_CMD_NOP;
+	        core_txd <= #1 1'b0;
+	        shift    <= #1 1'b0;
+	        ld       <= #1 1'b0;
+	        cmd_ack  <= #1 1'b0;
+	        c_state  <= #1 ST_IDLE;
+	        ack_out  <= #1 1'b0;
+	    end
+	  else if (rst | i2c_al)
+	   begin
+	       core_cmd <= #1 `I2C_CMD_NOP;
+	       core_txd <= #1 1'b0;
+	       shift    <= #1 1'b0;
+	       ld       <= #1 1'b0;
+	       cmd_ack  <= #1 1'b0;
+	       c_state  <= #1 ST_IDLE;
+	       ack_out  <= #1 1'b0;
+	   end
+	else
+	  begin
+	      // initially reset all signals
+	      core_txd <= #1 sr[7];
+	      shift    <= #1 1'b0;
+	      ld       <= #1 1'b0;
+	      cmd_ack  <= #1 1'b0;
+
+	      case (c_state) // synopsys full_case parallel_case
+	        ST_IDLE:
+	          if (go)
+	            begin
+	                if (start)
+	                  begin
+	                      c_state  <= #1 ST_START;
+	                      core_cmd <= #1 `I2C_CMD_START;
+	                  end
+	                else if (read)
+	                  begin
+	                      c_state  <= #1 ST_READ;
+	                      core_cmd <= #1 `I2C_CMD_READ;
+	                  end
+	                else if (write)
+	                  begin
+	                      c_state  <= #1 ST_WRITE;
+	                      core_cmd <= #1 `I2C_CMD_WRITE;
+	                  end
+	                else // stop
+	                  begin
+	                      c_state  <= #1 ST_STOP;
+	                      core_cmd <= #1 `I2C_CMD_STOP;
+	                  end
+
+	                ld <= #1 1'b1;
+	            end
+
+	        ST_START:
+	          if (core_ack)
+	            begin
+	                if (read)
+	                  begin
+	                      c_state  <= #1 ST_READ;
+	                      core_cmd <= #1 `I2C_CMD_READ;
+	                  end
+	                else
+	                  begin
+	                      c_state  <= #1 ST_WRITE;
+	                      core_cmd <= #1 `I2C_CMD_WRITE;
+	                  end
+
+	                ld <= #1 1'b1;
+	            end
+
+	        ST_WRITE:
+	          if (core_ack)
+	            if (cnt_done)
+	              begin
+	                  c_state  <= #1 ST_ACK;
+	                  core_cmd <= #1 `I2C_CMD_READ;
+	              end
+	            else
+	              begin
+	                  c_state  <= #1 ST_WRITE;       // stay in same state
+	                  core_cmd <= #1 `I2C_CMD_WRITE; // write next bit
+	                  shift    <= #1 1'b1;
+	              end
+
+	        ST_READ:
+	          if (core_ack)
+	            begin
+	                if (cnt_done)
+	                  begin
+	                      c_state  <= #1 ST_ACK;
+	                      core_cmd <= #1 `I2C_CMD_WRITE;
+	                  end
+	                else
+	                  begin
+	                      c_state  <= #1 ST_READ;       // stay in same state
+	                      core_cmd <= #1 `I2C_CMD_READ; // read next bit
+	                  end
+
+	                shift    <= #1 1'b1;
+	                core_txd <= #1 ack_in;
+	            end
+
+	        ST_ACK:
+	          if (core_ack)
+	            begin
+	               if (stop)
+	                 begin
+	                     c_state  <= #1 ST_STOP;
+	                     core_cmd <= #1 `I2C_CMD_STOP;
+	                 end
+	               else
+	                 begin
+	                     c_state  <= #1 ST_IDLE;
+	                     core_cmd <= #1 `I2C_CMD_NOP;
+
+	                     // generate command acknowledge signal
+	                     cmd_ack  <= #1 1'b1;
+	                 end
+
+	                 // assign ack_out output to bit_controller_rxd (contains last received bit)
+	                 ack_out <= #1 core_rxd;
+
+	                 core_txd <= #1 1'b1;
+	             end
+	           else
+	             core_txd <= #1 ack_in;
+
+	        ST_STOP:
+	          if (core_ack)
+	            begin
+	                c_state  <= #1 ST_IDLE;
+	                core_cmd <= #1 `I2C_CMD_NOP;
+
+	                // generate command acknowledge signal
+	                cmd_ack  <= #1 1'b1;
+	            end
+
+	      endcase
+	  end
+endmodule
diff --git a/fpga/usrp3/lib/wishbone/i2c_master_defines.v b/fpga/usrp3/lib/wishbone/i2c_master_defines.v
new file mode 100644
index 000000000..ee3b694fa
--- /dev/null
+++ b/fpga/usrp3/lib/wishbone/i2c_master_defines.v
@@ -0,0 +1,64 @@
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  WISHBONE rev.B2 compliant I2C Master controller defines    ////
+////                                                             ////
+////                                                             ////
+////  Author: Richard Herveille                                  ////
+////          richard@asics.ws                                   ////
+////          www.asics.ws                                       ////
+////                                                             ////
+////  Downloaded from: http://www.opencores.org/projects/i2c/    ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2001 Richard Herveille                        ////
+////                    richard@asics.ws                         ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+//  CVS Log
+//
+//  $Id: i2c_master_defines.v,v 1.3 2001/11/05 11:59:25 rherveille Exp $
+//
+//  $Date: 2001/11/05 11:59:25 $
+//  $Revision: 1.3 $
+//  $Author: rherveille $
+//  $Locker:  $
+//  $State: Exp $
+//
+// Change History:
+//               $Log: i2c_master_defines.v,v $
+//               Revision 1.3  2001/11/05 11:59:25  rherveille
+//               Fixed wb_ack_o generation bug.
+//               Fixed bug in the byte_controller statemachine.
+//               Added headers.
+//
+
+
+// I2C registers wishbone addresses
+
+// bitcontroller states
+`define I2C_CMD_NOP   4'b0000
+`define I2C_CMD_START 4'b0001
+`define I2C_CMD_STOP  4'b0010
+`define I2C_CMD_WRITE 4'b0100
+`define I2C_CMD_READ  4'b1000
diff --git a/fpga/usrp3/lib/wishbone/i2c_master_top.v b/fpga/usrp3/lib/wishbone/i2c_master_top.v
new file mode 100644
index 000000000..be1fcfe55
--- /dev/null
+++ b/fpga/usrp3/lib/wishbone/i2c_master_top.v
@@ -0,0 +1,301 @@
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  WISHBONE revB.2 compliant I2C Master controller Top-level  ////
+////                                                             ////
+////                                                             ////
+////  Author: Richard Herveille                                  ////
+////          richard@asics.ws                                   ////
+////          www.asics.ws                                       ////
+////                                                             ////
+////  Downloaded from: http://www.opencores.org/projects/i2c/    ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2001 Richard Herveille                        ////
+////                    richard@asics.ws                         ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+//  CVS Log
+//
+//  $Id: i2c_master_top.v,v 1.11 2005/02/27 09:26:24 rherveille Exp $
+//
+//  $Date: 2005/02/27 09:26:24 $
+//  $Revision: 1.11 $
+//  $Author: rherveille $
+//  $Locker:  $
+//  $State: Exp $
+//
+// Change History:
+//               $Log: i2c_master_top.v,v $
+//               Revision 1.11  2005/02/27 09:26:24  rherveille
+//               Fixed register overwrite issue.
+//               Removed full_case pragma, replaced it by a default statement.
+//
+//               Revision 1.10  2003/09/01 10:34:38  rherveille
+//               Fix a blocking vs. non-blocking error in the wb_dat output mux.
+//
+//               Revision 1.9  2003/01/09 16:44:45  rherveille
+//               Fixed a bug in the Command Register declaration.
+//
+//               Revision 1.8  2002/12/26 16:05:12  rherveille
+//               Small code simplifications
+//
+//               Revision 1.7  2002/12/26 15:02:32  rherveille
+//               Core is now a Multimaster I2C controller
+//
+//               Revision 1.6  2002/11/30 22:24:40  rherveille
+//               Cleaned up code
+//
+//               Revision 1.5  2001/11/10 10:52:55  rherveille
+//               Changed PRER reset value from 0x0000 to 0xffff, conform specs.
+//
+
+// synopsys translate_off
+//`include "timescale.v"
+// synopsys translate_on
+
+`include "i2c_master_defines.v"
+
+module i2c_master_top(
+	wb_clk_i, wb_rst_i, arst_i, wb_adr_i, wb_dat_i, wb_dat_o,
+	wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_inta_o,
+	scl_pad_i, scl_pad_o, scl_padoen_o, sda_pad_i, sda_pad_o, sda_padoen_o );
+
+	// parameters
+	parameter ARST_LVL = 1'b0; // asynchronous reset level
+
+	//
+	// inputs & outputs
+	//
+
+	// wishbone signals
+	input        wb_clk_i;     // master clock input
+	input        wb_rst_i;     // synchronous active high reset
+	input        arst_i;       // asynchronous reset
+	input  [2:0] wb_adr_i;     // lower address bits
+	input  [7:0] wb_dat_i;     // databus input
+	output [7:0] wb_dat_o;     // databus output
+	input        wb_we_i;      // write enable input
+	input        wb_stb_i;     // stobe/core select signal
+	input        wb_cyc_i;     // valid bus cycle input
+	output       wb_ack_o;     // bus cycle acknowledge output
+	output       wb_inta_o;    // interrupt request signal output
+
+	reg [7:0] wb_dat_o;
+	reg wb_ack_o;
+	reg wb_inta_o;
+
+	// I2C signals
+	// i2c clock line
+	input  scl_pad_i;       // SCL-line input
+	output scl_pad_o;       // SCL-line output (always 1'b0)
+	output scl_padoen_o;    // SCL-line output enable (active low)
+
+	// i2c data line
+	input  sda_pad_i;       // SDA-line input
+	output sda_pad_o;       // SDA-line output (always 1'b0)
+	output sda_padoen_o;    // SDA-line output enable (active low)
+
+
+	//
+	// variable declarations
+	//
+
+	// registers
+	reg  [15:0] prer; // clock prescale register
+	reg  [ 7:0] ctr;  // control register
+	reg  [ 7:0] txr;  // transmit register
+	wire [ 7:0] rxr;  // receive register
+	reg  [ 7:0] cr;   // command register
+	wire [ 7:0] sr;   // status register
+
+	// done signal: command completed, clear command register
+	wire done;
+
+	// core enable signal
+	wire core_en;
+	wire ien;
+
+	// status register signals
+	wire irxack;
+	reg  rxack;       // received aknowledge from slave
+	reg  tip;         // transfer in progress
+	reg  irq_flag;    // interrupt pending flag
+	wire i2c_busy;    // bus busy (start signal detected)
+	wire i2c_al;      // i2c bus arbitration lost
+	reg  al;          // status register arbitration lost bit
+
+	//
+	// module body
+	//
+
+	// generate internal reset
+	wire rst_i = arst_i ^ ARST_LVL;
+
+	// generate wishbone signals
+	wire wb_wacc = wb_cyc_i & wb_stb_i & wb_we_i;
+
+	// generate acknowledge output signal
+	always @(posedge wb_clk_i)
+	  wb_ack_o <= #1 wb_cyc_i & wb_stb_i & ~wb_ack_o; // because timing is always honored
+
+	// assign DAT_O
+	always @(posedge wb_clk_i)
+	begin
+	  case (wb_adr_i) // synopsis parallel_case
+	    3'b000: wb_dat_o <= #1 prer[ 7:0];
+	    3'b001: wb_dat_o <= #1 prer[15:8];
+	    3'b010: wb_dat_o <= #1 ctr;
+	    3'b011: wb_dat_o <= #1 rxr; // write is transmit register (txr)
+	    3'b100: wb_dat_o <= #1 sr;  // write is command register (cr)
+	    3'b101: wb_dat_o <= #1 txr;
+	    3'b110: wb_dat_o <= #1 cr;
+	    3'b111: wb_dat_o <= #1 0;   // reserved
+	  endcase
+	end
+
+	// generate registers
+	always @(posedge wb_clk_i or negedge rst_i)
+	  if (!rst_i)
+	    begin
+	        prer <= #1 16'hffff;
+	        ctr  <= #1  8'h0;
+	        txr  <= #1  8'h0;
+	    end
+	  else if (wb_rst_i)
+	    begin
+	        prer <= #1 16'hffff;
+	        ctr  <= #1  8'h0;
+	        txr  <= #1  8'h0;
+	    end
+	  else
+	    if (wb_wacc)
+	      case (wb_adr_i) // synopsis parallel_case
+	         3'b000 : prer [ 7:0] <= #1 wb_dat_i;
+	         3'b001 : prer [15:8] <= #1 wb_dat_i;
+	         3'b010 : ctr         <= #1 wb_dat_i;
+	         3'b011 : txr         <= #1 wb_dat_i;
+	         default: ;
+	      endcase
+
+	// generate command register (special case)
+	always @(posedge wb_clk_i or negedge rst_i)
+	  if (~rst_i)
+	    cr <= #1 8'h0;
+	  else if (wb_rst_i)
+	    cr <= #1 8'h0;
+	  else if (wb_wacc)
+	    begin
+	        if (core_en & (wb_adr_i == 3'b100) )
+	          cr <= #1 wb_dat_i;
+	    end
+	  else
+	    begin
+	        if (done | i2c_al)
+	          cr[7:4] <= #1 4'h0;           // clear command bits when done
+	                                        // or when aribitration lost
+	        cr[2:1] <= #1 2'b0;             // reserved bits
+	        cr[0]   <= #1 2'b0;             // clear IRQ_ACK bit
+	    end
+
+
+	// decode command register
+	wire sta  = cr[7];
+	wire sto  = cr[6];
+	wire rd   = cr[5];
+	wire wr   = cr[4];
+	wire ack  = cr[3];
+	wire iack = cr[0];
+
+	// decode control register
+	assign core_en = ctr[7];
+	assign ien = ctr[6];
+
+	// hookup byte controller block
+	i2c_master_byte_ctrl byte_controller (
+		.clk      ( wb_clk_i     ),
+		.rst      ( wb_rst_i     ),
+		.nReset   ( rst_i        ),
+		.ena      ( core_en      ),
+		.clk_cnt  ( prer         ),
+		.start    ( sta          ),
+		.stop     ( sto          ),
+		.read     ( rd           ),
+		.write    ( wr           ),
+		.ack_in   ( ack          ),
+		.din      ( txr          ),
+		.cmd_ack  ( done         ),
+		.ack_out  ( irxack       ),
+		.dout     ( rxr          ),
+		.i2c_busy ( i2c_busy     ),
+		.i2c_al   ( i2c_al       ),
+		.scl_i    ( scl_pad_i    ),
+		.scl_o    ( scl_pad_o    ),
+		.scl_oen  ( scl_padoen_o ),
+		.sda_i    ( sda_pad_i    ),
+		.sda_o    ( sda_pad_o    ),
+		.sda_oen  ( sda_padoen_o )
+	);
+
+	// status register block + interrupt request signal
+	always @(posedge wb_clk_i or negedge rst_i)
+	  if (!rst_i)
+	    begin
+	        al       <= #1 1'b0;
+	        rxack    <= #1 1'b0;
+	        tip      <= #1 1'b0;
+	        irq_flag <= #1 1'b0;
+	    end
+	  else if (wb_rst_i)
+	    begin
+	        al       <= #1 1'b0;
+	        rxack    <= #1 1'b0;
+	        tip      <= #1 1'b0;
+	        irq_flag <= #1 1'b0;
+	    end
+	  else
+	    begin
+	        al       <= #1 i2c_al | (al & ~sta);
+	        rxack    <= #1 irxack;
+	        tip      <= #1 (rd | wr);
+	        irq_flag <= #1 (done | i2c_al | irq_flag) & ~iack; // interrupt request flag is always generated
+	    end
+
+	// generate interrupt request signals
+	always @(posedge wb_clk_i or negedge rst_i)
+	  if (!rst_i)
+	    wb_inta_o <= #1 1'b0;
+	  else if (wb_rst_i)
+	    wb_inta_o <= #1 1'b0;
+	  else
+	    wb_inta_o <= #1 irq_flag && ien; // interrupt signal is only generated when IEN (interrupt enable bit is set)
+
+	// assign status register bits
+	assign sr[7]   = rxack;
+	assign sr[6]   = i2c_busy;
+	assign sr[5]   = al;
+	assign sr[4:2] = 3'h0; // reserved
+	assign sr[1]   = tip;
+	assign sr[0]   = irq_flag;
+
+endmodule
diff --git a/fpga/usrp3/lib/wishbone/settings_bus.v b/fpga/usrp3/lib/wishbone/settings_bus.v
new file mode 100644
index 000000000..53bb14f5b
--- /dev/null
+++ b/fpga/usrp3/lib/wishbone/settings_bus.v
@@ -0,0 +1,49 @@
+//
+// Copyright 2011-2012 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+
+// Grab settings off the wishbone bus, send them out to our simpler bus on the fast clock
+
+module settings_bus
+  #(parameter AWIDTH=16, parameter DWIDTH=32, parameter SWIDTH=8)
+    (input wb_clk, 
+     input wb_rst, 
+     input [AWIDTH-1:0] wb_adr_i,
+     input [DWIDTH-1:0] wb_dat_i,
+     input wb_stb_i,
+     input wb_we_i,
+     output reg wb_ack_o,
+     output reg strobe,
+     output reg [SWIDTH-1:0] addr,
+     output reg [31:0] data);
+
+   reg 	    stb_int, stb_int_d1;
+   
+   always @(posedge wb_clk)
+     if(wb_rst)
+       begin
+	  strobe <= 1'b0;
+	  addr <= {SWIDTH{1'b0}};
+	  data <= 32'd0;
+       end
+     else if(wb_we_i & wb_stb_i & ~wb_ack_o)
+       begin
+	  strobe <= 1'b1;
+	  addr <= wb_adr_i[SWIDTH+1:2];
+	  data <= wb_dat_i;
+       end
+     else
+       strobe <= 1'b0;
+
+   always @(posedge wb_clk)
+     if(wb_rst)
+       wb_ack_o <= 0;
+     else
+       wb_ack_o <= wb_stb_i & ~wb_ack_o;
+
+endmodule // settings_bus
diff --git a/fpga/usrp3/lib/wishbone/settings_readback.v b/fpga/usrp3/lib/wishbone/settings_readback.v
new file mode 100644
index 000000000..e7c74cab7
--- /dev/null
+++ b/fpga/usrp3/lib/wishbone/settings_readback.v
@@ -0,0 +1,43 @@
+//
+// Copyright 2011-2012 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+//
+// Use this module in conjunction with settings_bus.v to add stateful reads
+// to the settings bis. This enables you to do things like have registers reset atomicly
+// as they are read. It also pipelines the address path to ease timing.
+//
+
+module settings_readback
+  #(parameter AWIDTH=16, parameter DWIDTH=32, parameter RB_ADDRW=2)
+   (
+    input wb_clk, 
+    input wb_rst, 
+    input [AWIDTH-1:0] wb_adr_i,
+    input wb_stb_i,
+    input wb_we_i,
+    input [DWIDTH-1:0] rb_data,
+    output reg [RB_ADDRW-1:0] rb_addr,
+    output [DWIDTH-1:0] wb_dat_o,
+    output reg rb_rd_stb
+    );
+
+   always @(posedge wb_clk)
+     if (wb_stb_i && ~wb_we_i) begin
+	rb_addr <= wb_adr_i[RB_ADDRW+1:2];
+	rb_rd_stb <= 1'b1;	
+     end else begin
+	rb_rd_stb <= 1'b0;	
+     end
+   
+   assign wb_dat_o = rb_data;
+
+   
+
+endmodule // settings_readback
+
+  
\ No newline at end of file
diff --git a/fpga/usrp3/lib/wishbone/simple_uart.v b/fpga/usrp3/lib/wishbone/simple_uart.v
new file mode 100644
index 000000000..8c5226f10
--- /dev/null
+++ b/fpga/usrp3/lib/wishbone/simple_uart.v
@@ -0,0 +1,68 @@
+//
+// Copyright 2011 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+
+module simple_uart
+  #(parameter CLKDIV_DEFAULT = 16'd0, parameter RX_SIZE=8, parameter TX_SIZE=0)
+   (input clk_i, input rst_i,
+    input we_i, input stb_i, input cyc_i, output reg ack_o,
+    input [2:0] adr_i, input [31:0] dat_i, output reg [31:0] dat_o,
+    output rx_int_o, output tx_int_o, output tx_o, input rx_i, output baud_o);
+
+   // Register Map
+   localparam SUART_CLKDIV = 0;
+   localparam SUART_TXLEVEL = 1;
+   localparam SUART_RXLEVEL = 2;
+   localparam SUART_TXCHAR = 3;
+   localparam SUART_RXCHAR = 4;
+
+   wire       wb_acc = cyc_i & stb_i;            // WISHBONE access
+   wire       wb_wr  = wb_acc & we_i;            // WISHBONE write access
+
+   reg [15:0] clkdiv;
+   wire [7:0] rx_char;
+   wire       tx_fifo_full, rx_fifo_empty;
+   wire [15:0] tx_fifo_level, rx_fifo_level;
+
+   always @(posedge clk_i)
+     if (rst_i)
+       ack_o <= 1'b0;
+     else
+       ack_o <= wb_acc & ~ack_o;
+
+   always @(posedge clk_i)
+     if (rst_i)
+       clkdiv <= CLKDIV_DEFAULT;
+     else if (wb_wr)
+       case(adr_i)
+	 SUART_CLKDIV : clkdiv <= dat_i[15:0];
+       endcase // case(adr_i)
+
+   always @(posedge clk_i)
+     case (adr_i)
+       SUART_TXLEVEL : dat_o <= tx_fifo_level;
+       SUART_RXLEVEL : dat_o <= rx_fifo_level;
+       SUART_RXCHAR : dat_o <= rx_char;
+     endcase // case(adr_i)
+
+   simple_uart_tx #(.SIZE(TX_SIZE)) simple_uart_tx
+     (.clk(clk_i),.rst(rst_i),
+      .fifo_in(dat_i[7:0]),.fifo_write(ack_o && wb_wr && (adr_i == SUART_TXCHAR)),
+      .fifo_level(tx_fifo_level),.fifo_full(tx_fifo_full),
+      .clkdiv(clkdiv),.baudclk(baud_o),.tx(tx_o));
+
+   simple_uart_rx #(.SIZE(RX_SIZE)) simple_uart_rx
+     (.clk(clk_i),.rst(rst_i),
+      .fifo_out(rx_char),.fifo_read(ack_o && ~wb_wr && (adr_i == SUART_RXCHAR)),
+      .fifo_level(rx_fifo_level),.fifo_empty(rx_fifo_empty),
+      .clkdiv(clkdiv),.rx(rx_i));
+
+   assign     tx_int_o = ~tx_fifo_full;
+   assign     rx_int_o = ~rx_fifo_empty;
+
+endmodule // simple_uart
diff --git a/fpga/usrp3/lib/wishbone/simple_uart_rx.v b/fpga/usrp3/lib/wishbone/simple_uart_rx.v
new file mode 100644
index 000000000..6be177c93
--- /dev/null
+++ b/fpga/usrp3/lib/wishbone/simple_uart_rx.v
@@ -0,0 +1,74 @@
+//
+// Copyright 2011-2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+
+
+module simple_uart_rx
+    #(parameter SIZE=8)
+    (input clk, input rst,
+     output [7:0] fifo_out, input fifo_read, output [15:0] fifo_level, output fifo_empty,
+     input [15:0] clkdiv, input rx);
+
+   reg 		  rx_d1, rx_d2;
+   always @(posedge clk)
+     if(rst)
+       {rx_d2,rx_d1} <= 0;
+     else
+       {rx_d2,rx_d1} <= {rx_d1,rx};
+
+   reg [15:0] 	  baud_ctr;
+   reg [3:0] 	  bit_ctr;
+   reg [7:0] 	  sr;
+
+   wire 	  neg_trans = rx_d2 & ~rx_d1;
+   wire 	  shift_now = baud_ctr == (clkdiv>>1);
+   wire 	  stop_now = (bit_ctr == 10) && shift_now;
+   wire 	  go_now = (bit_ctr == 0) && neg_trans;
+
+   always @(posedge clk)
+     if(rst)
+       sr <= 0;
+     else if(shift_now)
+       sr <= {rx_d2,sr[7:1]};
+
+   always @(posedge clk)
+     if(rst)
+       baud_ctr <= 0;
+     else
+       if(go_now)
+	 baud_ctr <= 1;
+       else if(stop_now)
+	 baud_ctr <= 0;
+       else if(baud_ctr >= clkdiv)
+	 baud_ctr <= 1;
+       else if(baud_ctr != 0)
+	 baud_ctr <= baud_ctr + 1;
+
+   always @(posedge clk)
+     if(rst)
+       bit_ctr <= 0;
+     else
+       if(go_now)
+	 bit_ctr <= 1;
+       else if(stop_now)
+	 bit_ctr <= 0;
+       else if(baud_ctr == clkdiv)
+	 bit_ctr <= bit_ctr + 1;
+
+   wire 	  i_tready, o_tvalid;
+   wire 	  full = ~i_tready;
+   wire 	  write = ~full & stop_now;
+   assign fifo_empty = ~o_tvalid;
+
+   axi_fifo #(.WIDTH(8), .SIZE(SIZE)) fifo
+     (.clk(clk),.reset(rst), .clear(1'b0),
+      .i_tdata(sr),.i_tvalid(write),.i_tready(i_tready),
+      .o_tdata(fifo_out),.o_tvalid(o_tvalid),.o_tready(fifo_read),
+      .space(),.occupied(fifo_level) );
+
+endmodule // simple_uart_rx
diff --git a/fpga/usrp3/lib/wishbone/simple_uart_tb.v b/fpga/usrp3/lib/wishbone/simple_uart_tb.v
new file mode 100644
index 000000000..b7071ee5d
--- /dev/null
+++ b/fpga/usrp3/lib/wishbone/simple_uart_tb.v
@@ -0,0 +1,132 @@
+//
+// Copyright 2013 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+module simple_uart_tb();
+   
+   localparam SUART_CLKDIV = 0;
+   localparam SUART_TXLEVEL = 1;
+   localparam SUART_RXLEVEL = 2;
+   localparam SUART_TXCHAR = 3;
+   localparam SUART_RXCHAR = 4;
+   
+   reg           clk;
+   reg 		 rst;
+
+   reg 		 we_i;
+   reg 		 stb_i;
+   reg 		 cyc_i;
+   wire 	 ack_o;
+   reg [2:0] 	 adr_i;
+   reg [31:0] 	 dat_i;
+   wire [31:0] 	 dat_o;
+   wire 	 rx_int_o;
+   wire 	 tx_int_o;
+   wire 	 tx_o;
+   reg 		 rx_i;
+   wire 	 baud_o;
+
+   reg [31:0] 	 read_data;
+   
+
+   initial 
+     clk = 0;
+
+   // 200MHz clock
+   always
+     #2.5 clk = ~clk;
+
+   initial begin
+      rst <= 0;
+      we_i <= 0;
+      stb_i <= 0;
+      cyc_i <= 0;
+      adr_i <= 0;
+      dat_i <= 0;
+      rx_i <= 0;
+   end
+   
+   
+   task write_wb;
+      input [31:0] data_in;
+      input [2:0]  addr_in;
+
+      begin
+	 @(negedge clk);	 
+	 dat_i <= data_in;
+	 adr_i <= addr_in;
+	 we_i <= 1;
+	 stb_i <= 1;
+	 cyc_i <= 1;
+	 @(negedge clk);
+	 while (ack_o == 0) begin
+	    @(negedge clk);
+	 end
+	 dat_i <= 0;
+	 adr_i <= 0;
+	 we_i <= 0;
+	 stb_i <= 0;
+	 cyc_i <= 0;
+      end
+   endtask // write_wb
+
+   
+   task read_wb;
+      output [31:0] data_out;
+      input [2:0]  addr_in;
+
+      begin
+	 @(negedge clk);	 
+	 adr_i <= addr_in;
+	 we_i <= 0;
+	 stb_i <= 1;
+	 cyc_i <= 1;
+	 @(negedge clk);
+	 while (ack_o == 0) begin
+	    @(negedge clk);
+	 end
+	 data_out <= dat_o;
+	 adr_i <= 0;
+	 stb_i <= 0;
+	 cyc_i <= 0;
+      end
+   endtask // write_wb
+
+   initial begin
+      @(negedge clk);    
+      rst <= 1;
+      repeat(10) @(negedge clk);
+      rst <= 0;
+      repeat(10) @(negedge clk);
+      write_wb(4'h0620,SUART_CLKDIV);
+      repeat(10) @(negedge clk);
+      read_wb(read_data,SUART_TXLEVEL);
+      repeat(10) @(negedge clk);
+   end // initial begin
+   
+   
+   
+   simple_uart
+     #(.CLKDIV_DEFAULT(16'd0))
+   simple_uart_i
+     (
+      .clk_i(clk),
+      .rst_i(rst),
+      .we_i(we_i),
+      .stb_i(stb_i),
+      .cyc_i(cyc_i),
+      .ack_o(ack_o),
+      .adr_i(adr_i),
+      .dat_i(dat_i),
+      .dat_o(dat_o),
+      .rx_int_o(rx_int_o),
+      .tx_int_o(tx_int_o), 
+      .tx_o(tx_o), 
+      .rx_i(rx_i),
+      .baud_o(baud_o)
+      );
+
+   
+
+endmodule // simple_uart_tb
diff --git a/fpga/usrp3/lib/wishbone/simple_uart_tx.v b/fpga/usrp3/lib/wishbone/simple_uart_tx.v
new file mode 100644
index 000000000..cf287a715
--- /dev/null
+++ b/fpga/usrp3/lib/wishbone/simple_uart_tx.v
@@ -0,0 +1,72 @@
+//
+// Copyright 2011-2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+
+module simple_uart_tx
+    #(parameter SIZE=0)
+    (input clk, input rst,
+     input [7:0] fifo_in, input fifo_write, output [15:0] fifo_level, output fifo_full, 
+     input [15:0] clkdiv, output baudclk, output reg tx);
+
+   reg [15:0] 	  baud_ctr;
+   reg [3:0] 	  bit_ctr;
+
+   wire 	  read, empty;
+   wire [7:0] 	  char_to_send;
+   wire 	  i_tready, o_tvalid;
+
+   assign fifo_full = ~i_tready;
+   assign empty = ~o_tvalid;
+
+   axi_fifo #(.WIDTH(8), .SIZE(SIZE)) fifo
+     (.clk(clk),.reset(rst), .clear(1'b0),
+      .i_tdata(fifo_in), .i_tvalid(fifo_write), .i_tready(i_tready),
+      .o_tdata(char_to_send),.o_tvalid(o_tvalid),.o_tready(read),
+      .space(fifo_level),.occupied() );
+
+   always @(posedge clk)
+     if(rst)
+       baud_ctr <= 0;
+     else if (baud_ctr >= clkdiv)
+       baud_ctr <= 1;
+     else
+       baud_ctr <= baud_ctr + 1;
+
+   always @(posedge clk)
+     if(rst)
+       bit_ctr <= 0;
+     else if(baud_ctr == clkdiv)
+       if(bit_ctr == 10)
+	 bit_ctr <= 0;
+       else if(bit_ctr != 0)
+	 bit_ctr <= bit_ctr + 1;
+       else if(~empty)
+	 bit_ctr <= 1;
+
+   always @(posedge clk)
+     if(rst)
+       tx <= 1;
+     else
+       case(bit_ctr)
+	 0 : tx <= 1;
+	 1 : tx <= 0;
+	 2 : tx <= char_to_send[0];
+	 3 : tx <= char_to_send[1];
+	 4 : tx <= char_to_send[2];
+	 5 : tx <= char_to_send[3];
+	 6 : tx <= char_to_send[4];
+	 7 : tx <= char_to_send[5];
+	 8 : tx <= char_to_send[6];
+	 9 : tx <= char_to_send[7];
+	 default : tx <= 1;
+       endcase // case(bit_ctr)
+
+   assign 	  read = (bit_ctr == 9) && (baud_ctr == clkdiv);
+   assign 	  baudclk = (baud_ctr == 1);  // Only for debug purposes
+
+endmodule // simple_uart_tx
diff --git a/fpga/usrp3/lib/wishbone/wb_1master.v b/fpga/usrp3/lib/wishbone/wb_1master.v
new file mode 100644
index 000000000..fb313efae
--- /dev/null
+++ b/fpga/usrp3/lib/wishbone/wb_1master.v
@@ -0,0 +1,464 @@
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  WISHBONE Connection Bus Top Level		                 ////
+////                                                             ////
+////                                                             ////
+////  Original Author: Johny Chi		                 ////
+////                   chisuhua@yahoo.com.cn                     ////
+////  Modified By Matt Ettus, matt@ettus.com                     ////
+////                                                             ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2000, 2007 Authors and OPENCORES.ORG           ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+//   Up to 8 slaves share a Wishbone Bus connection to 1 master
+
+  module wb_1master
+    #(parameter	decode_w = 8,			// address decode width
+      parameter	s0_addr = 8'h0,			// slave 0 address
+      parameter	s0_mask = 8'h0,			// slave 0 don't cares
+      parameter	s1_addr = 8'h0,			// slave 1 address
+      parameter	s1_mask = 8'h0,			// slave 1 don't cares
+      parameter	s2_addr = 8'h0,			// slave 2 address
+      parameter	s2_mask = 8'h0,			// slave 2 don't cares
+      parameter	s3_addr = 8'h0,			// slave 3 address
+      parameter	s3_mask = 8'h0,			// slave 3 don't cares
+      parameter	s4_addr = 8'h0,			// slave 4 address
+      parameter	s4_mask = 8'h0,			// slave 4 don't cares
+      parameter	s5_addr = 8'h0,			// slave 5 address
+      parameter	s5_mask = 8'h0,			// slave 5 don't cares
+      parameter	s6_addr = 8'h0,			// slave 6 address
+      parameter	s6_mask = 8'h0,			// slave 6 don't cares
+      parameter	s7_addr = 8'h0,			// slave 7 address
+      parameter	s7_mask = 8'h0,			// slave 7 don't cares
+      parameter	s8_addr = 8'h0,			// slave 8 address
+      parameter	s8_mask = 8'h0,			// slave 8 don't cares
+      parameter	s9_addr = 8'h0,			// slave 9 address
+      parameter	s9_mask = 8'h0,			// slave 9 don't cares
+      parameter	sa_addr = 8'h0,			// slave a address
+      parameter	sa_mask = 8'h0,			// slave a don't cares
+      parameter	sb_addr = 8'h0,			// slave b address
+      parameter	sb_mask = 8'h0,			// slave b don't cares
+      parameter	sc_addr = 8'h0,			// slave c address
+      parameter	sc_mask = 8'h0,			// slave c don't cares
+      parameter	sd_addr = 8'h0,			// slave d address
+      parameter	sd_mask = 8'h0,			// slave d don't cares
+      parameter	se_addr = 8'h0,			// slave e address
+      parameter	se_mask = 8'h0,			// slave e don't cares
+      parameter	sf_addr = 8'h0,			// slave f address
+      parameter	sf_mask = 8'h0,			// slave f don't cares
+            
+      parameter	dw = 32,		// Data bus Width
+      parameter	aw = 32,		// Address bus Width
+      parameter	sw = 4)                 // Number of Select Lines
+      
+      (input clk_i, 
+       input rst_i,
+       
+       // Master  Interface
+       input [dw-1:0]   m0_dat_i,
+       output [dw-1:0] 	m0_dat_o,
+       input [aw-1:0] 	m0_adr_i,
+       input [sw-1:0] 	m0_sel_i,
+       input 		m0_we_i,
+       input 		m0_cyc_i,
+       input 		m0_stb_i,
+       output 		m0_ack_o,
+       output 		m0_err_o,
+       output 		m0_rty_o,
+       
+       // Slave Interfaces
+       input [dw-1:0] 	s0_dat_i,
+       output [dw-1:0] 	s0_dat_o,
+       output [aw-1:0] 	s0_adr_o,
+       output [sw-1:0] 	s0_sel_o,
+       output 		s0_we_o,
+       output 		s0_cyc_o,
+       output 		s0_stb_o,
+       input 		s0_ack_i,
+       input 		s0_err_i,
+       input 		s0_rty_i,
+       
+       input [dw-1:0] 	s1_dat_i,
+       output [dw-1:0] 	s1_dat_o,
+       output [aw-1:0] 	s1_adr_o,
+       output [sw-1:0] 	s1_sel_o,
+       output 		s1_we_o,
+       output 		s1_cyc_o,
+       output 		s1_stb_o,
+       input 		s1_ack_i,
+       input 		s1_err_i,
+       input 		s1_rty_i,
+       
+       input [dw-1:0] 	s2_dat_i,
+       output [dw-1:0] 	s2_dat_o,
+       output [aw-1:0] 	s2_adr_o,
+       output [sw-1:0] 	s2_sel_o,
+       output 		s2_we_o,
+       output 		s2_cyc_o,
+       output 		s2_stb_o,
+       input 		s2_ack_i,
+       input 		s2_err_i,
+       input 		s2_rty_i,
+       
+       input [dw-1:0] 	s3_dat_i,
+       output [dw-1:0] 	s3_dat_o,
+       output [aw-1:0] 	s3_adr_o,
+       output [sw-1:0] 	s3_sel_o,
+       output 		s3_we_o,
+       output 		s3_cyc_o,
+       output 		s3_stb_o,
+       input 		s3_ack_i,
+       input 		s3_err_i,
+       input 		s3_rty_i,
+       
+       input [dw-1:0] 	s4_dat_i,
+       output [dw-1:0] 	s4_dat_o,
+       output [aw-1:0] 	s4_adr_o,
+       output [sw-1:0] 	s4_sel_o,
+       output 		s4_we_o,
+       output 		s4_cyc_o,
+       output 		s4_stb_o,
+       input 		s4_ack_i,
+       input 		s4_err_i,
+       input 		s4_rty_i,
+       
+       input [dw-1:0] 	s5_dat_i,
+       output [dw-1:0] 	s5_dat_o,
+       output [aw-1:0] 	s5_adr_o,
+       output [sw-1:0] 	s5_sel_o,
+       output 		s5_we_o,
+       output 		s5_cyc_o,
+       output 		s5_stb_o,
+       input 		s5_ack_i,
+       input 		s5_err_i,
+       input 		s5_rty_i,
+       
+       input [dw-1:0] 	s6_dat_i,
+       output [dw-1:0] 	s6_dat_o,
+       output [aw-1:0] 	s6_adr_o,
+       output [sw-1:0] 	s6_sel_o,
+       output 		s6_we_o,
+       output 		s6_cyc_o,
+       output 		s6_stb_o,
+       input 		s6_ack_i,
+       input 		s6_err_i,
+       input 		s6_rty_i,
+       
+       input [dw-1:0] 	s7_dat_i,
+       output [dw-1:0] 	s7_dat_o,
+       output [aw-1:0] 	s7_adr_o,
+       output [sw-1:0] 	s7_sel_o,
+       output 		s7_we_o,
+       output 		s7_cyc_o,
+       output 		s7_stb_o,
+       input 		s7_ack_i,
+       input 		s7_err_i,
+       input 		s7_rty_i,
+
+       input [dw-1:0] 	s8_dat_i,
+       output [dw-1:0] 	s8_dat_o,
+       output [aw-1:0] 	s8_adr_o,
+       output [sw-1:0] 	s8_sel_o,
+       output 		s8_we_o,
+       output 		s8_cyc_o,
+       output 		s8_stb_o,
+       input 		s8_ack_i,
+       input 		s8_err_i,
+       input 		s8_rty_i,
+       
+       input [dw-1:0] 	s9_dat_i,
+       output [dw-1:0] 	s9_dat_o,
+       output [aw-1:0] 	s9_adr_o,
+       output [sw-1:0] 	s9_sel_o,
+       output 		s9_we_o,
+       output 		s9_cyc_o,
+       output 		s9_stb_o,
+       input 		s9_ack_i,
+       input 		s9_err_i,
+       input 		s9_rty_i,
+       
+       input [dw-1:0] 	sa_dat_i,
+       output [dw-1:0] 	sa_dat_o,
+       output [aw-1:0] 	sa_adr_o,
+       output [sw-1:0] 	sa_sel_o,
+       output 		sa_we_o,
+       output 		sa_cyc_o,
+       output 		sa_stb_o,
+       input 		sa_ack_i,
+       input 		sa_err_i,
+       input 		sa_rty_i,
+       
+       input [dw-1:0] 	sb_dat_i,
+       output [dw-1:0] 	sb_dat_o,
+       output [aw-1:0] 	sb_adr_o,
+       output [sw-1:0] 	sb_sel_o,
+       output 		sb_we_o,
+       output 		sb_cyc_o,
+       output 		sb_stb_o,
+       input 		sb_ack_i,
+       input 		sb_err_i,
+       input 		sb_rty_i,
+       
+       input [dw-1:0] 	sc_dat_i,
+       output [dw-1:0] 	sc_dat_o,
+       output [aw-1:0] 	sc_adr_o,
+       output [sw-1:0] 	sc_sel_o,
+       output 		sc_we_o,
+       output 		sc_cyc_o,
+       output 		sc_stb_o,
+       input 		sc_ack_i,
+       input 		sc_err_i,
+       input 		sc_rty_i,
+       
+       input [dw-1:0] 	sd_dat_i,
+       output [dw-1:0] 	sd_dat_o,
+       output [aw-1:0] 	sd_adr_o,
+       output [sw-1:0] 	sd_sel_o,
+       output 		sd_we_o,
+       output 		sd_cyc_o,
+       output 		sd_stb_o,
+       input 		sd_ack_i,
+       input 		sd_err_i,
+       input 		sd_rty_i,
+       
+       input [dw-1:0] 	se_dat_i,
+       output [dw-1:0] 	se_dat_o,
+       output [aw-1:0] 	se_adr_o,
+       output [sw-1:0] 	se_sel_o,
+       output 		se_we_o,
+       output 		se_cyc_o,
+       output 		se_stb_o,
+       input 		se_ack_i,
+       input 		se_err_i,
+       input 		se_rty_i,
+       
+       input [dw-1:0] 	sf_dat_i,
+       output [dw-1:0] 	sf_dat_o,
+       output [aw-1:0] 	sf_adr_o,
+       output [sw-1:0] 	sf_sel_o,
+       output 		sf_we_o,
+       output 		sf_cyc_o,
+       output 		sf_stb_o,
+       input 		sf_ack_i,
+       input 		sf_err_i,
+       input 		sf_rty_i
+       );
+   
+   // ////////////////////////////////////////////////////////////////
+   //
+   // Local wires
+   //
+   
+   wire [15:0] 		ssel_dec;
+   reg [dw-1:0] 	i_dat_s;	// internal share bus , slave data to master
+   
+   // Master output Interface
+   assign 		m0_dat_o = i_dat_s;
+   
+   always @*
+     case(ssel_dec)
+       1   : i_dat_s <= s0_dat_i;
+       2   : i_dat_s <= s1_dat_i;
+       4   : i_dat_s <= s2_dat_i;
+       8   : i_dat_s <= s3_dat_i;
+       16  : i_dat_s <= s4_dat_i;
+       32  : i_dat_s <= s5_dat_i;
+       64  : i_dat_s <= s6_dat_i;
+       128 : i_dat_s <= s7_dat_i;
+       256 : i_dat_s <= s8_dat_i;
+       512 : i_dat_s <= s9_dat_i;
+       1024 : i_dat_s <= sa_dat_i;
+       2048 : i_dat_s <= sb_dat_i;
+       4096 : i_dat_s <= sc_dat_i;
+       8192 : i_dat_s <= sd_dat_i;
+       16384 : i_dat_s <= se_dat_i;
+       32768 : i_dat_s <= sf_dat_i;
+       default : i_dat_s <= s0_dat_i;
+     endcase // case(ssel_dec)
+   
+   assign 		{m0_ack_o, m0_err_o, m0_rty_o} 
+     =  {s0_ack_i | s1_ack_i | s2_ack_i | s3_ack_i | s4_ack_i | s5_ack_i | s6_ack_i | s7_ack_i |
+	 s8_ack_i | s9_ack_i | sa_ack_i | sb_ack_i | sc_ack_i | sd_ack_i | se_ack_i | sf_ack_i ,
+	 s0_err_i | s1_err_i | s2_err_i | s3_err_i | s4_err_i | s5_err_i | s6_err_i | s7_err_i |
+	 s8_err_i | s9_err_i | sa_err_i | sb_err_i | sc_err_i | sd_err_i | se_err_i | sf_err_i ,
+	 s0_rty_i | s1_rty_i | s2_rty_i | s3_rty_i | s4_rty_i | s5_rty_i | s6_rty_i | s7_rty_i |
+	 s8_rty_i | s9_rty_i | sa_rty_i | sb_rty_i | sc_rty_i | sd_rty_i | se_rty_i | sf_rty_i };
+
+   // Slave output interfaces
+   assign 		s0_adr_o = m0_adr_i;
+   assign 		s0_sel_o = m0_sel_i;
+   assign 		s0_dat_o = m0_dat_i;
+   assign 		s0_we_o = m0_we_i;
+   assign 		s0_cyc_o = m0_cyc_i;
+   assign 		s0_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[0];   
+   
+   assign 		s1_adr_o = m0_adr_i;
+   assign 		s1_sel_o = m0_sel_i;
+   assign 		s1_dat_o = m0_dat_i;
+   assign 		s1_we_o = m0_we_i;
+   assign 		s1_cyc_o = m0_cyc_i;
+   assign 		s1_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[1];   
+   
+   assign 		s2_adr_o = m0_adr_i;
+   assign 		s2_sel_o = m0_sel_i;
+   assign 		s2_dat_o = m0_dat_i;
+   assign 		s2_we_o = m0_we_i;
+   assign 		s2_cyc_o = m0_cyc_i;
+   assign 		s2_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[2];   
+   
+   assign 		s3_adr_o = m0_adr_i;
+   assign 		s3_sel_o = m0_sel_i;
+   assign 		s3_dat_o = m0_dat_i;
+   assign 		s3_we_o = m0_we_i;
+   assign 		s3_cyc_o = m0_cyc_i;
+   assign 		s3_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[3];   
+   
+   assign 		s4_adr_o = m0_adr_i;
+   assign 		s4_sel_o = m0_sel_i;
+   assign 		s4_dat_o = m0_dat_i;
+   assign 		s4_we_o = m0_we_i;
+   assign 		s4_cyc_o = m0_cyc_i;
+   assign 		s4_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[4];   
+   
+   assign 		s5_adr_o = m0_adr_i;
+   assign 		s5_sel_o = m0_sel_i;
+   assign 		s5_dat_o = m0_dat_i;
+   assign 		s5_we_o = m0_we_i;
+   assign 		s5_cyc_o = m0_cyc_i;
+   assign 		s5_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[5];   
+   
+   assign 		s6_adr_o = m0_adr_i;
+   assign 		s6_sel_o = m0_sel_i;
+   assign 		s6_dat_o = m0_dat_i;
+   assign 		s6_we_o = m0_we_i;
+   assign 		s6_cyc_o = m0_cyc_i;
+   assign 		s6_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[6];   
+   
+   assign 		s7_adr_o = m0_adr_i;
+   assign 		s7_sel_o = m0_sel_i;
+   assign 		s7_dat_o = m0_dat_i;
+   assign 		s7_we_o = m0_we_i;
+   assign 		s7_cyc_o = m0_cyc_i;
+   assign 		s7_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[7];   
+   
+   assign 		s8_adr_o = m0_adr_i;
+   assign 		s8_sel_o = m0_sel_i;
+   assign 		s8_dat_o = m0_dat_i;
+   assign 		s8_we_o = m0_we_i;
+   assign 		s8_cyc_o = m0_cyc_i;
+   assign 		s8_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[8];   
+   
+   assign 		s9_adr_o = m0_adr_i;
+   assign 		s9_sel_o = m0_sel_i;
+   assign 		s9_dat_o = m0_dat_i;
+   assign 		s9_we_o = m0_we_i;
+   assign 		s9_cyc_o = m0_cyc_i;
+   assign 		s9_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[9];   
+   
+   assign 		sa_adr_o = m0_adr_i;
+   assign 		sa_sel_o = m0_sel_i;
+   assign 		sa_dat_o = m0_dat_i;
+   assign 		sa_we_o = m0_we_i;
+   assign 		sa_cyc_o = m0_cyc_i;
+   assign 		sa_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[10];   
+   
+   assign 		sb_adr_o = m0_adr_i;
+   assign 		sb_sel_o = m0_sel_i;
+   assign 		sb_dat_o = m0_dat_i;
+   assign 		sb_we_o = m0_we_i;
+   assign 		sb_cyc_o = m0_cyc_i;
+   assign 		sb_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[11];   
+   
+   assign 		sc_adr_o = m0_adr_i;
+   assign 		sc_sel_o = m0_sel_i;
+   assign 		sc_dat_o = m0_dat_i;
+   assign 		sc_we_o = m0_we_i;
+   assign 		sc_cyc_o = m0_cyc_i;
+   assign 		sc_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[12];   
+   
+   assign 		sd_adr_o = m0_adr_i;
+   assign 		sd_sel_o = m0_sel_i;
+   assign 		sd_dat_o = m0_dat_i;
+   assign 		sd_we_o = m0_we_i;
+   assign 		sd_cyc_o = m0_cyc_i;
+   assign 		sd_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[13];   
+   
+   assign 		se_adr_o = m0_adr_i;
+   assign 		se_sel_o = m0_sel_i;
+   assign 		se_dat_o = m0_dat_i;
+   assign 		se_we_o = m0_we_i;
+   assign 		se_cyc_o = m0_cyc_i;
+   assign 		se_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[14];   
+   
+   assign 		sf_adr_o = m0_adr_i;
+   assign 		sf_sel_o = m0_sel_i;
+   assign 		sf_dat_o = m0_dat_i;
+   assign 		sf_we_o = m0_we_i;
+   assign 		sf_cyc_o = m0_cyc_i;
+   assign 		sf_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[15];   
+   
+   // Address decode logic
+   // WARNING -- must make sure these are mutually exclusive!
+
+
+   assign 		ssel_dec[0] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s0_addr) & s0_mask);
+   assign 		ssel_dec[1] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s1_addr) & s1_mask);
+   assign 		ssel_dec[2] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s2_addr) & s2_mask);
+   assign 		ssel_dec[3] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s3_addr) & s3_mask);
+   assign 		ssel_dec[4] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s4_addr) & s4_mask);
+   assign 		ssel_dec[5] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s5_addr) & s5_mask);
+   assign 		ssel_dec[6] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s6_addr) & s6_mask);
+   assign 		ssel_dec[7] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s7_addr) & s7_mask);
+   assign 		ssel_dec[8] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s8_addr) & s8_mask);
+   assign 		ssel_dec[9] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s9_addr) & s9_mask);
+   assign 		ssel_dec[10] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sa_addr) & sa_mask);
+   assign 		ssel_dec[11] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sb_addr) & sb_mask);
+   assign 		ssel_dec[12] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sc_addr) & sc_mask);
+   assign 		ssel_dec[13] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sd_addr) & sd_mask);
+   assign 		ssel_dec[14] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ se_addr) & se_mask);
+   assign 		ssel_dec[15] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sf_addr) & sf_mask);
+
+/*
+   assign 		ssel_dec[0] = (m0_adr_i[aw -1 : aw - decode_w ] == s0_addr);
+   assign 		ssel_dec[1] = (m0_adr_i[aw -1 : aw - decode_w ] == s1_addr);
+   assign 		ssel_dec[2] = (m0_adr_i[aw -1 : aw - decode_w ] == s2_addr);
+   assign 		ssel_dec[3] = (m0_adr_i[aw -1 : aw - decode_w ] == s3_addr);
+   assign 		ssel_dec[4] = (m0_adr_i[aw -1 : aw - decode_w ] == s4_addr);
+   assign 		ssel_dec[5] = (m0_adr_i[aw -1 : aw - decode_w ] == s5_addr);
+   assign 		ssel_dec[6] = (m0_adr_i[aw -1 : aw - decode_w ] == s6_addr);
+   assign 		ssel_dec[7] = (m0_adr_i[aw -1 : aw - decode_w ] == s7_addr);
+   assign 		ssel_dec[8] = (m0_adr_i[aw -1 : aw - decode_w ] == s8_addr);
+   assign 		ssel_dec[9] = (m0_adr_i[aw -1 : aw - decode_w ] == s9_addr);
+   assign 		ssel_dec[10] = (m0_adr_i[aw -1 : aw - decode_w ] == sa_addr);
+   assign 		ssel_dec[11] = (m0_adr_i[aw -1 : aw - decode_w ] == sb_addr);
+   assign 		ssel_dec[12] = (m0_adr_i[aw -1 : aw - decode_w ] == sc_addr);
+   assign 		ssel_dec[13] = (m0_adr_i[aw -1 : aw - decode_w ] == sd_addr);
+   assign 		ssel_dec[14] = (m0_adr_i[aw -1 : aw - decode_w ] == se_addr);
+   assign 		ssel_dec[15] = (m0_adr_i[aw -1 : aw - decode_w ] == sf_addr);
+ */ 
+endmodule // wb_1master
diff --git a/fpga/usrp3/lib/xge/Makefile.srcs b/fpga/usrp3/lib/xge/Makefile.srcs
new file mode 100644
index 000000000..29e5e3e26
--- /dev/null
+++ b/fpga/usrp3/lib/xge/Makefile.srcs
@@ -0,0 +1,30 @@
+##################################################
+# OpenCore XGE MAC Sources
+##################################################
+XGE_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/xge/, \
+rtl/verilog/fault_sm.v \
+rtl/verilog/generic_fifo.v \
+rtl/verilog/generic_fifo_ctrl.v \
+rtl/verilog/generic_mem_xilinx_block.v \
+rtl/verilog/generic_mem_medium.v \
+rtl/verilog/generic_mem_small.v \
+rtl/verilog/meta_sync.v \
+rtl/verilog/meta_sync_single.v \
+rtl/verilog/rx_checker.v \
+rtl/verilog/rx_data_fifo.v \
+rtl/verilog/rx_dequeue.v \
+rtl/verilog/rx_enqueue.v \
+rtl/verilog/rx_hold_fifo.v \
+rtl/verilog/sync_clk_core.v \
+rtl/verilog/sync_clk_wb.v \
+rtl/verilog/sync_clk_xgmii_tx.v \
+rtl/verilog/tx_checker.v \
+rtl/verilog/tx_data_fifo.v \
+rtl/verilog/tx_dequeue.v \
+rtl/verilog/tx_enqueue.v \
+rtl/verilog/tx_hold_fifo.v \
+rtl/verilog/wishbone_if.v \
+rtl/verilog/xge_mac.v \
+rtl/verilog/xge_mac_wb.v \
+))
+
diff --git a/fpga/usrp3/lib/xge/README.txt b/fpga/usrp3/lib/xge/README.txt
new file mode 100644
index 000000000..d4cb1a0d0
--- /dev/null
+++ b/fpga/usrp3/lib/xge/README.txt
@@ -0,0 +1,103 @@
+
+========================
+10GE MAC Core
+========================
+
+
+------------------------
+1. Directory Structure
+------------------------
+
+The directory structure for this project is shown below.
+
+.
+|-- doc                 - Documentation files
+|
+|-- rtl
+|   |-- include         - Verilog defines and utils
+|   `-- verilog         - Verilog source files for xge_mac
+|
+|-- sim
+|   |-- systemc         - SystemC simulation directory
+|   `-- verilog         - Verilog simulation directory
+|
+`-- tbench
+    |-- systemc         - SystemC test-bench source files
+    `-- verilog         - Verilog test-bench source files
+
+
+
+------------------------
+2. Simulation
+------------------------
+
+There are two simulation environments that can be used to validate the code.
+The verilog simulation is very basic and meant for those who want to look
+at how the MAC operates without going through the effort of setting up SystemC.
+The SystemC environment is more sophisticated and covers all features of the MAC.
+
+
+
+------------------------
+2.1 Verilog Simulation
+------------------------
+
+To run the verilog simulation, compile all project files under rtl/verilog along with
+top level testbench file:
+
+  - tbench/verilog/tb_xge_mac.v
+
+There is a Modelsim "do" file called "sim.do" under sim/verilog for those using Modelsim.
+Once all the files are compiled, start simulation using entity "tb".
+
+
+The verilog simulation reads packets from "packet_tx.txt" and writes them to the MAC
+transmit fifo using the packet transmit interface (pkt_tx_data). As frames become
+available in the transmit fifo, the MAC calulates the CRC and sends them out on xgmii_tx.
+The xgmii_tx interface is looped-back to xgmii_rx in the testbench. The frames are thus
+processed by the MAC receive engine and stored in the receive fifo. The testbench reads
+frames from the receive interface (pkt_rx_data) and prints out the results.
+
+
+
+------------------------
+2.2 SystemC Simulation
+------------------------
+
+In order to use the SystemC environment it is required to first install SystemC from
+www.systemc.org. Free membership may be required to download the core SystemC files.
+
+The testbench was developed and tested with Verilator, a free HDL simulator that
+compiles verilog into C++ or SystemC code. You can download Verilator from
+www.veripool.org. You also need to install SystemPerl and Verilog-Perl for waveform
+traces.
+
+
+Once all the required tools are installed:
+
+  - Move to directory sim/systemc
+
+  - Type "./compile.sh"
+
+  - Type "./run.sh"
+
+
+If the simulation is running correctly you should see messages from the scoreboard
+as packets are transmited and received on the various interfaces.
+
+Simulation output:
+
+    -----------------------
+    Packet size 
+    -----------------------
+    SCOREBOARD XGMII INTERFACE TX (60)
+    SCOREBOARD XGMII INTERFACE TX (60)
+    SCOREBOARD PACKET INTERFACE TX (50)
+    SCOREBOARD XGMII INTERFACE TX (60)
+    SCOREBOARD PACKET INTERFACE TX (51)
+    SCOREBOARD XGMII INTERFACE TX (60)
+    SCOREBOARD PACKET INTERFACE RX (TX SIZE=60  RX SIZE=60)
+    ...
+
+
+
diff --git a/fpga/usrp3/lib/xge/doc/xge_mac_spec.pdf b/fpga/usrp3/lib/xge/doc/xge_mac_spec.pdf
new file mode 100644
index 000000000..e17e997d7
Binary files /dev/null and b/fpga/usrp3/lib/xge/doc/xge_mac_spec.pdf differ
diff --git a/fpga/usrp3/lib/xge/rtl/include/CRC32_D64.v b/fpga/usrp3/lib/xge/rtl/include/CRC32_D64.v
new file mode 100644
index 000000000..f13f85e1f
--- /dev/null
+++ b/fpga/usrp3/lib/xge/rtl/include/CRC32_D64.v
@@ -0,0 +1,266 @@
+///////////////////////////////////////////////////////////////////////
+// File:  CRC32_D64.v                             
+// Date:  Fri Feb  8 19:30:02 2008                                                      
+//                                                                     
+// Copyright (C) 1999-2003 Easics NV.                 
+// This source file may be used and distributed without restriction    
+// provided that this copyright statement is not removed from the file 
+// and that any derivative work contains the original copyright notice
+// and the associated disclaimer.
+//
+// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
+// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+//
+// Purpose: Verilog module containing a synthesizable CRC function
+//   * polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
+//   * data width: 64
+//                                                                     
+// Info: tools@easics.be
+//       http://www.easics.com                                  
+///////////////////////////////////////////////////////////////////////
+ 
+ 
+//module CRC32_D64;
+ 
+  // polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
+  // data width: 64
+  // convention: the first serial data bit is D[63]
+  function [31:0] nextCRC32_D64;
+ 
+    input [63:0] Data;
+    input [31:0] CRC;
+ 
+    reg [63:0] D;
+    reg [31:0] C;
+    reg [31:0] NewCRC;
+ 
+  begin
+ 
+    D = Data;
+    C = CRC;
+ 
+    NewCRC[0] = D[63] ^ D[61] ^ D[60] ^ D[58] ^ D[55] ^ D[54] ^ D[53] ^ 
+                D[50] ^ D[48] ^ D[47] ^ D[45] ^ D[44] ^ D[37] ^ D[34] ^ 
+                D[32] ^ D[31] ^ D[30] ^ D[29] ^ D[28] ^ D[26] ^ D[25] ^ 
+                D[24] ^ D[16] ^ D[12] ^ D[10] ^ D[9] ^ D[6] ^ D[0] ^ 
+                C[0] ^ C[2] ^ C[5] ^ C[12] ^ C[13] ^ C[15] ^ C[16] ^ 
+                C[18] ^ C[21] ^ C[22] ^ C[23] ^ C[26] ^ C[28] ^ C[29] ^ 
+                C[31];
+    NewCRC[1] = D[63] ^ D[62] ^ D[60] ^ D[59] ^ D[58] ^ D[56] ^ D[53] ^ 
+                D[51] ^ D[50] ^ D[49] ^ D[47] ^ D[46] ^ D[44] ^ D[38] ^ 
+                D[37] ^ D[35] ^ D[34] ^ D[33] ^ D[28] ^ D[27] ^ D[24] ^ 
+                D[17] ^ D[16] ^ D[13] ^ D[12] ^ D[11] ^ D[9] ^ D[7] ^ 
+                D[6] ^ D[1] ^ D[0] ^ C[1] ^ C[2] ^ C[3] ^ C[5] ^ C[6] ^ 
+                C[12] ^ C[14] ^ C[15] ^ C[17] ^ C[18] ^ C[19] ^ C[21] ^ 
+                C[24] ^ C[26] ^ C[27] ^ C[28] ^ C[30] ^ C[31];
+    NewCRC[2] = D[59] ^ D[58] ^ D[57] ^ D[55] ^ D[53] ^ D[52] ^ D[51] ^ 
+                D[44] ^ D[39] ^ D[38] ^ D[37] ^ D[36] ^ D[35] ^ D[32] ^ 
+                D[31] ^ D[30] ^ D[26] ^ D[24] ^ D[18] ^ D[17] ^ D[16] ^ 
+                D[14] ^ D[13] ^ D[9] ^ D[8] ^ D[7] ^ D[6] ^ D[2] ^ 
+                D[1] ^ D[0] ^ C[0] ^ C[3] ^ C[4] ^ C[5] ^ C[6] ^ C[7] ^ 
+                C[12] ^ C[19] ^ C[20] ^ C[21] ^ C[23] ^ C[25] ^ C[26] ^ 
+                C[27];
+    NewCRC[3] = D[60] ^ D[59] ^ D[58] ^ D[56] ^ D[54] ^ D[53] ^ D[52] ^ 
+                D[45] ^ D[40] ^ D[39] ^ D[38] ^ D[37] ^ D[36] ^ D[33] ^ 
+                D[32] ^ D[31] ^ D[27] ^ D[25] ^ D[19] ^ D[18] ^ D[17] ^ 
+                D[15] ^ D[14] ^ D[10] ^ D[9] ^ D[8] ^ D[7] ^ D[3] ^ 
+                D[2] ^ D[1] ^ C[0] ^ C[1] ^ C[4] ^ C[5] ^ C[6] ^ C[7] ^ 
+                C[8] ^ C[13] ^ C[20] ^ C[21] ^ C[22] ^ C[24] ^ C[26] ^ 
+                C[27] ^ C[28];
+    NewCRC[4] = D[63] ^ D[59] ^ D[58] ^ D[57] ^ D[50] ^ D[48] ^ D[47] ^ 
+                D[46] ^ D[45] ^ D[44] ^ D[41] ^ D[40] ^ D[39] ^ D[38] ^ 
+                D[33] ^ D[31] ^ D[30] ^ D[29] ^ D[25] ^ D[24] ^ D[20] ^ 
+                D[19] ^ D[18] ^ D[15] ^ D[12] ^ D[11] ^ D[8] ^ D[6] ^ 
+                D[4] ^ D[3] ^ D[2] ^ D[0] ^ C[1] ^ C[6] ^ C[7] ^ C[8] ^ 
+                C[9] ^ C[12] ^ C[13] ^ C[14] ^ C[15] ^ C[16] ^ C[18] ^ 
+                C[25] ^ C[26] ^ C[27] ^ C[31];
+    NewCRC[5] = D[63] ^ D[61] ^ D[59] ^ D[55] ^ D[54] ^ D[53] ^ D[51] ^ 
+                D[50] ^ D[49] ^ D[46] ^ D[44] ^ D[42] ^ D[41] ^ D[40] ^ 
+                D[39] ^ D[37] ^ D[29] ^ D[28] ^ D[24] ^ D[21] ^ D[20] ^ 
+                D[19] ^ D[13] ^ D[10] ^ D[7] ^ D[6] ^ D[5] ^ D[4] ^ 
+                D[3] ^ D[1] ^ D[0] ^ C[5] ^ C[7] ^ C[8] ^ C[9] ^ C[10] ^ 
+                C[12] ^ C[14] ^ C[17] ^ C[18] ^ C[19] ^ C[21] ^ C[22] ^ 
+                C[23] ^ C[27] ^ C[29] ^ C[31];
+    NewCRC[6] = D[62] ^ D[60] ^ D[56] ^ D[55] ^ D[54] ^ D[52] ^ D[51] ^ 
+                D[50] ^ D[47] ^ D[45] ^ D[43] ^ D[42] ^ D[41] ^ D[40] ^ 
+                D[38] ^ D[30] ^ D[29] ^ D[25] ^ D[22] ^ D[21] ^ D[20] ^ 
+                D[14] ^ D[11] ^ D[8] ^ D[7] ^ D[6] ^ D[5] ^ D[4] ^ 
+                D[2] ^ D[1] ^ C[6] ^ C[8] ^ C[9] ^ C[10] ^ C[11] ^ 
+                C[13] ^ C[15] ^ C[18] ^ C[19] ^ C[20] ^ C[22] ^ C[23] ^ 
+                C[24] ^ C[28] ^ C[30];
+    NewCRC[7] = D[60] ^ D[58] ^ D[57] ^ D[56] ^ D[54] ^ D[52] ^ D[51] ^ 
+                D[50] ^ D[47] ^ D[46] ^ D[45] ^ D[43] ^ D[42] ^ D[41] ^ 
+                D[39] ^ D[37] ^ D[34] ^ D[32] ^ D[29] ^ D[28] ^ D[25] ^ 
+                D[24] ^ D[23] ^ D[22] ^ D[21] ^ D[16] ^ D[15] ^ D[10] ^ 
+                D[8] ^ D[7] ^ D[5] ^ D[3] ^ D[2] ^ D[0] ^ C[0] ^ C[2] ^ 
+                C[5] ^ C[7] ^ C[9] ^ C[10] ^ C[11] ^ C[13] ^ C[14] ^ 
+                C[15] ^ C[18] ^ C[19] ^ C[20] ^ C[22] ^ C[24] ^ C[25] ^ 
+                C[26] ^ C[28];
+    NewCRC[8] = D[63] ^ D[60] ^ D[59] ^ D[57] ^ D[54] ^ D[52] ^ D[51] ^ 
+                D[50] ^ D[46] ^ D[45] ^ D[43] ^ D[42] ^ D[40] ^ D[38] ^ 
+                D[37] ^ D[35] ^ D[34] ^ D[33] ^ D[32] ^ D[31] ^ D[28] ^ 
+                D[23] ^ D[22] ^ D[17] ^ D[12] ^ D[11] ^ D[10] ^ D[8] ^ 
+                D[4] ^ D[3] ^ D[1] ^ D[0] ^ C[0] ^ C[1] ^ C[2] ^ C[3] ^ 
+                C[5] ^ C[6] ^ C[8] ^ C[10] ^ C[11] ^ C[13] ^ C[14] ^ 
+                C[18] ^ C[19] ^ C[20] ^ C[22] ^ C[25] ^ C[27] ^ C[28] ^ 
+                C[31];
+    NewCRC[9] = D[61] ^ D[60] ^ D[58] ^ D[55] ^ D[53] ^ D[52] ^ D[51] ^ 
+                D[47] ^ D[46] ^ D[44] ^ D[43] ^ D[41] ^ D[39] ^ D[38] ^ 
+                D[36] ^ D[35] ^ D[34] ^ D[33] ^ D[32] ^ D[29] ^ D[24] ^ 
+                D[23] ^ D[18] ^ D[13] ^ D[12] ^ D[11] ^ D[9] ^ D[5] ^ 
+                D[4] ^ D[2] ^ D[1] ^ C[0] ^ C[1] ^ C[2] ^ C[3] ^ C[4] ^ 
+                C[6] ^ C[7] ^ C[9] ^ C[11] ^ C[12] ^ C[14] ^ C[15] ^ 
+                C[19] ^ C[20] ^ C[21] ^ C[23] ^ C[26] ^ C[28] ^ C[29];
+    NewCRC[10] = D[63] ^ D[62] ^ D[60] ^ D[59] ^ D[58] ^ D[56] ^ D[55] ^ 
+                 D[52] ^ D[50] ^ D[42] ^ D[40] ^ D[39] ^ D[36] ^ D[35] ^ 
+                 D[33] ^ D[32] ^ D[31] ^ D[29] ^ D[28] ^ D[26] ^ D[19] ^ 
+                 D[16] ^ D[14] ^ D[13] ^ D[9] ^ D[5] ^ D[3] ^ D[2] ^ 
+                 D[0] ^ C[0] ^ C[1] ^ C[3] ^ C[4] ^ C[7] ^ C[8] ^ C[10] ^ 
+                 C[18] ^ C[20] ^ C[23] ^ C[24] ^ C[26] ^ C[27] ^ C[28] ^ 
+                 C[30] ^ C[31];
+    NewCRC[11] = D[59] ^ D[58] ^ D[57] ^ D[56] ^ D[55] ^ D[54] ^ D[51] ^ 
+                 D[50] ^ D[48] ^ D[47] ^ D[45] ^ D[44] ^ D[43] ^ D[41] ^ 
+                 D[40] ^ D[36] ^ D[33] ^ D[31] ^ D[28] ^ D[27] ^ D[26] ^ 
+                 D[25] ^ D[24] ^ D[20] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ 
+                 D[12] ^ D[9] ^ D[4] ^ D[3] ^ D[1] ^ D[0] ^ C[1] ^ C[4] ^ 
+                 C[8] ^ C[9] ^ C[11] ^ C[12] ^ C[13] ^ C[15] ^ C[16] ^ 
+                 C[18] ^ C[19] ^ C[22] ^ C[23] ^ C[24] ^ C[25] ^ C[26] ^ 
+                 C[27];
+    NewCRC[12] = D[63] ^ D[61] ^ D[59] ^ D[57] ^ D[56] ^ D[54] ^ D[53] ^ 
+                 D[52] ^ D[51] ^ D[50] ^ D[49] ^ D[47] ^ D[46] ^ D[42] ^ 
+                 D[41] ^ D[31] ^ D[30] ^ D[27] ^ D[24] ^ D[21] ^ D[18] ^ 
+                 D[17] ^ D[15] ^ D[13] ^ D[12] ^ D[9] ^ D[6] ^ D[5] ^ 
+                 D[4] ^ D[2] ^ D[1] ^ D[0] ^ C[9] ^ C[10] ^ C[14] ^ 
+                 C[15] ^ C[17] ^ C[18] ^ C[19] ^ C[20] ^ C[21] ^ C[22] ^ 
+                 C[24] ^ C[25] ^ C[27] ^ C[29] ^ C[31];
+    NewCRC[13] = D[62] ^ D[60] ^ D[58] ^ D[57] ^ D[55] ^ D[54] ^ D[53] ^ 
+                 D[52] ^ D[51] ^ D[50] ^ D[48] ^ D[47] ^ D[43] ^ D[42] ^ 
+                 D[32] ^ D[31] ^ D[28] ^ D[25] ^ D[22] ^ D[19] ^ D[18] ^ 
+                 D[16] ^ D[14] ^ D[13] ^ D[10] ^ D[7] ^ D[6] ^ D[5] ^ 
+                 D[3] ^ D[2] ^ D[1] ^ C[0] ^ C[10] ^ C[11] ^ C[15] ^ 
+                 C[16] ^ C[18] ^ C[19] ^ C[20] ^ C[21] ^ C[22] ^ C[23] ^ 
+                 C[25] ^ C[26] ^ C[28] ^ C[30];
+    NewCRC[14] = D[63] ^ D[61] ^ D[59] ^ D[58] ^ D[56] ^ D[55] ^ D[54] ^ 
+                 D[53] ^ D[52] ^ D[51] ^ D[49] ^ D[48] ^ D[44] ^ D[43] ^ 
+                 D[33] ^ D[32] ^ D[29] ^ D[26] ^ D[23] ^ D[20] ^ D[19] ^ 
+                 D[17] ^ D[15] ^ D[14] ^ D[11] ^ D[8] ^ D[7] ^ D[6] ^ 
+                 D[4] ^ D[3] ^ D[2] ^ C[0] ^ C[1] ^ C[11] ^ C[12] ^ 
+                 C[16] ^ C[17] ^ C[19] ^ C[20] ^ C[21] ^ C[22] ^ C[23] ^ 
+                 C[24] ^ C[26] ^ C[27] ^ C[29] ^ C[31];
+    NewCRC[15] = D[62] ^ D[60] ^ D[59] ^ D[57] ^ D[56] ^ D[55] ^ D[54] ^ 
+                 D[53] ^ D[52] ^ D[50] ^ D[49] ^ D[45] ^ D[44] ^ D[34] ^ 
+                 D[33] ^ D[30] ^ D[27] ^ D[24] ^ D[21] ^ D[20] ^ D[18] ^ 
+                 D[16] ^ D[15] ^ D[12] ^ D[9] ^ D[8] ^ D[7] ^ D[5] ^ 
+                 D[4] ^ D[3] ^ C[1] ^ C[2] ^ C[12] ^ C[13] ^ C[17] ^ 
+                 C[18] ^ C[20] ^ C[21] ^ C[22] ^ C[23] ^ C[24] ^ C[25] ^ 
+                 C[27] ^ C[28] ^ C[30];
+    NewCRC[16] = D[57] ^ D[56] ^ D[51] ^ D[48] ^ D[47] ^ D[46] ^ D[44] ^ 
+                 D[37] ^ D[35] ^ D[32] ^ D[30] ^ D[29] ^ D[26] ^ D[24] ^ 
+                 D[22] ^ D[21] ^ D[19] ^ D[17] ^ D[13] ^ D[12] ^ D[8] ^ 
+                 D[5] ^ D[4] ^ D[0] ^ C[0] ^ C[3] ^ C[5] ^ C[12] ^ C[14] ^ 
+                 C[15] ^ C[16] ^ C[19] ^ C[24] ^ C[25];
+    NewCRC[17] = D[58] ^ D[57] ^ D[52] ^ D[49] ^ D[48] ^ D[47] ^ D[45] ^ 
+                 D[38] ^ D[36] ^ D[33] ^ D[31] ^ D[30] ^ D[27] ^ D[25] ^ 
+                 D[23] ^ D[22] ^ D[20] ^ D[18] ^ D[14] ^ D[13] ^ D[9] ^ 
+                 D[6] ^ D[5] ^ D[1] ^ C[1] ^ C[4] ^ C[6] ^ C[13] ^ C[15] ^ 
+                 C[16] ^ C[17] ^ C[20] ^ C[25] ^ C[26];
+    NewCRC[18] = D[59] ^ D[58] ^ D[53] ^ D[50] ^ D[49] ^ D[48] ^ D[46] ^ 
+                 D[39] ^ D[37] ^ D[34] ^ D[32] ^ D[31] ^ D[28] ^ D[26] ^ 
+                 D[24] ^ D[23] ^ D[21] ^ D[19] ^ D[15] ^ D[14] ^ D[10] ^ 
+                 D[7] ^ D[6] ^ D[2] ^ C[0] ^ C[2] ^ C[5] ^ C[7] ^ C[14] ^ 
+                 C[16] ^ C[17] ^ C[18] ^ C[21] ^ C[26] ^ C[27];
+    NewCRC[19] = D[60] ^ D[59] ^ D[54] ^ D[51] ^ D[50] ^ D[49] ^ D[47] ^ 
+                 D[40] ^ D[38] ^ D[35] ^ D[33] ^ D[32] ^ D[29] ^ D[27] ^ 
+                 D[25] ^ D[24] ^ D[22] ^ D[20] ^ D[16] ^ D[15] ^ D[11] ^ 
+                 D[8] ^ D[7] ^ D[3] ^ C[0] ^ C[1] ^ C[3] ^ C[6] ^ C[8] ^ 
+                 C[15] ^ C[17] ^ C[18] ^ C[19] ^ C[22] ^ C[27] ^ C[28];
+    NewCRC[20] = D[61] ^ D[60] ^ D[55] ^ D[52] ^ D[51] ^ D[50] ^ D[48] ^ 
+                 D[41] ^ D[39] ^ D[36] ^ D[34] ^ D[33] ^ D[30] ^ D[28] ^ 
+                 D[26] ^ D[25] ^ D[23] ^ D[21] ^ D[17] ^ D[16] ^ D[12] ^ 
+                 D[9] ^ D[8] ^ D[4] ^ C[1] ^ C[2] ^ C[4] ^ C[7] ^ C[9] ^ 
+                 C[16] ^ C[18] ^ C[19] ^ C[20] ^ C[23] ^ C[28] ^ C[29];
+    NewCRC[21] = D[62] ^ D[61] ^ D[56] ^ D[53] ^ D[52] ^ D[51] ^ D[49] ^ 
+                 D[42] ^ D[40] ^ D[37] ^ D[35] ^ D[34] ^ D[31] ^ D[29] ^ 
+                 D[27] ^ D[26] ^ D[24] ^ D[22] ^ D[18] ^ D[17] ^ D[13] ^ 
+                 D[10] ^ D[9] ^ D[5] ^ C[2] ^ C[3] ^ C[5] ^ C[8] ^ C[10] ^ 
+                 C[17] ^ C[19] ^ C[20] ^ C[21] ^ C[24] ^ C[29] ^ C[30];
+    NewCRC[22] = D[62] ^ D[61] ^ D[60] ^ D[58] ^ D[57] ^ D[55] ^ D[52] ^ 
+                 D[48] ^ D[47] ^ D[45] ^ D[44] ^ D[43] ^ D[41] ^ D[38] ^ 
+                 D[37] ^ D[36] ^ D[35] ^ D[34] ^ D[31] ^ D[29] ^ D[27] ^ 
+                 D[26] ^ D[24] ^ D[23] ^ D[19] ^ D[18] ^ D[16] ^ D[14] ^ 
+                 D[12] ^ D[11] ^ D[9] ^ D[0] ^ C[2] ^ C[3] ^ C[4] ^ 
+                 C[5] ^ C[6] ^ C[9] ^ C[11] ^ C[12] ^ C[13] ^ C[15] ^ 
+                 C[16] ^ C[20] ^ C[23] ^ C[25] ^ C[26] ^ C[28] ^ C[29] ^ 
+                 C[30];
+    NewCRC[23] = D[62] ^ D[60] ^ D[59] ^ D[56] ^ D[55] ^ D[54] ^ D[50] ^ 
+                 D[49] ^ D[47] ^ D[46] ^ D[42] ^ D[39] ^ D[38] ^ D[36] ^ 
+                 D[35] ^ D[34] ^ D[31] ^ D[29] ^ D[27] ^ D[26] ^ D[20] ^ 
+                 D[19] ^ D[17] ^ D[16] ^ D[15] ^ D[13] ^ D[9] ^ D[6] ^ 
+                 D[1] ^ D[0] ^ C[2] ^ C[3] ^ C[4] ^ C[6] ^ C[7] ^ C[10] ^ 
+                 C[14] ^ C[15] ^ C[17] ^ C[18] ^ C[22] ^ C[23] ^ C[24] ^ 
+                 C[27] ^ C[28] ^ C[30];
+    NewCRC[24] = D[63] ^ D[61] ^ D[60] ^ D[57] ^ D[56] ^ D[55] ^ D[51] ^ 
+                 D[50] ^ D[48] ^ D[47] ^ D[43] ^ D[40] ^ D[39] ^ D[37] ^ 
+                 D[36] ^ D[35] ^ D[32] ^ D[30] ^ D[28] ^ D[27] ^ D[21] ^ 
+                 D[20] ^ D[18] ^ D[17] ^ D[16] ^ D[14] ^ D[10] ^ D[7] ^ 
+                 D[2] ^ D[1] ^ C[0] ^ C[3] ^ C[4] ^ C[5] ^ C[7] ^ C[8] ^ 
+                 C[11] ^ C[15] ^ C[16] ^ C[18] ^ C[19] ^ C[23] ^ C[24] ^ 
+                 C[25] ^ C[28] ^ C[29] ^ C[31];
+    NewCRC[25] = D[62] ^ D[61] ^ D[58] ^ D[57] ^ D[56] ^ D[52] ^ D[51] ^ 
+                 D[49] ^ D[48] ^ D[44] ^ D[41] ^ D[40] ^ D[38] ^ D[37] ^ 
+                 D[36] ^ D[33] ^ D[31] ^ D[29] ^ D[28] ^ D[22] ^ D[21] ^ 
+                 D[19] ^ D[18] ^ D[17] ^ D[15] ^ D[11] ^ D[8] ^ D[3] ^ 
+                 D[2] ^ C[1] ^ C[4] ^ C[5] ^ C[6] ^ C[8] ^ C[9] ^ C[12] ^ 
+                 C[16] ^ C[17] ^ C[19] ^ C[20] ^ C[24] ^ C[25] ^ C[26] ^ 
+                 C[29] ^ C[30];
+    NewCRC[26] = D[62] ^ D[61] ^ D[60] ^ D[59] ^ D[57] ^ D[55] ^ D[54] ^ 
+                 D[52] ^ D[49] ^ D[48] ^ D[47] ^ D[44] ^ D[42] ^ D[41] ^ 
+                 D[39] ^ D[38] ^ D[31] ^ D[28] ^ D[26] ^ D[25] ^ D[24] ^ 
+                 D[23] ^ D[22] ^ D[20] ^ D[19] ^ D[18] ^ D[10] ^ D[6] ^ 
+                 D[4] ^ D[3] ^ D[0] ^ C[6] ^ C[7] ^ C[9] ^ C[10] ^ C[12] ^ 
+                 C[15] ^ C[16] ^ C[17] ^ C[20] ^ C[22] ^ C[23] ^ C[25] ^ 
+                 C[27] ^ C[28] ^ C[29] ^ C[30];
+    NewCRC[27] = D[63] ^ D[62] ^ D[61] ^ D[60] ^ D[58] ^ D[56] ^ D[55] ^ 
+                 D[53] ^ D[50] ^ D[49] ^ D[48] ^ D[45] ^ D[43] ^ D[42] ^ 
+                 D[40] ^ D[39] ^ D[32] ^ D[29] ^ D[27] ^ D[26] ^ D[25] ^ 
+                 D[24] ^ D[23] ^ D[21] ^ D[20] ^ D[19] ^ D[11] ^ D[7] ^ 
+                 D[5] ^ D[4] ^ D[1] ^ C[0] ^ C[7] ^ C[8] ^ C[10] ^ C[11] ^ 
+                 C[13] ^ C[16] ^ C[17] ^ C[18] ^ C[21] ^ C[23] ^ C[24] ^ 
+                 C[26] ^ C[28] ^ C[29] ^ C[30] ^ C[31];
+    NewCRC[28] = D[63] ^ D[62] ^ D[61] ^ D[59] ^ D[57] ^ D[56] ^ D[54] ^ 
+                 D[51] ^ D[50] ^ D[49] ^ D[46] ^ D[44] ^ D[43] ^ D[41] ^ 
+                 D[40] ^ D[33] ^ D[30] ^ D[28] ^ D[27] ^ D[26] ^ D[25] ^ 
+                 D[24] ^ D[22] ^ D[21] ^ D[20] ^ D[12] ^ D[8] ^ D[6] ^ 
+                 D[5] ^ D[2] ^ C[1] ^ C[8] ^ C[9] ^ C[11] ^ C[12] ^ 
+                 C[14] ^ C[17] ^ C[18] ^ C[19] ^ C[22] ^ C[24] ^ C[25] ^ 
+                 C[27] ^ C[29] ^ C[30] ^ C[31];
+    NewCRC[29] = D[63] ^ D[62] ^ D[60] ^ D[58] ^ D[57] ^ D[55] ^ D[52] ^ 
+                 D[51] ^ D[50] ^ D[47] ^ D[45] ^ D[44] ^ D[42] ^ D[41] ^ 
+                 D[34] ^ D[31] ^ D[29] ^ D[28] ^ D[27] ^ D[26] ^ D[25] ^ 
+                 D[23] ^ D[22] ^ D[21] ^ D[13] ^ D[9] ^ D[7] ^ D[6] ^ 
+                 D[3] ^ C[2] ^ C[9] ^ C[10] ^ C[12] ^ C[13] ^ C[15] ^ 
+                 C[18] ^ C[19] ^ C[20] ^ C[23] ^ C[25] ^ C[26] ^ C[28] ^ 
+                 C[30] ^ C[31];
+    NewCRC[30] = D[63] ^ D[61] ^ D[59] ^ D[58] ^ D[56] ^ D[53] ^ D[52] ^ 
+                 D[51] ^ D[48] ^ D[46] ^ D[45] ^ D[43] ^ D[42] ^ D[35] ^ 
+                 D[32] ^ D[30] ^ D[29] ^ D[28] ^ D[27] ^ D[26] ^ D[24] ^ 
+                 D[23] ^ D[22] ^ D[14] ^ D[10] ^ D[8] ^ D[7] ^ D[4] ^ 
+                 C[0] ^ C[3] ^ C[10] ^ C[11] ^ C[13] ^ C[14] ^ C[16] ^ 
+                 C[19] ^ C[20] ^ C[21] ^ C[24] ^ C[26] ^ C[27] ^ C[29] ^ 
+                 C[31];
+    NewCRC[31] = D[62] ^ D[60] ^ D[59] ^ D[57] ^ D[54] ^ D[53] ^ D[52] ^ 
+                 D[49] ^ D[47] ^ D[46] ^ D[44] ^ D[43] ^ D[36] ^ D[33] ^ 
+                 D[31] ^ D[30] ^ D[29] ^ D[28] ^ D[27] ^ D[25] ^ D[24] ^ 
+                 D[23] ^ D[15] ^ D[11] ^ D[9] ^ D[8] ^ D[5] ^ C[1] ^ 
+                 C[4] ^ C[11] ^ C[12] ^ C[14] ^ C[15] ^ C[17] ^ C[20] ^ 
+                 C[21] ^ C[22] ^ C[25] ^ C[27] ^ C[28] ^ C[30];
+ 
+    nextCRC32_D64 = NewCRC;
+ 
+  end
+ 
+  endfunction
+ 
+//endmodule
+ 
diff --git a/fpga/usrp3/lib/xge/rtl/include/CRC32_D8.v b/fpga/usrp3/lib/xge/rtl/include/CRC32_D8.v
new file mode 100644
index 000000000..814648684
--- /dev/null
+++ b/fpga/usrp3/lib/xge/rtl/include/CRC32_D8.v
@@ -0,0 +1,101 @@
+///////////////////////////////////////////////////////////////////////
+// File:  CRC32_D8.v                             
+// Date:  Fri Feb  8 19:26:59 2008                                                      
+//                                                                     
+// Copyright (C) 1999-2003 Easics NV.                 
+// This source file may be used and distributed without restriction    
+// provided that this copyright statement is not removed from the file 
+// and that any derivative work contains the original copyright notice
+// and the associated disclaimer.
+//
+// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
+// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+//
+// Purpose: Verilog module containing a synthesizable CRC function
+//   * polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
+//   * data width: 8
+//                                                                     
+// Info: tools@easics.be
+//       http://www.easics.com                                  
+///////////////////////////////////////////////////////////////////////
+ 
+ 
+//module CRC32_D8;
+ 
+  // polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
+  // data width: 8
+  // convention: the first serial data bit is D[7]
+  function [31:0] nextCRC32_D8;
+ 
+    input [7:0] Data;
+    input [31:0] CRC;
+ 
+    reg [7:0] D;
+    reg [31:0] C;
+    reg [31:0] NewCRC;
+ 
+  begin
+ 
+    D = Data;
+    C = CRC;
+ 
+    NewCRC[0] = D[6] ^ D[0] ^ C[24] ^ C[30];
+    NewCRC[1] = D[7] ^ D[6] ^ D[1] ^ D[0] ^ C[24] ^ C[25] ^ C[30] ^ 
+                C[31];
+    NewCRC[2] = D[7] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^ C[24] ^ C[25] ^ 
+                C[26] ^ C[30] ^ C[31];
+    NewCRC[3] = D[7] ^ D[3] ^ D[2] ^ D[1] ^ C[25] ^ C[26] ^ C[27] ^ 
+                C[31];
+    NewCRC[4] = D[6] ^ D[4] ^ D[3] ^ D[2] ^ D[0] ^ C[24] ^ C[26] ^ 
+                C[27] ^ C[28] ^ C[30];
+    NewCRC[5] = D[7] ^ D[6] ^ D[5] ^ D[4] ^ D[3] ^ D[1] ^ D[0] ^ C[24] ^ 
+                C[25] ^ C[27] ^ C[28] ^ C[29] ^ C[30] ^ C[31];
+    NewCRC[6] = D[7] ^ D[6] ^ D[5] ^ D[4] ^ D[2] ^ D[1] ^ C[25] ^ C[26] ^ 
+                C[28] ^ C[29] ^ C[30] ^ C[31];
+    NewCRC[7] = D[7] ^ D[5] ^ D[3] ^ D[2] ^ D[0] ^ C[24] ^ C[26] ^ 
+                C[27] ^ C[29] ^ C[31];
+    NewCRC[8] = D[4] ^ D[3] ^ D[1] ^ D[0] ^ C[0] ^ C[24] ^ C[25] ^ 
+                C[27] ^ C[28];
+    NewCRC[9] = D[5] ^ D[4] ^ D[2] ^ D[1] ^ C[1] ^ C[25] ^ C[26] ^ 
+                C[28] ^ C[29];
+    NewCRC[10] = D[5] ^ D[3] ^ D[2] ^ D[0] ^ C[2] ^ C[24] ^ C[26] ^ 
+                 C[27] ^ C[29];
+    NewCRC[11] = D[4] ^ D[3] ^ D[1] ^ D[0] ^ C[3] ^ C[24] ^ C[25] ^ 
+                 C[27] ^ C[28];
+    NewCRC[12] = D[6] ^ D[5] ^ D[4] ^ D[2] ^ D[1] ^ D[0] ^ C[4] ^ C[24] ^ 
+                 C[25] ^ C[26] ^ C[28] ^ C[29] ^ C[30];
+    NewCRC[13] = D[7] ^ D[6] ^ D[5] ^ D[3] ^ D[2] ^ D[1] ^ C[5] ^ C[25] ^ 
+                 C[26] ^ C[27] ^ C[29] ^ C[30] ^ C[31];
+    NewCRC[14] = D[7] ^ D[6] ^ D[4] ^ D[3] ^ D[2] ^ C[6] ^ C[26] ^ C[27] ^ 
+                 C[28] ^ C[30] ^ C[31];
+    NewCRC[15] = D[7] ^ D[5] ^ D[4] ^ D[3] ^ C[7] ^ C[27] ^ C[28] ^ 
+                 C[29] ^ C[31];
+    NewCRC[16] = D[5] ^ D[4] ^ D[0] ^ C[8] ^ C[24] ^ C[28] ^ C[29];
+    NewCRC[17] = D[6] ^ D[5] ^ D[1] ^ C[9] ^ C[25] ^ C[29] ^ C[30];
+    NewCRC[18] = D[7] ^ D[6] ^ D[2] ^ C[10] ^ C[26] ^ C[30] ^ C[31];
+    NewCRC[19] = D[7] ^ D[3] ^ C[11] ^ C[27] ^ C[31];
+    NewCRC[20] = D[4] ^ C[12] ^ C[28];
+    NewCRC[21] = D[5] ^ C[13] ^ C[29];
+    NewCRC[22] = D[0] ^ C[14] ^ C[24];
+    NewCRC[23] = D[6] ^ D[1] ^ D[0] ^ C[15] ^ C[24] ^ C[25] ^ C[30];
+    NewCRC[24] = D[7] ^ D[2] ^ D[1] ^ C[16] ^ C[25] ^ C[26] ^ C[31];
+    NewCRC[25] = D[3] ^ D[2] ^ C[17] ^ C[26] ^ C[27];
+    NewCRC[26] = D[6] ^ D[4] ^ D[3] ^ D[0] ^ C[18] ^ C[24] ^ C[27] ^ 
+                 C[28] ^ C[30];
+    NewCRC[27] = D[7] ^ D[5] ^ D[4] ^ D[1] ^ C[19] ^ C[25] ^ C[28] ^ 
+                 C[29] ^ C[31];
+    NewCRC[28] = D[6] ^ D[5] ^ D[2] ^ C[20] ^ C[26] ^ C[29] ^ C[30];
+    NewCRC[29] = D[7] ^ D[6] ^ D[3] ^ C[21] ^ C[27] ^ C[30] ^ C[31];
+    NewCRC[30] = D[7] ^ D[4] ^ C[22] ^ C[28] ^ C[31];
+    NewCRC[31] = D[5] ^ C[23] ^ C[29];
+ 
+    nextCRC32_D8 = NewCRC;
+ 
+  end
+ 
+  endfunction
+ 
+//endmodule
+ 
+ 
\ No newline at end of file
diff --git a/fpga/usrp3/lib/xge/rtl/include/defines.v b/fpga/usrp3/lib/xge/rtl/include/defines.v
new file mode 100644
index 000000000..095f303bf
--- /dev/null
+++ b/fpga/usrp3/lib/xge/rtl/include/defines.v
@@ -0,0 +1,125 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  File name "defines.v"                                       ////
+////                                                              ////
+////  This file is part of the "10GE MAC" project                 ////
+////  http://www.opencores.org/cores/xge_mac/                     ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - A. Tanguay (antanguay@opencores.org)                  ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2008 AUTHORS. All rights reserved.             ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+ 
+// Define MDIO to add support for clause 22 and clause 45 MDIO interface
+`define MDIO
+// If WB clock is 62.5MHz and max MDC spec is 2.5MHz, then divide by 25
+//`define MDC_HALF_PERIOD 13 // Closest int to 12.5
+`define MDC_HALF_PERIOD 100
+ 
+// CPU Registers
+ 
+`define CPUREG_CONFIG0      8'h00
+`define CPUREG_INT_PENDING  8'h04
+`define CPUREG_INT_STATUS   8'h08
+`define CPUREG_INT_MASK     8'h0c
+//`ifdef MDIO
+`define CPUREG_MDIO_DATA    8'h10
+`define CPUREG_MDIO_ADDR    8'h14
+`define CPUREG_MDIO_OP      8'h18
+`define CPUREG_MDIO_CONTROL 8'h1c
+`define CPUREG_MDIO_STATUS  8'h1c
+`define CPUREG_GPIO         8'h20
+//`endif
+
+// Ethernet codes
+ 
+`define IDLE       8'h07
+`define PREAMBLE   8'h55
+`define SEQUENCE   8'h9c
+`define SFD        8'hd5
+`define START      8'hfb
+`define TERMINATE  8'hfd
+`define ERROR      8'hfe
+ 
+ 
+ 
+`define LINK_FAULT_OK      2'd0
+`define LINK_FAULT_LOCAL   2'd1
+`define LINK_FAULT_REMOTE  2'd2
+ 
+`define FAULT_SEQ_LOCAL  1'b0
+`define FAULT_SEQ_REMOTE 1'b1
+ 
+`define LOCAL_FAULT   8'd1
+`define REMOTE_FAULT  8'd2
+ 
+`define PAUSE_FRAME   48'h010000c28001
+ 
+`define LANE0        7:0
+`define LANE1       15:8
+`define LANE2      23:16
+`define LANE3      31:24
+`define LANE4      39:32
+`define LANE5      47:40
+`define LANE6      55:48
+`define LANE7      63:56
+ 
+ 
+`define TXSTATUS_NONE       8'h0
+`define TXSTATUS_EOP        3'd6
+`define TXSTATUS_SOP        3'd7
+ 
+`define RXSTATUS_NONE       8'h0
+`define RXSTATUS_ERR        3'd5
+`define RXSTATUS_EOP        3'd6
+`define RXSTATUS_SOP        3'd7
+ 
+ 
+//
+// FIFO Size: 8 * (2^AWIDTH) will be the size in bytes
+//            7 --> 128 entries, 1024 bytes for data fifo
+//
+`define TX_DATA_FIFO_AWIDTH 9
+`define RX_DATA_FIFO_AWIDTH 9
+ 
+//
+// FIFO Size: Holding FIFOs are 16 deep
+//
+`define TX_HOLD_FIFO_AWIDTH 4
+`define RX_HOLD_FIFO_AWIDTH 4
+ 
+ 
+// Memory types
+`define MEM_AUTO_SMALL 1
+`define MEM_AUTO_MEDIUM 2
+`define MEM_AUTO_XILINX 3
+ 
+ 
+// Changed system packet interface to big endian (12/12/2009)
+// Comment out to use legacy mode
+`define BIGENDIAN
diff --git a/fpga/usrp3/lib/xge/rtl/include/timescale.v b/fpga/usrp3/lib/xge/rtl/include/timescale.v
new file mode 100644
index 000000000..64502185f
--- /dev/null
+++ b/fpga/usrp3/lib/xge/rtl/include/timescale.v
@@ -0,0 +1 @@
+`timescale 1ps / 1ps
diff --git a/fpga/usrp3/lib/xge/rtl/include/utils.v b/fpga/usrp3/lib/xge/rtl/include/utils.v
new file mode 100644
index 000000000..6137b3e31
--- /dev/null
+++ b/fpga/usrp3/lib/xge/rtl/include/utils.v
@@ -0,0 +1,71 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  File name "utils.v"                                         ////
+////                                                              ////
+////  This file is part of the "10GE MAC" project                 ////
+////  http://www.opencores.org/cores/xge_mac/                     ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - A. Tanguay (antanguay@opencores.org)                  ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2008 AUTHORS. All rights reserved.             ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+ 
+ 
+function [63:0] reverse_64b;
+  input [63:0]   data;
+  integer        i;
+    begin
+        for (i = 0; i < 64; i = i + 1) begin
+            reverse_64b[i] = data[63 - i];
+        end
+    end
+endfunction
+ 
+ 
+function [31:0] reverse_32b;
+  input [31:0]   data;
+  integer        i;
+    begin
+        for (i = 0; i < 32; i = i + 1) begin
+            reverse_32b[i] = data[31 - i];
+        end
+    end
+endfunction
+ 
+ 
+function [7:0] reverse_8b;
+  input [7:0]   data;
+  integer        i;
+    begin
+        for (i = 0; i < 8; i = i + 1) begin
+            reverse_8b[i] = data[7 - i];
+        end
+    end
+endfunction
+ 
+ 
diff --git a/fpga/usrp3/lib/xge/rtl/verilog/CRC32_D64.v b/fpga/usrp3/lib/xge/rtl/verilog/CRC32_D64.v
new file mode 100644
index 000000000..f13f85e1f
--- /dev/null
+++ b/fpga/usrp3/lib/xge/rtl/verilog/CRC32_D64.v
@@ -0,0 +1,266 @@
+///////////////////////////////////////////////////////////////////////
+// File:  CRC32_D64.v                             
+// Date:  Fri Feb  8 19:30:02 2008                                                      
+//                                                                     
+// Copyright (C) 1999-2003 Easics NV.                 
+// This source file may be used and distributed without restriction    
+// provided that this copyright statement is not removed from the file 
+// and that any derivative work contains the original copyright notice
+// and the associated disclaimer.
+//
+// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
+// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+//
+// Purpose: Verilog module containing a synthesizable CRC function
+//   * polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
+//   * data width: 64
+//                                                                     
+// Info: tools@easics.be
+//       http://www.easics.com                                  
+///////////////////////////////////////////////////////////////////////
+ 
+ 
+//module CRC32_D64;
+ 
+  // polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
+  // data width: 64
+  // convention: the first serial data bit is D[63]
+  function [31:0] nextCRC32_D64;
+ 
+    input [63:0] Data;
+    input [31:0] CRC;
+ 
+    reg [63:0] D;
+    reg [31:0] C;
+    reg [31:0] NewCRC;
+ 
+  begin
+ 
+    D = Data;
+    C = CRC;
+ 
+    NewCRC[0] = D[63] ^ D[61] ^ D[60] ^ D[58] ^ D[55] ^ D[54] ^ D[53] ^ 
+                D[50] ^ D[48] ^ D[47] ^ D[45] ^ D[44] ^ D[37] ^ D[34] ^ 
+                D[32] ^ D[31] ^ D[30] ^ D[29] ^ D[28] ^ D[26] ^ D[25] ^ 
+                D[24] ^ D[16] ^ D[12] ^ D[10] ^ D[9] ^ D[6] ^ D[0] ^ 
+                C[0] ^ C[2] ^ C[5] ^ C[12] ^ C[13] ^ C[15] ^ C[16] ^ 
+                C[18] ^ C[21] ^ C[22] ^ C[23] ^ C[26] ^ C[28] ^ C[29] ^ 
+                C[31];
+    NewCRC[1] = D[63] ^ D[62] ^ D[60] ^ D[59] ^ D[58] ^ D[56] ^ D[53] ^ 
+                D[51] ^ D[50] ^ D[49] ^ D[47] ^ D[46] ^ D[44] ^ D[38] ^ 
+                D[37] ^ D[35] ^ D[34] ^ D[33] ^ D[28] ^ D[27] ^ D[24] ^ 
+                D[17] ^ D[16] ^ D[13] ^ D[12] ^ D[11] ^ D[9] ^ D[7] ^ 
+                D[6] ^ D[1] ^ D[0] ^ C[1] ^ C[2] ^ C[3] ^ C[5] ^ C[6] ^ 
+                C[12] ^ C[14] ^ C[15] ^ C[17] ^ C[18] ^ C[19] ^ C[21] ^ 
+                C[24] ^ C[26] ^ C[27] ^ C[28] ^ C[30] ^ C[31];
+    NewCRC[2] = D[59] ^ D[58] ^ D[57] ^ D[55] ^ D[53] ^ D[52] ^ D[51] ^ 
+                D[44] ^ D[39] ^ D[38] ^ D[37] ^ D[36] ^ D[35] ^ D[32] ^ 
+                D[31] ^ D[30] ^ D[26] ^ D[24] ^ D[18] ^ D[17] ^ D[16] ^ 
+                D[14] ^ D[13] ^ D[9] ^ D[8] ^ D[7] ^ D[6] ^ D[2] ^ 
+                D[1] ^ D[0] ^ C[0] ^ C[3] ^ C[4] ^ C[5] ^ C[6] ^ C[7] ^ 
+                C[12] ^ C[19] ^ C[20] ^ C[21] ^ C[23] ^ C[25] ^ C[26] ^ 
+                C[27];
+    NewCRC[3] = D[60] ^ D[59] ^ D[58] ^ D[56] ^ D[54] ^ D[53] ^ D[52] ^ 
+                D[45] ^ D[40] ^ D[39] ^ D[38] ^ D[37] ^ D[36] ^ D[33] ^ 
+                D[32] ^ D[31] ^ D[27] ^ D[25] ^ D[19] ^ D[18] ^ D[17] ^ 
+                D[15] ^ D[14] ^ D[10] ^ D[9] ^ D[8] ^ D[7] ^ D[3] ^ 
+                D[2] ^ D[1] ^ C[0] ^ C[1] ^ C[4] ^ C[5] ^ C[6] ^ C[7] ^ 
+                C[8] ^ C[13] ^ C[20] ^ C[21] ^ C[22] ^ C[24] ^ C[26] ^ 
+                C[27] ^ C[28];
+    NewCRC[4] = D[63] ^ D[59] ^ D[58] ^ D[57] ^ D[50] ^ D[48] ^ D[47] ^ 
+                D[46] ^ D[45] ^ D[44] ^ D[41] ^ D[40] ^ D[39] ^ D[38] ^ 
+                D[33] ^ D[31] ^ D[30] ^ D[29] ^ D[25] ^ D[24] ^ D[20] ^ 
+                D[19] ^ D[18] ^ D[15] ^ D[12] ^ D[11] ^ D[8] ^ D[6] ^ 
+                D[4] ^ D[3] ^ D[2] ^ D[0] ^ C[1] ^ C[6] ^ C[7] ^ C[8] ^ 
+                C[9] ^ C[12] ^ C[13] ^ C[14] ^ C[15] ^ C[16] ^ C[18] ^ 
+                C[25] ^ C[26] ^ C[27] ^ C[31];
+    NewCRC[5] = D[63] ^ D[61] ^ D[59] ^ D[55] ^ D[54] ^ D[53] ^ D[51] ^ 
+                D[50] ^ D[49] ^ D[46] ^ D[44] ^ D[42] ^ D[41] ^ D[40] ^ 
+                D[39] ^ D[37] ^ D[29] ^ D[28] ^ D[24] ^ D[21] ^ D[20] ^ 
+                D[19] ^ D[13] ^ D[10] ^ D[7] ^ D[6] ^ D[5] ^ D[4] ^ 
+                D[3] ^ D[1] ^ D[0] ^ C[5] ^ C[7] ^ C[8] ^ C[9] ^ C[10] ^ 
+                C[12] ^ C[14] ^ C[17] ^ C[18] ^ C[19] ^ C[21] ^ C[22] ^ 
+                C[23] ^ C[27] ^ C[29] ^ C[31];
+    NewCRC[6] = D[62] ^ D[60] ^ D[56] ^ D[55] ^ D[54] ^ D[52] ^ D[51] ^ 
+                D[50] ^ D[47] ^ D[45] ^ D[43] ^ D[42] ^ D[41] ^ D[40] ^ 
+                D[38] ^ D[30] ^ D[29] ^ D[25] ^ D[22] ^ D[21] ^ D[20] ^ 
+                D[14] ^ D[11] ^ D[8] ^ D[7] ^ D[6] ^ D[5] ^ D[4] ^ 
+                D[2] ^ D[1] ^ C[6] ^ C[8] ^ C[9] ^ C[10] ^ C[11] ^ 
+                C[13] ^ C[15] ^ C[18] ^ C[19] ^ C[20] ^ C[22] ^ C[23] ^ 
+                C[24] ^ C[28] ^ C[30];
+    NewCRC[7] = D[60] ^ D[58] ^ D[57] ^ D[56] ^ D[54] ^ D[52] ^ D[51] ^ 
+                D[50] ^ D[47] ^ D[46] ^ D[45] ^ D[43] ^ D[42] ^ D[41] ^ 
+                D[39] ^ D[37] ^ D[34] ^ D[32] ^ D[29] ^ D[28] ^ D[25] ^ 
+                D[24] ^ D[23] ^ D[22] ^ D[21] ^ D[16] ^ D[15] ^ D[10] ^ 
+                D[8] ^ D[7] ^ D[5] ^ D[3] ^ D[2] ^ D[0] ^ C[0] ^ C[2] ^ 
+                C[5] ^ C[7] ^ C[9] ^ C[10] ^ C[11] ^ C[13] ^ C[14] ^ 
+                C[15] ^ C[18] ^ C[19] ^ C[20] ^ C[22] ^ C[24] ^ C[25] ^ 
+                C[26] ^ C[28];
+    NewCRC[8] = D[63] ^ D[60] ^ D[59] ^ D[57] ^ D[54] ^ D[52] ^ D[51] ^ 
+                D[50] ^ D[46] ^ D[45] ^ D[43] ^ D[42] ^ D[40] ^ D[38] ^ 
+                D[37] ^ D[35] ^ D[34] ^ D[33] ^ D[32] ^ D[31] ^ D[28] ^ 
+                D[23] ^ D[22] ^ D[17] ^ D[12] ^ D[11] ^ D[10] ^ D[8] ^ 
+                D[4] ^ D[3] ^ D[1] ^ D[0] ^ C[0] ^ C[1] ^ C[2] ^ C[3] ^ 
+                C[5] ^ C[6] ^ C[8] ^ C[10] ^ C[11] ^ C[13] ^ C[14] ^ 
+                C[18] ^ C[19] ^ C[20] ^ C[22] ^ C[25] ^ C[27] ^ C[28] ^ 
+                C[31];
+    NewCRC[9] = D[61] ^ D[60] ^ D[58] ^ D[55] ^ D[53] ^ D[52] ^ D[51] ^ 
+                D[47] ^ D[46] ^ D[44] ^ D[43] ^ D[41] ^ D[39] ^ D[38] ^ 
+                D[36] ^ D[35] ^ D[34] ^ D[33] ^ D[32] ^ D[29] ^ D[24] ^ 
+                D[23] ^ D[18] ^ D[13] ^ D[12] ^ D[11] ^ D[9] ^ D[5] ^ 
+                D[4] ^ D[2] ^ D[1] ^ C[0] ^ C[1] ^ C[2] ^ C[3] ^ C[4] ^ 
+                C[6] ^ C[7] ^ C[9] ^ C[11] ^ C[12] ^ C[14] ^ C[15] ^ 
+                C[19] ^ C[20] ^ C[21] ^ C[23] ^ C[26] ^ C[28] ^ C[29];
+    NewCRC[10] = D[63] ^ D[62] ^ D[60] ^ D[59] ^ D[58] ^ D[56] ^ D[55] ^ 
+                 D[52] ^ D[50] ^ D[42] ^ D[40] ^ D[39] ^ D[36] ^ D[35] ^ 
+                 D[33] ^ D[32] ^ D[31] ^ D[29] ^ D[28] ^ D[26] ^ D[19] ^ 
+                 D[16] ^ D[14] ^ D[13] ^ D[9] ^ D[5] ^ D[3] ^ D[2] ^ 
+                 D[0] ^ C[0] ^ C[1] ^ C[3] ^ C[4] ^ C[7] ^ C[8] ^ C[10] ^ 
+                 C[18] ^ C[20] ^ C[23] ^ C[24] ^ C[26] ^ C[27] ^ C[28] ^ 
+                 C[30] ^ C[31];
+    NewCRC[11] = D[59] ^ D[58] ^ D[57] ^ D[56] ^ D[55] ^ D[54] ^ D[51] ^ 
+                 D[50] ^ D[48] ^ D[47] ^ D[45] ^ D[44] ^ D[43] ^ D[41] ^ 
+                 D[40] ^ D[36] ^ D[33] ^ D[31] ^ D[28] ^ D[27] ^ D[26] ^ 
+                 D[25] ^ D[24] ^ D[20] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ 
+                 D[12] ^ D[9] ^ D[4] ^ D[3] ^ D[1] ^ D[0] ^ C[1] ^ C[4] ^ 
+                 C[8] ^ C[9] ^ C[11] ^ C[12] ^ C[13] ^ C[15] ^ C[16] ^ 
+                 C[18] ^ C[19] ^ C[22] ^ C[23] ^ C[24] ^ C[25] ^ C[26] ^ 
+                 C[27];
+    NewCRC[12] = D[63] ^ D[61] ^ D[59] ^ D[57] ^ D[56] ^ D[54] ^ D[53] ^ 
+                 D[52] ^ D[51] ^ D[50] ^ D[49] ^ D[47] ^ D[46] ^ D[42] ^ 
+                 D[41] ^ D[31] ^ D[30] ^ D[27] ^ D[24] ^ D[21] ^ D[18] ^ 
+                 D[17] ^ D[15] ^ D[13] ^ D[12] ^ D[9] ^ D[6] ^ D[5] ^ 
+                 D[4] ^ D[2] ^ D[1] ^ D[0] ^ C[9] ^ C[10] ^ C[14] ^ 
+                 C[15] ^ C[17] ^ C[18] ^ C[19] ^ C[20] ^ C[21] ^ C[22] ^ 
+                 C[24] ^ C[25] ^ C[27] ^ C[29] ^ C[31];
+    NewCRC[13] = D[62] ^ D[60] ^ D[58] ^ D[57] ^ D[55] ^ D[54] ^ D[53] ^ 
+                 D[52] ^ D[51] ^ D[50] ^ D[48] ^ D[47] ^ D[43] ^ D[42] ^ 
+                 D[32] ^ D[31] ^ D[28] ^ D[25] ^ D[22] ^ D[19] ^ D[18] ^ 
+                 D[16] ^ D[14] ^ D[13] ^ D[10] ^ D[7] ^ D[6] ^ D[5] ^ 
+                 D[3] ^ D[2] ^ D[1] ^ C[0] ^ C[10] ^ C[11] ^ C[15] ^ 
+                 C[16] ^ C[18] ^ C[19] ^ C[20] ^ C[21] ^ C[22] ^ C[23] ^ 
+                 C[25] ^ C[26] ^ C[28] ^ C[30];
+    NewCRC[14] = D[63] ^ D[61] ^ D[59] ^ D[58] ^ D[56] ^ D[55] ^ D[54] ^ 
+                 D[53] ^ D[52] ^ D[51] ^ D[49] ^ D[48] ^ D[44] ^ D[43] ^ 
+                 D[33] ^ D[32] ^ D[29] ^ D[26] ^ D[23] ^ D[20] ^ D[19] ^ 
+                 D[17] ^ D[15] ^ D[14] ^ D[11] ^ D[8] ^ D[7] ^ D[6] ^ 
+                 D[4] ^ D[3] ^ D[2] ^ C[0] ^ C[1] ^ C[11] ^ C[12] ^ 
+                 C[16] ^ C[17] ^ C[19] ^ C[20] ^ C[21] ^ C[22] ^ C[23] ^ 
+                 C[24] ^ C[26] ^ C[27] ^ C[29] ^ C[31];
+    NewCRC[15] = D[62] ^ D[60] ^ D[59] ^ D[57] ^ D[56] ^ D[55] ^ D[54] ^ 
+                 D[53] ^ D[52] ^ D[50] ^ D[49] ^ D[45] ^ D[44] ^ D[34] ^ 
+                 D[33] ^ D[30] ^ D[27] ^ D[24] ^ D[21] ^ D[20] ^ D[18] ^ 
+                 D[16] ^ D[15] ^ D[12] ^ D[9] ^ D[8] ^ D[7] ^ D[5] ^ 
+                 D[4] ^ D[3] ^ C[1] ^ C[2] ^ C[12] ^ C[13] ^ C[17] ^ 
+                 C[18] ^ C[20] ^ C[21] ^ C[22] ^ C[23] ^ C[24] ^ C[25] ^ 
+                 C[27] ^ C[28] ^ C[30];
+    NewCRC[16] = D[57] ^ D[56] ^ D[51] ^ D[48] ^ D[47] ^ D[46] ^ D[44] ^ 
+                 D[37] ^ D[35] ^ D[32] ^ D[30] ^ D[29] ^ D[26] ^ D[24] ^ 
+                 D[22] ^ D[21] ^ D[19] ^ D[17] ^ D[13] ^ D[12] ^ D[8] ^ 
+                 D[5] ^ D[4] ^ D[0] ^ C[0] ^ C[3] ^ C[5] ^ C[12] ^ C[14] ^ 
+                 C[15] ^ C[16] ^ C[19] ^ C[24] ^ C[25];
+    NewCRC[17] = D[58] ^ D[57] ^ D[52] ^ D[49] ^ D[48] ^ D[47] ^ D[45] ^ 
+                 D[38] ^ D[36] ^ D[33] ^ D[31] ^ D[30] ^ D[27] ^ D[25] ^ 
+                 D[23] ^ D[22] ^ D[20] ^ D[18] ^ D[14] ^ D[13] ^ D[9] ^ 
+                 D[6] ^ D[5] ^ D[1] ^ C[1] ^ C[4] ^ C[6] ^ C[13] ^ C[15] ^ 
+                 C[16] ^ C[17] ^ C[20] ^ C[25] ^ C[26];
+    NewCRC[18] = D[59] ^ D[58] ^ D[53] ^ D[50] ^ D[49] ^ D[48] ^ D[46] ^ 
+                 D[39] ^ D[37] ^ D[34] ^ D[32] ^ D[31] ^ D[28] ^ D[26] ^ 
+                 D[24] ^ D[23] ^ D[21] ^ D[19] ^ D[15] ^ D[14] ^ D[10] ^ 
+                 D[7] ^ D[6] ^ D[2] ^ C[0] ^ C[2] ^ C[5] ^ C[7] ^ C[14] ^ 
+                 C[16] ^ C[17] ^ C[18] ^ C[21] ^ C[26] ^ C[27];
+    NewCRC[19] = D[60] ^ D[59] ^ D[54] ^ D[51] ^ D[50] ^ D[49] ^ D[47] ^ 
+                 D[40] ^ D[38] ^ D[35] ^ D[33] ^ D[32] ^ D[29] ^ D[27] ^ 
+                 D[25] ^ D[24] ^ D[22] ^ D[20] ^ D[16] ^ D[15] ^ D[11] ^ 
+                 D[8] ^ D[7] ^ D[3] ^ C[0] ^ C[1] ^ C[3] ^ C[6] ^ C[8] ^ 
+                 C[15] ^ C[17] ^ C[18] ^ C[19] ^ C[22] ^ C[27] ^ C[28];
+    NewCRC[20] = D[61] ^ D[60] ^ D[55] ^ D[52] ^ D[51] ^ D[50] ^ D[48] ^ 
+                 D[41] ^ D[39] ^ D[36] ^ D[34] ^ D[33] ^ D[30] ^ D[28] ^ 
+                 D[26] ^ D[25] ^ D[23] ^ D[21] ^ D[17] ^ D[16] ^ D[12] ^ 
+                 D[9] ^ D[8] ^ D[4] ^ C[1] ^ C[2] ^ C[4] ^ C[7] ^ C[9] ^ 
+                 C[16] ^ C[18] ^ C[19] ^ C[20] ^ C[23] ^ C[28] ^ C[29];
+    NewCRC[21] = D[62] ^ D[61] ^ D[56] ^ D[53] ^ D[52] ^ D[51] ^ D[49] ^ 
+                 D[42] ^ D[40] ^ D[37] ^ D[35] ^ D[34] ^ D[31] ^ D[29] ^ 
+                 D[27] ^ D[26] ^ D[24] ^ D[22] ^ D[18] ^ D[17] ^ D[13] ^ 
+                 D[10] ^ D[9] ^ D[5] ^ C[2] ^ C[3] ^ C[5] ^ C[8] ^ C[10] ^ 
+                 C[17] ^ C[19] ^ C[20] ^ C[21] ^ C[24] ^ C[29] ^ C[30];
+    NewCRC[22] = D[62] ^ D[61] ^ D[60] ^ D[58] ^ D[57] ^ D[55] ^ D[52] ^ 
+                 D[48] ^ D[47] ^ D[45] ^ D[44] ^ D[43] ^ D[41] ^ D[38] ^ 
+                 D[37] ^ D[36] ^ D[35] ^ D[34] ^ D[31] ^ D[29] ^ D[27] ^ 
+                 D[26] ^ D[24] ^ D[23] ^ D[19] ^ D[18] ^ D[16] ^ D[14] ^ 
+                 D[12] ^ D[11] ^ D[9] ^ D[0] ^ C[2] ^ C[3] ^ C[4] ^ 
+                 C[5] ^ C[6] ^ C[9] ^ C[11] ^ C[12] ^ C[13] ^ C[15] ^ 
+                 C[16] ^ C[20] ^ C[23] ^ C[25] ^ C[26] ^ C[28] ^ C[29] ^ 
+                 C[30];
+    NewCRC[23] = D[62] ^ D[60] ^ D[59] ^ D[56] ^ D[55] ^ D[54] ^ D[50] ^ 
+                 D[49] ^ D[47] ^ D[46] ^ D[42] ^ D[39] ^ D[38] ^ D[36] ^ 
+                 D[35] ^ D[34] ^ D[31] ^ D[29] ^ D[27] ^ D[26] ^ D[20] ^ 
+                 D[19] ^ D[17] ^ D[16] ^ D[15] ^ D[13] ^ D[9] ^ D[6] ^ 
+                 D[1] ^ D[0] ^ C[2] ^ C[3] ^ C[4] ^ C[6] ^ C[7] ^ C[10] ^ 
+                 C[14] ^ C[15] ^ C[17] ^ C[18] ^ C[22] ^ C[23] ^ C[24] ^ 
+                 C[27] ^ C[28] ^ C[30];
+    NewCRC[24] = D[63] ^ D[61] ^ D[60] ^ D[57] ^ D[56] ^ D[55] ^ D[51] ^ 
+                 D[50] ^ D[48] ^ D[47] ^ D[43] ^ D[40] ^ D[39] ^ D[37] ^ 
+                 D[36] ^ D[35] ^ D[32] ^ D[30] ^ D[28] ^ D[27] ^ D[21] ^ 
+                 D[20] ^ D[18] ^ D[17] ^ D[16] ^ D[14] ^ D[10] ^ D[7] ^ 
+                 D[2] ^ D[1] ^ C[0] ^ C[3] ^ C[4] ^ C[5] ^ C[7] ^ C[8] ^ 
+                 C[11] ^ C[15] ^ C[16] ^ C[18] ^ C[19] ^ C[23] ^ C[24] ^ 
+                 C[25] ^ C[28] ^ C[29] ^ C[31];
+    NewCRC[25] = D[62] ^ D[61] ^ D[58] ^ D[57] ^ D[56] ^ D[52] ^ D[51] ^ 
+                 D[49] ^ D[48] ^ D[44] ^ D[41] ^ D[40] ^ D[38] ^ D[37] ^ 
+                 D[36] ^ D[33] ^ D[31] ^ D[29] ^ D[28] ^ D[22] ^ D[21] ^ 
+                 D[19] ^ D[18] ^ D[17] ^ D[15] ^ D[11] ^ D[8] ^ D[3] ^ 
+                 D[2] ^ C[1] ^ C[4] ^ C[5] ^ C[6] ^ C[8] ^ C[9] ^ C[12] ^ 
+                 C[16] ^ C[17] ^ C[19] ^ C[20] ^ C[24] ^ C[25] ^ C[26] ^ 
+                 C[29] ^ C[30];
+    NewCRC[26] = D[62] ^ D[61] ^ D[60] ^ D[59] ^ D[57] ^ D[55] ^ D[54] ^ 
+                 D[52] ^ D[49] ^ D[48] ^ D[47] ^ D[44] ^ D[42] ^ D[41] ^ 
+                 D[39] ^ D[38] ^ D[31] ^ D[28] ^ D[26] ^ D[25] ^ D[24] ^ 
+                 D[23] ^ D[22] ^ D[20] ^ D[19] ^ D[18] ^ D[10] ^ D[6] ^ 
+                 D[4] ^ D[3] ^ D[0] ^ C[6] ^ C[7] ^ C[9] ^ C[10] ^ C[12] ^ 
+                 C[15] ^ C[16] ^ C[17] ^ C[20] ^ C[22] ^ C[23] ^ C[25] ^ 
+                 C[27] ^ C[28] ^ C[29] ^ C[30];
+    NewCRC[27] = D[63] ^ D[62] ^ D[61] ^ D[60] ^ D[58] ^ D[56] ^ D[55] ^ 
+                 D[53] ^ D[50] ^ D[49] ^ D[48] ^ D[45] ^ D[43] ^ D[42] ^ 
+                 D[40] ^ D[39] ^ D[32] ^ D[29] ^ D[27] ^ D[26] ^ D[25] ^ 
+                 D[24] ^ D[23] ^ D[21] ^ D[20] ^ D[19] ^ D[11] ^ D[7] ^ 
+                 D[5] ^ D[4] ^ D[1] ^ C[0] ^ C[7] ^ C[8] ^ C[10] ^ C[11] ^ 
+                 C[13] ^ C[16] ^ C[17] ^ C[18] ^ C[21] ^ C[23] ^ C[24] ^ 
+                 C[26] ^ C[28] ^ C[29] ^ C[30] ^ C[31];
+    NewCRC[28] = D[63] ^ D[62] ^ D[61] ^ D[59] ^ D[57] ^ D[56] ^ D[54] ^ 
+                 D[51] ^ D[50] ^ D[49] ^ D[46] ^ D[44] ^ D[43] ^ D[41] ^ 
+                 D[40] ^ D[33] ^ D[30] ^ D[28] ^ D[27] ^ D[26] ^ D[25] ^ 
+                 D[24] ^ D[22] ^ D[21] ^ D[20] ^ D[12] ^ D[8] ^ D[6] ^ 
+                 D[5] ^ D[2] ^ C[1] ^ C[8] ^ C[9] ^ C[11] ^ C[12] ^ 
+                 C[14] ^ C[17] ^ C[18] ^ C[19] ^ C[22] ^ C[24] ^ C[25] ^ 
+                 C[27] ^ C[29] ^ C[30] ^ C[31];
+    NewCRC[29] = D[63] ^ D[62] ^ D[60] ^ D[58] ^ D[57] ^ D[55] ^ D[52] ^ 
+                 D[51] ^ D[50] ^ D[47] ^ D[45] ^ D[44] ^ D[42] ^ D[41] ^ 
+                 D[34] ^ D[31] ^ D[29] ^ D[28] ^ D[27] ^ D[26] ^ D[25] ^ 
+                 D[23] ^ D[22] ^ D[21] ^ D[13] ^ D[9] ^ D[7] ^ D[6] ^ 
+                 D[3] ^ C[2] ^ C[9] ^ C[10] ^ C[12] ^ C[13] ^ C[15] ^ 
+                 C[18] ^ C[19] ^ C[20] ^ C[23] ^ C[25] ^ C[26] ^ C[28] ^ 
+                 C[30] ^ C[31];
+    NewCRC[30] = D[63] ^ D[61] ^ D[59] ^ D[58] ^ D[56] ^ D[53] ^ D[52] ^ 
+                 D[51] ^ D[48] ^ D[46] ^ D[45] ^ D[43] ^ D[42] ^ D[35] ^ 
+                 D[32] ^ D[30] ^ D[29] ^ D[28] ^ D[27] ^ D[26] ^ D[24] ^ 
+                 D[23] ^ D[22] ^ D[14] ^ D[10] ^ D[8] ^ D[7] ^ D[4] ^ 
+                 C[0] ^ C[3] ^ C[10] ^ C[11] ^ C[13] ^ C[14] ^ C[16] ^ 
+                 C[19] ^ C[20] ^ C[21] ^ C[24] ^ C[26] ^ C[27] ^ C[29] ^ 
+                 C[31];
+    NewCRC[31] = D[62] ^ D[60] ^ D[59] ^ D[57] ^ D[54] ^ D[53] ^ D[52] ^ 
+                 D[49] ^ D[47] ^ D[46] ^ D[44] ^ D[43] ^ D[36] ^ D[33] ^ 
+                 D[31] ^ D[30] ^ D[29] ^ D[28] ^ D[27] ^ D[25] ^ D[24] ^ 
+                 D[23] ^ D[15] ^ D[11] ^ D[9] ^ D[8] ^ D[5] ^ C[1] ^ 
+                 C[4] ^ C[11] ^ C[12] ^ C[14] ^ C[15] ^ C[17] ^ C[20] ^ 
+                 C[21] ^ C[22] ^ C[25] ^ C[27] ^ C[28] ^ C[30];
+ 
+    nextCRC32_D64 = NewCRC;
+ 
+  end
+ 
+  endfunction
+ 
+//endmodule
+ 
diff --git a/fpga/usrp3/lib/xge/rtl/verilog/CRC32_D8.v b/fpga/usrp3/lib/xge/rtl/verilog/CRC32_D8.v
new file mode 100644
index 000000000..814648684
--- /dev/null
+++ b/fpga/usrp3/lib/xge/rtl/verilog/CRC32_D8.v
@@ -0,0 +1,101 @@
+///////////////////////////////////////////////////////////////////////
+// File:  CRC32_D8.v                             
+// Date:  Fri Feb  8 19:26:59 2008                                                      
+//                                                                     
+// Copyright (C) 1999-2003 Easics NV.                 
+// This source file may be used and distributed without restriction    
+// provided that this copyright statement is not removed from the file 
+// and that any derivative work contains the original copyright notice
+// and the associated disclaimer.
+//
+// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
+// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+//
+// Purpose: Verilog module containing a synthesizable CRC function
+//   * polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
+//   * data width: 8
+//                                                                     
+// Info: tools@easics.be
+//       http://www.easics.com                                  
+///////////////////////////////////////////////////////////////////////
+ 
+ 
+//module CRC32_D8;
+ 
+  // polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
+  // data width: 8
+  // convention: the first serial data bit is D[7]
+  function [31:0] nextCRC32_D8;
+ 
+    input [7:0] Data;
+    input [31:0] CRC;
+ 
+    reg [7:0] D;
+    reg [31:0] C;
+    reg [31:0] NewCRC;
+ 
+  begin
+ 
+    D = Data;
+    C = CRC;
+ 
+    NewCRC[0] = D[6] ^ D[0] ^ C[24] ^ C[30];
+    NewCRC[1] = D[7] ^ D[6] ^ D[1] ^ D[0] ^ C[24] ^ C[25] ^ C[30] ^ 
+                C[31];
+    NewCRC[2] = D[7] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^ C[24] ^ C[25] ^ 
+                C[26] ^ C[30] ^ C[31];
+    NewCRC[3] = D[7] ^ D[3] ^ D[2] ^ D[1] ^ C[25] ^ C[26] ^ C[27] ^ 
+                C[31];
+    NewCRC[4] = D[6] ^ D[4] ^ D[3] ^ D[2] ^ D[0] ^ C[24] ^ C[26] ^ 
+                C[27] ^ C[28] ^ C[30];
+    NewCRC[5] = D[7] ^ D[6] ^ D[5] ^ D[4] ^ D[3] ^ D[1] ^ D[0] ^ C[24] ^ 
+                C[25] ^ C[27] ^ C[28] ^ C[29] ^ C[30] ^ C[31];
+    NewCRC[6] = D[7] ^ D[6] ^ D[5] ^ D[4] ^ D[2] ^ D[1] ^ C[25] ^ C[26] ^ 
+                C[28] ^ C[29] ^ C[30] ^ C[31];
+    NewCRC[7] = D[7] ^ D[5] ^ D[3] ^ D[2] ^ D[0] ^ C[24] ^ C[26] ^ 
+                C[27] ^ C[29] ^ C[31];
+    NewCRC[8] = D[4] ^ D[3] ^ D[1] ^ D[0] ^ C[0] ^ C[24] ^ C[25] ^ 
+                C[27] ^ C[28];
+    NewCRC[9] = D[5] ^ D[4] ^ D[2] ^ D[1] ^ C[1] ^ C[25] ^ C[26] ^ 
+                C[28] ^ C[29];
+    NewCRC[10] = D[5] ^ D[3] ^ D[2] ^ D[0] ^ C[2] ^ C[24] ^ C[26] ^ 
+                 C[27] ^ C[29];
+    NewCRC[11] = D[4] ^ D[3] ^ D[1] ^ D[0] ^ C[3] ^ C[24] ^ C[25] ^ 
+                 C[27] ^ C[28];
+    NewCRC[12] = D[6] ^ D[5] ^ D[4] ^ D[2] ^ D[1] ^ D[0] ^ C[4] ^ C[24] ^ 
+                 C[25] ^ C[26] ^ C[28] ^ C[29] ^ C[30];
+    NewCRC[13] = D[7] ^ D[6] ^ D[5] ^ D[3] ^ D[2] ^ D[1] ^ C[5] ^ C[25] ^ 
+                 C[26] ^ C[27] ^ C[29] ^ C[30] ^ C[31];
+    NewCRC[14] = D[7] ^ D[6] ^ D[4] ^ D[3] ^ D[2] ^ C[6] ^ C[26] ^ C[27] ^ 
+                 C[28] ^ C[30] ^ C[31];
+    NewCRC[15] = D[7] ^ D[5] ^ D[4] ^ D[3] ^ C[7] ^ C[27] ^ C[28] ^ 
+                 C[29] ^ C[31];
+    NewCRC[16] = D[5] ^ D[4] ^ D[0] ^ C[8] ^ C[24] ^ C[28] ^ C[29];
+    NewCRC[17] = D[6] ^ D[5] ^ D[1] ^ C[9] ^ C[25] ^ C[29] ^ C[30];
+    NewCRC[18] = D[7] ^ D[6] ^ D[2] ^ C[10] ^ C[26] ^ C[30] ^ C[31];
+    NewCRC[19] = D[7] ^ D[3] ^ C[11] ^ C[27] ^ C[31];
+    NewCRC[20] = D[4] ^ C[12] ^ C[28];
+    NewCRC[21] = D[5] ^ C[13] ^ C[29];
+    NewCRC[22] = D[0] ^ C[14] ^ C[24];
+    NewCRC[23] = D[6] ^ D[1] ^ D[0] ^ C[15] ^ C[24] ^ C[25] ^ C[30];
+    NewCRC[24] = D[7] ^ D[2] ^ D[1] ^ C[16] ^ C[25] ^ C[26] ^ C[31];
+    NewCRC[25] = D[3] ^ D[2] ^ C[17] ^ C[26] ^ C[27];
+    NewCRC[26] = D[6] ^ D[4] ^ D[3] ^ D[0] ^ C[18] ^ C[24] ^ C[27] ^ 
+                 C[28] ^ C[30];
+    NewCRC[27] = D[7] ^ D[5] ^ D[4] ^ D[1] ^ C[19] ^ C[25] ^ C[28] ^ 
+                 C[29] ^ C[31];
+    NewCRC[28] = D[6] ^ D[5] ^ D[2] ^ C[20] ^ C[26] ^ C[29] ^ C[30];
+    NewCRC[29] = D[7] ^ D[6] ^ D[3] ^ C[21] ^ C[27] ^ C[30] ^ C[31];
+    NewCRC[30] = D[7] ^ D[4] ^ C[22] ^ C[28] ^ C[31];
+    NewCRC[31] = D[5] ^ C[23] ^ C[29];
+ 
+    nextCRC32_D8 = NewCRC;
+ 
+  end
+ 
+  endfunction
+ 
+//endmodule
+ 
+ 
\ No newline at end of file
diff --git a/fpga/usrp3/lib/xge/rtl/verilog/defines.v b/fpga/usrp3/lib/xge/rtl/verilog/defines.v
new file mode 100644
index 000000000..c78203353
--- /dev/null
+++ b/fpga/usrp3/lib/xge/rtl/verilog/defines.v
@@ -0,0 +1,121 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  File name "defines.v"                                       ////
+////                                                              ////
+////  This file is part of the "10GE MAC" project                 ////
+////  http://www.opencores.org/cores/xge_mac/                     ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - A. Tanguay (antanguay@opencores.org)                  ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2008 AUTHORS. All rights reserved.             ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+// If WB clock is 62.5MHz and max MDC spec is 2.5MHz, then divide by 25
+//`define MDC_HALF_PERIOD 13 // Closest int to 12.5
+`define MDC_HALF_PERIOD 100
+
+// CPU Registers
+
+`define CPUREG_CONFIG0      8'h00
+`define CPUREG_INT_PENDING  8'h04
+`define CPUREG_INT_STATUS   8'h08
+`define CPUREG_INT_MASK     8'h0c
+`define CPUREG_MDIO_DATA    8'h10
+`define CPUREG_MDIO_ADDR    8'h14
+`define CPUREG_MDIO_OP      8'h18
+`define CPUREG_MDIO_CONTROL 8'h1c
+`define CPUREG_MDIO_STATUS  8'h1c
+`define CPUREG_GPIO         8'h20
+
+// Ethernet codes
+
+`define IDLE       8'h07
+`define PREAMBLE   8'h55
+`define SEQUENCE   8'h9c
+`define SFD        8'hd5
+`define START      8'hfb
+`define TERMINATE  8'hfd
+`define ERROR      8'hfe
+
+
+
+`define LINK_FAULT_OK      2'd0
+`define LINK_FAULT_LOCAL   2'd1
+`define LINK_FAULT_REMOTE  2'd2
+
+`define FAULT_SEQ_LOCAL  1'b0
+`define FAULT_SEQ_REMOTE 1'b1
+
+`define LOCAL_FAULT   8'd1
+`define REMOTE_FAULT  8'd2
+
+`define PAUSE_FRAME   48'h010000c28001
+
+`define LANE0        7:0
+`define LANE1       15:8
+`define LANE2      23:16
+`define LANE3      31:24
+`define LANE4      39:32
+`define LANE5      47:40
+`define LANE6      55:48
+`define LANE7      63:56
+
+
+`define TXSTATUS_NONE       8'h0
+`define TXSTATUS_EOP        3'd6
+`define TXSTATUS_SOP        3'd7
+
+`define RXSTATUS_NONE       8'h0
+`define RXSTATUS_ERR        3'd5
+`define RXSTATUS_EOP        3'd6
+`define RXSTATUS_SOP        3'd7
+
+
+//
+// FIFO Size: 8 * (2^AWIDTH) will be the size in bytes
+//            7 --> 128 entries, 1024 bytes for data fifo
+//
+`define TX_DATA_FIFO_AWIDTH 7
+`define RX_DATA_FIFO_AWIDTH 7
+
+//
+// FIFO Size: Holding FIFOs are 16 deep
+//
+`define TX_HOLD_FIFO_AWIDTH 4
+`define RX_HOLD_FIFO_AWIDTH 4
+
+
+// Memory types
+`define MEM_AUTO_SMALL 1
+`define MEM_AUTO_MEDIUM 2
+`define MEM_AUTO_XILINX 3
+
+
+// Changed system packet interface to big endian (12/12/2009)
+// Comment out to use legacy mode (i.e. the correct mode)
+//`define BIGENDIAN
diff --git a/fpga/usrp3/lib/xge/rtl/verilog/fault_sm.v b/fpga/usrp3/lib/xge/rtl/verilog/fault_sm.v
new file mode 100644
index 000000000..525459ca3
--- /dev/null
+++ b/fpga/usrp3/lib/xge/rtl/verilog/fault_sm.v
@@ -0,0 +1,287 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  File name "fault_sm.v"                                      ////
+////                                                              ////
+////  This file is part of the "10GE MAC" project                 ////
+////  http://www.opencores.org/cores/xge_mac/                     ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - A. Tanguay (antanguay@opencores.org)                  ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2008 AUTHORS. All rights reserved.             ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+ 
+ 
+`include "defines.v"
+ 
+module fault_sm(/*AUTOARG*/
+  // Outputs
+  status_local_fault_crx, status_remote_fault_crx,
+  // Inputs
+  clk_xgmii_rx, reset_xgmii_rx_n, local_fault_msg_det,
+  remote_fault_msg_det
+  );
+ 
+input         clk_xgmii_rx;
+input         reset_xgmii_rx_n;
+ 
+input  [1:0]  local_fault_msg_det;
+input  [1:0]  remote_fault_msg_det;
+ 
+output        status_local_fault_crx;
+output        status_remote_fault_crx;
+ 
+/*AUTOREG*/
+// Beginning of automatic regs (for this module's undeclared outputs)
+reg                     status_local_fault_crx;
+reg                     status_remote_fault_crx;
+// End of automatics
+ 
+reg    [1:0]  curr_state;
+ 
+reg    [7:0]  col_cnt;
+reg    [1:0]  fault_sequence;
+reg    [1:0]  last_seq_type;
+reg    [1:0]  link_fault;
+reg    [2:0]  seq_cnt;
+reg    [1:0]  seq_type;
+ 
+reg    [1:0]  seq_add;
+ 
+/*AUTOWIRE*/
+ 
+ 
+parameter [1:0]
+             SM_INIT       = 2'd0,
+             SM_COUNT      = 2'd1,
+             SM_FAULT      = 2'd2,
+             SM_NEW_FAULT  = 2'd3;
+ 
+ 
+always @(/*AS*/local_fault_msg_det or remote_fault_msg_det) begin
+ 
+    //---
+    // Fault indication. Indicate remote or local fault
+ 
+    fault_sequence = local_fault_msg_det | remote_fault_msg_det;
+ 
+ 
+    //---
+    // Sequence type, local, remote, or ok
+ 
+    if (|local_fault_msg_det) begin
+        seq_type = `LINK_FAULT_LOCAL;
+    end
+    else if (|remote_fault_msg_det) begin
+        seq_type = `LINK_FAULT_REMOTE;
+    end
+    else begin
+        seq_type = `LINK_FAULT_OK;
+    end
+ 
+ 
+    //---
+    // Adder for number of faults, if detected in lower 4 lanes and
+    // upper 4 lanes, add 2. That's because we process 64-bit at a time
+    // instead of typically 32-bit xgmii.
+ 
+    if (|remote_fault_msg_det) begin
+        seq_add = remote_fault_msg_det[1] + remote_fault_msg_det[0];
+    end
+    else begin
+        seq_add = local_fault_msg_det[1] + local_fault_msg_det[0];
+    end
+ 
+end
+ 
+always @(posedge clk_xgmii_rx or negedge reset_xgmii_rx_n) begin
+ 
+    if (reset_xgmii_rx_n == 1'b0) begin
+ 
+ 
+        status_local_fault_crx <= 1'b0;
+        status_remote_fault_crx <= 1'b0;
+ 
+    end
+    else begin
+ 
+        //---
+        // Status signal to generate local/remote fault interrupts
+ 
+        status_local_fault_crx <= curr_state == SM_FAULT &&
+                                  link_fault == `LINK_FAULT_LOCAL;
+ 
+        status_remote_fault_crx <= curr_state == SM_FAULT &&
+                                   link_fault == `LINK_FAULT_REMOTE;
+ 
+    end
+ 
+end
+ 
+always @(posedge clk_xgmii_rx or negedge reset_xgmii_rx_n) begin
+ 
+    if (reset_xgmii_rx_n == 1'b0) begin
+ 
+        curr_state <= SM_INIT;
+ 
+        col_cnt <= 8'b0;
+        last_seq_type <= `LINK_FAULT_OK;
+        link_fault <= `LINK_FAULT_OK;
+        seq_cnt <= 3'b0;
+ 
+    end
+    else begin
+ 
+        case (curr_state)
+ 
+          SM_INIT:
+            begin
+ 
+                last_seq_type <= seq_type;
+ 
+                if (|fault_sequence) begin
+ 
+                    // If a fault is detected, capture the type of
+                    // fault and start column counter. We need 4 fault
+                    // messages in 128 columns to accept the fault.
+ 
+                    if (fault_sequence[0]) begin
+                        col_cnt <= 8'd2;
+                    end
+                    else begin
+                        col_cnt <= 8'd1;
+                    end
+                    seq_cnt <= {1'b0, seq_add};
+                    curr_state <= SM_COUNT;
+ 
+                end
+                else begin
+ 
+                    // If no faults, stay in INIT and clear counters
+ 
+                    col_cnt <= 8'b0;
+                    seq_cnt <= 3'b0;
+ 
+                end
+            end
+ 
+          SM_COUNT:
+            begin
+ 
+                col_cnt <= col_cnt + 8'd2;
+                seq_cnt <= seq_cnt + {1'b0, seq_add};
+ 
+                if (!fault_sequence[0] && col_cnt >= 8'd127) begin
+ 
+                    // No new fault in lower lanes and almost
+                    // reached the 128 columns count, abort fault. 
+ 
+                    curr_state <= SM_INIT;
+ 
+                end
+                else if (col_cnt > 8'd127) begin
+ 
+                    // Reached the 128 columns count, abort fault.
+ 
+                    curr_state <= SM_INIT;
+ 
+                end
+                else if (|fault_sequence) begin
+ 
+                    // If fault type has changed, move to NEW_FAULT.
+                    // If not, after detecting 4 fault messages move to
+                    // FAULT state.
+ 
+                    if (seq_type != last_seq_type) begin
+                        curr_state <= SM_NEW_FAULT;
+                    end
+                    else begin
+                        if ((seq_cnt + {1'b0, seq_add}) > 3'd3) begin
+                            col_cnt <= 8'b0;
+                            link_fault <= seq_type;
+                            curr_state <= SM_FAULT;
+                        end
+                    end
+ 
+                end
+            end
+ 
+          SM_FAULT:
+            begin
+ 
+                col_cnt <= col_cnt + 8'd2;
+ 
+                if (!fault_sequence[0] && col_cnt >= 8'd127) begin
+ 
+                    // No new fault in lower lanes and almost
+                    // reached the 128 columns count, abort fault. 
+ 
+                    curr_state <= SM_INIT;
+ 
+                end
+                else if (col_cnt > 8'd127) begin
+ 
+                    // Reached the 128 columns count, abort fault.
+ 
+                    curr_state <= SM_INIT;
+ 
+                end
+                else if (|fault_sequence) begin
+ 
+                    // Clear the column count each time we see a fault,
+                    // if fault changes, go no next state.
+ 
+                    col_cnt <= 8'd0;
+ 
+                    if (seq_type != last_seq_type) begin
+                        curr_state <= SM_NEW_FAULT;
+                    end
+                end
+ 
+            end
+ 
+          SM_NEW_FAULT:
+            begin
+ 
+                // Capture new fault type. Start counters.
+ 
+                col_cnt <= 8'b0;
+                last_seq_type <= seq_type;
+ 
+                seq_cnt <= {1'b0, seq_add};
+                curr_state <= SM_COUNT;
+ 
+            end
+ 
+        endcase
+ 
+    end
+ 
+end
+ 
+endmodule
+ 
diff --git a/fpga/usrp3/lib/xge/rtl/verilog/generic_fifo.v b/fpga/usrp3/lib/xge/rtl/verilog/generic_fifo.v
new file mode 100644
index 000000000..aabe24171
--- /dev/null
+++ b/fpga/usrp3/lib/xge/rtl/verilog/generic_fifo.v
@@ -0,0 +1,204 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  File name "generic_fifo.v"                                  ////
+////                                                              ////
+////  This file is part of the "10GE MAC" project                 ////
+////  http://www.opencores.org/cores/xge_mac/                     ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - A. Tanguay (antanguay@opencores.org)                  ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2008 AUTHORS. All rights reserved.             ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+ 
+`include "defines.v"
+ 
+module generic_fifo(
+ 
+    wclk,
+    wrst_n,
+    wen,
+    wdata,
+    wfull,
+    walmost_full,
+ 
+    rclk,
+    rrst_n,
+    ren,
+    rdata,
+    rempty,
+    ralmost_empty
+);
+ 
+//---
+// Parameters
+ 
+parameter DWIDTH = 32;
+parameter AWIDTH = 3;
+parameter RAM_DEPTH = (1 << AWIDTH);
+parameter SYNC_WRITE = 1;
+parameter SYNC_READ = 1;
+parameter REGISTER_READ = 0;
+parameter EARLY_READ = 0;
+parameter CLOCK_CROSSING = 1;
+parameter ALMOST_EMPTY_THRESH = 1;
+parameter ALMOST_FULL_THRESH = RAM_DEPTH-2;
+parameter MEM_TYPE = `MEM_AUTO_SMALL;
+ 
+//---
+// Ports
+ 
+input          wclk;
+input          wrst_n;
+input          wen;
+input  [DWIDTH-1:0] wdata;
+output         wfull;
+output         walmost_full;
+ 
+input          rclk;
+input          rrst_n;
+input          ren;
+output [DWIDTH-1:0] rdata;
+output         rempty;
+output         ralmost_empty;
+ 
+// Wires
+ 
+wire             mem_wen;
+wire [AWIDTH:0]  mem_waddr;
+ 
+wire             mem_ren;
+wire [AWIDTH:0]  mem_raddr;
+ 
+ 
+generic_fifo_ctrl #(.AWIDTH (AWIDTH),
+                    .RAM_DEPTH (RAM_DEPTH), 
+                    .EARLY_READ (EARLY_READ),
+                    .CLOCK_CROSSING (CLOCK_CROSSING),
+                    .ALMOST_EMPTY_THRESH (ALMOST_EMPTY_THRESH),
+                    .ALMOST_FULL_THRESH (ALMOST_FULL_THRESH)
+                    )
+  ctrl0(.wclk (wclk),
+        .wrst_n (wrst_n),
+        .wen (wen),
+        .wfull (wfull),
+        .walmost_full (walmost_full),
+ 
+        .mem_wen (mem_wen),
+        .mem_waddr (mem_waddr),
+ 
+        .rclk (rclk),
+        .rrst_n (rrst_n),
+        .ren (ren),
+        .rempty (rempty),
+        .ralmost_empty (ralmost_empty),
+ 
+        .mem_ren (mem_ren),
+        .mem_raddr (mem_raddr)
+        );
+ 
+ 
+   generate
+      if (MEM_TYPE == `MEM_AUTO_SMALL) begin
+	 
+         generic_mem_small #(.DWIDTH (DWIDTH),
+                             .AWIDTH (AWIDTH),
+                             .RAM_DEPTH (RAM_DEPTH),
+                             .SYNC_WRITE (SYNC_WRITE),
+                             .SYNC_READ (SYNC_READ),
+                             .REGISTER_READ (REGISTER_READ)
+                             )
+           mem0(.wclk (wclk),
+		.wrst_n (wrst_n),
+		.wen (mem_wen),	
+		.waddr (mem_waddr),
+		.wdata (wdata),
+	   
+		.rclk (rclk),
+		.rrst_n (rrst_n),
+		.ren (mem_ren),
+		.roen (ren),
+		.raddr (mem_raddr),
+		.rdata (rdata)
+		);
+	 
+      end
+      
+      if (MEM_TYPE == `MEM_AUTO_MEDIUM) begin
+	 
+         generic_mem_medium #(.DWIDTH (DWIDTH),
+                              .AWIDTH (AWIDTH),
+                              .RAM_DEPTH (RAM_DEPTH),
+                              .SYNC_WRITE (SYNC_WRITE),
+                              .SYNC_READ (SYNC_READ),
+                              .REGISTER_READ (REGISTER_READ)
+                              )
+           mem0(.wclk (wclk),
+		.wrst_n (wrst_n),
+		.wen (mem_wen),	
+		.waddr (mem_waddr),
+		.wdata (wdata),
+	   
+		.rclk (rclk),
+		.rrst_n (rrst_n),
+		.ren (mem_ren),
+		.roen (ren),
+		.raddr (mem_raddr),
+		.rdata (rdata)
+		);
+	 
+      end // if (MEM_TYPE == `MEM_AUTO_MEDIUM)
+
+      if (MEM_TYPE == `MEM_AUTO_XILINX) begin
+
+	 
+	 generic_mem_xilinx_block #(.DWIDTH (DWIDTH),
+				    .AWIDTH (AWIDTH),
+				    .RAM_DEPTH (RAM_DEPTH),
+				    .SYNC_WRITE (SYNC_WRITE),
+				    .SYNC_READ (SYNC_READ),
+				    .REGISTER_READ (REGISTER_READ)
+				    )
+           mem0(.wclk (wclk),
+		.wrst_n (wrst_n),
+		.wen (mem_wen),	
+		.waddr (mem_waddr),
+		.wdata (wdata),
+	   
+		.rclk (rclk),
+		.rrst_n (rrst_n),
+		.ren (mem_ren),
+		.roen (ren),
+		.raddr (mem_raddr),
+		.rdata (rdata)
+		);
+      end
+
+   endgenerate
+   
+endmodule
+
diff --git a/fpga/usrp3/lib/xge/rtl/verilog/generic_fifo_ctrl.v b/fpga/usrp3/lib/xge/rtl/verilog/generic_fifo_ctrl.v
new file mode 100644
index 000000000..d64e662af
--- /dev/null
+++ b/fpga/usrp3/lib/xge/rtl/verilog/generic_fifo_ctrl.v
@@ -0,0 +1,273 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  File name "generic_fifo_ctrl.v"                             ////
+////                                                              ////
+////  This file is part of the "10GE MAC" project                 ////
+////  http://www.opencores.org/cores/xge_mac/                     ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - A. Tanguay (antanguay@opencores.org)                  ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2008 AUTHORS. All rights reserved.             ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+ 
+ 
+module generic_fifo_ctrl(
+ 
+    wclk,
+    wrst_n,
+    wen,
+    wfull,
+    walmost_full,
+ 
+    mem_wen,
+    mem_waddr,
+ 
+    rclk,
+    rrst_n,
+    ren,
+    rempty,
+    ralmost_empty,
+ 
+    mem_ren,
+    mem_raddr
+);
+ 
+//---
+// Parameters
+ 
+parameter AWIDTH = 3;
+parameter RAM_DEPTH = (1 << AWIDTH);
+parameter EARLY_READ = 0;
+parameter CLOCK_CROSSING = 1;
+parameter ALMOST_EMPTY_THRESH = 1;
+parameter ALMOST_FULL_THRESH = RAM_DEPTH-2;
+ 
+//---
+// Ports
+ 
+input              wclk;
+input              wrst_n;
+input              wen;
+output             wfull;
+output             walmost_full;
+ 
+output             mem_wen;
+output [AWIDTH:0]  mem_waddr;
+ 
+input              rclk;
+input              rrst_n;
+input              ren;
+output             rempty;
+output             ralmost_empty;
+ 
+output             mem_ren;
+output [AWIDTH:0]  mem_raddr;
+ 
+ 
+ 
+//---
+// Local declarations
+ 
+// Registers
+ 
+reg  [AWIDTH:0]   wr_ptr;
+reg  [AWIDTH:0]   rd_ptr;
+reg  [AWIDTH:0]   next_rd_ptr;
+ 
+// Combinatorial
+ 
+wire [AWIDTH:0]   wr_gray;
+reg  [AWIDTH:0]   wr_gray_reg;
+reg  [AWIDTH:0]   wr_gray_meta;
+reg  [AWIDTH:0]   wr_gray_sync;
+reg  [AWIDTH:0]   wck_rd_ptr;
+wire [AWIDTH:0]   wck_level;
+ 
+wire [AWIDTH:0]   rd_gray;
+reg  [AWIDTH:0]   rd_gray_reg;
+reg  [AWIDTH:0]   rd_gray_meta;
+reg  [AWIDTH:0]   rd_gray_sync;
+reg  [AWIDTH:0]   rck_wr_ptr;
+wire [AWIDTH:0]   rck_level;
+ 
+wire [AWIDTH:0]   depth;
+wire [AWIDTH:0]   empty_thresh;
+wire [AWIDTH:0]   full_thresh;
+ 
+// Variables
+ 
+integer         i;
+ 
+//---
+// Assignments
+ 
+assign depth = RAM_DEPTH[AWIDTH:0];
+assign empty_thresh = ALMOST_EMPTY_THRESH[AWIDTH:0];
+assign full_thresh = ALMOST_FULL_THRESH[AWIDTH:0];
+ 
+assign wfull = (wck_level == depth);
+assign walmost_full = (wck_level >= (depth - full_thresh));
+assign rempty = (rck_level == 0);
+assign ralmost_empty = (rck_level <= empty_thresh);
+ 
+//---
+// Write Pointer
+ 
+always @(posedge wclk or negedge wrst_n)
+begin
+    if (!wrst_n) begin
+        wr_ptr <= {(AWIDTH+1){1'b0}};
+    end
+    else if (wen && !wfull) begin
+        wr_ptr <= wr_ptr + {{(AWIDTH){1'b0}}, 1'b1};
+    end
+end
+ 
+//---
+// Read Pointer
+ 
+always @(ren, rd_ptr, rck_wr_ptr)
+begin
+    next_rd_ptr = rd_ptr;
+    if (ren && rd_ptr != rck_wr_ptr) begin
+        next_rd_ptr = rd_ptr + {{(AWIDTH){1'b0}}, 1'b1};
+    end
+end
+ 
+always @(posedge rclk or negedge rrst_n)
+begin
+    if (!rrst_n) begin
+        rd_ptr <= {(AWIDTH+1){1'b0}};
+    end
+    else begin
+        rd_ptr <= next_rd_ptr;
+    end
+end
+ 
+//---
+// Binary to Gray conversion
+ 
+assign wr_gray = wr_ptr ^ (wr_ptr >> 1);
+assign rd_gray = rd_ptr ^ (rd_ptr >> 1);
+ 
+//---
+// Gray to Binary conversion
+ 
+always @(wr_gray_sync)
+begin
+    rck_wr_ptr[AWIDTH] = wr_gray_sync[AWIDTH];
+    for (i = 0; i < AWIDTH; i = i + 1) begin
+        rck_wr_ptr[AWIDTH-i-1] = rck_wr_ptr[AWIDTH-i] ^ wr_gray_sync[AWIDTH-i-1];
+    end
+end
+ 
+always @(rd_gray_sync)
+begin
+    wck_rd_ptr[AWIDTH] = rd_gray_sync[AWIDTH];
+    for (i = 0; i < AWIDTH; i = i + 1) begin
+        wck_rd_ptr[AWIDTH-i-1] = wck_rd_ptr[AWIDTH-i] ^ rd_gray_sync[AWIDTH-i-1];
+    end
+end
+ 
+//---
+// Clock-Domain Crossing
+ 
+generate
+    if (CLOCK_CROSSING) begin
+ 
+        // Instantiate metastability flops
+        always @(posedge rclk or negedge rrst_n)
+        begin
+            if (!rrst_n) begin
+                rd_gray_reg <= {(AWIDTH+1){1'b0}};
+                wr_gray_meta <= {(AWIDTH+1){1'b0}};
+                wr_gray_sync <= {(AWIDTH+1){1'b0}};
+            end
+            else begin
+                rd_gray_reg <= rd_gray;
+                wr_gray_meta <= wr_gray_reg;
+                wr_gray_sync <= wr_gray_meta;
+            end
+        end
+ 
+        always @(posedge wclk or negedge wrst_n)
+        begin
+            if (!wrst_n) begin
+                wr_gray_reg <= {(AWIDTH+1){1'b0}};
+                rd_gray_meta <= {(AWIDTH+1){1'b0}};
+                rd_gray_sync <= {(AWIDTH+1){1'b0}};
+            end
+            else begin
+                wr_gray_reg <= wr_gray;
+                rd_gray_meta <= rd_gray_reg;
+                rd_gray_sync <= rd_gray_meta;
+            end
+        end
+    end
+    else begin
+ 
+        // No clock domain crossing
+        always @(wr_gray or rd_gray)
+        begin
+            wr_gray_sync = wr_gray;
+            rd_gray_sync = rd_gray;
+        end
+    end
+endgenerate
+ 
+//---
+// FIFO Level
+ 
+assign wck_level = wr_ptr - wck_rd_ptr;
+assign rck_level = rck_wr_ptr - rd_ptr;
+ 
+//---
+// Memory controls
+ 
+assign  mem_waddr = wr_ptr;
+assign  mem_wen = wen && !wfull;
+ 
+generate
+    if (EARLY_READ) begin
+ 
+        // With early read, data will be present at output
+        // before ren is asserted. Usufull if we want to add
+        // an output register and not add latency.
+        assign mem_raddr = next_rd_ptr;
+        assign mem_ren = 1'b1;
+ 
+    end
+    else begin
+ 
+        assign mem_raddr = rd_ptr;
+        assign mem_ren = ren;
+ 
+    end
+endgenerate
+ 
+endmodule
diff --git a/fpga/usrp3/lib/xge/rtl/verilog/generic_mem_medium.v b/fpga/usrp3/lib/xge/rtl/verilog/generic_mem_medium.v
new file mode 100644
index 000000000..db857ff63
--- /dev/null
+++ b/fpga/usrp3/lib/xge/rtl/verilog/generic_mem_medium.v
@@ -0,0 +1,180 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  File name "generic_mem_medium.v"                            ////
+////                                                              ////
+////  This file is part of the "10GE MAC" project                 ////
+////  http://www.opencores.org/cores/xge_mac/                     ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - A. Tanguay (antanguay@opencores.org)                  ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2008 AUTHORS. All rights reserved.             ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+ 
+ 
+module generic_mem_medium(
+ 
+    wclk,
+    wrst_n,
+    wen,
+    waddr,
+    wdata,
+ 
+    rclk,
+    rrst_n,
+    ren,
+    roen,
+    raddr,
+    rdata
+);
+ 
+//---
+// Parameters
+ 
+parameter DWIDTH = 32;
+parameter AWIDTH = 3;
+parameter RAM_DEPTH = (1 << AWIDTH);
+parameter SYNC_WRITE = 1;
+parameter SYNC_READ = 1;
+parameter REGISTER_READ = 0;
+ 
+//---
+// Ports
+ 
+input               wclk;
+input               wrst_n;
+input               wen;
+input  [AWIDTH:0]   waddr;
+input  [DWIDTH-1:0] wdata;
+ 
+input               rclk;
+input               rrst_n;
+input               ren;
+input               roen;
+input  [AWIDTH:0]   raddr;
+output [DWIDTH-1:0] rdata;
+ 
+// Registered outputs
+reg    [DWIDTH-1:0] rdata;
+ 
+ 
+//---
+// Local declarations
+ 
+// Registers
+ 
+reg  [DWIDTH-1:0] mem_rdata;
+ 
+ 
+// Memory - infer using Xilinx pragma for block ram.
+//synthesis attribute ram_style of mem is block
+reg  [DWIDTH-1:0] mem [0:RAM_DEPTH-1];
+ 
+// Variables
+ 
+integer         i;
+ 
+ 
+//---
+// Memory Write
+ 
+generate
+    if (SYNC_WRITE) begin
+ 
+        // Generate synchronous write
+        always @(posedge wclk)
+        begin
+            if (wen) begin
+                mem[waddr[AWIDTH-1:0]] <= wdata;
+            end
+        end
+    end
+    else begin
+ 
+        // Generate asynchronous write
+        always @(wen, waddr, wdata)
+        begin
+            if (wen) begin
+                mem[waddr[AWIDTH-1:0]] = wdata;
+            end
+        end
+    end
+endgenerate
+ 
+//---
+// Memory Read
+ 
+generate
+    if (SYNC_READ) begin
+ 
+        // Generate registered memory read
+        always @(posedge rclk /* IJB  or negedge rrst_n*/)
+        begin
+            if (!rrst_n) begin
+                mem_rdata <= {(DWIDTH){1'b0}};
+            end else if (ren) begin
+                mem_rdata <= mem[raddr[AWIDTH-1:0]];
+            end
+        end
+    end
+    else begin
+ 
+        // Generate unregisters memory read
+        always @(raddr, rclk)
+        begin
+            mem_rdata = mem[raddr[AWIDTH-1:0]];
+        end
+    end
+endgenerate
+ 
+generate
+    if (REGISTER_READ) begin
+ 
+        // Generate registered output
+        always @(posedge rclk /* IJB or negedge rrst_n*/ )
+        begin
+            if (!rrst_n) begin
+                rdata <= {(DWIDTH){1'b0}};
+            end else if (roen) begin
+                rdata <= mem_rdata;
+            end
+        end
+ 
+    end
+    else begin
+ 
+        // Generate unregisters output
+        always @(mem_rdata)
+        begin
+            rdata = mem_rdata;
+        end
+ 
+    end
+endgenerate
+ 
+endmodule
+ 
diff --git a/fpga/usrp3/lib/xge/rtl/verilog/generic_mem_small.v b/fpga/usrp3/lib/xge/rtl/verilog/generic_mem_small.v
new file mode 100644
index 000000000..552e628e7
--- /dev/null
+++ b/fpga/usrp3/lib/xge/rtl/verilog/generic_mem_small.v
@@ -0,0 +1,181 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  File name "generic_mem_small.v"                             ////
+////                                                              ////
+////  This file is part of the "10GE MAC" project                 ////
+////  http://www.opencores.org/cores/xge_mac/                     ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - A. Tanguay (antanguay@opencores.org)                  ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2008 AUTHORS. All rights reserved.             ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+ 
+
+ 
+module generic_mem_small(
+ 
+    wclk,
+    wrst_n,
+    wen,
+    waddr,
+    wdata,
+ 
+    rclk,
+    rrst_n,
+    ren,
+    roen,
+    raddr,
+    rdata
+);
+ 
+//---
+// Parameters
+ 
+parameter DWIDTH = 32;
+parameter AWIDTH = 3;
+parameter RAM_DEPTH = (1 << AWIDTH);
+parameter SYNC_WRITE = 1;
+parameter SYNC_READ = 1;
+parameter REGISTER_READ = 0;
+ 
+//---
+// Ports
+ 
+input               wclk;
+input               wrst_n;
+input               wen;
+input  [AWIDTH:0]   waddr;
+input  [DWIDTH-1:0] wdata;
+ 
+input               rclk;
+input               rrst_n;
+input               ren;
+input               roen;
+input  [AWIDTH:0]   raddr;
+output [DWIDTH-1:0] rdata;
+ 
+// Registered outputs
+reg    [DWIDTH-1:0] rdata;
+ 
+ 
+//---
+// Local declarations
+ 
+// Registers
+ 
+reg  [DWIDTH-1:0] mem_rdata;
+ 
+ 
+// Memory
+ 
+(* ram_style = "block" *) reg  [DWIDTH-1:0] mem [0:RAM_DEPTH-1];
+ 
+// Variables
+ 
+integer         i;
+ 
+ 
+//---
+// Memory Write
+ 
+generate
+    if (SYNC_WRITE) begin
+ 
+        // Generate synchronous write
+        always @(posedge wclk)
+        begin
+            if (wen) begin
+                mem[waddr[AWIDTH-1:0]] <= wdata;
+            end
+        end
+    end
+    else begin
+ 
+        // Generate asynchronous write
+        always @(wen, waddr, wdata)
+        begin
+            if (wen) begin
+                mem[waddr[AWIDTH-1:0]] = wdata;
+            end
+        end
+    end
+endgenerate
+ 
+//---
+// Memory Read
+ 
+generate
+    if (SYNC_READ) begin
+ 
+        // Generate registered memory read
+        always @(posedge rclk  /* IJB or negedge rrst_n */)
+        begin
+            if (!rrst_n) begin
+                mem_rdata <= {(DWIDTH){1'b0}};
+            end else if (ren) begin
+                mem_rdata <= mem[raddr[AWIDTH-1:0]];
+            end
+        end
+    end
+    else begin
+ 
+        // Generate unregisters memory read
+        always @(raddr, rclk)
+        begin
+            mem_rdata = mem[raddr[AWIDTH-1:0]];
+        end
+    end
+endgenerate
+ 
+generate
+    if (REGISTER_READ) begin
+ 
+        // Generate registered output
+        always @(posedge rclk /* IJB or negedge rrst_n*/)
+        begin
+            if (!rrst_n) begin
+                rdata <= {(DWIDTH){1'b0}};
+            end else if (roen) begin
+                rdata <= mem_rdata;
+            end
+        end
+ 
+    end
+    else begin
+ 
+        // Generate unregisters output
+        always @(mem_rdata)
+        begin
+            rdata = mem_rdata;
+        end
+ 
+    end
+endgenerate
+ 
+endmodule
+ 
diff --git a/fpga/usrp3/lib/xge/rtl/verilog/generic_mem_xilinx_block.v b/fpga/usrp3/lib/xge/rtl/verilog/generic_mem_xilinx_block.v
new file mode 100644
index 000000000..4a7baf431
--- /dev/null
+++ b/fpga/usrp3/lib/xge/rtl/verilog/generic_mem_xilinx_block.v
@@ -0,0 +1,154 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  File name "generic_mem_medium.v"                            ////
+////                                                              ////
+////  This file is part of the "10GE MAC" project                 ////
+////  http://www.opencores.org/cores/xge_mac/                     ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - A. Tanguay (antanguay@opencores.org)                  ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2008 AUTHORS. All rights reserved.             ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+ 
+ 
+module generic_mem_xilinx_block(
+ 
+    wclk,
+    wrst_n,
+    wen,
+    waddr,
+    wdata,
+ 
+    rclk,
+    rrst_n,
+    ren,
+    roen,
+    raddr,
+    rdata
+);
+ 
+//---
+// Parameters
+ 
+parameter DWIDTH = 32;
+parameter AWIDTH = 3;
+parameter RAM_DEPTH = (1 << AWIDTH);
+parameter SYNC_WRITE = 1;
+parameter SYNC_READ = 1;
+parameter REGISTER_READ = 0;
+ 
+//---
+// Ports
+ 
+input               wclk;
+input               wrst_n;
+input               wen;
+input  [AWIDTH:0]   waddr;
+input  [DWIDTH-1:0] wdata;
+ 
+input               rclk;
+input               rrst_n;
+input               ren;
+input               roen;
+input  [AWIDTH:0]   raddr;
+output [DWIDTH-1:0] rdata;
+ 
+// Registered outputs
+reg    [DWIDTH-1:0] rdata;
+ 
+ 
+//---
+// Local declarations
+ 
+// Registers
+ 
+reg  [DWIDTH-1:0] mem_rdata;
+ 
+ 
+// Memory - infer using Xilinx pragma for block ram.
+//synthesis attribute ram_style of mem is block
+reg  [DWIDTH-1:0] mem [0:RAM_DEPTH-1];
+ 
+// Variables
+ 
+integer         i;
+ 
+   
+   //---
+   // Memory Write
+   
+   // Generate synchronous write
+   always @(posedge wclk)
+     begin
+        if (wen) begin
+           mem[waddr[AWIDTH-1:0]] <= wdata;
+        end
+     end
+   
+
+   //---
+   // Memory Read
+
+   // Generate registered memory read
+   always @(posedge rclk)
+     begin
+	if (!rrst_n) begin
+           mem_rdata <= {(DWIDTH){1'b0}};
+	end else if (ren) begin
+           mem_rdata <= mem[raddr[AWIDTH-1:0]];
+	end
+     end
+   
+ 
+generate
+    if (REGISTER_READ) begin
+ 
+        // Generate registered output
+        always @(posedge rclk)
+        begin
+            if (!rrst_n) begin
+                rdata <= {(DWIDTH){1'b0}};
+            end else if (roen) begin
+                rdata <= mem_rdata;
+            end
+        end
+ 
+    end
+    else begin
+ 
+        // Generate unregisters output
+        always @(mem_rdata)
+        begin
+            rdata = mem_rdata;
+        end
+ 
+    end
+endgenerate
+ 
+endmodule
+ 
diff --git a/fpga/usrp3/lib/xge/rtl/verilog/meta_sync.v b/fpga/usrp3/lib/xge/rtl/verilog/meta_sync.v
new file mode 100644
index 000000000..db35d4b5c
--- /dev/null
+++ b/fpga/usrp3/lib/xge/rtl/verilog/meta_sync.v
@@ -0,0 +1,76 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  File name "meta_sync.v"                                     ////
+////                                                              ////
+////  This file is part of the "10GE MAC" project                 ////
+////  http://www.opencores.org/cores/xge_mac/                     ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - A. Tanguay (antanguay@opencores.org)                  ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2008 AUTHORS. All rights reserved.             ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+ 
+ 
+module meta_sync(/*AUTOARG*/
+  // Outputs
+  out,
+  // Inputs
+  clk, reset_n, in
+  );
+ 
+parameter DWIDTH = 1;
+parameter EDGE_DETECT = 0;
+ 
+input                clk;
+input                reset_n;
+ 
+input  [DWIDTH-1:0]  in;
+ 
+output [DWIDTH-1:0]  out;
+ 
+generate
+genvar               i;
+ 
+    for (i = 0; i < DWIDTH; i = i + 1) begin : meta
+ 
+        meta_sync_single #(.EDGE_DETECT (EDGE_DETECT))
+          meta_sync_single0 (
+                      // Outputs
+                      .out              (out[i]),
+                      // Inputs
+                      .clk              (clk),
+                      .reset_n          (reset_n),
+                      .in               (in[i]));
+ 
+    end
+ 
+endgenerate
+ 
+endmodule
+ 
+ 
\ No newline at end of file
diff --git a/fpga/usrp3/lib/xge/rtl/verilog/meta_sync_single.v b/fpga/usrp3/lib/xge/rtl/verilog/meta_sync_single.v
new file mode 100644
index 000000000..e2c7d8cbb
--- /dev/null
+++ b/fpga/usrp3/lib/xge/rtl/verilog/meta_sync_single.v
@@ -0,0 +1,105 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  File name "meta_sync_single.v"                              ////
+////                                                              ////
+////  This file is part of the "10GE MAC" project                 ////
+////  http://www.opencores.org/cores/xge_mac/                     ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - A. Tanguay (antanguay@opencores.org)                  ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2008 AUTHORS. All rights reserved.             ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+ 
+ 
+module meta_sync_single(/*AUTOARG*/
+  // Outputs
+  out,
+  // Inputs
+  clk, reset_n, in
+  );
+ 
+parameter EDGE_DETECT = 0;
+ 
+input   clk;
+input   reset_n;
+ 
+input   in;
+ 
+output  out;
+ 
+reg     out;
+ 
+ 
+ 
+generate
+ 
+    if (EDGE_DETECT) begin
+ 
+      reg   meta;
+      reg   edg1;
+      reg   edg2;
+ 
+        always @(posedge clk or negedge reset_n) begin
+ 
+            if (reset_n == 1'b0) begin
+                meta <= 1'b0;
+                edg1 <= 1'b0;
+                edg2 <= 1'b0;
+                out <= 1'b0;
+            end
+            else begin
+                meta <= in;
+                edg1 <= meta;
+                edg2 <= edg1;
+                out <= edg1 ^ edg2;
+            end
+        end
+ 
+    end
+    else begin
+ 
+      reg   meta;
+ 
+        always @(posedge clk or negedge reset_n) begin
+ 
+            if (reset_n == 1'b0) begin
+                meta <= 1'b0;
+                out <= 1'b0;
+            end
+            else begin
+                meta <= in;
+                out <= meta;
+            end
+        end
+ 
+    end
+ 
+endgenerate
+ 
+endmodule
+ 
diff --git a/fpga/usrp3/lib/xge/rtl/verilog/rx_checker.v b/fpga/usrp3/lib/xge/rtl/verilog/rx_checker.v
new file mode 100644
index 000000000..cb775a8d8
--- /dev/null
+++ b/fpga/usrp3/lib/xge/rtl/verilog/rx_checker.v
@@ -0,0 +1,275 @@
+//
+// Synthesizable Rx checker for 10G Ethernet MAC.
+// Collects recevied packets and checks them against the deterministic expected result
+// to verify correct loopback functionality if used with the tx_checker.
+//
+
+`define IDLE 0
+`define SEARCH 1
+`define RECEIVE1 2
+`define RECEIVE2 3
+`define RECEIVE3 4
+`define DONE 5
+`define ERROR1 6
+`define ERROR2 7
+`define ERROR3 8
+
+
+module rx_checker
+  (
+   input clk156,
+   input rst,
+   input enable,
+   output reg done,
+   output reg correct,
+   output reg [1:0] error,
+   //
+   input pkt_rx_avail,
+   input pkt_rx_val,
+   input pkt_rx_sop,
+   input pkt_rx_eop,
+   input [2:0] pkt_rx_mod,
+   input [63:0] pkt_rx_data,
+   input pkt_rx_err,
+   output reg pkt_rx_ren
+   );
+
+
+   reg [10:0] 	 payload;
+   reg [10:0] 	 count;
+   reg [7:0] 	 state;
+
+   
+always @(posedge clk156)
+  if (rst)
+    begin
+       // Reset
+       state <= `IDLE;
+       done <= 0;
+       correct <= 0;
+       error <= 0;
+       pkt_rx_ren <= 0;
+       count <= 0;
+       payload <= 45; // 1 less than ethernet minimum payload size.\
+    end
+  else
+    begin
+       // Defaults
+       state <= state;
+       done <= 0;
+       correct <= 0;
+       error <= 0;
+       pkt_rx_ren <= 0;
+       count <= count;
+       payload <= payload;
+       
+            
+       case(state)
+	 // Wait in IDLE state until enabled.
+	 // incomming packets will not be detected in this state.
+	 `IDLE: begin
+	    if (enable)  
+	      state <= `SEARCH;
+	 end // case: `IDLE
+	 //
+	 // Search for pkt_rx_avail going asserted to show that a packet is in the MAC's FIFO's.
+	 // Then assert pkt_rx_ren back to MAC to start transfer. pkt_rx_ren now remains asserted until 
+	 // at least EOP, longer if pkt_rx_avail is still asserted at EOP as back-to-back Rx is possible.
+	 // We can come into this state with pkt_rx_ren already enabled for back-to-back Rx cases.
+	 //
+	 `SEARCH: begin
+	      if (pkt_rx_val)
+	      state <= `ERROR1;  // Illegal signalling
+	    else if (payload == 1500)
+	      state <= `DONE;
+	    else if (pkt_rx_avail)
+	      begin // rx_avail has been asserted, now assert rx_ren to start transfer.
+		 payload <= payload + 1; 
+		 pkt_rx_ren <= 1;
+		 state <= `RECEIVE1;
+	      end
+	 end
+	 //
+	 // Now wait for pkt_rx_val and pkt_rx_sop to assert in the same cycle with the first 
+	 // 8 octects of a new packet. When asserted check all data bits against expected data.
+	 // Go to error states if something doesn't match or work correctly.
+	 //
+	 `RECEIVE1: begin
+	    pkt_rx_ren <= 1;
+	    
+	    if (pkt_rx_err)
+	      state <= `ERROR3; // CRC error from MAC
+	    else if (pkt_rx_val && pkt_rx_sop && ~pkt_rx_eop)
+	      begin
+		 if ((pkt_rx_data[63:16] == 48'h0001020304) && (pkt_rx_data[15:0] == 16'h0000) && (pkt_rx_mod == 3'h0))
+		   state <= `RECEIVE2;
+		 else
+		   state <= `ERROR2; // Data missmatch error	 
+	      end	    
+	    else if (pkt_rx_val || pkt_rx_sop || pkt_rx_eop) // Error condition
+	      begin
+		 state <= `ERROR1; // Illegal signalling
+	      end
+	 end // case: `RECEIVE1
+	 //
+	 // Check all data bits against expected data.
+	 // Go to error states if something doesn't match or work correctly.
+	 //
+	 `RECEIVE2: begin
+	    pkt_rx_ren <= 1;
+	    
+	    if (pkt_rx_err)
+	      state <= `ERROR3; // CRC error from MAC
+	    else if (pkt_rx_val && ~pkt_rx_sop && ~pkt_rx_eop)
+	      begin
+		 if ((pkt_rx_data[63:32] == 32'h05060708) && 
+		     (pkt_rx_data[31:16] == 16'h88b5) && 
+		     (pkt_rx_data[15:0] == 16'hBEEF) && 
+		     (pkt_rx_mod == 3'h0))
+		   begin
+		      count <= payload - 2; // Preload counter for this packet
+		      state <= `RECEIVE3;
+		   end
+		 else
+		   state <= `ERROR2; // Data missmatch error	 
+	      end	    
+	    else if (~pkt_rx_val || pkt_rx_sop || pkt_rx_eop) // Error condition
+	      begin
+		 state <= `ERROR1; // Illegal signalling
+	      end
+	 end // case: `RECEIVE2
+	 //
+	 // Should now have received both MAC addresses, the ETHERTYPE and first 2 octects of payload.
+	 // Check remaining payload whilst looking for end of packet.
+	 // Currently don;pt support chained RX of packets, pkt_rx_en will go to 0.
+	 // (Remember packets are bigendian)
+	 //
+	 `RECEIVE3: begin
+	    count <= count - 8;
+	    
+	    if (pkt_rx_err)
+	      state <= `ERROR3; // CRC error from MAC
+	    else if (pkt_rx_val && ~pkt_rx_sop) 
+	      begin
+		 case({pkt_rx_eop,pkt_rx_mod})
+		   4'b0000: begin
+		      if (pkt_rx_data[63:0] == {8{count[10:3]}})
+			begin
+			   pkt_rx_ren <= 1;
+			   state <= `RECEIVE3;
+			end
+		      else
+			state <= `ERROR2; // Data missmatch error	 
+		   end
+		   4'b1000: begin
+		      if (pkt_rx_data[63:0] == {8{count[10:3]}})
+			begin
+			   pkt_rx_ren <= 0;	     
+			   state <= `SEARCH;
+			end
+		      else
+			state <= `ERROR2; // Data missmatch error	 
+		   end
+		   4'b1001: begin
+		      if (pkt_rx_data[63:56] == {1{count[10:3]}})	      
+			begin
+			   pkt_rx_ren <= 0;	     
+			   state <= `SEARCH;
+			end	     
+		      else
+			state <= `ERROR2; // Data missmatch error	 
+		   end
+		   4'b1010: begin
+		      if (pkt_rx_data[63:48] == {2{count[10:3]}})		
+			begin
+			   pkt_rx_ren <= 0;	     
+			   state <= `SEARCH;
+			end
+		      else
+			state <= `ERROR2; // Data missmatch error	 
+		   end
+		   4'b1011: begin
+		      if (pkt_rx_data[63:40] == {3{count[10:3]}})		
+			begin
+			   pkt_rx_ren <= 0;	     
+			   state <= `SEARCH;
+			end
+		      else
+			state <= `ERROR2; // Data missmatch error	 
+		   end
+		   4'b1100: begin
+		      if (pkt_rx_data[63:32] == {4{count[10:3]}})
+			begin
+			   pkt_rx_ren <= 0;	     
+			   state <= `SEARCH;
+			end
+		      else
+			state <= `ERROR2; // Data missmatch error	 
+		   end
+		   4'b1101: begin
+		      if (pkt_rx_data[63:24] == {5{count[10:3]}})
+			begin
+			   pkt_rx_ren <= 0;	     
+			   state <= `SEARCH;
+			end
+		      else
+			state <= `ERROR2; // Data missmatch error	 
+		   end
+		   4'b1110: begin
+		      if (pkt_rx_data[63:16] == {6{count[10:3]}})
+			begin
+			   pkt_rx_ren <= 0;	     
+			   state <= `SEARCH;
+			end
+		      else
+			state <= `ERROR2; // Data missmatch error	 
+		   end
+		   4'b1111: begin
+		      if (pkt_rx_data[63:8] == {7{count[10:3]}})
+			begin
+			   pkt_rx_ren <= 0;	     
+			   state <= `SEARCH;
+			end
+		      else
+			state <= `ERROR2; // Data missmatch error	 
+		   end
+		   default: state <= `ERROR1;  // Illegal signalling
+		 endcase // case({pkt_rx_eop,pkt_rx_mod})		 
+	      end	   
+	 end
+	 //
+	 // Finished. Received and verified full sequence. Now assert corret signal and done.
+	 // Stay in this state until reset.
+	 //
+	 `DONE: begin
+	    done <= 1;
+	    correct <= 1;
+	 end
+	 //
+	 // Signal protocol error.
+	 // Stay in this state until reset.
+	 //
+	 `ERROR1: begin
+	    done <= 1;
+	    error <= 1;
+	 end
+	 //
+	 // Data payload of packet did not match reference
+	 // Stay in this state until reset.
+	 //
+	 `ERROR2: begin
+	    done <= 1;
+	    error <= 2;
+	 end
+	 //
+	 // CRC error reported by MAC
+	 // Stay in this state until reset.
+	 //
+	 `ERROR3: begin
+	    done <= 1;
+	    error <= 3;
+	 end
+       endcase
+    end
+
+endmodule // rx_checker
diff --git a/fpga/usrp3/lib/xge/rtl/verilog/rx_data_fifo.v b/fpga/usrp3/lib/xge/rtl/verilog/rx_data_fifo.v
new file mode 100644
index 000000000..e38747f45
--- /dev/null
+++ b/fpga/usrp3/lib/xge/rtl/verilog/rx_data_fifo.v
@@ -0,0 +1,95 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  File name "rx_data_fifo.v"                                  ////
+////                                                              ////
+////  This file is part of the "10GE MAC" project                 ////
+////  http://www.opencores.org/cores/xge_mac/                     ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - A. Tanguay (antanguay@opencores.org)                  ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2008 AUTHORS. All rights reserved.             ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+ 
+ 
+`include "defines.v"
+ 
+module rx_data_fifo(/*AUTOARG*/
+  // Outputs
+  rxdfifo_wfull, rxdfifo_rdata, rxdfifo_rstatus, rxdfifo_rempty,
+  rxdfifo_ralmost_empty,
+  // Inputs
+  clk_xgmii_rx, clk_156m25, reset_xgmii_rx_n, reset_156m25_n,
+  rxdfifo_wdata, rxdfifo_wstatus, rxdfifo_wen, rxdfifo_ren
+  );
+ 
+input         clk_xgmii_rx;
+input         clk_156m25;
+input         reset_xgmii_rx_n;
+input         reset_156m25_n;
+ 
+input [63:0]  rxdfifo_wdata;
+input [7:0]   rxdfifo_wstatus;
+input         rxdfifo_wen;
+ 
+input         rxdfifo_ren;
+ 
+output        rxdfifo_wfull;
+ 
+output [63:0] rxdfifo_rdata;
+output [7:0]  rxdfifo_rstatus;
+output        rxdfifo_rempty;
+output        rxdfifo_ralmost_empty;
+ 
+generic_fifo #(
+  .DWIDTH (72),
+  .AWIDTH (`RX_DATA_FIFO_AWIDTH),
+  .REGISTER_READ (0),
+  .EARLY_READ (1),
+  .CLOCK_CROSSING (1),
+  .ALMOST_EMPTY_THRESH (4),
+  .MEM_TYPE (`MEM_AUTO_XILINX)
+)
+fifo0(
+    .wclk (clk_xgmii_rx),
+    .wrst_n (reset_xgmii_rx_n),
+    .wen (rxdfifo_wen),
+    .wdata ({rxdfifo_wstatus, rxdfifo_wdata}),
+    .wfull (rxdfifo_wfull),
+    .walmost_full (),
+ 
+    .rclk (clk_156m25),
+    .rrst_n (reset_156m25_n),
+    .ren (rxdfifo_ren),
+    .rdata ({rxdfifo_rstatus, rxdfifo_rdata}),
+    .rempty (rxdfifo_rempty),
+    .ralmost_empty (rxdfifo_ralmost_empty)
+);
+ 
+ 
+endmodule
+ 
diff --git a/fpga/usrp3/lib/xge/rtl/verilog/rx_dequeue.v b/fpga/usrp3/lib/xge/rtl/verilog/rx_dequeue.v
new file mode 100644
index 000000000..3603f6d0c
--- /dev/null
+++ b/fpga/usrp3/lib/xge/rtl/verilog/rx_dequeue.v
@@ -0,0 +1,205 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  File name "rx_dequeue.v"                                    ////
+////                                                              ////
+////  This file is part of the "10GE MAC" project                 ////
+////  http://www.opencores.org/cores/xge_mac/                     ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - A. Tanguay (antanguay@opencores.org)                  ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2008 AUTHORS. All rights reserved.             ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+ 
+ 
+`include "defines.v"
+ 
+module rx_dequeue(/*AUTOARG*/
+  // Outputs
+  rxdfifo_ren, pkt_rx_data, pkt_rx_val, pkt_rx_sop, pkt_rx_eop,
+  pkt_rx_err, pkt_rx_mod, pkt_rx_avail, status_rxdfifo_udflow_tog,
+  // Inputs
+  clk_156m25, reset_156m25_n, rxdfifo_rdata, rxdfifo_rstatus,
+  rxdfifo_rempty, rxdfifo_ralmost_empty, pkt_rx_ren
+  );
+ 
+input         clk_156m25;
+input         reset_156m25_n;
+ 
+input [63:0]  rxdfifo_rdata;
+input [7:0]   rxdfifo_rstatus;
+input         rxdfifo_rempty;
+input         rxdfifo_ralmost_empty;
+ 
+input         pkt_rx_ren;
+ 
+output        rxdfifo_ren;
+ 
+output [63:0] pkt_rx_data;
+output        pkt_rx_val;
+output        pkt_rx_sop;
+output        pkt_rx_eop;
+output        pkt_rx_err;
+output [2:0]  pkt_rx_mod;
+output        pkt_rx_avail;
+ 
+output        status_rxdfifo_udflow_tog;
+ 
+/*AUTOREG*/
+// Beginning of automatic regs (for this module's undeclared outputs)
+reg                     pkt_rx_avail;
+reg [63:0]              pkt_rx_data;
+reg                     pkt_rx_eop;
+reg                     pkt_rx_err;
+reg [2:0]               pkt_rx_mod;
+reg                     pkt_rx_sop;
+reg                     pkt_rx_val;
+reg                     status_rxdfifo_udflow_tog;
+// End of automatics
+ 
+reg           end_eop;
+ 
+/*AUTOWIRE*/
+ 
+ 
+// End eop to force one cycle between packets
+ 
+assign rxdfifo_ren = !rxdfifo_rempty && pkt_rx_ren && !end_eop;
+ 
+ 
+ 
+always @(posedge clk_156m25 or negedge reset_156m25_n) begin
+ 
+    if (reset_156m25_n == 1'b0) begin
+ 
+        pkt_rx_avail <= 1'b0;
+ 
+        pkt_rx_data <= 64'b0;
+        pkt_rx_sop <= 1'b0;
+        pkt_rx_eop <= 1'b0;
+        pkt_rx_err <= 1'b0;
+        pkt_rx_mod <= 3'b0;
+ 
+        pkt_rx_val <= 1'b0;
+ 
+        end_eop <= 1'b0;
+ 
+        status_rxdfifo_udflow_tog <= 1'b0;
+ 
+    end
+    else begin
+ 
+        pkt_rx_avail <= !rxdfifo_ralmost_empty;
+ 
+ 
+ 
+        // If eop shows up at the output of the fifo, we drive eop on
+        // the bus on the next read. This will be the last read for this
+        // packet. The fifo is designed to output data early. On last read,
+        // data from next packet will appear at the output of fifo. Modulus
+        // of packet length is in lower bits.
+ 
+        pkt_rx_eop <= rxdfifo_ren && rxdfifo_rstatus[`RXSTATUS_EOP];
+        pkt_rx_mod <= {3{rxdfifo_ren & rxdfifo_rstatus[`RXSTATUS_EOP]}} & rxdfifo_rstatus[2:0];
+ 
+ 
+        pkt_rx_val <= rxdfifo_ren;
+ 
+        if (rxdfifo_ren) begin
+ 
+            `ifdef BIGENDIAN
+	    pkt_rx_data <= {rxdfifo_rdata[7:0],
+                            rxdfifo_rdata[15:8],
+                            rxdfifo_rdata[23:16],
+                            rxdfifo_rdata[31:24],
+                            rxdfifo_rdata[39:32],
+                            rxdfifo_rdata[47:40],
+                            rxdfifo_rdata[55:48],
+                            rxdfifo_rdata[63:56]};
+            `else
+	    pkt_rx_data <= rxdfifo_rdata;
+            `endif
+ 
+        end
+ 
+ 
+        if (rxdfifo_ren && rxdfifo_rstatus[`RXSTATUS_SOP]) begin
+ 
+            // SOP indication on first word
+ 
+            pkt_rx_sop <= 1'b1;
+            pkt_rx_err <= 1'b0;
+ 
+        end
+        else begin
+ 
+            pkt_rx_sop <= 1'b0;
+ 
+ 
+            // Give an error if FIFO is to underflow
+ 
+            if (rxdfifo_rempty && pkt_rx_ren && !end_eop) begin
+                pkt_rx_val <= 1'b1;
+                pkt_rx_eop <= 1'b1;
+                pkt_rx_err <= 1'b1;
+            end
+ 
+        end
+ 
+ 
+        if (rxdfifo_ren && |(rxdfifo_rstatus[`RXSTATUS_ERR])) begin
+ 
+            // Status stored in FIFO is propagated to error signal.
+ 
+            pkt_rx_err <= 1'b1;
+ 
+        end
+ 
+ 
+        //---
+        // EOP indication at the end of the frame. Cleared otherwise.
+ 
+        if (rxdfifo_ren && rxdfifo_rstatus[`RXSTATUS_EOP]) begin
+            end_eop <= 1'b1;
+        end
+        else if (pkt_rx_ren) begin
+            end_eop <= 1'b0;
+        end
+ 
+ 
+ 
+        //---
+        // FIFO errors, used to generate interrupts
+ 
+        if (rxdfifo_rempty && pkt_rx_ren && !end_eop) begin
+            status_rxdfifo_udflow_tog <= ~status_rxdfifo_udflow_tog;
+        end
+ 
+    end
+end
+ 
+endmodule
diff --git a/fpga/usrp3/lib/xge/rtl/verilog/rx_enqueue.v b/fpga/usrp3/lib/xge/rtl/verilog/rx_enqueue.v
new file mode 100644
index 000000000..98a5ac660
--- /dev/null
+++ b/fpga/usrp3/lib/xge/rtl/verilog/rx_enqueue.v
@@ -0,0 +1,763 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  File name "rx_enqueue.v"                                    ////
+////                                                              ////
+////  This file is part of the "10GE MAC" project                 ////
+////  http://www.opencores.org/cores/xge_mac/                     ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - A. Tanguay (antanguay@opencores.org)                  ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2008 AUTHORS. All rights reserved.             ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+ 
+ 
+`include "defines.v"
+ 
+module rx_enqueue(/*AUTOARG*/
+  // Outputs
+  rxdfifo_wdata, rxdfifo_wstatus, rxdfifo_wen, rxhfifo_ren,
+  rxhfifo_wdata, rxhfifo_wstatus, rxhfifo_wen, local_fault_msg_det,
+  remote_fault_msg_det, status_crc_error_tog,
+  status_fragment_error_tog, status_rxdfifo_ovflow_tog,
+  status_pause_frame_rx_tog,
+  // Inputs
+  clk_xgmii_rx, reset_xgmii_rx_n, xgmii_rxd, xgmii_rxc, rxdfifo_wfull,
+  rxhfifo_rdata, rxhfifo_rstatus, rxhfifo_rempty,
+  rxhfifo_ralmost_empty
+  );
+ 
+`include "CRC32_D64.v"
+`include "CRC32_D8.v"
+`include "utils.v"
+ 
+input         clk_xgmii_rx;
+input         reset_xgmii_rx_n;
+ 
+input  [63:0] xgmii_rxd;
+input  [7:0]  xgmii_rxc;
+ 
+input         rxdfifo_wfull;
+ 
+input  [63:0] rxhfifo_rdata;
+input  [7:0]  rxhfifo_rstatus;
+input         rxhfifo_rempty;
+input         rxhfifo_ralmost_empty;
+ 
+output [63:0] rxdfifo_wdata;
+output [7:0]  rxdfifo_wstatus;
+output        rxdfifo_wen;   
+ 
+output        rxhfifo_ren;
+ 
+output [63:0] rxhfifo_wdata;
+output [7:0]  rxhfifo_wstatus;
+output        rxhfifo_wen;
+ 
+output [1:0]  local_fault_msg_det;
+output [1:0]  remote_fault_msg_det;
+ 
+output        status_crc_error_tog;
+output        status_fragment_error_tog;
+output        status_rxdfifo_ovflow_tog;
+ 
+output        status_pause_frame_rx_tog;
+ 
+ 
+ 
+ 
+/*AUTOREG*/
+// Beginning of automatic regs (for this module's undeclared outputs)
+reg [1:0]               local_fault_msg_det;
+reg [1:0]               remote_fault_msg_det;
+reg [63:0]              rxdfifo_wdata;
+reg                     rxdfifo_wen;
+reg [7:0]               rxdfifo_wstatus;
+reg                     rxhfifo_ren;
+reg [63:0]              rxhfifo_wdata;
+reg                     rxhfifo_wen;
+reg [7:0]               rxhfifo_wstatus;
+reg                     status_crc_error_tog;
+reg                     status_fragment_error_tog;
+reg                     status_pause_frame_rx_tog;
+reg                     status_rxdfifo_ovflow_tog;
+// End of automatics
+ 
+/*AUTOWIRE*/
+ 
+ 
+reg [63:32]   xgmii_rxd_d1;
+reg [7:4]     xgmii_rxc_d1;
+ 
+reg [63:0]    xgxs_rxd_barrel;
+reg [7:0]     xgxs_rxc_barrel;
+ 
+reg [63:0]    xgxs_rxd_barrel_d1;
+reg [7:0]     xgxs_rxc_barrel_d1;
+ 
+reg           barrel_shift;
+ 
+reg [31:0]    crc32_d64;
+reg [31:0]    crc32_d8;
+ 
+reg [3:0]     crc_bytes;
+reg [3:0]     next_crc_bytes;
+ 
+reg [63:0]    crc_shift_data;
+reg           crc_start_8b;
+reg           crc_done;
+reg	      crc_good;
+reg           crc_clear;
+ 
+reg [31:0]    crc_rx;
+reg [31:0]    next_crc_rx;
+ 
+reg [2:0]     curr_state;
+reg [2:0]     next_state;
+ 
+reg [13:0]    curr_byte_cnt;
+reg [13:0]    next_byte_cnt;
+ 
+reg           fragment_error;
+reg           rxd_ovflow_error;
+ 
+reg           coding_error;
+reg           next_coding_error;
+ 
+reg [7:0]     addmask;
+reg [7:0]     datamask;
+ 
+reg           pause_frame;
+reg           next_pause_frame;
+reg           pause_frame_hold;
+ 
+reg           good_pause_frame;
+ 
+reg           drop_data;
+reg           next_drop_data;
+ 
+reg           pkt_pending;
+ 
+reg           rxhfifo_ren_d1;
+ 
+reg           rxhfifo_ralmost_empty_d1;
+ 
+ 
+parameter [2:0]
+             SM_IDLE = 3'd0,
+             SM_RX = 3'd1;
+ 
+always @(posedge clk_xgmii_rx or negedge reset_xgmii_rx_n) begin
+ 
+    if (reset_xgmii_rx_n == 1'b0) begin
+ 
+        xgmii_rxd_d1 <= 32'b0;
+        xgmii_rxc_d1 <= 4'b0;
+ 
+        xgxs_rxd_barrel <= 64'b0;
+        xgxs_rxc_barrel <= 8'b0;
+ 
+        xgxs_rxd_barrel_d1 <= 64'b0;
+        xgxs_rxc_barrel_d1 <= 8'b0;
+ 
+        barrel_shift <= 1'b0;
+ 
+        local_fault_msg_det <= 2'b0;
+        remote_fault_msg_det <= 2'b0;
+ 
+        crc32_d64 <= 32'b0;
+        crc32_d8 <= 32'b0;
+        crc_bytes <= 4'b0;
+ 
+        crc_shift_data <= 64'b0;
+        crc_done <= 1'b0;
+        crc_rx <= 32'b0;
+ 
+        pause_frame_hold <= 1'b0;
+ 
+        status_crc_error_tog <= 1'b0;
+        status_fragment_error_tog <= 1'b0;
+        status_rxdfifo_ovflow_tog <= 1'b0;
+ 
+        status_pause_frame_rx_tog <= 1'b0;
+ 
+    end
+    else begin
+ 
+        //---
+        // Link status RC layer
+        // Look for local/remote messages on lower 4 lanes and upper
+        // 4 lanes. This is a 64-bit interface but look at each 32-bit
+        // independantly.
+ 
+        local_fault_msg_det[1] <= (xgmii_rxd[63:32] ==
+                                   {`LOCAL_FAULT, 8'h0, 8'h0, `SEQUENCE} &&
+                                   xgmii_rxc[7:4] == 4'b0001);
+ 
+        local_fault_msg_det[0] <= (xgmii_rxd[31:0] ==
+                                   {`LOCAL_FAULT, 8'h0, 8'h0, `SEQUENCE} &&
+                                   xgmii_rxc[3:0] == 4'b0001);
+ 
+        remote_fault_msg_det[1] <= (xgmii_rxd[63:32] ==
+                                    {`REMOTE_FAULT, 8'h0, 8'h0, `SEQUENCE} &&
+                                    xgmii_rxc[7:4] == 4'b0001);
+ 
+        remote_fault_msg_det[0] <= (xgmii_rxd[31:0] ==
+                                    {`REMOTE_FAULT, 8'h0, 8'h0, `SEQUENCE} &&
+                                    xgmii_rxc[3:0] == 4'b0001);
+ 
+ 
+        //---
+        // Rotating barrel. This function allow us to always align the start of
+        // a frame with LANE0. If frame starts in LANE4, it will be shifted 4 bytes
+        // to LANE0, thus reducing the amount of logic needed at the next stage.
+ 
+        xgmii_rxd_d1[63:32] <= xgmii_rxd[63:32];
+        xgmii_rxc_d1[7:4] <= xgmii_rxc[7:4];
+ 
+        if (xgmii_rxd[`LANE0] == `START && xgmii_rxc[0]) begin
+ 
+            xgxs_rxd_barrel <= xgmii_rxd;
+            xgxs_rxc_barrel <= xgmii_rxc;
+ 
+            barrel_shift <= 1'b0;
+ 
+        end
+        else if (xgmii_rxd[`LANE4] == `START && xgmii_rxc[4]) begin
+ 
+            xgxs_rxd_barrel <= {xgmii_rxd[31:0], xgmii_rxd_d1[63:32]};
+            xgxs_rxc_barrel <= {xgmii_rxc[3:0], xgmii_rxc_d1[7:4]};
+ 
+            barrel_shift <= 1'b1;
+ 
+        end
+        else if (barrel_shift) begin
+ 
+            xgxs_rxd_barrel <= {xgmii_rxd[31:0], xgmii_rxd_d1[63:32]};
+            xgxs_rxc_barrel <= {xgmii_rxc[3:0], xgmii_rxc_d1[7:4]};
+ 
+        end
+        else begin
+ 
+            xgxs_rxd_barrel <= xgmii_rxd;
+            xgxs_rxc_barrel <= xgmii_rxc;
+ 
+        end
+ 
+        xgxs_rxd_barrel_d1 <= xgxs_rxd_barrel;
+        xgxs_rxc_barrel_d1 <= xgxs_rxc_barrel;
+ 
+ 
+        //---
+        // When final CRC calculation begins we capture info relevant to
+        // current frame CRC claculation continues while next frame is
+        // being received.
+ 
+        if (crc_start_8b) begin
+ 
+            pause_frame_hold <= pause_frame;
+ 
+        end
+ 
+        //---
+        // CRC Checking
+ 
+        crc_rx <= next_crc_rx;
+ 
+        if (crc_clear) begin
+ 
+            // CRC is cleared at the beginning of the frame, calculate
+            // 64-bit at a time otherwise
+ 
+            crc32_d64 <= 32'hffffffff;
+ 
+        end
+        else begin
+ 
+            crc32_d64 <= nextCRC32_D64(reverse_64b(xgxs_rxd_barrel_d1), crc32_d64);
+ 
+        end
+ 
+        if (crc_bytes != 4'b0) begin
+ 
+            // When reaching the end of the frame we switch from 64-bit mode
+            // to 8-bit mode to accomodate odd number of bytes in the frame.
+            // crc_bytes indicated the number of remaining payload byte to
+            // compute CRC on. Calculate and decrement until it reaches 0.
+ 
+            if (crc_bytes == 4'b1) begin
+                crc_done <= 1'b1;
+            end
+ 
+            crc32_d8 <= nextCRC32_D8(reverse_8b(crc_shift_data[7:0]), crc32_d8);
+            crc_shift_data <= {8'h00, crc_shift_data[63:8]};
+            crc_bytes <= crc_bytes - 4'b1;
+ 
+        end
+        else if (crc_bytes == 4'b0) begin
+ 
+            // Per Clause 46. Control code during data must be reported
+            // as a CRC error. Indicated here by coding_error. Corrupt CRC
+            // if coding error is detected.
+ 
+            if (coding_error || next_coding_error) begin
+                crc32_d8 <= ~crc32_d64;
+            end
+            else begin
+                crc32_d8 <= crc32_d64;
+            end
+ 
+            crc_done <= 1'b0;
+ 
+            crc_shift_data <= xgxs_rxd_barrel_d1;
+            crc_bytes <= next_crc_bytes;
+ 
+        end
+ 
+        //---
+        // Error detection
+ 
+        if (crc_done && !crc_good) begin
+            status_crc_error_tog <= ~status_crc_error_tog;
+        end
+ 
+        if (fragment_error) begin
+            status_fragment_error_tog <= ~status_fragment_error_tog;
+        end
+ 
+        if (rxd_ovflow_error) begin
+            status_rxdfifo_ovflow_tog <= ~status_rxdfifo_ovflow_tog;
+        end
+ 
+        //---
+        // Frame receive indication
+ 
+        if (good_pause_frame) begin
+            status_pause_frame_rx_tog <= ~status_pause_frame_rx_tog;
+        end
+ 
+    end
+ 
+end
+ 
+ 
+always @(/*AS*/crc32_d8 or crc_done or crc_rx or pause_frame_hold) begin
+ 
+ 
+    crc_good = 1'b0;
+    good_pause_frame = 1'b0;
+ 
+    if (crc_done) begin
+ 
+        // Check CRC. If this is a pause frame, report it to cpu.
+ 
+        if (crc_rx == ~reverse_32b(crc32_d8)) begin
+            crc_good = 1'b1;
+            good_pause_frame = pause_frame_hold;
+        end
+ 
+    end
+ 
+end
+ 
+always @(posedge clk_xgmii_rx or negedge reset_xgmii_rx_n) begin
+ 
+    if (reset_xgmii_rx_n == 1'b0) begin
+ 
+        curr_state <= SM_IDLE;
+        curr_byte_cnt <= 14'b0;
+        coding_error <= 1'b0;
+        pause_frame <= 1'b0;
+ 
+    end
+    else begin
+ 
+        curr_state <= next_state;
+        curr_byte_cnt <= next_byte_cnt;
+        coding_error <= next_coding_error;
+        pause_frame <= next_pause_frame;
+ 
+    end
+ 
+end
+ 
+ 
+always @(/*AS*/coding_error or crc_rx or curr_byte_cnt or curr_state
+         or pause_frame or xgxs_rxc_barrel or xgxs_rxc_barrel_d1
+         or xgxs_rxd_barrel or xgxs_rxd_barrel_d1) begin
+ 
+    next_state = curr_state;
+ 
+    rxhfifo_wdata = xgxs_rxd_barrel_d1;
+    rxhfifo_wstatus = `RXSTATUS_NONE;
+    rxhfifo_wen = 1'b0;
+ 
+    addmask[0] = !(xgxs_rxd_barrel_d1[`LANE0] == `TERMINATE && xgxs_rxc_barrel_d1[0]);
+    addmask[1] = !(xgxs_rxd_barrel_d1[`LANE1] == `TERMINATE && xgxs_rxc_barrel_d1[1]);
+    addmask[2] = !(xgxs_rxd_barrel_d1[`LANE2] == `TERMINATE && xgxs_rxc_barrel_d1[2]);
+    addmask[3] = !(xgxs_rxd_barrel_d1[`LANE3] == `TERMINATE && xgxs_rxc_barrel_d1[3]);
+    addmask[4] = !(xgxs_rxd_barrel_d1[`LANE4] == `TERMINATE && xgxs_rxc_barrel_d1[4]);
+    addmask[5] = !(xgxs_rxd_barrel_d1[`LANE5] == `TERMINATE && xgxs_rxc_barrel_d1[5]);
+    addmask[6] = !(xgxs_rxd_barrel_d1[`LANE6] == `TERMINATE && xgxs_rxc_barrel_d1[6]);
+    addmask[7] = !(xgxs_rxd_barrel_d1[`LANE7] == `TERMINATE && xgxs_rxc_barrel_d1[7]);
+ 
+    datamask[0] = addmask[0];
+    datamask[1] = &addmask[1:0];
+    datamask[2] = &addmask[2:0];
+    datamask[3] = &addmask[3:0];
+    datamask[4] = &addmask[4:0];
+    datamask[5] = &addmask[5:0];
+    datamask[6] = &addmask[6:0];
+    datamask[7] = &addmask[7:0];
+ 
+    next_crc_bytes = 4'b0;
+    next_crc_rx = crc_rx;
+    crc_start_8b = 1'b0;
+    crc_clear = 1'b0;
+ 
+    next_byte_cnt = curr_byte_cnt;
+ 
+    fragment_error = 1'b0;
+ 
+    next_coding_error = coding_error;
+    next_pause_frame = pause_frame;
+ 
+    case (curr_state)
+ 
+        SM_IDLE:
+          begin
+ 
+              next_byte_cnt = 14'b0;
+              crc_clear = 1'b1;
+              next_coding_error = 1'b0;
+              next_pause_frame = 1'b0;
+ 
+ 
+              // Detect the start of a frame
+ 
+              if (xgxs_rxd_barrel_d1[`LANE0] == `START && xgxs_rxc_barrel_d1[0] &&
+                  xgxs_rxd_barrel_d1[`LANE1] == `PREAMBLE && !xgxs_rxc_barrel_d1[1] &&
+                  xgxs_rxd_barrel_d1[`LANE2] == `PREAMBLE && !xgxs_rxc_barrel_d1[2] &&
+                  xgxs_rxd_barrel_d1[`LANE3] == `PREAMBLE && !xgxs_rxc_barrel_d1[3] &&
+                  xgxs_rxd_barrel_d1[`LANE4] == `PREAMBLE && !xgxs_rxc_barrel_d1[4] &&
+                  xgxs_rxd_barrel_d1[`LANE5] == `PREAMBLE && !xgxs_rxc_barrel_d1[5] &&
+                  xgxs_rxd_barrel_d1[`LANE6] == `PREAMBLE && !xgxs_rxc_barrel_d1[6] &&
+                  xgxs_rxd_barrel_d1[`LANE7] == `SFD && !xgxs_rxc_barrel_d1[7]) begin
+ 
+                  next_state = SM_RX;
+              end
+ 
+          end
+ 
+        SM_RX:
+          begin
+ 
+              // Pause frames are filtered
+ 
+              rxhfifo_wen = !pause_frame;
+ 
+ 
+              if (xgxs_rxd_barrel_d1[`LANE0] == `START && xgxs_rxc_barrel_d1[0] &&
+                  xgxs_rxd_barrel_d1[`LANE7] == `SFD && !xgxs_rxc_barrel_d1[7]) begin
+ 
+                  // Fragment received, if we are still at SOP stage don't store
+                  // the frame. If not, write a fake EOP and flag frame as bad.
+ 
+                  next_byte_cnt = 14'b0;
+                  crc_clear = 1'b1;
+                  next_coding_error = 1'b0;
+ 
+                  fragment_error = 1'b1;
+                  rxhfifo_wstatus[`RXSTATUS_ERR] = 1'b1;
+ 
+                  if (curr_byte_cnt == 14'b0) begin
+                      rxhfifo_wen = 1'b0;
+                  end
+                  else begin
+                      rxhfifo_wstatus[`RXSTATUS_EOP] = 1'b1;
+                  end
+ 
+              end
+              else if (curr_byte_cnt > 14'd9900) begin
+ 
+                  // Frame too long, TERMMINATE must have been corrupted.
+                  // Abort transfer, write a fake EOP, report as fragment.
+ 
+                  fragment_error = 1'b1;
+                  rxhfifo_wstatus[`RXSTATUS_ERR] = 1'b1;
+ 
+                  rxhfifo_wstatus[`RXSTATUS_EOP] = 1'b1;
+                  next_state = SM_IDLE;
+ 
+              end
+              else begin
+ 
+                  // Pause frame receive, these frame will be filtered
+ 
+                  if (curr_byte_cnt == 14'd0 &&
+                      xgxs_rxd_barrel_d1[47:0] == `PAUSE_FRAME) begin
+ 
+                      rxhfifo_wen = 1'b0;
+                      next_pause_frame = 1'b1;
+                  end
+ 
+ 
+                  // Control character during data phase, force CRC error
+ 
+                  if (|(xgxs_rxc_barrel_d1 & datamask)) begin
+ 
+                      next_coding_error = 1'b1;
+                  end
+ 
+ 
+                  // Write SOP to status bits during first byte
+ 
+                  if (curr_byte_cnt == 14'b0) begin
+                      rxhfifo_wstatus[`RXSTATUS_SOP] = 1'b1;
+                  end
+ 
+                  /* verilator lint_off WIDTH */
+                  next_byte_cnt = curr_byte_cnt +
+                                  addmask[0] + addmask[1] + addmask[2] + addmask[3] +
+                                  addmask[4] + addmask[5] + addmask[6] + addmask[7];
+                  /* verilator lint_on WIDTH */
+ 
+ 
+ 
+                  // We will not write to the fifo if all is left
+                  // are four or less bytes of crc. We also strip off the
+                  // crc, which requires looking one cycle ahead
+                  // wstatus: 
+                  //   [2:0] modulus of packet length
+ 
+                  // Look one cycle ahead for TERMINATE in lanes 0 to 4
+ 
+                  if (xgxs_rxd_barrel[`LANE4] == `TERMINATE && xgxs_rxc_barrel[4]) begin
+ 
+                      rxhfifo_wstatus[`RXSTATUS_EOP] = 1'b1;
+                      rxhfifo_wstatus[2:0] = 3'd0;
+ 
+                      crc_start_8b = 1'b1;
+                      next_crc_bytes = 4'd8;
+                      next_crc_rx = xgxs_rxd_barrel[31:0];
+ 
+                      next_state = SM_IDLE;
+ 
+                  end
+ 
+                  if (xgxs_rxd_barrel[`LANE3] == `TERMINATE && xgxs_rxc_barrel[3]) begin
+ 
+                      rxhfifo_wstatus[`RXSTATUS_EOP] = 1'b1;
+                      rxhfifo_wstatus[2:0] = 3'd7;
+ 
+                      crc_start_8b = 1'b1;
+                      next_crc_bytes = 4'd7;
+                      next_crc_rx = {xgxs_rxd_barrel[23:0], xgxs_rxd_barrel_d1[63:56]};
+ 
+                      next_state = SM_IDLE;
+ 
+                  end
+ 
+                  if (xgxs_rxd_barrel[`LANE2] == `TERMINATE && xgxs_rxc_barrel[2]) begin
+ 
+                      rxhfifo_wstatus[`RXSTATUS_EOP] = 1'b1;
+                      rxhfifo_wstatus[2:0] = 3'd6;
+ 
+                      crc_start_8b = 1'b1;
+                      next_crc_bytes = 4'd6;
+                      next_crc_rx = {xgxs_rxd_barrel[15:0], xgxs_rxd_barrel_d1[63:48]};
+ 
+                      next_state = SM_IDLE;
+ 
+                  end
+ 
+                  if (xgxs_rxd_barrel[`LANE1] == `TERMINATE && xgxs_rxc_barrel[1]) begin
+ 
+                      rxhfifo_wstatus[`RXSTATUS_EOP] = 1'b1;
+                      rxhfifo_wstatus[2:0] = 3'd5;
+ 
+                      crc_start_8b = 1'b1;
+                      next_crc_bytes = 4'd5;
+                      next_crc_rx = {xgxs_rxd_barrel[7:0], xgxs_rxd_barrel_d1[63:40]};
+ 
+                      next_state = SM_IDLE;
+ 
+                  end
+ 
+                  if (xgxs_rxd_barrel[`LANE0] == `TERMINATE && xgxs_rxc_barrel[0]) begin
+ 
+                      rxhfifo_wstatus[`RXSTATUS_EOP] = 1'b1;
+                      rxhfifo_wstatus[2:0] = 3'd4;
+ 
+                      crc_start_8b = 1'b1;
+                      next_crc_bytes = 4'd4;
+                      next_crc_rx = xgxs_rxd_barrel_d1[63:32];
+ 
+                      next_state = SM_IDLE;
+ 
+                  end
+ 
+                  // Look at current cycle for TERMINATE in lanes 5 to 7
+ 
+                  if (xgxs_rxd_barrel_d1[`LANE7] == `TERMINATE &&
+                      xgxs_rxc_barrel_d1[7]) begin
+ 
+                      rxhfifo_wstatus[`RXSTATUS_EOP] = 1'b1;
+                      rxhfifo_wstatus[2:0] = 3'd3;
+ 
+                      crc_start_8b = 1'b1;
+                      next_crc_bytes = 4'd3;
+                      next_crc_rx = xgxs_rxd_barrel_d1[55:24];
+ 
+                      next_state = SM_IDLE;
+ 
+                  end
+ 
+                  if (xgxs_rxd_barrel_d1[`LANE6] == `TERMINATE &&
+                      xgxs_rxc_barrel_d1[6]) begin
+ 
+                      rxhfifo_wstatus[`RXSTATUS_EOP] = 1'b1;
+                      rxhfifo_wstatus[2:0] = 3'd2;
+ 
+                      crc_start_8b = 1'b1;
+                      next_crc_bytes = 4'd2;
+                      next_crc_rx = xgxs_rxd_barrel_d1[47:16];
+ 
+                      next_state = SM_IDLE;
+ 
+                  end
+ 
+                  if (xgxs_rxd_barrel_d1[`LANE5] == `TERMINATE &&
+                      xgxs_rxc_barrel_d1[5]) begin
+ 
+                      rxhfifo_wstatus[`RXSTATUS_EOP] = 1'b1;
+                      rxhfifo_wstatus[2:0] = 3'd1;
+ 
+                      crc_start_8b = 1'b1;
+                      next_crc_bytes = 4'd1;
+                      next_crc_rx = xgxs_rxd_barrel_d1[39:8];
+ 
+                      next_state = SM_IDLE;
+ 
+                  end
+              end
+          end
+ 
+        default:
+          begin
+              next_state = SM_IDLE;
+          end
+ 
+    endcase
+ 
+end
+ 
+ 
+always @(posedge clk_xgmii_rx or negedge reset_xgmii_rx_n) begin
+ 
+    if (reset_xgmii_rx_n == 1'b0) begin
+ 
+        rxhfifo_ralmost_empty_d1 <= 1'b1;
+ 
+        drop_data <= 1'b0;
+ 
+        pkt_pending <= 1'b0;
+ 
+        rxhfifo_ren_d1 <= 1'b0;
+ 
+    end
+    else begin
+ 
+        rxhfifo_ralmost_empty_d1 <= rxhfifo_ralmost_empty;
+ 
+        drop_data <= next_drop_data;
+ 
+        pkt_pending <= rxhfifo_ren;
+ 
+        rxhfifo_ren_d1 <= rxhfifo_ren;
+ 
+    end
+ 
+end
+ 
+always @(/*AS*/crc_done or crc_good or drop_data or pkt_pending
+         or rxdfifo_wfull or rxhfifo_ralmost_empty_d1 or rxhfifo_rdata
+         or rxhfifo_ren_d1 or rxhfifo_rstatus) begin
+ 
+    rxd_ovflow_error = 1'b0;
+ 
+    rxdfifo_wdata = rxhfifo_rdata;
+    rxdfifo_wstatus = rxhfifo_rstatus;
+ 
+    next_drop_data = drop_data;
+ 
+ 
+    // There must be at least 8 words in holding FIFO before we start reading.
+    // This provides enough time for CRC calculation.
+ 
+    rxhfifo_ren = !rxhfifo_ralmost_empty_d1 ||
+                  (pkt_pending && !rxhfifo_rstatus[`RXSTATUS_EOP]);
+ 
+ 
+    if (rxhfifo_ren_d1 && rxhfifo_rstatus[`RXSTATUS_SOP]) begin
+ 
+        // Reset drop flag on SOP
+ 
+        next_drop_data = 1'b0;
+ 
+    end
+ 
+    if (rxhfifo_ren_d1 && rxdfifo_wfull && !next_drop_data) begin
+ 
+        // FIFO overflow, abort transfer. The rest of the frame
+        // will be dropped. Since we can't put an EOP indication
+        // in a fifo already full, there will be no EOP and receive
+        // side will need to sync on next SOP.
+ 
+        rxd_ovflow_error = 1'b1;
+        next_drop_data = 1'b1;
+ 
+    end
+ 
+ 
+    rxdfifo_wen = rxhfifo_ren_d1 && !next_drop_data;
+ 
+ 
+ 
+    if (crc_done && !crc_good) begin
+ 
+        // Flag packet with error when CRC error is detected
+ 
+        rxdfifo_wstatus[`RXSTATUS_ERR] = 1'b1;
+ 
+    end
+ 
+end
+ 
+endmodule
+ 
+ 
\ No newline at end of file
diff --git a/fpga/usrp3/lib/xge/rtl/verilog/rx_hold_fifo.v b/fpga/usrp3/lib/xge/rtl/verilog/rx_hold_fifo.v
new file mode 100644
index 000000000..14c4abc65
--- /dev/null
+++ b/fpga/usrp3/lib/xge/rtl/verilog/rx_hold_fifo.v
@@ -0,0 +1,91 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  File name "rx_hold_fifo.v"                                  ////
+////                                                              ////
+////  This file is part of the "10GE MAC" project                 ////
+////  http://www.opencores.org/cores/xge_mac/                     ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - A. Tanguay (antanguay@opencores.org)                  ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2008 AUTHORS. All rights reserved.             ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+ 
+ 
+`include "defines.v"
+ 
+module rx_hold_fifo(/*AUTOARG*/
+  // Outputs
+  rxhfifo_rdata, rxhfifo_rstatus, rxhfifo_rempty,
+  rxhfifo_ralmost_empty,
+  // Inputs
+  clk_xgmii_rx, reset_xgmii_rx_n, rxhfifo_wdata, rxhfifo_wstatus,
+  rxhfifo_wen, rxhfifo_ren
+  );
+ 
+input         clk_xgmii_rx;
+input         reset_xgmii_rx_n;
+ 
+input [63:0]  rxhfifo_wdata;
+input [7:0]   rxhfifo_wstatus;
+input         rxhfifo_wen;
+ 
+input         rxhfifo_ren;
+ 
+output [63:0] rxhfifo_rdata;
+output [7:0]  rxhfifo_rstatus;
+output        rxhfifo_rempty;
+output        rxhfifo_ralmost_empty;
+ 
+generic_fifo #(
+  .DWIDTH (72),
+  .AWIDTH (`RX_HOLD_FIFO_AWIDTH),
+  .REGISTER_READ (1),
+  .EARLY_READ (1),
+  .CLOCK_CROSSING (0),
+  .ALMOST_EMPTY_THRESH (7),
+  .MEM_TYPE (`MEM_AUTO_XILINX)
+)
+fifo0(
+    .wclk (clk_xgmii_rx),
+    .wrst_n (reset_xgmii_rx_n),
+    .wen (rxhfifo_wen),
+    .wdata ({rxhfifo_wstatus, rxhfifo_wdata}),
+    .wfull (),
+    .walmost_full (),
+ 
+    .rclk (clk_xgmii_rx),
+    .rrst_n (reset_xgmii_rx_n),
+    .ren (rxhfifo_ren),
+    .rdata ({rxhfifo_rstatus, rxhfifo_rdata}),
+    .rempty (rxhfifo_rempty),
+    .ralmost_empty (rxhfifo_ralmost_empty)
+);
+ 
+ 
+endmodule
+ 
diff --git a/fpga/usrp3/lib/xge/rtl/verilog/sync_clk_core.v b/fpga/usrp3/lib/xge/rtl/verilog/sync_clk_core.v
new file mode 100644
index 000000000..30e9bd5c3
--- /dev/null
+++ b/fpga/usrp3/lib/xge/rtl/verilog/sync_clk_core.v
@@ -0,0 +1,73 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  File name "sync_clk_core.v"                                 ////
+////                                                              ////
+////  This file is part of the "10GE MAC" project                 ////
+////  http://www.opencores.org/cores/xge_mac/                     ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - A. Tanguay (antanguay@opencores.org)                  ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2008 AUTHORS. All rights reserved.             ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+ 
+ 
+`include "defines.v"
+ 
+module sync_clk_core(/*AUTOARG*/
+  // Inputs
+  clk_xgmii_tx, reset_xgmii_tx_n
+  );
+ 
+input         clk_xgmii_tx;
+input         reset_xgmii_tx_n;
+ 
+//input         ctrl_tx_disable_padding;
+ 
+//output        ctrl_tx_disable_padding_ccr;
+ 
+ 
+/*AUTOREG*/
+ 
+/*AUTOWIRE*/
+ 
+//wire  [0:0]             sig_out;
+ 
+//assign {ctrl_tx_disable_padding_ccr} = sig_out;
+ 
+//meta_sync #(.DWIDTH (1)) meta_sync0 (
+//                      // Outputs
+//                      .out              (sig_out),
+//                      // Inputs
+//                      .clk              (clk_xgmii_tx),
+//                      .reset_n          (reset_xgmii_tx_n),
+//                      .in               ({
+//                                          ctrl_tx_disable_padding
+//                                         }));
+ 
+endmodule
+ 
diff --git a/fpga/usrp3/lib/xge/rtl/verilog/sync_clk_wb.v b/fpga/usrp3/lib/xge/rtl/verilog/sync_clk_wb.v
new file mode 100644
index 000000000..a5c3f6230
--- /dev/null
+++ b/fpga/usrp3/lib/xge/rtl/verilog/sync_clk_wb.v
@@ -0,0 +1,135 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  File name "sync_clk_wb.v"                                   ////
+////                                                              ////
+////  This file is part of the "10GE MAC" project                 ////
+////  http://www.opencores.org/cores/xge_mac/                     ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - A. Tanguay (antanguay@opencores.org)                  ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2008 AUTHORS. All rights reserved.             ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+ 
+ 
+`include "defines.v"
+ 
+module sync_clk_wb(/*AUTOARG*/
+  // Outputs
+  status_crc_error, status_fragment_error, status_txdfifo_ovflow,
+  status_txdfifo_udflow, status_rxdfifo_ovflow, status_rxdfifo_udflow,
+  status_pause_frame_rx, status_local_fault, status_remote_fault,
+  // Inputs
+  wb_clk_i, wb_rst_i, status_crc_error_tog, status_fragment_error_tog,
+  status_txdfifo_ovflow_tog, status_txdfifo_udflow_tog,
+  status_rxdfifo_ovflow_tog, status_rxdfifo_udflow_tog,
+  status_pause_frame_rx_tog, status_local_fault_crx,
+  status_remote_fault_crx
+  );
+ 
+input         wb_clk_i;
+input         wb_rst_i;
+ 
+input         status_crc_error_tog;
+input         status_fragment_error_tog;
+ 
+input         status_txdfifo_ovflow_tog;
+ 
+input         status_txdfifo_udflow_tog;
+ 
+input         status_rxdfifo_ovflow_tog;
+ 
+input         status_rxdfifo_udflow_tog;
+ 
+input         status_pause_frame_rx_tog;
+ 
+input         status_local_fault_crx;
+input         status_remote_fault_crx;
+ 
+output        status_crc_error;
+output        status_fragment_error;
+ 
+output        status_txdfifo_ovflow;
+ 
+output        status_txdfifo_udflow;
+ 
+output        status_rxdfifo_ovflow;
+ 
+output        status_rxdfifo_udflow;
+ 
+output        status_pause_frame_rx;
+ 
+output        status_local_fault;
+output        status_remote_fault;
+ 
+/*AUTOREG*/
+ 
+/*AUTOWIRE*/
+ 
+wire  [6:0]             sig_out1;
+wire  [1:0]             sig_out2;
+ 
+assign status_crc_error = sig_out1[6];
+assign status_fragment_error = sig_out1[5];
+assign status_txdfifo_ovflow = sig_out1[4];
+assign status_txdfifo_udflow = sig_out1[3];
+assign status_rxdfifo_ovflow = sig_out1[2];
+assign status_rxdfifo_udflow = sig_out1[1];
+assign status_pause_frame_rx = sig_out1[0];
+ 
+assign status_local_fault = sig_out2[1];
+assign status_remote_fault = sig_out2[0];
+ 
+meta_sync #(.DWIDTH (7), .EDGE_DETECT (1)) meta_sync0 (
+                      // Outputs
+                      .out              (sig_out1),
+                      // Inputs
+                      .clk              (wb_clk_i),
+                      .reset_n          (~wb_rst_i),
+                      .in               ({
+                                          status_crc_error_tog,
+                                          status_fragment_error_tog,
+                                          status_txdfifo_ovflow_tog,
+                                          status_txdfifo_udflow_tog,
+                                          status_rxdfifo_ovflow_tog,
+                                          status_rxdfifo_udflow_tog,
+                                          status_pause_frame_rx_tog
+                                         }));
+ 
+meta_sync #(.DWIDTH (2), .EDGE_DETECT (0)) meta_sync1 (
+                      // Outputs
+                      .out              (sig_out2),
+                      // Inputs
+                      .clk              (wb_clk_i),
+                      .reset_n          (~wb_rst_i),
+                      .in               ({
+                                          status_local_fault_crx,
+                                          status_remote_fault_crx
+                                         }));
+ 
+endmodule
+ 
\ No newline at end of file
diff --git a/fpga/usrp3/lib/xge/rtl/verilog/sync_clk_xgmii_tx.v b/fpga/usrp3/lib/xge/rtl/verilog/sync_clk_xgmii_tx.v
new file mode 100644
index 000000000..34527b0bc
--- /dev/null
+++ b/fpga/usrp3/lib/xge/rtl/verilog/sync_clk_xgmii_tx.v
@@ -0,0 +1,85 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  File name "sync_clk_xgmii.v"                                ////
+////                                                              ////
+////  This file is part of the "10GE MAC" project                 ////
+////  http://www.opencores.org/cores/xge_mac/                     ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - A. Tanguay (antanguay@opencores.org)                  ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2008 AUTHORS. All rights reserved.             ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+ 
+ 
+`include "defines.v"
+ 
+module sync_clk_xgmii_tx(/*AUTOARG*/
+  // Outputs
+  ctrl_tx_enable_ctx, status_local_fault_ctx, status_remote_fault_ctx,
+  // Inputs
+  clk_xgmii_tx, reset_xgmii_tx_n, ctrl_tx_enable,
+  status_local_fault_crx, status_remote_fault_crx
+  );
+ 
+input         clk_xgmii_tx;
+input         reset_xgmii_tx_n;
+ 
+input         ctrl_tx_enable;
+ 
+input         status_local_fault_crx;
+input         status_remote_fault_crx;
+ 
+output        ctrl_tx_enable_ctx;
+ 
+output        status_local_fault_ctx;
+output        status_remote_fault_ctx;
+ 
+/*AUTOREG*/
+ 
+/*AUTOWIRE*/
+ 
+wire  [2:0]             sig_out;
+ 
+assign ctrl_tx_enable_ctx = sig_out[2];
+assign status_local_fault_ctx = sig_out[1];
+assign status_remote_fault_ctx = sig_out[0];
+ 
+meta_sync #(.DWIDTH (3)) meta_sync0 (
+                      // Outputs
+                      .out              (sig_out),
+                      // Inputs
+                      .clk              (clk_xgmii_tx),
+                      .reset_n          (reset_xgmii_tx_n),
+                      .in               ({
+                                          ctrl_tx_enable,
+                                          status_local_fault_crx,
+                                          status_remote_fault_crx
+                                         }));
+ 
+endmodule
+ 
\ No newline at end of file
diff --git a/fpga/usrp3/lib/xge/rtl/verilog/timescale.v b/fpga/usrp3/lib/xge/rtl/verilog/timescale.v
new file mode 100644
index 000000000..64502185f
--- /dev/null
+++ b/fpga/usrp3/lib/xge/rtl/verilog/timescale.v
@@ -0,0 +1 @@
+`timescale 1ps / 1ps
diff --git a/fpga/usrp3/lib/xge/rtl/verilog/tx_checker.v b/fpga/usrp3/lib/xge/rtl/verilog/tx_checker.v
new file mode 100644
index 000000000..002746186
--- /dev/null
+++ b/fpga/usrp3/lib/xge/rtl/verilog/tx_checker.v
@@ -0,0 +1,143 @@
+//
+// Synthesizable Tx checker for 10G Ethernet MAC.
+// Generates deterministic packets that can be looped back and
+// checked for correctness
+//
+`define IDLE 0
+`define MAC1 1
+`define MAC2 2
+`define PAYLOAD1 3
+`define WAIT 4
+`define DONE 5
+
+
+module tx_checker
+  (
+   input clk156,
+   input rst,
+   input enable,
+   output reg done,
+   //
+   output reg pkt_tx_val,
+   output reg pkt_tx_sop,
+   output reg pkt_tx_eop,
+   output reg [2:0] pkt_tx_mod,
+   output reg [63:0] pkt_tx_data
+   );
+   
+   reg [10:0] 	 payload;
+   reg [10:0] 	 count;
+   reg [7:0] 	 state;
+   reg [9:0] 	 delay;
+   
+   
+   
+
+
+always @(posedge clk156)
+  if (rst)
+    begin
+       state <= `IDLE;
+       count <= 0;
+       payload <= 45; // 1 less than ethernet minimum payload size.\
+       done <= 0;
+       delay <= 0;
+       pkt_tx_val <= 0;
+       pkt_tx_sop <= 0;
+       pkt_tx_eop <= 0;
+       pkt_tx_data <= 0;
+       pkt_tx_mod <= 0;
+    end
+  else 
+    begin
+       state <= state;
+       pkt_tx_val <= 0;
+       pkt_tx_sop <= 0;
+       pkt_tx_eop <= 0;
+       pkt_tx_data <= 0;
+       pkt_tx_mod <= 0;
+       payload <= payload;
+       count <= count;
+       done <= 0;
+       delay <= delay;
+       
+       
+  
+       case(state)
+	 // Wait in IDLE state until enabled.
+	 // As we leave the idle state increment the payload count
+	 // so that we have a test pattern that changes each iteration.
+	 `IDLE: begin
+	    if (enable)
+	      begin
+		 if (payload == 1500)
+		   state <= `DONE;
+		 else
+		   begin
+		      payload <= payload + 1; // Might need to tweak this later..
+		      state <= `MAC1;
+		   end
+	      end
+	 end
+	 // Assert SOP (Start of Packet) for 1 cycle.
+	 // Assert VAL (Tx Valid) for duration of packet.
+	 // Put first 8 octets out, including
+	 // DST MAC addr and first 2 bytes of SRC MAC.
+	 `MAC1: begin
+	    pkt_tx_val <= 1;
+	    pkt_tx_sop <= 1;
+	    pkt_tx_data[63:16] <= 48'h0001020304; // DST MAC
+	    pkt_tx_data[15:0] <= 16'h0000; // SRC MAC msb's
+	    pkt_tx_mod <= 3'h0; // All octects valid
+	    state <= `MAC2;
+	 end
+	 // SOP now deasserted for rest of packet.
+	 // VAL remains asserted.
+	 // Tx rest of SRC MAC and ether type then first two data octets.
+	 `MAC2: begin
+	    pkt_tx_val <= 1;
+	    pkt_tx_data[63:32] <= 32'h05060708; // SRC MAC lsb's
+	    pkt_tx_data[31:16] <= 16'h88b5;     // Ethertype
+	    pkt_tx_data[15:0] <= 16'hBEEF;      // First 2 bytes of payload.
+	    pkt_tx_mod <= 3'h0; // All octects valid
+	    count <= payload - 2; // Preload counter for this packet
+	    state <= `PAYLOAD1;
+	 end
+	 // Iterate in this state until end of packet.
+	 // The first clock cycle in this state, SRC MAC and ETHERTYPE are being Tx'ed due to pipelining
+	 `PAYLOAD1: begin
+	    pkt_tx_val <= 1;
+	    pkt_tx_data <= {8{count[10:3]}}; // Data pattern is 64bit word count value.
+	    count <= count - 8;
+	    if ((count[10:3] == 0) || (count[10:0] == 8)) // down to 8 or less octects to Tx.
+	      begin
+		 pkt_tx_mod <= count[2:0];
+		 pkt_tx_eop <= 1;
+		 state <= `WAIT;
+		 delay <= 20; // 20 cycle delay in END state before Tx next packet
+	      end
+	 end // case: `PAYLOAD1
+	 // Because of pipelining EOP is actually asserted in this state
+	 // but we are already commited to the end of packet so no decisions need to be made.
+	 // Make signals idle ready for next state after.
+	 // Delay start of next packet to rate control test.
+	 `WAIT:begin
+	    delay <= delay - 1;
+	    if (delay == 0)
+	      state <= `IDLE;	    
+	 end
+	 // Have now transmitted one packet of every legal size (no jumbo frames)
+	 // Stay in this state asserting done flag until reset.
+	 `DONE:begin 	   
+	    state <= `DONE;
+	    done <= 1;
+	 end
+	 
+       endcase // case(state)
+      
+    end	    
+	    
+endmodule // tx_checker
+
+   
+   
\ No newline at end of file
diff --git a/fpga/usrp3/lib/xge/rtl/verilog/tx_data_fifo.v b/fpga/usrp3/lib/xge/rtl/verilog/tx_data_fifo.v
new file mode 100644
index 000000000..1aa9f952c
--- /dev/null
+++ b/fpga/usrp3/lib/xge/rtl/verilog/tx_data_fifo.v
@@ -0,0 +1,96 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  File name "tx_data_fifo.v"                                  ////
+////                                                              ////
+////  This file is part of the "10GE MAC" project                 ////
+////  http://www.opencores.org/cores/xge_mac/                     ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - A. Tanguay (antanguay@opencores.org)                  ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2008 AUTHORS. All rights reserved.             ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+ 
+ 
+`include "defines.v"
+ 
+module tx_data_fifo(/*AUTOARG*/
+  // Outputs
+  txdfifo_wfull, txdfifo_walmost_full, txdfifo_rdata, txdfifo_rstatus,
+  txdfifo_rempty, txdfifo_ralmost_empty,
+  // Inputs
+  clk_xgmii_tx, clk_156m25, reset_xgmii_tx_n, reset_156m25_n,
+  txdfifo_wdata, txdfifo_wstatus, txdfifo_wen, txdfifo_ren
+  );
+ 
+input         clk_xgmii_tx;
+input         clk_156m25;
+input         reset_xgmii_tx_n;
+input         reset_156m25_n;
+ 
+input [63:0]  txdfifo_wdata;
+input [7:0]   txdfifo_wstatus;
+input         txdfifo_wen;
+ 
+input         txdfifo_ren;
+ 
+output        txdfifo_wfull;
+output        txdfifo_walmost_full;
+ 
+output [63:0] txdfifo_rdata;
+output [7:0]  txdfifo_rstatus;
+output        txdfifo_rempty;
+output        txdfifo_ralmost_empty;
+ 
+generic_fifo #(
+  .DWIDTH (72),
+  .AWIDTH (`TX_DATA_FIFO_AWIDTH),
+  .REGISTER_READ (1),
+  .EARLY_READ (1),
+  .CLOCK_CROSSING (1),
+  .ALMOST_EMPTY_THRESH (7),
+  .ALMOST_FULL_THRESH (12),
+  .MEM_TYPE (`MEM_AUTO_XILINX)
+)
+fifo0(
+    .wclk (clk_156m25),
+    .wrst_n (reset_156m25_n),
+    .wen (txdfifo_wen),
+    .wdata ({txdfifo_wstatus, txdfifo_wdata}),
+    .wfull (txdfifo_wfull),
+    .walmost_full (txdfifo_walmost_full),
+ 
+    .rclk (clk_xgmii_tx),
+    .rrst_n (reset_xgmii_tx_n),
+    .ren (txdfifo_ren),
+    .rdata ({txdfifo_rstatus, txdfifo_rdata}),
+    .rempty (txdfifo_rempty),
+    .ralmost_empty (txdfifo_ralmost_empty)
+);
+ 
+endmodule
+ 
diff --git a/fpga/usrp3/lib/xge/rtl/verilog/tx_dequeue.v b/fpga/usrp3/lib/xge/rtl/verilog/tx_dequeue.v
new file mode 100644
index 000000000..8444514ee
--- /dev/null
+++ b/fpga/usrp3/lib/xge/rtl/verilog/tx_dequeue.v
@@ -0,0 +1,938 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  File name "tx_dequeue.v"                                    ////
+////                                                              ////
+////  This file is part of the "10GE MAC" project                 ////
+////  http://www.opencores.org/cores/xge_mac/                     ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - A. Tanguay (antanguay@opencores.org)                  ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2008 AUTHORS. All rights reserved.             ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+ 
+ 
+`include "defines.v"
+ 
+module tx_dequeue(/*AUTOARG*/
+  // Outputs
+  txdfifo_ren, txhfifo_ren, txhfifo_wdata, txhfifo_wstatus,
+  txhfifo_wen, xgmii_txd, xgmii_txc, status_txdfifo_udflow_tog,
+  // Inputs
+  clk_xgmii_tx, reset_xgmii_tx_n, ctrl_tx_enable_ctx,
+  status_local_fault_ctx, status_remote_fault_ctx, txdfifo_rdata,
+  txdfifo_rstatus, txdfifo_rempty, txdfifo_ralmost_empty,
+  txhfifo_rdata, txhfifo_rstatus, txhfifo_rempty,
+  txhfifo_ralmost_empty, txhfifo_wfull, txhfifo_walmost_full
+  );
+`include "CRC32_D64.v"
+`include "CRC32_D8.v"
+`include "utils.v"
+ 
+input         clk_xgmii_tx;
+input         reset_xgmii_tx_n;
+ 
+input         ctrl_tx_enable_ctx;
+ 
+input         status_local_fault_ctx;
+input         status_remote_fault_ctx;
+ 
+input  [63:0] txdfifo_rdata;
+input  [7:0]  txdfifo_rstatus;
+input         txdfifo_rempty;
+input         txdfifo_ralmost_empty;
+ 
+input  [63:0] txhfifo_rdata;
+input  [7:0]  txhfifo_rstatus;
+input         txhfifo_rempty;
+input         txhfifo_ralmost_empty;
+ 
+input         txhfifo_wfull;
+input         txhfifo_walmost_full;
+ 
+output        txdfifo_ren;
+ 
+output        txhfifo_ren;
+ 
+output [63:0] txhfifo_wdata;
+output [7:0]  txhfifo_wstatus;
+output        txhfifo_wen;   
+ 
+output [63:0] xgmii_txd;
+output [7:0]  xgmii_txc;
+ 
+output        status_txdfifo_udflow_tog;
+ 
+ 
+ 
+ 
+/*AUTOREG*/
+// Beginning of automatic regs (for this module's undeclared outputs)
+reg                     status_txdfifo_udflow_tog;
+reg                     txdfifo_ren;
+reg                     txhfifo_ren;
+reg [63:0]              txhfifo_wdata;
+reg                     txhfifo_wen;
+reg [7:0]               txhfifo_wstatus;
+reg [7:0]               xgmii_txc;
+reg [63:0]              xgmii_txd;
+// End of automatics
+ 
+/*AUTOWIRE*/
+ 
+ 
+reg   [63:0]    xgxs_txd;
+reg   [7:0]     xgxs_txc;
+ 
+reg   [63:0]    next_xgxs_txd;
+reg   [7:0]     next_xgxs_txc;
+ 
+reg   [2:0]     curr_state_enc;
+reg   [2:0]     next_state_enc;
+ 
+reg   [0:0]     curr_state_pad;
+reg   [0:0]     next_state_pad;
+ 
+reg             start_on_lane0;
+reg             next_start_on_lane0;
+ 
+reg   [2:0]     ifg_deficit;
+reg   [2:0]     next_ifg_deficit;
+ 
+reg             ifg_4b_add;
+reg             next_ifg_4b_add;
+ 
+reg             ifg_8b_add;
+reg             next_ifg_8b_add;
+ 
+reg             ifg_8b2_add;
+reg             next_ifg_8b2_add;
+ 
+reg   [7:0]     eop;
+reg   [7:0]     next_eop;
+ 
+reg   [63:32]   xgxs_txd_barrel;
+reg   [7:4]     xgxs_txc_barrel;
+ 
+reg   [63:0]    txhfifo_rdata_d1;
+ 
+reg   [13:0]    byte_cnt;
+ 
+reg   [31:0]    crc32_d64;
+reg   [31:0]    crc32_d8;
+reg   [31:0]    crc32_tx;
+ 
+reg   [63:0]    shift_crc_data;
+reg   [3:0]     shift_crc_eop;
+reg   [3:0]     shift_crc_cnt;
+ 
+reg   [31:0]    crc_data;
+ 
+reg             frame_available;
+reg             next_frame_available;
+ 
+reg   [63:0]    next_txhfifo_wdata;
+reg   [7:0]     next_txhfifo_wstatus;
+reg             next_txhfifo_wen;   
+ 
+reg             txdfifo_ren_d1;
+ 
+parameter [2:0]
+             SM_IDLE      = 3'd0,
+             SM_PREAMBLE  = 3'd1,
+             SM_TX        = 3'd2,
+             SM_EOP       = 3'd3,
+             SM_TERM      = 3'd4,
+             SM_TERM_FAIL = 3'd5,
+             SM_IFG       = 3'd6;
+ 
+parameter [0:0]
+             SM_PAD_EQ    = 1'd0,
+             SM_PAD_PAD   = 1'd1;
+ 
+ 
+//---
+// RC layer
+ 
+always @(posedge clk_xgmii_tx or negedge reset_xgmii_tx_n) begin
+ 
+    if (reset_xgmii_tx_n == 1'b0) begin
+ 
+        xgmii_txd <= {8{`IDLE}};
+        xgmii_txc <= 8'hff;
+ 
+    end
+    else begin
+ 
+ 
+        //---
+        // RC Layer, insert local or remote fault messages based on status
+        // of fault state-machine
+ 
+        if (status_local_fault_ctx) begin
+ 
+            // If local fault detected, send remote fault message to
+            // link partner
+ 
+            xgmii_txd <= {`REMOTE_FAULT, 8'h0, 8'h0, `SEQUENCE,
+                          `REMOTE_FAULT, 8'h0, 8'h0, `SEQUENCE};
+            xgmii_txc <= {4'b0001, 4'b0001};
+        end
+        else if (status_remote_fault_ctx) begin
+ 
+            // If remote fault detected, inhibit transmission and send
+            // idle codes
+ 
+            xgmii_txd <= {8{`IDLE}};
+            xgmii_txc <= 8'hff;
+        end
+        else begin
+            xgmii_txd <= xgxs_txd;
+            xgmii_txc <= xgxs_txc;
+        end
+    end
+ 
+end
+ 
+ 
+always @(posedge clk_xgmii_tx or negedge reset_xgmii_tx_n) begin
+ 
+    if (reset_xgmii_tx_n == 1'b0) begin
+ 
+        curr_state_enc <= SM_IDLE;
+ 
+        start_on_lane0 <= 1'b1;
+        ifg_deficit <= 3'b0;
+        ifg_4b_add <= 1'b0;
+        ifg_8b_add <= 1'b0;
+        ifg_8b2_add <= 1'b0;
+ 
+        eop <= 8'b0;
+ 
+        txhfifo_rdata_d1 <= 64'b0;
+ 
+        xgxs_txd_barrel <= {4{`IDLE}};
+        xgxs_txc_barrel <= 4'hf;
+ 
+        frame_available <= 1'b0;
+ 
+        xgxs_txd <= {8{`IDLE}};
+        xgxs_txc <= 8'hff;
+ 
+        status_txdfifo_udflow_tog <= 1'b0;
+ 
+    end
+    else begin
+ 
+        curr_state_enc <= next_state_enc;
+ 
+        start_on_lane0 <= next_start_on_lane0;
+        ifg_deficit <= next_ifg_deficit;
+        ifg_4b_add <= next_ifg_4b_add;
+        ifg_8b_add <= next_ifg_8b_add;
+        ifg_8b2_add <= next_ifg_8b2_add;
+ 
+        eop <= next_eop;
+ 
+        txhfifo_rdata_d1 <= txhfifo_rdata;
+ 
+        xgxs_txd_barrel <= next_xgxs_txd[63:32];
+        xgxs_txc_barrel <= next_xgxs_txc[7:4];
+ 
+        frame_available <= next_frame_available;
+ 
+        //---
+        // Barrel shifter. Previous stage always align packet with LANE0.
+        // This stage allow us to shift packet to align with LANE4 if needed
+        // for correct inter frame gap (IFG).
+ 
+        if (next_start_on_lane0) begin
+ 
+            xgxs_txd <= next_xgxs_txd;
+            xgxs_txc <= next_xgxs_txc;
+ 
+        end
+        else begin
+ 
+            xgxs_txd <= {next_xgxs_txd[31:0], xgxs_txd_barrel};
+            xgxs_txc <= {next_xgxs_txc[3:0], xgxs_txc_barrel};
+ 
+        end
+ 
+        //---
+        // FIFO errors, used to generate interrupts.
+ 
+        if (txdfifo_ren && txdfifo_rempty) begin
+            status_txdfifo_udflow_tog <= ~status_txdfifo_udflow_tog;
+        end
+ 
+    end
+ 
+end
+ 
+always @(/*AS*/crc32_tx or ctrl_tx_enable_ctx or curr_state_enc or eop
+         or frame_available or ifg_4b_add or ifg_8b2_add or ifg_8b_add
+         or ifg_deficit or start_on_lane0 or status_local_fault_ctx
+         or txhfifo_ralmost_empty or txhfifo_rdata_d1
+         or txhfifo_rempty or txhfifo_rstatus) begin
+ 
+    next_state_enc = curr_state_enc;
+ 
+    next_start_on_lane0 = start_on_lane0;
+    next_ifg_deficit = ifg_deficit;
+    next_ifg_4b_add = ifg_4b_add;
+    next_ifg_8b_add = ifg_8b_add;
+    next_ifg_8b2_add = ifg_8b2_add;
+ 
+    next_eop = eop;
+ 
+    next_xgxs_txd = {8{`IDLE}};
+    next_xgxs_txc = 8'hff;
+ 
+    txhfifo_ren = 1'b0;
+ 
+    next_frame_available = frame_available;
+ 
+    case (curr_state_enc)
+ 
+        SM_IDLE:
+          begin
+ 
+              // Wait for frame to be available. There should be a least N bytes in the
+              // data fifo or a crc in the control fifo. The N bytes in the data fifo
+              // give time to the enqueue engine to calculate crc and write it to the
+              // control fifo. If crc is already in control fifo we can start transmitting
+              // with no concern. Transmission is inhibited if local or remote faults
+              // are detected.
+ 
+              if (ctrl_tx_enable_ctx && frame_available &&
+                  !status_local_fault_ctx && !status_local_fault_ctx) begin
+ 
+                  txhfifo_ren = 1'b1;
+                  next_state_enc = SM_PREAMBLE;
+ 
+              end
+              else begin
+ 
+                  next_frame_available = !txhfifo_ralmost_empty;
+                  next_ifg_4b_add = 1'b0;
+ 
+              end
+ 
+          end
+ 
+        SM_PREAMBLE:
+         begin
+ 
+             // On reading SOP from fifo, send SFD and preamble characters
+ 
+             if (txhfifo_rstatus[`TXSTATUS_SOP]) begin
+ 
+                 next_xgxs_txd = {`SFD, {6{`PREAMBLE}}, `START};
+                 next_xgxs_txc = 8'h01;
+ 
+                 txhfifo_ren = 1'b1;
+ 
+                 next_state_enc = SM_TX;
+ 
+             end
+             else begin
+ 
+                 next_frame_available = 1'b0;
+                 next_state_enc = SM_IDLE;
+ 
+             end
+ 
+ 
+             // Depending on deficit idle count calculations, add 4 bytes
+             // or IFG or not. This will determine on which lane start the
+             // next frame.
+ 
+             if (ifg_4b_add) begin
+                 next_start_on_lane0 = 1'b0;
+             end
+             else begin
+                 next_start_on_lane0 = 1'b1;
+             end
+ 
+          end
+ 
+        SM_TX:
+          begin
+ 
+              next_xgxs_txd = txhfifo_rdata_d1;
+              next_xgxs_txc = 8'h00;
+ 
+              txhfifo_ren = 1'b1;
+ 
+ 
+              // Wait for EOP indication to be read from the fifo, then
+              // transition to next state.
+ 
+              if (txhfifo_rstatus[`TXSTATUS_EOP]) begin
+ 
+                  txhfifo_ren = 1'b0;
+                  next_frame_available = !txhfifo_ralmost_empty;
+                  next_state_enc = SM_EOP;
+ 
+              end
+              else if (txhfifo_rempty || txhfifo_rstatus[`TXSTATUS_SOP]) begin
+ 
+                  // Failure condition, we did not see EOP and there
+                  // is no more data in fifo or SOP, force end of packet transmit.
+ 
+                  next_state_enc = SM_TERM_FAIL;
+ 
+              end
+ 
+              next_eop[0] = txhfifo_rstatus[2:0] == 3'd1;
+              next_eop[1] = txhfifo_rstatus[2:0] == 3'd2;
+              next_eop[2] = txhfifo_rstatus[2:0] == 3'd3;
+              next_eop[3] = txhfifo_rstatus[2:0] == 3'd4;
+              next_eop[4] = txhfifo_rstatus[2:0] == 3'd5;
+              next_eop[5] = txhfifo_rstatus[2:0] == 3'd6;
+              next_eop[6] = txhfifo_rstatus[2:0] == 3'd7;
+              next_eop[7] = txhfifo_rstatus[2:0] == 3'd0;
+ 
+          end
+ 
+        SM_EOP:
+          begin
+ 
+              // Insert TERMINATE character in correct lane depending on position
+              // of EOP read from fifo. Also insert CRC read from control fifo.
+ 
+              if (eop[0]) begin
+                  next_xgxs_txd = {{2{`IDLE}}, `TERMINATE, 
+                                   crc32_tx[31:0], txhfifo_rdata_d1[7:0]};
+                  next_xgxs_txc = 8'b11100000;
+              end
+ 
+              if (eop[1]) begin
+                  next_xgxs_txd = {`IDLE, `TERMINATE,
+                                   crc32_tx[31:0], txhfifo_rdata_d1[15:0]};
+                  next_xgxs_txc = 8'b11000000;
+              end
+ 
+              if (eop[2]) begin
+                  next_xgxs_txd = {`TERMINATE, crc32_tx[31:0], txhfifo_rdata_d1[23:0]};
+                  next_xgxs_txc = 8'b10000000;
+              end
+ 
+              if (eop[3]) begin
+                  next_xgxs_txd = {crc32_tx[31:0], txhfifo_rdata_d1[31:0]};
+                  next_xgxs_txc = 8'b00000000;
+              end
+ 
+              if (eop[4]) begin
+                  next_xgxs_txd = {crc32_tx[23:0], txhfifo_rdata_d1[39:0]};
+                  next_xgxs_txc = 8'b00000000;
+              end
+ 
+              if (eop[5]) begin
+                  next_xgxs_txd = {crc32_tx[15:0], txhfifo_rdata_d1[47:0]};
+                  next_xgxs_txc = 8'b00000000;
+              end
+ 
+              if (eop[6]) begin
+                  next_xgxs_txd = {crc32_tx[7:0], txhfifo_rdata_d1[55:0]};
+                  next_xgxs_txc = 8'b00000000;
+              end
+ 
+              if (eop[7]) begin
+                  next_xgxs_txd = {txhfifo_rdata_d1[63:0]};
+                  next_xgxs_txc = 8'b00000000;
+              end
+ 
+              if (!frame_available) begin
+ 
+                  // If there is not another frame ready to be transmitted, interface
+                  // will go idle and idle deficit idle count calculation is irrelevant.
+                  // Set deficit to 0.
+ 
+                  next_ifg_deficit = 3'b0;
+ 
+              end
+              else begin
+ 
+                  // Idle deficit count calculated based on number of "wasted" bytes
+                  // between TERMINATE and alignment of next frame in LANE0.
+ 
+                  next_ifg_deficit = ifg_deficit +
+                                     {2'b0, eop[0] | eop[4]} +
+                                     {1'b0, eop[1] | eop[5], 1'b0} +
+                                     {1'b0, eop[2] | eop[6],
+                                      eop[2] | eop[6]};
+              end
+ 
+              // IFG corrections based on deficit count and previous starting lane
+              // Calculated based on following table:
+              //
+              //                 DIC=0          DIC=1          DIC=2          DIC=3
+              //              -------------  -------------  -------------  -------------
+              // PktLen       IFG      Next  IFG      Next  IFG      Next  IFG      Next
+              // Modulus      Length   DIC   Length   DIC   Length   DIC   Length   DIC
+              // -----------------------------------------------------------------------
+              //    0           12      0      12      1      12      2      12      3
+              //    1           11      1      11      2      11      3      15      0
+              //    2           10      2      10      3      14      0      14      1
+              //    3            9      3      13      0      13      1      13      2
+              //
+              //
+              // In logic it translates into adding 4, 8, or 12 bytes of IFG relative
+              // to LANE0.
+              //   IFG and Add columns assume no deficit applied
+              //   IFG+DIC and Add+DIC assume deficit must be applied
+              //
+              //                        Start lane 0       Start lane 4	
+              // EOP Pads IFG  IFG+DIC	Add   Add+DIC	   Add    Add IFG
+              // 0   3    11   15        8     12           12     16
+              // 1   2    10   14        8     12           12     16
+              // 2   1    9    13        8     12           12     16
+              // 3   8    12   12        4     4            8      8
+              // 4   7    11   15        4     8            8      12
+              // 5   6    10   14        4     8            8      12
+              // 6   5    9    13        4     8            8      12
+              // 7   4    12   12        8     8            12     12
+ 
+              if (!frame_available) begin
+ 
+                  // If there is not another frame ready to be transmitted, interface
+                  // will go idle and idle deficit idle count calculation is irrelevant.
+ 
+                  next_ifg_4b_add = 1'b0;
+                  next_ifg_8b_add = 1'b0;
+                  next_ifg_8b2_add = 1'b0;
+ 
+              end
+              else if (next_ifg_deficit[2] == ifg_deficit[2]) begin
+ 
+                  // Add 4 bytes IFG
+ 
+                  next_ifg_4b_add = (eop[0] & !start_on_lane0) |
+                                    (eop[1] & !start_on_lane0) |
+                                    (eop[2] & !start_on_lane0) |
+                                    (eop[3] & start_on_lane0) |
+                                    (eop[4] & start_on_lane0) |
+                                    (eop[5] & start_on_lane0) |
+                                    (eop[6] & start_on_lane0) |
+                                    (eop[7] & !start_on_lane0);
+ 
+                  // Add 8 bytes IFG
+ 
+                  next_ifg_8b_add = (eop[0]) |
+                                    (eop[1]) |
+                                    (eop[2]) |
+                                    (eop[3] & !start_on_lane0) |
+                                    (eop[4] & !start_on_lane0) |
+                                    (eop[5] & !start_on_lane0) |
+                                    (eop[6] & !start_on_lane0) |
+                                    (eop[7]);
+ 
+                  // Add another 8 bytes IFG
+ 
+                  next_ifg_8b2_add = 1'b0;
+ 
+              end
+              else begin
+ 
+                  // Add 4 bytes IFG
+ 
+                  next_ifg_4b_add = (eop[0] & start_on_lane0) |
+                                    (eop[1] & start_on_lane0) |
+                                    (eop[2] & start_on_lane0) |
+                                    (eop[3] &  start_on_lane0) |
+                                    (eop[4] & !start_on_lane0) |
+                                    (eop[5] & !start_on_lane0) |
+                                    (eop[6] & !start_on_lane0) |
+                                    (eop[7] & !start_on_lane0);
+ 
+                  // Add 8 bytes IFG
+ 
+                  next_ifg_8b_add = (eop[0]) |
+                                    (eop[1]) |
+                                    (eop[2]) |
+                                    (eop[3] & !start_on_lane0) |
+                                    (eop[4]) |
+                                    (eop[5]) |
+                                    (eop[6]) |
+                                    (eop[7]);
+ 
+                  // Add another 8 bytes IFG
+ 
+                  next_ifg_8b2_add = (eop[0] & !start_on_lane0) |
+                                     (eop[1] & !start_on_lane0) |
+                                     (eop[2] & !start_on_lane0);
+ 
+              end
+ 
+              if (|eop[2:0]) begin
+ 
+                  if (frame_available) begin
+ 
+                      // Next state depends on number of IFG bytes to be inserted.
+                      // Skip idle state if needed.
+ 
+                      if (next_ifg_8b2_add) begin
+                          next_state_enc = SM_IFG;
+                      end
+                      else if (next_ifg_8b_add) begin
+                          next_state_enc = SM_IDLE;
+                      end
+                      else begin
+                          txhfifo_ren = 1'b1;
+                          next_state_enc = SM_PREAMBLE;
+                      end
+ 
+                  end
+                  else begin
+                      next_state_enc = SM_IFG;
+                  end
+              end
+ 
+              if (|eop[7:3]) begin
+                  next_state_enc = SM_TERM;
+              end
+ 
+          end
+ 
+        SM_TERM:
+          begin
+ 
+              // Insert TERMINATE character in correct lane depending on position
+              // of EOP read from fifo. Also insert CRC read from control fifo.
+ 
+              if (eop[3]) begin
+                  next_xgxs_txd = {{7{`IDLE}}, `TERMINATE};
+                  next_xgxs_txc = 8'b11111111;
+              end
+ 
+              if (eop[4]) begin
+                  next_xgxs_txd = {{6{`IDLE}}, `TERMINATE, crc32_tx[31:24]};
+                  next_xgxs_txc = 8'b11111110;
+              end
+ 
+              if (eop[5]) begin
+                  next_xgxs_txd = {{5{`IDLE}}, `TERMINATE, crc32_tx[31:16]};
+                  next_xgxs_txc = 8'b11111100;
+              end
+ 
+              if (eop[6]) begin
+                  next_xgxs_txd = {{4{`IDLE}}, `TERMINATE, crc32_tx[31:8]};
+                  next_xgxs_txc = 8'b11111000;
+              end
+ 
+              if (eop[7]) begin
+                  next_xgxs_txd = {{3{`IDLE}}, `TERMINATE, crc32_tx[31:0]};
+                  next_xgxs_txc = 8'b11110000;
+              end
+ 
+              // Next state depends on number of IFG bytes to be inserted.
+              // Skip idle state if needed.
+ 
+              if (frame_available && !ifg_8b_add) begin
+                  txhfifo_ren = 1'b1;
+                  next_state_enc = SM_PREAMBLE;
+              end
+              else if (frame_available) begin
+                  next_state_enc = SM_IDLE;
+              end
+              else begin
+                  next_state_enc = SM_IFG;
+              end
+ 
+          end
+ 
+        SM_TERM_FAIL:
+          begin
+ 
+              next_xgxs_txd = {{7{`IDLE}}, `TERMINATE};
+              next_xgxs_txc = 8'b11111111;
+              next_state_enc = SM_IFG;
+ 
+          end
+ 
+        SM_IFG:
+          begin
+ 
+              next_state_enc = SM_IDLE;
+ 
+          end
+ 
+        default:
+          begin
+              next_state_enc = SM_IDLE;
+          end
+ 
+    endcase
+ 
+end
+ 
+ 
+always @(/*AS*/crc32_d64 or txhfifo_wen or txhfifo_wstatus) begin
+ 
+    if (txhfifo_wen && txhfifo_wstatus[`TXSTATUS_SOP]) begin
+        crc_data = 32'hffffffff;
+    end
+    else begin
+        crc_data = crc32_d64;
+    end
+ 
+end
+ 
+always @(/*AS*/byte_cnt or curr_state_pad or txdfifo_rdata
+         or txdfifo_rempty or txdfifo_ren_d1 or txdfifo_rstatus
+         or txhfifo_walmost_full) begin
+ 
+    next_state_pad = curr_state_pad;
+ 
+    next_txhfifo_wdata = txdfifo_rdata;
+    next_txhfifo_wstatus = txdfifo_rstatus;
+ 
+    txdfifo_ren = 1'b0;
+    next_txhfifo_wen = 1'b0;
+ 
+    case (curr_state_pad)
+ 
+      SM_PAD_EQ: begin
+ 
+ 
+          //---
+          // If room availabe in hoding fifo and data available in
+          // data fifo, transfer data words. If transmit state machine
+          // is reading from fifo we can assume room will be available.
+ 
+          if (!txhfifo_walmost_full) begin
+ 
+              txdfifo_ren = !txdfifo_rempty;
+ 
+          end
+ 
+ 
+          //---
+          // This logic dependent on read during previous cycle.
+ 
+          if (txdfifo_ren_d1) begin
+ 
+              next_txhfifo_wen = 1'b1;
+ 
+              // On EOP, decide if padding is required for this packet.
+ 
+              if (txdfifo_rstatus[`TXSTATUS_EOP]) begin
+ 
+                  if (byte_cnt < 14'd56) begin
+ 
+                      next_txhfifo_wstatus = `TXSTATUS_NONE;
+                      txdfifo_ren = 1'b0;
+                      next_state_pad = SM_PAD_PAD;
+ 
+                  end
+                  else if (byte_cnt == 14'd56 &&
+                           (txdfifo_rstatus[2:0] == 3'd1 ||
+                            txdfifo_rstatus[2:0] == 3'd2 ||
+                            txdfifo_rstatus[2:0] == 3'd3)) begin
+ 
+                      // Pad up to LANE3, keep the other 4 bytes for crc that will
+                      // be inserted by dequeue engine.
+ 
+                      next_txhfifo_wstatus[2:0] = 3'd4;
+ 
+                      // Pad end bytes with zeros.
+ 
+                      if (txdfifo_rstatus[2:0] == 3'd1)
+                        next_txhfifo_wdata[31:8] = 24'b0;
+                      if (txdfifo_rstatus[2:0] == 3'd2)
+                        next_txhfifo_wdata[31:16] = 16'b0;
+                      if (txdfifo_rstatus[2:0] == 3'd3)
+                        next_txhfifo_wdata[31:24] = 8'b0;
+ 
+                      txdfifo_ren = 1'b0;
+ 
+                  end
+                  else begin
+ 
+                      txdfifo_ren = 1'b0;
+ 
+                  end
+ 
+              end
+ 
+          end
+ 
+      end
+ 
+      SM_PAD_PAD: begin
+ 
+          //---
+          // Pad packet to 64 bytes by writting zeros to holding fifo.
+ 
+          if (!txhfifo_walmost_full) begin
+ 
+              next_txhfifo_wdata = 64'b0;
+              next_txhfifo_wstatus = `TXSTATUS_NONE;
+              next_txhfifo_wen = 1'b1;
+ 
+              if (byte_cnt == 14'd56) begin
+ 
+ 
+                  // Pad up to LANE3, keep the other 4 bytes for crc that will
+                  // be inserted by dequeue engine.
+ 
+                  next_txhfifo_wstatus[`TXSTATUS_EOP] = 1'b1;
+                  next_txhfifo_wstatus[2:0] = 3'd4;
+ 
+                  next_state_pad = SM_PAD_EQ;
+ 
+              end
+ 
+          end
+ 
+      end
+ 
+      default:
+        begin
+            next_state_pad = SM_PAD_EQ;
+        end
+ 
+    endcase
+ 
+end
+ 
+ 
+always @(posedge clk_xgmii_tx or negedge reset_xgmii_tx_n) begin
+ 
+    if (reset_xgmii_tx_n == 1'b0) begin
+ 
+        curr_state_pad <= SM_PAD_EQ;
+ 
+        txdfifo_ren_d1 <= 1'b0;
+ 
+        txhfifo_wdata <= 64'b0;
+        txhfifo_wstatus <= 8'b0;
+        txhfifo_wen <= 1'b0;   
+ 
+        byte_cnt <= 14'b0;
+ 
+        shift_crc_data <= 64'b0;
+        shift_crc_eop <= 4'b0;
+        shift_crc_cnt <= 4'b0;
+ 
+    end
+    else begin
+ 
+        curr_state_pad <= next_state_pad;
+ 
+        txdfifo_ren_d1 <= txdfifo_ren;
+ 
+        txhfifo_wdata <= next_txhfifo_wdata;
+        txhfifo_wstatus <= next_txhfifo_wstatus;
+        txhfifo_wen <= next_txhfifo_wen;
+ 
+ 
+        //---
+        // Reset byte count on SOP
+ 
+        if (next_txhfifo_wen) begin
+ 
+            if (next_txhfifo_wstatus[`TXSTATUS_SOP]) begin
+ 
+                byte_cnt <= 14'd8;
+ 
+            end
+            else begin
+ 
+                byte_cnt <= byte_cnt + 14'd8;
+ 
+            end
+ 
+        end
+ 
+ 
+        //---
+        // Calculate CRC as data is written to holding fifo. The holding fifo creates
+        // a delay that allow the CRC calculation to complete before the end of the frame
+        // is ready to be transmited.
+ 
+        if (txhfifo_wen) begin
+ 
+            crc32_d64 <= nextCRC32_D64(reverse_64b(txhfifo_wdata), crc_data);
+ 
+        end
+ 
+        if (txhfifo_wen && txhfifo_wstatus[`TXSTATUS_EOP]) begin
+ 
+            // Last bytes calculated 8-bit at a time instead of 64-bit. Start
+            // this process at the end of the frame.
+ 
+            crc32_d8 <= crc32_d64;
+ 
+            shift_crc_data <= txhfifo_wdata;
+            shift_crc_cnt <= 4'd9;
+ 
+            if (txhfifo_wstatus[2:0] == 3'b0) begin
+              shift_crc_eop <= 4'd8;
+            end
+            else begin
+                shift_crc_eop <= {1'b0, txhfifo_wstatus[2:0]};
+            end
+ 
+        end
+        else if (shift_crc_eop != 4'b0) begin
+ 
+            // Complete crc calculation 8-bit at a time until finished. This can
+            // be 1 to 8 bytes long.
+ 
+            crc32_d8 <= nextCRC32_D8(reverse_8b(shift_crc_data[7:0]), crc32_d8);
+ 
+            shift_crc_data <= {8'b0, shift_crc_data[63:8]};
+            shift_crc_eop <= shift_crc_eop - 4'd1;
+ 
+        end
+ 
+ 
+        //---
+        // Update CRC register at the end of calculation. Always update after 8
+        // cycles for deterministic results, even if a single byte was present in
+        // last data word.
+ 
+        if (shift_crc_cnt == 4'b1) begin
+ 
+            crc32_tx <= ~reverse_32b(crc32_d8);
+ 
+        end
+        else begin
+ 
+            shift_crc_cnt <= shift_crc_cnt - 4'd1;
+ 
+        end
+ 
+    end
+ 
+end
+ 
+endmodule
+ 
diff --git a/fpga/usrp3/lib/xge/rtl/verilog/tx_enqueue.v b/fpga/usrp3/lib/xge/rtl/verilog/tx_enqueue.v
new file mode 100644
index 000000000..6a17d76f2
--- /dev/null
+++ b/fpga/usrp3/lib/xge/rtl/verilog/tx_enqueue.v
@@ -0,0 +1,179 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  File name "tx_enqueue.v"                                    ////
+////                                                              ////
+////  This file is part of the "10GE MAC" project                 ////
+////  http://www.opencores.org/cores/xge_mac/                     ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - A. Tanguay (antanguay@opencores.org)                  ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2008 AUTHORS. All rights reserved.             ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+ 
+ 
+`include "defines.v"
+ 
+module tx_enqueue(/*AUTOARG*/
+  // Outputs
+  pkt_tx_full, txdfifo_wdata, txdfifo_wstatus, txdfifo_wen,
+  status_txdfifo_ovflow_tog,
+  // Inputs
+  clk_156m25, reset_156m25_n, pkt_tx_data, pkt_tx_val, pkt_tx_sop,
+  pkt_tx_eop, pkt_tx_mod, txdfifo_wfull, txdfifo_walmost_full
+  );
+ 
+`include "CRC32_D64.v"
+`include "CRC32_D8.v"
+`include "utils.v"
+ 
+input         clk_156m25;
+input         reset_156m25_n;
+ 
+input  [63:0] pkt_tx_data;
+input         pkt_tx_val;
+input         pkt_tx_sop;
+input         pkt_tx_eop;
+input  [2:0]  pkt_tx_mod;
+ 
+input         txdfifo_wfull;
+input         txdfifo_walmost_full;
+ 
+output        pkt_tx_full;
+ 
+output [63:0] txdfifo_wdata;
+output [7:0]  txdfifo_wstatus;
+output        txdfifo_wen;
+ 
+output        status_txdfifo_ovflow_tog;
+ 
+/*AUTOREG*/
+// Beginning of automatic regs (for this module's undeclared outputs)
+reg                     status_txdfifo_ovflow_tog;
+reg [63:0]              txdfifo_wdata;
+reg                     txdfifo_wen;
+reg [7:0]               txdfifo_wstatus;
+// End of automatics
+ 
+/*AUTOWIRE*/
+ 
+ 
+reg             txd_ovflow;
+reg             next_txd_ovflow;
+ 
+ 
+ 
+// Full status if data fifo is almost full.
+// Current packet can complete transfer since data input rate
+// matches output rate. But next packet must wait for more headroom.
+ 
+assign pkt_tx_full = txdfifo_walmost_full;
+ 
+ 
+ 
+always @(posedge clk_156m25 or negedge reset_156m25_n) begin
+ 
+    if (reset_156m25_n == 1'b0) begin
+ 
+        txd_ovflow <= 1'b0;
+ 
+        status_txdfifo_ovflow_tog <= 1'b0;
+ 
+    end
+    else begin
+ 
+        txd_ovflow <= next_txd_ovflow;
+ 
+        //---
+        // FIFO errors, used to generate interrupts
+ 
+        if (next_txd_ovflow && !txd_ovflow) begin
+            status_txdfifo_ovflow_tog <= ~status_txdfifo_ovflow_tog;
+        end
+ 
+    end
+ 
+end
+ 
+always @(/*AS*/pkt_tx_data or pkt_tx_eop or pkt_tx_mod or pkt_tx_sop
+         or pkt_tx_val or txd_ovflow or txdfifo_wfull) begin
+ 
+    txdfifo_wstatus = `TXSTATUS_NONE;
+    txdfifo_wen = pkt_tx_val;
+ 
+    next_txd_ovflow = txd_ovflow;
+ 
+    `ifdef BIGENDIAN
+    txdfifo_wdata = {pkt_tx_data[7:0], pkt_tx_data[15:8], pkt_tx_data[23:16], pkt_tx_data[31:24],
+                     pkt_tx_data[39:32], pkt_tx_data[47:40], pkt_tx_data[55:48],
+                     pkt_tx_data[63:56]};
+    `else
+    txdfifo_wdata = pkt_tx_data;
+    `endif
+ 
+    // Write SOP marker to fifo.
+ 
+    if (pkt_tx_val && pkt_tx_sop) begin
+ 
+        txdfifo_wstatus[`TXSTATUS_SOP] = 1'b1;
+ 
+    end
+ 
+ 
+    // Write EOP marker to fifo.
+ 
+    if (pkt_tx_val) begin
+ 
+        if (pkt_tx_eop) begin
+            txdfifo_wstatus[2:0] = pkt_tx_mod;
+            txdfifo_wstatus[`TXSTATUS_EOP] = 1'b1;
+        end
+ 
+    end
+ 
+ 
+    // Overflow indication
+ 
+    if (pkt_tx_val) begin
+ 
+        if (txdfifo_wfull) begin
+ 
+            next_txd_ovflow = 1'b1;
+ 
+        end
+        else if (pkt_tx_sop) begin
+ 
+            next_txd_ovflow = 1'b0;
+ 
+        end
+    end
+ 
+end
+ 
+ 
+endmodule
+ 
\ No newline at end of file
diff --git a/fpga/usrp3/lib/xge/rtl/verilog/tx_hold_fifo.v b/fpga/usrp3/lib/xge/rtl/verilog/tx_hold_fifo.v
new file mode 100644
index 000000000..a71c256c6
--- /dev/null
+++ b/fpga/usrp3/lib/xge/rtl/verilog/tx_hold_fifo.v
@@ -0,0 +1,96 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  File name "tx_hold_fifo.v"                                  ////
+////                                                              ////
+////  This file is part of the "10GE MAC" project                 ////
+////  http://www.opencores.org/cores/xge_mac/                     ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - A. Tanguay (antanguay@opencores.org)                  ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2008 AUTHORS. All rights reserved.             ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+ 
+ 
+`include "defines.v"
+ 
+module tx_hold_fifo(/*AUTOARG*/
+  // Outputs
+  txhfifo_wfull, txhfifo_walmost_full, txhfifo_rdata, txhfifo_rstatus,
+  txhfifo_rempty, txhfifo_ralmost_empty,
+  // Inputs
+  clk_xgmii_tx, reset_xgmii_tx_n, txhfifo_wdata, txhfifo_wstatus,
+  txhfifo_wen, txhfifo_ren
+  );
+ 
+input         clk_xgmii_tx;
+input         reset_xgmii_tx_n;
+ 
+input [63:0]  txhfifo_wdata;
+input [7:0]   txhfifo_wstatus;
+input         txhfifo_wen;
+ 
+input         txhfifo_ren;
+ 
+output        txhfifo_wfull;
+output        txhfifo_walmost_full;
+ 
+output [63:0] txhfifo_rdata;
+output [7:0]  txhfifo_rstatus;
+output        txhfifo_rempty;
+output        txhfifo_ralmost_empty;
+ 
+generic_fifo #(
+  .DWIDTH (72),
+  .AWIDTH (`TX_HOLD_FIFO_AWIDTH),
+  .REGISTER_READ (1),
+  .EARLY_READ (1),
+  .CLOCK_CROSSING (0),
+  .ALMOST_EMPTY_THRESH (7),
+  .ALMOST_FULL_THRESH (4),
+//  .MEM_TYPE (`MEM_AUTO_SMALL)
+  .MEM_TYPE (`MEM_AUTO_XILINX)
+)
+fifo0(
+    .wclk (clk_xgmii_tx),
+    .wrst_n (reset_xgmii_tx_n),
+    .wen (txhfifo_wen),
+    .wdata ({txhfifo_wstatus, txhfifo_wdata}),
+    .wfull (txhfifo_wfull),
+    .walmost_full (txhfifo_walmost_full),
+ 
+    .rclk (clk_xgmii_tx),
+    .rrst_n (reset_xgmii_tx_n),
+    .ren (txhfifo_ren),
+    .rdata ({txhfifo_rstatus, txhfifo_rdata}),
+    .rempty (txhfifo_rempty),
+    .ralmost_empty (txhfifo_ralmost_empty)
+);
+ 
+endmodule
+ 
+ 
\ No newline at end of file
diff --git a/fpga/usrp3/lib/xge/rtl/verilog/utils.v b/fpga/usrp3/lib/xge/rtl/verilog/utils.v
new file mode 100644
index 000000000..6137b3e31
--- /dev/null
+++ b/fpga/usrp3/lib/xge/rtl/verilog/utils.v
@@ -0,0 +1,71 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  File name "utils.v"                                         ////
+////                                                              ////
+////  This file is part of the "10GE MAC" project                 ////
+////  http://www.opencores.org/cores/xge_mac/                     ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - A. Tanguay (antanguay@opencores.org)                  ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2008 AUTHORS. All rights reserved.             ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+ 
+ 
+function [63:0] reverse_64b;
+  input [63:0]   data;
+  integer        i;
+    begin
+        for (i = 0; i < 64; i = i + 1) begin
+            reverse_64b[i] = data[63 - i];
+        end
+    end
+endfunction
+ 
+ 
+function [31:0] reverse_32b;
+  input [31:0]   data;
+  integer        i;
+    begin
+        for (i = 0; i < 32; i = i + 1) begin
+            reverse_32b[i] = data[31 - i];
+        end
+    end
+endfunction
+ 
+ 
+function [7:0] reverse_8b;
+  input [7:0]   data;
+  integer        i;
+    begin
+        for (i = 0; i < 8; i = i + 1) begin
+            reverse_8b[i] = data[7 - i];
+        end
+    end
+endfunction
+ 
+ 
diff --git a/fpga/usrp3/lib/xge/rtl/verilog/wishbone_if.v b/fpga/usrp3/lib/xge/rtl/verilog/wishbone_if.v
new file mode 100644
index 000000000..b70bc7294
--- /dev/null
+++ b/fpga/usrp3/lib/xge/rtl/verilog/wishbone_if.v
@@ -0,0 +1,1031 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  File name "wishbone.v"                                      ////
+////                                                              ////
+////  This file is part of the "10GE MAC" project                 ////
+////  http://www.opencores.org/cores/xge_mac/                     ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - A. Tanguay (antanguay@opencores.org)                  ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2008 AUTHORS. All rights reserved.             ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+`include "defines.v"
+
+module wishbone_if(/*AUTOARG*/
+  // Outputs
+  wb_dat_o, wb_ack_o, wb_int_o, ctrl_tx_enable,
+  mdc, mdio_out, mdio_tri, xge_gpo,
+
+  // Inputs
+  wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_we_i, wb_stb_i, wb_cyc_i,
+  status_crc_error, status_fragment_error, status_txdfifo_ovflow,
+  status_txdfifo_udflow, status_rxdfifo_ovflow, status_rxdfifo_udflow,
+  status_pause_frame_rx, status_local_fault, status_remote_fault,
+  mdio_in, xge_gpi
+  );
+
+
+input         wb_clk_i;
+input         wb_rst_i;
+
+input  [7:0]  wb_adr_i;
+input  [31:0] wb_dat_i;
+input         wb_we_i;
+input         wb_stb_i;
+input         wb_cyc_i;
+
+output [31:0] wb_dat_o;
+output        wb_ack_o;
+output        wb_int_o;
+
+input         status_crc_error;
+input         status_fragment_error;
+
+input         status_txdfifo_ovflow;
+
+input         status_txdfifo_udflow;
+
+input         status_rxdfifo_ovflow;
+
+input         status_rxdfifo_udflow;
+
+input         status_pause_frame_rx;
+
+input         status_local_fault;
+input         status_remote_fault;
+
+output        ctrl_tx_enable;
+
+output reg    mdc;
+output reg    mdio_out;
+output reg    mdio_tri;   // Assert to tristate driver.
+input      mdio_in;
+input [7:0] xge_gpi;
+output reg [7:0] xge_gpo;
+
+   //
+   // State Declarations
+   //
+   parameter  IDLE = 0,
+		PREAMBLE1 = 1,
+		PREAMBLE2 = 2,
+		PREAMBLE3 = 3,
+		PREAMBLE4 = 4,
+		PREAMBLE5 = 5,
+		PREAMBLE6 = 6,
+		PREAMBLE7 = 7,
+		PREAMBLE8 = 8,
+		PREAMBLE9 = 9,
+		PREAMBLE10 = 10,
+		PREAMBLE11 = 11,
+		PREAMBLE12 = 12,
+		PREAMBLE13 = 13,
+		PREAMBLE14 = 14,
+		PREAMBLE15 = 15,
+		PREAMBLE16 = 16,
+		PREAMBLE17 = 17,
+		PREAMBLE18 = 18,
+		PREAMBLE19 = 19,
+		PREAMBLE20 = 20,
+		PREAMBLE21 = 21,
+		PREAMBLE22 = 22,
+		PREAMBLE23 = 23,
+		PREAMBLE24 = 24,
+		PREAMBLE25 = 25,
+		PREAMBLE26 = 26,
+		PREAMBLE27 = 27,
+		PREAMBLE28 = 28,
+		PREAMBLE29 = 29,
+		PREAMBLE30 = 30,
+		PREAMBLE31 = 31,
+		PREAMBLE32 = 32,
+		START1 = 33,
+		C22_START2 = 34,
+		C45_START2 = 35,
+		OP1 = 36,
+		OP2 = 37,
+		PRTAD1 = 38,
+		PRTAD2 = 39,
+		PRTAD3 = 40,
+		PRTAD4 = 41,
+		PRTAD5 = 42,
+		DEVAD1 = 43,
+		DEVAD2 = 44,
+		DEVAD3 = 45,
+		DEVAD4 = 46,
+		DEVAD5 = 47,
+		TA1 = 48,
+		TA2 = 49,
+		TA3 = 50,
+		READ1 = 51,
+		READ2 = 52,
+		READ3 = 53,
+		READ4 = 54,
+		READ5 = 55,
+		READ6 = 56,
+		READ7 = 57,
+		READ8 = 58,
+		READ9 = 59,
+		READ10 = 60,
+		READ11 = 61,
+		READ12 = 62,
+		READ13 = 63,
+		READ14 = 64,
+		READ15 = 65,
+		READ16 = 66,
+		WRITE1 = 67,
+		WRITE2 = 68,
+		WRITE3 = 69,
+		WRITE4 = 70,
+		WRITE5 = 71,
+		WRITE6 = 72,
+		WRITE7 = 73,
+		WRITE8 = 74,
+		WRITE9 = 75,
+		WRITE10 = 76,
+		WRITE11 = 77,
+		WRITE12 = 78,
+		WRITE13 = 79,
+		WRITE14 = 80,
+		WRITE15 = 81,
+		WRITE16 = 82,
+		C45_ADDR1 = 83,
+		C45_ADDR2 = 84,
+		C45_ADDR3 = 85,
+		C45_ADDR4 = 86,
+		C45_ADDR5 = 87,
+		C45_ADDR6 = 88,
+		C45_ADDR7 = 89,
+		C45_ADDR8 = 90,
+		C45_ADDR9 = 91,
+		C45_ADDR10 = 92,
+		C45_ADDR11 = 93,
+		C45_ADDR12 = 94,
+		C45_ADDR13 = 95,
+		C45_ADDR14 = 96,
+		C45_ADDR15 = 97,
+		C45_ADDR16 = 98,
+		PREIDLE = 99;
+
+
+
+
+/*AUTOREG*/
+// Beginning of automatic regs (for this module's undeclared outputs)
+reg [31:0]              wb_dat_o;
+reg                     wb_int_o;
+// End of automatics
+
+reg  [0:0]              cpureg_config0;
+reg  [8:0]              cpureg_int_pending;
+reg  [8:0]              cpureg_int_mask;
+
+reg                     cpuack;
+
+reg                     status_remote_fault_d1;
+reg                     status_local_fault_d1;
+
+reg [15:0]			mdio_read_data;
+reg [15:0] 			mdio_write_data;
+reg [15:0] 			mdio_address;
+reg [12:0] 			mdio_operation;
+reg 				mdio_control;
+reg [7:0] 			mdc_clk_count;
+reg 				mdc_falling_edge;
+reg 				mdio_running;
+reg 				mdio_done;
+reg [7:0] 			state;
+reg [7:0] 			xge_gpi_reg;
+reg [7:0] 			xge_gpo_reg;
+
+
+
+/*AUTOWIRE*/
+
+wire [8:0] 			int_sources;
+
+
+//---
+// Source of interrupts, some are edge sensitive, others
+// expect a pulse signal.
+
+assign int_sources = {
+                      status_fragment_error,
+                      status_crc_error,
+
+                      status_pause_frame_rx,
+
+                      status_remote_fault ^ status_remote_fault_d1,
+                      status_local_fault ^ status_local_fault_d1,
+
+                      status_rxdfifo_udflow,
+                      status_rxdfifo_ovflow,
+                      status_txdfifo_udflow,
+                      status_txdfifo_ovflow
+                      };
+
+//---
+// Config Register 0
+
+//TODO
+//assign ctrl_tx_enable = cpureg_config0[0];
+assign ctrl_tx_enable = 1'b1;
+
+
+
+//---
+// Wishbone signals
+
+assign wb_ack_o = cpuack && wb_stb_i;
+
+always @(posedge wb_clk_i or posedge wb_rst_i) begin
+
+    if (wb_rst_i == 1'b1) begin
+
+        cpureg_config0 <= 1'h1;
+        cpureg_int_pending <= 9'b0;
+        cpureg_int_mask <= 9'b0;
+
+        wb_dat_o <= 32'b0;
+        wb_int_o <= 1'b0;
+
+        cpuack <= 1'b0;
+
+       mdio_address <= 0;
+       mdio_operation <= 0;
+       mdio_write_data <= 0;
+
+       mdio_running <= 0;
+       xge_gpi_reg <= 0;
+       xge_gpo <= 0;
+       xge_gpo_reg <= 0;
+
+
+
+
+ //       status_remote_fault_d1 <= status_remote_fault;
+ //       status_local_fault_d1 <= status_local_fault;
+       // IJB. Original code was unsynthesizable and a little bizzare
+       // implying reset would latch data.
+       status_remote_fault_d1 <= 0;
+       status_local_fault_d1 <= 0;
+    end
+    else begin
+
+        wb_int_o <= |(cpureg_int_pending & cpureg_int_mask);
+
+        cpureg_int_pending <= cpureg_int_pending | int_sources;
+
+        cpuack <= wb_cyc_i && wb_stb_i;
+
+        status_remote_fault_d1 <= status_remote_fault;
+        status_local_fault_d1 <= status_local_fault;
+
+       // Handshake to MDIO state machine to reset running flag in status.
+       // Wait for falling MDC edge to prevent S/W race condition occuring
+       // where done flag still asserted but running flag now cleared (repeatedly).
+       if (mdio_done && mdc_falling_edge)
+	 mdio_running <= 0;
+
+       // Register GPIO to allow regs placed in the I/O cells and provide some metastability prot
+       xge_gpi_reg <= xge_gpi;
+       xge_gpo <= xge_gpo_reg;
+
+
+        //---
+        // Read access
+
+        if (wb_cyc_i && wb_stb_i && !wb_we_i) begin
+
+            case ({wb_adr_i[7:2], 2'b0})
+
+              `CPUREG_CONFIG0: begin
+                  wb_dat_o <= {31'b0, cpureg_config0};
+              end
+
+              `CPUREG_INT_PENDING: begin
+                  wb_dat_o <= {23'b0, cpureg_int_pending};
+                  cpureg_int_pending <= int_sources;
+                  wb_int_o <= 1'b0;
+              end
+
+              `CPUREG_INT_STATUS: begin
+                  wb_dat_o <= {23'b0, int_sources};
+              end
+
+              `CPUREG_INT_MASK: begin
+                  wb_dat_o <= {23'b0, cpureg_int_mask};
+              end
+
+	      `CPUREG_MDIO_DATA: begin
+		 wb_dat_o <= {16'b0, mdio_read_data};
+	      end
+
+	      `CPUREG_MDIO_STATUS: begin
+		 wb_dat_o <= {31'b0, mdio_running};
+	      end
+
+	      `CPUREG_GPIO: begin
+		 wb_dat_o <= {24'b0, xge_gpi_reg};
+	      end
+
+
+              default: begin
+              end
+
+            endcase
+
+        end
+
+        //---
+        // Write access
+
+        if (wb_cyc_i && wb_stb_i && wb_we_i) begin
+	   $display("reg write @ addr %x",({wb_adr_i[7:2], 2'b0}));
+
+            case ({wb_adr_i[7:2], 2'b0})
+
+              `CPUREG_CONFIG0: begin
+                  cpureg_config0 <= wb_dat_i[0:0];
+              end
+
+              `CPUREG_INT_PENDING: begin
+                  cpureg_int_pending <= wb_dat_i[8:0] | cpureg_int_pending | int_sources;
+              end
+
+              `CPUREG_INT_MASK: begin
+                  cpureg_int_mask <= wb_dat_i[8:0];
+              end
+
+	      `CPUREG_MDIO_DATA: begin
+		 mdio_write_data <= wb_dat_i[15:0];
+	      end
+
+	       `CPUREG_MDIO_ADDR: begin
+		 mdio_address <= wb_dat_i[15:0];
+	       end
+
+	      `CPUREG_MDIO_OP: begin
+		 mdio_operation <= wb_dat_i[12:0];
+	       end
+
+	      `CPUREG_MDIO_CONTROL: begin
+		 // Trigger mdio operation here. Cleared by state machine at end of bus transaction.
+		 if (wb_dat_i[0])
+		   mdio_running <= 1;
+	      end
+
+	      `CPUREG_GPIO: begin
+		 xge_gpo_reg <= wb_dat_i[7:0];
+	       end
+
+
+              default: begin
+              end
+
+            endcase
+
+        end
+
+    end
+
+end // always @ (posedge wb_clk_i or posedge wb_rst_i)
+
+   //
+   // Produce mdc clock as a signal synchronously from Wishbone clock.
+   //
+   always @(posedge wb_clk_i or posedge wb_rst_i)
+     if (wb_rst_i)
+       begin
+	  mdc_clk_count <= 1;
+	  mdc <= 0;
+	  mdc_falling_edge <= 0;
+       end
+     else if (mdc_clk_count == `MDC_HALF_PERIOD)
+       begin
+	  mdc_clk_count <= 1;
+	  mdc <= ~mdc;
+	  mdc_falling_edge <= mdc;
+       end
+     else
+       begin
+	  mdc_clk_count <= mdc_clk_count + 1;
+	  mdc_falling_edge <= 0;
+       end
+
+   //
+   // MDIO state machine
+   //
+   always @(posedge wb_clk_i or posedge wb_rst_i)
+     if (wb_rst_i)
+       begin
+	  mdio_tri <= 1;
+	  mdio_out <= 0;
+	  mdio_done <= 0;
+	  mdio_read_data <= 0;
+	  state <= IDLE;
+       end
+     else if (mdc_falling_edge)
+       //
+       // This is the MDIO bus controller. Use falling edge of MDC.
+       //
+       begin
+	  // Defaults
+	  mdio_tri <= 1;
+	  mdio_out <= 0;
+	  mdio_done <= 0;
+
+
+	  case(state)
+	    // IDLE.
+	    // In Clause 22 & 45 the master of the MDIO bus is tristate during idle.
+	    //
+	    IDLE: begin
+	       mdio_tri <= 1;
+	       mdio_out <= 0;
+	       if (mdio_running)
+		 state <= PREAMBLE1;
+	    end
+	    // Preamble. All MDIO transactions begin witrh 32bits of 1 bits as a preamble.
+	    PREAMBLE1: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;
+	       state <= PREAMBLE2;
+	    end
+	    PREAMBLE2: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;
+	       state <= PREAMBLE3;
+	    end
+	    PREAMBLE3: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;
+	       state <= PREAMBLE4;
+	    end
+	    PREAMBLE4: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;
+	       state <= PREAMBLE5;
+	    end
+	    PREAMBLE5: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;
+	       state <= PREAMBLE6;
+	    end
+	    PREAMBLE6: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;
+	       state <= PREAMBLE7;
+	    end
+	    PREAMBLE7: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;
+	       state <= PREAMBLE8;
+	    end
+	    PREAMBLE8: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;
+	       state <= PREAMBLE9;
+	    end
+	    PREAMBLE9: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;
+	       state <= PREAMBLE10;
+	    end
+	    PREAMBLE10: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;
+	       state <= PREAMBLE11;
+	    end
+	    PREAMBLE11: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;
+	       state <= PREAMBLE12;
+	    end
+	    PREAMBLE12: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;
+	       state <= PREAMBLE13;
+	    end
+	    PREAMBLE13: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;
+	       state <= PREAMBLE14;
+	    end
+	    PREAMBLE14: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;
+	       state <= PREAMBLE15;
+	    end
+	    PREAMBLE15: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;
+	       state <= PREAMBLE16;
+	    end
+	    PREAMBLE16: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;
+	       state <= PREAMBLE17;
+	    end
+	    PREAMBLE17: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;
+	       state <= PREAMBLE18;
+	    end
+	    PREAMBLE18: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;
+	       state <= PREAMBLE19;
+	    end
+	    PREAMBLE19: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;
+	       state <= PREAMBLE20;
+	    end
+	    PREAMBLE20: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;
+	       state <= PREAMBLE21;
+	    end
+	    PREAMBLE21: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;
+	       state <= PREAMBLE22;
+	    end
+	    PREAMBLE22: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;
+	       state <= PREAMBLE23;
+	    end
+	    PREAMBLE23: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;
+	       state <= PREAMBLE24;
+	    end
+	    PREAMBLE24: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;
+	       state <= PREAMBLE25;
+	    end
+	    PREAMBLE25: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;
+	       state <= PREAMBLE26;
+	    end
+	    PREAMBLE26: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;
+	       state <= PREAMBLE27;
+	    end
+	    PREAMBLE27: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;
+	       state <= PREAMBLE28;
+	    end
+	    PREAMBLE28: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;
+	       state <= PREAMBLE29;
+	    end
+	    PREAMBLE29: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;
+	       state <= PREAMBLE30;
+	    end
+	    PREAMBLE30: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;
+	       state <= PREAMBLE31;
+	    end
+	    PREAMBLE31: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;
+	       state <= PREAMBLE32;
+	    end
+	    PREAMBLE32: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;
+	       state <= START1;
+	    end
+	    //
+	    // Start code for Clause 22 is 01 and Clause 45 is 00
+	    //
+	    START1: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 0;
+	       if (mdio_operation[12])
+		 // Clause 45 bit set.
+		 state <= C45_START2;
+	       else
+		 state <= C22_START2;
+	    end
+	    //
+	    // 2nd Clause 22 start bit is a 1
+	    //
+	    C22_START2: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 1;
+	       state <= OP1;
+	    end
+	    //
+	    // 2nd Clause 45 start bit is a 0
+	    //
+	    C45_START2: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 0;
+	       state <= OP1;
+	    end
+	    //
+	    // Both Clause 22 & 45 use 2 bits for operation and are compatable.
+	    // Note we don't screen here for illegal Clause 22 ops.
+	    //
+	    OP1: begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_operation[11];
+	       state <= OP2;
+	    end
+	    OP2: begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_operation[10];
+	       state <= PRTAD1;
+	    end
+	    //
+	    // Both Clause 22 & 45 use 2 sucsessive 5 bit fields to form a hierarchical address
+	    // though it's used slightly different between the 2 standards.
+	    //
+	    PRTAD1: begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_operation[9];
+	       state <= PRTAD2;
+	    end
+	    PRTAD2: begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_operation[8];
+	       state <= PRTAD3;
+	    end
+	    PRTAD3: begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_operation[7];
+	       state <= PRTAD4;
+	    end
+	    PRTAD4: begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_operation[6];
+	       state <= PRTAD5;
+	    end
+	    PRTAD5: begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_operation[5];
+	       state <= DEVAD1;
+	    end
+	    DEVAD1: begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_operation[4];
+	       state <= DEVAD2;
+	    end
+	    DEVAD2: begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_operation[3];
+	       state <= DEVAD3;
+	    end
+	    DEVAD3: begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_operation[2];
+	       state <= DEVAD4;
+	    end
+	    DEVAD4: begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_operation[1];
+	       state <= DEVAD5;
+	    end
+	    DEVAD5: begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_operation[0];
+	       state <= TA1;
+	    end
+	    //
+	    // Both Clause 22 & Clause 45 use the same turn around on the bus.
+	    // Reads have Z as the first bit and 0 driven by the slave for the 2nd bit.
+	    // Note that slaves drive the bus on the rising edge of MDC.
+	    // Writes and Address cycles have 10 driven by the master.
+	    //
+	    TA1: begin
+	       if (mdio_operation[11] == 0) // Write/Address
+		 begin
+		    mdio_tri <= 0;
+		    mdio_out <= 1;
+		    state <= TA2;
+		 end
+	       else // Read
+		 begin
+		    mdio_tri <= 1;
+		    state <= TA3;
+		 end
+	    end
+	    TA2: begin
+	       mdio_tri <= 0;
+	       mdio_out <= 0;
+	       if (!mdio_operation[12]) // Clause 22 Write
+		 state <= WRITE1;
+	       else if (mdio_operation[10]) // Clause 45 Write
+		 state <= WRITE1;
+	       else // Clause 45 ADDRESS
+		 state <= C45_ADDR1;
+	    end
+	    TA3: begin
+	       mdio_tri <= 1;
+	       state <= READ1;
+	    end
+	    //
+	    // Clause 22 Reads and both forms of clause 45 Reads have the same bus transaction from here out.
+	    //
+	    READ1: begin
+	       mdio_tri <= 1;
+	       mdio_read_data[15] <= mdio_in;
+	       state <= READ2;
+	    end
+	    READ2: begin
+	       mdio_tri <= 1;
+	       mdio_read_data[14] <= mdio_in;
+	       state <= READ3;
+	    end
+	    READ3: begin
+	       mdio_tri <= 1;
+	       mdio_read_data[13] <= mdio_in;
+	       state <= READ4;
+	    end
+	    READ4: begin
+	       mdio_tri <= 1;
+	       mdio_read_data[12] <= mdio_in;
+	       state <= READ5;
+	    end
+	    READ5: begin
+	       mdio_tri <= 1;
+	       mdio_read_data[11] <= mdio_in;
+	       state <= READ6;
+	    end
+	    READ6: begin
+	       mdio_tri <= 1;
+	       mdio_read_data[10] <= mdio_in;
+	       state <= READ7;
+	    end
+	    READ7: begin
+	       mdio_tri <= 1;
+	       mdio_read_data[9] <= mdio_in;
+	       state <= READ8;
+	    end
+	    READ8: begin
+	       mdio_tri <= 1;
+	       mdio_read_data[8] <= mdio_in;
+	       state <= READ9;
+	    end
+	    READ9: begin
+	       mdio_tri <= 1;
+	       mdio_read_data[7] <= mdio_in;
+	       state <= READ10;
+	    end
+	    READ10: begin
+	       mdio_tri <= 1;
+	       mdio_read_data[6] <= mdio_in;
+	       state <= READ11;
+	    end
+	    READ11: begin
+	       mdio_tri <= 1;
+	       mdio_read_data[5] <= mdio_in;
+	       state <= READ12;
+	    end
+	    READ12: begin
+	       mdio_tri <= 1;
+	       mdio_read_data[4] <= mdio_in;
+	       state <= READ13;
+	    end
+	    READ13: begin
+	       mdio_tri <= 1;
+	       mdio_read_data[3] <= mdio_in;
+	       state <= READ14;
+	    end
+	    READ14: begin
+	       mdio_tri <= 1;
+	       mdio_read_data[2] <= mdio_in;
+	       state <= READ15;
+	    end
+	    READ15: begin
+	       mdio_tri <= 1;
+	       mdio_read_data[1] <= mdio_in;
+	       state <= READ16;
+	    end
+	    READ16: begin
+	       mdio_tri <= 1;
+	       mdio_read_data[0] <= mdio_in;
+	       state <= PREIDLE;
+	       mdio_done <= 1;
+	    end
+	    //
+	    // Write 16bits of data for all types of Write.
+	    //
+	    WRITE1:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_write_data[15];
+	       state <= WRITE2;
+	    end
+	    WRITE2:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_write_data[14];
+	       state <= WRITE3;
+	    end
+	    WRITE3:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_write_data[13];
+	       state <= WRITE4;
+	    end
+	    WRITE4:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_write_data[12];
+	       state <= WRITE5;
+	    end
+	    WRITE5:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_write_data[11];
+	       state <= WRITE6;
+	    end
+	    WRITE6:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_write_data[10];
+	       state <= WRITE7;
+	    end
+	    WRITE7:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_write_data[9];
+	       state <= WRITE8;
+	    end
+	    WRITE8:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_write_data[8];
+	       state <= WRITE9;
+	    end
+	    WRITE9:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_write_data[7];
+	       state <= WRITE10;
+	    end
+	    WRITE10:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_write_data[6];
+	       state <= WRITE11;
+	    end
+	    WRITE11:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_write_data[5];
+	       state <= WRITE12;
+	    end
+	    WRITE12:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_write_data[4];
+	       state <= WRITE13;
+	    end
+	    WRITE13:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_write_data[3];
+	       state <= WRITE14;
+	    end
+	    WRITE14:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_write_data[2];
+	       state <= WRITE15;
+	    end
+	    WRITE15:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_write_data[1];
+	       state <= WRITE16;
+	    end
+	    WRITE16:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_write_data[0];
+	       state <= PREIDLE;
+	       mdio_done <= 1;
+	    end
+	    //
+	    // Write 16bits of address for a Clause 45 Address transaction
+	    //
+	    C45_ADDR1:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_address[15];
+	       state <= C45_ADDR2;
+	    end
+	    C45_ADDR2:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_address[14];
+	       state <= C45_ADDR3;
+	    end
+	    C45_ADDR3:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_address[13];
+	       state <= C45_ADDR4;
+	    end
+	    C45_ADDR4:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_address[12];
+	       state <= C45_ADDR5;
+	    end
+	    C45_ADDR5:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_address[11];
+	       state <= C45_ADDR6;
+	    end
+	    C45_ADDR6:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_address[10];
+	       state <= C45_ADDR7;
+	    end
+	    C45_ADDR7:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_address[9];
+	       state <= C45_ADDR8;
+	    end
+	    C45_ADDR8:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_address[8];
+	       state <= C45_ADDR9;
+	    end
+	    C45_ADDR9:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_address[7];
+	       state <= C45_ADDR10;
+	    end
+	    C45_ADDR10:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_address[6];
+	       state <= C45_ADDR11;
+	    end
+	    C45_ADDR11:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_address[5];
+	       state <= C45_ADDR12;
+	    end
+	    C45_ADDR12:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_address[4];
+	       state <= C45_ADDR13;
+	    end
+	    C45_ADDR13:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_address[3];
+	       state <= C45_ADDR14;
+	    end
+	    C45_ADDR14:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_address[2];
+	       state <= C45_ADDR15;
+	    end
+	    C45_ADDR15:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_address[1];
+	       state <= C45_ADDR16;
+	    end
+	    C45_ADDR16:begin
+	       mdio_tri <= 0;
+	       mdio_out <= mdio_address[0];
+	       state <= PREIDLE;
+	       mdio_done <= 1;
+	    end
+	    //
+	    // PREIDLE allows the mdio_running bit to reset.
+	    //
+	    PREIDLE: begin
+	       state <= IDLE;
+	    end
+	  endcase // case(state)
+
+       end // if (mdc_falling_edge)
+
+
+
+
+endmodule
+
diff --git a/fpga/usrp3/lib/xge/rtl/verilog/xge_mac.v b/fpga/usrp3/lib/xge/rtl/verilog/xge_mac.v
new file mode 100644
index 000000000..2b08e3b61
--- /dev/null
+++ b/fpga/usrp3/lib/xge/rtl/verilog/xge_mac.v
@@ -0,0 +1,329 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  File name "xge_mac.v"                                       ////
+////                                                              ////
+////  This file is part of the "10GE MAC" project                 ////
+////  http://www.opencores.org/cores/xge_mac/                     ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - A. Tanguay (antanguay@opencores.org)                  ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2008 AUTHORS. All rights reserved.             ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+
+module xge_mac (/*AUTOARG*/
+  // Outputs
+  xgmii_txd, xgmii_txc, pkt_tx_full,
+  pkt_rx_val, pkt_rx_sop, pkt_rx_mod, pkt_rx_err, pkt_rx_eop,
+  pkt_rx_data, pkt_rx_avail,
+  status_crc_error, status_fragment_error, status_txdfifo_ovflow,
+  status_txdfifo_udflow, status_rxdfifo_ovflow, status_rxdfifo_udflow,
+  status_pause_frame_rx, status_local_fault, status_remote_fault,
+  // Inputs
+  xgmii_rxd, xgmii_rxc, reset_xgmii_tx_n, reset_xgmii_rx_n,
+  reset_156m25_n, pkt_tx_val, pkt_tx_sop, pkt_tx_mod, pkt_tx_eop,
+  pkt_tx_data, pkt_rx_ren, ctrl_tx_enable,
+  clk_xgmii_tx, clk_xgmii_rx, clk_156m25
+);
+
+/*AUTOINPUT*/
+// Beginning of automatic inputs (from unused autoinst inputs)
+input                   clk_156m25;             // To rx_dq0 of rx_dequeue.v, ...
+input                   clk_xgmii_rx;           // To rx_eq0 of rx_enqueue.v, ...
+input                   clk_xgmii_tx;           // To tx_dq0 of tx_dequeue.v, ...
+input                   pkt_rx_ren;             // To rx_dq0 of rx_dequeue.v
+input [63:0]            pkt_tx_data;            // To tx_eq0 of tx_enqueue.v
+input                   pkt_tx_eop;             // To tx_eq0 of tx_enqueue.v
+input [2:0]             pkt_tx_mod;             // To tx_eq0 of tx_enqueue.v
+input                   pkt_tx_sop;             // To tx_eq0 of tx_enqueue.v
+input                   pkt_tx_val;             // To tx_eq0 of tx_enqueue.v
+input                   reset_156m25_n;         // To rx_dq0 of rx_dequeue.v, ...
+input                   reset_xgmii_rx_n;       // To rx_eq0 of rx_enqueue.v, ...
+input                   reset_xgmii_tx_n;       // To tx_dq0 of tx_dequeue.v, ...
+input [7:0]             xgmii_rxc;              // To rx_eq0 of rx_enqueue.v
+input [63:0]            xgmii_rxd;              // To rx_eq0 of rx_enqueue.v
+input                   ctrl_tx_enable;         // From wishbone_if0 of wishbone_if.v
+// End of automatics
+
+/*AUTOOUTPUT*/
+// Beginning of automatic outputs (from unused autoinst outputs)
+output                  pkt_rx_avail;           // From rx_dq0 of rx_dequeue.v
+output [63:0]           pkt_rx_data;            // From rx_dq0 of rx_dequeue.v
+output                  pkt_rx_eop;             // From rx_dq0 of rx_dequeue.v
+output                  pkt_rx_err;             // From rx_dq0 of rx_dequeue.v
+output [2:0]            pkt_rx_mod;             // From rx_dq0 of rx_dequeue.v
+output                  pkt_rx_sop;             // From rx_dq0 of rx_dequeue.v
+output                  pkt_rx_val;             // From rx_dq0 of rx_dequeue.v
+output                  pkt_tx_full;            // From tx_eq0 of tx_enqueue.v
+output [7:0]            xgmii_txc;              // From tx_dq0 of tx_dequeue.v
+output [63:0]           xgmii_txd;              // From tx_dq0 of tx_dequeue.v
+
+output        status_crc_error;
+output        status_fragment_error;
+output        status_txdfifo_ovflow;
+output        status_txdfifo_udflow;
+output        status_rxdfifo_ovflow;
+output        status_rxdfifo_udflow;
+output        status_pause_frame_rx;
+output        status_local_fault;
+output        status_remote_fault;
+
+// End of automatics
+
+/*AUTOWIRE*/
+// Beginning of automatic wires (for undeclared instantiated-module outputs)
+wire                    ctrl_tx_enable_ctx;     // From sync_clk_xgmii_tx0 of sync_clk_xgmii_tx.v
+wire [1:0]              local_fault_msg_det;    // From rx_eq0 of rx_enqueue.v
+wire [1:0]              remote_fault_msg_det;   // From rx_eq0 of rx_enqueue.v
+wire                    rxdfifo_ralmost_empty;  // From rx_data_fifo0 of rx_data_fifo.v
+wire [63:0]             rxdfifo_rdata;          // From rx_data_fifo0 of rx_data_fifo.v
+wire                    rxdfifo_rempty;         // From rx_data_fifo0 of rx_data_fifo.v
+wire                    rxdfifo_ren;            // From rx_dq0 of rx_dequeue.v
+wire [7:0]              rxdfifo_rstatus;        // From rx_data_fifo0 of rx_data_fifo.v
+wire [63:0]             rxdfifo_wdata;          // From rx_eq0 of rx_enqueue.v
+wire                    rxdfifo_wen;            // From rx_eq0 of rx_enqueue.v
+wire                    rxdfifo_wfull;          // From rx_data_fifo0 of rx_data_fifo.v
+wire [7:0]              rxdfifo_wstatus;        // From rx_eq0 of rx_enqueue.v
+wire                    rxhfifo_ralmost_empty;  // From rx_hold_fifo0 of rx_hold_fifo.v
+wire [63:0]             rxhfifo_rdata;          // From rx_hold_fifo0 of rx_hold_fifo.v
+wire                    rxhfifo_rempty;         // From rx_hold_fifo0 of rx_hold_fifo.v
+wire                    rxhfifo_ren;            // From rx_eq0 of rx_enqueue.v
+wire [7:0]              rxhfifo_rstatus;        // From rx_hold_fifo0 of rx_hold_fifo.v
+wire [63:0]             rxhfifo_wdata;          // From rx_eq0 of rx_enqueue.v
+wire                    rxhfifo_wen;            // From rx_eq0 of rx_enqueue.v
+wire [7:0]              rxhfifo_wstatus;        // From rx_eq0 of rx_enqueue.v
+wire                    status_local_fault_ctx; // From sync_clk_xgmii_tx0 of sync_clk_xgmii_tx.v
+wire                    status_remote_fault_ctx;// From sync_clk_xgmii_tx0 of sync_clk_xgmii_tx.v
+wire                    txdfifo_ralmost_empty;  // From tx_data_fifo0 of tx_data_fifo.v
+wire [63:0]             txdfifo_rdata;          // From tx_data_fifo0 of tx_data_fifo.v
+wire                    txdfifo_rempty;         // From tx_data_fifo0 of tx_data_fifo.v
+wire                    txdfifo_ren;            // From tx_dq0 of tx_dequeue.v
+wire [7:0]              txdfifo_rstatus;        // From tx_data_fifo0 of tx_data_fifo.v
+wire                    txdfifo_walmost_full;   // From tx_data_fifo0 of tx_data_fifo.v
+wire [63:0]             txdfifo_wdata;          // From tx_eq0 of tx_enqueue.v
+wire                    txdfifo_wen;            // From tx_eq0 of tx_enqueue.v
+wire                    txdfifo_wfull;          // From tx_data_fifo0 of tx_data_fifo.v
+wire [7:0]              txdfifo_wstatus;        // From tx_eq0 of tx_enqueue.v
+wire                    txhfifo_ralmost_empty;  // From tx_hold_fifo0 of tx_hold_fifo.v
+wire [63:0]             txhfifo_rdata;          // From tx_hold_fifo0 of tx_hold_fifo.v
+wire                    txhfifo_rempty;         // From tx_hold_fifo0 of tx_hold_fifo.v
+wire                    txhfifo_ren;            // From tx_dq0 of tx_dequeue.v
+wire [7:0]              txhfifo_rstatus;        // From tx_hold_fifo0 of tx_hold_fifo.v
+wire                    txhfifo_walmost_full;   // From tx_hold_fifo0 of tx_hold_fifo.v
+wire [63:0]             txhfifo_wdata;          // From tx_dq0 of tx_dequeue.v
+wire                    txhfifo_wen;            // From tx_dq0 of tx_dequeue.v
+wire                    txhfifo_wfull;          // From tx_hold_fifo0 of tx_hold_fifo.v
+wire [7:0]              txhfifo_wstatus;        // From tx_dq0 of tx_dequeue.v
+// End of automatics
+
+rx_enqueue rx_eq0(/*AUTOINST*/
+                  // Outputs
+                  .rxdfifo_wdata        (rxdfifo_wdata[63:0]),
+                  .rxdfifo_wstatus      (rxdfifo_wstatus[7:0]),
+                  .rxdfifo_wen          (rxdfifo_wen),
+                  .rxhfifo_ren          (rxhfifo_ren),
+                  .rxhfifo_wdata        (rxhfifo_wdata[63:0]),
+                  .rxhfifo_wstatus      (rxhfifo_wstatus[7:0]),
+                  .rxhfifo_wen          (rxhfifo_wen),
+                  .local_fault_msg_det  (local_fault_msg_det[1:0]),
+                  .remote_fault_msg_det (remote_fault_msg_det[1:0]),
+                  .status_crc_error_tog (status_crc_error),
+                  .status_fragment_error_tog(status_fragment_error),
+                  .status_rxdfifo_ovflow_tog(status_rxdfifo_ovflow),
+                  .status_pause_frame_rx_tog(status_pause_frame_rx),
+                  // Inputs
+                  .clk_xgmii_rx         (clk_xgmii_rx),
+                  .reset_xgmii_rx_n     (reset_xgmii_rx_n),
+                  .xgmii_rxd            (xgmii_rxd[63:0]),
+                  .xgmii_rxc            (xgmii_rxc[7:0]),
+                  .rxdfifo_wfull        (rxdfifo_wfull),
+                  .rxhfifo_rdata        (rxhfifo_rdata[63:0]),
+                  .rxhfifo_rstatus      (rxhfifo_rstatus[7:0]),
+                  .rxhfifo_rempty       (rxhfifo_rempty),
+                  .rxhfifo_ralmost_empty(rxhfifo_ralmost_empty));
+
+rx_dequeue rx_dq0(/*AUTOINST*/
+                  // Outputs
+                  .rxdfifo_ren          (rxdfifo_ren),
+                  .pkt_rx_data          (pkt_rx_data[63:0]),
+                  .pkt_rx_val           (pkt_rx_val),
+                  .pkt_rx_sop           (pkt_rx_sop),
+                  .pkt_rx_eop           (pkt_rx_eop),
+                  .pkt_rx_err           (pkt_rx_err),
+                  .pkt_rx_mod           (pkt_rx_mod[2:0]),
+                  .pkt_rx_avail         (pkt_rx_avail),
+                  .status_rxdfifo_udflow_tog(status_rxdfifo_udflow),
+                  // Inputs
+                  .clk_156m25           (clk_156m25),
+                  .reset_156m25_n       (reset_156m25_n),
+                  .rxdfifo_rdata        (rxdfifo_rdata[63:0]),
+                  .rxdfifo_rstatus      (rxdfifo_rstatus[7:0]),
+                  .rxdfifo_rempty       (rxdfifo_rempty),
+                  .rxdfifo_ralmost_empty(rxdfifo_ralmost_empty),
+                  .pkt_rx_ren           (pkt_rx_ren));
+
+rx_data_fifo rx_data_fifo0(/*AUTOINST*/
+                           // Outputs
+                           .rxdfifo_wfull       (rxdfifo_wfull),
+                           .rxdfifo_rdata       (rxdfifo_rdata[63:0]),
+                           .rxdfifo_rstatus     (rxdfifo_rstatus[7:0]),
+                           .rxdfifo_rempty      (rxdfifo_rempty),
+                           .rxdfifo_ralmost_empty(rxdfifo_ralmost_empty),
+                           // Inputs
+                           .clk_xgmii_rx        (clk_xgmii_rx),
+                           .clk_156m25          (clk_156m25),
+                           .reset_xgmii_rx_n    (reset_xgmii_rx_n),
+                           .reset_156m25_n      (reset_156m25_n),
+                           .rxdfifo_wdata       (rxdfifo_wdata[63:0]),
+                           .rxdfifo_wstatus     (rxdfifo_wstatus[7:0]),
+                           .rxdfifo_wen         (rxdfifo_wen),
+                           .rxdfifo_ren         (rxdfifo_ren));
+
+rx_hold_fifo rx_hold_fifo0(/*AUTOINST*/
+                           // Outputs
+                           .rxhfifo_rdata       (rxhfifo_rdata[63:0]),
+                           .rxhfifo_rstatus     (rxhfifo_rstatus[7:0]),
+                           .rxhfifo_rempty      (rxhfifo_rempty),
+                           .rxhfifo_ralmost_empty(rxhfifo_ralmost_empty),
+                           // Inputs
+                           .clk_xgmii_rx        (clk_xgmii_rx),
+                           .reset_xgmii_rx_n    (reset_xgmii_rx_n),
+                           .rxhfifo_wdata       (rxhfifo_wdata[63:0]),
+                           .rxhfifo_wstatus     (rxhfifo_wstatus[7:0]),
+                           .rxhfifo_wen         (rxhfifo_wen),
+                           .rxhfifo_ren         (rxhfifo_ren));
+
+tx_enqueue tx_eq0 (/*AUTOINST*/
+                   // Outputs
+                   .pkt_tx_full         (pkt_tx_full),
+                   .txdfifo_wdata       (txdfifo_wdata[63:0]),
+                   .txdfifo_wstatus     (txdfifo_wstatus[7:0]),
+                   .txdfifo_wen         (txdfifo_wen),
+                   .status_txdfifo_ovflow_tog(status_txdfifo_ovflow),
+                   // Inputs
+                   .clk_156m25          (clk_156m25),
+                   .reset_156m25_n      (reset_156m25_n),
+                   .pkt_tx_data         (pkt_tx_data[63:0]),
+                   .pkt_tx_val          (pkt_tx_val),
+                   .pkt_tx_sop          (pkt_tx_sop),
+                   .pkt_tx_eop          (pkt_tx_eop),
+                   .pkt_tx_mod          (pkt_tx_mod[2:0]),
+                   .txdfifo_wfull       (txdfifo_wfull),
+                   .txdfifo_walmost_full(txdfifo_walmost_full));
+
+tx_dequeue tx_dq0(/*AUTOINST*/
+                  // Outputs
+                  .txdfifo_ren          (txdfifo_ren),
+                  .txhfifo_ren          (txhfifo_ren),
+                  .txhfifo_wdata        (txhfifo_wdata[63:0]),
+                  .txhfifo_wstatus      (txhfifo_wstatus[7:0]),
+                  .txhfifo_wen          (txhfifo_wen),
+                  .xgmii_txd            (xgmii_txd[63:0]),
+                  .xgmii_txc            (xgmii_txc[7:0]),
+                  .status_txdfifo_udflow_tog(status_txdfifo_udflow),
+                  // Inputs
+                  .clk_xgmii_tx         (clk_xgmii_tx),
+                  .reset_xgmii_tx_n     (reset_xgmii_tx_n),
+                  .ctrl_tx_enable_ctx   (ctrl_tx_enable_ctx),
+                  .status_local_fault_ctx(status_local_fault_ctx),
+                  .status_remote_fault_ctx(status_remote_fault_ctx),
+                  .txdfifo_rdata        (txdfifo_rdata[63:0]),
+                  .txdfifo_rstatus      (txdfifo_rstatus[7:0]),
+                  .txdfifo_rempty       (txdfifo_rempty),
+                  .txdfifo_ralmost_empty(txdfifo_ralmost_empty),
+                  .txhfifo_rdata        (txhfifo_rdata[63:0]),
+                  .txhfifo_rstatus      (txhfifo_rstatus[7:0]),
+                  .txhfifo_rempty       (txhfifo_rempty),
+                  .txhfifo_ralmost_empty(txhfifo_ralmost_empty),
+                  .txhfifo_wfull        (txhfifo_wfull),
+                  .txhfifo_walmost_full (txhfifo_walmost_full));
+
+tx_data_fifo tx_data_fifo0(/*AUTOINST*/
+                           // Outputs
+                           .txdfifo_wfull       (txdfifo_wfull),
+                           .txdfifo_walmost_full(txdfifo_walmost_full),
+                           .txdfifo_rdata       (txdfifo_rdata[63:0]),
+                           .txdfifo_rstatus     (txdfifo_rstatus[7:0]),
+                           .txdfifo_rempty      (txdfifo_rempty),
+                           .txdfifo_ralmost_empty(txdfifo_ralmost_empty),
+                           // Inputs
+                           .clk_xgmii_tx        (clk_xgmii_tx),
+                           .clk_156m25          (clk_156m25),
+                           .reset_xgmii_tx_n    (reset_xgmii_tx_n),
+                           .reset_156m25_n      (reset_156m25_n),
+                           .txdfifo_wdata       (txdfifo_wdata[63:0]),
+                           .txdfifo_wstatus     (txdfifo_wstatus[7:0]),
+                           .txdfifo_wen         (txdfifo_wen),
+                           .txdfifo_ren         (txdfifo_ren));
+
+tx_hold_fifo tx_hold_fifo0(/*AUTOINST*/
+                           // Outputs
+                           .txhfifo_wfull       (txhfifo_wfull),
+                           .txhfifo_walmost_full(txhfifo_walmost_full),
+                           .txhfifo_rdata       (txhfifo_rdata[63:0]),
+                           .txhfifo_rstatus     (txhfifo_rstatus[7:0]),
+                           .txhfifo_rempty      (txhfifo_rempty),
+                           .txhfifo_ralmost_empty(txhfifo_ralmost_empty),
+                           // Inputs
+                           .clk_xgmii_tx        (clk_xgmii_tx),
+                           .reset_xgmii_tx_n    (reset_xgmii_tx_n),
+                           .txhfifo_wdata       (txhfifo_wdata[63:0]),
+                           .txhfifo_wstatus     (txhfifo_wstatus[7:0]),
+                           .txhfifo_wen         (txhfifo_wen),
+                           .txhfifo_ren         (txhfifo_ren));
+
+fault_sm fault_sm0(/*AUTOINST*/
+                   // Outputs
+                   .status_local_fault_crx(status_local_fault),
+                   .status_remote_fault_crx(status_remote_fault),
+                   // Inputs
+                   .clk_xgmii_rx        (clk_xgmii_rx),
+                   .reset_xgmii_rx_n    (reset_xgmii_rx_n),
+                   .local_fault_msg_det (local_fault_msg_det[1:0]),
+                   .remote_fault_msg_det(remote_fault_msg_det[1:0]));
+
+sync_clk_xgmii_tx sync_clk_xgmii_tx0(/*AUTOINST*/
+                                     // Outputs
+                                     .ctrl_tx_enable_ctx(ctrl_tx_enable_ctx),
+                                     .status_local_fault_ctx(status_local_fault_ctx),
+                                     .status_remote_fault_ctx(status_remote_fault_ctx),
+                                     // Inputs
+                                     .clk_xgmii_tx      (clk_xgmii_tx),
+                                     .reset_xgmii_tx_n  (reset_xgmii_tx_n),
+                                     .ctrl_tx_enable    (ctrl_tx_enable),
+                                     .status_local_fault_crx(status_local_fault),
+                                     .status_remote_fault_crx(status_remote_fault));
+
+// IJB. This module has only inputs and is treated as a black box by XST which causes a fatal error.
+// Commented out. Original pupose/intent unknown.
+//sync_clk_core sync_clk_core0(/*AUTOINST*/
+//                             // Inputs
+//                            .clk_xgmii_tx      (clk_xgmii_tx),
+//                             .reset_xgmii_tx_n  (reset_xgmii_tx_n));
+
+endmodule
diff --git a/fpga/usrp3/lib/xge/rtl/verilog/xge_mac_wb.v b/fpga/usrp3/lib/xge/rtl/verilog/xge_mac_wb.v
new file mode 100644
index 000000000..615602db9
--- /dev/null
+++ b/fpga/usrp3/lib/xge/rtl/verilog/xge_mac_wb.v
@@ -0,0 +1,229 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  File name "xge_mac_wb.v"                                       ////
+////                                                              ////
+////  This file is part of the "10GE MAC" project                 ////
+////  http://www.opencores.org/cores/xge_mac/                     ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - A. Tanguay (antanguay@opencores.org)                  ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2008 AUTHORS. All rights reserved.             ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+
+module xge_mac_wb (
+  // Outputs
+  xgmii_txd, xgmii_txc, pkt_tx_full,
+  pkt_rx_val, pkt_rx_sop, pkt_rx_mod, pkt_rx_err, pkt_rx_eop,
+  pkt_rx_data, pkt_rx_avail,
+  wb_int_o, wb_dat_o, wb_ack_o,
+  mdc, mdio_out, mdio_tri, xge_gpo,
+
+  // Inputs
+  xgmii_rxd, xgmii_rxc,
+  wb_we_i, wb_stb_i, wb_rst_i, wb_dat_i,
+  wb_cyc_i, wb_clk_i, wb_adr_i,
+  reset_xgmii_tx_n, reset_xgmii_rx_n, reset_156m25_n,
+  pkt_tx_val, pkt_tx_sop, pkt_tx_mod, pkt_tx_eop,
+  pkt_tx_data, pkt_rx_ren,
+  clk_xgmii_tx, clk_xgmii_rx, clk_156m25,
+  mdio_in, xge_gpi
+);
+
+  input                   clk_156m25;             // To rx_dq0 of rx_dequeue.v, ...
+  input                   clk_xgmii_rx;           // To rx_eq0 of rx_enqueue.v, ...
+  input                   clk_xgmii_tx;           // To tx_dq0 of tx_dequeue.v, ...
+  input                   pkt_rx_ren;             // To rx_dq0 of rx_dequeue.v
+  input [63:0]            pkt_tx_data;            // To tx_eq0 of tx_enqueue.v
+  input                   pkt_tx_eop;             // To tx_eq0 of tx_enqueue.v
+  input [2:0]             pkt_tx_mod;             // To tx_eq0 of tx_enqueue.v
+  input                   pkt_tx_sop;             // To tx_eq0 of tx_enqueue.v
+  input                   pkt_tx_val;             // To tx_eq0 of tx_enqueue.v
+  input                   reset_156m25_n;         // To rx_dq0 of rx_dequeue.v, ...
+  input                   reset_xgmii_rx_n;       // To rx_eq0 of rx_enqueue.v, ...
+  input                   reset_xgmii_tx_n;       // To tx_dq0 of tx_dequeue.v, ...
+  input [7:0]             wb_adr_i;               // To wishbone_if0 of wishbone_if.v
+  input                   wb_clk_i;               // To sync_clk_wb0 of sync_clk_wb.v, ...
+  input                   wb_cyc_i;               // To wishbone_if0 of wishbone_if.v
+  input [31:0]            wb_dat_i;               // To wishbone_if0 of wishbone_if.v
+  input                   wb_rst_i;               // To sync_clk_wb0 of sync_clk_wb.v, ...
+  input                   wb_stb_i;               // To wishbone_if0 of wishbone_if.v
+  input                   wb_we_i;                // To wishbone_if0 of wishbone_if.v
+  input [7:0]             xgmii_rxc;              // To rx_eq0 of rx_enqueue.v
+  input [63:0]            xgmii_rxd;              // To rx_eq0 of rx_enqueue.v
+  input 		          mdio_in;
+  input [7:0]		      xge_gpi;
+
+  output                  pkt_rx_avail;           // From rx_dq0 of rx_dequeue.v
+  output [63:0]           pkt_rx_data;            // From rx_dq0 of rx_dequeue.v
+  output                  pkt_rx_eop;             // From rx_dq0 of rx_dequeue.v
+  output                  pkt_rx_err;             // From rx_dq0 of rx_dequeue.v
+  output [2:0]            pkt_rx_mod;             // From rx_dq0 of rx_dequeue.v
+  output                  pkt_rx_sop;             // From rx_dq0 of rx_dequeue.v
+  output                  pkt_rx_val;             // From rx_dq0 of rx_dequeue.v
+  output                  pkt_tx_full;            // From tx_eq0 of tx_enqueue.v
+  output                  wb_ack_o;               // From wishbone_if0 of wishbone_if.v
+  output [31:0]           wb_dat_o;               // From wishbone_if0 of wishbone_if.v
+  output                  wb_int_o;               // From wishbone_if0 of wishbone_if.v
+  output [7:0]            xgmii_txc;              // From tx_dq0 of tx_dequeue.v
+  output [63:0]           xgmii_txd;              // From tx_dq0 of tx_dequeue.v
+  output                  mdc;
+  output                  mdio_out;
+  output                  mdio_tri;               // Assert to tristate driver.
+  output [7:0] 	          xge_gpo;
+
+  wire                    ctrl_tx_enable;         // From wishbone_if0 of wishbone_if.v
+  wire                    ctrl_tx_enable_ctx;     // From sync_clk_xgmii_tx0 of sync_clk_xgmii_tx.v
+  wire                    status_local_fault_ctx; // From sync_clk_xgmii_tx0 of sync_clk_xgmii_tx.v
+  wire                    status_remote_fault_ctx;// From sync_clk_xgmii_tx0 of sync_clk_xgmii_tx.v
+  wire                    status_crc_error;       // From sync_clk_wb0 of sync_clk_wb.v
+  wire                    status_crc_error_tog;   // From rx_eq0 of rx_enqueue.v
+  wire                    status_fragment_error;  // From sync_clk_wb0 of sync_clk_wb.v
+  wire                    status_fragment_error_tog;// From rx_eq0 of rx_enqueue.v
+  wire                    status_local_fault;     // From sync_clk_wb0 of sync_clk_wb.v
+  wire                    status_local_fault_crx; // From fault_sm0 of fault_sm.v
+  wire                    status_pause_frame_rx;  // From sync_clk_wb0 of sync_clk_wb.v
+  wire                    status_pause_frame_rx_tog;// From rx_eq0 of rx_enqueue.v
+  wire                    status_remote_fault;    // From sync_clk_wb0 of sync_clk_wb.v
+  wire                    status_remote_fault_crx;// From fault_sm0 of fault_sm.v
+  wire                    status_rxdfifo_ovflow;  // From sync_clk_wb0 of sync_clk_wb.v
+  wire                    status_rxdfifo_ovflow_tog;// From rx_eq0 of rx_enqueue.v
+  wire                    status_rxdfifo_udflow;  // From sync_clk_wb0 of sync_clk_wb.v
+  wire                    status_rxdfifo_udflow_tog;// From rx_dq0 of rx_dequeue.v
+  wire                    status_txdfifo_ovflow;  // From sync_clk_wb0 of sync_clk_wb.v
+  wire                    status_txdfifo_ovflow_tog;// From tx_eq0 of tx_enqueue.v
+  wire                    status_txdfifo_udflow;  // From sync_clk_wb0 of sync_clk_wb.v
+  wire                    status_txdfifo_udflow_tog;// From tx_dq0 of tx_dequeue.v
+
+  xge_mac xge_mac (
+    // Clocks and Resets
+    .clk_156m25             (clk_156m25),
+    .clk_xgmii_rx           (clk_xgmii_rx),
+    .clk_xgmii_tx           (clk_xgmii_tx),
+    .reset_156m25_n         (reset_156m25_n),
+    .reset_xgmii_rx_n       (reset_xgmii_rx_n),
+    .reset_xgmii_tx_n       (reset_xgmii_tx_n),
+    // XGMII
+    .xgmii_txc              (xgmii_txc[7:0]),
+    .xgmii_txd              (xgmii_txd[63:0]),
+    .xgmii_rxc              (xgmii_rxc[7:0]),
+    .xgmii_rxd              (xgmii_rxd[63:0]),
+    // Packet interface
+    .pkt_rx_avail           (pkt_rx_avail),
+    .pkt_rx_data            (pkt_rx_data),
+    .pkt_rx_eop             (pkt_rx_eop),
+    .pkt_rx_err             (pkt_rx_err),
+    .pkt_rx_mod             (pkt_rx_mod),
+    .pkt_rx_sop             (pkt_rx_sop),
+    .pkt_rx_val             (pkt_rx_val),
+    .pkt_tx_full            (pkt_tx_full),
+    // Inputs
+    .pkt_rx_ren             (pkt_rx_ren),
+    .pkt_tx_data            (pkt_tx_data),
+    .pkt_tx_eop             (pkt_tx_eop),
+    .pkt_tx_mod             (pkt_tx_mod),
+    .pkt_tx_sop             (pkt_tx_sop),
+    .pkt_tx_val             (pkt_tx_val),
+    // Control and Status
+    .ctrl_tx_enable         (ctrl_tx_enable),
+    .status_crc_error       (status_crc_error_tog),
+    .status_fragment_error  (status_fragment_error_tog),
+    .status_txdfifo_ovflow  (status_txdfifo_ovflow_tog),
+    .status_txdfifo_udflow  (status_txdfifo_udflow_tog),
+    .status_rxdfifo_ovflow  (status_rxdfifo_ovflow_tog),
+    .status_rxdfifo_udflow  (status_rxdfifo_udflow_tog),
+    .status_pause_frame_rx  (status_pause_frame_rx_tog),
+    .status_local_fault     (status_local_fault_crx),
+    .status_remote_fault    (status_remote_fault_crx)
+  );
+
+  sync_clk_wb sync_clk_wb0 (
+    // Outputs
+    .status_crc_error      (status_crc_error),
+    .status_fragment_error (status_fragment_error),
+    .status_txdfifo_ovflow (status_txdfifo_ovflow),
+    .status_txdfifo_udflow (status_txdfifo_udflow),
+    .status_rxdfifo_ovflow (status_rxdfifo_ovflow),
+    .status_rxdfifo_udflow (status_rxdfifo_udflow),
+    .status_pause_frame_rx (status_pause_frame_rx),
+    .status_local_fault    (status_local_fault),
+    .status_remote_fault   (status_remote_fault),
+    // Inputs
+    .wb_clk_i              (wb_clk_i),
+    .wb_rst_i              (wb_rst_i),
+    .status_crc_error_tog  (status_crc_error_tog),
+    .status_fragment_error_tog(status_fragment_error_tog),
+    .status_txdfifo_ovflow_tog(status_txdfifo_ovflow_tog),
+    .status_txdfifo_udflow_tog(status_txdfifo_udflow_tog),
+    .status_rxdfifo_ovflow_tog(status_rxdfifo_ovflow_tog),
+    .status_rxdfifo_udflow_tog(status_rxdfifo_udflow_tog),
+    .status_pause_frame_rx_tog(status_pause_frame_rx_tog),
+    .status_local_fault_crx(status_local_fault_crx),
+    .status_remote_fault_crx(status_remote_fault_crx)
+  );
+
+
+// IJB. This module has only inputs and is treated as a black box by XST which causes a fatal error.
+// Commented out. Original pupose/intent unknown.
+//sync_clk_core sync_clk_core0(/*AUTOINST*/
+//                             // Inputs
+//                            .clk_xgmii_tx      (clk_xgmii_tx),
+//                             .reset_xgmii_tx_n  (reset_xgmii_tx_n));
+  wishbone_if wishbone_if0 (
+    // Outputs
+    .wb_dat_o              (wb_dat_o[31:0]),
+    .wb_ack_o              (wb_ack_o),
+    .wb_int_o              (wb_int_o),
+    .ctrl_tx_enable        (ctrl_tx_enable),
+    // Inputs
+    .wb_clk_i              (wb_clk_i),
+    .wb_rst_i              (wb_rst_i),
+    .wb_adr_i              (wb_adr_i[7:0]),
+    .wb_dat_i              (wb_dat_i[31:0]),
+    .wb_we_i               (wb_we_i),
+    .wb_stb_i              (wb_stb_i),
+    .wb_cyc_i              (wb_cyc_i),
+    .status_crc_error      (status_crc_error),
+    .status_fragment_error (status_fragment_error),
+    .status_txdfifo_ovflow (status_txdfifo_ovflow),
+    .status_txdfifo_udflow (status_txdfifo_udflow),
+    .status_rxdfifo_ovflow (status_rxdfifo_ovflow),
+    .status_rxdfifo_udflow (status_rxdfifo_udflow),
+    .status_pause_frame_rx (status_pause_frame_rx),
+    .status_local_fault    (status_local_fault),
+    .status_remote_fault   (status_remote_fault),
+    // MDIO
+    .mdc(mdc),
+    .mdio_in(mdio_in),
+    .mdio_out(mdio_out),
+    .mdio_tri(mdio_tri),
+    .xge_gpo(xge_gpo),
+    .xge_gpi(xge_gpi)
+  );
+
+endmodule
diff --git a/fpga/usrp3/lib/xge/sim/verilog/xge_mac.prj b/fpga/usrp3/lib/xge/sim/verilog/xge_mac.prj
new file mode 100644
index 000000000..b99046a72
--- /dev/null
+++ b/fpga/usrp3/lib/xge/sim/verilog/xge_mac.prj
@@ -0,0 +1,43 @@
+verilog work ../../rtl/verilog/fault_sm.v -i ../../rtl/include
+
+verilog work ../../rtl/verilog/generic_mem_small.v -i ../../rtl/include
+
+verilog work ../../rtl/verilog/generic_mem_medium.v -i ../../rtl/include
+
+verilog work ../../rtl/verilog/generic_fifo_ctrl.v -i ../../rtl/include
+
+verilog work ../../rtl/verilog/generic_fifo.v -i ../../rtl/include
+
+verilog work ../../rtl/verilog/meta_sync.v -i ../../rtl/include
+
+verilog work ../../rtl/verilog/meta_sync_single.v -i ../../rtl/include
+
+verilog work ../../rtl/verilog/rx_hold_fifo.v -i ../../rtl/include
+
+verilog work ../../rtl/verilog/rx_data_fifo.v -i ../../rtl/include
+
+verilog work ../../rtl/verilog/rx_dequeue.v -i ../../rtl/include
+
+verilog work ../../rtl/verilog/rx_enqueue.v -i ../../rtl/include
+
+verilog work ../../rtl/verilog/sync_clk_core.v -i ../../rtl/include
+
+verilog work ../../rtl/verilog/sync_clk_wb.v -i ../../rtl/include
+
+verilog work ../../rtl/verilog/sync_clk_xgmii_tx.v -i ../../rtl/include
+
+verilog work ../../rtl/verilog/tx_hold_fifo.v -i ../../rtl/include
+
+verilog work ../../rtl/verilog/tx_data_fifo.v -i ../../rtl/include
+
+verilog work ../../rtl/verilog/tx_dequeue.v -i ../../rtl/include
+
+verilog work ../../rtl/verilog/tx_enqueue.v -i ../../rtl/include
+
+verilog work ../../rtl/verilog/wishbone_if.v -i ../../rtl/include
+
+verilog work ../../rtl/verilog/xge_mac.v -i ../../rtl/include
+
+verilog work ../../tbench/verilog/tb_xge_mac.v -i ../../rtl/include
+
+
diff --git a/fpga/usrp3/lib/xge/tbench/verilog/packets_tx.txt b/fpga/usrp3/lib/xge/tbench/verilog/packets_tx.txt
new file mode 100644
index 000000000..8e8411c97
--- /dev/null
+++ b/fpga/usrp3/lib/xge/tbench/verilog/packets_tx.txt
@@ -0,0 +1,73 @@
+SEND_PKT
+59
+00 00 01 00 00 01 00 10 94 00 00 02 88 b5 00 01
+02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11
+12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21
+22 23 24 25 26 27 28 29 2a 2b 2c
+
+SEND_PKT
+60
+00 00 01 00 00 01 00 10 94 00 00 02 88 b5 00 01
+02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11
+12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21
+22 23 24 25 26 27 28 29 2a 2b 2c 2d
+
+SEND_PKT
+61
+00 00 01 00 00 01 00 10 94 00 00 02 88 b5 00 01
+02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11
+12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21
+22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e
+
+SEND_PKT
+62
+00 00 01 00 00 01 00 10 94 00 00 02 88 b5 00 01
+02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11
+12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21
+22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f
+
+SEND_PKT
+63
+00 00 01 00 00 01 00 10 94 00 00 02 88 b5 00 01
+02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11
+12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21
+22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 30
+
+SEND_PKT
+64
+00 00 01 00 00 01 00 10 94 00 00 02 88 b5 00 01
+02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11
+12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21
+22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 30 31
+
+SEND_PKT
+65
+00 00 01 00 00 01 00 10 94 00 00 02 88 b5 00 01
+02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11
+12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21
+22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 30 31
+32
+
+SEND_PKT
+66
+00 00 01 00 00 01 00 10 94 00 00 02 88 b5 00 01
+02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11
+12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21
+22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 30 31
+32 33
+
+SEND_PKT
+67
+00 00 01 00 00 01 00 10 94 00 00 02 88 b5 00 01
+02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11
+12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21
+22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 30 31
+32 33 34
+
+SEND_PKT
+68
+00 00 01 00 00 01 00 10 94 00 00 02 88 b5 00 01
+02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11
+12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21
+22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 30 31
+32 33 34 35
diff --git a/fpga/usrp3/lib/xge/tbench/verilog/tb_xge_mac.v b/fpga/usrp3/lib/xge/tbench/verilog/tb_xge_mac.v
new file mode 100644
index 000000000..bb3de297c
--- /dev/null
+++ b/fpga/usrp3/lib/xge/tbench/verilog/tb_xge_mac.v
@@ -0,0 +1,514 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  File name "tb_xge_mac.v"                                    ////
+////                                                              ////
+////  This file is part of the "10GE MAC" project                 ////
+////  http://www.opencores.org/cores/xge_mac/                     ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - A. Tanguay (antanguay@opencores.org)                  ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2008 AUTHORS. All rights reserved.             ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+ 
+ 
+`include "timescale.v"
+`include "defines.v"
+ 
+//`define GXB
+//`define XIL
+ 
+module tb;
+ 
+ 
+/*AUTOREG*/
+ 
+reg [7:0]     tx_buffer[0:10000];
+integer       tx_length;
+ 
+reg           clk_156m25;
+reg           clk_312m50;
+reg           clk_xgmii_rx;
+reg           clk_xgmii_tx;
+ 
+reg           reset_156m25_n;
+reg           reset_xgmii_rx_n;
+reg           reset_xgmii_tx_n;
+ 
+reg           pkt_rx_ren;
+ 
+reg  [63:0]   pkt_tx_data;
+reg           pkt_tx_val;
+reg           pkt_tx_sop;
+reg           pkt_tx_eop;
+reg  [2:0]    pkt_tx_mod;
+ 
+/*AUTOWIRE*/
+// Beginning of automatic wires (for undeclared instantiated-module outputs)
+wire                    pkt_rx_avail;           // From dut of xge_mac.v
+wire [63:0]             pkt_rx_data;            // From dut of xge_mac.v
+wire                    pkt_rx_eop;             // From dut of xge_mac.v
+wire                    pkt_rx_err;             // From dut of xge_mac.v
+wire [2:0]              pkt_rx_mod;             // From dut of xge_mac.v
+wire                    pkt_rx_sop;             // From dut of xge_mac.v
+wire                    pkt_rx_val;             // From dut of xge_mac.v
+wire                    pkt_tx_full;            // From dut of xge_mac.v
+wire                    wb_ack_o;               // From dut of xge_mac.v
+wire [31:0]             wb_dat_o;               // From dut of xge_mac.v
+wire                    wb_int_o;               // From dut of xge_mac.v
+wire [7:0]              xgmii_txc;              // From dut of xge_mac.v
+wire [63:0]             xgmii_txd;              // From dut of xge_mac.v
+// End of automatics
+ 
+wire  [7:0]   wb_adr_i;
+wire  [31:0]  wb_dat_i;
+ 
+wire [7:0]              xgmii_rxc;
+wire [63:0]             xgmii_rxd;
+ 
+wire [3:0]              tx_dataout;
+ 
+wire                    xaui_tx_l0_n;
+wire                    xaui_tx_l0_p;
+wire                    xaui_tx_l1_n;
+wire                    xaui_tx_l1_p;
+wire                    xaui_tx_l2_n;
+wire                    xaui_tx_l2_p;
+wire                    xaui_tx_l3_n;
+wire                    xaui_tx_l3_p;
+ 
+xge_mac dut(/*AUTOINST*/
+            // Outputs
+            .pkt_rx_avail               (pkt_rx_avail),
+            .pkt_rx_data                (pkt_rx_data[63:0]),
+            .pkt_rx_eop                 (pkt_rx_eop),
+            .pkt_rx_err                 (pkt_rx_err),
+            .pkt_rx_mod                 (pkt_rx_mod[2:0]),
+            .pkt_rx_sop                 (pkt_rx_sop),
+            .pkt_rx_val                 (pkt_rx_val),
+            .pkt_tx_full                (pkt_tx_full),
+            .wb_ack_o                   (wb_ack_o),
+            .wb_dat_o                   (wb_dat_o[31:0]),
+            .wb_int_o                   (wb_int_o),
+            .xgmii_txc                  (xgmii_txc[7:0]),
+            .xgmii_txd                  (xgmii_txd[63:0]),
+            // Inputs
+            .clk_156m25                 (clk_156m25),
+            .clk_xgmii_rx               (clk_xgmii_rx),
+            .clk_xgmii_tx               (clk_xgmii_tx),
+            .pkt_rx_ren                 (pkt_rx_ren),
+            .pkt_tx_data                (pkt_tx_data[63:0]),
+            .pkt_tx_eop                 (pkt_tx_eop),
+            .pkt_tx_mod                 (pkt_tx_mod[2:0]),
+            .pkt_tx_sop                 (pkt_tx_sop),
+            .pkt_tx_val                 (pkt_tx_val),
+            .reset_156m25_n             (reset_156m25_n),
+            .reset_xgmii_rx_n           (reset_xgmii_rx_n),
+            .reset_xgmii_tx_n           (reset_xgmii_tx_n),
+            .wb_adr_i                   (wb_adr_i[7:0]),
+            .wb_clk_i                   (wb_clk_i),
+            .wb_cyc_i                   (wb_cyc_i),
+            .wb_dat_i                   (wb_dat_i[31:0]),
+            .wb_rst_i                   (wb_rst_i),
+            .wb_stb_i                   (wb_stb_i),
+            .wb_we_i                    (wb_we_i),
+            .xgmii_rxc                  (xgmii_rxc[7:0]),
+            .xgmii_rxd                  (xgmii_rxd[63:0]));
+ 
+`ifdef GXB
+// Example of transceiver instance
+gxb gxb(// Outputs
+        .rx_ctrldetect                  ({xgmii_rxc[7],
+                                          xgmii_rxc[5],
+                                          xgmii_rxc[3],
+                                          xgmii_rxc[1],
+                                          xgmii_rxc[6],
+                                          xgmii_rxc[4],
+                                          xgmii_rxc[2],
+                                          xgmii_rxc[0]}),
+        .rx_dataout                     ({xgmii_rxd[63:56],
+                                          xgmii_rxd[47:40],
+                                          xgmii_rxd[31:24],
+                                          xgmii_rxd[15:8],
+                                          xgmii_rxd[55:48],
+                                          xgmii_rxd[39:32],
+                                          xgmii_rxd[23:16],
+                                          xgmii_rxd[7:0]}),
+        .tx_dataout                     (tx_dataout[3:0]),
+        // Inputs
+        .pll_inclk                      (clk_156m25),
+        .rx_analogreset                 (~reset_156m25_n),
+        .rx_cruclk                      ({clk_156m25, clk_156m25, clk_156m25, clk_156m25}),
+        .rx_datain                      (tx_dataout[3:0]),
+        .rx_digitalreset                (~reset_156m25_n),
+        .tx_ctrlenable                  ({xgmii_txc[7],
+                                          xgmii_txc[5],
+                                          xgmii_txc[3],
+                                          xgmii_txc[1],
+                                          xgmii_txc[6],
+                                          xgmii_txc[4],
+                                          xgmii_txc[2],
+                                          xgmii_txc[0]}),
+        .tx_datain                      ({xgmii_txd[63:56],
+                                          xgmii_txd[47:40],
+                                          xgmii_txd[31:24],
+                                          xgmii_txd[15:8],
+                                          xgmii_txd[55:48],
+                                          xgmii_txd[39:32],
+                                          xgmii_txd[23:16],
+                                          xgmii_txd[7:0]}),
+        .tx_digitalreset                (~reset_156m25_n));
+`endif
+ 
+`ifdef XIL
+// Example of transceiver instance
+xaui_block xaui(// Outputs
+                .txoutclk               (),
+                .xgmii_rxd              (xgmii_rxd[63:0]),
+                .xgmii_rxc              (xgmii_rxc[7:0]),
+                .xaui_tx_l0_p           (xaui_tx_l0_p),
+                .xaui_tx_l0_n           (xaui_tx_l0_n),
+                .xaui_tx_l1_p           (xaui_tx_l1_p),
+                .xaui_tx_l1_n           (xaui_tx_l1_n),
+                .xaui_tx_l2_p           (xaui_tx_l2_p),
+                .xaui_tx_l2_n           (xaui_tx_l2_n),
+                .xaui_tx_l3_p           (xaui_tx_l3_p),
+                .xaui_tx_l3_n           (xaui_tx_l3_n),
+                .txlock                 (),
+                .align_status           (),
+                .sync_status            (),
+                .mgt_tx_ready           (),
+                .drp_o                  (),
+                .drp_rdy                (),
+                .status_vector          (),
+                // Inputs
+                .dclk                   (clk_156m25),
+                .clk156                 (clk_156m25),
+                .clk312                 (clk_312m50),
+                .refclk                 (clk_156m25),
+                .reset                  (~reset_156m25_n),
+                .reset156               (~reset_156m25_n),
+                .xgmii_txd              (xgmii_txd[63:0]),
+                .xgmii_txc              (xgmii_txc[7:0]),
+                .xaui_rx_l0_p           (xaui_tx_l0_p),
+                .xaui_rx_l0_n           (xaui_tx_l0_n),
+                .xaui_rx_l1_p           (xaui_tx_l1_p),
+                .xaui_rx_l1_n           (xaui_tx_l1_n),
+                .xaui_rx_l2_p           (xaui_tx_l2_p),
+                .xaui_rx_l2_n           (xaui_tx_l2_n),
+                .xaui_rx_l3_p           (xaui_tx_l3_p),
+                .xaui_rx_l3_n           (xaui_tx_l3_n),
+                .signal_detect          (4'b1111),
+                .drp_addr               (7'b0),
+                .drp_en                 (2'b0),
+                .drp_i                  (16'b0),
+                .drp_we                 (2'b0),
+                .configuration_vector   (7'b0));
+ 
+glbl glbl();
+`endif
+ 
+//---
+// Unused for this testbench
+ 
+assign wb_adr_i = 8'b0;
+assign wb_clk_i = 1'b0;
+assign wb_cyc_i = 1'b0;
+assign wb_dat_i = 32'b0;
+assign wb_rst_i = 1'b1;
+assign wb_stb_i = 1'b0;
+assign wb_we_i = 1'b0;
+ 
+ 
+//---
+// XGMII Loopback
+// This test is done with loopback on XGMII or using one of the tranceiver examples
+ 
+`ifndef GXB
+  `ifndef XIL
+    assign xgmii_rxc = xgmii_txc;
+    assign xgmii_rxd = xgmii_txd;
+  `endif
+`endif
+ 
+//---
+// Clock generation
+ 
+initial begin
+    clk_156m25 = 1'b0;
+    clk_xgmii_rx = 1'b0;
+    clk_xgmii_tx = 1'b0;
+    forever begin
+        WaitPS(3200);
+        clk_156m25 = ~clk_156m25;
+        clk_xgmii_rx = ~clk_xgmii_rx;
+        clk_xgmii_tx = ~clk_xgmii_tx;
+    end
+end
+ 
+initial begin
+    clk_312m50 = 1'b0;
+    forever begin
+        WaitPS(1600);
+        clk_312m50 = ~clk_312m50;
+    end
+end
+ 
+//---
+// Reset Generation
+ 
+initial begin
+    reset_156m25_n = 1'b0;
+    reset_xgmii_rx_n = 1'b0;
+    reset_xgmii_tx_n = 1'b0;
+    WaitNS(20);
+    reset_156m25_n = 1'b1;
+    reset_xgmii_rx_n = 1'b1;
+    reset_xgmii_tx_n = 1'b1;
+end
+ 
+ 
+//---
+// Init signals
+ 
+initial begin
+ 
+    for (tx_length = 0; tx_length <= 1000; tx_length = tx_length + 1) begin
+        tx_buffer[tx_length] = 0;
+    end
+ 
+    pkt_rx_ren = 1'b0;
+ 
+    pkt_tx_data = 64'b0;
+    pkt_tx_val = 1'b0;
+    pkt_tx_sop = 1'b0;
+    pkt_tx_eop = 1'b0;
+    pkt_tx_mod = 3'b0;
+ 
+end
+ 
+task WaitNS;
+  input [31:0] delay;
+    begin
+        #(1000*delay);
+    end
+endtask
+ 
+task WaitPS;
+  input [31:0] delay;
+    begin
+        #(delay);
+    end
+endtask
+ 
+ 
+//---
+// Task to send a single packet
+ 
+task TxPacket;
+  integer        i;
+    begin
+ 
+        $display("Transmit packet with length: %d", tx_length);
+ 
+        @(posedge clk_156m25);
+        WaitNS(1);
+        pkt_tx_val = 1'b1;
+ 
+        for (i = 0; i < tx_length; i = i + 8) begin
+ 
+            pkt_tx_sop = 1'b0;
+            pkt_tx_eop = 1'b0;
+            pkt_tx_mod = 2'b0;
+ 
+            if (i == 0) pkt_tx_sop = 1'b1;
+ 
+            if (i + 8 >= tx_length) begin
+                pkt_tx_eop = 1'b1;
+                pkt_tx_mod = tx_length % 8;
+            end
+ 
+            pkt_tx_data[`LANE7] = tx_buffer[i];
+            pkt_tx_data[`LANE6] = tx_buffer[i+1];
+            pkt_tx_data[`LANE5] = tx_buffer[i+2];
+            pkt_tx_data[`LANE4] = tx_buffer[i+3];
+            pkt_tx_data[`LANE3] = tx_buffer[i+4];
+            pkt_tx_data[`LANE2] = tx_buffer[i+5];
+            pkt_tx_data[`LANE1] = tx_buffer[i+6];
+            pkt_tx_data[`LANE0] = tx_buffer[i+7];
+ 
+            @(posedge clk_156m25);
+            WaitNS(1);
+ 
+        end
+ 
+        pkt_tx_val = 1'b0;
+        pkt_tx_eop = 1'b0;
+        pkt_tx_mod = 3'b0;
+ 
+    end
+ 
+endtask
+ 
+ 
+//---
+// Task to read a single packet from command file and transmit
+ 
+task CmdTxPacket;
+  input [31:0] file;
+  integer count;
+  integer data;
+  integer i;
+    begin
+ 
+        count = $fscanf(file, "%2d", tx_length);
+ 
+        if (count == 1) begin
+ 
+            for (i = 0; i < tx_length; i = i + 1) begin
+ 
+                count = $fscanf(file, "%2X", data);
+                if (count) begin
+                    tx_buffer[i] = data;
+                end
+ 
+            end
+ 
+            TxPacket();
+ 
+        end
+    end
+ 
+endtask
+ 
+ 
+//---
+// Task to read commands from file and stop when complete
+ 
+task ProcessCmdFile;
+  integer    file_cmd;
+  integer  count;
+  reg [8*8-1:0] str;
+    begin
+ 
+        file_cmd = $fopen("../../tbench/verilog/packets_tx.txt", "r");
+        if (!file_cmd) $stop;
+ 
+        while (!$feof(file_cmd)) begin
+ 
+            count = $fscanf(file_cmd, "%s", str);
+       // IJB. WTF!    if (count != 1) $continue;
+	   if (count === 1) // IJB. I think this is what's intended.
+	     begin
+	   
+		$display("CMD %s", str);
+ 
+		case (str)
+ 
+		  "SEND_PKT":
+                    begin
+                       CmdTxPacket(file_cmd);
+                    end
+ 
+		endcase // case(str)
+	     end
+ 
+        end
+ 
+        $fclose(file_cmd);
+ 
+        WaitNS(50000);
+        $stop;
+ 
+    end
+endtask
+ 
+initial begin
+    WaitNS(5000);
+`ifdef XIL
+    WaitNS(200000);
+`endif
+    ProcessCmdFile();
+end
+ 
+ 
+//---
+// Task to read a single packet from receive interface and display
+ 
+task RxPacket;
+  reg done;
+    begin
+ 
+        done = 0;
+ 
+        pkt_rx_ren <= 1'b1;
+        @(posedge clk_156m25);
+ 
+        while (!done) begin
+ 
+            if (pkt_rx_val) begin
+ 
+                if (pkt_rx_sop) begin
+                    $display("\n\n------------------------");
+                end
+ 
+                $display("%x", pkt_rx_data);
+ 
+                if (pkt_rx_eop) begin
+                    done <= 1;
+                    pkt_rx_ren <= 1'b0;
+                end
+ 
+                if (pkt_rx_eop) begin
+                    $display("------------------------\n\n");
+                end
+ 
+            end
+ 
+            @(posedge clk_156m25);
+ 
+        end
+ 
+    end
+endtask
+ 
+initial begin
+ 
+    forever begin
+ 
+        if (pkt_rx_avail) begin
+            RxPacket();
+        end
+ 
+        @(posedge clk_156m25);
+ 
+    end
+ 
+end
+ 
+endmodule
+ 
\ No newline at end of file
diff --git a/fpga/usrp3/lib/xge_interface/Makefile.srcs b/fpga/usrp3/lib/xge_interface/Makefile.srcs
new file mode 100644
index 000000000..63cef065d
--- /dev/null
+++ b/fpga/usrp3/lib/xge_interface/Makefile.srcs
@@ -0,0 +1,10 @@
+##################################################
+# Logic to interface to Opencores 10G MAC
+##################################################
+XGE_INTERFACE_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/xge_interface/, \
+axi64_to_xge64.v \
+axi_count_packets_in_fifo.v \
+xge64_to_axi64.v \
+xge_handshake.v \
+xge_mac_wrapper.v \
+))
diff --git a/fpga/usrp3/lib/xge_interface/axi64_to_xge64.v b/fpga/usrp3/lib/xge_interface/axi64_to_xge64.v
new file mode 100644
index 000000000..3921c607c
--- /dev/null
+++ b/fpga/usrp3/lib/xge_interface/axi64_to_xge64.v
@@ -0,0 +1,89 @@
+//
+// Copyright 2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+//
+// Removes 6 alignment bytes at the beginning of every packet.
+// This gives us proper alignment to the IP/UDP header.
+//
+// Place an SOF indication in bit[3] of the output tuser.
+//
+
+module axi64_to_xge64
+  (
+   input clk,
+   input reset,
+   input clear,
+   input [63:0] s_axis_tdata,
+   input [3:0] s_axis_tuser,
+   input s_axis_tlast,
+   input s_axis_tvalid,
+   output s_axis_tready,
+   output [63:0] m_axis_tdata,
+   output [3:0] m_axis_tuser,
+   output m_axis_tlast,
+   output m_axis_tvalid,
+   input m_axis_tready
+   );
+
+   localparam STORE_FIRST = 0;
+   localparam FORWARD_FULL = 1;
+   localparam RELEASE_LAST = 2;
+
+   reg [1:0] state;
+   reg [15:0] saved;
+   reg [2:0]  last_occ;
+   reg 	      last_sof;
+
+   //on last line when eof and not finishing with 7 or 8 bytes as last word.
+   wire       last_line = (s_axis_tlast && !(s_axis_tuser[2:0] == 3'b111 || s_axis_tuser[2:0] == 3'b000));
+
+   always @(posedge clk) begin
+      if(reset | clear) begin
+         last_sof <= 0;
+         last_occ <= 0;
+         state <= STORE_FIRST;
+      end
+      else begin
+         if (s_axis_tvalid && s_axis_tready) begin
+            saved <= s_axis_tdata[63:48];
+            last_occ <= s_axis_tuser[2:0];
+            last_sof <= (state == STORE_FIRST) ;
+         end
+
+         case(state)
+
+           STORE_FIRST: begin
+              if (s_axis_tvalid && s_axis_tready) begin
+                 state <= FORWARD_FULL;
+              end
+           end
+
+           FORWARD_FULL: begin
+              if (s_axis_tvalid && s_axis_tready && s_axis_tlast) begin
+                 state <= last_line? STORE_FIRST : RELEASE_LAST;
+              end
+           end
+
+           RELEASE_LAST: begin
+              if (m_axis_tvalid && m_axis_tready) begin
+                 state <= STORE_FIRST;
+              end
+           end
+
+         endcase //state
+      end
+   end
+
+   assign m_axis_tdata[63:0] = {s_axis_tdata[47:0], saved};
+   assign m_axis_tuser[3] = last_sof;
+   assign m_axis_tlast = (state == RELEASE_LAST)? 1'b1 : last_line;
+   assign m_axis_tuser[2:0] = ((state == RELEASE_LAST)? last_occ : (last_line? s_axis_tuser[2:0] : 3'b110)) + 3'b010;
+   assign m_axis_tvalid = (state == STORE_FIRST)? 0 : ((state == RELEASE_LAST)? 1 : s_axis_tvalid);
+   assign s_axis_tready = (state == STORE_FIRST)? 1 : ((state == RELEASE_LAST)? 0 : m_axis_tready);
+
+endmodule //fifo69_txrealign
diff --git a/fpga/usrp3/lib/xge_interface/axi_count_packets_in_fifo.v b/fpga/usrp3/lib/xge_interface/axi_count_packets_in_fifo.v
new file mode 100644
index 000000000..6ae746b09
--- /dev/null
+++ b/fpga/usrp3/lib/xge_interface/axi_count_packets_in_fifo.v
@@ -0,0 +1,158 @@
+//
+// Copyright 2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+//
+// Tracks the number of complete packets in an AXI FIFO so that
+// the XGE MAC can commit to transmitting a packet.
+//
+ 
+module axi_count_packets_in_fifo
+  (
+   input clk,
+   input reset,
+   input in_axis_tvalid,
+   input in_axis_tready,
+   input in_axis_tlast,
+   input out_axis_tvalid,
+   input out_axis_tready,
+   input out_axis_tlast,
+   input pkt_tx_full,
+   output enable_tx
+   );
+
+   localparam WAIT_SOF = 0;
+   localparam WAIT_EOF = 1;
+   
+   localparam WAIT_FULL = 0;
+   localparam DELAY_TO_EOF = 1;
+   localparam WAIT_SPACE = 2;
+   
+   
+   reg 	      in_state, out_state;
+   reg [1:0]  full_state;
+   reg 	      pause_tx;
+   	      
+   reg [7:0] pkt_count;
+
+   
+   //
+   // Count packets arriving into large FIFO
+   //
+   always @(posedge clk)
+     if (reset) begin
+	in_state <= WAIT_SOF;
+     end else
+       case(in_state)
+	 WAIT_SOF: 
+	   if (in_axis_tvalid && in_axis_tready) begin
+	      in_state <= WAIT_EOF;
+	   end else begin
+	      in_state <= WAIT_SOF;
+	   end
+	 WAIT_EOF: 
+	   if (in_axis_tlast && in_axis_tvalid && in_axis_tready) begin
+	      in_state <= WAIT_SOF;
+	   end else begin
+	      in_state <= WAIT_EOF;
+	   end
+       endcase // case(in_state)
+   
+
+   //
+   // Count packets leaving large FIFO
+   //
+   always @(posedge clk)
+     if (reset) begin
+	out_state <= WAIT_SOF;
+     end else
+       case(out_state)
+	 WAIT_SOF: 
+	   if (out_axis_tvalid && out_axis_tready) begin
+	      out_state <= WAIT_EOF;
+	   end else begin
+	      out_state <= WAIT_SOF;
+	   end
+	 WAIT_EOF: 
+	   if (out_axis_tlast && out_axis_tvalid && out_axis_tready) begin
+	      out_state <= WAIT_SOF;
+	   end else begin
+	      out_state <= WAIT_EOF;
+	   end
+       endcase // case(in_state)
+   
+
+   //
+   // Count packets in FIFO.
+   // No protection on counter wrap, 
+   // unclear how such an error could occur or how to gracefully deal with it.
+   //
+   always @(posedge clk)
+     if (reset)
+       pkt_count <= 0;
+     else if (((out_state==WAIT_EOF) && out_axis_tlast && out_axis_tvalid && out_axis_tready) 
+	      && ((in_state==WAIT_EOF) && in_axis_tlast && in_axis_tvalid && in_axis_tready))
+       pkt_count <= pkt_count;
+     else if ((out_state==WAIT_EOF) && out_axis_tlast && out_axis_tvalid && out_axis_tready)
+       pkt_count <= pkt_count - 1;
+     else if ((in_state==WAIT_EOF) && in_axis_tlast && in_axis_tvalid && in_axis_tready)
+       pkt_count <= pkt_count + 1;
+   
+
+   //
+   // Guard against Tx MAC overflow (as indicated by pkt_tx_full)
+   //
+   always @(posedge clk)
+     if (reset) begin
+	pause_tx <= 0;
+	full_state <= WAIT_FULL;
+     end	
+     else begin
+	pause_tx <= 0;	
+	case(full_state)
+	  WAIT_FULL:
+	    // Search for pkt_tx_full going asserted
+	    if (pkt_tx_full && (out_state == WAIT_SOF)) begin
+	       full_state <= WAIT_SPACE;
+	       pause_tx <= 1;
+	    end else if (pkt_tx_full && (out_state == WAIT_EOF)) begin
+	       full_state <= DELAY_TO_EOF;
+	    end
+	  
+	  DELAY_TO_EOF:
+	    // pkt_tx_full has gone asserted during Tx of a packet from FIFO.
+	    // Wait until either FIFO has space again and transition direct to WAIT_FULL
+	    // or at EOF if pkt_tx_full is still asserted the transition to WAIT_SPACE until
+	    // MAC flags there is space again.
+	    if (pkt_tx_full && out_axis_tlast && out_axis_tvalid && out_axis_tready) begin
+	       full_state <= WAIT_SPACE;
+	       pause_tx <= 1;
+	    end else if (pkt_tx_full) begin
+	       full_state <= DELAY_TO_EOF;
+	    end else
+	      full_state <= WAIT_FULL;
+	  
+	  WAIT_SPACE:
+	    // Wait for MAC to flag space in internal Tx FIFO again then transition to WAIT_FULL.
+	    if (pkt_tx_full) begin
+	       full_state <= WAIT_SPACE;
+	       pause_tx <= 1;
+	    end else
+	      full_state <= WAIT_FULL;
+	  
+	endcase // case(full_state)
+     end
+	
+
+   // Enable Tx to MAC
+   assign enable_tx = (pkt_count != 0) && ~pause_tx;
+   
+   
+   
+
+endmodule // count_tx_packets
+
diff --git a/fpga/usrp3/lib/xge_interface/xge64_to_axi64.v b/fpga/usrp3/lib/xge_interface/xge64_to_axi64.v
new file mode 100644
index 000000000..f4af538c5
--- /dev/null
+++ b/fpga/usrp3/lib/xge_interface/xge64_to_axi64.v
@@ -0,0 +1,311 @@
+//
+// Copyright 2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+// Adds 6 bytes at the beginning of every packet
+// This gives us good32/64bit alignment of IP/UDP headers.
+//
+// The 6 bytes added include an octet passed as a parameter allowing a label to
+// be added as metatdata in the header padding. This is typically the ingress
+// port to be tagged in the packet as metadata.
+//
+// bit[65] EOF
+// bit[64] SOF
+// bit[68:66] occ
+//
+// This design will break if downstream can not be guarenteed to be ready to accept data.
+// XGE MAC expects to be able to stream whole packet with no handshaking.
+// We force downstream packet gate to discard packet by signalling error with tlast and
+// resynchronizing with upstream.
+//
+
+module xge64_to_axi64
+  #(parameter LABEL=0)
+   (
+    input clk, 
+    input reset, 
+    input clear,
+    input [63:0] datain,
+    input [2:0] occ,
+    input sof,
+    input eof,
+    input err,
+    input valid, 
+    output reg [63:0] axis_tdata,
+    output reg [3:0] axis_tuser,
+    output reg axis_tlast,
+    output reg axis_tvalid,   // Signal data avilable to downstream
+    input axis_tready
+    );
+
+   localparam EMPTY  = 0;
+   localparam IN_USE = 1;
+   localparam FLUSHING3 = 2;
+   localparam FLUSHING4 = 3;
+   localparam FLUSHING5 = 4;
+   localparam FLUSHING6 = 5;
+   localparam FLUSHING7 = 6;
+   localparam FLUSHING8 = 7;
+   localparam ERROR1 = 8;
+
+
+   localparam EOF1 = 3'b001;
+   localparam EOF2 = 3'b010;
+   localparam EOF3 = 3'b011;
+   localparam EOF4 = 3'b100;
+   localparam EOF5 = 3'b101;
+   localparam EOF6 = 3'b110;
+   localparam EOF7 = 3'b111;
+   localparam EOF8 = 3'b000;
+
+   reg [3:0] state;
+   reg 	     err_reg;
+   reg [47:0] holding_reg;
+
+   always @(posedge clk)
+     if(reset | clear) begin
+	state <= EMPTY;
+	axis_tdata <= 0;
+	holding_reg <= 0;
+	axis_tvalid <= 0;	
+     end else begin
+	// Defaults
+	axis_tvalid <= 0;
+	axis_tuser <= 0;
+	axis_tlast <= 0;
+	err_reg <= 0;
+	
+	case(state)
+	  EMPTY: begin
+	     if (valid & axis_tready & sof) begin
+		// Start of packet should always be received in this state.
+		// It should NEVER be possible to get a packet from the MAC with EOF also set in 
+		// the first 64 bits so not designed for.
+		// Add pad. Store last 6 octets into holding, change state to show data in holding.	
+		state <= IN_USE;
+		axis_tvalid <= 1;
+	     end
+	     else if (valid & ~axis_tready)
+	       // Assert on this condition, add H/W to deal with overflow later.
+	       $display("ERROR: xge64_to_axi64, valid & ~axis_tready");
+	     
+	     holding_reg <= datain[16 +: 48];
+	     axis_tdata[48 +: 16] <= datain[15:0];
+	     axis_tdata[47:0] <= {40'h0, LABEL}; // Tag packet with label
+	  end
+	  
+	  IN_USE: begin
+	     if (valid & axis_tready & (eof | err)) begin
+		// End of packet should always be received in this state.
+		// If Error is asserted from MAC, immediate EOF is forced,
+		// and the error flag set in tuser. State machine will return to WAIT
+		// state and search for new SOF thereby discarding anything left of error packet.
+		//
+		// In the case of 3 through 8 valid octets in the final 64bits input, 
+		// we must run another cycle afterwards since we have 6 more bytes still in holding.
+		err_reg <= err;
+		holding_reg <= datain[16 +: 48];
+		axis_tdata[63:48] <= datain[15:0];
+		axis_tdata[47:0] <= holding_reg;
+		axis_tvalid <= 1;
+		
+		case(occ[2:0])
+		  // 8 valid Octets in last word of packet, finish next cycle
+		  0: begin
+		     state <= FLUSHING8;
+		  end
+		  // 7 valid Octets in last word of packet, finish next cycle
+		  7: begin
+		     state <= FLUSHING7;
+		  end
+		  // 6 valid octets in last word of packet, finish next cycle
+		  6: begin
+		     state <= FLUSHING6;
+		  end
+		  // 5 valid octets in last word of packet, finish next cycle
+		  5: begin
+		     state <= FLUSHING5;
+		  end		    
+		  // 4 valid octets in last word of packet, finish next cycle
+		  4: begin
+		     state <= FLUSHING4;
+		  end
+		  // 3 valid octets in last word of packet, finish next cycle
+		  3: begin
+		     state <= FLUSHING3;
+		  end
+		  // 2 valid octets in last word of packet, finish this cycle
+		  2: begin
+		     axis_tuser <= {err,EOF8};
+		     state <= EMPTY;
+		     axis_tlast <= 1;
+		  end
+		  // 1 valid octets in last word of packet, finish this cycle
+		  1: begin
+		     axis_tuser <= {err,EOF7};
+		     state <= EMPTY;
+		     axis_tlast <= 1;
+		  end
+		endcase // case (occ[2:0])		
+	     end // if (valid & axis_tready & eof)
+	     else if (valid & axis_tready) begin
+		// No EOF indication so in packet payload somewhere still.
+		state <= IN_USE;
+		holding_reg <= datain[16 +: 48];
+		axis_tdata[63:48] <= datain[15:0];
+		axis_tdata[47:0] <= holding_reg;
+		axis_tvalid <= 1;
+	     end
+	     else if (valid & ~axis_tready) begin
+		// Assert on this condition
+		$display("ERROR: xge64_to_axi64, valid & ~axis_tready");
+		// Keep error state asserted ready for downstream to accept
+		state <= ERROR1;
+		axis_tlast <= 1;
+		axis_tvalid <= 1;
+		axis_tuser <= {1'b1, EOF8}; // Force error in this packet.
+	     end else if (~valid) begin
+		// Assert on this condition, don't expect the MAC to ever throtle dataflow intra-packet.
+		$display("ERROR: xge64_to_axi64, ~valid ");
+		state <= ERROR1;
+		axis_tlast <= 1;
+		axis_tvalid <= 1;
+		axis_tuser <= {1'b1, EOF8}; // Force error in this packet.
+	     end
+	  end // case: IN_USE
+
+	  FLUSHING3: begin
+	     if (axis_tready) begin
+		// EOF has been received last cycle.
+		// Ethernet interframe gap means we don't have to search for back-to-back EOF-SOF here.
+		// 1 valid Octets to finish
+		state <= EMPTY;
+		axis_tlast <= 1;
+		axis_tuser <= {err_reg, EOF1};
+		axis_tdata[47:0] <= holding_reg;
+		axis_tvalid <= 1;
+	     end else begin
+		state <= ERROR1;
+		axis_tlast <= 1;
+		axis_tvalid <= 1;
+		axis_tuser <= {1'b1, EOF8}; // Force error in this packet.
+	     end // else: !if(axis_tready)
+	  end
+	  
+	  FLUSHING4: begin
+	     if (axis_tready) begin
+		// EOF has been received last cycle.
+		// Ethernet interframe gap means we don't have to search for back-to-back EOF-SOF here.
+		// 2 valid Octets to finish
+		state <= EMPTY;
+		axis_tlast <= 1;
+		axis_tuser <= {err_reg, EOF2};
+		axis_tdata[47:0] <= holding_reg;
+		axis_tvalid <= 1;
+	     end else begin
+		state <= ERROR1;
+		axis_tlast <= 1;
+		axis_tvalid <= 1;
+		axis_tuser <= {1'b1, EOF8}; // Force error in this packet.
+	     end // else: !if(axis_tready)
+	  end
+	  
+	  FLUSHING5: begin
+	     if (axis_tready) begin
+		// EOF has been received last cycle.
+		// Ethernet interframe gap means we don't have to search for back-to-back EOF-SOF here.
+		// 3 valid Octets to finish
+		state <= EMPTY;
+		axis_tlast <= 1;
+		axis_tuser <= {err_reg, EOF3};
+		axis_tdata[47:0] <= holding_reg;
+		axis_tvalid <= 1;
+	     end else begin
+		state <= ERROR1;
+		axis_tlast <= 1;
+		axis_tvalid <= 1;
+		axis_tuser <= {1'b1, EOF8}; // Force error in this packet.
+	     end // else: !if(axis_tready)
+	  end
+	  
+	  FLUSHING6: begin
+	     if (axis_tready) begin
+		// EOF has been received last cycle.
+		// Ethernet interframe gap means we don't have to search for back-to-back EOF-SOF here.
+		// 4 valid Octets to finish
+		state <= EMPTY;
+		axis_tlast <= 1;
+		axis_tuser <= {err_reg, EOF4};
+		axis_tdata[47:0] <= holding_reg;
+		axis_tvalid <= 1;
+	     end else begin
+		state <= ERROR1;
+		axis_tlast <= 1;
+		axis_tvalid <= 1;
+		axis_tuser <= {1'b1, EOF8}; // Force error in this packet.
+	     end // else: !if(axis_tready)
+	  end
+	  
+	  FLUSHING7: begin
+	     if (axis_tready) begin
+		// EOF has been received last cycle.
+		// Ethernet interframe gap means we don't have to search for back-to-back EOF-SOF here.
+		// 5 valid Octets to finish
+		state <= EMPTY;
+		axis_tlast <= 1;
+		axis_tuser <= {err_reg, EOF5};
+		axis_tdata[47:0] <= holding_reg;
+		axis_tvalid <= 1;
+	     end else begin
+		state <= ERROR1;
+		axis_tlast <= 1;
+		axis_tvalid <= 1;
+		axis_tuser <= {1'b1, EOF8}; // Force error in this packet.
+	     end // else: !if(axis_tready)
+	  end
+	  
+	  FLUSHING8: begin
+	     if (axis_tready) begin
+		// EOF has been received last cycle.
+		// Ethernet interframe gap means we don't have to search for back-to-back EOF-SOF here.
+		// 6 valid Octets to finish
+		state <= EMPTY;
+		axis_tlast <= 1;
+		axis_tuser <= {err_reg, EOF6};
+		axis_tdata[47:0] <= holding_reg;
+		axis_tvalid <= 1;
+	     end else begin
+		state <= ERROR1;
+		axis_tlast <= 1;
+		axis_tvalid <= 1;
+		axis_tuser <= {1'b1, EOF8}; // Force error in this packet.
+	     end // else: !if(axis_tready)
+	  end
+
+	  ERROR1: begin
+	     // We were already actively receiving a packet from the upstream MAC and the downstream
+	     // signaled not ready by de-asserting tready. Since we can't back pressure the MAC we have to
+	     // abandon the current packet, discarding any data already sent down stream by sending an asserted error
+	     // with a tlast when ever tready becomes asserted again. Meanwhile we start dropping arriving MAC
+	     // data on the floor since there is nothing useful we can do with it currently.
+	     if (axis_tready)
+	       begin
+		  // OK tready is asserted again so tlast is geting accepted this cycle along with an asserted error.
+		  state <= EMPTY;
+	       end else begin
+		  // Keep error state asserted ready for downstream to accept
+		  axis_tlast <= 1;
+		  axis_tvalid <= 1;
+		  axis_tuser <= {1'b1, EOF8}; // Force error in this packet.
+	       end
+	  end // case: ERROR1
+	  
+
+	endcase // case(state)
+     end // else: !if(reset | clear)
+
+endmodule
diff --git a/fpga/usrp3/lib/xge_interface/xge_handshake.v b/fpga/usrp3/lib/xge_interface/xge_handshake.v
new file mode 100644
index 000000000..9f0dd184b
--- /dev/null
+++ b/fpga/usrp3/lib/xge_interface/xge_handshake.v
@@ -0,0 +1,63 @@
+//
+// Copyright 2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+//
+//
+// Provide required handshake to Opencores XGE MAC to initiate Rx of one available packet
+// 
+//
+
+
+module xge_handshake
+  (
+   input clk,
+   input reset,
+   output reg pkt_rx_ren,
+   input pkt_rx_avail,
+   input pkt_rx_eop
+   );
+
+   localparam IDLE=0;
+   localparam RX=1;
+
+   reg 	      state;
+   
+
+   always @(posedge clk)
+     if (reset) begin
+	pkt_rx_ren <= 0;
+	state <= IDLE;
+     end else begin
+	case (state)
+	  //
+	  // Wait for pkt_rx_avail to be asserted, then assert pkt_rx_ren next cycle
+	  //
+	  IDLE: begin
+	     if (pkt_rx_avail) begin
+		pkt_rx_ren <= 1;
+		state <= RX;
+	     end else begin
+		pkt_rx_ren <= 0;
+		state <= IDLE;
+	     end
+	  end
+	  //
+	  // Keep pkt_rx_ren asserted until EOF received.
+	  //
+	  RX: begin
+	     if (pkt_rx_eop) begin
+		pkt_rx_ren <= 0;
+		state <= IDLE;
+	     end else begin
+		pkt_rx_ren <= 1;
+		state <= RX;
+	     end
+	  end   
+	     
+	endcase // case(state)
+     end // else: !if(reset)
+endmodule // xge_handshake
diff --git a/fpga/usrp3/lib/xge_interface/xge_mac_wrapper.v b/fpga/usrp3/lib/xge_interface/xge_mac_wrapper.v
new file mode 100644
index 000000000..136ff8dff
--- /dev/null
+++ b/fpga/usrp3/lib/xge_interface/xge_mac_wrapper.v
@@ -0,0 +1,394 @@
+/////////////////////////////////////////////////////////////////////
+//
+// Copyright 2013-2016 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: xge_mac_wrapper
+// Description:
+//   Wrap XGE MAC + optional wishbone interface
+//
+//   *) Signals are crossed between the MAC's own 156.25MHz clock domain and the
+//   main FPGA clock domain.
+//   *) 6 byte Padding is added at RX, including metadata so that IP headers become aligned.
+//   *) 6 Byte padding is stripped at TX, so that Eth header data starts immediately.
+//   *) TX & RX can buffer at least an MTU sized packet
+//   *) On TX, to not start an Ethernet Tx until a complete packet is present in the
+//   last Tx FIFO so that the MAC doesn't underrun.
+//
+/////////////////////////////////////////////////////////////////////
+
+module xge_mac_wrapper #(
+  parameter PORTNUM = 8'd0,
+  parameter WISHBONE = 1
+)(
+  // XGMII
+  input         xgmii_clk,
+  output [63:0] xgmii_txd,
+  output [7:0]  xgmii_txc,
+  input  [63:0] xgmii_rxd,
+  input  [7:0]  xgmii_rxc,
+  // Client FIFO Interfaces
+  input         sys_clk,
+  input         sys_rst,          // From sys_clk domain.
+  output [63:0] rx_tdata,
+  output [3:0]  rx_tuser,
+  output        rx_tlast,
+  output        rx_tvalid,
+  input         rx_tready,
+  input  [63:0] tx_tdata,
+  input  [3:0]  tx_tuser,                // Bit[3] (error) is ignored for now.
+  input         tx_tlast,
+  input         tx_tvalid,
+  output        tx_tready,
+  // Control and Status
+  input         phy_ready,
+  input         ctrl_tx_enable,
+  output        status_crc_error,
+  output        status_fragment_error,
+  output        status_txdfifo_ovflow,
+  output        status_txdfifo_udflow,
+  output        status_rxdfifo_ovflow,
+  output        status_rxdfifo_udflow,
+  output        status_pause_frame_rx,
+  output        status_local_fault,
+  output        status_remote_fault,
+  // MDIO
+  output        mdc,
+  output        mdio_in,
+  input         mdio_out,
+  // Wishbone interface
+  input [7:0]   wb_adr_i,               // To wishbone_if0 of wishbone_if.v
+  input         wb_clk_i,               // To sync_clk_wb0 of sync_clk_wb.v, ...
+  input         wb_cyc_i,               // To wishbone_if0 of wishbone_if.v
+  input [31:0]  wb_dat_i,               // To wishbone_if0 of wishbone_if.v
+  input         wb_rst_i,               // To sync_clk_wb0 of sync_clk_wb.v, ...
+  input         wb_stb_i,               // To wishbone_if0 of wishbone_if.v
+  input         wb_we_i,                // To wishbone_if0 of wishbone_if.v
+  output        wb_ack_o,               // From wishbone_if0 of wishbone_if.v
+  output [31:0] wb_dat_o,               // From wishbone_if0 of wishbone_if.v
+  output        wb_int_o                // From wishbone_if0 of wishbone_if.v
+);
+
+  //
+  // Generate 156MHz synchronized sys_rst locally
+  //
+
+  wire xgmii_reset, ctrl_tx_enable_xclk;
+  wire phy_ready_xgmiiclk, sys_rst_xgmiiclk;
+
+  synchronizer #(
+     .INITIAL_VAL(1'b0), .STAGES(3)
+  ) phy_ready_sync_i (
+     .clk(xgmii_clk), .rst(1'b0 /* no reset */), .in(phy_ready), .out(phy_ready_xgmiiclk)
+  );
+
+  synchronizer #(
+     .INITIAL_VAL(1'b1), .STAGES(3)
+  ) sys_rst_sync_i (
+     .clk(xgmii_clk), .rst(1'b0 /* no reset */), .in(sys_rst), .out(sys_rst_xgmiiclk)
+  );
+
+  synchronizer #(
+     .INITIAL_VAL(1'b1), .STAGES(3)
+  ) tx_enabled_sync_i (
+     .clk(xgmii_clk), .rst(1'b0 /* no reset */), .in(ctrl_tx_enable), .out(ctrl_tx_enable_xclk)
+  );
+
+  assign xgmii_reset = !phy_ready_xgmiiclk || sys_rst_xgmiiclk;
+
+  //
+  // 10G MAC
+  //
+  wire [63:0] eth_rx_data;
+  wire        eth_rx_avail;
+  wire        eth_rx_eof;
+  wire        eth_rx_err;
+  wire [2:0]  eth_rx_occ;
+  wire        eth_rx_sof;
+  wire        eth_rx_valid;
+  wire        eth_rx_ren;
+
+  wire        eth_tx_full;
+  wire [63:0] eth_tx_data;
+  wire        eth_tx_eof;
+  wire [2:0]  eth_tx_occ;
+  wire        eth_tx_sof;
+  wire        eth_tx_valid;
+
+  generate if (WISHBONE == 1) begin
+    xge_mac_wb xge_mac_wb (
+      // Clocks and Resets
+      .clk_156m25             (xgmii_clk),
+      .clk_xgmii_rx           (xgmii_clk),
+      .clk_xgmii_tx           (xgmii_clk),
+      .reset_156m25_n         (~xgmii_reset),
+      .reset_xgmii_rx_n       (~xgmii_reset),
+      .reset_xgmii_tx_n       (~xgmii_reset),
+      // XGMII
+      .xgmii_txc              (xgmii_txc[7:0]),
+      .xgmii_txd              (xgmii_txd[63:0]),
+      .xgmii_rxc              (xgmii_rxc[7:0]),
+      .xgmii_rxd              (xgmii_rxd[63:0]),
+      // MDIO
+      .mdc                    (mdc),
+      .mdio_out               (mdio_in),// Switch sense of in and out here for master and slave.
+      .mdio_tri               (mdio_tri),
+      .xge_gpo                (),
+      .mdio_in                (mdio_out), // Switch sense of in and out here for master and slave.
+      .xge_gpi                (/*{2'b00,align_status,mgt_tx_ready,sync_status[3:0]}*/0),
+      // Packet interface
+      .pkt_rx_avail           (eth_rx_avail),
+      .pkt_rx_data            (eth_rx_data),
+      .pkt_rx_eop             (eth_rx_eof),
+      .pkt_rx_err             (eth_rx_err),
+      .pkt_rx_mod             (eth_rx_occ),
+      .pkt_rx_sop             (eth_rx_sof),
+      .pkt_rx_val             (eth_rx_valid),
+      .pkt_tx_full            (eth_tx_full),
+      // Inputs
+      .pkt_rx_ren             (eth_rx_ren),
+      .pkt_tx_data            (eth_tx_data),
+      .pkt_tx_eop             (eth_tx_eof),
+      .pkt_tx_mod             (eth_tx_occ),
+      .pkt_tx_sop             (eth_tx_sof),
+      .pkt_tx_val             (eth_tx_valid),
+      .wb_ack_o               (wb_ack_o),
+      .wb_dat_o               (wb_dat_o),
+      .wb_adr_i               (wb_adr_i[7:0]),
+      .wb_clk_i               (wb_clk_i),
+      .wb_cyc_i               (wb_cyc_i),
+      .wb_dat_i               (wb_dat_i),
+      .wb_rst_i               (wb_rst_i),
+      .wb_stb_i               (wb_stb_i),
+      .wb_we_i                (wb_we_i),
+      .wb_int_o               (xge_int)
+    );
+
+    assign status_crc_error = 1'b0;
+    assign status_fragment_error = 1'b0;
+    assign status_txdfifo_ovflow = 1'b0;
+    assign status_txdfifo_udflow = 1'b0;
+    assign status_rxdfifo_ovflow = 1'b0;
+    assign status_rxdfifo_udflow = 1'b0;
+    assign status_pause_frame_rx = 1'b0;
+    assign status_local_fault = 1'b0;
+    assign status_remote_fault = 1'b0;
+
+  end else begin
+    xge_mac xge_mac (
+      // Clocks and Resets
+      .clk_156m25             (xgmii_clk),
+      .clk_xgmii_rx           (xgmii_clk),
+      .clk_xgmii_tx           (xgmii_clk),
+      .reset_156m25_n         (~xgmii_reset),
+      .reset_xgmii_rx_n       (~xgmii_reset),
+      .reset_xgmii_tx_n       (~xgmii_reset),
+      // XGMII
+      .xgmii_txc              (xgmii_txc[7:0]),
+      .xgmii_txd              (xgmii_txd[63:0]),
+      .xgmii_rxc              (xgmii_rxc[7:0]),
+      .xgmii_rxd              (xgmii_rxd[63:0]),
+      // Packet interface
+      .pkt_rx_avail           (eth_rx_avail),
+      .pkt_rx_data            (eth_rx_data),
+      .pkt_rx_eop             (eth_rx_eof),
+      .pkt_rx_err             (eth_rx_err),
+      .pkt_rx_mod             (eth_rx_occ),
+      .pkt_rx_sop             (eth_rx_sof),
+      .pkt_rx_val             (eth_rx_valid),
+      .pkt_tx_full            (eth_tx_full),
+      // Inputs
+      .pkt_rx_ren             (eth_rx_ren),
+      .pkt_tx_data            (eth_tx_data),
+      .pkt_tx_eop             (eth_tx_eof),
+      .pkt_tx_mod             (eth_tx_occ),
+      .pkt_tx_sop             (eth_tx_sof),
+      .pkt_tx_val             (eth_tx_valid),
+      // Control and Status
+      .ctrl_tx_enable         (ctrl_tx_enable_xclk),
+      .status_crc_error       (status_crc_error),
+      .status_fragment_error  (status_fragment_error),
+      .status_txdfifo_ovflow  (status_txdfifo_ovflow),
+      .status_txdfifo_udflow  (status_txdfifo_udflow),
+      .status_rxdfifo_ovflow  (status_rxdfifo_ovflow),
+      .status_rxdfifo_udflow  (status_rxdfifo_udflow),
+      .status_pause_frame_rx  (status_pause_frame_rx),
+      .status_local_fault     (status_local_fault),
+      .status_remote_fault    (status_remote_fault)
+    );
+
+    assign wb_ack_o = 1'b0;
+    assign wb_dat_o = 1'b0;
+    assign wb_int_o = 1'b0;
+    assign mdio_in = 1'b0;
+    assign mdc = 1'b0;
+  end
+  endgenerate
+
+  ///////////////////////////////////////////////////////////////////////////////////////
+    // RX FIFO Chain
+  ///////////////////////////////////////////////////////////////////////////////////////
+  wire [63:0] rx_tdata_int;
+  wire [3:0]  rx_tuser_int;
+  wire        rx_tlast_int;
+  wire        rx_tvalid_int;
+  wire        rx_tready_int;
+
+  //
+  // Logic to drive pkt_rx_ren on XGE MAC
+  //
+  xge_handshake xge_handshake (
+    .clk(xgmii_clk),
+    .reset(xgmii_reset),
+    .pkt_rx_ren(eth_rx_ren),
+    .pkt_rx_avail(eth_rx_avail),
+    .pkt_rx_eop(eth_rx_eof)
+  );
+
+  //
+  // Add pad of 6 empty bytes before MAC addresses of new Rxed packet so that IP
+  // headers are alligned. Also put metadata in first octet of pad that shows
+  // ingress port.
+  //
+  xge64_to_axi64 #(
+    .LABEL(PORTNUM)
+  ) xge64_to_axi64 (
+    .clk(xgmii_clk),
+    .reset(xgmii_reset),
+    .clear(1'b0),
+    .datain(eth_rx_data),
+    .occ(eth_rx_occ),
+    .sof(eth_rx_sof),
+    .eof(eth_rx_eof),
+    .err(eth_rx_err),
+    .valid(eth_rx_valid),
+    .axis_tdata(rx_tdata_int),
+    .axis_tuser(rx_tuser_int),
+    .axis_tlast(rx_tlast_int),
+    .axis_tvalid(rx_tvalid_int),
+    .axis_tready(rx_tready_int)
+  );
+
+  //
+  // Large FIFO must be able to run input side at 64b@156MHz to sustain 10Gb Rx.
+  //
+  axi64_4k_2clk_fifo rxfifo_2clk (
+    .s_aresetn(~xgmii_reset),
+    .s_aclk(xgmii_clk),
+    .s_axis_tvalid(rx_tvalid_int),
+    .s_axis_tready(rx_tready_int),
+    .s_axis_tdata(rx_tdata_int),
+    .s_axis_tlast(rx_tlast_int),
+    .s_axis_tuser(rx_tuser_int),
+    .axis_wr_data_count(),
+
+    .m_aclk(sys_clk),
+    .m_axis_tvalid(rx_tvalid),
+    .m_axis_tready(rx_tready),
+    .m_axis_tdata(rx_tdata),
+    .m_axis_tlast(rx_tlast),
+    .m_axis_tuser(rx_tuser),
+    .axis_rd_data_count()
+  );
+
+
+  ///////////////////////////////////////////////////////////////////////////////////////
+  // TX FIFO Chain
+  ///////////////////////////////////////////////////////////////////////////////////////
+
+  wire [63:0] tx_tdata_int;
+  wire [3:0]  tx_tuser_int;
+  wire        tx_tlast_int;
+  wire        tx_tvalid_int;
+  wire        tx_tready_int;
+
+  wire [63:0] tx_tdata_int2;
+  wire [3:0]  tx_tuser_int2;
+  wire        tx_tlast_int2;
+  wire        tx_tvalid_int2;
+  wire        tx_tready_int2;
+
+  wire        tx_tvalid_int3;
+  wire        tx_tready_int3;
+  wire        tx_sof_int3;
+  wire        enable_tx;
+
+  axi64_4k_2clk_fifo txfifo_2clk_1x (
+    .s_aresetn(~xgmii_reset),
+    .s_aclk(sys_clk),
+    .s_axis_tvalid(tx_tvalid),
+    .s_axis_tready(tx_tready),
+    .s_axis_tdata(tx_tdata),
+    .s_axis_tlast(tx_tlast),
+    .s_axis_tuser(tx_tuser),
+    .axis_wr_data_count(),
+
+    .m_aclk(xgmii_clk),
+    .m_axis_tvalid(tx_tvalid_int),
+    .m_axis_tready(tx_tready_int),
+    .m_axis_tdata(tx_tdata_int),
+    .m_axis_tlast(tx_tlast_int),
+    .m_axis_tuser(tx_tuser_int),
+    .axis_rd_data_count()
+  );
+
+  //
+  // Strip the 6 octet ethernet padding we used internally.
+  // Put SOF into bit[3] of tuser.
+  //
+  axi64_to_xge64 axi64_to_xge64 (
+    .clk(xgmii_clk),
+    .reset(xgmii_reset),
+    .clear(1'b0),
+    .s_axis_tdata(tx_tdata_int),
+    .s_axis_tuser(tx_tuser_int),
+    .s_axis_tlast(tx_tlast_int),
+    .s_axis_tvalid(tx_tvalid_int),
+    .s_axis_tready(tx_tready_int),
+    .m_axis_tdata(tx_tdata_int2),
+    .m_axis_tuser(tx_tuser_int2),
+    .m_axis_tlast(tx_tlast_int2),
+    .m_axis_tvalid(tx_tvalid_int2),
+    .m_axis_tready(tx_tready_int2)
+  );
+
+  //
+  // Large FIFO can hold a max sized ethernet packet.
+  //
+  axi_fifo #(.WIDTH(64+4+1), .SIZE(10)) txfifo_2 (
+    .clk(xgmii_clk), .reset(xgmii_reset), .clear(1'b0),
+    .i_tdata({tx_tlast_int2, tx_tuser_int2, tx_tdata_int2}),
+    .i_tvalid(tx_tvalid_int2),
+    .i_tready(tx_tready_int2),
+    .o_tvalid(tx_tvalid_int3),
+    .o_tready(tx_tready_int3),
+    .o_tdata({eth_tx_eof,tx_sof_int3,eth_tx_occ,eth_tx_data}),
+    .space(), .occupied()
+  );
+
+  //
+  // Monitor number of Ethernet packets in tx_fifo2
+  //
+  axi_count_packets_in_fifo axi_count_packets_in_fifo (
+    .clk(xgmii_clk),
+    .reset(xgmii_reset),
+    .in_axis_tvalid(tx_tvalid_int2),
+    .in_axis_tready(tx_tready_int2),
+    .in_axis_tlast(tx_tlast_int2),
+    .out_axis_tvalid(tx_tvalid_int3),
+    .out_axis_tready(tx_tready_int3),
+    .out_axis_tlast(eth_tx_eof),
+    .pkt_tx_full(eth_tx_full),
+    .enable_tx(enable_tx)
+  );
+
+  //
+  //
+  // Supress FIFO flags to stop overflow of MAC in Tx direction
+  //
+  assign eth_tx_valid     = tx_tvalid_int3 & enable_tx;
+  assign tx_tready_int3   = enable_tx;
+  assign eth_tx_sof       = tx_sof_int3 & enable_tx;
+
+endmodule
diff --git a/fpga/usrp3/lib/zpu/Makefile.srcs b/fpga/usrp3/lib/zpu/Makefile.srcs
new file mode 100644
index 000000000..3ce491ae9
--- /dev/null
+++ b/fpga/usrp3/lib/zpu/Makefile.srcs
@@ -0,0 +1,21 @@
+#
+# Copyright 2010-2012 Ettus Research LLC
+#
+
+##################################################
+# ZPU Open Cores Sources
+##################################################
+ZPU_CORE_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/zpu/, \
+zpu_top_pkg.vhd \
+zpu_wb_top.vhd \
+wishbone/wishbone_pkg.vhd \
+wishbone/zpu_system.vhd \
+wishbone/zpu_wb_bridge.vhd \
+core/zpu_core.vhd \
+core/zpupkg.vhd \
+zpu_bootram.v \
+))
+
+ZPU_CONFIG_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/zpu/, \
+core/zpu_config.vhd \
+))
diff --git a/fpga/usrp3/lib/zpu/core/zpu_config.vhd b/fpga/usrp3/lib/zpu/core/zpu_config.vhd
new file mode 100644
index 000000000..560547223
--- /dev/null
+++ b/fpga/usrp3/lib/zpu/core/zpu_config.vhd
@@ -0,0 +1,20 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+package zpu_config is
+	-- generate trace output or not.
+	constant	Generate_Trace		: boolean := false;
+	constant 	wordPower			: integer := 5;
+	-- during simulation, set this to '0' to get matching trace.txt 
+	constant	DontCareValue		: std_logic := '0';
+	-- Clock frequency in MHz.
+	constant	ZPU_Frequency		: std_logic_vector(7 downto 0) := x"40";
+	-- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
+	constant 	maxAddrBitIncIO		: integer := 15;
+	
+	-- start byte address of stack. 
+	-- point to top of RAM - 2*words
+	constant 	spStart				: std_logic_vector(maxAddrBitIncIO downto 0) := x"3ff8";
+	
+end zpu_config;
diff --git a/fpga/usrp3/lib/zpu/core/zpu_core.vhd b/fpga/usrp3/lib/zpu/core/zpu_core.vhd
new file mode 100644
index 000000000..f32c76f6f
--- /dev/null
+++ b/fpga/usrp3/lib/zpu/core/zpu_core.vhd
@@ -0,0 +1,948 @@
+
+-- Company: ZPU4 generic memory interface CPU
+-- Engineer: yvind Harboe
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use IEEE.STD_LOGIC_arith.ALL;
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+
+
+
+
+entity zpu_core is
+    Port ( clk : in std_logic;
+	 		  areset : in std_logic;
+	 		  enable : in std_logic; 
+	 		  mem_req : out std_logic;
+	 		  mem_we : out std_logic;
+	 		  mem_ack : in std_logic; 
+	 		  mem_read : in std_logic_vector(wordSize-1 downto 0);
+	 		  mem_write : out std_logic_vector(wordSize-1 downto 0);
+			  out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0);
+	 		  mem_writeMask: out std_logic_vector(wordBytes-1 downto 0);
+	 		  interrupt : in std_logic;
+	 		  break : out std_logic;
+	 		  zpu_status : out std_logic_vector(63 downto 0));
+end zpu_core;
+
+architecture behave of zpu_core is
+
+type InsnType is 
+(
+State_AddTop,
+State_Dup,
+State_DupStackB,
+State_Pop,
+State_Popdown,
+State_Add,
+State_Or,
+State_And,
+State_Store,
+State_AddSP,
+State_Shift,
+State_Nop,
+State_Im,
+State_LoadSP,
+State_StoreSP,
+State_Emulate,
+State_Load,
+State_PushPC,
+State_PushSP,
+State_PopPC,
+State_PopPCRel,
+State_Not,
+State_Flip,
+State_PopSP,
+State_Neqbranch,
+State_Eq,
+State_Loadb,
+State_Mult,
+State_Lessthan,
+State_Lessthanorequal,
+State_Ulessthanorequal,
+State_Ulessthan,
+State_Pushspadd,
+State_Call,
+State_Callpcrel,
+State_Sub,
+State_Break,
+State_Storeb,
+State_Interrupt,
+State_InsnFetch
+);
+
+type StateType is 
+(
+State_Idle, -- using first state first on the list out of paranoia 
+State_Load2,
+State_Popped,
+State_LoadSP2,
+State_LoadSP3,
+State_AddSP2,
+State_Fetch,
+State_Execute,
+State_Decode,
+State_Decode2,
+State_Resync,
+
+State_StoreSP2,
+State_Resync2,
+State_Resync3,
+State_Loadb2,
+State_Storeb2,
+State_Mult2,
+State_Mult3,
+State_Mult5,
+State_Mult6,
+State_Mult4,
+State_BinaryOpResult
+); 
+
+
+signal	pc				: std_logic_vector(maxAddrBitIncIO downto 0);
+signal	sp				: std_logic_vector(maxAddrBitIncIO downto minAddrBit);
+signal	incSp			: std_logic_vector(maxAddrBitIncIO downto minAddrBit);
+signal	incIncSp			: std_logic_vector(maxAddrBitIncIO downto minAddrBit);
+signal	decSp			: std_logic_vector(maxAddrBitIncIO downto minAddrBit);
+signal  stackA   		: std_logic_vector(wordSize-1 downto 0);
+signal  binaryOpResult		: std_logic_vector(wordSize-1 downto 0);
+signal  multResult2  		: std_logic_vector(wordSize-1 downto 0);
+signal  multResult3  		: std_logic_vector(wordSize-1 downto 0);
+signal  multResult  		: std_logic_vector(wordSize-1 downto 0);
+signal  multA 		: std_logic_vector(wordSize-1 downto 0);
+signal  multB  		: std_logic_vector(wordSize-1 downto 0);
+signal  stackB  		: std_logic_vector(wordSize-1 downto 0);
+signal	idim_flag			: std_logic;
+signal	busy 				: std_logic;
+signal mem_readEnable : std_logic;
+signal mem_addr : std_logic_vector(maxAddrBitIncIO downto minAddrBit);
+signal mem_delayAddr : std_logic_vector(maxAddrBitIncIO downto minAddrBit);
+signal mem_delayReadEnable : std_logic;
+signal mem_busy : std_logic;
+signal decodeWord : std_logic_vector(wordSize-1 downto 0);
+
+
+signal state : StateType;
+signal insn : InsnType;
+type InsnArray is array(0 to wordBytes-1) of InsnType;
+signal decodedOpcode : InsnArray;
+
+type OpcodeArray is array(0 to wordBytes-1) of std_logic_vector(7 downto 0);
+
+signal opcode : OpcodeArray;
+
+
+
+
+signal	begin_inst			: std_logic;
+signal trace_opcode		: std_logic_vector(7 downto 0);
+signal	trace_pc				: std_logic_vector(maxAddrBitIncIO downto 0);
+signal	trace_sp				: std_logic_vector(maxAddrBitIncIO downto minAddrBit);
+signal	trace_topOfStack				: std_logic_vector(wordSize-1 downto 0);
+signal	trace_topOfStackB				: std_logic_vector(wordSize-1 downto 0);
+
+signal	out_mem_req : std_logic;
+
+signal inInterrupt : std_logic;
+
+-- state machine.
+
+begin
+   mem_writeMask <= (others => '1');
+
+	zpu_status(maxAddrBitIncIO downto 0) <= trace_pc;
+	zpu_status(31) <= '1';
+	zpu_status(39 downto 32) <= trace_opcode;
+	zpu_status(40) <= '1' when (state = State_Idle) else '0';
+	zpu_status(62) <= '1';
+
+	traceFileGenerate:
+   if Generate_Trace generate
+	trace_file: trace port map (
+       	clk => clk,
+       	begin_inst => begin_inst,
+       	pc => trace_pc,
+		opcode => trace_opcode,
+		sp => trace_sp,
+		memA => trace_topOfStack,
+		memB => trace_topOfStackB,
+		busy => busy,
+		intsp => (others => 'U')
+        );
+	end generate;
+
+	
+	-- the memory subsystem will tell us one cycle later whether or 
+	-- not it is busy
+	out_mem_addr(maxAddrBitIncIO downto minAddrBit) <= mem_addr;
+	out_mem_addr(minAddrBit-1 downto 0) <= (others => '0');
+	mem_req <= out_mem_req;
+	
+	incSp <= sp + 1;
+	incIncSp <= sp + 2;
+	decSp <= sp - 1;
+	
+	mem_busy <= out_mem_req and not mem_ack; -- '1' when the memory is busy
+
+	opcodeControl:
+	process(clk, areset)
+		variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0);
+		variable spOffset : std_logic_vector(4 downto 0);
+		variable tSpOffset : std_logic_vector(4 downto 0);
+		variable nextPC : std_logic_vector(maxAddrBitIncIO downto 0);
+		variable tNextState : InsnType;
+		variable tDecodedOpcode : InsnArray;
+		variable tMultResult : std_logic_vector(wordSize*2-1 downto 0);
+	begin
+		if areset = '1' then
+			state <= State_Idle;
+			break <= '0';
+			sp <= spStart(maxAddrBitIncIO downto minAddrBit);
+			 
+			pc <= (others => '0');
+			idim_flag <= '0';
+			begin_inst <= '0';
+			mem_we <= '0';
+			multA <= (others => '0');
+			multB <= (others => '0');
+			out_mem_req <= '0';
+			mem_addr <= (others => DontCareValue);
+			mem_write <= (others => DontCareValue);
+			inInterrupt <= '0';
+		elsif (clk'event and clk = '1') then
+			-- we must multiply unconditionally to get pipelined multiplication
+        	tMultResult := multA * multB;
+    		multResult3 <= multResult2;
+    		multResult2 <= multResult;
+    		multResult <= tMultResult(wordSize-1 downto 0);
+    		
+			
+			spOffset(4):=not opcode(conv_integer(pc(byteBits-1 downto 0)))(4);
+			spOffset(3 downto 0):=opcode(conv_integer(pc(byteBits-1 downto 0)))(3 downto 0);
+			nextPC := pc + 1;
+
+			-- prepare trace snapshot
+			trace_opcode <= opcode(conv_integer(pc(byteBits-1 downto 0)));
+			trace_pc <= pc;
+			trace_sp <=	sp;
+			trace_topOfStack <= stackA;
+			trace_topOfStackB <= stackB;
+			begin_inst <= '0';
+
+			-- we terminate the requeset as soon as we get acknowledge
+			if mem_ack = '1' then
+				out_mem_req <= '0';
+				mem_we <= '0';
+			end if;
+			
+			if interrupt='0' then
+				inInterrupt <= '0'; -- no longer in an interrupt
+			end if;
+
+			case state is
+				when State_Idle =>
+					if enable='1' then
+						state <= State_Resync; 
+					end if;
+				-- Initial state of ZPU, fetch top of stack + first instruction 
+				when State_Resync =>
+					if mem_busy='0' then
+						mem_addr <= sp;
+						out_mem_req <= '1';
+						state <= State_Resync2;
+					end if;
+				when State_Resync2 =>
+					if mem_busy='0' then
+						stackA <= mem_read;
+						mem_addr <= incSp;
+						out_mem_req <= '1';
+						state <= State_Resync3;
+					end if;
+				when State_Resync3 =>
+					if mem_busy='0' then
+						stackB <= mem_read;
+						mem_addr <= pc(maxAddrBitIncIO downto minAddrBit);
+						out_mem_req <= '1';
+						state <= State_Decode;
+					end if;
+				when State_Decode =>
+					if mem_busy='0' then
+						decodeWord <= mem_read;
+						state <= State_Decode2;
+					end if;
+				when State_Decode2 =>
+					-- decode 4 instructions in parallel
+					for i in 0 to wordBytes-1 loop
+						tOpcode := decodeWord((wordBytes-1-i+1)*8-1 downto (wordBytes-1-i)*8);
+
+						tSpOffset(4):=not tOpcode(4);
+						tSpOffset(3 downto 0):=tOpcode(3 downto 0);
+
+						opcode(i) <= tOpcode;
+						if (tOpcode(7 downto 7)=OpCode_Im) then
+							tNextState:=State_Im;
+						elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then
+							if tSpOffset = 0 then
+								tNextState := State_Pop;
+							elsif tSpOffset=1 then
+								tNextState := State_PopDown;
+							else
+								tNextState :=State_StoreSP;
+							end if;
+						elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then
+							if tSpOffset = 0 then
+								tNextState :=State_Dup;
+							elsif tSpOffset = 1 then
+								tNextState :=State_DupStackB;
+							else
+								tNextState :=State_LoadSP;
+							end if;
+						elsif (tOpcode(7 downto 5)=OpCode_Emulate) then
+							tNextState :=State_Emulate;
+							if tOpcode(5 downto 0)=OpCode_Neqbranch then
+								tNextState :=State_Neqbranch;
+							elsif tOpcode(5 downto 0)=OpCode_Eq then
+								tNextState :=State_Eq;
+							elsif tOpcode(5 downto 0)=OpCode_Lessthan then
+								tNextState :=State_Lessthan;
+							elsif tOpcode(5 downto 0)=OpCode_Lessthanorequal then
+								--tNextState :=State_Lessthanorequal;
+							elsif tOpcode(5 downto 0)=OpCode_Ulessthan then
+								tNextState :=State_Ulessthan;
+							elsif tOpcode(5 downto 0)=OpCode_Ulessthanorequal then
+								--tNextState :=State_Ulessthanorequal;
+							elsif tOpcode(5 downto 0)=OpCode_Loadb then
+								tNextState :=State_Loadb;
+							elsif tOpcode(5 downto 0)=OpCode_Mult then
+								tNextState :=State_Mult;
+							elsif tOpcode(5 downto 0)=OpCode_Storeb then
+								tNextState :=State_Storeb;
+							elsif tOpcode(5 downto 0)=OpCode_Pushspadd then
+								tNextState :=State_Pushspadd;
+							elsif tOpcode(5 downto 0)=OpCode_Callpcrel then
+								tNextState :=State_Callpcrel;
+							elsif tOpcode(5 downto 0)=OpCode_Call then
+								--tNextState :=State_Call;
+							elsif tOpcode(5 downto 0)=OpCode_Sub then
+								tNextState :=State_Sub;
+							elsif tOpcode(5 downto 0)=OpCode_PopPCRel then
+								--tNextState :=State_PopPCRel;
+							end if;								
+						elsif (tOpcode(7 downto 4)=OpCode_AddSP) then
+							if tSpOffset = 0 then
+								tNextState := State_Shift;
+							elsif tSpOffset = 1 then
+								tNextState := State_AddTop;
+							else
+								tNextState :=State_AddSP;
+							end if;
+						else
+							case tOpcode(3 downto 0) is
+								when OpCode_Nop =>
+									tNextState :=State_Nop;
+								when OpCode_PushSP =>
+									tNextState :=State_PushSP;
+								when OpCode_PopPC =>
+									tNextState :=State_PopPC;
+								when OpCode_Add =>
+									tNextState :=State_Add;
+								when OpCode_Or =>
+									tNextState :=State_Or;
+								when OpCode_And =>
+									tNextState :=State_And;
+								when OpCode_Load =>
+									tNextState :=State_Load;
+								when OpCode_Not =>
+									tNextState :=State_Not;
+								when OpCode_Flip =>
+									tNextState :=State_Flip;
+								when OpCode_Store =>
+									tNextState :=State_Store;
+								when OpCode_PopSP =>
+									tNextState :=State_PopSP;
+								when others =>
+									tNextState := State_Break;
+
+							end case;
+						end if;
+						tDecodedOpcode(i) := tNextState;
+						
+					end loop;
+					
+					insn <= tDecodedOpcode(conv_integer(pc(byteBits-1 downto 0)));
+					
+					-- once we wrap, we need to fetch
+					tDecodedOpcode(0) := State_InsnFetch;
+
+					decodedOpcode <= tDecodedOpcode;
+					state <= State_Execute;
+						
+
+
+					-- Each instruction must:
+					--
+					-- 1. set idim_flag
+					-- 2. increase pc if applicable
+					-- 3. set next state if appliable
+					-- 4. do it's operation
+					 
+				when State_Execute =>
+					insn <= decodedOpcode(conv_integer(nextPC(byteBits-1 downto 0)));
+									
+					case insn is
+						when State_InsnFetch =>
+							state <= State_Fetch;
+						when State_Im =>
+							if mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '1';
+								pc <= pc + 1;
+								
+								if idim_flag='1' then 
+									stackA(wordSize-1 downto 7) <= stackA(wordSize-8 downto 0);
+									stackA(6 downto 0) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6 downto 0);
+								else
+									out_mem_req <= '1';
+									mem_we <= '1';
+									mem_addr <= incSp;
+									mem_write <= stackB;
+									stackB <= stackA;
+									sp <= decSp;
+									for i in wordSize-1 downto 7 loop
+										stackA(i) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6);
+									end loop;
+									stackA(6 downto 0) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6 downto 0);
+								end if;
+							else	
+								insn <= insn;
+							end if;
+						when State_StoreSP =>
+							if mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								state <= State_StoreSP2;
+								
+								out_mem_req <= '1';
+								mem_we <= '1';
+								mem_addr <= sp+spOffset;
+								mem_write <= stackA;
+								stackA <= stackB;
+								sp <= incSp;
+							else	
+								insn <= insn;
+							end if;
+
+					
+						when State_LoadSP =>
+							if mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								state <= State_LoadSP2;
+		
+								sp <= decSp;
+								out_mem_req <= '1';
+								mem_we <= '1';
+								mem_addr <= incSp;
+								mem_write <= stackB;
+							else	
+								insn <= insn;
+							end if;
+						when State_Emulate =>
+							if mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								sp <= decSp;
+								out_mem_req <= '1';
+								mem_we <= '1';
+								mem_addr <= incSp;
+								mem_write <= stackB;
+								stackA <= (others => DontCareValue);
+								stackA(maxAddrBitIncIO downto 0) <= pc + 1;
+								stackB <= stackA;
+								
+								-- The emulate address is:
+								--        98 7654 3210
+								-- 0000 00aa aaa0 0000
+								pc <= (others => '0');
+								pc(9 downto 5) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(4 downto 0);
+								state <= State_Fetch;
+							else	
+								insn <= insn;
+							end if;
+						when State_Callpcrel =>
+							if mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								stackA <= (others => DontCareValue);
+								stackA(maxAddrBitIncIO downto 0) <= pc + 1;
+								
+								pc <= pc + stackA(maxAddrBitIncIO downto 0);
+								state <= State_Fetch;
+							else	
+								insn <= insn;
+							end if;
+						when State_Call =>
+							if mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								stackA <= (others => DontCareValue);
+								stackA(maxAddrBitIncIO downto 0) <= pc + 1;
+								pc <= stackA(maxAddrBitIncIO downto 0);
+								state <= State_Fetch;
+							else	
+								insn <= insn;
+							end if;
+						when State_AddSP =>
+							if mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								state <= State_AddSP2;
+								
+								out_mem_req <= '1';
+								mem_addr <= sp+spOffset;
+							else	
+								insn <= insn;
+							end if;
+						when State_PushSP =>
+							if mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								pc <= pc + 1;
+								
+								sp <= decSp;
+								stackA <= (others => '0');
+								stackA(maxAddrBitIncIO downto minAddrBit) <= sp;
+								stackB <= stackA;
+								out_mem_req <= '1';
+								mem_we <= '1';
+								mem_addr <= incSp;
+								mem_write <= stackB;
+							else	
+								insn <= insn;
+							end if;
+						when State_PopPC =>
+							if mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								pc <= stackA(maxAddrBitIncIO downto 0);
+								sp <= incSp;
+								
+								out_mem_req <= '1';
+								mem_we <= '1';
+								mem_addr <= incSp;
+								mem_write <= stackB;
+								state <= State_Resync;
+							else	
+								insn <= insn;
+							end if;
+						when State_PopPCRel =>
+							if mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								pc <= stackA(maxAddrBitIncIO downto 0) + pc;
+								sp <= incSp;
+								
+								out_mem_req <= '1';
+								mem_we <= '1';
+								mem_addr <= incSp;
+								mem_write <= stackB;
+								state <= State_Resync;
+							else	
+								insn <= insn;
+							end if;
+						when State_Add =>
+							if mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								stackA <= stackA + stackB;
+								
+								out_mem_req <= '1';
+								mem_addr <= incIncSp;
+								sp <= incSp;
+								state <= State_Popped;
+							else	
+								insn <= insn;
+							end if;
+						when State_Sub =>
+							begin_inst <= '1';
+							idim_flag <= '0';
+							binaryOpResult <= stackB - stackA;
+							state <= State_BinaryOpResult;
+						when State_Pop =>
+							if mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								mem_addr <= incIncSp;
+								out_mem_req <= '1';
+								sp <= incSp;
+								stackA <= stackB;
+								state <= State_Popped;						
+							else	
+								insn <= insn;
+							end if;
+						when State_PopDown =>
+							if mem_busy='0' then
+								-- PopDown leaves top of stack unchanged
+								begin_inst <= '1';
+								idim_flag <= '0';
+								mem_addr <= incIncSp;
+								out_mem_req <= '1';
+								sp <= incSp;
+								state <= State_Popped;						
+							else	
+								insn <= insn;
+							end if;
+						when State_Or =>
+							if mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								stackA <= stackA or stackB;
+								out_mem_req <= '1';
+								mem_addr <= incIncSp;
+								sp <= incSp;
+								state <= State_Popped;
+							else	
+								insn <= insn;
+							end if;
+						when State_And =>
+							if mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+		
+								stackA <= stackA and stackB;
+								out_mem_req <= '1';
+								mem_addr <= incIncSp;
+								sp <= incSp;
+								state <= State_Popped;
+							else	
+								insn <= insn;
+							end if;
+						when State_Eq =>
+							begin_inst <= '1';
+							idim_flag <= '0';
+	
+		            		binaryOpResult <= (others => '0');
+		                	if (stackA=stackB) then
+		                		binaryOpResult(0) <= '1';
+		                	end if;
+							state <= State_BinaryOpResult;
+		                when State_Ulessthan =>
+							begin_inst <= '1';
+							idim_flag <= '0';
+	
+		            		binaryOpResult <= (others => '0');
+		                	if (stackA<stackB) then
+		                		binaryOpResult(0) <= '1';
+		                	end if;
+							state <= State_BinaryOpResult;
+		                when State_Ulessthanorequal =>
+							begin_inst <= '1';
+							idim_flag <= '0';
+	
+		            		binaryOpResult <= (others => '0');
+		                	if (stackA<=stackB) then
+		                		binaryOpResult(0) <= '1';
+		                	end if;
+							state <= State_BinaryOpResult;
+		                when State_Lessthan =>
+							begin_inst <= '1';
+							idim_flag <= '0';
+	
+		            		binaryOpResult <= (others => '0');
+		                	if (signed(stackA)<signed(stackB)) then
+		                		binaryOpResult(0) <= '1';
+		                	end if;
+							state <= State_BinaryOpResult;
+		                when State_Lessthanorequal =>
+							begin_inst <= '1';
+							idim_flag <= '0';
+	
+		            		binaryOpResult <= (others => '0');
+		                	if (signed(stackA)<=signed(stackB)) then
+		                		binaryOpResult(0) <= '1';
+		                	end if;
+							state <= State_BinaryOpResult;
+						when State_Load =>
+							if mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								state <= State_Load2;
+								
+								mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit);
+								out_mem_req <= '1';
+							else	
+								insn <= insn;
+							end if;
+
+						when State_Dup =>
+							if mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								pc <= pc + 1; 
+								
+								sp <= decSp;
+								stackB <= stackA;
+								mem_write <= stackB;
+								mem_addr <= incSp;
+								out_mem_req <= '1';
+								mem_we <= '1';
+							else	
+								insn <= insn;
+							end if;
+						when State_DupStackB =>
+							if mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								pc <= pc + 1; 
+								
+								sp <= decSp;
+								stackA <= stackB;
+								stackB <= stackA;
+								mem_write <= stackB;
+								mem_addr <= incSp;
+								out_mem_req <= '1';
+								mem_we <= '1';
+							else	
+								insn <= insn;
+							end if;
+						when State_Store =>
+							if mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								pc <= pc + 1;
+								mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit);
+								mem_write <= stackB;
+								out_mem_req <= '1';
+								mem_we <= '1';
+								sp <= incIncSp;
+								state <= State_Resync;
+							else	
+								insn <= insn;
+							end if;
+						when State_PopSP =>
+							if mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								pc <= pc + 1;
+								
+								mem_write <= stackB;
+								mem_addr <= incSp;
+								out_mem_req <= '1';
+								mem_we <= '1';
+								sp <= stackA(maxAddrBitIncIO downto minAddrBit);
+								state <= State_Resync;
+							else	
+								insn <= insn;
+							end if;
+						when State_Nop =>	
+							begin_inst <= '1';
+							idim_flag <= '0';
+							pc <= pc + 1;
+						when State_Not =>
+							begin_inst <= '1';
+							idim_flag <= '0';
+							pc <= pc + 1; 
+							
+							stackA <= not stackA;
+						when State_Flip =>
+							begin_inst <= '1';
+							idim_flag <= '0';
+							pc <= pc + 1; 
+							
+							for i in 0 to wordSize-1 loop
+								stackA(i) <= stackA(wordSize-1-i);
+				  			end loop;
+						when State_AddTop =>
+							begin_inst <= '1';
+							idim_flag <= '0';
+							pc <= pc + 1; 
+							
+							stackA <= stackA + stackB;
+						when State_Shift =>
+							begin_inst <= '1';
+							idim_flag <= '0';
+							pc <= pc + 1; 
+							
+							stackA(wordSize-1 downto 1) <= stackA(wordSize-2 downto 0);
+							stackA(0) <= '0';
+						when State_Pushspadd =>
+							begin_inst <= '1';
+							idim_flag <= '0';
+							pc <= pc + 1; 
+							
+							stackA <= (others => '0');
+							stackA(maxAddrBitIncIO downto minAddrBit) <= stackA(maxAddrBitIncIO-minAddrBit downto 0)+sp;
+						when State_Neqbranch =>
+							-- branches are almost always taken as they form loops
+							begin_inst <= '1';
+							idim_flag <= '0';
+							sp <= incIncSp;
+		                	if (stackB/=0) then
+		                		pc <= stackA(maxAddrBitIncIO downto 0) + pc;
+		                	else
+		                		pc <= pc + 1;
+		                	end if;		
+		                	-- need to fetch stack again.				
+							state <= State_Resync;
+		                when State_Mult =>
+							begin_inst <= '1';
+							idim_flag <= '0';
+		
+							multA <= stackA;
+							multB <= stackB;
+							state <= State_Mult2;
+						when State_Break =>
+							report "Break instruction encountered" severity failure;
+							break <= '1';
+
+						when State_Loadb =>
+							if mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								state <= State_Loadb2;
+								
+								mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit);
+								out_mem_req <= '1';
+							else	
+								insn <= insn;
+							end if;
+						when State_Storeb =>
+							if mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								state <= State_Storeb2;
+								
+								mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit);
+								out_mem_req <= '1';
+							else	
+								insn <= insn;
+							end if;
+				
+						when others =>
+--							sp <= (others => DontCareValue);
+							report "Illegal instruction" severity failure;
+							break <= '1';
+					end case;
+
+
+				when State_StoreSP2 =>
+					if mem_busy='0' then
+						mem_addr <= incSp;
+						out_mem_req <= '1';
+						state <= State_Popped;
+					end if;
+				when State_LoadSP2 =>
+					if mem_busy='0' then
+						state <= State_LoadSP3;
+						out_mem_req <= '1';
+						mem_addr <= sp+spOffset+1;
+					end if;
+				when State_LoadSP3 =>
+					if mem_busy='0' then
+						pc <= pc + 1;
+						state <= State_Execute;
+						stackB <= stackA;
+						stackA <= mem_read;
+					end if;
+				when State_AddSP2 =>
+					if mem_busy='0' then
+						pc <= pc + 1;
+						state <= State_Execute;
+						stackA <= stackA + mem_read;
+					end if;
+				when State_Load2 =>
+					if mem_busy='0' then
+						stackA <= mem_read;
+						pc <= pc + 1;
+						state <= State_Execute;
+					end if;
+				when State_Loadb2 =>
+					if mem_busy='0' then
+						stackA <= (others => '0');
+						stackA(7 downto 0) <= mem_read(((wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8);
+						pc <= pc + 1;
+						state <= State_Execute;
+					end if;
+				when State_Storeb2 =>
+					if mem_busy='0' then
+						mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit);
+						mem_write <= mem_read;
+						mem_write(((wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8) <= stackB(7 downto 0) ;
+						out_mem_req <= '1';
+						mem_we <= '1';
+						pc <= pc + 1;
+						sp <= incIncSp;
+						state <= State_Resync;
+					end if;
+				when State_Fetch =>
+					if mem_busy='0' then
+						if interrupt='1' and inInterrupt='0' and idim_flag='0' then
+							-- We got an interrupt
+							inInterrupt <= '1';
+							
+							sp <= decSp;
+							out_mem_req <= '1';
+							mem_we <= '1';
+							mem_addr <= incSp;
+							mem_write <= stackB;
+							stackA <= (others => DontCareValue);
+							stackA(maxAddrBitIncIO downto 0) <= pc;
+							stackB <= stackA;
+							
+							pc <= conv_std_logic_vector(32, maxAddrBitIncIo+1); -- interrupt address
+							
+			  				report "ZPU jumped to interrupt!" severity note;
+						else
+							mem_addr <= pc(maxAddrBitIncIO downto minAddrBit);
+							out_mem_req <= '1';
+							state <= State_Decode;
+						end if;
+					end if;
+                when State_Mult2 =>
+					state <= State_Mult3;
+                when State_Mult3 =>
+					state <= State_Mult4;
+                when State_Mult4 =>
+					state <= State_Mult5;
+                when State_Mult5 =>
+            		stackA <= multResult3;
+                	state <= State_Mult6;
+                when State_Mult6 =>
+					if mem_busy='0' then
+						out_mem_req <= '1';
+						mem_addr <= incIncSp;
+						sp <= incSp;
+						state <= State_Popped;
+					end if;
+				when State_BinaryOpResult =>
+					if mem_busy='0' then
+						-- NB!!!! we know that the memory isn't busy at this point!!!!
+						out_mem_req <= '1';
+						mem_addr <= incIncSp;
+						sp <= incSp;
+						stackA <= binaryOpResult;
+						state <= State_Popped;
+					end if;
+				when State_Popped =>
+					if mem_busy='0' then
+						pc <= pc + 1;
+						stackB <= mem_read;
+						state <= State_Execute;
+					end if;
+				when others =>	
+--					sp <= (others => DontCareValue);
+					report "Illegal state" severity failure;
+					break <= '1';
+			end case;
+		end if;
+	end process;
+
+
+
+end behave;
diff --git a/fpga/usrp3/lib/zpu/core/zpupkg.vhd b/fpga/usrp3/lib/zpu/core/zpupkg.vhd
new file mode 100644
index 000000000..a7e6cf1d0
--- /dev/null
+++ b/fpga/usrp3/lib/zpu/core/zpupkg.vhd
@@ -0,0 +1,168 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+
+library work;
+use work.zpu_config.all;
+
+package zpupkg is
+
+	-- This bit is set for read/writes to IO
+	-- FIX!!! eventually this should be set to wordSize-1 so as to
+	-- to make the address of IO independent of amount of memory
+	-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
+	-- libraries.
+	
+	constant byteBits			: integer := wordPower-3; -- # of bits in a word that addresses bytes
+	constant maxAddrBit			: integer := maxAddrBitIncIO-1;
+	constant ioBit				: integer := maxAddrBit+1;
+	constant wordSize			: integer := 2**wordPower;
+	constant wordBytes			: integer := wordSize/8;
+	constant minAddrBit			: integer := byteBits;
+	-- configurable internal stack size. Probably going to be 16 after toolchain is done
+	constant	stack_bits		: integer := 5; 
+	constant	stack_size		: integer := 2**stack_bits; 
+
+	component dualport_ram is
+	port (clk : in std_logic;
+		memAWriteEnable : in std_logic;
+		memAAddr : in std_logic_vector(maxAddrBit downto minAddrBit);
+		memAWrite : in std_logic_vector(wordSize-1 downto 0);
+		memARead : out std_logic_vector(wordSize-1 downto 0);
+		memBWriteEnable : in std_logic;
+		memBAddr : in std_logic_vector(maxAddrBit downto minAddrBit);
+		memBWrite : in std_logic_vector(wordSize-1 downto 0);
+		memBRead : out std_logic_vector(wordSize-1 downto 0));
+	end component;
+
+	component dram is
+		port (clk : in std_logic;
+			areset : in std_logic;
+			mem_writeEnable : in std_logic;
+			mem_readEnable : in std_logic;
+			mem_addr : in std_logic_vector(maxAddrBit downto 0);
+			mem_write : in std_logic_vector(wordSize-1 downto 0);
+			mem_read : out std_logic_vector(wordSize-1 downto 0);
+			mem_busy : out std_logic;
+			mem_writeMask : in std_logic_vector(wordBytes-1 downto 0));
+	end component;
+
+
+	component trace is
+	  port(
+	       	clk         : in std_logic;
+	       	begin_inst  : in std_logic;
+	       	pc          : in std_logic_vector(maxAddrBitIncIO downto 0);
+			opcode		: in std_logic_vector(7 downto 0);
+			sp			: in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
+			memA		: in std_logic_vector(wordSize-1 downto 0);
+			memB		: in std_logic_vector(wordSize-1 downto 0);
+			busy         : in std_logic;
+			intSp		: in std_logic_vector(stack_bits-1 downto 0)
+			);
+	end component;
+
+	component zpu_core is
+    port ( clk : in std_logic;
+	 		  areset : in std_logic;
+	 		  enable : in std_logic; 
+	 		  mem_req : out std_logic;
+	 		  mem_we : out std_logic;
+	 		  mem_ack : in std_logic; 
+	 		  mem_read : in std_logic_vector(wordSize-1 downto 0);
+	 		  mem_write : out std_logic_vector(wordSize-1 downto 0);
+			  out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0);
+	 		  mem_writeMask: out std_logic_vector(wordBytes-1 downto 0);
+	 		  interrupt : in std_logic;
+	 		  break : out std_logic;
+	 		  zpu_status : out std_logic_vector(63 downto 0));
+	end component;
+
+
+	
+	component timer is
+  	port(
+       	clk             : in std_logic;
+		areset			: in std_logic;
+		sample			: in std_logic;
+		reset			: in std_logic;
+		counter			: out std_logic_vector(63 downto 0));
+	end component;
+
+	component  zpuio is
+		port (	areset			: in std_logic;
+				cpu_clk			: in std_logic;
+				clk_status		: in std_logic_vector(2 downto 0);
+				cpu_din			: in std_logic_vector(15 downto 0);
+				cpu_a			: in std_logic_vector(20 downto 0);
+				cpu_we			: in std_logic_vector(1 downto 0);
+				cpu_re			: in std_logic;
+				cpu_dout		: inout std_logic_vector(15 downto 0));
+	end component;
+
+
+
+	
+	-- opcode decode constants
+	constant	OpCode_Im		: std_logic_vector(7 downto 7) := "1";
+	constant	OpCode_StoreSP	: std_logic_vector(7 downto 5) := "010";
+	constant	OpCode_LoadSP	: std_logic_vector(7 downto 5) := "011";
+	constant	OpCode_Emulate	: std_logic_vector(7 downto 5) := "001";
+	constant	OpCode_AddSP	: std_logic_vector(7 downto 4) := "0001";
+	constant	OpCode_Short	: std_logic_vector(7 downto 4) := "0000";
+	
+	constant	OpCode_Break	: std_logic_vector(3 downto 0) := "0000";
+	constant	OpCode_Shiftleft: std_logic_vector(3 downto 0) := "0001";
+	constant	OpCode_PushSP	: std_logic_vector(3 downto 0) := "0010";
+	constant	OpCode_PushInt	: std_logic_vector(3 downto 0) := "0011";
+	
+	constant	OpCode_PopPC	: std_logic_vector(3 downto 0) := "0100";
+	constant	OpCode_Add		: std_logic_vector(3 downto 0) := "0101";
+	constant	OpCode_And		: std_logic_vector(3 downto 0) := "0110";
+	constant	OpCode_Or		: std_logic_vector(3 downto 0) := "0111";
+	
+	constant	OpCode_Load		: std_logic_vector(3 downto 0) := "1000";
+	constant	OpCode_Not		: std_logic_vector(3 downto 0) := "1001";
+	constant	OpCode_Flip		: std_logic_vector(3 downto 0) := "1010";
+	constant	OpCode_Nop		: std_logic_vector(3 downto 0) := "1011";
+	
+	constant	OpCode_Store	: std_logic_vector(3 downto 0) := "1100";
+	constant	OpCode_PopSP	: std_logic_vector(3 downto 0) := "1101";
+	constant	OpCode_Compare	: std_logic_vector(3 downto 0) := "1110";
+	constant	OpCode_PopInt	: std_logic_vector(3 downto 0) := "1111";
+	
+	constant	OpCode_Lessthan				: std_logic_vector(5 downto 0) := conv_std_logic_vector(36, 6);
+	constant	OpCode_Lessthanorequal		: std_logic_vector(5 downto 0) := conv_std_logic_vector(37, 6);
+	constant	OpCode_Ulessthan			: std_logic_vector(5 downto 0) := conv_std_logic_vector(38, 6);
+	constant	OpCode_Ulessthanorequal		: std_logic_vector(5 downto 0) := conv_std_logic_vector(39, 6);
+
+	constant	OpCode_Swap					: std_logic_vector(5 downto 0) := conv_std_logic_vector(40, 6);
+	constant	OpCode_Mult					: std_logic_vector(5 downto 0) := conv_std_logic_vector(41, 6);
+	
+	constant	OpCode_Lshiftright			: std_logic_vector(5 downto 0) := conv_std_logic_vector(42, 6);
+	constant	OpCode_Ashiftleft			: std_logic_vector(5 downto 0) := conv_std_logic_vector(43, 6);
+	constant	OpCode_Ashiftright			: std_logic_vector(5 downto 0) := conv_std_logic_vector(44, 6);
+	constant	OpCode_Call					: std_logic_vector(5 downto 0) := conv_std_logic_vector(45, 6);
+
+	constant	OpCode_Eq					: std_logic_vector(5 downto 0) := conv_std_logic_vector(46, 6);
+	constant	OpCode_Neq					: std_logic_vector(5 downto 0) := conv_std_logic_vector(47, 6);
+
+	constant	OpCode_Sub					: std_logic_vector(5 downto 0) := conv_std_logic_vector(49, 6);
+	constant	OpCode_Loadb				: std_logic_vector(5 downto 0) := conv_std_logic_vector(51, 6);
+	constant	OpCode_Storeb				: std_logic_vector(5 downto 0) := conv_std_logic_vector(52, 6);
+
+	constant	OpCode_Eqbranch				: std_logic_vector(5 downto 0) := conv_std_logic_vector(55, 6);
+	constant	OpCode_Neqbranch			: std_logic_vector(5 downto 0) := conv_std_logic_vector(56, 6);
+	constant	OpCode_Poppcrel				: std_logic_vector(5 downto 0) := conv_std_logic_vector(57, 6);
+
+	constant	OpCode_Pushspadd			: std_logic_vector(5 downto 0) := conv_std_logic_vector(61, 6);
+	constant	OpCode_Mult16x16			: std_logic_vector(5 downto 0) := conv_std_logic_vector(62, 6);
+	constant	OpCode_Callpcrel			: std_logic_vector(5 downto 0) := conv_std_logic_vector(63, 6);
+	
+
+
+	constant OpCode_Size		: integer := 8;
+
+
+		
+end zpupkg;
diff --git a/fpga/usrp3/lib/zpu/wishbone/wishbone_pkg.vhd b/fpga/usrp3/lib/zpu/wishbone/wishbone_pkg.vhd
new file mode 100644
index 000000000..fbe9fc1d5
--- /dev/null
+++ b/fpga/usrp3/lib/zpu/wishbone/wishbone_pkg.vhd
@@ -0,0 +1,86 @@
+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - �yvind Harboe - oyvind.harboe@zylin.com
+-- 
+-- The FreeBSD license
+-- 
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+-- 
+-- 1. Redistributions of source code must retain the above copyright
+--    notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+--    copyright notice, this list of conditions and the following
+--    disclaimer in the documentation and/or other materials
+--    provided with the distribution.
+-- 
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+-- 
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+package wishbone_pkg is
+
+	type wishbone_bus_in is record
+		adr			: std_logic_vector(15 downto 0); 
+		sel			: std_logic_vector(3 downto 0); 
+		we			: std_logic;
+		dat			: std_logic_vector(31 downto 0); 	-- Note! Data written with 'we'
+		cyc			: std_logic; 
+		stb			: std_logic;
+	end record;
+
+	type wishbone_bus_out is record
+		dat		: std_logic_vector(31 downto 0);
+		ack			: std_logic;
+	end record;
+	
+	type wishbone_bus is record
+		insig		: wishbone_bus_in;
+		outsig  	: wishbone_bus_out;
+	end record;
+
+	component atomic32_access is
+	port (	cpu_clk			: in std_logic;
+			areset			: in std_logic;
+	
+			-- Wishbone from CPU interface
+			wb_16_i			: in wishbone_bus_in;
+			wb_16_o     	: out wishbone_bus_out;
+			-- Wishbone to FPGA registers and ethernet core
+			wb_32_i			: in wishbone_bus_out;
+			wb_32_o			: out wishbone_bus_in);
+	end component;
+	
+	component eth_access_corr is
+	port (	cpu_clk			: in std_logic;
+			areset			: in std_logic;
+	
+			-- Wishbone from Wishbone MUX
+			eth_raw_o		: out wishbone_bus_out;
+			eth_raw_i		: in wishbone_bus_in;
+			
+			-- Wishbone ethernet core
+			eth_slave_i 	: in wishbone_bus_out;
+			eth_slave_o		: out wishbone_bus_in);
+	end component;
+
+
+end wishbone_pkg;
diff --git a/fpga/usrp3/lib/zpu/wishbone/zpu_system.vhd b/fpga/usrp3/lib/zpu/wishbone/zpu_system.vhd
new file mode 100644
index 000000000..976997123
--- /dev/null
+++ b/fpga/usrp3/lib/zpu/wishbone/zpu_system.vhd
@@ -0,0 +1,105 @@
+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - �yvind Harboe - oyvind.harboe@zylin.com
+-- 
+-- The FreeBSD license
+-- 
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+-- 
+-- 1. Redistributions of source code must retain the above copyright
+--    notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+--    copyright notice, this list of conditions and the following
+--    disclaimer in the documentation and/or other materials
+--    provided with the distribution.
+-- 
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+-- 
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.all; 
+
+library work;
+use work.zpu_top_pkg.all;
+use work.wishbone_pkg.all;
+use work.zpupkg.all;
+use work.zpu_config.all;
+
+entity zpu_system is
+	generic(
+			simulate		: boolean := false);
+	port (	areset			: in std_logic;
+			cpu_clk			: in std_logic;
+
+			-- ZPU Control signals
+			enable			: in std_logic;
+			interrupt		: in std_logic;
+
+			zpu_status		: out std_logic_vector(63 downto 0);
+
+			-- wishbone interfaces
+			zpu_wb_i		: in wishbone_bus_out;
+			zpu_wb_o		: out wishbone_bus_in);
+end zpu_system;
+
+architecture behave of zpu_system is
+
+signal	mem_req					: std_logic;
+signal	mem_we 					: std_logic;
+signal	mem_ack 				: std_logic; 
+signal	mem_read 				: std_logic_vector(wordSize-1 downto 0);
+signal	mem_write 				: std_logic_vector(wordSize-1 downto 0);
+signal	out_mem_addr 			: std_logic_vector(maxAddrBitIncIO downto 0);
+signal	mem_writeMask			: std_logic_vector(wordBytes-1 downto 0);
+
+
+begin
+
+	my_zpu_core:
+	zpu_core port map (
+    	clk 				=> cpu_clk, 
+		areset 				=> areset,
+	 	enable 				=> enable,
+	  	mem_req 			=> mem_req,
+	 	mem_we 				=> mem_we,
+	 	mem_ack 			=> mem_ack, 
+	 	mem_read 			=> mem_read,
+	 	mem_write 			=> mem_write,
+		out_mem_addr 		=> out_mem_addr,
+	 	mem_writeMask		=> mem_writeMask,
+	 	interrupt			=> interrupt,
+	 	zpu_status			=> zpu_status,
+	 	break				=> open);
+
+	my_zpu_wb_bridge:
+	zpu_wb_bridge port map (
+		clk 				=> cpu_clk,
+	 	areset 				=> areset,
+	  	mem_req 			=> mem_req,
+	 	mem_we 				=> mem_we,
+	 	mem_ack 			=> mem_ack, 
+	 	mem_read 			=> mem_read,
+	 	mem_write 			=> mem_write,
+		out_mem_addr 		=> out_mem_addr,
+	 	mem_writeMask		=> mem_writeMask,
+		zpu_wb_i			=> zpu_wb_i,
+		zpu_wb_o			=> zpu_wb_o);
+
+end behave;
diff --git a/fpga/usrp3/lib/zpu/wishbone/zpu_wb_bridge.vhd b/fpga/usrp3/lib/zpu/wishbone/zpu_wb_bridge.vhd
new file mode 100644
index 000000000..3eb46d82e
--- /dev/null
+++ b/fpga/usrp3/lib/zpu/wishbone/zpu_wb_bridge.vhd
@@ -0,0 +1,83 @@
+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - �yvind Harboe - oyvind.harboe@zylin.com
+-- 
+-- The FreeBSD license
+-- 
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+-- 
+-- 1. Redistributions of source code must retain the above copyright
+--    notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+--    copyright notice, this list of conditions and the following
+--    disclaimer in the documentation and/or other materials
+--    provided with the distribution.
+-- 
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+-- 
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+library work;
+use work.zpu_top_pkg.all;
+use work.wishbone_pkg.all;
+use work.zpupkg.all;
+use work.zpu_config.all;
+
+entity zpu_wb_bridge is
+	port (	-- Native ZPU interface
+ 			clk 				: in std_logic;
+	 		areset 				: in std_logic;
+
+	 		mem_req 			: in std_logic;
+	 		mem_we				: in std_logic;
+	 		mem_ack				: out std_logic; 
+	 		mem_read 			: out std_logic_vector(wordSize-1 downto 0);
+	 		mem_write 			: in std_logic_vector(wordSize-1 downto 0);
+			out_mem_addr 		: in std_logic_vector(maxAddrBitIncIO downto 0);
+	 		mem_writeMask		: in std_logic_vector(wordBytes-1 downto 0);
+			
+			-- Wishbone from ZPU
+			zpu_wb_i			: in wishbone_bus_out;
+			zpu_wb_o			: out wishbone_bus_in);
+
+end zpu_wb_bridge;
+
+architecture behave of zpu_wb_bridge is
+
+begin
+
+	mem_read <= zpu_wb_i.dat;
+	mem_ack <= zpu_wb_i.ack;
+	
+	zpu_wb_o.adr <= out_mem_addr;
+	zpu_wb_o.dat <= mem_write;
+	zpu_wb_o.sel <= mem_writeMask;
+	zpu_wb_o.stb <= mem_req;
+	zpu_wb_o.cyc <= mem_req;
+	zpu_wb_o.we <= mem_we;
+
+end behave;
+
+			
+
+	
+
diff --git a/fpga/usrp3/lib/zpu/zpu_bootram.v b/fpga/usrp3/lib/zpu/zpu_bootram.v
new file mode 100644
index 000000000..04cb83f26
--- /dev/null
+++ b/fpga/usrp3/lib/zpu/zpu_bootram.v
@@ -0,0 +1,125 @@
+//
+// Copyright 2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+module zpu_bootram #(
+    parameter ADDR_WIDTH    = 16,
+    parameter DATA_WIDTH    = 32,
+    parameter MAX_ADDR      = 16'h7FFC
+) (
+    input                   clk,
+    input                   rst,
+
+    input                   mem_stb,
+    input                   mem_wea,
+    input  [ADDR_WIDTH-1:0] mem_addra,
+    input  [DATA_WIDTH-1:0] mem_dina,
+    output [DATA_WIDTH-1:0] mem_douta,
+    output reg              mem_acka,
+
+    input                   ldr_stb,
+    input                   ldr_wea,
+    input  [ADDR_WIDTH-1:0] ldr_addra,
+    input  [DATA_WIDTH-1:0] ldr_dina,
+    output                  ldr_acka,
+    
+    output reg              zpu_rst
+);
+    localparam SR_LDR_ADDR_REG  = 4'h0;
+    localparam SR_LDR_DATA_REG  = 4'h1;
+    
+    //---------------------------------------------------------
+    // Mem ack logic
+    always @(posedge clk) begin
+        if (rst) mem_acka <= 0;
+        else     mem_acka <= mem_stb & ~mem_acka;
+    end
+
+    //---------------------------------------------------------
+    // Instantiate 2 bootram modules
+    // They will both initialize with the pre-built ZPU firmware
+    //
+    wire        ram0_ena, ram1_ena;
+    wire [3:0]  ram0_wea, ram1_wea;
+    wire [12:0] ram0_addra, ram1_addra;
+    wire [31:0] ram0_dina, ram0_douta, ram1_dina, ram1_douta;
+    
+    bootram sys_ram0(
+        .clka(clk),
+        .ena(ram0_ena),
+        .wea(ram0_wea),
+        .addra(ram0_addra),
+        .dina(ram0_dina),
+        .douta(ram0_douta));
+
+    bootram sys_ram1(
+        .clka(clk),
+        .ena(ram1_ena),
+        .wea(ram1_wea),
+        .addra(ram1_addra),
+        .dina(ram1_dina),
+        .douta(ram1_douta));
+      
+    //---------------------------------------------------------
+    // Settings bus interface for bootloader
+    wire                    ldr_set_stb;
+    wire [3:0]              ldr_set_addr;
+    wire [DATA_WIDTH-1:0]   ldr_set_data;
+
+    //@TODO: This address truncation seems unclean. Maybe settings_bus can take a addr_width as a param.
+    wire [7:0]              ldr_set_addr_w;
+    settings_bus #(.AWIDTH(ADDR_WIDTH), .DWIDTH(DATA_WIDTH)) ldr_settings_bus
+    (
+        .wb_clk(clk), .wb_rst(rst),
+        .wb_adr_i(ldr_addra), .wb_dat_i(ldr_dina), 
+        .wb_stb_i(ldr_stb), .wb_we_i(ldr_wea), .wb_ack_o(ldr_acka),
+        .strobe(ldr_set_stb), .addr(ldr_set_addr_w), .data(ldr_set_data)
+    );
+    assign ldr_set_addr = ldr_set_addr_w[3:0];
+
+    //---------------------------------------------------------
+    // Selection logic
+    //
+    reg             bootram_ptr;
+    reg [12:0]      ldr_curr_wr_addr;
+    wire            ldr_we_stb;
+
+    assign {ram0_ena, ram0_wea, ram0_addra, ram0_dina} = bootram_ptr ? {mem_stb, {4{(mem_wea & ~zpu_rst)}}, mem_addra[14:2], mem_dina} : 
+                                                                       {ldr_we_stb, {4{ldr_we_stb}}, ldr_curr_wr_addr, ldr_set_data};
+    assign {ram1_ena, ram1_wea, ram1_addra, ram1_dina} = bootram_ptr ? {ldr_we_stb, {4{ldr_we_stb}}, ldr_curr_wr_addr, ldr_set_data} : 
+                                                                       {mem_stb, {4{(mem_wea & ~zpu_rst)}}, mem_addra[14:2], mem_dina};
+    assign mem_douta                                   = bootram_ptr ? ram0_douta : ram1_douta;
+
+    //---------------------------------------------------------
+    // Boot loader
+    //
+    assign ldr_we_stb = ~zpu_rst && ldr_set_stb && (ldr_set_addr == SR_LDR_DATA_REG);
+
+    always @(posedge clk) begin
+        if (rst) begin
+            zpu_rst             <= 1;
+            bootram_ptr         <= 1;
+            ldr_curr_wr_addr    <= 13'h0;
+        end else if (ldr_set_stb & ~zpu_rst) begin
+            case (ldr_set_addr)
+                SR_LDR_ADDR_REG: begin
+                    ldr_curr_wr_addr <= ldr_set_data[14:2];
+                end
+                SR_LDR_DATA_REG: begin
+                    ldr_curr_wr_addr <= ldr_curr_wr_addr + 1;
+                    if ({1'b0, ldr_curr_wr_addr, 2'b00} == MAX_ADDR) begin
+                        zpu_rst     <= 1;
+                        bootram_ptr <= ~bootram_ptr;
+                    end
+                end
+            endcase
+        end else begin
+            zpu_rst <= 0;
+        end
+    end
+
+endmodule
diff --git a/fpga/usrp3/lib/zpu/zpu_top_pkg.vhd b/fpga/usrp3/lib/zpu/zpu_top_pkg.vhd
new file mode 100644
index 000000000..23ff48c39
--- /dev/null
+++ b/fpga/usrp3/lib/zpu/zpu_top_pkg.vhd
@@ -0,0 +1,46 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+library work;
+use work.zpupkg.all;
+use work.zpu_config.all;
+use work.wishbone_pkg.all;
+
+package zpu_top_pkg is
+    component zpu_wb_bridge is
+    port (	-- Native ZPU interface
+            clk 				: in std_logic;
+            areset 				: in std_logic;
+
+            mem_req 			: in std_logic;
+            mem_we				: in std_logic;
+            mem_ack				: out std_logic; 
+            mem_read 			: out std_logic_vector(wordSize-1 downto 0);
+            mem_write 			: in std_logic_vector(wordSize-1 downto 0);
+            out_mem_addr 		: in std_logic_vector(maxAddrBitIncIO downto 0);
+            mem_writeMask		: in std_logic_vector(wordBytes-1 downto 0);
+            
+            -- Wishbone from ZPU
+            zpu_wb_i			: in wishbone_bus_out;
+            zpu_wb_o			: out wishbone_bus_in);
+    end component;
+
+    component zpu_system is
+    generic(
+            simulate		: boolean := false);
+    port (	areset			: in std_logic;
+            cpu_clk			: in std_logic;
+
+            -- ZPU Control signals
+            enable			: in std_logic;
+            interrupt		: in std_logic;
+
+            zpu_status		: out std_logic_vector(63 downto 0);
+
+            -- wishbone interfaces
+            zpu_wb_i		: in wishbone_bus_out;
+            zpu_wb_o		: out wishbone_bus_in);
+    end component;
+
+end zpu_top_pkg;
diff --git a/fpga/usrp3/lib/zpu/zpu_wb_top.vhd b/fpga/usrp3/lib/zpu/zpu_wb_top.vhd
new file mode 100644
index 000000000..48e5ee31d
--- /dev/null
+++ b/fpga/usrp3/lib/zpu/zpu_wb_top.vhd
@@ -0,0 +1,74 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+library work;
+use work.zpu_top_pkg.all;
+use work.wishbone_pkg.all;
+use work.zpupkg.all;
+use work.zpu_config.all;
+
+------------------------------------------------------------------------
+-- Top level ZPU + wishbone componenent to use in a verilog design:
+--   zpu_wb_top wraps around the zpu_system component.
+--   All IO lines are exposed as std_logic for verilog.
+------------------------------------------------------------------------
+entity zpu_wb_top is
+    generic (
+        dat_w: integer := 32;
+        adr_w: integer := 16;
+        sel_w: integer := 4
+    );
+    port (
+        clk: in std_logic;
+        rst: in std_logic;
+        enb: in std_logic;
+
+        -- wishbone interface
+        dat_i: in std_logic_vector(dat_w-1 downto 0);
+        ack_i: in std_logic;
+        adr_o: out std_logic_vector(adr_w-1 downto 0);
+        sel_o: out std_logic_vector(sel_w-1 downto 0);
+        we_o: out std_logic;
+        dat_o: out std_logic_vector(dat_w-1 downto 0);
+        cyc_o: out std_logic;
+        stb_o: out std_logic;
+
+        -- misc zpu signals
+        interrupt: in std_logic;
+        zpu_status: out std_logic_vector(63 downto 0)
+    );
+
+end zpu_wb_top;
+
+architecture syn of zpu_wb_top is
+
+--wishbone interface (records)
+signal zpu_wb_i: wishbone_bus_out;
+signal zpu_wb_o: wishbone_bus_in;
+
+begin
+
+--assign wishbone signals to records
+zpu_wb_i.dat <= dat_i;
+zpu_wb_i.ack <= ack_i;
+
+adr_o <= zpu_wb_o.adr;
+sel_o <= zpu_wb_o.sel;
+we_o <= zpu_wb_o.we;
+dat_o <= zpu_wb_o.dat;
+cyc_o <= zpu_wb_o.cyc;
+stb_o <= zpu_wb_o.stb;
+
+--instantiate the zpu system
+zpu_system0: zpu_system port map(
+    cpu_clk => clk,
+    areset => rst,
+    enable => enb,
+    interrupt => interrupt,
+    zpu_status => zpu_status,
+    zpu_wb_i => zpu_wb_i,
+    zpu_wb_o => zpu_wb_o
+);
+
+end architecture syn;
diff --git a/fpga/usrp3/lib/zynq_fifo/.gitignore b/fpga/usrp3/lib/zynq_fifo/.gitignore
new file mode 100644
index 000000000..40aef90fe
--- /dev/null
+++ b/fpga/usrp3/lib/zynq_fifo/.gitignore
@@ -0,0 +1,2 @@
+/*.exe
+/*.vcd
diff --git a/fpga/usrp3/lib/zynq_fifo/Makefile.srcs b/fpga/usrp3/lib/zynq_fifo/Makefile.srcs
new file mode 100644
index 000000000..0a63d1627
--- /dev/null
+++ b/fpga/usrp3/lib/zynq_fifo/Makefile.srcs
@@ -0,0 +1,15 @@
+#
+# Copyright 2012 Ettus Research LLC
+#
+
+##################################################
+# ZYNQ FIFO interface sources
+##################################################
+ZYNQ_FIFO_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/zynq_fifo/, \
+zf_arbiter.v \
+zf_stream_to_host.v \
+zf_host_to_stream.v \
+zf_slave_readback.v \
+zf_slave_settings.v \
+zynq_fifo_top.v \
+))
diff --git a/fpga/usrp3/lib/zynq_fifo/zf_arbiter.v b/fpga/usrp3/lib/zynq_fifo/zf_arbiter.v
new file mode 100644
index 000000000..8a6bc7778
--- /dev/null
+++ b/fpga/usrp3/lib/zynq_fifo/zf_arbiter.v
@@ -0,0 +1,231 @@
+//////////////////////////////////////////////////////////////////////////////////
+// Copyright Ettus Research LLC
+// Copyright 2014 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// The ZYNQ FIFO configuration arbiter:
+//  - holds configuration memory addresses
+//  - setting and readback for slave state machines
+//  - stream of memory addresses for master state machines
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module zf_arbiter
+#(
+    parameter STREAMS_WIDTH = 2,
+    parameter CMDFIFO_DEPTH = 4,
+    parameter PAGE_WIDTH = 16,
+    parameter USE_INT_STREAM_SEL = 0    // Use internal round robin stream selection
+)
+(
+    input clk,
+    input rst,
+
+    //------------------------------------------------------------------
+    //-- settings interface
+    //------------------------------------------------------------------
+    input [31:0] set_addr,
+    input [31:0] set_data,
+    input set_stb,
+
+    //------------------------------------------------------------------
+    //-- readback interface
+    //------------------------------------------------------------------
+    input [31:0] rb_addr,
+    output [31:0] rb_data,
+    input rb_stb,
+
+    //------------------------------------------------------------------
+    //-- fifo interactive interface
+    //------------------------------------------------------------------
+    output [71:0] cmd_tdata,
+    output cmd_tvalid,
+    input cmd_tready,
+    input [7:0] sts_tdata,
+    input sts_tvalid,
+    output sts_tready,
+
+    //------------------------------------------------------------------
+    //-- which stream to process? externally provided if USE_INT_STREAM_SEL = 0
+    //------------------------------------------------------------------
+    input [STREAMS_WIDTH-1:0] ext_stream_sel,
+    input ext_stream_valid,
+
+    output [31:0] debug
+);
+
+////////////////////////////////////////////////////////////////////////
+///////////////////////////// Begin R T L //////////////////////////////
+////////////////////////////////////////////////////////////////////////
+
+    localparam NUM_STREAMS = (1 << STREAMS_WIDTH);
+
+    reg [STREAMS_WIDTH-1:0] which_stream;
+
+    //readback mux assignment
+    reg [31:0] rb_data_i [NUM_STREAMS-1:0];
+    assign rb_data = rb_data_i[rb_addr[STREAMS_WIDTH+4:5]];
+
+    //cmd + sts fifo mux signals
+    wire [72:0] cmd_data_i [NUM_STREAMS-1:0];
+    assign cmd_tdata = cmd_data_i[which_stream];
+    wire cmd_tvalid_i [NUM_STREAMS-1:0];
+    wire sts_tready_i [NUM_STREAMS-1:0];
+
+    ////////////////////////////////////////////////////////////////////
+    // state machine for driving fifo arbitration
+    ////////////////////////////////////////////////////////////////////
+    localparam STATE_SET_WHICH_STREAM = 0;
+    localparam STATE_ASSERT_DO_CMD = 1;
+    localparam STATE_ASSERT_DO_STS = 2;
+    localparam STATE_SOME_IDLE = 3;
+
+    reg [1:0] state;
+
+    wire [STREAMS_WIDTH-1:0] stream_sel;
+    wire stream_valid;
+
+    generate
+    if (USE_INT_STREAM_SEL) begin
+        reg [STREAMS_WIDTH-1:0] int_stream_sel;
+        always @(posedge clk) begin
+            if (rst) begin
+                int_stream_sel <= 0;
+            end else begin
+                if (state == STATE_SET_WHICH_STREAM) begin
+                    if (int_stream_sel < NUM_STREAMS-1) begin
+                        int_stream_sel <= int_stream_sel + 1;
+                    end else begin
+                        int_stream_sel <= 0;
+                    end
+                end
+            end
+        end
+        assign stream_sel = int_stream_sel;
+        assign stream_valid = 1'b1;
+    end else begin
+        assign stream_sel = ext_stream_sel;
+        assign stream_valid = ext_stream_valid;
+    end
+    endgenerate
+
+    always @(posedge clk) begin
+        if (rst) begin
+            state <= STATE_SET_WHICH_STREAM;
+            which_stream <= 0;
+        end
+        else case (state)
+
+        STATE_SET_WHICH_STREAM: begin
+            if (cmd_tvalid_i[stream_sel]) state <= STATE_ASSERT_DO_CMD;
+            which_stream <= stream_sel;
+        end
+
+        STATE_ASSERT_DO_CMD: begin
+            if (cmd_tvalid && cmd_tready) state <= STATE_ASSERT_DO_STS;
+        end
+
+        STATE_ASSERT_DO_STS: begin
+            if (sts_tvalid && sts_tready) state <= STATE_SOME_IDLE;
+        end
+
+        STATE_SOME_IDLE: begin
+            state <= STATE_SET_WHICH_STREAM;
+        end
+
+        default: state <= STATE_SET_WHICH_STREAM;
+
+        endcase //state
+    end
+
+    ////////////////////////////////////////////////////////////////////
+    // memory map + fifos for the host control/status
+    ////////////////////////////////////////////////////////////////////
+
+    wire do_cmd = (state == STATE_ASSERT_DO_CMD);
+    wire do_sts = (state == STATE_ASSERT_DO_STS);
+
+    assign cmd_tvalid = do_cmd && cmd_tvalid_i[which_stream];
+    assign sts_tready = do_sts && sts_tready_i[which_stream];
+
+    genvar i;
+    generate
+    for (i=0; i < NUM_STREAMS; i=i+1) begin : stream_circuit
+
+        wire [PAGE_WIDTH-3:0] set_addr32 = set_addr[PAGE_WIDTH-1:2];
+        wire write_clear = set_stb && (set_addr32 == (0 + i*8));
+        wire write_addr  = set_stb && (set_addr32 == (1 + i*8));
+        wire write_size  = set_stb && (set_addr32 == (2 + i*8));
+        wire write_sts_rdy  = set_stb && (set_addr32 == (3 + i*8));
+        wire write_sts      = set_stb && (set_addr32 == (4 + i*8));
+
+        wire [PAGE_WIDTH-3:0] rb_addr32 = rb_addr[PAGE_WIDTH-1:2];
+        wire read_sig            = (rb_addr32 == (0 + i*8));
+        wire read_status         = (rb_addr32 == (4 + i*8));
+        wire read_sts_occupied   = (rb_addr32 == (5 + i*8));
+        wire read_cmd_addr_space = (rb_addr32 == (6 + i*8));
+        wire read_cmd_size_space = (rb_addr32 == (7 + i*8));
+
+        wire [15:0] sts_occupied, cmd_addr_space, cmd_size_space;
+        wire [7:0] sts_readback;
+
+        wire [15:0] this_stream = i;
+        always @* begin
+            if (read_sig) rb_data_i[i] <= {16'hACE0, this_stream};
+            else if (read_status) rb_data_i[i] <= {24'b0, sts_readback};
+            else if (read_sts_occupied) rb_data_i[i] <= {16'b0, sts_occupied};
+            else if (read_cmd_addr_space) rb_data_i[i] <= {16'b0, cmd_addr_space};
+            else if (read_cmd_size_space) rb_data_i[i] <= {16'b0, cmd_size_space};
+            else rb_data_i[i] <= 32'h12345678;
+        end
+
+        wire [31:0] cmd_addr, cmd_size;
+        wire cmd_addr_tvalid, cmd_size_tvalid;
+        assign cmd_data_i[i][32+39:32+36] = 4'b0; //reserved - 0?
+        assign cmd_data_i[i][32+35:64] = i[3:0]; //tag
+        assign cmd_data_i[i][63:32] = cmd_addr;
+        assign cmd_data_i[i][31] = 1'b0; //DRE ReAlignment Request
+        assign cmd_data_i[i][30] = 1'b1; //always EOF for tlast stream
+        assign cmd_data_i[i][29:24] = 6'b0; //DRE Stream Alignment
+        assign cmd_data_i[i][23] = 1'b1; // Transfer type, 0 = No addr incr / FIFO mode, 1 = incr addr
+        assign cmd_data_i[i][22:0] = cmd_size[22:0];
+
+        axi_fifo #(.WIDTH(32), .SIZE(CMDFIFO_DEPTH)) crl_addr_fifo
+        (
+            .clk(clk), .reset(rst), .clear(write_clear),
+            .i_tdata(set_data), .i_tvalid(write_addr), .i_tready(), .space(cmd_addr_space),
+            .o_tdata(cmd_addr), .o_tvalid(cmd_addr_tvalid), .o_tready(cmd_tready && do_cmd && (which_stream == i)), .occupied()
+        );
+
+        axi_fifo #(.WIDTH(32), .SIZE(CMDFIFO_DEPTH)) crl_size_fifo
+        (
+            .clk(clk), .reset(rst), .clear(write_clear),
+            .i_tdata(set_data), .i_tvalid(write_size), .i_tready(), .space(cmd_size_space),
+            .o_tdata(cmd_size), .o_tvalid(cmd_size_tvalid), .o_tready(cmd_tready && do_cmd && (which_stream == i)), .occupied()
+        );
+
+        assign cmd_tvalid_i[i] = cmd_addr_tvalid && cmd_size_tvalid && stream_valid;
+
+        wire dm_sts_tvalid = sts_tvalid && do_sts && (which_stream == i);
+
+        axi_fifo #(.WIDTH(8), .SIZE(CMDFIFO_DEPTH)) sts_fifo
+        (
+            .clk(clk), .reset(rst), .clear(),
+            .i_tdata((write_sts)?set_data[7:0]:sts_tdata), .i_tvalid(dm_sts_tvalid || write_sts), .i_tready(sts_tready_i[i]), .space(),
+            .o_tdata(sts_readback), .o_tvalid(), .o_tready(write_sts_rdy), .occupied(sts_occupied)
+        );
+
+    end
+    endgenerate
+
+    assign debug[1:0] = state;
+    assign debug[4] = cmd_tvalid;
+    assign debug[5] = cmd_tready;
+    assign debug[6] = sts_tvalid;
+    assign debug[7] = sts_tready;
+    assign debug[8] = stream_sel;
+    assign debug[9] = which_stream;
+    assign debug[15] = rb_addr[STREAMS_WIDTH+4:5];
+
+endmodule //zf_arbiter
diff --git a/fpga/usrp3/lib/zynq_fifo/zf_host_to_stream.v b/fpga/usrp3/lib/zynq_fifo/zf_host_to_stream.v
new file mode 100644
index 000000000..8fd1d1985
--- /dev/null
+++ b/fpga/usrp3/lib/zynq_fifo/zf_host_to_stream.v
@@ -0,0 +1,143 @@
+//////////////////////////////////////////////////////////////////////////////////
+// Copyright Ettus Research LLC
+// Copyright 2014 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// The ZYNQ FIFO - read DDR and write to FIFO:
+//  - implements read state machine for AXI master on DDR
+//  - provides output fifos to external fabric
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module zf_host_to_stream
+#(
+    parameter PROT = 3'b010 //data, non-secure, unpriv
+)
+(
+    input clk,
+    input rst,
+    input enb,
+
+    //------------------------------------------------------------------
+    //-- DDR read signals - master
+    //------------------------------------------------------------------
+    output [31:0] AXI_ARADDR,
+    output [2:0] AXI_ARPROT,
+    output AXI_ARVALID,
+    input AXI_ARREADY,
+    input [63:0] AXI_RDATA,
+    input [1:0] AXI_RRESP,
+    input AXI_RVALID,
+    output AXI_RREADY,
+
+    //------------------------------------------------------------------
+    // FIFO streaming interfaces
+    //------------------------------------------------------------------
+    output [63:0] o_tdata,
+    output o_tlast,
+    output o_tvalid,
+    input o_tready,
+
+    //------------------------------------------------------------------
+    // configuration interface
+    //------------------------------------------------------------------
+    input [31:0] mem_addr,
+    input mem_valid,
+    output mem_ack,
+
+    output [31:0] debug
+);
+
+////////////////////////////////////////////////////////////////////////
+///////////////////////////// Begin R T L //////////////////////////////
+////////////////////////////////////////////////////////////////////////
+
+
+    localparam STATE_WAIT_MEM = 0;
+    localparam STATE_WRITE_ADDR = 1;
+    localparam STATE_READ_DATA = 2;
+    localparam STATE_WRITE_LINE = 3;
+    localparam STATE_DONE = 4;
+
+    reg [31:0] base_addr;
+    reg [63:0] line;
+    reg [15:0] line32_count;
+    reg first_line;
+
+    reg [2:0] state;
+    always @(posedge clk) begin
+        if (rst) begin
+            state <= STATE_WAIT_MEM;
+            base_addr <= 0;
+            line <= 0;
+            line32_count <= 0;
+            first_line <= 1;
+        end
+        else if (enb) case (state)
+        STATE_WAIT_MEM: begin
+            if (mem_valid) begin
+                state <= STATE_WRITE_ADDR;
+            end
+            base_addr <= mem_addr;
+            first_line <= 1;
+        end
+
+        STATE_WRITE_ADDR: begin
+            if (AXI_ARVALID && AXI_ARREADY) begin
+                state <= STATE_READ_DATA;
+            end
+        end
+
+        STATE_READ_DATA: begin
+            if (AXI_RVALID && AXI_RREADY) begin
+                line <= AXI_RDATA;
+                state <= STATE_WRITE_LINE;
+                if (first_line) begin
+                    //round up to multiple of 64 minus one line
+                    //Note! words32 are swapped here, inspect lower for length
+                    line32_count <= AXI_RDATA[15:0] - 16'b1;
+                    first_line <= 0;
+                end
+            end
+        end
+
+        STATE_WRITE_LINE: begin
+            if (o_tvalid && o_tready) begin
+                if (o_tlast) state <= STATE_DONE;
+                else state <= STATE_WRITE_ADDR;
+                base_addr <= base_addr + 32'h8;
+                line32_count <= line32_count - 16'h2;
+            end
+        end
+
+        STATE_DONE: begin
+            state <= STATE_WAIT_MEM;
+        end
+
+        default: state <= STATE_WAIT_MEM;
+
+        endcase //state
+    end
+
+    assign o_tdata = {line[31:0], line[63:32]};
+    assign o_tlast = (line32_count[15:1] == 15'b0); //ignore low bit
+    assign o_tvalid = (state == STATE_WRITE_LINE);
+    assign mem_ack = (state == STATE_DONE);
+
+    //the master read address always comes from the reg
+    assign AXI_ARADDR = base_addr;
+    assign AXI_ARVALID = (state == STATE_WRITE_ADDR);
+    assign AXI_RREADY = (state == STATE_READ_DATA);
+    assign AXI_ARPROT = PROT;
+
+    assign debug[2:0] = state;
+    assign debug[3] = first_line;
+    assign debug[4] = mem_valid;
+    assign debug[5] = mem_ack;
+    assign debug[6] = AXI_ARVALID;
+    assign debug[7] = AXI_ARREADY;
+    assign debug[8] = AXI_RVALID;
+    assign debug[9] = AXI_RREADY;
+
+endmodule //zf_host_to_stream
diff --git a/fpga/usrp3/lib/zynq_fifo/zf_slave_readback.v b/fpga/usrp3/lib/zynq_fifo/zf_slave_readback.v
new file mode 100644
index 000000000..807931513
--- /dev/null
+++ b/fpga/usrp3/lib/zynq_fifo/zf_slave_readback.v
@@ -0,0 +1,95 @@
+//////////////////////////////////////////////////////////////////////////////////
+// Copyright Ettus Research LLC
+// Copyright 2014 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// The ZYNQ FIFO slave readback:
+//  - implements read state machine for 32-bit addressable AXI slave
+//  - provides readback for state of per-stream fifo pointers
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module zf_slave_readback
+#(
+    parameter CONFIG_BASE = 32'h40000000
+)
+(
+    input clk,
+    input rst,
+
+    //------------------------------------------------------------------
+    //-- control read signals - slave
+    //------------------------------------------------------------------
+    input [31:0] AXI_ARADDR,
+    input AXI_ARVALID,
+    output AXI_ARREADY,
+    output [31:0] AXI_RDATA,
+    output [1:0] AXI_RRESP,
+    output AXI_RVALID,
+    input AXI_RREADY,
+
+    //------------------------------------------------------------------
+    // readback interface
+    //------------------------------------------------------------------
+    output reg [31:0] addr,
+    input [31:0] data,
+    output strobe,
+
+    output [31:0] debug
+);
+
+////////////////////////////////////////////////////////////////////////
+///////////////////////////// Begin R T L //////////////////////////////
+////////////////////////////////////////////////////////////////////////
+
+    //------------------------------------------------------------------
+    // Control read state machine responds to AXI control reads
+    // Used for reading back the state of the various FIFOs
+    //------------------------------------------------------------------
+    localparam STATE_ADDR = 0;
+    localparam STATE_READ = 1;
+    localparam STATE_DATA = 2;
+
+    reg [3:0] state;
+
+    always @(posedge clk) begin
+        if (rst) begin
+            state <= STATE_ADDR;
+            addr <= 0;
+        end
+        else case (state)
+
+        STATE_ADDR: begin
+            if (AXI_ARVALID && AXI_ARREADY) begin
+                state <= STATE_READ;
+                addr <= (AXI_ARADDR - CONFIG_BASE);
+            end
+        end
+
+        STATE_READ: begin
+            state <= STATE_DATA;
+        end
+
+        STATE_DATA: begin
+            if (AXI_RVALID && AXI_RREADY) begin
+                state <= STATE_ADDR;
+            end
+        end
+
+        default: state <= STATE_ADDR;
+
+        endcase //state
+    end
+
+    assign strobe = AXI_RVALID && AXI_RREADY;
+
+    //readback data
+    assign AXI_RDATA = data;
+    //only acking address reads from the wait state
+    assign AXI_ARREADY = (state == STATE_ADDR);
+    //when to release outputs from the slave
+    assign AXI_RVALID = (state == STATE_DATA);
+    assign AXI_RRESP = 0;
+
+endmodule //zf_slave_readback
diff --git a/fpga/usrp3/lib/zynq_fifo/zf_slave_settings.v b/fpga/usrp3/lib/zynq_fifo/zf_slave_settings.v
new file mode 100644
index 000000000..91edf6bfe
--- /dev/null
+++ b/fpga/usrp3/lib/zynq_fifo/zf_slave_settings.v
@@ -0,0 +1,99 @@
+//////////////////////////////////////////////////////////////////////////////////
+// Copyright Ettus Research LLC
+// Copyright 2014 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// The ZYNQ FIFO slave settings:
+//  - implements write state machine for 32-bit addressable AXI slave
+//  - provides settings for state of per-stream fifo pointers
+//  - implements configuration of FIFO's physical DDR addresses
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module zf_slave_settings
+#(
+    parameter CONFIG_BASE = 32'h40000000
+)
+(
+    input clk,
+    input rst,
+
+    //------------------------------------------------------------------
+    //-- control write signals - slave
+    //------------------------------------------------------------------
+    input [31:0] AXI_AWADDR,
+    input AXI_AWVALID,
+    output AXI_AWREADY,
+    input [31:0] AXI_WDATA,
+    input [3:0] AXI_WSTRB,
+    input AXI_WVALID,
+    output AXI_WREADY,
+    output [1:0] AXI_BRESP,
+    output AXI_BVALID,
+    input AXI_BREADY,
+
+    //------------------------------------------------------------------
+    // settings interface
+    //------------------------------------------------------------------
+    output reg [31:0] addr,
+    output reg [31:0] data,
+    output strobe,
+
+    output [31:0] debug
+);
+
+////////////////////////////////////////////////////////////////////////
+///////////////////////////// Begin R T L //////////////////////////////
+////////////////////////////////////////////////////////////////////////
+
+    //------------------------------------------------------------------
+    // Control write state machine responds to AXI control writes
+    // Used for setting the state of the various FIFOs
+    //------------------------------------------------------------------
+    localparam STATE_ADDR = 0;
+    localparam STATE_DATA = 1;
+    localparam STATE_WRITE = 2;
+
+    reg [1:0] state;
+
+    always @(posedge clk) begin
+        if (rst) begin
+            state <= STATE_ADDR;
+            addr <= 0;
+            data <= 0;
+        end
+        else case (state)
+
+        STATE_ADDR: begin
+            if (AXI_AWVALID && AXI_AWREADY) begin
+                addr <= (AXI_AWADDR - CONFIG_BASE);
+                state <= STATE_DATA;
+            end
+        end
+
+        STATE_DATA: begin
+            if (AXI_WVALID && AXI_WREADY) begin
+                data <= AXI_WDATA;
+                state <= STATE_WRITE;
+            end
+        end
+
+        STATE_WRITE: begin
+            state <= STATE_ADDR;
+        end
+
+        default: state <= STATE_ADDR;
+
+        endcase //state
+    end
+
+    assign strobe = (state == STATE_WRITE);
+
+    //assign to slave write
+    assign AXI_AWREADY = (state == STATE_ADDR);
+    assign AXI_WREADY = (state == STATE_DATA);
+    assign AXI_BRESP = 0;
+    assign AXI_BVALID = AXI_BREADY; //FIXME - we can choose not to assert valid
+
+endmodule //zf_slave_settings
diff --git a/fpga/usrp3/lib/zynq_fifo/zf_stream_to_host.v b/fpga/usrp3/lib/zynq_fifo/zf_stream_to_host.v
new file mode 100644
index 000000000..b85b56ab8
--- /dev/null
+++ b/fpga/usrp3/lib/zynq_fifo/zf_stream_to_host.v
@@ -0,0 +1,154 @@
+//////////////////////////////////////////////////////////////////////////////////
+//
+// Copyright Ettus Research LLC
+// Copyright 2014 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// The ZYNQ FIFO - read FIFO and write to DDR:
+//  - implements write state machine for AXI master on DDR
+//  - provides input fifos from external fabric
+//////////////////////////////////////////////////////////////////////////////////
+
+
+//This implementation takes many states to do individual
+//64 bit xfers from FIFO to the AXI write master.
+//TODO: use axi 4/full with busts,
+//in this case we should be able to directly connect the fifo
+//to the write lines with much less state machinery.
+
+module zf_stream_to_host
+#(
+    parameter PROT = 3'b010, //data, non-secure, unpriv
+    parameter STRB = 4'b1111 //write all bytes
+)
+(
+    input clk,
+    input rst,
+    input enb,
+
+    //------------------------------------------------------------------
+    //-- DDR write signals - master
+    //------------------------------------------------------------------
+    output [31:0] AXI_AWADDR,
+    output [2:0] AXI_AWPROT,
+    output AXI_AWVALID,
+    input AXI_AWREADY,
+    output [63:0] AXI_WDATA,
+    output [3:0] AXI_WSTRB,
+    output AXI_WVALID,
+    input AXI_WREADY,
+    input [1:0] AXI_BRESP,
+    input AXI_BVALID,
+    output AXI_BREADY,
+
+    //------------------------------------------------------------------
+    // FIFO streaming interfaces
+    //------------------------------------------------------------------
+    input [63:0] i_tdata,
+    input i_tlast,
+    input i_tvalid,
+    output i_tready,
+
+    //------------------------------------------------------------------
+    // configuration interface
+    //------------------------------------------------------------------
+    input [31:0] mem_addr,
+    input mem_valid,
+    output mem_ack,
+
+    output [31:0] debug
+);
+
+////////////////////////////////////////////////////////////////////////
+///////////////////////////// Begin R T L //////////////////////////////
+////////////////////////////////////////////////////////////////////////
+
+    localparam STATE_WAIT_MEM = 0;
+    localparam STATE_READ_LINE = 1;
+    localparam STATE_WRITE_ADDR = 2;
+    localparam STATE_WRITE_DATA = 3;
+    localparam STATE_WRITE_B = 4;
+    localparam STATE_DONE = 5;
+
+    reg [31:0] base_addr;
+    reg [63:0] line;
+    reg last;
+
+    reg [2:0] state;
+    always @(posedge clk) begin
+        if (rst) begin
+            state <= STATE_WAIT_MEM;
+            base_addr <= 0;
+            line <= 0;
+            last <= 0;
+        end
+        else if (enb) case (state)
+        STATE_WAIT_MEM: begin
+            if (mem_valid) begin
+                state <= STATE_READ_LINE;
+            end
+            base_addr <= mem_addr;
+        end
+
+        STATE_READ_LINE: begin
+            if (i_tvalid && i_tready) begin
+                line <= i_tdata;
+                last <= i_tlast;
+                state <= STATE_WRITE_ADDR;
+            end
+        end
+
+        STATE_WRITE_ADDR: begin
+            if (AXI_AWVALID && AXI_AWREADY) begin
+                state <= STATE_WRITE_DATA;
+            end
+        end
+
+        STATE_WRITE_DATA: begin
+            if (AXI_WVALID && AXI_WREADY) begin
+                state <= STATE_WRITE_B;
+            end
+        end
+
+        STATE_WRITE_B: begin
+            if (AXI_BREADY && AXI_BVALID) begin//FIXME, slave may not assert valid
+                if (last) state <= STATE_DONE;
+                else state <= STATE_READ_LINE;
+                base_addr <= base_addr + 32'h8;
+            end
+        end
+
+        STATE_DONE: begin
+            state <= STATE_WAIT_MEM;
+        end
+
+        default: state <= STATE_WAIT_MEM;
+
+        endcase //state
+    end
+
+    assign i_tready = (state == STATE_READ_LINE);
+    assign mem_ack = (state == STATE_DONE);
+
+    //assign to master write
+    assign AXI_AWVALID = (state == STATE_WRITE_ADDR);
+    assign AXI_WVALID = (state == STATE_WRITE_DATA);
+    assign AXI_AWADDR = base_addr;
+    assign AXI_WDATA = {line[31:0], line[63:32]};
+
+    assign AXI_WSTRB  = STRB;
+    assign AXI_AWPROT = PROT;
+    assign AXI_BREADY = (state == STATE_WRITE_B);
+
+    assign debug[2:0] = state;
+    assign debug[4] = mem_valid;
+    assign debug[5] = mem_ack;
+    assign debug[6] = AXI_AWVALID;
+    assign debug[7] = AXI_AWREADY;
+    assign debug[8] = AXI_WVALID;
+    assign debug[9] = AXI_WREADY;
+    assign debug[10] = AXI_BVALID;
+    assign debug[11] = AXI_BREADY;
+
+endmodule //zf_stream_to_host
diff --git a/fpga/usrp3/lib/zynq_fifo/zynq_fifo_top.v b/fpga/usrp3/lib/zynq_fifo/zynq_fifo_top.v
new file mode 100644
index 000000000..793e93c71
--- /dev/null
+++ b/fpga/usrp3/lib/zynq_fifo/zynq_fifo_top.v
@@ -0,0 +1,440 @@
+`timescale 1ns / 1ps
+
+//////////////////////////////////////////////////////////////////////////////////
+// Copyright Ettus Research LLC
+// Copyright 2013 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// The ZYNQ FIFO Top:
+//  - takes read and write 32-bit addressable AXI slave
+//  - takes read and write 64-bit addressable AXI master
+//  - drives N input and output AXI stream FIFOs
+//////////////////////////////////////////////////////////////////////////////////
+
+// Mapping:
+// Page0 - stream to host config
+// Page1 - host to stream config
+
+module zynq_fifo_top
+#(
+    parameter CONFIG_BASE = 32'h40000000,
+    parameter PAGE_WIDTH = 10, //in bytes, must fit widths below
+    parameter H2S_STREAMS_WIDTH = 2,
+    parameter H2S_CMDFIFO_DEPTH = 4,
+    parameter S2H_STREAMS_WIDTH = 2,
+    parameter S2H_CMDFIFO_DEPTH = 4,
+    parameter PROT = 3'b010 //data, non-secure, unpriv
+)
+(
+    input clk,
+    input rst,
+
+    //------------------------------------------------------------------
+    // AXI slave addressable signals - control
+    //------------------------------------------------------------------
+    //control write signals - slave
+    input [31:0] CTL_AXI_AWADDR,
+    input CTL_AXI_AWVALID,
+    output CTL_AXI_AWREADY,
+    input [31:0] CTL_AXI_WDATA,
+    input [3:0] CTL_AXI_WSTRB,
+    input CTL_AXI_WVALID,
+    output CTL_AXI_WREADY,
+    output [1:0] CTL_AXI_BRESP,
+    output CTL_AXI_BVALID,
+    input CTL_AXI_BREADY,
+
+    //control read signals - slave
+    input [31:0] CTL_AXI_ARADDR,
+    input CTL_AXI_ARVALID,
+    output CTL_AXI_ARREADY,
+    output [31:0] CTL_AXI_RDATA,
+    output [1:0] CTL_AXI_RRESP,
+    output CTL_AXI_RVALID,
+    input CTL_AXI_RREADY,
+
+    //------------------------------------------------------------------
+    // AXI master addressable signals - DDR access
+    //------------------------------------------------------------------
+    //memory write signals - master
+    output [5:0] DDR_AXI_AWID,
+    output [31:0] DDR_AXI_AWADDR,
+    output [2:0] DDR_AXI_AWPROT,
+    output DDR_AXI_AWVALID,
+    input DDR_AXI_AWREADY,
+    output [63:0] DDR_AXI_WDATA,
+    output [7:0] DDR_AXI_WSTRB,
+    output DDR_AXI_WVALID,
+    input DDR_AXI_WREADY,
+    input [1:0] DDR_AXI_BRESP,
+    input DDR_AXI_BVALID,
+    output DDR_AXI_BREADY,
+    output [7:0] DDR_AXI_AWLEN,
+    output [2:0] DDR_AXI_AWSIZE,
+    output [1:0] DDR_AXI_AWBURST,
+    output [3:0] DDR_AXI_AWCACHE,
+    output DDR_AXI_WLAST,
+
+    //memory read signals - master
+    output [5:0] DDR_AXI_ARID,
+    output [31:0] DDR_AXI_ARADDR,
+    output [2:0] DDR_AXI_ARPROT,
+    output DDR_AXI_ARVALID,
+    input DDR_AXI_ARREADY,
+    input [63:0] DDR_AXI_RDATA,
+    input [1:0] DDR_AXI_RRESP,
+    input DDR_AXI_RVALID,
+    output DDR_AXI_RREADY,
+    input DDR_AXI_RLAST,
+    output [3:0] DDR_AXI_ARCACHE,
+    output [7:0] DDR_AXI_ARLEN,
+    output [1:0] DDR_AXI_ARBURST,
+    output [2:0] DDR_AXI_ARSIZE,
+
+    //------------------------------------------------------------------
+    // AXI streams host to stream
+    //------------------------------------------------------------------
+    output [63:0] h2s_tdata,
+    output h2s_tlast,
+    output h2s_tvalid,
+    input h2s_tready,
+
+    //------------------------------------------------------------------
+    // AXI streams stream to host
+    //------------------------------------------------------------------
+    input [63:0] s2h_tdata,
+    input s2h_tlast,
+    input s2h_tvalid,
+    output s2h_tready,
+
+    output event_irq,
+
+    //------------------------------------------------------------------
+    // Settings bus interface that will got to e300 core
+    //------------------------------------------------------------------
+    output [31:0] core_set_data,
+    output [7:0]  core_set_addr,
+    output        core_set_stb,
+    input [31:0]  core_rb_data,
+
+    //------------------------------------------------------------------
+    // Settings bus interface for crossbar (in e300 core)
+    //------------------------------------------------------------------
+    output [31:0] xbar_set_data,
+    output [31:0] xbar_set_addr,
+    output        xbar_set_stb,
+    input [31:0]  xbar_rb_data,
+    output [31:0] xbar_rb_addr,
+    output        xbar_rb_stb,
+
+    output [31:0] debug
+);
+
+////////////////////////////////////////////////////////////////////////
+///////////////////////////// Begin R T L //////////////////////////////
+////////////////////////////////////////////////////////////////////////
+
+    //interrupt wires
+    wire h2s_irq, s2h_irq;
+    assign event_irq = h2s_irq | s2h_irq;
+
+    wire [31:0] set_addr, set_data;
+    wire [31:0] rb_addr, rb_data;
+    wire [31:0] rb_data_s2h, rb_data_h2s;
+    wire set_stb, set_stb_s2h, set_stb_h2s, set_stb_dest_lookup;
+    wire rb_stb, rb_stb_s2h, rb_stb_h2s;
+
+    wire [2:0] set_page = set_addr[PAGE_WIDTH+2:PAGE_WIDTH];
+    wire [2:0] rb_page = rb_addr[PAGE_WIDTH+2:PAGE_WIDTH];
+
+    // each arbiter gets 1 page, e300_core the next,
+    // destination lookup, and xbar gets two pages
+    assign set_stb_s2h         = set_stb && (set_page == 3'h0);
+    assign set_stb_h2s         = set_stb && (set_page == 3'h1);
+    assign core_set_stb        = set_stb && (set_page == 3'h2);
+    assign set_stb_dest_lookup = set_stb && (set_page == 3'h3);
+    assign xbar_set_stb        = set_stb && (set_page == 3'h4 || set_page == 3'h5);
+
+    assign rb_stb_s2h = rb_stb && (rb_page == 3'h0);
+    assign rb_stb_h2s = rb_stb && (rb_page == 3'h1);
+    assign xbar_rb_stb = rb_stb && (rb_page == 3'h4);
+    assign rb_data = (rb_page == 3'h0)? rb_data_s2h :
+                     (rb_page == 3'h1)? rb_data_h2s :
+                     (rb_page == 3'h2)? core_rb_data:
+                     // no readback for dest_lookup
+                     (rb_page == 3'h4)? xbar_rb_data:
+                     32'hdeadbeef;
+
+    assign core_set_addr = set_addr[7:0];
+    assign core_set_data = set_data;
+
+    assign xbar_rb_addr = rb_addr[10:0];
+    assign xbar_set_data = set_data;
+    assign xbar_set_addr = set_addr[10:0];
+
+    //------------------------------------------------------------------
+    // configuration slaves
+    //------------------------------------------------------------------
+    zf_slave_settings #(.CONFIG_BASE(CONFIG_BASE)) zf_slave_settings
+    (
+        .clk(clk), .rst(rst),
+        .AXI_AWADDR(CTL_AXI_AWADDR),
+        .AXI_AWVALID(CTL_AXI_AWVALID),
+        .AXI_AWREADY(CTL_AXI_AWREADY),
+        .AXI_WDATA(CTL_AXI_WDATA),
+        .AXI_WSTRB(CTL_AXI_WSTRB),
+        .AXI_WVALID(CTL_AXI_WVALID),
+        .AXI_WREADY(CTL_AXI_WREADY),
+        .AXI_BRESP(CTL_AXI_BRESP),
+        .AXI_BVALID(CTL_AXI_BVALID),
+        .AXI_BREADY(CTL_AXI_BREADY),
+        .addr(set_addr), .data(set_data), .strobe(set_stb),
+        .debug()
+    );
+    zf_slave_readback #(.CONFIG_BASE(CONFIG_BASE)) zf_slave_readback
+    (
+        .clk(clk), .rst(rst),
+        .AXI_ARADDR(CTL_AXI_ARADDR),
+        .AXI_ARVALID(CTL_AXI_ARVALID),
+        .AXI_ARREADY(CTL_AXI_ARREADY),
+        .AXI_RDATA(CTL_AXI_RDATA),
+        .AXI_RRESP(CTL_AXI_RRESP),
+        .AXI_RVALID(CTL_AXI_RVALID),
+        .AXI_RREADY(CTL_AXI_RREADY),
+        .addr(rb_addr), .data(rb_data), .strobe(rb_stb),
+        .debug()
+    );
+
+    //------------------------------------------------------------------
+    // fifo to ddr
+    //------------------------------------------------------------------
+    wire [71:0] s2h_cmd_tdata;
+    wire [7:0] s2h_sts_tdata;
+    wire s2h_cmd_tvalid, s2h_cmd_tready;
+    wire s2h_sts_tvalid, s2h_sts_tready;
+
+    assign s2h_irq = s2h_sts_tvalid;
+
+    //lookup destination
+    wire [63:0] s2h_tdata_i0;
+    wire s2h_tready_i0, s2h_tvalid_i0, s2h_tlast_i0;
+    wire [S2H_STREAMS_WIDTH-1:0] which_stream_s2h;
+
+    cvita_dest_lookup #(.DEST_WIDTH(S2H_STREAMS_WIDTH)) s2h_dest_gen
+    (
+        .clk(clk), .rst(rst),
+        .set_stb(set_stb_dest_lookup), .set_addr(set_addr[9:2]), .set_data(set_data),
+        .i_tdata(s2h_tdata), .i_tlast(s2h_tlast), .i_tvalid(s2h_tvalid), .i_tready(s2h_tready),
+        .o_tdata(s2h_tdata_i0), .o_tlast(s2h_tlast_i0), .o_tvalid(s2h_tvalid_i0), .o_tready(s2h_tready_i0),
+        .o_tdest(which_stream_s2h)
+    );
+
+    //only active in cycles between command and tlast
+    //this prevents bullshit consumption after tlast
+    reg s2h_active;
+    always @(posedge clk) begin
+        if (rst) s2h_active <= 0;
+        else if (s2h_cmd_tvalid && s2h_cmd_tready) s2h_active <= 1;
+        else if (s2h_tready_i0 && s2h_tvalid_i0 && s2h_tlast_i0) s2h_active <= 0;
+    end
+
+    //cut fifo comms when not in active state
+    wire [63:0] s2h_tdata_i1;
+    wire s2h_tready_i1, s2h_tvalid_i1, s2h_tlast_i1;
+    assign s2h_tdata_i1 = s2h_tdata_i0;
+    assign s2h_tlast_i1 = s2h_tlast_i0;
+    assign s2h_tvalid_i1 = s2h_tvalid_i0 && s2h_active;
+    assign s2h_tready_i0 = s2h_tready_i1 && s2h_active;
+
+    wire [31:0] s2h_arbiter_debug;
+    zf_arbiter #(
+        .STREAMS_WIDTH(H2S_STREAMS_WIDTH),
+        .CMDFIFO_DEPTH(H2S_CMDFIFO_DEPTH),
+        .PAGE_WIDTH(PAGE_WIDTH)
+    ) s2h_arbiter
+    (
+        .clk(clk), .rst(rst),
+        .set_addr(set_addr), .set_data(set_data), .set_stb(set_stb_s2h),
+        .rb_addr(rb_addr), .rb_data(rb_data_s2h), .rb_stb(rb_stb_s2h),
+        .cmd_tdata(s2h_cmd_tdata), .cmd_tvalid(s2h_cmd_tvalid), .cmd_tready(s2h_cmd_tready),
+        .sts_tdata(s2h_sts_tdata), .sts_tvalid(s2h_sts_tvalid), .sts_tready(s2h_sts_tready),
+        .ext_stream_sel(which_stream_s2h), .ext_stream_valid(s2h_tvalid_i0),
+        .debug(s2h_arbiter_debug)
+    );
+
+    //------------------------------------------------------------------
+    // ddr to fifo
+    //------------------------------------------------------------------
+    wire [71:0] h2s_cmd_tdata;
+    wire [7:0] h2s_sts_tdata;
+    wire h2s_cmd_tvalid, h2s_cmd_tready;
+    wire h2s_sts_tvalid, h2s_sts_tready;
+
+    assign h2s_irq = h2s_sts_tvalid;
+
+    wire [31:0] h2s_arbiter_debug;
+    zf_arbiter #(
+        .STREAMS_WIDTH(S2H_STREAMS_WIDTH),
+        .CMDFIFO_DEPTH(S2H_CMDFIFO_DEPTH),
+        .PAGE_WIDTH(PAGE_WIDTH),
+        .USE_INT_STREAM_SEL(1)
+    ) h2s_arbiter
+    (
+        .clk(clk), .rst(rst),
+        .set_addr(set_addr), .set_data(set_data), .set_stb(set_stb_h2s),
+        .rb_addr(rb_addr), .rb_data(rb_data_h2s), .rb_stb(rb_stb_h2s),
+        .cmd_tdata(h2s_cmd_tdata), .cmd_tvalid(h2s_cmd_tvalid), .cmd_tready(h2s_cmd_tready),
+        .sts_tdata(h2s_sts_tdata), .sts_tvalid(h2s_sts_tvalid), .sts_tready(h2s_sts_tready),
+        .ext_stream_sel(), .ext_stream_valid(),
+        .debug(h2s_arbiter_debug)
+    );
+
+    //------------------------------------------------------------------
+    // axi_datamover
+    //------------------------------------------------------------------
+    wire reset_dm = rst;
+    axi_dma_stream inst_axi_dma_stream
+    (
+        //host to stream reset stuff
+        .m_axi_mm2s_aclk(clk),
+        .m_axi_mm2s_aresetn(!reset_dm),
+        .mm2s_halt(1'b0),
+        .mm2s_halt_cmplt(),
+        .mm2s_err(),
+
+        //host to stream command
+        .m_axis_mm2s_cmdsts_aclk(clk),
+        .m_axis_mm2s_cmdsts_aresetn(!reset_dm),
+        .s_axis_mm2s_cmd_tvalid(h2s_cmd_tvalid),
+        .s_axis_mm2s_cmd_tready(h2s_cmd_tready),
+        .s_axis_mm2s_cmd_tdata(h2s_cmd_tdata),
+
+        //host to stream status
+        .m_axis_mm2s_sts_tvalid(h2s_sts_tvalid),
+        .m_axis_mm2s_sts_tready(h2s_sts_tready),
+        .m_axis_mm2s_sts_tdata(h2s_sts_tdata),
+        .m_axis_mm2s_sts_tkeep(),
+        .m_axis_mm2s_sts_tlast(),
+
+        //store and forward - always can post
+        .mm2s_allow_addr_req(1'b1),
+        .mm2s_addr_req_posted(),
+        .mm2s_rd_xfer_cmplt(),
+
+        //HP RD connection to DDR
+        .m_axi_mm2s_arid(DDR_AXI_ARID),
+        .m_axi_mm2s_araddr(DDR_AXI_ARADDR),
+        .m_axi_mm2s_arlen(DDR_AXI_ARLEN),
+        .m_axi_mm2s_arsize(DDR_AXI_ARSIZE),
+        .m_axi_mm2s_arburst(DDR_AXI_ARBURST),
+        .m_axi_mm2s_arprot(DDR_AXI_ARPROT),
+        .m_axi_mm2s_arcache(DDR_AXI_ARCACHE),
+        .m_axi_mm2s_aruser(),
+        .m_axi_mm2s_arvalid(DDR_AXI_ARVALID),
+        .m_axi_mm2s_arready(DDR_AXI_ARREADY),
+        .m_axi_mm2s_rdata(DDR_AXI_RDATA),
+        .m_axi_mm2s_rresp(DDR_AXI_RRESP),
+        .m_axi_mm2s_rlast(DDR_AXI_RLAST),
+        .m_axi_mm2s_rvalid(DDR_AXI_RVALID),
+        .m_axi_mm2s_rready(DDR_AXI_RREADY),
+
+        //AXI host to stream connection
+        .m_axis_mm2s_tdata({h2s_tdata[31:0], h2s_tdata[63:32]}),
+        .m_axis_mm2s_tkeep(), //dont care
+        .m_axis_mm2s_tlast(h2s_tlast),
+        .m_axis_mm2s_tvalid(h2s_tvalid),
+        .m_axis_mm2s_tready(h2s_tready),
+
+        //unused debug
+        .mm2s_dbg_sel(4'b0),
+        .mm2s_dbg_data(),
+
+        //stream to host reset stuff
+        .m_axi_s2mm_aclk(clk),
+        .m_axi_s2mm_aresetn(!reset_dm),
+        .s2mm_halt(1'b0),
+        .s2mm_halt_cmplt(),
+        .s2mm_err(),
+
+        //stream to host command
+        .m_axis_s2mm_cmdsts_awclk(clk),
+        .m_axis_s2mm_cmdsts_aresetn(!reset_dm),
+        .s_axis_s2mm_cmd_tvalid(s2h_cmd_tvalid),
+        .s_axis_s2mm_cmd_tready(s2h_cmd_tready),
+        .s_axis_s2mm_cmd_tdata(s2h_cmd_tdata),
+
+        //stream to host status
+        .m_axis_s2mm_sts_tvalid(s2h_sts_tvalid),
+        .m_axis_s2mm_sts_tready(s2h_sts_tready),
+        .m_axis_s2mm_sts_tdata(s2h_sts_tdata),
+        .m_axis_s2mm_sts_tkeep(),
+        .m_axis_s2mm_sts_tlast(),
+
+        //store and forward - always can post
+        .s2mm_allow_addr_req(1'b1),
+        .s2mm_addr_req_posted(),
+        .s2mm_wr_xfer_cmplt(),
+        .s2mm_ld_nxt_len(),
+        .s2mm_wr_len(),
+
+        //HP WR connection to DDR
+        .m_axi_s2mm_awid(DDR_AXI_AWID),
+        .m_axi_s2mm_awaddr(DDR_AXI_AWADDR),
+        .m_axi_s2mm_awlen(DDR_AXI_AWLEN),
+        .m_axi_s2mm_awsize(DDR_AXI_AWSIZE),
+        .m_axi_s2mm_awburst(DDR_AXI_AWBURST),
+        .m_axi_s2mm_awprot(DDR_AXI_AWPROT),
+        .m_axi_s2mm_awcache(DDR_AXI_AWCACHE),
+        .m_axi_s2mm_awuser(),
+        .m_axi_s2mm_awvalid(DDR_AXI_AWVALID),
+        .m_axi_s2mm_awready(DDR_AXI_AWREADY),
+        .m_axi_s2mm_wdata(DDR_AXI_WDATA),
+        .m_axi_s2mm_wstrb(DDR_AXI_WSTRB),
+        .m_axi_s2mm_wlast(DDR_AXI_WLAST),
+        .m_axi_s2mm_wvalid(DDR_AXI_WVALID),
+        .m_axi_s2mm_wready(DDR_AXI_WREADY),
+        .m_axi_s2mm_bresp(DDR_AXI_BRESP),
+        .m_axi_s2mm_bvalid(DDR_AXI_BVALID),
+        .m_axi_s2mm_bready(DDR_AXI_BREADY),
+
+        //AXI stream to host connection
+        .s_axis_s2mm_tdata({s2h_tdata_i1[31:0], s2h_tdata_i1[63:32]}),
+        .s_axis_s2mm_tkeep(8'hff), //all bytes valid
+        .s_axis_s2mm_tlast(s2h_tlast_i1),
+        .s_axis_s2mm_tvalid(s2h_tvalid_i1),
+        .s_axis_s2mm_tready(s2h_tready_i1),
+
+        //unused debug
+        .s2mm_dbg_sel(4'b0),
+        .s2mm_dbg_data()
+    );
+
+    //------------------------------------------------------------------
+    // chipscope debugs
+    //------------------------------------------------------------------
+/*  wire [35:0] CONTROL;
+    wire [255:0] DATA;
+    wire [7:0] TRIG;
+
+    chipscope_icon chipscope_icon(.CONTROL0(CONTROL));
+
+    chipscope_ila chipscope_ila
+    (
+        .CONTROL(CONTROL), .CLK(clk),
+        .DATA(DATA), .TRIG0(TRIG)
+    );
+
+    assign DATA[255:256-64] = {set_addr, set_data};
+    assign DATA[79:76] = which_stream_s2h;
+    assign DATA[75:72] = {1'b0, s2h_tlast, s2h_tvalid, s2h_tready};
+    assign DATA[71:68] = {1'b0, s2h_tlast_i0, s2h_tvalid_i0, s2h_tready_i0};
+    assign DATA[67:64] = {1'b0, s2h_tlast_i1, s2h_tvalid_i1, s2h_tready_i1};
+    assign DATA[63:0] = s2h_tdata_i1;
+
+    assign TRIG = {
+        set_stb, s2h_tlast_i0, s2h_tvalid_i0, s2h_tready_i0,
+        (set_stb && (set_page == 2'h2)), s2h_tlast_i1, s2h_tvalid_i1, s2h_tready_i1
+    };
+*/
+endmodule //zynq_fifo_top
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