From bafa9d95453387814ef25e6b6256ba8db2df612f Mon Sep 17 00:00:00 2001 From: Martin Braun Date: Thu, 23 Jan 2020 16:10:22 -0800 Subject: Merge FPGA repository back into UHD repository MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The FPGA codebase was removed from the UHD repository in 2014 to reduce the size of the repository. However, over the last half-decade, the split between the repositories has proven more burdensome than it has been helpful. By merging the FPGA code back, it will be possible to create atomic commits that touch both FPGA and UHD codebases. Continuous integration testing is also simplified by merging the repositories, because it was previously difficult to automatically derive the correct UHD branch when testing a feature branch on the FPGA repository. This commit also updates the license files and paths therein. We are therefore merging the repositories again. Future development for FPGA code will happen in the same repository as the UHD host code and MPM code. == Original Codebase and Rebasing == The original FPGA repository will be hosted for the foreseeable future at its original local location: https://github.com/EttusResearch/fpga/ It can be used for bisecting, reference, and a more detailed history. The final commit from said repository to be merged here is 05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as v4.0.0.0-pre-uhd-merge. If you have changes in the FPGA repository that you want to rebase onto the UHD repository, simply run the following commands: - Create a directory to store patches (this should be an empty directory): mkdir ~/patches - Now make sure that your FPGA codebase is based on the same state as the code that was merged: cd src/fpga # Or wherever your FPGA code is stored git rebase v4.0.0.0-pre-uhd-merge Note: The rebase command may look slightly different depending on what exactly you're trying to rebase. - Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge: git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches Note: Make sure that only patches are stored in your output directory. It should otherwise be empty. Make sure that you picked the correct range of commits, and only commits you wanted to rebase were exported as patch files. - Go to the UHD repository and apply the patches: cd src/uhd # Or wherever your UHD repository is stored git am --directory fpga ~/patches/* rm -rf ~/patches # This is for cleanup == Contributors == The following people have contributed mainly to these files (this list is not complete): Co-authored-by: Alex Williams Co-authored-by: Andrej Rode Co-authored-by: Ashish Chaudhari Co-authored-by: Ben Hilburn Co-authored-by: Ciro Nishiguchi Co-authored-by: Daniel Jepson Co-authored-by: Derek Kozel Co-authored-by: EJ Kreinar Co-authored-by: Humberto Jimenez Co-authored-by: Ian Buckley Co-authored-by: Jörg Hofrichter Co-authored-by: Jon Kiser Co-authored-by: Josh Blum Co-authored-by: Jonathon Pendlum Co-authored-by: Martin Braun Co-authored-by: Matt Ettus Co-authored-by: Michael West Co-authored-by: Moritz Fischer Co-authored-by: Nick Foster Co-authored-by: Nicolas Cuervo Co-authored-by: Paul Butler Co-authored-by: Paul David Co-authored-by: Ryan Marlow Co-authored-by: Sugandha Gupta Co-authored-by: Sylvain Munaut Co-authored-by: Trung Tran Co-authored-by: Vidush Vishwanath Co-authored-by: Wade Fife --- fpga/usrp3/lib/zpu/zpu_wb_top.vhd | 74 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 fpga/usrp3/lib/zpu/zpu_wb_top.vhd (limited to 'fpga/usrp3/lib/zpu/zpu_wb_top.vhd') diff --git a/fpga/usrp3/lib/zpu/zpu_wb_top.vhd b/fpga/usrp3/lib/zpu/zpu_wb_top.vhd new file mode 100644 index 000000000..48e5ee31d --- /dev/null +++ b/fpga/usrp3/lib/zpu/zpu_wb_top.vhd @@ -0,0 +1,74 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library work; +use work.zpu_top_pkg.all; +use work.wishbone_pkg.all; +use work.zpupkg.all; +use work.zpu_config.all; + +------------------------------------------------------------------------ +-- Top level ZPU + wishbone componenent to use in a verilog design: +-- zpu_wb_top wraps around the zpu_system component. +-- All IO lines are exposed as std_logic for verilog. +------------------------------------------------------------------------ +entity zpu_wb_top is + generic ( + dat_w: integer := 32; + adr_w: integer := 16; + sel_w: integer := 4 + ); + port ( + clk: in std_logic; + rst: in std_logic; + enb: in std_logic; + + -- wishbone interface + dat_i: in std_logic_vector(dat_w-1 downto 0); + ack_i: in std_logic; + adr_o: out std_logic_vector(adr_w-1 downto 0); + sel_o: out std_logic_vector(sel_w-1 downto 0); + we_o: out std_logic; + dat_o: out std_logic_vector(dat_w-1 downto 0); + cyc_o: out std_logic; + stb_o: out std_logic; + + -- misc zpu signals + interrupt: in std_logic; + zpu_status: out std_logic_vector(63 downto 0) + ); + +end zpu_wb_top; + +architecture syn of zpu_wb_top is + +--wishbone interface (records) +signal zpu_wb_i: wishbone_bus_out; +signal zpu_wb_o: wishbone_bus_in; + +begin + +--assign wishbone signals to records +zpu_wb_i.dat <= dat_i; +zpu_wb_i.ack <= ack_i; + +adr_o <= zpu_wb_o.adr; +sel_o <= zpu_wb_o.sel; +we_o <= zpu_wb_o.we; +dat_o <= zpu_wb_o.dat; +cyc_o <= zpu_wb_o.cyc; +stb_o <= zpu_wb_o.stb; + +--instantiate the zpu system +zpu_system0: zpu_system port map( + cpu_clk => clk, + areset => rst, + enable => enb, + interrupt => interrupt, + zpu_status => zpu_status, + zpu_wb_i => zpu_wb_i, + zpu_wb_o => zpu_wb_o +); + +end architecture syn; -- cgit v1.2.3