From ff1546f8137f7f92bb250f685561b0c34cc0e053 Mon Sep 17 00:00:00 2001
From: Ben Hilburn <ben.hilburn@ettus.com>
Date: Fri, 14 Feb 2014 12:05:07 -0800
Subject: Pushing the bulk of UHD-3.7.0 code.

---
 fpga/usrp3/lib/xge/Makefile.srcs | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)
 create mode 100644 fpga/usrp3/lib/xge/Makefile.srcs

(limited to 'fpga/usrp3/lib/xge/Makefile.srcs')

diff --git a/fpga/usrp3/lib/xge/Makefile.srcs b/fpga/usrp3/lib/xge/Makefile.srcs
new file mode 100644
index 000000000..5af520788
--- /dev/null
+++ b/fpga/usrp3/lib/xge/Makefile.srcs
@@ -0,0 +1,29 @@
+##################################################
+# OpenCore XGE MAC Sources
+##################################################
+XGE_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/xge/, \
+rtl/verilog/fault_sm.v \
+rtl/verilog/generic_fifo.v \
+rtl/verilog/generic_fifo_ctrl.v \
+rtl/verilog/generic_mem_xilinx_block.v \
+rtl/verilog/generic_mem_medium.v \
+rtl/verilog/generic_mem_small.v \
+rtl/verilog/meta_sync.v \
+rtl/verilog/meta_sync_single.v \
+rtl/verilog/rx_checker.v \
+rtl/verilog/rx_data_fifo.v \
+rtl/verilog/rx_dequeue.v \
+rtl/verilog/rx_enqueue.v \
+rtl/verilog/rx_hold_fifo.v \
+rtl/verilog/sync_clk_core.v \
+rtl/verilog/sync_clk_wb.v \
+rtl/verilog/sync_clk_xgmii_tx.v \
+rtl/verilog/tx_checker.v \
+rtl/verilog/tx_data_fifo.v \
+rtl/verilog/tx_dequeue.v \
+rtl/verilog/tx_enqueue.v \
+rtl/verilog/tx_hold_fifo.v \
+rtl/verilog/wishbone_if.v \
+rtl/verilog/xge_mac.v \
+))
+
-- 
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